<NME> instructions_0f.rs <BEF> #![allow(non_snake_case)] extern "C" { fn get_rand_int() -> i32; } unsafe fn undefined_instruction() { dbg_assert!(false, "Undefined instructions"); trigger_ud() } unsafe fn unimplemented_sse() { dbg_assert!(false, "Unimplemented SSE instruction"); trigger_ud() } use cpu::arith::{ bsf16, bsf32, bsr16, bsr32, bt_mem, bt_reg, btc_mem, btc_reg, btr_mem, btr_reg, bts_mem, bts_reg, cmpxchg8, cmpxchg16, cmpxchg32, popcnt, shld16, shld32, shrd16, shrd32, xadd8, xadd16, xadd32, }; use cpu::arith::{ imul_reg16, imul_reg32, saturate_sd_to_sb, saturate_sd_to_sw, saturate_sd_to_ub, saturate_sw_to_sb, saturate_sw_to_ub, saturate_ud_to_ub, saturate_uw, }; use cpu::cpu::*; use cpu::fpu::fpu_set_tag_word; use cpu::global_pointers::*; use cpu::misc_instr::{ adjust_stack_reg, bswap, cmovcc16, cmovcc32, fxrstor, fxsave, get_stack_pointer, jmpcc16, jmpcc32, push16, push32, setcc_mem, setcc_reg, test_b, test_be, test_l, test_le, test_o, test_p, test_s, test_z, }; use cpu::misc_instr::{lar, lsl, verr, verw}; use cpu::misc_instr::{lss16, lss32}; use cpu::sse_instr::*; #[no_mangle] pub unsafe fn instr16_0F00_0_mem(addr: i32) { // sldt if !*protected_mode || vm86_mode() { trigger_ud(); return; } return_on_pagefault!(safe_write16(addr, *sreg.offset(LDTR as isize) as i32)); } #[no_mangle] pub unsafe fn instr32_0F00_0_mem(addr: i32) { instr16_0F00_0_mem(addr) } #[no_mangle] pub unsafe fn instr16_0F00_0_reg(r: i32) { if !*protected_mode || vm86_mode() { trigger_ud(); return; } write_reg16(r, *sreg.offset(LDTR as isize) as i32); } #[no_mangle] pub unsafe fn instr32_0F00_0_reg(r: i32) { if !*protected_mode || vm86_mode() { trigger_ud(); return; } write_reg32(r, *sreg.offset(LDTR as isize) as i32); } #[no_mangle] pub unsafe fn instr16_0F00_1_mem(addr: i32) { // str if !*protected_mode || vm86_mode() { trigger_ud(); return; } return_on_pagefault!(safe_write16(addr, *sreg.offset(TR as isize) as i32)); } #[no_mangle] pub unsafe fn instr32_0F00_1_mem(addr: i32) { instr16_0F00_1_mem(addr) } #[no_mangle] pub unsafe fn instr16_0F00_1_reg(r: i32) { if !*protected_mode || vm86_mode() { trigger_ud(); return; } write_reg16(r, *sreg.offset(TR as isize) as i32); } #[no_mangle] pub unsafe fn instr32_0F00_1_reg(r: i32) { if !*protected_mode || vm86_mode() { trigger_ud(); return; } write_reg32(r, *sreg.offset(TR as isize) as i32); } #[no_mangle] pub unsafe fn instr16_0F00_2_mem(addr: i32) { // lldt if !*protected_mode || vm86_mode() { trigger_ud(); } else if 0 != *cpl { trigger_gp(0); } else { return_on_pagefault!(load_ldt(return_on_pagefault!(safe_read16(addr)))); }; } #[no_mangle] pub unsafe fn instr32_0F00_2_mem(addr: i32) { instr16_0F00_2_mem(addr) } #[no_mangle] pub unsafe fn instr16_0F00_2_reg(r: i32) { if !*protected_mode || vm86_mode() { trigger_ud(); } else if 0 != *cpl { trigger_gp(0); } else { return_on_pagefault!(load_ldt(read_reg16(r))); }; } #[no_mangle] pub unsafe fn instr32_0F00_2_reg(r: i32) { instr16_0F00_2_reg(r) } #[no_mangle] pub unsafe fn instr16_0F00_3_mem(addr: i32) { // ltr if !*protected_mode || vm86_mode() { trigger_ud(); } else if 0 != *cpl { trigger_gp(0); } else { load_tr(return_on_pagefault!(safe_read16(addr))); }; } #[no_mangle] pub unsafe fn instr32_0F00_3_mem(addr: i32) { instr16_0F00_3_mem(addr); } #[no_mangle] pub unsafe fn instr16_0F00_3_reg(r: i32) { if !*protected_mode || vm86_mode() { trigger_ud(); } else if 0 != *cpl { trigger_gp(0); } else { load_tr(read_reg16(r)); }; } #[no_mangle] pub unsafe fn instr32_0F00_3_reg(r: i32) { instr16_0F00_3_reg(r) } #[no_mangle] pub unsafe fn instr16_0F00_4_mem(addr: i32) { if !*protected_mode || vm86_mode() { dbg_log!("verr #ud"); trigger_ud(); return; } verr(return_on_pagefault!(safe_read16(addr))); } #[no_mangle] pub unsafe fn instr32_0F00_4_mem(addr: i32) { instr16_0F00_4_mem(addr) } #[no_mangle] pub unsafe fn instr16_0F00_4_reg(r: i32) { if !*protected_mode || vm86_mode() { dbg_log!("verr #ud"); trigger_ud(); return; } verr(read_reg16(r)); } #[no_mangle] pub unsafe fn instr32_0F00_4_reg(r: i32) { instr16_0F00_4_reg(r) } #[no_mangle] pub unsafe fn instr16_0F00_5_mem(addr: i32) { if !*protected_mode || vm86_mode() { dbg_log!("verw #ud"); trigger_ud(); return; } verw(return_on_pagefault!(safe_read16(addr))); } #[no_mangle] pub unsafe fn instr32_0F00_5_mem(addr: i32) { instr16_0F00_5_mem(addr) } #[no_mangle] pub unsafe fn instr16_0F00_5_reg(r: i32) { if !*protected_mode || vm86_mode() { dbg_log!("verw #ud"); trigger_ud(); return; } verw(read_reg16(r)); } #[no_mangle] pub unsafe fn instr32_0F00_5_reg(r: i32) { instr16_0F00_5_reg(r) } #[no_mangle] pub unsafe fn instr16_0F01_0_reg(_r: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr32_0F01_0_reg(_r: i32) { trigger_ud(); } unsafe fn sgdt(addr: i32, mask: i32) { return_on_pagefault!(writable_or_pagefault(addr, 6)); safe_write16(addr, *gdtr_size).unwrap(); safe_write32(addr + 2, *gdtr_offset & mask).unwrap(); } #[no_mangle] pub unsafe fn instr16_0F01_0_mem(addr: i32) { sgdt(addr, 0xFFFFFF) } #[no_mangle] pub unsafe fn instr32_0F01_0_mem(addr: i32) { sgdt(addr, -1) } #[no_mangle] pub unsafe fn instr16_0F01_1_reg(_r: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr32_0F01_1_reg(_r: i32) { trigger_ud(); } unsafe fn sidt(addr: i32, mask: i32) { return_on_pagefault!(writable_or_pagefault(addr, 6)); safe_write16(addr, *idtr_size).unwrap(); safe_write32(addr + 2, *idtr_offset & mask).unwrap(); } #[no_mangle] pub unsafe fn instr16_0F01_1_mem(addr: i32) { sidt(addr, 0xFFFFFF) } #[no_mangle] pub unsafe fn instr32_0F01_1_mem(addr: i32) { sidt(addr, -1) } #[no_mangle] pub unsafe fn instr16_0F01_2_reg(_r: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr32_0F01_2_reg(_r: i32) { trigger_ud(); } unsafe fn lgdt(addr: i32, mask: i32) { if 0 != *cpl { trigger_gp(0); return; } let size = return_on_pagefault!(safe_read16(addr)); let offset = return_on_pagefault!(safe_read32s(addr + 2)); *gdtr_size = size; *gdtr_offset = offset & mask; } #[no_mangle] pub unsafe fn instr16_0F01_2_mem(addr: i32) { lgdt(addr, 0xFFFFFF); } #[no_mangle] pub unsafe fn instr32_0F01_2_mem(addr: i32) { lgdt(addr, -1); } #[no_mangle] pub unsafe fn instr16_0F01_3_reg(_r: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr32_0F01_3_reg(_r: i32) { trigger_ud(); } unsafe fn lidt(addr: i32, mask: i32) { if 0 != *cpl { trigger_gp(0); return; } let size = return_on_pagefault!(safe_read16(addr)); let offset = return_on_pagefault!(safe_read32s(addr + 2)); *idtr_size = size; *idtr_offset = offset & mask; } #[no_mangle] pub unsafe fn instr16_0F01_3_mem(addr: i32) { lidt(addr, 0xFFFFFF); } #[no_mangle] pub unsafe fn instr32_0F01_3_mem(addr: i32) { lidt(addr, -1); } #[no_mangle] pub unsafe fn instr16_0F01_4_reg(r: i32) { // smsw write_reg16(r, *cr); } #[no_mangle] pub unsafe fn instr32_0F01_4_reg(r: i32) { write_reg32(r, *cr); } #[no_mangle] pub unsafe fn instr16_0F01_4_mem(addr: i32) { return_on_pagefault!(safe_write16(addr, *cr)); } #[no_mangle] pub unsafe fn instr32_0F01_4_mem(addr: i32) { return_on_pagefault!(safe_write16(addr, *cr)); } #[no_mangle] pub unsafe fn lmsw(mut new_cr0: i32) { new_cr0 = *cr & !15 | new_cr0 & 15; if *protected_mode { // lmsw cannot be used to switch back new_cr0 |= CR0_PE } set_cr0(new_cr0); } #[no_mangle] pub unsafe fn instr16_0F01_6_reg(r: i32) { if 0 != *cpl { trigger_gp(0); return; } lmsw(read_reg16(r)); } #[no_mangle] pub unsafe fn instr32_0F01_6_reg(r: i32) { instr16_0F01_6_reg(r); } #[no_mangle] pub unsafe fn instr16_0F01_6_mem(addr: i32) { if 0 != *cpl { trigger_gp(0); return; } lmsw(return_on_pagefault!(safe_read16(addr))); } #[no_mangle] pub unsafe fn instr32_0F01_6_mem(addr: i32) { instr16_0F01_6_mem(addr) } #[no_mangle] pub unsafe fn instr16_0F01_7_reg(_r: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr32_0F01_7_reg(_r: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr16_0F01_7_mem(addr: i32) { // invlpg if 0 != *cpl { trigger_gp(0); return; } invlpg(addr); } #[no_mangle] pub unsafe fn instr32_0F01_7_mem(addr: i32) { instr16_0F01_7_mem(addr) } #[no_mangle] pub unsafe fn instr16_0F02_mem(addr: i32, r: i32) { if !*protected_mode || vm86_mode() { dbg_log!("lar #ud"); trigger_ud(); return; } write_reg16( r, lar(return_on_pagefault!(safe_read16(addr)), read_reg16(r)), ); } #[no_mangle] pub unsafe fn instr16_0F02_reg(r1: i32, r: i32) { if !*protected_mode || vm86_mode() { dbg_log!("lar #ud"); trigger_ud(); return; } write_reg16(r, lar(read_reg16(r1), read_reg16(r))); } #[no_mangle] pub unsafe fn instr32_0F02_mem(addr: i32, r: i32) { if !*protected_mode || vm86_mode() { dbg_log!("lar #ud"); trigger_ud(); return; } write_reg32( r, lar(return_on_pagefault!(safe_read16(addr)), read_reg32(r)), ); } #[no_mangle] pub unsafe fn instr32_0F02_reg(r1: i32, r: i32) { if !*protected_mode || vm86_mode() { dbg_log!("lar #ud"); trigger_ud(); return; } write_reg32(r, lar(read_reg16(r1), read_reg32(r))); } #[no_mangle] pub unsafe fn instr16_0F03_mem(addr: i32, r: i32) { if !*protected_mode || vm86_mode() { dbg_log!("lsl #ud"); trigger_ud(); return; } write_reg16( r, lsl(return_on_pagefault!(safe_read16(addr)), read_reg16(r)), ); } #[no_mangle] pub unsafe fn instr16_0F03_reg(r1: i32, r: i32) { if !*protected_mode || vm86_mode() { dbg_log!("lsl #ud"); trigger_ud(); return; } write_reg16(r, lsl(read_reg16(r1), read_reg16(r))); } #[no_mangle] pub unsafe fn instr32_0F03_mem(addr: i32, r: i32) { if !*protected_mode || vm86_mode() { dbg_log!("lsl #ud"); trigger_ud(); return; } write_reg32( r, lsl(return_on_pagefault!(safe_read16(addr)), read_reg32(r)), ); } #[no_mangle] pub unsafe fn instr32_0F03_reg(r1: i32, r: i32) { if !*protected_mode || vm86_mode() { dbg_log!("lsl #ud"); trigger_ud(); return; } write_reg32(r, lsl(read_reg16(r1), read_reg32(r))); } #[no_mangle] pub unsafe fn instr_0F04() { undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F05() { undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F06() { // clts if 0 != *cpl { dbg_log!("clts #gp"); trigger_gp(0); } else { if false { dbg_log!("clts"); } *cr &= !CR0_TS; }; } #[no_mangle] pub unsafe fn instr_0F07() { undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F08() { // invd undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F09() { if 0 != *cpl { dbg_log!("wbinvd #gp"); trigger_gp(0); } else { // wbinvd }; } #[no_mangle] pub unsafe fn instr_0F0A() { undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F0B() { // UD2 trigger_ud(); } #[no_mangle] pub unsafe fn instr_0F0C() { undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F0D() { // nop undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F0E() { undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F0F() { undefined_instruction(); } pub unsafe fn instr_0F10(source: reg128, r: i32) { // movups xmm, xmm/m128 mov_rm_r128(source, r); } pub unsafe fn instr_0F10_reg(r1: i32, r2: i32) { instr_0F10(read_xmm128s(r1), r2); } pub unsafe fn instr_0F10_mem(addr: i32, r: i32) { instr_0F10(return_on_pagefault!(safe_read128s(addr)), r); } pub unsafe fn instr_F30F10_reg(r1: i32, r2: i32) { // movss xmm, xmm/m32 let data = read_xmm128s(r1); write_xmm32(r2, data.u32[0] as i32); } pub unsafe fn instr_F30F10_mem(addr: i32, r: i32) { // movss xmm, xmm/m32 let data = return_on_pagefault!(safe_read32s(addr)); write_xmm128(r, data, 0, 0, 0); } pub unsafe fn instr_660F10(source: reg128, r: i32) { // movupd xmm, xmm/m128 mov_rm_r128(source, r); } pub unsafe fn instr_660F10_reg(r1: i32, r2: i32) { instr_660F10(read_xmm128s(r1), r2); } pub unsafe fn instr_660F10_mem(addr: i32, r: i32) { instr_660F10(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_F20F10_reg(r1: i32, r2: i32) { // movsd xmm, xmm/m64 let data = read_xmm128s(r1); write_xmm64(r2, data.u64[0]); } pub unsafe fn instr_F20F10_mem(addr: i32, r: i32) { // movsd xmm, xmm/m64 let data = return_on_pagefault!(safe_read64s(addr)); write_xmm128_2(r, data, 0); } pub unsafe fn instr_0F11_reg(r1: i32, r2: i32) { // movups xmm/m128, xmm mov_r_r128(r1, r2); } pub unsafe fn instr_0F11_mem(addr: i32, r: i32) { // movups xmm/m128, xmm mov_r_m128(addr, r); } pub unsafe fn instr_F30F11_reg(rm_dest: i32, reg_src: i32) { // movss xmm/m32, xmm let data = read_xmm128s(reg_src); write_xmm32(rm_dest, data.u32[0] as i32); } pub unsafe fn instr_F30F11_mem(addr: i32, r: i32) { // movss xmm/m32, xmm let data = read_xmm128s(r); return_on_pagefault!(safe_write32(addr, data.u32[0] as i32)); } pub unsafe fn instr_660F11_reg(r1: i32, r2: i32) { // movupd xmm/m128, xmm mov_r_r128(r1, r2); } pub unsafe fn instr_660F11_mem(addr: i32, r: i32) { // movupd xmm/m128, xmm mov_r_m128(addr, r); } #[no_mangle] pub unsafe fn instr_F20F11_reg(r1: i32, r2: i32) { // movsd xmm/m64, xmm let data = read_xmm128s(r2); write_xmm64(r1, data.u64[0]); } pub unsafe fn instr_F20F11_mem(addr: i32, r: i32) { // movsd xmm/m64, xmm let data = read_xmm64s(r); return_on_pagefault!(safe_write64(addr, data)); } pub unsafe fn instr_0F12_mem(addr: i32, r: i32) { // movlps xmm, m64 let data = return_on_pagefault!(safe_read64s(addr)); write_xmm64(r, data); } pub unsafe fn instr_0F12_reg(r1: i32, r2: i32) { // movhlps xmm, xmm let data = read_xmm128s(r1); write_xmm64(r2, data.u64[1]); } pub unsafe fn instr_660F12_reg(_r1: i32, _r: i32) { trigger_ud(); } pub unsafe fn instr_660F12_mem(addr: i32, r: i32) { // movlpd xmm, m64 let data = return_on_pagefault!(safe_read64s(addr)); write_xmm64(r, data); } #[no_mangle] pub unsafe fn instr_F20F12_mem(_addr: i32, _r: i32) { unimplemented_sse(); } #[no_mangle] pub unsafe fn instr_F20F12_reg(_r1: i32, _r2: i32) { unimplemented_sse(); } #[no_mangle] pub unsafe fn instr_F30F12_mem(_addr: i32, _r: i32) { unimplemented_sse(); } #[no_mangle] pub unsafe fn instr_F30F12_reg(_r1: i32, _r2: i32) { unimplemented_sse(); } pub unsafe fn instr_0F13_mem(addr: i32, r: i32) { // movlps m64, xmm movl_r128_m64(addr, r); } pub unsafe fn instr_0F13_reg(_r1: i32, _r2: i32) { trigger_ud(); } pub unsafe fn instr_660F13_reg(_r1: i32, _r: i32) { trigger_ud(); } pub unsafe fn instr_660F13_mem(addr: i32, r: i32) { // movlpd xmm/m64, xmm movl_r128_m64(addr, r); } #[no_mangle] pub unsafe fn instr_0F14(source: u64, r: i32) { // unpcklps xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm64s(r); write_xmm128( r, destination as i32, source as i32, (destination >> 32) as i32, (source >> 32) as i32, ); } pub unsafe fn instr_0F14_reg(r1: i32, r2: i32) { instr_0F14(read_xmm64s(r1), r2); } pub unsafe fn instr_0F14_mem(addr: i32, r: i32) { instr_0F14(return_on_pagefault!(safe_read64s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F14(source: u64, r: i32) { // unpcklpd xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm64s(r); write_xmm128( r, destination as i32, (destination >> 32) as i32, source as i32, (source >> 32) as i32, ); } pub unsafe fn instr_660F14_reg(r1: i32, r2: i32) { instr_660F14(read_xmm64s(r1), r2); } pub unsafe fn instr_660F14_mem(addr: i32, r: i32) { instr_660F14(return_on_pagefault!(safe_read64s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F15(source: reg128, r: i32) { // unpckhps xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); write_xmm128( r, destination.u32[2] as i32, source.u32[2] as i32, destination.u32[3] as i32, source.u32[3] as i32, ); } pub unsafe fn instr_0F15_reg(r1: i32, r2: i32) { instr_0F15(read_xmm128s(r1), r2); } pub unsafe fn instr_0F15_mem(addr: i32, r: i32) { instr_0F15(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F15(source: reg128, r: i32) { // unpckhpd xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); write_xmm128( r, destination.u32[2] as i32, destination.u32[3] as i32, source.u32[2] as i32, source.u32[3] as i32, ); } pub unsafe fn instr_660F15_reg(r1: i32, r2: i32) { instr_660F15(read_xmm128s(r1), r2); } pub unsafe fn instr_660F15_mem(addr: i32, r: i32) { instr_660F15(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F16_mem(addr: i32, r: i32) { // movhps xmm, m64 movh_m64_r128(addr, r); } #[no_mangle] pub unsafe fn instr_0F16_reg(r1: i32, r2: i32) { // movlhps xmm, xmm let data = read_xmm128s(r1); let orig = read_xmm128s(r2); write_xmm128_2(r2, orig.u64[0], data.u64[0]); } #[no_mangle] pub unsafe fn instr_660F16_mem(addr: i32, r: i32) { // movhpd xmm, m64 movh_m64_r128(addr, r); } #[no_mangle] pub unsafe fn instr_660F16_reg(_r1: i32, _r2: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr_F30F16_reg(_r1: i32, _r2: i32) { unimplemented_sse(); } #[no_mangle] pub unsafe fn instr_F30F16_mem(_addr: i32, _r: i32) { unimplemented_sse(); } #[no_mangle] pub unsafe fn instr_0F17_mem(addr: i32, r: i32) { // movhps m64, xmm movh_r128_m64(addr, r); } #[no_mangle] pub unsafe fn instr_0F17_reg(_r1: i32, _r2: i32) { trigger_ud(); } } #[no_mangle] pub unsafe fn instr_660F16_reg(_r1: i32, _r2: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr_0F17_mem(addr: i32, r: i32) { // movhps m64, xmm // prefetch // nop for us } pub unsafe fn instr_0F19_reg(_r1: i32, _r2: i32) {} pub unsafe fn instr_0F19_mem(_addr: i32, _r: i32) {} #[no_mangle] pub unsafe fn instr_0F1A() { undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F1B() { undefined_instruction(); } pub unsafe fn instr_0F1C_reg(_r1: i32, _r2: i32) {} pub unsafe fn instr_0F1C_mem(_addr: i32, _r: i32) {} pub unsafe fn instr_0F1D_reg(_r1: i32, _r2: i32) {} // prefetch // nop for us } #[no_mangle] pub unsafe fn instr_0F1A() { undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F1B() { undefined_instruction(); } pub unsafe fn instr_0F1F_reg(_r1: i32, _r2: i32) {} pub unsafe fn instr_0F1F_mem(_addr: i32, _r: i32) {} #[no_mangle] pub unsafe fn instr_0F20(r: i32, creg: i32) { if 0 != *cpl { write_reg32(r, *cr.offset(4)); }, _ => { dbg_log!("{}", creg); undefined_instruction(); }, } } #[no_mangle] pub unsafe fn instr_0F21(r: i32, mut dreg_index: i32) { if 0 != *cpl { trigger_gp(0); return; } if dreg_index == 4 || dreg_index == 5 { if 0 != *cr.offset(4) & CR4_DE { dbg_log!("#ud mov dreg 4/5 with cr4.DE set"); trigger_ud(); return; } else { // DR4 and DR5 refer to DR6 and DR7 respectively dreg_index += 2 } } write_reg32(r, *dreg.offset(dreg_index as isize)); if false { dbg_log!( "read dr{}: {:x}", dreg_index, *dreg.offset(dreg_index as isize) ); } } #[no_mangle] pub unsafe fn instr_0F22(r: i32, creg: i32) { if 0 != *cpl { trigger_gp(0); return; } let data = read_reg32(r); // mov cr, addr match creg { 0 => { if false { dbg_log!("cr0 <- {:x}", data); } set_cr0(data); }, 2 => { dbg_log!("cr2 <- {:x}", data); *cr.offset(2) = data }, 3 => set_cr3(data), 4 => { dbg_log!("cr4 <- {:x}", data); if 0 != data as u32 & ((1 << 11 | 1 << 12 | 1 << 15 | 1 << 16 | 1 << 19) as u32 | 0xFFC00000) { dbg_log!("trigger_gp: Invalid cr4 bit"); trigger_gp(0); return; } else { if 0 != (*cr.offset(4) ^ data) & (CR4_PGE | CR4_PSE | CR4_PAE) { full_clear_tlb(); } if data & CR4_PAE != 0 && 0 != (*cr.offset(4) ^ data) & (CR4_PGE | CR4_PSE | CR4_SMEP) { load_pdpte(*cr.offset(3)); } *cr.offset(4) = data; } }, _ => { dbg_log!("{}", creg); undefined_instruction(); }, } } #[no_mangle] pub unsafe fn instr_0F23(r: i32, mut dreg_index: i32) { if 0 != *cpl { trigger_gp(0); return; } if dreg_index == 4 || dreg_index == 5 { if 0 != *cr.offset(4) & CR4_DE { dbg_log!("#ud mov dreg 4/5 with cr4.DE set"); trigger_ud(); return; } else { // DR4 and DR5 refer to DR6 and DR7 respectively dreg_index += 2 } } *dreg.offset(dreg_index as isize) = read_reg32(r); if false { dbg_log!( "write dr{}: {:x}", dreg_index, *dreg.offset(dreg_index as isize) ); } } #[no_mangle] pub unsafe fn instr_0F24() { undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F25() { undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F26() { undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F27() { undefined_instruction(); } pub unsafe fn instr_0F28(source: reg128, r: i32) { // movaps xmm, xmm/m128 // XXX: Aligned read or #gp mov_rm_r128(source, r); } pub unsafe fn instr_0F28_reg(r1: i32, r2: i32) { instr_0F28(read_xmm128s(r1), r2); } pub unsafe fn instr_0F28_mem(addr: i32, r: i32) { instr_0F28(return_on_pagefault!(safe_read128s(addr)), r); } pub unsafe fn instr_660F28(source: reg128, r: i32) { // movapd xmm, xmm/m128 // XXX: Aligned read or #gp // Note: Same as movdqa (660F6F) mov_rm_r128(source, r); } pub unsafe fn instr_660F28_reg(r1: i32, r2: i32) { instr_660F28(read_xmm128s(r1), r2); } pub unsafe fn instr_660F28_mem(addr: i32, r: i32) { instr_660F28(return_on_pagefault!(safe_read128s(addr)), r); } pub unsafe fn instr_0F29_mem(addr: i32, r: i32) { // movaps m128, xmm let data = read_xmm128s(r); // XXX: Aligned write or #gp return_on_pagefault!(safe_write128(addr, data)); } pub unsafe fn instr_0F29_reg(r1: i32, r2: i32) { // movaps xmm, xmm mov_r_r128(r1, r2); } pub unsafe fn instr_660F29_mem(addr: i32, r: i32) { // movapd m128, xmm let data = read_xmm128s(r); // XXX: Aligned write or #gp return_on_pagefault!(safe_write128(addr, data)); } pub unsafe fn instr_660F29_reg(r1: i32, r2: i32) { // movapd xmm, xmm mov_r_r128(r1, r2); } #[no_mangle] pub unsafe fn instr_0F2A(source: u64, r: i32) { // cvtpi2ps xmm, mm/m64 // Note: Casts here can fail // XXX: Should round according to round control let source: [i32; 2] = std::mem::transmute(source); let result = [source[0] as f32, source[1] as f32]; write_xmm64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F2A_reg(r1: i32, r2: i32) { instr_0F2A(read_mmx64s(r1), r2); } pub unsafe fn instr_0F2A_mem(addr: i32, r: i32) { instr_0F2A(return_on_pagefault!(safe_read64s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F2A(source: u64, r: i32) { // cvtpi2pd xmm, xmm/m64 // movapd xmm, xmm mov_r_r128(r1, r2); } pub unsafe fn instr_0F2B_reg(_r1: i32, _r2: i32) { trigger_ud(); } pub unsafe fn instr_0F2B_mem(addr: i32, r: i32) { // movntps m128, xmm #[no_mangle] pub unsafe fn instr_0F2C_reg(r1: i32, r2: i32) { instr_0F2C(read_xmm64s(r1), r2); } pub unsafe fn instr_660F2C(source: reg128, r: i32) { // cvttpd2pi mm, xmm/m128 write_mmx_reg64( r, sse_convert_with_truncation_f64_to_i32(source.f64[0]) as u32 as u64 | (sse_convert_with_truncation_f64_to_i32(source.f64[1]) as u32 as u64) << 32, ); transition_fpu_to_mmx(); } #[no_mangle] pub unsafe fn instr_660F2C_mem(addr: i32, r: i32) { instr_660F2C(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F2C_reg(r1: i32, r2: i32) { instr_660F2C(read_xmm128s(r1), r2); } pub unsafe fn instr_F20F2C(source: u64, r: i32) { // cvttsd2si r32, xmm/m64 let source = f64::from_bits(source); write_reg32(r, sse_convert_with_truncation_f64_to_i32(source)); } #[no_mangle] pub unsafe fn instr_F20F2C_reg(r1: i32, r2: i32) { instr_F20F2C(read_xmm64s(r1), r2); } #[no_mangle] pub unsafe fn instr_F20F2C_mem(addr: i32, r: i32) { instr_F20F2C(return_on_pagefault!(safe_read64s(addr)), r); } pub unsafe fn instr_F30F2C(source: f32, r: i32) { // cvttss2si write_reg32(r, sse_convert_with_truncation_f32_to_i32(source)); } #[no_mangle] pub unsafe fn instr_F30F2C_mem(addr: i32, r: i32) { instr_F30F2C(return_on_pagefault!(safe_read_f32(addr)), r); } #[no_mangle] pub unsafe fn instr_F30F2C_reg(r1: i32, r2: i32) { instr_F30F2C(read_xmm_f32(r1), r2); } pub unsafe fn instr_0F2D(source: u64, r: i32) { // cvtps2pi mm, xmm/m64 let source: [f32; 2] = std::mem::transmute(source); let result = [ sse_convert_f32_to_i32(source[0]), sse_convert_f32_to_i32(source[1]), ]; write_mmx_reg64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } #[no_mangle] pub unsafe fn instr_0F2D_reg(r1: i32, r2: i32) { instr_0F2D(read_xmm64s(r1), r2); } #[no_mangle] pub unsafe fn instr_0F2D_mem(addr: i32, r: i32) { instr_0F2D(return_on_pagefault!(safe_read64s(addr)), r); } pub unsafe fn instr_660F2D(source: reg128, r: i32) { // cvtpd2pi mm, xmm/m128 let result = [ sse_convert_f64_to_i32(source.f64[0]), sse_convert_f64_to_i32(source.f64[1]), #[no_mangle] pub unsafe fn instr_F30F2C_reg(r1: i32, r2: i32) { instr_F30F2C(read_xmm_f32(r1), r2); } pub unsafe fn instr_0F2E(source: f32, r: i32) { // ucomiss xmm1, xmm2/m32 let destination = read_xmm_f32(r); let destination = f64::from_bits(read_xmm64s(r)); let source = f64::from_bits(source); *flags_changed = 0; *flags &= !FLAGS_ALL; if destination == source { *flags |= FLAG_ZERO } else if destination < source { *flags |= FLAG_CARRY } else if destination > source { // all flags cleared } else { // TODO: Signal on SNaN *flags |= FLAG_ZERO | FLAG_PARITY | FLAG_CARRY } } pub unsafe fn instr_660F2E_reg(r1: i32, r: i32) { instr_660F2E(read_xmm64s(r1), r); } pub unsafe fn instr_660F2E_mem(addr: i32, r: i32) { instr_660F2E(return_on_pagefault!(safe_read64s(addr)), r) } #[no_mangle] pub unsafe fn instr_0F2F(source: f32, r: i32) { // comiss xmm1, xmm2/m32 let destination = read_xmm_f32(r); *flags_changed = 0; *flags &= !FLAGS_ALL; if destination == source { *flags |= FLAG_ZERO } else if destination < source { *flags |= FLAG_CARRY } else if destination > source { // all flags cleared } else { // TODO: Signal on SNaN or QNaN *flags |= FLAG_ZERO | FLAG_PARITY | FLAG_CARRY } } pub unsafe fn instr_0F2F_reg(r1: i32, r2: i32) { instr_0F2F(read_xmm_f32(r1), r2) } pub unsafe fn instr_0F2F_mem(addr: i32, r: i32) { instr_0F2F(return_on_pagefault!(safe_read_f32(addr)), r); } #[no_mangle] pub unsafe fn instr_660F2F(source: u64, r: i32) { // comisd xmm1, xmm2/m64 let destination = f64::from_bits(read_xmm64s(r)); let source = f64::from_bits(source); *flags_changed = 0; *flags &= !FLAGS_ALL; if destination == source { *flags |= FLAG_ZERO } else if destination < source { *flags |= FLAG_CARRY } else if destination > source { // all flags cleared } else { // TODO: Signal on SNaN or QNaN *flags |= FLAG_ZERO | FLAG_PARITY | FLAG_CARRY } } pub unsafe fn instr_660F2F_reg(r1: i32, r: i32) { instr_660F2F(read_xmm64s(r1), r); } pub unsafe fn instr_660F2F_mem(addr: i32, r: i32) { instr_660F2F(return_on_pagefault!(safe_read64s(addr)), r) } #[no_mangle] pub unsafe fn instr_0F30() { // wrmsr - write maschine specific register if 0 != *cpl { trigger_gp(0); return; } let index = read_reg32(ECX); let low = read_reg32(EAX); let high = read_reg32(EDX); if index != IA32_SYSENTER_ESP { dbg_log!("wrmsr ecx={:x} data={:x}:{:x}", index, high, low); } if index == IA32_SYSENTER_CS { *sysenter_cs = low & 0xFFFF } else if index == IA32_SYSENTER_EIP { *sysenter_eip = low } else if index == IA32_SYSENTER_ESP { *sysenter_esp = low } else if index == MSR_IA32_FEAT_CTL { // linux 5.x } else if index == MSR_TEST_CTRL { // linux 5.x } else if index == IA32_APIC_BASE_MSR { dbg_assert!( high == 0, ("Changing APIC address (high 32 bits) not supported") ); let address = low & !(IA32_APIC_BASE_BSP | IA32_APIC_BASE_EXTD | IA32_APIC_BASE_EN); dbg_assert!( address == APIC_ADDRESS, ("Changing APIC address not supported") ); dbg_assert!(low & IA32_APIC_BASE_EXTD == 0, "x2apic not supported"); *apic_enabled = low & IA32_APIC_BASE_EN == IA32_APIC_BASE_EN } else if index == IA32_TIME_STAMP_COUNTER { set_tsc(low as u32, high as u32); } else if index == IA32_BIOS_SIGN_ID { // } else if index == MSR_MISC_FEATURE_ENABLES { // Linux 4, see: https://patchwork.kernel.org/patch/9528279/ } else if index == IA32_MISC_ENABLE { // Enable Misc. Processor Features } else if index == IA32_MCG_CAP { // netbsd } else if index == IA32_KERNEL_GS_BASE { // Only used in 64 bit mode (by SWAPGS), but set by kvm-unit-test dbg_log!("GS Base written"); } else if index == IA32_PAT { // } else { dbg_log!("Unknown msr: {:x}", index); dbg_assert!(false); } } pub unsafe fn instr_0F31() { // rdtsc - read timestamp counter if 0 == *cpl || 0 == *cr.offset(4) & CR4_TSD { let tsc = read_tsc(); write_reg32(EAX, tsc as i32); write_reg32(EDX, (tsc >> 32) as i32); if false { dbg_log!("rdtsc edx:eax={:x}:{:x}", read_reg32(EDX), read_reg32(EAX)); } } else { trigger_gp(0); }; } #[no_mangle] pub unsafe fn instr_0F32() { // rdmsr - read maschine specific register if 0 != *cpl { trigger_gp(0); return; } let index = read_reg32(ECX); dbg_log!("rdmsr ecx={:x}", index); let mut low: i32 = 0; let mut high: i32 = 0; if index == IA32_SYSENTER_CS { low = *sysenter_cs } else if index == IA32_SYSENTER_EIP { low = *sysenter_eip } else if index == IA32_SYSENTER_ESP { low = *sysenter_esp } else if index == IA32_TIME_STAMP_COUNTER { let tsc = read_tsc(); low = tsc as i32; high = (tsc >> 32) as i32 } else if index == MSR_IA32_FEAT_CTL { // linux 5.x } else if index == MSR_TEST_CTRL { // linux 5.x } else if index == IA32_PLATFORM_ID { } else if index == IA32_APIC_BASE_MSR { if *acpi_enabled { low = APIC_ADDRESS; if *apic_enabled { low |= IA32_APIC_BASE_EN } } } else if index == IA32_BIOS_SIGN_ID { } else if index == MSR_PLATFORM_INFO { low = 1 << 8 } else if index == MSR_MISC_FEATURE_ENABLES { } else if index == IA32_MISC_ENABLE { // Enable Misc. Processor Features low = 1 << 0; // fast string } else if index == IA32_RTIT_CTL { // linux4 } else if index == MSR_SMI_COUNT { } else if index == IA32_MCG_CAP { // netbsd } else if index == IA32_PAT { // } else if index == MSR_PKG_C2_RESIDENCY { } else { dbg_log!("Unknown msr: {:x}", index); dbg_assert!(false); } write_reg32(EAX, low); write_reg32(EDX, high); } #[no_mangle] pub unsafe fn instr_0F33() { // rdpmc undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F34() { // sysenter let seg = *sysenter_cs & 0xFFFC; if !*protected_mode || seg == 0 { trigger_gp(0); return; } else { *flags &= !FLAG_VM & !FLAG_INTERRUPT; *instruction_pointer = *sysenter_eip; write_reg32(ESP, *sysenter_esp); *sreg.offset(CS as isize) = seg as u16; *segment_is_null.offset(CS as isize) = false; *segment_limits.offset(CS as isize) = -1i32 as u32; *segment_offsets.offset(CS as isize) = 0; update_cs_size(true); *cpl = 0; cpl_changed(); *sreg.offset(SS as isize) = (seg + 8) as u16; *segment_is_null.offset(SS as isize) = false; *segment_limits.offset(SS as isize) = -1i32 as u32; *segment_offsets.offset(SS as isize) = 0; *stack_size_32 = true; return; }; } #[no_mangle] pub unsafe fn instr_0F35() { // sysexit let seg = *sysenter_cs & 0xFFFC; if !*protected_mode || 0 != *cpl || seg == 0 { trigger_gp(0); return; } else { *instruction_pointer = read_reg32(EDX); write_reg32(ESP, read_reg32(ECX)); *sreg.offset(CS as isize) = (seg + 16 | 3) as u16; *segment_is_null.offset(CS as isize) = false; *segment_limits.offset(CS as isize) = -1i32 as u32; *segment_offsets.offset(CS as isize) = 0; update_cs_size(true); *cpl = 3; cpl_changed(); *sreg.offset(SS as isize) = (seg + 24 | 3) as u16; *segment_is_null.offset(SS as isize) = false; *segment_limits.offset(SS as isize) = -1i32 as u32; *segment_offsets.offset(SS as isize) = 0; *stack_size_32 = true; return; }; } #[no_mangle] pub unsafe fn instr_0F36() { undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F37() { // getsec undefined_instruction(); } #[no_mangle] pub unsafe fn instr_0F38() { unimplemented_sse(); } #[no_mangle] pub unsafe fn instr_0F39() { unimplemented_sse(); } #[no_mangle] pub unsafe fn instr_0F3A() { unimplemented_sse(); } #[no_mangle] pub unsafe fn instr_0F3B() { unimplemented_sse(); } #[no_mangle] pub unsafe fn instr_0F3C() { unimplemented_sse(); } #[no_mangle] pub unsafe fn instr_0F3D() { unimplemented_sse(); } #[no_mangle] pub unsafe fn instr_0F3E() { unimplemented_sse(); } #[no_mangle] pub unsafe fn instr_0F3F() { unimplemented_sse(); } pub unsafe fn instr16_0F40_mem(addr: i32, r: i32) { cmovcc16(test_o(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F40_reg(r1: i32, r: i32) { cmovcc16(test_o(), read_reg16(r1), r); } pub unsafe fn instr32_0F40_mem(addr: i32, r: i32) { cmovcc32(test_o(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F40_reg(r1: i32, r: i32) { cmovcc32(test_o(), read_reg32(r1), r); } pub unsafe fn instr16_0F41_mem(addr: i32, r: i32) { cmovcc16(!test_o(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F41_reg(r1: i32, r: i32) { cmovcc16(!test_o(), read_reg16(r1), r); } pub unsafe fn instr32_0F41_mem(addr: i32, r: i32) { cmovcc32(!test_o(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F41_reg(r1: i32, r: i32) { cmovcc32(!test_o(), read_reg32(r1), r); } pub unsafe fn instr16_0F42_mem(addr: i32, r: i32) { cmovcc16(test_b(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F42_reg(r1: i32, r: i32) { cmovcc16(test_b(), read_reg16(r1), r); } pub unsafe fn instr32_0F42_mem(addr: i32, r: i32) { cmovcc32(test_b(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F42_reg(r1: i32, r: i32) { cmovcc32(test_b(), read_reg32(r1), r); } pub unsafe fn instr16_0F43_mem(addr: i32, r: i32) { cmovcc16(!test_b(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F43_reg(r1: i32, r: i32) { cmovcc16(!test_b(), read_reg16(r1), r); } pub unsafe fn instr32_0F43_mem(addr: i32, r: i32) { cmovcc32(!test_b(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F43_reg(r1: i32, r: i32) { cmovcc32(!test_b(), read_reg32(r1), r); } pub unsafe fn instr16_0F44_mem(addr: i32, r: i32) { cmovcc16(test_z(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F44_reg(r1: i32, r: i32) { cmovcc16(test_z(), read_reg16(r1), r); } pub unsafe fn instr32_0F44_mem(addr: i32, r: i32) { cmovcc32(test_z(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F44_reg(r1: i32, r: i32) { cmovcc32(test_z(), read_reg32(r1), r); } pub unsafe fn instr16_0F45_mem(addr: i32, r: i32) { cmovcc16(!test_z(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F45_reg(r1: i32, r: i32) { cmovcc16(!test_z(), read_reg16(r1), r); } pub unsafe fn instr32_0F45_mem(addr: i32, r: i32) { cmovcc32(!test_z(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F45_reg(r1: i32, r: i32) { cmovcc32(!test_z(), read_reg32(r1), r); } pub unsafe fn instr16_0F46_mem(addr: i32, r: i32) { cmovcc16(test_be(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F46_reg(r1: i32, r: i32) { cmovcc16(test_be(), read_reg16(r1), r); } pub unsafe fn instr32_0F46_mem(addr: i32, r: i32) { cmovcc32(test_be(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F46_reg(r1: i32, r: i32) { cmovcc32(test_be(), read_reg32(r1), r); } pub unsafe fn instr16_0F47_mem(addr: i32, r: i32) { cmovcc16(!test_be(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F47_reg(r1: i32, r: i32) { cmovcc16(!test_be(), read_reg16(r1), r); } pub unsafe fn instr32_0F47_mem(addr: i32, r: i32) { cmovcc32(!test_be(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F47_reg(r1: i32, r: i32) { cmovcc32(!test_be(), read_reg32(r1), r); } pub unsafe fn instr16_0F48_mem(addr: i32, r: i32) { cmovcc16(test_s(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F48_reg(r1: i32, r: i32) { cmovcc16(test_s(), read_reg16(r1), r); } pub unsafe fn instr32_0F48_mem(addr: i32, r: i32) { cmovcc32(test_s(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F48_reg(r1: i32, r: i32) { cmovcc32(test_s(), read_reg32(r1), r); } pub unsafe fn instr16_0F49_mem(addr: i32, r: i32) { cmovcc16(!test_s(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F49_reg(r1: i32, r: i32) { cmovcc16(!test_s(), read_reg16(r1), r); } pub unsafe fn instr32_0F49_mem(addr: i32, r: i32) { cmovcc32(!test_s(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F49_reg(r1: i32, r: i32) { cmovcc32(!test_s(), read_reg32(r1), r); } pub unsafe fn instr16_0F4A_mem(addr: i32, r: i32) { cmovcc16(test_p(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F4A_reg(r1: i32, r: i32) { cmovcc16(test_p(), read_reg16(r1), r); } pub unsafe fn instr32_0F4A_mem(addr: i32, r: i32) { cmovcc32(test_p(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F4A_reg(r1: i32, r: i32) { cmovcc32(test_p(), read_reg32(r1), r); } pub unsafe fn instr16_0F4B_mem(addr: i32, r: i32) { cmovcc16(!test_p(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F4B_reg(r1: i32, r: i32) { cmovcc16(!test_p(), read_reg16(r1), r); } pub unsafe fn instr32_0F4B_mem(addr: i32, r: i32) { cmovcc32(!test_p(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F4B_reg(r1: i32, r: i32) { cmovcc32(!test_p(), read_reg32(r1), r); } pub unsafe fn instr16_0F4C_mem(addr: i32, r: i32) { cmovcc16(test_l(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F4C_reg(r1: i32, r: i32) { cmovcc16(test_l(), read_reg16(r1), r); } pub unsafe fn instr32_0F4C_mem(addr: i32, r: i32) { cmovcc32(test_l(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F4C_reg(r1: i32, r: i32) { cmovcc32(test_l(), read_reg32(r1), r); } pub unsafe fn instr16_0F4D_mem(addr: i32, r: i32) { cmovcc16(!test_l(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F4D_reg(r1: i32, r: i32) { cmovcc16(!test_l(), read_reg16(r1), r); } pub unsafe fn instr32_0F4D_mem(addr: i32, r: i32) { cmovcc32(!test_l(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F4D_reg(r1: i32, r: i32) { cmovcc32(!test_l(), read_reg32(r1), r); } pub unsafe fn instr16_0F4E_mem(addr: i32, r: i32) { cmovcc16(test_le(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F4E_reg(r1: i32, r: i32) { cmovcc16(test_le(), read_reg16(r1), r); } pub unsafe fn instr32_0F4E_mem(addr: i32, r: i32) { cmovcc32(test_le(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F4E_reg(r1: i32, r: i32) { cmovcc32(test_le(), read_reg32(r1), r); } pub unsafe fn instr16_0F4F_mem(addr: i32, r: i32) { cmovcc16(!test_le(), return_on_pagefault!(safe_read16(addr)), r); } pub unsafe fn instr16_0F4F_reg(r1: i32, r: i32) { cmovcc16(!test_le(), read_reg16(r1), r); } pub unsafe fn instr32_0F4F_mem(addr: i32, r: i32) { cmovcc32(!test_le(), return_on_pagefault!(safe_read32s(addr)), r); } pub unsafe fn instr32_0F4F_reg(r1: i32, r: i32) { cmovcc32(!test_le(), read_reg32(r1), r); } #[no_mangle] pub unsafe fn instr_0F50_reg(r1: i32, r2: i32) { // movmskps r, xmm let source = read_xmm128s(r1); let data = (source.u32[0] >> 31 | source.u32[1] >> 31 << 1 | source.u32[2] >> 31 << 2 | source.u32[3] >> 31 << 3) as i32; write_reg32(r2, data); } #[no_mangle] pub unsafe fn instr_0F50_mem(_addr: i32, _r1: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr_660F50_reg(r1: i32, r2: i32) { // movmskpd r, xmm let source = read_xmm128s(r1); let data = (source.u32[1] >> 31 | source.u32[3] >> 31 << 1) as i32; write_reg32(r2, data); } #[no_mangle] pub unsafe fn instr_660F50_mem(_addr: i32, _r1: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr_0F51(source: reg128, r: i32) { // sqrtps xmm, xmm/mem128 // XXX: Should round according to round control let result = reg128 { f32: [ source.f32[0].sqrt(), source.f32[1].sqrt(), source.f32[2].sqrt(), source.f32[3].sqrt(), ], }; write_xmm_reg128(r, result); } pub unsafe fn instr_0F51_reg(r1: i32, r2: i32) { instr_0F51(read_xmm128s(r1), r2); } pub unsafe fn instr_0F51_mem(addr: i32, r: i32) { instr_0F51(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F51(source: reg128, r: i32) { // sqrtpd xmm, xmm/mem128 // XXX: Should round according to round control let result = reg128 { f64: [source.f64[0].sqrt(), source.f64[1].sqrt()], }; } #[no_mangle] pub unsafe fn instr_660F50_mem(_addr: i32, _r1: i32) { trigger_ud(); } pub unsafe fn instr_0F54(source: reg128, r: i32) { // andps xmm, xmm/mem128 // XXX: Aligned access or #gp #[no_mangle] pub unsafe fn instr_0F56(source: reg128, r: i32) { // orps xmm, xmm/mem128 // XXX: Aligned access or #gp por_r128(source, r); } pub unsafe fn instr_0F56_reg(r1: i32, r2: i32) { instr_0F56(read_xmm128s(r1), r2); } pub unsafe fn instr_0F56_mem(addr: i32, r: i32) { instr_0F56(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F56(source: reg128, r: i32) { // orpd xmm, xmm/mem128 // XXX: Aligned access or #gp por_r128(source, r); } pub unsafe fn instr_660F56_reg(r1: i32, r2: i32) { instr_660F56(read_xmm128s(r1), r2); } pub unsafe fn instr_660F56_mem(addr: i32, r: i32) { instr_660F56(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F57(source: reg128, r: i32) { // xorps xmm, xmm/mem128 // XXX: Aligned access or #gp pxor_r128(source, r); } pub unsafe fn instr_0F57_reg(r1: i32, r2: i32) { instr_0F57(read_xmm128s(r1), r2); } pub unsafe fn instr_0F57_mem(addr: i32, r: i32) { instr_0F57(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F57(source: reg128, r: i32) { // xorpd xmm, xmm/mem128 // XXX: Aligned access or #gp pxor_r128(source, r); } pub unsafe fn instr_660F57_reg(r1: i32, r2: i32) { instr_660F57(read_xmm128s(r1), r2); } pub unsafe fn instr_660F57_mem(addr: i32, r: i32) { instr_660F57(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F58(source: reg128, r: i32) { // addps xmm, xmm/mem128 let destination = read_xmm128s(r); let result = reg128 { f32: [ source.f32[0] + destination.f32[0], source.f32[1] + destination.f32[1], source.f32[2] + destination.f32[2], source.f32[3] + destination.f32[3], ], }; write_xmm_reg128(r, result); } pub unsafe fn instr_0F58_reg(r1: i32, r2: i32) { instr_0F58(read_xmm128s(r1), r2); } pub unsafe fn instr_0F58_mem(addr: i32, r: i32) { instr_0F58(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F58(source: reg128, r: i32) { // addpd xmm, xmm/mem128 let destination = read_xmm128s(r); let result = reg128 { f64: [ source.f64[0] + destination.f64[0], source.f64[1] + destination.f64[1], ], }; write_xmm_reg128(r, result); } pub unsafe fn instr_660F58_reg(r1: i32, r2: i32) { instr_660F58(read_xmm128s(r1), r2); } pub unsafe fn instr_660F58_mem(addr: i32, r: i32) { instr_660F58(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_F20F58(source: u64, r: i32) { // addsd xmm, xmm/mem64 let destination = read_xmm64s(r); write_xmm_f64(r, f64::from_bits(source) + f64::from_bits(destination)); } pub unsafe fn instr_F20F58_reg(r1: i32, r2: i32) { instr_F20F58(read_xmm64s(r1), r2); } pub unsafe fn instr_660F57_mem(addr: i32, r: i32) { instr_660F57(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F60(source: i32, r: i32) { // punpcklbw mm, mm/m32 let destination: [u8; 8] = std::mem::transmute(read_mmx64s(r)); let source: [u8; 4] = std::mem::transmute(source); let mut result = [0; 8]; for i in 0..4 { result[2 * i + 0] = destination[i]; result[2 * i + 1] = source[i]; } write_mmx_reg64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F60_reg(r1: i32, r2: i32) { instr_0F60(read_mmx32s(r1), r2); } pub unsafe fn instr_0F60_mem(addr: i32, r: i32) { instr_0F60(return_on_pagefault!(safe_read32s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F60(source: reg128, r: i32) { // punpcklbw xmm, xmm/m128 // XXX: Aligned access or #gp let destination: [u8; 8] = std::mem::transmute(read_xmm64s(r)); let mut result = reg128 { i8_0: [0; 16] }; for i in 0..8 { result.u8_0[2 * i + 0] = destination[i]; result.u8_0[2 * i + 1] = source.u8_0[i]; } write_xmm_reg128(r, result); } pub unsafe fn instr_660F60_reg(r1: i32, r2: i32) { instr_660F60(read_xmm128s(r1), r2); } pub unsafe fn instr_660F60_mem(addr: i32, r: i32) { instr_660F60(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F61(source: i32, r: i32) { // punpcklwd mm, mm/m32 let destination: [u16; 4] = std::mem::transmute(read_mmx64s(r)); let source: [u16; 2] = std::mem::transmute(source); let mut result = [0; 4]; for i in 0..2 { result[2 * i + 0] = destination[i]; result[2 * i + 1] = source[i]; } write_mmx_reg64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F61_reg(r1: i32, r2: i32) { instr_0F61(read_mmx32s(r1), r2); } pub unsafe fn instr_0F61_mem(addr: i32, r: i32) { instr_0F61(return_on_pagefault!(safe_read32s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F61(source: reg128, r: i32) { // punpcklwd xmm, xmm/m128 // XXX: Aligned access or #gp let destination: [u16; 4] = std::mem::transmute(read_xmm64s(r)); let mut result = reg128 { i8_0: [0; 16] }; for i in 0..4 { result.u16_0[2 * i + 0] = destination[i]; result.u16_0[2 * i + 1] = source.u16_0[i]; } write_xmm_reg128(r, result); } pub unsafe fn instr_660F61_reg(r1: i32, r2: i32) { instr_660F61(read_xmm128s(r1), r2); } pub unsafe fn instr_660F61_mem(addr: i32, r: i32) { instr_660F61(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F62(source: i32, r: i32) { // punpckldq mm, mm/m32 let destination = read_mmx64s(r); write_mmx_reg64( r, (destination & 0xFFFF_FFFF) | (source as u32 as u64) << 32, ); transition_fpu_to_mmx(); } pub unsafe fn instr_0F62_reg(r1: i32, r2: i32) { instr_0F62(read_mmx32s(r1), r2); } pub unsafe fn instr_0F62_mem(addr: i32, r: i32) { instr_0F62(return_on_pagefault!(safe_read32s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F62(source: reg128, r: i32) { // punpckldq xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); write_xmm128( r, destination.u32_0[0] as i32, source.u32_0[0] as i32, destination.u32_0[1] as i32, source.u32_0[1] as i32, ); } pub unsafe fn instr_660F62_reg(r1: i32, r2: i32) { instr_660F62(read_xmm128s(r1), r2); } pub unsafe fn instr_660F62_mem(addr: i32, r: i32) { instr_660F62(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F63(source: u64, r: i32) { // packsswb mm, mm/m64 let destination: [u16; 4] = std::mem::transmute(read_mmx64s(r)); let source: [u16; 4] = std::mem::transmute(source); let mut result: [u8; 8] = [0; 8]; for i in 0..4 { result[i + 0] = saturate_sw_to_sb(destination[i] as i32); result[i + 4] = saturate_sw_to_sb(source[i] as i32); } write_mmx_reg64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F63_reg(r1: i32, r2: i32) { instr_0F63(read_mmx64s(r1), r2); } pub unsafe fn instr_0F63_mem(addr: i32, r: i32) { instr_0F63(return_on_pagefault!(safe_read64s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F63(source: reg128, r: i32) { // packsswb xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); let mut result = reg128 { i8_0: [0; 16] }; for i in 0..8 { result.u8_0[i + 0] = saturate_sw_to_sb(destination.u16_0[i] as i32); result.u8_0[i + 8] = saturate_sw_to_sb(source.u16_0[i] as i32); } write_xmm_reg128(r, result) } pub unsafe fn instr_660F63_reg(r1: i32, r2: i32) { instr_660F63(read_xmm128s(r1), r2); } pub unsafe fn instr_660F63_mem(addr: i32, r: i32) { instr_660F63(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F64(source: u64, r: i32) { // pcmpgtb mm, mm/m64 let destination: [i8; 8] = std::mem::transmute(read_mmx64s(r)); let source: [i8; 8] = std::mem::transmute(source); let mut result: [u8; 8] = [0; 8]; for i in 0..8 { result[i] = if destination[i] > source[i] { 255 } else { 0 }; } write_mmx_reg64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F64_reg(r1: i32, r2: i32) { instr_0F64(read_mmx64s(r1), r2); } pub unsafe fn instr_0F64_mem(addr: i32, r: i32) { instr_0F64(return_on_pagefault!(safe_read64s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F64(source: reg128, r: i32) { // pcmpgtb xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); let mut result = reg128 { i8_0: [0; 16] }; for i in 0..16 { result.u8_0[i] = if destination.i8_0[i] as i32 > source.i8_0[i] as i32 { 255 } else { 0 }; } write_xmm_reg128(r, result); } pub unsafe fn instr_660F64_reg(r1: i32, r2: i32) { instr_660F64(read_xmm128s(r1), r2); } pub unsafe fn instr_660F64_mem(addr: i32, r: i32) { instr_660F64(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F65(source: u64, r: i32) { // pcmpgtw mm, mm/m64 let destination: [i16; 4] = std::mem::transmute(read_mmx64s(r)); let source: [i16; 4] = std::mem::transmute(source); let mut result: [u16; 4] = [0; 4]; for i in 0..4 { result[i] = if destination[i] > source[i] { 0xFFFF } else { 0 } } write_mmx_reg64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F65_reg(r1: i32, r2: i32) { instr_0F65(read_mmx64s(r1), r2); } pub unsafe fn instr_0F65_mem(addr: i32, r: i32) { instr_0F65(return_on_pagefault!(safe_read64s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F65(source: reg128, r: i32) { // pcmpgtw xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); let mut result = reg128 { i8_0: [0; 16] }; for i in 0..8 { result.u16_0[i] = if destination.i16_0[i] > source.i16_0[i] { 0xFFFF } else { 0 }; } write_xmm_reg128(r, result); } pub unsafe fn instr_660F65_reg(r1: i32, r2: i32) { instr_660F65(read_xmm128s(r1), r2); } pub unsafe fn instr_660F65_mem(addr: i32, r: i32) { instr_660F65(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F66(source: u64, r: i32) { // pcmpgtd mm, mm/m64 let destination: [i32; 2] = std::mem::transmute(read_mmx64s(r)); let source: [i32; 2] = std::mem::transmute(source); let mut result = [0; 2]; for i in 0..2 { result[i] = if destination[i] > source[i] { -1 } else { 0 } } write_mmx_reg64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F66_reg(r1: i32, r2: i32) { instr_0F66(read_mmx64s(r1), r2); } pub unsafe fn instr_0F66_mem(addr: i32, r: i32) { instr_0F66(return_on_pagefault!(safe_read64s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F66(source: reg128, r: i32) { // pcmpgtd xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); write_xmm128( r, if destination.i32_0[0] > source.i32_0[0] { -1 } else { 0 }, if destination.i32_0[1] > source.i32_0[1] { -1 } else { 0 }, if destination.i32_0[2] > source.i32_0[2] { -1 } else { 0 }, if destination.i32_0[3] > source.i32_0[3] { -1 } else { 0 }, ); } pub unsafe fn instr_660F66_reg(r1: i32, r2: i32) { instr_660F66(read_xmm128s(r1), r2); } pub unsafe fn instr_660F66_mem(addr: i32, r: i32) { instr_660F66(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F67(source: u64, r: i32) { // packuswb mm, mm/m64 let destination: [u16; 4] = std::mem::transmute(read_mmx64s(r)); let source: [u16; 4] = std::mem::transmute(source); let mut result = [0; 8]; for i in 0..4 { result[i + 0] = saturate_sw_to_ub(destination[i]); result[i + 4] = saturate_sw_to_ub(source[i]); } write_mmx_reg64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F67_reg(r1: i32, r2: i32) { instr_0F67(read_mmx64s(r1), r2); } pub unsafe fn instr_0F67_mem(addr: i32, r: i32) { instr_0F67(return_on_pagefault!(safe_read64s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F67(source: reg128, r: i32) { // packuswb xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); let mut result = reg128 { i8_0: [0; 16] }; for i in 0..8 { result.u8_0[i + 0] = saturate_sw_to_ub(destination.u16_0[i]); result.u8_0[i + 8] = saturate_sw_to_ub(source.u16_0[i]); } write_xmm_reg128(r, result); } pub unsafe fn instr_660F67_reg(r1: i32, r2: i32) { instr_660F67(read_xmm128s(r1), r2); } pub unsafe fn instr_660F67_mem(addr: i32, r: i32) { instr_660F67(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F68(source: u64, r: i32) { // punpckhbw mm, mm/m64 let destination: [u8; 8] = std::mem::transmute(read_mmx64s(r)); let source: [u8; 8] = std::mem::transmute(source); let mut result: [u8; 8] = [0; 8]; for i in 0..4 { result[2 * i + 0] = destination[i + 4]; result[2 * i + 1] = source[i + 4]; } write_mmx_reg64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F68_reg(r1: i32, r2: i32) { instr_0F68(read_mmx64s(r1), r2); } pub unsafe fn instr_0F68_mem(addr: i32, r: i32) { instr_0F68(return_on_pagefault!(safe_read64s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F68(source: reg128, r: i32) { // punpckhbw xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); let mut result = reg128 { i8_0: [0; 16] }; for i in 0..8 { result.u8_0[2 * i + 0] = destination.u8_0[i + 8]; result.u8_0[2 * i + 1] = source.u8_0[i + 8]; } write_xmm_reg128(r, result); } pub unsafe fn instr_660F68_reg(r1: i32, r2: i32) { instr_660F68(read_xmm128s(r1), r2); } pub unsafe fn instr_660F68_mem(addr: i32, r: i32) { instr_660F68(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F69(source: u64, r: i32) { // punpckhwd mm, mm/m64 let destination: [u16; 4] = std::mem::transmute(read_mmx64s(r)); let source: [u16; 4] = std::mem::transmute(source); let result = [destination[2], source[2], destination[3], source[3]]; write_mmx_reg64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F69_reg(r1: i32, r2: i32) { instr_0F69(read_mmx64s(r1), r2); } pub unsafe fn instr_0F69_mem(addr: i32, r: i32) { instr_0F69(return_on_pagefault!(safe_read64s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F69(source: reg128, r: i32) { // punpckhwd xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); let mut result = reg128 { i8_0: [0; 16] }; for i in 0..4 { result.u16_0[2 * i + 0] = destination.u16_0[i + 4]; result.u16_0[2 * i + 1] = source.u16_0[i + 4]; } write_xmm_reg128(r, result); } pub unsafe fn instr_660F69_reg(r1: i32, r2: i32) { instr_660F69(read_xmm128s(r1), r2); } pub unsafe fn instr_660F69_mem(addr: i32, r: i32) { instr_660F69(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F6A(source: u64, r: i32) { // punpckhdq mm, mm/m64 let destination = read_mmx64s(r); write_mmx_reg64(r, (destination >> 32) | (source >> 32 << 32)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F6A_reg(r1: i32, r2: i32) { instr_0F6A(read_mmx64s(r1), r2); } pub unsafe fn instr_0F6A_mem(addr: i32, r: i32) { instr_0F6A(return_on_pagefault!(safe_read64s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F6A(source: reg128, r: i32) { // punpckhdq xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); write_xmm128( r, destination.u32_0[2] as i32, source.u32_0[2] as i32, destination.u32_0[3] as i32, source.u32_0[3] as i32, ); } pub unsafe fn instr_660F6A_reg(r1: i32, r2: i32) { instr_660F6A(read_xmm128s(r1), r2); } pub unsafe fn instr_660F6A_mem(addr: i32, r: i32) { instr_660F6A(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F6B(source: u64, r: i32) { // packssdw mm, mm/m64 let destination: [u32; 2] = std::mem::transmute(read_mmx64s(r)); let source: [u32; 2] = std::mem::transmute(source); let mut result = [0; 4]; for i in 0..2 { result[i + 0] = saturate_sd_to_sw(destination[i]); result[i + 2] = saturate_sd_to_sw(source[i]); } write_mmx_reg64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F6B_reg(r1: i32, r2: i32) { instr_0F6B(read_mmx64s(r1), r2); } pub unsafe fn instr_0F6B_mem(addr: i32, r: i32) { instr_0F6B(return_on_pagefault!(safe_read64s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F6B(source: reg128, r: i32) { // packssdw xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); let mut result = reg128 { i8_0: [0; 16] }; for i in 0..4 { result.u16_0[i + 0] = saturate_sd_to_sw(destination.u32_0[i]); result.u16_0[i + 4] = saturate_sd_to_sw(source.u32_0[i]); } write_xmm_reg128(r, result); } pub unsafe fn instr_660F6B_reg(r1: i32, r2: i32) { instr_660F6B(read_xmm128s(r1), r2); } pub unsafe fn instr_660F6B_mem(addr: i32, r: i32) { instr_660F6B(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F6C_mem(_addr: i32, _r: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr_0F6C_reg(_r1: i32, _r2: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr_660F6C(source: reg128, r: i32) { // punpcklqdq xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); write_xmm128( r, destination.u32_0[0] as i32, destination.u32_0[1] as i32, source.u32_0[0] as i32, source.u32_0[1] as i32, ); } pub unsafe fn instr_660F6C_reg(r1: i32, r2: i32) { instr_660F6C(read_xmm128s(r1), r2); } pub unsafe fn instr_660F6C_mem(addr: i32, r: i32) { instr_660F6C(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F6D_mem(_addr: i32, _r: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr_0F6D_reg(_r1: i32, _r2: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr_660F6D(source: reg128, r: i32) { // punpckhqdq xmm, xmm/m128 // XXX: Aligned access or #gp let destination = read_xmm128s(r); write_xmm128( r, destination.u32_0[2] as i32, destination.u32_0[3] as i32, source.u32_0[2] as i32, source.u32_0[3] as i32, ); } pub unsafe fn instr_660F6D_reg(r1: i32, r2: i32) { instr_660F6D(read_xmm128s(r1), r2); } pub unsafe fn instr_660F6D_mem(addr: i32, r: i32) { instr_660F6D(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F6E(source: i32, r: i32) { // movd mm, r/m32 write_mmx_reg64(r, source as u32 as u64); transition_fpu_to_mmx(); } pub unsafe fn instr_0F6E_reg(r1: i32, r2: i32) { instr_0F6E(read_reg32(r1), r2); } pub unsafe fn instr_0F6E_mem(addr: i32, r: i32) { instr_0F6E(return_on_pagefault!(safe_read32s(addr)), r); } #[no_mangle] pub unsafe fn instr_660F6E(source: i32, r: i32) { // movd mm, r/m32 write_xmm128(r, source, 0, 0, 0); } pub unsafe fn instr_660F6E_reg(r1: i32, r2: i32) { instr_660F6E(read_reg32(r1), r2); } pub unsafe fn instr_660F6E_mem(addr: i32, r: i32) { instr_660F6E(return_on_pagefault!(safe_read32s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F6F(source: u64, r: i32) { // movq mm, mm/m64 write_mmx_reg64(r, source); transition_fpu_to_mmx(); } #[no_mangle] pub unsafe fn instr_0F6F_reg(r1: i32, r2: i32) { instr_0F6F(read_mmx64s(r1), r2); } pub unsafe fn instr_0F6F_mem(addr: i32, r: i32) { instr_0F6F(return_on_pagefault!(safe_read64s(addr)), r); } pub unsafe fn instr_660F6F(source: reg128, r: i32) { // movdqa xmm, xmm/mem128 // XXX: Aligned access or #gp mov_rm_r128(source, r); } pub unsafe fn instr_660F6F_reg(r1: i32, r2: i32) { instr_660F6F(read_xmm128s(r1), r2); } pub unsafe fn instr_660F6F_mem(addr: i32, r: i32) { instr_660F6F(return_on_pagefault!(safe_read128s(addr)), r); } pub unsafe fn instr_F30F6F(source: reg128, r: i32) { // movdqu xmm, xmm/m128 mov_rm_r128(source, r); } pub unsafe fn instr_F30F6F_reg(r1: i32, r2: i32) { instr_F30F6F(read_xmm128s(r1), r2); } pub unsafe fn instr_F30F6F_mem(addr: i32, r: i32) { instr_F30F6F(return_on_pagefault!(safe_read128s(addr)), r); } #[no_mangle] pub unsafe fn instr_0F70(source: u64, r: i32, imm8: i32) { // pshufw mm1, mm2/m64, imm8 let source: [u16; 4] = std::mem::transmute(source); let mut result = [0; 4]; for i in 0..4 { result[i] = source[(imm8 >> (2 * i) & 3) as usize] } write_mmx_reg64(r, std::mem::transmute(result)); transition_fpu_to_mmx(); } pub unsafe fn instr_0F70_reg(r1: i32, r2: i32, imm: i32) { instr_0F70(read_mmx64s(r1), r2, imm); } pub unsafe fn instr_0F70_mem(addr: i32, r: i32, imm: i32) { instr_0F70(return_on_pagefault!(safe_read64s(addr)), r, imm); } #[no_mangle] pub unsafe fn instr_660F70(source: reg128, r: i32, imm8: i32) { // pshufd xmm, xmm/mem128, imm8 // XXX: Aligned access or #gp write_xmm128( r, source.u32_0[(imm8 & 3) as usize] as i32, source.u32_0[(imm8 >> 2 & 3) as usize] as i32, source.u32_0[(imm8 >> 4 & 3) as usize] as i32, source.u32_0[(imm8 >> 6 & 3) as usize] as i32, ); } pub unsafe fn instr_660F70_reg(r1: i32, r2: i32, imm: i32) { instr_660F70(read_xmm128s(r1), r2, imm); } pub unsafe fn instr_660F70_mem(addr: i32, r: i32, imm: i32) { instr_660F70(return_on_pagefault!(safe_read128s(addr)), r, imm); } #[no_mangle] pub unsafe fn instr_F20F70(source: reg128, r: i32, imm8: i32) { // pshuflw xmm, xmm/m128, imm8 // XXX: Aligned access or #gp write_xmm128( r, source.u16_0[(imm8 & 3) as usize] as i32 | (source.u16_0[(imm8 >> 2 & 3) as usize] as i32) << 16, source.u16_0[(imm8 >> 4 & 3) as usize] as i32 | (source.u16_0[(imm8 >> 6 & 3) as usize] as i32) << 16, source.u32_0[2] as i32, source.u32_0[3] as i32, ); } pub unsafe fn instr_F20F70_reg(r1: i32, r2: i32, imm: i32) { instr_F20F70(read_xmm128s(r1), r2, imm); } pub unsafe fn instr_F20F70_mem(addr: i32, r: i32, imm: i32) { instr_F20F70(return_on_pagefault!(safe_read128s(addr)), r, imm); } #[no_mangle] pub unsafe fn instr_F30F70(source: reg128, r: i32, imm8: i32) { // pshufhw xmm, xmm/m128, imm8 // XXX: Aligned access or #gp write_xmm128( r, source.u32_0[0] as i32, source.u32_0[1] as i32, source.u16_0[(imm8 & 3 | 4) as usize] as i32 | (source.u16_0[(imm8 >> 2 & 3 | 4) as usize] as i32) << 16, source.u16_0[(imm8 >> 4 & 3 | 4) as usize] as i32 | (source.u16_0[(imm8 >> 6 & 3 | 4) as usize] as i32) << 16, ); } pub unsafe fn instr_F30F70_reg(r1: i32, r2: i32, imm: i32) { instr_F30F70(read_xmm128s(r1), r2, imm); } pub unsafe fn instr_F30F70_mem(addr: i32, r: i32, imm: i32) { instr_F30F70(return_on_pagefault!(safe_read128s(addr)), r, imm); } pub unsafe fn instr_0F71_2_mem(_addr: i32, _r: i32) { trigger_ud(); } pub unsafe fn instr_0F71_4_mem(_addr: i32, _r: i32) { trigger_ud(); } pub unsafe fn instr_0F71_6_mem(_addr: i32, _r: i32) { trigger_ud(); } #[no_mangle] pub unsafe fn instr_0F71_2_reg(r: i32, imm8: i32) { // psrlw mm, imm8 psrlw_r64(r, imm8 as u64); } #[no_mangle] pub unsafe fn instr_0F71_4_reg(r: i32, imm8: i32) { // psraw mm, imm8 psraw_r64(r, imm8 as u64); } #[no_mangle] pub unsafe fn instr_0F71_6_reg(r: i32, imm8: i32) { // psllw mm, imm8 psllw_r64(r, imm8 as u64); } pub unsafe fn instr_660F71_2_mem(_addr: i32, _r: i32) { trigger_ud(); } pub unsafe fn instr_660F71_4_mem(_addr: i32, _r: i32) { trigger_ud(); } pub unsafe fn instr_660F71_6_mem(_addr: i32, _r:
{'addition_count': 2805, 'commit_subject': 'Fix the order of functions in instructions_0f.rs', 'deletion_count': 2795, 'file_extension': '.rs', 'lang': 'rs', 'license': 'bsd-2-clause', 'repo_name': 'copy/v86'}