Title of Invention: Source/drain-on insulator (S/DOI) field effect transistor using oxidized amorphous silicon and method of fabrication
Abstract: Source and drain regions of field effect transistors are fabricated with an electrically insulating layer formed thereunder so as to reduce junction capacitance between each and a semiconductor body in which the regions are formed. Shallow trench isolation partially surrounds each transistor so as to further electrically isolate the source and drain regions from the semiconductor body. Typically for a single transistor only one surface of each drain and source region make direct contact to the semiconductor body and these surfaces are on opposite sides of a channel region of each transistor. One method of fabrication of the source and drain regions is to form an isolating isolation region around active areas in which a transistor is to be formed in a semiconductor body. Trenches separated by portions of the body are then formed in the active areas in which transistors are to be formed. On bottom surfaces of the trenches are formed an electrically insulating layer. The trenches are then filled with semiconductor material of a conductivity type opposite that of the semiconductor body. The semiconductor filled portion of each trench then serves as a drain and/or source of a field effect transistor.
Detailed Description: Part PAC: DETAILED DESCRIPTION
Part PAR: Referring now to FIGS. 1 and 2, there are shown a cross-sectional view and a top view, respectively, of a semiconductor structure 2 comprising a semiconductor body 3 having formed therein a drain region 6 and a source region 7 of a field effect transistor in accordance with the present invention. The semiconductor body 3 has a major surface 4 and is of a first conductivity type. A shallow trench isolation region 5, typically of silicon oxide, extends from surface 4 into the body 3 so as to electrically isolate portions of the body 3 in which transistors and/or other components are to be formed. Trench isolation region 5 may be denoted as a dielectric isolation region. For simplicity, only one isolated portion of the body 3 containing a drain region 6 and a source region 7 of a field effect transistor are shown. Drain region 6 and source region 7 are of a conductivity type which is opposite that of the first conductivity type. For example, body 3 can be of p-type conductivity and drain region 6 and source region 7 are of n-type conductivity. This combination of conductivity types results in an n-channel field effect transistor being formed. Body 3 can be of n-type conductivity and drain region 6 and source region 7 are of p-type conductivity. This combination of conductivity types results in a p-channel field effect transistor being formed.
Part PAR_2: The source and drain regions of a field effect transistor reverse as the current therethrough reverses and may be denoted as first and second output regions or first and second semiconductor regions. The field effect transistor can be an insulated gate field effect transistor (IGFET) or a junction field effect transistor (JFET). Under the drain region 6 is a dielectric layer 8, typically of silicon oxide, and under the source region 7 is a dielectric layer 9, typically of silicon oxide. Dielectric layers 8 and 9 restrict the flow of parasitic current from the source and drain regions 7 and 6 into the semiconductor body 3 and also can significantly reduce the capacitance of the source region 7 and drain region 6 to the semiconductor body 3.
Part PAR_3: Drain region 6 has side walls 6a, 6b, 6c, and 6d and a bottom surface 6e. Source region 7 has side walls 7a, 7b, 7c, and 7d and a bottom surface 7e. Side wall 6a of drain region 6 and side wall 7a of source region 7 each make direct contact with bulk portion 3 and the portion of body 3 therebetween becomes the channel region of the field effect transistor. Side walls 6b, 6c, and 6d, and bottom surface 6e of drain region 6 are electrically isolated from body 3 by shallow trench region 5 and dielectric layer 8. Side walls 7b, 7c, and 7d, and bottom surface 6e of source region 7 are electrically isolated from body 3 by shallow trench region 5 and dielectric layer 9.
Part PAR_4: As a result of isolating regions 5 and 8, the junction capacitance of drain region 6 to the body 3 is reduced from that of a conventional field effect transistor. As a result of isolating regions 5 and 9, the junction capacitance of source region 7 to the body 3 is reduced from that of a conventional field effect transistor.
Part PAR_5: The drain region 6 and the source region of FIGS. 1 and 2 can be fabricated as follows:
Part PAR_6: The major surface 4 of the semiconductor body 3 is patterned to define areas thereon in which transistors are to be formed. An insulating isolation region 5 extending from the major surface 4 of the semiconductor body 3 into the body 3 is formed to surround areas of the body 3 in which transistors are to be formed. These surrounded areas are denoted as active areas. Two trenches are etched into at least one active area with the trenches being separated by portions of the body 3. Each trench has three side walls defined by portions of the insulating isolation region 5 and has a fourth side wall and a bottom surface defined by the body 3. The bottom surfaces of the trenches are covered by an insulating layer, typically, silicon oxide. The trenches are then filled with a semiconductive material which is then doped to be of the opposite conductivity of the body 3 such that the filled trenches become the drain and source regions 6 and 7, respectively, of the transistor. The fourth side walls 6a and 7a are each in direct contact with the bulk portion 3, face each other, and are separated by portions of the body 3.
Part PAR_7: Referring now to FIG. 3, there is shown a sectional view of a semiconductor structure 9 comprising partially completed Source/Drain-On-Insulator (S/DOI) field effect transistors and conventional field effect transistors fabricated in a common semiconductor body 14 in accordance with a first illustrative embodiment of the present invention. Semiconductor body 14, which is of a first conductivity type, is typically silicon. Two S/DOI transistors are shown on the left, and two conventional transistors are shown on the right. A Shallow Trench Isolation (STI) 10 (also denoted as an insulating isolation region) surrounds the two groups of transistors. STI 10 is typically silicon oxide. With respect to the conventional transistors, a semiconductor region 16, which is of the opposite conductivity type of body 14, serves as a common source/drain region for the two conventional transistors and is formed in body 14. Regions 17a and 17b, which are also of the opposite conductivity type, serve as drain/source regions of the left and right conventional transistors, respectively, and are formed in body 14. Portions 14a and 14b of body 14 are channel regions, regions 20a and 20b are polysilicon gates, and regions 21a and 21b are gate oxide layers of the left and right conventional transistors, respectively. Side wall dielectric layers 22a and 22b, which are typically oxide layers, cover sidewalls of the polysilicon gates 20a and 20b. In the S/DOI transistors shown on the left side of FIG. 3, portions 114a and 114b of body 14 remain underneath gate oxide layers 121a and 121b, respectively, which underlay polysilicon gates 120a and 120b, respectively. Gates 120a and 120b have on side walls thereof side wall spacers 120a and 120b, respectively, which are typically silicon oxide. Region 116, which is of a second semiconductive type opposite the first conductivity type, serves as a common source/drain region for the two S/DOI transistors and is formed in body 14. Regions 117a and 117b, also of a second semiconductor type, serve as drain/source regions for the left and right S/DOI transistors, respectively, and are formed in body 14. The source/drain region 116 and drain/source regions 117a and 117b, are typically formed from an ion-implanted, deposited amorphous silicon layer, as will be described in more detail herein below. Underlying the source/drain region 116 and drain/source regions 117a and 117b of the S/DOI transistors is a segmented silicon oxide layer 124, which is formed as is described herein below. This layer of silicon oxide 124 restricts the flow of parasitic currents from the source/drain region 116 and drain/source regions 117a and 117b of the S/DOI transistors into the semiconductor body 14. The silicon oxide layer 124 also significantly reduce the capacitance of the source/drain region 116 and drain/source regions 117a and 117b to the semiconductor body 14. The source/drain region 116 and drain source regions 117a and 117b are resistively connected to the Lightly Doped Drain (LDD) extensions (not shown) which are formed underneath the side wall spacers 122a and 122b, as is described herein below. It is to be noted that the channel regions 118a and 118b of the S/DOI transistors are connected to the respective portions of the semiconductor body 114a and 114b. Thus the S/DOI transistors do not suffer from the floating body effect (FBE) which degrades the performance of transistors formed using a conventional Silicon-on-Insulator SOI process.
Part PAR_8: FIGS. 4 through 18 illustrate a process for fabricating the semiconductor structure 9 of FIG. 3.
Part PAR_9: FIG. 4 shows a sectional view of the semiconductor structure 9 after initial conventional processing has been completed. Structure 9 at this point in the process flow comprises a semiconductor body 14, which includes portions 14r and 14l that are surrounded by regions of Shallow Trench Isolation STI silicon oxide 10, and polysilicon 20a, 20b, 120a, and 120b are covered on top surfaces thereof by remaining portions of a silicon nitride hard mask 30 which was used in the patterning of the polysilicon.
Part PAR_10: A standard wet clean is done to remove the etch residue following the polysilicon etch. Sidewalls of the polysilicon gates 20a, 20b, 120a, and 120b are then oxidized to a thickness of 5 to 15 nm, dependent upon the process and product being produced. Suitable masking is applied and a Lightly Doped Drain (LDD) extension implantation (not shown) to form n-channel transistors is now performed and the structure is annealed. A second layer of silicon oxide is now deposited on the side walls of the polysilicon gates 20a, 20b, 120a and 120b to form side wall spacers 32, as is shown in FIG. 5. Spacers 32 each include the previous oxide grown on the sidewalls of gates 20a, 20b, 120a and 120b. Suitable masking is applied, and a second Lightly Doped Drain extension implantation (not shown) is performed to form p-channel transistors, and the structure is annealed. A third layer of silicon oxide is now deposited on the sidewalls of the polysilicon gates to form a spacer 34, as is shown in FIG. 6. Spacer 34, as shown, includes the previous spacer 32.
Part PAR_11: All the processing up to this point follows conventional processes for the forming of a conventional CMOS Integrated Circuit.
Part PAR_12: FIG. 7 illustrates the structure after the next steps in this first illustrative example, which are the first steps of the innovative method of this invention for forming S/DOI transistors. A blocking layer 36 of silicon nitride is deposited over the surface of the semiconductor body 14. A typical value for the thickness of layer 36 is approximately 20 nm. Standard photolithography techniques are then used to define regions where the blocking silicon nitride layer 36 will remain, and where conventional transistors will be formed. The blocking silicon nitride layer 36 is removed by etching from the region where S/DOI transistors are to be formed. The etchant used should etch silicon nitride but not attack silicon or silicon oxide.
Part PAR_13: FIG. 8 illustrates the structure after the next steps in the process. An anisotropic etch which selectively removes silicon is used to remove the silicon from portions of body 14 adjacent to the polysilicon gates 120a and 120b to from trenches 38. In a typical embodiment the silicon is removed in these trenches 38 to a depth such that the bottom thereof is approximately 60 nm beneath the interface surface 12 between STI oxide 10 and the semiconductor body 14. The silicon underneath the polysilicon gates 120 is not removed.
Part PAR_14: FIG. 9 illustrates the structure after a layer 40 of intrinsic, undoped amorphous silicon has been deposited on the semiconductor body 14. This layer of amorphous silicon 40 fills the trenches 38 where the silicon adjacent to the polysilicon gates 120a and 120b was removed in the previous step.
Part PAR_15: FIG. 10 illustrates the structure after the amorphous silicon layer 40 is anisotropically etched from the surface of the semiconductor body 14. The etch used should selectively etch silicon, and not etch silicon nitride or silicon oxide. In a typical embodiment the etch is controlled to leave approximately 30 nm of silicon 42 in the bottoms of the trenches 38.
Part PAR_16: FIG. 11 illustrates the structure after the semiconductor body 14 has been subjected to a Rapid Thermal Nitridation RTN process which forms a layer of silicon nitride 44 with a typical thickness of approximately 5 nm on all exposed silicon surfaces.
Part PAR_17: FIG. 12 illustrates the structure after the semiconductor body 14 has been exposed to an anisotropic etch which removes the silicon nitride layer 44 from most of the top surface of the amorphous silicon 42 exposed in the area 46, but leaves the silicon nitride 44 on the sidewalls of the silicon underneath the polysilicon gates 120 and underneath the STI oxide 10, and also leaves the majority of the thickness of the blocking nitride layer 36.
Part PAR_18: FIG. 13 illustrates the structure after the semiconductor body 14 has been exposed to a Rapid Thermal Oxidation RTO process which oxidizes the exposed amorphous silicon 42 resulting in a layer of silicon oxide 50 of thickness in the range 50 to 80 nm. The top surface of silicon oxide 50 should be approximately coplanar or overlap with an interface 12 between STI oxide 10 and the semiconductor body 14.
Part PAR_19: FIG. 14 illustrates the structure after the semiconductor body 14 has been exposed to an isotropic silicon nitride etch which removes the exposed portion of the remaining RTN silicon nitride layer 44 but leaves the buried portions 44a and 44aa, and the majority of the thickness of the blocking nitride layer 36.
Part PAR_20: FIG. 15 illustrates the structure after a second layer of undoped intrinsic amorphous silicon 52 has been deposited on the semiconductor body 14. This layer of amorphous silicon fills the area adjacent to the polysilicon gates 120a and 120b. Care must be taken to prevent the formation of a native oxide interface between the intrinsic polysilicon film 52 and the sides of the silicon body region 114a and 114b.
Part PAR_21: FIG. 16 illustrates the structure after the semiconductor body 14 has been exposed to an etch which removes the amorphous silicon 52 to surface 14s such that all of the silicon is removed above STI 10. The etch should selectively etch amorphous silicon, and not etch silicon oxide or silicon nitride. This leaves behind portions 54 of amorphous silicon region 52, which are adjacent to, and conductively connected to portions 114a and 115b of the semiconductor body 14 underneath the polysilicon gates 120a and 120b.
Part PAR_22: FIG. 17 illustrates the structure after the semiconductor body has been exposed to an etch which completely removes the blocking silicon nitride hard mask 30 and silicon nitride layer 36. The etch should selectively etch silicon nitride, and not etch silicon oxide or amorphous silicon and crystalline silicon.
Part PAR_23: Finally, FIG. 18 illustrates the structure after the semiconductor body 14 has been exposed to suitable masking and ion implantation to selectively dope the polysilicon gates 20a, 20b, 120a and 120b, and the amorphous silicon regions 54 and the crystalline silicon regions 56, to selectively form either n-channel or p-channel transistors. These masking and ion implantation operations would be the same as those used in the conventional processing sequence for forming conventional CMOS transistor or Integrated Circuits, and the process sequence from this point forward would follow the conventional process sequence.
Part PAR_24: One alternative variation of the process described in the above first illustrative example of the present invention would result in the elimination of several of the process steps described above, namely the deposition of a first layer 40 of intrinsic, undoped amorphous silicon, illustrated in FIG. 9, and the subsequent anisotropic etch of the layer 40. Starting with the structure as described in FIG. 7, an anisotropic etch which selectively removes silicon is used to remove the silicon from the regions 38 adjacent to the polysilicon gates 120a and 120b, as is shown in FIG. 8. The silicon is removed to a lesser depth than described previously so that the resulting structure is similar to that described in FIG. 10, except that the region 42 is now a portion of the body 14, rather than a remaining portion of the layer 40 of amorphous silicon. The process then continues as described above with the semiconductor body being subjected to a Rapid Thermal Nitridation RTN process to form the layer of silicon nitride 44 as shown in FIG. 11.
Part PAR_25: Referring now to FIG. 19, there is shown a sectional view of a semiconductor structure 209 comprising two partially completed Source/Drain-On-Insulator (S/DOI) field effect transistors (shown on the left) and two partially completed conventional field effect transistors (shown on the right) fabricated in a common semiconductor body 214 in accordance with a second embodiment of the present invention. Semiconductor body 214, which is of a first conductivity type, is typically silicon, and has a major surface 214s. A Shallow Trench Isolation (STI) 210, surrounds the two groups of transistors and extends from the major surface 214 into body 214 to a surface 212. With respect to the conventional transistors, a semiconductor region 216, which is of the opposite conductivity type of body 214, serves as a common source/drain region for the two conventional transistors and is formed in body 214. Regions 217a and 217b, also of the opposite conductivity type, serve as drain/source regions of the left and right conventional transistors, respectively, and are formed in body 214. Regions 214a and 214b of body 214 are channel regions, regions 220a and 220b are polysilicon gates, and layers 221a and 221b are gate oxide layers, of the left and right transistors, respectively. Layers 222a and 222b are oxide layers which cover the sidewalls of the polysilicon gates 220a and 220b, respectively.
Part PAR_26: In the S/DOI transistors shown on the left, portions 314a and 314b of semiconductor body 214 are underneath the polysilicon gates 320a and 320b, respectively. Gates 320a and 320b have the oxide layers 322a and 322b, respectively, on sides thereof. Common source/drain region 316 and the drain/source regions 317a and 317b of the left and right transistors, respectively, are typically formed from an ion-implanted, deposited amorphous silicon layer, as will be described in more detail herein below. Underlying the source/drain region 316 and drain/source regions 317a and 317b of the S/DOI transistors is a silicon oxide layer 242, on whose lower surface and sidewalls is a layer of silicon nitride 213a, which layers are formed as is described herein below. These layers of silicon oxide 242 and silicon nitride 213a restrict the flow of parasitic currents from the source/drain region 316 and drain source regions 317a and 317b of the S/DOI transistors into the semiconductor body 214. The silicon oxide layers 242 and silicon nitride layers 213a also significantly reduce the capacitance of the source/drain region 316 and drain source regions 317a and 317b to the semiconductor body 214. The source/drain region 316 and drain source regions 317a and 317b are resistively connected to the Lightly Doped Drain (LDD) extensions (not shown) which are formed underneath the deposited oxide regions 322a and 322b, as is described herein below. It is to be noted that channel regions 318a and 318b of the S/DOI transistors are subportions of portions 314a and 314b, respectively, of body 214. Thus the S/DOI transistors do not suffer from the floating body effect (FBE) which degrades the performance of transistors formed using a conventional Silicon-on-Insulator SOI process.
Part PAR_27: FIG. 20 shows a sectional view of the semiconductor structure 209 after initial conventional processing has been completed. Structure 209 at this point in the process flow comprises a semiconductor body 214, which includes portions 214r and 214l that are surrounded by regions of Shallow Trench Isolation STI silicon oxide 210, and polysilicon gate conductors 220a, 220b, 320a, and 320b, which are separated from the portions of the semiconductor body 214r and 214l by layers of thin gate oxide 221a, 221b, 321a, and 321b, respectively. The polysilicon gate conductors 220a, 220b, 320a and 320b are covered on their top surface with the remaining portions of a silicon nitride hard mask 230 which was used in the patterning of the polysilicon.
Part PAR_28: A standard wet clean is done to remove the etch residue following the polysilicon etch. Typically, this etch is chosen to selectively remove materials other than silicon oxide. The sidewalls of the polysilicon gates are then oxidized to a thickness of 5 to 15 nm, dependent upon the process and product being produced. Suitable masking is applied and a Lightly Doped Drain LDD extension implantation to form n-channel transistors is now performed and the structure is annealed. A second layer of silicon oxide is now deposited on the sidewalls of the polysilicon gates 220a, 220b, 320a and 320b to form sidewall spacers 232a, 232b, 332a and 332b (shown in FIG. 21). Spacers 232a, 232b, 332a and 332b include the previous oxide grown on the sidewalls of gates 220a, 220b, 320a and 320b. Suitable masking is applied, and a second Lightly Doped Drain (LDD) extension implantation (not shown) is performed to form p-channel transistors, and the structure is annealed. A third layer of silicon oxide is now deposited on the sidewalls of the polysilicon gates 32a, 32b, 220a, and 220b to form spacers 234a, 234b, 334a and 334b, respectively, as is shown in FIG. 22. Spacers 234a, 234b, 334a and 334b, as shown, include the previous spacers 232a, 232b, 332a and 332b.
Part PAR_29: All the processing up to this point follows conventional processes for forming a conventional CMOS Integrated Circuit.
Part PAR_30: FIG. 23 illustrates the structure after the next steps in this second illustrative example, which are the first steps of the innovative method of this invention for forming S/DOI transistors. A blocking layer of silicon nitride 236 of thickness approximately 20 nm is deposited over the surface 214s of the semiconductor body 214. Standard photolithography techniques are then used to define regions where the blocking silicon nitride layer 236 will remain, and where conventional transistors will be formed. The blocking silicon nitride is removed by etching from the region where S/DOI transistors are to be formed. The etchant used should etch silicon nitride but not attack silicon or silicon oxide.
Part PAR_31: FIG. 24 illustrates the structure after the next steps in the process. An anisotropic etch which selectively removes silicon is used to remove the silicon from regions adjacent to the polysilicon gates 320a and 320b to from trenches 238. Silicon is removed in these regions to a depth such that the bottom of trenches 238 is typically approximately 60 nm beneath the surface 212 between STI oxide 210 and the semiconductor body 214. The silicon underneath the polysilicon gates 320a and 320b is not removed.
Part PAR_32: FIG. 25 illustrates the structure after a conformal layer of silicon nitride 213 has been deposited over the surface of the semiconductor body 214. Material other than silicon nitride may be used for this conformal layer. For example, a layer of polysilicon could be used. For the purposes of this detailed description, it is assumed that silicon nitride has been used.
Part PAR_33: FIG. 26 illustrates the structure after a layer of silicon oxide 240 has been deposited on the semiconductor body 214. This layer of silicon oxide 240 fills the trenches 238 where the silicon adjacent to the polysilicon gates 320a and 320b was removed in the previous step.
Part PAR_34: FIG. 27 illustrates the structure after the silicon oxide layer 240 is partially etched from the surface of the semiconductor body 214, leaving silicon oxide region 242 only in bottom portions of trenches 238. The etch used should selectively etch silicon oxide, and not etch silicon nitride or silicon. The etch is controlled to typically leave approximately 50 to 80 nm of silicon oxide 242 in the bottoms of the trenches 238. This silicon oxide region 242 should typically be at or above the interface 212 between the STI oxide 210 and the semiconductor body 214.
Part PAR_35: FIG. 28 illustrates the structure after the semiconductor body has been exposed to an isotropic etch which removes the silicon nitride layer 213 from the top surface of the semiconductor body 214, and from the sidewalls of the portions of regions 238 which are not filled with silicon oxide layer 242, leaving remaining portion 213a. Care must be taken to leave the majority of the thickness of the blocking nitride layer 236.
Part PAR_36: FIG. 29 illustrates the structure after a layer of undoped intrinsic amorphous silicon 252 has been deposited on the semiconductor body 214. This layer of amorphous silicon fills the unfilled portions of trenches 238. Care must be taken to inhibit oxide growth prior to the deposition of the amorphous silicon, so that there is no oxide between the amorphous silicon and the portions of the semiconductor body 314a and 314b under the gates 320a and 320b.
Part PAR_37: FIG. 30 illustrates the structure after the semiconductor body 214 has been exposed to an etch which removes a portion of the amorphous silicon layer 252 to a level just below the surface of the STI oxide 210. The etch should selectively etch amorphous silicon, and not etch silicon oxide or silicon nitride. This leaves behind remaining portions 252a of amorphous silicon regions 252, which are adjacent to, and conductively connected to, the silicon underneath the polysilicon gates 320a and 320b.
Part PAR_38: FIG. 31 illustrates the structure 209 after the semiconductor body 214 has been exposed to an etch which completely removes the silicon nitride hard mask 230 and the blocking nitride layer 236. The etch should selectively etch silicon nitride, and not etch silicon oxide, amorphous silicon, or crystalline silicon.
Part PAR_39: Finally, FIG. 32 illustrates the structure 209 after the semiconductor body has been exposed to suitable masking and ion implantation to selectively dope the polysilicon gates 220a, 220b, 320a and 320b, amorphous silicon regions 254, and the portions of the crystalline silicon regions 214r not underneath gates 220a and 220b, to selectively form either n-channel or p-channel transistors with source/drain regions 316 and 216 and drain source regions 317a, 317b, 217a and 217b. These masking and ion implantation operations would be the same as those used in the conventional processing sequence for forming conventional CMOS transistor or Integrated Circuits, and the process sequence from this point forward would follow the conventional process sequence.
Part PAR_40: It is to be understood that the particular structures and processes described are merely illustrative of the general principles of the invention. Various modifications are possible without departing from the spirit and scope of the invention. For example, the semiconductor body could be of p-type or n-type conductivity or could be gallium arsinide or another semiconductor such as Germanium. Further, the transistors formed could be all n-channel or all p-channel, rather than the combination of both n-channel and p-channel transistors described herein. Further, other dielectric materials than silicon oxide or silicon dioxide could be used to fill the bottom of the trenches, and the dielectric could be either a single material or a composite of several materials. Still further, the source/drain regions could be semiconductor materials other than silicon, and could be either amorphous, partially recrystallized, polycrystalline, or fully single crystal, or Germanium, or a combination of some haveing silicon and other having Germanium. Still further, the source/drain regions could be of a different semiconductor material than the semiconductor body. Still further, the structure of the region which defines the active areas could be different than the Shallow Trench Isolation (STI) structure illustrated, and could use dielectric material other than silicon oxide or silicon dioxide. Further, transistors having a geometry which is different than those described can be used. Furthermore, the concepts described herein may be applied to other types of devices and transistors, such as, for example, bipolar transistors, and in general to all types of semiconductor devices where it is necessary to reduce the parasitic current flowing between various devices, to reduce the capacitance between various elements of the devices, and also to provide a known potential to the semiconductive material in which the device is fabricated.


{'bibliographic_information': "{'Patent Number': '062948172', 'Series Code': '9', 'Application Number': '4594835', 'Application Type': '1', 'Art unit': '285', 'Application Filing Date': '19991213', 'Title of Invention': 'Source/drain-on insulator (S/DOI) field effect transistor using oxidized amorphous silicon and method of fabrication', 'Issue Date': '20010925', 'Number of Claims': '16', 'Exemplary Claim Number(s)': '1', 'Primary Examiner': 'Wojciechowicz; Edward', 'Number of Drawing Sheets': '16', 'Number of figures': '32'}", 'source_file': './grant/2001/pftaps20010925_wk39.txt', 'source_data': 'USPTO-Grant'}