Title of Invention: Non-volatile memory (NVM) express (NVMe) data processing method and system Abstract: A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved. Detailed Description: Part general_description_paragraphs: Part CROSS-REFERENCE TO RELATED APPLICATIONS: This application is a continuation of International Patent Application No. PCT/CN2018/093919, filed on Jun. 30, 2018, the disclosure of which is hereby incorporated by reference in its entirety. Part TECHNICAL FIELD: This application relates to the storage field, and in particular, to a data processing method and a storage system. Part BACKGROUND: With development of storage technologies, especially with continuous improvement of solid-state drive (SSD) performance in a storage device using an SSD as a storage medium, a serial advanced technology attachment (SATA) interface standard and a serial ATA advanced host controller interface/advanced host controller interface (AHCI) standard designed for a conventional hard disk drive cannot meet requirements of the SSD, becoming a bottleneck that limits an SSD processing capability. Therefore, a non-volatile memory express (NVMe) emerges. The NVMe is an interface that allows a host to communicate with a non-volatile memory (NVM) subsystem, and the interface used by the NVM subsystem (including a controller and at least one SSD) for communication is attached to a Peripheral Component Interconnect (PCI) express (PCIe) interface using a register interface, to optimize enterprise-grade solid-state storage and consumer-grade solid-state storage. This provides advantages of high performance and a low access delay. In an NVMe data processing process, the host creates an input/output (I/O) submission queue and an I/O completion queue in a memory of the host, and an NVMe controller completes data processing based on a mechanism including a pair of an I/O submission queue and an I/O completion queue. The I/O submission queue is a ring buffer used for storing one or more data operation requests to be executed by the controller, and the I/O completion queue is a ring buffer used for storing an operation result of a data operation request completed by the controller. Each I/O submission queue corresponds to one I/O completion queue, and one I/O completion queue may correspond to a plurality of I/O submission queues. A matching relationship between an I/O completion queue and an I/O submission queue is specified by the host. An operation result of a to-be-executed data operation request in each I/O submission queue is stored in a specified I/O completion queue. The NVMe data processing process includes: when the host receives one or more to-be-executed data operation requests, the host first stores the one or more data operation requests in an I/O submission queue. Then, the host updates an I/O submission queue tail doorbell register (located in a storage area of the NVMe controller), and notifies the NVMe controller of the to-be-executed data operation requests using a doorbell. The NVMe controller obtains the to-be-executed data operation request in the I/O submission queue in a direct memory access (DMA) read manner. After processing the data operation request, the NVMe controller stores an operation result in an I/O completion queue in a DMA write manner. The I/O completion queue is an I/O completion queue that matches an I/O submission queue used by the NVMe controller to obtain a data operation requests. Each time the NVMe controller stores an operation result of a data operation request in the I/O completion queue, the NVMe controller first sends an interrupt request to the host, to notify the host that the data operation request is completed. In the foregoing process, the host and the NVMe controller need to notify each other in an interrupt manner using a doorbell mechanism. Consequently, a data processing process is complex. Part SUMMARY: This application provides a data processing method and a storage system, to resolve a problem that a data processing process is complex in a conventional technology. According to a first aspect, this application provides a data processing method, and the method includes: communicating, by a non-volatile memory express (NVMe) controller, with a host using a PCIe bus; receiving, by the NVMe controller, a first PCIe packet sent by the host; and storing at least one submission queue entry (SQE) in a target I/O submission queue based on entrance information of the target I/O submission queue. A memory in the NVMe controller is provided with at least one I/O submission queue. The first PCIe packet includes the entrance information of the target I/O submission queue and the at least one SQE. One SQE corresponds to one data operation request, and each data operation request is used to perform a read or write operation on a storage medium managed by the NVMe controller. In this application, data is stored in an I/O submission queue on a side of the NVMe controller, and the host directly sends an SQE to the NVMe controller using a PCIe packet. Therefore, this avoids a case in which the host needs to update, when sending each SQE, an I/O submission queue tail doorbell register (located in a storage area of the NVMe controller) to notify the NVMe controller of a to-be-executed data operation request, and the NVMe controller reads the SQE from an I/O submission queue of a memory in the host based on a doorbell using a PCIe. The host and the NVMe controller communicate with each other based on the entrance information of the target I/O submission queue, and the NVMe controller may store the SQE based on the entrance information of the target I/O submission queue. Therefore, a doorbell mechanism in a conventional technology can be cancelled, and a data processing process is simplified. In a possible implementation, the entrance information of the target I/O submission queue is a unique first PCIe address in an addressable PCIe address space of the host, and a process in which the NVMe controller stores the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue includes: determining a second address based on the first PCIe address, where the second address is an address at which the target I/O submission queue is stored in the memory of the NVMe controller; and storing the at least one SQE in the target I/O submission queue based on the second address. In a possible implementation, a process in which the NVMe controller determines the second address based on the first PCIe address includes: an identifier of the target I/O submission queue is first determined based on the first PCIe address of the target I/O submission queue, and then the second address is determined based on the identifier of the target I/O submission queue. In this application, all I/O submission queues may be marked using PCIe addresses in the addressable PCIe address space of the host. One PCIe address is allocated to each I/O submission queue, and the PCIe address is used as entrance information of the I/O submission queue. The NVMe controller may store the at least one SQE in the target I/O submission queue based on the PCIe address. In another possible implementation, the NVMe controller calculates the identifier of the target I/O submission queue according to the following formula: the ⁢ ⁢ identifier ⁢ ⁢ of ⁢ ⁢ the ⁢ ⁢ target ⁢ ⁢ I / O ⁢ ⁢ submission ⁢ ⁢ queue = ADD 11 - ADD 12 MCS × 64 . Herein, ADD11 is the first PCIe address of the target I/O submission queue, ADD12 is a start address that is of consecutive address spaces allocated from the addressable PCIe address space of the host and that is used to identify each I/O submission queue, and the MCS is a maximum quantity of coalesced SQEs in each I/O submission queue. Through calculation using the foregoing formula, the NVMe controller may determine the identifier of the target I/O submission queue and a storage location of the I/O submission queue in the memory of the NVMe controller, and further store the at least one SQE in the target I/O submission queue. In another possible implementation, before the NVMe controller receives the first PCIe packet of the host, the NVMe controller receives a creation instruction of the host, sets the at least one I/O submission queue in the memory of the NVMe controller according to the creation instruction, and records an association relationship between an identifier of each I/O submission queue and information about an address of each I/O submission queue in the memory of the NVMe controller. According to the method in the foregoing process, the NVMe controller may create the at least one I/O submission queue according to a service requirement, to store data in the I/O submission queue. In another possible implementation, before the NVMe controller receives the creation instruction of the host, the NVMe controller negotiates the maximum quantity of coalesced SQEs (MCS) in each I/O submission queue with the host. The MCS obtained through negotiation is a smaller value of a maximum quantity of coalesced SQEs in each I/O submission queue supported by the NVMe controller and a maximum quantity of coalesced SQEs in each I/O submission queue supported by the host. The NVMe controller and the host may determine, in an MCS negotiation manner, a maximum quantity of SQEs that can be pushed by the host each time, in other words, a maximum quantity of SQEs that can be carried in one PCIe packet. In this push manner, a quantity of packets between the host and the NVMe controller can be reduced, and data processing efficiency is improved. In another possible implementation, before the NVMe controller receives the creation instruction of the host, the NVMe controller negotiates a maximum quantity of coalesced CQEs (MCC) in each I/O completion queue with the host. The MCC obtained through negotiation is a smaller value of a maximum quantity of coalesced CQEs in each I/O completion queue supported by the NVMe controller and a maximum quantity of coalesced CQEs in each I/O completion queue supported by the host. The NVMe controller and the host may determine, in an MCC negotiation manner, a maximum quantity of CQEs that can be pushed by the NVMe controller each time, in other words, a maximum quantity of CQEs that can be carried in one PCIe packet. In this push manner, a quantity of packets between the host and the NVMe controller can be reduced, and data processing efficiency is improved. Optionally, a process in which the host negotiates the MCC with the NVMe controller and a process in which the host negotiates the MCS with the NVMe controller may be simultaneously performed. In other words, a negotiation request packet sent by the host includes both MCS negotiation content and MCC negotiation content. A response result returned by the NVMe controller for the negotiation request packet also includes both the MCS and the MCC that are determined by the NVMe controller. Alternatively, a process in which the host negotiates the MCC with the NVMe controller and a process in which the host negotiates the MCS with the NVMe controller may be separately performed. The MCC is determined using different negotiation request packets. In another possible implementation, the first PCIe packet further includes depth information M of the target I/O submission queue, M indicates a quantity of SQEs carried in the first PCIe packet, and 1≤M≤MCS. The storing, by the NVMe controller, the at least one SQE in the target I/O submission queue includes: determining a preset sequence of M SQEs, and storing the M SQEs in the target I/O submission queue in the preset sequence of the M SQEs. The preset sequence of the M SQEs is a sequence in which the host receives data operation requests. According to the descriptions of the foregoing process, the NVMe controller may store the SQEs in the sequence in which the host receives data operation requests, in order to ensure that a sequence of storing SQEs in an I/O submission queue in the memory of the NVMe controller is consistent with the sequence in which the host receives data operation requests. In another possible implementation, a memory in the host is provided with at least one I/O completion queue. The NVMe controller obtains the at least one SQE from the target I/O submission queue; performs, based on a data operation request carried in the at least one SQE, a read or write operation on a storage medium managed by the NVMe controller; and sends a second PCIe packet to the host. The second PCIe packet includes entrance information of a target I/O completion queue and at least one completion queue entry (CQE). Each CQE is an operation result of a data operation request that is carried in each SQE and that is executed by the NVMe controller. According to the descriptions of the foregoing process, the NVMe controller may also store the at least one CQE in the target I/O completion queue based on the entrance information of the target I/O completion queue. Therefore, an interrupt mechanism in a conventional technical solution is cancelled, a data processing process is simplified, and processing efficiency is improved. In another possible implementation, when a CQE coalescing condition is met, the NVMe controller uses operation results of at least two data operation requests as payload data of the second PCIe packet. One CQE corresponds to an operation result of one data operation request. The CQE coalescing condition includes: a maximum coalesced CQE size MCCB meets a first threshold, or a time recorded by an I/O completion queue coalescing timer CQT meets a second threshold. The NVMe controller may send a plurality of CQEs to the host in a push manner using a same PCIe packet. In other words, the NVMe controller simultaneously uses a plurality of CQEs as payload data of one PCIe packet, and sends the packet to the host. This reduces a quantity of packets between the host and the NVMe controller, and improves processing efficiency. In another possible implementation, the second PCIe packet further includes depth information N of the target I/O completion queue, and N indicates a quantity of CQEs carried in the second PCIe packet. The NVMe controller uses N CQEs as the payload data of the second PCIe packet in a preset sequence, where 1≤N≤MCC, and the MCC is a positive integer. The preset sequence of the N CQEs is a sequence in which the NVMe controller completes operation results generated for corresponding SQEs. It is ensured, in the second PCIe packet using the preset sequence, that a sequence in which the host stores operation results is consistent with a sequence in which the NVMe controller actually generates operation results. In another possible implementation, the host is an embedded processor, and the embedded processor can send a PCIe packet with a capacity of at least 64 bytes. In a possible embodiment, in addition to using a segment of consecutive first address spaces in a base address register to allocate PCIe addresses to a plurality of I/O submission queues, the host may also use several inconsecutive storage spaces in the base address register to represent all I/O submission queues. In this case, the host and the NVMe controller each record a mapping relationship between an address allocated to each I/O submission queue and an identifier of the I/O submission queue, and the host may send the first PCIe packet to the NVMe controller based on the mapping relationship. The first PCIe packet includes a PCIe address allocated by the host to the target I/O submission queue, and the PCIe address is used as the entrance information of the target I/O submission queue. Therefore, the NVMe controller may parse the first PCIe packet to obtain a PCIe address field allocated by the host to the target I/O submission queue; then determine, based on the mapping relationship, an identifier of an I/O submission queue corresponding to the PCIe address field; and store the at least one SQE of the first PCIe packet in the target I/O submission queue based on the identifier of the I/O submission queue. In this way, a process in which the NVMe controller stores the at least one SQE based on the entrance information of the target I/O submission queue is completed. In the foregoing process, a doorbell mechanism in a conventional technology can also be avoided, and a data processing process is simplified. In addition, the host may send, in a push manner, a plurality of SQEs to the NVMe controller under an SQE coalescing condition using a same PCIe packet. This reduces a quantity of message packets between the host and the NVMe controller, and improves data processing efficiency. In another possible embodiment, the addressable PCIe address space of the host includes an address space of the memory in the host and an address space of a PCIe base address register in the host. In addition to using address in the address space of the base address register to map identifiers of all I/O submission queues in the foregoing step, addresses in the address space of the memory in the host may also be used to map the identifiers of all the I/O submission queues in this embodiment of the present application. The identifier of each I/O submission queue corresponds to a unique PCIe address. In this case, the host stores a mapping relationship between an address in the address space of the memory and an identifier of an I/O submission queue. The host may send, to the NVMe controller based on the mapping relationship, a PCIe packet that carries at least one SQE. Alternatively, the NVMe controller may determine, based on the mapping relationship and a mapping address carried in the PCIe packet, an identifier of an I/O submission queue corresponding to the mapping address, and further store the at least one SQE in the target I/O submission queue. According to the foregoing method, a doorbell mechanism in a conventional technology can also be cancelled, and a data processing process is simplified. In addition, the host sends a plurality of SQEs to the NVMe controller under the SQE coalescing condition using a same PCIe packet. This reduces a quantity of message packets between the host and the NVMe controller, and improves data processing efficiency. In another possible embodiment, in addition to mapping an identifier of an I/O submission queue according to a PCIe protocol using an address, the host and the NVMe controller may also transmit the identifier of the target I/O submission queue to the NVMe controller based on a pre-agreement using a specified field in a PCIe packet or a part of payload data. Then the NVMe controller parses the PCIe packet to obtain the foregoing specified field (for example, a reserved field in the PCIe packet or a start bit of the payload data), and determines, based on the pre-agreement, the identifier of the I/O submission queue indicated by the specified field. Therefore, a doorbell mechanism in a conventional technology can also be cancelled, and a data processing process is simplified. According to a second aspect, this application provides a data processing method, and the method includes: communicating, by an NVMe controller, with a host using a PCIe bus; determining, by the host, entrance information of a target I/O submission queue based on an identifier of the target I/O submission queue of a to-be-sent data operation request; and sending a first PCIe packet to the NVMe controller. A memory in the NVMe controller is provided with at least one I/O submission queue. The first PCIe packet includes the entrance information of the target I/O submission queue and at least one SQE. One SQE corresponds to one data operation request, and each data operation request is used to perform a read or write operation on a storage medium managed by the NVMe controller. In a possible implementation, the host allocates a unique PCIe address in an addressable PCIe address space of the host to each I/O submission queue. The entrance information of the target I/O submission queue is a first PCIe address of the target I/O submission queue, and the addressable PCIe address space of the host is a storage space of a memory in the host or an address space of a PCIe base address register in the host. The host determines the first PCIe address of the target I/O submission queue based on the identifier of the target I/O submission queue. In another possible implementation, the host sends a creation instruction to the NVMe controller. The creation instruction is used to instruct the NVMe controller to set the at least one I/O submission queue in the memory of the NVMe controller, and record an association relationship between an identifier of each I/O submission queue and a first PCIe address of each I/O submission queue. In another possible implementation, before the host sends the creation instruction to the NVMe controller, the host negotiates a maximum quantity of coalesced SQEs MCS in each I/O submission queue with the NVMe controller. The MCS obtained through negotiation is a smaller value of a maximum quantity of coalesced SQEs in each I/O submission queue supported by the NVMe controller and a maximum quantity of coalesced SQEs in each I/O submission queue supported by the host. In another possible implementation, the first PCIe packet further includes depth information M of the target I/O submission queue, M indicates a quantity of SQEs carried in the first PCIe packet, and 1≤M≤MCS. In another possible implementation, before the first PCIe packet is sent, when an SQE coalescing condition is met, the host uses at least two SQEs as payload data of the first PCIe packet. One data operation request corresponds to one SQE, and each data operation request is used to perform a read or write operation on a storage medium managed by the NVMe controller. The SQE coalescing condition includes: a maximum coalesced SQE size MCSB meets a third threshold, or a time recorded by an I/O submission queue coalescing timer SQT meets a fourth threshold. In another possible implementation, the host receives a second PCIe packet sent by the NVMe controller, where the second PCIe packet includes entrance information of a target I/O completion queue and at least one CQE, and each CQE is an operation result of a data operation request that is carried in each SQE and that is executed by the NVMe controller; and stores the at least one CQE in the target I/O completion queue based on the entrance information of the target I/O completion queue. In another possible implementation, the entrance information of the target I/O completion queue is a unique second PCIe address in the addressable PCIe address space of the host, and a process in which the host stores the at least one CQE in the target I/O completion queue based on the entrance information of the target I/O completion queue includes: a third address is first determined based on the second PCIe address, where the third address is an address at which the target I/O completion queue is stored in the memory of the host; and then the at least one CQE is stored in the target I/O completion queue based on the third address. In another possible implementation, a process in which the host determines the third address based on the second PCIe address includes: an identifier of the target I/O completion queue is first determined based on the second PCIe address, and then the third address is determined based on the identifier of the target I/O completion queue. In another possible implementation, the host calculates the identifier of the target I/O completion queue according to the following formula: the ⁢ ⁢ identifier ⁢ ⁢ of ⁢ ⁢ the ⁢ ⁢ target ⁢ ⁢ I / O ⁢ ⁢ completion ⁢ ⁢ queue = ADD 21 - ADD 22 MCC × 64 . Herein, ADD21 is the second PCIe address of the target I/O completion queue, ADD22 is a start address that is of consecutive address spaces allocated from the addressable PCIe address space of the host and that is used to identify each I/O completion queue, and the MCC is a maximum quantity of coalesced CQEs in each I/O completion queue. The host stores the at least one CQE in the memory of the host based on the identifier of the target I/O completion queue. In another possible implementation, the host is an embedded processor, and the embedded processor can send a PCIe packet with a capacity of at least 64 bytes. In a possible embodiment, in addition to using a segment of consecutive first address spaces in a base address register to allocate PCIe addresses to a plurality of I/O completion queues, the host may also use several inconsecutive storage spaces in the base address register to represent all I/O completion queues. In this case, the host and the NVMe controller each record a mapping relationship between an address allocated to each I/O completion queue and an identifier of the I/O completion queue, and the NVMe controller may send the second PCIe packet to the host based on the mapping relationship. The second PCIe packet includes a PCIe address allocated by the host to the target I/O completion queue, and the PCIe address is used as the entrance information of the target I/O completion queue. Therefore, the host may parse the second PCIe packet to obtain a PCIe address field allocated to the target I/O submission queue; then determine, based on the mapping relationship, an identifier of an I/O completion queue corresponding to the PCIe address field; and store the at least one CQE of the second PCIe packet in the target I/O completion queue based on the identifier of the I/O completion queue. In this way, a process in which the host stores the at least one CQE based on the entrance information of the target I/O completion queue is completed. In the foregoing process, an interrupt mechanism in a conventional technology can also be cancelled, and a data processing process is simplified. In addition, the NVMe controller may send, in a push manner using a same PCIe packet, a plurality of CQEs to the host in a CQE coalescing manner in the method shown in FIG. 3A, FIG. 3B, and FIG. 3C. This reduces a quantity of message packets between the host and the NVMe controller, and improves data processing efficiency. In another possible embodiment, the addressable PCIe address space of the host includes an address space of the memory in the host and an address space of a PCIe base address register in the host. In addition to using address in the address space of the base address register to map identifiers of all I/O completion queues in the foregoing step, addresses in the address space of the memory in the host may also be used to map the identifiers of all the I/O completion queues in this embodiment of the present application. The identifier of each I/O completion queue corresponds to a unique address. In this case, the host and the NVMe controller each store a mapping relationship between an address in the address space of the memory and an identifier of an I/O completion queue. The NVMe controller may send, to the host based on the mapping relationship, a PCIe packet that carries at least one CQE. Alternatively, the host may determine, based on the mapping relationship and a mapping address carried in the PCIe packet, an identifier of an I/O completion queue corresponding to the mapping address, and further store the at least one CQE in the target I/O completion queue. According to the foregoing method, an interrupt mechanism in a conventional technology can also be cancelled, and a data processing process is simplified. In addition, the NVMe controller may send, in a CQE coalescing manner shown in FIG. 3A, FIG. 3B, and FIG. 3C, a plurality of CQEs to the host using a same PCIe packet. This reduces a quantity of message packets between the host and the NVMe controller, and improves data processing efficiency. In another possible implementation, in addition to identifying the target I/O completion queue according to a PCIe standard using an address, the NVMe controller may also transmit the identifier of the target I/O completion queue to the host based on a pre-agreement using a specified field in a PCIe packet or a part of payload data. Then the host parses, based on the pre-agreement, the PCIe packet using the foregoing specified field (for example, a reserved field in the PCIe packet or a start bit of the payload data), to obtain the identifier of the target I/O completion queue carried in the PCIe packet, and stores an operation result in the I/O completion queue. In another possible implementation, the host records a correspondence between an I/O submission queue and an I/O completion queue. Correspondingly, the second PCIe packet may also directly carry the identifier of the target I/O submission queue. After receiving the second PCIe packet, the host may obtain the identifier of the target I/O submission queue; then determine the target I/O completion queue based on the correspondence between an I/O submission queue and an I/O completion queue; and store, in the target I/O completion queue, the at least one CQE carried in the second PCIe packet. According to a third aspect, this application provides a data processing method, and the method includes: communicating, by an NVMe controller, with a host using a PCIe bus standard; receiving, by the NVMe controller, a first PCIe packet sent by the host; and storing at least one SQE in a target I/O submission queue based on entrance information of the target I/O submission queue. A memory in the NVMe controller is provided with at least one I/O submission queue. The first PCIe packet includes the entrance information of the target I/O submission queue and the at least one SQE. One SQE corresponds to one data operation request, and each data operation request is used to perform a read or write operation on a storage medium managed by the NVMe controller. In this application, data is stored in an I/O submission queue on a side of the NVMe controller, and the host directly sends an SQE to the NVMe controller using a PCIe packet. Therefore, this avoids a case in which the host needs to update, when sending each SQE, an I/O submission queue tail doorbell register (located in a storage area of the NVMe controller) to notify the NVMe controller of a to-be-executed data operation request, and the NVMe controller reads the SQE from an I/O submission queue of a memory in the host based on a doorbell using a PCIe. The host and the NVMe controller communicate with each other based on the entrance information of the target I/O submission queue, and the NVMe controller may store the SQE based on the entrance information of the target I/O submission queue. Therefore, a doorbell mechanism in a conventional technology can be cancelled, and a data processing process is simplified. In a possible implementation, the entrance information of the target I/O submission queue is a unique first PCIe address in an addressable PCIe address space of the host, and a process in which the NVMe controller stores the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue includes: determining a second address based on the first PCIe address, where the second address is an address at which the target I/O submission queue is stored in the memory of the NVMe controller; and storing the at least one SQE in the target I/O submission queue based on the second address. In a possible implementation, a process in which the NVMe controller determines the second address based on the first PCIe address includes: an identifier of the target I/O submission queue is first determined based on the first PCIe address of the target I/O submission queue, and then the second address is determined based on the identifier of the target I/O submission queue. In this application, all I/O submission queues may be marked using PCIe addresses in the addressable PCIe address space of the host. One PCIe address is allocated to each I/O submission queue, and the PCIe address is used as entrance information of the I/O submission queue. The NVMe controller may store the at least one SQE in the target I/O submission queue based on the PCIe address. In another possible implementation, the NVMe controller calculates the identifier of the target I/O submission queue according to the following formula: the ⁢ ⁢ identifier ⁢ ⁢ of ⁢ ⁢ the ⁢ ⁢ target ⁢ ⁢ I / O ⁢ ⁢ submission ⁢ ⁢ queue = ADD 11 - ADD 12 MCS × 64 . Herein, ADD11 is the first PCIe address of the target I/O submission queue, ADD12 is a start address that is of consecutive address spaces allocated from the addressable PCIe address space of the host and that is used to identify each I/O submission queue, and the MCS is a maximum quantity of coalesced SQEs in each I/O submission queue. Through calculation using the foregoing formula, the NVMe controller may determine the identifier of the target I/O submission queue, determine a storage location of the target I/O submission queue in the NVMe controller based on the identifier of the target I/O submission queue, and further store the at least one SQE in the target I/O submission queue. In another possible implementation, before the NVMe controller receives the first PCIe packet of the host, the NVMe controller receives a creation instruction of the host, sets the at least one I/O submission queue in the memory of the NVMe controller according to the creation instruction, and records an association relationship between an identifier of each I/O submission queue and information about an address of each I/O submission queue in the memory of the NVMe controller. According to the method in the foregoing process, the NVMe controller may create the at least one I/O submission queue according to a service requirement, to store data in the I/O submission queue. In another possible implementation, before the NVMe controller receives the creation instruction of the host, the NVMe controller negotiates the maximum quantity of coalesced SQEs MCS in each I/O submission queue with the host. The MCS obtained through negotiation is a smaller value of a maximum quantity of coalesced SQEs in each I/O submission queue supported by the NVMe controller and a maximum quantity of coalesced SQEs in each I/O submission queue supported by the host. The NVMe controller and the host may determine, in an MCS negotiation manner, a maximum quantity of SQEs that can be pushed by the host each time, in other words, a maximum quantity of SQEs that can be carried in one PCIe packet. In this push manner, a quantity of packets between the host and the NVMe controller can be reduced, and data processing efficiency is improved. In another possible implementation, the first PCIe packet further includes depth information M of the target I/O submission queue, M indicates a quantity of SQEs carried in the first PCIe packet, and 1≤M≤MCS. The storing, by the NVMe controller, the at least one SQE in the target I/O submission queue includes: determining a preset sequence of M SQEs, and storing the M SQEs in the target I/O submission queue in the preset sequence of the M SQEs. The preset sequence of the M SQEs is a sequence in which the host receives data operation requests. According to the descriptions of the foregoing process, the NVMe controller may store the SQEs in the sequence in which the host receives data operation requests, in order to ensure that a sequence of storing SQEs in an I/O submission queue in the memory of the NVMe controller is consistent with the sequence in which the host receives data operation requests. According to a fourth aspect, this application provides a data processing method, and the method includes: a memory in a host is provided with at least one I/O completion queue; and an NVMe controller obtains at least one SQE from a target I/O submission queue, performs, based on a data operation request carried in the at least one SQE, a read or write operation on a storage medium managed by the NVMe controller, and sends a second PCIe packet to the host. The second PCIe packet includes entrance information of a target I/O completion queue and at least one completion queue entry (CQE). Each CQE is an operation result of a data operation request that is carried in each SQE and that is executed by the NVMe controller. According to the descriptions of the foregoing process, the NVMe controller may also store the at least one CQE in the target I/O completion queue based on the entrance information of the target I/O completion queue. Therefore, an interrupt mechanism in a conventional technical solution is cancelled, a data processing process is simplified, and processing efficiency is improved. In a possible implementation, when a CQE coalescing condition is met, the NVMe controller uses operation results of at least two data operation requests as payload data of the second PCIe packet. One CQE corresponds to an operation result of one data operation request. The CQE coalescing condition includes: a maximum coalesced CQE size MCCB meets a first threshold, or a time recorded by an I/O completion queue coalescing timer CQT meets a second threshold. The NVMe controller may send a plurality of CQEs to the host in a push manner using a same PCIe packet. In other words, the NVMe controller simultaneously uses a plurality of CQEs as payload data of one PCIe packet, and sends the packet to the host. This reduces a quantity of packets between the host and the NVMe controller, and improves processing efficiency. In another possible implementation, the second PCIe packet further includes depth information N of the target I/O completion queue, and N indicates a quantity of CQEs carried in the second PCIe packet. The NVMe controller uses N CQEs as the payload data of the second PCIe packet in a preset sequence, where 1≤N≤MCC, and the MCC is a positive integer. The preset sequence of the N CQEs is a sequence in which the NVMe controller completes operation results generated for corresponding SQEs. It is ensured, in the second PCIe packet using the preset sequence, that a sequence in which the host stores operation results is consistent with a sequence in which the NVMe controller actually generates operation results. In another possible implementation, the host is an embedded processor, and the embedded processor can send a PCIe packet with a capacity of at least 64 bytes. According to a fifth aspect, this application provides a data processing apparatus, and the apparatus includes modules configured to perform the data processing methods in any one of the foregoing aspects or the possible implementations of the foregoing aspects. According to a sixth aspect, this application provides a storage system for data processing. The storage system includes a host, an NVMe controller, a first memory, and a second memory. The host, the NVMe controller, the first memory, and the second memory communicate with each other using a PCIe bus. The first memory stores a computer instruction executed by the host, and stores data in an I/O completion queue. The second memory stores a computer instruction executed by the NVMe controller, and stores data in an I/O submission queue. When the storage system runs, the NVMe controller is configured to execute a computer executable instruction in the second memory, to perform operation steps of the method according to the first aspect or any possible implementation of the first aspect and the method according to the third aspect or any possible implementation of the third aspect using hardware resources in the storage system. The host is configured to execute a computer executable instruction in the first memory, to perform operation steps of the method according to the second aspect or any possible implementation of the second aspect and the method according to the fourth aspect or any possible implementation of the fourth aspect using hardware resources in the storage system. According to a seventh aspect, this application provides a computer readable storage medium, and the computer readable storage medium stores an instruction. When the instruction runs on a computer, the computer is enabled to perform the methods in the foregoing aspects. According to an eighth aspect, this application provides a computer program product including an instruction. When the instruction runs on a computer, the computer is enabled to perform the methods in the foregoing aspects. In this application, the implementations provided in the foregoing aspects can be further combined to provide more implementations. Part DESCRIPTION OF EMBODIMENTS: The following describes the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. FIG. 1 is a schematic diagram of an architecture of a storage system 100 according to an embodiment of the present application. As shown in the figure, the storage system 100 includes a host 101, an NVMe controller 102, at least one solid-state drive (SSD) 103, a first memory 104, and a second memory 105. The host and the NVMe controller each are provided with a memory. For ease of subsequent description, a memory in the host is referred to as the first memory 104, and a memory in the NVMe controller is referred to as the second memory 105. The host 101, the NVMe controller 102, the at least one SSD 103, the first memory 104, and the second memory 105 communicate with each other using a Peripheral Component Interconnect express (PCIe) bus standard. In this embodiment of the present application, the host 101 is a processor, and the processor may be a central processing unit (CPU), or the processor may be another general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or another programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or the like. The general-purpose processor may be a microprocessor, any conventional processor, or the like. Alternatively, the processor may be a system on a chip (SoC) or an embedded processor. The processor can send a PCIe packet with a capacity of at least 64 bytes. The first memory 104 and the second memory 105 each may be implemented by a random access memory (RAM) or another storage medium. In the storage system, the NVMe controller 102 and the at least one solid-state drive 103 may be collectively referred to as an NVM subsystem. The NVMe subsystem is configured to receive and execute a data operation request sent by the host. Each data operation request is used to perform a read or write operation on the solid-state drive 103 managed by the NVMe controller 102. It should be understood that, in the architecture of the storage system shown in FIG. 1, there may be one or more NVMe controllers 102, and only one NVMe controller is shown in the figure. When the storage system includes a plurality of NVMe controllers, an active-state NVMe controller communicates with the host, and other NVMe controllers are used as standby-state NVMe controllers. When the active-state NVMe controller is faulty, one standby-state NVMe controller is upgraded to the active-state NVMe controller. In this embodiment of this application, an example in which the storage system includes only one NVMe controller is used for description. An NVMe data processing process is implemented based on an input/output (I/O) submission queue (SQ) and an I/O completion queue (CQ). The I/O submission queue is used to store a data operation request. The data operation request is invoked by an upper-layer application and is sent to the host using a host interface. The data operation request includes a request of reading data stored in the SSD and a request of writing data into the SSD. For example, the first memory 104 of the host 101 is configured to store data in the I/O completion queue, and the second memory 105 of the NVMe controller 102 is configured to store data in the I/O submission queue. The I/O submission queue is a logical concept and includes one or more units. Each unit stores one data operation request, and each data operation request may be stored in a storage space of a maximum of 64 bytes. The I/O submission queue corresponds to a ring buffer used for storing one or more data operation requests, and may be represented using a physical region page (PRG) or a scatter/gather list (SGL). Each data operation request (which may also be referred to as a submission queue entry (SQE) or a submission queue element (SQE)) may be stored in one unit of the I/O submission queue. The unit may be referred to as a slot of the I/O submission queue, and each slot corresponds to two PRGs or one SGL in the buffer. The I/O submission queue is provided with a head pointer and a tail pointer. The head pointer is used to indicate a slot of an SQE that can be removed at a current moment, and the tail pointer is used to indicate a slot of a newly added SQE that can be stored at a current moment. In an initialization phase, the head pointer=the tail pointer=0. Each time a new SQE is added to the I/O submission queue, 1 is added to the tail pointer. Each time an SQE is removed from the I/O submission queue, 1 is added to the head pointer. To-be-executed data operation requests need to be successively stored in slots of a submission queue in a receiving sequence, and then are successively read in a first in first out (FIFO) sequence. The I/O completion queue is a ring buffer used for storing an operation result of a data operation request completed by the NVMe controller. Similar to a structure of the I/O submission queue, the I/O completion queue is also a logical concept, and includes one or more units. Each unit may be referred to as a slot. The I/O completion queue also corresponds to a ring buffer used for storing operation results of one or more data operation requests, and may be represented using a PRG or an SGL. The operation result of each data operation request may also be referred to as a completion queue entry (CQE) or a completion queue element (CQE). Each I/O submission queue corresponds to one I/O completion queue, and one I/O completion queue may correspond to a plurality of I/O submission queues. A matching relationship between an I/O completion queue and an I/O submission queue is specified by the host. An operation result of a data operation request in each I/O submission queue is stored in a specified I/O completion queue. Further, the NVMe data processing process further includes a management submission queue and a management completion queue. The management submission queue is used to store management requests of the host and the NVMe controller. For example, a request of creating an I/O submission queue by the host may be stored in the management submission queue. The management completion queue is used to store an operation result of a data operation request completed by the NVMe controller. For example, the management submission queue and the management completion queue may be stored in the first memory of the host. Logical structures of the management submission queue and the management completion queue are similar to that of the I/O submission queue and the I/O completion queue. Details are not described herein again. In a conventional NVMe data processing process, the memory in the host implements the I/O submission queue and the I/O completion queue. In addition, the host and the NVMe controller need to communicate with each other in an interrupt manner using a doorbell mechanism. The I/O submission queue includes a data operation request, and an operation result of the data operation request is stored in the I/O completion queue. Consequently, an entire NVMe data processing process is complex. In the following embodiments of the present application, a process of implementing an I/O submission queue and an I/O completion queue is mainly improved, but the management submission queue and the management completion queue are still implemented using a conventional technical solution. In other words, the management submission queue and the management completion queue are still stored in the memory of the host. In a data processing process, the host first
{'bibliographic_information': "{'country': 'US', 'doc-number': '16673320', 'kind': 'B2', 'date': '20191104', 'extension': '56', 'invention_title': 'Non-volatile memory (NVM) express (NVMe) data processing method and system'}", 'source_file': './grant/2021/ipg211109.xml', 'source_data': 'USPTO-Grant'}