Title of Invention: BOOSTING CIRCUIT AND RFID TAG INCLUDING BOOSTING CIRCUIT Abstract: One object is to provide a boosting circuit whose boosting efficiency is enhanced. Another object is to provide an RFID tag including a boosting circuit whose boosting efficiency is enhanced. A node corresponding to an output terminal of a unit boosting circuit or a gate electrode of a transistor connected to the node is boosted by bootstrap operation, so that a decrease in potential which corresponds to substantially the same as the threshold potential of the transistor can be prevented and a decrease in output potential of the unit boosting circuit can be prevented. Detailed Description: CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. application Ser. No. 14/088,496, filed Nov. 25, 2013, now allowed, which is a continuation of U.S. application Ser. No. 13/031,715, filed Feb. 22, 2011, now U.S. Pat. No. 8,593,840, which claims the benefit of a foreign priority application filed in Japan as Serial No. 2010-045752 on Mar. 2, 2010, all of which are incorporated by reference. TECHNICAL FIELD The disclosed invention relates to a boosting circuit and an RFID tag including the boosting circuit. BACKGROUND ART In recent years, semiconductor devices which transmit and receive data wirelessly have been actively developed. The semiconductor device which transmits and receives data wirelessly is called a radio frequency identification (RFID) tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, a wireless chip, a transponder, and the like, and those put in practical use generally include a silicon substrate. The semiconductor devices which transmit and receive data wirelessly (hereinafter referred to as RFID tags) generally have a structure in which inside circuits are made to operate by power obtained wirelessly. In the structure, each circuit is made to operate by using power from an antenna through a power supply circuit, a constant voltage circuit, or the like. As an RFID tag becomes to have a higher function, it is required to mount a circuit that needs high voltage for operation. For example, in the case where a memory element is mounted on an RFID tag, it is necessary to increase voltage supplied from the power supply circuit or the constant voltage circuit. In order to increase the voltage of power, a structure in which an RFID tag is provided with a boosting circuit is considered (see Patent Document 1). REFERENCE [Patent Document 1] Japanese Published Patent Application No. 2006-109429 DISCLOSURE OF INVENTION A conventionally used boosting circuit (a charge pump circuit) has a structure where a plurality of unit boosting circuits is connected in series. The unit boosting circuit includes a transistor in which a gate electrode and a source electrode are connected to each other and a capacitor in which one electrode is connected to a drain electrode of the transistor and a clock signal or an inverted clock signal is applied to the other electrode. The boosting circuit has the following mechanism: when an input signal is input to a source electrode of a transistor in a first stage unit boosting circuit, in each unit boosting circuit, the input signal is boosted up by capacitive coupling of a capacitor to which a clock signal or an inverted clock signal is input, so that a signal obtained by boosting up the input signal is output from a drain electrode of a transistor in a last stage unit boosting circuit. However, there is a problem in that when a transistor in which a gate electrode and a source electrode are connected to each other is used in a unit boosting circuit, the potential boosted in each unit boosting circuit is reduced by threshold potential of a transistor in the next stage unit boosting circuit. In other words, in the case where transistors in unit boosting circuits each have substantially the same threshold potential, the potential of a signal output from the boosting circuit is reduced by the product of threshold potential of a transistor in a unit boosting circuit multiplied by the number of unit boosting circuits; thus, the boosting efficiency of the boosting circuit is prevented. When the potential applied to one electrode of a capacitor is boosted by capacitive coupling of the capacitor in a unit boosting circuit, a transistor is brought out of conduction. At this time, when the off-state current of the transistor is not sufficiently small, leakage current is generated between a source and a drain of the transistor, which leads to another problem in that boosting due to capacitive coupling is not performed sufficiently. In view of the foregoing problems, an object of one embodiment of the disclosed invention is to provide a boosting circuit whose boosting efficiency is enhanced. Another object is to provide an RFID tag including a boosting circuit whose boosting efficiency is enhanced. According to one embodiment of the disclosed invention, a node corresponding to an output terminal of a unit boosting circuit is boosted by bootstrap operation, so that a decrease in output potential of the unit boosting circuit can be prevented. According to another embodiment of the disclosed invention, a gate electrode of a transistor connected to a node corresponding to an output terminal of a unit boosting circuit is boosted by bootstrap operation, so that a decrease in potential which corresponds to substantially the same as the threshold potential of the transistor can be prevented and a decrease in output potential of the unit boosting circuit can be prevented. According to another embodiment of the disclosed invention, a material which can make an off-state current sufficiently small, for example, an oxide semiconductor is used for a transistor included in a boosting circuit, so that leakage current in a non-conduction state of the transistor can be reduced. Specifically, any of the following structures can be employed, for example. One embodiment of the disclosed invention is a boosting circuit including a first transistor including a first gate electrode; a first source electrode; and a first drain electrode, a second transistor including a second gate electrode; a second source electrode; and a second drain electrode, a first capacitor, and a second capacitor, in which the first gate electrode, one of the first source electrode and the first drain electrode, and one of the second source electrode and the second drain electrode are electrically connected to one another, in which the other of the first source electrode and the first drain electrode, the second gate electrode, one electrode of the first capacitor, and one electrode of the second capacitor are electrically connected to one another, in which the other of the second source electrode and the second drain electrode and the other electrode of the first capacitor are electrically connected to each other, in which an input signal is input to the one of the first source electrode and the first drain electrode, in which a clock signal is input to the other electrode of the second capacitor, and in which a signal obtained by boosting the input signal is output from the other of the first source electrode and the first drain electrode. Another embodiment of the disclosed invention is a boosting circuit including n stages of unit boosting circuits (n is a natural number and an even number) electrically connected to each other in series. Each unit boosting circuit includes a first transistor including a first gate electrode; a first source electrode; and a first drain electrode, a second transistor including a second gate electrode; a second source electrode; and a second drain electrode, a first capacitor, and a second capacitor, in which the first gate electrode, one of the first source electrode and the first drain electrode, and one of the second source electrode and the second drain electrode are electrically connected to one another, in which the other of the first source electrode and the first drain electrode, the second gate electrode, one electrode of the first capacitor, and one electrode of the second capacitor are electrically connected to one another, and in which the other of the second source electrode and the second drain electrode and the other electrode of the first capacitor are electrically connected to each other. An input signal is input to the one of the first source electrode and the first drain electrode in a first stage unit boosting circuit, a clock signal is input to the other electrode of the second capacitor in a (2M−1)th stage unit boosting circuit (M is a natural number which satisfies 1≦M≦n/2), an inverted clock signal is input to the other electrode of the second capacitor in a 2M-th stage unit boosting circuit, and a signal obtained by boosting the input signal is output from the other of the first source electrode and the first drain electrode in an n-th stage unit boosting circuit. Another embodiment of the disclosed invention is a boosting circuit including n stages of unit boosting circuits (n is a natural number) electrically connected to each other in series. Each unit boosting circuit includes a first transistor including a first gate electrode; a first source electrode; and a first drain electrode, a second transistor including a second gate electrode; a second source electrode; and a second drain electrode, a first capacitor, and a second capacitor, in which the first gate electrode, one of the first source electrode and the first drain electrode, and one of the second source electrode and the second drain electrode are electrically connected to one another, in which the other of the first source electrode and the first drain electrode, the second gate electrode, one electrode of the first capacitor, and one electrode of the second capacitor are electrically connected to one another, and in which the other of the second source electrode and the second drain electrode and the other electrode of the first capacitor are electrically connected to each other. An input signal is input to the one of the first source electrode and the first drain electrode in a first stage unit boosting circuit, a signal obtained by boosting the input signal is output from the other of the first source electrode and the first drain electrode in an n-th stage unit boosting circuit, and an inverted clock signal is input to the other electrode of the second capacitor in the n-th stage unit boosting circuit. For all values of M (M is a natural number which satisfies 1≦M (n<1)), when n is an even number and M is an odd number, or n is an odd number and M is an even number, a clock signal is input to the other electrode of the second capacitor in a M-th stage unit boosting circuit, and when n is an even number and M is an even number, or n is an odd number and M is an odd number, an inverted clock signal is input to the other electrode of the second capacitor in the M-th stage unit boosting circuit. The unit boosting circuit further includes a third transistor including a third gate electrode; a third source electrode; and a third drain electrode, in which one of the third source electrode and the third drain electrode, the other of the second source electrode and the second drain electrode, and the other electrode of the first capacitor are electrically connected to one another, in which the other of the third source electrode and the third drain electrode and a low-potential power supply are electrically connected to each other, in which a reset signal is input to the third gate electrode, and in which a potential of the low-potential power supply is lower than a potential of the input signal. Another embodiment of the disclosed invention is a boosting circuit including n stages of unit boosting circuits (n is a natural number and an even number) electrically connected to each other in series. Each unit boosting circuit includes a first transistor including a first gate electrode; a first source electrode; and a first drain electrode, a second transistor including a second gate electrode; a second source electrode; and a second drain electrode, a third transistor including a third gate electrode; a third source electrode; and a third drain electrode, a fourth transistor including a fourth gate electrode; a fourth source electrode; and a fourth drain electrode, a first capacitor, a second capacitor, and an analog switch including first to fourth terminals, in which the first gate electrode, one of the first source electrode and the first drain electrode, one of the second source electrode and the second drain electrode, and one of the fourth source electrode and the fourth drain electrode are electrically connected to one another, in which the other of the first source electrode and the first drain electrode, the second gate electrode, one electrode of the first capacitor, and the fourth gate electrode are electrically connected to one another, in which the other of the second source electrode and the second drain electrode, the other electrode of the first capacitor, and one of the third source electrode and the third drain electrode are electrically connected to one another, in which the other of the third source electrode and the third drain electrode and a low-potential power supply are electrically connected to each other, and in which the other of the fourth source electrode and the fourth drain electrode, one electrode of the second capacitor, and the first terminal of the analog switch are electrically connected to one another. An input signal is input to the one of the first source electrode and the first drain electrode in a first stage unit boosting circuit, a clock signal is input to the third gate electrode and the other electrode of the second capacitor in a (2M−1)th stage unit boosting circuit (M is a natural number which satisfies 1≦M≦n/2), an inverted clock signal is input to the third gate electrode and the other electrode of the second capacitor in the 2M-th stage unit boosting circuit, a clock signal is input to the second terminal of the analog switch and an inverted clock signal is input to the third terminal of the analog switch in a (2M−1)th stage unit boosting circuit, an inverted clock signal is input to the second terminal of the analog switch and a clock signal is input to the third terminal of the analog switch in the 2M-th stage unit boosting circuit, a signal obtained by boosting the input signal is output from the other of the fourth source electrode and the fourth drain electrode in an n-th stage unit boosting circuit, a potential of the low-potential power supply is lower than a potential of the input signal, and the fourth terminal of the analog switch in a (K−1)th stage unit boosting circuit (K is a natural number which satisfies 2≦K≦n) is electrically connected to one of the first source electrode and the first drain electrode in a K-th stage unit boosting circuit. Another embodiment of the disclosed invention is a boosting circuit including n stages of unit boosting circuits (n is a natural number) electrically connected to each other in series. Each unit boosting circuit includes a first transistor including a first gate electrode; a first source electrode; and a first drain electrode, a second transistor including a second gate electrode; a second source electrode; and a second drain electrode, a third transistor including a third gate electrode; a third source electrode; and a third drain electrode, a fourth transistor including a fourth gate electrode; a fourth source electrode; and a fourth drain electrode, a first capacitor, a second capacitor, and an analog switch including first to fourth terminals, in which the first gate electrode, one of the first source electrode and the first drain electrode, one of the second source electrode and the second drain electrode, and one of the fourth source electrode and the fourth drain electrode are electrically connected to one another, in which the other of the first source electrode and the first drain electrode, the second gate electrode, one electrode of the first capacitor, and the fourth gate electrode are electrically connected to one another, in which the other of the second source electrode and the second drain electrode, the other electrode of the first capacitor, and one of the third source electrode and the third drain electrode are electrically connected to one another, in which the other of the third source electrode and the third drain electrode and a low-potential power supply are electrically connected to each other, and in which the other of the fourth source electrode and the fourth drain electrode, one electrode of the second capacitor, and the first terminal of the analog switch are electrically connected to one another. An input signal is input to the one of the first source electrode and the first drain electrode in a first stage unit boosting circuit, a signal obtained by boosting the input signal is output from the other of the fourth source electrode and the fourth drain electrode in an n-th stage unit boosting circuit, a potential of the low-potential power supply is lower than a potential of the input signal, and the fourth terminal of the analog switch in a (K−1)th stage unit boosting circuit (K is a natural number which satisfies 2≦K≦n) is electrically connected to one of the first source electrode and the first drain electrode in a K-th stage unit boosting circuit. For all values of M (M is a natural number which satisfies 1≦M≦(n−1)), when n is an even number and M is an odd number, or n is an odd number and M is an even number, in a M-th stage, a clock signal is input to the third gate electrode and the other electrode of the second capacitor; a clock signal is input to the second terminal of the analog switch; and an inverted clock signal is input to the third terminal of the analog switch, and when n is an even number and M is an even number, or n is an odd number and M is an odd number, in the M-th stage, an inverted clock signal is input to the third gate electrode and the other electrode of the second capacitor; an inverted clock signal is input to the second terminal of the analog switch; and a clock signal is input to the third terminal of the analog switch. Here, the following is preferable: the analog switch includes a fifth transistor that is an n-channel transistor including a fifth gate electrode; a fifth source electrode; and a fifth drain electrode, and a sixth transistor that is a p-channel transistor including a sixth gate electrode; a sixth source electrode; and a sixth drain electrode, in which one of the fifth source electrode and the fifth drain electrode and one of the sixth source electrode and the sixth drain electrode are electrically connected to each other so as to function as the first terminal of the analog switch, in which the fifth gate electrode or the sixth gate electrode functions as the second terminal of the analog switch or the third terminal of the analog switch, and in which the other of the fifth source electrode and the fifth drain electrode and the other of the sixth source electrode and the sixth drain electrode are electrically connected to each other so as to function as the fourth terminal of the analog switch. The fifth transistor preferably includes an oxide semiconductor material. It is preferable that the first transistor, the second transistor, and the fourth transistor each include an oxide semiconductor material. Another embodiment of the disclosed invention is an RFID tag including the above boosting circuit. Note that in this specification and the like, the term “over” or “below” does not necessarily mean that a component is placed “directly on” or “directly under” another component. For example, the expression “a gate electrode over a gate insulating layer” can mean the case where there is an additional component between the gate insulating layer and the gate electrode. In addition, in this specification and the like, the term “electrode” or “wiring” does not limit a function of a component. For example, an “electrode” is sometimes used as part of a “wiring”, and vice versa. Further, the term “electrode” or “wiring” can include the case where a plurality of “electrodes” or “wirings” is formed in an integrated manner. Functions of a “source” and a “drain” may sometimes be switched when transistors of different polarities are employed or when the direction of current flowing is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be used to denote the drain and the source, respectively, in this specification. Note that in this specification and the like, the term “electrically connected” includes the case where components are connected through an object having any electric function. There is no particular limitation on an object having any electric function as long as electric signals can be transmitted and received between components that are connected through the object. Examples of an “object having any electric function” are a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element with a variety of functions as well as an electrode and a wiring. According to one embodiment of the disclosed invention, a node corresponding to an output terminal of a unit boosting circuit is boosted by bootstrap operation, so that a decrease in output potential of the unit boosting circuit can be prevented. Therefore, a boosting circuit whose boosting efficiency is enhanced can be provided. According to another embodiment of the disclosed invention, a gate electrode of a transistor connected to a node corresponding to an output terminal of a unit boosting circuit is boosted by bootstrap operation, so that a decrease in potential which corresponds to substantially the same as the threshold potential of the transistor can be prevented and a decrease in output potential of the unit boosting circuit can be prevented. Therefore, a boosting circuit whose boosting efficiency is enhanced can be provided. According to another embodiment of the disclosed invention, a material which can make an off-state current sufficiently small, for example, an oxide semiconductor is used for a transistor included in a boosting circuit, so that a decrease in output potential caused by leakage current in a non-conduction state of the transistor can be suppressed. Therefore, a boosting circuit whose boosting efficiency is enhanced can be provided. Another embodiment of the disclosed invention can provide an RFID tag including a boosting circuit whose boosting efficiency is enhanced. BRIEF DESCRIPTION OF DRAWINGS In the accompanying drawings: FIG. 1 is a circuit diagram of a boosting circuit according to one embodiment of the disclosed invention; FIG. 2 is a circuit diagram of a boosting circuit according to one embodiment of the disclosed invention; FIG. 3 is a timing chart showing operation of a boosting circuit according to one embodiment of the disclosed invention; FIG. 4 is a circuit diagram of a boosting circuit according to one embodiment of the disclosed invention; FIG. 5 is a timing chart showing operation of a boosting circuit according to one embodiment of the disclosed invention; FIG. 6 is a block diagram of an RFID tag according to one embodiment of the disclosed invention; FIGS. 7A to 7D are each a cross-sectional view of a transistor according to one embodiment of the disclosed invention; FIGS. 8A to 8E are cross-sectional views illustrating a manufacturing process of a transistor according to one embodiment of the disclosed invention; FIG. 9 is a cross-sectional view of a semiconductor device according to one embodiment of the disclosed invention; FIGS. 10A to 10D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the disclosed invention; FIGS. 11A to 11C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the disclosed invention; FIGS. 12A to 12C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the disclosed invention; and FIGS. 13A and 13B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the disclosed invention. BEST MODE FOR CARRYING OUT THE INVENTION Examples of embodiments of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to the following description and it will be readily appreciated by those skilled in the art that modes and details can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description in the following embodiments. Note that the position, size, range, and the like of each component illustrated in the drawings and the like are not accurately represented in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, and the like disclosed in the drawings and the like. In this specification and the like, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not limit the number of components numerically. Embodiment 1 In this embodiment, a boosting circuit according to one embodiment of the disclosed invention will be described with reference to FIG. 1, FIG. 2, and FIG. 3. Note that in a circuit diagram, “OS” may be written beside a transistor in order to indicate that the transistor includes an oxide semiconductor. (Circuit Configuration) An example of a circuit configuration of a boosting circuit according to one embodiment of the disclosed invention will be described with reference to a circuit diagram of FIG. 1. A boosting circuit illustrated in FIG. 1 is formed with n stages of unit boosting circuits 111_1 to 111—n (n is a natural number) which are electrically connected to each other in series. Here, a unit boosting circuit forms one stage of the boosting circuit. Each of the unit boosting circuits 111_1 to 111—n includes a transistor 101, a capacitor 102, a transistor 103, and a capacitor 106. Note that in the case where the electrostatic capacitance of a gate insulating layer of the transistor 103 is large, the capacitor 102 may be omitted because the transistor 103 can also function as the capacitor 102. Each of the unit boosting circuits 111_1 to 111—n has the following structure: a gate electrode of the transistor 101, one of a source electrode and a drain electrode of the transistor 101, and one of a source electrode and a drain electrode of the transistor 103 are electrically connected to one another; the other of the source electrode and the drain electrode of the transistor 101, a gate electrode of the transistor 103, one electrode of the capacitor 102, and one electrode of the capacitor 106 are electrically connected to one another; and the other of the source electrode and the drain electrode of the transistor 103 and the other electrode of the capacitor 102 are electrically connected to each other. In an m-th stage unit boosting circuit (m is a natural number which satisfies 1≦M≦n), a portion where the other of the source electrode and the drain electrode of the transistor 101, the gate electrode of the transistor 103, the one electrode of the capacitor 102, and the one electrode of the capacitor 106 are connected is called a node N1—m. Further, in the m-th stage unit boosting circuit, a portion where the other of the source electrode and the drain electrode of the transistor 103 and the other electrode of the capacitor 102 are connected is called a node N2—m. The one of the source electrode and the drain electrode of the transistor 101 in a K-th stage unit boosting circuit (K is a natural number which satisfies 2≦K≦n) and the other of the source electrode and the drain electrode of the transistor 101 in a (K−1)th stage unit boosting circuit are electrically connected to each other. In other words, the one of the source electrode and the drain electrode of the transistor 101 in the K-th stage unit boosting circuit is connected to a node N1_(K−1) in the (K−1)th stage unit boosting circuit. In a (2M−1)th stage unit boosting circuit (M is a natural number which satisfies 1≦M≦n/2, hare, n is a natural number and an even number), the other electrode of the capacitor 106 is electrically connected to a clock signal line 121. In a 2M-th stage unit boosting circuit (M is a natural which satisfies 1≦M≦n/2), the other electrode of the capacitor 106 is electrically connected to a clock signal line 122. Here, a clock signal CLK is input to the clock signal line 121 and a clock signal CLKB is input to the clock signal line 122. Needless to say, the clock signal CLKB can be input to the clock signal line 121 and the clock signal CLK can be input to the clock signal line 122. The clock signal CLK and the clock signal CLKB have opposite phases. For example, when the clock signal CLK is a high-level signal, the clock signal CLKB is a low-level signal. As the clock signal CLKB, for example, an inverted signal of the clock signal CLK can be used. The clock signal CLKB can be generated by inversion of the potential state of the clock signal CLK with a NOT circuit such as an inverter, for example. In the clock signal CLK and the clock signal CLKB, levels of a potential such as high level and low level can be determined as appropriate. Alternatively, the clock signal CLK can be generated with use of a buffer circuit and an oscillator circuit such as a ring oscillator, for example. The clock signal is not limited to the clock signal CLK and the clock signal CLKB, and three or more kinds of clock signals can be used. Note that FIG. 1 illustrates the boosting circuit in the case where the number of stages n is an even number. In the case where the number of stages n of the boosting circuit is an odd number, the connection between the clock signal line 121 and a (n−1)th stage unit boosting circuit and the connection between the clock signal line 122 and the n-th stage unit boosting circuit illustrated in FIG. 1 are exchanged for a connection between the clock signal line 121 and the n-th stage unit boosting circuit and a connection between the clock signal line 122 and the (n−1)th stage unit boosting circuit. In a first stage unit boosting circuit (i.e., a unit boosting circuit 111_1), the one of the source electrode and the drain electrode of the transistor 101 functions as an input terminal IN to which a signal IN is input. The potential value of the signal IN can be set as appropriate. In the n-th stage unit boosting circuit (i.e., a unit boosting circuit 111—n), the other of the source electrode and the drain electrode of the transistor 101 functions as an output terminal OUT from which a signal OUT that is obtained by boosting the signal IN is output. The other of the source electrode and the drain electrode of the transistor 101 in the unit boosting circuit 111—n is electrically connected to one electrode of a capacitor 120. A potential Vc1 is applied to the other electrode of the capacitor 120. The potential Vc1 may be any potential. For example, the same potential as a high-level potential VH or a low-level potential VL may be employed. The capacitance of the capacitor 120 is preferably larger than that of the capacitor 102 in the unit boosting circuit. Thus, the potential state of an output signal that is output from the output terminal OUT (i.e., a signal OUT that is an output signal of the boosting circuit) can be stabilized. Note that the circuit configuration of the boosting circuit according to one embodiment of the disclosed invention is not limited to the structure illustrated in the circuit diagram of FIG. 1. For example, the circuit configuration of the boosting circuit illustrated in FIG. 2 may be employed. One of the differences between the boosting circuit illustrated in FIG. 2 and the boosting circuit illustrated in FIG. 1 is that whether unit boosting circuits 111_1 to 111—n each have a transistor 107 or not. One of a source electrode and a drain electrode of the transistor 107 is electrically connected to the other of the source electrode and the drain electrode of the transistor 103 and the other electrode of the capacitor 102. The other of the source electrode and the drain electrode of the transistor 107 is electrically connected to a low-potential power supply VSS. A gate electrode of the transistor 107 is electrically connected to a reset signal line 123. A reset signal RES is input to the reset signal line 123. The potential value of the reset signal RES can be set as appropriate as long as the transistor 107 is brought into conduction by input of the reset signal RES. The potential of the low-potential power supply VSS is lower than the potential of the signal IN. As described above, each unit boosting circuit in the boosting circuit according to one embodiment of the disclosed invention includes the transistor 101 and the capacitor 102, which are included in each unit boosting circuit in the conventional boosting circuit, and further includes the transistor 103 and the capacitor 106. In addition to the conventional boosting of the node N1—m by inversion of a clock signal, such a bootstrap operation of the transistor 103 and the capacitor 102 can boost the node N1—m; thus, the boosting efficiency of the boosting circuit can be enhanced. It is preferable that the transistor 101 and the transistor 103 be formed using a material which can make an off-state current sufficiently small, for example, an oxide semiconductor. Accordingly, a decrease in the potential of the node N1—m caused by leakage current in a non-conduction state of the transistor 101 and the transistor 103 can be suppressed. Therefore, in the above bootstrap operation, the potential of the node N1—m can be kept for a long time, so that the boosting efficiency of the boosting circuit can be enhanced. (Circuit Operation) Next, an example of operation of the boosting circuits illustrated in FIG. 1 and FIG. 2 will be described with reference to a timing chart of FIG. 3. The operation of the boosting circuits illustrated in FIG. 1 and FIG. 2 can be explained by dividing the operation into operations corresponding to a plurality of periods in accordance with the clock signal CLK and the clock signal CLKB. In this embodiment, as an example of operation of the boosting circuit, changes in potentials of the node N1_1, a node N2_1, a node N1_2, and a node N2_2 in a first period to a third period which are set depending on change in the clock signal CLK will be described with reference to the timing chart of FIG. 3. Note that an example of operation of the boosting circuits illustrated in FIG. 1 and FIG. 2 in the following conditions will be described in this embodiment: a high-level signal (potential VH) is input as the signal IN; the clock signal CLK serves as a clock signal that periodically oscillates between a high level (potential VH) and a low level (potential VL≈0V); the clock signal CLKB serves as an inverted clock signal of the clock signal CLK; the potential of low-potential power supply VSS is potential VL; the transistor 101 and the transistor 103 in each unit boosting circuit are n-channel transistors; the threshold potentials (potentials Vth) of the transistor 101 and the transistor 103 in each unit boosting circuit are the same; and the initial potentials of the node N1—m and the node N2—m each are VL. The timing chart of FIG. 3 shows an example of ideal operation of the boosting circuits illustrated in FIG. 1 and FIG. 2, and the boosting circuits illustrated in FIG. 1 and FIG. 2 do not necessarily operate as in the timing chart of FIG. 3. For example, a load, capacity, and noise in the circuit might cause a difference from operation illustrated in FIG. 3 in some cases. Note that in the case where the boosting circuit illustrated in FIG. 2 is employed, the reset signal RES is input before the signal IN is input so that the transistor 107 in a unit boosting circuit 111—m is brought into conduction; thus the potential of the node N2—m can be decreased to the same potential (potential VL) as that of the low-potential power supply VSS. Accordingly, when bootstrap operation is performed with use of the transistor 103 and the capacitor 102, the potential of the node N1—m can be certainly increased. First, the signal IN (potential VH) is input to the input terminal IN of the unit boosting circuit 111_1, and the first period starts. In the first period, the clock signal CLK is set to low level and the clock signal CLKB is set to high level (see FIG. 3). When the signal IN is input to the unit boosting circuit 111_1, the potential VH is applied to the gate electrode of the transistor 101, so that the transistor 101 is brought into conduction and the potential of the node N1_1 is increased. In the transistor 103 in the unit boosting circuit 111_1, when the difference between the potential of the node N1_1 (i.e., the potential of the gate electrode of the transistor 103) and the potential of the node N2_1 is larger than the threshold potential Vth of the transistor 103, the transistor 103 is brought into conduction and the potential of the node N2_1 is increased. Here, as the potential of the node N2_1 (i.e., the potential of the other electrode of the capacitor 102) is increased, the potential of the one electrode of the capacitor 102 (i.e., the potential of the node N1_1) is increased by capacitive coupling. Accordingly, the potential of the gate electrode of the transistor 103 is sufficiently increased and thus the potential of the node N2_1 becomes VH. The potential of the node N1_1 is increased from the potential Vth as the reference by the same magnitude as that of the node N2_1, so that the potential of the node N1_1 becomes (VH+Vth). Such operation in which the potentials of the node N1_1 and the node N2_1 are increased by capacitive coupling of the transistor 103 and the capacitor 102 is called bootstrap operation. Note that when the potential of the node N2_1 becomes VH, the transistor 103 is brought out of conduction and the node N2_1 is brought into a floating state. Further, when the potential of the node N1_1 becomes (VH Vth), the transistor 101 is brought out of conduction. On the other hand, in the unit boosting circuit 111_2 in the first period, the potential of the other electrode of the capacitor 106 which is electrically connected to the clock signal line 122 changes from VL to VH, and the potential of the node N1_2 is also increased by approximately the potential difference VH by capacitive coupling of the capacitor 106. In such a manner, the potential of the node N1_2 is increased to approximately VH. Accordingly, when the difference between the potential of the node N1_2 (i.e., the potential of the gate electrode of the transistor 103) and the potential of the node N2_2 is larger than the threshold potential Vth of the transistor 103; thus, the transistor 103 is brought into conduction. Accordingly, as the potential of the node N1_1 is increased, the potential of the node N2_2 is increased. As the potential of the node N2_2 (i.e., the potential of the other electrode of the capacitor 102) is increased, the potential of the one electrode of the capacitor 102 (i.e., the potential of the node N1_2) is increased by capacitive coupling. Thus, the potential of the gate electrode of the transistor 103 is sufficiently increased and the node N2_2 has the same potential as that of the node N1_1, so that the potential of the node N2_2 becomes (VH+Vth). The potential of the node N1_2 is increased from the potential VH as the reference by the same magnitude as that of the node N2_2, so that the potential of the node N1_2 becomes (2VH+Vth). Note that when the potential of the node N2_2 becomes (VH+Vth), the transistor 103 is brought out of conduction and the node N2_2 is brought into a floating state. Further, when the potential of the node N1_2 becomes VH, the transistor 101 is brought out of conduction. Note that in the first period, the potential of the node N1_2 is higher than VH, so that the transistor 101 is brought out of conduction. In the unit boosting circuit 111_1, by bootstrap operation of the transistor 103 and the capacitor 102, the potential of the node N1_1 can be increased before boosting of the potential of the node N1_1 by inversion of the clock signal which is performed later. Thus, the boosting efficiency of the boosting circuit can be enhanced. When the transistor 101 and the transistor 103 are formed using a material which can make an off-state current sufficiently small, for example, an oxide semiconductor, a decrease in the potential of the node N1—m caused by leakage current in a non-conduction state of the transistor 101 and the transistor 103 can be suppressed. Therefore, in the above bootstrap operation, the boosting efficiency of the boosting circuit can be further enhanced. Next, the clock signal CLK and the clock signal CLKB are inverted and the second period starts. In other words, in the second period, the clock signal CLK is set to high level and the clock signal CLKB is set to low level (see FIG. 3). In the second period, the potential of the other electrode of the capacitor 106 in the unit boosting circuit 111_1 changes from VL to VH, and the potential of the node N1_1 is increased by approximately the potential difference VH by capacitive coupling of the capacitor 106. In such a manner, the potential of the node N1_1 is increased to approximately (2VH+Vth). Note that although the potential of the node N2_1 is also increased by capacitive coupling of the capacitor 102, this increase brings the transistor 103 into conduction and the potential of the node N2_1 returns to the potential VH soon. When the transistor 101 is formed using a material which can make an off-state current sufficiently small, for example, an oxide semiconductor, a decrease in the potential of the node N1_1 caused by leakage current in a non-conduction state of the transistor 101 can be suppressed. Therefore, the potential of the node N1_1 can be kept for a long time, so that the boosting efficiency of the boosting circuit can be enhanced. In the unit boosting circuit 111_2, the potential of the other electrode of the capacitor 106 changes from VH to VL, and the potential of the node N1_2 is decreased by approximately the potential difference VH by capacitive coupling of a capacitor 106. In such a manner, the potential of the node N1_2 is decreased to approximately (VH+Vth). At this time, the potential of the node N2_2 is also decreased by capacitive coupling of the capacitor 102, so that the potential of the node N2_2 is decreased to approximately Vth. At this time, the transistor 101 and the transistor 103 in the unit boosting circuit 111_2 are brought into conduction, so that the potential (2VH+Vth) of the node N1_1 is supplied to the node N1_2 and the node N2_2 and the potentials of the node N1_2 and the node N2_2 are increased. As the potential of the node N2_2 (i.e., the potential of the other electrode of the capacitor 102) is increased, the potential of the one electrode of the capacitor 102 (i.e., the potential of the node N1_2) is increased by capacitive coupling. Thus, the potential of the gate electrode of the transistor 103 is sufficiently increased, so that the potential of the node N2_2 becomes (2VH+Vth). The potential of the node N1_2 is increased from the potential (VH+Vth) as the reference by the same magnitude as that of the node N2_2, so that the potential of the node N1_2 becomes (3VH+Vth) at a maximum. Note that when the potential of the node N2_2 becomes (2VH+Vth), the transistor 103 is brought out of conduction and the node N2_2 is brought into a floating state. Further, when the potential of the node N1_2 is set to 2VH, the transistor 101 is brought out of conduction. In the unit boosting circuit 111_2, by bootstrap operation of the transistor 103 and the capacitor 102, the potential of the node N1_2 can be increased before boosting of the potential of the node N1_2 by inversion of the clock signal which is performed later. Thus, the boosting efficiency of the boosting circuit can be enhanced. When the transistor 101 and the transistor 103 are formed using a material which can make an off-state current sufficiently small, for example, an oxide semiconductor, a decrease in the potential of the node N1—m caused by leakage current in a non-conduction state of the transistor 101 and the transistor 103 can be suppressed. Therefore, in the above bootstrap operation, the boosting efficiency of the boosting circuit can be further enhanced. Next, the clock signal CLK and the clock signal CLKB are inverted again and the third period starts. In other words, in the third period, the clock signal CLK is set to low level and the clock signal CLKB is set to high level (see FIG. 3). In the third period, the potential of the other electrode of the capacitor 106 in the unit boosting circuit 111_2 changes from VL to VH, and the potential of the node N1_2 is also increased by approximately the potential difference VH by capacitive coupling of the capacitor 106. In such a manner, the potential of the node N1_2 is increased to approximately (4VH+Vth). Note that although the potential of the node N2_2 is also increased by capacitive coupling of the capacitor 102, this increase brings the transistor 103 into conduction and the potential of the node N2_2 returns to the potential (2VH+Vth) soon. Thus, also in the unit boosting circuit 111_3, the potential of the node N1_3 is increased in a manner similar to that of the unit boosting circuits 111_1 and 111_2. The potential of the node N1_3 is further increased by bootstrap operation of the transistor 103 and the capacitor 102. In each of the third and subsequent stage unit boosting circuits, operations which are similar to those of the previous stage unit boosting circuits are sequentially performed in accordance with a periodical change of the clock signal CLK or the clock signal CLKB which periodically oscillates between a high level and a low level, so that the potential of the node N1—m is higher as the number of stages m is larger. The signal OUT that is output from the output terminal OUT is boosted in every unit boosting circuit in which a potential is boosted with the periodically change of the clock signal CLK or the clock signal CLKB between a high level and a low level, so that the potential of the signal OUT is obtained by boosting the signal IN depending on the number of stages. In such a manner, in the boosting circuits illustrated in FIG. 1 and FIG. 2, the potential of the signal IN is boosted and the signal OUT having the boosted potential is output as an output signal. Note that in the third period, although the potential of the node N1_1 in the unit boosting circuit 111_1 is decreased by capacitive coupling of the capacitor 106 and the capacitor 102 in accordance with change in potential of the other electrode of the capacitor 106 from VH to VL, the potential of the node N1_1 is increased to the previous potential when the clock signal CLK is inverted next. After that, the potential of the node N1_1 is increased or decreased in accordance with inversion of the clock signal CLK. This can be applied to the second stage and subsequent stage unit boosting circuits. As described above, when the boosting circuit according to one embodiment of the disclosed invention is employed, in addition to the conventional boosting of the node N1—m by inversion of a clock signal, the node N1—m can be boosted by bootstrap operation of the transistor 103 and the capacitor 102; thus, the boosting efficiency of the boosting circuit can be enhanced. When the transistor 101 and the transistor 103 are formed using a material which can make an off-state current sufficiently small, for example, an oxide semiconductor, a decrease in the potential of the node N1—m caused by leakage current in a non-conduction state of the transistor 101 and
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