Title of Invention: SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF Abstract: A semiconductor memory device includes a first insulating portion. The semiconductor memory device further includes a phase-change material element that contacts the first insulating portion. The semiconductor memory device further includes an electrode that contacts a side surface of the phase-change material element, the side surface of the phase-change material element being not parallel to a top surface of the electrode. The semiconductor memory device further includes a second insulating portion surrounding the phase-change material element. Detailed Description: CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional application of U.S. application Ser. No. 13/675,975 (filed on Nov. 13, 2012), which claims priority to or is related to Chinese Patent Application No. 201110295406.3 (filed on Sep. 27, 2011); the prior applications are incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a manufacturing method thereof. 2. Description of the Related Art A phase-change memory (PCM), such as a phase-change random access memory (PCRAM), can be of high storage density and high endurance, and can be written and/or read with high speed and driven with low drive current. FIG. 1 illustrates a diagram illustrating a memory cell 100 of a PCRAM device having a buried electrode contact (BEC). As shown in FIG. 1, the memory cell 100 has a first insulating layer 107 in which a lower via, a BEC, is formed, wherein the lower via contacts a first electrode 101 and comprises a liner 103 and a metal plug 105. For example, the liner 103 can be formed of titanium nitride (TiN), while the metal plug 105 embedded in the liner 103 can be formed of one or more of copper, aluminium, tungsten, nickel and/or one or more of other metals, an alloy of some of these metals, or a stack of some of these metals. The lower via contacts a phase-change material layer 113 (which may be a phase-change material island or phase-change material island-shaped layer) that is formed in a second insulating layer 109; the lower via serves as an electrode for the phase-change material layer 113. A second electrode 115 is provided on the phase-change material layer 113 and can be a contact or a via, for example. A third insulating layer 111 is formed to cover the second electrode 115. A small electrode contact area in a PCRAM device is critical for reducing the drive current and device size. As indicated by the double-arrow line in FIG. 1, the BEC (i.e., the lower via) has a critical dimension (width or diameter) of about 70 nm. Given existing standard contact processes, it is difficult to directly form a BEC with a 70 nm critical dimension using a patterning process at the 180 nm or 130 nm process node. On the other hand, an advanced process capable of patterning 70 nm critical dimensions may substantially increase the process cost and/or the equipment cost. SUMMARY One or more embodiments of the invention may be related to a semiconductor memory device. The semiconductor memory device may include a first insulating portion. The semiconductor memory device may further include a phase-change material element that contacts the first insulating portion. For example, a bottom surface or a top surface of the phase-change material element may contact the first insulating portion. The semiconductor memory device may further include a first electrode that contacts a first side surface of the phase-change material element, the first side surface of the phase-change material element being not parallel to a top surface of the first electrode. The semiconductor memory device may further include a second insulating portion surrounding the phase-change material element. In one or more embodiments, the phase-change material element extends into the first insulating portion. In one or more embodiments, the first electrode is narrower than the phase-change material element in a direction parallel to the first side surface of the phase-change material element. In one or more embodiments, a thickness of the first electrode is smaller than a width of the first electrode. In one or more embodiments, the semiconductor memory device may include a first via comprising a liner and a metal plug disposed between two portions of the liner. The first electrode and the liner are formed from a continuous layer of a same material. In one or more embodiments, the semiconductor memory device may include a second electrode contacting a second side surface of the phase-change material element, the second side surface of the phase-change material element being not parallel to a top surface of the second electrode. The second side surface of the phase-change material element may be substantially parallel to and/or opposite the first side surface of the phase-change material element. In one or more embodiments, the first electrode, the second electrodes, and a liner of a via are formed from a continuous layer of a same material. In one or more embodiments, the semiconductor memory device may include a second electrode contacting the top surface of the phase-change material element. In one or more embodiments, part of the second insulating portion is disposed between the first electrode and the first insulating portion. One or more embodiments of the invention may be related to a method for manufacturing a semiconductor memory device. The method may include the following steps: providing a first insulating portion; forming an electrode layer that overlaps the first insulating portion; patterning the electrode layer to reduce a width of the electrode layer; forming a second insulating portion; forming an opening that penetrates through the second insulating portion and the electrode layer to form at least a first electrode; and forming a phase-change material element in the opening, wherein the first electrode contacts a first side surface of the phase-change material element, the first side surface of the phase-change material being not parallel to a top surface of the first electrode. In one or more embodiments, the phase-change material element extends into the first insulating portion. In one or more embodiments, the first electrode is formed narrower than the phase-change material element in a direction parallel to the first side surface of the phase-change material element. In one or more embodiments, a thickness of the first electrode is smaller than a width of the first electrode. In one or more embodiments, the method may include the following steps: forming a conductive layer on a substrate; forming the first insulating portion on the conductive layer; and forming a through hole in the first insulating portion to penetrate through the first insulating portion, wherein a first portion of the electrode layer covers a portion of the conductive layer exposed by the through hole and covers a sidewall of the through hole. In one or more embodiments, the method may include the following steps: before patterning the electrode layer, forming a second conductive layer that overlaps the electrode layer and extends into the through hole; and etching-back the second conductive layer to expose at least a portion of the electrode layer and to forma conductive plug of a via in the through hole, wherein the first portion of the electrode layer is used as a liner of the via. In one or more embodiments, method may include the following steps: forming a conductive layer on a substrate; forming the first insulating portion on the conductive layer; forming a through hole extending to the conductive layer in the first insulating portion; depositing a liner material to cover at least a portion of the first insulating portion, a portion of the conductive layer exposed by the through hole, and a sidewall of the through hole; forming a metal material layer on the liner material; and performing chemical mechanical polishing until a first portion of the metal material layer and a first portion of the liner material, which are disposed on a top surface of the first insulating layer, are removed, resulting in a second portion of the metal material layer and a second portion of the liner material remaining in the through hole, wherein the electrode layer contacts at least one of the second portion of the metal material layer and the second portion of the liner material. In one or more embodiments, the method may include using the electrode layer to forma second electrode when forming the opening, wherein the second electrode contacts a second side surface of the phase-change material element. In one or more embodiments, the method may include the following steps: forming a third insulating layer to cover the phase-change material element and the second insulating portion; and forming a via penetrating through the third insulating layer and the second insulating layer and extending to the second electrode. In one or more embodiments, the method may include the following step: forming a second electrode that contacts a top surface of the phase-change material layer. In one or more embodiments, the step of forming the phase-change material element may include the following steps: forming a phase-change material layer that overlaps the second insulating portion and fills the opening; performing chemical mechanical polishing on the phase-change material layer to form the phase-change material element such that a top surface of the phase-change material element is substantially flush with a top surface of the second insulating layer. One or more embodiments of the invention may be related to a semiconductor memory device that may include the following elements: a first phase-change material layer embedded in an insulating material; and a first electrode that laterally contacts the first phase-change material layer. In one or more embodiments, at a contact surface of the first electrode with the first phase-change material layer, a width, b, of the first electrode is smaller than a size, c, of the first phase-change material layer in a direction along the width. In one or more embodiments, at a contact surface of the first electrode with the first phase-change material layer, a thickness, a, of the first electrode is smaller than the width, b, of the first electrode. In one or more embodiments, the semiconductor memory device may include the following elements: a first via electrically connected to the first electrode, wherein the first via comprises a liner and a metal plug. In one or more embodiments, the first electrode together with the liner of the first via electrically connected to the first electrode are formed from a continuous layer of a same material. In one or more embodiments, the first electrode is formed of titanium nitride, tantalum nitride, or titanium. In one or more embodiments, the first electrode is a flat bar-shape conductor. In one or more embodiments, the semiconductor memory device may include a second electrode in contact with the first phase-change material layer. In one or more embodiments, the semiconductor memory device may include a second via electrically connected to the second electrode. In one or more embodiments, the second electrode laterally contacts the first phase-change material layer. In one or more embodiments, the second electrode is formed of titanium nitride, tantalum nitride, or titanium. In one or more embodiments, at contact surfaces of the second electrodes with the first phase-change material layer, a width, b, of the second electrode is smaller than a size, c, of the first phase-change material layer in a direction along the width of the first electrode. In one or more embodiments, at a contact surface of the second electrode with the first phase-change material layer, a thickness, a, of the second electrode is smaller than the width, b, of the second electrode. In one or more embodiments, the second electrode is a flat bar-shaped conductor. In one or more embodiments, the first and second electrodes together with the liner of the first via electrically connected to the first electrode are formed from a continuous layer of the same material. In one or more embodiments, the second electrode contacts and covers the upper surface of the first phase-change material layer. In one or more embodiments, the semiconductor memory device may include a second via electrically connected to the second electrode, and the second via is located on the second electrode. In one or more embodiments, the second electrode extends beyond an edge of an upper surface of the first phase-change material layer, and the second via is located on a portion of the second electrode that extends beyond the edge of the upper surface of the first phase-change material layer. In one or more embodiments, the second via is substantially aligned with the first via electrically connected to the first electrode in a vertical direction. In one or more embodiments, the semiconductor memory device may include the following elements: a second phase-change material layer embedded in the insulating material; and a third electrode and a fourth electrode that are in contact with the second phase-change material layer; wherein the third electrode laterally contacts a side surface of the second phase-change material layer; and wherein the third electrode is electrically connected to the first electrode and the fourth electrode is not connected to the second electrode. One or more embodiments of the invention may be related to a method for manufacturing a semiconductor memory device. The method may include the following steps: providing a substrate with a first insulating layer formed thereon; forming an electrode layer over the first insulating layer; patterning the electrode layer; forming a second insulating layer to at least cover the patterned electrode layer; forming an opening that penetrates through the second insulating layer and the electrode layer; and forming a phase-change material layer in the opening, wherein the patterned electrode layer laterally contacts the phase-change material layer, thereby at least forming a first electrode that laterally contacts the phase-change material layer. In one or more embodiments, at a contact surface of the first electrode with the phase-change material layer, a width, b, of the first electrode is smaller than a size, c, of the phase-change material layer in a direction along the width of the first electrode. In one or more embodiments, at a contact surface of the first electrode with the first phase-change material layer, a thickness, a, of the first electrode is smaller than the width, b, of the first electrode. In one or more embodiments, the substrate is also formed thereon with a conductive layer underlying the first insulating layer, wherein a through hole penetrating through the first insulating layer is formed in the first insulating layer, and the step of forming an electrode layer over the first insulating layer causes the electrode layer to cover the bottom surface and sidewall of the through hole. In an embodiment, the method further comprising, before patterning the electrode layer: forming a second conductive layer over the electrode layer; and, performing etch-back of the second conductive layer such that the electrode layer over the first insulating layer is exposed while the second conductive layer material in the through hole is remained, thereby forming a via extending to the conductive layer. In one or more embodiments, the electrode layer that covers the bottom surface and sidewall of the through hole is used as a liner of the first via. In one or more embodiments, the substrate is formed thereon with a conductive layer underlying the first insulating layer, a through hole penetrating through the first insulating layer to the conductive layer is formed in the first insulating layer, the via comprising a liner and a metal plug. In one or more embodiments, the step of providing a substrate comprises: forming a through hole extending to the conductive layer in the first insulating layer; depositing a liner material to cover the first insulating layer as well as the bottom surface and sidewall of the through hole; forming a metal material layer over the liner material; and performing chemical mechanical polishing until the metal material layer and the liner over the first insulating layer are removed. In one or more embodiments, the electrode layer and the liner layer of the via are formed from a same material or different materials. In one or more embodiments, the electrode layer is formed of titanium nitride, tantalum nitride, or titanium. In one or more embodiments, the first electrode is a flat bar-shaped conductor. In one or more embodiments, the patterned electrode layer laterally contacts the opposite sides of the phase-change material layer, thereby forming the first electrode and a second electrode that laterally contacts the phase-change material layer. In one or more embodiments, the second electrode is formed of titanium nitride, tantalum nitride, or titanium. In one or more embodiments, at a contact surface of the second electrode with the phase-change material layer, a width, b, of the second electrode is smaller than a size, c, of the phase-change material layer in a direction along the width. In one or more embodiments, at a contact surface of the second electrode with the phase-change material layer, a thickness, a, of the second electrode is smaller than the width, b, of the second electrode. In one or more embodiments, the second electrode is a flat bar-shaped conductor. In one or more embodiments, the method may include the following steps: forming a third insulating layer to cover the phase-change material layer and the second insulating layer; and forming a via penetrating through the third insulating layer and the second insulating layer and extending to the second electrode. In one or more embodiments, the method may include forming a second electrode over the second insulating layer and the phase-change material layer, the second electrode substantially covers the upper surface of the phase-change material layer. In one or more embodiments, the method may include the following steps: forming a third insulating layer over the second insulating layer and the second electrode; and forming a via penetrating through the third insulating layer and extending to the second electrode. In one or more embodiments, the second electrode extends beyond an edge of an upper surface of the phase-change material layer, and the second via is located on a portion of the second electrode that extends beyond the edge of the upper surface of the phase-change material layer. In one or more embodiments, the via extending to the second electrode is substantially aligned with the via electrically connected to the first electrode in a vertical direction. In one or more embodiments, the step of forming a phase-change material layer in the opening comprises: forming a phase-change material layer on the second insulating layer so as to fill up the opening; performing chemical mechanical polishing on the formed phase-change material layer such that the upper surface of the phase-change material layer is substantially flush with the upper surface of the second insulating layer, thereby forming the phase-change material layer. In one or more embodiments, a plurality of semiconductor memory devices is stacked in a direction perpendicular to a bottom surface of the substrate. One or more embodiments of the invention may be related to a semiconductor memory that may include the following elements: a first insulating layer; a phase-change material layer over the first insulating layer; a first electrode over the first insulating layer, wherein the first electrode laterally contacts the phase-change material layer; and a second insulating layer over the first insulating layer, the second insulating layer surrounding the phase-change material layer. On or more embodiments of the invention may be related to a method of manufacturing a semiconductor memory device. The method may include the following steps: providing a substrate with a first insulating layer formed thereon; forming an electrode layer over the first insulating layer; patterning the electrode layer; forming a second insulating layer to at least cover the patterned electrode layer; forming an opening that penetrates through the second insulating layer and the electrode layer; and forming a phase-change material layer in the opening, wherein the patterned electrode layer laterally contacts the phase-change material layer, thereby at least forming a first electrode that laterally contacts the phase-change material layer. Embodiments of the present invention will become apparent from the following detailed description with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. The present invention can be better understood by the following detailed descriptions with reference to the accompanying drawings, in which: FIG. 1 is a schematic diagram illustrating a conventional memory cell 100 of a phase-change memory having a BEC; FIG. 2A, FIG. 2B, and FIG. 2C illustrate arrangements of one or more electrodes and phase-change material in a memory device according to one or more embodiments of the present invention; FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D, and FIG. 3E illustrate examples in arranging one or more electrodes and a phase-change material (island-shaped) layer in a semiconductor memory device (e.g., a PCRAM device) according to one or more embodiments of the present invention; FIG. 4A, FIG. 4B, FIG. 4C, and FIG. 4D illustrate semiconductor memory devices according to one or more embodiments of the present invention; FIG. 5 illustrates a semiconductor memory device according to one or more embodiments of the present invention. FIG. 6(a), FIG. 6(b), FIG. 6(c), and FIG. 6(d) illustrate views of a semiconductor device according to one or more embodiments of the present invention; FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, and FIG. 12 illustrate steps in a method of manufacturing a semiconductor memory device according to one or more embodiments of the present invention; FIG. 13(a), FIG. 13(b), FIG. 13(c), FIG. 14(a), FIG. 14(b), FIG. 15, FIG. 16, FIG. 17, FIG. 18, and FIG. 19 illustrate steps in a method of manufacturing a semiconductor memory device according to one or more embodiments of the present invention; FIG. 20, FIG. 21(a), FIG. 21(b), FIG. 22(a), FIG. 22(b), FIG. 22(c), FIG. 23(a), FIG. 23(b), FIG. 24, FIG. 25, FIG. 26, FIG. 27, and FIG. 28 illustrate steps in a method of manufacturing a semiconductor memory device according to one or more embodiments of the present invention; FIG. 29(a), FIG. 29(b), FIG. 29(c), FIG. 30(a), FIG. 30(b), FIG. 31, FIG. 32, FIG. 33, FIG. 34, FIG. 35, and FIG. 36 illustrate steps in a method of manufacturing a semiconductor memory device according to one or more embodiments of the present invention; FIG. 37, FIG. 38(a), FIG. 38(b), FIG. 39(a), FIG. 39(b), and FIG. 39(c) illustrate steps in a method of manufacturing a semiconductor device according to one or more embodiments of the present invention; and FIG. 40 illustrates performance improvement of one or more embodiments of the present invention over a conventional device. It should be appreciated that these drawings are merely illustrative and are not intended to limit the scope of the disclosure. In the figures, various elements have not been drawn strictly to scale or according to their actual shapes, wherein some elements (e.g. layers or parts) can be magnified with respect to other elements, for the purpose of more clearly explaining the principles of the present invention. Moreover, those details that would otherwise obscure the gist of the present disclosure may not be shown in the figures. DETAILED DESCRIPTION One or more embodiments of the present disclosure will be described below in conjunction with the accompanying drawings. Note that in the figures, reference numbers for the same components, elements, or objects may not be repeatedly shown; those reference numbers that need to be emphasized may be repeatedly shown. Various embodiments are described herein below, including methods and techniques. It should be kept in mind that the invention might also cover an article of manufacture that includes a non-transitory computer readable medium on which computer-readable instructions for carrying out embodiments of the inventive technique are stored. The computer readable medium may include, for example, semiconductor, magnetic, opto-magnetic, optical, or other forms of computer readable medium for storing computer readable code. Further, the invention may also cover apparatuses for practicing embodiments of the invention. Such apparatus may include circuits, dedicated and/or programmable, to carry out operations pertaining to embodiments of the invention. Examples of such apparatus include a general purpose computer and/or a dedicated computing device when appropriately programmed and may include a combination of a computer/computing device and dedicated/programmable hardware circuits (such as electrical, mechanical, and/or optical circuits) adapted for the various operations pertaining to embodiments of the invention. Although the terms first, second, third etc. maybe used herein to describe various signals, elements, components, regions, layers, and/or sections, these signals, elements, components, regions, layers, and/or sections should not be limited by these terms. These terms may be used to distinguish one signal, element, component, region, layer, or section from another signal, region, layer or section. Thus, a first signal, element, component, region, layer, or section discussed below may be termed a second signal, element, component, region, layer, or section without departing from the teachings of the present invention. The description of an element as a “first” element may not require or imply the presence of a second element or other elements. The terms first, second, third etc. may also be used herein to differentiate different categories of elements. For conciseness, the terms first, second, third, etc. may represent first-category, second-category, third-category, etc., respectively. FIGS. 2A-2C illustrate examples of arrangements of one or more electrodes and a phase-change material (island-shaped) layer in a semiconductor memory device according to one or more embodiments of the present invention. As illustrated in FIG. 2A, a semiconductor memory device according to one or more embodiments of the present invention may comprise a phase-change element 213 or phase-change material (island-shaped) layer 213 (which also can be referred as a first phase-change material island-shaped layer, as can be understood from the description hereunder) embedded in one or more insulating elements (e.g., 211, 209 and 207); the semiconductor memory device may further comprise an electrode 217 (which also can be referred to as a first electrode) that laterally connects (to a side surface of) the first phase-change material island-shaped layer. In some embodiments, as described below in conjunction with FIG. 6, the electrode is generally configured such that at a contact surface of the electrode (e.g. 217) with the phase-change material island-shaped layer, the width of the electrode is larger than the thickness of the electrode, so as to reduce the contact area of the electrode with the phase-change material island-shaped layer. In some embodiments, the electrode 217 can be a flat bar-shaped conductor. In one or more embodiments, the electrode 217 may have one or more other shapes. In one or more embodiments, the semiconductor memory device may not be a PCRAM. In a number of embodiments, the insulating layers 207, 209 and 211 can be formed over a substrate (not shown) and/or an underlying layer. For example, the substrate may be or may include one or more of a mono-crystalline silicon substrate, a poly-silicon substrate, a semiconductor-on-insulator (SOI) substrate, a glass substrate, a sapphire substrate, a metal (e.g. stainless) substrate, a plastic substrate, etc. The phase-change material can be an alloy of chalcogenide, such as GST (Ge—Sb—Te, germanium-antimony-tellurium). In one or more embodiments, the phase-change element may include one or more other phase-change materials. It should be understood that the lateral direction may be defined with respect to the phase-change material island-shaped layer and has a meaning as commonly known. The lateral direction can also be understood as a direction substantially parallel to a bottom surface of the phase-change element 213 and/or parallel to a top surface or a bottom surface of the substrate. Since the substrate is generally placed horizontally, generally, the lateral direction can also be understood as a substantially horizontal direction. In one or more embodiments, as illustrated in FIG. 2A, a bottom portion of the phase-change elements extends into the insulating layer 207, and the bottom surface of the phase-change element 213 is disposed below the bottom surface of the electrode 217 and is disposed below the interface between the insulating layers 207 and 209. FIG. 2B illustrates an example of an arrangement of an electrode and a phase-change element (or phase-change material island-shaped layer) in a semiconductor memory device according to one or more embodiments. As illustrated in FIG. 2B, the electrode 217 laterally contacts the phase-change material island-shaped layer 213 at the lowest end of the side surface of said phase-change material island-shaped layer 213. The surface of the electrode 217 is substantially flush with (and aligned with) the bottom surface of the phase-change material island-shaped layer 213. In one or more embodiments, in order to realize the lateral contact between the electrode and the phase-change material island-shaped layer, over-etching maybe performed after forming the electrode 217 and during the process of forming an opening for the phase-change material. If the over-etching substantially stops at the top surface of the insulating layer 207, the arrangement illustrated in FIG. 2B may be formed. If a part of the insulating material under the opening is also etched in the over-etching, a recess on the insulating layer 207 maybe formed, and the phase-change element 213 may extend into the insulating layer 207, resulting in the arrangement illustrated in FIG. 2A. FIG. 2C illustrates an example of an arrangement of an electrode and a phase-change material island-shaped layer in a semiconductor memory device according to one or more embodiments. As illustrated in FIG. 2C, the electrode 217 connects to the phase-change material island-shaped layer 213 at the upper end of the side wall of the phase-change material island-shaped layer 213. The top surface of the electrode 217 is substantially flush with (and aligned with) the upper surface of the phase-change material island-shaped layer 213. In one or more embodiments, the combination of the insulating layer 207 and the insulating layer 209 may represent an integral insulating layer and can be, as a whole, formed from one insulating material layer instead of being formed from two insulating material layers. As illustrated in FIGS. 2A-2C, the electrode 217 may be disposed between the insulating layers 207 and 209 or between the insulating layers 209 and 211. The phase-change material island-shaped layer can be regarded as being embedded in an insulating material that includes the elements 211, 209 and 207. The insulating layer 211 illustrated in FIGS. 2A-2C can facilitate the forming of an electrical connection (e.g. a wire or via) to the phase-change material island-shaped layer 213 and can electrically and/or thermally insulate the phase-change material island-shaped layer 213 from materials (such as metal wiring) disposed on the insulating layer 211. In one or more embodiments, the semiconductor memory device may not include the insulating layer 211. In one or more embodiments, metal wiring (analogous to the metal wiring 115 illustrated in FIG. 1) may directly contact and cover the phase-change material island-shaped layer 213 and may be disposed between the phase-change element 213 and the insulating layer 211, and the insulating layer 211 can serve as a passivation layer and/or an interlayer insulating layer. In one or more embodiments, the semiconductor memory device may include one or more other electrodes that are analogous to one or more electrodes illustrated in FIG. 1. FIGS. 3A-3E illustrate examples of arrangements of one or more electrodes and a phase-change material island-shaped layer in a semiconductor memory device, such as a PCRAM device, according to one or more embodiments of the present invention. The arrangements illustrated in FIGS. 3A-3C include elements analogous to elements in the situations illustrated in FIGS. 2A-2C, respectively. In addition to the first electrode 317, the second electrode 319 may be included. As illustrated in FIGS. 3A, 3B, and 3C, the second electrode 319 may laterally contact the phase-change material island-shaped layer. In one or more embodiments, the contact area associated with each of the electrodes 317 and 319 may be substantially smaller than the contact area associated with the electrode 217 illustrated in FIGS. 2A-2C. In one or more embodiments, the second electrode 319 is configured such that at a contact surface of the second electrode 319 with the phase-change material island-shaped layer, the width of the second electrode 319 is larger than the thickness of the second electrode 319, thereby reducing the contact area of the second electrode with the phase-change material island-shaped layer. In some embodiments, the second electrode 319 can be a flat bar-shaped conductor so as to reduce its contact area with the phase-change material island-shaped layer. In one or more embodiments, the second electrode 319 may have one or more other shapes. The second electrode 319 may be disposed between the insulating elements 307 and 309 or between the insulating elements 309 and 311. In one or more embodiments, as illustrated in FIGS. 3D and 3E, the second electrode 319 is formed over the phase-change material island-shaped layer 313 and contacts the upper surface (or top surface) of the phase-change material island-shaped layer 313. In one or more embodiments, the second electrode 319 substantially covers the upper surface of the phase-change material island-shaped layer 313 such that the phase-change material can be prevented from being etched during the electrode patterning process. In one or more embodiments, as illustrated in FIG. 3E, the second electrode 319 extends substantially beyond at least one edge of the phase-change material island-shaped layer 313, so as to form an electrical connection (for example, upper via, as illustrated in FIG. 4D and described below) to an element that is not aligned with the phase-change element. In one or more embodiments, the first electrode and/or the second electrode can be formed of one or more of titanium nitride (TiN), tantalum nitride (TaN), and Titanium. In one or more embodiments, the first electrode and/or the second electrode can be formed of same or different suitable conductive and/or semiconductive materials. In one or more embodiments, as will be described later, the semiconductor memory device may further comprise a first wiring or a first via electrically connected to the first electrode, and/or a second wiring or a second via electrically connected to the second electrode. FIGS. 4A-4D illustrate semiconductor memory devices according to one or more embodiments of the present invention. As illustrated in FIG. 4A, the semiconductor memory device 400a may comprise a phase-change material island-shaped layer 413 (or phase-change element 413) embedded in an insulating material (including elements 407, 409 and 411). The semiconductor memory device 400a may further comprise a first electrode 417 and a second electrode 419 that laterally contact opposite side surfaces of the phase-change material island-shaped layer 413. The semiconductor memory device 400a may further comprise a via (which can be referred to as a lower via or a first via) electrically connected to the first electrode 417. The lower via can comprise a liner 403 and a metal plug 405. In one or more embodiments, the liner 403 of the lower via, the first electrode 417, and the second electrode 419 are formed from a continuous layer of a same material, which may include one or more of titanium nitride (TiN), tantalum nitride (TaN), and titanium. The electrodes 417 and 419 can be formed by the process of forming via liner in a via formation process cycle using a liner material (such as TiN material). The electrode layer for forming the electrodes 417 and 419 can be formed simultaneously with the liner 403 of the lower via in a liner forming step in the via formation process cycle. In one or more embodiments, the electrodes 417 and 419 can be made of one or more suitable conductive materials different from the via liner material. In one or more embodiments, the electrode layer is formed using the liner material in a via formation process cycle; advantageously, several process steps can be saved and the process becomes simple. The metal plug 405 can be formed using one or more of copper, aluminium, tungsten, nickel, and an alloy or stack of some of these metals through one or more of sputtering, electroplating, electroless plating, etc. The semiconductor memory device 400a may further comprise a via (which is also referred as an upper via or a second via) electrically connected to the second electrode 419. The upper via can comprise a liner 423 and a metal plug 425. The materials for forming the liner 423 and the metal plug 425 can be the same as or different from the materials for forming the liner 403 and the metal plug 405, respectively. In one or more embodiments, the semiconductor memory device 400a can further comprise conductors (e.g. wirings) 401 and 421 that are respectively electrically connected to the upper via and the lower via. It should be understood that the materials and methods for forming the liners and the metal plugs of the vias are not limited to the materials and methods discussed above. One skilled in the art can freely select suitable materials and methods as needed or based on design requirements. Further, it should be understood that the upper via and the lower via mentioned herein are merely illustrative, and one skilled in the art can select suitable manners for the connections between either of the first and second electrodes and other layers, components, or elements as needed. In one or more embodiments, one or both of the vias can be replaced by one or more of wiring(s), doped semiconductor layer(s), etc. FIG. 4B illustrates a semiconductor memory device 400b according to one or more embodiments of the present invention. As illustrated in FIG. 4B, the semiconductor memory device 400b comprises two upper vias that are respectively electrically connected to the first electrode 417 and the second electrode 419. Additionally or alternatively, the device 400b may comprise two lower vias that are respectively connected to the first electrode 417 and the second electrode 419. One or both of the lower vias maybe analogous to the lower via discussed with reference to FIG. 4A. FIG. 4C illustrates a semiconductor memory device 400c according to one or more embodiments of the present invention. The semiconductor memory device 400c may comprise a phase-change material island-shaped layer 413 (or phase-change element 413) embedded in an insulating material (which may include elements 407, 409 and 411). The semiconductor memory device 400c may comprise a first electrode 417 that laterally contacts to a side surface of the phase-change material island-shaped layer 413. The semiconductor memory device 400c may comprise a second electrode 419 that is located over the phase-change material island-shaped layer 413 and contacts the upper surface (or top surface) of the phase-change material island-shaped layer 413. The upper surface of the phase-change element 413 may be substantially perpendicular to the side surface of the phase-change element 413. In one or more embodiments, the second electrode 419 substantially covers the upper surface of the phase-change material island-shaped layer 413, so as to protect the phase-change material island-shaped layer during etching performed for the patterning of the electrode. In one or more embodiments, the second electrode 419 can be formed from TiN. In one or more embodiments, the second electrode 419 can be implemented using a suitable conductive material or a stack of conductive materials. The semiconductor memory device 400c may further comprise a lower via electrically connected to the first electrode 417, wherein the lower via can comprise a liner 403 and a metal plug 405. The semiconductor memory device 400c may further comprise an upper via that is located over the second electrode 419 and electrically connected to the second electrode 419. The upper via can comprise a liner 423 and a metal plug 425. In one or more embodiments, the semiconductor memory device 400a can further comprise conductors (such as wirings) 401 and 421 that are respectively electrically connected to the lower via and the upper via. FIG. 4D illustrates a semiconductor memory device 400d according to one or more embodiments of the present invention. In the semiconductor memory device 400d, the second electrode 419 not only covers the upper surface of the phase-change material island-shaped layer 413, but also extends beyond the edge of the upper surface of the phase-change material island-shaped layer 413, and an upper via comprising the liner 423 and the metal plug 425 is formed over a portion of the second electrode 419 that extends beyond the edge of the upper surface of the phase-change material island-shaped layer 413. In one or more embodiments, the upper via is substantially aligned with the lower via connected to the first electrode 417 in a longitudinal direction (or in a vertical direction) that is substantially perpendicular to the extension direction of the second electrode 419 and/or substantially perpendicular to the upper surface of the phase-change element 413. One skilled in the art would appreciate that the manufacturing process for device 400d may be substantially similar to that for device 400c. FIG. 5 illustrates a semiconductor memory device 500 according to one or more embodiments of the present invention. The semiconductor memory device 500 may comprise a first phase-change material island-shaped layer 523 (or phase-change element 523) and a second phase-change material island-shaped layer 533 (or phase-change element 522). The semiconductor memory device 500 may further comprise a first electrode 527 and a second electrode 529 that contact the first phase-change material island-shaped layer 523, wherein the first electrode 527 laterally contacts a side surface of the first phase-change material island-shaped layer 523, and wherein the second electrode 529 contacts the top surface (or upper surface) of the first phase-change material island-shaped layer 523. The semiconductor memory device 500 may further comprise a third electrode 537 and a fourth electrode 539 that contact the second phase-change material island-shaped layer 533, wherein the third electrode 537 laterally contacts a side surface of the second phase-change material island-shaped layer 533, and wherein the fourth electrode 539 contacts the top surface (or upper surface) of the second phase-change material island-shaped layer 533. Each of the first electrode 527 and the third electrode 537 may be disposed between the insulating layers 507 and 509. Each of the second electrode 529 and the fourth electrode 539 may be disposed between the insulating layers 509 and 511. The second electrode 529 is located over the first phase-change material island-shaped layer 523 and contacts the upper surface of the first phase-change material island-shaped layer 523. In one or more embodiments, the second electrode 529 substantially covers the upper surface of the first phase-change material island-shaped layer 523. The fourth electrode 539 is located over the second phase-change material island-shaped layer 533 and contacts the upper surface of the second phase-change material island-shaped layer 533. In one or more embodiments, the fourth electrode 539 substantially covers the upper surface of the second phase-change material island-shaped layer 533. The semiconductor memory device 500 may further comprise a lower via electrically connected to the first electrode 527 and the third electrode 537. The lower via can comprise a liner 503 and a metal plug 505. The first electrode 527 and the third electrode 537 may be electrically connected to each other through the line 503 and/or through the metal plug 505. The semiconductor memory device 500 may further comprise a first upper via that is located over the second electrode 529 and electrically connected to the second electrode 529, wherein the second electrode 529 may be disposed between the first upper via and the first phase-change element 523, wherein the first upper via can comprise a liner 543 and a metal plug 525, and wherein a portion of the liner 543 is disposed between the metal plug 525 and the second electrode 529. The semiconductor memory device 500 may further comprise a second upper via that is located over the fourth electrode 539 and connected to the fourth electrode 539, wherein the second upper via can comprise a liner 553 and a metal plug 535. In one or more embodiments, the second electrode 529 and the fourth electrode 539 are not electrically connected to each another. In one or more embodiments, the semiconductor memory device 500 can further comprise wirings 501, wirings 521, and wirings 531 that are electrically connected to the lower via, the first upper via, and the second upper via, respectively. One skilled in the art can readily understand that one or more of the elements discussed with reference to FIG. 5 can be combined with one or more elements discussed with reference to one or more of FIGS. 4A-4E as well as other known elements. Although FIG. 5 illustrates an example of two memory cells disposed in a plane parallel to the bottom surface of the insulating layer(s) and/or the top surface of the insulating layer(s), the present disclosure is not limited thereto. In one or more embodiments, memory cells can be stacked in a perpendicular direction (perpendicular to the substrate surface and/or perpendicular to the bottom and/or top surface of one or more insulating layers), and thus memory density in a surface area can be increased. FIGS. 6(a), 6(b), 6(c), and 6(d) illustrate views of a semiconductor memory device according to one or more embodiments of the present invention. The views may clearly illustrate the contact areas between electrodes and a phase-change element. The semiconductor memory device may include one or more elements analogous to one or more elements discussed with reference to FIG. 4A. FIG. 6(a) illustrates a partially exposed view of the device viewed from the top, FIG. 6(b) illustrates a cross-sectional view at line A-A′ viewed from the front, FIG. 6(c) illustrates a partially exposed view at line B-B′ seen from the right side, and FIG. 6(d) illustrates an enlarged view of a portion of the view illustrated in FIG. 6(c). FIG. 6(d) illustrates the contact area (which corresponds to cross-sectional dimensions thickness a×width b of the electrode 419) between the electrode 419 and the phase-change material 413. Herein, one or more features described in connection with the second electrode 419 can also be suitably applied to the first electrode 417. For example, the first electrode 417 may also have a thickness a and a width b, and a contact area between the phase-change material 413 and the first electrode 417 also can be defined by the cross-sectional dimensions of the first electrode 417. As can be seen from FIG. 6(b), the structure of the device is substantially similar to the structure illustrated in FIG. 4A, except the metal wiring 401. Therefore, reference numbers similar to those illustrated in FIG. 4A may be employed in FIG. 6 to indicate similar components, and detailed descriptions thereof may be omitted. Note that the two dotted circles illustrated in FIG. 6(a) respectively represent the upper via and the lower via, while the solid circles represent the metal plugs therein, respectfully. The portion between a dotted circle and a solid circle represents the liner 403 or the liner 423. In FIG. 6(c) and FIG. 6(d), the lower via is indicated by a dotted line. It should be understood that FIGS. 6(a)-6(d) are illustrative and are not intended to limit the scope of the present invention in any manner. It should be understood that various patterns or graphs and their sizes and relative relationships illustrated in FIGS. 6(a)-6(d) are illustrative, unless specifically indicated to the contrary. For example, as for via, although one or more embodiments may employ a via of a circle shape, a via of a square shape or another suitable shape may be alternatively or additionally used. For example, the minimum size of a via can depend on process conditions. Some critical sizes discussed in the background section of this specification are not intended to limit the scope of the present invention, but merely examples. In one or more embodiments, as illustrated in FIG. 6(a), edges of the first electrode 417 and edge of the second electrode 419 are tangent to the circumference of the lower via and the circumference of the upper via, respectively, in a plan view of the memory device. In one or more embodiments, one or more edges of an electrode and the circumference of a via may have one or more additional or alternative relationships. One or more sizes of one or more of the first electrode, the second electrode, the upper via, and the lower via may depend on design rules and/or manufacturing processes (e.g. lithography and etching); sizes equal to or larger than minimum sizes can be employed. In one or more embodiments, it is contemplated to break through the minimum size allowed by design rules so as to realize a minimum size that can be realized by technologic process as possible. Various relations may be possible between the first/second electrode and the corresponding wiring or via. In one or more embodiments, one or more edges of the first electrode 417 and/or the second electrode 419 can intersect the circumference of the upper via and/or the circumference of the lower via in a plan view of the memory device, give a minimized width b of the first electrode 417 and/or a minimized width b of the second electrode 419. In one or more embodiments, the diameter of a via may be smaller than the width
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