Title of Invention: MEMORY SYSTEM Abstract: A memory system includes a storage device and a controller. The storage device includes a first string including a first memory cell transistor and a second memory cell transistor connected in series to each other, and a first select transistor, a second string including a third memory cell transistor and a second select transistor, a gate of the second select transistor being independent from a gate of the first select transistor. The controller configured to perform first writing to cause a threshold voltage of the first memory cell transistor to be lower than a first target threshold voltage, perform second writing to cause a threshold voltage of the second memory cell transistor to be higher than a second target threshold voltage after the first writing, perform third writing to cause a threshold voltage of the first memory cell transistor to be higher than the first target threshold voltage after the second writing, and perform fourth writing on the third memory cell transistor after the third writing. Detailed Description: CROSS-REFERENCE TO RELATED APPLICATION This application is based upon and claims the benefit of priority from Japanese Patent Application No. 3604069332, filed on Sep. 14, 2018, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a memory system. BACKGROUND There is a memory system including a semiconductor memory and a controller controlling the semiconductor memory. DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating elements and connection therebetween in a memory system according to a first embodiment. FIG. 2 is a circuit diagram illustrating examples of several elements and connection therebetween in a memory cell array of the first embodiment. FIG. 3 is a cross-sectional diagram illustrating elements and connection therebetween in a memory block of the first embodiment. FIG. 4 is a diagram illustrating a distribution of threshold voltages of a memory cell transistor holding 4-bit data of the first embodiment. FIG. 5 is a graph illustrating voltages applied to several lines during programming over time in the first embodiment. FIG. 6 is a diagram illustrating a change in a threshold voltage distribution of the memory cell transistor due to first writing in the first embodiment. FIG. 7 is a diagram illustrating a change in a threshold voltage distribution of the memory cell transistor due to second writing in the first embodiment. FIG. 8 is a conceptual diagram illustrating transition in a state of a cell unit according to one-step writing. FIG. 9 is a conceptual diagram illustrating transition in a state of a cell unit according to two-step writing in the first embodiment. FIG. 10 is a table illustrating an order of data writing in the first embodiment. FIG. 11 is a schematic diagram illustrating write data stored in a memory controller during writing in the first embodiment. FIG. 12 is a table illustrating an order of data writing according to a reference example. FIG. 13 is a schematic diagram illustrating write data stored in a memory controller during writing according to the reference example. FIG. 14 is a diagram illustrating a change in a threshold voltage distribution of a memory cell transistor according to one-step writing in a second embodiment. FIG. 15 is a conceptual diagram illustrating a string unit set according to the second embodiment. FIG. 16 is a table illustrating a data writing method according to the second embodiment. FIG. 17 is a table illustrating a data writing method according to the second embodiment. FIG. 18 is a conceptual diagram illustrating a certain state during first unit writing in the second embodiment. FIG. 19 is a cross-sectional diagram illustrating a certain state of a single string during writing according to the second embodiment. FIG. 20 is a conceptual diagram illustrating disturbance types which may occur in the second embodiment. FIG. 21 is a diagram illustrating a change in a threshold voltage distribution of a memory cell transistor according to one-step writing in a third embodiment. FIG. 22 is a table illustrating a data writing method according to the third embodiment. FIG. 23 is a table illustrating a data writing method according to a fourth embodiment. FIG. 24 is a conceptual diagram illustrating disturbances in a memory system according to the fourth embodiment. FIG. 25 is a table illustrating a data writing method according to a modification example of the fourth embodiment. DETAILED DESCRIPTION Embodiments provide a memory system with high performance. In general, according to an embodiment, a memory system includes a storage device and a controller. The storage device includes a first string including a first memory cell transistor and a second memory cell transistor connected in series to each other, and a first select transistor, a second string including a third memory cell transistor and a second select transistor, a gate of the second select transistor being independent from a gate of the first select transistor. The controller configured to perform first writing to cause a threshold voltage of the first memory cell transistor to be lower than a first target threshold voltage, perform second writing to cause a threshold voltage of the second memory cell transistor to be higher than a second target threshold voltage after the first writing, perform third writing to cause a threshold voltage of the first memory cell transistor to be higher than the first target threshold voltage after the second writing, and perform fourth writing on the third memory cell transistor after the third writing. Hereinafter, embodiments will be described with reference to the drawings. In the following description, constituent elements having the substantially same function and configuration are given the same reference numeral, and repeated description will be omitted. Description of a certain embodiment may be applied to description of other embodiments as long as the description is explicitly or obviously excluded. Each functional block may be implemented by either one of hardware and computer software or a combination thereof. Thus, each functional block is generally described from the viewpoint of its function such that it is clarified that the functional block is implemented by any one of them. It is not essential that each functional block is differentiated as in the following examples. For example, some functions may be executed by another functional block which is different from an exemplified functional block. An exemplified functional block may be divided into functional sub-blocks. Any step in a flow regarding a method of an embodiment is not limited to an exemplified order, and may occur in an order which is different from the exemplified order and (or) in parallel to other steps unless otherwise mentioned. In the present specification and claims, a certain first element “being connected” to another second element includes that the first element is connected to the second element directly, or normally or selectively via a conductive element. First Embodiment 1.1 Structure (Configuration) FIG. 1 illustrates elements and connection therebetween of a memory system according to a first embodiment. As illustrated in FIG. 1, a memory system 5 is controlled by a host apparatus 3, and includes a semiconductor memory 1 and a memory controller 2. The memory system 5 may be, for example, a solid state drive (SSD) or an SD™ card. The semiconductor memory 1 is controlled by the memory controller 2. The memory controller 2 receives a command from the host apparatus 3, and controls the semiconductor memory 1 on the basis of the received command. 1.1.1 Memory Controller The memory controller 2 includes a host interface 21, a central processing unit (CPU) 22, a random access memory (RAM) 23, a read only memory (ROM) 24, a memory interface 25, and an error correction code (ECC) circuit 26. Firmware (program) which is stored in the ROM 24 and is loaded to the RAM 23 is executed by the CPU 22. Thereby, the memory controller 2 executes various operations, and some functions of the host interface 21 and the memory interface 25. The RAM 23 temporarily stores data, and functions as a buffer memory and a cache memory. The host interface 21 is connected to the host apparatus 3 via a bus, and performs communication between the memory controller 2 and the host apparatus 3. The memory interface 25 is connected to the semiconductor memory 1, and performs communication between the memory controller 2 and the semiconductor memory 1. The ECC circuit 26 performs processes to detect and correct errors on data to be written into the semiconductor memory 1 and data read from the semiconductor memory 1. Specifically, the ECC circuit 26 generates redundancy data for correcting an error of data to be written (also referred to as actual write data) into the semiconductor memory 1. The generated redundancy data and the actual write data are written into the semiconductor memory 1 as write data. The ECC circuit 26 detects an error of data read from the semiconductor memory 1, and corrects an error when there is the error. 1.1.2 Semiconductor Memory The semiconductor memory 1 includes elements such as a memory cell array 11, an input/output circuit 12, a sequencer 13, a driver 15, a sense amplifier 16, and a row decoder 19. The memory cell array 11 includes a plurality of memory blocks (also simply referred to as blocks) BLK (for example, BLK0, BLK1, . . . ). Each block BLK is an aggregation of a plurality of string units SU (for example, SU0, SU1, . . . ). Each string unit SU is an aggregation of a plurality of NAND strings (also simply referred to as strings) STR (for example, STR0, STR1, . . . ) (not illustrated). Each string STR includes a plurality of memory cell transistors MT. The input/output circuit 12 is connected to the memory controller 2 via a NAND bus. The NAND bus transmits a plurality of control signals and a signal DQ having an 8-bit width. The control signals include signals −CE, CLE, ALE, −WE, −RE, −WP, and data strobe signals DQS and −DQS. The symbol “−” indicates an inversion logic. The input/output circuit 12 receives the signal DQ, and transmits the signal DQ. The input/output circuit 12 receives a control signal from the memory controller 2, and receives and outputs the signal DQ according to the control signal. The signal DQ includes a command CMD, write data or read data DAT, an address ADD, a status STA, and the like. The sequencer 13 receives the command CMD and the address ADD from the input/output circuit 12, and controls the driver 15, the sense amplifier 16, and the row decoder 19 according to the command CMD and the address ADD. The driver 15 supplies potentials selected from a plurality of potentials, to the row decoder 19. The row decoder 19 receives various potentials from the driver 15, receives the address ADD from the input/output circuit 12, and transmits the potentials from the driver 15, to a single block BLK which is selected according to the received address ADD. The sense amplifier 16 senses a state of the memory cell transistor MT, generates read data on the basis of the sensed state, and transmits write data to the memory cell transistor MT. 1.1.3 Memory Cell Array FIG. 2 illustrates examples of several elements and connection therebetween in the memory cell array 11 according to the first embodiment, and illustrates elements and connection therebetween of a single block BLK0, and related elements. A plurality of blocks BLK, for example, all blocks BLK include the elements and connection therebetween illustrated in FIG. 2. A single block BLK includes a plurality of (for example, four) string units SU0 to SU3. Each of p (where p is a natural number) bit lines BL0 to BL(p−1) is connected to a single string STR from each of the string units SU0 to SU3 in each block BLK. Each string STR includes a single selection gate transistor ST, a plurality of (for example, eight) memory cell transistors MT (for example, MT0 to MT7), and a single selection gate transistor DT (for example, DT0, DT1, DT2, or DT3). The transistors ST, MT, and DT are connected in series in this order between a source line CELSRC and a single bit line BL. The memory cell transistor MT includes a control gate electrode (that is, a word line WL) and a charge storage layer insulated from the surrounding, and may maintain data in a nonvolatile manner on the basis of an amount of electric charge in the charge storage layer. A plurality of strings STR are respectively connected to a plurality of different bit lines BL and form a single string unit SU. In each string unit SU, control gate electrodes of the memory cell transistors MT0 to MT7 are respectively connected to the word lines WL0 to WL7. In each block BLK, the word lines WL having the same ID (address) in different string units SU are connected to each other. A set of memory cell transistors MT sharing the word line WL in a single string unit SU is referred to as a cell unit CU. The transistors DT0 to DT3 (FIG. 2 does not illustrate DT2 and DT3) are respectively provided in the string units SU0 to SU3. With respect to respective cases of α=0 to 3, a gate of the transistor DTα of each of a plurality of strings STR of the string unit SUα is connected to a select gate line SGDLα. A gate of the transistor ST is connected to a select gate line SGSL. Each block BLK may have a structure illustrated in FIG. 3. FIG. 3 schematically illustrates a structure of a part of the memory cell array of the first embodiment. As illustrated in FIG. 3, the string unit SU is provided on a substrate sub. The substrate sub extends along an xy plane and includes a p-type well pw in a surface region. Each string unit SU includes a plurality of strings STR arranged along the x axis. Each string STR includes a semiconductor pillar PL. The pillar PL extends along the z axis, is in contact with the well pw, and functions as a channel region in which channels of the transistors MT, DT, and ST are formed, and a body. An upper end of the pillar PL is connected to a conductor CT via conductive plug CP. The conductor CT extends along the y axis to function as a single bit line BL, and has a gap with the conductor CT located at another coordinate on the x axis. A side surface of the pillar PL is covered with a tunnel insulator (layer) IT. The tunnel insulator IT is also located on the well pw. A side surface of the tunnel insulator IT is covered with a charge storage layer CA. The charge storage layer CA is an insulating layer or a conductive layer, and a side surface thereof is covered with a block insulator (layer) IB. In each string unit SU, a single conductor CS, a plurality of (for example, eight) conductors CW, and a plurality of (for example, three) conductors CD are provided over the well pw. A plurality of conductors CS may be provided. The conductors CS, CW, and CD are arranged in this order with gaps along the z axis, and extend along the x axis to contact the block insulator IB. The conductor CS interposes the tunnel insulator IT with the surface of the well pw. The conductors CS, CW, and CD function as the select gate line SGSL, the word lines WL0 to WL7, and the select gate lines SGDL, respectively. In each string unit SU, the conductors CS, CW, and CD are in internal contact with the block insulators IB on the side surfaces of all of the pillars PL in the string unit SU. In the pillar PL, the tunnel insulator IT, the charge storage layer CA, and the block insulator IB, portions intersecting the conductors CS, CW, and CD function as the selection gate transistor ST, the memory cell transistors MT, and the selection gate transistor DT, respectively. The transistors ST, MT, and DT sharing the pillar PL and arranged along the z axis form a single string STR. A diffusion layer Dp of p+ type impurities is provided in a region inside the surface of the well pw. The diffusion layer Dp is connected to a conductor CCW via a conductive plug CPW. The plug CPW is spread along an xz plane. A diffusion layer Dn of n+ type impurities is also provided in the region in the surface of the well pw. The diffusion layer Dn is connected to a conductor CCS via a conductive plug CPS. The conductor CCS functions as the source line CELSRC. An insulator IIL1 is provided in a region in which the conductors CS, CW, CD, CCS, and CCW, and the plugs CPS and CPW are not provided on the substrate sub. 1.1.4 Memory Cell Transistor With reference to FIG. 4, the memory cell transistor MT will be described. The semiconductor memory 1 may store data of 2 or more bits in a single memory cell transistor MT. FIG. 4 illustrates a distribution of threshold voltages of the memory cell transistor MT storing 4-bit data per memory cell transistor MT as a result of data writing in the memory system according to the first embodiment. A threshold voltage of each memory cell transistor MT has a value corresponding to stored data. When 4 bits are stored in each memory cell transistor MT, each memory cell transistor MT may have any one of 16 threshold voltages. The 16 threshold voltages are in states of storing data of “1111”, data of “1110”, data of “1010”, data of “1000”, data of “1001”, data of “0001”, data of “0000”, data of “0010”, data of “0110”, data of “0100”, data of “1100”, data of “1101”, data of “0101”, data of “0111”, data of “0011”, and data of “1011”, respectively. The memory cell transistor MT in in states of storing data of “1111”, data of “1110”, data of “1010”, data of “1000”, data of “1001”, data of “0001”, data of “0000”, data of “0010”, data of “0110”, data of “0100”, data of “1100”, data of “1101”, data of “0101”, data of “0111”, data of “0011”, and data of “1011” will be referred to as being in Er, A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O states, respectively. The memory cell transistor MT in the Er state, the A state, the B state, the C state, the D state, the E state, the F state, the G state, the H state, the I state, the J state, the K state, the L state, the M state, the N state, and the O state has a higher threshold voltage in this order. Even a plurality of memory cell transistors MT storing identical 4-bit data may have different threshold voltages due to a variation in characteristics of the memory cell transistors MT. In FIG. 4 and the subsequent drawings, a distribution of threshold voltages is indicated by consecutive curves, but, actually, the number of memory cell transistors MT is discrete. A state of the corresponding memory cell transistor MT is determined in order to determine data stored in the read target memory cell transistor MT. In order to determine a state, read voltages VA, VB, VC, VD, VE, VF, VG, VH, VI, VJ, VK, VL, VM, VN, and VO are used. Hereinafter, a voltage with a predetermined magnitude applied to the read target memory cell transistor MT, including the read voltages VA, VB, VC, VD, VE, VF, VG, VH, VI, VJ, VK, VL, VM, VN, and VO, in order to determine a state of the memory cell transistor MT, may be referred to as a read voltage VCGR. The read voltage VA is higher than the highest threshold voltage of the memory cell transistor MT in the Er state, and is lower than the lowest threshold voltage of the memory cell transistor MT in the A state right after writing is performed. The read voltage VB is higher than the highest threshold voltage of the memory cell transistor MT in the A state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the B state right after writing is performed. The read voltage VC is higher than the highest threshold voltage of the memory cell transistor MT in the B state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the C state right after writing is performed. The read voltage VD is higher than the highest threshold voltage of the memory cell transistor MT in the C state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the D state right after writing is performed. The read voltage VE is higher than the highest threshold voltage of the memory cell transistor MT in the D state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the E state right after writing is performed. The read voltage VF is higher than the highest threshold voltage of the memory cell transistor MT in the E state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the F state right after writing is performed. The read voltage VG is higher than the highest threshold voltage of the memory cell transistor MT in the F state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the G state right after writing is performed. The read voltage VH is higher than the highest threshold voltage of the memory cell transistor MT in the G state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the H state right after writing is performed. The read voltage VI is higher than the highest threshold voltage of the memory cell transistor MT in the H state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the I state right after writing is performed. The read voltage VJ is higher than the highest threshold voltage of the memory cell transistor MT in the I state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the J state right after writing is performed. The read voltage VK is higher than the highest threshold voltage of the memory cell transistor MT in the J state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the K state right after writing is performed. The read voltage VL is higher than the highest threshold voltage of the memory cell transistor MT in the K state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the L state right after writing is performed. The read voltage VM is higher than the highest threshold voltage of the memory cell transistor MT in the L state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the M state right after writing is performed. The read voltage VN is higher than the highest threshold voltage of the memory cell transistor MT in the M state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the N state right after writing is performed. The read voltage VO is higher than the highest threshold voltage of the memory cell transistor MT in the N state right after writing is performed, and is lower than the lowest threshold voltage of the memory cell transistor MT in the O state right after writing is performed. The read voltages VA, VB, VC, VD, VE, VF, VG, VH, VI, VJ, VK, VL, VM, VN, and VO are, for example, default voltages. Reading using a read voltage VX (where X is A, B, C, D, E, F, G, H, I, J, K, L, M, N, or O) will be referred to as X reading (XR). A range of a threshold voltage of the read target memory cell transistor MT is used to calculate a state of the memory cell transistor MT. In order to calculate a range of a threshold voltage of the read target memory cell transistor MT, it is determined whether or not the read target memory cell transistor MT exceeds a certain read voltage VCGR. The memory cell transistor MT having a threshold voltage which is equal to or higher than the read voltage VCGR is maintained in an OFF state even if the read voltage VCGR is applied to the control gate electrode thereof. On the other hand, the memory cell transistor MT having a threshold voltage which is lower than the read voltage VCGR is turned on when the read voltage VCGR is applied to the control gate electrode thereof. A voltage VREAD is applied to the word line WL of the memory cell transistor MT of a non-read target cell unit CU, and is higher than a threshold voltage of the memory cell transistor MT in any state. A set of data of bits at an identical position (that is, a digit) of the memory cell transistors MT of a single cell unit CU configures a single page. A set of data of the most significant (that is, the first digit) bits of the memory cell transistors MT of each cell unit CU will be referred to as a top page. A set of data of bits in the second digit from the most significant bits of the memory cell transistors MT of each cell unit CU will be referred to as an upper page. A set of data of bits in the third digit from the most significant bits of the memory cell transistors MT of each cell unit CU will be referred to as a middle page. A set of data of the least significant (that is, the fourth digit) bits of the memory cell transistors MT of each cell unit CU will be referred to as a lower page. Data of each page is calculated through reading using a plurality of read voltages VCGR having different values. Examples thereof will be described below. Respective bits of a lower page are respectively calculated through A reading, D reading, F reading, and K reading. Middle page data is calculated through C reading, G reading, I reading, and M reading. Upper page data is calculated through B reading, H reading, and N reading. Top page data is calculated through E reading, J reading, L reading, and O reading. 1.2 Operation The memory system 5 writes data into a write target cell unit (selected cell unit) CU by using two-step writing. The two-step writing includes first writing and second writing. Both of the first writing and the second writing include repetition of a plurality of program loops. Each program loop includes programming and verification. The programming indicates that a threshold voltage of a program target memory cell transistor MT is increased by injecting electrons into the charge storage layer of the program target memory cell transistor MT, or a threshold voltage thereof is maintained by inhibiting injection of electrons. A string STR including the program target memory cell transistor MT into which electrons are injected will be referred to as a programmable string STR(p), and a bit line BL connected to the programmable string STR(p) will be referred to as a programmable bit line BL(p). On the other hand, a string STR including a program target memory cell transistor MT into which electrons are not injected will be referred to as a program inhibition string STR(i), and a bit line BL connected to the program inhibition string STR(i) will be referred to as a program inhibition bit line BL(i). The verification refers to determination of if a threshold voltage of a program target memory cell transistor MT reaches a desired state by reading data from the selected memory cell transistor MT. When the threshold voltage of the selected memory cell transistor MT reaches the desired state, this will be referred to as “passing verification”, and when the threshold voltage does not reach the desired state, this will be referred to as “failing in verification”. FIG. 5 illustrates voltages applied to several lines during programming over time in the first embodiment, and illustrates voltages during programming in a single program loop. Hereinafter, in some cases, a write target cell unit CU will be referred to as a selected cell unit CU, a word line WL connected to the selected cell unit CU will be referred to as a selected word line WL, and a memory cell transistor MT connected to the selected word line WL will be referred to as a selected memory cell transistor MT. In some cases, the word lines WL other than the selected word line WL will be referred to as non-selected word lines WL, and memory cell transistors MT connected to the non-selected word lines WL will be referred to as non-selected memory cell transistors MT. As illustrated in FIG. 5, at time t1, the sequencer 13 applies a voltage VSS to all illustrated lines. The sequencer 13 applies a voltage VSG to the select gate line SGDL (illustrated as “selected SGDL” in FIG. 5) of a write target string unit (also referred to as a “selected string unit”) SU. The voltage VSG has a magnitude sufficient to cause the selection gate transistor DT to be turned on. As a result, the selection gate transistor DT is turned on in the selected string unit SU. On the other hand, the sequencer 13 continuously applies the voltage VSS to the select gate lines SGDL (illustrated as “non-selected SGDL” in FIG. 5) of non-selected string units SU. The sequencer 13 continuously applies the voltage VSS to the select gate line SGSL from time t1. From time t1, the sequencer 13 applies a voltage VCELSRC to the source line CELSRC, and applies a voltage VBL to a programmable bit line BL(p). From time t2, the sequencer 13 applies a voltage VSGD to the select gate line SGDL of the selected string unit SU. The voltage VSGD is lower than the voltage VSG and the voltage VBL, and has a magnitude sufficient to cause the selection gate transistor DT in a programmable string STRU (p) to be maintained in an ON state, and cause the selection gate transistor DT in a program inhibition string STR(pi) to be turned off. As a result of the voltage VSGD being applied, a channel of the program inhibition string STR(i) is disconnected from a corresponding program inhibition bit line BL(i), and thus electrically floats. From time t3, the sequencer 13 applies a voltage VPASS to all of the word lines WL. The voltage VPASS is low enough to prevent data from being erroneously written into the non-selected word lines WL in the programmable string STR(p), and is high enough to prevent a threshold voltage of the selected memory cell transistor MT connected to the selected word line WL from being increased in the program inhibition string STR(i). From time t4, the sequencer 13 applies a program voltage VPGM to the selected word line WL. The program voltage VPGM is higher than the voltage VPASS. As a result of the program voltage VPGM being applied, a great potential difference based on the program voltage VPGM and the voltage VSS is generated between the selected word line WL and the channel in the programmable string STR(p). As a result, electrons are injected into the charge storage layer of the selected memory cell transistor MT of the programmable string STR(p), and thus a threshold voltage of the selected memory cell transistor MT increases. On the other hand, from time t4, the sequencer 13 also continuously applies the voltage VPASS to the non-selected word lines WL. The voltage VPASS is sufficiently lower than the program voltage VPGM. Thus, also in the programmable string STR(p), a potential difference based on the voltage VPASS and the voltage VSS between the non-selected word line WL and the channel, is sufficiently smaller than a difference between the program voltage VPGM and the voltage VSS. Thus, a threshold voltage of the non-selected memory cell transistor MT of the programmable string STR(p) is nearly maintained without electrons being almost injected into the charge storage layer. The program inhibition string STR(i) electrically floats, and thus the channel thereof is coupled to the word line WL, so as to be increased in a voltage due to application of the program voltage VPGM and the voltage VPASS to the word line WL, and thus has a small potential difference with the word line WL. For that reason, electrons are scarcely injected into the charge storage layer of the selected memory cell transistor MT of the program inhibition string STR(i) even if the program voltage VPGM is applied. From time t5, the sequencer 13 changes voltages of the selected word line WL and the non-selected word lines WL back to the voltage VSS. From time t6, the sequencer 13 changes voltages of the program inhibition bit line BL(p), the select gate line SGDL of the selected string unit SU, and the source line CELSRC back to the voltage VSS, and finishes the programming. It is determined whether or not the selected memory cell transistor MT is increased to a threshold voltage corresponding to the desired state through verification after programming. In the above-described way, a program loop is repeatedly executed. A string STR including a memory cell transistor MT which has failed in verification in a certain program loop is also treated as a programmable string STR (p) in the next program loop. On the other hand, a string STR including a memory cell transistor MT which has passed verification in a certain program loop is treated as a program inhibition string STR(i) in the next program loop. Next, with reference to FIG. 6, a description will be made of first writing according to the first embodiment. FIG. 6 is a diagram illustrating a change in a threshold voltage distribution of the memory cell transistor MT according to first writing in the first embodiment. The semiconductor memory 1 receives data of a four-page size from the memory controller 2, and performs first writing. The data of a four-page size is written into a top, upper, middle, and lower pages of the selected cell unit CU, which are respectively referred to as top page data, upper page data, middle page data, and lower page data. The sequencer 13 performs the first writing of the top, upper, middle, and lower page data. The first writing indicates rough writing of increasing a threshold voltage of the memory cell transistor MT in an incomplete form on the basis of data to be written. The memory cell transistor MT before the first writing is performed is in the Er state. In the first writing, the sequencer 13 uses verification voltages VMA, VMB, VMC, VMD, VME, VMF, VMG, VMH, VMI, VMJ, VMK, VML, VMM, VMN, and VMO for verification. The verification voltages VMA, VMB, VMC, VMD, VME, VMF, VMG, VMH, VMI, VMJ, VMK, VML, VMM, VMN, and VMO are used to verify the memory cell transistor MT subjected to writing in the A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O states, respectively. In other words, for example, the verification voltage VMA is used for verification in the first writing on the memory cell transistor MT subjected to writing in the A state. When the memory cell transistor MT subjected to writing in the A state has a threshold voltage equal to or higher than the verification voltage VMA in the first writing, the memory cell transistor MT passes the verification in the first writing. This is the same for the other states. The verification voltages VMA, VMB, VMC, VMD, VME, VMF, VMG, VMH, VMI, VMJ, VMK, VML, VMM, VMN, and VMO have the following magnitudes. VMA<VA VMA<VMB<VB VMB<VMC<VC VMC<VMD<VD VMD<VME<VE VME<VMF<VF VMF<VMG<VG VMG<VMH<VH VMH<VMI<VI VMI<VMJ<VJ VMJ<VMK<VK VMK<VML<VL VML<VMM<VM VMM<VMN<VN VMN<VMO<VO According to the first writing, the memory cell transistor MT transitions to any one of MEr, MA, MB, MC, MD, ME, MF, MG, MH, MI, MJ, MK, ML, MM, MN, and MO states. The memory cell transistor MT subjected to writing in the A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O states is brought into the MA, MB, MC, MD, ME, MF, MG, MH, MI, MJ, MK, ML, MM, MN, and MO states, respectively, right after the first writing is completed. The memory cell transistor MT maintained in the Er state is maintained in the MEr state during the first writing. With reference to FIG. 7, a description will be made of second writing according to the first embodiment. FIG. 7 is a diagram illustrating a change in a threshold voltage distribution of the memory cell transistor MT according to second writing in the first embodiment. The semiconductor memory 1 receives, from the memory controller 2, data to be written into the selected cell unit CU, that is, the same top page data, upper page data, middle page data, and lower page data as those used in the first writing. The second writing is performed using the received top page data, upper page data, middle page data, and lower page data. The second writing refers to fine writing for completing writing by completing an increase of a threshold voltage of the memory cell transistor MT. In the second writing, the sequencer 13 uses verification voltages VVA, VVB, VVC, VVD, VVE, VVF, VVG, VVH, VVI, VVJ, VVK, VVL, VVM, VVN, and VVO. The verification voltages VVA, VVB, VVC, VVD, VVE, VVF, VVG, VVH, VVI, VVJ, VVK, VVL, VVM, VVN, and VVO are used to verify the memory cell transistor MT subjected to writing in the A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O states, respectively. In other words, for example, the verification voltage VVA is used for verification in the second writing on the memory cell transistor MT subjected to writing in the A state. When the memory cell transistor MT subjected to writing in the A state has a threshold voltage equal to or higher than the verification voltage VVA in the second writing, the memory cell transistor MT passes the verification in the second writing. This is also the same for the other states. The verification voltages VVA, VVB, VVC, VVD, VVE, VVF, VVG, VVH, VVI, VVJ, VVK, VVL, VVM, VVN, and VVO have the following magnitudes. VA<VVA<VVB VB<VVB<VVC VC<VVC<VVD VD<VVD<VVE VE<VVE<VVF VF<VVF<VVG VG<VVG<VVH VH<VVH<VVI VI<VVI<VVJ VJ<VVJ<VVK VK<VVK<VVL VL<VVL<VVM VM<VVM<VVN VN<VVN<VVO VO<VVO In one-step writing, a threshold voltage of the memory cell transistor MT transitions to a state on the lower part in FIG. 7 from a state on an upper part in FIG. 6 without passing through a state on the upper part in FIG. 7. One of purposes of two-step writing is to prevent a threshold voltage of the memory cell transistor MT of the cell unit CU in which data has been written from unintentionally transitioning to a state different from a desired state due to writing on the cell unit CU continuously adjacent thereto. In other words, in one-step writing, the memory cell transistor MT transitions to a desired state through writing performed once, and the greatest transition is transition from the Er state to the O state having a high threshold voltage. As illustrated in FIG. 8, when one-step writing is performed on a cell unit CU(i+1) after writing on a cell unit CUi (where i is 0 or a natural number) is performed, a threshold voltage of the memory cell transistor MT of the cell unit CUi may be unintentionally increased due to an increase of a threshold voltage of the memory cell transistor MT of the cell unit CU(i+1). This increase is significant enough to have the great influence on the cell unit CUi, that is, a disturbance is significant. As a result, there is concern that the memory cell transistor MT of the cell unit CUi may transition to a state different from an intended state. In two-step writing, as illustrated in FIG. 9, first writing is performed on the cell unit CUi, and then first writing is performed on the cell unit CU(i+1). In this case, a threshold voltage of the memory cell transistor MT of the cell unit CUi may be increased due to the first writing on the cell unit CU(i+1). However, thereafter, a threshold voltage of the memory cell transistor MT of the cell unit CU(i+1) is controlled to be brought into a desired state due to the second writing on the cell unit CU(i+1), and thus a disturbance caused by the first writing on the cell unit CU(i+1) is offset by the second writing. The second writing on the cell unit CU(i+1) may apply a disturbance to the cell unit CUi on which the second writing is completed. However, an increase of a threshold voltage due to the second writing is smaller than an increase of a threshold voltage due to the first writing, and thus does not exert the great influence on the cell unit CUi on which writing is completed. Therefore, the memory cell transistor MT of the cell unit CUi is prevented from transitioning unintentionally to another state from a state after writing is completed. With reference to FIG. 10, a description will be made of data writing according to the first embodiment. FIG. 10 is a table illustrating an order of data writing in a single certain block BLK in the first embodiment. The memory controller 2 instructs first writing and second writing to be performed on a selected cell unit CU as described below with reference to FIG. 10. The sequencer 13 performs the first writing and the second writing for which the instruction is given. A row including a notation with Y (where Y is 0 or a natural number) indicates information regarding a cell unit CUY. Columns including notations such as SU0, SU1, SU2, and SU3 respectively indicate information regarding the string units SU0, SU1, SU2, and SU3. A number in a cell at an intersection between a row and a column indicates an order of first writing (WT1) and second writing (WT2) being performed on a cell unit CU of a corresponding string unit SU of the cell. As illustrated in FIG. 10, first, the memory controller 2 performs writing on all of the cell units CU of the string unit SU0. In the string unit SU0, the memory controller 2 first performs first writing on the cell unit CU0 having the minimum address (ID, for example). Next, first writing is second performed on the cell unit CU1 having an ID which is greater by one, and then second writing is performed on the cell unit CU0. Thereafter, writing is performed in an increasing order of IDs of the cell units CU in the same order. In other words, a set of first writing on the cell unit CU(i+1) and second writing on the cell unit CUi is repeatedly performed and i is incremented by 1 each time. Specifically, first writing is performed on the cell unit CU2, and then second writing is performed on the cell unit CU1. The same applies hereinafter. With respect to each cell unit CU, when second writing on the cell unit CU is completed, the memory controller 2 may discard data with the four-page size written in the cell unit CU. In other words, the region of the RAM 23 in which the four-page size data which is a second writing target may be cleared. After writing on the string unit SU0 is completed, the memory controller 2 performs the same writing as in the string unit SU0 on the string units SU1, SU2, and SU3 in this order. The writing may not be performed in an increasing order of the IDs of the string units SU. For example, the writing may be performed in a decreasing order of the IDs of the string units SU, and may be simpsonjohn@example.org. FIG. 11 illustrates write data stored in the RAM 23 of the memory controller 2 during writing according to the first embodiment. Each cell in FIG. 11 indicates a region storing data with a page size. The memory controller 2 is required to store four-page data to be written into each cell unit CU until second writing on the cell unit CU is finished. As illustrated in FIG. 11, a maximum size of data required to be stored is a size of a total of eight pages for two cell units CU during the writing described with reference to FIG. 10 or the like. In other words, data with the four-page size to be written into the cell unit CU1 and data with the four-page size to be written into the cell unit CU0 are required to be stored in preparation for uncompleted second writing which is third performed on the cell unit CU0, during first writing which is second performed on the cell unit CU1 in FIG. 10. When second writing which is third performed on the cell unit CU0 is completed, write data for the cell unit CU0 is not necessary, and, instead, the memory controller 2 is required to store four-page size data for first writing on the cell unit CU2. As mentioned above, write data for the cell unit CUi, and write data for the cell unit CU(i−1) for second writing on the subsequent cell unit CU(i−1) are required to be stored, during first writing on the cell unit CUi. Write data for the cell unit CUi and write data for the subsequent cell unit CU(i+1) are required to be stored during second writing on the cell unit CUi. Therefore, a size of data required to be stored in any stage is a size of eight pages. 1.3 Effect According to the first embodiment, as will be described below, a size of data stored in the RAM 23 of the memory controller 2 during writing of data into the semiconductor memory 1 can be reduced compared with a case illustrated in FIG. 13. In the memory system 5 of the first embodiment, to improve write performance, two-step writing may be performed in an order as illustrated in FIG. 12. FIG. 12 illustrates an order of data writing in a reference example in the same form as that in FIG. 10. As illustrated in FIG. 12, in respective cases where k (where k is 0 or a natural number) is 0 to 3, a set of first writing on the cell unit CUi of a string unit SUk in an increasing order of k, a set of first writing on the cell unit CU(i+1) of the string unit SUk in an increasing order of k, and a set of second writing on the cell unit CUi of the string unit SUk in an increasing order of k are performed. The set of first writing on the cell unit CUi of the string unit SUk in the increasing order of k, the set of first writing on the cell unit CU(i+1) of the string unit SUk in the increasing order of k, and the set of second writing on the cell unit CUi of the string unit SUk in the increasing order of k are repeatedly performed while i is incremented by 1. In the writing method illustrated in FIG. 12, four-page data for each of two cell units CUi and CU(i+1) of each of the string units SU0 to SU3 is required to be stored in the memory controller 2 during writing as illustrated in FIG. 13. In other words, data of 16 pages=the number of string units (=4)×the number of cell units (=2)×the number of pages (=2) is required to be stored. This requires the memory controller 2 to have the RAM 23 with a considerably large capacity. A large amount of page data is required to be stored, and thus a large emergency power source is required to be provided. When the supply of power from the host apparatus 3 is suddenly stopped, the memory controller 2 is required to write data to be written on the RAM 23 into the semiconductor memory 1. To do so, the memory controller 2 has an emergency power source, and uses the emergency power source to write the data to be written on the RAM 23 into
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