Title of Invention: SOLID-STATE IMAGE PICKUP DEVICE AND METHOD OF MANUFACTURING SAME Abstract: A solid-state image pickup device including: a photoelectric conversion section configured to convert incident light into a signal charge; a transfer transistor configured to read the signal charge from the photoelectric conversion section and transfer the signal charge; and an amplifying transistor configured to amplify the signal charge read by the transfer transistor, wherein a compressive stress film having a compressive stress is formed on the amplifying transistor. Detailed Description: RELATED APPLICATION DATA This application is a continuation of U.S. patent application Ser. No. 13/335,030 filed Dec. 22, 2011, which is a division of U.S. patent application Ser. No. 12/372,857, filed Feb. 18, 2009, now U.S. Pat. No. 8,120,684 issued on Feb. 21, 2012, the entirety of which is incorporated herein by reference to the extent permitted by law. The present application claims the benefit of priority to Japanese Patent Application No. JP 2008-054560 filed in the Japan Patent Office on Mar. 5, 2008, the entirety of which is incorporated by reference herein to the extent permitted by law. BACKGROUND OF THE INVENTION The present invention relates to a solid-state image pickup device and a method of manufacturing the same. With recent increase in degree of integration of semiconductor elements, solid-state image pickup devices have also been increased in the number of pixels and advanced in miniaturization. On the other hand, characteristic degradation attendant thereon is becoming a great problem. For example, an SN ratio is important for the improvement of image quality. Specifically, as the miniaturization progresses, a decrease of photons that can be taken in due to the miniaturization of a photodiode (PD) as a photoelectric conversion element inevitably reduces a signal quantity. It is thus necessary to improve the SN ratio by reducing noise. In CMOS (Complementary Metal Oxide Semiconductor) image sensors, in particular, as shown in FIG. 14, a charge obtained by photoelectric conversion in a photodiode 221 is accumulated in a floating diffusion 226 via a transfer transistor 222 and thereafter subjected to signal amplification in an amplifying transistor 224 in many cases. A noise proportional to a frequency generated in the amplifying transistor 224, or 1/f noise, is dominant as random noise of a pixel, and it is important to suppress the noise. In general, the following relation holds for the 1/f noise. in2=KF((IdAF)/(CoxWLefffEF)) (1) where in2 is drain current noise density [A2/Hz], KF (flicker noise coefficient) is a factor dependent on the element, Id is a drain current, Cox is a gate capacitance per unit area, and Leff is an effective gate length. This is disclosed in IEEE Transaction on Electron Devices, Vol. 48, No. 5, May 2001, pp. 921 to 927. According to the above Equation (1), a reduction of line width of the amplifying transistor 224, that is, miniaturization of the amplifying transistor 224 sharply increases the noise. KF is a factor dependent on the amplifying transistor 224, and is greatly affected by process factors. One of the process factors is a stress applied to a channel part of the amplifying transistor 224. For higher speed and lower power consumption of a minute pixel, reducing gate wiring resistance and contact resistance by applying silicide to transistors within a pixel region is a very effective means, and the amplifying transistor 224 is no exception. Generally, silicide techniques have been introduced to a generation of 0.25 μm or later in CMOS logic. While a pixel region in a CMOS image sensor is highly likely to operate as a device as long as ohmic characteristics are maintained, techniques for reducing resistance such as salicide formation or the like become necessary with a reduction of a contact diameter. However, a local tensile stress occurs in a channel part of a fine amplifying transistor where salicide is formed. In addition, a correlation is found between stress and 1/f noise. The application of tensile stress increases the 1/f noise regardless of whether a carrier species is electrons or holes, or in both cases of an N-MOS and a P-MOS (see Authored by T. Ohguro, Y. Okayama, K. Matsuzawa, K. Matsunaga, N. Aoki, K. Kojima, H. S. Momose, and K. Ishimaru, “The impact of oxynitride process, deuterium annealing and STI stress to 1/f noise of 0.11 CMOS” 2003 Symposium on VLSI Technology Digest of Technical Papers, 2003, p. 37 and Authored by Shigenobu Maeda, You-Seung Jin, Jung-A Choi, Sun-Young Oh, Hyun-Woo Lee, Jae-Yoon Yoo, Min-Chul Sun, Ja-Hum Ku, Kwon Lee, Su-Gon Bae, Sung-Gun Kang, Jeong-Hwan Yang, Young-Wug Kim, and Kwang-Pyuk Suh, “Impact of Mechanical Stress Engineering on Flicker Noise Characteristics” 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 102 to 103, for example). For the above-described reasons, when pixels are miniaturized and salicide is introduced into the pixels, it is difficult to tolerate noise degradation when a high SN ratio is to be achieved. A process of manufacturing a CMOS image sensor in related art will next be described with reference to FIGS. 15A to 15E. As shown in FIG. 15A, a P-type well region 212 is formed in an N-type silicon substrate 211. Next, a photodiode 221 for performing photoelectric conversion is formed at a predetermined position on the surface side of the silicon substrate 211. The photodiode 221 is formed by a P-type region, an N-type region, and a P-type region from a bottom layer by performing ion implantation of phosphorus (P) as an N-type impurity and boron (B) as a P-type impurity using an ion implantation mask formed by patterning a resist film formed on the silicon substrate 211. The energy of the ion implantation is adjusted such that the photodiode 221 is desirably formed between the surface of the semiconductor substrate 211 and a depth of 5 μm to 15 μm for visible light, and is for example formed between the surface of the semiconductor substrate 211 and a depth of about 5 μm. As described above, an N-type substrate is used as the silicon substrate 211, and therefore isolation of the photodiode 221 is performed by the P-type well region 212. Next, MOS type transistors within a pixel are formed. As shown in FIG. 15B, a gate insulating film 231 is formed on the silicon substrate 211, and then a polysilicon film for forming gate electrodes is formed. Next, a resist mask (not shown) to serve as an etching mask for forming the gate electrodes is formed on the polysilicon film. With the resist mask used as etching mask, the polysilicon film is patterned, whereby the gate electrodes 232 of a transfer transistor, a reset transistor, an amplifying transistor, and a selecting transistor are formed by polysilicon. Next, as shown in FIG. 15C, side walls 233 are formed on the side part of each of the gate electrodes 232 for a purpose of suppressing a short channel effect of a MOS transistor (not shown) of a peripheral circuit, the reset transistor, the amplifying transistor, the selecting transistor, and the like. The side walls 233 are formed by a silicon oxide film, for example. However, the side walls 233 can be formed by a silicon nitride film. Next, a resist mask (not shown) is formed, and diffusion layers 234, 235, 236, and 237 serving as sources and drains of the transistors are formed in the semiconductor substrate 211 by ion implantation using the resist mask. In general, when holes and electrons are compared with each other as carriers, holes are more easily trapped on the gate insulating film 231 and the interface. Thus, this time, electrons are selected as carriers, that is, N-MOS is formed. A floating diffusion 226 is also formed at the same time by the ion implantation. Next, as shown in FIG. 15D, silicide layers 241 to 249 are formed on the diffusion layers 234 to 237, on the floating diffusion 226, and on the gate electrodes 232, respectively, by a salicide process. Prior to the salicide process, because silicide layers have low optical transparency, a silicide blocking film 251 is formed on the photodiode 221 to prevent the formation of a silicide layer on the photodiode 221. The silicide blocking film 251 is desirably formed by a silicon oxide film, a silicon nitride film, a silicon oxynitride film or the like. A titanium silicide, a tantalum silicide, a molybdenum silicide, a nickel silicide, a tungsten silicide, a nickel-platinum silicide or the like can be applied as the silicide layers 241 to 249. Next, as shown in FIG. 15E, an etching stopper film 252 for temporarily stopping etching at a time of contact processing is formed on an entire surface over the silicon substrate 211. The etching stopper film 252 is formed by a silicon nitride film, a silicon oxynitride film or the like that makes it easy to secure a selective etching ratio with respect to a silicon oxide film as an interlayer insulating film to be formed later. Thereafter, though not shown, an interlayer insulating film is formed, and a contact part is formed using tungsten. Further, a wiring layer, an interlayer insulating film, a planarizing insulating film, a color filter layer, and a microchip lens, and the like are formed, whereby the CMOS image sensor is completed. However, in the above-described CMOS image sensor, variations in 1/f noise increase significantly due not only to a finer design rule of the amplifying transistor (AMP) but also to the load of tensile stress on the channel part by the silicide layers 243 and 244 of the amplifying transistor 224. As a result, the SN ratio is lowered, and it is difficult to obtain sufficient image quality. SUMMARY OF THE INVENTION A problem to be solved is that when a silicide layer is introduced into a transistor within a pixel or the like to miniaturize the pixel, variations in 1/f noise increase significantly due to the load of tensile stress on the channel part of the transistor by the silicide layer, so that the SN ratio is lowered and thus sufficient image quality cannot be obtained. The present invention makes it possible to prevent the lowering of the SN ratio by suppressing increase in variation in 1/f noise and thus obtain sufficient image quality even when a silicide layer is introduced into a transistor to miniaturize the pixel. According to an embodiment of the present invention, there is provided a solid-state image pickup device including: a photoelectric conversion section configured to convert incident light into a signal charge; a transfer transistor configured to read the signal charge from the photoelectric conversion section and transfer the signal charge; and an amplifying transistor configured to amplify the signal charge read by the transfer transistor, wherein a compressive stress film for applying a compressive stress to a channel part of the amplifying transistor is formed on the amplifying transistor. In the solid-state image pickup device according to the above-described embodiment of the present invention, the compressive stress film is formed on the amplifying transistor. Therefore, a local tensile stress applied to a channel region of the amplifying transistor is relieved by the compressive stress of the compressive stress film, so that an increase in variation in 1/f noise of the amplifying transistor can be suppressed. According to an embodiment of the present invention, there is provided a method of manufacturing a solid-state image pickup device, the solid-state image pickup device including, in a semiconductor substrate, a photoelectric conversion section configured to convert incident light into a signal charge, a transfer transistor configured to read the signal charge from the photoelectric conversion section and transfer the signal charge, and an amplifying transistor configured to amplify the signal charge read by the transfer transistor. The method includes the steps of: forming, after forming the amplifying transistor in the semiconductor substrate, an insulating film on the semiconductor substrate, the insulating film having an opening part on the amplifying transistor; forming a compressive stress film covering the amplifying transistor and having a compressive stress on the insulating film; and leaving the compressive stress film only on the amplifying transistor and removing the compressive stress film on other regions. In the method of manufacturing the solid-state image pickup device according to the above-described embodiment of the present invention, the compressive stress film is formed on the amplifying transistor. Therefore, a local tensile stress applied to a channel region of the amplifying transistor is relieved by the compressive stress of the compressive stress film, so that an increase in variation in 1/f noise of the amplifying transistor can be suppressed. According to an embodiment of the present invention, there is provided a method of manufacturing a solid-state image pickup device, the solid-state image pickup device including, in a semiconductor substrate, a photoelectric conversion section configured to convert incident light into a signal charge, a transfer transistor configured to read the signal charge from the photoelectric conversion section and transfer the signal charge, and an amplifying transistor configured to amplify the signal charge read by the transfer transistor. The method includes the steps of: forming, after forming the amplifying transistor in the semiconductor substrate, a compressive stress film covering the amplifying transistor and having a compressive stress on the semiconductor substrate; and leaving the compressive stress film only on the amplifying transistor and removing the compressive stress film on regions other than on the amplifying transistor. In the method of manufacturing the solid-state image pickup device according to the above-described embodiment of the present invention, the compressive stress film is formed on the amplifying transistor. Therefore, a local tensile stress applied to a channel region of the amplifying transistor is relieved by the compressive stress of the compressive stress film, so that an increase in variation in 1/f noise of the amplifying transistor can be suppressed. A solid-state image pickup device according to an embodiment of the present invention can suppress an increase in variation in 1/f noise of the amplifying transistor. Thus, because the lowering of the SN ratio can be suppressed, there is an advantage of being able to obtain excellent image quality by achieving a high SN ratio. A method of manufacturing a solid-state image pickup device according to an embodiment of the present invention can suppress an increase in variation in 1/f noise of the amplifying transistor. Thus, because the lowering of the SN ratio can be suppressed, there is an advantage of being able to obtain excellent image quality by achieving a high SN ratio. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration sectional view of an embodiment (first embodiment) of a solid-state image pickup device according to the present invention; FIG. 2 is a circuit configuration diagram of an embodiment (first embodiment) of a solid-state image pickup device according to the present invention; FIG. 3 is a circuit configuration diagram showing another circuit configuration in the first embodiment of the solid-state image pickup device; FIG. 4 is a schematic configuration sectional view of an embodiment (second embodiment) of a solid-state image pickup device according to the present invention; FIG. 5 is a schematic configuration sectional view of an embodiment (third embodiment) of a solid-state image pickup device according to the present invention; FIG. 6 is a schematic configuration sectional view of an embodiment (fourth embodiment) of a solid-state image pickup device according to the present invention; FIGS. 7A to 7I are manufacturing process sectional views of an embodiment (first embodiment) of a method of manufacturing a solid-state image pickup device according to the present invention; FIGS. 8A and 8B are manufacturing process sectional views of an embodiment (second embodiment) of a method of manufacturing a solid-state image pickup device according to the present invention; FIG. 9 is a manufacturing process sectional view of an embodiment (third embodiment) of a method of manufacturing a solid-state image pickup device according to the present invention; FIG. 10 is a manufacturing process sectional view of an embodiment (fourth embodiment) of a method of manufacturing a solid-state image pickup device according to the present invention; FIG. 11 is a manufacturing process sectional view of an embodiment (fifth embodiment) of a method of manufacturing a solid-state image pickup device according to the present invention; FIGS. 12A to 12E are manufacturing process sectional views of an embodiment (sixth embodiment) of a method of manufacturing a solid-state image pickup device according to the present invention; FIG. 13 is a schematic perspective sectional view of a CMOS image sensor of a back-surface irradiation type; FIG. 14 is a schematic configuration sectional view of an example of a solid-state image pickup device in related art; and FIG. 15A to 15E are manufacturing process sectional views of an example of a method of manufacturing the solid-state image pickup device in related art. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment (first embodiment) of a solid-state image pickup device according to the present invention will be described with reference to a schematic configuration sectional view of FIG. 1 and a circuit configuration diagram of FIG. 2. The solid-state image pickup device is a CMOS image sensor. FIG. 1 shows a sensor section of a pixel section of the CMOS image sensor and a group of transistors within the pixel. FIG. 2 shows an example of a circuit configuration of the CMOS image sensor. Description will be made below with reference to FIG. 1 and FIG. 2. A semiconductor substrate 11 of a first conduction type has a well region 12 of a second conduction type formed therein, the second conduction type being an opposite conduction type from the first conduction type. Description in the following will be made supposing that, as an example, the first conduction type is an N-type and the second conduction type is a P-type. For example an N-type silicon substrate is used as the above-described semiconductor substrate 11. A photoelectric conversion section (for example a photodiode (PD)) 21 for converting incident light into a signal charge is formed at a predetermined position on the surface side of the semiconductor substrate 11. The photoelectric conversion section 21 will hereinafter be described as photodiode 21. The photodiode 21 is for example formed by a P-type region, an N-type region, and a P-type region from a bottom layer in the semiconductor substrate 11. The photodiode 21 is desirably formed between the surface of the semiconductor substrate 11 and a depth of 5 μm to 15 μm for visible light, and is for example formed between the surface of the semiconductor substrate 11 and a depth of about 5 μm. As described above, an N-type silicon substrate is used as the semiconductor substrate 11, and therefore element isolation for the photodiode 21 is performed by the well region 12. MOS type transistors within the pixel are formed on the semiconductor substrate 11. Gate electrodes 32 are formed on the semiconductor substrate 11 with a gate insulating film 31 interposed between the gate electrodes 32 and the semiconductor substrate 11. These gate electrodes 32 are the gate electrode 32 (32R) of a reset transistor of the pixel transistor group, the gate electrode 32 (32A) of an amplifying transistor of the pixel transistor group, and the gate electrode 32 (32S) of a selecting transistor of the pixel transistor group. Each of the gate electrodes 32 is formed by polysilicon, for example. In addition, the gate electrode 32 (32T) of a transfer transistor for reading the signal charge from the photodiode 21 and transferring the signal charge is formed adjoining the photodiode 21. Incidentally, each gate electrode 32 has very fine dimensions of 0.1 μm×0.1 μm, for example. Side walls 33 are formed on the side part of each of the gate electrodes 32. The side walls 33 are formed by a silicon oxide film, for example. Alternatively, the side walls 33 may be formed by a silicon nitride film. Diffusion layers 34, 35, 36, and 37 serving as sources and drains of the transistors are formed in the semiconductor substrate 11 on both sides of the respective gate electrodes 32. In this case, as an example, the diffusion layer 35 is shared as one diffusion layer 35 of the reset transistor 23 and one diffusion layer 35 of the amplifying transistor 24, and the diffusion layer 36 is shared as another diffusion layer 36 of the amplifying transistor 24 and one diffusion layer 36 of the selecting transistor 25. A floating diffusion (FD) 26 is also formed in the semiconductor substrate 11. In general, when holes and electrons are compared with each other as carriers, holes are more easily trapped on the gate insulating film 31 and the interface. Thus, in this case, electrons are selected as carriers, that is, NMOS transistors are formed. Silicide layers 41 to 44, 45, and 46 to 49 are formed on the diffusion layers 34 to 37, on the floating diffusion 26, and on the gate electrodes 32, respectively. In addition, a silicide blocking film 51 is formed on the photodiode 21 to prevent the formation of a silicide layer as described above on the photodiode 21. The silicide blocking film 51 is desirably formed by a silicon oxide film, a silicon nitride film, a silicon oxynitride film or the like. A titanium silicide, a tantalum silicide, a molybdenum silicide, a nickel silicide, a tungsten silicide, a nickel-platinum silicide or the like can be applied as the silicide layers 41 to 49. The transfer transistor 22 is connected between the cathode electrode of the photodiode 21 and the floating diffusion 26 as a charge-voltage converting section. The transfer transistor 22 transfers the signal charge (electrons in this case) stored in the photodiode 21 as a result of photoelectric conversion by the photodiode 21 to the floating diffusion 26 when a transfer pulse TRG is supplied to the gate electrode (control electrode) 32TG. The reset transistor 23 has a drain electrode (diffusion layer 35) connected to a reset line, and has a source electrode (diffusion layer 34) connected to the floating diffusion 26. When a reset pulse RST is supplied to the gate electrode 32R prior to the transfer of the signal charge from the photodiode 21 to the floating diffusion 26, the reset transistor 23 resets the potential of the floating diffusion 26 to a reset voltage Vrst. The amplifying transistor 24 has the gate electrode 32A connected to the floating diffusion 26, and has a drain electrode (common diffusion layer 35) connected to a pixel power supply Vdd. The amplifying transistor 24 outputs the potential of the floating diffusion 26 after being reset by the reset transistor 23 as a reset level, and outputs the potential of the floating diffusion 26 after the transfer transistor 22 transfers the signal charge as a signal level. The selecting transistor 25 for example has a drain electrode (diffusion layer 36) connected to the source electrode (common diffusion layer 36) of the amplifying transistor 24, and has a source electrode connected to an output signal line. When a selecting pulse SEL is supplied to the gate electrode 32S, the selecting transistor 25 is set in an on state, and outputs a signal output from the amplifying transistor 24 with the pixel in a selected state to the output signal line (wiring 75). Incidentally, the selecting transistor 25 can also be connected between the pixel power supply Vdd and the drain electrode of the amplifying transistor 24. An etching stopper film 52 having an opening 53 formed on the amplifying transistor 24 is formed on an entire surface over the semiconductor substrate 11. The etching stopper film 52 is formed by a silicon nitride film, a silicon oxynitride film or the like that makes it easy to secure a selective etching ratio with respect to a silicon oxide film as an interlayer insulating film to be formed later. On the other hand, a compressive stress film 54 having a compressive stress is formed on the amplifying transistor 24 so as to cover the amplifying transistor 24. This compressive stress film 54 is formed by a silicon oxide film, for example. The etching stopper film 52 and the compressive stress film 54 are desirably of different film species because different film species make it easy to secure a processing (etching) selectivity. For example, as described above, the etching stopper film 52 is formed by a silicon nitride film, and the compressive stress film 54 is formed by a silicon oxide film. Of course, it may be vice versa, or two species of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film can be selected and used. When the etching stopper film 52 and the compressive stress film 54 are of a same species, a structure having an intermediate film of a different species inserted between the etching stopper film 52 and the compressive stress film 54 is desirable. Though not shown, for example, when a silicon nitride film is applied as the etching stopper film 52, a silicon oxide film is applied as the intermediate film. Further formed are for example wiring 71 for connecting the transfer transistor electrode 32T and a driving circuit (not shown) to each other, wiring 72 for connecting the gate electrode 32R of the reset transistor 23 and the driving circuit (not shown) to each other, wiring 73 for connecting the gate electrode 32A of the amplifying transistor 24 and the floating diffusion 26 to each other, wiring 74 for connecting the gate electrode 32S of the selecting transistor 25 and the driving circuit (not shown) to each other, wiring 75 for connecting the diffusion layer 37 of the selecting transistor 25 and a horizontal scanning circuit (output) (not shown) to each other, wiring 76 for connecting the diffusion layer 35 shared between the reset transistor 23 and the amplifying transistor 24 and the pixel power supply Vdd (not shown) to each other, and the like. In the solid-state image pickup device 1 according to the present embodiment, the compressive stress film 54 having a compressive stress is formed on the amplifying transistor 24. Therefore, a local tensile stress applied to a channel region of the amplifying transistor 24 which stress is caused by the silicide layers 42 and 43 formed on the diffusion layers 35 and 36 of the amplifying transistor 24 is relieved by the compressive stress of the compressive stress film 54, so that an increase in variation in 1/f noise of the amplifying transistor 24 can be suppressed. Thus, because lowering of an SN ratio can be suppressed, there is an advantage of being able to obtain excellent image quality by achieving a high SN ratio. The circuit configuration of a pixel transistor section shown by FIG. 2 may be formed as shown in FIG. 3. As shown in FIG. 3, a photodiode 21 is provided, and a transfer transistor 22 is provided so as to be connected to the photodiode 21. The transfer transistor 22 is connected between the cathode electrode of the photodiode 21 and a floating diffusion 26 as a charge-voltage converting section. The transfer transistor 22 transfers a signal charge (electrons in this case) stored in the photodiode 21 as a result of photoelectric conversion by the photodiode 21 to the floating diffusion 26 when a transfer pulse TRG is supplied to the gate electrode (control electrode) 32TG. A reset transistor 23 has a drain electrode (diffusion layer 35) connected to a pixel power supply Vdd, and has a source electrode (diffusion layer 34) connected to the floating diffusion 26. When a reset pulse RST is supplied to the gate electrode 32R prior to the transfer of the signal charge from the photodiode 21 to the floating diffusion 26, the reset transistor 23 resets the potential of the floating diffusion 26 to a reset voltage Vrst. An amplifying transistor 24 has a gate electrode 32A connected to the floating diffusion 26. The amplifying transistor 24 outputs the potential of the floating diffusion 26 after being reset by the reset transistor 23 as a reset level, and outputs the potential of the floating diffusion 26 after the transfer transistor 22 transfers the signal charge as a signal level. A selecting transistor 25 for example has a drain electrode (diffusion layer 36) connected to the source electrode (common diffusion layer 36) of the amplifying transistor 24, and has a source electrode connected to an output signal line. When a selecting pulse SEL is supplied to the gate electrode 32S, the selecting transistor 25 is set in an on state, and outputs a signal output from the amplifying transistor 24 with the pixel in a selected state to the output signal line (wiring 75). An example in which a compressive stress film is formed without an etching stopper film being formed will next be described as an embodiment (second embodiment) of a solid-state image pickup device according to the present invention with reference to a schematic configuration sectional view of FIG. 4. In the foregoing first embodiment, the etching stopper film is formed to prevent excessive etching into the diffusion layers when a contact is formed. When the etching stopper film is not required, a compressive stress film is formed without the etching stopper film being formed. A solid-state image pickup device in this case (second embodiment) will be described in the following. As shown in FIG. 4, a semiconductor substrate 11 of a first conduction type has a well region 12 of a second conduction type formed therein, the second conduction type being an opposite conduction type from the first conduction type. Description in the following will be made supposing that, as an example, the first conduction type is an N-type and the second conduction type is a P-type. For example an N-type silicon substrate is used as the above-described semiconductor substrate 11. A photoelectric conversion section (for example a photodiode (PD)) 21 for converting incident light into a signal charge is formed at a predetermined position on the surface side of the semiconductor substrate 11. The photodiode 21 is for example formed by a P-type region, an N-type region, and a P-type region from a bottom layer in the semiconductor substrate 11. The photodiode 21 is desirably formed between the surface of the semiconductor substrate 11 and a depth of 5 μm to 15 μm for visible light, and is for example formed between the surface of the semiconductor substrate 11 and a depth of about 5 μm. As described above, an N-type silicon substrate is used as the semiconductor substrate 11, and therefore element isolation for the photodiode 21 is performed by the well region 12. MOS type transistors within the pixel are formed on the semiconductor substrate 11. Gate electrodes 32 are formed on the semiconductor substrate 11 with a gate insulating film 31 interposed between the gate electrodes 32 and the semiconductor substrate 11. These gate electrodes 32 are the gate electrode 32 (32R) of a reset transistor of the pixel transistor group, the gate electrode 32 (32A) of an amplifying transistor of the pixel transistor group, and the gate electrode 32 (32S) of a selecting transistor of the pixel transistor group. Each of the gate electrodes 32 is formed by polysilicon, for example. In addition, the gate electrode 32 (32T) of a transfer transistor for reading the signal charge from the photodiode 21 and transferring the signal charge is formed adjoining the photodiode 21. Incidentally, each gate electrode 32 has very fine dimensions of 0.1 μm×0.1 μm, for example. Side walls 33 are formed on the side part of each of the gate electrodes 32. The side walls 33 are formed by a silicon oxide film, for example. Alternatively, the side walls 33 may be formed by a silicon nitride film. Diffusion layers 34, 35, 36, and 37 serving as sources and drains of the transistors are formed in the semiconductor substrate 11 on both sides of the respective gate electrodes 32. In this case, as an example, the diffusion layer 35 is shared as one diffusion layer 35 of the reset transistor 23 and one diffusion layer 35 of the amplifying transistor 24, and the diffusion layer 36 is shared as another diffusion layer 36 of the amplifying transistor 24 and one diffusion layer 36 of the selecting transistor 25. A floating diffusion (FD) 26 is also formed in the semiconductor substrate 11. In general, when holes and electrons are compared with each other as carriers, holes are more easily trapped on the gate insulating film 31 and the interface. Thus, in this case, electrons are selected as carriers, that is, NMOS transistors are formed. Silicide layers 41 to 44, 45, and 46 to 49 are formed on the diffusion layers 34 to 37, on the floating diffusion 26, and on the gate electrodes 32, respectively. In addition, a silicide blocking film 51 is formed on the photodiode 21 to prevent the formation of a silicide layer as described above on the photodiode 21. The silicide blocking film 51 is desirably formed by a silicon oxide film, a silicon nitride film, a silicon oxynitride film or the like. A titanium silicide, a tantalum silicide, a molybdenum silicide, a nickel silicide, a tungsten silicide, a nickel-platinum silicide or the like can be applied as the silicide layers 41 to 49. The transfer transistor 22 is connected between the cathode electrode of the photodiode 21 and the floating diffusion 26 as a charge-voltage converting section. The transfer transistor 22 transfers the signal charge (electrons in this case) stored in the photodiode 21 as a result of photoelectric conversion by the photodiode 21 to the floating diffusion 26 when a transfer pulse TRG is supplied to the gate electrode (control electrode) 32T. The reset transistor 23 has a drain electrode (diffusion layer 35) connected to a reset line, and has a source electrode (diffusion layer 34) connected to the floating diffusion 26. When a reset pulse RST is supplied to the gate electrode 32R prior to the transfer of the signal charge from the photodiode 21 to the floating diffusion 26, the reset transistor 23 resets the potential of the floating diffusion 26 to a reset voltage Vrst. The amplifying transistor 24 has the gate electrode 32A connected to the floating diffusion 26, and has a drain electrode (common diffusion layer 35) connected to a pixel power supply Vdd. The amplifying transistor 24 outputs the potential of the floating diffusion 26 after being reset by the reset transistor 23 as a reset level, and outputs the potential of the floating diffusion 26 after the transfer transistor 22 transfers the signal charge as a signal level. The selecting transistor 25 for example has a drain electrode (diffusion layer 36) connected to the source electrode (common diffusion layer 36) of the amplifying transistor 24, and has a source electrode connected to an output signal line. When a selecting pulse SEL is supplied to the gate electrode 32S, the selecting transistor 25 is set in an on state, and outputs a signal output from the amplifying transistor 24 with the pixel in a selected state to the output signal line (wiring 75). Incidentally, the selecting transistor 25 can also be connected between the pixel power supply Vdd and the drain electrode of the amplifying transistor 24. A compressive stress film 54 having a compressive stress is formed on the amplifying transistor 24 so as to cover the amplifying transistor 24. This compressive stress film 54 is formed by a silicon nitride film or a silicon oxide film, for example. Further formed are for example wiring 71 for connecting the gate electrode 32T of the transfer transistor 22 and a driving circuit (not shown) to each other, wiring 72 for connecting the gate electrode 32R of the reset transistor 23 and the driving circuit (not shown) to each other, wiring 73 for connecting the gate electrode 32A of the amplifying transistor 24 and the floating diffusion 26 to each other, wiring 74 for connecting the gate electrode 32S of the selecting transistor 25 and the driving circuit (not shown) to each other, wiring 75 for connecting the diffusion layer 37 of the selecting transistor 25 and a horizontal scanning circuit (output) (not shown) to each other, wiring 76 for connecting the diffusion layer 35 shared between the reset transistor 23 and the amplifying transistor 24 and the pixel power supply Vdd (not shown) to each other, and the like. In the solid-state image pickup device 2 according to the present embodiment, the compressive stress film 54 having a compressive stress is formed on the amplifying transistor 24. Therefore, a local tensile stress applied to a channel region of the amplifying transistor 24 which stress is caused by the silicide layers 42 and 43 formed on the diffusion layers 35 and 36 of the amplifying transistor 24 is relieved by the compressive stress of the compressive stress film 54, so that an increase in variation in 1/f noise of the amplifying transistor 24 can be suppressed. Thus, because lowering of an SN ratio can be suppressed, there is an advantage of being able to obtain excellent image quality by achieving a high SN ratio. In addition, because the etching stopper film as in the first embodiment is not formed, there is an advantage of being able to reduce each of the numbers of film formation steps, lithography steps, and etching steps, for example, by one as compared with the solid-state image pickup device 1 according to the first embodiment. An example having an element isolation region of a shallow trench element isolation structure made by forming an insulator within a groove, the element isolation region being adjacent to a diffusion layer of an amplifying transistor, will next be described as an embodiment (third embodiment) of a solid-state image pickup device 3 according to the present invention with reference to a schematic configuration sectional view of FIG. 5. As shown in FIG. 5, a semiconductor substrate 11 of a first conduction type has a well region 12 of a second conduction type formed therein, the second conduction type being an opposite conduction type from the first conduction type. Description in the following will be made supposing that, as an example, the first conduction type is an N-type and the second conduction type is a P-type. For example an N-type silicon substrate is used as the above-described semiconductor substrate 11. An element isolation region 96 of an STI (Shallow Trench Isolation) structure is formed which separates regions for forming pixel transistors such as a region for forming a reset transistor, a region for forming an amplifying transistor, a region for forming a selecting transistor, and the like formed in the semiconductor substrate 11. A photoelectric conversion section (for example a photodiode (PD)) 21 for converting incident light into a signal charge is formed at a predetermined position on the surface side of the semiconductor substrate 11. The photodiode 21 is for example formed by a P-type region, an N-type region, and a P-type region from a bottom layer in the semiconductor substrate 11. The photodiode 21 is desirably formed between the surface of the semiconductor substrate 11 and a depth of 5 μm to 15 μm for visible light, and is for example formed between the surface of the semiconductor substrate 11 and a depth of about 5 μm. As described above, an N-type silicon substrate is used as the semiconductor substrate 11, and therefore element isolation for the photodiode 21 is performed by the well region 12. MOS type transistors within the pixel are formed on the semiconductor substrate 11. Gate electrodes 32 are formed on the semiconductor substrate 11 with a gate insulating film 31 interposed between the gate electrodes 32 and the semiconductor substrate 11. These gate electrodes 32 are the gate electrode 32 (32R) of the reset transistor of the pixel transistor group, the gate electrode 32 (32S) of the selecting transistor of the pixel transistor group, and the gate electrode 32 (32A) of the amplifying transistor of the pixel transistor group. Each of the gate electrodes 32 is formed by polysilicon, for example. In addition, the gate electrode 32 (32T) of a transfer transistor for reading the signal charge from the photodiode 21 and transferring the signal charge is formed adjoining the photodiode 21. Incidentally, each gate electrode 32 has very fine dimensions of 0.1 μm×0.1 μm, for example. Side walls 33 are formed on the side part of each of the gate electrodes 32. The side walls 33 are formed by a silicon oxide film, for example. Alternatively, the side walls 33 may be formed by a silicon nitride film. Diffusion layers 34, 35, 38, and 39 serving as sources and drains of the transistors are formed in the semiconductor substrate 11 on both sides of the respective gate electrodes 32. In this case, as an example, the diffusion layer 35 is shared as one diffusion layer 35 of the reset transistor 23 and one diffusion layer 35 of the amplifying transistor 24, and the diffusion layer 36 is shared as another diffusion layer 36 of the amplifying transistor 24 and one diffusion layer 36 of the selecting transistor 25. A floating diffusion (FD) 26 is also formed in the semiconductor substrate 11. In general, when holes and electrons are compared with each other as carriers, holes are more easily trapped on the gate insulating film 31 and the interface. Thus, in this case, electrons are selected as carriers, that is, NMOS transistors are formed. Silicide layers 41, 42, 101, and 102, 45, and 46 to 49 are formed so as to correspond to the diffusion layers 34, 35, 38, and 39, the floating diffusion 26, and the gate electrodes 32, respectively. In addition, a silicide blocking film 51 is formed on the photodiode 21 to prevent the formation of a silicide layer as described above on the photodiode 21. The silicide blocking film 51 is desirably formed by a silicon oxide film, a silicon nitride film, a silicon oxynitride film or the like. A titanium silicide, a tantalum silicide, a molybdenum silicide, a nickel silicide, a tungsten silicide, a nickel-platinum silicide or the like can be applied as the silicide layers 41, 42, 101, and 102 and 45 to 49. The transfer transistor 22 is connected between the cathode electrode of the photodiode 21 and the floating diffusion 26 as a charge-voltage converting section. The transfer transistor 22 transfers the signal charge (electrons in this case) stored in the photodiode 21 as a result of photoelectric conversion by the photodiode 21 to the floating diffusion 26 when a transfer pulse TRG is supplied to the gate electrode (control electrode) 32T. The reset transistor 23 has a drain electrode (diffusion layer 35) connected to a reset line, and has a source electrode (diffusion layer 34) connected to the floating diffusion 26. When a reset pulse RST is supplied to the gate electrode 32R prior to the transfer of the signal charge from the photodiode 21 to the floating diffusion 26, the reset transistor 23 resets the potential of the floating diffusion 26 to a reset voltage Vrst. The amplifying transistor 24 has the gate electrode 32A connected to the floating diffusion 26. The amplifying transistor 24 outputs the potential of the floating diffusion 26 after being reset by the reset transistor 23 as a reset level, and outputs the potential of the floating diffusion 26 after the transfer transistor 22 transfers the signal charge as a signal level. The selecting transistor 25 for example has a drain electrode (diffusion layer 38) connected to the source electrode (common diffusion layer 38) of the amplifying transistor 24, and has a source electrode connected to an output signal line. When a selecting pulse SEL is supplied to the gate electrode 32S, the selecting transistor 25 is set in an on state, and outputs a signal output from the amplifying transistor 24 with the pixel in a selected state to the output signal line (wiring 75). An etching stopper film 52 having an opening 53 formed on the amplifying transistor 24 is formed on an entire surface over the semiconductor substrate 11. The etching stopper film 52 is formed by a silicon nitride film, a silicon oxynitride film or the like that makes it easy to secure a selective etching ratio with respect to a silicon oxide film as an interlayer insulating film to be formed later. On the other hand, a compressive stress film 54 having a compressive stress is formed on the amplifying transistor 24 so as to cover the amplifying transistor 24. This compressive stress film 54 is formed by a silicon oxide film, for example. The etching stopper film 52 and the compressive stress film 54 are desirably of different film species because different film species make it easy to secure a processing (etching) selectivity. For example, as described above, the etching stopper film 52 is formed by a silicon nitride film, and the compressive stress film 54 is formed by a silicon oxide film. Of course, it may be vice versa, or two species of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film can be selected and used. When the etching stopper film 52 and the compressive stress film 54 are of a same species, a structure having an intermediate film of a different species inserted between the etching stopper film 52 and the compressive stress film 54 is desirable. Though not shown, for example, when a silicon nitride film is applied as the etching stopper film 52, a silicon oxide film is applied as the intermediate film. Further formed are for example wiring 71 for connecting the gate electrode 32T of the transfer transistor 22 and a driving circuit (not shown) to each other, wiring 72 for connecting the gate electrode 32R of the reset transistor 23 and the driving circuit (not shown) to each other, wiring 73 for connecting the gate electrode 32A of the amplifying transistor 24 and the floating diffusion 26 to each other, wiring 74 for connecting the gate electrode 32S of the selecting transistor 25 and the driving circuit (not shown) to each other, wiring 75 for connecting the diffusion layer 39 of the amplifying transistor 24 and a horizontal scanning circuit (output) (not shown) to each other, wiring 76 for connecting the diffusion layer 35 shared between the reset transistor 23 and the selecting transistor 25 and the pixel power supply Vdd (not shown) to each other, and the like. In the solid-state image pickup device 3 according to the present embodiment, the compressive stress film 54 having a compressive stress is formed on the amplifying transistor 24. Therefore, a local tensile stress applied to a channel region of the amplifying transistor 24 which stress is caused by the silicide layers 101 and 102 formed on the diffusion layers 38 and 39 of the amplifying transistor 24 and the element isolation region 96 is relieved by the compressive stress of the compressive stress film 54, so that an increase in variation in 1/f noise of the amplifying transistor 24 can be suppressed. Hence, because lowering of an SN ratio can be suppressed, there is an advantage of being able to obtain excellent image quality by achieving a high SN ratio. Thus, noise is reduced, whereby an STI element isolation region can be formed for isolation between elements. It is therefore possible to form a narrower space between elements, and achieve a higher degree of integration. An embodiment (fourth embodiment) of a solid-state image pickup device 4 according to the present invention will next be described with reference to a schematic configuration sectional view of FIG. 6. As shown in FIG. 6, a semiconductor substrate 11 of a first conduction type has a well region 12 of a second conduction type formed therein, the second conduction type being an opposite conduction type from the first conduction type. Description in the following will be made supposing that, as an example, the first conduction type is an N-type and the second conduction type is a P-type. For example an N-type silicon substrate is used as the above-described semiconductor substrate 11. A photoelectric conversion section (for example a photodiode (PD)) 21 for converting incident light into a signal charge is formed at a predetermined position on the surface side of the semiconductor substrate 11. The photoelectric conversion section 21 will hereinafter be described as photodiode 21. The photodiode 21 is for example formed by a P-type region, an N-type region, and a P-type region from a bottom layer in the semiconductor substrate 11. The photodiode 21 is desirably formed between the surface of the semiconductor substrate 11 and a depth of 5 μm to 15 μm for visible light, and is for example formed between the surface of the semiconductor substrate 11 and a depth of about 5 μm. As described above, an N-type silicon substrate is used as the semiconductor substrate 11, and therefore element isolation for the photodiode 21 is performed by the well region 12. MOS type transistors within the pixel are formed on the semiconductor substrate 11. Gate electrodes 32 are
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