Title of Invention: Load recognition and series arc detection using bandpass filter signatures Abstract: A method and system for determining whether arcing is present in an electrical circuit includes sensing a change in an alternating current in the circuit and developing a corresponding input signal, analyzing the input signal to determine the presence of broadband noise in a predetermined range of frequencies, and producing a corresponding output signal, and processing the input signal and the output signal in a predetermined fashion to determine whether an arcing fault is present in the circuit. The processing includes determining a type of load connected to the electrical circuit, based at least in part upon the input signal and the output signal, and monitoring high frequency noise in a 20 KHz band for each ⅛ cycle of the alternating current. Detailed Description: Part general_description_paragraphs: Part CROSS-REFERENCE TO RELATED APPLICATION: This is a continuation-in-part of U.S. patent application Ser. No. 10/107,621, filed Mar. 27, 2002 now U.S. Pat. No. 7,068,480, entitled “Arc Detection Using Load Recognition, Harmonic Content and Broadband Noise”, which is a continuation-in-part of U.S. patent application Ser. No. 09/981,603, filed Oct. 17, 2001, entitled “Arc Fault Circuit Interrupter System”. Part FIELD OF THE INVENTION: The present invention relates to the protection of electrical circuits and, more particularly, to the detection of electrical faults of the type known as arcing faults in an electrical circuit. Part BACKGROUND OF THE INVENTION: The electrical systems in residential, commercial and industrial applications usually include a panelboard for receiving electrical power from a utility source. The power is then routed through protection devices to designated branch circuits supplying one or more loads. These overcurrent devices are typically circuit interrupters such as circuit breakers and fuses which are designed to interrupt the electrical current if the limits of the conductors supplying the loads are surpassed. Circuit breakers are a preferred type of circuit interrupter because a resetting mechanism allows their reuse. Typically, circuit breakers interrupt an electric circuit due to a disconnect or trip condition such as a current overload or ground fault. The current overload condition results when a current exceeds the continuous rating of the breaker for a time interval determined by the trip current. A ground fault trip condition is created by an imbalance of currents flowing between a line conductor and a neutral conductor which could be caused by a leakage current or an arcing fault to ground. Arcing faults are commonly defined as current through ionized gas between two ends of a broken conductor or at a faulty contact or connector (“series” arcs), or, between two conductors supplying a load, or between a conductor and ground (“parallel” arcs). However, arcing faults may not cause a conventional circuit breaker to trip. Arcing fault current levels may be reduced by branch or load impedance to a level below the trip curve settings of the circuit breaker. In addition, an arcing fault which does not contact a grounded conductor or person will not trip a ground fault protector. There are many conditions that may cause an arcing fault. For example, corroded, worn or aged wiring, connectors, contacts or insulation, loose connections, wiring damaged by nails or staples through the insulation, and electrical stress caused by repeated overloading, lightning strikes, etc. These faults may damage the conductor insulation and/or cause the conductor to reach an unacceptable temperature. The present invention concerns detection of low current series arcs that occur within the normal operating range of household appliances and/or low current series arc fault detection that is within the handle rating of the protection device (e.g., a household circuit breaker). U.S. Pat. No. 6,008,973 (commonly assigned) based largely on slope changes in the load current and does not look at specific sub harmonic, broadband noise content and/or utilize load recognition. In contrast, this invention uses sub harmonic content, broadband noise and load recognition to set thresholds and select arc signatures. In our above-referenced application (pending U.S. patent application Ser. No. 10/107,621, filed Mar. 27, 2002) frequency was monitored at half cycle intervals for broadband noise, primarily in 33 KHz and 58 KHz bands. We have discovered that certain load types, such as a light dimmer load, have certain high frequency characteristics which can be used to develop algorithms to detect, for example, approximately what phase angle the light dimmer is set at and to use the appropriate arcing algorithms to detect arcing for that particular dimmer setting. We have found that the high frequency component of a typical light dimmer wave form will occur primarily on the rising edge of the current wave form. During arcing, noise is not localized to the rising edge of the current waveform, however. Therefore, this characteristic can be used to better distinguish arcing from normal operating noise. Also, in some load types, during arcing conditions, noise is present only where the current is non-zero; however, during arcing , currents are zero around the voltage zero crossings. High frequency noise is therefore essentially zero at these areas of the wave form. We have found that this generally holds true for any arcing in any type of load. Furthermore, in the present invention, we have discovered that monitoring high frequency noise in a 20 KHz band at ⅛ line cycle intervals may be used to obtain improved load recognition using arc detection methods and apparatus described in the above-referenced parent applications. The invention may be applied to residential, commercial, industrial applications for circuit protection against series arc faults. Part OBJECTS AND SUMMARY OF THE INVENTION: It is an object of the present invention to provide an arc fault detection system and method which reliably detects arc fault conditions which may be ignored by conventional circuit interrupters. Another object of the invention is to provide an arc fault detection system which utilizes a minimum number of highly reliable electronic signal processing components, such as a microcontroller, to perform most of the signal processing and analyzing functions, so as to be relatively simple and yet highly reliable in operation. Other and further objects and advantages of the invention will be apparent to those skilled in the art from the present specification taken with the accompanying drawings and appended claims. In accordance with one aspect of the invention, a method of determining whether arcing is present in an electrical circuit comprises sensing a change in current in the circuit and developing a corresponding input signal, analyzing the input signal to determine the presence of broadband noise in a predetermined range of frequencies including a 20 KHz band, and producing a corresponding output signal, and processing the input signal and the output signal in a predetermined fashion to determine whether an arcing fault is present in the circuit, the processing including determining a type of load connected to the electrical circuit, based upon the input signal and the output signal. In accordance with another aspect of the invention, a system for determining whether arcing is present in an electrical circuit comprises a sensor for sensing an alternating current in the circuit and developing a corresponding sensor signal, a circuit for analyzing the sensor signal to determine the presence of broadband noise in a predetermined range of frequencies, and producing a corresponding output signal, and a controller for processing the sensor signal and the output signal to determine load current characteristics and to determine, using the load current characteristics and the presence of broadband noise, a type of load connected to the electrical circuit and whether an arcing fault is present in the circuit, said circuit for analyzing including a circuit for detecting high frequency noise in a 20 KHz frequency band for each ⅛ cycle of said alternating current. In accordance with another aspect of the invention, there is provided a controller for a system for determining whether arcing is present in an electrical circuit in response to input signals, the input signals corresponding to an alternating current in the circuit and to the presence of broadband noise in a predetermined range of frequencies including 20 KHz frequency band, the controller comprising a plurality of counters, means for incrementing one or more of the plurality of counters in accordance with the input signals and means for periodically determining a type of load connected to the electrical circuit and whether an arcing fault is present using at least the states of one or more of the plurality counters, and a means for monitoring high frequency wire in said 20 KHz band for each ⅛ cycle of said alternating current. In accordance with another aspect of the invention, there is provided a method of determining whether arcing is present in an electrical circuit in response to input signals, the input signals corresponding to an alternating current in the circuit and to the presence of broadband noise in a predetermined range of frequencies in the circuit including a 20 KHz band, the method comprises incrementing one or more of a plurality of counters in accordance with the input signals, periodically determining a type of load connected to the electrical circuit and whether an arcing fault is present using the states of one or more of the plurality of counters, and monitoring high frequency noise in said 20 KHz band for each ⅛ cycle of said alternating current. Part DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT: This invention pertains to the use of a system on chip solution for arc fault detection primarily for use in circuit breakers or electrical outlet receptacles, or other electrical devices, typically but not limited to the 15 or 20 ampere size. Referring to FIGS. 1a and 1b, this microchip 10, when incorporated on an electronic printed wiring board 12 with a minimum of external components, provides arc fault detection and tripping of the host wiring device. The system on chip is an application specific integrated circuit which combines analog and digital signal processing on a single microchip. A block diagram is shown in FIG. 2. The “system on chip” 10 monitors line voltage and current in the host device and analyzes them for the presence of an arc fault. If certain arc detection criteria are met as determined by an arcing algorithm embedded within the software of a microcontroller's 14 memory 18, the chip signals an external SCR98 causing it to disconnect the device from the load. The ASIC generally includes a processor or microcontroller 14, memories, amplifier stages, filters, A/D converter, analog multiplexer, a voltage regulator and power on reset circuit. The tasks of the ASIC are: measure line voltage, detect voltage zero crossings, measure 60 Hz line current, measure ground fault current, detect ground loops (grounded neutral) in neutral line, detect high frequency components of line current, provide voltage regulation for all ASIC circuits, detect presence of a signal to commence self test, generate a self test high frequency current source, provide under voltage reset (POR) for the microcontroller, provide a trip signal to fire a trip solenoid driver, provide a watchdog to reset the microcontroller, and make a trip decision based on embedded code in the microcontroller. The ASIC can operate in two different modes: The “normal” mode corresponds to the mode where the processor 14 is the master. In normal mode, the microprocessor controls the data conversion rate (A-to-D), counters, interruptions and data memories. The microprocessor executes code stored in a ROM memory. Moreover, the microprocessor controls the activity of all analog blocks by forcing “power down” signal in order to limit the power dissipation. This mode is the normal operation mode of the ASIC. The “slave” mode corresponds to the mode where the processor 14 is the slave and is controlled by a standard communication channel (e.g., a JTAG) interface or port 15 (see FIGS. 1a and 1b). Two main operations can be done in this mode using the JTAG interface 15: debug mode, and register values and data transfer. The JTAG port can be used to couple a personal computer (PC) or other external processor to the ASIC, using the processor 14 of the ASIC as a slave processor. This permits interrogation of the ASIC counters, registers, etc. as well as rewriting to memories, registers, etc. of the ASIC. The JTAG ports 15 include data in/out ports (TDI, TDO), and reset (TRST), clock (TCLK) and mode select (TMS) ports. The processor 14, in one embodiment, is the ARM7TDMI from ARM company. The ARM has a boundary scan circuit around its interface which is used for production test or for connection to an in-circuit emulator (ICE) interface (i.e., the JTAG) for system and software debugging. The JTAG interface is accessible via the pins TDI, TDO, TMS, TCK and TRST and behaves as specified in the JTAG specification. The processor is 32 bits wide and has a CPU frequency of 12 MHz. An external resonator 90 (FIG. 1b) has a frequency of 24 MHz which is divided by two for the CPU. The microprocessor analyzes the current, ground fault and di/dt signals and by means of an arc detection algorithm makes a trip decision, using the presence of broadband noise and the current signature and rise time (di/dt). One such algorithm is described in U.S. Pat. No. 6,259,996, issued Jul. 10, 2001 to which reference is invited. While the line voltage is fed to the microprocessor, it may be optionally used by the algorithm to effect various levels of arc detection as dictated by the embedded software. The microprocessor uses the zero crossing signal to synchronize the arc detection algorithm with line voltage. There are different clock domains in the ASIC: A clock for the ARM, the bus controller and the memories. The microprocessor clock frequency is 12 MHz. Clocks for the peripherals (counters, watchdog, ADC, BP filters) are 4 MHz, 1 MHz and 250 KHz frequencies. These clocks are fixed and derived from the ARM clocks. There are two memory domains. The program memory, which contains the software for the ARM operation, the program memory space contains a 10 kb ROM (2560 words of 32 bits), and the program memory start address is 0000:0000hex. The data memory 16 contains the program data and consists of two RAMs of 128 bytes×16 bits for a total of 512 bytes. The memory access can be 32 bits or 16 bits wide. The ARM selects the access mode. The data memory start address is 0004:0000hex. In addition to the memories, the processor can also access registers. The register memory start address is 0008:0000hex. The various functional blocks (see FIG. 2) and their respective operation is described briefly below: A 3.3V regulator 20 provides a finely regulated DC power source for use by the analog and digital sections of the chip. The input to the chip need only be roughly regulated to within coarse limits, for example 4 to 7 volts. The POR or power on reset circuit 22 senses the chip's regulated voltage supply and holds the microcontroller in a reset state if the voltage is below a safe operating limit. The analog reference circuit (AREF) 24 provides a reference point for the input signals at the midpoint of the analog power supply to allow the amplified signals to swing both positive and negative. The AREF is externally connected to the REFIN pin 26. A V1/Vn differential amplifier 28 differentially measures line voltage at the terminals of the host device via an externally located voltage divider 29 (FIG. 1b). The voltage signal is low pass filtered as shown at the low pass filter block 30 to remove high frequency noise or harmonics and to provide anti-aliasing. The filtered signal is sent to a first channel of a multiplexer 32 and also to the input of a zero crossing detector 34. The output voltage at VCAP pin and an external capacitor 91 (FIG. 1b) provides an anti-aliasing low-pass filter (LPF) for the A/D converter 86. The typical differential input range at the inputs is +/−0.65V. A comparator 34 at the output of the line voltage differential amplifier 28 detects zero crossings (ZC) in the line voltage for use in synchronizing an arc detection algorithm. An amplifier 36 at the INTEG input amplifies the externally integrated output of a di/dt sensor before it is lowpass filtered 38 for anti-aliasing and sent to a second channel of the multiplexer 32 previously referenced. The output of a di/dt sensor 25 (see FIG. 1) monitoring line current through the host device is connected to the input of a di/dt amplifier 40 after first being high pass filtered by filter capacitors 42 (FIG. 1b) to remove the 60 Hz component. The di/dt signal is amplified at amplifier 40 and sent to the input of three bandpass filters 50, 52, 54. Broadband noise in the 10 KHz to 100 KHz range appearing at the DIDT input is one indicator of the presence of arcing. FIG. 3 shows a more detailed block diagram of the di/dt sensing system. Three switched cap (SC) bandpass filters (BPF) 50, 52, 54 set respectively at 20, 33 and 58 KHz, filter the di/dt signal to determine if there is broadband noise in the line current. The output of the filters is monitored by a set of comparators 60 whose outputs change state when a predetermined threshold is exceeded. The microprocessor 14 (FIG. 2) monitors the state of each filter's comparator individually and also the logically ANDed output at AND gates 62 of the 33 and 58 KHz filters to determine the presence of broadband noise. The comparator 60 outputs and the AND gates 62 are synchronized by the same clock (f=1 MHz) as the switched capacitor bandpass filters 50, 52 54. It should be noted that the ANDing of the comparator outputs with the clock insures that the components of high frequency in the passbands of both the 33 KHz and 58 KHz filters must be simultaneously present and of sufficient amplitude in order to be considered broadband noise and therefore be counted by the 33/58 counter. Separate counters are provided for future use, for counting the components in the passbands of the 20 KHz, 33 KHz and 58 KHz BPF's, respectively. The ASIC provides an amplification of the di/dt input signal and performs analog signal processing. As described above, the signal going through three independent switched-cap bandpass filters (BP) (20, 33 and 58 KHz) is compared to a fixed threshold reference voltage in both directions (positive and negative). The 20 KHz BP has a typical quality factor Q of 4. Both 33 and 58 KHz BP have typical Q of 8. The outputs of the comparators control separate counters. The ANDed boolean combination of 33 and 58 KHz BP comparator outputs controls a 4th counter as shown in FIG. 3. All comparator outputs are synchronized on the switched-cap clock (1 MHz) and are stable during each period of 1 μs. The counters can be reset or disable by software. An anti-aliasing filter is placed in the first stage. The cut-off frequency is typically 150 KHz. The sampling clock frequency of bandpass filters is F1MHz. Clamping anti-parallel diodes are placed between AREF and DIDT pins internal to the ASIC. The Z-domain function of the switched-cap bandpass filters can be described by the following expression: Yi=a(Xi−Xi−1)−b Yi−1−c Yi−2 Where Xi and Yi are, respectively, the ith samples of input and output voltages and a, b and c are the filter coefficients. Coefficient of normalized BP 20 KHz 33 KHz 58 KHz a 0.031 0.026 0.047 b −1.953 −1.932 −1.825 c 0.969 0.974 0.952 The output of a ground fault sensing transformer 35 (FIG. 1b) is connected to the input of a GFIN amplifier 80 (FIG. 2), which has a high gain to amplify the small output from the sensor. The ground fault signal is amplified and lowpass filtered (82) (FIG. 2) for anti-aliasing before being fed to the third channel of the multiplexer 32 (FIG. 2). Referring also to FIG. 4, this circuit performs an amplification and anti-aliasing low pass (LP) filtering of the ground fault (GF) input voltage before A-to-D conversion and provides high pass (HP) filtering and amplification for the grounded neutral detection at pin GFOSC. The first gain stage 80 is a current-to-voltage converter providing signal for both low and high pass filters 82, 83 (FIG. 2). The 3 dB bandwidth of the high pass filter will be typical 15 KHz. The LP and HP filters are made by internal resistors and external capacitors 81 and 85 respectively. Clamping anti-parallel diodes 87 (see FIG. 1b) are placed between AREF and GFIN pins for transient protection. The chip 10 has provision for personnel level ground fault protection when provided with a grounded neutral sensing transformer 83 (FIG. 4) as well as the 5 mA ground fault transformer 35 (FIG. 4). To make this feature functional, the output GFOUT may be coupled by means of a capacitor 81 to the input of GFHF. GFOSC is then capacitively coupled to the winding of the neutral sensing transformer 83. When thus connected, this forms a dormant oscillator neutral detection system, including second opamp 84 and comparator 89. The function of the second amplifier 84 at GFHF is to provide the total loop gain necessary to put the dormant oscillator into oscillation when a sufficiently low resistance grounded neutral condition exists. The multiplexer 32 (FIG. 2) alternately selects between the three channel inputs, i.e., current, line voltage or ground fault and passes the selected signal to the input of an analog to digital (A/D) converter (ADC) 86 (FIG. 2). The analog to digital converter 86 is a single channel sigma delta converter which alternately digitizes the current, line voltage and ground fault signals for analysis by the microprocessor. The line current signal at ASIC pin INTEG is obtained by an external low-pass 30 filter 83a placed in the output of the di/dt coil 25 (FIG. 1a). The ASIC amplifies the INTEG signal. An anti-aliasing LP filter is obtained by an external capacitor 88 (FIG. 1b) placed at ICAP pin before A-to-D conversion stage. The watchdog (WD) 92 monitors the operation of the ARM microprocessor 14. If the software does not reset the watchdog counter at periodic times, the watchdog generates a hard reset of the microprocessor. Alternately, it could be used to cause a trip condition. The watchdog is based on a 15 bit wide periodic counter which is driven by the 250 KHz clock. The counter is reset by software with the WDG_RST address. Writing a 1 on this address resets the counter. As noted, the watchdog must be reset only in a specific time window, otherwise a hard reset is generated. If the watchdog is reset before the counter reaches 2^14, or if the counter is not reset before the counter reaches 2^15, the watchdog reset is generated for the ARM and for the WD counter. To allow the ARM to check the watchdog value, the MSB (bit 14) can be read and if the value is 1, the processor must reset the counter. When the watchdog generates a reset, a specific register is set to indicate that a watchdog reset has occurred. This register value can be read even after the reset. When a trip decision is reached, a trip signal buffer 96 latches and drives the gate of an SCR 98 of an external firing circuit (FIG. 1a). In order to conserve stored energy during the trip sequence, the microprocessor is halted and portions of the analog circuitry are disabled. The SCR 98 is connected in series with a trip coil 100. In the ON state, the SCR 98 causes the coil 100 to be momentarily shorted across the line to mechanically de-latch the contacts of the host device and to subsequently interrupt flow of current. The push to test (PTT) circuit 102 monitors the status of a push to test (PTT) button 104. When the push to test button is depressed, line voltage is applied through an external voltage divider in circuit 102 to the PTT input of the chip 10. The circuit senses that a system test is being requested and signals the microprocessor to enter a test mode. The activation of the test button 104 (not part of the ASIC) is detected by the PTT comparator 93 (FIG. 2) as a voltage at a PTT (Push-to-Test) pin. With the microprocessor in the test mode, test signal buffer 106 acts as a current source driving a test winding 45 (FIG. 1a) of the di/dt sensor with a sharply rising and falling edge square wave at each of the center frequencies of the bandpass filters, namely 20 KHz (when used), 33 KHz and 58 KHz in turn. TABLE 1 below briefly describes each pin of the ASIC 10. Name Type Description VSUP Power High positive ASIC supply voltage VDDA Power Analog positive ASIC supply voltage and regulator output VDD Power Digital positive ASIC supply voltage (input) AGND Power Analog ground GND Power Digital ground INTEG Analog Input for Current measurement ICAP Analog Input for LP filter REFIN Analog Input sense of reference voltage AREF Analog Analog reference output DIDT Analog Input for DIDT measurement TEST Analog Test output signal TRIP Analog Trip output signal VL Analog Input for voltage measurement VN Analog Input for voltage measurement VCAP Analog Input for LP filter PTT Analog PTT Input signal CLKI Analog Input clock of quartz CLKO Analog Output clock of quartz GFIN Analog Input signal for GF measurement GFOUT Analog Output of gain stage GFLF Analog Input for LP filter GFHF Analog Input for HP filter GFOSC Analog Output of GF dormant gain stage TDI Digital-in Data in TDO Digital-out Data out TCLK Digital-in Clock in TMS Digital-in Select in TRST Digital-in Reset in (active low) Additional Operational Description The ground fault detection feature's primary purpose is to detect arcing to ground, in the incipient stages of arcing, where a grounding conductor is in the proximity of the faulty line conductor. Such detection and tripping can clear arc faults before they develop into major events. As discussed earlier, by the use of appropriate ground fault and neutral sensing transformers, this feature can be used to provide personnel protection as well as arc to ground detection. When the push to test button 104 is depressed, line voltage is applied to push to test circuit 102 in such a way as to cause ground fault current to flow through the ground fault sensing transformer 83 and simultaneously force the microcontroller 14 into the test mode as described previously. The microprocessor monitors the output of both the ground fault detection circuitry and the output of the bandpass filters (caused by the test buffer driving the test winding) to determine if the bandpass filter detection circuitry is functional. Only if counters 66 and 68 have sufficiently high counts and sufficiently high ground fault signal peaks are present, will a trip signal be given. A calibration routine allows the microprocessor 14 to compensate for the offset voltages generated by each of the operational amplifiers in the line voltage, current and ground fault measurement circuits. Immediately following power up and at periodic intervals (to update the data, e.g., to compensate for thermal drift), the microprocessor initiates a calibration procedure. During this time period, the line voltage and current measurement circuits are internally disconnected from their respective input terminals and each of the operational amplifiers is connected in turn to analog reference voltage (AREF) 24. The respective offset voltages (one for each op amp) are then read by the microprocessor and their values are stored in memory. The stored offset voltages are subtracted from the measured signal values by the software. The ground fault offset is measured by internally shorting the first stage amplifier (80) gain setting resistors and reading the offset voltage on an external AC coupling capacitor directly from the input. The software subtracts this value from the measured signal value. Residential type circuit breakers incorporating arc fault circuit protection require a very small printed wiring board with low power dissipation. Arc fault circuit interruption requires significant analog and digital signal processing in order to reliably distinguish between arc faults and electrically noisy loads, such as arcs from light switches and universal motors. In a previous embodiment, such processing was achieved using a separate analog ASIC (application specific integrated circuit) and a microcontroller. The system on chip design provides a reduced package size, approximately ⅓ reduction, as well as a reduction in external components required. The combination of reduced parts and part placement results in a significant cost reduction and ease of assembly. Bandpass filter performance is more consistent, offset voltage correction is improved, test circuit performance is improved, and ground fault personnel protection can be provided. Using load current, rate of rise of the load current (di/dt) and system line voltage, the invention detects series arcing conditions in household appliance cords and electrical wiring. Using load current, rate of rise of the load current (di/dt) and system line voltage inputs the method presented below will recognize the load if one is present, use the appropriate arc detection algorithms that match the load and determine if there are arcing signatures. When arcing signatures are detected, a trip signal is initiated and opens the circuit breaker, disabling the arcing source. The described embodiment of the invention is for 15 A or 20 A household branch circuit breakers but the invention is not so limited. We have found that series arc signatures are different with different types of loads in series with the arc. We have found that the best way to detect series arcing is to first categorize the signature of the load current and then look for arcing signatures for that type of load. We have found that most residential loads can be categorized, by their wave shape and phase relationship, into eight categories. We have designated these categories: “compressors,” “computers,” “computers and resistive,” “brush motor,” “light dimmer,” “light dimmer and resistive,” “variable speed motors” and “resistive.” Even though these load type designations were used, others may be included or substituted, without departing from the invention. We have achieved improved arc detection times and improved resistance to nuisance trips using the below-described technique. This technique is described hereinbelow in connection with a number of flowcharts briefly described above and which will be more fully described hereinbelow. In particular, in addition to the technique described in our above-referenced parent applications, we have found that the use of the high gain low queue factor 20 KHz bandpass filter divided into ⅛ line cycle increments offers additional improvement in some types of load. That is, using the high-resolution high frequency components at each ⅛ line cycle and looking for the presence of high frequency components at different locations of the line cycle, provides improved arc detection and resistance to nuisance tripping. Depending on the load type, the signature for the high frequency components will be different under normal load conditions, such as start up, and steady state conditions, from that under arcing conditions. In particular, we have discovered with some loads such as a typical vacuum cleaner load, that a high gain low queue filter bandpass filter will have a constant non-zero output. However, during series arcing of such a load, the continuous filter output will go to zero near the voltage zero crossings when the arcing current is zero. During arcing, there will be no high frequency components when the currents are zero, which occur randomly in arcing events, whereas during normal running loads the high frequency components are generally more uniform. Thus, using a high gain, low queue filter and dividing the line cycle into multiple sections, we have found that improved arc detection can be achieved. Referring now to FIGS. 5A–5C, a main program sequence at a start 202 initializes 204 the microprocessor or controller (see FIG. 6), and then waits 206 for the next zero voltage crossing of monitored current and then starts A/D conversion 208. A self test or push to test (PTT) mode 212 is then enabled which, if called for and successful, energizes a trip solenoid to trip a breaker. In addition to the foregoing, the flowcharts briefly described above and more fully discussed hereinbelow offer some additional improvements over those disclosed in our above-referenced copending application (Ser. No. 10/107,621, filed Mar. 27, 2002). One aim in the present application was to improve code efficiency and also to recompile the coding and modules for use with an improved processor type. In the embodiment described hereinabove, the processor, may be of a type designated ARM7TDMI provided by the ARM Company (Advanced Reduced Instruction Set Computer (IRSC) Machine) which is essentially code provided for the ASIC vendor to permit the ASIC carry out the arc detection in accordance with the invention. Referring now again to FIGS. 5A–5C, the main program sequence then sequences through a number of other modules, further details of which are shown in the following figures of drawing. Briefly, these include a detect load type module 240, shown in FIGS. 7A–7J, an update history buffers module 242, shown in FIG. 8 and an undercurrent monitor module 244, shown in FIG. 9. These are followed by an over 5 amp resistive algorithm module 246 shown in FIG. 10, an inductive arcing timer module 248 shown in FIG. 11, and a set parameters module 250 shown in FIG. 12. This latter module 250 and the following three modules 252, 254 and 256 shown respectively in FIG. 12 FIGS. 13A–13F, FIGS. 14A–14B and FIGS. 15A–15D are repeated three times for each of three separate algorithms which are designated algorithm 1, algorithm 2 and algorithm 3. In each of these algorithms, some of the parameters are changed somewhat as each of the modules are run. Accordingly, modules 258, 260, 262 and 264 are identical modules run with somewhat differing parameters for “algorithm 2” and similarly, modules 266, 268, 270 and 272 are the same modules, again run with somewhat different parameters for “algorithm 3.” Next, a missing half cycle module 291 is shown in FIG. 16 and a parallel arc algorithms module 291 shown in FIGS. 17A–17F are run. This latter parallel arc algorithms module 291 is a so-called type B algorithm to test for parallel arcing in a manner more fully explained in our prior U.S. Pat. No. 6,259,996 accordingly, and referring briefly to FIGS. 13A–13F, the algorithms shown here are essentially similar to those shown in our above-referenced prior patent. Following the parallel arc algorithms, start up algorithms 278 are performed as shown in FIG. 18. At this point, the trip equation is run at 280, as shown in FIGS. 19A–19J. At 282, the program sequence checks for zero crossing to verify the half cycle is complete. Upon completion of the half cycle, the main sequence proceeds to a check for current shelf module 284 shown in FIGS. 20A–20B followed by a use 20 KHz filter module 286 shown in FIGS. 21A–21C. It is at this point that the 20 KHz filter is used in accordance with one aspect of the invention to monitor high frequency noise for each ⅛ line cycle as discussed above. The next module 288 reads the high frequency count from the 20 KHz filter as shown further in FIGS. 22A–22B, and the half cycle results are stored at module 290 shown in FIG. 23. A test button debounce register is read at 292 and if greater than 2, the self-test mode is set true, the test button debounce is set equal to 4 and the four seconds count register is set to zero at 294, whereupon the main sequence is ready to repeat from the top of FIG. 5A. While the specific algorithms shown herein differ somewhat from those shown in the above-referenced parent application, the basic theory and manner of operation is the same, wherein the module looks at various peaks, areas and rise times, as well as various ratios of values from one sample to the next for over given groups of samples, as well as factors such as the change in peak position from one cycle to the next. All of these factors are used to increment or set a number of registers or counters in software for selecting an appropriate load type algorithm to be run later in the arc detection algorithms or trip equation of FIGS. 19A–19J. FIG. 6 shows the above-referenced initialization module 204 which includes a start 230, initialization of software counters/registers 233, clears RAM data, and goes to a return. The designated load types in the present embodiment are compressor load, computer load, resistive computer load, resistive, inductive brush load, light dimmer, light dimmer resistive load and variable speed motor. Other load types or subgroupings of upload types based on the same or other criteria may be designated or utilized without departing from the invention. In accordance with the described embodiment of the invention, the microcontroller or microprocessor implements a number of counters in software. These counters are incremented and decremented in accordance with the detect load type routine or module, to be described presently, as well as in accordance with other routines or modules, including an arc detection algorithm or “trip equation” to be described later. The controller then determines, based upon the states of various counters or subgroups of counters not only the load type, from among the types given above, but also whether arcing is present. As will be seen presently, a different algorithm or different subroutines or portions of algorithms are used for each kind of load, once the type of load has been determined, to determine whether arcing is occurring based upon the sensor inputs obtained as described above. Thus, a number of counters or registers are incremented and/or set in accordance with the incoming sensor signals. The states of these registers and/or counters are used in various algorithms or subroutines to determine not only the load type, but the occurrence of arcing of a type and/or sufficient magnitude to cause a trip signal to be given, so as to trip a circuit breaker to an open position. As will become apparent from the ensuing description, the method of the invention also selects one of the load types as a default. In the present embodiment, the resistive load type is the default selection in the event that none of the other load types is determined to be present by the detect load type routine of FIGS. 7A through 7J. Referring now to FIG. 7A, at 304 a peak position of the incoming waveform is monitored for the purpose of setting the absolute value for the peak position difference between half cycle 1 and half cycle 2 in a delta peak position register. Thereupon, a half area n register 310 sets the area equal to one half of area n, the area under the waveform on the nth (e.g., first) half cycle. The algorithm then looks at a plurality of previously taken samples (1–14) at 312 and (15–32) at 314 to determine an appropriate setting for a midpoint register at 316, 318 or 320. In this regard, the illustrated embodiment takes 32 samples per line cycle. The midpoint register or counter count corresponds to the sample and the cycle at which the midpoint or spike in current occurs. Next, at 322 a rise time register is set equal to the ratio of peak 1 to maximum di/dt1, i.e., of the first half cycle, and an aspect ratio register is set equal to the ratio of the area to the peak in the first half cycle. If two times the area in the first half cycle is greater than the value in the minimum amps register (324), load current is set qrogers@example.net. If not, load current is set qrogers@example.net. Continuing to FIG. 7B, if the load current is true 330, the peak register is checked, and if below 4000 (331), values in the aspect ratio peak position, rise tune and midpoint registers are qrogers@example.net. The shelf count is checked at 333, and the load type counter is incremented 334 if these registers are less than certain values. If not, aspect ratio peak portion and midpoint values (at 336) the shelf count and inductive brush count (at 337) are checked and the load type register or counter is incremented by two at 338, depending on these values, i.e., if these values are greater than or less than selected quantities. In FIG. 7C, delta and peak position max di/dt register values are read at 340 and if these values are greater or less than selected quantities, the factor 1 and 2 register are set to selected qrogers@example.net. Next, aspect ratio register and others are read at 342, and if greater or less than selected quantities, the resistive computer count register or counter is incremented by qrogers@example.net. Additional checking of register values and incrementing of inductive brush count and resistive computer count load type register and setting of factors are illustrated at 345, 346, 347, 348, 349, 350 and 352, whereupon the program proceeds to FIG. 7D. It will be noted that a “false” reading in the load current =true register 330 or a “no” at the peak position and midpoint readings 340 direct the program to FIG. 7G. In FIGS. 7D, 7E and 7F, a number of other register values are tested and if within certain ranges, or above or below certain values, various load type registers and factor registers are set, in much the same way as in FIG. 7C. Referring next to FIG. 7G, in the described embodiment, the load type counters are essentially free running, and in order to prevent them from overflowing, they are all decremented by one count, assuming they are currently above zero. This is illustrated in the steps 404 through 430. Proceeding to FIG. 7H, the counts in the counters for the various load type are checked at 436 along with a “load type” counter and if greater than certain values, the load type counter is decremented by two at 438 or, if not, and the load type counter is non-zero (440), the load type counter is decremented by qrogers@example.net. If the load type counter is not greater than 0, a peak minus 25 percent register is qrogers@example.net. At reference numerals 444–450, further checks of the load type counter and a below 5A register (at 444) are run for either decrementing the load type counter (446) or for setting the load type counter equal to 12 (450). FIGS. 7I and 7J indicate a number of settings of a detected load counter or register, based upon the counts in a number of the load type counters. FIG. 7J indicates setting of a detected load counter to default 1 or default 2 conditions and the setting of a check high frequency count register to true based on certain conditions in resistive count and various peak counters as indicated. FIG. 8 shows the module 242 for updating history buffers in which a number of registers or buffers are updated as indicated. FIG. 9 shows the undercurrent monitor module 244 which checks for a below 5 amp current condition. FIG. 10 shows the over 5 amp resistive module 246. This module monitors the condition of a number of counters as indicated at 502–506 and increments or decrements a frequency counter, as shown at 508–512. At 514, an over 5 amp high frequency register is initially set false and the absolute value of the difference between a high frequency count at 33 KHz and 58 KHz for the first and third half cycles is calculated. Referring now to FIG. 11, the inductive arcing timer module 248 is shown in additional detail. This module begins at 550 by checking hit 30 and hit 20 registers. These registers relate to 30 Hz or 20 Hz harmonics in the current signature. The inductive arcing timer module then checks the states of slope changes counters and correspondingly increments or decrements an arcing inductive counter at 552 and 554 or 556, depending on its current state. FIG. 12 shows the set parameters module 250. This module sets parameter 1 and parameter 2 registers and a numerator and denominator sign register as well as an a Temp 2 register, depending on the algorithm selected. In this regard three algorithms are selectable in the illustrated embodiment, and as seen with respect to the main program sequence. In FIGS. 5A–5C, the module of FIG. 12 is run three times, one for each of these algorithms. The module itself, as seen in FIG. 12, determines which algorithm is being called for, as indicated at reference numerals 600, 602 and 603. Similarly, the registers set by the module are indicated at reference numerals 604, 605, 606, 608 and 610. FIGS. 13A–13F show a self-test limit module 252. This module sets certain limits of a percent register for each of the three algorithm types, and like the module of FIG. 12 is run three times as shown in FIGS. 5A–5C, one time for each algorithm, determined as indicated at 620, 622 and 623. In each case, the module sets percent limits (as defined in the table below) for the various load types for each algorithm as generally shown in FIGS. 13A–13F. This includes settings for default 1 and default 2 load types as well. TABLE 1 Test Limits Definitions Limit_1[0] = 12 Limit_2[0] = 12 Limit_3[0] = 16 Limit_1[1] = 24 Limit_2[1] = 24 Limit_3[1] = 16 Limit_1[2] = 128 Limit_2[2] = 128 Limit_3[2] = 128 Limit_1[3] = 64 Limit_2[3] = 64 Limit_3[3] = 32 Limit_1[4] = 32 Limit_2[4] = 32 Limit_3[4] = 32 Limit_1[5] = 64 Limit_2[5] = 64 Limit_3[5] = 64 Limit_1[6] = 100 Limit_2[6] = 100 Limit_3[6] = 100 Limit_1[7] = 100 Limit_2[7] = 100 Limit_3[7] = 64 Limit_1[8] = 128 Limit_2[8] = 128 Limit_3[8] = 128 Limit_1[9] = 32 Limit_2[9] = 32 Limit_3[9] = 32 Limit_1[10] = 32 Limit_2[10] = 32 Limit_3[10] = 32 FIGS. 14A–14B show the check limit module 254. This module essentially checks to see if the “parameters” have changed by certain percentage limits as set in the module of FIGS. 13A–13F. A “ratio is greater than test limit” register or buffer is initially set to false as qrogers@example.net. The sign of the parameters from one sample to the next is next checked at 642 and if positive, indicating a rising wave form edge, the ratio sign is set true at 644 and if negative, indicating a falling edge, the ratio sign buffer is set qrogers@example.net. The value of a ratio register is then set as the absolute value of the difference between the parameters at 648, and at 650 a stop overflow limit is set. If the ratio is greater than the stop overflow setting as shown at 652, ratio is set equal thereto at 654 or is set equal to a percentage of the current ratio value at 656 if it is not greater than the stop overflow limit. The state of the below 5 amp buffer is checked at 658, and if true, the ratio is set to qrogers@example.net. If not, if the ratio sign is true and ratio is greater than parameter 1, a ratio is greater than test limit register or buffer is set qrogers@example.net. If the ratio sign is set false and the ratio is greater than parameter 2, the ratio is greater than test limit buffer is set true as qrogers@example.net. FIGS. 15A–15D show the check slope changes module 256. In the same fashion as the previous modules 250, 252 and 254, this module is also activated or run for each of the three algorithms in the illustrated embodiment, as indicated in FIGS. 5A–5C. It should be noted that in the modules as shown in the flowcharts, certain conventions have been used, including the use of an exclamation point (1) to indicate a logic NOT and && to indicate a logic AND. In the check slope changes module, initially a hit buffer is set false showing at reference numeral 700 and this buffer will be set true if certain slope change conditions are met as determined by the remainder of the module. Here, slope one refers to algorithm 1 and slope 2 to algorithm 2 and slope 3 to algorithm 3. The portion of the module in FIG. 15A determines whether the current signature appears more like a start up condition or more like an arcing condition. This portion of the module extends up to and including step 704 in FIG. 15B. Similarly, the portion of the module following step 704 through and including the remaining portion of FIG. 15B comprises further checks for start up conditions vs. arcing. In the portion of the module in FIG. 15C, as the down count increases, this indicates a greater probability of a start up condition. Finally, the down count is decremented each cycle as indicated at reference numeral 720 of FIG. 15C to avoid overfilling its register. In the illustrated embodiment, the maximum down count in the down count register is 18 as indicated in FIG. 15D at reference numeral 724.
{'bibliographic_information': "{'country': 'US', 'doc-number': '10436671', 'kind': 'B2', 'date': '20030513', 'extension': '553', 'invention_title': 'Load recognition and series arc detection using bandpass filter signatures'}", 'source_file': './grant/2006/ipg061114.xml', 'source_data': 'USPTO-Grant'}