Title of Invention: System architecture for multiple input/output devices
Abstract: A system or a board that interacts with a processor and multi I/O devices such as high-speed facsimile modems. The processor inputs/outputs data to I/O devices. Each I/O device includes an indicator, such as an Interrupt Request output, to signify a request that the I/O device will output or input data. If the indicator signifies a request, the processor will input data from or output data to the I/O device within a predetermined period Ti, in order to prevent the data from being lost. To this end, the new system or board includes a timer that periodically interrupts the processor and causes it to execute an interrupt service at a period T, where T&lt;=Ti, whereupon the processor detects the indicators of I/O devices, and reads data from or writes data to any I/O device that signals a request.
Detailed Description: Part PAC: DESCRIPTION OF THE PREFERRED EMBODIMENT
Part PAR: Referring to FIG. 1, there is shown in block form a fax-on-demand system 10 which is constructed in accordance with one embodiment of the present invention. The system 10 generally includes a processor or computer 12 such as an IBM compatible 386 PC, and an I/O board 14 comprised of several I/O devices such as multiple Rockwell's R96MFX MONOFAX (a registered trademark of Rockwell) facsimile modems 20, 30 and 50. In one embodiment according to the present invention each facsimile modem 20, 30, 50 is set to a parallel data mode. It should however by understood that other components of the system 10 may alternatively be used.
Part PAR_2: The R96MFX facsimile modem is a high-speed synchronous 9600 bits per second (bps) half-duplex modem, with the following settings:
Part PA1: 1. Parallel Data Mode (PDM). When control bit PDM is a 1 and the modem is a transmitter, it accepts data for transmission from DBUFF. When PDM is a 1 and the modem is a receiver, the modem provides the received data to the host using DBUFF. PA1 2. Data Buffer (DBUFF). In the parallel data mode, the host obtains received data byte from the modem by reading a data byte from DBUFF; the host sends data to the modem to be transmitted by writing a data byte to DBUFF. PA1 3. Buffer Available 2 (BA2). When set to a 1, status bit BA2 signifies that, when the modem is in parallel data mode, it has read register DBUFF when transmitting (buffer becomes empty), or it has written register DBUFF when receiving (buffer become full). These conditions can also cause IRQ (Interrupt Request) to be asserted. PA1 Ti=1 second* 1 byte/9600 bps, PA1 Ti=1000 ms* 8 bits/9600 bps, PA1 Ti=0.83 ms. PA1 1. Dials the telephone number of the fax-on-demand, for instance from the telephone handset of facsimile machine; PA1 2. keys in a required 4-digit ID code, such as 1234; and PA1 3. issues a START command. PA1 1. Places (i.e., electronically) the facsimile document into the facsimile machine, and dial the telephone number of the fax-on-demand, for instance from the telephone handset of the facsimile machine; PA1 2. keys in a 4-digit ID code, such as *1234; and PA1 3. issues a START command. PA1 1. The processor writes a data byte to the serial port. PA1 2. The serial port serializes the data and feeds it to the modem one bit at a time. PA1 3. The modem sends it over the telephone line to the other computer system. PA1 4. The serial port interrupts the processor to request another byte. PA1 1. The modem receives the data over the telephone line, and sends the serial bit stream to the serial port. PA1 2. The serial port interrupts the processor when it has assembled 8 bits into a byte. PA1 3. The processor jumps to the serial port's interrupt service routine. PA1 4. The interrupt service routine inputs the data byte and stores it in memory. PA1 1. The processor writes a data byte to parallel port. PA1 2. The output device fetches the data byte. PA1 3. The parallel port interrupts the processor to request another new data byte. PA1 1. The input device sends data byte to parallel port. PA1 2. The parallel port interrupts the processor. PA1 3. The processor jumps to the parallel port's interrupt service routine. PA1 4. The interrupt service routine inputs the data byte and stores it in memory.
Part PAR_3: Once BA2 is set to 1 by modem, when the modem is transmitting, the following data byte will be written to the DBUFF within a period Ti, in order to prevent the modem from losing the transmission of the following data byte.
Part PAR_4: Once BA2 is set to 1 by modem, when the modem is receiving, the data byte will be read from the DBUFF within a period Ti, in order to prevent the data byte from losing because the modem may write following new received data byte into the DBUFF.
Part PAR_5: When the R96MFX facsimile modem operates at its highest speed of 9600 bps, the period Ti is about:
Part PAR_6: When a modem, i.e., 20, 30 or 50 is a transmitter, it accepts data for transmission from DBUFF 22, 32 or 52, respectively, and sets a status bit BA2 21, 31 or 51, respectively, to 1 to signify that it has read register DBUFF 22, 32 or 52 which buffer (DBUFF) becomes empty and need following new data. When a modem, i.e., 20, 30 or 50 is a receiver, the modem provides the received data to the processor 12 using DBUFF 22, 32 or 52 and sets a status bit BA2 21, 31 or 51 to 1 to signify that it has written on register DBUFF 22, 32 or 52 which buffer becomes full. Here, the status bit BA2 is the indicator.
Part PAR_7: In order to connect the modem 20, 30 or 50 to a transmission path, such as a phone line, a net control unit (not shown) is provided for each of the facsimile modems 20, 30 and 50. The net control unit is provided with a ring signal detector (not shown) and a dual tone multifrequency (DTMF) digit detector (not shown).
Part PAR_8: The processor 12 may include one or all of the following components: a central processing unit (CPU) 15, a hard drive 16, a memory 18, a timer 24 and a programmable interrupt controller (PIC) 25. The CPU 15 provides control flow for the modems 20, 30 and 50. The hard drive 16 may be included as part of the processor 12 in order to store facsimile documents. The memory 18 may be a random access memory (RAM) which allocates memory blocks M1, M2 and MN to service the facsimile modems 20, 30 and 50, respectively. The processor 12 includes a square wave generator, such as an Intel 8254 programmable interval timer working in mode 3, or the timer 24 for generating a periodic square wave signal with an exemplary period T=0.64 msec. It should be clear that other periods for the timer 24 may alternatively be selected as deemed appropriate. The PIC 25 may be an Intel 8259 programmable interrupt controller.
Part PAR_9: The timer 24 is connected to the PIC 25 and periodically, at the end of the period T, causes the CPU 15 to execute an interrupt service, as it will be further described in relation to FIG. 2. It should be noted that the CPU interrupt period T (i.e., 0.64 msec) is less than the modem period Ti (i.e., 0.83 msec) of each facsimile modem.
Part PAR_10: The hard drive 16, the RAM 18, the timer 24, the PIC 25 and the I/O board 14 including the facsimile modems 20, 30, and 50 are connected to the CPU 15 via a system bus (SB) 26 for transmission of data and signals therebetween.
Part PAR_11: In use, when a subscriber wishes to demand a facsimile document from the fax-on-demand system 10, the subscriber performs the following functions:
Part PAR_12: The fax-on-demand system 10 will then send the facsimile document of the ID code 1234 to the gonzalessteven@example.org.
Part PAR_13: In response to the subscriber, the fax-on-demand system 10 detects a call from the ring detector, receives the 4-digit ID code from the DTMF digit detector, and connects the facsimile modem such as the facsimile modem 20 to the phone line. The CPU 15 executes the transmits facsimile flow control, fetches the facsimile document corresponding to the ID code 1234 from the hard drive 16 to memory block M1 of the RAM 18.
Part PAR_14: An important part of the transmit facsimile flow control is for the processor 12 to send the transmitted data from M1 of the RAM 18 to the transmitter or the modem 20 for transmission to subscriber's facsimile machine. During the transmits facsimile flow control, when the CPU 15 controls modem 20 to transmit data, the modem becomes active. When the modem becomes active for transmitting, it receives transmitted data byte from the data buffer DBUFF 22, and if the modem reads the data byte from the DBUFF 22, it sets the BA2 21 to request the following new data byte. In response to that modem 20 becoming active, the periodic interrupt service begins to handle with modem 20, and to respond the request BA2 21 and to send transmitted data from M1 of the RAM 18 to the DBUFF 22 of the modem 20.
Part PAR_15: For the periodic interrupt service, at each periodic interrupt service triggered by the timer 24, the CPU 15 checks the bit BA2 or indicator (i.e., 21), and if the BA2 21 signifies a request, the CPU 15 will sequentially reads a data byte of the facsimile document from the memory block M1, and writes it to the DBUFF 22 of the facsimile modem 20 for transmission to the subscriber.
Part PAR_16: When the subscriber desires to send (or store) a facsimile document to the fax-on-demand system 10, the subscriber performs the following tasks:
Part PAR_17: The fax-on-demand system 10 receives the facsimile document at once, and store it in the hard drive 16 with the ID code 1234.
Part PAR_18: In response to the subscriber, the fax-on-demand system 10 detects a call from the ring detector, receives the * and the 4-digit ID code from the DTMF digit detector, and connects the facsimile modem such as the modem 30 to the phone line. The CPU 15 executes the receiving facsimile flow control.
Part PAR_19: An important part of the receiving facsimile flow control is for the processor 12 to obtain the received data from the receiver or modem 30 and store them to M2 of the RAM 18. During the receiving facsimile flow control, when the CPU 15 controls modem 20 to receive data, the modem becomes active for reception from subscriber's facsimile machine. When modem the becomes active, it stores received data byte to the data buffer DBUFF 32, and if the modem stores a data byte to the DBUFF 32, it sets the BA2 31 to request for the processor 12 to read the data byte and empty the DBUFF 32 for the following new received data byte. In response to that modem 30 becomes active, the periodic interrupt service begins to handle with modem 30, and to respond the request BA2 31 and to send received data byte from DBUFF 32 of the modem 30 to the M2 of the RAM 18.
Part PAR_20: For the periodic interrupt service, at each periodic interrupt service triggered by the timer 24, the CPU 15 checks the bit BA2 (or indicator) 31; and if BA2 signifies a request, the CPU 15 will read a data byte from DBUFF 32 and sequentially writes it to the memory block M2 of the RAM 18.
Part PAR_21: After all the data bytes of the facsimile document of the subscriber are received by the periodic interrupt services, the CPU 15 sends the facsimile document from memory block M2 to the hard drive 16 and stores it as a file with the corresponding ID code. The fax-on-demand system 10, through its facsimile modems 20, 30 and 50, can simultaneously service multiple subscribers.
Part PAR_22: Referring now to FIG. 2, it illustrates the interrupt service used in the system 10 of FIG. 1. At the end of the period T, the timer 24 independently and periodically informs or triggers the CPU 15 to execute the interrupt service. The interrupt service transfers data byte between the RAM 18 and the multiple facsimile modems 20, 30 and 50. It should be noted that for each interrupt, the interrupt service will service multiple facsimile modems 20, 30 and 50.
Part PAR_23: As shown in FIG. 2 at block 61, whenever the timer 24 interrupts the CPU 15, the CPU 15 executes the interrupt service and goes to the block 61. Blocks 61 and 62 describe the routine of having the CPU 15 service a first facsimile modem, i.e., 20. In block 61, the CPU 15 checks whether the facsimile modem 20 is active, i.e., whether it is transmitting or receiving data, and signifies a request of data transfer (the bit BA2 21 is set to 1). If the modem 20 active and has a request, the CPU 15 goes to block 62; otherwise the CPU 15 skips block 62.
Part PAR_24: At block 62, when the modem 20 acts as a transmitter, the CPU 15 sequentially reads a data byte from M1 of the RAM 18 and writes the data byte into the DBUFF 22. On the other hand, and when the modem 20 acts as a receiver, the CPU 15 reads a data byte from the DBUFF 22, and sequentially writes the data byte into M1 of the RAM 18.
Part PAR_25: After the CPU 15 services the first modem 20, it proceeds to service the second facsimile modem 30. Reference is made to blocks 63 and 64. At block 63 the CPU 15 checks whether the modem 30 is active and signifies a request of data transfer (bit BA2 31 is set to 1). If the modem 30 is active and has a request, the CPU 15 proceeds to block 64. Otherwise, the CPU 15 skips block 64. At block 64, when the modem 30 acts as a transmitter, the CPU 15 reads a byte from memory block M2 of the RAM 18, and writes the byte into DBUFF 32. On the other hand, if the modem 30 acts as a receiver, the CPU 15 reads a byte from the DBUFF 32 and writes the byte into memory block M2 of the RAM 18.
Part PAR_26: Following the foregoing logic and routine, the CPU 15 proceeds to blocks 67 and 68 and services modem (N). Finally, the CPU 15 terminates the interrupt service, returns to its original operation and repeats the interrupt service in the following periodic interrupt triggered by the timer 24.
Part PAR_27: The interrupt service is repeated and executed at the end of the period T, and each facsimile modem 20, 30 or 50 allows data transfer within a period Ti after it signifies a request (BA2 is set to 1). It should be noted that if the period T is less than or equal to the period Ti, then at least one interrupt is caused by the timer 24 within a period Ti. So, whenever any facsimile modem signifies a request of data transfer, the interrupt service triggered by the timer 24 can service the request in time, so that no data bytes from any of the modem 20, 30 or 50 are lost or overrun.
Part PAR_28: The RAM 18 works as data buffer, which accelerates data transfer for the interrupt service. In the fax-on-demand system 10, received or transmitted data may be directly transferred between the hard drive 16 and the modems 20, 30 and 50 without assistance from the RAM 18. In this case, it could take a longer time for the CPU 15 to service each modem, because the reading or writing of data from the hard drive 16 could be relatively slow. During the interrupt service, when the CPU 15 spends more time on some modems, such as the modem 20, data for other modems such as the modems 30 and 50 may overrun, because now the CPU 15 cannot service these modems 30, 50 on time.
Part PAR_29: The interrupt priority of the timer 24 is higher than some interrupts from other devices and some operations of the CPU 15, such as file transfer between the RAM 18 and the hard drive 16. For example, the CPU 15 may be reading a facsimile document from the hard drive 16 for the modem 20, but the timer 24 can interrupt its operation and cause the CPU 15 to transfer the data byte between the RAM 18 and the modems 30 and 50 if the modems 30 and 50 are active.
Part PAR_30: The I/O devices may have different Ti. For example, the first modem 20 has a period T1, while the second modem 30 has a period T2, and modem (N) has a different period Tn. In this particular example let us assume that T&lt;T1, T&lt;T2, and T&lt;Tn, which can also be expressed by the general equation: T&lt;Ti.
Part PAR_31: For the software architecture, the interrupt service can be programmed as an interrupt routine or multiple interrupt routines. For example, in the programming of multiple interrupt routines, a first interrupt routine services modem 20, and a second interrupt routine services modem 30. When the timer 24 interrupts the CPU 15, the first interrupt routine is executed, then the second interrupt routine is executed.
Part PAR_32: In the interrupt service, the data byte may be processed while it is being transferred. For example, the data byte is read from the RAM 18, converted to another format, and written to the modem; or, alternatively, the data byte is read from the modem, converted to another format and written to the RAM 18.
Part PAR_33: There are various methods that can be used to send received data from modems 20, 30 and 50 to RAM 18, or send transmitted data from RAM 18 to the modems. In the embodiment, we describe that the processor 12 directly writes/reads the parallel port DBUFF 22, 32 and 52 of the modem for data transfer, but computer or processor can use other accesses to I/O devices such as serial port, parallel port and DMA (Direct Memory Access) method.
Part PAR_34: The I/O device is generally connected to the computer by a serial port or a parallel port, and the modem is generally connected to the computer by a serial port. When the computer is transmitting data to another computer via the modem:
Part PAR_35: When the computer is receiving data from another system via modem:
Part PAR_36: The serial port such as Intel 8250 UART generally uses a register for transmitter's data and a bit of the status register for signifying transmitter's interrupt request; and use another register for receiver's data and another bit of the status register for signifying receiver's interrupt request.
Part PAR_37: Another I/O interface is the parallel port. When the parallel port is sending data to the output device:
Part PAR_38: When the parallel port is receiving data from the input device:
Part PAR_39: The parallel port such as Motorola 6821 PIA may use a register for output data and another register for input data and a bit of the status register for input and input interrupt request.
Part PAR_40: For each serial port or parallel port, it has the data registers or the data buffer, and it has the interrupt request bits or the indicators. When the interrupt request bit of the serial port or parallel port is set, the processor will response the request within a period Ti according to the feature of the I/O device that connects to the serial port or parallel port. If the computer includes multiple serial ports and/or parallel ports, it is possible to disable the interrupt requests to the processor from the multi serial ports and/or parallel ports, and to use the interrupt of a periodic Timer to interrupt the processor. In the Timer's interrupt service, the processor checks the interrupt request bits of the multi serial ports and/or parallel ports, and writes data to or read data from the multi serial ports and/or parallel ports that show the requests. A system architecture for multi serial ports and/or parallel ports can be based on the present embodiment of the fax-on-demand system described herein.
Part PAR_41: In the computer system with I/O devices, the I/O interfaces such as serial port and parallel port may be a part of the computer, (that is, the computer has the I/O interfaces) or a part of the I/O devices (that is, the I/O devices have the I/O interfaces). For convenience, when we mention the I/O device including modem, facsimile modem in our description, the I/O device includes the I/O interface. For example, when the modem connects to the computer via a serial port, the serial port is treated as a part of the modem even if the serial port is a part of the computer, and to write a data byte to the modem means to write the data byte to the serial port, and to read a data byte from the modem means to read the data byte from the serial port.
Part PAR_42: The present invention also includes modifications and improvements to the system 10. For instance, an I/O device generally has an IRQ output (Interrupt Request output, such as R96MFX's IRQ pin). In the traditional design, the IRQ output is connected to the PIC 25, and causes the CPU 15 to execute an interrupt service for this I/O device only. It therefore becomes possible to connect IRQ outputs of eight modems 20, 30 and 50 to an 8-bit data buffer (such as 74LS244 of Texas Instruments). Then, in the interrupt service, the CPU 15 reads the data buffer and determines which modems 20, 30 or 50 have requests, and accelerates the interrupt process. Here, the IRQ output is the indicator of the I/O devices.
Part PAR_43: Some I/O devices work slowly and allow longer period Ti after they signify the requests, such as during the R96MFX modem transmits the facsimile handshake signal at 300 bps. In this case, the CPU 15 may not check this facsimile modem at the period T. For example, the CPU 15 skip a few interrupt services of the Timer 24, then checks this modem afterwards. However, the CPU 15 does not skip the interrupt service of the remaining facsimile modems.
Part PAR_44: The timer 24 may have a shorter period T that is shorter than half of the period Ti of the facsimile modem (T&lt;Ti/2). In this example, there are at least two interrupts within the period Ti, and the interrupt service might not process the request when it first detects the request, but it can process the request during the following interrupt services.
Part PAR_45: In the embodiment of fax-on-demand, when the processor supports one modem, its period is T, but when the processor supports 32 modems, its period remains T, and the number of interrupts is identical in both cases. So the number of interrupts for the processor does not increase, i.e., overload, when the number of modems increase in a computer system. For example , if the processor supports 32 facsimile modems, in one (1) second, in our method the computer receives about 1s/0.63 ms=1587 interrupts, (i.e., the computer receives one interrupt in each 630 us); but in the conventional design the computer receives 32*1s/0.83 ms=38554 interrupts, (i.e., the computer receives one interrupt in each average 26 us).
Part PAR_46: The present system 10 may be used in various commercial applications. A few of these applications are described below.
Part PAL: Network Facsimile Servers
Part PAR_47: Network facsimile servers are becoming increasingly popular for providing means with which to control and optimize facsimile communication. The user simply indicates the facsimile number, and the facsimile server does the rest. Incoming facsimiles can be directed back to individual workstations as well.
Part PAL_2: E-Mail Facsimile Gateways
Part PAR_48: With an E-mail facsimile gateway a business can expand its mail system by adding facsimile as an additional messaging capability. This extends the convenience of E-mail communications beyond the network boundaries. With an E-mail facsimile gateway, all users can send and receive facsimiles from within the E-mail package.
Part PAL_3: Mini/Mainframe Facsimile Servers
Part PAR_49: Many mini/mainframe facsimile servers work in the same way as LAN-facsimile servers: users can send and receive facsimiles from their terminals.
Part PAL_4: Broadcast/High-Volume Faxing
Part PAR_50: This feature is used to send the same information to a large number of people (fax telemarketing).
Part PAL_5: Facsimile on Demand
Part PAR_51: For example, a publisher wishes to deliver information upon requests from subscribers, users or members of the public. The system 10 enables public selective access of the informed desired to be delivered or published.
Part PAL_6: Facsimile Mailbox/Multi-Media Mailbox
Part PAR_52: Using this system, a user is able to retrieve his or her facsimiles from any remote location.
Part PAL_7: Digital Store-and-Forward (Via Packet Networks)
Part PAR_53: This feature is particularly useful for international facsimile traffic. The facsimiles are sent over data networks as data packets. One such facsimile packet-switched node is described in the co-pending patent application Ser. No. 08/210,889 filed on Mar. 18, 1994, by the same application, which is incorporated herein by reference in its entirety.
Part PAL_8: Store-and-Forward
Part PAR_54: By using this feature, the system 10 is capable of receiving a facsimile and forwarding or broadcasting it to other users in the system.
Part PAR_55: While specific embodiments of the system with multiple I/O devices have been illustrated and described in accordance with the present invention, modifications and changes of the apparatus, parameters, use and operation will become apparent to those skilled in the art, without departing from the scope of the invention.


{'bibliographic_information': "{'Patent Number': '060056746', 'Series Code': '8', 'Application Number': '6076289', 'Application Type': '1', 'Art unit': '272', 'Application Filing Date': '19960227', 'Title of Invention': 'System architecture for multiple input/output devices', 'Issue Date': '19991221', 'Number of Claims': '16', 'Exemplary Claim Number(s)': '1', 'Assistant Examiner': 'Nguyen; Madeleine Au', 'Primary Examiner': 'Coles; Edward L.', 'Number of Drawing Sheets': '3', 'Number of figures': '3'}", 'source_file': './grant/1999/pftaps19991221_wk51.txt', 'source_data': 'USPTO-Grant'}