Abstract
Abstract− The design and implementation of a CMOS currentmode fourth-order Butterworth continuous-time leap-frog (LF) multiple loop feedback (MLF) lowpass filter is described. The filter is implemented using a fully-differential linear, low voltage and low power operational transconductance amplifier (OTA). PSpice simulations using a standard TSMC 0.18µm CMOS process with 1.5V power supply have shown that the cut-off frequency of the filter ranges from 240MHz to 300MHz and dynamic range is about 58dB at 240MHz of cut-off frequency. The power consumption of the filter is only from 22.3 to 55mW. The total output noise density is about 390nA/√Hz.
I. INTRODUCTION
Ultra wideband (UWB) is an upcoming standard for shortrange, high data rate communications link. Recently, UWB technologies have attracted considerable attention [1] . In order to achieve the highest integration for UWB receivers, the direct down-conversion architecture is used. As can be seen from the Figure 1 , the analogue baseband block of the receiver is composed of variable gain amplifiers (VGA) and lowpass filters. The VGAs increase the signal amplitude, while the lowpass filter reduces the amount of the out-ofband signal in order to increase the dynamic range available for the useful signal. The VGA design has been well studied in the literature [2, 3] . For UWB analogue front-end, the variable gain range does not need to be very large; thus the implementation of VGA is not critical. Therefore, the lowpass filter design becomes the most critical in the analogue baseband. The Gm-C based lowpass filter is the only option as the cut-off frequency of filter access to a few hundred megahertz. Although there are a few high performances Gm-C filter can be also found in the literature [4] [5] [6] [7] [8] [9] [10] , they all suffer from the relatively high power consumptions. In order to minimize the power consumption, both operational transconductance amplifiers (OTAs) and filters need to be designed carefully. At the OTA design point of view, the lower supply voltage leads the low power consumption. However, most of the specifications of the OTA rely strongly on the supply voltage. The performances Figure 1 Receiver channels of the OTA are decreased with the low supply voltage. Moreover, large transconductances are needed for the implementation of high-frequency filters. The implementation of large transconductances requires the use of wider transistors and large tail currents. The use of small transistor lengths pushes the parasitic poles to higher frequencies, but the OTA dc gain is reduced and mobility degradation effects become more severe. On the other hand, the use of large drain currents reduces even further the transistor dc gain and increases the power consumption. At the filter design point of view, the sensitivity and parasitic effects are important. The cascade method has been widely used for wireless communication and computer hard disk drive (HDD) design [4] [5] [6] . However, the cascade suffers from the relative high sensitivity, especially as filters order increasing. The LC ladder simulation method is insensitive, but the floating capacitors are needed, which is sensitive to the parasitic effects [7, 8] . Moreover, converting the passive components into OTA leads significant power consumption. The multiple loop feedback (MLF) based configurations are insensitive and can be used for very high frequency (VHF) as well as low power consumption applications [9, 10] . All the high impedance nodes are grounded with capacitors, thus the parasitic effects are minimum. Therefore, we proposed a fourth-order Gm-C lowpass filter based on leap-frog (LF) MLF configuration in this paper. The Nauta OTAs are used to implement the filter. The cut-off frequency of 240MHz with 22.3mW power consumption is achieved. Both of the filter and OTA are designed in standard TSMC 0.18µm process and the cut-off frequency of the filter can also be controlled in the range of 240-300MHz. The design of a fully-balanced Nauta OTA is discussed in Section II. Filter architecture and synthesis are described in Section III. The simulation results are given in Section IV, and finally conclusions are given in Section V.
II. FULLY-BALANCED NAUTA OTA
The differential transconductance circuit described by Nauta [11] was selected for this filter. This circuit has advantages for high frequency designs using deepsubmicron CMOS technology; there are no internal nodes to give rise to parasitic poles, the relatively high output conductance of sub-micron MOSFETs can be compensated by choosing transistor sizes appropriately, and large input and output voltage swings are possible for a given supply voltage. The transconductance of the Nauta OTA is dependant on the supply voltage V dd , which provides a means of tuning the filter. The basis of the Nauta OTA is a differential transconductor using two inverters, g1, and g2, as shown in Figure 2 . 
II. FULLY-BALANCED NAUTA OTA
where W p , L p , W n , L n are the widths and lengths of the Pand N-channel devices, and K p , K n are approximately µC ox /2 for the P-and N-channel devices respectively, the transfer function of the transconductor can be calculated: 
II. FULLY-BALANCED NAUTA OTA
Thus all the non-linear terms cancel in the differential output current (I o+ -I o-), being present only as equal commonmode components in I o+ and I o-. The linearity of the differential transfer function is independent of matching between the P-and N-channel devices, provided both have a square law response. Since in practice the OTA will be used as an integrator with a capacitive load, it is necessary to set V cm so that the output current is zero with zero differential input voltage, in order to avoid the capacitors charging. The value of V cm at which I o+ and I o-are zero is found by setting I dn = I dp :
II. FULLY-BALANCED NAUTA OTA
If a number of integrators using these OTAs are connected in a network with overall negative feedback, the quiescent operating point of the transconductors will then be V cm . If K n W n /L n is made equal to K p W p /L p , and V tn = V tp (for normal CMOS processes the threshold voltages of the Pand N-channel devices are nominally equal), this reduces to V cm = V dd /2. This is desirable for a practical circuit, since with the quiescent operating point of the inverters set midway between the supply rails, the maximum symetrical output voltage swing is available. Assuming this condition is used in practice, putting these values into (3) and differentiating gives the small-signal transconductance:
II. FULLY-BALANCED NAUTA OTA
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II. FULLY-BALANCED NAUTA OTA
Transconductance g m is thus proportional to supply voltage V dd ; clearly this is only true as long as the transistors remain in saturation, which limits the minimum supply voltage and transconductance which can be used; reducing the supply voltage also reduces the available input and output voltage swing. The two-inverter transconductor by itself has common-mode gain equal to the differential mode gain, i.e. common-mode rejection of 0dB. This is undesirable, since under large-signal conditions in a multi-stage filter, the common-mode square law distortion terms could sum together and become large. Additionally, especially for dep sub-micron geometry devices, the output resistance of the inverters is quite low, leading to low integrator DC gain, and correspondingly low Q. The addition of four more inverters g m3 -g m6 provides control of common-mode gain, and output resistance, as shown in the complete Nauta OTA circuit in Figure 3 . Therefore if g m6 is made slightly larger so that g m6 = g m5 + g o1 , the output current will be zero, and the output resistance infinite. However, for a common-mode signal V cm applied to both outputs is expressed in (7) . So the output of g 1 is effectively loaded by a resistance 1/(g o1 +g m5 +g m6 ) for common-mode signals, while simultaneously for differential-mode signals the DC output resistance can be made infinite by suitable sizing of g m5 and g m6 . The same function is performed for the non-inverting output by g m3 and g m4 . Making g m3 -g m6 larger results in lower commonmode gain, but greater power consumption, chip area and parasitic capacitance, and also requires better matching between transconductors. As a compromise, the area of g m3 -g m6 was made approximately half that of g m1 , g m2 , yielding a common-mode gain of around unity. The widths of g m3 and g m6 were increased empirically, and the open-loop gain of the complete OTA plotted, to find the optimum sizes for maximizing the low frequency gain and therefore the output resistance.
II. FULLY-BALANCED NAUTA OTA
) ( 
II. FULLY-BALANCED NAUTA OTA
The fully balanced realization of the function in (8) using the current-mode LF MLF configuration is shown in Figure  4 .
II. FULLY-BALANCED NAUTA OTA
The overall transfer function of the circuit can be derived as The design formulae for the filter can be attained by coefficient matching between (8) and (9) 
II. FULLY-BALANCED NAUTA OTA
The filter is designed with identical unit OTAs using the CMOS OTA cell in Figure 3 to improve OTA matching and facilitate design automation. The cut-off frequency of the filter is chosen around 240 MHz. Using the computed parameter values in (10) and choosing identical transconductance of 1.5mS for g i (i=1,2…4) the capacitor values can be calculated, but the parasitic capacitance must also be taken into account. For the circuit of Figure 3 , the parasitic capacitance is about 0.1pF. The capacitance values are recalculated below: C 1 =0.6612pF, C 2 =2.0534pF, C 3 =3.0378pF, C 4 =2.9452pF.
IV. SIMULATION RESULTS
The circuit was designed and simulated using BSIM 3v3 Spice models for a TSMC 0.18µm CMOS process available from MOSIS [13] . Figure 5 shows the magnitude response of the filter with differential supply voltage. As can be seen from Figure 5 , by varying the supply voltage of the unit OTA cell, the tuning range of cut−off frequency is around 240−300MHz. The maximum total power consumption of the filter is about 55mW at 300MHz of cut-off frequency and the minimum total power consumption of the filter is about only 22.3mW at 240MHz of cut-off frequency for a single 1.5V power supply. Simulation of the filter has also shown a total harmonic distortion (THD) of less than 1% with a single tone of 750µA. The dynamic range is about 58dB at f c =240MHz. The performance of the filter offers significant improvements; especially the power consumption is smaller than other designs in the literature, making the presented filter well suitable for portable electronics products. This paper has described a 240MHz current-mode fullybalanced fourth-order Butterworth lowpass filter based on the LF MLF configuration, applied to the UWB applications. A linear single stage Nauta OTA with a typically large transconductance has been used. Simulation results using 1.5V 0.18µm CMOS show that the power consumption of proposed filter is about 22.3mW at f c = 240MHz. The frequency tuning range is from 240MHz to 300MHz. These results have shown that the current-mode MLF LF filter can achieve very high frequency with relatively low power consumption and may become one of the filtering solutions for future UWB systems.

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