Title: 4 bit magnitude comparator VHDL
Tags: vhdl;comparator;magnitude
Question: I have to make a 4bit magnitude comparator in VHDL with only concurrent statements (no if/else or case/when).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Exercise is
port (  A : in std_logic_vector (3 downto 0);
B : in std_logic_vector (3 downto 0);
Ag : out std_logic;
Bg : out std_logic;
AeqB: out std_logic
);
end Exercise;
architecture Comparator of Exercise is
Ag <= '1'when (A&gt;B) else '0';
Bg <= '1' when (B&gt;A) else '0';  --Problem: Here if i sumulate B="ZZZZ", Bg is 1, asi if B&gt;A
AeqB<= '1' when (A=B) else '0';
end Comparator;
The problem is that i need to take in count all the other values of std_logic (U,X,Z,W,L,H,-), i know there is the others but cant figure it out how to make the comparator with with/select statement.
Thanks
Comment: Generally a std_logic_vector  can be considered unsigned by using package numeric_std_unsigned (-2008), which uses numeric_std calls with type conversions to unsigned for various operators including relational operators. This is a collision between meta values and binary values which numeric_std resolves as FALSE if either operand contains meta values. The default operators (IEEE Std 1076-2008 9.2.3 Relational operators in this case) are pure positional - order in the enumerated std_ulogic type definition, and 'Z' has a higher position than '1' or '0'.

Comment: VHDL2008 support is still lacking in many tools, including Xilinx, so you may not want to use numeric_std_unsigned just yet.

Comment: If your definition of magnitude is the usual arithmetic one, then you would be better using numeric_std which will treat your vectors as numeric data. You then have to decide whether they are signed or unsigned numbers, and declare them as `signed` or `unsigned` respectively (or perform type conversions to the appropriate form).


Here is another answer: library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comp_4 is
port (  A:IN STD_LOGIC_VECTOR(0 to 3);
B:IN STD_LOGIC_VECTOR(0 to 3);
ET:OUT STD_LOGIC;
GT:OUT STD_LOGIC;
LT:OUT STD_LOGIC);
end comp_4;
architecture dataflow of comp_4 is
begin
with A-B(0 to 3) select
ET <=   '1' when "0000",
'0' when others;
with A &gt; B select
GT <=   '1' when true,
'0' when others;
with A < B select
LT <=   '1' when true,
'0' when others;
end dataflow;
Comment for this answer: The code I have written is trying to model a 4 bit comparator using the with - select - when statement. The entity definition is pretty straightforward.

Here is another answer: In general you can 'convert' the various values that std_logic can take into either 0 or 1 using the to_01 function. I think it's in package numeric_std.

{'source': 'StackExchangeDataset', 'subset': 'stackoverflow.com', 'metadata': {'AnswerCount': 2, 'CommentCount': 3, 'ContentLicense': 'CC BY-SA 3.0', 'CreationDate': '2015:00:06/27/15', 'FavoriteCount': 1.0, 'PostTypeId': 1, 'Tags': '<vhdl><comparator><magnitude>', 'Title': '4 bit magnitude comparator VHDL', 'ViewCount': 10230, 'id': 31092840, 'user_AboutMe': None, 'user_AccountId': 5867046.0, 'user_DisplayName': 'rockstiff', 'user_Reputation': 325.0, 'user_Views': 29.0, 'user_id': 4620644.0}}