nyu-dice-lab/Qwen-2.5-Instruct-Mix-Verilog-Reasoning-GT-7B Text Generation • 8B • Updated May 14 • 1
nyu-dice-lab/Qwen-2.5-Instruct-Unverified-Verilog-Reasoning-GT-7B Text Generation • 8B • Updated May 13 • 2
nyu-dice-lab/Qwen-2.5-Instruct-Unverified-Verilog-GT-7B Text Generation • 8B • Updated May 13 • 1
nyu-dice-lab/Qwen-2.5-Instruct-Multishot-First-Reasoning-7Bv2 Text Generation • 8B • Updated May 11 • 2
nyu-dice-lab/Mistral-Instruct-v0.3-Verilog-Reasoning-7B Text Generation • 7B • Updated May 10 • 2
nyu-dice-lab/Qwen-2.5-Instruct-Multishot-First-Reasoning-7B Text Generation • 8B • Updated May 10 • 1
nyu-dice-lab/Qwen-2.5-Instruct-Multishot-Last-Reasoning-7B Text Generation • 8B • Updated May 10 • 2
nyu-dice-lab/Qwen-2.5-Instruct-Verilog-Reasoning-7B-Mix-20K Text Generation • 8B • Updated May 10 • 5
nyu-dice-lab/Qwen-2.5-Instruct-Multishot-First-Instruction-7B Text Generation • 8B • Updated May 10 • 2
nyu-dice-lab/Qwen-2.5-Instruct-Multishot-Last-Instruction-7B Text Generation • 8B • Updated May 10 • 2