"
],
"text/html": [
"\n",
" \n",
" \n",
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" [9198/9198 59:32, Epoch 3/3]\n",
"
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" \n",
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" \n",
" Epoch | \n",
" Training Loss | \n",
" Validation Loss | \n",
"
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" \n",
" \n",
" \n",
" 1 | \n",
" 0.982200 | \n",
" 0.913574 | \n",
"
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" \n",
" 2 | \n",
" 0.886600 | \n",
" 0.837943 | \n",
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" 3 | \n",
" 0.817100 | \n",
" 0.816834 | \n",
"
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" \n",
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]
},
"metadata": {}
},
{
"output_type": "execute_result",
"data": {
"text/plain": [
"TrainOutput(global_step=9198, training_loss=0.9767863951083965, metrics={'train_runtime': 3576.5038, 'train_samples_per_second': 5.143, 'train_steps_per_second': 2.572, 'total_flos': 4389900065280000.0, 'train_loss': 0.9767863951083965, 'epoch': 3.0})"
]
},
"metadata": {},
"execution_count": 12
}
]
},
{
"cell_type": "code",
"source": [
"import math\n",
"eval_results = trainer.evaluate()\n",
"print(f\"Perplexity: {math.exp(eval_results['eval_loss']):.2f}\")"
],
"metadata": {
"colab": {
"base_uri": "https://localhost:8080/",
"height": 54
},
"id": "e8zjETMYVkiC",
"outputId": "a7633c8b-5710-43ef-f8d4-b48f716cef43"
},
"execution_count": 13,
"outputs": [
{
"output_type": "display_data",
"data": {
"text/plain": [
""
],
"text/html": [
"\n",
" \n",
" \n",
"
\n",
" [192/192 01:51]\n",
"
\n",
" "
]
},
"metadata": {}
},
{
"output_type": "stream",
"name": "stdout",
"text": [
"Perplexity: 2.26\n"
]
}
]
},
{
"cell_type": "code",
"source": [
"trainer.push_to_hub()"
],
"metadata": {
"colab": {
"base_uri": "https://localhost:8080/"
},
"id": "-GfBv0XUCmS0",
"outputId": "fb2aa31d-5b90-4b5a-a203-1d75f32faa33"
},
"execution_count": null,
"outputs": [
{
"output_type": "stream",
"name": "stderr",
"text": [
"Several commits (2) will be pushed upstream.\n",
"WARNING:huggingface_hub.repository:Several commits (2) will be pushed upstream.\n",
"The progress bars may be unreliable.\n",
"WARNING:huggingface_hub.repository:The progress bars may be unreliable.\n"
]
}
]
},
{
"cell_type": "markdown",
"source": [
"Testing the model"
],
"metadata": {
"id": "GI7L2JxvpWZi"
}
},
{
"cell_type": "code",
"source": [
"prompt = 'library IEEE;\\nuse IEEE.STD_LOGIC_1164.ALL;\\nentity XOR_BitABit is\\nPort ( A : in STD_LOGIC_VECTOR (3 downto 0);\\nB : in STD_LOGIC_VECTOR (3 downto 0);\\nZ : out STD_LOGIC_VECTOR (3 downto 0));\\nend XOR_BitABit;\\narchitecture Behavioral of XOR_BitABit is\\nsignal Zout : STD_LOGIC_VECTOR(3 downto 0);\\nbegin\\nZout(0) <= A(0) XOR B(0);\\nZout(1) <= A(1) XOR B(1);\\nZout(2) <= A(2) XOR B(2);\\nZout(3) <= A(3) XOR B(3);\\nZ <= Zout;\\nend Behavioral;'\n",
"\n",
"from transformers import AutoModelForCausalLM, TrainingArguments, Trainer, pipeline, AutoTokenizer\n",
"model = AutoModelForCausalLM.from_pretrained('/content/drive/MyDrive/LLM_project/gpt2_hdl/')\n",
"tokenizer = AutoTokenizer.from_pretrained('gpt2')\n",
"inputs = tokenizer(prompt, return_tensors='pt').input_ids\n",
"output = model.generate(inputs, max_length = 500)"
],
"metadata": {
"id": "zENqnxJtFe92"
},
"execution_count": null,
"outputs": []
},
{
"cell_type": "code",
"source": [
"tokenizer.batch_decode(output, skip_special_tokens=True)"
],
"metadata": {
"colab": {
"base_uri": "https://localhost:8080/"
},
"id": "E_zNFE4enyKP",
"outputId": "1ba920c6-7373-4a84-987d-c55233d316f7"
},
"execution_count": 16,
"outputs": [
{
"output_type": "execute_result",
"data": {
"text/plain": [
"['library IEEE;\\nuse IEEE.STD_LOGIC_1164.ALL;\\nentity XOR_BitABit is\\nPort ( A : in STD_LOGIC_VECTOR (3 downto 0);\\nB : in STD_LOGIC_VECTOR (3 downto 0);\\nZ : out STD_LOGIC_VECTOR (3 downto 0));\\nend XOR_BitABit;\\narchitecture Behavioral of XOR_BitABit is\\nsignal Zout : STD_LOGIC_VECTOR(3 downto 0);\\nbegin\\nZout(0) <= A(0) XOR B(0);\\nZout(1) <= A(1) XOR B(1);\\nZout(2) <= A(2) XOR B(2);\\nZout(3) <= A(3) XOR B(3);\\nZ <= Zout;\\nend Behavioral;\\n\\nThe given HDL code is for a hardware design that implements a bit-wise AND operation between two input vectors. \\n\\nThe entity declaration defines the inputs and outputs of the design. It has two ports: A and B, which are input vectors of type STD_LOGIC_VECTOR. \\n\\nThe architecture declaration defines the behavior of the design. It uses the IEEE.STD_LOGIC_1164 library for standard logic operations. \\n\\nThe architecture section defines the behavior of the design. It uses the behavioral package to implement the bit-wise AND operation between two input vectors. \\n\\nThe architecture section also includes a signal named Zout, which is an input vector of type STD_LOGIC_VECTOR. \\n\\nOverall, this HDL code implements a bit-wise AND operation between two input vectors. It performs the bit-wise AND operation on the input vectors A and B, and assigns the result to the output vector Zout. \\n\\nOverall, this HDL code implements a bit-wise AND operation between two input vectors. It performs the bit-wise AND operation on the input vectors A and B, and assigns the result to the output vector Zout. \\n\\nOverall, this HDL code implements a bit-wise AND operation between two input vectors. It performs the bit-wise AND operation on the input vectors A and B, and assigns the result to the output vector']"
]
},
"metadata": {},
"execution_count": 16
}
]
},
{
"cell_type": "code",
"source": [
"prompt = 'Implement a full adder circuit in HDL. A and B are the inputs, Cin in the input carray and S and Cout are output sum and carry respectively'\n",
"inputs = tokenizer(prompt, return_tensors='pt').input_ids\n",
"output = model.generate(inputs, max_length = 500)\n",
"print('\\n\\n')\n",
"tokenizer.batch_decode(output, skip_special_tokens=True)"
],
"metadata": {
"colab": {
"base_uri": "https://localhost:8080/"
},
"id": "72lgmFgOoS-t",
"outputId": "7a810124-a1c6-4208-afc0-aca4934f727d"
},
"execution_count": 18,
"outputs": [
{
"output_type": "stream",
"name": "stdout",
"text": [
"\n",
"\n",
"\n"
]
},
{
"output_type": "execute_result",
"data": {
"text/plain": [
"[\"Implement a full adder circuit in HDL. A and B are the inputs, Cin in the input carray and S and Cout are output sum and carry respectively.\\n\\nThe circuit should have the following inputs and outputs:\\n\\nInputs:\\n- Cin: a single bit input representing the input signal\\n- S: a single bit input representing the input signal\\n- Cout: a single bit input representing the output signal\\n\\nOutputs:\\n- Cout: a single bit output representing the output signal\\n\\nThe circuit should have the following outputs:\\n- Cout: a single bit output representing the output signal\\n\\nThe circuit should be implemented using VHDL.\\nlibrary ieee;\\nuse ieee.std_logic_1164.all;\\n\\nentity adder is\\n\\tport (\\n\\t\\tCin : in std_logic_vector(3 downto 0);\\n\\t\\tS : in std_logic_vector(3 downto 0);\\n\\t\\tCout : out std_logic_vector(3 downto 0)\\n\\t);\\nend adder;\\n\\narchitecture rtl of adder is\\nbegin\\n\\tCout <= Cin when S = '1' else Cout;\\n\\tCout <= Cin when S = '0' else Cout;\\nend rtl;\\n\\nThe given HDL code is for a full adder circuit. \\n\\nThe entity declaration defines the inputs and outputs of the circuit. \\n\\nThe inputs Cin and S are of type std_logic_vector and are of type std_logic_vector. \\n\\nThe inputs Cin and S are of type std_logic_vector and are of type std_logic_vector. \\n\\nThe architecture section of the code defines the behavior of the circuit. \\n\\nThe architecture section includes a process block that triggers on the rising edge of the input signal Cin. \\n\\nInside the process block, there is a process statement that triggers on the rising edge of the input signal Cin. \\n\\nInside the process block, there is a process statement that triggers on the rising edge of the input signal Cin. \\n\\nInside the process block, there is a process statement that triggers on the rising edge of the input signal Cin. \\n\\nInside the process block, there is\"]"
]
},
"metadata": {},
"execution_count": 18
}
]
},
{
"cell_type": "code",
"source": [
"prompt = 'library IEEE;\\nuse IEEE.STD_LOGIC_1164.ALL;\\nentity XOR_BitABit is\\nPort ( A : in STD_LOGIC_VECTOR (3'\n",
"inputs = tokenizer(prompt, return_tensors='pt').input_ids\n",
"output = model.generate(inputs, max_length = 200)\n",
"tokenizer.batch_decode(output, skip_special_tokens=True)"
],
"metadata": {
"colab": {
"base_uri": "https://localhost:8080/"
},
"id": "5gVMAoVTpaFl",
"outputId": "f4732bae-766d-47a5-a507-d76630077ea9"
},
"execution_count": 19,
"outputs": [
{
"output_type": "execute_result",
"data": {
"text/plain": [
"['library IEEE;\\nuse IEEE.STD_LOGIC_1164.ALL;\\nentity XOR_BitABit is\\nPort ( A : in STD_LOGIC_VECTOR (3 downto 0);\\n\\t\\t\\tB : in STD_LOGIC_VECTOR (3 downto 0);\\n\\t\\t\\tC : in STD_LOGIC_VECTOR (3 downto 0);\\n\\t\\t\\tD : in STD_LOGIC_VECTOR (3 downto 0);\\n\\t\\t\\tE : in STD_LOGIC_VECTOR (3 downto 0);\\n\\t\\t\\tF : in STD_LOGIC_VECTOR (3 downto 0);\\n\\t\\t\\tG : in STD_LOGIC_VECTOR (3 downto 0);\\n\\t\\t\\tH : in STD_LOGIC_VECTOR (3 downto 0']"
]
},
"metadata": {},
"execution_count": 19
}
]
},
{
"cell_type": "markdown",
"source": [
"The model is repeating the same thing, Let's try changin top_k and top_p"
],
"metadata": {
"id": "eBHLqfNepx-X"
}
},
{
"cell_type": "code",
"source": [
"prompt = 'library IEEE;\\nuse IEEE.STD_LOGIC_1164.ALL;\\nentity XOR_BitABit is\\nPort ( A : in STD_LOGIC_VECTOR (3'\n",
"inputs = tokenizer(prompt, return_tensors='pt').input_ids\n",
"output = model.generate(inputs, max_length = 200, do_sample=True, top_k = 0, top_p = 0.95)\n",
"tokenizer.batch_decode(output, skip_special_tokens=True)"
],
"metadata": {
"colab": {
"base_uri": "https://localhost:8080/"
},
"id": "q8ns1bgRoS8k",
"outputId": "fdbbd101-bf55-4ea0-f5d8-02e4245c5290"
},
"execution_count": 23,
"outputs": [
{
"output_type": "execute_result",
"data": {
"text/plain": [
"['library IEEE;\\nuse IEEE.STD_LOGIC_1164.ALL;\\nentity XOR_BitABit is\\nPort ( A : in STD_LOGIC_VECTOR (3 downto 0);\\n\\t\\tB : in STD_LOGIC_VECTOR (3 downto 0);\\n\\t\\tH : out STD_LOGIC_VECTOR (2 downto 0);\\n\\t\\tR : out STD_LOGIC_VECTOR (2 downto 0));\\nend XOR_BitABit;\\n\\narchitecture Behavioral of XOR_BitABit is\\nbegin\\n\\n\\tR <= A;\\n\\tH <= b;\\n\\nend Behavioral;\\n\\n\\nThis HDL code represents an asynchronous bit-bit multiplication operation. \\n\\nThe code describes a simple operation that is implemented using the entity declaration and port declaration. The entity declaration defines the inputs and outputs of the operation. \\n\\nInside']"
]
},
"metadata": {},
"execution_count": 23
}
]
},
{
"cell_type": "code",
"source": [
"prompt = 'summarize this library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.randgen_package.all; entity chaoticMap is Port ( clk : in std_logic; reset : in std_logic; output : out std_logic); end chaoticMap; architecture Behavioral of chaoticMap is -- Supposing 2 integer bits and two\\'s complement, the constants -- correspond to zero, one and minus one values constant zero : signed(N_BIT-1 downto 0) := (others => \\'0\\'); constant one : signed(N_BIT-1 downto 0) := (N_BIT-2 => \\'1\\', others => \\'0\\'); constant minusone : signed(N_BIT-1 downto 0) := (N_BIT-1 => \\'1\\', N_BIT-2 => \\'1\\', others => \\'0\\'); -- Stores the current state signal reg : signed(N_BIT-1 downto 0); begin -- update map proc_map: process(clk,reset) begin if reset = \\'0\\' then if rising_edge(clk) then -- 1.875 * reg = (2*reg) - (reg/8) = (reg<<1) - (reg>>3) if (reg < zero) then -- reg = 1.875 * reg + 1 reg <= (( reg(N_BIT-2 downto 0) & \"0\" ) - ( \"111\" & reg(N_BIT-1 downto 3) )) + one; else -- reg = 1.875 * reg - 1 reg <= (( reg(N_BIT-2 downto 0)&\\'0\\' ) - ( \"000\" & reg(N_BIT-1 downto 3) )) + minusone; end if; end if; else -- init reg <= X0; end if; end process; output <= reg(N_BIT-1); end Behavioral;'\n",
"inputs = tokenizer(prompt, return_tensors='pt').input_ids\n",
"output = model.generate(inputs, max_length = 1000, do_sample=True, top_k = 0, top_p = 0.95, temperature = 0.9)\n",
"tokenizer.batch_decode(output, skip_special_tokens=True)"
],
"metadata": {
"colab": {
"base_uri": "https://localhost:8080/"
},
"id": "AyumjC72oS5J",
"outputId": "c8d625a1-2465-44e3-849f-18ca61cf6e28"
},
"execution_count": 29,
"outputs": [
{
"output_type": "execute_result",
"data": {
"text/plain": [
"['summarize this library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.randgen_package.all; entity chaoticMap is Port ( clk : in std_logic; reset : in std_logic; output : out std_logic); end chaoticMap; architecture Behavioral of chaoticMap is -- Supposing 2 integer bits and two\\'s complement, the constants -- correspond to zero, one and minus one values constant zero : signed(N_BIT-1 downto 0) := (others => \\'0\\'); constant one : signed(N_BIT-1 downto 0) := (N_BIT-2 => \\'1\\', others => \\'0\\'); constant minusone : signed(N_BIT-1 downto 0) := (N_BIT-1 => \\'1\\', N_BIT-2 => \\'1\\', others => \\'0\\'); -- Stores the current state signal reg : signed(N_BIT-1 downto 0); begin -- update map proc_map: process(clk,reset) begin if reset = \\'0\\' then if rising_edge(clk) then -- 1.875 * reg = (2*reg) - (reg/8) = (reg<<1) - (reg>>3) if (reg < zero) then -- reg = 1.875 * reg + 1 reg <= (( reg(N_BIT-2 downto 0) & \"0\" ) - ( \"111\" & reg(N_BIT-1 downto 3) )) + one; else -- reg = 1.875 * reg - 1 reg <= (( reg(N_BIT-2 downto 0)&\\'0\\' ) - ( \"000\" & reg(N_BIT-1 downto 3) )) + minusone; end if; end if; else -- init reg <= X0; end if; end process; output <= reg(N_BIT-1); end Behavioral;\\n\\nArchitecture Behavioral of chaoticMap is\\n\\nbegin -- update proc_map proc_map: process is\\n begin\\n if proc_map = \\'1\\' then\\n output <= \\'0\\';\\n\\treg <= (reg<<1);\\nelse\\n\\treg <= 0;\\nend if;\\nend Behavioral;\\n\\nThe given HDL code is an HDL (Hardware Description Language) code for a generic map with a 2-bit input and 2-bit output. \\n\\nThe entity \"Behavioral\" defines the interface \"genericMap\" and the ports \"clk,reset\" and \"output\" are of type std_logic. The architecture \"Behavioral\" implements the functionality of the generic map.\\n\\nThe architecture \"Behavioral\" instantiates the generic map \"genmap\" with a single input port \"clk\" and a select port \"output\" as an additional output port. The output is of type std_logic and has the same value as the corresponding input port \"clk\". The gen map component in the architecture \"Behavioral\" includes an input port \"reg\", which represents the current state of the map. When the clock signal \"reset\" is high, the output \"output\" is set to the state specified by the \"reg\" type TTX and the input port \"clk\" is connected to the input port \"output\". The gen map component in the architecture \"Behavioral\" uses the \"reg\" type to store the current state of the map.\\n\\nThe actual implementation of the generic map circuit is not specified. It is assumed that the generic map circuit has the appropriate inputs and outputs.\\n\\nOverall, this HDL code represents a generic map for a 2-bit input map based on the input signals and an output port. The gen map component can be instantiated with either a 2-bit or 4-bit input and output ports. The output ports can be any of the multiplexers specified in the generic map component.\\n\\nIn summary, this HDL code describes an entity that maps a 2-bit input and a 4-bit output using the generic map. It enables the use of a generic map component for generating different values based on the input signals and provides an output signal, that could be used in a system simulation environment to test the functionality of the 2-bit input and output ports in a system simulation.\\n\\nOverall, this HDL code provides a generic map for a 2-bit input map based on the input signals and an output port for instantiating it. It provides the inputs and outputs of the 2-bit input and a generic map component for instantiating the generated 4-bit input and output ports using the gen map component. This enables the useiction of different sizes and sizes of different input signals to control the different output port']"
]
},
"metadata": {},
"execution_count": 29
}
]
},
{
"cell_type": "code",
"source": [
"prompt = 'summarize the hdl code \\n library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;\\nentity ROM is generic ( DATA_WIDTH : positive := 8; -- Width of data bus ADDR_WIDTH : positive := 10; -- Width of address bus FILE_NAME : string := \"data.txt\" -- External initialization file name ); port ( address : in std_logic_vector(ADDR_WIDTH - 1 downto 0); data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0) ); end ROM;\\narchitecture Behavioral of ROM is type memory_array is array (0 to 2**ADDR_WIDTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0); signal memory : memory_array; \\n procedure initialize_memory(file_name : string) is file data_file : text; variable line_buf : line; variable data_value : std_logic_vector(DATA_WIDTH - 1 downto 0); begin file_open(data_file, file_name, read_mode); for i in 0 to memory high loop readline(data_file, line_buf); read(line_buf, data_value); memory(i) <= data_value; end loop; file_close(data_file); end initialize_memory; \\n begin initialize_memory(FILE_NAME); \\n process(address) begin data_out <= memory(to_integer(unsigned(address))); end process; end Behavioral;'\n",
"inputs = tokenizer(prompt, return_tensors='pt').input_ids\n",
"output = model.generate(inputs, max_length = 1000, do_sample=True, top_k = 0, top_p = 0.95, temperature = 0.9)\n",
"tokenizer.batch_decode(output, skip_special_tokens=True)"
],
"metadata": {
"colab": {
"base_uri": "https://localhost:8080/"
},
"id": "1qygiBRroS3g",
"outputId": "06c46465-37c3-4e17-e8b8-cdac9ea3d367"
},
"execution_count": 31,
"outputs": [
{
"output_type": "execute_result",
"data": {
"text/plain": [
"['summarize the hdl code \\n library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;\\nentity ROM is generic ( DATA_WIDTH : positive := 8; -- Width of data bus ADDR_WIDTH : positive := 10; -- Width of address bus FILE_NAME : string := \"data.txt\" -- External initialization file name ); port ( address : in std_logic_vector(ADDR_WIDTH - 1 downto 0); data_out : out std_logic_vector(DATA_WIDTH - 1 downto 0) ); end ROM;\\narchitecture Behavioral of ROM is type memory_array is array (0 to 2**ADDR_WIDTH - 1) of std_logic_vector(DATA_WIDTH - 1 downto 0); signal memory : memory_array; \\n procedure initialize_memory(file_name : string) is file data_file : text; variable line_buf : line; variable data_value : std_logic_vector(DATA_WIDTH - 1 downto 0); begin file_open(data_file, file_name, read_mode); for i in 0 to memory high loop readline(data_file, line_buf); read(line_buf, data_value); memory(i) <= data_value; end loop; file_close(data_file); end initialize_memory; \\n begin initialize_memory(FILE_NAME); \\n process(address) begin data_out <= memory(to_integer(unsigned(address))); end process; end Behavioral; \\n\\nend Behavioral;\\n\\nThis is an HDL code for a ROM (Hardware Description Language) code for a 32-bit ROM. \\n\\nThe ROM defines the data type (data_array) and the address types (address, address_WIDTH, data_out, write_mode). It also provides a control signal (memory) and an asynchronous data operation.\\n\\nThe process assigns the data to the main process (init_memory). This process waits for input signals and then decrements the data based on the memory value (address). When the data is full, it output the value of the input data (data_line_buf).\\n\\nOverall, this ROM code implements a 32-bit ROM by adding 16 and 16-bit assignments to address, read line_buf, and read(line_buf) operations. It also has a buffer memory with one line.\\n\\nThis ROM code instantiates a memory (open) memory and stores the input data (data_file) in it. The result of the operation is read from the input memory (address) and the write (write) operation is ready.\\n\\nIf the data_file is empty, it updates the memory (data_file) to read and writes the corresponding value from the stored value to the main process (init_memory).\\n\\nIn summary, this ROM code implements a 32-bit ROM by using a 32-bit memory assignment to address and reading from the input memory (address) and the write operation (write_mode) to the main process (init_memory). It also assigns the data to the buffer memory (address) and the asynchronous data operation ready.\\n\\nIn summary, this ROM code implements a 32-bit ROM based on the input memory, assigning the data to the memory used for the ROM, and then storing it in the buffer memory as the main process. This enables the ROM to write and read from the memory using the same input.\\n\\nOverall, this code implements a 32-bit ROM by implementing the 32-bit data output to address and reading from the buffer memory. It also assigns the data to the buffer memory for the corresponding write operation.\\n\\nThe ROM code does not contain any logic implementation or testbench to verify the functionality of this ROM. The ROM only has a generic assignment statement that represents the address to be written and read. It does not contain any architecture or testbench functionality peppers with assertions or checks to verify the functionality of this ROM.\\n\\nThis code provides a starting point for the implementation of a 32-bit ROM for generating the 32-bit data output based on the available memory assignments. If the data_file is empty or if the memory (open) memory is empty, the memory values are written and the data output is also read from the main process (init_memory).\\n\\nNote that this ROM code is only a starting point, and you should not add any additional libraries or code to the code.\\nlibrary IEEE;\\nuse IEEE.STD_LOGIC_1164.ALL;\\nuse']"
]
},
"metadata": {},
"execution_count": 31
}
]
},
{
"cell_type": "code",
"source": [
"model.push_to_hub('gpt2_hdl')\n",
"tokenizer.push_to_hub('gpt2_hdl')"
],
"metadata": {
"colab": {
"base_uri": "https://localhost:8080/",
"height": 84,
"referenced_widgets": [
"f352767983804a2db9861b5fe5d7e62d",
"61d00504878348b38c96d47aa455041e",
"af2bddf7a7d34900bf9015883ca25a0a",
"0b0d40b580c74280a285bc8172bd97aa",
"0c00d73b13544deba888d073e0c4d253",
"f6cc1a0c45b3434b9ec8ada8bd9a12a8",
"8347d0dbb7824e67b24885bc828ad6d5",
"3430d7e427de495b8622deb9fdec3cfa",
"b574faa5d5074f39b524186e9a54f2bf",
"3ed231ed51104195b8fff16e1fec1105",
"7619a3c330504c2c9bad50e69842e165"
]
},
"id": "IfPhOk0zkzdb",
"outputId": "7b25602b-5342-41f9-f447-7731aa13ac39"
},
"execution_count": 35,
"outputs": [
{
"output_type": "display_data",
"data": {
"text/plain": [
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"source": [
"###Gradio Webapp"
],
"metadata": {
"id": "RaPZEj-I4ast"
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},
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"cell_type": "code",
"source": [
"import pandas as pd\n",
"import torch\n",
"from google.colab import drive\n",
"drive.mount('/content/drive')\n",
"!pip install transformers"
],
"metadata": {
"id": "XvaKYG42MYOA"
},
"execution_count": null,
"outputs": []
},
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"source": [
"!pip install -q gradio\n",
"import gradio as gr\n",
"from transformers import AutoModelForCausalLM, TrainingArguments, Trainer, pipeline, AutoTokenizer\n",
"model = AutoModelForCausalLM.from_pretrained('myn11/gpt2_hdl').to('cuda')\n",
"tokenizer = AutoTokenizer.from_pretrained('myn11/gpt2_hdl')"
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"examples = [\n",
" ['summarise the code library IEEE;use IEEE.std_logic_1164.all;entity Top is port (dips_i : in std_logic_vector(3 downto 0);pbs_i : in std_logic;leds_o : out std_logic_vector(3 downto 0));end entity Top;architecture RTL of Top is begin leds_o <= dips_i when pbs_i=\"0\" else (others => \"1\"); end architecture RTL;'],\n",
" ['Explain the code library ieee;use ieee.std_logic_1164.all;entity test is port(clk : in std_logic;d : in std_logic ;q :out std_logic );end test;architecture rtl of test is begin process (clk) begin if rising_edge(clk) then q <= d; end if; end; end rtl;'],\n",
" ['Write a VHDL code for a read-only memory (ROM) module that takes an external data initialization file, and is parameterized by the data width, address width, and file name. The module should have an address input and a data output. It should read data from the file and provide the corresponding data output based on the given address.']\n",
"]\n",
"\n",
"title = \"GPT2 fine tuned for HDL\"\n",
"\n",
"def process_input(text):\n",
" input = tokenizer(text, truncation=True, return_tensors='pt').input_ids.to('cuda')\n",
" output = model.generate(input, max_length=1000, do_sample=True, top_k=50, top_p=0.92)\n",
" return tokenizer.batch_decode(output, skip_special_tokens=True)\n",
"\n",
"model_gui = gr.Interface(\n",
" process_input,\n",
" gr.Textbox(lines=3,label=\"Input\"),\n",
" gr.Textbox(lines=3, label=\"GPT2_HDL\"),\n",
" title=title,\n",
" examples=examples\n",
")\n",
"model_gui.launch(share=True)"
],
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"output_type": "stream",
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"Colab notebook detected. To show errors in colab notebook, set debug=True in launch()\n",
"Running on public URL: https://914623a42bfd061ca1.gradio.live\n",
"\n",
"This share link expires in 72 hours. For free permanent hosting and GPU upgrades, run `gradio deploy` from Terminal to deploy to Spaces (https://huggingface.co/spaces)\n"
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