<s> void RISCVTargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) { if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_4 ) ; else emitAttribute ( RISCVAttrs :: STACK_ALIGN , RISCVAttrs :: ALIGN_16 ) ; std :: string Arch = "rv32" ; if ( STI . hasFeature ( RISCV :: Feature64Bit ) ) Arch = "rv64" ; if ( STI . hasFeature ( RISCV :: FeatureRV32E ) ) Arch += "e1p9" ; else Arch += "i2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtM ) ) Arch += "_m2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtA ) ) Arch += "_a2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtF ) ) Arch += "_f2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtD ) ) Arch += "_d2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtC ) ) Arch += "_c2p0" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtB ) ) Arch += "_b0p93" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtV ) ) Arch += "_v0p10" ; if ( STI . hasFeature ( RISCV :: FeatureExtZfh ) ) Arch += "_zfh0p1" ; if ( STI . hasFeature ( RISCV :: FeatureExtZba ) ) Arch += "_zba0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbb ) ) Arch += "_zbb0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbc ) ) Arch += "_zbc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbe ) ) Arch += "_zbe0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbf ) ) Arch += "_zbf0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbm ) ) Arch += "_zbm0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbp ) ) Arch += "_zbp0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbproposedc ) ) Arch += "_zbproposedc0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbr ) ) Arch += "_zbr0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbs ) ) Arch += "_zbs0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZbt ) ) Arch += "_zbt0p93" ; if ( STI . hasFeature ( RISCV :: FeatureExtZvamo ) ) Arch += "_zvamo0p10" ; if ( STI . hasFeature ( RISCV :: FeatureStdExtZvlsseg ) ) Arch += "_zvlsseg0p10" ; emitTextAttribute ( RISCVAttrs :: ARCH , Arch ) ; } </s>

Emit the build attributes that only depend on the hardware that we expect .


<s> void RISCVTargetStreamer :: finish ( ) { finishAttributeSection ( ) ; } </s>

finish - after all the new live ranges have been created , compute the remaining live range , and rewrite instructions to use the new registers .


"getIntImmCost can only estimate cost of materialising integers"

Calculate the cost of materializing a 64-bit value .


Return the expected cost of materialization for the given integer immediate of the specified type for a given instruction .


<s> const RISCVTargetLowering * getTLI ( ) const { return TLI ; } </s>

Getter for generic TargetLowering class .


<s> bool RISCVTTIImpl :: isLoweredToCall ( const Function * F ) { if ( F -> getName ( ) . startswith ( "llvm.riscv.pulp" ) ) return false ; return BaseT :: isLoweredToCall ( F ) ; } </s>

Test whether calls to a function lower to actual program function calls .


<s> StringRef getPassName ( ) const override { return SNITCH_FREP_LOOPS_NAME ; } </s>

getPassName - Return a nice clean name for a pass .


"  not dead because the phi node has a user that is not MI\n"

isDead - Returns true if this is a dead def kill slot .


<s>
void
print
(
raw_ostream
&
OS
,
const
TargetRegisterInfo
*
TRI
=
nullptr
)
const
{
if
(
isReg
(
)
)
{
OS
<<
"register: "
<<
printReg
(
Contents
.
R
.
Reg
,
TRI
,
Contents
.
R
.
Sub
)
<<
'\n'
;
}
if
(
isImm
(
)
)
{
OS
<<
"immediate: "
<<
Contents
.
ImmVal
<<
'\n'
;
}
}
</s>

print - Print a debug representation of the operand to the given stream .


runOnMachineFunction - Emit the function body .