<s>
void
BlackfinAsmPrinter
::
emitLinkage
(
const
std
::
string
&
name
,
GlobalValue
::
LinkageTypes
l
)
{
switch
(
l
)
{
default
:
llvm_unreachable
(
"Unknown linkage type!"
)
;
case
GlobalValue
::
InternalLinkage
:
case
GlobalValue
::
PrivateLinkage
:
case
GlobalValue
::
LinkerPrivateLinkage
:
break
;
case
GlobalValue
::
ExternalLinkage
:
O
<<
TAI
->
getGlobalDirective
(
)
<<
name
<<
"\n"
;
break
;
case
GlobalValue
::
LinkOnceAnyLinkage
:
case
GlobalValue
::
LinkOnceODRLinkage
:
case
GlobalValue
::
WeakAnyLinkage
:
case
GlobalValue
::
WeakODRLinkage
:
O
<<
TAI
->
getGlobalDirective
(
)
<<
name
<<
"\n"
;
O
<<
TAI
->
getWeakDefDirective
(
)
<<
name
<<
"\n"
;
break
;
}
}
</s>

This emits linkage information about GVSym based on GV , if this is supported by the target .

Blackfin
"Unknown linkage type!"
"\n"
"\n"
"\n"


<s> bool BlackfinAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << '[' ; printOperand ( MI , OpNo ) ; O << ']' ; return false ; } </s>

Print the specified operand of MI , an INLINEASM instruction , using the specified assembler variant as an address .


<s> bool BlackfinAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'r' : break ; } } printOperand ( MI , OpNo ) ; return false ; } </s>

PrintAsmOperand - Print out an operand for an inline asm expression .


<s>
bool
BlackfinAsmPrinter
::
runOnMachineFunction
(
MachineFunction
&
MF
)
{
SetupMachineFunction
(
MF
)
;
EmitConstantPool
(
MF
.
getConstantPool
(
)
)
;
EmitJumpTableInfo
(
MF
.
getJumpTableInfo
(
)
,
MF
)
;
const
Function
*
F
=
MF
.
getFunction
(
)
;
OutStreamer
.
SwitchSection
(
getObjFileLowering
(
)
.
SectionForGlobal
(
F
,
Mang
,
TM
)
)
;
EmitAlignment
(
2
,
F
)
;
emitLinkage
(
CurrentFnName
,
F
->
getLinkage
(
)
)
;
printVisibility
(
CurrentFnName
,
F
->
getVisibility
(
)
)
;
O
<<
"\t.type\t"
<<
CurrentFnName
<<
", STT_FUNC\n"
<<
CurrentFnName
<<
":\n"
;
if
(
DW
)
DW
->
BeginFunction
(
&
MF
)
;
for
(
MachineFunction
::
const_iterator
I
=
MF
.
begin
(
)
,
E
=
MF
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
VerboseAsm
&&
(
I
->
pred_empty
(
)
||
I
->
isOnlyReachableByFallthrough
(
)
)
)
{
}
else
{
printBasicBlockLabel
(
I
,
true
,
true
,
VerboseAsm
)
;
O
<<
'\n'
;
}
for
(
MachineBasicBlock
::
const_iterator
II
=
I
->
begin
(
)
,
E
=
I
->
end
(
)
;
II
!=
E
;
++
II
)
{
printInstruction
(
II
)
;
++
EmittedInsts
;
}
}
O
<<
"\t.size "
<<
CurrentFnName
<<
", .-"
<<
CurrentFnName
<<
"\n"
;
if
(
DW
)
DW
->
EndFunction
(
&
MF
)
;
return
false
;
}
</s>

runOnMachineFunction - Emit the function body .

Blackfin
2
"\t.type\t"
", STT_FUNC\n"
":\n"
"\t.size "
", .-"
"\n"


<s> void EmitInstruction ( const MachineInstr * MI ) { printInstruction ( MI ) ; OutStreamer . AddBlankLine ( ) ; } </s>

EmitInstruction - This callback is invoked when an instruction is emitted , to advance the hazard state .


<s> void EmitInstruction ( const MachineInstr * MI ) { SmallString < 128 > Str ; raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ; } </s>


<s>
virtual
const
char
*
getPassName
(
)
const
{
return
"Blackfin Assembly Printer"
;
}
</s>

getPassName - Return a nice clean name for a pass .


<s> bool BlackfinAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) return true ; O << '[' ; printOperand ( MI , OpNo , O ) ; O << ']' ; return false ; } </s>


<s> bool BlackfinAsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ 0 ] ) { if ( ExtraCode [ 1 ] != 0 ) return true ; switch ( ExtraCode [ 0 ] ) { default : return true ; case 'r' : break ; } } printOperand ( MI , OpNo , O ) ; return false ; } </s>


"FP elimination on a non-leaf function is not supported"


emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> bool BlackfinFrameInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> bool BlackfinFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) ; } </s>


<s> bool BlackfinFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return true ; } </s>

hasReservedCallFrame - Under normal circumstances , when a frame pointer is not required , we reserve argument space for call sites in the function immediately on entry to the current function .


<s>
void
BlackfinInstrInfo
::
copyPhysReg
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
DebugLoc
DL
,
unsigned
DestReg
,
unsigned
SrcReg
,
bool
KillSrc
)
const
{
if
(
BF
::
ALLRegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
MOVE
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
if
(
BF
::
D16RegClass
.
contains
(
DestReg
,
SrcReg
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
SLL16i
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
if
(
BF
::
DRegClass
.
contains
(
DestReg
)
)
{
if
(
SrcReg
==
BF
::
NCC
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
MOVENCC_z
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
BITTGL
)
,
DestReg
)
.
addReg
(
DestReg
)
.
addImm
(
0
)
;
return
;
}
if
(
SrcReg
==
BF
::
CC
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
MOVECC_zext
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
}
if
(
BF
::
DRegClass
.
contains
(
SrcReg
)
)
{
if
(
DestReg
==
BF
::
NCC
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
SETEQri_not
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
.
addImm
(
0
)
;
return
;
}
if
(
DestReg
==
BF
::
CC
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
MOVECC_nz
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
}
if
(
DestReg
==
BF
::
NCC
&&
SrcReg
==
BF
::
CC
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
MOVE_ncccc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
if
(
DestReg
==
BF
::
CC
&&
SrcReg
==
BF
::
NCC
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
MOVE_ccncc
)
,
DestReg
)
.
addReg
(
SrcReg
,
getKillRegState
(
KillSrc
)
)
;
return
;
}
llvm_unreachable
(
"Bad reg-to-reg copy"
)
;
}
</s>


<s>
void
BlackfinInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
if
(
inClass
(
BF
::
DPRegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD32fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
D16RegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD16fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
AnyCCRegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD8fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
llvm_unreachable
(
"Cannot load regclass from stack slot"
)
;
}
</s>

Load the specified register of the given register class from the specified stack frame index .


<s>
void
BlackfinInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
,
const
TargetRegisterInfo
*
TRI
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
if
(
inClass
(
BF
::
DPRegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE32fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
D16RegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE16fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
AnyCCRegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE8fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
llvm_unreachable
(
(
std
::
string
(
"Cannot store regclass to stack slot: "
)
+
RC
->
getName
(
)
)
.
c_str
(
)
)
;
}
</s>

Store the specified register of the given register class to the specified stack frame index .


<s>
void
BlackfinInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
::
getUnknownLoc
(
)
;
if
(
inClass
(
BF
::
DPRegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD32fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
D16RegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD16fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
AnyCCRegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD8fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
llvm_unreachable
(
"Cannot load regclass from stack slot"
)
;
}
</s>


<s>
void
BlackfinInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
::
getUnknownLoc
(
)
;
if
(
inClass
(
BF
::
DPRegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE32fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
D16RegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE16fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
AnyCCRegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE8fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
llvm_unreachable
(
(
std
::
string
(
"Cannot store regclass to stack slot: "
)
+
RC
->
getName
(
)
)
.
c_str
(
)
)
;
}
</s>


<s> virtual const BlackfinRegisterInfo & getRegisterInfo ( ) const { return RI ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> unsigned BlackfinInstrInfo :: isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case BF :: LOAD32fi : case BF :: LOAD16fi : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot , return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot .


<s> unsigned BlackfinInstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { switch ( MI -> getOpcode ( ) ) { default : break ; case BF :: STORE32fi : case BF :: STORE16fi : if ( MI -> getOperand ( 1 ) . isFI ( ) && MI -> getOperand ( 2 ) . isImm ( ) && MI -> getOperand ( 2 ) . getImm ( ) == 0 ) { FrameIndex = MI -> getOperand ( 1 ) . getIndex ( ) ; return MI -> getOperand ( 0 ) . getReg ( ) ; } break ; } return 0 ; } </s>

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot , return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot .


<s>
void
BlackfinInstrInfo
::
loadRegFromStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
DestReg
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
if
(
inClass
(
BF
::
DPRegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD32fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
D16RegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD16fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
AnyCCRegClass
,
DestReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
LOAD8fi
)
,
DestReg
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
llvm_unreachable
(
"Cannot load regclass from stack slot"
)
;
}
</s>


<s>
void
BlackfinInstrInfo
::
storeRegToStackSlot
(
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
,
unsigned
SrcReg
,
bool
isKill
,
int
FI
,
const
TargetRegisterClass
*
RC
)
const
{
DebugLoc
DL
=
I
!=
MBB
.
end
(
)
I
->
getDebugLoc
(
)
:
DebugLoc
(
)
;
if
(
inClass
(
BF
::
DPRegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE32fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
D16RegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE16fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
if
(
inClass
(
BF
::
AnyCCRegClass
,
SrcReg
,
RC
)
)
{
BuildMI
(
MBB
,
I
,
DL
,
get
(
BF
::
STORE8fi
)
)
.
addReg
(
SrcReg
,
getKillRegState
(
isKill
)
)
.
addFrameIndex
(
FI
)
.
addImm
(
0
)
;
return
;
}
llvm_unreachable
(
(
std
::
string
(
"Cannot store regclass to stack slot: "
)
+
RC
->
getName
(
)
)
.
c_str
(
)
)
;
}
</s>


<s> unsigned BlackfinIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const { if ( Len < 5 || Name [ 4 ] != '.' || Name [ 0 ] != 'l' || Name [ 1 ] != 'l' || Name [ 2 ] != 'v' || Name [ 3 ] != 'm' ) return 0 ; return 0 ; } </s>


"Blackfin intrinsics are not overloaded"

Create or insert an LLVM Function declaration for an intrinsic , and return it .


Return a string with the name of the plan and the applicable VFs and UFs .


<s> static FunctionType * getType ( LLVMContext & Context , unsigned id ) { Type * ResultTy = NULL ; std :: vector < Type * > ArgTys ; bool IsVarArg = false ; return FunctionType :: get ( ResultTy , ArgTys , IsVarArg ) ; } </s>

Overload to return most specific vector type .


<s> static FunctionType * getType ( LLVMContext & Context , unsigned id ) { Type * ResultTy = NULL ; SmallVector < Type * , 8 > ArgTys ; bool IsVarArg = false ; return FunctionType :: get ( ResultTy , ArgTys , IsVarArg ) ; } </s>


<s> static const FunctionType * getType ( LLVMContext & Context , unsigned id ) { const Type * ResultTy = NULL ; std :: vector < const Type * > ArgTys ; bool IsVarArg = false ; return FunctionType :: get ( ResultTy , ArgTys , IsVarArg ) ; } </s>


<s> bool BlackfinIntrinsicInfo :: isOverloaded ( unsigned IntrID ) const { const bool OTable [ ] = { } ; if ( IntrID == 0 ) return false ; else return OTable [ IntrID - Intrinsic :: num_intrinsics ] ; } </s>

Returns true if the intrinsic can be overloaded .


<s> unsigned BlackfinIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const { return 0 ; } </s>


<s> SDNode * BlackfinDAGToDAGISel :: Select ( SDValue Op ) { SDNode * N = Op . getNode ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: FrameIndex : { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ; return CurDAG -> SelectNodeTo ( N , BF :: ADDpp , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , MVT :: i32 ) ) ; } } return SelectCode ( Op ) ; } </s>

Main hook for targets to transform nodes into machine nodes .


<s> const BlackfinInstrInfo & getInstrInfo ( ) { return * static_cast < const BlackfinTargetMachine & > ( TM ) . getInstrInfo ( ) ; } </s>


"Blackfin DAG->DAG Pattern Instruction Selection"


<s> const BlackfinRegisterInfo * getRegisterInfo ( ) { return static_cast < const BlackfinTargetMachine & > ( TM ) . getRegisterInfo ( ) ; } </s>


<s> void BlackfinDAGToDAGISel :: PostprocessISelDAG ( ) { FixRegisterClasses ( * CurDAG ) ; } </s>

PostprocessISelDAG ( ) - This hook allows the target to hack on the graph right after selection .


<s> SDNode * BlackfinDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case ISD :: FrameIndex : { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , MVT :: i32 ) ; return CurDAG -> SelectNodeTo ( N , BF :: ADDpp , MVT :: i32 , TFI , CurDAG -> getTargetConstant ( 0 , MVT :: i32 ) ) ; } } return SelectCode ( N ) ; } </s>


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const { return MVT :: i16 ; } </s>

Returns the type for the shift amount of a shift opcode .


<s> std :: pair < unsigned , const TargetRegisterClass * > BlackfinTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { typedef std :: pair < unsigned , const TargetRegisterClass * > Pair ; using namespace BF ; if ( Constraint . size ( ) != 1 ) return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; switch ( Constraint [ 0 ] ) { case 'r' : return Pair ( 0U , VT == MVT :: i16 ? D16RegisterClass : DPRegisterClass ) ; case 'a' : return Pair ( 0U , PRegisterClass ) ; case 'd' : return Pair ( 0U , DRegisterClass ) ; case 'e' : return Pair ( 0U , AccuRegisterClass ) ; case 'A' : return Pair ( A0 , AccuRegisterClass ) ; case 'B' : return Pair ( A1 , AccuRegisterClass ) ; case 'b' : return Pair ( 0U , IRegisterClass ) ; case 'v' : return Pair ( 0U , BRegisterClass ) ; case 'f' : return Pair ( 0U , MRegisterClass ) ; case 'C' : return Pair ( CC , JustCCRegisterClass ) ; case 'x' : return Pair ( 0U , GRRegisterClass ) ; case 'w' : return Pair ( 0U , ALLRegisterClass ) ; case 'Z' : return Pair ( P3 , PRegisterClass ) ; case 'Y' : return Pair ( P1 , PRegisterClass ) ; } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>

Given a physical register constraint ( e.g .


<s> MVT :: SimpleValueType BlackfinTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>

Return the value type to use for ISD : :SETCC .


<s>
SDValue
BlackfinTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SmallVector
<
CCValAssign
,
16
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AllocateStack
(
12
,
4
)
;
CCInfo
.
AnalyzeFormalArguments
(
Ins
,
CC_Blackfin
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
ArgLocs
[
i
]
;
if
(
VA
.
isRegLoc
(
)
)
{
EVT
RegVT
=
VA
.
getLocVT
(
)
;
TargetRegisterClass
*
RC
=
VA
.
getLocReg
(
)
==
BF
::
P0
BF
::
PRegisterClass
:
BF
::
DRegisterClass
;
assert
(
RC
->
contains
(
VA
.
getLocReg
(
)
)
&&
"Unexpected regclass in CCState"
)
;
assert
(
RC
->
hasType
(
RegVT
)
&&
"Unexpected regclass in CCState"
)
;
unsigned
Reg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MF
.
getRegInfo
(
)
.
addLiveIn
(
VA
.
getLocReg
(
)
,
Reg
)
;
SDValue
ArgValue
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
Reg
,
RegVT
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
if
(
VA
.
getLocInfo
(
)
!=
CCValAssign
::
Full
)
ArgValue
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
ArgValue
)
;
InVals
.
push_back
(
ArgValue
)
;
}
else
{
assert
(
VA
.
isMemLoc
(
)
&&
"CCValAssign must be RegLoc or MemLoc"
)
;
unsigned
ObjSize
=
VA
.
getLocVT
(
)
.
getStoreSize
(
)
;
int
FI
=
MFI
->
CreateFixedObject
(
ObjSize
,
VA
.
getLocMemOffset
(
)
,
true
,
false
)
;
SDValue
FIN
=
DAG
.
getFrameIndex
(
FI
,
MVT
::
i32
)
;
InVals
.
push_back
(
DAG
.
getLoad
(
VA
.
getValVT
(
)
,
dl
,
Chain
,
FIN
,
,
0
,
false
,
false
,
0
)
)
;
}
}
return
Chain
;
}
</s>

This hook must be implemented to lower the incoming ( formal ) arguments , described by the Ins array , into the specified DAG .


<s>
SDValue
BlackfinTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Blackfin."
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
SDValue
(
)
;
case
ISD
::
RETURNADDR
:
return
SDValue
(
)
;
case
ISD
::
ADDE
:
case
ISD
::
SUBE
:
return
LowerADDE
(
Op
,
DAG
)
;
}
}
</s>

LowerOperation - Provide custom lowering hooks for some operations .

Blackfin
"Should not custom lower this!"
ISD::GlobalAddress
ISD::GlobalTLSAddress
"TLS not implemented for Blackfin."
ISD::JumpTable
ISD::FRAMEADDR
ISD::RETURNADDR
ISD::ADDE
ISD::SUBE


<s>
SDValue
BlackfinTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Blackfin
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Opi
=
Outs
[
i
]
.
Val
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
Opi
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
ZExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
AExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Opi
,
SDValue
(
)
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
}
else
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
}
</s>

This hook must be implemented to lower outgoing return values , described by the Outs array , into the specified DAG .


"Do not know how to custom type legalize this operation!"

ReplaceNodeResults - Replace the results of node with an illegal result type with new values built out of custom code .


<s>
SDValue
BlackfinTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SmallVector
<
CCValAssign
,
16
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AllocateStack
(
12
,
4
)
;
CCInfo
.
AnalyzeFormalArguments
(
Ins
,
CC_Blackfin
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
ArgLocs
[
i
]
;
if
(
VA
.
isRegLoc
(
)
)
{
EVT
RegVT
=
VA
.
getLocVT
(
)
;
TargetRegisterClass
*
RC
=
VA
.
getLocReg
(
)
==
BF
::
P0
BF
::
PRegisterClass
:
BF
::
DRegisterClass
;
assert
(
RC
->
contains
(
VA
.
getLocReg
(
)
)
&&
"Unexpected regclass in CCState"
)
;
assert
(
RC
->
hasType
(
RegVT
)
&&
"Unexpected regclass in CCState"
)
;
unsigned
Reg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MF
.
getRegInfo
(
)
.
addLiveIn
(
VA
.
getLocReg
(
)
,
Reg
)
;
SDValue
ArgValue
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
Reg
,
RegVT
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
if
(
VA
.
getLocInfo
(
)
!=
CCValAssign
::
Full
)
ArgValue
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
ArgValue
)
;
InVals
.
push_back
(
ArgValue
)
;
}
else
{
assert
(
VA
.
isMemLoc
(
)
&&
"CCValAssign must be RegLoc or MemLoc"
)
;
unsigned
ObjSize
=
VA
.
getLocVT
(
)
.
getStoreSizeInBits
(
)
/
8
;
int
FI
=
MFI
->
CreateFixedObject
(
ObjSize
,
VA
.
getLocMemOffset
(
)
)
;
SDValue
FIN
=
DAG
.
getFrameIndex
(
FI
,
MVT
::
i32
)
;
InVals
.
push_back
(
DAG
.
getLoad
(
VA
.
getValVT
(
)
,
dl
,
Chain
,
FIN
,
,
0
)
)
;
}
}
return
Chain
;
}
</s>


<s>
SDValue
BlackfinTargetLowering
::
LowerReturn
(
SDValue
Chain
,
unsigned
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Blackfin
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Opi
=
Outs
[
i
]
.
Val
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
Opi
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
ZExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
AExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Opi
,
SDValue
(
)
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
}
else
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
}
</s>


<s>
SDValue
BlackfinTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SmallVector
<
CCValAssign
,
16
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AllocateStack
(
12
,
4
)
;
CCInfo
.
AnalyzeFormalArguments
(
Ins
,
CC_Blackfin
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
ArgLocs
[
i
]
;
if
(
VA
.
isRegLoc
(
)
)
{
EVT
RegVT
=
VA
.
getLocVT
(
)
;
TargetRegisterClass
*
RC
=
VA
.
getLocReg
(
)
==
BF
::
P0
BF
::
PRegisterClass
:
BF
::
DRegisterClass
;
assert
(
RC
->
contains
(
VA
.
getLocReg
(
)
)
&&
"Unexpected regclass in CCState"
)
;
assert
(
RC
->
hasType
(
RegVT
)
&&
"Unexpected regclass in CCState"
)
;
unsigned
Reg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MF
.
getRegInfo
(
)
.
addLiveIn
(
VA
.
getLocReg
(
)
,
Reg
)
;
SDValue
ArgValue
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
Reg
,
RegVT
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
if
(
VA
.
getLocInfo
(
)
!=
CCValAssign
::
Full
)
ArgValue
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
ArgValue
)
;
InVals
.
push_back
(
ArgValue
)
;
}
else
{
assert
(
VA
.
isMemLoc
(
)
&&
"CCValAssign must be RegLoc or MemLoc"
)
;
unsigned
ObjSize
=
VA
.
getLocVT
(
)
.
getStoreSize
(
)
;
int
FI
=
MFI
->
CreateFixedObject
(
ObjSize
,
VA
.
getLocMemOffset
(
)
,
true
)
;
SDValue
FIN
=
DAG
.
getFrameIndex
(
FI
,
MVT
::
i32
)
;
InVals
.
push_back
(
DAG
.
getLoad
(
VA
.
getValVT
(
)
,
dl
,
Chain
,
FIN
,
,
0
,
false
,
false
,
0
)
)
;
}
}
return
Chain
;
}
</s>


<s>
SDValue
BlackfinTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Blackfin
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Opi
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
Opi
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
ZExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
AExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Opi
,
SDValue
(
)
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
}
else
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
}
</s>


<s>
SDValue
BlackfinTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SmallVector
<
CCValAssign
,
16
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
getTargetMachine
(
)
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AllocateStack
(
12
,
4
)
;
CCInfo
.
AnalyzeFormalArguments
(
Ins
,
CC_Blackfin
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
ArgLocs
[
i
]
;
if
(
VA
.
isRegLoc
(
)
)
{
EVT
RegVT
=
VA
.
getLocVT
(
)
;
TargetRegisterClass
*
RC
=
VA
.
getLocReg
(
)
==
BF
::
P0
BF
::
PRegisterClass
:
BF
::
DRegisterClass
;
assert
(
RC
->
contains
(
VA
.
getLocReg
(
)
)
&&
"Unexpected regclass in CCState"
)
;
assert
(
RC
->
hasType
(
RegVT
)
&&
"Unexpected regclass in CCState"
)
;
unsigned
Reg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MF
.
getRegInfo
(
)
.
addLiveIn
(
VA
.
getLocReg
(
)
,
Reg
)
;
SDValue
ArgValue
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
Reg
,
RegVT
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
if
(
VA
.
getLocInfo
(
)
!=
CCValAssign
::
Full
)
ArgValue
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
ArgValue
)
;
InVals
.
push_back
(
ArgValue
)
;
}
else
{
assert
(
VA
.
isMemLoc
(
)
&&
"CCValAssign must be RegLoc or MemLoc"
)
;
unsigned
ObjSize
=
VA
.
getLocVT
(
)
.
getStoreSize
(
)
;
int
FI
=
MFI
->
CreateFixedObject
(
ObjSize
,
VA
.
getLocMemOffset
(
)
,
true
)
;
SDValue
FIN
=
DAG
.
getFrameIndex
(
FI
,
MVT
::
i32
)
;
InVals
.
push_back
(
DAG
.
getLoad
(
VA
.
getValVT
(
)
,
dl
,
Chain
,
FIN
,
MachinePointerInfo
(
)
,
false
,
false
,
0
)
)
;
}
}
return
Chain
;
}
</s>


<s> BlackfinTargetLowering :: ConstraintType BlackfinTargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) != 1 ) return TargetLowering :: getConstraintType ( Constraint ) ; switch ( Constraint [ 0 ] ) { case 'r' : return C_RegisterClass ; case 'a' : case 'd' : case 'z' : case 'D' : case 'W' : case 'e' : case 'b' : case 'v' : case 'f' : case 'c' : case 't' : case 'u' : case 'k' : case 'x' : case 'y' : case 'w' : return C_RegisterClass ; case 'A' : case 'B' : case 'C' : case 'Z' : case 'Y' : return C_Register ; } return TargetLowering :: getConstraintType ( Constraint ) ; } </s>

Given a constraint letter , return the type of constraint for this target .


<s> std :: pair < unsigned , const TargetRegisterClass * > BlackfinTargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { typedef std :: pair < unsigned , const TargetRegisterClass * > Pair ; using namespace BF ; if ( Constraint . size ( ) != 1 ) return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; switch ( Constraint [ 0 ] ) { case 'r' : return Pair ( 0U , VT == MVT :: i16 ? D16RegisterClass : DPRegisterClass ) ; case 'a' : return Pair ( 0U , PRegisterClass ) ; case 'd' : return Pair ( 0U , DRegisterClass ) ; case 'e' : return Pair ( 0U , AccuRegisterClass ) ; case 'A' : return Pair ( A0 , AccuRegisterClass ) ; case 'B' : return Pair ( A1 , AccuRegisterClass ) ; case 'b' : return Pair ( 0U , IRegisterClass ) ; case 'v' : return Pair ( 0U , BRegisterClass ) ; case 'f' : return Pair ( 0U , MRegisterClass ) ; case 'C' : return Pair ( CC , JustCCRegisterClass ) ; case 'x' : return Pair ( 0U , GRRegisterClass ) ; case 'w' : return Pair ( 0U , ALLRegisterClass ) ; case 'Z' : return Pair ( P3 , PRegisterClass ) ; case 'Y' : return Pair ( P1 , PRegisterClass ) ; case 'z' : return Pair ( 0U , zConsRegisterClass ) ; case 'D' : return Pair ( 0U , DConsRegisterClass ) ; case 'W' : return Pair ( 0U , WConsRegisterClass ) ; case 'c' : return Pair ( 0U , cConsRegisterClass ) ; case 't' : return Pair ( 0U , tConsRegisterClass ) ; case 'u' : return Pair ( 0U , uConsRegisterClass ) ; case 'k' : return Pair ( 0U , kConsRegisterClass ) ; case 'y' : return Pair ( 0U , yConsRegisterClass ) ; } return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; } </s>


<s> EVT BlackfinTargetLowering :: getSetCCResultType ( EVT VT ) const { return MVT :: i32 ; } </s>


<s> TargetLowering :: ConstraintWeight BlackfinTargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'z' : case 'D' : case 'W' : case 'e' : case 'b' : case 'v' : case 'f' : case 'c' : case 't' : case 'u' : case 'k' : case 'x' : case 'y' : case 'w' : return CW_Register ; case 'A' : case 'B' : case 'C' : case 'Z' : case 'Y' : return CW_SpecificReg ; } return weight ; } </s>

Examine constraint string and operand type and determine a weight value .


<s> const char * BlackfinTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return 0 ; case BFISD :: CALL : return "BFISD::CALL" ; case BFISD :: RET_FLAG : return "BFISD::RET_FLAG" ; case BFISD :: Wrapper : return "BFISD::Wrapper" ; } } </s>

getTargetNodeName - This method returns the name of a target specific


<s> bool BlackfinTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return false ; } </s>

Return true if folding a constant offset with the given GlobalAddress is legal .


<s>
SDValue
BlackfinTargetLowering
::
LowerFormalArguments
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
InputArg
>
&
Ins
,
DebugLoc
dl
,
SelectionDAG
&
DAG
,
SmallVectorImpl
<
SDValue
>
&
InVals
)
const
{
MachineFunction
&
MF
=
DAG
.
getMachineFunction
(
)
;
MachineFrameInfo
*
MFI
=
MF
.
getFrameInfo
(
)
;
SmallVector
<
CCValAssign
,
16
>
ArgLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
getTargetMachine
(
)
,
ArgLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AllocateStack
(
12
,
4
)
;
CCInfo
.
AnalyzeFormalArguments
(
Ins
,
CC_Blackfin
)
;
for
(
unsigned
i
=
0
,
e
=
ArgLocs
.
size
(
)
;
i
!=
e
;
++
i
)
{
CCValAssign
&
VA
=
ArgLocs
[
i
]
;
if
(
VA
.
isRegLoc
(
)
)
{
EVT
RegVT
=
VA
.
getLocVT
(
)
;
TargetRegisterClass
*
RC
=
VA
.
getLocReg
(
)
==
BF
::
P0
BF
::
PRegisterClass
:
BF
::
DRegisterClass
;
assert
(
RC
->
contains
(
VA
.
getLocReg
(
)
)
&&
"Unexpected regclass in CCState"
)
;
assert
(
RC
->
hasType
(
RegVT
)
&&
"Unexpected regclass in CCState"
)
;
unsigned
Reg
=
MF
.
getRegInfo
(
)
.
createVirtualRegister
(
RC
)
;
MF
.
getRegInfo
(
)
.
addLiveIn
(
VA
.
getLocReg
(
)
,
Reg
)
;
SDValue
ArgValue
=
DAG
.
getCopyFromReg
(
Chain
,
dl
,
Reg
,
RegVT
)
;
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
SExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertSext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
else
if
(
VA
.
getLocInfo
(
)
==
CCValAssign
::
ZExt
)
ArgValue
=
DAG
.
getNode
(
ISD
::
AssertZext
,
dl
,
RegVT
,
ArgValue
,
DAG
.
getValueType
(
VA
.
getValVT
(
)
)
)
;
if
(
VA
.
getLocInfo
(
)
!=
CCValAssign
::
Full
)
ArgValue
=
DAG
.
getNode
(
ISD
::
TRUNCATE
,
dl
,
VA
.
getValVT
(
)
,
ArgValue
)
;
InVals
.
push_back
(
ArgValue
)
;
}
else
{
assert
(
VA
.
isMemLoc
(
)
&&
"CCValAssign must be RegLoc or MemLoc"
)
;
unsigned
ObjSize
=
VA
.
getLocVT
(
)
.
getStoreSize
(
)
;
int
FI
=
MFI
->
CreateFixedObject
(
ObjSize
,
VA
.
getLocMemOffset
(
)
,
true
)
;
SDValue
FIN
=
DAG
.
getFrameIndex
(
FI
,
MVT
::
i32
)
;
InVals
.
push_back
(
DAG
.
getLoad
(
VA
.
getValVT
(
)
,
dl
,
Chain
,
FIN
,
MachinePointerInfo
(
)
,
false
,
false
,
0
)
)
;
}
}
return
Chain
;
}
</s>


<s>
SDValue
BlackfinTargetLowering
::
LowerOperation
(
SDValue
Op
,
SelectionDAG
&
DAG
)
const
{
switch
(
Op
.
getOpcode
(
)
)
{
default
:
Op
.
getNode
(
)
->
dump
(
)
;
llvm_unreachable
(
"Should not custom lower this!"
)
;
case
ISD
::
GlobalAddress
:
return
LowerGlobalAddress
(
Op
,
DAG
)
;
case
ISD
::
GlobalTLSAddress
:
llvm_unreachable
(
"TLS not implemented for Blackfin."
)
;
case
ISD
::
JumpTable
:
return
LowerJumpTable
(
Op
,
DAG
)
;
case
ISD
::
FRAMEADDR
:
return
SDValue
(
)
;
case
ISD
::
RETURNADDR
:
return
SDValue
(
)
;
case
ISD
::
ADDE
:
case
ISD
::
SUBE
:
return
LowerADDE
(
Op
,
DAG
)
;
}
}
</s>


<s>
SDValue
BlackfinTargetLowering
::
LowerReturn
(
SDValue
Chain
,
CallingConv
::
ID
CallConv
,
bool
isVarArg
,
const
SmallVectorImpl
<
ISD
::
OutputArg
>
&
Outs
,
const
SmallVectorImpl
<
SDValue
>
&
OutVals
,
DebugLoc
dl
,
SelectionDAG
&
DAG
)
const
{
SmallVector
<
CCValAssign
,
16
>
RVLocs
;
CCState
CCInfo
(
CallConv
,
isVarArg
,
DAG
.
getMachineFunction
(
)
,
DAG
.
getTarget
(
)
,
RVLocs
,
*
DAG
.
getContext
(
)
)
;
CCInfo
.
AnalyzeReturn
(
Outs
,
RetCC_Blackfin
)
;
if
(
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
liveout_empty
(
)
)
{
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
DAG
.
getMachineFunction
(
)
.
getRegInfo
(
)
.
addLiveOut
(
RVLocs
[
i
]
.
getLocReg
(
)
)
;
}
SDValue
Flag
;
for
(
unsigned
i
=
0
;
i
!=
RVLocs
.
size
(
)
;
++
i
)
{
CCValAssign
&
VA
=
RVLocs
[
i
]
;
assert
(
VA
.
isRegLoc
(
)
&&
"Can only return in registers!"
)
;
SDValue
Opi
=
OutVals
[
i
]
;
switch
(
VA
.
getLocInfo
(
)
)
{
default
:
llvm_unreachable
(
"Unknown loc info!"
)
;
case
CCValAssign
::
Full
:
break
;
case
CCValAssign
::
SExt
:
Opi
=
DAG
.
getNode
(
ISD
::
SIGN_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
ZExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ZERO_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
case
CCValAssign
::
AExt
:
Opi
=
DAG
.
getNode
(
ISD
::
ANY_EXTEND
,
dl
,
VA
.
getLocVT
(
)
,
Opi
)
;
break
;
}
Chain
=
DAG
.
getCopyToReg
(
Chain
,
dl
,
VA
.
getLocReg
(
)
,
Opi
,
SDValue
(
)
)
;
Flag
=
Chain
.
getValue
(
1
)
;
}
if
(
Flag
.
getNode
(
)
)
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
,
Flag
)
;
}
else
{
return
DAG
.
getNode
(
BFISD
::
RET_FLAG
,
dl
,
MVT
::
Other
,
Chain
)
;
}
}
</s>


<s>
void
BlackfinRegisterInfo
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
if
(
!
hasReservedCallFrame
(
MF
)
)
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
!=
0
)
{
assert
(
Amount
%
4
==
0
&&
"Unaligned call frame size"
)
;
if
(
I
->
getOpcode
(
)
==
BF
::
ADJCALLSTACKDOWN
)
{
adjustRegister
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
BF
::
SP
,
BF
::
P1
,
Amount
)
;
}
else
{
assert
(
I
->
getOpcode
(
)
==
BF
::
ADJCALLSTACKUP
&&
"Unknown call frame pseudo instruction"
)
;
adjustRegister
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
BF
::
SP
,
BF
::
P1
,
Amount
)
;
}
}
}
MBB
.
erase
(
I
)
;
}
</s>

This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy pseudo instructions ( but only if the Target is using them ) .


"FP elimination on a non-leaf function is not supported"


emitProlog/emitEpilog - These methods insert prolog and epilog code into the function .


<s> const unsigned * BlackfinRegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { using namespace BF ; static const unsigned CalleeSavedRegs [ ] = { FP , R4 , R5 , R6 , R7 , P3 , P4 , P5 , 0 } ; return CalleeSavedRegs ; } </s>


<s>
int
BlackfinRegisterInfo
::
getDwarfRegNum
(
unsigned
RegNum
,
bool
isEH
)
const
{
llvm_unreachable
(
"What is the dwarf register number"
)
;
return
1
;
}
</s>

Map a target register to an equivalent dwarf register number .

Blackfin
"What is the dwarf register number"
1


<s> unsigned BlackfinRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return hasFP ( MF ) ? BF :: FP : BF :: SP ; } </s>


<s> const TargetRegisterClass * getPointerRegClass ( unsigned Kind = 0 ) const { return & BF :: PRegClass ; } </s>

getPointerRegClass - Returns a TargetRegisterClass used for pointer values .


<s> unsigned BlackfinRegisterInfo :: getRARegister ( ) const { return BF :: RETS ; } </s>

This method should return the register where the return address can be found .


<s> BitVector BlackfinRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { using namespace BF ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AZ ) ; Reserved . set ( AN ) ; Reserved . set ( AQ ) ; Reserved . set ( AC0 ) ; Reserved . set ( AC1 ) ; Reserved . set ( AV0 ) ; Reserved . set ( AV0S ) ; Reserved . set ( AV1 ) ; Reserved . set ( AV1S ) ; Reserved . set ( V ) ; Reserved . set ( VS ) ; Reserved . set ( CYCLES ) . set ( CYCLES2 ) ; Reserved . set ( L0 ) ; Reserved . set ( L1 ) ; Reserved . set ( L2 ) ; Reserved . set ( L3 ) ; Reserved . set ( SP ) ; Reserved . set ( RETS ) ; if ( hasFP ( MF ) ) Reserved . set ( FP ) ; return Reserved ; } </s>

getReservedRegs - Returns a bitset indexed by physical register number indicating if a register is a special register that has particular uses and should be considered unavailable at all times , e.g .


<s> bool BlackfinRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return NoFramePointerElim || MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( ) ; } </s>

hasFP - Return true if the specified function should have a dedicated frame pointer register .


<s> void BlackfinRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const { } </s>

processFunctionBeforeFrameFinalized - This method is called immediately before the specified function 's frame layout ( MF.getFrameInfo ( ) ) is finalized .


<s> bool BlackfinRegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ; } </s>

Returns true if the target requires ( and can make use of ) the register scavenger .


<s> unsigned BlackfinRegisterInfo :: getFrameRegister ( MachineFunction & MF ) const { return hasFP ( MF ) ? BF :: FP : BF :: SP ; } </s>


<s> bool BlackfinRegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) ; } </s>


<s>
void
BlackfinRegisterInfo
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
TargetFrameInfo
*
TFI
=
MF
.
getTarget
(
)
.
getFrameInfo
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
!=
0
)
{
assert
(
Amount
%
4
==
0
&&
"Unaligned call frame size"
)
;
if
(
I
->
getOpcode
(
)
==
BF
::
ADJCALLSTACKDOWN
)
{
adjustRegister
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
BF
::
SP
,
BF
::
P1
,
Amount
)
;
}
else
{
assert
(
I
->
getOpcode
(
)
==
BF
::
ADJCALLSTACKUP
&&
"Unknown call frame pseudo instruction"
)
;
adjustRegister
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
BF
::
SP
,
BF
::
P1
,
Amount
)
;
}
}
}
MBB
.
erase
(
I
)
;
}
</s>


<s> unsigned BlackfinRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? BF :: FP : BF :: SP ; } </s>


<s> BitVector BlackfinRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; using namespace BF ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AZ ) ; Reserved . set ( AN ) ; Reserved . set ( AQ ) ; Reserved . set ( AC0 ) ; Reserved . set ( AC1 ) ; Reserved . set ( AV0 ) ; Reserved . set ( AV0S ) ; Reserved . set ( AV1 ) ; Reserved . set ( AV1S ) ; Reserved . set ( V ) ; Reserved . set ( VS ) ; Reserved . set ( CYCLES ) . set ( CYCLES2 ) ; Reserved . set ( L0 ) ; Reserved . set ( L1 ) ; Reserved . set ( L2 ) ; Reserved . set ( L3 ) ; Reserved . set ( SP ) ; Reserved . set ( RETS ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FP ) ; return Reserved ; } </s>


<s>
void
BlackfinRegisterInfo
::
eliminateCallFramePseudoInstr
(
MachineFunction
&
MF
,
MachineBasicBlock
&
MBB
,
MachineBasicBlock
::
iterator
I
)
const
{
const
TargetFrameLowering
*
TFI
=
MF
.
getTarget
(
)
.
getFrameLowering
(
)
;
if
(
!
TFI
->
hasReservedCallFrame
(
MF
)
)
{
int64_t
Amount
=
I
->
getOperand
(
0
)
.
getImm
(
)
;
if
(
Amount
!=
0
)
{
assert
(
Amount
%
4
==
0
&&
"Unaligned call frame size"
)
;
if
(
I
->
getOpcode
(
)
==
BF
::
ADJCALLSTACKDOWN
)
{
adjustRegister
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
BF
::
SP
,
BF
::
P1
,
Amount
)
;
}
else
{
assert
(
I
->
getOpcode
(
)
==
BF
::
ADJCALLSTACKUP
&&
"Unknown call frame pseudo instruction"
)
;
adjustRegister
(
MBB
,
I
,
I
->
getDebugLoc
(
)
,
BF
::
SP
,
BF
::
P1
,
Amount
)
;
}
}
}
MBB
.
erase
(
I
)
;
}
</s>


<s> unsigned BlackfinRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? BF :: FP : BF :: SP ; } </s>


<s> BitVector BlackfinRegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; using namespace BF ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( AZ ) ; Reserved . set ( AN ) ; Reserved . set ( AQ ) ; Reserved . set ( AC0 ) ; Reserved . set ( AC1 ) ; Reserved . set ( AV0 ) ; Reserved . set ( AV0S ) ; Reserved . set ( AV1 ) ; Reserved . set ( AV1S ) ; Reserved . set ( V ) ; Reserved . set ( VS ) ; Reserved . set ( CYCLES ) . set ( CYCLES2 ) ; Reserved . set ( L0 ) ; Reserved . set ( L1 ) ; Reserved . set ( L2 ) ; Reserved . set ( L3 ) ; Reserved . set ( SP ) ; Reserved . set ( RETS ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FP ) ; return Reserved ; } </s>


<s> virtual const TargetFrameInfo * getFrameInfo ( ) const { return & FrameInfo ; } </s>

getFrameInfo - Return the frame info object for the current function .


<s> bool BlackfinTargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( createBlackfinISelDag ( * this , OptLevel ) ) ; return false ; } </s>

addInstSelector - This method should install an instruction selector pass , which converts from LLVM code to machine instructions .


<s> virtual const BlackfinInstrInfo * getInstrInfo ( ) const { return & InstrInfo ; } </s>


<s> const TargetIntrinsicInfo * getIntrinsicInfo ( ) const { return & IntrinsicInfo ; } </s>

If intrinsic information is available , return it . If not , return null .


<s> virtual const BlackfinRegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ; } </s>

getRegisterInfo - TargetInstrInfo is a superset of MRegister info .


<s> virtual const BlackfinSubtarget * getSubtargetImpl ( ) const { return & Subtarget ; } </s>

Virtual method implemented by subclasses that returns a reference to that target 's TargetSubtargetInfo-derived member variable .