<s> static bool cortex_a9_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int * cost ) { switch ( REG_NOTE_KIND ( link ) ) { case REG_DEP_ANTI : * cost = 0 ; return false ; case REG_DEP_TRUE : case REG_DEP_OUTPUT : if ( recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { if ( GET_MODE_CLASS ( GET_MODE ( SET_DEST ( PATTERN ( insn ) ) ) ) == MODE_FLOAT || GET_MODE_CLASS ( GET_MODE ( SET_SRC ( PATTERN ( insn ) ) ) ) == MODE_FLOAT ) { enum attr_type attr_type_insn = get_attr_type ( insn ) ; enum attr_type attr_type_dep = get_attr_type ( dep ) ; if ( REG_P ( SET_DEST ( PATTERN ( insn ) ) ) && reg_set_p ( SET_DEST ( PATTERN ( insn ) ) , dep ) ) { if ( ( attr_type_insn == TYPE_FMACS || attr_type_insn == TYPE_FMACD ) && ( attr_type_dep == TYPE_FMACS || attr_type_dep == TYPE_FMACD ) ) { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) - 3 ; else * cost = insn_default_latency ( dep ) ; return false ; } else { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) + 1 ; else * cost = insn_default_latency ( dep ) ; } return false ; } } } } break ; default : gcc_unreachable ( ) ; } return true ; } </s>


<s> static unsigned feature_count ( const arm_feature_set * set ) { return ( bit_count ( ARM_FSET_CPU1 ( * set ) ) + bit_count ( ARM_FSET_CPU2 ( * set ) ) ) ; } </s>

Return the number of features in feature-set SET .


<s> void neon_const_bounds ( rtx operand , HOST_WIDE_INT low , HOST_WIDE_INT high ) { bounds_check ( operand , low , high , NULL_TREE , "constant" ) ; } </s>


<s> void neon_split_vcombine ( rtx operands [ 3 ] ) { unsigned int dest = REGNO ( operands [ 0 ] ) ; unsigned int src1 = REGNO ( operands [ 1 ] ) ; unsigned int src2 = REGNO ( operands [ 2 ] ) ; machine_mode halfmode = GET_MODE ( operands [ 1 ] ) ; unsigned int halfregs = HARD_REGNO_NREGS ( src1 , halfmode ) ; rtx destlo , desthi ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest , 0 ) ; desthi = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( src2 == dest && src1 == dest + halfregs ) { rtx x = gen_rtx_SET ( destlo , operands [ 1 ] ) ; rtx y = gen_rtx_SET ( desthi , operands [ 2 ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , x , y ) ) ) ; return ; } if ( ! reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; } } </s>

Split operands into moves from op [ 1 ] + op [ 2 ] into op [ 0 ] .


<s> static rtx neon_vdup_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; rtx x ; if ( GET_CODE ( vals ) != CONST_VECTOR || GET_MODE_SIZE ( inner_mode ) > 4 ) return NULL_RTX ; if ( ! const_vec_duplicate_p ( vals , & x ) ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , x ) ; return gen_rtx_VEC_DUPLICATE ( mode , x ) ; } </s>

Return a non-NULL RTX iff VALS is a vector constant that can be loaded into a register using VDUP . If this is the case , and GENERATE is set , we also generate instructions to do this and return an RTX to assign to the register .


<s> int neon_vector_mem_operand ( rtx op , int type , bool strict ) { rtx ind ; if ( strict && ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return FALSE ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , 0 ) ; if ( reload_completed && ( GET_CODE ( ind ) == LABEL_REF || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , 0 ) , 1 ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( ( type != 1 && GET_CODE ( ind ) == POST_INC ) || ( type == 0 && GET_CODE ( ind ) == PRE_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; if ( type == 2 && GET_CODE ( ind ) == POST_MODIFY && GET_CODE ( XEXP ( ind , 1 ) ) == PLUS && REG_P ( XEXP ( XEXP ( ind , 1 ) , 1 ) ) ) return true ; if ( type == 0 && GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , 0 ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , 0 ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , 1 ) ) && INTVAL ( XEXP ( ind , 1 ) ) > - 1024 && ( INTVAL ( XEXP ( ind , 1 ) ) < ( VALID_NEON_QREG_MODE ( GET_MODE ( op ) ) ? 1016 : 1024 ) ) && ( INTVAL ( XEXP ( ind , 1 ) ) & 3 ) == 0 ) return TRUE ; return FALSE ; } </s>

Return TRUE if OP is a memory operand which we can load or store a vector to/from . TYPE is one of the following values : 0 - Vector load/stor ( vldr ) 1 - Core registers ( ldm ) 2 - Element/structure loads ( vld1 )


<s> void thumb2_expand_return ( bool simple_return ) { int i , num_regs ; unsigned long saved_regs_mask ; arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; saved_regs_mask = offsets -> saved_regs_mask ; for ( i = 0 , num_regs = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) num_regs ++ ; if ( ! simple_return && saved_regs_mask ) { if ( num_regs == 1 ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; rtx reg = gen_rtx_REG ( SImode , PC_REGNUM ) ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; XVECEXP ( par , 0 , 0 ) = ret_rtx ; XVECEXP ( par , 0 , 1 ) = gen_rtx_SET ( reg , addr ) ; RTX_FRAME_RELATED_P ( XVECEXP ( par , 0 , 1 ) ) = 1 ; emit_jump_insn ( par ) ; } else { saved_regs_mask &= ~ ( 1 << LR_REGNUM ) ; saved_regs_mask |= ( 1 << PC_REGNUM ) ; arm_emit_multi_reg_pop ( saved_regs_mask ) ; } } else { emit_jump_insn ( simple_return_rtx ) ; } } </s>


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != 0 ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5 && TARGET_ARM ) { if ( ! call_used_regs [ 3 ] ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_HARD_FLOAT && TARGET_VFP ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s> static int vfp3_const_double_index ( rtx x ) { REAL_VALUE_TYPE r , m ; int sign , exponent ; unsigned HOST_WIDE_INT mantissa , mant_hi ; unsigned HOST_WIDE_INT mask ; int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; bool fail ; if ( ! TARGET_VFP3 || ! CONST_DOUBLE_P ( x ) ) return - 1 ; r = * CONST_DOUBLE_REAL_VALUE ( x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - 1 ; sign = REAL_VALUE_NEGATIVE ( r ) ? 1 : 0 ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; mantissa = w . elt ( 0 ) ; mant_hi = w . elt ( 1 ) ; if ( mantissa != 0 ) return - 1 ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return - 1 ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return - 1 ; gcc_assert ( mantissa >= 16 && mantissa <= 31 ) ; exponent = 5 - exponent ; if ( exponent < 0 || exponent > 7 ) return - 1 ; return ( sign << 7 ) | ( ( exponent ^ 3 ) << 4 ) | ( mantissa - 16 ) ; } </s>

Return an integer index for a VFPv3 immediate operand X suitable for the fconst [ sd ] instruction , or -1 if X is n't suitable .


<s> static bool aapcs_vfp_allocate ( CUMULATIVE_ARGS * pcum , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { int rmode_size = MAX ( GET_MODE_SIZE ( pcum -> aapcs_vfp_rmode ) , GET_MODE_SIZE ( SFmode ) ) ; int shift = rmode_size / GET_MODE_SIZE ( SFmode ) ; unsigned mask = ( 1 << ( shift * pcum -> aapcs_vfp_rcount ) ) - 1 ; int regno ; for ( regno = 0 ; regno < NUM_VFP_ARG_REGS ; regno += shift ) if ( ( ( pcum -> aapcs_vfp_regs_free >> regno ) & mask ) == mask ) { pcum -> aapcs_vfp_reg_alloc = mask << regno ; if ( mode == BLKmode || ( mode == TImode && ! TARGET_NEON ) || ! arm_hard_regno_mode_ok ( FIRST_VFP_REGNUM + regno , mode ) ) { int i ; int rcount = pcum -> aapcs_vfp_rcount ; int rshift = shift ; machine_mode rmode = pcum -> aapcs_vfp_rmode ; rtx par ; if ( ! TARGET_NEON ) { if ( rmode == V2SImode ) rmode = DImode ; else if ( rmode == V4SImode ) { rmode = DImode ; rcount *= 2 ; rshift /= 2 ; } } par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( rcount ) ) ; for ( i = 0 ; i < rcount ; i ++ ) { rtx tmp = gen_rtx_REG ( rmode , FIRST_VFP_REGNUM + regno + i * rshift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( rmode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } pcum -> aapcs_reg = par ; } else pcum -> aapcs_reg = gen_rtx_REG ( mode , FIRST_VFP_REGNUM + regno ) ; return true ; } return false ; } </s>

Implement the allocate field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


<s> static bool aarch_macro_fusion_pair_p ( rtx_insn * prev , rtx_insn * curr ) { rtx prev_set = single_set ( prev ) ; rtx curr_set = single_set ( curr ) ; if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_AES_AESMC && aarch_crypto_can_dual_issue ( prev , curr ) ) return true ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT && arm_sets_movw_movt_fusible_p ( prev_set , curr_set ) ) return true ; return false ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_PAIR_P . Return true if PREV and CURR should be kept together during scheduling .


<s> static void arm32_output_mi_thunk ( FILE * file , tree , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { int this_regno = ( aggregate_value_p ( TREE_TYPE ( TREE_TYPE ( function ) ) , function ) ? R1_REGNUM : R0_REGNUM ) ; rtx temp = gen_rtx_REG ( Pmode , IP_REGNUM ) ; rtx this_rtx = gen_rtx_REG ( Pmode , this_regno ) ; reload_completed = 1 ; emit_note ( NOTE_INSN_PROLOGUE_END ) ; if ( delta != 0 ) arm_split_constant ( PLUS , Pmode , NULL_RTX , delta , this_rtx , this_rtx , false ) ; if ( vcall_offset != 0 ) { emit_move_insn ( temp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; arm_split_constant ( PLUS , Pmode , NULL_RTX , vcall_offset , temp , temp , false ) ; emit_move_insn ( temp , gen_rtx_MEM ( Pmode , temp ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = 1 ; } rtx funexp = XEXP ( DECL_RTL ( function ) , 0 ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; rtx_insn * insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = 1 ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , 1 ) ; final ( insn , file , 1 ) ; final_end_function ( ) ; reload_completed = 0 ; } </s>


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { machine_mode mode ; if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( ! arm_pic_data_is_text_relative || ( GET_CODE ( x ) == SYMBOL_REF && ( ! SYMBOL_REF_LOCAL_P ( x ) || ( SYMBOL_REF_DECL ( x ) ? DECL_WEAK ( SYMBOL_REF_DECL ( x ) ) : 0 ) ) ) ) fputs ( "(GOT)" , asm_out_file ) ; else fputs ( "(GOTOFF)" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } else for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , GET_MODE_INNER ( mode ) , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s> static bool arm_const_not_ok_for_debug_p ( rtx p ) { tree decl_op0 = NULL ; tree decl_op1 = NULL ; if ( GET_CODE ( p ) == MINUS ) { if ( GET_CODE ( XEXP ( p , 1 ) ) == SYMBOL_REF ) { decl_op1 = SYMBOL_REF_DECL ( XEXP ( p , 1 ) ) ; if ( decl_op1 && GET_CODE ( XEXP ( p , 0 ) ) == SYMBOL_REF && ( decl_op0 = SYMBOL_REF_DECL ( XEXP ( p , 0 ) ) ) ) { if ( ( VAR_P ( decl_op1 ) || TREE_CODE ( decl_op1 ) == CONST_DECL ) && ( VAR_P ( decl_op0 ) || TREE_CODE ( decl_op0 ) == CONST_DECL ) ) return ( get_variable_section ( decl_op1 , false ) != get_variable_section ( decl_op0 , false ) ) ; if ( TREE_CODE ( decl_op1 ) == LABEL_DECL && TREE_CODE ( decl_op0 ) == LABEL_DECL ) return ( DECL_CONTEXT ( decl_op1 ) != DECL_CONTEXT ( decl_op0 ) ) ; } return true ; } } return false ; } </s>

This is a temporary fix for PR60655 . Ideally we need to handle most of these cases in the generic part but currently we reject minus ( .. ) ( sym_ref ) . We try to ameliorate the case with minus ( sym_ref1 ) ( sym_ref2 ) where they are in the same section .


<s> bool arm_coproc_builtin_available ( enum unspecv builtin ) { if ( TARGET_THUMB1 ) return false ; switch ( builtin ) { case VUNSPEC_CDP : case VUNSPEC_LDC : case VUNSPEC_LDCL : case VUNSPEC_STC : case VUNSPEC_STCL : case VUNSPEC_MCR : case VUNSPEC_MRC : if ( arm_arch4 ) return true ; break ; case VUNSPEC_CDP2 : case VUNSPEC_LDC2 : case VUNSPEC_LDC2L : case VUNSPEC_STC2 : case VUNSPEC_STC2L : case VUNSPEC_MCR2 : case VUNSPEC_MRC2 : if ( arm_arch5 ) return true ; break ; case VUNSPEC_MCRR : case VUNSPEC_MRRC : if ( arm_arch6 || arm_arch5te ) return true ; break ; case VUNSPEC_MCRR2 : case VUNSPEC_MRRC2 : if ( arm_arch6 ) return true ; break ; default : gcc_unreachable ( ) ; } return false ; } </s>

This function checks for the availability of the coprocessor builtin passed in BUILTIN for the current target . Returns true if it is available and false otherwise . If a BUILTIN is passed for which this function has not been implemented it will cause an exception .


<s>
void
arm_declare_function_name
(
FILE
*
stream
,
const
char
*
name
,
tree
decl
)
{
fprintf
(
stream
,
"\t.syntax unified\n"
)
;
if
(
TARGET_THUMB
)
{
if
(
is_called_in_ARM_mode
(
decl
)
||
(
TARGET_THUMB1
&&
!
TARGET_THUMB1_ONLY
&&
cfun
->
is_thunk
)
)
fprintf
(
stream
,
"\t.code 32\n"
)
;
else
if
(
TARGET_THUMB1
)
fprintf
(
stream
,
"\t.code\t16\n\t.thumb_func\n"
)
;
else
fprintf
(
stream
,
"\t.thumb\n\t.thumb_func\n"
)
;
}
else
fprintf
(
stream
,
"\t.arm\n"
)
;
asm_fprintf
(
asm_out_file
,
"\t.fpu %s\n"
,
(
TARGET_SOFT_FLOAT
"softvfp"
:
arm_identify_fpu_from_isa
(
arm_active_target
.
isa
)
)
)
;
if
(
TARGET_POKE_FUNCTION_NAME
)
arm_poke_function_name
(
stream
,
(
const
char
*
)
name
)
;
}
</s>

Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .


<s> static bool arm_evpc_neon_vext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ 0 ] + 1 ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = 1 ; i < nelt ; next ++ , i ++ ) { if ( next == 2 * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == 2 ) && ( d -> vmode != V2DImode ) ) return false ; else next = 0 ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ 0 ] ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vextv16qi ; break ; case V8QImode : gen = gen_neon_vextv8qi ; break ; case V4HImode : gen = gen_neon_vextv4hi ; break ; case V8HImode : gen = gen_neon_vextv8hi ; break ; case V2SImode : gen = gen_neon_vextv2si ; break ; case V4SImode : gen = gen_neon_vextv4si ; break ; case V4HFmode : gen = gen_neon_vextv4hf ; break ; case V8HFmode : gen = gen_neon_vextv8hf ; break ; case V2SFmode : gen = gen_neon_vextv2sf ; break ; case V4SFmode : gen = gen_neon_vextv4sf ; break ; case V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s> static bool arm_evpc_neon_vrev ( struct expand_vec_perm_d * d ) { unsigned int i , j , diff , nelt = d -> nelt ; rtx ( * gen ) ( rtx , rtx ) ; if ( ! d -> one_vector_p ) return false ; diff = d -> perm [ 0 ] ; switch ( diff ) { case 7 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev64v16qi ; break ; case V8QImode : gen = gen_neon_vrev64v8qi ; break ; default : return false ; } break ; case 3 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev32v16qi ; break ; case V8QImode : gen = gen_neon_vrev32v8qi ; break ; case V8HImode : gen = gen_neon_vrev64v8hi ; break ; case V4HImode : gen = gen_neon_vrev64v4hi ; break ; case V8HFmode : gen = gen_neon_vrev64v8hf ; break ; case V4HFmode : gen = gen_neon_vrev64v4hf ; break ; default : return false ; } break ; case 1 : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev16v16qi ; break ; case V8QImode : gen = gen_neon_vrev16v8qi ; break ; case V8HImode : gen = gen_neon_vrev32v8hi ; break ; case V4HImode : gen = gen_neon_vrev32v4hi ; break ; case V4SImode : gen = gen_neon_vrev64v4si ; break ; case V2SImode : gen = gen_neon_vrev64v2si ; break ; case V4SFmode : gen = gen_neon_vrev64v4sf ; break ; case V2SFmode : gen = gen_neon_vrev64v2sf ; break ; default : return false ; } break ; default : return false ; } for ( i = 0 ; i < nelt ; i += diff + 1 ) for ( j = 0 ; j <= diff ; j += 1 ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] != i + diff - j ) return false ; } if ( d -> testing_p ) return true ; emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } </s>


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vtrnv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vtrnv4hf_internal ; break ; case V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { std :: swap ( in0 , in1 ) ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == 8 ? d -> nelt : 0 ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) odd = 0 ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 1 ) ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * 2 + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vuzpv16qi_internal ; break ; case V8QImode : gen = gen_neon_vuzpv8qi_internal ; break ; case V8HImode : gen = gen_neon_vuzpv8hi_internal ; break ; case V4HImode : gen = gen_neon_vuzpv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vuzpv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vuzpv4hf_internal ; break ; case V4SImode : gen = gen_neon_vuzpv4si_internal ; break ; case V2SImode : gen = gen_neon_vuzpv2si_internal ; break ; case V2SFmode : gen = gen_neon_vuzpv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vuzpv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( swap_nelt != 0 ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> static bool arm_evpc_neon_vzip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ^ is_swapped ] ; high = nelt / 2 ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case V8HFmode : gen = gen_neon_vzipv8hf_internal ; break ; case V4HFmode : gen = gen_neon_vzipv4hf_internal ; break ; case V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case V2SFmode : gen = gen_neon_vzipv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vzipv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( is_swapped ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( high ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> void arm_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode ; rtx ( * gen ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } bdst = TARGET_THUMB1 ? bval : gen_rtx_REG ( CCmode , CC_REGNUM ) ; emit_insn ( gen ( bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; if ( TARGET_THUMB1 ) emit_insn ( gen_cstoresi_eq0_thumb1 ( bval , bdst ) ) ; else { x = gen_rtx_EQ ( SImode , bdst , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } } </s>


<s> static void arm_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { if ( mode == SImode ) gcc_assert ( ! TARGET_IDIV ) ; machine_mode libval_mode = smallest_mode_for_size ( 2 * GET_MODE_BITSIZE ( mode ) , MODE_INT ) ; rtx libval = emit_library_call_value ( libfunc , NULL_RTX , LCT_CONST , libval_mode , 2 , op0 , GET_MODE ( op0 ) , op1 , GET_MODE ( op1 ) ) ; rtx quotient = simplify_gen_subreg ( mode , libval , libval_mode , 0 ) ; rtx remainder = simplify_gen_subreg ( mode , libval , libval_mode , GET_MODE_SIZE ( mode ) ) ; gcc_assert ( quotient ) ; gcc_assert ( remainder ) ; * quot_p = quotient ; * rem_p = remainder ; } </s>

Generate call to __aeabi_ [ mode ] divmod ( op0 , op1 ) .


<s> static machine_mode arm_floatn_mode ( int n , bool extended ) { if ( ! extended && n == 16 ) return arm_fp16_format == ARM_FP16_FORMAT_IEEE ? HFmode : VOIDmode ; return default_floatn_mode ( n , extended ) ; } </s>

Implement TARGET_FLOATN_MODE . Make very sure that we do n't provide _Float16 if we are using anything other than ieee format for 16-bit floating point . Otherwise , punt to the default implementation .


<s> bool arm_frame_pointer_required ( void ) { if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( TARGET_ARM && TARGET_APCS_FRAME && ! crtl -> is_leaf ) return true ; if ( ! IS_INTERRUPT ( arm_current_func_type ( ) ) && flag_stack_check == STATIC_BUILTIN_STACK_CHECK && arm_except_unwind_info ( & global_options ) == UI_TARGET && cfun -> can_throw_non_call_exceptions ) { HOST_WIDE_INT size = get_frame_size ( ) ; if ( size <= 0 ) return false ; if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { size += 32 * UNITS_PER_WORD ; if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) return true ; } else return true ; } return false ; } </s>


"parameter passing for argument of type "

Determine where to put an argument to a function . Value is zero to push the argument on the stack , or a hard register in which to store the argument . MODE is the argument 's machine mode . TYPE is the data type of the argument ( as a tree ) . This is null for libcalls where that information may not be available . CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called . NAMED is nonzero if this argument is a named parameter ( otherwise it is an extra parameter matching an ellipsis ) . On the ARM , normally the first 16 bytes are passed in registers r0-r3 ; all other arguments are passed on the stack . If ( NAMED == 0 ) ( which happens only in assign_parms , since TARGET_SETUP_INCOMING_VARARGS is defined ) , say it is passed in the stack ( function_prologue will indeed make it pass in the stack if necessary ) .


<s> static bool arm_function_ok_for_sibcall ( tree decl , tree exp ) { unsigned long func_type ; if ( cfun -> machine -> sibcall_blocked ) return false ; if ( TARGET_THUMB1 ) return false ; if ( TARGET_VXWORKS_RTP && flag_pic && decl && ! targetm . binds_local_p ( decl ) ) return false ; if ( TARGET_APCS_FRAME && TARGET_ARM && TARGET_HARD_FLOAT && decl && arm_is_long_call_p ( decl ) ) return false ; if ( TARGET_INTERWORK && decl && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; func_type = arm_current_func_type ( ) ; if ( IS_INTERRUPT ( func_type ) ) return false ; if ( IS_CMSE_ENTRY ( arm_current_func_type ( ) ) ) return false ; if ( TREE_CODE ( exp ) == CALL_EXPR ) { tree fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; if ( lookup_attribute ( "cmse_nonsecure_call" , TYPE_ATTRIBUTES ( fntype ) ) ) return false ; } if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; tree decl_or_type = decl ; if ( ! decl ) decl_or_type = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; a = arm_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( ! rtx_equal_p ( a , b ) ) return false ; } if ( IS_STACKALIGN ( func_type ) ) return false ; if ( TARGET_AAPCS_BASED && arm_abi == ARM_ABI_AAPCS && decl && DECL_WEAK ( decl ) ) return false ; if ( ! decl && CALL_EXPR_BY_DESCRIPTOR ( exp ) && ! flag_trampolines ) { tree fntype = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; CUMULATIVE_ARGS cum ; cumulative_args_t cum_v ; arm_init_cumulative_args ( & cum , fntype , NULL_RTX , NULL_TREE ) ; cum_v = pack_cumulative_args ( & cum ) ; for ( tree t = TYPE_ARG_TYPES ( fntype ) ; t ; t = TREE_CHAIN ( t ) ) { tree type = TREE_VALUE ( t ) ; if ( ! VOID_TYPE_P ( type ) ) arm_function_arg_advance ( cum_v , TYPE_MODE ( type ) , type , true ) ; } if ( ! arm_function_arg ( cum_v , SImode , integer_type_node , true ) ) return false ; } return true ; } </s>

Return non-zero if it is ok to make a tail-call to DECL .


<s> static int arm_get_vfp_saved_size ( void ) { unsigned int regno ; int count ; int saved ; saved = 0 ; if ( TARGET_HARD_FLOAT ) { count = 0 ; for ( regno = FIRST_VFP_REGNUM ; regno < LAST_VFP_REGNUM ; regno += 2 ) { if ( ( ! df_regs_ever_live_p ( regno ) || call_used_regs [ regno ] ) && ( ! df_regs_ever_live_p ( regno + 1 ) || call_used_regs [ regno + 1 ] ) ) { if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } count = 0 ; } else count ++ ; } if ( count > 0 ) { if ( count == 2 && ! arm_arch6 ) count ++ ; saved += count * 8 ; } } return saved ; } </s>

Return the number of bytes required to save VFP registers .


"%qE attribute ignored without -mcmse option."

"%qE attribute only applies to base type of a "

Called upon detection of the use of the cmse_nonsecure_call attribute , this function will check whether the attribute is allowed here and will add the attribute to the function type tree or otherwise issue a diagnostic . The reason we check this at declaration time is to only allow the use of the attribute with declarations of function pointers and not function declarations . This function checks NODE is of the expected type and issues diagnostics otherwise using NAME . If it is not of the expected type * NO_ADD_ATTRS will be set to true .


"%qE attribute only applies to functions"

"%qE attribute has no effect on functions "

Called upon detection of the use of the cmse_nonsecure_entry attribute , this function will check whether the attribute is allowed here and will add the attribute to the function declaration tree or otherwise issue a warning .


<s> int arm_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_HARD_FLOAT && regno == VFPCC_REGNUM ) ) ; if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_HARD_FLOAT && IS_VFP_REGNUM ( regno ) ) { if ( mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == DFmode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == HImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , 2 ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , 3 ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , 6 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ; return FALSE ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) { if ( ARM_NUM_REGS ( mode ) > 4 ) return FALSE ; if ( TARGET_THUMB2 ) return TRUE ; return ! ( TARGET_LDRD && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; } if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return FALSE ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


<s> static const char * arm_identify_fpu_from_isa ( sbitmap isa ) { auto_sbitmap fpubits ( isa_num_bits ) ; auto_sbitmap cand_fpubits ( isa_num_bits ) ; bitmap_and ( fpubits , isa , isa_all_fpubits ) ; if ( bitmap_empty_p ( fpubits ) ) return "softvfp" ; for ( unsigned int i = 0 ; i < ARRAY_SIZE ( all_fpus ) ; i ++ ) { arm_initialize_isa ( cand_fpubits , all_fpus [ i ] . isa_bits ) ; if ( bitmap_equal_p ( fpubits , cand_fpubits ) ) return all_fpus [ i ] . name ; } gcc_unreachable ( ) ; } </s>

Match an ISA feature bitmap to a named FPU . We always use the first entry that exactly matches the feature set , so that we effectively canonicalize the FPU name for the assembler .


<s> static void arm_initialize_isa ( sbitmap isa , const enum isa_feature * isa_bits ) { bitmap_clear ( isa ) ; while ( * isa_bits != isa_nobit ) bitmap_set_bit ( isa , * ( isa_bits ++ ) ) ; } </s>

Convert a static initializer array of feature bits to sbitmap representation .


<s> static int arm_needs_doubleword_align ( machine_mode mode , const_tree type ) { if ( ! type ) return GET_MODE_ALIGNMENT ( mode ) > PARM_BOUNDARY ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) > PARM_BOUNDARY ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) > PARM_BOUNDARY ; int ret = 0 ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( DECL_ALIGN ( field ) > PARM_BOUNDARY ) { if ( TREE_CODE ( field ) == FIELD_DECL ) return 1 ; else ret = - 1 ; } return ret ; } </s>

Return 1 if double word alignment is required for argument passing . Return -1 if double word alignment used to be required for argument passing before PR77728 ABI fix , but is not required anymore . Return 0 if double word alignment is not required and was n't requried before either .


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"-g with -mno-apcs-frame may not give sensible debugging"

"can not use -mtp=cp15 with 16-bit Thumb"

"-mslow-flash-data only supports non-pic code on armv7-m targets"

"-mpure-code only supports non-pic code on armv7-m targets"

Check any incompatible options that the user has specified .


"target CPU does not support THUMB instructions"

"target CPU does not support unaligned accesses"

Reset options between modes that the user has specified .


<s>
static
void
arm_option_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
int
flags
=
ptr
->
x_target_flags
;
const
char
*
fpu_name
;
fpu_name
=
(
ptr
->
x_arm_fpu_index
==
TARGET_FPU_auto
"auto"
:
all_fpus
[
ptr
->
x_arm_fpu_index
]
.
name
)
;
fprintf
(
file
,
"%*sselected arch %s\n"
,
indent
,
""
,
TARGET_THUMB2_P
(
flags
)
"thumb2"
:
TARGET_THUMB_P
(
flags
)
"thumb1"
:
"arm"
)
;
fprintf
(
file
,
"%*sselected fpu %s\n"
,
indent
,
""
,
fpu_name
)
;
}
</s>

arm
"auto"
"%*sselected arch %s\n"
""
"thumb2"
"thumb1"
"arm"
"%*sselected fpu %s\n"
""


<s> static void arm_option_restore ( struct gcc_options * , struct cl_target_option * ptr ) { arm_configure_build_target ( & arm_active_target , ptr , & global_options_set , false ) ; } </s>


"\t%@ Function supports interworking.\n"

"\t%@ Fast Interrupt Service Routine.\n"

"\t%@ Naked Function: prologue and epilogue provided by programmer.\n"

"\t%@ Volatile: function does not return.\n"

"\t%@ Nested: function declared inside another function.\n"

"\t%@ Stack Align: May be called with mis-aligned SP.\n"

"\t%@ Non-secure entry function: called from non-secure code.\n"

"\t%@ args = %d, pretend = %d, frame = %wd\n"

"\t%@ frame_needed = %d, uses_anonymous_args = %d\n"

Place some comments into the assembler stream describing the current function .


<s> static void arm_output_mi_thunk ( FILE * file , tree thunk , HOST_WIDE_INT delta , HOST_WIDE_INT vcall_offset , tree function ) { if ( TARGET_32BIT ) arm32_output_mi_thunk ( file , thunk , delta , vcall_offset , function ) ; else arm_thumb1_mi_thunk ( file , thunk , delta , vcall_offset , function ) ; } </s>

Output code to add DELTA to the first argument , and then jump to FUNCTION . Used for C++ multiple inheritance .


<s> static rtx_insn * arm_pic_static_addr ( rtx orig , rtx reg ) { rtx l1 , labelno , offset_rtx ; gcc_assert ( flag_pic ) ; labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; offset_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; offset_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , orig , offset_rtx ) , UNSPEC_SYMBOL_OFFSET ) ; offset_rtx = gen_rtx_CONST ( Pmode , offset_rtx ) ; return emit_insn ( gen_pic_load_addr_unified ( reg , offset_rtx , labelno ) ) ; } </s>

Generate code to load the address of a static var when flag_pic is set .


This function is used to print CPU tuning information as comment in assembler file . Pointers are not printed for now .


<s>
static
bool
arm_rtx_costs
(
rtx
x
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
outer_code
,
int
opno
ATTRIBUTE_UNUSED
,
int
*
total
,
bool
speed
)
{
bool
result
;
int
code
=
GET_CODE
(
x
)
;
gcc_assert
(
current_tune
->
insn_extra_cost
)
;
result
=
arm_rtx_costs_internal
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
current_tune
->
insn_extra_cost
,
total
,
speed
)
;
if
(
dump_file
&&
(
dump_flags
&
TDF_DETAILS
)
)
{
print_rtl_single
(
dump_file
,
x
)
;
fprintf
(
dump_file
,
"\n%s cost: %d (%s)\n"
,
speed
"Hot"
:
"Cold"
,
*
total
,
result
"final"
:
"partial"
)
;
}
return
result
;
}
</s>

arm
"\n%s cost: %d (%s)\n"
"Hot"
"Cold"
"final"
"partial"


<s> static int arm_save_coproc_regs ( void ) { int saved_size = 0 ; unsigned reg ; unsigned start_reg ; rtx insn ; for ( reg = LAST_IWMMXT_REGNUM ; reg >= FIRST_IWMMXT_REGNUM ; reg -- ) if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) { insn = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; insn = gen_rtx_MEM ( V2SImode , insn ) ; insn = emit_set_insn ( insn , gen_rtx_REG ( V2SImode , reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = 1 ; saved_size += 8 ; } if ( TARGET_HARD_FLOAT ) { start_reg = FIRST_VFP_REGNUM ; for ( reg = FIRST_VFP_REGNUM ; reg < LAST_VFP_REGNUM ; reg += 2 ) { if ( ( ! df_regs_ever_live_p ( reg ) || call_used_regs [ reg ] ) && ( ! df_regs_ever_live_p ( reg + 1 ) || call_used_regs [ reg + 1 ] ) ) { if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; start_reg = reg + 2 ; } } if ( start_reg != reg ) saved_size += vfp_emit_fstmd ( start_reg , ( reg - start_reg ) / 2 ) ; } return saved_size ; } </s>

Emit RTL to save coprocessor registers on function entry . Returns the number of bytes pushed .


<s>
static
void
arm_setup_incoming_varargs
(
cumulative_args_t
pcum_v
,
machine_mode
mode
,
tree
type
,
int
*
pretend_size
,
int
second_time
ATTRIBUTE_UNUSED
)
{
CUMULATIVE_ARGS
*
pcum
=
get_cumulative_args
(
pcum_v
)
;
int
nregs
;
cfun
->
machine
->
uses_anonymous_args
=
1
;
if
(
pcum
->
pcs_variant
<=
ARM_PCS_AAPCS_LOCAL
)
{
nregs
=
pcum
->
aapcs_ncrn
;
if
(
nregs
&
1
)
{
int
res
=
arm_needs_doubleword_align
(
mode
,
type
)
;
if
(
res
<
0
&&
warn_psabi
)
inform
(
input_location
,
"parameter passing for argument of "
"type %qT changed in GCC 7.1"
,
type
)
;
else
if
(
res
>
0
)
nregs
++
;
}
}
else
nregs
=
pcum
->
nregs
;
if
(
nregs
<
NUM_ARG_REGS
)
*
pretend_size
=
(
NUM_ARG_REGS
nregs
)
*
UNITS_PER_WORD
;
}
</s>

Worker function for TARGET_SETUP_INCOMING_VARARGS . On the ARM , PRETEND_SIZE is set in order to have the prologue push the last named arg and all anonymous args onto the stack . XXX I know the prologue should n't be pushing registers , but it is faster that way .


<s> void arm_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , neg_bval ; machine_mode mode ; enum memmodel mod_s , mod_f ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = ( operands [ 5 ] != const0_rtx ) ; mod_s = memmodel_from_int ( INTVAL ( operands [ 6 ] ) ) ; mod_f = memmodel_from_int ( INTVAL ( operands [ 7 ] ) ) ; neg_bval = TARGET_THUMB1 ? operands [ 0 ] : operands [ 8 ] ; mode = GET_MODE ( mem ) ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( mod_s ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_release ( mod_s ) ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_acquire ( mod_s ) ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; if ( TARGET_32BIT ) { cond = arm_gen_compare_reg ( NE , rval , oldval , neg_bval ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } else { emit_move_insn ( neg_bval , const1_rtx ) ; cond = gen_rtx_NE ( VOIDmode , rval , oldval ) ; if ( thumb1_cmpneg_operand ( oldval , SImode ) ) emit_unlikely_jump ( gen_cbranchsi4_scratch ( neg_bval , rval , oldval , label2 , cond ) ) ; else emit_unlikely_jump ( gen_cbranchsi4_insn ( cond , rval , oldval , label2 ) ) ; } arm_emit_store_exclusive ( mode , neg_bval , mem , newval , use_release ) ; if ( TARGET_32BIT ) { cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , neg_bval , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; } if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , neg_bval , const0_rtx ) ; emit_unlikely_jump ( gen_cbranchsi4 ( x , neg_bval , const0_rtx , label1 ) ) ; } if ( ! is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; if ( is_armv8_sync || ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( mod_s ) ; if ( is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; } </s>

Split a compare and swap pattern . It is IMPLEMENTATION DEFINED whether another memory store between the load-exclusive and store-exclusive can reset the monitor from Exclusive to Open state . This means we must wait until after reload to split the pattern , lest we get a register spill in the middle of the atomic sequence .


<s> bool arm_validize_comparison ( rtx * comparison , rtx * op1 , rtx * op2 ) { enum rtx_code code = GET_CODE ( * comparison ) ; int code_int ; machine_mode mode = ( GET_MODE ( * op1 ) == VOIDmode ) ? GET_MODE ( * op2 ) : GET_MODE ( * op1 ) ; gcc_assert ( GET_MODE ( * op1 ) != VOIDmode || GET_MODE ( * op2 ) != VOIDmode ) ; if ( code == UNEQ || code == LTGT ) return false ; code_int = ( int ) code ; arm_canonicalize_comparison ( & code_int , op1 , op2 , 0 ) ; PUT_CODE ( * comparison , ( enum rtx_code ) code_int ) ; switch ( mode ) { case SImode : if ( ! arm_add_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_add_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case DImode : if ( ! cmpdi_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! cmpdi_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case HFmode : if ( ! TARGET_VFP_FP16INST ) break ; mode = SFmode ; * op1 = convert_to_mode ( mode , * op1 , 1 ) ; * op2 = convert_to_mode ( mode , * op2 , 1 ) ; case SFmode : case DFmode : if ( ! vfp_compare_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! vfp_compare_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; default : break ; } return false ; } </s>

Returns true if a valid comparison operation and makes the operands in a form that is valid .


"attribute %<target%> argument not a string"

"invalid fpu for attribute(target(\"%s\"))"

"auto fpu selection not currently permitted here"

Inner function to process the attribute ( ( target ( ... ) ) ) , take an argument and set the current options from the argument . If we have a list , recursively go over the list .


<s> tree arm_valid_target_attribute_tree ( tree args , struct gcc_options * opts , struct gcc_options * opts_set ) { struct cl_target_option cl_opts ; if ( ! arm_valid_target_attribute_rec ( args , opts ) ) return NULL_TREE ; cl_target_option_save ( & cl_opts , opts ) ; arm_configure_build_target ( & arm_active_target , & cl_opts , opts_set , false ) ; arm_option_check_internal ( opts ) ; arm_option_override_internal ( opts , opts_set ) ; return build_target_option_node ( opts ) ; } </s>

Return a TARGET_OPTION_NODE tree of the target options listed or NULL .


"%qE attribute not available to functions with arguments "

"%qE attribute not available to functions with variable number "

"%qE attribute not available to functions that return value on "

This function returns true if a function with declaration FNDECL and type FNTYPE uses the stack to pass arguments or return variables and false otherwise . This is used for functions with the attributes 'cmse_nonsecure_call ' or 'cmse_nonsecure_entry ' and this function will issue diagnostic messages if the stack is used . NAME is the name of the attribute used .


<s> static void emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; rtx_insn * jump = emit_jump_insn ( insn ) ; add_int_reg_note ( jump , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> rtx legitimize_tls_address ( rtx x , rtx reg ) { rtx dest , tp , label , labelno , sum , ret , eqv , addend ; rtx_insn * insns ; unsigned int model = SYMBOL_REF_TLS_MODEL ( x ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_GD32 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; } return dest ; case TLS_MODEL_LOCAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; dest = gen_rtx_PLUS ( Pmode , dest , addend ) ; } return dest ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 4 , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? 8 : 4 ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else if ( TARGET_THUMB2 ) emit_insn ( gen_tls_load_dot_plus_four ( reg , NULL , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp ( NULL_RTX ) ; reg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LE32 ) ) , UNSPEC_TLS ) ; reg = force_reg ( SImode , gen_rtx_CONST ( SImode , reg ) ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; default : abort ( ) ; } } </s>

ADDR contains a thread-local SYMBOL_REF . Generate code to compute this ( thread-local ) address .


<s> static unsigned long thumb1_compute_save_reg_mask ( void ) { unsigned long mask ; unsigned reg ; mask = 0 ; for ( reg = 0 ; reg < 12 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; if ( frame_pointer_needed ) mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & 0xff || thumb_force_lr_save ( ) ) mask |= ( 1 << LR_REGNUM ) ; if ( ( mask & 0xff ) == 0 && ( ( mask & 0x0f00 ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( 1 << LAST_LO_REGNUM ) ; if ( reg * UNITS_PER_WORD <= ( unsigned ) arm_size_return_regs ( ) ) reg = LAST_LO_REGNUM ; if ( callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; } if ( ( CALLER_INTERWORKING_SLOT_SIZE + ROUND_UP_WORD ( get_frame_size ( ) ) + crtl -> outgoing_args_size ) >= 504 ) { for ( reg = LAST_ARG_REGNUM + 1 ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( mask & ( 1 << reg ) ) break ; if ( reg > LAST_LO_REGNUM ) { mask |= 1 << LAST_LO_REGNUM ; } } return mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function .


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || mode == DFmode ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return 0 ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return ( offset > - 256 && offset < 256 ) ; return ( use_ldrd && offset > - 1024 && offset < 1024 && ( offset & 3 ) == 0 ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( arm_disable_literal_pool && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) return 0 ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid Thumb-2 address operand .


<s> static int thumb2_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ) { enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_HARD_FLOAT && ( mode == SFmode || mode == DFmode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 256 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) { if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1016 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; return val > - 256 && val < 256 && ( val & 3 ) == 0 ; } else return 0 ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > 0 && INTVAL ( op ) <= 3 ) ; } return ( code == CONST_INT && INTVAL ( index ) < 4096 && INTVAL ( index ) > - 256 ) ; } </s>

Return nonzero if INDEX is a valid Thumb-2 address index operand .


<s>
static
void
thumb_pop
(
FILE
*
f
,
unsigned
long
mask
)
{
int
regno
;
int
lo_mask
=
mask
&
0xFF
;
int
pushed_words
=
0
;
gcc_assert
(
mask
)
;
if
(
lo_mask
==
0
&&
(
mask
&
(
1
<<
PC_REGNUM
)
)
)
{
thumb_exit
(
f
,
1
)
;
return
;
}
fprintf
(
f
,
"\tpop\t{"
)
;
for
(
regno
=
0
;
regno
<=
LAST_LO_REGNUM
;
regno
++
,
lo_mask
>>=
1
)
{
if
(
lo_mask
&
1
)
{
asm_fprintf
(
f
,
"%r"
,
regno
)
;
if
(
(
lo_mask
&
~
1
)
!=
0
)
fprintf
(
f
,
", "
)
;
pushed_words
++
;
}
}
if
(
mask
&
(
1
<<
PC_REGNUM
)
)
{
if
(
TARGET_INTERWORK
||
TARGET_BACKTRACE
||
crtl
->
calls_eh_return
||
IS_CMSE_ENTRY
(
arm_current_func_type
(
)
)
)
{
fprintf
(
f
,
"}\n"
)
;
thumb_exit
(
f
,
1
)
;
return
;
}
else
{
if
(
mask
&
0xFF
)
fprintf
(
f
,
", "
)
;
asm_fprintf
(
f
,
"%r"
,
PC_REGNUM
)
;
}
}
fprintf
(
f
,
"}\n"
)
;
}
</s>

Emit code to push or pop registers to or from the stack . F is the assembly file . MASK is the registers to pop .


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != 0 ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5 && TARGET_ARM ) { if ( ! call_used_regs [ 3 ] ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( saved_int_regs && IS_CMSE_ENTRY ( func_type ) ) return 0 ; if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_HARD_FLOAT ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s> static bool arm_array_mode_supported_p ( machine_mode mode , unsigned HOST_WIDE_INT nelems ) { if ( TARGET_NEON && ! BYTES_BIG_ENDIAN && ( VALID_NEON_DREG_MODE ( mode ) || VALID_NEON_QREG_MODE ( mode ) ) && ( nelems >= 2 && nelems <= 4 ) ) return true ; return false ; } </s>

Implements target hook array_mode_supported_p .


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { machine_mode mode ; if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( ! arm_pic_data_is_text_relative || ( GET_CODE ( x ) == SYMBOL_REF && ( ! SYMBOL_REF_LOCAL_P ( x ) || ( SYMBOL_REF_DECL ( x ) ? DECL_WEAK ( SYMBOL_REF_DECL ( x ) ) : 0 ) ) ) ) fputs ( "(GOT)" , asm_out_file ) ; else fputs ( "(GOTOFF)" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } else for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , as_a < scalar_float_mode > ( GET_MODE_INNER ( mode ) ) , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s> static void arm_compute_frame_layout ( void ) { struct arm_stack_offsets * offsets ; unsigned long func_type ; int saved ; int core_saved ; HOST_WIDE_INT frame_size ; int i ; offsets = & cfun -> machine -> stack_offsets ; frame_size = ROUND_UP_WORD ( get_frame_size ( ) ) ; offsets -> saved_args = crtl -> args . pretend_args_size ; offsets -> frame = ( offsets -> saved_args + arm_compute_static_chain_stack_bytes ( ) + ( frame_pointer_needed ? 4 : 0 ) ) ; if ( TARGET_32BIT ) { unsigned int regno ; offsets -> saved_regs_mask = arm_compute_save_core_reg_mask ( ) ; core_saved = bit_count ( offsets -> saved_regs_mask ) * 4 ; saved = core_saved ; if ( TARGET_REALLY_IWMMXT ) { for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) saved += 8 ; } func_type = arm_current_func_type ( ) ; if ( ! IS_VOLATILE ( func_type ) && TARGET_HARD_FLOAT ) saved += arm_get_vfp_saved_size ( ) ; } else { offsets -> saved_regs_mask = thumb1_compute_save_core_reg_mask ( ) ; core_saved = bit_count ( offsets -> saved_regs_mask ) * 4 ; saved = core_saved ; if ( TARGET_BACKTRACE ) saved += 16 ; } offsets -> saved_regs = offsets -> saved_args + arm_compute_static_chain_stack_bytes ( ) + saved ; offsets -> soft_frame = offsets -> saved_regs + CALLER_INTERWORKING_SLOT_SIZE ; if ( crtl -> is_leaf && frame_size == 0 && ! cfun -> calls_alloca ) { offsets -> outgoing_args = offsets -> soft_frame ; offsets -> locals_base = offsets -> soft_frame ; return ; } if ( ARM_DOUBLEWORD_ALIGN && ( offsets -> soft_frame & 7 ) ) { offsets -> soft_frame += 4 ; if ( frame_size + crtl -> outgoing_args_size == 0 ) { int reg = - 1 ; bool prefer_callee_reg_p = false ; if ( ! any_sibcall_could_use_r3 ( ) && arm_size_return_regs ( ) <= 12 && ( offsets -> saved_regs_mask & ( 1 << 3 ) ) == 0 && ( TARGET_THUMB2 || ! ( TARGET_LDRD && current_tune -> prefer_ldrd_strd ) ) ) { reg = 3 ; if ( ! TARGET_THUMB2 ) prefer_callee_reg_p = true ; } if ( reg == - 1 || prefer_callee_reg_p ) { for ( i = 4 ; i <= ( TARGET_THUMB1 ? LAST_LO_REGNUM : 11 ) ; i ++ ) { if ( ! fixed_regs [ i ] && ( offsets -> saved_regs_mask & ( 1 << i ) ) == 0 ) { reg = i ; break ; } } } if ( reg != - 1 ) { offsets -> saved_regs += 4 ; offsets -> saved_regs_mask |= ( 1 << reg ) ; } } } offsets -> locals_base = offsets -> soft_frame + frame_size ; offsets -> outgoing_args = ( offsets -> locals_base + crtl -> outgoing_args_size ) ; if ( ARM_DOUBLEWORD_ALIGN ) { if ( offsets -> outgoing_args & 7 ) offsets -> outgoing_args += 4 ; gcc_assert ( ! ( offsets -> outgoing_args & 7 ) ) ; } } </s>

Calculate stack offsets . These are used to calculate register elimination offsets and in prologue/epilogue code . Also calculates which registers should be saved .


<s> static unsigned long arm_compute_save_core_reg_mask ( void ) { unsigned int save_reg_mask = 0 ; unsigned long func_type = arm_current_func_type ( ) ; unsigned int reg ; if ( IS_NAKED ( func_type ) ) return 0 ; if ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) save_reg_mask |= ( 1 << ARM_HARD_FRAME_POINTER_REGNUM ) | ( 1 << IP_REGNUM ) | ( 1 << LR_REGNUM ) | ( 1 << PC_REGNUM ) ; save_reg_mask |= arm_compute_save_reg0_reg12_mask ( ) ; if ( df_regs_ever_live_p ( LR_REGNUM ) || ( save_reg_mask && optimize_size && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! crtl -> tail_call_emit && ! crtl -> calls_eh_return ) ) save_reg_mask |= 1 << LR_REGNUM ; if ( cfun -> machine -> lr_save_eliminated ) save_reg_mask &= ~ ( 1 << LR_REGNUM ) ; if ( TARGET_REALLY_IWMMXT && ( ( bit_count ( save_reg_mask ) + ARM_NUM_INTS ( crtl -> args . pretend_args_size + arm_compute_static_chain_stack_bytes ( ) ) ) % 2 ) != 0 ) { for ( reg = 4 ; reg <= 12 ; reg ++ ) if ( ( save_reg_mask & ( 1 << reg ) ) == 0 ) break ; if ( reg <= 12 ) save_reg_mask |= ( 1 << reg ) ; else { cfun -> machine -> sibcall_blocked = 1 ; save_reg_mask |= ( 1 << 3 ) ; } } if ( TARGET_THUMB2 && IS_NESTED ( func_type ) && flag_pic && ( save_reg_mask & THUMB2_WORK_REGS ) == 0 ) { reg = thumb_find_work_register ( 1 << 4 ) ; if ( ! call_used_regs [ reg ] ) save_reg_mask |= ( 1 << reg ) ; } return save_reg_mask ; } </s>

Compute a bit mask of which core registers need to be saved on the stack for the current function . This is used by arm_compute_frame_layout , which may add extra registers .


<s>
void
arm_declare_function_name
(
FILE
*
stream
,
const
char
*
name
,
tree
decl
)
{
tree
target_parts
=
DECL_FUNCTION_SPECIFIC_TARGET
(
decl
)
;
struct
cl_target_option
*
targ_options
;
if
(
target_parts
)
targ_options
=
TREE_TARGET_OPTION
(
target_parts
)
;
else
targ_options
=
TREE_TARGET_OPTION
(
target_option_current_node
)
;
gcc_assert
(
targ_options
)
;
std
::
string
arch_to_print
;
if
(
targ_options
->
x_arm_arch_string
)
arch_to_print
=
targ_options
->
x_arm_arch_string
;
if
(
arch_to_print
!=
arm_last_printed_arch_string
)
{
std
::
string
arch_name
=
arch_to_print
.
substr
(
0
,
arch_to_print
.
find
(
"+"
)
)
;
asm_fprintf
(
asm_out_file
,
"\t.arch %s\n"
,
arch_name
.
c_str
(
)
)
;
const
arch_option
*
arch
=
arm_parse_arch_option_name
(
all_architectures
,
"-march"
,
targ_options
->
x_arm_arch_string
)
;
auto_sbitmap
opt_bits
(
isa_num_bits
)
;
gcc_assert
(
arch
)
;
if
(
arch
->
common
.
extensions
)
{
for
(
const
struct
cpu_arch_extension
*
opt
=
arch
->
common
.
extensions
;
opt
->
name
!=
;
opt
++
)
{
if
(
!
opt
->
remove
)
{
arm_initialize_isa
(
opt_bits
,
opt
->
isa_bits
)
;
if
(
bitmap_subset_p
(
opt_bits
,
arm_active_target
.
isa
)
&&
!
bitmap_subset_p
(
opt_bits
,
isa_all_fpubits
)
)
asm_fprintf
(
asm_out_file
,
"\t.arch_extension %s\n"
,
opt
->
name
)
;
}
}
}
arm_last_printed_arch_string
=
arch_to_print
;
}
fprintf
(
stream
,
"\t.syntax unified\n"
)
;
if
(
TARGET_THUMB
)
{
if
(
is_called_in_ARM_mode
(
decl
)
||
(
TARGET_THUMB1
&&
!
TARGET_THUMB1_ONLY
&&
cfun
->
is_thunk
)
)
fprintf
(
stream
,
"\t.code 32\n"
)
;
else
if
(
TARGET_THUMB1
)
fprintf
(
stream
,
"\t.code\t16\n\t.thumb_func\n"
)
;
else
fprintf
(
stream
,
"\t.thumb\n\t.thumb_func\n"
)
;
}
else
fprintf
(
stream
,
"\t.arm\n"
)
;
std
::
string
fpu_to_print
=
TARGET_SOFT_FLOAT
"softvfp"
:
arm_identify_fpu_from_isa
(
arm_active_target
.
isa
)
;
if
(
fpu_to_print
!=
arm_last_printed_arch_string
)
{
asm_fprintf
(
asm_out_file
,
"\t.fpu %s\n"
,
fpu_to_print
.
c_str
(
)
)
;
arm_last_printed_fpu_string
=
fpu_to_print
;
}
if
(
TARGET_POKE_FUNCTION_NAME
)
arm_poke_function_name
(
stream
,
(
const
char
*
)
name
)
;
}
</s>

Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .

arm
0
"+"
"\t.arch %s\n"
"-march"
"\t.arch_extension %s\n"
"\t.syntax unified\n"
"\t.code 32\n"
"\t.code\t16\n\t.thumb_func\n"
"\t.thumb\n\t.thumb_func\n"
"\t.arm\n"
"softvfp"
"\t.fpu %s\n"


<s> static bool arm_evpc_neon_vext ( struct expand_vec_perm_d * d ) { unsigned int i , nelt = d -> perm . length ( ) ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ 0 ] + 1 ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = 1 ; i < nelt ; next ++ , i ++ ) { if ( next == 2 * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == 2 ) && ( d -> vmode != V2DImode ) ) return false ; else next = 0 ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ 0 ] ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vextv16qi ; break ; case E_V8QImode : gen = gen_neon_vextv8qi ; break ; case E_V4HImode : gen = gen_neon_vextv4hi ; break ; case E_V8HImode : gen = gen_neon_vextv8hi ; break ; case E_V2SImode : gen = gen_neon_vextv2si ; break ; case E_V4SImode : gen = gen_neon_vextv4si ; break ; case E_V4HFmode : gen = gen_neon_vextv4hf ; break ; case E_V8HFmode : gen = gen_neon_vextv8hf ; break ; case E_V2SFmode : gen = gen_neon_vextv2sf ; break ; case E_V4SFmode : gen = gen_neon_vextv4sf ; break ; case E_V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ; emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ; return true ; } </s>


<s> static bool arm_evpc_neon_vrev ( struct expand_vec_perm_d * d ) { unsigned int i , j , diff , nelt = d -> perm . length ( ) ; rtx ( * gen ) ( rtx , rtx ) ; if ( ! d -> one_vector_p ) return false ; diff = d -> perm [ 0 ] ; switch ( diff ) { case 7 : switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vrev64v16qi ; break ; case E_V8QImode : gen = gen_neon_vrev64v8qi ; break ; default : return false ; } break ; case 3 : switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vrev32v16qi ; break ; case E_V8QImode : gen = gen_neon_vrev32v8qi ; break ; case E_V8HImode : gen = gen_neon_vrev64v8hi ; break ; case E_V4HImode : gen = gen_neon_vrev64v4hi ; break ; case E_V8HFmode : gen = gen_neon_vrev64v8hf ; break ; case E_V4HFmode : gen = gen_neon_vrev64v4hf ; break ; default : return false ; } break ; case 1 : switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vrev16v16qi ; break ; case E_V8QImode : gen = gen_neon_vrev16v8qi ; break ; case E_V8HImode : gen = gen_neon_vrev32v8hi ; break ; case E_V4HImode : gen = gen_neon_vrev32v4hi ; break ; case E_V4SImode : gen = gen_neon_vrev64v4si ; break ; case E_V2SImode : gen = gen_neon_vrev64v2si ; break ; case E_V4SFmode : gen = gen_neon_vrev64v4sf ; break ; case E_V2SFmode : gen = gen_neon_vrev64v2sf ; break ; default : return false ; } break ; default : return false ; } for ( i = 0 ; i < nelt ; i += diff + 1 ) for ( j = 0 ; j <= diff ; j += 1 ) { gcc_assert ( i + j < nelt ) ; if ( d -> perm [ i + j ] != i + diff - j ) return false ; } if ( d -> testing_p ) return true ; emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } </s>


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case E_V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case E_V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case E_V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case E_V8HFmode : gen = gen_neon_vtrnv8hf_internal ; break ; case E_V4HFmode : gen = gen_neon_vtrnv4hf_internal ; break ; case E_V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case E_V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case E_V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case E_V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { std :: swap ( in0 , in1 ) ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == 8 ? nelt : 0 ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) odd = 0 ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 1 ) ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * 2 + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vuzpv16qi_internal ; break ; case E_V8QImode : gen = gen_neon_vuzpv8qi_internal ; break ; case E_V8HImode : gen = gen_neon_vuzpv8hi_internal ; break ; case E_V4HImode : gen = gen_neon_vuzpv4hi_internal ; break ; case E_V8HFmode : gen = gen_neon_vuzpv8hf_internal ; break ; case E_V4HFmode : gen = gen_neon_vuzpv4hf_internal ; break ; case E_V4SImode : gen = gen_neon_vuzpv4si_internal ; break ; case E_V2SImode : gen = gen_neon_vuzpv2si_internal ; break ; case E_V2SFmode : gen = gen_neon_vuzpv2sf_internal ; break ; case E_V4SFmode : gen = gen_neon_vuzpv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( swap_nelt != 0 ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> static bool arm_evpc_neon_vzip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> perm . length ( ) ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ^ is_swapped ] ; high = nelt / 2 ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case E_V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case E_V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case E_V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case E_V8HFmode : gen = gen_neon_vzipv8hf_internal ; break ; case E_V4HFmode : gen = gen_neon_vzipv4hf_internal ; break ; case E_V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case E_V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case E_V2SFmode : gen = gen_neon_vzipv2sf_internal ; break ; case E_V4SFmode : gen = gen_neon_vzipv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( is_swapped ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( high ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> void arm_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode ; rtx ( * gen ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case E_QImode : case E_HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case E_SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case E_DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_THUMB1 ) { switch ( mode ) { case E_QImode : gen = gen_atomic_compare_and_swapt1qi_1 ; break ; case E_HImode : gen = gen_atomic_compare_and_swapt1hi_1 ; break ; case E_SImode : gen = gen_atomic_compare_and_swapt1si_1 ; break ; case E_DImode : gen = gen_atomic_compare_and_swapt1di_1 ; break ; default : gcc_unreachable ( ) ; } } else { switch ( mode ) { case E_QImode : gen = gen_atomic_compare_and_swap32qi_1 ; break ; case E_HImode : gen = gen_atomic_compare_and_swap32hi_1 ; break ; case E_SImode : gen = gen_atomic_compare_and_swap32si_1 ; break ; case E_DImode : gen = gen_atomic_compare_and_swap32di_1 ; break ; default : gcc_unreachable ( ) ; } } bdst = TARGET_THUMB1 ? bval : gen_rtx_REG ( CC_Zmode , CC_REGNUM ) ; emit_insn ( gen ( bdst , rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; if ( TARGET_THUMB1 ) emit_insn ( gen_cstoresi_eq0_thumb1 ( bval , bdst ) ) ; else { x = gen_rtx_EQ ( SImode , bdst , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } } </s>


<s> static bool arm_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { if ( ! TARGET_32BIT ) return false ; * p1 = CC_REGNUM ; * p2 = TARGET_HARD_FLOAT ? VFPCC_REGNUM : INVALID_REGNUM ; return true ; } </s>

Implement TARGET_FIXED_CONDITION_CODE_REGS . We only have condition code registers when not targetting Thumb1 . The VFP condition register only exists when generating hard-float code .


<s> static bool arm_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return ( regno == CC_REGNUM || ( TARGET_HARD_FLOAT && regno == VFPCC_REGNUM ) ) ; if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < 2 ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_HARD_FLOAT && IS_VFP_REGNUM ( regno ) ) { if ( mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == DFmode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( mode == HImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , 2 ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , 3 ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , 4 ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , 6 ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , 8 ) ) ; return false ; } if ( TARGET_REALLY_IWMMXT ) { if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return mode == SImode ; if ( IS_IWMMXT_REGNUM ( regno ) ) return VALID_IWMMXT_REG_MODE ( mode ) ; } if ( regno <= LAST_ARM_REGNUM ) { if ( ARM_NUM_REGS ( mode ) > 4 ) return false ; if ( TARGET_THUMB2 ) return true ; return ! ( TARGET_LDRD && GET_MODE_SIZE ( mode ) > 4 && ( regno & 1 ) != 0 ) ; } if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return GET_MODE_CLASS ( mode ) == MODE_INT ; return false ; } </s>

Returns true if REGNO is a valid register for holding a quantity of type MODE .


<s> static const char * arm_identify_fpu_from_isa ( sbitmap isa ) { auto_sbitmap fpubits ( isa_num_bits ) ; auto_sbitmap cand_fpubits ( isa_num_bits ) ; bitmap_and ( fpubits , isa , isa_all_fpubits ) ; if ( bitmap_empty_p ( fpubits ) ) return "softvfp" ; for ( unsigned int i = 0 ; i < TARGET_FPU_auto ; i ++ ) { arm_initialize_isa ( cand_fpubits , all_fpus [ i ] . isa_bits ) ; if ( bitmap_equal_p ( fpubits , cand_fpubits ) ) return all_fpus [ i ] . name ; } gcc_unreachable ( ) ; } </s>

Match an ISA feature bitmap to a named FPU . We always use the first entry that exactly matches the feature set , so that we effectively canonicalize the FPU name for the assembler .


<s> static bool arm_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { if ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) ) return true ; if ( TARGET_NEON && ( VALID_NEON_DREG_MODE ( mode1 ) || VALID_NEON_QREG_MODE ( mode1 ) || VALID_NEON_STRUCT_MODE ( mode1 ) ) && ( VALID_NEON_DREG_MODE ( mode2 ) || VALID_NEON_QREG_MODE ( mode2 ) || VALID_NEON_STRUCT_MODE ( mode2 ) ) ) return true ; return false ; } </s>


"iwmmxt requires an AAPCS compatible ABI for proper operation"

"iwmmxt abi requires an iwmmxt capable cpu"

"target CPU does not support interworking"

"AAPCS does not support -mcaller-super-interworking"

"AAPCS does not support -mcallee-super-interworking"

"target CPU does not support ARMv8-M Security Extensions"

"ARMv8-M Security Extensions incompatible with selected FPU"

"-mfloat-abi=hard: selected processor lacks an FPU"

Perform some validation between the desired architecture and the rest of the options .


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"-g with -mno-apcs-frame may not give sensible debugging"

"can not use -mtp=cp15 with 16-bit Thumb"

"%s only supports non-pic code on M-profile targets with the "

Check any incompatible options that the user has specified .


<s> static void arm_option_params_internal ( void ) { if ( TARGET_THUMB1 ) { targetm . min_anchor_offset = 0 ; targetm . max_anchor_offset = 127 ; } else if ( TARGET_THUMB2 ) { targetm . min_anchor_offset = - 248 ; targetm . max_anchor_offset = 4095 ; } else { targetm . min_anchor_offset = TARGET_MIN_ANCHOR_OFFSET ; targetm . max_anchor_offset = TARGET_MAX_ANCHOR_OFFSET ; } max_insns_skipped = optimize_size ? 4 : current_tune -> max_insns_skipped ; if ( TARGET_THUMB2 ) max_insns_skipped = MIN ( max_insns_skipped , MAX_INSN_PER_IT_BLOCK ) ; } </s>

Recompute the global settings depending on target attribute options .


"selected fp16 options are incompatible"

Reconfigure global status flags from the active_target.isa .


<s>
static
void
arm_print_asm_arch_directives
(
)
{
const
arch_option
*
arch
=
arm_parse_arch_option_name
(
all_architectures
,
"-march"
,
arm_active_target
.
arch_name
)
;
auto_sbitmap
opt_bits
(
isa_num_bits
)
;
gcc_assert
(
arch
)
;
asm_fprintf
(
asm_out_file
,
"\t.arch %s\n"
,
arm_active_target
.
arch_name
)
;
arm_last_printed_arch_string
=
arm_active_target
.
arch_name
;
if
(
!
arch
->
common
.
extensions
)
return
;
for
(
const
struct
cpu_arch_extension
*
opt
=
arch
->
common
.
extensions
;
opt
->
name
!=
;
opt
++
)
{
if
(
!
opt
->
remove
)
{
arm_initialize_isa
(
opt_bits
,
opt
->
isa_bits
)
;
if
(
bitmap_subset_p
(
opt_bits
,
arm_active_target
.
isa
)
&&
!
bitmap_subset_p
(
opt_bits
,
isa_all_fpubits
)
)
asm_fprintf
(
asm_out_file
,
"\t.arch_extension %s\n"
,
opt
->
name
)
;
}
}
}
</s>

Print .arch and .arch_extension directives corresponding to the current architecture configuration .

arm
"-march"
"\t.arch %s\n"
"\t.arch_extension %s\n"


"Error: found feature bits in the ALL_FPU_INTERAL"

" group that are not defined by any FPU.\n"

Scan the static data tables generated by parsecpu.awk looking for potential issues with the data . Here we check for consistency between the fpu bits , in particular we check that ISA_ALL_FPU_INTERNAL does not contain a feature bit that is not defined by any FPU flag .


"accessing thread-local storage is not currently supported "

Return TRUE if X contains any TLS symbol references .


<s> static void arm_trampoline_init ( rtx m_tramp , tree fndecl , rtx chain_value ) { rtx fnaddr , mem , a_tramp ; emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? 8 : 12 ) ; emit_move_insn ( mem , chain_value ) ; mem = adjust_address ( m_tramp , SImode , TARGET_32BIT ? 12 : 16 ) ; fnaddr = XEXP ( DECL_RTL ( fndecl ) , 0 ) ; emit_move_insn ( mem , fnaddr ) ; a_tramp = XEXP ( m_tramp , 0 ) ; emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , "__clear_cache" ) , LCT_NORMAL , VOIDmode , a_tramp , Pmode , plus_constant ( Pmode , a_tramp , TRAMPOLINE_SIZE ) , Pmode ) ; } </s>

Emit RTL insns to initialize the variable parts of a trampoline .


<s> bool arm_validize_comparison ( rtx * comparison , rtx * op1 , rtx * op2 ) { enum rtx_code code = GET_CODE ( * comparison ) ; int code_int ; machine_mode mode = ( GET_MODE ( * op1 ) == VOIDmode ) ? GET_MODE ( * op2 ) : GET_MODE ( * op1 ) ; gcc_assert ( GET_MODE ( * op1 ) != VOIDmode || GET_MODE ( * op2 ) != VOIDmode ) ; if ( code == UNEQ || code == LTGT ) return false ; code_int = ( int ) code ; arm_canonicalize_comparison ( & code_int , op1 , op2 , 0 ) ; PUT_CODE ( * comparison , ( enum rtx_code ) code_int ) ; switch ( mode ) { case E_SImode : if ( ! arm_add_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! arm_add_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case E_DImode : if ( ! cmpdi_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! cmpdi_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; case E_HFmode : if ( ! TARGET_VFP_FP16INST ) break ; mode = SFmode ; * op1 = convert_to_mode ( mode , * op1 , 1 ) ; * op2 = convert_to_mode ( mode , * op2 , 1 ) ; case E_SFmode : case E_DFmode : if ( ! vfp_compare_operand ( * op1 , mode ) ) * op1 = force_reg ( mode , * op1 ) ; if ( ! vfp_compare_operand ( * op2 , mode ) ) * op2 = force_reg ( mode , * op2 ) ; return true ; default : break ; } return false ; } </s>

Returns true if a valid comparison operation and makes the operands in a form that is valid .


"attribute %<target%> argument not a string"

"invalid fpu for target attribute or pragma %qs"

"auto fpu selection not currently permitted here"

"invalid architecture for target attribute or pragma %qs"

"unknown target attribute or pragma %qs"

Inner function to process the attribute ( ( target ( ... ) ) ) , take an argument and set the current options from the argument . If we have a list , recursively go over the list .


<s> static void cmse_clear_registers ( sbitmap to_clear_bitmap , uint32_t * padding_bits_to_clear , int padding_bits_len , rtx scratch_reg , rtx clearing_reg ) { bool saved_clearing = false ; rtx saved_clearing_reg = NULL_RTX ; int i , regno , clearing_regno , minregno = R0_REGNUM , maxregno = minregno - 1 ; gcc_assert ( arm_arch_cmse ) ; if ( ! bitmap_empty_p ( to_clear_bitmap ) ) { minregno = bitmap_first_set_bit ( to_clear_bitmap ) ; maxregno = bitmap_last_set_bit ( to_clear_bitmap ) ; } clearing_regno = REGNO ( clearing_reg ) ; gcc_assert ( padding_bits_len <= NUM_ARG_REGS ) ; for ( i = 0 , regno = R0_REGNUM ; i < padding_bits_len ; i ++ , regno ++ ) { uint64_t mask ; rtx rtx16 , dest , cleared_reg = gen_rtx_REG ( SImode , regno ) ; if ( padding_bits_to_clear [ i ] == 0 ) continue ; if ( TARGET_THUMB1 && REGNO ( scratch_reg ) > LAST_LO_REGNUM ) { if ( ( clearing_regno > maxregno || ! bitmap_bit_p ( to_clear_bitmap , clearing_regno ) ) && ! saved_clearing ) { gcc_assert ( clearing_regno <= LAST_LO_REGNUM ) ; emit_move_insn ( scratch_reg , clearing_reg ) ; saved_clearing = true ; saved_clearing_reg = scratch_reg ; } scratch_reg = clearing_reg ; } mask = ( ~ padding_bits_to_clear [ i ] ) & 0xFFFF ; emit_move_insn ( scratch_reg , gen_int_mode ( mask , SImode ) ) ; mask = ( ~ padding_bits_to_clear [ i ] ) >> 16 ; rtx16 = gen_int_mode ( 16 , SImode ) ; dest = gen_rtx_ZERO_EXTRACT ( SImode , scratch_reg , rtx16 , rtx16 ) ; if ( mask ) emit_insn ( gen_rtx_SET ( dest , gen_int_mode ( mask , SImode ) ) ) ; emit_insn ( gen_andsi3 ( cleared_reg , cleared_reg , scratch_reg ) ) ; } if ( saved_clearing ) emit_move_insn ( clearing_reg , saved_clearing_reg ) ; if ( clearing_regno <= maxregno && bitmap_bit_p ( to_clear_bitmap , clearing_regno ) ) { emit_move_insn ( clearing_reg , const0_rtx ) ; emit_use ( clearing_reg ) ; bitmap_clear_bit ( to_clear_bitmap , clearing_regno ) ; } for ( regno = minregno ; regno <= maxregno ; regno ++ ) { if ( ! bitmap_bit_p ( to_clear_bitmap , regno ) ) continue ; if ( IS_VFP_REGNUM ( regno ) ) { if ( TARGET_VFP_DOUBLE && VFP_REGNO_OK_FOR_DOUBLE ( regno ) && bitmap_bit_p ( to_clear_bitmap , regno + 1 ) ) { emit_move_insn ( gen_rtx_REG ( DFmode , regno ) , CONST1_RTX ( DFmode ) ) ; emit_use ( gen_rtx_REG ( DFmode , regno ) ) ; regno ++ ; } else { emit_move_insn ( gen_rtx_REG ( SFmode , regno ) , CONST1_RTX ( SFmode ) ) ; emit_use ( gen_rtx_REG ( SFmode , regno ) ) ; } } else { emit_move_insn ( gen_rtx_REG ( SImode , regno ) , clearing_reg ) ; emit_use ( gen_rtx_REG ( SImode , regno ) ) ; } } } </s>

Clear registers secret before doing a cmse_nonsecure_call or returning from a cmse_nonsecure_entry function . TO_CLEAR_BITMAP indicates which registers are to be fully cleared , using the value in register CLEARING_REG if more efficient . The PADDING_BITS_LEN entries array PADDING_BITS_TO_CLEAR gives the bits that needs to be cleared in caller-saved core registers , with SCRATCH_REG used as a scratch register for that clearing . NOTE : one of three following assertions must hold : - SCRATCH_REG is a low register - CLEARING_REG is in the set of registers fully cleared ( ie . its bit is set in TO_CLEAR_BITMAP ) - CLEARING_REG is a low register .


Clear caller saved registers not used to pass return values and leaked condition flags before exiting a cmse_nonsecure_entry function .


<s> bool gen_ldm_seq ( rtx * operands , int nops , bool sort_regs ) { int regs [ MAX_LDM_STM_OPS ] , mem_order [ MAX_LDM_STM_OPS ] ; rtx mems [ MAX_LDM_STM_OPS ] ; int i , j , base_reg ; rtx base_reg_rtx ; HOST_WIDE_INT offset ; int write_back = FALSE ; int ldm_case ; rtx addr ; ldm_case = load_multiple_sequence ( operands , nops , regs , mem_order , & base_reg , & offset , ! sort_regs ) ; if ( ldm_case == 0 ) return false ; if ( sort_regs ) for ( i = 0 ; i < nops - 1 ; i ++ ) for ( j = i + 1 ; j < nops ; j ++ ) if ( regs [ i ] > regs [ j ] ) { int t = regs [ i ] ; regs [ i ] = regs [ j ] ; regs [ j ] = t ; } base_reg_rtx = gen_rtx_REG ( Pmode , base_reg ) ; if ( TARGET_THUMB1 ) { gcc_assert ( peep2_reg_dead_p ( nops , base_reg_rtx ) ) ; gcc_assert ( ldm_case == 1 || ldm_case == 5 ) ; write_back = TRUE ; } if ( ldm_case == 5 ) { rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG ( SImode , regs [ 0 ] ) ; emit_insn ( gen_addsi3 ( newbase , base_reg_rtx , GEN_INT ( offset ) ) ) ; offset = 0 ; if ( ! TARGET_THUMB1 ) base_reg_rtx = newbase ; } for ( i = 0 ; i < nops ; i ++ ) { addr = plus_constant ( Pmode , base_reg_rtx , offset + i * 4 ) ; mems [ i ] = adjust_automodify_address_nv ( operands [ nops + mem_order [ i ] ] , SImode , addr , 0 ) ; } emit_insn ( arm_gen_load_multiple_1 ( nops , regs , mems , base_reg_rtx , write_back ? offset + i * 4 : 0 ) ) ; return true ; } </s>

Called from a peephole2 expander to turn a sequence of loads into an LDM instruction . OPERANDS are the operands found by the peephole matcher ; NOPS indicates how many separate loads we are trying to combine . SORT_REGS is true if we can reorder the registers because they are used commutatively subsequently . Returns true iff we could generate a new instruction .


<s> static bool mem_ok_for_ldrd_strd ( rtx mem , rtx * base , rtx * offset , HOST_WIDE_INT * align ) { rtx addr ; gcc_assert ( base != NULL && offset != NULL ) ; if ( side_effects_p ( mem ) ) return false ; if ( GET_CODE ( mem ) == SUBREG ) return false ; gcc_assert ( MEM_P ( mem ) ) ; * offset = const0_rtx ; * align = MEM_ALIGN ( mem ) ; addr = XEXP ( mem , 0 ) ; if ( ! arm_legitimate_address_p ( DImode , addr , reload_in_progress || reload_completed ) ) return false ; if ( REG_P ( addr ) ) { * base = addr ; return true ; } else if ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == MINUS ) { * base = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return ( REG_P ( * base ) && CONST_INT_P ( * offset ) ) ; } return false ; } </s>

Helper for gen_operands_ldrd_strd . Returns true iff the memory operand MEM 's address contains an immediate offset from the base register and has no side effects , in which case it sets BASE and OFFSET accordingly .


<s> static unsigned long thumb1_compute_save_core_reg_mask ( void ) { unsigned long mask ; unsigned reg ; mask = 0 ; for ( reg = 0 ; reg < 12 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; if ( frame_pointer_needed ) mask |= 1 << HARD_FRAME_POINTER_REGNUM ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & 0xff || thumb_force_lr_save ( ) ) mask |= ( 1 << LR_REGNUM ) ; if ( ( mask & 0xff ) == 0 && ( ( mask & 0x0f00 ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( 1 << LAST_LO_REGNUM ) ; if ( reg * UNITS_PER_WORD <= ( unsigned ) arm_size_return_regs ( ) ) reg = LAST_LO_REGNUM ; if ( callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; } if ( ( CALLER_INTERWORKING_SLOT_SIZE + ROUND_UP_WORD ( get_frame_size ( ) ) + crtl -> outgoing_args_size ) >= 504 ) { for ( reg = LAST_ARG_REGNUM + 1 ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( mask & ( 1 << reg ) ) break ; if ( reg > LAST_LO_REGNUM ) { mask |= 1 << LAST_LO_REGNUM ; } } return mask ; } </s>

Compute a bit mask of which core registers need to be saved on the stack for the current function .


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || mode == DFmode ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return 0 ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return ( offset > - 256 && offset < 256 ) ; return ( use_ldrd && offset > - 1024 && offset < 1024 && ( offset & 3 ) == 0 ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( can_avoid_literal_pool_for_label_p ( x ) ) return 0 ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid Thumb-2 address operand .


<s> static int thumb2_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ) { enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_HARD_FLOAT && ( mode == SFmode || mode == DFmode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 256 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) { if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1016 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; if ( TARGET_LDRD ) return IN_RANGE ( val , - 1020 , 1020 ) && ( val & 3 ) == 0 ; else return IN_RANGE ( val , - 255 , 4095 - 4 ) ; } else return 0 ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > 0 && INTVAL ( op ) <= 3 ) ; } return ( code == CONST_INT && INTVAL ( index ) < 4096 && INTVAL ( index ) > - 256 ) ; } </s>

Return nonzero if INDEX is a valid Thumb-2 address index operand .