<s> int const_ok_for_arm ( HOST_WIDE_INT i ) { int lowbit ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) != 0 && ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) != ( ( ~ ( unsigned HOST_WIDE_INT ) 0 ) & ~ ( unsigned HOST_WIDE_INT ) 0xffffffff ) ) ) return FALSE ; i &= ( unsigned HOST_WIDE_INT ) 0xffffffff ; if ( ( i & ~ ( unsigned HOST_WIDE_INT ) 0xff ) == 0 ) return TRUE ; lowbit = ffs ( ( int ) i ) - 1 ; if ( TARGET_ARM ) lowbit &= ~ 1 ; if ( ( i & ~ ( ( ( unsigned HOST_WIDE_INT ) 0xff ) << lowbit ) ) == 0 ) return TRUE ; if ( TARGET_ARM ) { if ( lowbit <= 4 && ( ( i & ~ 0xc000003f ) == 0 || ( i & ~ 0xf000000f ) == 0 || ( i & ~ 0xfc000003 ) == 0 ) ) return TRUE ; } else { HOST_WIDE_INT v ; v = i & 0xff ; v |= v << 16 ; if ( i == v || i == ( v | ( v << 8 ) ) ) return TRUE ; v = i & 0xff00 ; v |= v << 16 ; if ( i == v ) return TRUE ; } return FALSE ; } </s>

Return TRUE if int I is a valid immediate ARM constant .


<s> int const_ok_for_dimode_op ( HOST_WIDE_INT i , enum rtx_code code ) { HOST_WIDE_INT hi_val = ( i >> 32 ) & 0xFFFFFFFF ; HOST_WIDE_INT lo_val = i & 0xFFFFFFFF ; rtx hi = GEN_INT ( hi_val ) ; rtx lo = GEN_INT ( lo_val ) ; if ( TARGET_THUMB1 ) return 0 ; switch ( code ) { case AND : case IOR : case XOR : return ( const_ok_for_op ( hi_val , code ) || hi_val == 0xFFFFFFFF ) && ( const_ok_for_op ( lo_val , code ) || lo_val == 0xFFFFFFFF ) ; case PLUS : return arm_not_operand ( hi , SImode ) && arm_add_operand ( lo , SImode ) ; default : return 0 ; } } </s>

Return true if I is a valid di mode constant for the operation CODE .


<s> int const_ok_for_op ( HOST_WIDE_INT i , enum rtx_code code ) { if ( const_ok_for_arm ( i ) ) return 1 ; switch ( code ) { case SET : if ( arm_arch_thumb2 && ( i & 0xffff0000 ) == 0 ) return 1 ; else return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; case PLUS : if ( TARGET_THUMB2 && ( ( i & 0xfffff000 ) == 0 || ( ( - i ) & 0xfffff000 ) == 0 ) ) return 1 ; case COMPARE : case EQ : case NE : case GT : case LE : case LT : case GE : case GEU : case LTU : case GTU : case LEU : case UNORDERED : case ORDERED : case UNEQ : case UNGE : case UNLT : case UNGT : case UNLE : return const_ok_for_arm ( ARM_SIGN_EXTEND ( - i ) ) ; case MINUS : case XOR : return 0 ; case IOR : if ( TARGET_THUMB2 ) return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; return 0 ; case AND : return const_ok_for_arm ( ARM_SIGN_EXTEND ( ~ i ) ) ; default : gcc_unreachable ( ) ; } } </s>

Return true if I is a valid constant for the operation CODE .


<s> enum reg_class coproc_secondary_reload_class ( machine_mode mode , rtx x , bool wb ) { if ( mode == HFmode ) { if ( ! TARGET_NEON_FP16 ) return GENERAL_REGS ; if ( s_register_operand ( x , mode ) || neon_vector_mem_operand ( x , 2 , true ) ) return NO_REGS ; return GENERAL_REGS ; } if ( TARGET_NEON && ( MEM_P ( x ) || GET_CODE ( x ) == CONST_VECTOR ) && ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT || VALID_NEON_STRUCT_MODE ( mode ) ) ) return NO_REGS ; if ( arm_coproc_mem_operand ( x , wb ) || s_register_operand ( x , mode ) ) return NO_REGS ; return GENERAL_REGS ; } </s>

Return GENERAL_REGS if a scratch register required to reload x to/from coprocessor registers . Otherwise return NO_REGS .


<s> static bool cortexa7_older_only ( rtx_insn * insn ) { if ( recog_memoized ( insn ) < 0 ) return false ; switch ( get_attr_type ( insn ) ) { case TYPE_ALU_DSP_REG : case TYPE_ALU_SREG : case TYPE_ALUS_SREG : case TYPE_LOGIC_REG : case TYPE_LOGICS_REG : case TYPE_ADC_REG : case TYPE_ADCS_REG : case TYPE_ADR : case TYPE_BFM : case TYPE_REV : case TYPE_MVN_REG : case TYPE_SHIFT_IMM : case TYPE_SHIFT_REG : case TYPE_LOAD_BYTE : case TYPE_LOAD1 : case TYPE_STORE1 : case TYPE_FFARITHS : case TYPE_FADDS : case TYPE_FFARITHD : case TYPE_FADDD : case TYPE_FMOV : case TYPE_F_CVT : case TYPE_FCMPS : case TYPE_FCMPD : case TYPE_FCONSTS : case TYPE_FCONSTD : case TYPE_FMULS : case TYPE_FMACS : case TYPE_FMULD : case TYPE_FMACD : case TYPE_FDIVS : case TYPE_FDIVD : case TYPE_F_MRC : case TYPE_F_MRRC : case TYPE_F_FLAG : case TYPE_F_LOADS : case TYPE_F_STORES : return true ; default : return false ; } } </s>

Return true if and only if this insn can dual-issue only as older .


<s> static bool cortex_a9_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int * cost ) { switch ( REG_NOTE_KIND ( link ) ) { case REG_DEP_ANTI : * cost = 0 ; return false ; case REG_DEP_TRUE : case REG_DEP_OUTPUT : if ( recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { if ( GET_CODE ( PATTERN ( insn ) ) == SET ) { if ( GET_MODE_CLASS ( GET_MODE ( SET_DEST ( PATTERN ( insn ) ) ) ) == MODE_FLOAT || GET_MODE_CLASS ( GET_MODE ( SET_SRC ( PATTERN ( insn ) ) ) ) == MODE_FLOAT ) { enum attr_type attr_type_insn = get_attr_type ( insn ) ; enum attr_type attr_type_dep = get_attr_type ( dep ) ; if ( REG_P ( SET_DEST ( PATTERN ( insn ) ) ) && REG_P ( SET_DEST ( PATTERN ( dep ) ) ) && reg_overlap_mentioned_p ( SET_DEST ( PATTERN ( insn ) ) , SET_DEST ( PATTERN ( dep ) ) ) ) { if ( ( attr_type_insn == TYPE_FMACS || attr_type_insn == TYPE_FMACD ) && ( attr_type_dep == TYPE_FMACS || attr_type_dep == TYPE_FMACD ) ) { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) - 3 ; else * cost = insn_default_latency ( dep ) ; return false ; } else { if ( REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) * cost = insn_default_latency ( dep ) + 1 ; else * cost = insn_default_latency ( dep ) ; } return false ; } } } } break ; default : gcc_unreachable ( ) ; } return true ; } </s>


<s> static Mfix * create_fix_barrier ( Mfix * fix , HOST_WIDE_INT max_address ) { HOST_WIDE_INT count = 0 ; rtx_barrier * barrier ; rtx_insn * from = fix -> insn ; rtx_insn * selected = NULL ; int selected_cost ; HOST_WIDE_INT selected_address ; Mfix * new_fix ; HOST_WIDE_INT max_count = max_address - fix -> address ; rtx_code_label * label = gen_label_rtx ( ) ; selected_cost = arm_barrier_cost ( from ) ; selected_address = fix -> address ; while ( from && count < max_count ) { rtx_jump_table_data * tmp ; int new_cost ; gcc_assert ( ! BARRIER_P ( from ) ) ; if ( LABEL_P ( from ) ) count += get_label_padding ( from ) ; else count += get_attr_length ( from ) ; if ( tablejump_p ( from , NULL , & tmp ) ) { count += get_jump_table_size ( tmp ) ; new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = tmp ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( tmp ) ; continue ; } new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && ( ! selected || new_cost <= selected_cost ) ) { selected = from ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( from ) ; } gcc_assert ( selected ) ; if ( CALL_P ( selected ) ) { rtx_insn * next = NEXT_INSN ( selected ) ; if ( next && NOTE_P ( next ) && NOTE_KIND ( next ) == NOTE_INSN_CALL_ARG_LOCATION ) selected = next ; } from = emit_jump_insn_after ( gen_jump ( label ) , selected ) ; JUMP_LABEL ( from ) = label ; barrier = emit_barrier_after ( from ) ; emit_label_after ( label , barrier ) ; new_fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * new_fix ) ) ; new_fix -> insn = barrier ; new_fix -> address = selected_address ; new_fix -> next = fix -> next ; fix -> next = new_fix ; return new_fix ; } </s>

Find the best place in the insn stream in the range ( FIX- > address , MAX_ADDRESS ) to forcibly insert a minipool barrier . Create the barrier by inserting a jump and add a new fix entry for it .


";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n"


<s> static rtx emit_multi_reg_push ( unsigned long mask , unsigned long dwarf_regs_mask ) { int num_regs = 0 ; int num_dwarf_regs = 0 ; int i , j ; rtx par ; rtx dwarf ; int dwarf_par_index ; rtx tmp , reg ; dwarf_regs_mask &= ~ ( 1 << PC_REGNUM ) ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( 1 << i ) ) num_regs ++ ; if ( dwarf_regs_mask & ( 1 << i ) ) num_dwarf_regs ++ ; } gcc_assert ( num_regs && num_regs <= 16 ) ; gcc_assert ( ( dwarf_regs_mask & ~ mask ) == 0 ) ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( num_dwarf_regs + 1 ) ) ; dwarf_par_index = 1 ; for ( i = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) { if ( mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 * num_regs ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; if ( dwarf_regs_mask & ( 1 << i ) ) { tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( SImode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ++ ) = tmp ; } break ; } } for ( j = 1 , i ++ ; j < num_regs ; i ++ ) { if ( mask & ( 1 << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , 0 , j ) = gen_rtx_USE ( VOIDmode , reg ) ; if ( dwarf_regs_mask & ( 1 << i ) ) { tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , 4 * j ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , dwarf_par_index ++ ) = tmp ; } j ++ ; } } par = emit_insn ( par ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - 4 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; add_reg_note ( par , REG_FRAME_RELATED_EXPR , dwarf ) ; return par ; } </s>

Generate and emit an insn that we will recognize as a push_multi . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> inline static rtx_insn * emit_set_insn ( rtx x , rtx y ) { return emit_insn ( gen_rtx_SET ( VOIDmode , x , y ) ) ; } </s>

Emit an insn that 's a simple single-set . Both the operands must be known to be valid .


<s> static void emit_unlikely_jump ( rtx insn ) { int very_unlikely = REG_BR_PROB_BASE / 100 - 1 ; insn = emit_jump_insn ( insn ) ; add_int_reg_note ( insn , REG_BR_PROB , very_unlikely ) ; } </s>

Mark the previous jump instruction as unlikely .


<s> inline bool libcall_hasher :: equal ( const value_type * p1 , const compare_type * p2 ) { return rtx_equal_p ( p1 , p2 ) ; } </s>


<s> static bool fa726te_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int * cost ) { if ( REG_NOTE_KIND ( link ) == REG_DEP_TRUE && recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 && get_attr_conds ( dep ) == CONDS_SET ) { if ( get_attr_conds ( insn ) == CONDS_USE && get_attr_type ( insn ) != TYPE_BRANCH ) { * cost = 3 ; return false ; } if ( GET_CODE ( PATTERN ( insn ) ) == COND_EXEC || get_attr_conds ( insn ) == CONDS_USE ) { * cost = 0 ; return false ; } } return true ; } </s>


<s> static const char * fp_const_from_val ( REAL_VALUE_TYPE * r ) { if ( ! fp_consts_inited ) init_fp_table ( ) ; gcc_assert ( REAL_VALUES_EQUAL ( * r , value_fp0 ) ) ; return "0" ; } </s>

As for fp_immediate_constant , but value is passed directly , not in rtx .


<s> bool gen_ldm_seq ( rtx * operands , int nops , bool sort_regs ) { int regs [ MAX_LDM_STM_OPS ] , mem_order [ MAX_LDM_STM_OPS ] ; rtx mems [ MAX_LDM_STM_OPS ] ; int i , j , base_reg ; rtx base_reg_rtx ; HOST_WIDE_INT offset ; int write_back = FALSE ; int ldm_case ; rtx addr ; ldm_case = load_multiple_sequence ( operands , nops , regs , mem_order , & base_reg , & offset , ! sort_regs ) ; if ( ldm_case == 0 ) return false ; if ( sort_regs ) for ( i = 0 ; i < nops - 1 ; i ++ ) for ( j = i + 1 ; j < nops ; j ++ ) if ( regs [ i ] > regs [ j ] ) { int t = regs [ i ] ; regs [ i ] = regs [ j ] ; regs [ j ] = t ; } base_reg_rtx = gen_rtx_REG ( Pmode , base_reg ) ; if ( TARGET_THUMB1 ) { gcc_assert ( peep2_reg_dead_p ( nops , base_reg_rtx ) ) ; gcc_assert ( ldm_case == 1 || ldm_case == 5 ) ; write_back = TRUE ; } if ( ldm_case == 5 ) { rtx newbase = TARGET_THUMB1 ? base_reg_rtx : gen_rtx_REG ( SImode , regs [ 0 ] ) ; emit_insn ( gen_addsi3 ( newbase , base_reg_rtx , GEN_INT ( offset ) ) ) ; offset = 0 ; if ( ! TARGET_THUMB1 ) { base_reg = regs [ 0 ] ; base_reg_rtx = newbase ; } } for ( i = 0 ; i < nops ; i ++ ) { addr = plus_constant ( Pmode , base_reg_rtx , offset + i * 4 ) ; mems [ i ] = adjust_automodify_address_nv ( operands [ nops + mem_order [ i ] ] , SImode , addr , 0 ) ; } emit_insn ( arm_gen_load_multiple_1 ( nops , regs , mems , base_reg_rtx , write_back ? offset + i * 4 : 0 ) ) ; return true ; } </s>

Called from a peephole2 expander to turn a sequence of loads into an LDM instruction . OPERANDS are the operands found by the peephole matcher ; NOPS indicates how many separate loads we are trying to combine . SORT_REGS is true if we can reorder the registers because they are used commutatively subsequently . Returns true iff we could generate a new instruction .


<s> static HOST_WIDE_INT get_label_padding ( rtx label ) { HOST_WIDE_INT align , min_insn_size ; align = 1 << label_to_alignment ( label ) ; min_insn_size = TARGET_THUMB ? 2 : 4 ; return align > min_insn_size ? align - min_insn_size : 0 ; } </s>

Return the maximum amount of padding that will be inserted before label LABEL .


<s> inline hashval_t libcall_hasher :: hash ( const value_type * p1 ) { return hash_rtx ( p1 , VOIDmode , NULL , NULL , FALSE ) ; } </s>

Hash function for builtin functions with up to 3 arguments and a return type .


<s> rtx legitimize_tls_address ( rtx x , rtx reg ) { rtx dest , tp , label , labelno , sum , insns , ret , eqv , addend ; unsigned int model = SYMBOL_REF_TLS_MODEL ( x ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_GD32 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; } return dest ; case TLS_MODEL_LOCAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; dest = gen_rtx_PLUS ( Pmode , dest , addend ) ; } return dest ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 4 , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? 8 : 4 ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else if ( TARGET_THUMB2 ) emit_insn ( gen_tls_load_dot_plus_four ( reg , NULL , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp ( NULL_RTX ) ; reg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 2 , x , GEN_INT ( TLS_LE32 ) ) , UNSPEC_TLS ) ; reg = force_reg ( SImode , gen_rtx_CONST ( SImode , reg ) ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; default : abort ( ) ; } } </s>

ADDR contains a thread-local SYMBOL_REF . Generate code to compute this ( thread-local ) address .


<s> static bool mem_ok_for_ldrd_strd ( rtx mem , rtx * base , rtx * offset ) { rtx addr ; gcc_assert ( base != NULL && offset != NULL ) ; if ( side_effects_p ( mem ) ) return false ; if ( GET_CODE ( mem ) == SUBREG ) return false ; gcc_assert ( MEM_P ( mem ) ) ; * offset = const0_rtx ; addr = XEXP ( mem , 0 ) ; if ( ! arm_legitimate_address_p ( DImode , addr , reload_in_progress || reload_completed ) ) return false ; if ( REG_P ( addr ) ) { * base = addr ; return true ; } else if ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == MINUS ) { * base = XEXP ( addr , 0 ) ; * offset = XEXP ( addr , 1 ) ; return ( REG_P ( * base ) && CONST_INT_P ( * offset ) ) ; } return false ; } </s>

Helper for gen_operands_ldrd_strd . Returns true iff the memory operand MEM 's address contains an immediate offset from the base register and has no side effects , in which case it sets BASE and OFFSET accordingly .


<s>
void
neon_const_bounds
(
rtx
operand
,
HOST_WIDE_INT
low
,
HOST_WIDE_INT
high
)
{
bounds_check
(
operand
,
low
,
high
,
"constant out of range"
)
;
}
</s>


<s> int neon_immediate_valid_for_logic ( rtx op , machine_mode mode , int inverse , rtx * modconst , int * elementwidth ) { rtx tmpconst ; int tmpwidth ; int retval = neon_valid_immediate ( op , mode , inverse , & tmpconst , & tmpwidth ) ; if ( retval < 0 || retval > 5 ) return 0 ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return 1 ; } </s>

Return TRUE if rtx X is legal for use in a VORR or VBIC instruction . If the immediate is valid , write a constant suitable for using as an operand to VORR/VBIC/VAND/VORN to * MODCONST and the corresponding element width to * ELEMENTWIDTH . See neon_valid_immediate for description of INVERSE .


<s> int neon_immediate_valid_for_move ( rtx op , machine_mode mode , rtx * modconst , int * elementwidth ) { rtx tmpconst ; int tmpwidth ; int retval = neon_valid_immediate ( op , mode , 0 , & tmpconst , & tmpwidth ) ; if ( retval == - 1 ) return 0 ; if ( modconst ) * modconst = tmpconst ; if ( elementwidth ) * elementwidth = tmpwidth ; return 1 ; } </s>

Return TRUE if rtx X is legal for use as either a Neon VMOV ( or , implicitly , VMVN ) immediate . Write back width per element to * ELEMENTWIDTH ( or zero for float elements ) , and a modified constant ( whatever should be output for a VMOV ) in * MODCONST .


<s> int neon_immediate_valid_for_shift ( rtx op , machine_mode mode , rtx * modconst , int * elementwidth , bool isleftshift ) { unsigned int innersize = GET_MODE_SIZE ( GET_MODE_INNER ( mode ) ) ; unsigned int n_elts = CONST_VECTOR_NUNITS ( op ) , i ; unsigned HOST_WIDE_INT last_elt = 0 ; unsigned HOST_WIDE_INT maxshift ; for ( i = 0 ; i < n_elts ; i ++ ) { rtx el = CONST_VECTOR_ELT ( op , i ) ; unsigned HOST_WIDE_INT elpart ; if ( CONST_INT_P ( el ) ) elpart = INTVAL ( el ) ; else if ( CONST_DOUBLE_P ( el ) ) return 0 ; else gcc_unreachable ( ) ; if ( i != 0 && elpart != last_elt ) return 0 ; last_elt = elpart ; } maxshift = innersize * 8 ; if ( isleftshift ) { if ( last_elt >= maxshift ) return 0 ; } else { if ( last_elt == 0 || last_elt > maxshift ) return 0 ; } if ( elementwidth ) * elementwidth = innersize * 8 ; if ( modconst ) * modconst = CONST_VECTOR_ELT ( op , 0 ) ; return 1 ; } </s>

Return TRUE if rtx OP is legal for use in a VSHR or VSHL instruction . If the immediate is valid , write a constant suitable for using as an operand to VSHR/VSHL to * MODCONST and the corresponding element width to * ELEMENTWIDTH . ISLEFTSHIFT is for determine left or right shift , because they have different limitations .


<s>
void
neon_lane_bounds
(
rtx
operand
,
HOST_WIDE_INT
low
,
HOST_WIDE_INT
high
)
{
bounds_check
(
operand
,
low
,
high
,
"lane out of range"
)
;
}
</s>


<s> rtx neon_make_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; rtx target ; rtx const_vec = NULL_RTX ; int n_elts = GET_MODE_NUNITS ( mode ) ; int n_const = 0 ; int i ; if ( GET_CODE ( vals ) == CONST_VECTOR ) const_vec = vals ; else if ( GET_CODE ( vals ) == PARALLEL ) { for ( i = 0 ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , 0 , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) n_const ++ ; } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , 0 ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL && neon_immediate_valid_for_move ( const_vec , mode , NULL , NULL ) ) return const_vec ; else if ( ( target = neon_vdup_constant ( vals ) ) != NULL_RTX ) return target ; else if ( const_vec != NULL_RTX ) return const_vec ; else return NULL_RTX ; } </s>

Generate code to load VALS , which is a PARALLEL containing only constants ( for vec_init ) or CONST_VECTOR , efficiently into a register . Returns an RTX to copy into the register , or NULL_RTX for a PARALLEL that can not be converted into a CONST_VECTOR .


<s> void neon_pairwise_reduce ( rtx op0 , rtx op1 , machine_mode mode , rtx ( * reduc ) ( rtx , rtx , rtx ) ) { machine_mode inner = GET_MODE_INNER ( mode ) ; unsigned int i , parts = GET_MODE_SIZE ( mode ) / GET_MODE_SIZE ( inner ) ; rtx tmpsum = op1 ; for ( i = parts / 2 ; i >= 1 ; i /= 2 ) { rtx dest = ( i == 1 ) ? op0 : gen_reg_rtx ( mode ) ; emit_insn ( reduc ( dest , tmpsum , tmpsum ) ) ; tmpsum = dest ; } } </s>

Output a sequence of pairwise operations to implement a reduction . NOTE : We do `` too much work '' here , because pairwise operations work on two registers-worth of operands in one go . Unfortunately we ca n't exploit those extra calculations to do the full operation in fewer steps , I do n't think . Although all vector elements of the result but the first are ignored , we actually calculate the same result in each of the elements . An alternative such as initially loading a vector with zero to use as each of the second operands would use up an additional register and take an extra instruction , for no particular gain .


<s> void neon_reinterpret ( rtx dest , rtx src ) { emit_move_insn ( dest , gen_lowpart ( GET_MODE ( dest ) , src ) ) ; } </s>

Emit code to reinterpret one Neon type as another , without altering bits .


<s> void neon_split_vcombine ( rtx operands [ 3 ] ) { unsigned int dest = REGNO ( operands [ 0 ] ) ; unsigned int src1 = REGNO ( operands [ 1 ] ) ; unsigned int src2 = REGNO ( operands [ 2 ] ) ; machine_mode halfmode = GET_MODE ( operands [ 1 ] ) ; unsigned int halfregs = HARD_REGNO_NREGS ( src1 , halfmode ) ; rtx destlo , desthi ; if ( src1 == dest && src2 == dest + halfregs ) { emit_note ( NOTE_INSN_DELETED ) ; return ; } destlo = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest , 0 ) ; desthi = gen_rtx_REG_offset ( operands [ 0 ] , halfmode , dest + halfregs , GET_MODE_SIZE ( halfmode ) ) ; if ( src2 == dest && src1 == dest + halfregs ) { rtx x = gen_rtx_SET ( VOIDmode , destlo , operands [ 1 ] ) ; rtx y = gen_rtx_SET ( VOIDmode , desthi , operands [ 2 ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , x , y ) ) ) ; return ; } if ( ! reg_overlap_mentioned_p ( operands [ 2 ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; } else { if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ 2 ] ) ; if ( src1 != dest ) emit_move_insn ( destlo , operands [ 1 ] ) ; } } </s>

Split operands into moves from op [ 1 ] + op [ 2 ] into op [ 0 ] .


<s> static rtx neon_vdup_constant ( rtx vals ) { machine_mode mode = GET_MODE ( vals ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; bool all_same = true ; rtx x ; int i ; if ( GET_CODE ( vals ) != CONST_VECTOR || GET_MODE_SIZE ( inner_mode ) > 4 ) return NULL_RTX ; for ( i = 0 ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , 0 , i ) ; if ( i > 0 && ! rtx_equal_p ( x , XVECEXP ( vals , 0 , 0 ) ) ) all_same = false ; } if ( ! all_same ) return NULL_RTX ; x = copy_to_mode_reg ( inner_mode , XVECEXP ( vals , 0 , 0 ) ) ; return gen_rtx_VEC_DUPLICATE ( mode , x ) ; } </s>

Return a non-NULL RTX iff VALS is a vector constant that can be loaded into a register using VDUP . If this is the case , and GENERATE is set , we also generate instructions to do this and return an RTX to assign to the register .


<s> int neon_vector_mem_operand ( rtx op , int type , bool strict ) { rtx ind ; if ( ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return ! strict ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , 0 ) ; if ( reload_completed && ( GET_CODE ( ind ) == LABEL_REF || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , 0 ) , 1 ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , 0 ) ; if ( ( type != 1 && GET_CODE ( ind ) == POST_INC ) || ( type == 0 && GET_CODE ( ind ) == PRE_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , 0 ) , 0 ) ; if ( type == 2 && GET_CODE ( ind ) == POST_MODIFY && GET_CODE ( XEXP ( ind , 1 ) ) == PLUS && REG_P ( XEXP ( XEXP ( ind , 1 ) , 1 ) ) ) return true ; if ( type == 0 && GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , 0 ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , 0 ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , 1 ) ) && INTVAL ( XEXP ( ind , 1 ) ) > - 1024 && ( INTVAL ( XEXP ( ind , 1 ) ) < ( VALID_NEON_QREG_MODE ( GET_MODE ( op ) ) ? 1016 : 1024 ) ) && ( INTVAL ( XEXP ( ind , 1 ) ) & 3 ) == 0 ) return TRUE ; return FALSE ; } </s>

Return TRUE if OP is a memory operand which we can load or store a vector to/from . TYPE is one of the following values : 0 - Vector load/stor ( vldr ) 1 - Core registers ( ldm ) 2 - Element/structure loads ( vld1 )


<s> static int optimal_immediate_sequence ( enum rtx_code code , unsigned HOST_WIDE_INT val , struct four_ints * return_sequence ) { int best_consecutive_zeros = 0 ; int i ; int best_start = 0 ; int insns1 , insns2 ; struct four_ints tmp_sequence ; if ( TARGET_ARM ) { for ( i = 0 ; i < 32 ; i += 2 ) { int consecutive_zeros = 0 ; if ( ! ( val & ( 3 << i ) ) ) { while ( ( i < 32 ) && ! ( val & ( 3 << i ) ) ) { consecutive_zeros += 2 ; i += 2 ; } if ( consecutive_zeros > best_consecutive_zeros ) { best_consecutive_zeros = consecutive_zeros ; best_start = i - consecutive_zeros ; } i -= 2 ; } } } insns1 = optimal_immediate_sequence_1 ( code , val , return_sequence , best_start ) ; if ( best_start != 0 && ( ( ( ( unsigned HOST_WIDE_INT ) 1 ) << best_start ) < val ) ) { insns2 = optimal_immediate_sequence_1 ( code , val , & tmp_sequence , 0 ) ; if ( insns2 <= insns1 ) { * return_sequence = tmp_sequence ; insns1 = insns2 ; } } return insns1 ; } </s>

Return a sequence of integers , in RETURN_SEQUENCE that fit into ARM/THUMB2 immediates , and add up to VAL . Thr function return value gives the number of insns required .


<s>
const
char
*
output_call_mem
(
rtx
*
operands
)
{
gcc_assert
(
!
arm_arch5
)
;
if
(
TARGET_INTERWORK
)
{
output_asm_insn
(
"ldr%?\t%|ip, %0"
,
operands
)
;
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
output_asm_insn
(
"bx%?\t%|ip"
,
operands
)
;
}
else
if
(
regno_use_in
(
LR_REGNUM
,
operands
[
0
]
)
)
{
output_asm_insn
(
"ldr%?\t%|ip, %0"
,
operands
)
;
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
if
(
arm_arch4t
)
output_asm_insn
(
"bx%?\t%|ip"
,
operands
)
;
else
output_asm_insn
(
"mov%?\t%|pc, %|ip"
,
operands
)
;
}
else
{
output_asm_insn
(
"mov%?\t%|lr, %|pc"
,
operands
)
;
output_asm_insn
(
"ldr%?\t%|pc, %0"
,
operands
)
;
}
return
""
;
}
</s>

Output a 'call ' insn that is a reference in memory . This is disabled for ARMv5 and we prefer a blx instead because otherwise there 's a significant performance overhead .


<s>
const
char
*
output_move_quad
(
rtx
*
operands
)
{
if
(
REG_P
(
operands
[
0
]
)
)
{
if
(
MEM_P
(
operands
[
1
]
)
)
{
switch
(
GET_CODE
(
XEXP
(
operands
[
1
]
,
0
)
)
)
{
case
REG
:
output_asm_insn
(
"ldm%(ia%)\t%m1, %M0"
,
operands
)
;
break
;
case
LABEL_REF
:
case
CONST
:
output_asm_insn
(
"adr%?\t%0, %1"
,
operands
)
;
output_asm_insn
(
"ldm%(ia%)\t%0, %M0"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
else
{
rtx
ops
[
2
]
;
int
dest
,
src
,
i
;
gcc_assert
(
REG_P
(
operands
[
1
]
)
)
;
dest
=
REGNO
(
operands
[
0
]
)
;
src
=
REGNO
(
operands
[
1
]
)
;
if
(
dest
<
src
)
for
(
i
=
0
;
i
<
4
;
i
++
)
{
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
dest
+
i
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
src
+
i
)
;
output_asm_insn
(
"mov%?\t%0, %1"
,
ops
)
;
}
else
for
(
i
=
3
;
i
>=
0
;
i
)
{
ops
[
0
]
=
gen_rtx_REG
(
SImode
,
dest
+
i
)
;
ops
[
1
]
=
gen_rtx_REG
(
SImode
,
src
+
i
)
;
output_asm_insn
(
"mov%?\t%0, %1"
,
ops
)
;
}
}
}
else
{
gcc_assert
(
MEM_P
(
operands
[
0
]
)
)
;
gcc_assert
(
REG_P
(
operands
[
1
]
)
)
;
gcc_assert
(
!
reg_overlap_mentioned_p
(
operands
[
1
]
,
operands
[
0
]
)
)
;
switch
(
GET_CODE
(
XEXP
(
operands
[
0
]
,
0
)
)
)
{
case
REG
:
output_asm_insn
(
"stm%(ia%)\t%m0, %M1"
,
operands
)
;
break
;
default
:
gcc_unreachable
(
)
;
}
}
return
""
;
}
</s>

Output assembler code to perform a quadword move insn with operands OPERANDS .


<s>
const
char
*
output_move_vfp
(
rtx
*
operands
)
{
rtx
reg
,
mem
,
addr
,
ops
[
2
]
;
int
load
=
REG_P
(
operands
[
0
]
)
;
int
dp
=
GET_MODE_SIZE
(
GET_MODE
(
operands
[
0
]
)
)
==
8
;
int
integer_p
=
GET_MODE_CLASS
(
GET_MODE
(
operands
[
0
]
)
)
==
MODE_INT
;
const
char
*
templ
;
char
buff
[
50
]
;
machine_mode
mode
;
reg
=
operands
[
!
load
]
;
mem
=
operands
[
load
]
;
mode
=
GET_MODE
(
reg
)
;
gcc_assert
(
REG_P
(
reg
)
)
;
gcc_assert
(
IS_VFP_REGNUM
(
REGNO
(
reg
)
)
)
;
gcc_assert
(
mode
==
SFmode
||
mode
==
DFmode
||
mode
==
SImode
||
mode
==
DImode
||
(
TARGET_NEON
&&
VALID_NEON_DREG_MODE
(
mode
)
)
)
;
gcc_assert
(
MEM_P
(
mem
)
)
;
addr
=
XEXP
(
mem
,
0
)
;
switch
(
GET_CODE
(
addr
)
)
{
case
PRE_DEC
:
templ
=
"v%smdb%%?.%s\t%%0!, {%%%s1}%s"
;
ops
[
0
]
=
XEXP
(
addr
,
0
)
;
ops
[
1
]
=
reg
;
break
;
case
POST_INC
:
templ
=
"v%smia%%?.%s\t%%0!, {%%%s1}%s"
;
ops
[
0
]
=
XEXP
(
addr
,
0
)
;
ops
[
1
]
=
reg
;
break
;
default
:
templ
=
"v%sr%%?.%s\t%%%s0, %%1%s"
;
ops
[
0
]
=
reg
;
ops
[
1
]
=
mem
;
break
;
}
sprintf
(
buff
,
templ
,
load
"ld"
:
"st"
,
dp
"64"
:
"32"
,
dp
"P"
:
""
,
integer_p
"\t%@ int"
:
""
)
;
output_asm_insn
(
buff
,
ops
)
;
return
""
;
}
</s>

Output a VFP load or store instruction .


";; %smode fixup for i%d; addr %lu, range (%ld,%ld): "

Record INSN , which will need fixing up to load a value from the minipool . ADDRESS is the offset of the insn since the start of the function ; LOC is a pointer to the part of the insn which requires fixing ; VALUE is the constant that must be loaded , which is of type MODE .


<s> static void require_pic_register ( void ) { if ( ! crtl -> uses_pic_offset_table ) { gcc_assert ( can_create_pseudo_p ( ) ) ; if ( arm_pic_register != INVALID_REGNUM && ! ( TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM ) ) { if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = gen_rtx_REG ( Pmode , arm_pic_register ) ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) crtl -> uses_pic_offset_table = 1 ; } else { rtx_insn * seq , * insn ; if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = gen_reg_rtx ( Pmode ) ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) { crtl -> uses_pic_offset_table = 1 ; start_sequence ( ) ; if ( TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM ) emit_move_insn ( cfun -> machine -> pic_reg , gen_rtx_REG ( Pmode , arm_pic_register ) ) ; else arm_load_pic_register ( 0UL ) ; seq = get_insns ( ) ; end_sequence ( ) ; for ( insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) INSN_LOCATION ( insn ) = prologue_location ; insert_insn_on_edge ( seq , single_succ_edge ( ENTRY_BLOCK_PTR_FOR_FN ( cfun ) ) ) ; } } } } </s>

Record that the current function needs a PIC register . Initialize cfun- > machine- > pic_reg if we have not already done so .


<s>
static
const
char
*
shift_op
(
rtx
op
,
HOST_WIDE_INT
*
amountp
)
{
const
char
*
mnem
;
enum
rtx_code
code
=
GET_CODE
(
op
)
;
switch
(
code
)
{
case
ROTATE
:
if
(
!
CONST_INT_P
(
XEXP
(
op
,
1
)
)
)
{
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
code
=
ROTATERT
;
*
amountp
=
32
INTVAL
(
XEXP
(
op
,
1
)
)
;
mnem
=
"ror"
;
break
;
case
ASHIFT
:
case
ASHIFTRT
:
case
LSHIFTRT
:
case
ROTATERT
:
mnem
=
arm_shift_nmem
(
code
)
;
if
(
CONST_INT_P
(
XEXP
(
op
,
1
)
)
)
{
*
amountp
=
INTVAL
(
XEXP
(
op
,
1
)
)
;
}
else
if
(
REG_P
(
XEXP
(
op
,
1
)
)
)
{
*
amountp
=
1
;
return
mnem
;
}
else
{
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
break
;
case
MULT
:
if
(
!
CONST_INT_P
(
XEXP
(
op
,
1
)
)
)
{
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
*
amountp
=
INTVAL
(
XEXP
(
op
,
1
)
)
&
0xFFFFFFFF
;
if
(
*
amountp
&
(
*
amountp
1
)
)
{
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
*
amountp
=
int_log2
(
*
amountp
)
;
return
ARM_LSL_NAME
;
default
:
output_operand_lossage
(
"invalid shift operand"
)
;
return
;
}
if
(
code
==
ROTATERT
)
*
amountp
&=
31
;
else
if
(
*
amountp
!=
(
*
amountp
&
31
)
)
{
if
(
code
==
ASHIFT
)
mnem
=
"lsr"
;
*
amountp
=
32
;
}
if
(
*
amountp
==
0
)
return
;
return
mnem
;
}
</s>

Ensure valid constant shifts and return the appropriate shift mnemonic for the operation code . The returned result should not be overwritten . OP is the rtx code of the shift . On exit , * AMOUNTP will be -1 if the shift is by a register , or a constant shift .


<s> static unsigned long thumb1_compute_save_reg_mask ( void ) { unsigned long mask ; unsigned reg ; mask = 0 ; for ( reg = 0 ; reg < 12 ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; if ( flag_pic && ! TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM && crtl -> uses_pic_offset_table ) mask |= 1 << PIC_OFFSET_TABLE_REGNUM ; if ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM ; if ( mask & 0xff || thumb_force_lr_save ( ) ) mask |= ( 1 << LR_REGNUM ) ; if ( ( mask & 0xff ) == 0 && ( ( mask & 0x0f00 ) || TARGET_BACKTRACE ) ) { reg = thumb_find_work_register ( 1 << LAST_LO_REGNUM ) ; if ( reg * UNITS_PER_WORD <= ( unsigned ) arm_size_return_regs ( ) ) reg = LAST_LO_REGNUM ; if ( callee_saved_reg_p ( reg ) ) mask |= 1 << reg ; } if ( ( CALLER_INTERWORKING_SLOT_SIZE + ROUND_UP_WORD ( get_frame_size ( ) ) + crtl -> outgoing_args_size ) >= 504 ) { for ( reg = LAST_ARG_REGNUM + 1 ; reg <= LAST_LO_REGNUM ; reg ++ ) if ( mask & ( 1 << reg ) ) break ; if ( reg > LAST_LO_REGNUM ) { mask |= 1 << LAST_LO_REGNUM ; } } return mask ; } </s>

Compute a bit mask of which registers need to be saved on the stack for the current function .


<s> static rtx_insn * thumb1_emit_multi_reg_push ( unsigned long mask , unsigned long real_regs ) { unsigned long regno ; rtx par [ 10 ] , tmp , reg ; rtx_insn * insn ; int i , j ; for ( i = 0 ; mask ; ++ i , mask &= mask - 1 ) { regno = ctz_hwi ( mask ) ; reg = gen_rtx_REG ( SImode , regno ) ; if ( i == 0 ) tmp = gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ; else tmp = gen_rtx_USE ( VOIDmode , reg ) ; par [ i ] = tmp ; } tmp = plus_constant ( Pmode , stack_pointer_rtx , - 4 * i ) ; tmp = gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , tmp ) ; tmp = gen_frame_mem ( BLKmode , tmp ) ; tmp = gen_rtx_SET ( VOIDmode , tmp , par [ 0 ] ) ; par [ 0 ] = tmp ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( i , par ) ) ; insn = emit_insn ( tmp ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , - 4 * i ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , tmp ) ; par [ 0 ] = tmp ; for ( j = 0 ; real_regs ; ++ j , real_regs &= real_regs - 1 ) { regno = ctz_hwi ( real_regs ) ; reg = gen_rtx_REG ( SImode , regno ) ; tmp = plus_constant ( Pmode , stack_pointer_rtx , j * 4 ) ; tmp = gen_frame_mem ( SImode , tmp ) ; tmp = gen_rtx_SET ( VOIDmode , tmp , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; par [ j + 1 ] = tmp ; } if ( j == 0 ) tmp = par [ 0 ] ; else { RTX_FRAME_RELATED_P ( par [ 0 ] ) = 1 ; tmp = gen_rtx_SEQUENCE ( VOIDmode , gen_rtvec_v ( j + 1 , par ) ) ; } add_reg_note ( insn , REG_FRAME_RELATED_EXPR , tmp ) ; return insn ; } </s>

Like emit_multi_reg_push , but allowing for a different set of registers to be described as saved . MASK is the set of registers to be saved ; REAL_REGS is the set of registers to be described as saved . If REAL_REGS is 0 , only describe the stack adjustment .


<s> static int thumb1_extra_regs_pushed ( arm_stack_offsets * offsets , bool for_prologue ) { HOST_WIDE_INT amount ; unsigned long live_regs_mask = offsets -> saved_regs_mask ; unsigned long l_mask = live_regs_mask & ( for_prologue ? 0x40ff : 0xff ) ; unsigned long high_regs_pushed = bit_count ( live_regs_mask & 0x0f00 ) ; int n_free , reg_base , size ; if ( ! for_prologue && frame_pointer_needed ) amount = offsets -> locals_base - offsets -> saved_regs ; else amount = offsets -> outgoing_args - offsets -> saved_regs ; if ( ! optimize_size && amount != 512 ) return 0 ; if ( high_regs_pushed != 0 ) return 0 ; if ( l_mask == 0 && ( for_prologue || TARGET_BACKTRACE || ( live_regs_mask & 1 << LR_REGNUM ) == 0 || TARGET_INTERWORK || crtl -> args . pretend_args_size != 0 ) ) return 0 ; if ( for_prologue && ( ( flag_pic && arm_pic_register != INVALID_REGNUM ) || ( ! frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0 ) ) ) return 0 ; reg_base = 0 ; n_free = 0 ; if ( ! for_prologue ) { size = arm_size_return_regs ( ) ; reg_base = ARM_NUM_INTS ( size ) ; live_regs_mask >>= reg_base ; } while ( reg_base + n_free < 8 && ! ( live_regs_mask & 1 ) && ( for_prologue || call_used_regs [ reg_base + n_free ] ) ) { live_regs_mask >>= 1 ; n_free ++ ; } if ( n_free == 0 ) return 0 ; gcc_assert ( amount / 4 * 4 == amount ) ; if ( amount >= 512 && ( amount - n_free * 4 ) < 512 ) return ( amount - 508 ) / 4 ; if ( amount <= n_free * 4 ) return amount / 4 ; return 0 ; } </s>

Given the stack offsets and register mask in OFFSETS , decide how many additional registers to push instead of subtracting a constant from SP . For epilogues the principle is the same except we use pop . FOR_PROLOGUE indicates which we 're generating .


<s>
void
thumb1_final_prescan_insn
(
rtx_insn
*
insn
)
{
if
(
flag_print_asm_name
)
asm_fprintf
(
asm_out_file
,
"%@ 0x%04x\n"
,
INSN_ADDRESSES
(
INSN_UID
(
insn
)
)
)
;
if
(
INSN_CODE
(
insn
)
!=
CODE_FOR_cbranchsi4_insn
)
{
enum
attr_conds
conds
;
if
(
cfun
->
machine
->
thumb1_cc_insn
)
{
if
(
modified_in_p
(
cfun
->
machine
->
thumb1_cc_op0
,
insn
)
||
modified_in_p
(
cfun
->
machine
->
thumb1_cc_op1
,
insn
)
)
CC_STATUS_INIT
;
}
conds
=
get_attr_conds
(
insn
)
;
if
(
conds
==
CONDS_SET
)
{
rtx
set
=
single_set
(
insn
)
;
cfun
->
machine
->
thumb1_cc_insn
=
insn
;
cfun
->
machine
->
thumb1_cc_op0
=
SET_DEST
(
set
)
;
cfun
->
machine
->
thumb1_cc_op1
=
const0_rtx
;
cfun
->
machine
->
thumb1_cc_mode
=
CC_NOOVmode
;
if
(
INSN_CODE
(
insn
)
==
CODE_FOR_thumb1_subsi3_insn
)
{
rtx
src1
=
XEXP
(
SET_SRC
(
set
)
,
1
)
;
if
(
src1
==
const0_rtx
)
cfun
->
machine
->
thumb1_cc_mode
=
CCmode
;
}
else
if
(
REG_P
(
SET_DEST
(
set
)
)
&&
REG_P
(
SET_SRC
(
set
)
)
)
{
cfun
->
machine
->
thumb1_cc_op0
=
SET_SRC
(
set
)
;
}
}
else
if
(
conds
!=
CONDS_NOCOND
)
cfun
->
machine
->
thumb1_cc_insn
=
NULL_RTX
;
}
if
(
cfun
->
machine
->
lr_save_eliminated
&&
get_attr_far_jump
(
insn
)
==
FAR_JUMP_YES
)
internal_error
(
"Unexpected thumb1 far jump"
)
;
}
</s>

Scan INSN just before assembler is output for it . For Thumb-1 , we track the status of the condition codes ; this information is used in the cbranchsi4_insn pattern .

arm
"%@ 0x%04x\n"
1
"Unexpected thumb1 far jump"


<s> const char * thumb1_output_casesi ( rtx * operands ) { rtx diff_vec = PATTERN ( NEXT_INSN ( as_a < rtx_insn * > ( operands [ 0 ] ) ) ) ; gcc_assert ( GET_CODE ( diff_vec ) == ADDR_DIFF_VEC ) ; switch ( GET_MODE ( diff_vec ) ) { case QImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "bl\t%___gnu_thumb1_case_uqi" : "bl\t%___gnu_thumb1_case_sqi" ) ; case HImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? "bl\t%___gnu_thumb1_case_uhi" : "bl\t%___gnu_thumb1_case_shi" ) ; case SImode : return "bl\t%___gnu_thumb1_case_si" ; default : gcc_unreachable ( ) ; } } </s>

Output a Thumb-1 casesi dispatch sequence .


<s> static void thumb1_reorg ( void ) { basic_block bb ; FOR_EACH_BB_FN ( bb , cfun ) { rtx dest , src ; rtx pat , op0 , set = NULL ; rtx_insn * prev , * insn = BB_END ( bb ) ; bool insn_clobbered = false ; while ( insn != BB_HEAD ( bb ) && ! NONDEBUG_INSN_P ( insn ) ) insn = PREV_INSN ( insn ) ; if ( insn == BB_HEAD ( bb ) || INSN_CODE ( insn ) != CODE_FOR_cbranchsi4_insn ) continue ; pat = PATTERN ( insn ) ; op0 = XEXP ( XEXP ( SET_SRC ( pat ) , 0 ) , 0 ) ; gcc_assert ( insn != BB_HEAD ( bb ) ) ; for ( prev = PREV_INSN ( insn ) ; ( ! insn_clobbered && prev != BB_HEAD ( bb ) && ( NOTE_P ( prev ) || DEBUG_INSN_P ( prev ) || ( ( set = single_set ( prev ) ) != NULL && get_attr_conds ( prev ) == CONDS_NOCOND ) ) ) ; prev = PREV_INSN ( prev ) ) { if ( reg_set_p ( op0 , prev ) ) insn_clobbered = true ; } if ( insn_clobbered ) continue ; if ( ! set ) continue ; dest = SET_DEST ( set ) ; src = SET_SRC ( set ) ; if ( ! low_register_operand ( dest , SImode ) || ! low_register_operand ( src , SImode ) ) continue ; if ( REGNO ( op0 ) == REGNO ( src ) || REGNO ( op0 ) == REGNO ( dest ) ) { dest = copy_rtx ( dest ) ; src = copy_rtx ( src ) ; src = gen_rtx_MINUS ( SImode , src , const0_rtx ) ; PATTERN ( prev ) = gen_rtx_SET ( VOIDmode , dest , src ) ; INSN_CODE ( prev ) = - 1 ; XEXP ( XEXP ( SET_SRC ( pat ) , 0 ) , 0 ) = copy_rtx ( dest ) ; INSN_CODE ( insn ) = - 1 ; } } } </s>

Rewrite move insn into subtract of 0 if the condition codes will be useful in next conditional jump insn .


<s> void thumb2_expand_return ( bool simple_return ) { int i , num_regs ; unsigned long saved_regs_mask ; arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; saved_regs_mask = offsets -> saved_regs_mask ; for ( i = 0 , num_regs = 0 ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( 1 << i ) ) num_regs ++ ; if ( ! simple_return && saved_regs_mask ) { if ( num_regs == 1 ) { rtx par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( 2 ) ) ; rtx reg = gen_rtx_REG ( SImode , PC_REGNUM ) ; rtx addr = gen_rtx_MEM ( SImode , gen_rtx_POST_INC ( SImode , stack_pointer_rtx ) ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; XVECEXP ( par , 0 , 0 ) = ret_rtx ; XVECEXP ( par , 0 , 1 ) = gen_rtx_SET ( SImode , reg , addr ) ; RTX_FRAME_RELATED_P ( XVECEXP ( par , 0 , 1 ) ) = 1 ; emit_jump_insn ( par ) ; } else { saved_regs_mask &= ~ ( 1 << LR_REGNUM ) ; saved_regs_mask |= ( 1 << PC_REGNUM ) ; arm_emit_multi_reg_pop ( saved_regs_mask ) ; } } else { emit_jump_insn ( simple_return_rtx ) ; } } </s>


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return 1 ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || ( mode == DFmode && ( TARGET_SOFT_FLOAT || TARGET_VFP ) ) ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= 4 ) ) ) return arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , 0 ) , strict_p ) && GET_CODE ( XEXP ( x , 1 ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , 1 ) , 0 ) , XEXP ( x , 0 ) ) ) { rtx addend = XEXP ( XEXP ( x , 1 ) , 1 ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return 0 ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= 4 ) return ( offset > - 256 && offset < 256 ) ; return ( use_ldrd && offset > - 1024 && offset < 1024 && ( offset & 3 ) == 0 ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , 0 ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , 0 ) , 0 ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , 0 ) , 1 ) ) ) ) ) return 1 ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return 0 ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( arm_disable_literal_pool && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) ) return 0 ; else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return 1 ; return 0 ; } </s>

Return nonzero if X is a valid Thumb-2 address operand .


<s> static int thumb2_legitimate_index_p ( machine_mode mode , rtx index , int strict_p ) { enum rtx_code code = GET_CODE ( index ) ; if ( TARGET_HARD_FLOAT && TARGET_VFP && ( mode == SFmode || mode == DFmode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 256 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE ( mode ) ) { if ( ! TARGET_LDRD || mode != DImode ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; } if ( TARGET_NEON && VALID_NEON_QREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1016 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( TARGET_NEON && VALID_NEON_DREG_MODE ( mode ) ) return ( code == CONST_INT && INTVAL ( index ) < 1024 && INTVAL ( index ) > - 1024 && ( INTVAL ( index ) & 3 ) == 0 ) ; if ( arm_address_register_rtx_p ( index , strict_p ) && ( GET_MODE_SIZE ( mode ) <= 4 ) ) return 1 ; if ( mode == DImode || mode == DFmode ) { if ( code == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( index ) ; return val > - 256 && val < 256 && ( val & 3 ) == 0 ; } else return 0 ; } if ( code == MULT ) { rtx xiop0 = XEXP ( index , 0 ) ; rtx xiop1 = XEXP ( index , 1 ) ; return ( ( arm_address_register_rtx_p ( xiop0 , strict_p ) && thumb2_index_mul_operand ( xiop1 ) ) || ( arm_address_register_rtx_p ( xiop1 , strict_p ) && thumb2_index_mul_operand ( xiop0 ) ) ) ; } else if ( code == ASHIFT ) { rtx op = XEXP ( index , 1 ) ; return ( arm_address_register_rtx_p ( XEXP ( index , 0 ) , strict_p ) && CONST_INT_P ( op ) && INTVAL ( op ) > 0 && INTVAL ( op ) <= 3 ) ; } return ( code == CONST_INT && INTVAL ( index ) < 4096 && INTVAL ( index ) > - 256 ) ; } </s>

Return nonzero if INDEX is a valid Thumb-2 address index operand .


<s>
const
char
*
thumb2_output_casesi
(
rtx
*
operands
)
{
rtx
diff_vec
=
PATTERN
(
NEXT_INSN
(
as_a
<
rtx_insn
*
>
(
operands
[
2
]
)
)
)
;
gcc_assert
(
GET_CODE
(
diff_vec
)
==
ADDR_DIFF_VEC
)
;
output_asm_insn
(
"cmp\t%0, %1"
,
operands
)
;
output_asm_insn
(
"bhi\t%l3"
,
operands
)
;
switch
(
GET_MODE
(
diff_vec
)
)
{
case
QImode
:
return
"tbb\t[%|pc, %0]"
;
case
HImode
:
return
"tbh\t[%|pc, %0, lsl #1]"
;
case
SImode
:
if
(
flag_pic
)
{
output_asm_insn
(
"adr\t%4, %l2"
,
operands
)
;
output_asm_insn
(
"ldr\t%5, [%4, %0, lsl #2]"
,
operands
)
;
output_asm_insn
(
"add\t%4, %4, %5"
,
operands
)
;
return
"bx\t%4"
;
}
else
{
output_asm_insn
(
"adr\t%4, %l2"
,
operands
)
;
return
"ldr\t%|pc, [%4, %0, lsl #2]"
;
}
default
:
gcc_unreachable
(
)
;
}
}
</s>


<s> void thumb_expand_movmemqi ( rtx * operands ) { rtx out = copy_to_mode_reg ( SImode , XEXP ( operands [ 0 ] , 0 ) ) ; rtx in = copy_to_mode_reg ( SImode , XEXP ( operands [ 1 ] , 0 ) ) ; HOST_WIDE_INT len = INTVAL ( operands [ 2 ] ) ; HOST_WIDE_INT offset = 0 ; while ( len >= 12 ) { emit_insn ( gen_movmem12b ( out , in , out , in ) ) ; len -= 12 ; } if ( len >= 8 ) { emit_insn ( gen_movmem8b ( out , in , out , in ) ) ; len -= 8 ; } if ( len >= 4 ) { rtx reg = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( reg , gen_rtx_MEM ( SImode , in ) ) ) ; emit_insn ( gen_movsi ( gen_rtx_MEM ( SImode , out ) , reg ) ) ; len -= 4 ; offset += 4 ; } if ( len >= 2 ) { rtx reg = gen_reg_rtx ( HImode ) ; emit_insn ( gen_movhi ( reg , gen_rtx_MEM ( HImode , plus_constant ( Pmode , in , offset ) ) ) ) ; emit_insn ( gen_movhi ( gen_rtx_MEM ( HImode , plus_constant ( Pmode , out , offset ) ) , reg ) ) ; len -= 2 ; offset += 2 ; } if ( len ) { rtx reg = gen_reg_rtx ( QImode ) ; emit_insn ( gen_movqi ( reg , gen_rtx_MEM ( QImode , plus_constant ( Pmode , in , offset ) ) ) ) ; emit_insn ( gen_movqi ( gen_rtx_MEM ( QImode , plus_constant ( Pmode , out , offset ) ) , reg ) ) ; } } </s>


<s> static int thumb_find_work_register ( unsigned long pushed_regs_mask ) { int reg ; for ( reg = LAST_ARG_REGNUM ; reg >= 0 ; reg -- ) if ( ! df_regs_ever_live_p ( reg ) ) return reg ; if ( cfun -> machine -> uses_anonymous_args && crtl -> args . pretend_args_size > 0 ) return LAST_ARG_REGNUM ; if ( ! cfun -> machine -> uses_anonymous_args && crtl -> args . size >= 0 && crtl -> args . size <= ( LAST_ARG_REGNUM * UNITS_PER_WORD ) && ( TARGET_AAPCS_BASED ? crtl -> args . info . aapcs_ncrn < 4 : crtl -> args . info . nregs < 4 ) ) return LAST_ARG_REGNUM ; for ( reg = LAST_LO_REGNUM ; reg > LAST_ARG_REGNUM ; reg -- ) if ( pushed_regs_mask & ( 1 << reg ) ) return reg ; if ( TARGET_THUMB2 ) { for ( reg = FIRST_HI_REGNUM ; reg < 15 ; reg ++ ) if ( pushed_regs_mask & ( 1 << reg ) ) return reg ; } gcc_unreachable ( ) ; } </s>

Find a spare low register to use during the prolog of a function .


<s> static bool thumb_force_lr_save ( void ) { return ! cfun -> machine -> lr_save_eliminated && ( ! leaf_function_p ( ) || thumb_far_jump_used_p ( ) || df_regs_ever_live_p ( LR_REGNUM ) ) ; } </s>

Return true if the current function needs to save/restore LR .


<s> rtx thumb_legitimize_address ( rtx x , rtx orig_x , machine_mode mode ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , 1 ) ) && ( INTVAL ( XEXP ( x , 1 ) ) >= 32 * GET_MODE_SIZE ( mode ) || INTVAL ( XEXP ( x , 1 ) ) < 0 ) ) { rtx xop0 = XEXP ( x , 0 ) ; rtx xop1 = XEXP ( x , 1 ) ; HOST_WIDE_INT offset = INTVAL ( xop1 ) ; if ( optimize_size && offset >= 0 && offset < 256 + 31 * GET_MODE_SIZE ( mode ) ) { HOST_WIDE_INT delta ; if ( offset >= 256 ) delta = offset - ( 256 - GET_MODE_SIZE ( mode ) ) ; else if ( offset < 32 * GET_MODE_SIZE ( mode ) + 8 ) delta = 31 * GET_MODE_SIZE ( mode ) ; else delta = offset & ( ~ 31 * GET_MODE_SIZE ( mode ) ) ; xop0 = force_operand ( plus_constant ( Pmode , xop0 , offset - delta ) , NULL_RTX ) ; x = plus_constant ( Pmode , xop0 , delta ) ; } else if ( offset < 0 && offset > - 256 ) x = force_operand ( x , NULL_RTX ) ; else { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } else if ( GET_CODE ( x ) == PLUS && s_register_operand ( XEXP ( x , 1 ) , SImode ) && ! s_register_operand ( XEXP ( x , 0 ) , SImode ) ) { rtx xop0 = force_operand ( XEXP ( x , 0 ) , NULL_RTX ) ; x = gen_rtx_PLUS ( SImode , xop0 , XEXP ( x , 1 ) ) ; } if ( flag_pic ) { rtx new_x = legitimize_pic_address ( orig_x , mode , NULL_RTX ) ; if ( new_x != orig_x ) x = new_x ; } return x ; } </s>

Try machine-dependent ways of modifying an illegitimate Thumb address to be legitimate . If we find one , return the new , valid address .


<s>
static
void
thumb_pop
(
FILE
*
f
,
unsigned
long
mask
)
{
int
regno
;
int
lo_mask
=
mask
&
0xFF
;
int
pushed_words
=
0
;
gcc_assert
(
mask
)
;
if
(
lo_mask
==
0
&&
(
mask
&
(
1
<<
PC_REGNUM
)
)
)
{
thumb_exit
(
f
,
1
)
;
return
;
}
fprintf
(
f
,
"\tpop\t{"
)
;
for
(
regno
=
0
;
regno
<=
LAST_LO_REGNUM
;
regno
++
,
lo_mask
>>=
1
)
{
if
(
lo_mask
&
1
)
{
asm_fprintf
(
f
,
"%r"
,
regno
)
;
if
(
(
lo_mask
&
~
1
)
!=
0
)
fprintf
(
f
,
", "
)
;
pushed_words
++
;
}
}
if
(
mask
&
(
1
<<
PC_REGNUM
)
)
{
if
(
TARGET_INTERWORK
||
TARGET_BACKTRACE
||
crtl
->
calls_eh_return
)
{
fprintf
(
f
,
"}\n"
)
;
thumb_exit
(
f
,
1
)
;
return
;
}
else
{
if
(
mask
&
0xFF
)
fprintf
(
f
,
", "
)
;
asm_fprintf
(
f
,
"%r"
,
PC_REGNUM
)
;
}
}
fprintf
(
f
,
"}\n"
)
;
}
</s>

Emit code to push or pop registers to or from the stack . F is the assembly file . MASK is the registers to pop .


<s> static void thumb_set_frame_pointer ( arm_stack_offsets * offsets ) { HOST_WIDE_INT amount ; rtx insn , dwarf ; amount = offsets -> outgoing_args - offsets -> locals_base ; if ( amount < 1024 ) insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ) ; else { emit_insn ( gen_movsi ( hard_frame_pointer_rtx , GEN_INT ( amount ) ) ) ; if ( TARGET_THUMB2 ) { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; } else { insn = emit_insn ( gen_addsi3 ( hard_frame_pointer_rtx , hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; } dwarf = gen_rtx_SET ( VOIDmode , hard_frame_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , amount ) ) ; RTX_FRAME_RELATED_P ( dwarf ) = 1 ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; } RTX_FRAME_RELATED_P ( insn ) = 1 ; } </s>

Set the Thumb frame pointer from the stack pointer .


<s> int use_return_insn ( int iscond , rtx sibling ) { int regno ; unsigned int func_type ; unsigned long saved_int_regs ; unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return 0 ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return 0 ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return 0 ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return 0 ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == 0 || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == 4 ) ) ) return 0 ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == 4 && ! arm_arch5 && TARGET_ARM ) { if ( ! call_used_regs [ 3 ] ) return 0 ; if ( arm_size_return_regs ( ) >= ( 4 * UNITS_PER_WORD ) ) return 0 ; if ( sibling ) { gcc_assert ( CALL_P ( sibling ) ) ; if ( find_regno_fusage ( sibling , USE , 3 ) ) return 0 ; } if ( saved_int_regs & 0x7 ) return 0 ; } if ( TARGET_INTERWORK && saved_int_regs != 0 && ! IS_INTERRUPT ( func_type ) ) return 0 ; if ( iscond && arm_tune_strongarm ) { if ( saved_int_regs != 0 && saved_int_regs != ( 1 << LR_REGNUM ) ) return 0 ; if ( flag_pic && arm_pic_register != INVALID_REGNUM && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) return 0 ; } if ( saved_int_regs && ! ( saved_int_regs & ( 1 << LR_REGNUM ) ) ) return 0 ; if ( TARGET_HARD_FLOAT && TARGET_VFP ) for ( regno = FIRST_VFP_REGNUM ; regno <= LAST_VFP_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; if ( TARGET_REALLY_IWMMXT ) for ( regno = FIRST_IWMMXT_REGNUM ; regno <= LAST_IWMMXT_REGNUM ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_regs [ regno ] ) return 0 ; return 1 ; } </s>

Return true if this function 's epilogue can be output as RTL .


<s> bool use_simple_return_p ( void ) { arm_stack_offsets * offsets ; offsets = arm_get_frame_offsets ( ) ; return offsets -> outgoing_args != 0 ; } </s>

Return TRUE if we should try to use a simple_return insn , i.e . perform shrink-wrapping if possible . This is the case if we need to emit a prologue , which we can test by looking at the offsets .


<s>
static
bool
use_vfp_abi
(
enum
arm_pcs
pcs_variant
,
bool
is_double
)
{
if
(
pcs_variant
==
ARM_PCS_AAPCS_VFP
)
{
static
bool
seen_thumb1_vfp
=
false
;
if
(
TARGET_THUMB1
&&
!
seen_thumb1_vfp
)
{
sorry
(
"Thumb-1 hard-float VFP ABI"
)
;
seen_thumb1_vfp
=
true
;
}
return
true
;
}
if
(
pcs_variant
!=
ARM_PCS_AAPCS_LOCAL
)
return
false
;
return
(
TARGET_32BIT
&&
TARGET_VFP
&&
TARGET_HARD_FLOAT
&&
(
TARGET_VFP_DOUBLE
||
!
is_double
)
)
;
}
</s>

Return true if PCS_VARIANT should use VFP registers .


<s> int vfp3_const_double_for_bits ( rtx operand ) { REAL_VALUE_TYPE r0 ; if ( ! CONST_DOUBLE_P ( operand ) ) return 0 ; REAL_VALUE_FROM_CONST_DOUBLE ( r0 , operand ) ; if ( exact_real_truncate ( DFmode , & r0 ) ) { HOST_WIDE_INT value = real_to_integer ( & r0 ) ; value = value & 0xffffffff ; if ( ( value != 0 ) && ( ( value & ( value - 1 ) ) == 0 ) ) return int_log2 ( value ) ; } return 0 ; } </s>

If X is a CONST_DOUBLE with a value that is a power of 2 whose log2 is in [ 1 , 32 ] , return that log2 . Otherwise return -1 . This is used in the patterns for vcvt.s32.f32 floating-point to fixed-point conversions .


<s> static int vfp3_const_double_index ( rtx x ) { REAL_VALUE_TYPE r , m ; int sign , exponent ; unsigned HOST_WIDE_INT mantissa , mant_hi ; unsigned HOST_WIDE_INT mask ; int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1 ; bool fail ; if ( ! TARGET_VFP3 || ! CONST_DOUBLE_P ( x ) ) return - 1 ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - 1 ; sign = REAL_VALUE_NEGATIVE ( r ) ? 1 : 0 ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * 2 ) ; mantissa = w . elt ( 0 ) ; mant_hi = w . elt ( 1 ) ; if ( mantissa != 0 ) return - 1 ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ; mask = ( ( unsigned HOST_WIDE_INT ) 1 << ( point_pos - 5 ) ) - 1 ; if ( ( mantissa & mask ) != 0 ) return - 1 ; mantissa >>= point_pos - 5 ; if ( mantissa == 0 ) return - 1 ; gcc_assert ( mantissa >= 16 && mantissa <= 31 ) ; exponent = 5 - exponent ; if ( exponent < 0 || exponent > 7 ) return - 1 ; return ( sign << 7 ) | ( ( exponent ^ 3 ) << 4 ) | ( mantissa - 16 ) ; } </s>

Return an integer index for a VFPv3 immediate operand X suitable for the fconst [ sd ] instruction , or -1 if X is n't suitable .


<s> static int vfp_emit_fstmd ( int base_reg , int count ) { rtx par ; rtx dwarf ; rtx tmp , reg ; int i ; if ( count == 2 && ! arm_arch6 ) { if ( base_reg == LAST_VFP_REGNUM - 3 ) base_reg -= 2 ; count ++ ; } if ( count > 16 ) { int saved ; saved = vfp_emit_fstmd ( base_reg + 32 , count - 16 ) ; saved += vfp_emit_fstmd ( base_reg , 16 ) ; return saved ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count ) ) ; dwarf = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( count + 1 ) ) ; reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , 0 ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * 8 ) ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( 1 , reg ) , UNSPEC_PUSH_MULT ) ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - ( count * 8 ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 0 ) = tmp ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , 1 ) = tmp ; for ( i = 1 ; i < count ; i ++ ) { reg = gen_rtx_REG ( DFmode , base_reg ) ; base_reg += 2 ; XVECEXP ( par , 0 , i ) = gen_rtx_USE ( VOIDmode , reg ) ; tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( DFmode , plus_constant ( Pmode , stack_pointer_rtx , i * 8 ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( dwarf , 0 , i + 1 ) = tmp ; } par = emit_insn ( par ) ; add_reg_note ( par , REG_FRAME_RELATED_EXPR , dwarf ) ; RTX_FRAME_RELATED_P ( par ) = 1 ; return count * 8 ; } </s>

Emit RTL to save block of VFP register pairs to the stack . Returns the number of bytes pushed .


<s> static bool xscale_sched_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep , int * cost ) { if ( REG_NOTE_KIND ( link ) == 0 && recog_memoized ( insn ) >= 0 && recog_memoized ( dep ) >= 0 ) { int shift_opnum = get_attr_shift ( insn ) ; enum attr_type attr_type = get_attr_type ( dep ) ; if ( shift_opnum != 0 && ( attr_type == TYPE_ALU_SHIFT_IMM || attr_type == TYPE_ALUS_SHIFT_IMM || attr_type == TYPE_LOGIC_SHIFT_IMM || attr_type == TYPE_LOGICS_SHIFT_IMM || attr_type == TYPE_ALU_SHIFT_REG || attr_type == TYPE_ALUS_SHIFT_REG || attr_type == TYPE_LOGIC_SHIFT_REG || attr_type == TYPE_LOGICS_SHIFT_REG || attr_type == TYPE_MOV_SHIFT || attr_type == TYPE_MVN_SHIFT || attr_type == TYPE_MOV_SHIFT_REG || attr_type == TYPE_MVN_SHIFT_REG ) ) { rtx shifted_operand ; int opno ; extract_insn ( insn ) ; shifted_operand = recog_data . operand [ shift_opnum ] ; extract_insn ( dep ) ; preprocess_constraints ( dep ) ; for ( opno = 0 ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] == OP_IN ) continue ; if ( reg_overlap_mentioned_p ( recog_data . operand [ opno ] , shifted_operand ) ) { * cost = 2 ; return false ; } } } } return true ; } </s>


<s> static rtx aapcs_vfp_allocate_return_reg ( enum arm_pcs pcs_variant ATTRIBUTE_UNUSED , machine_mode mode , const_tree type ATTRIBUTE_UNUSED ) { if ( ! use_vfp_abi ( pcs_variant , false ) ) return NULL ; if ( mode == BLKmode || ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) >= GET_MODE_SIZE ( TImode ) && ! TARGET_NEON ) ) { int count ; machine_mode ag_mode ; int i ; rtx par ; int shift ; aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode , & count ) ; if ( ! TARGET_NEON ) { if ( ag_mode == V2SImode ) ag_mode = DImode ; else if ( ag_mode == V4SImode ) { ag_mode = DImode ; count *= 2 ; } } shift = GET_MODE_SIZE ( ag_mode ) / GET_MODE_SIZE ( SFmode ) ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( count ) ) ; for ( i = 0 ; i < count ; i ++ ) { rtx tmp = gen_rtx_REG ( ag_mode , FIRST_VFP_REGNUM + i * shift ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * GET_MODE_SIZE ( ag_mode ) ) ) ; XVECEXP ( par , 0 , i ) = tmp ; } return par ; } return gen_rtx_REG ( mode , FIRST_VFP_REGNUM ) ; } </s>

Implement the allocate_return_reg field in aapcs_cp_arg_layout . See the comment there for the behaviour of this function .


<s> static bool aarch_macro_fusion_pair_p ( rtx_insn * prev , rtx_insn * curr ) { rtx set_dest ; rtx prev_set = single_set ( prev ) ; rtx curr_set = single_set ( curr ) ; if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_AES_AESMC && aarch_crypto_can_dual_issue ( prev , curr ) ) return true ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT ) { set_dest = SET_DEST ( curr_set ) ; if ( GET_MODE ( set_dest ) != SImode ) return false ; if ( GET_CODE ( set_dest ) == ZERO_EXTRACT ) { if ( CONST_INT_P ( SET_SRC ( curr_set ) ) && CONST_INT_P ( SET_SRC ( prev_set ) ) && REG_P ( XEXP ( set_dest , 0 ) ) && REG_P ( SET_DEST ( prev_set ) ) && REGNO ( XEXP ( set_dest , 0 ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } else if ( GET_CODE ( SET_SRC ( curr_set ) ) == LO_SUM && REG_P ( SET_DEST ( curr_set ) ) && REG_P ( SET_DEST ( prev_set ) ) && GET_CODE ( SET_SRC ( prev_set ) ) == HIGH && REGNO ( SET_DEST ( curr_set ) ) == REGNO ( SET_DEST ( prev_set ) ) ) return true ; } return false ; } </s>

Implement TARGET_SCHED_MACRO_FUSION_PAIR_P . Return true if PREV and CURR should be kept together during scheduling .


<s>
static
void
arm_asm_trampoline_template
(
FILE
*
f
)
{
fprintf
(
f
,
"\t.syntax unified\n"
)
;
if
(
TARGET_ARM
)
{
fprintf
(
f
,
"\t.arm\n"
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #0]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr\t%r, [%r, #0]\n"
,
PC_REGNUM
,
PC_REGNUM
)
;
}
else
if
(
TARGET_THUMB2
)
{
fprintf
(
f
,
"\t.thumb\n"
)
;
asm_fprintf
(
f
,
"\tldr.w\t%r, [%r, #4]\n"
,
STATIC_CHAIN_REGNUM
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr.w\t%r, [%r, #4]\n"
,
PC_REGNUM
,
PC_REGNUM
)
;
}
else
{
ASM_OUTPUT_ALIGN
(
f
,
2
)
;
fprintf
(
f
,
"\t.code\t16\n"
)
;
fprintf
(
f
,
".Ltrampoline_start:\n"
)
;
asm_fprintf
(
f
,
"\tpush\t{r0, r1}\n"
)
;
asm_fprintf
(
f
,
"\tldr\tr0, [%r, #8]\n"
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tmov\t%r, r0\n"
,
STATIC_CHAIN_REGNUM
)
;
asm_fprintf
(
f
,
"\tldr\tr0, [%r, #8]\n"
,
PC_REGNUM
)
;
asm_fprintf
(
f
,
"\tstr\tr0, [%r, #4]\n"
,
SP_REGNUM
)
;
asm_fprintf
(
f
,
"\tpop\t{r0, %r}\n"
,
PC_REGNUM
)
;
}
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
assemble_aligned_integer
(
UNITS_PER_WORD
,
const0_rtx
)
;
}
</s>

Output assembler code for a block containing the constant parts of a trampoline , leaving space for the variable parts . On the ARM , ( if r8 is the static chain regnum , and remembering that referencing pc adds an offset of 8 ) the trampoline looks like : ldr r8 , [ pc , # 0 ] ldr pc , [ pc ] .word static chain value .word function 's address XXX FIXME : When the trampoline returns , r8 will be clobbered .


<s> static bool arm_assemble_integer ( rtx x , unsigned int size , int aligned_p ) { machine_mode mode ; if ( size == UNITS_PER_WORD && aligned_p ) { fputs ( "\t.word\t" , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; if ( NEED_GOT_RELOC && flag_pic && making_const_table && ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) ) { if ( ! arm_pic_data_is_text_relative || ( GET_CODE ( x ) == SYMBOL_REF && ! SYMBOL_REF_LOCAL_P ( x ) ) ) fputs ( "(GOT)" , asm_out_file ) ; else fputs ( "(GOTOFF)" , asm_out_file ) ; } fputc ( '\n' , asm_out_file ) ; return true ; } mode = GET_MODE ( x ) ; if ( arm_vector_mode_supported_p ( mode ) ) { int i , units ; gcc_assert ( GET_CODE ( x ) == CONST_VECTOR ) ; units = CONST_VECTOR_NUNITS ( x ) ; size = GET_MODE_UNIT_SIZE ( mode ) ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_integer ( elt , size , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT , 1 ) ; } else for ( i = 0 ; i < units ; i ++ ) { rtx elt = CONST_VECTOR_ELT ( x , i ) ; assemble_real ( * CONST_DOUBLE_REAL_VALUE ( elt ) , GET_MODE_INNER ( mode ) , i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT ) ; } return true ; } return default_assemble_integer ( x , size , aligned_p ) ; } </s>

Target hook for assembling integer objects . The ARM version needs to handle word-sized values specially .


<s> static bool arm_can_inline_p ( tree caller , tree callee ) { tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; struct cl_target_option * caller_opts = TREE_TARGET_OPTION ( caller_tree ? caller_tree : target_option_default_node ) ; struct cl_target_option * callee_opts = TREE_TARGET_OPTION ( callee_tree ? callee_tree : target_option_default_node ) ; const struct arm_fpu_desc * caller_fpu = & all_fpus [ caller_opts -> x_arm_fpu_index ] ; const struct arm_fpu_desc * callee_fpu = & all_fpus [ callee_opts -> x_arm_fpu_index ] ; if ( ( caller_fpu -> features & callee_fpu -> features ) != callee_fpu -> features ) return false ; if ( callee_fpu -> model != caller_fpu -> model || callee_fpu -> regs != callee_fpu -> regs ) return false ; return true ; } </s>

Hook to determine if one function can safely inline another .


<s> static int arm_compute_static_chain_stack_bytes ( void ) { if ( IS_NESTED ( arm_current_func_type ( ) ) && ( ( TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM ) || ( flag_stack_check == STATIC_BUILTIN_STACK_CHECK && ! df_regs_ever_live_p ( LR_REGNUM ) ) ) && arm_r3_live_at_start_p ( ) && crtl -> args . pretend_args_size == 0 ) return 4 ; return 0 ; } </s>

Compute the number of bytes used to store the static chain register on the stack , above the stack frame . We need to know this accurately to get the alignment of the rest of the stack frame correct .


<s>
void
arm_declare_function_name
(
FILE
*
stream
,
const
char
*
name
,
tree
decl
)
{
fprintf
(
stream
,
"\t.syntax unified\n"
)
;
if
(
TARGET_THUMB
)
{
if
(
is_called_in_ARM_mode
(
decl
)
||
(
TARGET_THUMB1
&&
!
TARGET_THUMB1_ONLY
&&
cfun
->
is_thunk
)
)
fprintf
(
stream
,
"\t.code 32\n"
)
;
else
if
(
TARGET_THUMB1
)
fprintf
(
stream
,
"\t.code\t16\n\t.thumb_func\n"
)
;
else
fprintf
(
stream
,
"\t.thumb\n\t.thumb_func\n"
)
;
}
else
fprintf
(
stream
,
"\t.arm\n"
)
;
asm_fprintf
(
asm_out_file
,
"\t.fpu %s\n"
,
TARGET_SOFT_FLOAT
"softvfp"
:
TARGET_FPU_NAME
)
;
if
(
TARGET_POKE_FUNCTION_NAME
)
arm_poke_function_name
(
stream
,
(
const
char
*
)
name
)
;
}
</s>

Implement ASM_DECLARE_FUNCTION_NAME . Output the ISA features used by the function fndecl .


<s> static void arm_emit_vfp_multi_reg_pop ( int first_reg , int num_regs , rtx base_reg ) { int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; gcc_assert ( num_regs && num_regs <= 32 ) ; if ( num_regs == 2 && ! arm_arch6 ) { if ( first_reg == 15 ) first_reg -- ; num_regs ++ ; } if ( num_regs > 16 ) { arm_emit_vfp_multi_reg_pop ( first_reg , 16 , base_reg ) ; arm_emit_vfp_multi_reg_pop ( first_reg + 16 , num_regs - 16 , base_reg ) ; return ; } par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + 1 ) ) ; tmp = gen_rtx_SET ( base_reg , plus_constant ( Pmode , base_reg , 8 * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , 0 ) = tmp ; for ( j = 0 , i = first_reg ; j < num_regs ; i += 2 ) { reg = gen_rtx_REG ( DFmode , i ) ; tmp = gen_rtx_SET ( reg , gen_frame_mem ( DFmode , plus_constant ( Pmode , base_reg , 8 * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = 1 ; XVECEXP ( par , 0 , j + 1 ) = tmp ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( TARGET_VFP && REGNO ( base_reg ) == IP_REGNUM ) { RTX_FRAME_RELATED_P ( par ) = 1 ; add_reg_note ( par , REG_CFA_DEF_CFA , hard_frame_pointer_rtx ) ; } else arm_add_cfa_adjust_cfa_note ( par , 2 * UNITS_PER_WORD * num_regs , base_reg , base_reg ) ; } </s>

Generate and emit an insn pattern that we will recognize as a pop_multi of NUM_REGS consecutive VFP regs , starting at FIRST_REG . Unfortunately , since this insn does not reflect very well the actual semantics of the operation , we need to annotate the insn for the benefit of DWARF2 frame unwind information .


<s> static bool arm_evpc_neon_vtrn ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; if ( d -> perm [ 0 ] == 0 ) odd = 0 ; else if ( d -> perm [ 0 ] == 1 ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i += 2 ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + 1 ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN ) { std :: swap ( in0 , in1 ) ; odd = ! odd ; } out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> static bool arm_evpc_neon_vuzp ( struct expand_vec_perm_d * d ) { unsigned int i , odd , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; int swap_nelt ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; swap_nelt = BYTES_BIG_ENDIAN && ! d -> one_vector_p && GET_MODE_SIZE ( d -> vmode ) == 8 ? d -> nelt : 0 ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ] ^ swap_nelt ; if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) odd = 0 ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 1 ) ) odd = 1 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt ; i ++ ) { unsigned elt = ( neon_pair_endian_lane_map ( d -> vmode , i ) * 2 + odd ) & mask ; if ( ( d -> perm [ i ] ^ swap_nelt ) != neon_pair_endian_lane_map ( d -> vmode , elt ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vuzpv16qi_internal ; break ; case V8QImode : gen = gen_neon_vuzpv8qi_internal ; break ; case V8HImode : gen = gen_neon_vuzpv8hi_internal ; break ; case V4HImode : gen = gen_neon_vuzpv4hi_internal ; break ; case V4SImode : gen = gen_neon_vuzpv4si_internal ; break ; case V2SImode : gen = gen_neon_vuzpv2si_internal ; break ; case V2SFmode : gen = gen_neon_vuzpv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vuzpv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( swap_nelt != 0 ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( odd ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> static bool arm_evpc_neon_vzip ( struct expand_vec_perm_d * d ) { unsigned int i , high , mask , nelt = d -> nelt ; rtx out0 , out1 , in0 , in1 ; rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; int first_elem ; bool is_swapped ; if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= 8 ) return false ; is_swapped = BYTES_BIG_ENDIAN ; first_elem = d -> perm [ neon_endian_lane_map ( d -> vmode , 0 ) ^ is_swapped ] ; high = nelt / 2 ; if ( first_elem == neon_endian_lane_map ( d -> vmode , high ) ) ; else if ( first_elem == neon_endian_lane_map ( d -> vmode , 0 ) ) high = 0 ; else return false ; mask = ( d -> one_vector_p ? nelt - 1 : 2 * nelt - 1 ) ; for ( i = 0 ; i < nelt / 2 ; i ++ ) { unsigned elt = neon_pair_endian_lane_map ( d -> vmode , i + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + is_swapped ) ] != elt ) return false ; elt = neon_pair_endian_lane_map ( d -> vmode , i + nelt + high ) & mask ; if ( d -> perm [ neon_pair_endian_lane_map ( d -> vmode , 2 * i + ! is_swapped ) ] != elt ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vzipv16qi_internal ; break ; case V8QImode : gen = gen_neon_vzipv8qi_internal ; break ; case V8HImode : gen = gen_neon_vzipv8hi_internal ; break ; case V4HImode : gen = gen_neon_vzipv4hi_internal ; break ; case V4SImode : gen = gen_neon_vzipv4si_internal ; break ; case V2SImode : gen = gen_neon_vzipv2si_internal ; break ; case V2SFmode : gen = gen_neon_vzipv2sf_internal ; break ; case V4SFmode : gen = gen_neon_vzipv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ; in1 = d -> op1 ; if ( is_swapped ) std :: swap ( in0 , in1 ) ; out0 = d -> target ; out1 = gen_reg_rtx ( d -> vmode ) ; if ( high ) std :: swap ( out0 , out1 ) ; emit_insn ( gen ( out0 , in0 , in1 , out1 ) ) ; return true ; } </s>


<s> void arm_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode ; rtx ( * gen ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; bval = operands [ 0 ] ; rval = operands [ 1 ] ; mem = operands [ 2 ] ; oldval = operands [ 3 ] ; newval = operands [ 4 ] ; is_weak = operands [ 5 ] ; mod_s = operands [ 6 ] ; mod_f = operands [ 7 ] ; mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ 1 ] , gen_lowpart ( mode , rval ) ) ; x = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_EQ ( SImode , x , const0_rtx ) ; emit_insn ( gen_rtx_SET ( bval , x ) ) ; } </s>


<s> bool arm_frame_pointer_required ( void ) { if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return true ; if ( cfun -> has_nonlocal_label ) return true ; if ( TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ( ) ) return true ; if ( ! IS_INTERRUPT ( arm_current_func_type ( ) ) && flag_stack_check == STATIC_BUILTIN_STACK_CHECK && arm_except_unwind_info ( & global_options ) == UI_TARGET && cfun -> can_throw_non_call_exceptions ) { HOST_WIDE_INT size = get_frame_size ( ) ; if ( size <= 0 ) return false ; if ( crtl -> is_leaf && ! cfun -> calls_alloca ) { size += 32 * UNITS_PER_WORD ; if ( size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT ) return true ; } else return true ; } return false ; } </s>


<s> static bool arm_function_ok_for_sibcall ( tree decl , tree exp ) { unsigned long func_type ; if ( cfun -> machine -> sibcall_blocked ) return false ; if ( TARGET_THUMB1 ) return false ; if ( TARGET_VXWORKS_RTP && flag_pic && ! targetm . binds_local_p ( decl ) ) return false ; if ( TARGET_INTERWORK && decl && TREE_PUBLIC ( decl ) && ! TREE_ASM_WRITTEN ( decl ) ) return false ; func_type = arm_current_func_type ( ) ; if ( IS_INTERRUPT ( func_type ) ) return false ; if ( ! VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) { rtx a , b ; tree decl_or_type = decl ; if ( ! decl ) decl_or_type = TREE_TYPE ( TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ) ; a = arm_function_value ( TREE_TYPE ( exp ) , decl_or_type , false ) ; b = arm_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( ! rtx_equal_p ( a , b ) ) return false ; } if ( IS_STACKALIGN ( func_type ) ) return false ; if ( TARGET_AAPCS_BASED && arm_abi == ARM_ABI_AAPCS && decl && DECL_WEAK ( decl ) ) return false ; return true ; } </s>

Return non-zero if it is ok to make a tail-call to DECL .


<s> rtx arm_gen_compare_reg ( enum rtx_code code , rtx x , rtx y , rtx scratch ) { machine_mode mode ; rtx cc_reg ; int dimode_comparison = GET_MODE ( x ) == DImode || GET_MODE ( y ) == DImode ; if ( dimode_comparison && ! REG_P ( x ) ) x = force_reg ( DImode , x ) ; mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; if ( dimode_comparison && mode != CC_CZmode ) { rtx clobber , set ; if ( mode == CC_Zmode && y != const0_rtx ) { gcc_assert ( ! reload_completed ) ; x = expand_binop ( DImode , xor_optab , x , y , NULL_RTX , 0 , OPTAB_WIDEN ) ; y = const0_rtx ; } if ( reload_completed ) gcc_assert ( scratch != NULL && GET_MODE ( scratch ) == SImode ) ; else scratch = gen_rtx_SCRATCH ( SImode ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , scratch ) ; set = gen_rtx_SET ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( 2 , set , clobber ) ) ) ; } else emit_set_insn ( cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ; return cc_reg ; } </s>

X and Y are two things to compare using CODE . Emit the compare insn and return the rtx for register 0 in the proper mode . FP means this is a floating point compare : I do n't think that it is needed on the arm .


<s> static void arm_insert_attributes ( tree fndecl , tree * attributes ) { const char * mode ; if ( ! TARGET_FLIP_THUMB ) return ; if ( TREE_CODE ( fndecl ) != FUNCTION_DECL || DECL_EXTERNAL ( fndecl ) || DECL_BUILT_IN ( fndecl ) || DECL_ARTIFICIAL ( fndecl ) ) return ; if ( current_function_decl ) { mode = TARGET_THUMB ? "thumb" : "arm" ; add_attribute ( mode , attributes ) ; return ; } if ( lookup_attribute ( "target" , * attributes ) != NULL ) return ; mode = thumb_flipper ? "thumb" : "arm" ; add_attribute ( mode , attributes ) ; thumb_flipper = ! thumb_flipper ; } </s>

For testing . Insert thumb or arm modes alternatively on functions .

arm "thumb" "arm" "target" "thumb" "arm"


<s> void arm_load_pic_register ( unsigned long saved_regs ATTRIBUTE_UNUSED ) { rtx l1 , labelno , pic_tmp , pic_rtx , pic_reg ; if ( crtl -> uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE ) return ; gcc_assert ( flag_pic ) ; pic_reg = cfun -> machine -> pic_reg ; if ( TARGET_VXWORKS_RTP ) { pic_rtx = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_BASE ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; emit_insn ( gen_pic_load_addr_32bit ( pic_reg , pic_rtx ) ) ; emit_insn ( gen_rtx_SET ( pic_reg , gen_rtx_MEM ( Pmode , pic_reg ) ) ) ; pic_tmp = gen_rtx_SYMBOL_REF ( Pmode , VXWORKS_GOTT_INDEX ) ; emit_insn ( gen_pic_offset_arm ( pic_reg , pic_reg , pic_tmp ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; pic_rtx = plus_constant ( Pmode , l1 , TARGET_ARM ? 8 : 4 ) ; pic_rtx = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( 1 , pic_rtx ) , UNSPEC_GOTSYM_OFF ) ; pic_rtx = gen_rtx_CONST ( Pmode , pic_rtx ) ; if ( TARGET_32BIT ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } else { if ( arm_pic_register != INVALID_REGNUM && REGNO ( pic_reg ) > LAST_LO_REGNUM ) { pic_tmp = gen_rtx_REG ( SImode , thumb_find_work_register ( saved_regs ) ) ; emit_insn ( gen_pic_load_addr_thumb1 ( pic_tmp , pic_rtx ) ) ; emit_insn ( gen_movsi ( pic_offset_table_rtx , pic_tmp ) ) ; emit_insn ( gen_pic_add_dot_plus_four ( pic_reg , pic_reg , labelno ) ) ; } else if ( arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM && REGNO ( pic_reg ) <= LAST_LO_REGNUM ) { emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; emit_move_insn ( gen_rtx_REG ( Pmode , arm_pic_register ) , pic_reg ) ; emit_use ( gen_rtx_REG ( Pmode , arm_pic_register ) ) ; } else emit_insn ( gen_pic_load_addr_unified ( pic_reg , pic_rtx , labelno ) ) ; } } emit_use ( pic_reg ) ; } </s>

Generate code to load the PIC register . In thumb mode SCRATCH is a low register .


<s> static bool arm_needs_doubleword_align ( machine_mode mode , const_tree type ) { if ( ! type ) return PARM_BOUNDARY < GET_MODE_ALIGNMENT ( mode ) ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) > PARM_BOUNDARY ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) > PARM_BOUNDARY ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( DECL_ALIGN ( field ) > PARM_BOUNDARY ) return true ; return false ; } </s>

Return 1 if double word alignment is required for argument passing . Return -1 if double word alignment used to be required for argument passing before PR77728 ABI fix , but is not required anymore . Return 0 if double word alignment is not required and was n't requried before either .


"enabling backtrace support is only meaningful when compiling for the Thumb"

"enabling callee interworking support is only meaningful when compiling for the Thumb"

"-g with -mno-apcs-frame may not give sensible debugging"

"can not use -mtp=cp15 with 16-bit Thumb"

"-mslow-flash-data only supports non-pic code on armv7-m targets"

Check any incompatible options that the user has specified .


"target CPU does not support THUMB instructions"

"target CPU does not support unaligned accesses"

Reset options between modes that the user has specified .


<s> static void arm_option_params_internal ( void ) { if ( TARGET_THUMB1 ) { targetm . min_anchor_offset = 0 ; targetm . max_anchor_offset = 127 ; } else if ( TARGET_THUMB2 ) { targetm . min_anchor_offset = - 248 ; targetm . max_anchor_offset = 4095 ; } else { targetm . min_anchor_offset = TARGET_MIN_ANCHOR_OFFSET ; targetm . max_anchor_offset = TARGET_MAX_ANCHOR_OFFSET ; } if ( optimize_size ) { max_insns_skipped = 6 ; if ( TARGET_THUMB2 ) max_insns_skipped = arm_restrict_it ? 1 : 4 ; } else max_insns_skipped = ( TARGET_THUMB2 && arm_restrict_it ) ? 1 : current_tune -> max_insns_skipped ; } </s>

Recompute the global settings depending on target attribute options .


<s>
static
void
arm_option_print
(
FILE
*
file
,
int
indent
,
struct
cl_target_option
*
ptr
)
{
int
flags
=
ptr
->
x_target_flags
;
const
struct
arm_fpu_desc
*
fpu_desc
=
&
all_fpus
[
ptr
->
x_arm_fpu_index
]
;
fprintf
(
file
,
"%*sselected arch %s\n"
,
indent
,
""
,
TARGET_THUMB2_P
(
flags
)
"thumb2"
:
TARGET_THUMB_P
(
flags
)
"thumb1"
:
"arm"
)
;
fprintf
(
file
,
"%*sselected fpu %s\n"
,
indent
,
""
,
fpu_desc
->
name
)
;
}
</s>

arm
"%*sselected arch %s\n"
""
"thumb2"
"thumb1"
"arm"
"%*sselected fpu %s\n"
""


<s>
void
arm_output_multireg_pop
(
rtx
*
operands
,
bool
return_pc
,
rtx
cond
,
bool
reverse
,
bool
update
)
{
int
i
;
char
pattern
[
100
]
;
int
offset
;
const
char
*
conditional
;
int
num_saves
=
XVECLEN
(
operands
[
0
]
,
0
)
;
unsigned
int
regno
;
unsigned
int
regno_base
=
REGNO
(
operands
[
1
]
)
;
offset
=
0
;
offset
+=
update
1
:
0
;
offset
+=
return_pc
1
:
0
;
for
(
i
=
offset
;
i
<
num_saves
;
i
++
)
{
regno
=
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
i
)
,
0
)
)
;
gcc_assert
(
(
regno
!=
SP_REGNUM
)
||
(
regno_base
==
SP_REGNUM
)
)
;
if
(
regno
==
regno_base
)
gcc_assert
(
!
update
)
;
}
conditional
=
reverse
"%?%D0"
:
"%?%d0"
;
if
(
(
regno_base
==
SP_REGNUM
)
&&
update
)
{
sprintf
(
pattern
,
"pop%s\t{"
,
conditional
)
;
}
else
{
if
(
regno_base
==
SP_REGNUM
)
sprintf
(
pattern
,
"ldmfd%s"
,
conditional
)
;
if
(
update
)
sprintf
(
pattern
,
"ldmia%s\t"
,
conditional
)
;
else
sprintf
(
pattern
,
"ldm%s\t"
,
conditional
)
;
strcat
(
pattern
,
reg_names
[
regno_base
]
)
;
if
(
update
)
strcat
(
pattern
,
"!, {"
)
;
else
strcat
(
pattern
,
", {"
)
;
}
strcat
(
pattern
,
reg_names
[
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
offset
)
,
0
)
)
]
)
;
for
(
i
=
offset
+
1
;
i
<
num_saves
;
i
++
)
{
strcat
(
pattern
,
", "
)
;
strcat
(
pattern
,
reg_names
[
REGNO
(
XEXP
(
XVECEXP
(
operands
[
0
]
,
0
,
i
)
,
0
)
)
]
)
;
}
strcat
(
pattern
,
"}"
)
;
if
(
IS_INTERRUPT
(
arm_current_func_type
(
)
)
&&
return_pc
)
strcat
(
pattern
,
"^"
)
;
output_asm_insn
(
pattern
,
&
cond
)
;
}
</s>

OPERANDS [ 0 ] is the entire list of insns that constitute pop , OPERANDS [ 1 ] is the base register , RETURN_PC is true iff return insn is in the list , UPDATE is true iff the list contains explicit update of base register .


<s> static void arm_override_options_after_change ( void ) { arm_override_options_after_change_1 ( & global_options ) ; } </s>


This function is used to print CPU tuning information as comment in assembler file . Pointers are not printed for now .


<s> static void arm_relayout_function ( tree fndecl ) { if ( DECL_USER_ALIGN ( fndecl ) ) return ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( ! callee_tree ) callee_tree = target_option_default_node ; DECL_ALIGN ( fndecl ) = FUNCTION_BOUNDARY_P ( TREE_TARGET_OPTION ( callee_tree ) -> x_target_flags ) ; } </s>

Hook to fix function 's alignment affected by target attribute .


<s>
static
bool
arm_rtx_costs
(
rtx
x
,
machine_mode
mode
ATTRIBUTE_UNUSED
,
int
outer_code
,
int
opno
ATTRIBUTE_UNUSED
,
int
*
total
,
bool
speed
)
{
bool
result
;
int
code
=
GET_CODE
(
x
)
;
if
(
TARGET_OLD_RTX_COSTS
||
(
!
current_tune
->
insn_extra_cost
&&
!
TARGET_NEW_GENERIC_COSTS
)
)
{
if
(
!
speed
)
result
=
arm_size_rtx_costs
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
total
)
;
else
result
=
current_tune
->
rtx_costs
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
total
,
speed
)
;
}
else
{
if
(
current_tune
->
insn_extra_cost
)
result
=
arm_new_rtx_costs
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
current_tune
->
insn_extra_cost
,
total
,
speed
)
;
else
result
=
arm_new_rtx_costs
(
x
,
(
enum
rtx_code
)
code
,
(
enum
rtx_code
)
outer_code
,
&
generic_extra_costs
,
total
,
speed
)
;
}
if
(
dump_file
&&
(
dump_flags
&
TDF_DETAILS
)
)
{
print_rtl_single
(
dump_file
,
x
)
;
fprintf
(
dump_file
,
"\n%s cost: %d (%s)\n"
,
speed
"Hot"
:
"Cold"
,
*
total
,
result
"final"
:
"partial"
)
;
}
return
result
;
}
</s>

arm
"\n%s cost: %d (%s)\n"
"Hot"
"Cold"
"final"
"partial"


<s> static bool arm_slowmul_rtx_costs ( rtx x , enum rtx_code code , enum rtx_code outer_code , int * total , bool speed ) { machine_mode mode = GET_MODE ( x ) ; if ( TARGET_THUMB ) { * total = thumb1_rtx_costs ( x , code , outer_code ) ; return true ; } switch ( code ) { case MULT : if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || mode == DImode ) { * total = COSTS_N_INSNS ( 20 ) ; return false ; } if ( CONST_INT_P ( XEXP ( x , 1 ) ) ) { unsigned HOST_WIDE_INT i = ( INTVAL ( XEXP ( x , 1 ) ) & ( unsigned HOST_WIDE_INT ) 0xffffffff ) ; int cost , const_ok = const_ok_for_arm ( i ) ; int j , booth_unit_size ; cost = const_ok ? 4 : 8 ; booth_unit_size = 2 ; for ( j = 0 ; i && j < 32 ; j += booth_unit_size ) { i >>= booth_unit_size ; cost ++ ; } * total = COSTS_N_INSNS ( cost ) ; * total += rtx_cost ( XEXP ( x , 0 ) , mode , code , 0 , speed ) ; return true ; } * total = COSTS_N_INSNS ( 20 ) ; return false ; default : return arm_rtx_costs_1 ( x , outer_code , total , speed ) ; ; } } </s>

RTX costs for cores with a slow MUL implementation . Thumb-2 is not supported on any `` slowmul '' cores , so it can be ignored .


<s> void arm_split_atomic_op ( enum rtx_code code , rtx old_out , rtx new_out , rtx mem , rtx value , rtx model_rtx , rtx cond ) { enum memmodel model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; machine_mode mode = GET_MODE ( mem ) ; machine_mode wmode = ( mode == DImode ? DImode : SImode ) ; rtx_code_label * label ; rtx x ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( model ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_release ( model ) ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_acquire ( model ) ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ; else old_out = new_out ; value = simplify_gen_subreg ( wmode , value , mode , 0 ) ; arm_emit_load_exclusive ( mode , old_out , mem , use_acquire ) ; switch ( code ) { case SET : new_out = value ; break ; case NOT : x = gen_rtx_AND ( wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } case PLUS : if ( mode == DImode ) { emit_move_insn ( new_out , old_out ) ; if ( code == PLUS ) x = gen_adddi3 ( new_out , new_out , value ) ; else x = gen_subdi3 ( new_out , new_out , value ) ; emit_insn ( x ) ; break ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; } arm_emit_store_exclusive ( mode , cond , mem , gen_lowpart ( mode , new_out ) , use_release ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; emit_unlikely_jump ( gen_cbranchsi4 ( x , cond , const0_rtx , label ) ) ; if ( is_armv8_sync || ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( model ) ; } </s>

Split an atomic operation pattern . Operation is given by CODE and is one of PLUS , MINUS , IOR , XOR , SET ( for an exchange operation ) or NOT ( for a nand operation ) . Operation is performed on the content at MEM and on VALUE following the memory model MODEL_RTX . The content at MEM before and after the operation is returned in OLD_OUT and NEW_OUT respectively while the success of the operation is returned in COND . Using a scratch register or an operand register for these determines what result is returned for that pattern .


<s> void arm_split_compare_and_swap ( rtx operands [ ] ) { rtx rval , mem , oldval , newval , scratch ; machine_mode mode ; enum memmodel mod_s , mod_f ; bool is_weak ; rtx_code_label * label1 , * label2 ; rtx x , cond ; rval = operands [ 0 ] ; mem = operands [ 1 ] ; oldval = operands [ 2 ] ; newval = operands [ 3 ] ; is_weak = ( operands [ 4 ] != const0_rtx ) ; mod_s = memmodel_from_int ( INTVAL ( operands [ 5 ] ) ) ; mod_f = memmodel_from_int ( INTVAL ( operands [ 6 ] ) ) ; scratch = operands [ 7 ] ; mode = GET_MODE ( mem ) ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( mod_s ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_release ( mod_s ) ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( mod_s ) || is_mm_consume ( mod_s ) || is_mm_acquire ( mod_s ) ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( mod_s ) ; label1 = NULL ; if ( ! is_weak ) { label1 = gen_label_rtx ( ) ; emit_label ( label1 ) ; } label2 = gen_label_rtx ( ) ; arm_emit_load_exclusive ( mode , rval , mem , use_acquire ) ; cond = arm_gen_compare_reg ( NE , rval , oldval , scratch ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; arm_emit_store_exclusive ( mode , scratch , mem , newval , use_release ) ; cond = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_COMPARE ( CCmode , scratch , const0_rtx ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; if ( ! is_weak ) { x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; } if ( ! is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; if ( is_armv8_sync || ! ( use_acquire || use_release ) ) arm_post_atomic_barrier ( mod_s ) ; if ( is_mm_relaxed ( mod_f ) ) emit_label ( label2 ) ; } </s>

Split a compare and swap pattern . It is IMPLEMENTATION DEFINED whether another memory store between the load-exclusive and store-exclusive can reset the monitor from Exclusive to Open state . This means we must wait until after reload to split the pattern , lest we get a register spill in the middle of the atomic sequence .


<s> bool arm_valid_symbolic_address_p ( rtx addr ) { rtx xop0 , xop1 = NULL_RTX ; rtx tmp = addr ; if ( GET_CODE ( tmp ) == SYMBOL_REF || GET_CODE ( tmp ) == LABEL_REF ) return true ; if ( GET_CODE ( addr ) == CONST ) tmp = XEXP ( addr , 0 ) ; if ( GET_CODE ( tmp ) == PLUS ) { xop0 = XEXP ( tmp , 0 ) ; xop1 = XEXP ( tmp , 1 ) ; if ( GET_CODE ( xop0 ) == SYMBOL_REF && CONST_INT_P ( xop1 ) ) return IN_RANGE ( INTVAL ( xop1 ) , - 0x8000 , 0x7fff ) ; } return false ; } </s>

Returns true if the pattern is a valid symbolic address , which is either a symbol_ref or ( symbol_ref + addend ) . According to the ARM ELF ABI , the initial addend of REL-type relocations processing MOVW and MOVT instructions is formed by interpreting the 16-bit literal field of the instruction as a 16-bit signed value in the range -32768 < = A < 32768 . In Thumb-1 mode , we use upper/lower relocations which have an 8-bit unsigned range of 0 < = A < 256 as described in the AAELF32 relocation handling documentation : REL-type relocations are encoded as unsigned in this case .


<s> static bool arm_valid_target_attribute_p ( tree fndecl , tree ARG_UNUSED ( name ) , tree args , int ARG_UNUSED ( flags ) ) { bool ret = true ; struct gcc_options func_options ; tree cur_tree , new_optimize ; gcc_assert ( ( fndecl != NULL_TREE ) && ( args != NULL_TREE ) ) ; tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) ; if ( ! func_optimize ) func_optimize = optimization_default_node ; memset ( & func_options , 0 , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; cur_tree = arm_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; if ( cur_tree == NULL_TREE ) ret = false ; new_optimize = build_optimization_node ( & func_options ) ; DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = cur_tree ; DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; finalize_options_struct ( & func_options ) ; return ret ; } </s>

Hook to validate attribute ( ( target ( `` string '' ) ) ) .


"attribute %<target%> argument not a string"

"invalid fpu for attribute(target(\"%s\"))"

Inner function to process the attribute ( ( target ( ... ) ) ) , take an argument and set the current options from the argument . If we have a list , recursively go over the list .


<s> tree arm_valid_target_attribute_tree ( tree args , struct gcc_options * opts , struct gcc_options * opts_set ) { if ( ! arm_valid_target_attribute_rec ( args , opts ) ) return NULL_TREE ; arm_option_override_internal ( opts , opts_set ) ; return build_target_option_node ( opts ) ; } </s>

Return a TARGET_OPTION_NODE tree of the target options listed or NULL .


<s> bool arm_vector_mode_supported_p ( machine_mode mode ) { if ( TARGET_NEON && ( mode == V2SFmode || mode == V4SImode || mode == V8HImode || mode == V4HFmode || mode == V16QImode || mode == V4SFmode || mode == V2DImode || mode == V8HFmode ) ) return true ; if ( ( TARGET_NEON || TARGET_IWMMXT ) && ( ( mode == V2SImode ) || ( mode == V4HImode ) || ( mode == V8QImode ) ) ) return true ; if ( TARGET_INT_SIMD && ( mode == V4UQQmode || mode == V4QQmode || mode == V2UHQmode || mode == V2HQmode || mode == V2UHAmode || mode == V2HAmode ) ) return true ; return false ; } </s>

Implements target hook vector_mode_supported_p .