<s> SDValue In2L = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue In2H = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue LSI = DAG . getMemOperand ( cast < MemSDNode > ( Node ) -> getMemOperand ( ) ) ; SDValue Ops [ ] = { Chain , In1 , In2L , In2H , LSI } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;

SDValue Result = DAG . getNode ( NewOp , dl , Tys , Ops , <NUM_LIT> ) ;


<s> regstate_t flags ; flags = <NUM_LIT> ; if ( GET_CODE ( x ) == COND_EXEC ) { if ( for_each_rtx ( & XEXP ( x , <NUM_LIT> ) , frv_registers_conflict_p_1 , & flags ) ) return true ; flags |= frv_cond_flags ( XEXP ( x , <NUM_LIT> ) ) ; x = XEXP ( x , <NUM_LIT> ) ; } return for_each_rtx ( & x , frv_registers_conflict_p_1 , & flags ) ;


<s> unsigned getLDSWaveSpillSize ( ) const {


<s> if ( IDVal == <STR_LIT> ) return ParseDirectiveTC ( is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> , DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ;


<s> WaitInsert ( ) : MachineFunctionPass ( ID ) {


<s> Kind = o . Kind ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case CondCode : CC = o . CC ;


<s> bool AMDGPUOperand :: isMubufOffset ( ) const {

return isImm ( ) && isUInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> case 'f' : case 'v' : return RegName + <NUM_LIT> ; case 'c' : if ( RegName [ <NUM_LIT> ] == 'r' ) return RegName + <NUM_LIT> ; }


<s> return ( MCII . get ( MCI . getOpcode ( ) ) ) ;


<s> unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; unsigned GPRCS1Size = <NUM_LIT> , GPRCS2Size = <NUM_LIT> , DPRCSSize = <NUM_LIT> ; int FramePtrSpillFI = <NUM_LIT> ; if ( VARegSaveSize ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - VARegSaveSize , MachineInstr :: FrameSetup ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , - NumBytes , MachineInstr :: FrameSetup ) ; return ; } for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; int FI = CSI [ i ] . getFrameIdx ( ) ; switch ( Reg ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Reg == FramePtr ) FramePtrSpillFI = FI ; if ( STI . isTargetDarwin ( ) ) { AFI -> addGPRCalleeSavedArea2Frame ( FI ) ; GPRCS2Size += <NUM_LIT> ; } else { AFI -> addGPRCalleeSavedArea1Frame ( FI ) ; GPRCS1Size += <NUM_LIT> ; } break ; default : AFI -> addDPRCalleeSavedAreaFrame ( FI ) ; DPRCSSize += <NUM_LIT> ; } } if ( GPRCS1Size > <NUM_LIT> ) MBBI ++ ; bool HasFP = hasFP ( MF ) ; if ( HasFP ) { unsigned ADDriOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( ADDriOpc ) , FramePtr ) . addFrameIndex ( FramePtrSpillFI ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; AddDefaultCC ( AddDefaultPred ( MIB ) ) ; } if ( GPRCS2Size > <NUM_LIT> ) MBBI ++ ; unsigned DPRCSOffset = NumBytes - ( GPRCS1Size + GPRCS2Size + DPRCSSize ) ; unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize ; unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size ; if ( HasFP ) AFI -> setFramePtrSpillOffset ( MFI -> getObjectOffset ( FramePtrSpillFI ) + NumBytes ) ; AFI -> setGPRCalleeSavedArea1Offset ( GPRCS1Offset ) ; AFI -> setGPRCalleeSavedArea2Offset ( GPRCS2Offset ) ; AFI -> setDPRCalleeSavedAreaOffset ( DPRCSOffset ) ; if ( DPRCSSize > <NUM_LIT> ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } NumBytes = DPRCSOffset ; if ( NumBytes ) {


<s> if ( ! Base . getNode ( ) ) Base = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( Base . getOpcode ( ) == <STR_LIT> ) { int64_t FrameIndex = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FrameIndex , VT ) ; } else if ( Base . getValueType ( ) != VT ) { assert ( VT == <STR_LIT> && Base . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( Base ) ; SDValue Trunc = CurDAG -> getNode ( <STR_LIT> , DL , VT , Base ) ; insertDAGNode ( CurDAG , Base . getNode ( ) , Trunc ) ;


<s> SDValue VAListP = N -> getOperand ( <NUM_LIT> ) ; const Value * VAListS = cast < SrcValueSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; DebugLoc dl = N -> getDebugLoc ( ) ; SDValue Base = DAG . getLoad ( <STR_LIT> , dl , Chain , VAListP , VAListS , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , VAListP , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Offset = DAG . getExtLoad ( <STR_LIT> , <STR_LIT> , dl , Base . getValue ( <NUM_LIT> ) , Tmp , NULL , <NUM_LIT> , <STR_LIT> , false , false , <NUM_LIT> ) ; DataPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Base , Offset ) ;

if ( N -> getValueType ( <NUM_LIT> ) . isFloatingPoint ( ) ) {


<s> default : return CSR_SaveList ; case CallingConv :: PreserveAll : return CSR_preserve_all_SaveList ; }


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , VarArgFrameBytes ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) {


<s> std :: string featureString ; OwningPtr < const TargetMachine > targetMachine ( T . createTargetMachine ( tripleString , featureString ) ) ;

InitRegisterMap ( targetMachine -> getRegisterInfo ( ) ) ;


<s> IntelExprStateMachine ( ) : State ( IES_INIT ) , PrevState ( IES_ERROR ) , BaseReg ( <NUM_LIT> ) , IndexReg ( <NUM_LIT> ) , TmpReg ( <NUM_LIT> ) , Scale ( <NUM_LIT> ) , Imm ( <NUM_LIT> ) , Sym ( nullptr ) , BracCount ( <NUM_LIT> ) , MemExpr ( false ) {


<s> const struct machine_frame_state & fs = cfun -> machine -> fs ;

if ( fs . sp_realigned && cfa_offset <= fs . sp_realigned_offset ) {


<s> bool IsSmallMemAccess ( unsigned AccessSize ) {


<s> if ( region . size ( ) > <NUM_LIT> ) { const llvm :: ELF :: Elf_Options * optb = reinterpret_cast < const llvm :: ELF :: Elf_Options * > ( region . begin ( ) ) ; const llvm :: ELF :: Elf_Options * opte = reinterpret_cast < const llvm :: ELF :: Elf_Options * > ( region . begin ( ) + size ) ; for ( const llvm :: ELF :: Elf_Options * opt = optb ; opt < opte ; opt += opt -> size ) { switch ( opt -> kind ) { default : break ; case llvm :: ELF :: ODK_REGINFO : if ( config ( ) . targets ( ) . triple ( ) . isArch32Bit ( ) ) { const llvm :: ELF :: Elf32_RegInfo * reg = reinterpret_cast < const llvm :: ELF :: Elf32_RegInfo * > ( opt + <NUM_LIT> ) ; m_GP0Map [ & pInput ] = reg -> ri_gp_value ; } else { const llvm :: ELF :: Elf64_RegInfo * reg = reinterpret_cast < const llvm :: ELF :: Elf64_RegInfo * > ( opt + <NUM_LIT> ) ; m_GP0Map [ & pInput ] = reg -> ri_gp_value ; } break ; } }


<s> DotDispVal = DotDisp . getZExtValue ( ) ; } else if ( isParsingInlineAsm ( ) && Tok . is ( AsmToken :: Identifier ) ) { unsigned DotDisp ; std :: pair < StringRef , StringRef > BaseMember = DotDispStr . split ( '.' ) ; if ( SemaCallback -> LookupInlineAsmField ( BaseMember . first , BaseMember . second , DotDisp ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; DotDispVal = DotDisp ; } else return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; if ( isParsingInlineAsm ( ) && Tok . is ( AsmToken :: Identifier ) ) { SMLoc Loc = SMLoc :: getFromPointer ( DotDispStr . data ( ) ) ; unsigned Len = DotDispStr . size ( ) ; unsigned Val = OrigDispVal + DotDispVal ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_DotOperator , Loc , Len , Val ) ) ; } NewDisp = MCConstantExpr :: Create ( OrigDispVal + DotDispVal , getContext ( ) ) ;


<s> void LLVM_EXTERNAL_VI<ISA_LIT>BILITY LLVMInitialize<ISA_LIT>AsmPrinter ( ) { TargetRegistry :: RegisterAsmPrinter ( getThe<ISA_LIT>Target ( ) , llvm :: create<ISA_LIT>AsmPrinterPass ) ;

TargetRegistry :: RegisterAsmPrinter ( getTheGCNTarget ( ) , create<ISA_LIT>AsmPrinterPass ) ;


<s> return decodeBDAddr20Operand ( Inst , Field , <STR_LIT> ) ;


<s> <ISA_LIT>DelaySlotKiller ( <ISA_LIT>TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , TII ( static_cast < const <ISA_LIT>InstrInfo * > ( tm . getInstrInfo ( ) ) ) {


<s> return symbol ; } note = find_reg_equal_equiv_note ( def_insn ) ; if ( note && GET_CODE ( XEXP ( note , <NUM_LIT> ) ) == SYMBOL_REF ) return XEXP ( note , <NUM_LIT> ) ; if ( recurse_p && REG_P ( src ) ) return mips_find_pic_call_symbol ( def_insn , src , false ) ; }


<s> bool IsFunction = MO . isGlobal ( ) && isa < Function > ( MO . getGlobal ( ) ) ; if ( TF & <STR_LIT> ) { if ( IsFunction ) { Expr = <ISA_LIT>Z80MCExpr :: create ( <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_PM_LO8 , Expr , IsNegated , Ctx ) ; } else { Expr = <ISA_LIT>Z80MCExpr :: create ( <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_LO8 , Expr , IsNegated , Ctx ) ; } } else if ( TF & <STR_LIT> ) { if ( IsFunction ) { Expr = <ISA_LIT>Z80MCExpr :: create ( <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_PM_HI8 , Expr , IsNegated , Ctx ) ; } else { Expr = <ISA_LIT>Z80MCExpr :: create ( <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_HI8 , Expr , IsNegated , Ctx ) ; } } else if ( TF != <NUM_LIT> ) {


<s> if ( ( T -> getContainedType ( <NUM_LIT> ) -> isFloatTy ( ) ) && ( T -> getContainedType ( <NUM_LIT> ) -> isFloatTy ( ) ) ) return CFRet ; if ( ( T -> getContainedType ( <NUM_LIT> ) -> isDoubleTy ( ) ) && ( T -> getContainedType ( <NUM_LIT> ) -> isDoubleTy ( ) ) ) return CDRet ; break ; default : break ;


<s> CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ;


<s> MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; <ISA_LIT>FI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ;


<s> if ( isa < UndefValue > ( GVar -> getInitializer ( ) ) ) return false ; return true ;


<s> int64_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result ;


<s> if ( MF . getFunction ( ) . hasPersonalityFn ( ) ) { Changed |= addCatches ( MF ) ; Changed |= replaceFuncletReturns ( MF ) ; } Changed |= removeUnnecessaryUnreachables ( MF ) ; if ( MF . getFunction ( ) . hasPersonalityFn ( ) ) { Changed |= addExceptionExtraction ( MF ) ; Changed |= restoreStackPointer ( MF ) ; } return Changed ;


<s> unsigned regCode = MRI . getEncodingValue ( MI . getOperand ( OpNo ) . getReg ( ) ) ;

return ( regCode & <NUM_LIT> ) >> shift ;


<s> PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfTable ; if ( T . getOS ( ) == Triple :: OpenBSD && T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = <NUM_LIT> ;


return createRegOperand ( <STR_LIT> , Val ) ;


<s> static const CostTblEntry < <STR_LIT> > CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; int Idx = - <NUM_LIT> ; if ( ST -> hasNEON ( ) ) Idx = CostTableLookup ( CostTbl , ISDOpcode , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * CostTbl [ Idx ] . Cost ; return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info ) ;


<s> case 'r' : case 'f' : case 'v' : return RegName + <NUM_LIT> ; case 'c' : if ( RegName [ <NUM_LIT> ] == 'r' ) return RegName + <NUM_LIT> ; } return RegName ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ;


<s> AU . addPreserved < SlotIndexes > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ;

AU . addPreserved < MachineDominatorTree > ( ) ;


<s> bool HasFP = hasFP ( MF ) ; DebugLoc DL ; if ( ForceStackAlign ) { if ( MFI -> hasCalls ( ) ) MaxAlign = ( StackAlign > MaxAlign ) ? StackAlign : MaxAlign ; else if ( MaxAlign < SlotSize ) MaxAlign = SlotSize ; } int TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) <ISA_LIT>FI -> setCalleeSavedFrameSize ( <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) - TailCallReturnAddrDelta ) ; if ( Is64Bit && ! Fn -> hasFnAttr ( Attribute :: NoRedZone ) && ! needsStackRealignment ( MF ) && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! Subtarget -> isTargetWin64 ( ) ) { uint64_t MinSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; if ( HasFP ) MinSize += SlotSize ; StackSize = std :: max ( MinSize , StackSize > <NUM_LIT> ? StackSize - <NUM_LIT> : <NUM_LIT> ) ; MFI -> setStackSize ( StackSize ) ; } else if ( Subtarget -> isTargetWin64 ( ) ) { StackSize += <NUM_LIT> ; MFI -> setStackSize ( StackSize ) ; } if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( getSUBriOpcode ( Is64Bit , - TailCallReturnAddrDelta ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( - TailCallReturnAddrDelta ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; const TargetData * TD = MF . getTarget ( ) . getTargetData ( ) ; uint64_t NumBytes = <NUM_LIT> ; int stackGrowth = - TD -> getPointerSize ( ) ; if ( HasFP ) { uint64_t FrameSize = StackSize - SlotSize ; if ( needsStackRealignment ( MF ) ) FrameSize = ( FrameSize + MaxAlign - <NUM_LIT> ) / MaxAlign * MaxAlign ; NumBytes = FrameSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( FramePtr , RegState :: Kill ) ; if ( needsFrameMoves ) { MCSymbol * FrameLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addSym ( FrameLabel ) ; if ( StackSize ) { MachineLocation SPDst ( MachineLocation :: VirtualFP ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP , <NUM_LIT> * stackGrowth ) ; Moves . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ; } else { MachineLocation SPDst ( StackPtr ) ; MachineLocation SPSrc ( StackPtr , stackGrowth ) ;


<s> if ( final_adjust > crtl -> outgoing_args_size || cfun -> calls_alloca || crtl -> calls_eh_return ) { emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; need_barrier_p = false ; } if ( frame_pointer_needed && ( final_adjust || cfun -> calls_alloca ) ) { insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , hard_frame_pointer_rtx , GEN_INT ( - callee_offset ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = callee_adjust == <NUM_LIT> ; } else aarch64_add_sp ( IP1_REGNUM , final_adjust , df_regs_ever_live_p ( IP1_REGNUM ) ) ; aarch64_restore_callee_saves ( DImode , callee_offset , R0_REGNUM , R30_REGNUM , callee_adjust != <NUM_LIT> , & cfi_ops ) ; aarch64_restore_callee_saves ( DFmode , callee_offset , V0_REGNUM , V31_REGNUM , callee_adjust != <NUM_LIT> , & cfi_ops ) ; if ( need_barrier_p ) emit_insn ( gen_stack_tie ( stack_pointer_rtx , stack_pointer_rtx ) ) ; if ( callee_adjust != <NUM_LIT> ) aarch64_pop_regs ( reg1 , reg2 , callee_adjust , & cfi_ops ) ; if ( callee_adjust != <NUM_LIT> || initial_adjust > <NUM_LIT> ) { insn = get_last_insn ( ) ; rtx new_cfa = plus_constant ( Pmode , stack_pointer_rtx , initial_adjust ) ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , new_cfa , cfi_ops ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; cfi_ops = NULL ; } aarch64_add_sp ( IP0_REGNUM , initial_adjust , df_regs_ever_live_p ( IP0_REGNUM ) ) ; if ( cfi_ops ) { insn = get_last_insn ( ) ; cfi_ops = alloc_reg_note ( REG_CFA_DEF_CFA , stack_pointer_rtx , cfi_ops ) ; REG_NOTES ( insn ) = cfi_ops ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;


<s> static void findUses ( Value * V , Function & F , SmallVectorImpl < std :: pair < CallBase * , Function * >> & Uses ) { for ( User * U : V -> users ( ) ) { if ( auto * BC = dyn_cast < BitCastOperator > ( U ) ) findUses ( BC , F , Uses ) ;

else if ( auto * A = dyn_cast < GlobalAlias > ( U ) ) findUses ( A , F , Uses ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Subtarget . hasV5TEOps ( ) ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } else { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ;


<s> for ( i = <NUM_LIT> ; i < n_parts ; i ++ ) { if ( i == <NUM_LIT> ) value = UINTVAL ( op ) ; else value >>= GET_MODE_BITSIZE ( part_mode ) ;

if ( ( value & part_mask ) != ( def & part_mask ) ) {


<s> setAttributeItem ( Attribute , Value , true ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVLD2_UPD ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; unsigned DefReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineInstr & UseMI : MRI -> use_nodbg_instructions ( DefReg ) ) { int UseIdx = SwapMap [ & UseMI ] ; SwapVector [ UseIdx ] . WillRemove = <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( UseMI . dump ( ) ) ; } } } else if ( SwapVector [ EntryIdx ] . IsStore && SwapVector [ EntryIdx ] . IsSwap ) { int Repr = EC -> getLeaderValue ( SwapVector [ EntryIdx ] . VSEId ) ; if ( ! SwapVector [ Repr ] . WebRejected ) { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; unsigned UseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( UseReg ) ; int DefIdx = SwapMap [ DefMI ] ; SwapVector [ DefIdx ] . WillRemove = <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI -> dump ( ) ) ; } } else if ( SwapVector [ EntryIdx ] . IsSwappable && SwapVector [ EntryIdx ] . SpecialHandling != <NUM_LIT> ) {


<s> UsesELFSectionDirectiveForBSS = true ; HasSingleParameterDotFile = false ;


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerVectorShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ;

if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ;


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const {

return createELFObjectWriter ( new <ISA_LIT>ELFObjectWriter ( OSType ) , OS , false ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


return ( __m512i ) __builtin_ia32_permdi512_mask ( ( __v8di ) __X , __I , ( __v8di ) _mm512_undefined_si512 ( ) , ( __mmask8 ) ( - <NUM_LIT> ) ) ;


<s> case 'f' : if ( Subtarget . hasSPE ( ) ) { if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else { if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'v' : if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Subtarget . hasQPX ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( Subtarget . hasAltivec ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> && Subtarget . useCRBits ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ;

} else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) {


<s> bool <ISA_LIT>DAGToDAGISel :: SelectGlobalValueConstantOffset ( SDValue Addr , SDValue & IntPtr ) { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Addr ) ) { IntPtr = CurDAG -> getIntPtrConstant ( Cst -> getZExtValue ( ) / <NUM_LIT> , SDLoc ( Addr ) , true ) ;


<s> return expandBinaryOperation ( Op , DAG ) ;


<s> MVT getFenceOperandTy ( const DataLayout & DL ) const override { return <STR_LIT> ;


<s> In = extractSubVector ( In , <NUM_LIT> , DAG , DL , std :: max ( <NUM_LIT> , ( unsigned ) VT . getSizeInBits ( ) / Scale ) ) ; InVT = In . getValueType ( ) ; }

if ( VT . getVectorNumElements ( ) != InVT . getVectorNumElements ( ) ) Opcode = getOpcode_EXTEND_VECTOR_INREG ( Opcode ) ;


return STI . getFeatureBits ( ) & <STR_LIT> ;


<s> <ISA_LIT>ISelAddressMode AM ( <ISA_LIT>ISelAddressMode :: AddrType :: ARI ) ; if ( ! matchAddress ( N , AM ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( AM . isPCRelative ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( AM . hasIndexReg ( ) || AM . Disp != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ;


<s> switch ( Letter ) { default : break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : { ConstantSDNode * CST = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! CST ) return ; unsigned Value = CST -> getZExtValue ( ) ; switch ( Letter ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case 'I' : if ( ( short ) Value == ( int ) Value ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case 'J' : case 'L' : if ( ( short ) Value == <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ;


<s> for ( BasicBlock * B : L . blocks ( ) ) { for ( auto I = B -> begin ( ) , E = B -> end ( ) ; I != E ; ++ I ) { auto * GEP = dyn_cast < GetElementPtrInst > ( I ) ; if ( ! GEP ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * GEP << <STR_LIT> ) ; const auto * R = dyn_cast < SCEVAddRecExpr > ( SE . getSCEV ( GEP ) ) ; if ( ! R || R -> getLoop ( ) != & L ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * R << <STR_LIT> ) ; const auto * Step = R -> getStepRecurrence ( SE ) ; const auto StepRange = SE . getSignedRange ( Step ) ; if ( ! InRange ( StepRange ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Step << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << StepRange << <STR_LIT> ) ; continue ; } const auto * Index = SE . getAddRecExpr ( SE . getConstant ( R -> getType ( ) , <NUM_LIT> ) , Step , & L , R -> getNoWrapFlags ( ) ) ; const auto IndexRange = SE . getSignedRange ( Index ) ; if ( ! InRange ( IndexRange ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Index << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << IndexRange << <STR_LIT> ) ; continue ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Changed = true ; SCEVExpander Rewriter ( SE , DL , <STR_LIT> ) ; Rewriter . disableCanonicalMode ( ) ; Rewriter . setInsertPoint ( & * I ) ; Value * BaseVal = Rewriter . expandCodeFor ( R -> getStart ( ) ) ; Value * IndexVal = Rewriter . expandCodeFor ( SE . getTruncateExpr ( Index , i8 ) ) ; IRBuilder < > Builder ( B , I ) ; Value * V = Builder . CreateBitCast ( BaseVal , i8Ptr ) ;

V = Builder . CreateGEP ( i8 , V , Builder . CreateZExt ( IndexVal , DL . getIndexType ( i8Ptr ) ) , <STR_LIT> ) ;


<s> <ISA_LIT>LoadStoreOpt ( ) : MachineFunctionPass ( & ID ) {


<s> bool isTargetRepo ( ) const { return TargetTriple . isOSBinFormatRepo ( ) ;


<s> static MCSymbol * GetAnonSym ( MCSymbol * Sym , MCContext & Ctx ) { SmallString < <NUM_LIT> > TmpStr ( Sym -> getName ( ) . begin ( ) , Sym -> getName ( ) . end ( ) ) ;


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ; addPass ( createUnpackMachineBundles ( nullptr ) ) ;


<s> O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; return ; case MachineOperand :: MO_GlobalAddress : if ( TM . getRelocationModel ( ) != Reloc :: Static ) { GlobalValue * GV = MO . getGlobal ( ) ; if ( ( ( GV -> isDeclaration ( ) || GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) || GV -> hasCommonLinkage ( ) ) ) ) {

O << * GetSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ;


<s> uint8_t Cost = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = & <STR_LIT> ;

if ( Subtarget -> useNEONForSinglePrecisionFP ( ) ) Cost = <NUM_LIT> ;


<s> case MachineOperand :: MO_Register : assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; assert ( MO . getReg ( ) > <STR_LIT> && MO . getReg ( ) < <STR_LIT> && <STR_LIT> ) ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP , isDarwin ) ;


<s> HasMFOCRF = false ; Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasFPU = false ; HasQPX = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasBPERMD = false ; HasExtDiv = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; FeatureMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ; HasPartwordAtomics = false ; HasDirectMove = false ;


<s> AtomicOrdering FenceOrdering = static_cast < AtomicOrdering > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; SynchronizationScope FenceScope = static_cast < SynchronizationScope > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; if ( FenceOrdering == AtomicOrdering :: SequentiallyConsistent && FenceScope == CrossThread ) { return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> static DecodeStatus DecodeQQRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) {


<s> if ( TM . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA ) getTargetStreamer ( ) -> EmitDirectiveHSACodeObjectVersion ( <NUM_LIT> , <NUM_LIT> ) ; IsaInfo :: IsaVersion ISA = IsaInfo :: getIsaVersion ( getSTI ( ) -> getFeatureBits ( ) ) ;

getTargetStreamer ( ) -> EmitDirectiveHSACodeObjectISA ( ISA . Major , ISA . Minor , ISA . Stepping , <STR_LIT> , <STR_LIT> ) ;


return ( INSN_P ( i1 ) && rtx_equal_p ( PATTERN ( i1 ) , PATTERN ( i3 ) ) && any_condjump_p ( i2 ) && onlyjump_p ( i2 ) ) ;


<s> else if ( ClUncheckedLdSt == UncheckedAlways ) return true ; unsigned FrameSize = <NUM_LIT> ;

for ( unsigned i = <NUM_LIT> , e = MFI -> getObjectIndexEnd ( ) ; i != e ; ++ i ) FrameSize += MFI -> getObjectSize ( i ) ;


<s> return ( Attributes & <ISA_LIT>FMA3Intrinsic ) != <NUM_LIT> ;


<s> AU . addRequired < MachineModuleInfo > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> int32_t Value = - ( int32_t ) CE -> getValue ( ) ; return <NUM_LIT> < Value && Value < <NUM_LIT> ;


<s> static MachineInstr * insertCopy ( const TargetInstrInfo * TII , MachineInstr & MI , unsigned Dst , unsigned Src , bool IsKill ) { MachineInstrBuilder MIB = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Src , getKillRegState ( IsKill ) ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; default : return false ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( i ) ; updateValueMap ( & Arg , ResultReg ) ; ++ i ; } MRI . addLiveIn ( <STR_LIT> ) ; auto * MFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( auto const & Arg : F -> args ( ) ) { <STR_LIT> ArgTy = getLegalType ( getSimpleType ( Arg . getType ( ) ) ) ; if ( ArgTy == <STR_LIT> ) { MFI -> clearParamsAndResults ( ) ; return false ; } MFI -> addParam ( ArgTy ) ; } if ( ! F -> getReturnType ( ) -> isVoidTy ( ) ) { <STR_LIT> RetTy = getLegalType ( getSimpleType ( F -> getReturnType ( ) ) ) ; if ( RetTy == <STR_LIT> ) { MFI -> clearParamsAndResults ( ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ;


<s> static int go_if_legitimate_address_internal ( rtx operand , enum machine_mode mode , int strict ) { int addr_mode ; if ( CONSTANT_ADDRESS_P ( operand ) && TARGET_M6812 ) { if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; } addr_mode = m68hc11_addr_mode | ( strict ? ADDR_STRICT : <NUM_LIT> ) ; if ( m68hc11_valid_addressing_p ( operand , mode , addr_mode ) ) { return <NUM_LIT> ; } if ( PUSH_POP_ADDRESS_P ( operand ) ) { return <NUM_LIT> ; } if ( symbolic_memory_operand ( operand , mode ) ) { return <NUM_LIT> ;


C_CPP_HASHNODE ( _Bool_keyword ) -> flags |= NODE_CONDITIONAL ;


<s> MBB . remove ( & MI ) ; return NewTerm ; } } else { if ( ! KillVal ) { TmpReg = MRI -> createVirtualRegister ( TRI -> getBoolRC ( ) ) ; ComputeKilledMaskMI = BuildMI ( MBB , MI , DL , TII -> get ( XorOpc ) , TmpReg ) . add ( Op ) . addReg ( Exec ) ; MaskUpdateMI = BuildMI ( MBB , MI , DL , TII -> get ( AndN2Opc ) , LiveMaskReg ) . addReg ( LiveMaskReg ) . addReg ( TmpReg ) ; } else { MaskUpdateMI = BuildMI ( MBB , MI , DL , TII -> get ( AndN2Opc ) , LiveMaskReg ) . addReg ( LiveMaskReg ) . add ( Op ) ; } } MachineInstr * EarlyTermMI = BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; MachineInstr * NewTerm ; MachineInstr * WQMMaskMI = nullptr ; Register LiveMaskWQM ; if ( IsDemote ) { LiveMaskWQM = MRI -> createVirtualRegister ( TRI -> getBoolRC ( ) ) ; WQMMaskMI = BuildMI ( MBB , MI , DL , TII -> get ( WQMOpc ) , LiveMaskWQM ) . addReg ( LiveMaskReg ) ; NewTerm = BuildMI ( MBB , MI , DL , TII -> get ( AndOpc ) , Exec ) . addReg ( Exec ) . addReg ( LiveMaskWQM ) ; } else { if ( Op . isImm ( ) ) { unsigned MovOpc = ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; NewTerm = BuildMI ( MBB , & MI , DL , TII -> get ( MovOpc ) , Exec ) . addImm ( <NUM_LIT> ) ; } else if ( ! IsWQM ) { NewTerm = BuildMI ( MBB , & MI , DL , TII -> get ( AndOpc ) , Exec ) . addReg ( Exec ) . addReg ( LiveMaskReg ) ; } else { unsigned Opcode = KillVal ? AndN2Opc : AndOpc ; NewTerm = BuildMI ( MBB , & MI , DL , TII -> get ( Opcode ) , Exec ) . addReg ( Exec ) . add ( Op ) ; } } LIS -> RemoveMachineInstrFromMaps ( MI ) ; MBB . remove ( & MI ) ; assert ( EarlyTermMI ) ; assert ( MaskUpdateMI ) ; assert ( NewTerm ) ; if ( ComputeKilledMaskMI ) LIS -> InsertMachineInstrInMaps ( * ComputeKilledMaskMI ) ;

LIS -> InsertMachineInstrInMaps ( * MaskUpdateMI ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( Operand + <NUM_LIT> ) ) ; return MCDisassembler :: Success ;


<s> if ( ! isGFX10Plus ( * STI ) ) return <NUM_LIT> ;

return hasGFX10_3Insts ( * STI ) ? <NUM_LIT> : <NUM_LIT> ;


<s> TargetRegisterClass :: sc_iterator I = RC -> getSuperClasses ( ) ; do { switch ( Super -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Super ; } Super = * I ++ ; } while ( Super ) ;


uint64_t Imm = MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> uint32_t GVarInfo = Linkage == GlobalValue :: ExternalLinkage ? <STR_LIT> : <STR_LIT> ; auto VarEntry = llvm :: make_unique < BTFKindVar > ( Global . getName ( ) , GVTypeId , GVarInfo ) ; uint32_t VarId = addType ( std :: move ( VarEntry ) ) ; if ( DataSecEntries . find ( SecName ) == DataSecEntries . end ( ) ) { DataSecEntries [ SecName ] = llvm :: make_unique < BTFKindDataSec > ( Asm , SecName ) ; } const DataLayout & DL = Global . getParent ( ) -> getDataLayout ( ) ; uint32_t Size = DL . getTypeAllocSize ( Global . getType ( ) -> getElementType ( ) ) ; DataSecEntries [ SecName ] -> addVar ( VarId , Asm -> getSymbol ( & Global ) , Size ) ; }


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( Src2Value ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( needsExt ) { unsigned ResultReg ; ResultReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , isZExt ) ; if ( ResultReg == <NUM_LIT> ) return false ; SrcReg1 = ResultReg ; if ( ! UseImm ) { ResultReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , isZExt ) ; if ( ResultReg == <NUM_LIT> ) return false ; SrcReg2 = ResultReg ; } } if ( ! UseImm ) { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CmpOpc ) ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; } else {


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getFirstTerminator ( ) ; if ( MBBI == MBB . end ( ) ) MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; if ( ! MBBI -> isTerminator ( ) ) MBBI = std :: next ( MBBI ) ; } auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t FPOffset = StackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ;

assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ;


<s> return ( __m128i ) __builtin_ia32_pabsw128_mask ( ( __v8hi ) __A , ( __v8hi ) _mm_setzero_si128 ( ) , ( __mmask8 ) __U ) ;


<s> unsigned int model = SYMBOL_REF_TLS_MODEL ( x ) ; switch ( model ) { case TLS_MODEL_GLOBAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_GD32 ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; } return dest ; case TLS_MODEL_LOCAL_DYNAMIC : if ( TARGET_GNU2_TLS ) { reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; dest = gen_rtx_PLUS ( Pmode , dest , addend ) ; } return dest ; case TLS_MODEL_INITIAL_EXEC : labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else if ( TARGET_THUMB2 ) emit_insn ( gen_tls_load_dot_plus_four ( reg , NULL , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC :


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ;

while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) { return std :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ;


<s> static MachineInstr * findFirstPredicateSetterFrom ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) { while ( I != MBB . begin ( ) ) { -- I ;


<s> mcld :: TargetRegistry :: RegisterDiagnosticLineInfo ( mcld :: The<ISA_LIT>elTarget , create<ISA_LIT>DiagLineInfo ) ;

mcld :: TargetRegistry :: RegisterDiagnosticLineInfo ( mcld :: The<ISA_LIT>64elTarget , create<ISA_LIT>DiagLineInfo ) ;


<s> if ( ! HBS :: getSubregMask ( Inp , B , W , MRI ) ) return false ; for ( Register R = AVs . find_first ( ) ; R ; R = AVs . find_next ( R ) ) { if ( ! BT . has ( R ) || Forbidden [ R ] ) continue ; const BitTracker :: RegisterCell & RC = BT . lookup ( R ) ; unsigned RW = RC . width ( ) ; if ( W == RW ) { if ( FRC != MRI . getRegClass ( R ) ) continue ; if ( ! HBS :: isTransparentCopy ( R , Inp , MRI ) ) continue ; if ( ! HBS :: isEqual ( InpRC , B , RC , <NUM_LIT> , W ) ) continue ; Out . Reg = R ; Out . Sub = <NUM_LIT> ; return true ; } if ( W * <NUM_LIT> != RW ) continue ; if ( MRI . getRegClass ( R ) != & <STR_LIT> ) continue ; if ( HBS :: isEqual ( InpRC , B , RC , <NUM_LIT> , W ) ) Out . Sub = <STR_LIT> ;

else if ( HBS :: isEqual ( InpRC , B , RC , W , W ) ) Out . Sub = <STR_LIT> ;


<s> SDLoc DL ( Node ) ; unsigned NF = Node -> getNumValues ( ) - <NUM_LIT> ; MVT VT = Node -> getSimpleValueType ( <NUM_LIT> ) ; unsigned Log2SEW = Log2_32 ( VT . getScalarSizeInBits ( ) ) ; <STR_LIT> LMUL = <ISA_LIT>TargetLowering :: getLMUL ( VT ) ; unsigned CurOp = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Operands ; if ( IsMasked ) { SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + CurOp , Node -> op_begin ( ) + CurOp + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; Operands . push_back ( MaskedOff ) ; CurOp += NF ; } MVT IndexVT ; addVectorLoadStoreOperands ( Node , Log2SEW , DL , CurOp , IsMasked , true , Operands , true , & IndexVT ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; <STR_LIT> IndexLMUL = <ISA_LIT>TargetLowering :: getLMUL ( IndexVT ) ; unsigned IndexLog2EEW = Log2_32 ( IndexVT . getScalarSizeInBits ( ) ) ; if ( IndexLog2EEW == <NUM_LIT> && ! Subtarget -> is64Bit ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const <STR_LIT> * P = <STR_LIT> ( NF , IsMasked , IsOrdered , IndexLog2EEW , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ;

MachineSDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ;


<s> fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - <NUM_LIT> , mode ) ; real_arithmetic ( & pred_half , MINUS_EXPR , & dconsthalf , & half_minus_pred_half ) ; half = force_reg ( mode , const_double_from_real_value ( pred_half , mode ) ) ; xa = expand_simple_binop ( mode , PLUS , xa , half , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xi = gen_reg_rtx ( int_mode_for_mode ( mode ) . require ( ) ) ;


<s> bool hasVirt ( ) const { return HasVirt ;


<s> Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( DestReg ) ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) {

assert ( <STR_LIT> . contains ( DestReg ) ) ;


<s> return Subtarget . isCallingConvWin64 ( CallConv ) ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : ForceFramePointer ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) , BytesToPopOnReturn ( <NUM_LIT> ) , ReturnAddrIndex ( <NUM_LIT> ) , TailCallReturnAddrDelta ( <NUM_LIT> ) , SRetReturnReg ( <NUM_LIT> ) , GlobalBaseReg ( <NUM_LIT> ) , ReserveFP ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , RegSaveFrameIndex ( <NUM_LIT> ) , VarArgsGPOffset ( <NUM_LIT> ) , VarArgsFPOffset ( <NUM_LIT> ) {


<s> virtual void EmitCodeAlignment ( unsigned ByteAlignment , unsigned MaxBytesToEmit = <NUM_LIT> ) {


<s> EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getBitcast ( IntVT , SourceConst ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , IntVT , N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) , MaskConst ) ; SDValue Res = DAG . getBitcast ( VT , NewAnd ) ; return Res ; } return SDValue ( ) ;


<s> assert ( BuildVec && BuildVec -> getOpcode ( ) == TargetOpcode :: G_BUILD_VECTOR ) ; for ( unsigned i = <NUM_LIT> ; i < ConstVec -> getNumElements ( ) ; ++ i ) GR -> add ( ConstVec -> getElementAsConstant ( i ) , & MF , BuildVec -> getOperand ( <NUM_LIT> + i ) . getReg ( ) ) ; } GR -> add ( Const , & MF , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } else { RegsAlreadyAddedToDT [ & MI ] = Reg ; assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; MachineInstr * SrcMI = MRI . getVRegDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( SrcMI && isSpvIntrinsic ( * SrcMI , <STR_LIT> ) ) ToEraseComposites . push_back ( SrcMI ) ; } } } }


<s> for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer -> EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer -> EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer -> EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; else OutStreamer -> EmitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( Reg , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ; } assert ( MRI -> hasOneDef ( Reg ) && <STR_LIT> ) ; MachineOperand * Def = & ( * ( MRI -> def_begin ( Reg ) ) ) ; MachineOperand * UseOperand = & ( RI ) ; bool UseIsOutsideDefMBB = Def -> getParent ( ) -> getParent ( ) != MBB ; if ( UseIsOutsideDefMBB && UseOperand -> isKill ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( Reg , TRI ) << <STR_LIT> ) ; UseOperand -> setIsKill ( false ) ; } }


<s> gcc_assert ( to == STACK_POINTER_REGNUM ) ; if ( from == ARG_POINTER_REGNUM ) return frame . stack_pointer_offset ; gcc_assert ( from == FRAME_POINTER_REGNUM ) ;

return frame . stack_pointer_offset - frame . frame_pointer_offset ;


<s> if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> static SDValue CreateStoreLR ( unsigned Opc , SelectionDAG & DAG , StoreSDNode * SD , SDValue Chain , unsigned Offset ) { SDValue Ptr = SD -> getBasePtr ( ) , Value = SD -> getValue ( ) ; EVT MemVT = SD -> getMemoryVT ( ) , BasePtrVT = Ptr . getValueType ( ) ; DebugLoc DL = SD -> getDebugLoc ( ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> ) ; if ( Offset ) Ptr = DAG . getNode ( <STR_LIT> , DL , BasePtrVT , Ptr , DAG . getConstant ( Offset , BasePtrVT ) ) ; SDValue Ops [ ] = { Chain , Value , Ptr } ;

return DAG . getMemIntrinsicNode ( Opc , DL , VTList , Ops , <NUM_LIT> , MemVT , SD -> getMemOperand ( ) ) ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( IMMEDIATE ) ; Op -> Imm . Value = Value ; Op -> StartLoc = Start ; Op -> EndLoc = End ;


<s> switch ( TI -> getOpcode ( ) ) { case <STR_LIT> : { MachineBasicBlock * TBB = TI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! MBB . isLayoutSuccessor ( TBB ) ) BuildMI ( MBB , TI , TI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( TBB ) ; TI -> eraseFromParent ( ) ; Changed = true ; break ; } case <STR_LIT> : case <STR_LIT> : { auto * EHPad = getMatchingEHPad ( TI ) ; auto CatchPos = EHPad -> begin ( ) ; if ( CatchPos -> isEHLabel ( ) ) ++ CatchPos ; MachineInstr * Catch = & * CatchPos ; unsigned ExnReg = Catch -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , TI , TI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( ExnReg ) ; TI -> eraseFromParent ( ) ; Changed = true ; break ; } } }


<s> if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> indirect_branch_type = indirect_branch_keep ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> indirect_branch_type = indirect_branch_thunk ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> indirect_branch_type = indirect_branch_thunk_inline ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> indirect_branch_type = indirect_branch_thunk_extern ; else gcc_unreachable ( ) ; } else cfun -> machine -> indirect_branch_type = ix86_indirect_branch ; if ( ( ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC ) && ( ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk_extern ) || ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk ) ) ) error ( <STR_LIT> <STR_LIT> , ( ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk_extern ) ? <STR_LIT> : <STR_LIT> ) ) ; if ( cfun -> machine -> indirect_branch_type != indirect_branch_keep && ( flag_cf_protection & CF_RETURN ) ) error ( <STR_LIT> <STR_LIT> ) ; } if ( cfun -> machine -> function_return_type == indirect_branch_unset ) { tree attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fndecl ) ) ; if ( attr != NULL ) { tree args = TREE_VALUE ( attr ) ; if ( args == NULL ) gcc_unreachable ( ) ; tree cst = TREE_VALUE ( args ) ; if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_keep ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk_inline ; else if ( strcmp ( TREE_STRING_POINTER ( cst ) , <STR_LIT> ) == <NUM_LIT> ) cfun -> machine -> function_return_type = indirect_branch_thunk_extern ; else gcc_unreachable ( ) ; }

else cfun -> machine -> function_return_type = ix86_function_return ;


<s> return ( int16x8_t ) __builtin_neon_vcombinev4hi ( __a , __b ) ;


<s> void <ISA_LIT>RegBankCombinerHelper :: applyMed3 ( MachineInstr & MI , Med3MatchInfo & MatchInfo ) { B . setInstrAndDebugLoc ( MI ) ;

B . buildInstr ( MatchInfo . Opc , { MI . getOperand ( <NUM_LIT> ) } , { MatchInfo . Val0 , MatchInfo . Val1 , MatchInfo . Val2 } , MI . getFlags ( ) ) ;


<s> } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOLoad , useAM3 ) ; if ( needVMOV ) { unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( ResultReg ) ) ; ResultReg = MoveReg ; } return true ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , O ) ;


<s> if ( ! Register :: isVirtualRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return nullptr ; MI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MI ) return nullptr ;


<s> for ( MCRegAliasIterator R ( Reg0 , TRI , true ) ; R . isValid ( ) ; ++ R ) {


<s> <ISA_LIT>Operand ( const <ISA_LIT>Operand & o ) : MCParsedAsmOperand ( ) { Kind = o . Kind ; StartLoc = o . StartLoc ; EndLoc = o . EndLoc ; switch ( Kind ) { case Register : Reg = o . Reg ;


<s> if ( MI . isBranch ( ) && ! MI . isBarrier ( ) ) return true ;


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getLoadLiteralOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ;


<s> HOST_WIDE_INT offset ; if ( from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) offset = info -> push_p ? <NUM_LIT> : - info -> total_size ; else if ( from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { offset = info -> push_p ? <NUM_LIT> : - info -> total_size ; if ( FRAME_GROWS_DOWNWARD ) offset += info -> fixed_size + info -> vars_size + info -> parm_size ; } else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = FRAME_GROWS_DOWNWARD ? info -> fixed_size + info -> vars_size + info -> parm_size : <NUM_LIT> ; else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) offset = info -> total_size ; else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) offset = info -> push_p ? info -> total_size : <NUM_LIT> ; else if ( from == RS6000_PIC_OFFSET_TABLE_REGNUM ) offset = <NUM_LIT> ; else gcc_unreachable ( ) ;


<s> default : return false ; case <STR_LIT> :: MxPCD32 : case <STR_LIT> :: MxPCD16 : case <STR_LIT> :: MxPCD8 : case <STR_LIT> :: MxPCI32 :


<s> unsigned getSGPRSetID ( ) const { return SGPRSetID ;


<s> unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( RHS ) return false ; ShReg = N . getOperand ( <NUM_LIT> ) ;

if ( CheckProfitability && ! isShifterOpProfitable ( N , ShOpcVal , ShImmVal ) ) return false ;


<s> void pru_function_profiler ( FILE * file , int labelno ATTRIBUTE_UNUSED ) {


return ( __m128 ) __builtin_ia32_vbcstnesh2ps128 ( ( const _Float16 * ) __P ) ;


<s> void addu10_0ExtOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N ) ;


<s> virtual const InstrItineraryData * getInstrItineraryData ( ) const {


<s> const struct cpu_cost_table * extra_cost = current_tune -> insn_extra_cost ; rtx_code code = GET_CODE ( x ) ; gcc_assert ( code == UNSPEC || code == UNSPEC_VOLATILE ) ; switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_UNALIGNED_LOAD : * cost = COSTS_N_INSNS ( ARM_NUM_REGS ( GET_MODE ( x ) ) ) ; if ( speed_p ) * cost += ( ARM_NUM_REGS ( GET_MODE ( x ) ) * extra_cost -> ldst . load + extra_cost -> ldst . load_unaligned ) ; * cost += arm_address_cost ( XEXP ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , GET_MODE ( x ) , ADDR_SPACE_GENERIC , speed_p ) ; return true ; case UNSPEC_UNALIGNED_STORE : * cost = COSTS_N_INSNS ( ARM_NUM_REGS ( GET_MODE ( x ) ) ) ; if ( speed_p ) * cost += ( ARM_NUM_REGS ( GET_MODE ( x ) ) * extra_cost -> ldst . store + extra_cost -> ldst . store_unaligned ) ; * cost += rtx_cost ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , VOIDmode , UNSPEC , <NUM_LIT> , speed_p ) ; * cost += arm_address_cost ( XEXP ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , GET_MODE ( x ) , ADDR_SPACE_GENERIC , speed_p ) ; return true ; case UNSPEC_VRINTZ : case UNSPEC_VRINTP : case UNSPEC_VRINTM : case UNSPEC_VRINTR : case UNSPEC_VRINTX : case UNSPEC_VRINTA : if ( speed_p ) * cost += extra_cost -> fp [ GET_MODE ( x ) == DFmode ] . roundint ; return true ; default : * cost = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; } return true ;


<s> return Fn . getFrameInfo ( ) -> hasStackObjects ( ) ;


<s> for ( MachineBasicBlock :: const_succ_iterator si = MBB -> succ_begin ( ) , se = MBB -> succ_end ( ) ; si != se ; ++ si ) { if ( ! visited . count ( * si ) ) { dfs ( * si ) ; } else if ( ! finished . count ( * si ) ) {

if ( ! DT . dominates ( * si , MBB ) ) {


<s> if ( MemOp . OuterDisp -> evaluateAsAbsolute ( Res ) ) return isInt < N > ( Res ) ; return true ; }


<s> bool MadeChange = false ; if ( Buckets . empty ( ) ) return MadeChange ; SmallSet < BasicBlock * , <NUM_LIT> > BBChanged ; for ( auto & Bucket : Buckets ) if ( prepareBaseForUpdateFormChain ( Bucket ) ) MadeChange |= rewriteLoadStores ( L , Bucket , BBChanged , UpdateForm ) ; if ( MadeChange ) for ( auto * BB : BBChanged ) DeleteDeadPHIs ( BB ) ;


while ( Pos < Vec . size ( ) ) EmitByte ( <STR_LIT> :: UNWIND_OPCODE_FINISH ) ;


<s> int Src0Idx = <STR_LIT> ( <STR_LIT> , <STR_LIT> :: src0 ) ; UnCondBrIter = I ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( ! AllowModify ) { TBB = I -> getOperand ( Src0Idx ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( Src0Idx ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( Src0Idx ) . getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { int Src0Idx = <STR_LIT> ( <STR_LIT> , <STR_LIT> :: src0 ) ; int Src1Idx = <STR_LIT> ( <STR_LIT> , <STR_LIT> :: src1 ) ; FBB = TBB ; TBB = I -> getOperand ( Src1Idx ) . getMBB ( ) ; Cond . push_back ( I -> getOperand ( Src0Idx ) ) ; if ( DisableCondReversion ) { Cond . push_back ( MachineOperand :: CreateImm ( COND_IRREVERSIBLE ) ) ; continue ; } unsigned reg = I -> getOperand ( Src0Idx ) . getReg ( ) ; bool can_reverse = false ; bool is_def_before_use = IsDefBeforeUse ( MBB , reg , MRI , can_reverse ) ; if ( can_reverse ) { can_reverse = ! IsSpilledAfterDef ( I , reg ) ; } if ( ! can_reverse ) { Cond . push_back ( MachineOperand :: CreateImm ( COND_IRREVERSIBLE ) ) ; continue ; } if ( is_def_before_use ) { Cond . push_back ( MachineOperand :: CreateImm ( COND_REVERSE_POSITIVE ) ) ; continue ; } if ( ! MRI . tracksLiveness ( ) ) { Cond . push_back ( MachineOperand :: CreateImm ( COND_IRREVERSIBLE ) ) ; continue ; } unsigned free_reg = <NUM_LIT> ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Cond [ <NUM_LIT> ] . getReg ( ) ) ) { RS -> enterBasicBlock ( & MBB ) ; RS -> forward ( std :: prev ( MBB . end ( ) ) ) ; free_reg = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( free_reg == <NUM_LIT> ) { Cond . push_back ( MachineOperand :: CreateImm ( COND_IRREVERSIBLE ) ) ; continue ;


<s> if ( ( Cmp & L ) || ( Cmp & G ) ) return ( Kind ) ( Cmp ^ ( L | G ) ) ;


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : case 'd' : switch ( VT . SimpleTy ) { case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default : break ; } break ; case 'a' : switch ( VT . SimpleTy ) { case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default : break ; } break ;


<s> if ( res < <NUM_LIT> && warn_psabi ) inform ( input_location , <STR_LIT> <STR_LIT> , type ) ; return res > <NUM_LIT> ? DOUBLEWORD_ALIGNMENT : PARM_BOUNDARY ;


<s> default : abort ( ) ; case ABI_AIX : ret = ( TARGET_32BIT ) ? <NUM_LIT> : <NUM_LIT> ;


<s> unsigned Rn = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned type = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned U = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; <STR_LIT> ShOp = <STR_LIT> ; switch ( type ) { case <NUM_LIT> : ShOp = <STR_LIT> ; break ; case <NUM_LIT> : ShOp = <STR_LIT> ; break ; case <NUM_LIT> : ShOp = <STR_LIT> ; break ;


<s> return ( Size <= ( Subtarget -> isMClass ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ? AtomicExpansionKind :: LLSC : AtomicExpansionKind :: None ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } MCSection * ELFSection = getContext ( ) . getELFSection ( Section , Type , ELF :: SHF_WRITE | ELF :: SHF_ALLOC | ELF :: SHF_MIPS_GPREL ) ;

getParser ( ) . getStreamer ( ) . SwitchSection ( ELFSection ) ;


<s> return ( __m128d ) __builtin_ia32_getexppd128_mask ( ( __v2df ) __A , ( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> assert ( Idx == <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: vaddr ) && <STR_LIT> ) ;


<s> State . SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; } } if ( State . I < State . SaveCount ) { assert ( State . I < State . MaxSaved && <STR_LIT> ) ; State . Saved [ State . I ++ ] = Inst ; if ( State . I < State . SaveCount ) return true ; } assert ( State . I == State . SaveCount && State . SaveCount > <NUM_LIT> && <STR_LIT> ) ; State . RecursiveCall = true ; switch ( State . Saved [ <NUM_LIT> ] . getOpcode ( ) ) { default : break ; case <STR_LIT> : EmitDataMask ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : EmitDirectGuardCall ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitIndirectGuardCall ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitIndirectGuardJmp ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitGuardReturn ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitGuardLoadOrStore ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitGuardLoadOrStoreTst ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitGuardSpLoad ( State . I , State . Saved , Out ) ; break ;


<s> void <ISA_LIT>ELFStreamer :: emitLabel ( MCSymbol * Symbol , SMLoc Loc ) { LastLabel = Symbol ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> MCStreamer * S = createELFStreamer ( Context , MAB , OS , Emitter , RelaxAll ) ; new <ISA_LIT>TargetELFStreamer ( * S ) ; return S ;


<s> AU . addPreserved < SlotIndexes > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> MBBInfo ( ) : Address ( <NUM_LIT> ) , Size ( <NUM_LIT> ) , Alignment ( <NUM_LIT> ) , NumTerminators ( <NUM_LIT> ) {


<s> create_fixed_operand ( & m_ops . last ( ) , x ) ;


<s> if ( type && INTEGRAL_TYPE_P ( type ) ) mode = arm_promote_function_mode ( type , mode , & unsignedp , fntype , <NUM_LIT> ) ; if ( pcs_variant != ARM_PCS_AAPCS ) { int i ; for ( i = <NUM_LIT> ; i < ARM_NUM_COPROC_SLOTS ; i ++ ) if ( aapcs_cp_arg_layout [ i ] . is_return_candidate ( pcs_variant , mode , type ) ) return aapcs_cp_arg_layout [ i ] . allocate_return_reg ( pcs_variant , mode , type ) ; } if ( type && arm_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size % UNITS_PER_WORD != <NUM_LIT> ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = int_mode_for_size ( size * BITS_PER_UNIT , <NUM_LIT> ) . require ( ) ;


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ;


<s> static int const_costs_int ( HOST_WIDE_INT value , int zero_cost ) { if ( CONST_OK_FOR_I ( value ) ) return zero_cost ; else if ( CONST_OK_FOR_J ( value ) ) return <NUM_LIT> ; else if ( CONST_OK_FOR_K ( value ) ) return <NUM_LIT> ;


<s> void SVEIntrinsicOpts :: getAnalysisUsage ( AnalysisUsage & AU ) const {

AU . addRequired < DominatorTreeWrapperPass > ( ) ;


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( & NewDestBB ) ; return ;


<s> <ISA_LIT>16InstrInfo :: <ISA_LIT>16InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>InstrInfo ( STI , <STR_LIT> ) , RI ( ) {


<s> I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = getOppositeCondition ( BranchCode ) ; unsigned JNCC = getBrCond ( BranchCode ) . getOpcode ( ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ;


<s> unsigned VecWidth = VecTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) ; if ( useHVX ( ) && isTypeForHVX ( VecTy ) ) { unsigned RegWidth = getRegisterBitWidth ( true ) ; assert ( RegWidth && <STR_LIT> ) ; if ( VecWidth % RegWidth == <NUM_LIT> ) return VecWidth / RegWidth ; const Align RegAlign ( RegWidth / <NUM_LIT> ) ; if ( ! Alignment || * Alignment > RegAlign ) Alignment = RegAlign ; assert ( Alignment ) ; unsigned AlignWidth = <NUM_LIT> * Alignment -> value ( ) ; unsigned NumLoads = alignTo ( VecWidth , AlignWidth ) / AlignWidth ; return <NUM_LIT> * NumLoads ; } unsigned Cost = VecTy -> getElementType ( ) -> isFloatingPointTy ( ) ? FloatFactor : <NUM_LIT> ; const Align BoundAlignment = std :: min ( Alignment . valueOrOne ( ) , Align ( <NUM_LIT> ) ) ; unsigned AlignWidth = <NUM_LIT> * BoundAlignment . value ( ) ;


<s> return PerformShiftCombine ( N , DCI , getSubtarget ( ) ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= <NUM_LIT> ) emit_window_save ( size_int_rtx ) ; else if ( size <= <NUM_LIT> ) { emit_window_save ( GEN_INT ( - <NUM_LIT> ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; emit_window_save ( size_rtx ) ; } } if ( sparc_leaf_function_p ) { sparc_frame_base_reg = stack_pointer_rtx ; sparc_frame_base_offset = size + SPARC_STACK_BIAS ; } else {


<s> if ( ASSEMBLER_DIALECT == ASM_ATT ) { if ( disp ) { if ( flag_pic ) output_pic_addr_const ( file , disp , <NUM_LIT> ) ; else if ( GET_CODE ( disp ) == LABEL_REF ) output_asm_label ( disp ) ; else output_addr_const ( file , disp ) ; } putc ( '(' , file ) ; if ( base ) print_reg ( base , code , file ) ; if ( index ) { putc ( ',' , file ) ; print_reg ( index , vsib ? <NUM_LIT> : code , file ) ; if ( scale != <NUM_LIT> || vsib ) fprintf ( file , <STR_LIT> , scale ) ; } putc ( ')' , file ) ; } else { rtx offset = NULL_RTX ; if ( disp ) { if ( GET_CODE ( disp ) == CONST && GET_CODE ( XEXP ( disp , <NUM_LIT> ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) ) ) { offset = XEXP ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) ; disp = gen_rtx_CONST ( VOIDmode , XEXP ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) ) ; } if ( flag_pic ) output_pic_addr_const ( file , disp , <NUM_LIT> ) ; else if ( GET_CODE ( disp ) == LABEL_REF ) output_asm_label ( disp ) ; else if ( CONST_INT_P ( disp ) ) offset = disp ; else output_addr_const ( file , disp ) ; } putc ( '[' , file ) ; if ( base ) { print_reg ( base , code , file ) ; if ( offset ) { if ( INTVAL ( offset ) >= <NUM_LIT> ) putc ( '+' , file ) ; fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( offset ) ) ; } } else if ( offset ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( offset ) ) ; else putc ( '0' , file ) ; if ( index ) { putc ( '+' , file ) ; print_reg ( index , vsib ? <NUM_LIT> : code , file ) ; if ( scale != <NUM_LIT> || vsib ) fprintf ( file , <STR_LIT> , scale ) ; } putc ( ']' , file ) ; }


<s> case <STR_LIT> : { if ( tryInlineAsm ( N ) ) return ; break ; } case <STR_LIT> : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) break ; SDValue DivLHS = N -> getOperand ( <NUM_LIT> ) ; SDValue DivRHS = N -> getOperand ( <NUM_LIT> ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == <STR_LIT> ) { TopPart = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , DivLHS , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , <NUM_LIT> ) ; } else { TopPart = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } TopPart = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , dl , <STR_LIT> , TopPart , SDValue ( ) ) . getValue ( <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opcode , <STR_LIT> , DivLHS , DivRHS , TopPart ) ;


<s> Tile64SelectionDAGInfo :: ~ Tile64SelectionDAGInfo ( ) {


<s> if ( FnSecName != <STR_LIT> ) { EHSecName += FnSecName ; } const MCSectionELF * EHSection = nullptr ; if ( const MCSymbol * Group = FnSection . getGroup ( ) ) { EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags | ELF :: SHF_GROUP , FnSection . getEntrySize ( ) , Group -> getName ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : return true ; default : return false ;


<s> GCNTargetMachine :: GCNTargetMachine ( const Target & T , StringRef TT , StringRef FS , StringRef CPU , TargetOptions Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) :

AMDGPUTargetMachine ( T , TT , FS , CPU , Options , RM , CM , OL ) {


<s> <ISA_LIT>HazardSchedule ( ) : MachineFunctionPass ( ID ) {


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: Naked ) ) { return Chain ; }


<s> if ( flag_pic && cfun -> machine -> pic_reg ) { rtx pic_reg = cfun -> machine -> pic_reg ; insn = emit_insn ( gen_load_pic_offset ( pic_reg , scratch_reg_0 ) ) ; insn = emit_insn ( gen_subsi3 ( pic_reg , pic_reg , scratch_reg_0 ) ) ; } if ( total_size > <NUM_LIT> ) { if ( flag_stack_check ) { rtx scratch_v4si = gen_rtx_REG ( V4SImode , REGNO ( scratch_reg_0 ) ) ; rtx sp_v4si = gen_rtx_REG ( V4SImode , STACK_POINTER_REGNUM ) ; rtx size_v4si = spu_const ( V4SImode , total_size - <NUM_LIT> ) ; if ( ! satisfies_constraint_K ( GEN_INT ( total_size - <NUM_LIT> ) ) ) { emit_move_insn ( scratch_v4si , size_v4si ) ; size_v4si = scratch_v4si ; } emit_insn ( gen_cgt_v4si ( scratch_v4si , sp_v4si , size_v4si ) ) ; emit_insn ( gen_vec_extractv4si ( scratch_reg_0 , scratch_v4si , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_spu_heq ( scratch_reg_0 , GEN_INT ( <NUM_LIT> ) ) ) ; } if ( total_size <= <NUM_LIT> ) { insn = frame_emit_store ( STACK_POINTER_REGNUM , sp_reg , - total_size ) ; insn = frame_emit_add_imm ( sp_reg , sp_reg , - total_size , scratch_reg_0 ) ; } else { insn = emit_move_insn ( scratch_reg_0 , sp_reg ) ; insn = frame_emit_add_imm ( sp_reg , sp_reg , - total_size , scratch_reg_1 ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; real = gen_addsi3 ( sp_reg , sp_reg , GEN_INT ( - total_size ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , real ) ; if ( total_size > <NUM_LIT> ) { insn = frame_emit_store ( REGNO ( scratch_reg_0 ) , sp_reg , <NUM_LIT> ) ; } if ( frame_pointer_needed ) { rtx fp_reg = gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ; HOST_WIDE_INT fp_offset = STACK_POINTER_OFFSET + crtl -> outgoing_args_size ; insn = frame_emit_add_imm ( fp_reg , sp_reg , fp_offset , scratch_reg_0 ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; real = gen_addsi3 ( fp_reg , sp_reg , GEN_INT ( fp_offset ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , real ) ; REGNO_POINTER_ALIGN ( HARD_FRAME_POINTER_REGNUM ) = STACK_BOUNDARY ; }


<s> static bool inline isImm3 ( int64_t I ) { return isUInt < <NUM_LIT> > ( I ) ;


<s> CCInfo . AnalyzeCallResult ( TheCall , RetCC_<ISA_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > ResultVals ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) {

Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ;


<s> default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> return ( int32x2_t ) __builtin_neon_vshlsv2si ( __a , __b ) ;


<s> void addImmCom8Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const auto * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( ~ ( uint8_t ) CE -> getValue ( ) ) ) ;


<s> return selectMVIAddr ( <STR_LIT> , Addr , Base , Disp ) ;


<s> Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;

Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;


<s> static rtx nds32_dwarf_register_span ( rtx reg ) { rtx dwarf_high , dwarf_low ; rtx dwarf_single ; machine_mode mode ; int regno ; mode = GET_MODE ( reg ) ; regno = REGNO ( reg ) ; if ( regno >= NDS32_FIRST_FPR_REGNUM && regno <= NDS32_LAST_FPR_REGNUM ) { if ( mode == DFmode || mode == SCmode ) { dwarf_high = gen_rtx_REG ( word_mode , regno ) ; dwarf_low = gen_rtx_REG ( word_mode , regno + <NUM_LIT> ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , dwarf_low , dwarf_high ) ) ; } else if ( mode == DCmode ) { rtx dwarf_high_re = gen_rtx_REG ( word_mode , regno ) ; rtx dwarf_low_re = gen_rtx_REG ( word_mode , regno + <NUM_LIT> ) ; rtx dwarf_high_im = gen_rtx_REG ( word_mode , regno ) ; rtx dwarf_low_im = gen_rtx_REG ( word_mode , regno + <NUM_LIT> ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , dwarf_low_re , dwarf_high_re , dwarf_high_im , dwarf_low_im ) ) ; } else if ( mode == SFmode || mode == SImode ) { dwarf_single = gen_rtx_REG ( word_mode , regno ) ; return gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , dwarf_single ) ) ; }


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ; return ;


<s> } if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI -> hasOneNonDBGUse ( SrcReg ) ) continue ; MI2 = MRI -> getVRegDef ( SrcReg ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MI2 || MI2 -> getOpcode ( ) != <STR_LIT> || MI2 -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) continue ; SrcReg = MI2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( DefMI ) TruncSize = <NUM_LIT> ; } else if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DefMI = MRI -> getVRegDef ( SrcReg ) ; if ( ! DefMI ) continue ; int64_t imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; else if ( imm == <NUM_LIT> ) TruncSize = <NUM_LIT> ; } if ( TruncSize == - <NUM_LIT> ) continue ;


<s> uint64_t Init = <NUM_LIT> ; for ( MachineInstr & I : MRI -> def_instructions ( Reg ) ) { if ( I . getOpcode ( ) != <STR_LIT> || I . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg || ! I . getOperand ( <NUM_LIT> ) . isImm ( ) || I . getNumOperands ( ) != <NUM_LIT> ) return false ; switch ( I . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) { default : return false ; case <STR_LIT> : if ( Def0 ) return false ; Def0 = & I ; Init |= I . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ; break ; case <STR_LIT> : if ( Def1 ) return false ; Def1 = & I ; Init |= static_cast < uint64_t > ( I . getOperand ( <NUM_LIT> ) . getImm ( ) ) << <NUM_LIT> ; break ; } } if ( ! Def0 || ! Def1 || Def0 -> getParent ( ) != Def1 -> getParent ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Def0 << <STR_LIT> << * Def1 << <STR_LIT> ) ; if ( SlotIndex :: isEarlierInstr ( LIS -> getInstructionIndex ( * Def1 ) , LIS -> getInstructionIndex ( * Def0 ) ) ) std :: swap ( Def0 , Def1 ) ; LIS -> RemoveMachineInstrFromMaps ( * Def0 ) ; LIS -> RemoveMachineInstrFromMaps ( * Def1 ) ; auto NewI = BuildMI ( * Def0 -> getParent ( ) , * Def0 , Def0 -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( Init ) ; Def0 -> eraseFromParent ( ) ; Def1 -> eraseFromParent ( ) ; LIS -> InsertMachineInstrInMaps ( * NewI ) ; LIS -> removeInterval ( Reg ) ; LIS -> createAndComputeVirtRegInterval ( Reg ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * NewI ) ;


<s> PreviousIn<ISA_LIT>16Mode = In<ISA_LIT>16Mode ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>2 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>3 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( <ISA_LIT>ABI != UnknownABI ) ; assert ( ( ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ; assert ( ( ( ! isGP64bit ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; }

if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ;


<s> void aarch64_split_add_offset ( scalar_int_mode mode , rtx dest , rtx src , rtx offset_rtx , rtx temp1 , rtx temp2 ) { aarch64_add_offset ( mode , dest , src , rtx_to_poly_int64 ( offset_rtx ) , temp1 , temp2 , false ) ;


<s> if ( Op . isImm ( ) ) O << ( int ) Op . getImm ( ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectArithImmed ( MachineOperand & Root ) const {

auto MaybeImmed = getImmedFromMO ( Root ) ;


<s> size_type size ( ) const { return V . size ( ) ;


<s> if ( LoopMap . count ( ML ) ) return LoopMap [ ML ] . get ( ) ; LoopMap [ ML ] = std :: make_unique < ConcreteRegion < MachineLoop >> ( ML ) ; return LoopMap [ ML ] . get ( ) ; } else { if ( ExceptionMap . count ( WE ) ) return ExceptionMap [ WE ] . get ( ) ; ExceptionMap [ WE ] = std :: make_unique < ConcreteRegion < <ISA_LIT>Exception >> ( WE ) ;


<s> void CFGStructurizer < PassT > :: removeUnconditionalBranch ( BlockT * srcBlk ) { InstrT * branchInstr ; while ( ( branchInstr = CFGTraits :: getLoopendBlockBranchInstr ( srcBlk ) ) && CFGTraits :: isUncondBranch ( branchInstr ) ) { if ( DEBUGME ) { errs ( ) << <STR_LIT> ;


<s> bool generateCompositeMacros ( ) const override { return true ;


<s> explicit FPMover ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) {


<s> const MCExpr * <ISA_LIT>TargetLowering :: LowerCustomJumpTableEntry ( const MachineJumpTableInfo * MJTI , const MachineBasicBlock * MBB , unsigned uid , MCContext & Ctx ) const { assert ( MBB -> getParent ( ) -> getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ && Subtarget -> isPICStyleGOT ( ) ) ;

return MCSymbolRefExpr :: Create ( MBB -> getSymbol ( ) , MCSymbolRefExpr :: VK_GOTOFF , Ctx ) ;


<s> SDValue Op1 = U -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( Op1 ) ) { if ( Imm -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) return false ; if ( U -> getOpcode ( ) == <STR_LIT> && Imm -> getAPIntValue ( ) . getBitWidth ( ) == <NUM_LIT> && Imm -> getAPIntValue ( ) . isIntN ( <NUM_LIT> ) ) return false ; } if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SDValue Val = Op1 . getOperand ( <NUM_LIT> ) ; if ( Val . getOpcode ( ) == <STR_LIT> ) return false ; } if ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) { if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isOneConstant ( U -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) return false ; if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isOneConstant ( U -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) return false ; } if ( U -> getOpcode ( ) == <STR_LIT> ) { SDValue U0 = U -> getOperand ( <NUM_LIT> ) ; SDValue U1 = U -> getOperand ( <NUM_LIT> ) ; if ( U0 . getOpcode ( ) == <STR_LIT> ) { auto * C = dyn_cast < ConstantSDNode > ( U0 . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getSExtValue ( ) == - <NUM_LIT> ) return false ; } if ( U1 . getOpcode ( ) == <STR_LIT> ) { auto * C = dyn_cast < ConstantSDNode > ( U1 . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getSExtValue ( ) == - <NUM_LIT> ) return false ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isa < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) ) return false ;


<s> GISelChangeObserver & Observer = Helper . Observer ; Observer . changingInstr ( MI ) ; MI . setDesc ( ST . getInstrInfo ( ) -> get ( getDSFPAtomicOpcode ( IID ) ) ) ; for ( int I = <NUM_LIT> ; I > <NUM_LIT> ; -- I ) MI . RemoveOperand ( I ) ; MI . RemoveOperand ( <NUM_LIT> ) ; Observer . changedInstr ( MI ) ; return true ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>32 ) ; for ( unsigned I = <NUM_LIT> ; I != RVLocs . size ( ) ; ++ I ) { Chain = DAG . getCopyFromReg ( Chain , DL , RVLocs [ I ] . getLocReg ( ) , RVLocs [ I ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;

InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ;


<s> case 'x' : case 'X' : case 'y' : case 'Y' : case 'z' : case 'Z' : return C_Register ; case 'Q' : return C_Memory ; case 'G' : case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : case 'R' : return C_Other ; default : break ; }


<s> virtual const Tile64TargetLowering * getTargetLowering ( ) const {


<s> bool isImm ( ) const override { return Kind == Integer || Kind == Symbol ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ;

CCState CCInfo ( CallConv , isVarArg , MF , getTargetMachine ( ) , RVLocs , Context ) ;


<s> if ( ( SignedDivRem || UnsignedDivRem ) && Args . size ( ) == <NUM_LIT> ) { if ( const Constant * C = dyn_cast < Constant > ( Args [ <NUM_LIT> ] ) ) { const ConstantInt * CVal = ( C -> getType ( ) -> isVectorTy ( ) ? dyn_cast_or_null < const ConstantInt > ( C -> getSplatValue ( ) ) : dyn_cast < const ConstantInt > ( C ) ) ; if ( CVal != nullptr && ( CVal -> getValue ( ) . isPowerOf2 ( ) || ( - CVal -> getValue ( ) ) . isPowerOf2 ( ) ) ) DivRemConstPow2 = true ; else DivRemConst = true ; } } if ( Ty -> isVectorTy ( ) ) { assert ( ST -> hasVector ( ) && <STR_LIT> ) ; unsigned VF = Ty -> getVectorNumElements ( ) ; unsigned NumVectors = getNumVectorRegs ( Ty ) ; if ( Opcode == Instruction :: Shl || Opcode == Instruction :: LShr || Opcode == Instruction :: AShr ) { return NumVectors ; } if ( DivRemConstPow2 ) return ( NumVectors * ( SignedDivRem ? SDivPow2Cost : <NUM_LIT> ) ) ; if ( DivRemConst ) return VF * DivMulSeqCost + getScalarizationOverhead ( Ty , Args ) ; if ( ( SignedDivRem || UnsignedDivRem ) && VF > <NUM_LIT> ) return <NUM_LIT> ;

if ( Opcode == Instruction :: FAdd || Opcode == Instruction :: FSub || Opcode == Instruction :: FMul || Opcode == Instruction :: FDiv ) {


<s> struct riscv_integer_op codes [ RISCV_MAX_INTEGER_OPS ] ; return MIN ( riscv_build_integer ( codes , val , VOIDmode ) , riscv_split_integer_cost ( val ) ) ;


<s> bool <ISA_LIT>HardwareLoops :: runOnMachineFunction ( MachineFunction & MF ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( skipFunction ( MF . getFunction ( ) ) ) return false ; bool Changed = false ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; const <ISA_LIT>Subtarget & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = HST . getInstrInfo ( ) ; TRI = HST . getRegisterInfo ( ) ; for ( auto & L : * MLI ) if ( ! L -> getParentLoop ( ) ) { bool L0Used = false ; bool L1Used = false ; Changed |= convertToHardwareLoop ( L , L0Used , L1Used ) ;


<s> if ( ! TARGET_ARCH_R2 ) { if ( TARGET_HAS_BMX ) error ( <STR_LIT> ) ; if ( TARGET_HAS_CDX ) error ( <STR_LIT> ) ; } if ( TARGET_ARCH_R2 && TARGET_BIG_ENDIAN ) error ( <STR_LIT> ) ; nios2_init_fpu_configs ( ) ; if ( nios2_custom_fpu_cfg_string && * nios2_custom_fpu_cfg_string ) nios2_handle_custom_fpu_cfg ( nios2_custom_fpu_cfg_string , NULL , false ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( nios2_fpu_insn ) ; i ++ ) nios2_handle_custom_fpu_insn_option ( i ) ; nios2_custom_check_insns ( ) ; target_option_default_node = target_option_current_node = build_target_option_node ( & global_options ) ;


<s> static DecodeStatus DecodeAddiGroupBranch ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) {


<s> static std :: pair < unsigned , const TargetRegisterClass * > parseRegisterNumber ( StringRef Constraint , const TargetRegisterClass * RC , const unsigned * Map ) {

assert ( * ( Constraint . end ( ) - <NUM_LIT> ) == '}' && <STR_LIT> ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>FixupSetCC ( ) {

return new <ISA_LIT>FixupSetCCPass ( ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> EVT VT = N0 . getValueType ( ) ; if ( ! VT . isScalableVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> || ! isNullConstant ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( ! isPredicateCCSettingOp ( N0 ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Pg = getPTrue ( DAG , SDLoc ( N ) , VT , <STR_LIT> ) ; return getPTest ( DAG , N -> getValueType ( <NUM_LIT> ) , Pg , N0 , <STR_LIT> ) ;


<s> return PredictableSelectIsExpensive ;


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> removeDeadFrameIndices ( MFI ) ; assert ( allSGPRSpillsAreDead ( MFI , None , None ) && <STR_LIT> ) ; if ( ! allStackObjectsAreDead ( MFI ) ) { assert ( RS && <STR_LIT> ) ; if ( FuncInfo -> isEntryFunction ( ) ) { int ScavengeFI = MFI . CreateFixedObject ( TRI -> getSpillSize ( <STR_LIT> ) , <NUM_LIT> , false ) ; RS -> addScavengingFrameIndex ( ScavengeFI ) ; } else { int ScavengeFI = MFI . CreateStackObject ( TRI -> getSpillSize ( <STR_LIT> ) , TRI -> getSpillAlign ( <STR_LIT> ) , false ) ; RS -> addScavengingFrameIndex ( ScavengeFI ) ;


<s> S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Dollar : case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . parseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( CE ) { int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: Create ( INT32_MIN , getContext ( ) ) ; } E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Parser . getTok ( ) . getString ( ) , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; } return false ; } } case AsmToken :: Colon : { <ISA_LIT>MCExpr :: VariantKind RefKind ; if ( parsePrefix ( RefKind ) ) return true ; const MCExpr * SubExprVal ; if ( getParser ( ) . parseExpression ( SubExprVal ) ) return true ; const MCExpr * ExprVal = <ISA_LIT>MCExpr :: Create ( RefKind , SubExprVal , getContext ( ) ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ExprVal , S , E ) ) ;


<s> void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override {


<s> AU . addRequired < MachineDominatorTree > ( ) ;

AU . addPreserved < MachineDominatorTree > ( ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , unsigned , bool * Fast ) const { if ( Disable<ISA_LIT>Unaligned ) return false ; if ( ! VT . isSimple ( ) ) return false ;

if ( VT . getSimpleVT ( ) . isVector ( ) ) {


<s> static HOST_WIDE_INT sparc_gcov_type_size ( void ) {


<s> SmallBitVector Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; unsigned ZMask = <NUM_LIT> ; int V1DstIndex = - <NUM_LIT> ; int V2DstIndex = - <NUM_LIT> ; bool V1UsedInPlace = false ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( Zeroable [ i ] ) { ZMask |= <NUM_LIT> << i ; continue ; } if ( i == Mask [ i ] ) { V1UsedInPlace = true ; continue ; } if ( V1DstIndex != - <NUM_LIT> || V2DstIndex != - <NUM_LIT> ) return SDValue ( ) ; if ( Mask [ i ] < <NUM_LIT> ) { V1DstIndex = i ; } else { V2DstIndex = i ; } } if ( V1DstIndex == - <NUM_LIT> && V2DstIndex == - <NUM_LIT> ) return SDValue ( ) ; unsigned V2SrcIndex = <NUM_LIT> ; if ( V1DstIndex != - <NUM_LIT> ) { V2SrcIndex = Mask [ V1DstIndex ] ; V2DstIndex = V1DstIndex ; V2 = V1 ; } else { V2SrcIndex = Mask [ V2DstIndex ] - <NUM_LIT> ; } if ( ! V1UsedInPlace ) V1 = DAG . getUNDEF ( <STR_LIT> ) ; unsigned InsertPSMask = V2SrcIndex << <NUM_LIT> | V2DstIndex << <NUM_LIT> | ZMask ;

assert ( ( InsertPSMask & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ;


<s> addSavedGPR ( MBB , MIB , LowGPR , false ) ; addSavedGPR ( MBB , MIB , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) addSavedGPR ( MBB , MIB , Reg , true ) ; } if ( IsVarArg ) for ( unsigned I = ZFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) addSavedGPR ( MBB , MIB , <STR_LIT> [ I ] , true ) ; } for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { unsigned Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) {


<s> } SmallVectorImpl < PredicatedMI > & Insts = Block . getInsts ( ) ; for ( auto & PredMI : Insts ) { if ( PredMI . Predicates . count ( VCTP ) || isVCTP ( PredMI . MI ) || VCMPOpcodeToVPT ( PredMI . MI -> getOpcode ( ) ) != <NUM_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * PredMI . MI << <STR_LIT> ; for ( auto * MI : PredMI . Predicates ) dbgs ( ) << <STR_LIT> << * MI ) ; return false ; } } if ( ! ValidateLiveOuts ( ) ) return false ; Register NumElements = VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RDA . hasLocalDefBefore ( VCTP , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineBasicBlock * InsertBB = StartInsertPt -> getParent ( ) ; if ( ! RDA . isReachingDefLiveOut ( StartInsertPt , NumElements ) ) { if ( auto * ElemDef = RDA . getLocalLiveOutMIDef ( InsertBB , NumElements ) ) { if ( RDA . isSafeToMoveForwards ( ElemDef , StartInsertPt ) ) { ElemDef -> removeFromParent ( ) ; InsertBB -> insert ( MachineBasicBlock :: iterator ( StartInsertPt ) , ElemDef ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else if ( RDA . isSafeToMoveBackwards ( StartInsertPt , ElemDef ) ) { StartInsertPt -> removeFromParent ( ) ; InsertBB -> insertAfter ( MachineBasicBlock :: iterator ( ElemDef ) , StartInsertPt ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ElemDef ) ; } else {

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ;


<s> rtx prev = NULL_RTX ; for ( insn = get_insns ( ) ; insn ; insn = ninsn ) { rtx set ; ninsn = next_nonnote_nondebug_insn ( insn ) ; if ( ( set = single_set ( insn ) ) == NULL_RTX ) { prev = NULL_RTX ; continue ; } if ( prev && rtx_equal_p ( SET_DEST ( prev ) , SET_SRC ( set ) ) && rtx_equal_p ( SET_DEST ( set ) , SET_SRC ( prev ) ) && ! volatile_refs_p ( SET_SRC ( prev ) ) && ! volatile_refs_p ( SET_DEST ( prev ) ) && ! volatile_refs_p ( SET_SRC ( set ) ) && ! volatile_refs_p ( SET_DEST ( set ) ) ) {

if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( insn ) ) ;