<s> bool <ISA_LIT>ElimCompare :: adjustCCMasksForInstr ( MachineInstr & MI , MachineInstr & Compare , SmallVectorImpl < MachineInstr * > & CCUsers , unsigned ConvOpc ) { unsigned CompareFlags = Compare . getDesc ( ) . TSFlags ; unsigned CompareCCValues = <STR_LIT> ( CompareFlags ) ; int Opcode = ( ConvOpc ? ConvOpc : MI . getOpcode ( ) ) ; const MCInstrDesc & Desc = TII -> get ( Opcode ) ; unsigned MIFlags = Desc . TSFlags ; if ( Compare . mayRaiseFPException ( ) ) { if ( ConvOpc && ! Desc . mayRaiseFPException ( ) ) return false ; if ( ! ConvOpc && ! MI . mayRaiseFPException ( ) ) return false ; } unsigned CCValues = <STR_LIT> ( MIFlags ) ; unsigned ReusableCCMask = CCValues ; if ( CompareFlags & <STR_LIT> ) ReusableCCMask &= <STR_LIT> ; unsigned OFImplies = <NUM_LIT> ; bool LogicalMI = false ; bool MIEquivalentToCmp = false ; if ( MI . getFlag ( MachineInstr :: NoSWrap ) && ( MIFlags & <STR_LIT> ) ) { } else if ( ( MIFlags & <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) { assert ( isAddWithImmediate ( Opcode ) && <STR_LIT> ) ; assert ( ! MI . mayLoadOrStore ( ) && <STR_LIT> ) ; int64_t RHS = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <STR_LIT> . contains ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && RHS == INT32_MIN ) return false ; OFImplies = ( RHS > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; } else if ( ( MIFlags & <STR_LIT> ) && CCValues ) {


<s> CUMULATIVE_ARGS next_cum = * get_cumulative_args ( cum ) ; ia64_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , <NUM_LIT> ) ; if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n * UNITS_PER_WORD ;


<s> SDValue V3 = Op . getOperand ( <NUM_LIT> ) ; SDValue V4 = Op . getOperand ( <NUM_LIT> ) ; return Concat256BitVectors ( Concat128BitVectors ( V1 , V2 , HalfVT , NumElems / <NUM_LIT> , DAG , dl ) , Concat128BitVectors ( V3 , V4 , HalfVT , NumElems / <NUM_LIT> , DAG , dl ) , ResVT , NumElems , DAG , dl ) ;


<s> } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ;


<s> if ( TARGET_ABI_OPEN_VMS && arg . end_marker_p ( ) ) { unsigned HOST_WIDE_INT regval = cum -> words ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) regval |= ( ( int ) cum -> atypes [ i ] ) << ( i * <NUM_LIT> + <NUM_LIT> ) ; emit_move_insn ( gen_rtx_REG ( DImode , GR_REG ( <NUM_LIT> ) ) , GEN_INT ( regval ) ) ; } if ( cum -> words + offset >= MAX_ARGUMENT_SLOTS ) return <NUM_LIT> ; if ( TARGET_ABI_OPEN_VMS ) { if ( FLOAT_MODE_P ( arg . mode ) ) return gen_rtx_REG ( arg . mode , FR_ARG_FIRST + cum -> words ) ; else return gen_rtx_REG ( arg . mode , basereg + cum -> words ) ; } if ( arg . type ) hfa_mode = hfa_element_mode ( arg . type , <NUM_LIT> ) ; if ( hfa_mode != VOIDmode && ( ! cum -> prototype || arg . named ) ) { rtx loc [ <NUM_LIT> ] ; int i = <NUM_LIT> ; int fp_regs = cum -> fp_regs ; int int_regs = cum -> words + offset ; int hfa_size = GET_MODE_SIZE ( hfa_mode ) ; int byte_size ; int args_byte_size ; byte_size = arg . promoted_size_in_bytes ( ) ; args_byte_size = int_regs * UNITS_PER_WORD ; offset = <NUM_LIT> ;

for ( ; ( offset < byte_size && fp_regs < MAX_ARGUMENT_SLOTS && args_byte_size < ( MAX_ARGUMENT_SLOTS * UNITS_PER_WORD ) ) ; i ++ ) {


<s> } if ( ( config ( ) . options ( ) . hasNow ( ) && file_format -> hasGOT ( ) ) || file_format -> hasGOTPLT ( ) ) { assert ( m_pGOTPLT != NULL ) ; if ( LinkerConfig :: DynObj == config ( ) . codeGenType ( ) ) m_pGOTPLT -> applyGOT0 ( file_format -> getDynamic ( ) . addr ( ) ) ;


<s> if ( TARGET_MMX ) cum -> mmx_nregs = MMX_REGPARM_MAX ; cum -> warn_sse = true ; cum -> warn_mmx = true ; cum -> maybe_vaarg = false ; if ( fntype && ! TARGET_64BIT ) { if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) { cum -> nregs = <NUM_LIT> ; cum -> fastcall = <NUM_LIT> ; } else cum -> nregs = ix86_function_regparm ( fntype , fndecl ) ; } cum -> float_in_sse = ix86_function_sseregparm ( fntype , fndecl ) ; if ( cum -> nregs || cum -> mmx_nregs || cum -> sse_nregs ) { for ( param = ( fntype ) ? TYPE_ARG_TYPES ( fntype ) : <NUM_LIT> ; param != <NUM_LIT> ; param = next_param ) { next_param = TREE_CHAIN ( param ) ; if ( next_param == <NUM_LIT> && TREE_VALUE ( param ) != void_type_node ) {


<s> if ( ! current_function_saves_lr ( ) && to == long_branch_regnum ) return <NUM_LIT> ;

if ( crtl -> is_leaf && ! df_regs_ever_live_p ( to ) && visium_interrupt_function_p ( ) ) return <NUM_LIT> ;


<s> std :: string CPU = sys :: getHostCPUName ( ) ; ParseSubtargetFeatures ( FS , CPU ) ; if ( HasAVX ) <ISA_LIT>SSELevel = NoMMXSSE ; } else { AutoDetectSubtargetFeatures ( ) ; if ( Is64Bit && ! HasAVX && <ISA_LIT>SSELevel < SSE2 ) <ISA_LIT>SSELevel = SSE2 ; } if ( Is64Bit ) { Has<ISA_LIT>_64 = true ; HasCMov = true ; } DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! Is64Bit || Has<ISA_LIT>_64 ) && <STR_LIT> ) ;

if ( isTargetDarwin ( ) || Is64Bit ) stackAlignment = <NUM_LIT> ;


<s> static uint64_t calculateMaxStackAlign ( const MachineFunction & MF ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; uint64_t MaxAlign = MFI -> getMaxAlignment ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = STI . getRegisterInfo ( ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; unsigned StackAlign = STI . getFrameLowering ( ) -> getStackAlignment ( ) ; if ( ForceStackAlign ) { if ( MFI -> hasCalls ( ) ) MaxAlign = ( StackAlign > MaxAlign ) ? StackAlign : MaxAlign ;

else if ( MaxAlign < SlotSize ) MaxAlign = SlotSize ;


<s> void init_cumulative_args ( struct sparc_args * cum , tree fntype , rtx , tree ) { cum -> words = <NUM_LIT> ; cum -> prototype_p = fntype && prototype_p ( fntype ) ;


<s> if ( ! CS ) return CS ; if ( ( CS . getIntrinsicID ( ) == <STR_LIT> || CS . getIntrinsicID ( ) == <STR_LIT> ) && isa < ConstantInt > ( CS . getArgument ( <NUM_LIT> ) ) && isa < ConstantInt > ( CS . getArgument ( <NUM_LIT> ) ) ) return CS ;


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ;

cum -> nbytes += ( arg . promoted_size_in_bytes ( ) + <NUM_LIT> ) & ~ <NUM_LIT> ;


<s> t . as_short [ <NUM_LIT> ] = permute_selectors [ element_selector_54 ] ; t . as_short [ <NUM_LIT> ] = permute_selectors [ element_selector_76 ] ; t . as_short [ <NUM_LIT> ] = permute_selectors [ element_selector_10 ] ; t . as_short [ <NUM_LIT> ] = permute_selectors [ element_selector_32 ] ; t . as_short [ <NUM_LIT> ] = permute_selectors [ element_selector_54 ] ; t . as_short [ <NUM_LIT> ] = permute_selectors [ element_selector_76 ] ; p = vec_splats ( t . as_m64 ) ; a = vec_splats ( __A ) ; r = vec_perm ( a , a , ( __vector unsigned char ) p ) ; return ( __m64 ) ( ( __vector long long ) r ) [ <NUM_LIT> ] ;


<s> auto IsHazardFn = [ this , Reg , TRI ] ( MachineInstr * MI ) { int DataIdx = createsVALUHazard ( * MI ) ; return DataIdx >= <NUM_LIT> && TRI -> regsOverlap ( MI -> getOperand ( DataIdx ) . getReg ( ) , Reg ) ; } ;

int WaitStatesNeededForDef = VALUWaitStates - getWaitStatesSince ( IsHazardFn ) ;


<s> if ( RegNo >= <NUM_LIT> || RegNo & <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ;

Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , VarArgsFrameIndex ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : break ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBIT_CONVERT ( Op . getNode ( ) , DAG ) ; case <STR_LIT> :


<s> <ISA_LIT>COFFMCAsmInfoMicrosoft :: <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) {


<s> else return ( ( TYPE_MODE ( type ) == BLKmode && ( unsigned HOST_WIDE_INT ) int_size_in_bytes ( type ) > <NUM_LIT> ) ) ;


<s> if ( findPointerConstIncrement ( Addr . getNode ( ) , & Base , & CInc ) ) { unsigned Offset = getPointerConstIncrement ( Addr -> getOpcode ( ) , Base , CInc , DCI . DAG ) ; for ( SDNode :: use_iterator UI = Base -> use_begin ( ) , UE = Base -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( UI . getUse ( ) . getResNo ( ) != Base . getResNo ( ) || User == Addr . getNode ( ) || User -> getNumOperands ( ) != <NUM_LIT> ) continue ; SDValue UserInc = User -> getOperand ( UI . getOperandNo ( ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; unsigned UserOffset = getPointerConstIncrement ( User -> getOpcode ( ) , Base , UserInc , DCI . DAG ) ; if ( ! UserOffset || UserOffset <= Offset ) continue ; unsigned NewConstInc = UserOffset - Offset ; SDValue NewInc = DCI . DAG . getConstant ( NewConstInc , SDLoc ( N ) , <STR_LIT> ) ; BaseUpdates . push_back ( { User , NewInc , NewConstInc } ) ; } } unsigned NumValidUpd = BaseUpdates . size ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumValidUpd ; ) { BaseUpdateUser & User = BaseUpdates [ I ] ; if ( ! isValidBaseUpdate ( N , User . N ) ) {


<s> uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( ! Binary ) { MI . dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; } const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( ( TSFlags & <STR_LIT> ) == <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; int Size = Desc . Size ; if ( ( TSFlags & <STR_LIT> ) != <STR_LIT> ) { bool isBundled = MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ;


<s> static unsigned int aarch64_sve_in_loop_reduction_latency ( vec_info * vinfo , stmt_vec_info stmt_info , tree vectype , const sve_vec_cost * sve_costs ) { switch ( aarch64_reduc_type ( vinfo , stmt_info ) ) { case EXTRACT_LAST_REDUCTION : return sve_costs -> clast_cost ; case FOLD_LEFT_REDUCTION : switch ( GET_MODE_INNER ( TYPE_MODE ( vectype ) ) ) {


<s> } else if ( ( LoadVT . getVectorNumElements ( ) % <NUM_LIT> ) == <NUM_LIT> ) { EquivLoadVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LoadVT . getVectorElementType ( ) , LoadVT . getVectorNumElements ( ) + <NUM_LIT> ) ; } } SDVTList VTList = DAG . getVTList ( EquivLoadVT , <STR_LIT> ) ; SDValue Load = DAG . getMemIntrinsicNode ( IsIntrinsic ? ( unsigned ) <STR_LIT> : Opcode , DL , VTList , Ops , M -> getMemoryVT ( ) , M -> getMemOperand ( ) ) ; SDValue Adjusted = adjustLoadValueTypeImpl ( Load , LoadVT , DL , DAG , Unpacked ) ;

return DAG . getMergeValues ( { Adjusted , Load . getValue ( <NUM_LIT> ) } , DL ) ;


<s> SDValue V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( i ) ) ; Ops . push_back ( V ) ; DCI . AddToWorklist ( V . getNode ( ) ) ; } EVT FloatVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ;

SDValue BV = DAG . getNode ( <STR_LIT> , dl , FloatVT , Ops ) ;


<s> bool <ISA_LIT>TargetMachine :: addSimpleCodeEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , bool DumpAsm , JITCodeEmitter & JCE ) { PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ; if ( DumpAsm ) { assert ( AsmPrinterCtor && <STR_LIT> ) ;

if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( ) , * this , OptLevel , true ) ) ;


<s> unsigned <ISA_LIT>AsmParser :: matchRegisterNameAlias ( StringRef Name , bool isVector ) { unsigned RegNum = isVector ? matchVectorRegName ( Name ) : MatchRegisterName ( Name ) ;

RegKind Kind = isVector ? RegKind :: NeonVector : RegKind :: Scalar ;


<s> if ( Width == <NUM_LIT> ) return getLRForRMW8 ( PtrIsCap , Ordering ) ; if ( Width == <NUM_LIT> ) return getLRForRMW16 ( PtrIsCap , Ordering ) ;

if ( Width == <NUM_LIT> ) return getLRForRMW32 ( PtrIsCap , Ordering ) ;


<s> if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( matchVectorAddress ( N , AM ) ) return false ; MVT VT = N . getSimpleValueType ( ) ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base_Reg . getNode ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } getAddressOperands ( AM , SDLoc ( N ) , Base , Scale , Index , Disp , Segment ) ; return true ;


<s> if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; if ( CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> || CRBit == <STR_LIT> ) Ret = <NUM_LIT> ; assert ( Ret != <NUM_LIT> && <STR_LIT> ) ;


<s> for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { PrevInstIsLFENCE = true ; continue ; } if ( MI . mayLoadOrStore ( ) && ! MI . isTerminator ( ) ) { if ( ! PrevInstIsLFENCE ) { BuildMI ( MBB , MI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; NumLFENCEsInserted ++ ; Modified = true ; } if ( OneLFENCEPerBasicBlock ) break ; } if ( MI . isTerminator ( ) && FirstTerminator == nullptr ) FirstTerminator = & MI ; if ( ! MI . isBranch ( ) || OmitBranchLFENCEs ) {


<s> } for ( int i = MFI . getObjectIndexBegin ( ) , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) if ( i != FramePointerSaveIndex && i != BasePointerSaveIndex ) MFI . setStackID ( i , TargetStackID :: Default ) ; for ( auto & R : VGPRToAGPRSpills ) { if ( R . second . IsDead ) MFI . RemoveStackObject ( R . first ) ;


<s> else switch_to_section ( data_section ) ;

if ( TARGET_LITTLE_ENDIAN ) fputs ( <STR_LIT> , asm_out_file ) ;


<s> assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( Subtarget . hasAVX2 ( ) ) if ( SDValue Extract = lowerShuffleOfExtractsAsVperm ( DL , V1 , V2 , Mask , DAG ) ) return Extract ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Zeroable , Subtarget , DAG ) ) return Insertion ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( Subtarget . hasSSSE3 ( ) ) { if ( Subtarget . hasVLX ( ) ) if ( SDValue Rotate = lowerShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ;

if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ;


<s> ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BasePtr ; if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else BasePtr = ( hasFP ( MF ) ? FramePtr : StackPtr ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; if ( MI . getOperand ( i + <NUM_LIT> ) . isImm ( ) ) { int Offset = getFrameIndexOffset ( MF , FrameIndex ) + ( int ) ( MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else { uint64_t Offset = getFrameIndexOffset ( MF , FrameIndex ) + ( uint64_t ) MI . getOperand ( i + <NUM_LIT> ) . getOffset ( ) ; MI . getOperand ( i + <NUM_LIT> ) . setOffset ( Offset ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> bool <ISA_LIT>InterleavedAccessGroup :: isSupported ( ) const { VectorType * ShuffleVecTy = Shuffles [ <NUM_LIT> ] -> getType ( ) ; uint64_t ShuffleVecSize = DL . getTypeSizeInBits ( ShuffleVecTy ) ;

Type * ShuffleEltTy = ShuffleVecTy -> getVectorElementType ( ) ;


<s> if ( FirstInstrToMove != SecondInstrToMove ) MBB -> splice ( FirstTerminator , MBB , SecondInstrToMove ) ; MBB -> splice ( FirstTerminator , MBB , CRI . MI ) ; unsigned Opc = CRI . MI -> getOpcode ( ) ; bool InvertOrigBranch , InvertNewBranch , TargetIsFallThrough ; computeBranchTargetAndInversion ( Opc , Branch -> getOpcode ( ) , UsingDef1 , InvertNewBranch , InvertOrigBranch , TargetIsFallThrough ) ; MachineInstr * SplitCond = UsingDef1 ? CRI . CopyDefs . second : CRI . CopyDefs . first ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( InvertNewBranch ? <STR_LIT> : <STR_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( TargetIsFallThrough ? <STR_LIT> : <STR_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Branch -> dump ( ) ) ; BlockSplitInfo BSI { Branch , SplitBefore , SplitCond , InvertNewBranch , InvertOrigBranch , TargetIsFallThrough , MBPI , CRI . MI , UsingDef1 ? CRI . CopyDefs . first : CRI . CopyDefs . second } ; bool Changed = splitMBB ( BSI ) ; if ( Changed ) { bool Input1CRlogical = CRI . TrueDefs . first && isCRLogical ( * CRI . TrueDefs . first ) ; bool Input2CRlogical = CRI . TrueDefs . second && isCRLogical ( * CRI . TrueDefs . second ) ;

if ( Input1CRlogical ) AllCRLogicalOps . push_back ( createCRLogicalOpInfo ( * CRI . TrueDefs . first ) ) ;


<s> auto * SVal = dyn_cast < MCSymbolRefExpr > ( getImm ( ) ) ; if ( ! SVal || SVal -> getKind ( ) != MCSymbolRefExpr :: VK_None ) return false ; StringRef Str = SVal -> getSymbol ( ) . getName ( ) ; char Prev = '\0' ; for ( char c : Str ) { if ( c != 'i' && c != 'o' && c != 'r' && c != 'w' ) return false ;


<s> CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Align ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else {

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ;


<s> static Relocator :: DWord helper_thumb32_cond_branch_upper ( Relocator :: DWord pUpper16 , Relocator :: DWord pOffset ) { uint32_t sign = ( ( pOffset & <NUM_LIT> ) >> <NUM_LIT> ) ; return ( pUpper16 & <NUM_LIT> ) | ( sign << <NUM_LIT> ) | ( ( pOffset & <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> BTFOffsetReloc OffsetReloc ; OffsetReloc . Label = ORSym ; OffsetReloc . OffsetNameOff = addString ( IndexPattern ) ; OffsetReloc . TypeID = RootId ; AccessOffsets [ AccessPattern . str ( ) ] = std :: stoi ( OffsetStr ) ;

OffsetRelocTable [ SecNameOff ] . push_back ( OffsetReloc ) ;


<s> if ( TARGET_ES0 && TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && TREE_ADDRESSABLE ( decl ) && TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) == ADDR_SPACE_GENERIC ) { tree type = TREE_TYPE ( decl ) ; tree attr = TYPE_ATTRIBUTES ( type ) ; int q = TYPE_QUALS_NO_ADDR_SPACE ( type ) | ENCODE_QUAL_ADDR_SPACE ( ADDR_SPACE_FAR ) ;

TREE_TYPE ( decl ) = build_type_attribute_qual_variant ( type , attr , q ) ;


<s> MachineInstr & SubRegMI2 = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( SubToRegDef2 ) . addImm ( <NUM_LIT> ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; MachineInstr & BFM = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( SubToRegDef ) . addUse ( SubToRegDef2 ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( SubRegMI , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( SubRegMI2 , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( BFM , TII , TRI , RBI ) ; I . eraseFromParent ( ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitAtomicCmpSwap ( MachineInstr & MI , MachineBasicBlock * BB ) const { MachineFunction * MF = BB -> getParent ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loop1MBB ) ;


<s> if ( MemOps [ i ] . Position < Position ) { Position = MemOps [ i ] . Position ; Loc = MemOps [ i ] . MBBI ; } } if ( Loc != MBB . begin ( ) ) RS -> forward ( std :: prev ( Loc ) ) ;


<s> Register GlobalBaseReg = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ;

return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ;


<s> return isImm ( <NUM_LIT> , <NUM_LIT> ) ;


<s> val = INTVAL ( first ) ; first_byte = val & <NUM_LIT> ; for ( i = <NUM_LIT> ; i < bytes ; i ++ ) { val >>= <NUM_LIT> ; if ( ( val & <NUM_LIT> ) != first_byte ) return false ; }


<s> uint64_t <ISA_LIT>GOT :: getGPDispAddress ( ) const {

return addr ( ) + <ISA_LIT>GOTGpOffset ;


<s> if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , GPU , FS , * this ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( ) ;

GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * I -> getTargetLowering ( ) ) ) ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) || MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) return false ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; break ; } return true ; }


<s> bool <ISA_LIT>Subtarget :: isVGPRSpillingEnabled ( const <ISA_LIT>MachineFunctionInfo * MFI ) const {

return MFI -> getShaderType ( ) == ShaderType :: COMPUTE || EnableVGPRSpilling ;


<s> if ( MaskVT . bitsGT ( Mask . getValueType ( ) ) ) { EVT newMaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , MaskVT . getSizeInBits ( ) ) ; VMask = DAG . getBitcast ( MaskVT , DAG . getNode ( <STR_LIT> , dl , newMaskVT , Mask ) ) ; } else { EVT BitcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , Mask . getValueType ( ) . getSizeInBits ( ) ) ; VMask = DAG . getNode ( <STR_LIT> , dl , MaskVT , DAG . getBitcast ( BitcastVT , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpcodeSelect = <STR_LIT> ; break ;


<s> bool isICmp = true ; bool needsExt = false ; switch ( SrcVT . SimpleTy ) { default : return false ; case <STR_LIT> : isICmp = false ; if ( isEquality ) CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; else CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : isICmp = false ; if ( isEquality ) CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; else CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( Src2Value ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( needsExt ) { SrcReg1 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , isZExt ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; if ( ! UseImm ) { SrcReg2 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , isZExt ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } } const MCInstrDesc & II = TII . get ( CmpOpc ) ; SrcReg1 = constrainOperandRegClass ( II , SrcReg1 , <NUM_LIT> ) ; if ( ! UseImm ) { SrcReg2 = constrainOperandRegClass ( II , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; } else { MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) ; if ( isICmp ) MIB . addImm ( Imm ) ; AddOptionalDefs ( MIB ) ; }

if ( Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ) ;


<s> SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ;

SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> , <STR_LIT> , MMO ) ;


<s> static Value * simplify<ISA_LIT>insertps ( const IntrinsicInst & II , InstCombiner :: BuilderTy & Builder ) { auto * CInt = dyn_cast < ConstantInt > ( II . getArgOperand ( <NUM_LIT> ) ) ; if ( ! CInt ) return nullptr ; auto * VecTy = cast < FixedVectorType > ( II . getType ( ) ) ; assert ( VecTy -> getNumElements ( ) == <NUM_LIT> && <STR_LIT> ) ; uint8_t Imm = CInt -> getZExtValue ( ) ; uint8_t ZMask = Imm & <NUM_LIT> ; uint8_t DestLane = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t SourceLane = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; ConstantAggregateZero * ZeroVector = ConstantAggregateZero :: get ( VecTy ) ; if ( ZMask == <NUM_LIT> ) return ZeroVector ; int ShuffleMask [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Value * V1 = II . getArgOperand ( <NUM_LIT> ) ; if ( ZMask ) { if ( ( II . getArgOperand ( <NUM_LIT> ) == II . getArgOperand ( <NUM_LIT> ) ) || ( ZMask & ( <NUM_LIT> << DestLane ) ) ) { V1 = ZeroVector ; ShuffleMask [ DestLane ] = SourceLane ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( ( ZMask >> i ) & <NUM_LIT> ) ShuffleMask [ i ] = i + <NUM_LIT> ; } else {


<s> if ( ( TARGET_ALTIVEC && ! TARGET_VSX ) || ( TARGET_VSX && ! TARGET_EFFICIENT_UNALIGNED_VSX ) ) return altivec_builtin_mask_for_load ;


return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) ;


<s> auto Exp = extractF64Exponent ( Hi , B ) ; const unsigned FractBits = <NUM_LIT> ; const auto SignBitMask = B . buildConstant ( S32 , UINT32_C ( <NUM_LIT> ) << <NUM_LIT> ) ; auto SignBit = B . buildAnd ( S32 , Hi , SignBitMask ) ; const auto FractMask = B . buildConstant ( S64 , ( UINT64_C ( <NUM_LIT> ) << FractBits ) - <NUM_LIT> ) ; const auto Zero32 = B . buildConstant ( S32 , <NUM_LIT> ) ; auto SignBit64 = B . buildMerge ( S64 , { Zero32 , SignBit } ) ; auto Shr = B . buildAShr ( S64 , FractMask , Exp ) ; auto Not = B . buildNot ( S64 , Shr ) ; auto Tmp0 = B . buildAnd ( S64 , Src , Not ) ; auto FiftyOne = B . buildConstant ( S32 , FractBits - <NUM_LIT> ) ; auto ExpLt0 = B . buildICmp ( CmpInst :: ICMP_SLT , S1 , Exp , Zero32 ) ; auto ExpGt51 = B . buildICmp ( CmpInst :: ICMP_SGT , S1 , Exp , FiftyOne ) ;

auto Tmp1 = B . buildSelect ( S64 , ExpLt0 , SignBit64 , Tmp0 ) ;


<s> InsertNOPLoad = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; HasLeonCycleCounter = false ; std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ;


<s> unsigned Idx = v2x ( R ) ; if ( Idx >= Bits . size ( ) ) return false ; return Bits . test ( Idx ) ;


<s> const Module * M = MMI -> getModule ( ) ; for ( const GlobalVariable & Global : M -> globals ( ) ) { StringRef SecName ; if ( Global . hasSection ( ) ) { SecName = Global . getSection ( ) ; } else if ( Global . hasInitializer ( ) ) { if ( Global . isConstant ( ) ) SecName = <STR_LIT> ; else SecName = Global . getInitializer ( ) -> isZeroValue ( ) ? <STR_LIT> : <STR_LIT> ; } if ( ProcessingMapDef != SecName . startswith ( <STR_LIT> ) ) continue ; if ( SecName == <STR_LIT> && Global . hasPrivateLinkage ( ) && DataSecEntries . find ( std :: string ( SecName ) ) == DataSecEntries . end ( ) ) { SectionKind GVKind = TargetLoweringObjectFile :: getKindForGlobal ( & Global , Asm -> TM ) ; if ( ! GVKind . isMergeableCString ( ) && ! GVKind . isMergeableConst ( ) ) { DataSecEntries [ std :: string ( SecName ) ] = std :: make_unique < BTFKindDataSec > ( Asm , std :: string ( SecName ) ) ; } } SmallVector < DIGlobalVariableExpression * , <NUM_LIT> > GVs ; Global . getDebugInfo ( GVs ) ; if ( GVs . size ( ) == <NUM_LIT> ) continue ; uint32_t GVTypeId = <NUM_LIT> ; DIGlobalVariable * DIGlobal = nullptr ; for ( auto * GVE : GVs ) { DIGlobal = GVE -> getVariable ( ) ; if ( SecName . startswith ( <STR_LIT> ) ) visitMapDefType ( DIGlobal -> getType ( ) , GVTypeId ) ; else visitTypeEntry ( DIGlobal -> getType ( ) , GVTypeId , false , false ) ; break ; } auto Linkage = Global . getLinkage ( ) ; if ( Linkage != GlobalValue :: InternalLinkage && Linkage != GlobalValue :: ExternalLinkage && Linkage != GlobalValue :: WeakAnyLinkage && Linkage != GlobalValue :: WeakODRLinkage && Linkage != GlobalValue :: ExternalWeakLinkage ) continue ; uint32_t GVarInfo ;

if ( Linkage == GlobalValue :: InternalLinkage ) {


<s> } else if ( REG_P ( new_entry . cstore . set_src ( ) ) ) { new_entry . cstore_reg_reg_copies . push_back ( new_entry . cstore ) ; reg = new_entry . cstore . set_src ( ) ; i = new_entry . cstore . insn ; log_msg ( <STR_LIT> ) ; log_rtx ( reg ) ; log_msg ( <STR_LIT> ) ; continue ; } else log_return ( other_set_found , <STR_LIT> ) ; gcc_assert ( new_entry . cstore_type != cstore_unknown ) ; log_msg ( <STR_LIT> ) ; new_entry . setcc = find_set_of_reg_bb ( m_ccreg , prev_nonnote_nondebug_insn_bb ( new_entry . cstore . insn ) ) ;

if ( new_entry . setcc . set_src ( ) == NULL_RTX ) log_return ( set_found , <STR_LIT> ) ;


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true , true , true ) ;


<s> return __builtin_loongson_punpckhwd_s ( s , t ) ;


<s> EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { bool UseGOT_PREL = ! ( GV -> hasHiddenVisibility ( ) || GV -> hasLocalLinkage ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; return Result ; } if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ;


<s> current_function_uses_pic_offset_table = <NUM_LIT> ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_EQUAL , orig , REG_NOTES ( insn ) ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == pic_offset_table_rtx ) return orig ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS ) return orig ; if ( reg == <NUM_LIT> ) { gcc_assert ( ! no_new_pseudos ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS ) ; base = legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg ) ; offset = legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , base == reg ? <NUM_LIT> : reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( ! arm_legitimate_index_p ( mode , offset , SET , <NUM_LIT> ) ) { gcc_assert ( ! no_new_pseudos ) ; offset = force_reg ( Pmode , offset ) ; } if ( GET_CODE ( offset ) == CONST_INT ) return plus_constant ( base , INTVAL ( offset ) ) ; } if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> && ( GET_MODE_CLASS ( mode ) == MODE_INT || TARGET_SOFT_FLOAT ) ) { emit_insn ( gen_addsi3 ( reg , base , offset ) ) ; return reg ; }

return gen_rtx_PLUS ( Pmode , base , offset ) ;


<s> if ( ! Op . isReg ( ) || Op . isUndef ( ) ) continue ; Register R = Op . getReg ( ) ; if ( TRI -> hasAGPRs ( TRI -> getRegClassForReg ( * MRI , R ) ) ) continue ; unsigned ShiftedBank = Bank ; if ( Bank != - <NUM_LIT> && R == Reg && Op . getSubReg ( ) ) { unsigned Offset = TRI -> getChannelFromSubReg ( Op . getSubReg ( ) ) ; LaneBitmask LM = TRI -> getSubRegIndexLaneMask ( Op . getSubReg ( ) ) ; if ( Offset && Bank < NUM_VGPR_BANKS ) { if ( TRI -> getNumCoveredRegs ( LM ) >= NUM_VGPR_BANKS ) continue ; ShiftedBank = ( Bank + Offset ) % NUM_VGPR_BANKS ; } else if ( Offset > <NUM_LIT> && Bank >= SGPR_BANK_OFFSET ) { if ( TRI -> getNumCoveredRegs ( LM ) / <NUM_LIT> >= NUM_SGPR_BANKS ) continue ; ShiftedBank = SGPR_BANK_OFFSET + ( Bank - SGPR_BANK_OFFSET + ( Offset >> <NUM_LIT> ) ) % NUM_SGPR_BANKS ; } }

uint32_t Mask = getRegBankMask ( R , Op . getSubReg ( ) , ( Reg == R ) ? ShiftedBank : - <NUM_LIT> ) ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> UseScaled = false ; ScaleFactor = <NUM_LIT> ; } static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; unsigned Opc ; const TargetRegisterClass * RC ; bool VTIsi1 = false ; bool UseRegOffset = Addr . isRegBase ( ) && ! Addr . getOffset ( ) && Addr . getReg ( ) && Addr . getOffsetReg ( ) ; unsigned Idx = UseRegOffset ? <NUM_LIT> : UseScaled ? <NUM_LIT> : <NUM_LIT> ; if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) Idx ++ ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VTIsi1 = true ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; break ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: sparc , true > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: sparcv9 , true > Y ( The<ISA_LIT>V9Target , <STR_LIT> , <STR_LIT> ) ;

RegisterTarget < Triple :: sparcel , true > Z ( The<ISA_LIT>elTarget , <STR_LIT> , <STR_LIT> ) ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : MF ( MF ) , SRetReturnReg ( <NUM_LIT> ) , GlobalBaseReg ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , InArgFIRange ( std :: make_pair ( - <NUM_LIT> , <NUM_LIT> ) ) , MaxCallFrameSize ( <NUM_LIT> ) , EmitNOAT ( false ) {


<s> bool Upper = IdxVal >= NumElems / <NUM_LIT> ; V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V , N1 , DAG . getConstant ( Upper ? IdxVal - NumElems / <NUM_LIT> : IdxVal , <STR_LIT> ) ) ; return Insert128BitVector ( N0 , V , IdxVal , DAG , dl ) ; } if ( Subtarget -> hasSSE41 ( ) ) return LowerINSERT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( EltVT == <STR_LIT> ) return SDValue ( ) ; if ( EltVT . getSizeInBits ( ) == <NUM_LIT> && isa < ConstantSDNode > ( N2 ) ) { if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } return SDValue ( ) ;


<s> tryParseProcIFlagsOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; assert ( Tok . is ( AsmToken :: Identifier ) && <STR_LIT> ) ; StringRef IFlagsStr = Tok . getString ( ) ; unsigned IFlags = <NUM_LIT> ; for ( int i = <NUM_LIT> , e = IFlagsStr . size ( ) ; i != e ; ++ i ) { unsigned Flag = StringSwitch < unsigned > ( IFlagsStr . substr ( i , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Flag == ~ <NUM_LIT> || ( IFlags & Flag ) ) return MatchOperand_NoMatch ; IFlags |= Flag ;


<s> if ( TARGET_AAPCS_BASED && arm_pcs_default != ARM_PCS_AAPCS && GET_MODE_CLASS ( mode ) == MODE_FLOAT ) {

if ( arm_libcall_uses_aapcs_base ( libcall ) ) return gen_rtx_REG ( mode , ARG_REGISTER ( <NUM_LIT> ) ) ;


<s> return __builtin_mve_vctp16q_mhi ( __a , __p ) ;


<s> HalfArg = DAG . getNode ( <STR_LIT> , dl , VT , HalfArg , Op ) ; DCI . AddToWorklist ( HalfArg . getNode ( ) ) ; for ( int i = <NUM_LIT> ; i < Iterations ; ++ i ) { SDValue NewEst = DAG . getNode ( <STR_LIT> , dl , VT , Est , Est ) ; DCI . AddToWorklist ( NewEst . getNode ( ) ) ; NewEst = DAG . getNode ( <STR_LIT> , dl , VT , HalfArg , NewEst ) ; DCI . AddToWorklist ( NewEst . getNode ( ) ) ; NewEst = DAG . getNode ( <STR_LIT> , dl , VT , FPThreeHalves , NewEst ) ; DCI . AddToWorklist ( NewEst . getNode ( ) ) ;

Est = DAG . getNode ( <STR_LIT> , dl , VT , Est , NewEst ) ;


<s> nios2_custom_check_insns ( ) ; return build_target_option_node ( & global_options , & global_options_set ) ;


<s> Optional < unsigned > FirstMaskArgument ; if ( Subtarget . hasStdExtV ( ) ) FirstMaskArgument = preAssignMask ( Ins ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT ArgVT = Ins [ i ] . VT ; <STR_LIT> ArgFlags = Ins [ i ] . Flags ; Type * ArgTy = nullptr ; if ( IsRet ) ArgTy = FType -> getReturnType ( ) ; else if ( Ins [ i ] . isOrigArg ( ) ) ArgTy = FType -> getParamType ( Ins [ i ] . getOrigArgIndex ( ) ) ;

<STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ;


<s> else if ( isAM4 && Offset == - <NUM_LIT> * ( int ) NumRegs ) Mode = <STR_LIT> ; else if ( Offset != <NUM_LIT> ) { if ( NumRegs <= <NUM_LIT> ) return false ; unsigned NewBase ; if ( Opcode == <STR_LIT> ) NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = <STR_LIT> ; if ( Offset < <NUM_LIT> ) { BaseOpc = <STR_LIT> ; Offset = - Offset ; } int ImmedOffset = <STR_LIT> ( Offset ) ; if ( ImmedOffset == - <NUM_LIT> ) return false ; BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , false , false , BaseKill ) . addImm ( ImmedOffset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; Base = NewBase ; BaseKill = true ; } bool isDPR = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool isDef = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; Opcode = getLoadStoreMultipleOpcode ( Opcode ) ; MachineInstrBuilder MIB = ( isAM4 ) ? BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode ) ) . addReg ( Base , false , false , BaseKill ) . addImm ( <STR_LIT> ( Mode ) ) . addImm ( Pred ) . addReg ( PredReg ) : BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode ) ) . addReg ( Base , false , false , BaseKill ) . addImm ( <STR_LIT> ( Mode , false , isDPR ? NumRegs << <NUM_LIT> : NumRegs ) ) . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned i = <NUM_LIT> ; i != NumRegs ; ++ i ) MIB = MIB . addReg ( Regs [ i ] . first , isDef , false , Regs [ i ] . second ) ;


<s> void addLOHDirective ( MCLOHType Kind , MILOHArgs Args ) { LOHContainerSet . push_back ( MILOHDirective ( Kind , Args ) ) ; LOHRelated . insert ( Args . begin ( ) , Args . end ( ) ) ;


<s> FormalArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , CCAssignFn AssignFn ) : <ISA_LIT>IncomingValueHandler ( MIRBuilder , MRI , AssignFn ) {


<s> rtx op1 = frv_read_argument ( call , <NUM_LIT> ) ; target = frv_legitimize_target ( icode , target ) ; op0 = frv_legitimize_argument ( icode , <NUM_LIT> , op0 ) ; op1 = frv_legitimize_argument ( icode , <NUM_LIT> , op1 ) ; pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ;


<s> else { mem_left = mem_hi ; mem_right = mem_lo ; } if ( sign ) { emit_insn ( gen_zero_extendqidi2 ( gen_lowpart ( DImode , dest_reg ) , mem_right ) ) ; emit_insn ( gen_extendqidi2 ( gen_lowpart ( DImode , left ) , mem_left ) ) ; emit_insn ( gen_insv ( gen_lowpart ( DImode , dest_reg ) , GEN_INT ( <NUM_LIT> - <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) , gen_lowpart ( DImode , left ) ) ) ; } else { rtx right = gen_reg_rtx ( mode ) ; emit_insn ( gen_zero_extendqidi2 ( gen_lowpart ( DImode , right ) , mem_right ) ) ; emit_insn ( gen_zero_extendqidi2 ( gen_lowpart ( DImode , left ) , mem_left ) ) ; emit_insn ( gen_insn_v1int_l ( gen_lowpart ( DImode , dest_reg ) , gen_lowpart ( DImode , left ) , gen_lowpart ( DImode , right ) ) ) ; } return ; } mema = XEXP ( mem , <NUM_LIT> ) ; addr_lo = force_reg ( Pmode , plus_constant ( Pmode , mema , byte_offset ) ) ; mem_lo = change_address ( mem , mode , gen_rtx_AND ( GET_MODE ( mema ) , addr_lo , GEN_INT ( - <NUM_LIT> ) ) ) ; set_mem_alias_set ( mem_lo , <NUM_LIT> ) ; last_byte_offset = ( bit_offset + bitsize - <NUM_LIT> ) / BITS_PER_UNIT ; addr_hi = force_reg ( Pmode , plus_constant ( Pmode , mema , last_byte_offset ) ) ; mem_hi = change_address ( mem , mode , gen_rtx_AND ( GET_MODE ( mema ) , addr_hi , GEN_INT ( - <NUM_LIT> ) ) ) ; set_mem_alias_set ( mem_hi , <NUM_LIT> ) ; if ( bitsize == <NUM_LIT> ) { addr_lo = make_safe_from ( addr_lo , dest_reg ) ; wide_result = dest_reg ;


<s> <ISA_LIT>DCFunction :: <ISA_LIT>DCFunction ( DCModule & DCM , const MCFunction & MCF ) : DCFunction ( DCM , MCF ) {


<s> } else { if ( w0 == <NUM_LIT> && ( TARGET_H8300 ? ( code == AND ) : ( code != IOR ) ) ) { length += <NUM_LIT> ; } else if ( ( TARGET_H8300H || TARGET_H8300S ) && ( b0 != <NUM_LIT> ) && ( b1 != <NUM_LIT> ) ) { length += <NUM_LIT> ; } else { if ( b0 != <NUM_LIT> ) length += <NUM_LIT> ; if ( b1 != <NUM_LIT> ) length += <NUM_LIT> ; } if ( w1 == <NUM_LIT> && ( TARGET_H8300 ? ( code == AND ) : ( code != IOR ) ) ) { length += <NUM_LIT> ; } else if ( ( TARGET_H8300H || TARGET_H8300S ) && code == IOR && w1 == <NUM_LIT> && ( w0 & <NUM_LIT> ) != <NUM_LIT> ) { length += <NUM_LIT> ; } else if ( ( TARGET_H8300H || TARGET_H8300S ) && code == AND && w1 == <NUM_LIT> ) { length += <NUM_LIT> ; } else if ( TARGET_H8300H || TARGET_H8300S ) { if ( w1 != <NUM_LIT> ) length += <NUM_LIT> ; } else { if ( b2 != <NUM_LIT> ) length += <NUM_LIT> ; if ( b3 != <NUM_LIT> ) length += <NUM_LIT> ; } } break ;


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsVarArg = MF . getFunction ( ) -> isVarArg ( ) ; if ( IsVarArg ) for ( unsigned I = MFI -> getVarArgsFirstGPR ( ) ; I < <STR_LIT> ; ++ I ) SavedRegs . set ( <STR_LIT> [ I ] ) ; if ( ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ) { SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set ( <STR_LIT> ) ; } if ( HasFP ) SavedRegs . set ( <STR_LIT> ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( <STR_LIT> ) ;

const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ;


<s> } else if ( FP_REG_P ( regno ) ) { if ( ! FP_REG_P ( regno + nregs - <NUM_LIT> ) ) return false ; if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && GET_MODE_CLASS ( mode ) != MODE_COMPLEX_FLOAT ) return false ; if ( GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_REG || ( ! call_used_regs [ regno ] && GET_MODE_UNIT_SIZE ( mode ) > UNITS_PER_FP_ARG ) ) return false ;


<s> assert ( MBBI != Entry -> end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ; MBBI -> eraseFromParent ( ) ; bool RemovedAllMTVRSAVEs = true ; for ( MachineFunction :: iterator I = MF -> begin ( ) , E = MF -> end ( ) ; I != E ; ++ I ) { if ( ! I -> empty ( ) && I -> back ( ) . isReturn ( ) ) { bool FoundIt = false ; for ( MBBI = I -> end ( ) ; MBBI != I -> begin ( ) ; ) { -- MBBI ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { MBBI -> eraseFromParent ( ) ; FoundIt = true ; break ; } }


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; SDLoc & dl = CLI . DL ; SmallVectorImpl < <STR_LIT> > & Outs = CLI . Outs ; SmallVectorImpl < SDValue > & OutVals = CLI . OutVals ;

SmallVectorImpl < <STR_LIT> > & Ins = CLI . Ins ;


<s> if ( TARGET_MIN_VLEN == <NUM_LIT> ) return mode_vtype_infos . ratio_for_min_vlen32 [ mode ] ; else return mode_vtype_infos . ratio_for_min_vlen64 [ mode ] ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned RegsNeeded ; const TargetRegisterClass * RegClass ; if ( IsVFPPushPop ) { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } else { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; unsigned FirstRegEnc = - <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) { MachineOperand & MO = MI -> getOperand ( i ) ; RegList . push_back ( MO ) ; if ( MO . isReg ( ) && ! MO . isImplicit ( ) && TRI -> getEncodingValue ( MO . getReg ( ) ) < FirstRegEnc ) FirstRegEnc = TRI -> getEncodingValue ( MO . getReg ( ) ) ; } const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( int CurRegEnc = FirstRegEnc - <NUM_LIT> ; CurRegEnc >= <NUM_LIT> && RegsNeeded ; -- CurRegEnc ) { unsigned CurReg = RegClass -> getRegister ( CurRegEnc ) ; if ( IsT1PushPop && CurRegEnc > TRI -> getEncodingValue ( <STR_LIT> ) ) continue ; if ( ! IsPop ) { RegList . push_back ( MachineOperand :: CreateReg ( CurReg , false , false , false , false , true ) ) ; -- RegsNeeded ; continue ; } if ( isCalleeSavedRegister ( CurReg , CSRegs ) || MI -> getParent ( ) -> computeRegisterLiveness ( TRI , CurReg , MI ) != MachineBasicBlock :: LQR_Dead ) {


<s> bool <ISA_LIT>AsmParser :: parseDirectiveEven ( SMLoc L ) { const MCSection * Section = getStreamer ( ) . getCurrentSection ( ) . first ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { TokError ( <STR_LIT> ) ; return false ; } if ( ! Section ) { getStreamer ( ) . InitSections ( ) ; Section = getStreamer ( ) . getCurrentSection ( ) . first ; } assert ( Section && <STR_LIT> ) ; if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> ) ;


<s> SPExcessSpillOffset = SinglePathFIs . size ( ) ;


<s> unsigned lg2 = SplatValue . countTrailingZeros ( ) ; SDValue Sz = DAG . getConstant ( EltTy . getSizeInBits ( ) - <NUM_LIT> , <STR_LIT> ) ; SDValue SGN = getTargetVShiftNode ( <STR_LIT> , dl , VT , N0 , Sz , DAG ) ; SDValue Amt = DAG . getConstant ( EltTy . getSizeInBits ( ) - lg2 , <STR_LIT> ) ; SDValue SRL = getTargetVShiftNode ( <STR_LIT> , dl , VT , SGN , Amt , DAG ) ; SDValue ADD = DAG . getNode ( <STR_LIT> , dl , VT , N0 , SRL ) ; SDValue Lg2Amt = DAG . getConstant ( lg2 , <STR_LIT> ) ; SDValue SRA = getTargetVShiftNode ( <STR_LIT> , dl , VT , ADD , Lg2Amt , DAG ) ; if ( SplatValue . isNonNegative ( ) ) return SRA ;

SmallVector < SDValue , <NUM_LIT> > V ( NumElts , DAG . getConstant ( <NUM_LIT> , EltTy ) ) ;


<s> case TYPE_DIV : if ( get_attr_size ( insn ) == SIZE_32 ) return true ; else break ; default : break ; } break ; case PROCESSOR_POWER7 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_ISYNC : case TYPE_SYNC : case TYPE_LOAD_L : case TYPE_STORE_C : return true ; case TYPE_LOAD : if ( get_attr_sign_extend ( insn ) == SIGN_EXTEND_YES && get_attr_update ( insn ) == UPDATE_YES ) return true ; else break ; case TYPE_STORE : if ( get_attr_update ( insn ) == UPDATE_YES && get_attr_indexed ( insn ) == INDEXED_YES ) return true ; else break ; default : break ; } break ; case PROCESSOR_POWER8 : type = get_attr_type ( insn ) ; switch ( type ) { case TYPE_MFCR : case TYPE_MTCR : case TYPE_ISYNC : case TYPE_SYNC : case TYPE_LOAD_L : case TYPE_STORE_C :


<s> return isImmTy ( ImmTyGprIdxMode ) ;


<s> SDLoc dl ( Op ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! Cst ) return SDValue ( ) ;

unsigned Val = Cst -> getZExtValue ( ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! EnableBasePointer ) return false ; if ( ( needsStackRealignment ( MF ) && MFI -> hasVarSizedObjects ( ) ) || MF . hasMSInlineAsm ( ) ) return true ; return false ;


<s> } if ( Subtarget . isDarwinABI ( ) ) return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_Darwin64_Altivec_SaveList : CSR_Darwin64_SaveList ) : ( Subtarget . hasAltivec ( ) ? CSR_Darwin32_Altivec_SaveList : CSR_Darwin32_SaveList ) ; if ( TM . is<ISA_LIT>64 ( ) && MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_SRV464_TLS_PE_SaveList ; bool SaveR2 = MF -> getRegInfo ( ) . isAllocatable ( <STR_LIT> ) ;

if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: Cold ) {


<s> else if ( ( fnmask & RS6000_BTM_P9_MISC ) == RS6000_BTM_P9_MISC ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128 ) ) == ( RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128 ) ) error ( <STR_LIT> , name , <STR_LIT> , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_HARD_FLOAT ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & RS6000_BTM_FLOAT128_HW ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_FLOAT128 ) != <NUM_LIT> ) error ( <STR_LIT> , name , <STR_LIT> ) ; else if ( ( fnmask & ( RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64 ) ) == ( RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64 ) ) error ( <STR_LIT> <STR_LIT> , name , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> unsigned HOST_WIDE_INT size = tree_to_uhwi ( TYPE_SIZE_UNIT ( type ) ) ; if ( size == GET_MODE_SIZE ( TImode ) ) return GET_MODE_BITSIZE ( maybe_split_mode ( TImode ) ) ; } return basic_align ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Index = AM . IndexReg ; if ( getSymbolicDisplacement ( AM , SDLoc ( N ) , Disp ) ) { assert ( ! AM . Disp && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; }

Disp = getI8Imm ( AM . Disp , SDLoc ( N ) ) ;


<s> <ISA_LIT>CodeEmitter ( TargetMachine & tm , JITCodeEmitter & mce ) : MachineFunctionPass ( ID ) , JTI ( <NUM_LIT> ) , II ( <NUM_LIT> ) , TD ( <NUM_LIT> ) , TM ( tm ) , MCE ( mce ) , MCPEs ( <NUM_LIT> ) , MJTEs ( <NUM_LIT> ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) {


<s> if ( const Instruction * I = dyn_cast < Instruction > ( V ) ) if ( auto * CI = dyn_cast < CallInst > ( I ) ) if ( auto * F = CI -> getCalledFunction ( ) ) if ( F -> getIntrinsicID ( ) == <STR_LIT> ) return true ;


<s> if ( get<ISA_LIT>TargetMachine ( ) . isPositionIndependent ( ) ) { addPass ( & LiveVariablesID ) ; addPass ( create<ISA_LIT>TLSDynamicCallPass ( ) ) ; } if ( EnableExtraTOCRegDeps ) addPass ( create<ISA_LIT>TOCRegDepsPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & MachinePipelinerID ) ;


return ( Val >= <NUM_LIT> && Val < <NUM_LIT> ) ;


<s> return ( Imm & <NUM_LIT> ) >> <NUM_LIT> ;


<s> LowOverheadLoop ( MachineLoop & ML , MachineLoopInfo & MLI , ReachingDefAnalysis & RDA , const TargetRegisterInfo & TRI , const <ISA_LIT>BaseInstrInfo & TII ) : ML ( ML ) , MLI ( MLI ) , RDA ( RDA ) , TRI ( TRI ) , TII ( TII ) { MF = ML . getHeader ( ) -> getParent ( ) ; if ( auto * MBB = ML . getLoopPreheader ( ) ) Preheader = MBB ; else if ( auto * MBB = MLI . findLoopPreheader ( & ML , true ) ) Preheader = MBB ;


<s> break ; case Type :: PointerTyID : { if ( OpaqueType OT = GetOpaqueType ( type ) ) { if ( IsImage ( OT ) ) return BRIG_TYPE_RWIMG ; if ( OT == Sampler ) return BRIG_TYPE_SAMP ; } unsigned AS = cast < PointerType > ( type ) -> getAddressSpace ( ) ; return DL . getPointerSize ( AS ) == <NUM_LIT> ? BRIG_TYPE_U64 : BRIG_TYPE_U32 ; } case Type :: StructTyID : return BRIG_TYPE_U8_ARRAY ; case Type :: VectorTyID : return static_cast < BrigType > ( getBrigType ( type -> getScalarType ( ) , DL , Signed ) | BRIG_TYPE_ARRAY ) ; case Type :: ArrayTyID : return static_cast < BrigType > ( getBrigType ( cast < ArrayType > ( type ) -> getElementType ( ) , DL , Signed ) | BRIG_TYPE_ARRAY ) ; default : type -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned getSRetReturnReg ( ) const { return SRetReturnReg ;


<s> if ( VT . getScalarType ( ) != <STR_LIT> && VT . is256BitVector ( ) ) return splitVectorIntBinary ( Op , DAG ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return splitVectorIntBinary ( Op , DAG ) ; return SDValue ( ) ;


<s> Offset *= - <NUM_LIT> ; case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) break ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) break ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) break ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; int UpdateOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! IsPairedInsn && ( UpdateOffset > <NUM_LIT> || UpdateOffset < - <NUM_LIT> ) ) break ; if ( IsPairedInsn ) { int Scale = getMemScale ( MemMI ) ; if ( UpdateOffset % Scale != <NUM_LIT> ) break ; int ScaledOffset = UpdateOffset / Scale ;

if ( ScaledOffset > <NUM_LIT> || ScaledOffset < - <NUM_LIT> ) break ;


<s> break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str ) ; aarch64_print_hint_for_core ( str ) ; break ; case AARCH64_PARSE_INVALID_FEATURE : error ( <STR_LIT> , invalid_extension . c_str ( ) , str ) ; aarch64_print_hint_for_extensions ( invalid_extension ) ; break ; default :


<s> MachineBasicBlock :: const_iterator I = MBB . getLastNonDebugInstr ( ) ; unsigned RetOpc = I -> getOpcode ( ) ; return RetOpc == <STR_LIT> || RetOpc == <STR_LIT> ;


<s> MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , DL , <STR_LIT> ) ) ; if ( Val . getNode ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RegTy , Val , Shift ) ; else Val = Shift ; OffsetInBytes += LoadSizeInBytes ; TotalBytesLoaded += LoadSizeInBytes ; Alignment = std :: min ( Alignment , LoadSizeInBytes ) ; } unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , Val ) ) ; return ; } } unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes ; SDValue Src = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , DL , PtrTy ) ) ;

SDValue Dst = DAG . getNode ( <STR_LIT> , DL , PtrTy , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ;


<s> bool <ISA_LIT>ConstantIslands :: OptimizeThumb2Branches ( MachineFunction & MF ) { bool MadeChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) { ImmBranch & Br = ImmBranches [ i ] ; unsigned Opcode = Br . MI -> getOpcode ( ) ; unsigned NewOpc = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; unsigned Bits = <NUM_LIT> ; switch ( Opcode ) { default : break ; case <STR_LIT> : NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : { NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } } if ( NewOpc ) { unsigned MaxOffs = ( ( <NUM_LIT> << ( Bits - <NUM_LIT> ) ) - <NUM_LIT> ) * Scale ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( Br . MI , DestBB , MaxOffs ) ) { Br . MI -> setDesc ( TII -> get ( NewOpc ) ) ; MachineBasicBlock * MBB = Br . MI -> getParent ( ) ; BBSizes [ MBB -> getNumber ( ) ] -= <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB , - <NUM_LIT> ) ; ++ NumT2BrShrunk ; MadeChange = true ; } } Opcode = Br . MI -> getOpcode ( ) ; if ( Opcode != <STR_LIT> ) continue ; NewOpc = <NUM_LIT> ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = llvm :: getInstrPredicate ( Br . MI , PredReg ) ; if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; else if ( Pred == <STR_LIT> ) NewOpc = <STR_LIT> ; if ( ! NewOpc ) continue ; MachineBasicBlock * DestBB = Br . MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ;

unsigned BrOffset = GetOffsetOf ( Br . MI ) + <NUM_LIT> - <NUM_LIT> ;


<s> <ISA_LIT>ATTAsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser ( parser ) { setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> void <ISA_LIT>MCInstLower :: lower ( const MachineInstr * MI , MCInst & OutMI ) const { int MCOpcode = ST . getInstrInfo ( ) -> pseudoToMCOpcode ( MI -> getOpcode ( ) ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { MCOperand MCOp ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_Register : MCOp = MCOperand :: createReg ( <STR_LIT> ( MO . getReg ( ) , ST ) ) ; break ;

case MachineOperand :: MO_MachineBasicBlock :


<s> uint32_t I ; float F ; } FPUnion ; uint8_t Sign = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Exp = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Mantissa = Imm & <NUM_LIT> ; FPUnion . I = <NUM_LIT> ; FPUnion . I |= Sign << <NUM_LIT> ; FPUnion . I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ;


<s> unsigned MOHiFlag , MOLoFlag ; bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ; SDValue JTIHi = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , MOHiFlag ) ; SDValue JTILo = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , MOLoFlag ) ;

return LowerLabelRef ( JTIHi , JTILo , isPIC , DAG ) ;


<s> MCValue Value ; if ( Kind == VK_<ISA_LIT>_PCREL_HI || Kind == VK_<ISA_LIT>_PCREL_LO || Kind == VK_<ISA_LIT>_GOT_HI || Kind == VK_<ISA_LIT>_CALL ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ;

if ( ! Value . isAbsolute ( ) ) return false ;


<s> if ( Version . Major >= <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> MCELFStreamer & <ISA_LIT>TargetELFStreamer :: getStreamer ( ) { return static_cast < MCELFStreamer & > ( Streamer ) ;


<s> static bool mcore_base_register_rtx_p ( const_rtx x , bool strict_p ) { return REG_P ( x ) && mcore_reg_ok_for_base_p ( x , strict_p ) ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> if ( ! ( SMALL_INT_RANGE ( offset , ( GET_MODE_SIZE ( DImode ) - <NUM_LIT> ) & ( ~ <NUM_LIT> ) , ( offset & ( GET_MODE_SIZE ( DImode ) - <NUM_LIT> ) & <NUM_LIT> ? <NUM_LIT> : - ( - GET_MODE_SIZE ( DImode ) | ( ~ <NUM_LIT> ) ) >> <NUM_LIT> ) ) ) ) return false ; t = REGNO ( rt ) ;


<s> const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return true ; } continue ; } else if ( MO . isRegMask ( ) ) { for ( unsigned PR : <STR_LIT> ) { if ( ! MI . modifiesRegister ( PR , & HRI ) ) continue ; Pred . push_back ( MO ) ; return true ;


<s> verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { auto Reloc = STI . getTargetTriple ( ) . getEnvironment ( ) == Triple :: GNUILP32 ? ELF :: R_AARCH64_P32_TLSDESC_CALL : ELF :: R_AARCH64_TLSDESC_CALL ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getExpr ( ) , MCFixupKind ( FirstLiteralRelocationKind + Reloc ) ) ) ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { return ; } uint64_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ;

<STR_LIT> :: write < uint32_t > ( OS , Binary , <STR_LIT> ) ;


<s> OS << <STR_LIT> << InstSyncBOptToString ( getInstSyncBarrierOpt ( ) ) << <STR_LIT> ; break ; case k_TraceSyncBarrierOpt : OS << <STR_LIT> << TraceSyncBOptToString ( getTraceSyncBarrierOpt ( ) ) << <STR_LIT> ; break ; case k_Memory : OS << <STR_LIT> ; if ( Memory . BaseRegNum ) OS << <STR_LIT> << RegName ( Memory . BaseRegNum ) ; if ( Memory . OffsetImm ) OS << <STR_LIT> << * Memory . OffsetImm ; if ( Memory . OffsetRegNum ) OS << <STR_LIT> << ( Memory . isNegative ? <STR_LIT> : <STR_LIT> ) << RegName ( Memory . OffsetRegNum ) ; if ( Memory . ShiftType != <STR_LIT> ) { OS << <STR_LIT> << <STR_LIT> ( Memory . ShiftType ) ; OS << <STR_LIT> << Memory . ShiftImm ; } if ( Memory . Alignment ) OS << <STR_LIT> << Memory . Alignment ; OS << <STR_LIT> ; break ; case k_PostIndexRegister : OS << <STR_LIT> << ( PostIdxReg . isAdd ? <STR_LIT> : <STR_LIT> ) << RegName ( PostIdxReg . RegNum ) ; if ( PostIdxReg . ShiftTy != <STR_LIT> ) OS << <STR_LIT> ( PostIdxReg . ShiftTy ) << <STR_LIT> << PostIdxReg . ShiftImm ; OS << <STR_LIT> ; break ; case k_ProcIFlags : { OS << <STR_LIT> ; unsigned IFlags = getProcIFlags ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i ) ) OS << <STR_LIT> ( <NUM_LIT> << i ) ; OS << <STR_LIT> ; break ; } case k_Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ; case k_ShifterImmediate : OS << <STR_LIT> << ( ShifterImm . isASR ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ShifterImm . Imm << <STR_LIT> ; break ; case k_ShiftedRegister : OS << <STR_LIT> << RegName ( RegShiftedReg . SrcReg ) << <STR_LIT> << <STR_LIT> ( RegShiftedReg . ShiftTy ) << <STR_LIT> << RegName ( RegShiftedReg . ShiftReg ) << <STR_LIT> ; break ; case k_ShiftedImmediate : OS << <STR_LIT> << RegName ( RegShiftedImm . SrcReg ) << <STR_LIT> << <STR_LIT> ( RegShiftedImm . ShiftTy ) << <STR_LIT> << RegShiftedImm . ShiftImm << <STR_LIT> ; break ; case k_RotateImmediate : OS << <STR_LIT> << <STR_LIT> << ( RotImm . Imm * <NUM_LIT> ) << <STR_LIT> ; break ; case k_ModifiedImmediate : OS << <STR_LIT> << ModImm . Bits << <STR_LIT> << ModImm . Rot << <STR_LIT> ; break ; case k_ConstantPoolImmediate : OS << <STR_LIT> << * getConstantPoolImm ( ) ; break ;


<s> MCELFStreamer :: EmitInstruction ( Inst , STI ) ; MCContext & Context = getContext ( ) ; const MCRegisterInfo * MCRegInfo = Context . getRegisterInfo ( ) ; for ( unsigned OpIndex = <NUM_LIT> ; OpIndex < Inst . getNumOperands ( ) ; ++ OpIndex ) { const MCOperand & Op = Inst . getOperand ( OpIndex ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; return MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , Flag , MFI . getObjectSize ( FI ) , Align ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_8 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF8 : return ELF :: R_<ISA_LIT>_DIFF8 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_LO8 : return ELF :: R_<ISA_LIT>_8_LO8 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HI8 : return ELF :: R_<ISA_LIT>_8_HI8 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HLO8 : return ELF :: R_<ISA_LIT>_8_HLO8 ; } case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_32 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF32 : return ELF :: R_<ISA_LIT>_DIFF32 ; } case FK_Data_2 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : return ELF :: R_<ISA_LIT>_16 ; case MCSymbolRefExpr :: VK_<ISA_LIT>_NONE : case MCSymbolRefExpr :: VK_<ISA_LIT>_PM : return ELF :: R_<ISA_LIT>_16_PM ; case MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF16 : return ELF :: R_<ISA_LIT>_DIFF16 ; } case <STR_LIT> : return ELF :: R_<ISA_LIT>_32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_7_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_13_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_16_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI_NEG ; case <STR_LIT> :


<s> return fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; case <STR_LIT> : return fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; case <STR_LIT> : return SrcReg ; case <STR_LIT> : { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; return ResultReg ; } } } unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( Subtarget -> hasAVX512 ( ) ) return <NUM_LIT> ; VT = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : {

if ( isUInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ;


<s> virtual void PrintSwitchToSection ( const MCAsmInfo & MAI , raw_ostream & OS , const MCExpr * Subsection ) const {


<s> MVT DestVT = VA . getLocVT ( ) ; MVT SrcVT = ArgVT ; ArgReg = emitIntExt ( SrcVT , ArgReg , DestVT , true ) ; if ( ! ArgReg ) return false ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { llvm_unreachable ( <STR_LIT> ) ; return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = RoundUpToAlignment ( ArgVT . getSizeInBits ( ) , <NUM_LIT> ) ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittle ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset ( ) + BEAlign ) ; unsigned Alignment = DL . getABITypeAlignment ( ArgVal -> getType ( ) ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getStack ( Addr . getOffset ( ) ) , MachineMemOperand :: MOStore , ArgVT . getStoreSize ( ) , Alignment ) ; ( void ) ( MMO ) ; return false ;


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( Reg ) ; return ResultReg ;


<s> static __inline vec_ullong2 spu_cmpabseq ( vec_double2 a , vec_double2 b ) { return ( ( vec_ullong2 ) ( si_dfcmeq ( ( qword ) ( a ) , ( qword ) ( b ) ) ) ) ;


<s> code = gimple_assign_rhs_code ( stmt ) ; if ( ! CONVERT_EXPR_CODE_P ( code ) && ( ( code != PLUS_EXPR && code != POINTER_PLUS_EXPR ) || TREE_CODE ( gimple_assign_rhs2 ( stmt ) ) != INTEGER_CST || ! tree_fits_uhwi_p ( gimple_assign_rhs2 ( stmt ) ) ) ) return stmt ; lhs = gimple_assign_rhs1 ( stmt ) ;


<s> void <ISA_LIT>16DAGToDAGISel :: get<ISA_LIT>16SPRefReg ( SDNode * Parent , SDValue & AliasReg ) { SDValue AliasFPReg = CurDAG -> getRegister ( <STR_LIT> , TLI -> getPointerTy ( ) ) ; if ( Parent ) { switch ( Parent -> getOpcode ( ) ) { case <STR_LIT> : { LoadSDNode * SD = dyn_cast < LoadSDNode > ( Parent ) ; switch ( SD -> getMemoryVT ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : case <NUM_LIT> : AliasReg = TM . getFrameLowering ( ) -> hasFP ( * MF ) ? AliasFPReg : get<ISA_LIT>16SPAliasReg ( ) ; return ; } break ; } case <STR_LIT> : { StoreSDNode * SD = dyn_cast < StoreSDNode > ( Parent ) ; switch ( SD -> getMemoryVT ( ) . getSizeInBits ( ) ) { case <NUM_LIT> :


<s> unsigned LR = HRI . getRARegister ( ) ; if ( ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) || HMFI . hasClobberLR ( ) ) return Op ; unsigned NumOps = Op . getNumOperands ( ) ; if ( Op . getOperand ( NumOps - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) -- NumOps ; for ( unsigned i = InlineAsm :: Op_FirstOperand ; i != NumOps ; ) { unsigned Flags = cast < ConstantSDNode > ( Op . getOperand ( i ) ) -> getZExtValue ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; ++ i ; switch ( InlineAsm :: getKind ( Flags ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Kind_RegUse : case InlineAsm :: Kind_Imm : case InlineAsm :: Kind_Mem :


<s> static const unsigned CalleeSavedRegs [ ] = {


<s> if ( ! isUInt < <NUM_LIT> > ( Imm ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > ( Imm ) ) ) ; return MCDisassembler :: Success ;


<s> int StartPos = <NUM_LIT> ; for ( int i = Bits . size ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( Bits . test ( i ) ) { StartPos = i ; break ; }

for ( int i = StartPos ; i >= <NUM_LIT> ; -- i ) Result += Bits . test ( i ) ? '1' : '0' ;


<s> return ( uint8x16_t ) __builtin_neon_vmvnv16qi ( ( int8x16_t ) __a ) ;


<s> bool getHasPercentPrefix ( ) const {


<s> explicit <ISA_LIT>MCExpr ( VariantKind Kind , const MCExpr * Expr ) : Kind ( Kind ) , Expr ( Expr ) {


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSABI , IsLittle ) ;


<s> if ( isV9 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = ( isV9 ) ? <STR_LIT> : nullptr ; ZeroDirective = <STR_LIT> ;


<s> std :: unique_ptr < DCModule > <ISA_LIT>DCTranslator :: createDCModule ( Module & M ) { return make_unique < <ISA_LIT>DCModule > ( * this , M ) ;


<s> bool <ISA_LIT>TTIImpl :: enableAggressiveInterleaving ( bool LoopHasReductions ) {


<s> SOffset = CurDAG -> getRegister ( Info -> getScratchWaveOffsetReg ( ) , <STR_LIT> ) ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; if ( CurDAG -> SignBitIsZero ( N0 ) ) { ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( isLegalMUBUFImmOffset ( C1 ) ) { VAddr = N0 ; ImmOffset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return true ;


<s> uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> ) { if ( LHS . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) && isPowerOf2_64 ( LHS . getConstantOperandVal ( <NUM_LIT> ) ) ) { SDValue Test = LHS . getOperand ( <NUM_LIT> ) ; uint64_t Mask = LHS . getConstantOperandVal ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Test , DAG . getConstant ( Log2_64 ( Mask ) , dl , <STR_LIT> ) , Dest ) ; } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , Dest ) ; } else if ( CC == <STR_LIT> && LHS . getOpcode ( ) != <STR_LIT> ) { uint64_t Mask = LHS . getValueSizeInBits ( ) - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , DAG . getConstant ( Mask , dl , <STR_LIT> ) , Dest ) ; } } if ( RHSC && RHSC -> getSExtValue ( ) == - <NUM_LIT> && CC == <STR_LIT> && LHS . getOpcode ( ) != <STR_LIT> && ProduceNonFlagSettingCondBr ) { uint64_t Mask = LHS . getValueSizeInBits ( ) - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , LHS , DAG . getConstant ( Mask , dl , <STR_LIT> ) , Dest ) ; } SDValue CCVal ;

SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , CCVal , DAG , dl ) ;


<s> void <ISA_LIT>InstPrinter :: printARIIMem ( const MCInst * MI , int opNum , raw_ostream & O ) { O << '(' ; printDisp ( MI , opNum + <STR_LIT> , O ) ; O << ',' ; printOperand ( MI , opNum + <STR_LIT> , O ) ;


<s> bool <ISA_LIT>TargetLowering :: getPostIndexedAddressParts ( SDNode * N , SDNode * Op , SDValue & Base , SDValue & Offset , <STR_LIT> & AM , SelectionDAG & DAG ) const { if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; } else return false ; bool isInc ; bool isLegal = false ; if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ;


for ( int i = <NUM_LIT> ; ( i < SearchBound ) && ( MI != MBBStart ) ; ++ i , ++ MI ) for ( auto & Op : MI -> implicit_operands ( ) ) if ( ( Op . getReg ( ) == <STR_LIT> ) && ( Op . isDef ( ) ) ) return & * MI ;


<s> if ( MEM_P ( operands [ <NUM_LIT> ] ) && MEM_P ( operands [ <NUM_LIT> ] ) ) return false ; return true ;


<s> return true ; } int Opcode = getV_CMPOpcode ( Pred , Size ) ; if ( Opcode == - <NUM_LIT> ) return false ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , Dst ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( ICmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , * TRI . getBoolRC ( ) , * MRI ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) ; I . eraseFromParent ( ) ;


<s> return false ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ;


<s> static void ia64_asm_unwind_emit ( FILE * out_file , rtx_insn * insn ) { bool unwind = ia64_except_unwind_info ( & global_options ) == UI_TARGET ; bool frame = dwarf2out_do_frame ( ) ; rtx note , pat ; bool handled_one ; if ( ! unwind && ! frame ) return ; if ( NOTE_INSN_BASIC_BLOCK_P ( insn ) ) { last_block = NOTE_BASIC_BLOCK ( insn ) -> next_bb == EXIT_BLOCK_PTR_FOR_FN ( cfun ) ; if ( need_copy_state ) { if ( unwind ) { fprintf ( out_file , <STR_LIT> ) ; fprintf ( out_file , <STR_LIT> , cfun -> machine -> state_num ) ; } need_copy_state = false ; } } if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; if ( INSN_CODE ( insn ) == CODE_FOR_alloc ) { rtx dest = SET_DEST ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) ; int dest_regno = REGNO ( dest ) ; if ( dest_regno == current_frame_info . r [ reg_save_ar_pfs ] ) { if ( unwind ) fprintf ( out_file , <STR_LIT> , ia64_debugger_regno ( dest_regno ) ) ; } else { if ( current_frame_info . total_size == <NUM_LIT> && ! frame_pointer_needed ) process_epilogue ( out_file , insn , unwind , frame ) ; if ( unwind ) fprintf ( out_file , <STR_LIT> ) ; } return ; } handled_one = false ; for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , <NUM_LIT> ) ) switch ( REG_NOTE_KIND ( note ) ) { case REG_CFA_ADJUST_CFA : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) pat = PATTERN ( insn ) ; process_cfa_adjust_cfa ( out_file , pat , insn , unwind , frame ) ; handled_one = true ; break ; case REG_CFA_OFFSET : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) pat = PATTERN ( insn ) ; process_cfa_offset ( out_file , pat , unwind ) ; handled_one = true ; break ; case REG_CFA_REGISTER : pat = XEXP ( note , <NUM_LIT> ) ; if ( pat == NULL ) pat = PATTERN ( insn ) ;

process_cfa_register ( out_file , pat , unwind ) ;


<s> std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ;


<s> return DAG . getConstant ( <NUM_LIT> , Op . getValueType ( ) . getSimpleVT ( ) ) ;


<s> if ( Personality == EHPersonality :: MSVC_CXX ) { OptionalArgs . push_back ( CxxLongjmpUnwind . getCallee ( ) ) ; OptionalArgs . push_back ( State ) ; OptionalArgs . push_back ( emitEHLSDA ( Builder , & F ) ) ; } else if ( Personality == EHPersonality :: MSVC_<ISA_LIT>SEH ) { OptionalArgs . push_back ( SehLongjmpUnwind . getCallee ( ) ) ; OptionalArgs . push_back ( State ) ; if ( UseStackGuard ) OptionalArgs . push_back ( Cookie ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } SmallVector < Value * , <NUM_LIT> > Args ; Args . push_back ( Builder . CreateBitCast ( Call . getArgOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ) ; Args . push_back ( Builder . getInt32 ( OptionalArgs . size ( ) ) ) ; Args . append ( OptionalArgs . begin ( ) , OptionalArgs . end ( ) ) ; CallBase * NewCall ; if ( auto * CI = dyn_cast < CallInst > ( & Call ) ) { CallInst * NewCI = Builder . CreateCall ( SetJmp3 , Args , OpBundles ) ; NewCI -> setTailCallKind ( CI -> getTailCallKind ( ) ) ; NewCall = NewCI ; } else { auto * II = cast < InvokeInst > ( & Call ) ; NewCall = Builder . CreateInvoke ( SetJmp3 , II -> getNormalDest ( ) , II -> getUnwindDest ( ) , Args , OpBundles ) ; } NewCall -> setCallingConv ( Call . getCallingConv ( ) ) ; NewCall -> setAttributes ( Call . getAttributes ( ) ) ; NewCall -> setDebugLoc ( Call . getDebugLoc ( ) ) ; NewCall -> takeName ( & Call ) ;


<s> EVT VT = Op . getValueType ( ) ; EVT HalfVT = VT . getHalfSizedIntegerVT ( * DAG . getContext ( ) ) ; SDValue one = DAG . getConstant ( <NUM_LIT> , HalfVT ) ; SDValue zero = DAG . getConstant ( <NUM_LIT> , HalfVT ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue LHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS , zero ) ; SDValue LHS_Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS , one ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , RHS , zero ) ; SDValue RHS_Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , RHS , one ) ; if ( VT == <STR_LIT> && DAG . MaskedValueIsZero ( RHS , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) && DAG . MaskedValueIsZero ( LHS , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { SDValue Res = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( HalfVT , HalfVT ) , LHS_Lo , RHS_Lo ) ; SDValue DIV = DAG . getNode ( <STR_LIT> , DL , VT , Res . getValue ( <NUM_LIT> ) , zero ) ; SDValue REM = DAG . getNode ( <STR_LIT> , DL , VT , Res . getValue ( <NUM_LIT> ) , zero ) ; Results . push_back ( DIV ) ;


<s> void <ISA_LIT>PacketizerList :: initPacketizerState ( ) { Dependence = false ; PromotedToDotNew = false ; GlueToNewValueJump = false ; GlueAllocframeStore = false ; FoundSequentialDependence = false ; return ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> bool <ISA_LIT>Operand :: isMubufOffset ( ) const {

return isImm ( ) && isUInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> return ( __m64 ) __builtin_ia32_pfrsqrt ( ( __v2sf ) __A ) ;


<s> <ISA_LIT>SplitDoubleRegs ( ) : MachineFunctionPass ( ID ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , InstrInfo ( ) , RegInfo ( ) , FrameLowering ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) , CallLoweringInfo ( & TLInfo ) , Legalizer ( * this ) , InstSelector ( create<ISA_LIT>InstructionSelector ( TM , * this , RegBankInfo ) ) , InlineAsmLoweringInfo ( & TLInfo ) {


<s> for ( const std :: pair < unsigned , <STR_LIT> > & LiveIn : LiveInAttrs ) if ( LiveIn . first == VReg ) return LiveIn . second . isZExt ( ) ;


<s> MappingSymbolCounter = <NUM_LIT> ; MCELFStreamer :: reset ( ) ; LastMappingSymbols . clear ( ) ; LastEMSInfo . reset ( ) ; getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ;


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : getSymbol ( MO . getGlobal ( ) ) -> print ( O , MAI ) ; break ; case MachineOperand :: MO_BlockAddress : { MCSymbol * BA = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; O << BA -> getName ( ) ; break ; }

case MachineOperand :: MO_ConstantPoolIndex :


<s> int Cost = getVectorIntrinsicInstrCost ( ID , RetTy ) ; if ( Cost != - <NUM_LIT> ) return Cost ;

return BaseT :: getIntrinsicInstrCost ( ID , RetTy , Tys , FMF , ScalarizationCostPassed , I ) ;


<s> if ( TARGET_MAVERICK ) size += <NUM_LIT> ; } if ( TARGET_IWMMXT_ABI ) size += <NUM_LIT> ; } return size ;


<s> const LLT RegTy = MRI . getType ( ValVReg ) ; if ( RegTy . getSizeInBytes ( ) > Size ) Size = RegTy . getSizeInBytes ( ) ;

assignValueToAddress ( ValVReg , Addr , Size , MPO , VA ) ;


<s> auto ADRP = MIRBuilder . buildInstr ( <STR_LIT> , { LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) } , { } ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags | <STR_LIT> ) ; MRI . setRegClass ( ADRP . getReg ( <NUM_LIT> ) , & <STR_LIT> ) ; if ( OpFlags & <STR_LIT> ) { ADRP = MIRBuilder . buildInstr ( <STR_LIT> , { LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) } , { ADRP } ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: usesConstantBus ( const MachineRegisterInfo & MRI , const MachineOperand & MO , const MCOperandInfo & OpInfo ) const { if ( MO . isImm ( ) ) return ! isInlineConstant ( MO , OpInfo ) ; if ( ! MO . isReg ( ) ) return true ; if ( ! MO . isUse ( ) ) return false ; if ( MO . getReg ( ) . isVirtual ( ) ) return RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ; if ( MO . getReg ( ) == <STR_LIT> ) return false ; if ( MO . isImplicit ( ) ) {

return MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> || MO . getReg ( ) == <STR_LIT> ;


<s> assert ( Kind == Memory && <STR_LIT> ) ;


<s> if ( Constraint == <STR_LIT> ) P = PredicateConstraint :: Upl ; return P ;


<s> return ( __a - ( __b * __aarch64_vget_lane_any ( __c , __lane ) ) ) ;


<s> sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( FPFastMathMode :: NSZ ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( FPFastMathMode :: NSZ ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( FPFastMathMode :: AllowRecip ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( FPFastMathMode :: AllowRecip ) ) { nameString += sep + <STR_LIT> ;


<s> bool R600InstrInfo :: isLegalToSplitMBBAt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const { for ( MachineInstr :: const_mop_iterator I = MBBI -> operands_begin ( ) , E = MBBI -> operands_end ( ) ; I != E ; ++ I ) {

if ( I -> isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( I -> getReg ( ) ) && I -> isUse ( ) && RI . isPhysRegLiveAcrossClauses ( I -> getReg ( ) ) ) return false ;


<s> <ISA_LIT>IntelInstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


return N != nullptr ? N -> Height : <NUM_LIT> ;


<s> PredicateExtraCost = <NUM_LIT> ; break ; default : break ; } } unsigned CmpCostPerVector = ( ValTy -> getScalarType ( ) -> isFloatTy ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumVecs_cmp = getNumberOfParts ( ValTy ) ; unsigned Cost = ( NumVecs_cmp * ( CmpCostPerVector + PredicateExtraCost ) ) ; return Cost ; } else { assert ( Opcode == Instruction :: Select ) ; unsigned PackCost = <NUM_LIT> ; Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I , VF ) : nullptr ) ; if ( CmpOpTy != nullptr ) PackCost = getVectorBitmaskConversionCost ( CmpOpTy , ValTy ) ; return getNumberOfParts ( ValTy ) + PackCost ; } } else { switch ( Opcode ) { case Instruction :: ICmp : {


<s> if ( Addr . getOpcode ( ) == <STR_LIT> && ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && isInt < <NUM_LIT> > ( IMMOffset -> getZExtValue ( ) ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( IMMOffset -> getZExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ; return true ;

} else if ( ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr ) ) && isInt < <NUM_LIT> > ( IMMOffset -> getZExtValue ( ) ) ) {


<s> return addOperand ( Inst , DAsm -> decodeSrcOp ( <ISA_LIT>Disassembler :: OPW512 , Imm | <NUM_LIT> ) ) ;


<s> if ( const GlobalVariable * GV = dyn_cast < GlobalVariable > ( V ) ) Globals . insert ( GV ) ; else { if ( const User * U = dyn_cast < User > ( V ) ) { for ( unsigned i = <NUM_LIT> , e = U -> getNumOperands ( ) ; i != e ; ++ i ) { DiscoverDependentGlobals ( U -> getOperand ( i ) , Globals ) ; } } }


<s> return new <ISA_LIT>InstPrinter ( MAI , MII , MRI , T ) ;


<s> unsigned <ISA_LIT>FrameLowering :: getStackWidth ( const MachineFunction & MF ) const {


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'r' : break ; } } printOperand ( MI , OpNo ) ;


<s> int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , It , DL , HII . get ( <STR_LIT> ) , TmpR ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ; unsigned TfrOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( TfrOpc ) , DstR ) . addReg ( TmpR , RegState :: Kill ) ;


<s> if ( CC == CallingConv :: GHC ) return CC_<ISA_LIT>_GHC ; if ( CC == CallingConv :: CFGuard_Check ) return CC_<ISA_LIT>_Win64_CFGuard_Check ; return Subtarget -> isTargetDarwin ( ) ? CC_<ISA_LIT>_DarwinPCS : CC_<ISA_LIT>_AAPCS ;


<s> <ISA_LIT>AsmBackend ( const Target & T , bool isThumb , <STR_LIT> Endian ) : MCAsmBackend ( Endian ) , isThumbMode ( isThumb ) {


<s> NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; StatepointOpers SOpers ( & MI ) ; if ( unsigned PatchBytes = SOpers . getNumPatchBytes ( ) ) { emit<ISA_LIT>Nops ( * OutStreamer , PatchBytes , Subtarget ) ; } else { const MachineOperand & CallTarget = SOpers . getCallTarget ( ) ; MCOperand CallTargetMCOp ; unsigned CallOpcode ; switch ( CallTarget . getType ( ) ) { case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : CallTargetMCOp = MCIL . LowerSymbolOperand ( CallTarget , MCIL . GetSymbolFromOperand ( CallTarget ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Immediate : CallTargetMCOp = MCOperand :: createImm ( CallTarget . getImm ( ) ) ; CallOpcode = <STR_LIT> ; break ; case MachineOperand :: MO_Register : if ( Subtarget -> useIndirectThunkCalls ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default :


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ;


<s> static DecodeStatus DecodeGPRPF64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> || RegNo & <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ;


<s> case HImode : return ( ADDR_DIFF_VEC_FLAGS ( diff_vec ) . offset_unsigned ? <STR_LIT> : <STR_LIT> ) ; case SImode : return <STR_LIT> ; default : gcc_unreachable ( ) ; }


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> ( STI . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> , <STR_LIT> ( STI . getTargetABI ( ) ) ? <STR_LIT> : <STR_LIT> ) , STI ( STI ) {


<s> if ( cc == <STR_LIT> || cc == <STR_LIT> ) { cc = <STR_LIT> ; pred = <NUM_LIT> ; } SDValue Chain = DAG . getSetCC ( op . getDebugLoc ( ) , <STR_LIT> , op . getOperand ( <NUM_LIT> ) , op . getOperand ( <NUM_LIT> ) , cc ) ; if ( Chain . getNode ( ) -> getOpcode ( ) != <STR_LIT> ) { bool negateCC ; tie ( Chain , negateCC ) = ConvertSETCC ( Chain , DAG ) ; if ( negateCC ) pred = <NUM_LIT> ; } Chain = DAG . getNode ( <STR_LIT> , op . getDebugLoc ( ) , <STR_LIT> , op . getOperand ( <NUM_LIT> ) , op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( pred , <STR_LIT> ) , Chain ) ; return Chain ;


<s> if ( Sym -> isVariable ( ) ) return Sym -> getValue ( ) -> EvaluateAsRelocatable ( Res , Layout ) ; Res = MCValue :: get ( Sym , <NUM_LIT> , <NUM_LIT> ) ; return true ;


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , FramePtrReg ) . addReg ( FuncInfo -> SGPRForFPSaveRestoreCopy ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } if ( FuncInfo -> SGPRForBPSaveRestoreCopy ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , BasePtrReg ) . addReg ( FuncInfo -> SGPRForBPSaveRestoreCopy ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } if ( FPSaveIndex ) { const int FramePtrFI = * FPSaveIndex ; assert ( ! MFI . isDeadObjectIndex ( FramePtrFI ) ) ; if ( spilledToMemory ( MF , FramePtrFI ) ) { initLiveRegs ( LiveRegs , TRI , FuncInfo , MF , MBB , MBBI , false ) ; MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister ( MRI , LiveRegs , <STR_LIT> ) ; if ( ! TmpVGPR ) report_fatal_error ( <STR_LIT> ) ; buildEpilogRestore ( ST , TRI , * FuncInfo , LiveRegs , MF , MBB , MBBI , TmpVGPR , FramePtrFI ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , FramePtrReg ) . addReg ( TmpVGPR , RegState :: Kill ) ; } else { assert ( MFI . getStackID ( FramePtrFI ) == TargetStackID :: SGPRSpill ) ; ArrayRef < <ISA_LIT>MachineFunctionInfo :: SpilledReg > Spill = FuncInfo -> getSGPRToVGPRSpills ( FramePtrFI ) ; assert ( Spill . size ( ) == <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , FramePtrReg ) . addReg ( Spill [ <NUM_LIT> ] . VGPR ) . addImm ( Spill [ <NUM_LIT> ] . Lane ) ; } } if ( BPSaveIndex ) { const int BasePtrFI = * BPSaveIndex ; assert ( ! MFI . isDeadObjectIndex ( BasePtrFI ) ) ; if ( spilledToMemory ( MF , BasePtrFI ) ) { initLiveRegs ( LiveRegs , TRI , FuncInfo , MF , MBB , MBBI , false ) ; MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister ( MRI , LiveRegs , <STR_LIT> ) ; if ( ! TmpVGPR ) report_fatal_error ( <STR_LIT> ) ; buildEpilogRestore ( ST , TRI , * FuncInfo , LiveRegs , MF , MBB , MBBI , TmpVGPR , BasePtrFI ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , BasePtrReg ) . addReg ( TmpVGPR , RegState :: Kill ) ; } else { assert ( MFI . getStackID ( BasePtrFI ) == TargetStackID :: SGPRSpill ) ; ArrayRef < <ISA_LIT>MachineFunctionInfo :: SpilledReg > Spill = FuncInfo -> getSGPRToVGPRSpills ( BasePtrFI ) ; assert ( Spill . size ( ) == <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , BasePtrReg ) . addReg ( Spill [ <NUM_LIT> ] . VGPR ) . addImm ( Spill [ <NUM_LIT> ] . Lane ) ; } }


<s> default : gcc_unreachable ( ) ; } if ( ! flag_iso && cpp_get_options ( pfile ) -> lang != CLK_ASM ) { cpp_define ( pfile , <STR_LIT> ) ; cpp_define ( pfile , <STR_LIT> ) ; __vector_keyword = get_identifier ( <STR_LIT> ) ; C_CPP_HASHNODE ( __vector_keyword ) -> flags |= NODE_CONDITIONAL ; vector_keyword = get_identifier ( <STR_LIT> ) ; C_CPP_HASHNODE ( vector_keyword ) -> flags |= NODE_CONDITIONAL ;

cpp_get_callbacks ( pfile ) -> macro_to_expand = spu_macro_to_expand ;


<s> <ISA_LIT>CtorDtorLowering ( ) : ModulePass ( ID ) {