<s> Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; MVT DestVT = Op . getValueType ( ) ; if ( DestVT . bitsLT ( <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( DestVT . bitsGT ( <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub ) ;


<s> MachineOperand DestBase = MI -> getOperand ( <NUM_LIT> ) ; uint64_t DestDisp = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand SrcBase = MI -> getOperand ( <NUM_LIT> ) ; uint64_t SrcDisp = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; uint64_t Length = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( DestBase ) . addImm ( DestDisp ) . addImm ( Length ) . addOperand ( SrcBase ) . addImm ( SrcDisp ) ; MI -> eraseFromParent ( ) ;


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = std :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ;

BuildMI ( BB , DL , TII -> get ( BranchOp ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TBB ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) return false ;

return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> const MCOperand & MO0 = MI -> getOperand ( OpNo ) ; const MCOperand & MO1 = MI -> getOperand ( OpNo + <NUM_LIT> ) ;


<s> MaskLZ -= ScaleDown ; bool ReplacingAnyExtend = false ; if ( X . getOpcode ( ) == <STR_LIT> ) { unsigned ExtendBits = X . getSimpleValueType ( ) . getSizeInBits ( ) - X . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) ; X = X . getOperand ( <NUM_LIT> ) ; MaskLZ = ExtendBits > MaskLZ ? <NUM_LIT> : MaskLZ - ExtendBits ; ReplacingAnyExtend = true ; } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getSimpleValueType ( ) . getSizeInBits ( ) , MaskLZ ) ; KnownBits Known = DAG . computeKnownBits ( X ) ; if ( MaskedHighBits != Known . Zero ) return true ; MVT VT = N . getSimpleValueType ( ) ; if ( ReplacingAnyExtend ) { assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , SDLoc ( X ) , VT , X ) ; insertDAGNode ( DAG , N , NewX ) ; X = NewX ; } SDLoc DL ( N ) ;

SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , DL , <STR_LIT> ) ;


<s> } unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , DL , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; }

int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ;


<s> explicit <ISA_LIT>MCExpr ( VariantKind Kind , const MCExpr * Expr ) : Kind ( Kind ) , Expr ( Expr ) {


<s> static unsigned getRegForName ( StringRef RegName ) { return StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand & MO ) const ;

MCSymbol * GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const ;


<s> static DecodeStatus decodeUImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const void * Decoder ) {

assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ;


<s> if ( instr -> getOpcode ( ) == AMDGPU :: RETURN ) return instr ; } return NULL ;


<s> calc_live_regs ( & d , live_regs_mask ) ; if ( target_flags != save_flags ) emit_insn ( gen_toggle_sz ( ) ) ; if ( TARGET_SH5 ) { int i ; int offset ; int align ; rtx r0 = gen_rtx_REG ( Pmode , R0_REG ) ; int offset_in_r0 = - <NUM_LIT> ; int sp_in_r0 = <NUM_LIT> ; if ( d % ( STACK_BOUNDARY / BITS_PER_UNIT ) ) d_rounding = ( ( STACK_BOUNDARY / BITS_PER_UNIT ) - d % ( STACK_BOUNDARY / BITS_PER_UNIT ) ) ; offset = d + d_rounding ; output_stack_adjust ( - offset , stack_pointer_rtx , <NUM_LIT> ) ; for ( align = <NUM_LIT> ; align >= <NUM_LIT> ; align -- ) for ( i = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( live_regs_mask [ i / <NUM_LIT> ] & ( <NUM_LIT> << ( i % <NUM_LIT> ) ) ) { enum machine_mode mode = REGISTER_NATURAL_MODE ( i ) ; int reg = i ; rtx reg_rtx , mem_rtx , pre_dec = NULL_RTX ; if ( mode == SFmode && ( i % <NUM_LIT> ) == <NUM_LIT> && ! TARGET_FPU_SINGLE && FP_REGISTER_P ( i ) && ( live_regs_mask [ ( i ^ <NUM_LIT> ) / <NUM_LIT> ] & ( <NUM_LIT> << ( ( i ^ <NUM_LIT> ) % <NUM_LIT> ) ) ) ) { mode = DFmode ; i -- ; reg -- ; } if ( ( GET_MODE_SIZE ( mode ) % ( STACK_BOUNDARY / BITS_PER_UNIT ) == <NUM_LIT> ) != align ) continue ; offset -= GET_MODE_SIZE ( mode ) ; reg_rtx = gen_rtx_REG ( mode , reg ) ; mem_rtx = gen_rtx_MEM ( mode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ) ; GO_IF_LEGITIMATE_ADDRESS ( mode , XEXP ( mem_rtx , <NUM_LIT> ) , try_pre_dec ) ; mem_rtx = NULL_RTX ; try_pre_dec : do if ( HAVE_PRE_DECREMENT && ( offset_in_r0 - offset == GET_MODE_SIZE ( mode ) || mem_rtx == NULL_RTX || i == PR_REG || SPECIAL_REGISTER_P ( i ) ) ) { pre_dec = gen_rtx_MEM ( mode , gen_rtx_PRE_DEC ( Pmode , r0 ) ) ; GO_IF_LEGITIMATE_ADDRESS ( mode , XEXP ( pre_dec , <NUM_LIT> ) , pre_dec_ok ) ; pre_dec = NULL_RTX ; break ; pre_dec_ok : mem_rtx = NULL_RTX ; offset += GET_MODE_SIZE ( mode ) ; } while ( <NUM_LIT> ) ; if ( mem_rtx != NULL_RTX ) goto addr_ok ; if ( offset_in_r0 == - <NUM_LIT> ) { emit_move_insn ( r0 , GEN_INT ( offset ) ) ; offset_in_r0 = offset ; } else if ( offset != offset_in_r0 ) { emit_move_insn ( r0 , gen_rtx_PLUS ( Pmode , r0 , GEN_INT ( offset - offset_in_r0 ) ) ) ; offset_in_r0 += offset - offset_in_r0 ; } if ( pre_dec != NULL_RTX ) { if ( ! sp_in_r0 ) { emit_move_insn ( r0 , gen_rtx_PLUS ( Pmode , r0 , stack_pointer_rtx ) ) ; sp_in_r0 = <NUM_LIT> ; } offset -= GET_MODE_SIZE ( mode ) ;

offset_in_r0 -= GET_MODE_SIZE ( mode ) ;


<s> OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } else { OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_bit_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; EmitULEB128 ( <NUM_LIT> ) ; } } else if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) { assert ( <STR_LIT> + <NUM_LIT> == <STR_LIT> && <STR_LIT> ) ; unsigned QReg = Reg - <STR_LIT> ; unsigned D1 = <NUM_LIT> + <NUM_LIT> * QReg ; unsigned D2 = D1 + <NUM_LIT> ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_regx ) ; EmitULEB128 ( D1 ) ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_piece ) ; EmitULEB128 ( <NUM_LIT> ) ; OutStreamer . AddComment ( <STR_LIT> ) ; EmitInt8 ( dwarf :: DW_OP_regx ) ; EmitULEB128 ( D2 ) ;


<s> bool MakeProgress = false ; int NumRemainedBlk = countActiveBlock ( OrderedBlks . begin ( ) , OrderedBlks . end ( ) ) ; do { ++ NumIter ; DEBUG ( dbgs ( ) << <STR_LIT> << NumIter << <STR_LIT> << NumRemainedBlk << <STR_LIT> ; ) ; SmallVectorImpl < MachineBasicBlock * > :: const_iterator It = OrderedBlks . begin ( ) ; SmallVectorImpl < MachineBasicBlock * > :: const_iterator E = OrderedBlks . end ( ) ; SmallVectorImpl < MachineBasicBlock * > :: const_iterator SccBeginIter = It ; MachineBasicBlock * SccBeginMBB = nullptr ; int SccNumBlk = <NUM_LIT> ; int SccNumIter ; while ( It != E ) { MBB = * It ; if ( ! SccBeginMBB ) { SccBeginIter = It ; SccBeginMBB = MBB ; SccNumIter = <NUM_LIT> ; SccNumBlk = NumRemainedBlk ; DEBUG ( dbgs ( ) << <STR_LIT> << getSCCNum ( SccBeginMBB ) ; dbgs ( ) << <STR_LIT> ; ) ; } if ( ! isRetiredBlock ( MBB ) ) patternMatch ( MBB ) ; ++ It ; bool ContNextScc = true ; if ( It == E || getSCCNum ( SccBeginMBB ) != getSCCNum ( * It ) ) { ++ SccNumIter ; int sccRemainedNumBlk = countActiveBlock ( SccBeginIter , It ) ; if ( sccRemainedNumBlk != <NUM_LIT> && sccRemainedNumBlk >= SccNumBlk ) { DEBUG ( dbgs ( ) << <STR_LIT> << getSCCNum ( MBB ) << <STR_LIT> << SccNumIter ; dbgs ( ) << <STR_LIT> ; ) ;


<s> return TargetTriple . isPS4CPU ( ) ;


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const { assert ( Pred1 . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Pred2 . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Pred1 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred1 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ;

if ( Pred2 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Pred2 [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ;


<s> Triple TheTriple ( TT ) ; if ( TheTriple . getArch ( ) == Triple :: nvptx64 ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _andn_u64 ( unsigned long long __X , unsigned long long __Y ) { return __andn_u64 ( __X , __Y ) ;


<s> const MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; assert ( MFI . getObjectSize ( FrameIdx ) >= TRI -> getSpillSize ( * RC ) && <STR_LIT> ) ; if ( RC -> getID ( ) == <STR_LIT> ) { unsigned Opc = <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; Register VirtReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MI , DebugLoc ( ) , get ( <STR_LIT> ) , VirtReg ) . addImm ( <NUM_LIT> ) ; MachineInstr * NewMI = addFrameReference ( BuildMI ( MBB , MI , DebugLoc ( ) , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; MachineOperand & MO = NewMI -> getOperand ( <NUM_LIT> ) ; MO . setReg ( VirtReg ) ; MO . setIsKill ( true ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( getCheriHWRegsReg ( ) ) ) ;


<s> if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : { PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = MaybeAlign ( DL . getABITypeAlignment ( PtrTy -> getElementType ( ) ) ) ; Info . flags = MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ;


<s> if ( MF . getFunction ( ) . hasMinSize ( ) ) return false ; return true ;


<s> gcc_assert ( GET_CODE ( parallel_rtx ) == PARALLEL ) ;

return XVECLEN ( parallel_rtx , <NUM_LIT> ) ;


<s> assert ( Kind == k_Memri && <STR_LIT> ) ;

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> ConstReg = TRI -> lookThruCopyLike ( Root . getOperand ( FirstMulOpIdx ) . getReg ( ) , MRI ) ; break ; case MachineCombinerPattern :: REASSOC_XY_BAC : ConstReg = TRI -> lookThruCopyLike ( Root . getOperand ( FirstMulOpIdx + <NUM_LIT> ) . getReg ( ) , MRI ) ; break ; default : return ; } MachineInstr * ConstDefInstr = MRI -> getVRegDef ( ConstReg ) ; const Constant * C = getConstantFromConstantPool ( ConstDefInstr ) ; assert ( isa < llvm :: ConstantFP > ( C ) && <STR_LIT> ) ; APFloat F1 ( ( dyn_cast < ConstantFP > ( C ) ) -> getValueAPF ( ) ) ; F1 . changeSign ( ) ; Constant * NegC = ConstantFP :: get ( dyn_cast < ConstantFP > ( C ) -> getContext ( ) , F1 ) ; Align Alignment = MF -> getDataLayout ( ) . getPrefTypeAlign ( C -> getType ( ) ) ; unsigned ConstPoolIdx = MCP -> getConstantPoolIndex ( NegC , Alignment ) ; MachineOperand * Placeholder = nullptr ; for ( auto * Inst : InsInstrs ) { for ( MachineOperand & Operand : Inst -> explicit_operands ( ) ) { assert ( Operand . isReg ( ) && <STR_LIT> ) ; if ( Operand . getReg ( ) == <STR_LIT> ) { Placeholder = & Operand ;


<s> CCState RetCCInfo ( CallConv , IsVarArg , MF , RetLocs , * DAG . getContext ( ) ) ; RetCCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( RetLocs . empty ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ; if ( CallConv == CallingConv :: GHC ) report_fatal_error ( <STR_LIT> ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; for ( unsigned I = <NUM_LIT> , E = RetLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = RetLocs [ I ] ; SDValue RetValue = OutVals [ I ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetValue = convertValVTToLocVT ( DAG , DL , VA , RetValue ) ; Register Reg = VA . getLocReg ( ) ; Chain = DAG . getCopyToReg ( Chain , DL , Reg , RetValue , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( Reg , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Glue . getNode ( ) ) RetOps . push_back ( Glue ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RetOps ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : case <STR_LIT> : { unsigned Size = getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ;

if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ) Size = alignTo ( Size , <NUM_LIT> ) ;


__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> static DecodeStatus DecodeMainLoRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return MCDisassembler :: Success ;


<s> if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case <STR_LIT> : case <STR_LIT> : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case <STR_LIT> :

if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TTI :: TCC_Free ;


<s> std :: vector < std :: string > sub_p1 ( Ax b ) { return D ( <STR_LIT> , <STR_LIT> , R ( b ) ) ;


<s> O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID : case Type :: VectorTyID : ElementSize = TD -> getTypeStoreSize ( ETy ) ; O << <STR_LIT> << * getSymbol ( GVar ) << <STR_LIT> ; if ( ElementSize ) { O << itostr ( ElementSize ) ; } O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerLoad ( Op , DAG ) ; case <STR_LIT> : return LowerStore ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerUAddSubO ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAddSubCarry ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ;

case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;


<s> if ( DestVT == <STR_LIT> ) DestVT = Op0 . getValueType ( ) ; return DAG . getNode ( <STR_LIT> , dl , DestVT , DAG . getConstant ( IID , <STR_LIT> ) , Op0 , Op1 , Op2 ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . LastADRP ) ; AFI . addLOHDirective ( MCLOH_AdrpAdrp , { & MI , Info . LastADRP } ) ; ++ NumADRPSimpleCandidate ; } if ( Info . IsCandidate ) { switch ( Info . Type ) { case MCLOH_AdrpAdd : { const MachineInstr * AddMI = Info . MI0 ; int DefIdx = mapRegToGPRIndex ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; int OpIdx = mapRegToGPRIndex ( AddMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LOHInfo DefInfo = LOHInfos [ OpIdx ] ; if ( DefIdx != OpIdx && ( DefInfo . OneUser || DefInfo . MultiUsers ) ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpAdd , { & MI , Info . MI0 } ) ; ++ NumADRSimpleCandidate ; break ; } case MCLOH_AdrpLdr : if ( supportLoadFromLiteral ( * Info . MI0 ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpLdr , { & MI , Info . MI0 } ) ; ++ NumADRPToLDR ; } break ; case MCLOH_AdrpAddLdr : { MachineInstr * AddMI = const_cast < MachineInstr * > ( Info . MI1 ) ; const MachineInstr * LdrMI = Info . MI0 ; auto AddIt = MachineBasicBlock :: iterator ( AddMI ) ; auto EndIt = AddMI -> getParent ( ) -> end ( ) ; if ( AddMI -> getIterator ( ) == EndIt || LdrMI != & * next_nodbg ( AddIt , EndIt ) ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\t' << * Info . MI1 << '\t' << * Info . MI0 ) ; AFI . addLOHDirective ( MCLOH_AdrpAddLdr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumADDToLDR ; break ; } case MCLOH_AdrpAddStr :


<s> return ! ( optimize > <NUM_LIT> && crtl -> is_leaf && only_leaf_regs_used ( ) ) ;


<s> return new <ISA_LIT>ShiftExpand ( ) ;


<s> assert ( ( SZ == <NUM_LIT> || SZ == <NUM_LIT> ) && <STR_LIT> ) ; <STR_LIT> IntID = ( SZ == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Value * Fn = <STR_LIT> ( M , IntID ) ; Value * Call = Builder . CreateCall ( Fn , { Addr , Val } , <STR_LIT> ) ; Value * Cmp = Builder . CreateICmpEQ ( Call , Builder . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ; Value * Ext = Builder . CreateZExt ( Cmp , Type :: getInt32Ty ( M -> getContext ( ) ) ) ;


<s> static unsigned getFixupKindLog2Size ( unsigned Kind ) { switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_PCRel_1 : case FK_SecRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_SecRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { getTargetStreamer ( ) . emitCCTopFunction ( CurrentFnSym -> getName ( ) ) ;

OutStreamer -> EmitLabel ( CurrentFnSym ) ;


<s> std :: tie ( NewFunc , ImplicitOffset ) = addOffsetArgumentToFunction ( M , Caller ) ; } if ( ! CalleeWithImplicitParam ) { CallToOld -> replaceAllUsesWith ( ImplicitOffset ) ; } else { llvm :: SmallVector < Value * , <NUM_LIT> > ImplicitOffsets ; for ( Use & U : CallToOld -> args ( ) ) { ImplicitOffsets . push_back ( U ) ; } ImplicitOffsets . push_back ( ImplicitOffset ) ; auto NewCaller = CallInst :: Create ( CalleeWithImplicitParam -> getFunctionType ( ) , CalleeWithImplicitParam , ImplicitOffsets , Twine ( ) , CallToOld ) ; NewCaller -> setTailCallKind ( CallToOld -> getTailCallKind ( ) ) ; NewCaller -> copyMetadata ( * CallToOld ) ; CallToOld -> replaceAllUsesWith ( NewCaller ) ; if ( CallToOld -> hasName ( ) ) { NewCaller -> takeName ( CallToOld ) ; } } CallToOld -> eraseFromParent ( ) ; if ( ! AlreadyProcessed ) { addImplicitParameterToCallers ( M , Caller , NewFunc ) ; Caller -> dropAllReferences ( ) ; Caller -> eraseFromParent ( ) ;


<s> if ( NumNonZero > <NUM_LIT> && ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; return LowerBuildVectorAsInsert ( Op , NonZeroMask , NumNonZero , NumZero , DAG , Subtarget ) ;


<s> Opnds . push_back ( Zero ) ; Opnds . push_back ( Addr . getOperand ( <NUM_LIT> ) ) ; unsigned SubOp = <STR_LIT> ; if ( Subtarget -> hasAddNoCarry ( ) ) { SubOp = <STR_LIT> ; Opnds . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) ) ; } MachineSDNode * MachineSub = CurDAG -> getMachineNode ( SubOp , DL , <STR_LIT> , Opnds ) ; Base = SDValue ( MachineSub , <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( ByteOffset , DL , <STR_LIT> ) ; return true ; } } } } else if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { SDLoc DL ( Addr ) ; if ( isUInt < <NUM_LIT> > ( CAddr -> getZExtValue ( ) ) ) { SDValue Zero = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; MachineSDNode * MovZero = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero ) ; Base = SDValue ( MovZero , <NUM_LIT> ) ;

Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT> ) ;


<s> if ( ! Value ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; MCContext & Ctx = Asm . getContext ( ) ; Value = adjustFixupValue ( Fixup , Value , Ctx , TheTriple , IsResolved ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes ( Fixup . getKind ( ) ) ; if ( FulleSizeInBytes == <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; } } else { assert ( ( Offset + FulleSizeInBytes ) <= Data . size ( ) && <STR_LIT> ) ; assert ( NumBytes <= FulleSizeInBytes && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = FulleSizeInBytes - <NUM_LIT> - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; } }


<s> bool <ISA_LIT>LibCalls :: useNativeFunc ( const StringRef F ) const {

return AllNative || llvm :: is_contained ( UseNative , F ) ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , LoPart , Zero ) ;

if ( isPIC ) Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , DL , PtrVT ) , Hi ) ;


<s> MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( copy1MBB ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI . eraseFromParent ( ) ;


return ( __m128 ) __builtin_ia32_rsqrtps ( ( __v4sf ) __A ) ;


<s> if ( Cond . empty ( ) ) return true ; assert ( Cond [ <NUM_LIT> ] . isImm ( ) && <STR_LIT> ) ;

unsigned opcode = Cond [ <NUM_LIT> ] . getImm ( ) ;


<s> static void setAquired ( AquiredVec & Aquired , const Vagon & V ) { std :: fill ( Aquired . begin ( ) + V . TopIdx , Aquired . begin ( ) + V . DeepIdx + <NUM_LIT> , true ) ;


<s> MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ;


<s> bool FoldAsMAD = tryAddToFoldList ( FoldList , MI , OpNo , OpToFold , TII ) ; if ( FoldAsMAD ) { MI -> untieRegOperand ( OpNo ) ; return true ; } MI -> setDesc ( TII -> get ( Opc ) ) ; } if ( OpToFold -> isImm ( ) ) { unsigned ImmOpc = <NUM_LIT> ; if ( Opc == <STR_LIT> ) ImmOpc = <STR_LIT> ; else if ( Opc == <STR_LIT> ) ImmOpc = <STR_LIT> ; if ( ImmOpc ) { MI -> setDesc ( TII -> get ( ImmOpc ) ) ; appendFoldCandidate ( FoldList , MI , OpNo , OpToFold ) ; return true ; } } if ( isUseMIInFoldList ( FoldList , MI ) ) return false ; unsigned CommuteOpNo = OpNo ; unsigned CommuteIdx0 = TargetInstrInfo :: CommuteAnyOperandIndex ; unsigned CommuteIdx1 = TargetInstrInfo :: CommuteAnyOperandIndex ; bool CanCommute = TII -> findCommutedOpIndices ( * MI , CommuteIdx0 , CommuteIdx1 ) ; if ( CanCommute ) { if ( CommuteIdx0 == OpNo ) CommuteOpNo = CommuteIdx1 ; else if ( CommuteIdx1 == OpNo ) CommuteOpNo = CommuteIdx0 ; } if ( CanCommute && ( ! MI -> getOperand ( CommuteIdx0 ) . isReg ( ) || ! MI -> getOperand ( CommuteIdx1 ) . isReg ( ) ) ) return false ; if ( ! CanCommute || ! TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ) return false ; if ( ! TII -> isOperandLegal ( * MI , CommuteOpNo , OpToFold ) ) { if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( OpToFold -> isImm ( ) || OpToFold -> isFI ( ) || OpToFold -> isGlobal ( ) ) ) { MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; unsigned OtherIdx = CommuteOpNo == CommuteIdx0 ? CommuteIdx1 : CommuteIdx0 ; MachineOperand & OtherOp = MI -> getOperand ( OtherIdx ) ; if ( ! OtherOp . isReg ( ) || ! TII -> getRegisterInfo ( ) . isVGPR ( MRI , OtherOp . getReg ( ) ) ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isDef ( ) ) ; unsigned MaybeCommutedOpc = MI -> getOpcode ( ) ;

int Op32 = <STR_LIT> ( MaybeCommutedOpc ) ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Target & T , const StringRef & TT ) { GlobalDirective = <STR_LIT> ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; AsciiDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; CommentString = <STR_LIT> ; AllowPeriodsInName = false ;


<s> static const int Table = ( int ( RoundingMode :: NearestTiesToEven ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardZero ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardNegative ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: TowardPositive ) << <NUM_LIT> * <STR_LIT> ) | ( int ( RoundingMode :: NearestTiesToAway ) << <NUM_LIT> * <STR_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RM , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;

SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( Table , DL , XLenVT ) , Shift ) ;


<s> Old . ChangeToImmediate ( Fold . ImmToFold ) ; return true ; } if ( Fold . isFI ( ) ) { Old . ChangeToFrameIndex ( Fold . FrameIndexToFold ) ; return true ; } MachineOperand * New = Fold . OpToFold ;

if ( TargetRegisterInfo :: isVirtualRegister ( Old . getReg ( ) ) && TargetRegisterInfo :: isVirtualRegister ( New -> getReg ( ) ) ) {


<s> } else base = XEXP ( ref , <NUM_LIT> ) ;

if ( GET_CODE ( base ) == PLUS ) offset += INTVAL ( XEXP ( base , <NUM_LIT> ) ) , base = XEXP ( base , <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3OMods ( SDValue In , SDValue & Src , SDValue & Clamp , SDValue & Omod ) const {


<s> bool <ISA_LIT>DAGToDAGISel :: selectIntAddr ( SDValue Addr , SDValue & Base , SDValue & Offset ) const {

return selectAddrRegImm ( Addr , Base , Offset ) || selectAddrDefault ( Addr , Base , Offset ) ;


<s> void <ISA_LIT>InstPrinter :: printExtendedRegister ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {

O << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) ;


<s> static SDValue PerformLOADCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && <STR_LIT> ( N ) && VT . isVector ( ) && DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return CombineBaseUpdate ( N , DCI ) ; return SDValue ( ) ;


<s> if ( MI -> hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineBasicBlock :: iterator I = MI ; ++ I ; MachineBasicBlock :: iterator E = MI -> getParent ( ) -> end ( ) ; while ( I != E && I -> isDebugInstr ( ) ) ++ I ;


<s> SDLoc dl ( Op ) ; return DAG . getNode ( Op . getOpcode ( ) , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ) ; } if ( VT . getSizeInBits ( ) < InVT . getSizeInBits ( ) ) { SDLoc dl ( Op ) ; SDValue Cv = DAG . getNode ( Op . getOpcode ( ) , dl , InVT . changeVectorElementTypeToInteger ( ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Cv ) ;


<s> case MODE_INT : if ( precision == CHAR_TYPE_SIZE ) return true ; if ( precision == SHORT_TYPE_SIZE ) return true ; if ( precision == INT_TYPE_SIZE ) return true ;

if ( precision == LONG_TYPE_SIZE ) return true ;


<s> return ( vec_sel ( __A , c , mask ) ) ; __A [ <NUM_LIT> ] = __A [ <NUM_LIT> ] / __B [ <NUM_LIT> ] ;


<s> const MCPhysReg * CSRegs = TRI . getCalleeSavedRegs ( & MF ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) LiveRegs . addReg ( CSRegs [ i ] ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; for ( unsigned Reg : RC ) { if ( LiveRegs . available ( MRI , Reg ) ) return Reg ;


<s> DebugLoc DL = MBBI -> getDebugLoc ( ) ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> for ( MachineBasicBlock :: succ_iterator I = MBB -> succ_begin ( ) , E = MBB -> succ_end ( ) ; I != E ; ++ I ) if ( * I != Succ ) return * I ;


<s> getDebugValueLocation ( const MachineInstr * MI ) const {


<s> Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op ) ; } SDVTList VTs = DAG . getVTList ( OpVT , <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VTs , Op ) ;

Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , dl , OpVT ) ) ;


<s> vmls_n_s32 ( int32x2_t a , int32x2_t b , int32_t c ) {


<s> assert ( ( Kind == Immediate || Kind == ContextImmediate ) && <STR_LIT> ) ; if ( Kind == Immediate ) return Imm . Val ; return static_cast < int16_t > ( Imm . Val ) ;


<s> if ( & MF -> front ( ) == MBB ) return <STR_LIT> ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>RegisterInfo & TRI = * Subtarget . getRegisterInfo ( ) ; LivePhysRegs LiveRegs ( TRI ) ; LiveRegs . addLiveIns ( * MBB ) ; const MCPhysReg * CSRegs = TRI . getCalleeSavedRegs ( MF ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) LiveRegs . addReg ( CSRegs [ i ] ) ;

const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ;


<s> <ISA_LIT>IncomingArgsHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI ) : <ISA_LIT>IncomingValueHandler ( MIRBuilder , MRI ) {


<s> } break ; case <STR_LIT> : case <STR_LIT> : { if ( ( AddConstant >= <NUM_LIT> && CompConstant <= <NUM_LIT> ) || ( AddConstant <= <NUM_LIT> && CompConstant >= <NUM_LIT> && CompConstant <= AddConstant + MaxUInt ) ) return true ; } break ; case <STR_LIT> : case <STR_LIT> : { if ( ( AddConstant > <NUM_LIT> && CompConstant < <NUM_LIT> ) || ( AddConstant < <NUM_LIT> && CompConstant >= <NUM_LIT> && CompConstant < AddConstant + MaxUInt ) || ( AddConstant >= <NUM_LIT> && CompConstant >= <NUM_LIT> && CompConstant >= AddConstant ) || ( AddConstant <= <NUM_LIT> && CompConstant < <NUM_LIT> && CompConstant < AddConstant ) ) return true ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> bool IsDangerousLoad ( const MachineInstr & MI , int * AddrIdx ) { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> uint64_t THMTo<ISA_LIT>Stub :: initSymValue ( ) const { return <NUM_LIT> ;


<s> } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; const char * Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: Create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateAdd ( PCRelExpr , MCConstantExpr :: Create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateSub ( PCRelExpr , DotExpr , OutContext ) ;


<s> if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Location . set ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; else { DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; } return Location ;


<s> if ( ! CONSTANT_P ( in ) ) { regno = true_regnum ( in ) ; if ( regno == - <NUM_LIT> || regno >= FIRST_PSEUDO_REGISTER ) code = MEM ; } if ( code == MEM ) return SQI_REGS ; return NO_REGS ;


<s> Op -> VectorIndex . Val = Idx ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> } auto I = <STR_LIT> ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addImm ( Mask ) , FI ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; for ( const auto & Info : CSI ) { I . addReg ( Info . getReg ( ) , RegState :: ImplicitDefine ) ;

<STR_LIT> ( I , Info . getFrameIdx ( ) , <NUM_LIT> ) ;


<s> void setManipulatesSP ( bool MSP ) { ManipulatesSP = MSP ;


<s> return BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( ResVReg ) . addUse ( GR . get<ISA_LIT>TypeID ( ResType ) ) . addImm ( static_cast < uint32_t > ( <STR_LIT> :: Function ) ) . constrainAllUses ( TII , TRI , RBI ) ;


<s> static int supersparc_adjust_cost ( rtx_insn * insn , rtx link , rtx_insn * dep_insn , int cost ) { enum attr_type insn_type ; if ( ! recog_memoized ( insn ) ) return <NUM_LIT> ; insn_type = get_attr_type ( insn ) ; if ( REG_NOTE_KIND ( link ) == <NUM_LIT> ) {

if ( insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD ) return cost + <NUM_LIT> ;


<s> unsigned getNumFixupKinds ( ) const {


<s> if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . add ( Cond [ <NUM_LIT> ] ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . add ( Cond [ <NUM_LIT> ] ) ; if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( FBB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( FBB ) ; return <NUM_LIT> ;


<s> if ( TARGET_DEBUG_B_MODE ) { GO_PRINTF ( <STR_LIT> ) ; GO_DEBUG_RTX ( xinsn ) ; } if ( iq2000_check_split ( xinsn , mode ) ) { return gen_rtx_LO_SUM ( Pmode , copy_to_mode_reg ( Pmode , gen_rtx_HIGH ( Pmode , xinsn ) ) , xinsn ) ; } if ( GET_CODE ( xinsn ) == PLUS ) { rtx xplus0 = XEXP ( xinsn , <NUM_LIT> ) ; rtx xplus1 = XEXP ( xinsn , <NUM_LIT> ) ; enum rtx_code code0 = GET_CODE ( xplus0 ) ; enum rtx_code code1 = GET_CODE ( xplus1 ) ; if ( code0 != REG && code1 == REG ) { xplus0 = XEXP ( xinsn , <NUM_LIT> ) ; xplus1 = XEXP ( xinsn , <NUM_LIT> ) ; code0 = GET_CODE ( xplus0 ) ; code1 = GET_CODE ( xplus1 ) ; } if ( code0 == REG && REG_MODE_OK_FOR_BASE_P ( xplus0 , mode ) && code1 == CONST_INT && ! SMALL_INT ( xplus1 ) ) { rtx int_reg = gen_reg_rtx ( Pmode ) ; rtx ptr_reg = gen_reg_rtx ( Pmode ) ; emit_move_insn ( int_reg , GEN_INT ( INTVAL ( xplus1 ) & ~ <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , ptr_reg , gen_rtx_PLUS ( Pmode , xplus0 , int_reg ) ) ) ;

return plus_constant ( Pmode , ptr_reg , INTVAL ( xplus1 ) & <NUM_LIT> ) ;


<s> assert ( useRVVForFixedLengthVectorVT ( OpVT ) && <STR_LIT> ) ; Ops . push_back ( convertToScalableVector ( ContainerVT , V , DAG , Subtarget ) ) ; } if ( ! VT . isFixedLengthVector ( ) ) return DAG . getNode ( <ISA_LIT>ISDOpc , DL , VT , Ops ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ;

SDValue VPOp = DAG . getNode ( <ISA_LIT>ISDOpc , DL , ContainerVT , Ops ) ;


<s> return ( int16x4_t ) __builtin_neon_vrshlsv4hi ( __a , __b ) ;


<s> if ( ! MI . mayLoadOrStore ( ) ) return false ; assert ( MI . hasOneMemOperand ( ) && <STR_LIT> ) ;

return ( * MI . memoperands_begin ( ) ) -> getSize ( ) == NumBytes ;


<s> <ISA_LIT>AsmBackend ( const Target & T , const Triple & TT , uint8_t OSABI , StringRef CPU ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( OSABI ) , CPU ( CPU ) , MCII ( T . createMCInstrInfo ( ) ) , RelaxTarget ( new MCInst * ) , Extender ( nullptr ) {


<s> for ( unsigned i = <NUM_LIT> , n = MI -> getNumOperands ( ) ; i < n ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ;

if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ;


<s> } if ( bbApproxSize < <NUM_LIT> ) { CriticalPathLength >>= <NUM_LIT> ; return ; } unsigned MaxPath = <NUM_LIT> ; for ( auto & SU : DAG -> SUnits ) MaxPath = std :: max ( MaxPath , isTop ( ) ? SU . getHeight ( ) : SU . getDepth ( ) ) ; CriticalPathLength = std :: max ( CriticalPathLength , MaxPath ) + <NUM_LIT> ;


<s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ;

if ( isa < FixedVectorType > ( DataType ) && DataType -> getScalarSizeInBits ( ) > ST -> getMaxELENForFixedLengthVectors ( ) ) return false ;


<s> unsigned BaseRegB = getBaseAndOffset ( MIb , OffsetB , SizeB ) ; if ( ! BaseRegB || ! SizeB ) return false ; if ( BaseRegA != BaseRegB ) return false ; if ( OffsetA > OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetA - ( int64_t ) OffsetB ) ; return ( SizeB <= offDiff ) ; } else if ( OffsetA < OffsetB ) { uint64_t offDiff = ( uint64_t ) ( ( int64_t ) OffsetB - ( int64_t ) OffsetA ) ; return ( SizeA <= offDiff ) ; }


<s> NumElts = RegVT . getVectorNumElements ( ) ; SubregIdx = ( Lane < NumElts ) ? <STR_LIT> : <STR_LIT> ; } unsigned OpcodeIndex ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : OpcodeIndex = <NUM_LIT> ; break ; } SDValue Pred = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue PredReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( MemAddr ) ; Ops . push_back ( MemUpdate ) ; Ops . push_back ( MemOpc ) ; Ops . push_back ( Align ) ; unsigned Opc = <NUM_LIT> ; if ( is64BitVector ) { Opc = DOpcodes [ OpcodeIndex ] ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) Ops . push_back ( N -> getOperand ( Vec + <NUM_LIT> ) ) ; } else { if ( Lane < NumElts ) { Opc = QOpcodes0 [ OpcodeIndex ] ; } else { Lane -= NumElts ; Opc = QOpcodes1 [ OpcodeIndex ] ; } for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) Ops . push_back ( CurDAG -> getTargetExtractSubreg ( SubregIdx , dl , RegVT , N -> getOperand ( Vec + <NUM_LIT> ) ) ) ; } Ops . push_back ( getI32Imm ( Lane ) ) ; Ops . push_back ( Pred ) ; Ops . push_back ( PredReg ) ; Ops . push_back ( Chain ) ; if ( ! IsLoad ) return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops . data ( ) , NumVecs + <NUM_LIT> ) ; std :: vector < EVT > ResTys ( NumVecs , RegVT ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * VLdLn = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops . data ( ) , NumVecs + <NUM_LIT> ) ; if ( is64BitVector ) return VLdLn ; for ( unsigned Vec = <NUM_LIT> ; Vec < NumVecs ; ++ Vec ) {

SDValue QuadVec = CurDAG -> getTargetInsertSubreg ( SubregIdx , dl , VT , N -> getOperand ( Vec + <NUM_LIT> ) , SDValue ( VLdLn , Vec ) ) ;


<s> sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; nds32_emit_pop_fpr_callee_saved ( gpr_padding ) ; } else { sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ; nds32_emit_adjust_frame ( stack_pointer_rtx , stack_pointer_rtx , sp_adjust ) ; } } if ( cfun -> machine -> use_eh_return_p ) { Rb = cfun -> machine -> eh_return_data_first_regno ; Re = cfun -> machine -> eh_return_data_last_regno ; nds32_emit_stack_pop_multiple ( Rb , Re , false , false , false ) ; } Rb = cfun -> machine -> callee_saved_first_gpr_regno ; Re = cfun -> machine -> callee_saved_last_gpr_regno ; if ( ! ( Rb == SP_REGNUM && Re == SP_REGNUM && cfun -> machine -> fp_size == <NUM_LIT> && cfun -> machine -> gp_size == <NUM_LIT> && cfun -> machine -> lp_size == <NUM_LIT> ) ) { nds32_emit_stack_pop_multiple ( Rb , Re , cfun -> machine -> fp_size , cfun -> machine -> gp_size , cfun -> machine -> lp_size ) ;


<s> int v9_regcmp_p ( enum rtx_code code ) { return ( code == EQ || code == NE || code == GE || code == LT || code == LE || code == GT ) ;


<s> if ( ( reg_classes_intersect_p ( from , GENERAL_REGS ) && reg_classes_intersect_p ( to , FP_REGS ) ) || ( reg_classes_intersect_p ( from , FP_REGS ) && reg_classes_intersect_p ( to , GENERAL_REGS ) ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> void <ISA_LIT>TargetStreamer :: emitUnwindRaw ( int64_t StackOffset , const SmallVectorImpl < uint8_t > & Opcodes ) {


<s> <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( STI . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( STI . getRegisterInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; <ISA_LIT>ABIInfo ABI = STI . getABI ( ) ; unsigned SP = <STR_LIT> ; const TargetRegisterClass * RC = & <STR_LIT> ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . adjustStackPtr ( SP , - StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , <NUM_LIT> ) , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } }


<s> for ( InstructionSetMap :: iterator It = PreviousRegSeqByReg . begin ( ) , E = PreviousRegSeqByReg . end ( ) ; It != E ; ++ It ) { std :: vector < MachineInstr * > & MIs = ( * It ) . second ; MIs . erase ( find ( MIs , MI ) , MIs . end ( ) ) ;


<s> inline bool isStoreInst ( const MCInstrDesc & MCInstD ) { return getInstrType ( MCInstD ) == <ISA_LIT>II :: TypeSTORE ;


<s> for ( unsigned i = NumElems / <NUM_LIT> , e = NumElems ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; return true ;


<s> Length = DAG . getZExtOrTrunc ( Length , DL , PtrVT ) ; Char = DAG . getZExtOrTrunc ( Char , DL , <STR_LIT> ) ; Char = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Char , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Limit = DAG . getNode ( <STR_LIT> , DL , PtrVT , Src , Length ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , Char ) ; Chain = End . getValue ( <NUM_LIT> ) ; SDValue Glue = End . getValue ( <NUM_LIT> ) ; SDValue Ops [ ] = { End , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Glue } ;

VTs = DAG . getVTList ( PtrVT , <STR_LIT> ) ;


<s> case MCExpr :: Constant : OS << cast < MCConstantExpr > ( Expr ) . getValue ( ) ; return ; case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SRE = cast < MCSymbolRefExpr > ( Expr ) ; const MCSymbol & Sym = SRE . getSymbol ( ) ; Sym . print ( OS , MAI ) ; return ; } case MCExpr :: Unary : { const MCUnaryExpr & UE = cast < MCUnaryExpr > ( Expr ) ; switch ( UE . getOpcode ( ) ) { case MCUnaryExpr :: LNot : OS << '!' ; break ; case MCUnaryExpr :: Minus : OS << '-' ; break ; case MCUnaryExpr :: Not : OS << '~' ; break ; case MCUnaryExpr :: Plus : OS << '+' ; break ; } printMCExpr ( * UE . getSubExpr ( ) , OS ) ; return ; } case MCExpr :: Binary : { const MCBinaryExpr & BE = cast < MCBinaryExpr > ( Expr ) ; if ( isa < MCConstantExpr > ( BE . getLHS ( ) ) || isa < MCSymbolRefExpr > ( BE . getLHS ( ) ) || isa < <ISA_LIT>GenericMCSymbolRefExpr > ( BE . getLHS ( ) ) ) { printMCExpr ( * BE . getLHS ( ) , OS ) ; } else { OS << '(' ; printMCExpr ( * BE . getLHS ( ) , OS ) ; OS << ')' ; } switch ( BE . getOpcode ( ) ) { case MCBinaryExpr :: Add : if ( const MCConstantExpr * RHSC = dyn_cast < MCConstantExpr > ( BE . getRHS ( ) ) ) { if ( RHSC -> getValue ( ) < <NUM_LIT> ) { OS << RHSC -> getValue ( ) ; return ; } }


<s> F -> insert ( MBBIter , XMMSaveMBB ) ; F -> insert ( MBBIter , EndMBB ) ; EndMBB -> splice ( EndMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( XMMSaveMBB ) ; XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; Register CountReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int RegSaveFrameIndex = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ;

BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) . addImm ( <STR_LIT> ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {

AU . addRequired < MemorySSAWrapperPass > ( ) ;


<s> TRI . splitReg ( SrcReg , SrcLo , SrcHi ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestLo ) . addReg ( SrcLo , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestHi ) . addReg ( SrcHi , getKillRegState ( KillSrc ) ) ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else if ( DestReg == <STR_LIT> && SrcReg == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else {


<s> MachineInstr * MI = I ; const DebugLoc & dl = MI -> getDebugLoc ( ) ; if ( isInt < <NUM_LIT> > ( CalleeAmt ) ) { BuildMI ( MBB , I , dl , TII . get ( ADDIInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addImm ( CalleeAmt ) ; } else { MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> <NUM_LIT> ) ;

BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & <NUM_LIT> ) ;


<s> SDLoc DL ( Op ) ; assert ( Op . getValueType ( ) . isScalableVector ( ) && TLI . isTypeLegal ( Op . getValueType ( ) ) && <STR_LIT> ) ; EVT OutVT = TLI . getTypeToTransformTo ( * DAG . getContext ( ) , VT ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , DL , OutVT ) ;

SDValue FVal = DAG . getConstant ( <NUM_LIT> , DL , OutVT ) ;


<s> Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , ELFWriterInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameLowering ( Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( Subtarget ) ) {


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateCondCode ( <STR_LIT> CC , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_CondCode ) ;


<s> static SDValue combineKSHIFT ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedElts = APInt :: getAllOnes ( VT . getVectorNumElements ( ) ) ;

if ( TLI . SimplifyDemandedVectorElts ( SDValue ( N , <NUM_LIT> ) , DemandedElts , DCI ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> return ( __m256bh ) __builtin_ia32_cvtne2ps2bf16_v16hi ( __A , __B ) ;


<s> if ( DisableShifterOp ) return false ; if ( N . getOpcode ( ) == <STR_LIT> ) { unsigned PowerOfTwo = <NUM_LIT> ; SDValue NewMulConst ; if ( canExtractShiftFromMul ( N , <NUM_LIT> , PowerOfTwo , NewMulConst ) ) { replaceDAGValue ( N . getOperand ( <NUM_LIT> ) , NewMulConst ) ; BaseReg = N ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , PowerOfTwo ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } } <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return false ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ;

Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal ) , SDLoc ( N ) , <STR_LIT> ) ;


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) || N -> getConstantOperandVal ( FirstOp ) != <NUM_LIT> ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Base -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; if ( ReplaceFlags ) {

if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) {


<s> case UHQmode : case USQmode : case UDQmode : case UHAmode : case USAmode : case UDAmode : case UTAmode : warning_at ( loc , <NUM_LIT> , <STR_LIT> , <STR_LIT> ) ; return args [ <NUM_LIT> ] ; default : error_at ( loc , <STR_LIT> , <STR_LIT> ) ; fold = error_mark_node ; break ; } fold = targetm . builtin_decl ( id , true ) ; if ( fold != error_mark_node ) fold = build_function_call_vec ( loc , vNULL , fold , & args , NULL ) ; break ; case AVR_BUILTIN_ROUNDFX : if ( args . length ( ) != <NUM_LIT> ) { error_at ( loc , <STR_LIT> , <STR_LIT> , ( int ) args . length ( ) ) ; fold = error_mark_node ; break ; } type0 = TREE_TYPE ( args [ <NUM_LIT> ] ) ; type1 = TREE_TYPE ( args [ <NUM_LIT> ] ) ; if ( ! FIXED_POINT_TYPE_P ( type0 ) ) { error_at ( loc , <STR_LIT> , <STR_LIT> ) ; fold = error_mark_node ; } if ( ! INTEGRAL_TYPE_P ( type1 ) ) { error_at ( loc , <STR_LIT> , <STR_LIT> ) ; fold = error_mark_node ; } switch ( TYPE_MODE ( type0 ) ) { case QQmode : id = AVR_BUILTIN_ROUNDHR ; break ; case HQmode : id = AVR_BUILTIN_ROUNDR ; break ; case SQmode : id = AVR_BUILTIN_ROUNDLR ; break ; case DQmode : id = AVR_BUILTIN_ROUNDLLR ; break ; case UQQmode : id = AVR_BUILTIN_ROUNDUHR ; break ; case UHQmode : id = AVR_BUILTIN_ROUNDUR ; break ; case USQmode : id = AVR_BUILTIN_ROUNDULR ; break ; case UDQmode : id = AVR_BUILTIN_ROUNDULLR ; break ; case HAmode : id = AVR_BUILTIN_ROUNDHK ; break ; case SAmode : id = AVR_BUILTIN_ROUNDK ; break ; case DAmode : id = AVR_BUILTIN_ROUNDLK ; break ; case TAmode : id = AVR_BUILTIN_ROUNDLLK ; break ; case UHAmode : id = AVR_BUILTIN_ROUNDUHK ; break ; case USAmode : id = AVR_BUILTIN_ROUNDUK ; break ; case UDAmode : id = AVR_BUILTIN_ROUNDULK ; break ; case UTAmode : id = AVR_BUILTIN_ROUNDULLK ; break ; default : error_at ( loc , <STR_LIT> , <STR_LIT> ) ; fold = error_mark_node ; break ;


<s> static const char * cached_match = NULL ; static bool cached_result ; int i ; if ( msp430_hwmult_type == LARGE ) return true ;

if ( target_mcu == NULL || msp430_hwmult_type != AUTO ) return false ;


<s> for ( auto I = std :: next ( DefMI . getIterator ( ) ) ; I != E ; ++ I ) { if ( I -> isDebugInstr ( ) ) continue ; if ( ++ NumInst > MaxInstScan ) return true ; if ( I -> modifiesRegister ( <STR_LIT> , TRI ) ) return true ; }


<s> if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; else if ( RC == <STR_LIT> ) { if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is<ISA_LIT>1 ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } else {

const TargetRegisterInfo * TRI = MBB . getParent ( ) -> getTarget ( ) . getRegisterInfo ( ) ;


<s> <ISA_LIT>SERegisterInfo :: <ISA_LIT>SERegisterInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>RegisterInfo ( ST ) {


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti , MII ) , Parser ( Parser ) , Lexer ( Parser . getLexer ( ) ) , MRI ( Parser . getContext ( ) . getRegisterInfo ( ) ) , SPRegClass ( MRI -> getRegClass ( <STR_LIT> ) ) , VPRegClass ( MRI -> getRegClass ( <STR_LIT> ) ) { AC = new <ISA_LIT>AsmInstCompress ( MII ) ;

AC -> setCompressEnabled ( Options . MCCompressInst ) ;


<s> assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; MVT MaskEltVT = <STR_LIT> ( VT . getScalarSizeInBits ( ) ) ; MVT MaskVecVT = <STR_LIT> ( MaskEltVT , VT . getVectorNumElements ( ) ) ; SDValue MaskNode = getConstVector ( Mask , MaskVecVT , DAG , DL , true ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , VT , MaskNode , V1 ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , V1 , MaskNode , V2 ) ;


<s> std :: vector < std :: string > max_gt ( Ax a , StepZIDS bs ) {

return D ( <STR_LIT> , R ( a ) , <STR_LIT> , <STR_LIT> , bs ) ;


<s> MIB . addImm ( <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . BlockMasksToRecompute . insert ( MIB . getInstr ( ) ) ; } else { ReplaceVCMPWithVPT ( VCMP , VCMP ) ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPST ) ; LoLoop . ToRemove . insert ( VPST ) ; } else if ( Block . containsVCTP ( ) ) { MachineInstr * VPST = Insts . front ( ) ; if ( Block . size ( ) == <NUM_LIT> ) { assert ( VPST -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; LoLoop . ToRemove . insert ( VPST ) ; } else LoLoop . BlockMasksToRecompute . insert ( VPST ) ; } else if ( Insts . front ( ) -> getOpcode ( ) == <STR_LIT> ) { MachineInstr * VPST = Insts . front ( ) ; auto Next = ++ MachineBasicBlock :: iterator ( VPST ) ; assert ( getVPTInstrPredicate ( * Next ) != <STR_LIT> && <STR_LIT> ) ; ( void ) Next ; MachineInstr * VprDef = RDA -> getUniqueReachingMIDef ( VPST , <STR_LIT> ) ; if ( VprDef && VCMPOpcodeToVPT ( VprDef -> getOpcode ( ) ) && ! LoLoop . ToRemove . contains ( VprDef ) ) { MachineInstr * VCMP = VprDef ; if ( std :: none_of ( ++ MachineBasicBlock :: iterator ( VCMP ) , MachineBasicBlock :: iterator ( VPST ) , hasVPRUse ) && RDA -> hasSameReachingDef ( VCMP , VPST , VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) && RDA -> hasSameReachingDef ( VCMP , VPST , VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { ReplaceVCMPWithVPT ( VCMP , VPST ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VPST ) ;


<s> static unsigned getPostIndexedLoadStoreOpcode ( unsigned Opc ) { switch ( Opc ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ;

default : llvm_unreachable ( <STR_LIT> ) ;


<s> return __builtin_c6x_sshl ( src1 , src2 ) ;


<s> case <STR_LIT> : case <STR_LIT> : return combineSelect ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineBitcast ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineCMov ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineAdd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSBB ( N , DAG ) ; case <STR_LIT> : return combineADC ( N , DAG , DCI ) ; case <STR_LIT> : return combineMul ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShift ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineAnd ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineOr ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineXor ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineLoad ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineMaskedLoad ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineMaskedStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ;

case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ;


<s> enum rtx_code rcode = GET_CODE ( cond ) ; if ( ! TARGET_PAIRED_FLOAT ) return <NUM_LIT> ;

paired_emit_vector_compare ( rcode , dest , op1 , op2 , cc_op0 , cc_op1 ) ;


<s> if ( flag_pic && cfun -> machine -> pic_reg ) { rtx pic_reg = cfun -> machine -> pic_reg ; insn = emit_insn ( gen_load_pic_offset ( pic_reg , scratch_reg_0 ) ) ; insn = emit_insn ( gen_subsi3 ( pic_reg , pic_reg , scratch_reg_0 ) ) ; } if ( total_size > <NUM_LIT> ) { if ( flag_stack_check ) { rtx scratch_v4si = gen_rtx_REG ( V4SImode , REGNO ( scratch_reg_0 ) ) ; rtx sp_v4si = gen_rtx_REG ( V4SImode , STACK_POINTER_REGNUM ) ; rtx size_v4si = spu_const ( V4SImode , total_size - <NUM_LIT> ) ; if ( ! satisfies_constraint_K ( GEN_INT ( total_size - <NUM_LIT> ) ) ) { emit_move_insn ( scratch_v4si , size_v4si ) ; size_v4si = scratch_v4si ; } emit_insn ( gen_cgt_v4si ( scratch_v4si , sp_v4si , size_v4si ) ) ; emit_insn ( gen_vec_extractv4si ( scratch_reg_0 , scratch_v4si , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_spu_heq ( scratch_reg_0 , GEN_INT ( <NUM_LIT> ) ) ) ; } if ( total_size <= <NUM_LIT> ) { insn = frame_emit_store ( STACK_POINTER_REGNUM , sp_reg , - total_size ) ; insn = frame_emit_add_imm ( sp_reg , sp_reg , - total_size , scratch_reg_0 ) ; } else { insn = emit_move_insn ( scratch_reg_0 , sp_reg ) ; insn = frame_emit_add_imm ( sp_reg , sp_reg , - total_size , scratch_reg_1 ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; real = gen_addsi3 ( sp_reg , sp_reg , GEN_INT ( - total_size ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , real ) ;


<s> unsigned NumSubRegElts = <NUM_LIT> / InSVT . getSizeInBits ( ) ; EVT SubRegVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubRegElts ) ; for ( unsigned i = <NUM_LIT> ; i < RegNum ; i ++ ) SubVec [ i ] = DAG . getNode ( <STR_LIT> , DL , SubRegVT , In , DAG . getIntPtrConstant ( i * NumSubRegElts , DL ) ) ; if ( Subtarget . hasSSE41 ( ) || OutSVT == <STR_LIT> ) return combineVectorTruncationWithPACKUS ( N , DAG , SubVec ) ; else if ( InSVT == <STR_LIT> ) return combineVectorTruncationWithPACKSS ( N , Subtarget , DAG , SubVec ) ; else return SDValue ( ) ;


<s> if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( ! GV -> hasLocalLinkage ( ) && GV -> hasDefaultVisibility ( ) ) { flags |= <STR_LIT> ; } return flags ; } if ( GV -> isStrongDefinitionForLinker ( ) ) return flags ; return flags | <STR_LIT> ;


<s> if ( Subtarget . isAIXABI ( ) ) { M . getOrInsertGlobal ( AIXSSPCanaryWordName , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; return ; } if ( ! Subtarget . isTargetLinux ( ) ) return TargetLowering :: insertSSPDeclarations ( M ) ;


<s> static machine_mode promote_arg ( machine_mode mode , bool prototyped ) { if ( ! prototyped && mode == SFmode ) mode = DFmode ; else if ( GET_MODE_SIZE ( mode ) < GET_MODE_SIZE ( SImode ) ) mode = SImode ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> } if ( SelectImm ( Addr , Base ) ) { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; }


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_FUNCTION_ENTER ( const MachineInstr & MI ) { const Function & F = MF -> getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) {


<s> case <ISA_LIT>MCExpr :: MEK_DTPREL : return getExprOpValue ( <ISA_LIT>Expr -> getSubExpr ( ) , Fixups , STI ) ; case <ISA_LIT>MCExpr :: MEK_CALL_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_CALL_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_DTPREL_HI : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_DTPREL_LO : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOTTPREL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_CALL : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_DISP : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_PAGE : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GOT_OFST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_GPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_LO : if ( <ISA_LIT>Expr -> isGpOff ( ) ) FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; else FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHEST : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HIGHER : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_HI : if ( <ISA_LIT>Expr -> isGpOff ( ) ) FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; else FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_PCREL_LO16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: MEK_TLSGD : FixupKind = isMicro<ISA_LIT> ( STI ) ? <STR_LIT> : <STR_LIT> ; break ;


<s> void print ( raw_ostream & OS ) const {


<s> setAliasRegs ( MF , SavedRegs , RA ) ; setAliasRegs ( MF , SavedRegs , FP ) ; } if ( hasBP ( MF ) ) setAliasRegs ( MF , SavedRegs , BP ) ; if ( <ISA_LIT>FI -> callsEhReturn ( ) ) <ISA_LIT>FI -> createEhDataRegsFI ( MF ) ; if ( <ISA_LIT>FI -> isISR ( ) ) <ISA_LIT>FI -> createISRRegFI ( MF ) ; if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ;

int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ;


<s> AtomicOrdering FenceOrdering = static_cast < AtomicOrdering > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; SynchronizationScope FenceScope = static_cast < SynchronizationScope > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; if ( FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread ) {

if ( Subtarget -> hasSSE2 ( ) || Subtarget -> is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;


<s> static SDValue getSETCC ( <STR_LIT> Cond , SDValue EFLAGS , const SDLoc & dl , SelectionDAG & DAG ) {

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( Cond , dl , <STR_LIT> ) , EFLAGS ) ;


<s> MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; InstructionSelector :: ComplexRendererFns Default = { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Root . getReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } } } ; if ( ! STI . hasFlatInstOffsets ( ) ) return Default ; const MachineInstr * OpDef = MRI . getVRegDef ( Root . getReg ( ) ) ; if ( ! OpDef || OpDef -> getOpcode ( ) != <STR_LIT> ) return Default ; Optional < int64_t > Offset = getConstantVRegVal ( OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! Offset . hasValue ( ) ) return Default ;

unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ;


<s> bool <ISA_LIT>InstrInfo :: areMemAccessesTriviallyDisjoint ( MachineInstr * MIa , MachineInstr * MIb , AliasAnalysis * AA ) const { const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned BaseRegA = <NUM_LIT> , BaseRegB = <NUM_LIT> ; int OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; int WidthA = <NUM_LIT> , WidthB = <NUM_LIT> ; assert ( MIa && MIa -> mayLoadOrStore ( ) && <STR_LIT> ) ; assert ( MIb && MIb -> mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) {


<s> <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned SP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned FP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ZERO = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned ADDu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; MachineLocation DstML , SrcML ; TII . adjustStackPtr ( SP , - StackSize , MBB , MBBI ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; MMI . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( AdjustSPLabel , - StackSize ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { unsigned Reg0 = MRI -> getDwarfRegNum ( RegInfo . getSubReg ( Reg , <STR_LIT> ) , true ) ; unsigned Reg1 = MRI -> getDwarfRegNum ( RegInfo . getSubReg ( Reg , <STR_LIT> ) , true ) ; if ( ! STI . isLittle ( ) ) std :: swap ( Reg0 , Reg1 ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel , Reg0 , Offset ) ) ; MMI . addFrameInst ( MCCFIInstruction :: createOffset ( CSLabel , Reg1 , Offset + <NUM_LIT> ) ) ;


<s> bool tilepro_legitimate_pic_operand_p ( rtx x ) {

if ( tilepro_pic_address_needs_scratch ( x ) ) return false ;


<s> return true ; } } if ( ( N1 . isUndef ( ) || DAG . ComputeNumSignBits ( VV1 ) > BitSize ) && ( N2 . isUndef ( ) || DAG . ComputeNumSignBits ( VV2 ) > BitSize ) ) { V1 = VV1 ; V2 = VV2 ; SrcVT = PackVT ; PackOpcode = <STR_LIT> ; return true ; } return false ; } ; SmallVector < int , <NUM_LIT> > BinaryMask ; createPackShuffleMask ( VT , BinaryMask , false ) ; if ( isTargetShuffleEquivalent ( TargetMask , BinaryMask , V1 , V2 ) ) if ( MatchPACK ( V1 , V2 ) ) return true ; SmallVector < int , <NUM_LIT> > UnaryMask ; createPackShuffleMask ( VT , UnaryMask , true ) ; if ( isTargetShuffleEquivalent ( TargetMask , UnaryMask , V1 ) ) if ( MatchPACK ( V1 , V1 ) ) return true ; return false ;


<s> assert ( Pred != <STR_LIT> && <STR_LIT> ) ; if ( Pred == <STR_LIT> ) { ++ MBIter ; continue ; } <STR_LIT> BlockMask = CreateVPTBlock ( MBIter , EndIter , DeadInstructions ) ; MachineInstrBuilder MIBuilder ; unsigned NewOpcode ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( unsigned ) BlockMask << <STR_LIT> ) ; if ( MachineInstr * VCMP = findVCMPToFoldIntoVPST ( MI , TRI , NewOpcode ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; VCMP -> dump ( ) ) ; MIBuilder = BuildMI ( Block , MI , DL , TII -> get ( NewOpcode ) ) ; MIBuilder . addImm ( ( uint64_t ) BlockMask ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; MIBuilder . add ( VCMP -> getOperand ( <NUM_LIT> ) ) ; for ( MachineInstr & MI : make_range ( VCMP -> getIterator ( ) , MI -> getIterator ( ) ) ) { MI . clearRegisterKills ( VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) , TRI ) ; MI . clearRegisterKills ( VCMP -> getOperand ( <NUM_LIT> ) . getReg ( ) , TRI ) ; } VCMP -> eraseFromParent ( ) ; } else { MIBuilder = BuildMI ( Block , MI , DL , TII -> get ( <STR_LIT> ) ) ; MIBuilder . addImm ( ( uint64_t ) BlockMask ) ; } finalizeBundle ( Block , MachineBasicBlock :: instr_iterator ( MIBuilder . getInstr ( ) ) , MBIter ) ; Modified = true ; } for ( MachineInstr * DeadMI : DeadInstructions ) { if ( DeadMI -> isInsideBundle ( ) ) DeadMI -> eraseFromBundle ( ) ; else DeadMI -> eraseFromParent ( ) ; }


<s> HasSubsectionsViaSymbols = true ; HasMachoZeroFillDirective = false ; HasMachoTBSSDirective = false ; HasStaticCtorDtorReferenceInStaticMode = false ; LinkerRequiresNonEmptyDwarfLines = true ; MaxInstLength = <NUM_LIT> ; SeparatorString = <STR_LIT> ; CommentColumn = <NUM_LIT> ; CommentString = <STR_LIT> ; LabelSuffix = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; LinkerPrivateGlobalPrefix = <STR_LIT> ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; AssemblerDialect = <NUM_LIT> ; AllowQuotesInName = false ; AllowNameToStartWithDigit = false ; AllowPeriodsInName = false ; ZeroDirective = <STR_LIT> ; AsciiDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ;


<s> return __builtin_aarch64_uqrshrn_nsi_uus ( __a , __b ) ;


return Defs . count ( V ) || SeenNoObjStore ;


<s> if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { Parser . Lex ( ) ; isParenExpr = true ; } if ( getLexer ( ) . getKind ( ) != AsmToken :: Dollar ) { if ( parseMemOffset ( IdVal , isParenExpr ) ) return MatchOperand_ParseFail ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = ParseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ;

if ( ! IdVal ) IdVal = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ;


<s> while ( NOp < NumOps ) T . addOperand ( MI -> getOperand ( NOp ++ ) ) ; MI -> setDesc ( get ( PredOpc ) ) ; while ( unsigned n = MI -> getNumOperands ( ) ) MI -> RemoveOperand ( n - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = T -> getNumOperands ( ) ; i < n ; ++ i ) MI -> addOperand ( T -> getOperand ( i ) ) ; MachineBasicBlock :: instr_iterator TI = T -> getIterator ( ) ; B . erase ( TI ) ; MachineRegisterInfo & MRI = B . getParent ( ) -> getRegInfo ( ) ;


<s> const MCOperand MO = MI . getOperand ( Op ) ; if ( MO . isImm ( ) ) { unsigned value = MO . getImm ( ) ; return static_cast < unsigned > ( value - <NUM_LIT> ) ; } assert ( MO . isExpr ( ) ) ; <STR_LIT> FixupKind = <STR_LIT> ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( FixupKind ) ) ) ;


<s> MVT <ISA_LIT>TargetLowering :: getSetCCResultType ( MVT VT ) const { return <STR_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ;

SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;


<s> unsigned ResultReg ; if ( Imm < <NUM_LIT> ) ResultReg = emitAddSub_ri ( false , VT , Op0 , Op0IsKill , - Imm ) ; else ResultReg = emitAddSub_ri ( true , VT , Op0 , Op0IsKill , Imm ) ; if ( ResultReg ) return ResultReg ; unsigned CReg = fastEmit_i ( VT , VT , <STR_LIT> , Imm ) ; if ( ! CReg ) return <NUM_LIT> ; ResultReg = emitAddSub_rr ( true , VT , Op0 , Op0IsKill , CReg , true ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return FirstMacroFusionInstKind :: Test ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return FirstMacroFusionInstKind :: And ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return FirstMacroFusionInstKind :: Cmp ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else if ( ImmValue < <NUM_LIT> && ImmValue >= - <NUM_LIT> ) { tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegOp . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ImmValue ) ) ; Instructions . push_back ( tmpInst ) ; } else {


<s> bool MatchA = false , MatchB = false ; for ( unsigned Half = <NUM_LIT> ; Half != <NUM_LIT> ; ++ Half ) { if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , HalfSize , Half * HalfSize ) ) { MatchA = true ; break ; } } for ( unsigned Half = <NUM_LIT> ; Half != <NUM_LIT> ; ++ Half ) {

if ( isSequentialOrUndefInRange ( Mask , HalfSize , HalfSize , Half * HalfSize ) ) {


<s> LowerVAARG ( N , Chain , DataPtr , DAG ) ; SDValue Res = DAG . getLoad ( N -> getValueType ( <NUM_LIT> ) , dl , Chain , DataPtr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; Results . push_back ( Res ) ;

Results . push_back ( SDValue ( Res . getNode ( ) , <NUM_LIT> ) ) ;


<s> MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; } else { MI . setOpcode ( <STR_LIT> ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ;


<s> DenseSet < unsigned > KilledRegs ; DenseSet < unsigned > UsedRegs ; for ( const MachineInstr * MI : Cand . Instrs ) { const MachineOperand & MO = getLoadStoreRegOp ( * MI ) ; unsigned Reg = MO . getReg ( ) ; bool IsKill = MO . isKill ( ) ; if ( IsKill ) KilledRegs . insert ( Reg ) ; Regs . push_back ( std :: make_pair ( Reg , IsKill ) ) ; UsedRegs . insert ( Reg ) ; if ( IsLoad ) { for ( const MachineOperand & MO : MI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) || MO . isDead ( ) ) continue ; assert ( MO . isImplicit ( ) ) ; unsigned DefReg = MO . getReg ( ) ; if ( is_contained ( ImpDefs , DefReg ) ) continue ; if ( MI -> readsRegister ( DefReg ) ) continue ; ImpDefs . push_back ( DefReg ) ; } } } typedef MachineBasicBlock :: iterator iterator ; MachineInstr * LatestMI = Cand . Instrs [ Cand . LatestMIIdx ] ; iterator InsertBefore = std :: next ( iterator ( LatestMI ) ) ; MachineBasicBlock & MBB = * LatestMI -> getParent ( ) ; unsigned Offset = getMemoryOpOffset ( * First ) ; unsigned Base = getLoadStoreBaseOp ( * First ) . getReg ( ) ; bool BaseKill = LatestMI -> killsRegister ( Base ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * First , PredReg ) ; DebugLoc DL = First -> getDebugLoc ( ) ; MachineInstr * Merged = nullptr ; if ( Cand . CanMergeToLSDouble ) Merged = CreateLoadStoreDouble ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged && Cand . CanMergeToLSMulti ) Merged = CreateLoadStoreMulti ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged ) return nullptr ; iterator EarliestI ( Cand . Instrs [ Cand . EarliestMIIdx ] ) ; bool EarliestAtBegin = false ; if ( EarliestI == MBB . begin ( ) ) { EarliestAtBegin = true ;


<s> void i386_pe_asm_named_section ( const char * name , unsigned int flags , tree decl ) { char flagchars [ <NUM_LIT> ] , * f = flagchars ; if ( ( flags & SECTION_EXCLUDE ) != <NUM_LIT> ) * f ++ = 'e' ; if ( ( flags & ( SECTION_CODE | SECTION_WRITE ) ) == <NUM_LIT> ) { * f ++ = 'd' ; * f ++ = 'r' ; } else { if ( flags & SECTION_CODE ) * f ++ = 'x' ; if ( flags & SECTION_WRITE ) * f ++ = 'w' ; if ( flags & SECTION_PE_SHARED ) * f ++ = 's' ; if ( ( flags & SECTION_EXCLUDE ) != <NUM_LIT> ) * f ++ = 'n' ; } if ( startswith ( name , LTO_SECTION_NAME_PREFIX ) ) * f ++ = '0' ; * f = '\0' ; fprintf ( asm_out_file , <STR_LIT> , name , flagchars ) ;


<s> bool <ISA_LIT>LegalizerInfo :: legalizeLoadStore ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & MIRBuilder , GISelChangeObserver & Observer ) const { assert ( MI . getOpcode ( ) == TargetOpcode :: G_STORE || MI . getOpcode ( ) == TargetOpcode :: G_LOAD ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT ValTy = MRI . getType ( ValReg ) ; if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) {


<s> if ( Sym ) { if ( Asm . isThumbFunc ( Sym ) ) Value |= <NUM_LIT> ; } } if ( IsResolved && ( unsigned ) Fixup . getKind ( ) == <STR_LIT> ) { assert ( Sym && <STR_LIT> ) ; if ( Sym -> isExternal ( ) || Value >= <NUM_LIT> ) IsResolved = false ; } if ( Sym && Sym -> isELF ( ) ) { unsigned Type = dyn_cast < MCSymbolELF > ( Sym ) -> getType ( ) ; if ( ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC ) ) {

if ( Asm . isThumbFunc ( Sym ) && ( FixupKind == <STR_LIT> ) ) IsResolved = false ;


<s> Value * <ISA_LIT>IREmitter :: visitATOMOR64_DAG ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> bool Result = AsmPrinter :: runOnMachineFunction ( F ) ; OutStreamer -> EmitRawText ( StringRef ( <STR_LIT> ) ) ;


<s> case <STR_LIT> : LC = isSigned ? RTLIB :: SDIVREM_I8 : RTLIB :: UDIVREM_I8 ; break ; case <STR_LIT> : LC = isSigned ? RTLIB :: SDIVREM_I16 : RTLIB :: UDIVREM_I16 ; break ; case <STR_LIT> : LC = isSigned ? RTLIB :: SDIVREM_I32 : RTLIB :: UDIVREM_I32 ; break ; case <STR_LIT> : LC = isSigned ? RTLIB :: SDIVREM_I64 : RTLIB :: UDIVREM_I64 ; break ; } SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> , e = Op -> getNumOperands ( ) ; i != e ; ++ i ) { EVT ArgVT = Op -> getOperand ( i ) . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . Node = Op -> getOperand ( i ) ; Entry . Ty = ArgTy ; Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty , nullptr ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ;

CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) . setInRegister ( ) . setSExtResult ( isSigned ) . setZExtResult ( ! isSigned ) ;


<s> if ( profiling ) { goto out ; } profiling ++ ; frompcindex = ( unsigned short * ) ( ( long ) frompcindex - ( long ) s_lowpc ) ; if ( ( unsigned long ) frompcindex > s_textsize ) { goto done ; } frompcindex = & froms [ ( ( long ) frompcindex ) / ( HASHFRACTION * sizeof ( * froms ) ) ] ; toindex = * frompcindex ; if ( toindex == <NUM_LIT> ) { toindex = ++ tos [ <NUM_LIT> ] . link ; if ( toindex >= tolimit ) { goto overflow ; } * frompcindex = toindex ; top = & tos [ toindex ] ; top -> selfpc = selfpc ; top -> count = <NUM_LIT> ; top -> link = <NUM_LIT> ; goto done ; } top = & tos [ toindex ] ;


<s> if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( nullptr ) ;


<s> SDValue <ISA_LIT>TargetLowering :: combineADD ( SDNode * N , DAGCombinerInfo & DCI ) const {

if ( auto Value = combineADDToADDZE ( N , DCI . DAG , Subtarget ) ) return Value ;


<s> NeedTruncation = true ; ArithOp = Arith ; } } } switch ( ArithOp . getOpcode ( ) ) { case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) goto default_case ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( ArithOp . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ) { if ( C -> getAPIntValue ( ) == <NUM_LIT> && ! Subtarget -> slowIncDec ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } if ( C -> getAPIntValue ( ) . isAllOnesValue ( ) && ! Subtarget -> slowIncDec ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } } Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) && Op -> hasOneUse ( ) && isa < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) && ! hasNonFlagsUse ( Op ) ) { EVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt >= BitWidth ) break ; APInt Mask = ArithOp . getOpcode ( ) == <STR_LIT> ? APInt :: getHighBitsSet ( BitWidth , BitWidth - ShAmt ) : APInt :: getLowBitsSet ( BitWidth , BitWidth - ShAmt ) ; if ( ! Mask . isSignedIntN ( <NUM_LIT> ) ) break ; SDValue New = DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , VT ) ) ; DAG . ReplaceAllUsesWith ( Op , New ) ; Op = New ; } break ; case <STR_LIT> : if ( ! hasNonFlagsUse ( Op ) ) break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : { if ( ! NeedTruncation && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) { SDValue EFLAGS = LowerVectorAllZeroTest ( Op , Subtarget , DAG ) ; if ( EFLAGS . getNode ( ) ) return EFLAGS ;


<s> SDValue Op0 , Op1 ; switch ( ConstraintCode ) { default : return true ; case 'm' :

if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ;


<s> } const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! MF . getFunction ( ) -> isVarArg ( ) ) { LRSpillSlot = MFI . CreateFixedObject ( RC -> getSize ( ) , <NUM_LIT> , true ) ; } else {

LRSpillSlot = MFI . CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , true ) ;


<s> return EQ ; case EQ : return NE ; case GT : return LE ; case LE :


<s> bool IsAltivecType = ST -> hasAltivec ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsVSXType = ST -> hasVSX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; bool IsQPXType = ST -> hasQPX ( ) && ( LT . second == <STR_LIT> || LT . second == <STR_LIT> ) ; unsigned MemBytes = Src -> getPrimitiveSizeInBits ( ) ; if ( Opcode == Instruction :: Load && ST -> hasVSX ( ) && IsAltivecType && ( MemBytes == <NUM_LIT> || ( ST -> hasP8Vector ( ) && MemBytes == <NUM_LIT> ) ) ) return <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( ! SrcBytes || ! Alignment || Alignment >= SrcBytes ) return Cost ; if ( Opcode == Instruction :: Load && ( ( ! ST -> hasP8Vector ( ) && IsAltivecType ) || IsQPXType ) && Alignment >= LT . second . getScalarType ( ) . getStoreSize ( ) ) return Cost + LT . first ; if ( IsVSXType || ( ST -> hasVSX ( ) && IsAltivecType ) ) return Cost ;

Cost += LT . first * ( SrcBytes / Alignment - <NUM_LIT> ) ;


<s> case VK_ABS_G0_NC : return <STR_LIT> ; case VK_PREL_G3 : return <STR_LIT> ; case VK_PREL_G2 : return <STR_LIT> ; case VK_PREL_G2_NC : return <STR_LIT> ; case VK_PREL_G1 : return <STR_LIT> ; case VK_PREL_G1_NC : return <STR_LIT> ; case VK_PREL_G0 : return <STR_LIT> ; case VK_PREL_G0_NC : return <STR_LIT> ; case VK_DTPREL_G2 : return <STR_LIT> ; case VK_DTPREL_G1 : return <STR_LIT> ; case VK_DTPREL_G1_NC : return <STR_LIT> ; case VK_DTPREL_G0 : return <STR_LIT> ; case VK_DTPREL_G0_NC : return <STR_LIT> ; case VK_DTPREL_HI12 : return <STR_LIT> ; case VK_DTPREL_LO12 : return <STR_LIT> ; case VK_DTPREL_LO12_NC : return <STR_LIT> ; case VK_TPREL_G2 : return <STR_LIT> ; case VK_TPREL_G1 : return <STR_LIT> ; case VK_TPREL_G1_NC : return <STR_LIT> ; case VK_TPREL_G0 : return <STR_LIT> ; case VK_TPREL_G0_NC : return <STR_LIT> ;


<s> MachineMemOperand * MemRef = cast < MemSDNode > ( N1 ) -> getMemOperand ( ) ; SDValue Ops0 [ ] = { N2 , LD -> getBasePtr ( ) , LD -> getChain ( ) } ; SDNode * ResNode = CurDAG -> SelectNodeTo ( Op , Opc , VT , <STR_LIT> , <STR_LIT> , Ops0 ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( ResNode ) , { MemRef } ) ; ReplaceUses ( SDValue ( N1 . getNode ( ) , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N1 . getNode ( ) , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; return true ;


<s> int leaf_function_p ; bool prologue_data_valid_p ;


<s> void addTraceSyncBarrierOptOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( unsigned ( getTraceSyncBarrierOpt ( ) ) ) ) ;


<s> void <ISA_LIT>CFGStructurizer :: addDummyExitBlock ( SmallVectorImpl < MachineBasicBlock * > & RetMBB ) { MachineBasicBlock * DummyExitBlk = FuncRep -> CreateMachineBasicBlock ( ) ; FuncRep -> push_back ( DummyExitBlk ) ; insertInstrEnd ( DummyExitBlk , <STR_LIT> ) ; for ( SmallVectorImpl < MachineBasicBlock * > :: iterator It = RetMBB . begin ( ) , E = RetMBB . end ( ) ; It != E ; ++ It ) { MachineBasicBlock * MBB = * It ; MachineInstr * MI = getReturnInstr ( MBB ) ; if ( MI ) MI -> eraseFromParent ( ) ; MBB -> addSuccessor ( DummyExitBlk ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ; ) ;


<s> if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> , offset ) ; return gen_rtx_PLUS ( Pmode , virtual_incoming_args_rtx , GEN_INT ( - offset ) ) ;


<s> case E_HImode : fn = gen_inswl ; break ; case E_SImode : fn = gen_insll ; break ; case E_DImode : fn = gen_insql ; break ; default :


OutStreamer . EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ;


<s> unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { if ( LHSDef -> getOpcode ( ) == TargetOpcode :: G_FRAME_INDEX ) return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHSDef -> getOperand ( <NUM_LIT> ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( RHSC >> Scale ) ; } , } } ; return { {

[ = ] ( MachineInstrBuilder & MIB ) { MIB . add ( LHS ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( RHSC >> Scale ) ; } , } } ;


<s> static bool r10k_needs_protection_p_call ( const_rtx x ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , x , NONCONST ) {


<s> <ISA_LIT>MCELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter ) : MCELFStreamer ( Context , TAB , OS , Emitter ) , MCII ( create<ISA_LIT>MCInstrInfo ( ) ) {


<s> static bool vlmax_avl_insn_p ( rtx_insn * rinsn ) {

return ( INSN_CODE ( rinsn ) == CODE_FOR_vlmax_avlsi || INSN_CODE ( rinsn ) == CODE_FOR_vlmax_avldi ) ;


<s> switch ( mode ) { case V2SFmode : return TARGET_PAIRED_SINGLE_FLOAT ;