<s> Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 ) , GPR3 ) . addReg ( GPR3 ) ) ; Call -> addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: COPY ) , OutReg ) . addReg ( GPR3 ) ; MachineBasicBlock :: iterator Last = I ; -- Last ; ++ I ; MI -> removeFromParent ( ) ; LIS -> repairIntervalsInRange ( & MBB , First , Last , OrigRegs ) ;


<s> reg_iterator argRegEnd ( ) const { return reg_arg . end ( ) ;


<s> virtual const char * getPassName ( ) const {


<s> unsigned DestReg = MemMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BaseReg = MemMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = MemMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned RegSize = TII -> getRegClass ( MemMI -> getDesc ( ) , <NUM_LIT> , TRI , MF ) -> getSize ( ) ; if ( MBBI == B || Offset != <NUM_LIT> ) return E ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; BitVector ModifiedRegs , UsedRegs ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ;

UsedRegs . resize ( TRI -> getNumRegs ( ) ) ;


<s> <ISA_LIT>SetP2AlignOperands ( ) : MachineFunctionPass ( ID ) {


<s> unsigned ImplicitBytes = getImplicitArgNumBytes ( F ) ; if ( ImplicitBytes != <NUM_LIT> ) { unsigned Alignment = getAlignmentForImplicitArgPtr ( ) ; TotalSize = alignTo ( ExplicitArgBytes , Alignment ) + ImplicitBytes ;


<s> SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ;


<s> FrameReg = TRI -> getStackRegister ( ) ;

return getFrameIndexOffsetFromSP ( MF , FI ) ;


<s> const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; bool isThumb = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) ; BBI . Size = <NUM_LIT> ; BBI . Unalign = <NUM_LIT> ; BBI . PostAlign = <NUM_LIT> ; for ( MachineInstr & I : * MBB ) { BBI . Size += TII -> getInstSizeInBytes ( I ) ; if ( I . isInlineAsm ( ) ) BBI . Unalign = isThumb ? <NUM_LIT> : <NUM_LIT> ; else if ( isThumb && mayOptimizeThumb2Instruction ( & I ) ) BBI . Unalign = <NUM_LIT> ; } if ( ! MBB -> empty ( ) && MBB -> back ( ) . getOpcode ( ) == <STR_LIT> ) { BBI . PostAlign = <NUM_LIT> ; MBB -> getParent ( ) -> ensureAlignment ( <NUM_LIT> ) ; }


<s> for ( ; MBBI != E ; ++ MBBI ) { MachineInstr & MI = * MBBI ; if ( MI . isCall ( ) || MI . isTerminator ( ) ) { ++ MBBI ; break ; } if ( ! MI . isDebugInstr ( ) ) MI2LocMap [ & MI ] = ++ Loc ; if ( ! isMemoryOp ( MI ) ) continue ; unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) != <STR_LIT> ) continue ; int Opc = MI . getOpcode ( ) ; bool isLd = isLoadSingle ( Opc ) ; unsigned Base = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = getMemoryOpOffset ( MI ) ; bool StopHere = false ; auto FindBases = [ & ] ( Base2InstMap & Base2Ops , BaseVec & Bases ) { MapIt BI = Base2Ops . find ( Base ) ; if ( BI == Base2Ops . end ( ) ) { Base2Ops [ Base ] . push_back ( & MI ) ; Bases . push_back ( Base ) ; return ; } for ( unsigned i = <NUM_LIT> , e = BI -> second . size ( ) ; i != e ; ++ i ) { if ( Offset == getMemoryOpOffset ( * BI -> second [ i ] ) ) { StopHere = true ; break ; } } if ( ! StopHere ) BI -> second . push_back ( & MI ) ; } ; if ( isLd ) FindBases ( Base2LdsMap , LdBases ) ; else FindBases ( Base2StsMap , StBases ) ; if ( StopHere ) { -- Loc ; break ; } } for ( unsigned i = <NUM_LIT> , e = LdBases . size ( ) ; i != e ; ++ i ) { unsigned Base = LdBases [ i ] ; SmallVectorImpl < MachineInstr * > & Lds = Base2LdsMap [ Base ] ; if ( Lds . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Lds , Base , true , MI2LocMap ) ; } for ( unsigned i = <NUM_LIT> , e = StBases . size ( ) ; i != e ; ++ i ) { unsigned Base = StBases [ i ] ; SmallVectorImpl < MachineInstr * > & Sts = Base2StsMap [ Base ] ; if ( Sts . size ( ) > <NUM_LIT> ) RetVal |= RescheduleOps ( MBB , Sts , Base , false , MI2LocMap ) ; } if ( MBBI != E ) { Base2LdsMap . clear ( ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool Trad ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , Trad ) , DataLayout ( <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , FrameInfo ( TargetFrameInfo :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) {


<s> static SDValue LowerBITCAST ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { MVT SrcVT = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = Op . getSimpleValueType ( ) ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { assert ( Subtarget -> hasSSE2 ( ) && <STR_LIT> ) ; if ( DstVT != <STR_LIT> ) return SDValue ( ) ; SDValue InVec = Op -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned NumElts = SrcVT . getVectorNumElements ( ) ; EVT SVT = SrcVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , SVT , InVec , DAG . getIntPtrConstant ( i ) ) ) ; Elts . append ( NumElts , DAG . getUNDEF ( SVT ) ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumElts * <NUM_LIT> ) ;

SDValue BV = DAG . getNode ( <STR_LIT> , dl , NewVT , Elts ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( Ctx ) ;


<s> return ( float32x4_t ) __builtin_neon_vreinterpretv4sfv16qi ( ( int8x16_t ) __a ) ;


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { assert ( TBB && <STR_LIT> ) ;

assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ;


<s> void <ISA_LIT>AsmPrinter :: setAndEmitFunctionVirtualRegisters ( const MachineFunction & MF ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; if ( NumBytes ) { O << <STR_LIT> << MFI . getMaxAlign ( ) . value ( ) << <STR_LIT> << DEPOTNAME << getFunctionNumber ( ) << <STR_LIT> << NumBytes << <STR_LIT> ; if ( static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . is64Bit ( ) ) { O << <STR_LIT> ; O << <STR_LIT> ; } else {


<s> MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( MRI -> getType ( Dst . getReg ( ) ) == LLT :: scalar ( <NUM_LIT> ) ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( Dst , * MRI ) ;

const TargetRegisterClass * SrcRC = TRI . getConstrainedRegClassForOperand ( Src , * MRI ) ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) {


<s> return LowerFAULTING_OP ( * MI , MCInstLowering ) ; case TargetOpcode :: FENTRY_CALL : return LowerFENTRY_CALL ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_OP : return LowerPATCHABLE_OP ( * MI , MCInstLowering ) ; case TargetOpcode :: STACKMAP : return LowerSTACKMAP ( * MI ) ; case TargetOpcode :: PATCHPOINT : return LowerPATCHPOINT ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_FUNCTION_ENTER : return LowerPATCHABLE_FUNCTION_ENTER ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_RET : return LowerPATCHABLE_RET ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_TAIL_CALL : return LowerPATCHABLE_TAIL_CALL ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_EVENT_CALL : return LowerPATCHABLE_EVENT_CALL ( * MI , MCInstLowering ) ; case TargetOpcode :: PATCHABLE_TYPED_EVENT_CALL : return LowerPATCHABLE_TYPED_EVENT_CALL ( * MI , MCInstLowering ) ; case <STR_LIT> : EmitAndCountInstruction ( MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; return ; case <STR_LIT> : return LowerASAN_CHECK_MEMACCESS ( * MI ) ; case <STR_LIT> : EmitAndCountInstruction ( MCInstBuilder ( getRetOpcode ( * Subtarget ) ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : EmitSEHInstruction ( MI ) ; return ; case <STR_LIT> : { assert ( MF -> hasWinCFI ( ) && <STR_LIT> ) ; MachineBasicBlock :: const_iterator MBBI ( MI ) ; for ( MBBI = PrevCrossBBInst ( MBBI ) ; MBBI != MachineBasicBlock :: const_iterator ( ) ; MBBI = PrevCrossBBInst ( MBBI ) ) { if ( ! MBBI -> isPseudo ( ) ) { if ( MBBI -> isCall ( ) ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; break ; } } return ; } case <STR_LIT> : EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( <STR_LIT> ) ) ; return ; } MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ; if ( MI -> isCall ( ) ) { SMShadowTracker . count ( TmpInst , getSubtargetInfo ( ) , CodeEmitter . get ( ) ) ; SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ;

OutStreamer -> emitInstruction ( TmpInst , getSubtargetInfo ( ) ) ;


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override {


<s> switch ( MIOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { unsigned ShAmt = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MIB . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> << ShAmt ) . addReg ( leaInReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; break ; } case <STR_LIT> : addRegOffset ( MIB , leaInReg , true , <NUM_LIT> ) ; break ; case <STR_LIT> : addRegOffset ( MIB , leaInReg , true , - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , leaInReg , true , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned Src2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill2 = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned leaInReg2 = <NUM_LIT> ; MachineInstr * InsMI2 = nullptr ; if ( Src == Src2 ) { addRegReg ( MIB , leaInReg , true , leaInReg , false ) ; } else { if ( Subtarget . is64Bit ( ) ) leaInReg2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; else leaInReg2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , & * MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) ; InsMI2 = BuildMI ( * MFI , & * MIB , MI -> getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( leaInReg2 , RegState :: Define , <STR_LIT> ) . addReg ( Src2 , getKillRegState ( isKill2 ) ) ; addRegReg ( MIB , leaInReg , true , leaInReg2 , true ) ; } if ( LV && isKill2 && InsMI2 ) LV -> replaceKillInstruction ( Src2 , MI , InsMI2 ) ; break ; }


<s> if ( ResourceTracker -> canReserveResources ( PseudoMI ) ) { ResourceTracker -> reserveResources ( PseudoMI ) ; MI -> getParent ( ) -> getParent ( ) -> DeleteMachineInstr ( PseudoMI ) ; return true ; } else { MI -> getParent ( ) -> getParent ( ) -> DeleteMachineInstr ( PseudoMI ) ;


<s> if ( roll ( deepElem ) . isImmRoll ( ) ) return roll ( deepElem ) ;

if ( blkswap :: goodFor ( <NUM_LIT> , deepElem ) ) return blkswap ( <NUM_LIT> , deepElem ) ;


<s> enum aarch64_symbol_type aarch64_classify_symbolic_expression ( rtx x ) { rtx offset ; split_const ( x , & x , & offset ) ;

return aarch64_classify_symbol ( x , offset ) ;


<s> StringRef InitOrFiniKernelName = <STR_LIT> ; if ( ! IsCtor ) InitOrFiniKernelName = <STR_LIT> ; Function * InitOrFiniKernel = Function :: createWithDefaultAttr ( FunctionType :: get ( Type :: getVoidTy ( M . getContext ( ) ) , false ) , GlobalValue :: InternalLinkage , <NUM_LIT> , InitOrFiniKernelName , & M ) ; BasicBlock * InitOrFiniKernelBB = BasicBlock :: Create ( M . getContext ( ) , <STR_LIT> , InitOrFiniKernel ) ; ReturnInst :: Create ( M . getContext ( ) , InitOrFiniKernelBB ) ;

InitOrFiniKernel -> setCallingConv ( CallingConv :: <ISA_LIT>_KERNEL ) ;


<s> auto * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getStack ( MF , <NUM_LIT> ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; DebugLoc dl = MBB . findDebugLoc ( InsertPt ) ; if ( NumBytes >= ALLOCFRAME_MAX ) { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; unsigned SP = HRI . getStackRegister ( ) ;

BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP ) . addImm ( - int ( NumBytes ) ) ;


<s> if ( GET_CODE ( src ) == CONST && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == PLUS ) { addend = XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ; src = XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ; } src = xtensa_legitimize_tls_address ( src ) ; if ( addend ) { src = gen_rtx_PLUS ( mode , src , addend ) ; src = force_operand ( src , dst ) ; } emit_move_insn ( dst , src ) ; return <NUM_LIT> ; } if ( ! TARGET_CONST16 ) { src = force_const_mem ( SImode , src ) ; operands [ <NUM_LIT> ] = src ; } if ( mode != SImode ) { if ( register_operand ( dst , mode ) ) { emit_move_insn ( simplify_gen_subreg ( SImode , dst , mode , <NUM_LIT> ) , src ) ; return <NUM_LIT> ; } else { src = force_reg ( SImode , src ) ; src = gen_lowpart_SUBREG ( mode , src ) ; operands [ <NUM_LIT> ] = src ; } } }

if ( ! ( reload_in_progress | reload_completed ) && ! xtensa_valid_move ( mode , operands ) ) operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ;


<s> if ( GET_CODE ( x ) == COND_EXEC ) x = COND_EXEC_CODE ( x ) ; if ( GET_CODE ( x ) == SET || GET_CODE ( x ) == CLOBBER ) { rtx dest = SET_DEST ( x ) ; while ( ( GET_CODE ( dest ) == SUBREG && ( ! REG_P ( SUBREG_REG ( dest ) ) || REGNO ( SUBREG_REG ( dest ) ) >= FIRST_PSEUDO_REGISTER ) ) || GET_CODE ( dest ) == ZERO_EXTRACT || GET_CODE ( dest ) == STRICT_LOW_PART ) dest = XEXP ( dest , <NUM_LIT> ) ; if ( GET_CODE ( dest ) == PARALLEL ) { for ( i = XVECLEN ( dest , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( XEXP ( XVECEXP ( dest , <NUM_LIT> , i ) , <NUM_LIT> ) != <NUM_LIT> ) ( * fun ) ( XEXP ( XVECEXP ( dest , <NUM_LIT> , i ) , <NUM_LIT> ) , x , data ) ; } else ( * fun ) ( dest , x , data ) ; } else if ( GET_CODE ( x ) == PARALLEL ) for ( i = XVECLEN ( x , <NUM_LIT> ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) walk_stores ( XVECEXP ( x , <NUM_LIT> , i ) , fun , data ) ;


<s> int <ISA_LIT>TTIImpl :: getArithmeticInstrCost ( unsigned Opcode , Type * Ty , TTI :: TargetCostKind CostKind , TTI :: OperandValueKind Op1Info , TTI :: OperandValueKind Op2Info , TTI :: OperandValueProperties Opd1PropInfo , TTI :: OperandValueProperties Opd2PropInfo , ArrayRef < const Value * > Args , const Instruction * CxtI ) { assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ; if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo , Args , CxtI ) ; int Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ; return vectorCostAdjustment ( Cost , Opcode , Ty , nullptr ) ;


<s> else { if ( round_mode != I387_CW_ANY ) output_asm_insn ( <STR_LIT> , operands ) ; if ( stack_top_dies || dimode_p ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; if ( round_mode != I387_CW_ANY ) output_asm_insn ( <STR_LIT> , operands ) ;


<s> LoadSDNode * Load = cast < LoadSDNode > ( CmpOp0 ) ; unsigned NumBits = Load -> getMemoryVT ( ) . getStoreSizeInBits ( ) ; if ( NumBits != <NUM_LIT> && NumBits != <NUM_LIT> ) return ; ConstantSDNode * Constant = cast < ConstantSDNode > ( CmpOp1 ) ; uint64_t Value = Constant -> getZExtValue ( ) ; uint64_t Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( Load -> getExtensionType ( ) == <STR_LIT> ) { int64_t SignedValue = Constant -> getSExtValue ( ) ; if ( uint64_t ( SignedValue ) + ( <NUM_LIT> << ( NumBits - <NUM_LIT> ) ) > Mask ) return ; if ( IsUnsigned ) Value &= Mask ; else if ( CCMask == <STR_LIT> || CCMask == <STR_LIT> ) Value &= Mask , IsUnsigned = true ; else if ( NumBits == <NUM_LIT> ) { if ( Value == <NUM_LIT> && CCMask == <STR_LIT> ) Value = <NUM_LIT> , CCMask = <STR_LIT> , IsUnsigned = true ;

else if ( Value == <NUM_LIT> && CCMask == <STR_LIT> ) Value = <NUM_LIT> , CCMask = <STR_LIT> , IsUnsigned = true ;


<s> APInt ImmValue ; EVT EltTy = N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) {

if ( ImmValue == ( ImmValue & ~ ( ImmValue + <NUM_LIT> ) ) ) {


<s> if ( AndMask ) { uint64_t AmtVal = AndMask -> getZExtValue ( ) ; if ( ( AmtVal & <NUM_LIT> ) == <NUM_LIT> ) { if ( N1 . hasOneUse ( ) ) { DCI . CombineTo ( N1 . getNode ( ) , AndOp ) ; return SDValue ( N , <NUM_LIT> ) ; } else { SDValue Replace = DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , AndOp ) ; DCI . AddToWorklist ( Replace . getNode ( ) ) ; return Replace ; } } else { unsigned BitWidth = AndMask -> getAPIntValue ( ) . getBitWidth ( ) ; uint64_t UpperBits = ( ( <NUM_LIT> << ( uint64_t ) BitWidth ) - <NUM_LIT> ) & <NUM_LIT> ; if ( ( AmtVal & UpperBits ) != UpperBits ) { auto NewMaskValue = ( AmtVal & <NUM_LIT> ) | UpperBits ; auto NewMask = DAG . getConstant ( NewMaskValue , SDLoc ( AndMaskOp ) , AndMaskOp . getValueType ( ) ) ; auto NewAnd = DAG . getNode ( N1 . getOpcode ( ) , SDLoc ( N1 ) , N1 . getValueType ( ) , AndOp , NewMask ) ; auto Replace = DAG . getNode ( N -> getOpcode ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NewAnd ) ; DCI . AddToWorklist ( Replace . getNode ( ) ) ; return Replace ; } } } } return SDValue ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : { unsigned BitWidth = Known . getBitWidth ( ) ; EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } break ; } case <STR_LIT> : case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSimpleVT ( ) ; unsigned BitWidth = Known . getBitWidth ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { assert ( BitWidth >= <NUM_LIT> && <STR_LIT> ) ; APInt Mask = APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; Known . Zero |= Mask ;

} else if ( VT == <STR_LIT> || VT == <STR_LIT> ) {


emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) , LCT_NORMAL , VOIDmode , <NUM_LIT> , XEXP ( m_tramp , <NUM_LIT> ) , Pmode ) ;


<s> AluKind AK = getAluKind ( QSrc [ i ] ) ;

AvailableAlus [ AK ] . push_back ( QSrc [ i ] ) ;


<s> rtx riscv_emit_move ( rtx dest , rtx src ) { return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ;


<s> default : return SDValue ( ) ; case <STR_LIT> : { assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } case <STR_LIT> : { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: PIC_ ) { SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } }


<s> auto LiveMask = LiveRegs [ U . RegUnit ] ; AtMIPressure . inc ( U . RegUnit , LiveMask , LiveMask | U . LaneMask , * MRI ) ; } MaxPressure = max ( AtMIPressure , MaxPressure ) ; for ( const auto & MO : MI . defs ( ) ) { if ( ! MO . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) || MO . isDead ( ) ) continue ; auto Reg = MO . getReg ( ) ; auto I = LiveRegs . find ( Reg ) ; if ( I == LiveRegs . end ( ) ) continue ; auto & LiveMask = I -> second ; auto PrevMask = LiveMask ; LiveMask &= ~ getDefRegMask ( MO , * MRI ) ; CurPressure . inc ( Reg , PrevMask , LiveMask , * MRI ) ; if ( LiveMask . none ( ) ) LiveRegs . erase ( I ) ; } for ( const auto & U : RegUses ) {

auto & LiveMask = LiveRegs [ U . RegUnit ] ;


<s> if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { llvm :: StringRef Sym = G -> getGlobal ( ) -> getName ( ) ; Function * F = G -> getGlobal ( ) -> getParent ( ) -> getFunction ( Sym ) ; if ( F && F -> hasFnAttribute ( <STR_LIT> ) ) { SpecialCallingConv = <STR_LIT> ; }


<s> if ( Cmp0 == APFloat :: cmpEqual ) return maxnum ( Src1 , Src2 ) ; APFloat :: cmpResult Cmp1 = Max3 . compare ( Src1 ) ; assert ( Cmp1 != APFloat :: cmpUnordered && <STR_LIT> ) ; if ( Cmp1 == APFloat :: cmpEqual ) return maxnum ( Src0 , Src2 ) ; return maxnum ( Src0 , Src1 ) ;


<s> bool <ISA_LIT>FastISel :: SelectFPToInt ( const Instruction * I , bool Signed ) { MVT DestVT ; if ( ! isTypeLegal ( I -> getType ( ) , DestVT ) || DestVT . isVector ( ) ) return false ; unsigned SrcReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( SrcVT == <STR_LIT> ) return false ; unsigned Opc ; if ( SrcVT == <STR_LIT> ) { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E , MCContext & Ctx ) {

auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Immediate , Ctx ) ;


<s> Align Alignment = std :: max ( TargetAlign , MaxAlign ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! FI -> mustSaveTOC ( ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = alignTo ( maxCallFrameSize , Alignment ) ;

if ( NewMaxCallFrameSize ) * NewMaxCallFrameSize = maxCallFrameSize ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( ( M [ i ] >= <NUM_LIT> && static_cast < unsigned > ( M [ i ] ) != i + WhichResult ) || ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && static_cast < unsigned > ( M [ i + <NUM_LIT> ] ) != i + NumElts + WhichResult ) ) return false ; } return true ;


<s> void dumpStack ( ) const { cerr << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != StackTop ; ++ i ) { cerr << <STR_LIT> << Stack [ i ] ; assert ( RegMap [ Stack [ i ] ] == i && <STR_LIT> ) ;


<s> static const MCPhysReg GeneralDoubleLow8RegDecoderTable [ ] = {


<s> std :: vector < <ISA_LIT>FrameSortingObject > SortingObjects ( MFI -> getObjectIndexEnd ( ) ) ; for ( auto & Obj : ObjectsToAllocate ) { SortingObjects [ Obj ] . IsValid = true ; SortingObjects [ Obj ] . ObjectIndex = Obj ; SortingObjects [ Obj ] . ObjectAlignment = MFI -> getObjectAlignment ( Obj ) ; int ObjectSize = MFI -> getObjectSize ( Obj ) ; if ( ObjectSize == <NUM_LIT> ) SortingObjects [ Obj ] . ObjectSize = <NUM_LIT> ; else SortingObjects [ Obj ] . ObjectSize = ObjectSize ; } for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . isDebugValue ( ) ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Index = MO . getIndex ( ) ; if ( Index >= <NUM_LIT> && Index < MFI -> getObjectIndexEnd ( ) && SortingObjects [ Index ] . IsValid ) SortingObjects [ Index ] . ObjectNumUses ++ ; } } } std :: stable_sort ( SortingObjects . begin ( ) , SortingObjects . end ( ) , <ISA_LIT>FrameSortingComparator ( ) ) ; int i = <NUM_LIT> ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> unsigned isDeviceBarrier = cast < ConstantSDNode > ( Op5 ) -> getZExtValue ( ) ; unsigned Opc = isDeviceBarrier ? <STR_LIT> : <STR_LIT> ; if ( Subtarget -> hasDataBarrier ( ) ) return DAG . getNode ( Opc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; else { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb1Only ( ) && <STR_LIT> ) ; return DAG . getNode ( Opc , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> void <ISA_LIT>AsmInstrumentation :: InstrumentInstruction ( const MCInst & Inst , SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCContext & Ctx , MCStreamer & Out ) {


<s> bool <ISA_LIT>InstrInfo :: SubsumesPredicate ( ArrayRef < MachineOperand > Pred1 , ArrayRef < MachineOperand > Pred2 ) const {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << to_hexstring ( Bundle ) << <STR_LIT> ) ; std :: bitset < <NUM_LIT> > bundle ; uint8_t bt ; int32_t val32 ; bundle = Bundle >> ( ( Extra . MayCompress ) ? <ISA_LIT>II :: Gen3SPUPredicateStart : <ISA_LIT>II :: SpuPredicateStart ) ; memcpy ( & bt , & bundle , <NUM_LIT> ) ; bt &= ( ( <NUM_LIT> << ( ( Extra . MayCompress ) ? <ISA_LIT>II :: Gen3SPUPredicateSize : <ISA_LIT>II :: SpuPredicateSize ) ) - <NUM_LIT> ) ; Extra . Predicate = bt ; bundle = Bundle >> ( <ISA_LIT>II :: SpuPolarityBit + ( ( Extra . MayCompress ) ? <ISA_LIT>II :: Gen3SPUStart : <ISA_LIT>II :: SPUStart ) ) ; memcpy ( & bt , & bundle , <NUM_LIT> ) ; bt &= <NUM_LIT> ;


<s> if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: x86 ) { Feat00Flags |= <NUM_LIT> ; } if ( M . getModuleFlag ( <STR_LIT> ) ) { Feat00Flags |= <NUM_LIT> ; } if ( M . getModuleFlag ( <STR_LIT> ) ) { Feat00Flags |= <NUM_LIT> ; } OutStreamer -> emitSymbolAttribute ( S , MCSA_Global ) ; OutStreamer -> emitAssignment ( S , MCConstantExpr :: create ( Feat00Flags , MMI -> getContext ( ) ) ) ; } OutStreamer -> emitSyntaxDirective ( ) ; bool is16 = TT . getEnvironment ( ) == Triple :: CODE16 ;

if ( M . getModuleInlineAsm ( ) . empty ( ) && is16 ) OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ;


<s> unsigned llvm :: getBLRCallOpcode ( const MachineFunction & MF ) {

if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hardenSlsBlr ( ) ) return <STR_LIT> ;


<s> llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) ) . addReg ( SourceRegister , getKillRegState ( IsKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addImm ( LPAC :: ADD ) ;


<s> if ( isVShiftRImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) { unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; } unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue NegShift = DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue NegShiftLeft = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Opc , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , NegShift ) ;


<s> unsigned Flag = ELF :: EF_CPU0_NOREORDER ;


<s> static std :: string computeDataLayout ( const Triple & TT ) { std :: string Ret ;


<s> SDValue Increment = DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Alignment ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , std :: min ( <NUM_LIT> , Alignment ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getUNDEF ( RegVT ) ; NewVec = Insert128BitVector ( NewVec , Load1 , <NUM_LIT> , DAG , dl ) ; NewVec = Insert128BitVector ( NewVec , Load2 , NumElems / <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo ( N , NewVec , TF , true ) ;


<s> void MandarinSubtarget :: anchor ( ) {


<s> unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( isSigned ) return - <NUM_LIT> << ( bits - <NUM_LIT> ) ;


<s> if ( Size <= <NUM_LIT> ) { unsigned MulOpc = Signed ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( MulOpc , SL , <STR_LIT> , N0 , N1 ) ; } unsigned MulLoOpc = Signed ? <STR_LIT> : <STR_LIT> ; unsigned MulHiOpc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue MulLo = DAG . getNode ( MulLoOpc , SL , <STR_LIT> , N0 , N1 ) ; SDValue MulHi = DAG . getNode ( MulHiOpc , SL , <STR_LIT> , N0 , N1 ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , MulLo , MulHi ) ;


<s> Value * Incoming = Phi -> getIncomingValue ( i ) ; BasicBlock * From = Phi -> getIncomingBlock ( i ) ; if ( isa < ConstantInt > ( Incoming ) ) { NewPhi -> addIncoming ( Broken , From ) ; continue ; } Phi -> setIncomingValue ( i , BoolFalse ) ; Value * PhiArg = handleLoopCondition ( Incoming , Broken , L , Term , LoopPhiConditions ) ; NewPhi -> addIncoming ( PhiArg , From ) ; } BasicBlock * IDom = DT -> getNode ( Parent ) -> getIDom ( ) -> getBlock ( ) ; for ( unsigned i = <NUM_LIT> , e = Phi -> getNumIncomingValues ( ) ; i != e ; ++ i ) { Value * Incoming = Phi -> getIncomingValue ( i ) ; if ( Incoming != BoolTrue ) continue ; BasicBlock * From = Phi -> getIncomingBlock ( i ) ; if ( From == IDom ) { CallInst * OldEnd = dyn_cast < CallInst > ( Parent -> getFirstInsertionPt ( ) ) ;

while ( OldEnd && OldEnd -> getCalledFunction ( ) != EndCf ) OldEnd = dyn_cast < CallInst > ( OldEnd -> getNextNode ( ) ) ;


<s> unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( U ) Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ( <STR_LIT> , imm ) ) ) ; else Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ( <STR_LIT> , imm ) ) ) ; return S ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue NandAB = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS ) ; SDValue NandABNandA = DAG . getNode ( <STR_LIT> , DL , VT , NandAB , LHS ) ; SDValue NandABNandB = DAG . getNode ( <STR_LIT> , DL , VT , NandAB , RHS ) ;

SDValue Xor = DAG . getNode ( <STR_LIT> , DL , VT , NandABNandA , NandABNandB ) ;


<s> MIB . addReg ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << From -> getName ( ) << <STR_LIT> << To -> getName ( ) << <STR_LIT> << * MIB . getInstr ( ) ) ; } } ; if ( BBPrevious -> isSuccessor ( BB ) ) FixFallthrough ( BBPrevious , BB ) ; if ( AfterNext && After -> isSuccessor ( AfterNext ) ) FixFallthrough ( After , AfterNext ) ; if ( BBNext && BB -> isSuccessor ( BBNext ) ) FixFallthrough ( BB , BBNext ) ;

BBUtils -> adjustBBOffsetsAfter ( After ) ;


<s> case <STR_LIT> : break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & sti , MCAsmParser & Parser , const MCInstrInfo & mii , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , sti ) , MII ( mii ) , InstInfo ( nullptr ) { setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ;

Instrumentation . reset ( Create<ISA_LIT>AsmInstrumentation ( Options , Parser . getContext ( ) , STI ) ) ;


<s> bool AMDGPUCFGStructurizer :: hasBackEdge ( MachineBasicBlock * MBB ) const { MachineLoop * LoopRep = MLI -> getLoopFor ( MBB ) ; if ( ! LoopRep ) return false ; MachineBasicBlock * LoopHeader = LoopRep -> getHeader ( ) ;

return MBB -> isSuccessor ( LoopHeader ) ;


<s> bool AllDead = true ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; Register R = Op . getReg ( ) ; if ( ! R . isVirtual ( ) || ! isDead ( R ) ) { AllDead = false ; break ; } Regs . push_back ( R ) ; } if ( ! AllDead ) continue ; B -> erase ( MI ) ;

for ( unsigned i = <NUM_LIT> , n = Regs . size ( ) ; i != n ; ++ i ) MRI . markUsesInDebugValueAsUndef ( Regs [ i ] ) ;


<s> case <STR_LIT> : return & AMDGPU :: R600_TReg32RegClass ; }


<s> } SkipInstruction = false ; if ( MapDefNotCollected ) { processGlobals ( true ) ; MapDefNotCollected = false ; } std :: unordered_map < uint32_t , StringRef > FuncArgNames ; for ( const DINode * DN : SP -> getRetainedNodes ( ) ) { if ( const auto * DV = dyn_cast < DILocalVariable > ( DN ) ) { uint32_t Arg = DV -> getArg ( ) ; if ( Arg ) { visitTypeEntry ( DV -> getType ( ) ) ; FuncArgNames [ Arg ] = DV -> getName ( ) ; } } } uint32_t ProtoTypeId ; visitSubroutineType ( SP -> getType ( ) , true , FuncArgNames , ProtoTypeId ) ; uint8_t Scope = SP -> isLocalToUnit ( ) ? <STR_LIT> : <STR_LIT> ; auto FuncTypeEntry = std :: make_unique < BTFTypeFunc > ( SP -> getName ( ) , ProtoTypeId , Scope ) ; uint32_t FuncTypeId = addType ( std :: move ( FuncTypeEntry ) ) ; for ( const auto & TypeEntry : TypeEntries ) TypeEntry -> completeType ( * this ) ; MCSymbol * FuncLabel = Asm -> getFunctionBegin ( ) ; BTFFuncInfo FuncInfo ; FuncInfo . Label = FuncLabel ; FuncInfo . TypeId = FuncTypeId ;


<s> if ( MBB -> pred_size ( ) == <NUM_LIT> && Loop != nullptr && Loop -> getHeader ( ) == MBB ) { for ( auto I = MBB -> pred_begin ( ) ; I != MBB -> pred_end ( ) ; ++ I ) if ( Loop -> contains ( * I ) ) PredMBB = ( * I == MBB ? nullptr : * I ) ; }

assert ( ( PredMBB == nullptr || ! Loop || Loop -> contains ( PredMBB ) ) && <STR_LIT> ) ;


<s> void spu_split_convert ( rtx ops [ ] ) { if ( REGNO ( ops [ <NUM_LIT> ] ) == REGNO ( ops [ <NUM_LIT> ] ) ) emit_note ( NOTE_INSN_DELETED ) ; else {

rtx op0 = gen_rtx_REG ( TImode , REGNO ( ops [ <NUM_LIT> ] ) ) ;


<s> unsigned LiteralPair0 = Literals [ i ] ; unsigned LiteralPair1 = ( i + <NUM_LIT> < e ) ? Literals [ i + <NUM_LIT> ] : <NUM_LIT> ; InsertPos = BuildMI ( MBB , InsertPos -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( LiteralPair0 ) . addImm ( LiteralPair1 ) ; }


<s> return getSubExpr ( ) -> findAssociatedFragment ( ) ;


<s> void <ISA_LIT>ScheduleDAGMI :: fillVgprSgprCost ( _Iterator First , _Iterator End , unsigned & VgprUsage , unsigned & SgprUsage ) { VgprUsage = <NUM_LIT> ; SgprUsage = <NUM_LIT> ; for ( _Iterator RegI = First ; RegI != End ; ++ RegI ) { unsigned Reg = * RegI ; if ( ! Register :: isVirtualRegister ( Reg ) ) continue ; PSetIterator PSetI = MRI . getPressureSets ( Reg ) ; for ( ; PSetI . isValid ( ) ; ++ PSetI ) { if ( * PSetI == <STR_LIT> :: VGPR_32 ) VgprUsage += PSetI . getWeight ( ) ;

else if ( * PSetI == <STR_LIT> :: SReg_32 ) SgprUsage += PSetI . getWeight ( ) ;


<s> const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; SmallVector < std :: pair < unsigned , bool > , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetDarwin ( ) ) ) continue ; bool isKill = true ; if ( Reg == <STR_LIT> ) { if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; }


<s> AMDGPUIntrinsicInfo :: AMDGPUIntrinsicInfo ( TargetMachine * tm ) : TargetIntrinsicInfo ( ) {


<s> setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; bool Split = false ; LLT Ty = MRI . getType ( VRegs [ i ] ) ; unsigned Dst = VRegs [ i ] ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , F . getCallingConv ( ) , [ & ] ( unsigned Reg , uint64_t Offset ) { if ( ! Split ) { Split = true ; Dst = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildUndef ( Dst ) ; } unsigned Tmp = MRI . createGenericVirtualRegister ( Ty ) ; MIRBuilder . buildInsert ( Tmp , Dst , Reg , Offset ) ; Dst = Tmp ; } ) ; if ( Dst != VRegs [ i ] ) MIRBuilder . buildCopy ( VRegs [ i ] , Dst ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; FormalArgHandler Handler ( MIRBuilder , MRI , AssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( F . isVarArg ( ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) { return false ; } uint64_t StackOffset = alignTo ( Handler . StackUsed , <NUM_LIT> ) ; auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setVarArgsStackIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackOffset , true ) ) ; }


<s> case Immediate : Inst . addOperand ( MCOperand :: createImm ( getImm ( ) ) ) ; break ; case ContextImmediate : Inst . addOperand ( MCOperand :: createImm ( getImmS16Context ( ) ) ) ; break ; default : Inst . addOperand ( MCOperand :: createExpr ( getExpr ( ) ) ) ; break ; }


<s> Ret += DataLayout :: getManglingComponent ( ST . getTargetTriple ( ) ) ; if ( ST . isTarget64BitILP32 ( ) || ! ST . is64Bit ( ) ) Ret += <STR_LIT> ; if ( ST . is64Bit ( ) || ST . isTargetCygMing ( ) || ST . isTargetWindows ( ) || ST . isTargetNaCl ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . isTargetNaCl ( ) ) ; else if ( ST . is64Bit ( ) || ST . isTargetDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . is64Bit ( ) ) Ret += <STR_LIT> ;


<s> if ( isa < LoadInst > ( Inst ) && isAcquireOrStronger ( Ord ) ) return Builder . CreateFence ( AtomicOrdering :: Acquire ) ;


<s> fix -> minipool = NULL ; gcc_assert ( fix -> forwards || fix -> backwards ) ; if ( ARM_DOUBLEWORD_ALIGN && fix -> fix_size >= <NUM_LIT> ) minipool_pad = <NUM_LIT> ; if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , GET_MODE_NAME ( mode ) , INSN_UID ( insn ) , ( unsigned long ) address , - <NUM_LIT> * ( long ) fix -> backwards , ( long ) fix -> forwards ) ; arm_print_value ( dump_file , fix -> value ) ; fprintf ( dump_file , <STR_LIT> ) ; } fix -> next = NULL ; if ( minipool_fix_head != NULL ) minipool_fix_tail -> next = fix ; else minipool_fix_head = fix ;


<s> if ( ! IsTailCallConvention ( CalleeCC ) && CalleeCC != CallingConv :: C ) return false ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; const Function * CallerF = DAG . getMachineFunction ( ) . getFunction ( ) ; CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; if ( GuaranteedTailCallOpt ) { if ( IsTailCallConvention ( CalleeCC ) && CCMatch ) return true ; return false ; } if ( RegInfo -> needsStackRealignment ( MF ) ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( ! CCMatch && CallerCC == CallingConv :: <ISA_LIT>_StdCall ) return false ; if ( isVarArg && ! Outs . empty ( ) ) { if ( Subtarget -> isTargetWin64 ( ) ) return false ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) if ( ! ArgLocs [ i ] . isRegLoc ( ) ) return false ; } bool Unused = false ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) { if ( ! Ins [ i ] . Used ) { Unused = true ; break ; } } if ( Unused ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CalleeCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCMatch ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ;

SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ;


<s> MachineInstr * MI = & * It ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool Is128B = HST . useHVXDblOps ( ) ; auto * RC = ! Is128B ? & <STR_LIT> : & <STR_LIT> ;

unsigned NeedAlign = RC -> getAlignment ( ) ;


<s> rs6000_call_darwin_1 ( value , func_desc , tlsarg , cookie , true ) ; gcc_unreachable ( ) ;


<s> TRI = Subtarget . getRegisterInfo ( ) ; bool Changed = false ; for ( MachineFunction :: iterator FI = MF . begin ( ) , FE = MF . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ;


<s> if ( MRI . getType ( Reg ) . getSizeInBits ( ) != ExpectedSize ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( RBI . getRegBank ( Reg , MRI , TRI ) -> getID ( ) != ExpectedRegBankID ) {


<s> if ( emitPseudoExpansionLowering ( * OutStreamer , MI ) ) return ; const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; <ISA_LIT>MCInstLower MCInstLowering ( OutContext , STI , * this ) ; StringRef Err ; if ( ! STI . getInstrInfo ( ) -> verifyInstruction ( * MI , Err ) ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getContext ( ) ; C . emitError ( <STR_LIT> + Err ) ; MI -> print ( errs ( ) ) ; } if ( MI -> isBundle ( ) ) { const MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineBasicBlock :: const_instr_iterator I = ++ MI -> getIterator ( ) ; while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( <STR_LIT> + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; }


<s> bool isImm24bit ( ) const { return isImmediate < <NUM_LIT> , <NUM_LIT> + <NUM_LIT> > ( ) ;


<s> if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : {

if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || Subtarget -> isLittle ( ) ) ) {


<s> if ( IsCRField ) { <ISA_LIT>FunctionInfo * FuncInfo = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! Subtarget . is32BitELFABI ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) , I . getFrameIdx ( ) ) ) ; } } else { if ( I . isSpilledToReg ( ) ) { unsigned Dst = I . getDstReg ( ) ; if ( Spilled [ Dst ] ) continue ; if ( VSRContainingGPRs [ Dst ] . second != <NUM_LIT> ) { assert ( Subtarget . hasP9Vector ( ) && <STR_LIT> ) ; NumPESpillVSR += <NUM_LIT> ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( VSRContainingGPRs [ Dst ] . first , getKillRegState ( true ) ) . addReg ( VSRContainingGPRs [ Dst ] . second , getKillRegState ( true ) ) ; } else if ( VSRContainingGPRs [ Dst ] . second == <NUM_LIT> ) { assert ( Subtarget . hasP8Vector ( ) && <STR_LIT> ) ; ++ NumPESpillVSR ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , TRI -> getSubReg ( Dst , <STR_LIT> ) ) . addReg ( VSRContainingGPRs [ Dst ] . first , getKillRegState ( true ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } Spilled . set ( Dst ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; if ( Subtarget . needsSwapsForVSXMemOps ( ) && ! MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) TII . storeRegToStackSlotNoUpd ( MBB , MI , Reg , ! IsLiveIn , I . getFrameIdx ( ) , RC , TRI ) ; else TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , I . getFrameIdx ( ) , RC , TRI ) ;


<s> static void arm_init_fp16_builtins ( void ) { tree fp16_type = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( fp16_type ) = <NUM_LIT> ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addRequired < MachineFunctionAnalysis > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ;

AU . addRequired < MachinePostDominatorTree > ( ) ;


<s> unsigned count = <NUM_LIT> ; while ( * p && isspace ( * p ) && * p != '\n' ) p ++ ; count ++ ; while ( * p && * p != '\n' && strncmp ( p , BaseTAI :: CommentString , strlen ( BaseTAI :: CommentString ) ) != <NUM_LIT> ) {


<s> vector < Constant * > SCEVParser :: createAString ( std :: string input , Type * Int8Ty ) { vector < Constant * > Init ; for ( unsigned i = <NUM_LIT> ; i < input . size ( ) ; i ++ ) { Init . push_back ( ConstantInt :: get ( Int8Ty , input [ i ] ) ) ;


<s> const DenseSet < StringRef > & getAttributes ( ) const override {


<s> assert ( OpIdx >= <NUM_LIT> && <STR_LIT> ) ;

MIB . addImm ( MI . getOperand ( OpIdx ) . getImm ( ) | <STR_LIT> :: GLC ) ;


<s>
<STR_LIT>
ShOpc
=
<STR_LIT>
(
MO3
.
getImm
(
)
)
;
O
<<
<STR_LIT>
<<
<STR_LIT>
(
ShOpc
)
;
if
(
MO2
.
getReg
(
)
)
{
O
<<
' '
<<
getRegisterName
(
MO2
.
getReg
(
)
)
;
assert
(
<STR_LIT>
(
MO3
.
getImm
(
)
)
==
<NUM_LIT>
)
;


<s> if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , <NUM_LIT> ) ; if ( reload_completed && ( LABEL_REF_P ( ind ) || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , <NUM_LIT> ) ; if ( wb_level > <NUM_LIT> && ( GET_CODE ( ind ) == POST_INC || GET_CODE ( ind ) == PRE_DEC || ( wb_level > <NUM_LIT> && ( GET_CODE ( ind ) == PRE_INC || GET_CODE ( ind ) == POST_DEC ) ) ) ) return arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ; if ( wb_level > <NUM_LIT> && ( GET_CODE ( ind ) == POST_MODIFY || GET_CODE ( ind ) == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( ind , <NUM_LIT> ) ) ) ind = XEXP ( ind , <NUM_LIT> ) ; int factor = MIN ( GET_MODE_SIZE ( GET_MODE ( op ) ) , <NUM_LIT> ) ;

if ( GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , <NUM_LIT> ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , <NUM_LIT> ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , <NUM_LIT> ) ) && IN_RANGE ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) , - <NUM_LIT> * factor , <NUM_LIT> * factor ) && ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) & ( factor - <NUM_LIT> ) ) == <NUM_LIT> ) return TRUE ;


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; SDLoc dl ( InputVector ) ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InputVector ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( <STR_LIT> ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf , ShAmt ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf , ShAmt ) ) ; } else { SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; EVT ElementType = InputVector . getValueType ( ) . getVectorElementType ( ) ; unsigned EltSize = ElementType . getSizeInBits ( ) / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t Offset = EltSize * i ; SDValue OffsetVal = DAG . getConstant ( Offset , TLI . getPointerTy ( ) ) ; SDValue ScalarAddr = DAG . getNode ( <STR_LIT> , dl , TLI . getPointerTy ( ) , StackPtr , OffsetVal ) ; Vals [ i ] = DAG . getLoad ( ElementType , dl , Ch , ScalarAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } } for ( SmallVectorImpl < SDNode * > :: iterator UI = Uses . begin ( ) , UE = Uses . end ( ) ; UI != UE ; ++ UI ) { SDNode * Extract = * UI ; SDValue Idx = Extract -> getOperand ( <NUM_LIT> ) ; uint64_t IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Extract , <NUM_LIT> ) , Vals [ IdxVal ] ) ; }


<s> host_basic_info_data_t hostInfo ; mach_msg_type_number_t infoCount ; infoCount = HOST_BASIC_INFO_COUNT ; host_info ( mach_host_self ( ) , HOST_BASIC_INFO , ( host_info_t ) & hostInfo , & infoCount ) ; if ( hostInfo . cpu_type != CPU_TYPE_POWERPC ) return <STR_LIT> ; switch ( hostInfo . cpu_subtype ) { case CPU_SUBTYPE_POWERPC_601 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_602 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_603 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_603e : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_603ev : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_604 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_604e : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_620 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_750 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_7400 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_7450 : return <STR_LIT> ; case CPU_SUBTYPE_POWERPC_970 : return <STR_LIT> ; default : ; } return <STR_LIT> ;


<s> CONSTEXPR svmatch_svnmatch_impl ( int unspec ) : m_unspec ( unspec ) {


<s> if ( Count % <NUM_LIT> ) return false ; while ( Count >= <NUM_LIT> ) { OS . write ( <STR_LIT> , <NUM_LIT> ) ; Count -= <NUM_LIT> ;


<s> if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ; else if ( CM == CodeModel :: JITDefault ) CM = CodeModel :: Large ;

else if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) report_fatal_error ( <STR_LIT> ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveModuleFP ( <STR_LIT> Value , bool Is32BitABI ) { <ISA_LIT>TargetStreamer :: emitDirectiveModuleFP ( Value , Is32BitABI ) ; StringRef ModuleValue ;


<s> <ISA_LIT>MCAsmInfoMicrosoft :: <ISA_LIT>MCAsmInfoMicrosoft ( const Triple & Triple ) { if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PointerSize = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: WinEH ; } AssemblerDialect = AsmWriterFlavor ;


<s> case TLSModel :: LocalDynamic : { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Offset = lowerTLSGetOffset ( Node , DAG , <STR_LIT> , Offset ) ; <ISA_LIT>MachineFunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; CPV = <ISA_LIT>ConstantPoolValue :: Create ( GV , <STR_LIT> ) ; SDValue DTPOffset = DAG . getConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; DTPOffset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , DTPOffset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ;

Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Offset , DTPOffset ) ;


<s> unsigned ValueEnumerator :: getInstructionID ( const Instruction * Inst ) const { InstructionMapType :: const_iterator I = InstructionMap . find ( Inst ) ; assert ( I != InstructionMap . end ( ) && <STR_LIT> ) ;


<s> emit_insn ( gen_xorv16qi3 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_xorv16qi3 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; } else if ( ! reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , destlo ) ) { if ( src1 != dest ) emit_move_insn ( destlo , operands [ <NUM_LIT> ] ) ; if ( src2 != dest + halfregs ) emit_move_insn ( desthi , operands [ <NUM_LIT> ] ) ; } else {


<s> break ; case MCK__HASH_8 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK__HASH_16 : if ( Op . isImm ( ) ) if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ; break ; case MCK_ModImm : if ( Op . isImm ( ) ) { const MCExpr * SOExpr = Op . getImm ( ) ; int64_t Value ; if ( ! SOExpr -> evaluateAsAbsolute ( Value ) ) return Match_Success ; assert ( ( Value >= std :: numeric_limits < int32_t > :: min ( ) && Value <= std :: numeric_limits < uint32_t > :: max ( ) ) && <STR_LIT> ) ; } break ; case MCK_rGPR : if ( hasV8Ops ( ) && Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) return Match_Success ; return Match_rGPR ; case MCK_GPRPair :

if ( Op . isReg ( ) && MRI -> getRegClass ( <STR_LIT> ) . contains ( Op . getReg ( ) ) ) return Match_Success ;


<s> virtual const char * getPassName ( ) const override {


<s> assert ( Idx % DstTy . getVectorNumElements ( ) == <NUM_LIT> ) ; ( void ) Idx ; const SDLoc & dl ( Op ) ; MVT ElemTy = SrcTy . getVectorElementType ( ) ; if ( ElemTy == <STR_LIT> ) return extractHvxSubvectorPred ( SrcV , IdxV , dl , DstTy , DAG ) ;

return extractHvxSubvectorReg ( SrcV , IdxV , dl , DstTy , DAG ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>LDCleanupPass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ;

assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> case <STR_LIT> : return ELF :: R_MICROBLAZE_NONE ; default :


<s> static unsigned int mips_machine_reorg2 ( void ) { mips_reorg_process_insns ( ) ;

if ( ! TARGET_MIPS16 && TARGET_EXPLICIT_RELOCS && TUNE_MIPS4130 && TARGET_VR4130_ALIGN ) vr4130_align_insns ( ) ;


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ;

SDValue RHS = Op . getOperand ( <NUM_LIT> ) ;


<s> AU . addRequired < TargetTransformInfoWrapperPass > ( ) ;


<s> static bool DisassembleLdStMiscFrm ( MCInst & MI , unsigned Opcode , uint32_t insn , unsigned short NumOps , unsigned & NumOpsAdded , bool isStore , BO B ) { const TargetInstrDesc & TID = <ISA_LIT>Insts [ Opcode ] ; bool isPrePost = isPrePostLdSt ( TID . TSFlags ) ; const TargetOperandInfo * OpInfo = TID . OpInfo ; if ( ! OpInfo ) return false ; unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; assert ( ( ( ! isStore && TID . getNumDefs ( ) > <NUM_LIT> ) || ( isStore && ( TID . getNumDefs ( ) == <NUM_LIT> || isPrePost ) ) ) && <STR_LIT> ) ; if ( isPrePost && isStore ) { assert ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } bool DualReg = HasDualReg ( Opcode ) ; if ( OpIdx >= NumOps ) return false ; assert ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; ++ OpIdx ; if ( DualReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) + <NUM_LIT> ) ) ) ; ++ OpIdx ; } if ( isPrePost && ! isStore ) { assert ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ;


<s> unsigned Reg = MO . getReg ( ) ; MachineRegisterInfo :: use_iterator nextI ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) , E = MRI -> use_end ( ) ; I != E ; I = nextI ) { nextI = std :: next ( I ) ; MachineOperand & Use = * I ; MachineInstr * UseMI = I -> getParent ( ) ; if ( UseMI == MI ) continue ; if ( Use . isDebug ( ) ) UseMI -> getOperand ( <NUM_LIT> ) . setReg ( <NUM_LIT> ) ;


<s> assert ( ( ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) + ( ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ) ) == <NUM_LIT> ) ;


<s> __o = __builtin_aarch64_set_qregxiv4si ( __o , ( int32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv4si ( __o , ( int32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv4si ( __o , ( int32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv4si ( __o , ( int32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __builtin_aarch64_st4v4si ( ( __builtin_aarch64_simd_si * ) __a , __o ) ;


<s> unsigned FrameReg = <STR_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MF . getFrameInfo ( ) -> getStackSize ( ) + SPAdj ; if ( MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ) { assert ( SPAdj == <NUM_LIT> && STI . getFrameLowering ( ) -> hasFP ( MF ) && <STR_LIT> ) ; if ( ! hasBasePointer ( MF ) ) { FrameReg = getFrameRegister ( MF ) ; Offset -= AFI -> getFramePtrSpillOffset ( ) ; } else FrameReg = BasePtr ; } if ( RS && FrameReg == <STR_LIT> && RS -> isScavengingFrameIndex ( FrameIndex ) ) { assert ( STI . getFrameLowering ( ) -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( AFI -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { unsigned TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ;


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) { assert ( ( Modifier == nullptr || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { O << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << formatImm ( ( int32_t ) Op . getImm ( ) ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ;


<s> static inline ChildIteratorType child_end ( NodeRef N ) {


<s> StringRef Name ; if ( check ( getParser ( ) . parseIdentifier ( Name ) , L , <STR_LIT> ) || parseToken ( AsmToken :: EndOfStatement ) ) return true ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Name ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , getContext ( ) ) ; Expr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_TLSDESC , getContext ( ) ) ; MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; getParser ( ) . getStreamer ( ) . EmitInstruction ( Inst , getSTI ( ) ) ; return false ;


<s> ++ SplitPoint ; if ( SplitPoint == BB -> end ( ) ) { MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; return BB ; } MachineFunction * MF = BB -> getParent ( ) ; MachineBasicBlock * SplitBB = MF -> CreateMachineBasicBlock ( BB -> getBasicBlock ( ) ) ; for ( MachineBasicBlock * Succ : BB -> successors ( ) ) { for ( MachineInstr & MI : * Succ ) { if ( ! MI . isPHI ( ) ) break ; for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I != E ; I += <NUM_LIT> ) { MachineOperand & FromBB = MI . getOperand ( I ) ; if ( BB == FromBB . getMBB ( ) ) { FromBB . setMBB ( SplitBB ) ; break ; } } } } MF -> insert ( ++ MachineFunction :: iterator ( BB ) , SplitBB ) ; SplitBB -> splice ( SplitBB -> begin ( ) , BB , SplitPoint , BB -> end ( ) ) ; SplitBB -> transferSuccessors ( BB ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitCCTopData ( StringRef Name ) {


<s> bbs = get_loop_body ( loop ) ; for ( i = <NUM_LIT> ; i < loop -> num_nodes ; i ++ ) if ( mn10300_block_contains_call ( bbs [ i ] ) ) { result = true ; break ; }


<s> rtx mema , wide_result ; int last_byte_offset ; HOST_WIDE_INT byte_offset = bit_offset / BITS_PER_UNIT ; mode = GET_MODE ( dest_reg ) ; hi = gen_reg_rtx ( mode ) ; if ( bitsize == <NUM_LIT> * BITS_PER_UNIT && ( bit_offset % BITS_PER_UNIT ) == <NUM_LIT> ) { rtx lo ; mem_lo = adjust_address ( mem , QImode , byte_offset ) ; mem_hi = adjust_address ( mem , QImode , byte_offset + <NUM_LIT> ) ; lo = gen_reg_rtx ( mode ) ; emit_insn ( gen_zero_extendqisi2 ( lo , mem_lo ) ) ; if ( sign ) { rtx tmp = gen_reg_rtx ( mode ) ; emit_insn ( gen_extendqisi2 ( gen_lowpart ( SImode , hi ) , mem_hi ) ) ; emit_insn ( gen_ashlsi3 ( gen_lowpart ( SImode , tmp ) , gen_lowpart ( SImode , hi ) , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_iorsi3 ( gen_lowpart ( SImode , dest_reg ) , gen_lowpart ( SImode , lo ) , gen_lowpart ( SImode , tmp ) ) ) ; } else { emit_insn ( gen_zero_extendqisi2 ( gen_lowpart ( SImode , hi ) , mem_hi ) ) ; emit_insn ( gen_insn_intlb ( gen_lowpart ( SImode , dest_reg ) , gen_lowpart ( SImode , hi ) , gen_lowpart ( SImode , lo ) ) ) ; } return ; } mema = XEXP ( mem , <NUM_LIT> ) ; addr_lo = force_reg ( Pmode , plus_constant ( Pmode , mema , byte_offset ) ) ; mem_lo = change_address ( mem , mode , gen_rtx_AND ( Pmode , addr_lo , GEN_INT ( - <NUM_LIT> ) ) ) ; set_mem_alias_set ( mem_lo , <NUM_LIT> ) ; last_byte_offset = ( bit_offset + bitsize - <NUM_LIT> ) / BITS_PER_UNIT ; addr_hi = force_reg ( Pmode , plus_constant ( Pmode , mema , last_byte_offset ) ) ; mem_hi = change_address ( mem , mode , gen_rtx_AND ( Pmode , addr_hi , GEN_INT ( - <NUM_LIT> ) ) ) ; set_mem_alias_set ( mem_hi , <NUM_LIT> ) ; if ( bitsize == <NUM_LIT> ) { addr_lo = make_safe_from ( addr_lo , dest_reg ) ; wide_result = dest_reg ;


<s> return reload_completed && visium_frame_size == <NUM_LIT> && ! visium_interrupt_function_p ( ) ;


<s> case CASE_WIDEOP_OPCODE_LMULS ( FWSUB_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WADD_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WADDU_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUB_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUBU_WV ) : { unsigned NewOpc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADDU_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUBU_WV ) } MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . copyImplicitOps ( MI ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ;


<s> case InlineAsm :: Constraint_m : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ;


<s> x = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( reloc ) ) , UNSPEC_RELOC32 ) ; x = gen_rtx_CONST ( Pmode , x ) ; if ( temp_reg == NULL ) { gcc_assert ( can_create_pseudo_p ( ) ) ; temp_reg = gen_reg_rtx ( Pmode ) ;


<s> prepareVolatileOrAtomicLoad ( SDValue Chain , SDLoc DL , SelectionDAG & DAG ) const {

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ;


<s> Instruction * <ISA_LIT>EmitIntrinsics :: visitSwitchInst ( SwitchInst & I ) { SmallVector < Value * , <NUM_LIT> > Args ; for ( auto & Op : I . operands ( ) ) if ( Op . get ( ) -> getType ( ) -> isSized ( ) ) Args . push_back ( Op ) ; IRB -> CreateIntrinsic ( <STR_LIT> , { I . getOperand ( <NUM_LIT> ) -> getType ( ) } , { Args } ) ; return & I ;


<s> case TYPE_VK : case TYPE_DEBUGREG : case TYPE_CONTROLREG : case TYPE_BNDR : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_MVSIBX : case TYPE_MVSIBY : case TYPE_MVSIBZ : return translateRMMemory ( mcInst , insn , Dis ) ; case TYPE_MSIB : return translateRMMemory ( mcInst , insn , Dis , true ) ; }


<s> std :: pair < MachineOperand * , unsigned > Src = Srcs [ j ] ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << <NUM_LIT> ) | Chan ) ; } }


<s> if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = TII . getFrameSize ( Old ) ; if ( Amount != <NUM_LIT> ) { Amount = alignTo ( Amount , getStackAlignment ( ) ) ; unsigned Opc = Old . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ; } else { assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; emitSPUpdate ( MBB , I , TII , dl , * RegInfo , Amount ) ; }


<s> return __builtin_mve_vandq_uv8hi ( __a , __b ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ;

unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ;


<s> generateInstSeqImpl ( ShiftedVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , LeadingZeros ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; } if ( LeadingZeros == <NUM_LIT> && ActiveFeatures [ <STR_LIT> ] ) { uint64_t LeadingOnesVal = Val | maskLeadingOnes < uint64_t > ( LeadingZeros ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( LeadingOnesVal , ActiveFeatures , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) { Res = TmpSeq ; if ( Res . size ( ) <= <NUM_LIT> ) return Res ; }


<s> const unsigned CmpWidth = MRI . getType ( LHS ) . getSizeInBits ( ) ; unsigned CBOpc = <NUM_LIT> ; if ( CmpWidth <= <NUM_LIT> ) CBOpc = ( Pred == CmpInst :: ICMP_EQ ? <STR_LIT> : <STR_LIT> ) ; else if ( CmpWidth == <NUM_LIT> ) CBOpc = ( Pred == CmpInst :: ICMP_EQ ? <STR_LIT> : <STR_LIT> ) ; else return false ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( CBOpc ) ) . addUse ( LHS ) . addMBB ( DestMBB ) . constrainAllUses ( TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return true ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * A << <STR_LIT> << * B << <STR_LIT> ) ; Value * Ptr = BasePtr ; if ( Offset ) Ptr = IRB . CreateConstGEP1_32 ( Ptr , Offset ) ;

IRB . CreateCall ( StgpFn , { Ptr , A , B } ) ;


<s> for ( i = <NUM_LIT> ; i < CONST_WIDE_INT_NUNITS ( op ) ; i ++ ) ins += num_insns_constant_wide ( CONST_WIDE_INT_ELT ( op , i ) ) ; return ins ; } case CONST_DOUBLE : if ( mode == SFmode || mode == SDmode ) { long l ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL32 ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; else REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; return num_insns_constant_wide ( ( HOST_WIDE_INT ) l ) ; } long l [ <NUM_LIT> ] ; if ( DECIMAL_FLOAT_MODE_P ( mode ) ) REAL_VALUE_TO_TARGET_DECIMAL64 ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; else REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , l ) ; high = l [ WORDS_BIG_ENDIAN == <NUM_LIT> ] ; low = l [ WORDS_BIG_ENDIAN != <NUM_LIT> ] ;

if ( TARGET_32BIT ) return ( num_insns_constant_wide ( low ) + num_insns_constant_wide ( high ) ) ;


<s> rtx x ; x = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( x , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) , oldval ) ) ) ;

x = expand_simple_binop ( SImode , IOR , newval , x , x , <NUM_LIT> , OPTAB_LIB_WIDEN ) ;


<s> if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>CTRLoops ( ) ) ;


<s> <ISA_LIT>MCInstLower ( MCContext & Ctx , AsmPrinter & Printer ) : Ctx ( Ctx ) , Printer ( Printer ) {


<s> if ( MF . getFrameInfo ( ) -> hasCalls ( ) ) MRI . setPhysRegUsed ( <STR_LIT> ) ; else MRI . setPhysRegUnused ( <STR_LIT> ) ;


<s> } assert ( NumBits <= <NUM_LIT> ) ; <STR_LIT> LoID = IsSigned ? <STR_LIT> : <STR_LIT> ; <STR_LIT> HiID = IsSigned ? <STR_LIT> : <STR_LIT> ; Value * Lo = Builder . CreateIntrinsic ( LoID , { } , { LHS , RHS } ) ; Value * Hi = Builder . CreateIntrinsic ( HiID , { } , { LHS , RHS } ) ; IntegerType * I64Ty = Builder . getInt64Ty ( ) ; Lo = Builder . CreateZExtOrTrunc ( Lo , I64Ty ) ; Hi = Builder . CreateZExtOrTrunc ( Hi , I64Ty ) ;

return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , <NUM_LIT> ) ) ;


<s> const MCSymbolRefExpr * RefA = Target . getSymA ( ) ;

return RefA && RefA -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_GLOBAL ;


MCELFStreamer :: EmitInstruction ( Inst , STI ) ;


<s> static inline ChildIteratorType child_end ( NodeType * N ) {


<s> switch ( In ) { case MCDisassembler :: Success : return true ;


<s> unsigned <ISA_LIT>TargetLowering :: GetAlignedArgumentStackSize ( unsigned StackSize , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( TM . getSubtargetImpl ( ) -> getRegisterInfo ( ) ) ; const TargetFrameLowering & TFI = * TM . getSubtargetImpl ( ) -> getFrameLowering ( ) ; unsigned StackAlignment = TFI . getStackAlignment ( ) ; uint64_t AlignMask = StackAlignment - <NUM_LIT> ; int64_t Offset = StackSize ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask ) ) ; } else { Offset = ( ( ~ AlignMask ) & Offset ) + StackAlignment + ( StackAlignment - SlotSize ) ; }


<s> if ( ! isJump ( static_cast < MachineInstr * > ( I ) -> getOpcode ( ) ) ) { return false ; } while ( I != MBB . begin ( ) && std :: prev ( I ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PriorI = std :: prev ( I ) ; if ( AllowModify ) I -> removeFromParent ( ) ; I = PriorI ; } MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( static_cast < MachineInstr * > ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == <STR_LIT> ) { MachineInstr * predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( SecondLastOpc == <STR_LIT> && LastOpc == <STR_LIT> ) { MachineInstr * predSet = -- I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MachineOperand :: CreateReg ( <STR_LIT> , false ) ) ; return false ;


<s> if ( M . size ( ) != static_cast < size_t > ( NumInputElements ) ) return None ; int NumLHSMatch = <NUM_LIT> , NumRHSMatch = <NUM_LIT> ; int LastLHSMismatch = - <NUM_LIT> , LastRHSMismatch = - <NUM_LIT> ; for ( int Idx = <NUM_LIT> ; Idx < NumInputElements ; ++ Idx ) { if ( M [ Idx ] == - <NUM_LIT> ) { ++ NumLHSMatch ; ++ NumRHSMatch ; continue ; } M [ Idx ] == Idx ? ++ NumLHSMatch : LastLHSMismatch = Idx ; M [ Idx ] == Idx + NumInputElements ? ++ NumRHSMatch : LastRHSMismatch = Idx ; } const int NumNeededToMatch = NumInputElements - <NUM_LIT> ;

if ( NumLHSMatch == NumNeededToMatch ) return std :: make_pair ( true , LastLHSMismatch ) ;


<s> static rtx frv_read_argument ( tree exp , unsigned int index ) {

return expand_normal ( CALL_EXPR_ARG ( exp , index ) ) ;


<s> assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ;

<STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> return __builtin_mve_vsubq_m_n_sv16qi ( __arm_vuninitializedq_s8 ( ) , __a , __b , __p ) ;


<s> if ( isPreIncrementForm ( MI , AddOffset ) ) {

OS << <STR_LIT> << Opcode << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> << decIncOperator ( MI ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) << <STR_LIT> ;


<s> const auto * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return getOccupancyWithLocalMemSize ( MFI -> getLDSSize ( ) , * MF . getFunction ( ) ) ;


<s> GetExternalSymbolSymbol ( const MachineOperand & MO ) const {

return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ;


<s> dbgprintf ( insn , <STR_LIT> ) ; int vvvv ; if ( insn -> vectorExtensionType == TYPE_EVEX ) vvvv = ( v2FromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) << <NUM_LIT> | vvvvFromEVEX3of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) vvvv = vvvvFromVEX3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) vvvv = vvvvFromVEX2of2 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_XOP ) vvvv = vvvvFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else return - <NUM_LIT> ; if ( insn -> mode != MODE_64BIT ) vvvv &= <NUM_LIT> ; insn -> vvvv = static_cast < Reg > ( vvvv ) ;


<s> MCInst LRWInst ; MCInstLowering . Lower ( Instr , LRWInst ) ; EmitToStreamer ( * OutStreamer , LRWInst ) ; Instr = BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addSym ( PCLabel ) ; MCInst GRSInst ; MCInstLowering . Lower ( Instr , GRSInst ) ; EmitToStreamer ( * OutStreamer , GRSInst ) ;


<s> case llvm :: ELF :: R_HEX_6_X : assert ( ! ( rsym -> reserved ( ) & ReserveRel ) && <STR_LIT> ) ; return ; case llvm :: ELF :: R_HEX_32 : if ( ld_backend . symbolNeedsPLT ( * rsym ) ) { if ( ! ( rsym -> reserved ( ) & ReservePLT ) ) { helper_PLT_init ( pReloc , * this ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReservePLT ) ; } } if ( ld_backend . symbolNeedsDynRel ( * rsym , ( rsym -> reserved ( ) & ReservePLT ) , true ) ) { if ( ld_backend . symbolNeedsCopyReloc ( pReloc , * rsym ) ) { LDSymbol & cpy_sym = defineSymbolforCopyReloc ( pBuilder , * rsym , ld_backend ) ; addCopyReloc ( * cpy_sym . resolveInfo ( ) , ld_backend ) ; } else { Relocation & reloc = helper_DynRel_init ( rsym , * pReloc . targetRef ( ) . frag ( ) , pReloc . targetRef ( ) . offset ( ) , llvm :: ELF :: R_HEX_RELATIVE , * this ) ; getRelRelMap ( ) . record ( pReloc , reloc ) ; rsym -> setReserved ( rsym -> reserved ( ) | ReserveRel ) ; ld_backend . checkAndSetHasTextRel ( * pSection . getLink ( ) ) ; } } return ; case llvm :: ELF :: R_HEX_GOTREL_LO16 : case llvm :: ELF :: R_HEX_GOTREL_HI16 : case llvm :: ELF :: R_HEX_GOTREL_32 : case llvm :: ELF :: R_HEX_GOTREL_32_6_X : case llvm :: ELF :: R_HEX_GOTREL_16_X :


<s> const MachineFunction * MF = MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const MachineInstr * Def = MRI . getVRegDef ( MO . getReg ( ) ) ; if ( ! Def ) return false ; if ( Def -> getOpcode ( ) == <STR_LIT> ) { C = Def -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; return true ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> if ( NumLoads > <NUM_LIT> ) return false ; if ( ! isPairableLdStInst ( FirstLdSt ) || ! isPairableLdStInst ( SecondLdSt ) ) return false ; unsigned FirstOpc = FirstLdSt . getOpcode ( ) ; unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ;


<s> else if ( TARGET_SOFT_FLOAT_ABI ) abi = <STR_LIT> ; else abi = <STR_LIT> ;

return build_string_literal ( strlen ( abi ) + <NUM_LIT> , abi ) ;


<s> MachineBasicBlock * <ISA_LIT>CFGStructurizer :: getLoopLandInfo ( MachineLoop * LoopRep ) const { LoopLandInfoMap :: const_iterator It = LLInfoMap . find ( LoopRep ) ; if ( It == LLInfoMap . end ( ) ) return nullptr ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << '\n' ) ; LLVM_DEBUG ( F . dump ( ) ) ; bool Changed = false ; const <ISA_LIT>Subtarget & Subtarget = F . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = Subtarget . getInstrInfo ( ) ; TRI = Subtarget . getRegisterInfo ( ) ; for ( MachineFunction :: iterator FI = F . begin ( ) , FE = F . end ( ) ; FI != FE ; ++ FI ) Changed |= runOnMachineBasicBlock ( * FI ) ; if ( Changed ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( F . dump ( ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> if ( parseRegister ( Operands , true ) == MatchOperand_Success ) return false ; if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ;


<s> Modified = false ; for ( MachineLoop * I : LI ) for ( auto L = df_begin ( I ) , LE = df_end ( I ) ; L != LE ; ++ L ) if ( L -> empty ( ) ) runOnLoop ( * * L , Fn ) ; return Modified ;


<s> TailCallArgumentInfo ( ) : FrameIdx ( <NUM_LIT> ) {


<s> ParseMemory ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { SMLoc S , E ; assert ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) && <STR_LIT> ) ; S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & BaseRegTok = Parser . getTok ( ) ; if ( BaseRegTok . isNot ( AsmToken :: Identifier ) ) { Error ( BaseRegTok . getLoc ( ) , <STR_LIT> ) ; return true ; } int BaseRegNum = TryParseRegister ( ) ; if ( BaseRegNum == - <NUM_LIT> ) { Error ( BaseRegTok . getLoc ( ) , <STR_LIT> ) ; return true ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( ! Tok . is ( AsmToken :: Comma ) && ! Tok . is ( AsmToken :: RBrac ) ) return true ; bool Preindexed = false ; bool Postindexed = false ;


<s> assert ( Op . isReg ( ) ) ; if ( In . isCall ( ) ) if ( Op . isDef ( ) && Op . isDead ( ) ) return true ;


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) {

if ( ! RM . hasValue ( ) ) return Reloc :: PIC_ ;


if ( ! ( Subtarget . hasAVX2 ( ) && ( isShuffleMaskInputInPlace ( <NUM_LIT> , Mask ) || isShuffleMaskInputInPlace ( <NUM_LIT> , Mask ) ) ) ) if ( SDValue V = lowerShuffleByMerging128BitLanes ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return V ;


<s> initializeGCNRegBankReassignPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> std :: pair < MachineOperand * , unsigned > Src = Srcs [ j ] ; if ( Src . first -> getReg ( ) == AMDGPU :: ALU_CONST ) Consts . push_back ( Src . second ) ; if ( AMDGPU :: R600_KC0RegClass . contains ( Src . first -> getReg ( ) ) || AMDGPU :: R600_KC1RegClass . contains ( Src . first -> getReg ( ) ) ) {

unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ;


<s> if ( ! MI . hasOneMemOperand ( ) ) return false ; const MachineMemOperand * MMO = * MI . memoperands_begin ( ) ; const unsigned AS = MMO -> getAddrSpace ( ) ; const bool IsConst = AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ; return MMO -> getAlign ( ) >= Align ( <NUM_LIT> ) && ! MMO -> isAtomic ( ) && ( IsConst || ! MMO -> isVolatile ( ) ) && ( IsConst || MMO -> isInvariant ( ) || memOpHasNoClobbered ( MMO ) ) && <ISA_LIT>InstrInfo :: isUniformMMO ( MMO ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; unsigned ArgNo = <NUM_LIT> ; for ( auto & Arg : Args ) { EVT VT = TLI . getValueType ( DL , Arg . Ty ) ;

MVT RegisterVT = TLI . getRegisterTypeForCallingConv ( F . getContext ( ) , F . getCallingConv ( ) , VT ) ;


<s> if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; int Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ; if ( Amount != <NUM_LIT> ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; MachineInstr * New ; if ( Old -> getOpcode ( ) == <STR_LIT> ) { New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - Amount ) ;


<s> SDNode * UpperHalfSign = CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , dl , <STR_LIT> , SDValue ( SignRot , <NUM_LIT> ) , getRC ( <STR_LIT> ) ) ; SDNode * UpperHalfSignMask = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperHalfSign , <NUM_LIT> ) ) ; SDNode * UpperLowerMask = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDNode * UpperLowerSelect = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperHalfSignMask , <NUM_LIT> ) , SDValue ( VecOp0 , <NUM_LIT> ) , SDValue ( UpperLowerMask , <NUM_LIT> ) ) ; SDNode * Shift = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( ShiftAmt ) ) { unsigned bytes = unsigned ( CN -> getZExtValue ( ) ) >> <NUM_LIT> ; unsigned bits = unsigned ( CN -> getZExtValue ( ) ) & <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { bytes = <NUM_LIT> - bytes ;

Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperLowerSelect , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ;


<s> MVT T = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; unsigned Reg = <NUM_LIT> ; unsigned size = <NUM_LIT> ; switch ( T . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ;


<s> const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ;

} else if ( Op . isImm ( ) || Op . isFPImm ( ) ) {


<s> else if ( First <= <NUM_LIT> ) emit<ISA_LIT>WinUnwindCode ( Win64EH :: UOP_SaveFRegD0D15 , First , Last ) ;

else emit<ISA_LIT>WinUnwindCode ( Win64EH :: UOP_SaveFRegD16D31 , First , Last ) ;


<s> if ( ! s390_can_eliminate ( from , to ) ) return <NUM_LIT> ; switch ( from ) { case FRAME_POINTER_REGNUM : offset = ( get_frame_size ( ) + STACK_POINTER_OFFSET + crtl -> outgoing_args_size ) ; break ; case ARG_POINTER_REGNUM : s390_init_frame_layout ( ) ; offset = cfun_frame_layout . frame_size + STACK_POINTER_OFFSET ; break ; case RETURN_ADDRESS_POINTER_REGNUM : s390_init_frame_layout ( ) ; if ( cfun_frame_layout . first_save_gpr_slot == - <NUM_LIT> ) { if ( cfun -> stdarg && ! cfun_save_arg_fprs_p ) return <NUM_LIT> ; gcc_unreachable ( ) ; } offset = ( cfun_frame_layout . frame_size + cfun_frame_layout . gprs_offset + ( RETURN_REGNUM - cfun_frame_layout . first_save_gpr_slot ) * UNITS_PER_LONG ) ; break ; case BASE_REGNUM : offset = <NUM_LIT> ; break ;


<s> MVT ExtVT ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; case <STR_LIT> : ExtVT = <STR_LIT> ; break ; } if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getZeroVector ( ExtVT , Subtarget , DAG , DL ) ; else if ( <STR_LIT> ( V1 . getNode ( ) ) ) V1 = getOnesVector ( ExtVT , Subtarget , DAG , DL ) ; else V1 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V1 ) ;

if ( V2 . isUndef ( ) ) V2 = DAG . getUNDEF ( ExtVT ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; return hasGOTReference ( BE -> getLHS ( ) ) || hasGOTReference ( BE -> getRHS ( ) ) ; } case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; return ( SymRef . getSymbol ( ) . getName ( ) == <STR_LIT> ) ; } case MCExpr :: Unary :

return hasGOTReference ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) ) ;


<s> switch ( Orig . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; Val = <NUM_LIT> ; break ; } BuildMI ( MBB , I , Orig . getDebugLoc ( ) , get ( Opc ) ) . addReg ( DstReg , RegState :: Define , SubIdx ) . addImm ( Val ) ;


<s> default : return true ; case <STR_LIT> : if ( HaveCond ) return true ; Cond . push_back ( MachineOperand :: CreateImm ( true ) ) ; Cond . push_back ( MI . getOperand ( <NUM_LIT> ) ) ; TBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; HaveCond = true ; break ; case <STR_LIT> : if ( HaveCond ) return true ; Cond . push_back ( MachineOperand :: CreateImm ( false ) ) ; Cond . push_back ( MI . getOperand ( <NUM_LIT> ) ) ; TBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; HaveCond = true ; break ; case <STR_LIT> : if ( ! HaveCond ) TBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; else FBB = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> Register OneVec = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned Opcode = <STR_LIT> ; auto MIB = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Opcode ) ) . addDef ( OneVec ) . addUse ( GR . get<ISA_LIT>TypeID ( ResType ) ) ; for ( unsigned i = <NUM_LIT> ; i < NumEles ; ++ i ) MIB . addUse ( OneReg ) ; constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; return OneVec ;


<s> int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset > <NUM_LIT> || Offset < - <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset & <NUM_LIT> ) return <STR_LIT> ; else if ( Offset > <NUM_LIT> || Offset < <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : { int64_t Offset = ( Value & ~ <NUM_LIT> ) ; if ( Offset == <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : return checkPCRelOffset ( Value , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , + <NUM_LIT> ) ;


<s> if ( size == UNITS_PER_WORD && aligned_p && ( ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( x ) ) || GET_CODE ( x ) == LABEL_REF ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputs ( <STR_LIT> , asm_out_file ) ; return true ; } return default_assemble_integer ( x , size , aligned_p ) ;


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( MachineFunction & mf , DenseMap < const Value * , unsigned > & vm , DenseMap < const BasicBlock * , MachineBasicBlock * > & bm , DenseMap < const AllocaInst * , int > & am , SmallSet < const Instruction * , <NUM_LIT> > & cil ) { return <STR_LIT> ( mf , vm , bm , am , cil ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , GenExecuteOnly ( EnableExecuteOnly ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) , GISel ( ) {


<s> } if ( ! ConstantsMatch ) continue ; SDValue Inp = ( i == <NUM_LIT> ) ? Node -> getOperand ( <NUM_LIT> ) : Node -> getOperand ( <NUM_LIT> ) ; SDValue SizeC = DAG . getConstant ( VT . getSizeInBits ( ) , dl , <STR_LIT> ) ; SDValue Index = getIndexFromUnindexedLoad ( Ld ) ; if ( ! Index ) return SDValue ( ) ; Index = DAG . getZExtOrTrunc ( Index , dl , <STR_LIT> ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SizeC , Index ) ; Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub ) ; SDValue AllOnes = DAG . getAllOnesConstant ( dl , VT ) ; SDValue LShr = DAG . getNode ( <STR_LIT> , dl , VT , AllOnes , Sub ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Inp , LShr ) ; } } } }


<s> if ( Subtarget . hasP9Altivec ( ) ) { Reduced = combineBVOfVecSExt ( N , DAG ) ; if ( Reduced ) return Reduced ; } if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( FirstInput . getOpcode ( ) != <STR_LIT> && FirstInput . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( FirstInput . getOpcode ( ) != N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ) return SDValue ( ) ; SDValue Ext1 = FirstInput . getOperand ( <NUM_LIT> ) ; SDValue Ext2 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Ext1 . getOpcode ( ) != <STR_LIT> || Ext2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * Ext1Op = dyn_cast < ConstantSDNode > ( Ext1 . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * Ext2Op = dyn_cast < ConstantSDNode > ( Ext2 . getOperand ( <NUM_LIT> ) ) ; if ( ! Ext1Op || ! Ext2Op ) return SDValue ( ) ; if ( Ext1 . getValueType ( ) != <STR_LIT> || Ext2 . getValueType ( ) != <STR_LIT> ) if ( Ext1 . getOperand ( <NUM_LIT> ) != Ext2 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; int FirstElem = Ext1Op -> getZExtValue ( ) ; int SecondElem = Ext2Op -> getZExtValue ( ) ; int SubvecIdx ; if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else return SDValue ( ) ; SDValue SrcVec = Ext1 . getOperand ( <NUM_LIT> ) ;

auto NodeType = ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> DefStack & DS = F -> second ; if ( Kind == NodeAttrs :: Use ) linkRefUp < UseNode * > ( SA , RA , DS ) ; else if ( Kind == NodeAttrs :: Def ) linkRefUp < DefNode * > ( SA , RA , DS ) ; else llvm_unreachable ( <STR_LIT> ) ;


<s> return mode == DImode || mode == SImode ? <NUM_LIT> : <NUM_LIT> ;


<s> return ( EncVal << <NUM_LIT> ) | ( EncVal << <NUM_LIT> ) | <NUM_LIT> ;


<s> aarch64_print_hint_for_core_or_arch ( str , false ) ;


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> SDValue L = DAG . getLoad ( NewVT , DL , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getPointerInfo ( ) , Load -> getOriginalAlign ( ) , Load -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getMergeValues ( { DAG . getBitcast ( VT , L ) , L . getValue ( <NUM_LIT> ) } , DL ) ;


<s> else if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ;

if ( imm != INT32_MIN ) imm *= ( <NUM_LIT> << shift ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) ) ;

Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> + getReg ( ) - <STR_LIT> ) ) ;