<s> LLVM_DUMP_METHOD void llvm :: printLivesAt ( SlotIndex <ISA_LIT> , const LiveIntervals & LIS , const MachineRegisterInfo & MRI ) { dbgs ( ) << <STR_LIT> << <ISA_LIT> << <STR_LIT> << * LIS . getInstructionFromIndex ( <ISA_LIT> ) ; unsigned Num = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , E = MRI . getNumVirtRegs ( ) ; I != E ; ++ I ) { const unsigned Reg = TargetRegisterInfo :: index2VirtReg ( I ) ; if ( ! LIS . hasInterval ( Reg ) ) continue ; const auto & LI = LIS . getInterval ( Reg ) ; if ( LI . hasSubRanges ( ) ) { bool firstTime = true ; for ( const auto & S : LI . subranges ( ) ) { if ( ! S . liveAt ( <ISA_LIT> ) ) continue ; if ( firstTime ) { dbgs ( ) << <STR_LIT> << PrintReg ( Reg , MRI . getTargetRegisterInfo ( ) ) << '\n' ; firstTime = false ;


<s> if ( MII . get ( MI -> getOpcode ( ) ) . TSFlags & <STR_LIT> ) O << <STR_LIT> ; else O << <STR_LIT> ; printOperand ( MI , OpNo , O ) ;


<s> static bool riscv_interrupt_type_p ( tree type ) {

return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) != NULL ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {

return new <ISA_LIT>PassConfig ( this , PM ) ;


<s> if ( InstTy == InstType :: Ambiguous && OpSize == <NUM_LIT> ) return true ;


<s> unsigned SubReg = TRI -> getSubReg ( VecReg , <STR_LIT> ) ; if ( ! SubReg ) SubReg = VecReg ; const TargetRegisterClass * RC = TRI -> getPhysRegClass ( SubReg ) ;

int RegIdx = TRI -> getHWRegIndex ( SubReg ) + Offset ;


<s> } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const TargetInstrInfo & TII = * TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; } }


<s> static inline bool reg_ok_for_index_p ( const_rtx x , bool strict ) { return reg_ok_for_base_p ( x , strict ) ;


<s> return ( MemVT . getSizeInBits ( ) <= MaxPrivateBits ) ; } else if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) { return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> * <NUM_LIT> ) ; }


<s> if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { if ( ( Op0 . getValueType ( ) == <STR_LIT> && ( isa < ConstantSDNode > ( Op0 ) || isa < ConstantSDNode > ( Op1 ) ) ) && ! DAG . getMachineFunction ( ) . getFunction ( ) -> optForMinSize ( ) && ! Subtarget . isAtom ( ) ) {


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( SRegsTable [ RegNo ] ) ) ;


<s> Known . One &= KnownRHS . One ; return ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Known , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override {


<s> RegisterMCAsmInfoFn Y ( getThe<ISA_LIT>V9Target ( ) , create<ISA_LIT>V9MCAsmInfo ) ; RegisterMCAsmInfoFn Z ( getThe<ISA_LIT>elTarget ( ) , create<ISA_LIT>MCAsmInfo ) ; for ( Target * T : { & getThe<ISA_LIT>Target ( ) , & getThe<ISA_LIT>V9Target ( ) , & getThe<ISA_LIT>elTarget ( ) } ) { TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createTargetAsmStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;

BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) ;


<s> fprintf ( stderr , <STR_LIT> ) ; if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( x , <NUM_LIT> ) ) == FB_REGNO && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) < - <NUM_LIT> || INTVAL ( XEXP ( x , <NUM_LIT> ) ) > ( <NUM_LIT> - GET_MODE_SIZE ( mode ) ) ) ) { rtx temp = gen_reg_rtx ( Pmode ) ; x = copy_rtx ( x ) ; emit_insn ( gen_rtx_SET ( temp , XEXP ( x , <NUM_LIT> ) ) ) ; XEXP ( x , <NUM_LIT> ) = temp ; } return x ;


<s> void <ISA_LIT>AsmPrinter :: emitEndOfAsmFile ( Module & M ) { for ( std :: map < const char * , const <STR_LIT> * > :: const_iterator it = StubsNeeded . begin ( ) ;


<s> static inline int vec_any_ne ( vec_float4 a , vec_float4 b ) { return ( ( int ) ( spu_extract ( spu_gather ( spu_cmpeq ( a , b ) ) , <NUM_LIT> ) != <NUM_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combine<ISA_LIT>INT_TO_FP ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineCVTP2I_CVTTP2I ( N , DAG , DCI ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineExtInVec ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftVar ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShuffle ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , TII -> get ( EndbrOpcode ) ) ; ++ NumEndBranchAdded ; return true ; } return false ;


<s> setHasFloatingPointExceptions ( false ) ;

setSchedulingPreference ( Sched :: RegPressure ) ;


<s> bool <ISA_LIT>TargetLowering :: isHvxOperation ( SDValue Op ) const { return Subtarget . isHVXVectorType ( ty ( Op ) , true ) || llvm :: any_of ( Op . getNode ( ) -> ops ( ) , [ this ] ( SDValue V ) { return Subtarget . isHVXVectorType ( ty ( V ) , true ) ; } ) ;


<s> bool isUpperSaturate ( const SDValue LHS , const SDValue RHS , const SDValue TrueVal , const SDValue FalseVal , const <STR_LIT> CC , const SDValue K ) {

return ( isGTorGE ( CC ) && ( ( K == RHS && K == TrueVal ) || ( K == LHS && K == FalseVal ) ) ) || ( isLTorLE ( CC ) && ( ( K == LHS && K == TrueVal ) || ( K == RHS && K == FalseVal ) ) ) ;


<s> else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; Base . ChangeToRegister ( BasePtr , false ) ; int64_t FIOffset ; Register IgnoredFrameReg ; if ( AfterFPPop ) { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; FIOffset = MFI . getObjectOffset ( FIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else { FIOffset = TFI -> getFrameIndexReference ( MF , FIndex , IgnoredFrameReg ) . getFixed ( ) ; } if ( BasePtr == StackPtr ) FIOffset += SPAdj ;

Disp . ChangeToImmediate ( FIOffset + Imm ) ;


<s> Sizes [ I ] = getSizeInBits ( Reg , MRI , * TRI ) ; } for ( unsigned I = <NUM_LIT> , E = MI . getNumExplicitDefs ( ) ; I != E ; ++ I ) { unsigned SizeI = getSizeInBits ( MI . getOperand ( I ) . getReg ( ) , MRI , * TRI ) ; Operands [ I ] = <STR_LIT> ( <STR_LIT> , SizeI ) ; } unsigned MappingID = <NUM_LIT> ; for ( const auto & Entry : Table ) { for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { int OpIdx = RegSrcOpIdx [ I ] ; Operands [ OpIdx ] = <STR_LIT> ( Entry . RegBanks [ I ] , Sizes [ I ] ) ;


<s> uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; Inst . addOperand ( MCOperand :: createImm ( Hint ) ) ;


<s> <ISA_LIT>MCLowerPrePass ( ) : MachineFunctionPass ( ID ) {


__o = __builtin_aarch64_set_qregciv4sf ( __o , ( float32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> const ChangesVec & getChanges ( ) const { return Changes ;


<s> DAG -> addMutation ( create<ISA_LIT>MacroFusionDAGMutation ( ) ) ;


<s> printU32ImmOperand ( MI , OpNo , O ) ;


<s> uint32_t Kind ; auto * Call = dyn_cast < CallInst > ( & I ) ;

if ( ! IsPreserveDIAccessIndexCall ( Call , Kind ) || AIChain . find ( Call ) != AIChain . end ( ) ) continue ;


<s>
void
<ISA_LIT>AsmPrinter
::
printVFPf64ImmOperand
(
const
MachineInstr
*
MI
,
int
OpNum
,
raw_ostream
&
O
)
{
const
ConstantFP
*
FP
=
MI
->
getOperand
(
OpNum
)
.
getFPImm
(
)
;
O
<<
'#'
<<
FP
->
getValueAPF
(
)
.
convertToDouble
(
)
;
if
(
isVerbose
(
)
)
{
O
<<
<STR_LIT>
<<
MAI
->
getCommentString
(
)
<<
' '
;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( <ISA_LIT>AsmPrinter & asmprinter ) : Printer ( asmprinter ) {


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSABI , CPU ) ;


<s> default_elf_asm_output_external ( file , decl , name ) ; if ( TREE_SYMBOL_REFERENCED ( DECL_ASSEMBLER_NAME ( decl ) ) ) { if ( ! TARGET_EXPLICIT_RELOCS && mips_in_small_data_p ( decl ) ) { fputs ( <STR_LIT> , file ) ; assemble_name ( file , name ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , int_size_in_bytes ( TREE_TYPE ( decl ) ) ) ; } }


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineBasicBlock :: iterator InsertPt , MachineInstr * LoadMI ) const { return nullptr ;


<s> Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < Register , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , false ) ) return false ; Register CalleeReg ; if ( Subtarget -> genLongCalls ( ) ) { CalleeReg = getLibcallReg ( TLI . getLibcallName ( Call ) ) ; if ( CalleeReg == <NUM_LIT> ) return false ; } unsigned CallOpc = <ISA_LIT>SelectCallOp ( Subtarget -> genLongCalls ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CallOpc ) ) ; if ( isThumb2 ) MIB . add ( predOps ( <STR_LIT> ) ) ; if ( Subtarget -> genLongCalls ( ) ) MIB . addReg ( CalleeReg ) ; else MIB . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; for ( Register R : RegArgs ) MIB . addReg ( R , RegState :: Implicit ) ;

MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ;


<s> if ( isTargetCOFF ( ) ) return <STR_LIT> ; if ( is64Bit ( ) ) return <STR_LIT> ; if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return <STR_LIT> ; return <STR_LIT> ; }


<s> <ISA_LIT>Type * SpirvType = getOrCreate<ISA_LIT>VectorType ( BaseType , NumElements , I , TII ) ; assign<ISA_LIT>TypeToVReg ( SpirvType , VReg , * CurMF ) ; return SpirvType ;


<s> auto Val = Map . find ( Name ) ; assert ( Val != Map . end ( ) && <STR_LIT> ) ; return getLibcallSignature ( Subtarget , Val -> second , Rets , Params ) ;


<s> <ISA_LIT>GenRegisterInfo ( STI . isABI_CheriPureCap ( ) ? <STR_LIT> : <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , STI . getHwMode ( ) ) {


<s> const BasicBlockInfo & BBI = BBInfo [ Block ] ;

dbgs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << format ( <STR_LIT> , UserOffset ) << <STR_LIT> << Block << <STR_LIT> << format ( <STR_LIT> , BBI . Offset , BBI . postOffset ( ) ) << * MI << format ( <STR_LIT> , CPEOffset , int ( CPEOffset - UserOffset ) ) ;


<s> Address Addr ; if ( ! ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; if ( ! EmitStore ( VT , SrcReg , Addr ) ) return false ;


<s> const char * output_add_immediate ( rtx * operands ) { HOST_WIDE_INT n = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( n != <NUM_LIT> || REGNO ( operands [ <NUM_LIT> ] ) != REGNO ( operands [ <NUM_LIT> ] ) ) {

if ( n < <NUM_LIT> ) output_multi_immediate ( operands , <STR_LIT> , <STR_LIT> , <NUM_LIT> , - n ) ;


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , false , true , true ) ;


<s> { machine_mode target_mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; REAL_VALUE_TYPE inf ; rtx tmp ; real_inf ( & inf ) ; tmp = const_double_from_real_value ( inf , target_mode ) ; tmp = validize_mem ( force_const_mem ( target_mode , tmp ) ) ; if ( target == <NUM_LIT> ) target = gen_reg_rtx ( target_mode ) ; emit_move_insn ( target , tmp ) ; return target ; } case IA64_BUILTIN_FABSQ :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI -> getOperand ( <NUM_LIT> ) . getImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) {

FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: Select ( SDNode * Node ) { return SelectCode ( Node ) ;


<s> const MCSchedClassDesc * SC = DAG -> getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return true ; if ( SC -> BeginGroup ) return ( CurrGroupSize == <NUM_LIT> ) ; assert ( ( getNumDecoderSlots ( SU ) <= <NUM_LIT> ) && ( CurrGroupSize < <NUM_LIT> ) && <STR_LIT> ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitFPU ( unsigned FPU ) { OS << <STR_LIT> << GetFPUName ( FPU ) << <STR_LIT> ;


<s> if ( getFMAPatterns ( Root , Patterns ) ) return true ;

return TargetInstrInfo :: getMachineCombinerPatterns ( Root , Patterns ) ;


<s> Result += ! isDuplexAGroup ( subInst1Opcode ) ; } else Result += Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && Type != <STR_LIT> && ( Type != <STR_LIT> || <ISA_LIT>MCInstrInfo :: isFloat ( MCII , ID ) ) ; return Result != <NUM_LIT> ;


<s> add_reg_br_prob_note ( jump , profile_probability :: very_unlikely ( ) ) ;


<s> for ( auto & D : PSU -> Preds ) { if ( D . getKind ( ) == SDep :: Data && ! hasDataDep ( D . getSUnit ( ) , SU ) ) { SDep newDep ( D . getSUnit ( ) , SDep :: Barrier ) ; NewDeps -> push_back ( newDep ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dumpSU ( DAG , D . getSUnit ( ) ) ) ;


<s> SDValue Index = N -> getIndex ( ) ; SDValue Mask = N -> getMask ( ) ; SDValue PassThru = N -> getPassThru ( ) ; MVT IndexVT = Index . getSimpleValueType ( ) ; assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; if ( IndexVT == <STR_LIT> ) return SDValue ( ) ; MVT OrigVT = VT ; if ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && ! IndexVT . is512BitVector ( ) ) { unsigned Factor = std :: min ( <NUM_LIT> / VT . getSizeInBits ( ) , <NUM_LIT> / IndexVT . getSizeInBits ( ) ) ; unsigned NumElts = VT . getVectorNumElements ( ) * Factor ; VT = <STR_LIT> ( VT . getVectorElementType ( ) , NumElts ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , NumElts ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; PassThru = ExtendToType ( PassThru , VT , DAG ) ; Index = ExtendToType ( Index , IndexVT , DAG ) ; Mask = ExtendToType ( Mask , MaskVT , DAG , true ) ; } SDValue Ops [ ] = { N -> getChain ( ) , PassThru , Mask , N -> getBasePtr ( ) , Index , N -> getScale ( ) } ; SDValue NewGather = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , Ops , N -> getMemoryVT ( ) , N -> getMemOperand ( ) ) ;

SDValue Extract = DAG . getNode ( <STR_LIT> , dl , OrigVT , NewGather , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> if ( Opcode == <STR_LIT> ) Opcode = <STR_LIT> ; int MCOpcode = ST . getInstrInfo ( ) -> pseudoToMCOpcode ( Opcode ) ; if ( MCOpcode == - <NUM_LIT> ) { LLVMContext & C = MI -> getParent ( ) -> getParent ( ) -> getFunction ( ) -> getContext ( ) ; C . emitError ( <STR_LIT> <STR_LIT> + Twine ( MI -> getOpcode ( ) ) ) ; } OutMI . setOpcode ( MCOpcode ) ; for ( const MachineOperand & MO : MI -> explicit_operands ( ) ) { MCOperand MCOp ; lowerOperand ( MO , MCOp ) ;


<s> void scalar_chain :: convert_reg ( rtx_insn * insn , rtx dst , rtx src ) { start_sequence ( ) ; if ( ! TARGET_INTER_UNIT_MOVES_FROM_VEC ) { rtx tmp = assign_386_stack_local ( smode , SLOT_STV_TEMP ) ; emit_move_insn ( tmp , src ) ; if ( ! TARGET_64BIT && smode == DImode ) { emit_move_insn ( gen_rtx_SUBREG ( SImode , dst , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , dst , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; } else emit_move_insn ( dst , copy_rtx ( tmp ) ) ; } else if ( ! TARGET_64BIT && smode == DImode ) { if ( TARGET_SSE4_1 ) {

rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) ) ;


<s> if ( getRelaxedOpcode ( Inst . getOpcode ( ) ) == Inst . getOpcode ( ) ) return false ; bool hasExprOrImm = false ; for ( unsigned i = <NUM_LIT> ; i < Inst . getNumOperands ( ) ; ++ i ) hasExprOrImm |= Inst . getOperand ( i ) . isExpr ( ) ; return hasExprOrImm ;


<s> AU . addRequired < <ISA_LIT>ArgumentUsageInfo > ( ) ;

AU . addRequired < DivergenceAnalysis > ( ) ;


<s> MachineInstr * ScalarDef = MRI . getVRegDef ( MaskDef -> getOperand ( i ) . getReg ( ) ) ; assert ( ScalarDef && <STR_LIT> ) ; while ( ScalarDef -> getOpcode ( ) == TargetOpcode :: COPY ) { ScalarDef = MRI . getVRegDef ( ScalarDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; assert ( ScalarDef && <STR_LIT> ) ;


return __builtin_ia32_vcvtw2ph128_mask ( ( __v8hi ) __B , _mm_setzero_ph ( ) , __A ) ;


<s> InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ; VarArgsSaveSize += XLenInBytes ; } for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) { const unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( ArgRegs [ I ] , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ;


<s> unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( ! Imm ) return ; O << <STR_LIT> << Imm ;


<s> UnsignedMap RegMap ; for ( IFMapType :: iterator I = IFMap . begin ( ) , E = IFMap . end ( ) ; I != E ; ++ I ) { unsigned VR = I -> first ; const TargetRegisterClass * RC = MRI -> getRegClass ( VR ) ; unsigned NewVR = MRI -> createVirtualRegister ( RC ) ; RegMap [ VR ] = NewVR ; } for ( IFMapType :: iterator I = IFMap . begin ( ) , E = IFMap . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = MRI -> getVRegDef ( I -> first ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewR = RegMap [ I -> first ] ; bool R32 = MRI -> getRegClass ( NewR ) == & <STR_LIT> ; const MCInstrDesc & D = R32 ? HII -> get ( <STR_LIT> ) : HII -> get ( <STR_LIT> ) ; IFRecord IF = I -> second [ <NUM_LIT> ] . first ; unsigned Wdh = IF . Wdh , Off = IF . Off ; unsigned InsS = <NUM_LIT> ; if ( R32 && MRI -> getRegClass ( IF . InsR ) == & <STR_LIT> ) { InsS = <STR_LIT> ; if ( Off >= <NUM_LIT> ) { InsS = <STR_LIT> ; Off -= <NUM_LIT> ; } } MachineBasicBlock :: iterator At = MI ; if ( MI -> isPHI ( ) ) At = B . getFirstNonPHI ( ) ; BuildMI ( B , At , DL , D , NewR ) . addReg ( IF . SrcR ) . addReg ( IF . InsR , <NUM_LIT> , InsS ) . addImm ( Wdh ) . addImm ( Off ) ; MRI -> clearKillFlags ( IF . SrcR ) ; MRI -> clearKillFlags ( IF . InsR ) ; }


<s> if ( ! skipToken ( AsmToken :: Identifier , <STR_LIT> ) || ! skipToken ( AsmToken :: LParen , <STR_LIT> ) ) return false ; int64_t ExprVal ; if ( ! parseExpr ( ExprVal ) ) return false ; unsigned PrevOprMask = UsedOprMask ; int CntVal = encodeDepCtr ( DepCtrName , ExprVal , UsedOprMask , getSTI ( ) ) ;


<s> static BasicBlock :: iterator first_use_of_in_block ( T & Values , BasicBlock * B ) { BasicBlock :: iterator FirstUse = B -> end ( ) , BEnd = B -> end ( ) ; using iterator = typename T :: iterator ;

for ( iterator I = Values . begin ( ) , E = Values . end ( ) ; I != E ; ++ I ) {


<s> return DecodeCPURegsRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Data [ Fixup . getOffset ( ) + i ] = uint8_t ( Value >> ( i * <NUM_LIT> ) ) ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : FPStackOffset ( <NUM_LIT> ) , RAStackOffset ( <NUM_LIT> ) , CPUTopSavedRegOff ( <NUM_LIT> ) , FPUTopSavedRegOff ( <NUM_LIT> ) , GPHolder ( - <NUM_LIT> , - <NUM_LIT> ) , HasLoadArgs ( false ) , HasStoreVarArgs ( false ) , SRetReturnReg ( <NUM_LIT> ) {


<s> int64_t IntVal ; if ( ! MatchRegisterName ( Parser . getTok ( ) , RegNo , IntVal ) ) { Parser . Lex ( ) ; Op = <ISA_LIT>Operand :: CreateImm ( IntVal , S , E , is<ISA_LIT>64 ( ) ) ; Operands . push_back ( Op ) ; return false ; } return Error ( S , <STR_LIT> ) ; case AsmToken :: LParen : case AsmToken :: Plus : case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Identifier : case AsmToken :: Dot : case AsmToken :: Dollar : if ( ! getParser ( ) . parseExpression ( EVal ) ) break ; default : return Error ( S , <STR_LIT> ) ; } if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( EVal ) ) Op = <ISA_LIT>Operand :: CreateImm ( CE -> getValue ( ) , S , E , is<ISA_LIT>64 ( ) ) ; else Op = <ISA_LIT>Operand :: CreateExpr ( EVal , S , E , is<ISA_LIT>64 ( ) ) ; Operands . push_back ( Op ) ; if ( getLexer ( ) . is ( AsmToken :: LParen ) ) { Parser . Lex ( ) ; S = Parser . getTok ( ) . getLoc ( ) ; int64_t IntVal ; switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Percent : Parser . Lex ( ) ; unsigned RegNo ; if ( MatchRegisterName ( Parser . getTok ( ) , RegNo , IntVal ) ) return Error ( S , <STR_LIT> ) ; Parser . Lex ( ) ; break ; case AsmToken :: Integer :

if ( getParser ( ) . parseAbsoluteExpression ( IntVal ) || IntVal < <NUM_LIT> || IntVal > <NUM_LIT> ) return Error ( S , <STR_LIT> ) ;


<s> if ( T . isArch64Bit ( ) && ( Features & <STR_LIT> ) ) { const MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_OPTIONS , ELF :: SHF_ALLOC | ELF :: SHF_MIPS_NOSTRIP , SectionKind :: getMetadata ( ) ) ; OS . SwitchSection ( Sec ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OS . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> Op -> Mem . ShiftType = ShiftType ; Op -> Mem . ShiftAmount = ShiftAmount ; Op -> Mem . Preindexed = Preindexed ; Op -> Mem . Postindexed = Postindexed ; Op -> Mem . Negative = Negative ; Op -> Mem . Writeback = Writeback ;


<s> Omod = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( In ) , <STR_LIT> ) ; return SelectVOP3Mods ( In , Src , SrcMods ) ;


<s> int getVarArgsStackIndex ( ) const { return VarArgsStackIndex ;


<s> static SDValue performFpToIntCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; if ( ! N -> getValueType ( <NUM_LIT> ) . isSimple ( ) ) return SDValue ( ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( ! Op . getValueType ( ) . isVector ( ) || ! Op . getValueType ( ) . isSimple ( ) || Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ConstVec = Op -> getOperand ( <NUM_LIT> ) ; if ( ! isa < BuildVectorSDNode > ( ConstVec ) ) return SDValue ( ) ; MVT FloatTy = Op . getSimpleValueType ( ) . getVectorElementType ( ) ; uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; if ( FloatBits != <NUM_LIT> && FloatBits != <NUM_LIT> && ( FloatBits != <NUM_LIT> || ! Subtarget -> hasFullFP16 ( ) ) ) return SDValue ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; if ( IntBits != <NUM_LIT> && IntBits != <NUM_LIT> && IntBits != <NUM_LIT> ) return SDValue ( ) ; if ( IntBits > FloatBits ) return SDValue ( ) ; BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t Bits = IntBits == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , Bits + <NUM_LIT> ) ;

if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > Bits ) return SDValue ( ) ;


<s> void printi8mem ( const MCInst * MI , unsigned OpNo ) {


<s> void printf64mem ( const MCInst * MI , unsigned OpNo ) {


<s> int Mask = - cast < ConstantSDNode > ( A . getNode ( ) ) -> getSExtValue ( ) ; assert ( isPowerOf2_32 ( - Mask ) ) ; SDValue M = CurDAG -> getTargetConstant ( Mask , dl , <STR_LIT> ) ; SDNode * AA = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , M ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_XINT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue Zero = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getSetCC ( DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Zero , <STR_LIT> ) ;


<s> } else if ( GlobalAddressSDNode * ga = dyn_cast < GlobalAddressSDNode > ( n ) ) { r = CurDAG -> getTargetGlobalAddress ( ga -> getGlobal ( ) , dl , <STR_LIT> ) ; return true ; } else if ( any_ok ) { r = v ; return true ; } return false ;


<s> for ( <ISA_LIT>MachineFunctionInfo :: reg_iterator i = MFI -> argRegBegin ( ) , e = MFI -> argRegEnd ( ) , b = i ; i != e ; ++ i ) { reg = * i ; assert ( reg != <STR_LIT> && <STR_LIT> ) ; if ( i != b ) decl += <STR_LIT> ; decl += <STR_LIT> ; decl += getRegisterTypeName ( reg ) ; decl += <STR_LIT> ; decl += getRegisterName ( reg ) ; } } decl += <STR_LIT> ; }

OutStreamer . EmitRawText ( Twine ( decl ) ) ;


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register PtrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register CmpVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( <STR_LIT> ( MRI . getType ( PtrReg ) . getAddressSpace ( ) ) && <STR_LIT> ) ; LLT ValTy = MRI . getType ( CmpVal ) ; LLT VecTy = LLT :: fixed_vector ( <NUM_LIT> , ValTy ) ; Register PackedVal = B . buildBuildVector ( VecTy , { NewVal , CmpVal } ) . getReg ( <NUM_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( DstReg ) . addUse ( PtrReg ) . addUse ( PackedVal ) . setMemRefs ( MI . memoperands ( ) ) ;


<s> bool isReg ( ) const { return Kind == Register ;


<s> if ( ! TheReg ) return - <NUM_LIT> ; return TheReg -> Encoding ;


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ;


<s> return & InstrInfo -> getRegisterInfo ( ) ;


<s> MCStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > && AB , std :: unique_ptr < MCObjectWriter > && OW , std :: unique_ptr < MCCodeEmitter > && CE , bool RelaxAll , bool IncrementalLinkerCompatible ) { <ISA_LIT>WinCOFFStreamer * S = new <ISA_LIT>WinCOFFStreamer ( C , std :: move ( AB ) , std :: move ( CE ) , std :: move ( OW ) ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ; S -> getAssembler ( ) . setIncrementalLinkerCompatible ( IncrementalLinkerCompatible ) ;


<s> if ( ! TARGET_SDATA_USE ) return <NUM_LIT> ; if ( GET_CODE ( op ) == SYMBOL_REF ) return SYMBOL_REF_SMALL_P ( op ) ;

if ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT && INT16_P ( INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) return SYMBOL_REF_SMALL_P ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ;


<s> static bool isREX ( struct InternalInstruction * insn , uint8_t prefix ) { return insn -> mode == MODE_64BIT && prefix >= <NUM_LIT> && prefix <= <NUM_LIT> ;


<s> if ( InputModifiers & <STR_LIT> ) O << '|' ; printOperand ( MI , OpNo + <NUM_LIT> , STI , O ) ;


<s> ConstantInt * ValConst = dyn_cast_or_null < ConstantInt > ( NodeVal -> getValue ( ) ) ; if ( ValConst && NodeName -> getString ( ) == LiteralName ) { return ValConst -> getZExtValue ( ) ; } }

report_fatal_error ( <STR_LIT> + LiteralName + <STR_LIT> ) ;


<s> static SDValue getFullRegister ( SDValue Op , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ;


<s> Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( GetPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_PLT ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; Expr = MCBinaryExpr :: CreateSub ( Expr , MCSymbolRefExpr :: Create ( GetPICBaseSymbol ( ) , Ctx ) , Ctx ) ; if ( MO . isJTI ( ) && MAI . hasSetDirective ( ) ) { MCSymbol * Label = Ctx . CreateTempSymbol ( ) ;

AsmPrinter . OutStreamer . EmitAssignment ( Label , Expr ) ;


<ISA_LIT>leTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> const std :: vector < <ISA_LIT>ScheduleBlock * > & getSuccs ( ) const { return Succs ;


<s> const char * name ; name = fcode == RS6000_OVLD_VEC_SPLATS ? <STR_LIT> : <STR_LIT> ; if ( fcode == RS6000_OVLD_VEC_SPLATS && nargs != <NUM_LIT> ) { error ( <STR_LIT> , name ) ; * res = resolved ; return error_mark_node ; } if ( fcode == RS6000_OVLD_VEC_PROMOTE && nargs != <NUM_LIT> ) { error ( <STR_LIT> , name ) ; * res = resolved ; return error_mark_node ; } if ( fcode == RS6000_OVLD_VEC_PROMOTE && ! INTEGRAL_TYPE_P ( TREE_TYPE ( ( * arglist ) [ <NUM_LIT> ] ) ) ) { * res = resolved_bad ; return error_mark_node ; } tree arg = ( * arglist ) [ <NUM_LIT> ] ; tree type = TREE_TYPE ( arg ) ; if ( ! SCALAR_FLOAT_TYPE_P ( type ) && ! INTEGRAL_TYPE_P ( type ) ) { * res = resolved_bad ; return error_mark_node ; } bool unsigned_p = TYPE_UNSIGNED ( type ) ; int size ; switch ( TYPE_MODE ( type ) ) { case E_TImode : type = unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node ;


<s> emit_insn ( gen_ashlsi3 ( tmp_gpr_si , element_si , const2_rtx ) ) ; emit_insn ( VECTOR_ELT_ORDER_BIG ? gen_vextuwlx ( dest_si , tmp_gpr_si , src ) : gen_vextuwrx ( dest_si , tmp_gpr_si , src ) ) ; } return ; } gcc_assert ( REG_P ( tmp_altivec ) ) ; if ( scalar_size == <NUM_LIT> ) { if ( ! VECTOR_ELT_ORDER_BIG ) { emit_insn ( gen_xordi3 ( tmp_gpr , element , const1_rtx ) ) ; element2 = tmp_gpr ; } else element2 = element ; emit_insn ( gen_rtx_SET ( tmp_gpr , gen_rtx_AND ( DImode , gen_rtx_ASHIFT ( DImode , element2 , GEN_INT ( <NUM_LIT> ) ) , GEN_INT ( <NUM_LIT> ) ) ) ) ; } else { if ( ! VECTOR_ELT_ORDER_BIG ) { rtx num_ele_m1 = GEN_INT ( GET_MODE_NUNITS ( mode ) - <NUM_LIT> ) ; emit_insn ( gen_anddi3 ( tmp_gpr , element , num_ele_m1 ) ) ; emit_insn ( gen_subdi3 ( tmp_gpr , num_ele_m1 , tmp_gpr ) ) ; element2 = tmp_gpr ; } else element2 = element ; emit_insn ( gen_ashldi3 ( tmp_gpr , element2 , GEN_INT ( bit_shift ) ) ) ; } if ( TARGET_P9_VECTOR ) emit_insn ( gen_vsx_splat_v2di ( tmp_altivec , tmp_gpr ) ) ; else if ( can_create_pseudo_p ( ) ) emit_insn ( gen_vsx_concat_v2di ( tmp_altivec , tmp_gpr , tmp_gpr ) ) ; else { rtx tmp_di = gen_rtx_REG ( DImode , REGNO ( tmp_altivec ) ) ; emit_move_insn ( tmp_di , tmp_gpr ) ; emit_insn ( gen_vsx_concat_v2di ( tmp_altivec , tmp_di , tmp_di ) ) ; } switch ( mode ) { case E_V2DFmode : emit_insn ( gen_vsx_vslo_v2df ( dest , src , tmp_altivec ) ) ; return ;


<s> MBB . push_back ( Waitcnt ) ; return ; } MachineBasicBlock :: iterator It = MBB . end ( ) ; MachineInstr * MI = & * ( -- It ) ; if ( MI -> isBranch ( ) ) { MBB . insert ( It , Waitcnt ) ; } else { MBB . push_back ( Waitcnt ) ;


<s> fprintf ( file , <STR_LIT> , indent , <STR_LIT> , ptr -> tune , processor_target_table [ ptr -> tune ] . name ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , ptr -> branch_cost ) ; if ( target_string ) { fprintf ( file , <STR_LIT> , indent , <STR_LIT> , target_string ) ; free ( target_string ) ; }


<s> MCELF :: SetBinding ( SD , ELF :: STB_LOCAL ) ; SD . setExternal ( false ) ; Symbol -> setSection ( * getCurrentSection ( ) ) ; const MCExpr * Value = MCSymbolRefExpr :: Create ( Start , getContext ( ) ) ; Symbol -> setVariableValue ( Value ) ;


<s> uint8_t <STR_LIT> ( ) { if ( FpABI == FpABIKind :: XX ) return ( uint8_t ) AFL_REG_32 ; return ( uint8_t ) CPR1Size ;


<s> return decodeBDAddr20Operand ( Inst , Field , <STR_LIT> ) ;


<s> void GCNPassConfig :: addPreEmitPass ( ) { addPass ( & PostRAHazardRecognizerID ) ; addPass ( create<ISA_LIT>InsertWaitsPass ( ) ) ; addPass ( create<ISA_LIT>ShrinkInstructionsPass ( ) ) ; addPass ( & <ISA_LIT>InsertSkipsPassID ) ; addPass ( create<ISA_LIT>DebuggerInsertNopsPass ( ) ) ;


<s> return __builtin_loongson_psubb_u ( s , t ) ;


<s> rtx_insn * insn = emit_insn ( gen_frame_store ( reg , frame_reg , offset ) ) ;


<s> bool hasVectorMemoryOp ( unsigned Opcode , Type * Ty , const MemAccessInfo & Info ) { if ( ST -> hasSVE ( ) ) return true ; return BaseT :: hasVectorMemoryOp ( Opcode , Ty , Info ) ;


<s> <ISA_LIT>ELFDynamic :: ~ <ISA_LIT>ELFDynamic ( ) {


<s> typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ; return ( unsigned long long ) __builtin_sh_media_MCNVS_WUB ( ( v4hi ) mm , ( v4hi ) mn ) ;


<s> if ( ! I -> isBranch ( ) ) break ; if ( ! getBranchInfo ( * I ) . Target -> isMBB ( ) ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; }


<s> else sprintf ( buffer , <STR_LIT> , inverted_p ? inverted_comp : comp , need_z_p ? <STR_LIT> : <STR_LIT> , op1 , op2 ) ; return buffer ; case <NUM_LIT> : case <NUM_LIT> : { const char * target = ( ( iq2000_branch_likely || length == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; char * c ; c = strchr ( buffer , '\0' ) ; if ( float_p ) sprintf ( c , <STR_LIT> , inverted_p ? comp : inverted_comp , target ) ;

else sprintf ( c , <STR_LIT> , inverted_p ? comp : inverted_comp , need_z_p ? <STR_LIT> : <STR_LIT> , op1 , op2 , target ) ;


<s> argmap_entry ( <STR_LIT> _VT , TargetRegisterClass * _RC ) : VT ( _VT ) , RC ( _RC ) , loc ( _RC -> begin ( ) ) {


<s> void GCNPassConfig :: addIRPasses ( ) {

addPass ( create<ISA_LIT>CodeGenPreparePass ( & getGCNTargetMachine ( ) ) ) ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ;


<s> void emitTagType ( const MCSymbolWasm * ) override {


<s> switch ( get_attr_type ( insn ) ) { case TYPE_MAC : if ( REG_P ( XEXP ( exp , <NUM_LIT> ) ) ) return XEXP ( exp , <NUM_LIT> ) ; else return XEXP ( exp , <NUM_LIT> ) ; default :


<s> static struct machine_function * loongarch_init_machine_status ( void ) { return ggc_cleared_alloc < machine_function > ( ) ;


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> if ( ! AlignConstantIslands ) return Align ( <NUM_LIT> ) ; unsigned CPI = CPEMI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; assert ( CPI < MCP -> getConstants ( ) . size ( ) && <STR_LIT> ) ;

return Align ( MCP -> getConstants ( ) [ CPI ] . getAlignment ( ) ) ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override {

return getSubtargetImpl ( ) -> getTargetLowering ( ) ;


<s> for ( unsigned i = <NUM_LIT> ; i <= <NUM_LIT> ; ++ i ) if ( ! MRI . reg_nodbg_empty ( <STR_LIT> + i ) ) { FPIsUsed = true ; break ; } if ( ! FPIsUsed ) return false ; Bundles = & getAnalysis < EdgeBundles > ( ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; bundleCFG ( MF ) ; StackTop = <NUM_LIT> ; df_iterator_default_set < MachineBasicBlock * > Processed ; MachineBasicBlock * Entry = & MF . front ( ) ; LiveBundle & Bundle = LiveBundles [ Bundles -> getBundle ( Entry -> getNumber ( ) , false ) ] ; if ( ( Entry -> getParent ( ) -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_RegCall ) && ( Bundle . Mask && ! Bundle . FixCount ) ) { assert ( ( Bundle . Mask & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Bundle . FixCount = <NUM_LIT> ; Bundle . FixStack [ <NUM_LIT> ] = <NUM_LIT> ; }


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> unsigned <ISA_LIT>TTIImpl :: getPrefetchDistance ( ) const {


<s> <ISA_LIT>Lowering = Subtarget -> getTargetLowering ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ;


<s> log_return ( false , <STR_LIT> ) ; } } if ( modified_in_p ( m_ccreg , e . cstore . insn ) && ! ( reg_dead_after_insn ( m_ccreg , e . cstore . insn ) || reg_unused_after_insn ( m_ccreg , e . cstore . insn ) ) ) { log_msg ( <STR_LIT> ) ; log_insn ( e . cstore . insn ) ; log_return ( false , <STR_LIT> ) ; } rtx_insn * prev_insn = e . cstore . insn ; for ( std :: vector < set_of_reg > :: const_reverse_iterator i = e . cstore_reg_reg_copies . rbegin ( ) ; i != e . cstore_reg_reg_copies . rend ( ) ; ++ i ) { if ( ! reg_dead_after_insn ( i -> set_src ( ) , i -> insn ) ) { log_msg ( <STR_LIT> ) ; log_insn ( i -> insn ) ; log_return ( false , <STR_LIT> ) ; } if ( reg_used_between_p ( i -> set_src ( ) , prev_insn , i -> insn ) ) { log_msg ( <STR_LIT> ) ; log_insn ( i -> insn ) ; log_return ( false , <STR_LIT> , REGNO ( i -> set_src ( ) ) ) ; } prev_insn = i -> insn ; } rtx cstore_dst = e . cstore_reg_reg_copies . empty ( ) ? e . cstore . set_dst ( ) : e . cstore_reg_reg_copies . front ( ) . set_dst ( ) ; if ( ! reg_dead_after_insn ( cstore_dst , trace . setcc . insn ) ) {


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>Subtarget & sti ) : <ISA_LIT>BaseRegisterInfo ( tii , sti ) {


<s> if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } default : break ;


<s> MCAsmParser & Parser = getParser ( ) ; auto Token = Parser . getLexer ( ) . peekTok ( false ) ; if ( Token . is ( AsmToken :: Identifier ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; StringRef Identifier = Token . getIdentifier ( ) ; OperandMatchResultTy ResTy = matchAnyRegisterNameWithoutDollar ( Operands , Identifier , S ) ; return ResTy ; } else if ( Token . is ( AsmToken :: Integer ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; int64_t RegNum = Token . getIntVal ( ) ; if ( RegNum < <NUM_LIT> || RegNum > <NUM_LIT> ) { Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; } Operands . push_back ( <STR_LIT> ( RegNum , Token . getString ( ) , getContext ( ) . getRegisterInfo ( ) , S , Token . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } LLVM_DEBUG ( dbgs ( ) << Parser . getTok ( ) . getKind ( ) << <STR_LIT> ) ; return MatchOperand_NoMatch ;


<s> case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != <STR_LIT> && CS != <STR_LIT> && CS != <STR_LIT> ) return CS ; }


<s> void <ISA_LIT>COFFMachineModuleInfo :: DecorateCygMingName ( MCSymbol * & Name , MCContext & Ctx , const GlobalValue * GV , const TargetData & TD ) { SmallString < <NUM_LIT> > NameStr ( Name -> getName ( ) . begin ( ) , Name -> getName ( ) . end ( ) ) ; DecorateCygMingName ( NameStr , GV , TD ) ; Name = Ctx . GetOrCreateSymbol ( NameStr . str ( ) ) ;


<s> static bool isNodeHidden ( const SCANode * N , const SpillCostAnalysisGraph & G ) { return ! N -> isVisible ( ) ;


<s> unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s3 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( const4 ) ) ; status = DecodeOperandRegister ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; return MCDisassembler :: Success ;


<s> AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) {


<s> case CortexA75 : PrefFunctionAlignment = <NUM_LIT> ; break ; case Cyclone : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM1 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 :


<s> if ( CONST_INT_P ( * cmp1 ) ) switch ( * code ) { case LE : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + <NUM_LIT> , mode ) ; if ( INTVAL ( * cmp1 ) < plus_one ) { * code = LT ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ; } break ; case LEU : plus_one = trunc_int_for_mode ( UINTVAL ( * cmp1 ) + <NUM_LIT> , mode ) ; if ( plus_one != <NUM_LIT> ) { * code = LTU ; * cmp1 = force_reg ( mode , GEN_INT ( plus_one ) ) ; return true ;


<s> temp = <NUM_LIT> ; while ( op ) temp ++ , op &= op - <NUM_LIT> ; return build_int_cst ( alpha_dimode_u , temp ) ;


<s> _mm_setcsr ( ( _mm_getcsr ( ) & ~ _MM_ROUND_MASK ) | __mode ) ;


<s> int Reg = ( int ) fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; int Base = ( int ) fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( CPURegsTable [ Reg ] ) ) ; } Inst . addOperand ( MCOperand :: CreateReg ( CPURegsTable [ Reg ] ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( CPURegsTable [ Base ] ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> void Initialize ( const MachineFunction & MF , bool isPIC ) { IsPIC = isPIC ;


<s> int i ; i = __builtin_spe_mfspefscr ( ) ;


<s> return ( poly16x4x2_t ) { vtrn1_p16 ( a , b ) , vtrn2_p16 ( a , b ) } ;


<s> virtual void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const {


<s> return CustomExpandInstNaCl<ISA_LIT> ( Inst , Out ) ;


<s> if ( ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) && CONSTANT_P ( x ) ) { return arc_legitimate_constant_p ( mode , x ) ; } if ( ( GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == PRE_INC || GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == POST_INC ) && RTX_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; if ( ( GET_CODE ( x ) == PRE_MODIFY || GET_CODE ( x ) == POST_MODIFY ) && GET_CODE ( XEXP ( ( x ) , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( ( x ) , <NUM_LIT> ) , XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) && legitimate_offset_address_p ( QImode , XEXP ( x , <NUM_LIT> ) , TARGET_AUTO_MODIFY_REG , strict ) ) return true ;


<s> APInt <STR_LIT> ( uint64_t LLVMInstr , const std :: map < Fields , Field > & Layout ) { APInt Insn ( InstructionSizeInBits , <NUM_LIT> ) ;


<s> AU . addPreserved < MachineBlockFrequencyInfo > ( ) ; AU . addPreservedID ( MachineDominatorsID ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> bool ReplacingAnyExtend = false ; if ( X . getOpcode ( ) == <STR_LIT> ) { unsigned ExtendBits = X . getSimpleValueType ( ) . getSizeInBits ( ) - X . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getSizeInBits ( ) ; X = X . getOperand ( <NUM_LIT> ) ; MaskLZ = ExtendBits > MaskLZ ? <NUM_LIT> : MaskLZ - ExtendBits ; ReplacingAnyExtend = true ; } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getSimpleValueType ( ) . getSizeInBits ( ) , MaskLZ ) ; APInt KnownZero , KnownOne ; DAG . computeKnownBits ( X , KnownZero , KnownOne ) ; if ( MaskedHighBits != KnownZero ) return true ; MVT VT = N . getSimpleValueType ( ) ; if ( ReplacingAnyExtend ) { assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , SDLoc ( X ) , VT , X ) ; InsertDAGNode ( DAG , N , NewX ) ; X = NewX ; } SDLoc DL ( N ) ;

SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , <STR_LIT> ) ;


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> int insn_code_number = recog_memoized ( insn ) ; location_t location = INSN_LOCATION ( insn ) ; if ( insn_code_number < <NUM_LIT> ) return ; struct recog_data_d recog_data_save = recog_data ; for ( int i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) recog_data . operand [ i ] = copy_rtx ( recog_data . operand [ i ] ) ; temp = get_insn_template ( insn_code_number , insn ) ; recog_data = recog_data_save ; if ( get_attr_cell_micro ( insn ) == CELL_MICRO_ALWAYS ) warning_at ( location , OPT_mwarn_cell_microcode , <STR_LIT> , temp , insn_data [ INSN_CODE ( insn ) ] . name , INSN_UID ( insn ) ) ;

else if ( get_attr_cell_micro ( insn ) == CELL_MICRO_CONDITIONAL ) warning_at ( location , OPT_mwarn_cell_microcode , <STR_LIT> , temp , insn_data [ INSN_CODE ( insn ) ] . name , INSN_UID ( insn ) ) ;


<s> if ( POINTER_TYPE_P ( TREE_TYPE ( arg ) ) ) op [ opc ] = convert_memory_address ( Pmode , op [ opc ] ) ; if ( ! ( * insn_data [ icode ] . operand [ opc ] . predicate ) ( op [ opc ] , mode ) ) op [ opc ] = copy_to_mode_reg ( mode , op [ opc ] ) ; break ; case SIMD_ARG_LANE_INDEX : gcc_assert ( opc > <NUM_LIT> ) ; if ( CONST_INT_P ( op [ opc ] ) ) { machine_mode vmode = insn_data [ icode ] . operand [ opc - <NUM_LIT> ] . mode ; aarch64_simd_lane_bounds ( op [ opc ] , <NUM_LIT> , GET_MODE_NUNITS ( vmode ) , exp ) ; op [ opc ] = GEN_INT ( ENDIAN_LANE_N ( vmode , INTVAL ( op [ opc ] ) ) ) ; } case SIMD_ARG_CONSTANT : if ( ! ( * insn_data [ icode ] . operand [ opc ] . predicate ) ( op [ opc ] , mode ) ) { error ( <STR_LIT> , exp , opc + <NUM_LIT> - have_retval ) ; return const0_rtx ; } break ; case SIMD_ARG_STOP : gcc_unreachable ( ) ; } opc ++ ; } } switch ( opc ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> :

pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ;


<s> } int Val = CE -> getValue ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RCurly ) ) return MatchOperand_ParseFail ; SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocOption ( Val , S , E ) ) ;


<s> static std :: pair < SDValue , SDValue > getDefaultScalableVLOps ( MVT VecVT , SDLoc DL , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( VecVT . isScalableVector ( ) && <STR_LIT> ) ; return getDefaultVLOps ( VecVT , VecVT , DL , DAG , Subtarget ) ;


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; if ( TFI -> hasFP ( MF ) ) return STI . getFramePointerReg ( ) ;


<s> deferred_isa_values &= ~ isa ; deferred_isa_values2 &= ~ isa2 ; if ( TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != <NUM_LIT> ) deferred_isa_values &= ~ OPTION_MASK_ISA_MMX ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = <NUM_LIT> ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != <NUM_LIT> || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != <NUM_LIT> || ( ( ix86_builtins_isa [ i ] . isa & OPTION_MASK_ISA_MMX ) != <NUM_LIT> && TARGET_64BIT && ( isa & OPTION_MASK_ISA_SSE2 ) != <NUM_LIT> ) ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ;

type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ;


<s> Result . push_back ( StringSwitch < StringRef > ( CPU ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) ) ; break ; } case <STR_LIT> :: NoArch : break ; }

return join ( Result . begin ( ) , Result . end ( ) , <STR_LIT> ) ;


<s> SMLoc S = getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto PSB = <STR_LIT> ( Tok . getString ( ) ) ; if ( ! PSB ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ;


<s> void <ISA_LIT>InstructionSelector :: renderVFPF32Imm ( MachineInstrBuilder & NewInstBuilder , const MachineInstr & OldInst , int OpIdx ) const { assert ( OldInst . getOpcode ( ) == TargetOpcode :: G_FCONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; APFloat FPImmValue = OldInst . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) ;

int FPImmEncoding = <STR_LIT> ( FPImmValue ) ;


<s> struct register_pass_info f = { p , <STR_LIT> , <NUM_LIT> , PASS_POS_INSERT_AFTER } ;


<s> void OrderedRegisterList :: insert ( unsigned VR ) { iterator L = llvm :: lower_bound ( Seq , VR , Ord ) ; if ( L == Seq . end ( ) ) Seq . push_back ( VR ) ; else Seq . insert ( L , VR ) ; unsigned S = Seq . size ( ) ; if ( S > MaxSize ) Seq . resize ( MaxSize ) ; assert ( Seq . size ( ) <= MaxSize ) ;


<s> return ( int32x4_t ) __builtin_neon_vqshl_s_nv4si ( __a , __b ) ;


<s> MachineBasicBlock :: const_reverse_iterator E = MI . getParent ( ) -> rend ( ) ; It ++ ; for ( ; It != E ; ++ It ) { if ( It -> modifiesRegister ( Reg , & getRegisterInfo ( ) ) && ( & * It ) != & DefMI ) return false ; if ( ( & * It ) == & DefMI ) break ;


<s> BlockFrequencies . insert ( std :: make_pair ( MBB , Freq ) ) ;


<s> if ( ( * cum + ( byte_size + <NUM_LIT> ) / <NUM_LIT> ) > MAX_REGISTER_ARGS ) return <NUM_LIT> ; if ( ( mode == BLKmode || ( type && AGGREGATE_TYPE_P ( type ) ) ) && byte_size < UNITS_PER_WORD && byte_size > <NUM_LIT> ) { machine_mode smode ; rtx gr_reg ; if ( byte_size < <NUM_LIT> ) byte_size = <NUM_LIT> ;

smode = smallest_int_mode_for_size ( byte_size * BITS_PER_UNIT ) ;


<s> AscizDirective = <STR_LIT> ; HiddenVisibilityAttr = MCSA_Invalid ; HiddenDeclarationVisibilityAttr = MCSA_Invalid ;

ProtectedVisibilityAttr = MCSA_Invalid ;


<s> const ThumbRegisterInfo * RegInfo = static_cast < const ThumbRegisterInfo * > ( STI . getRegisterInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = TII . getFrameSize ( Old ) ; if ( Amount != <NUM_LIT> ) { Amount = alignTo ( Amount , getStackAlign ( ) ) ; unsigned Opc = Old . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { emitCallSPUpdate ( MBB , I , TII , dl , * RegInfo , - Amount ) ;


<s> if ( ! DestIsHigh && ! SrcIsHigh ) MI . setDesc ( get ( LowOpcodeK ) ) ; else { if ( DestReg != SrcReg ) { emitGRX32Move ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , DestReg , SrcReg , <STR_LIT> , <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . isKill ( ) , MI . getOperand ( <NUM_LIT> ) . isUndef ( ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ; } MI . setDesc ( get ( DestIsHigh ? HighOpcode : LowOpcode ) ) ; MI . tieOperands ( <NUM_LIT> , <NUM_LIT> ) ; }


<s> dbgs ( ) << <STR_LIT> << SU -> NodeNum << <STR_LIT> << SU -> getHeight ( ) << <STR_LIT> << SU -> getDepth ( ) << <STR_LIT> << Cmp . DFSResult -> getSubtreeID ( SU ) << <STR_LIT> << Cmp . DFSResult -> getSubtreeLevel ( Cmp . DFSResult -> getSubtreeID ( SU ) ) ; if ( SU -> isScheduleLow ) dbgs ( ) << <STR_LIT> ;


<s> SDLoc dl ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) {


<s> if ( Kind == k_RegisterIndex && RegIdx . Index == <NUM_LIT> && RegIdx . Kind & RegKind_GPR ) return getGPR32Reg ( ) ; assert ( Kind == k_PhysRegister && <STR_LIT> ) ;


<s> bool HasStackObjects = MFI . hasStackObjects ( ) ; if ( HasStackObjects ) Info . setHasNonSpillStackObjects ( true ) ; if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) HasStackObjects = true ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . isAmdCodeObjectV2 ( MF ) ) { if ( HasStackObjects ) { unsigned PrivateSegmentBufferReg = TRI . getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: PRIVATE_SEGMENT_BUFFER ) ; Info . setScratchRSrcReg ( PrivateSegmentBufferReg ) ; unsigned PrivateSegmentWaveByteOffsetReg = TRI . getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: PRIVATE_SEGMENT_WAVE_BYTE_OFFSET ) ; Info . setScratchWaveOffsetReg ( PrivateSegmentWaveByteOffsetReg ) ; } else { unsigned ReservedBufferReg = TRI . reservedPrivateSegmentBufferReg ( MF ) ; unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ;

Info . setScratchRSrcReg ( ReservedBufferReg ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const {

const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


<s> void <ISA_LIT>InstPrinter :: printAddrModePCOperand ( const MCInst * MI , unsigned OpNum , const char * Modifier ) {


<s> int div_factor = <NUM_LIT> ; emit_move_insn ( tmp , gen_int_mode ( BYTES_PER_RISCV_VECTOR , mode ) ) ; if ( BYTES_PER_RISCV_VECTOR . is_constant ( ) ) { gcc_assert ( value . is_constant ( ) ) ; riscv_emit_move ( dest , GEN_INT ( value . to_constant ( ) ) ) ; return ; } else if ( ( factor % vlenb ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else if ( ( factor % ( vlenb / <NUM_LIT> ) ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else if ( ( factor % ( vlenb / <NUM_LIT> ) ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else if ( ( factor % ( vlenb / <NUM_LIT> ) ) == <NUM_LIT> ) div_factor = <NUM_LIT> ; else gcc_unreachable ( ) ; if ( div_factor != <NUM_LIT> ) riscv_expand_op ( LSHIFTRT , mode , tmp , tmp , gen_int_mode ( exact_log2 ( div_factor ) , QImode ) ) ; riscv_expand_mult_with_const_int ( mode , dest , tmp , factor / ( vlenb / div_factor ) ) ; HOST_WIDE_INT constant = offset - factor ; if ( constant == <NUM_LIT> ) return ; else if ( SMALL_OPERAND ( constant ) ) riscv_expand_op ( PLUS , mode , dest , dest , gen_int_mode ( constant , mode ) ) ; else { rtx high ; high = gen_int_mode ( CONST_HIGH_PART ( constant ) , mode ) ; constant = CONST_LOW_PART ( constant ) ; riscv_emit_move ( tmp , high ) ; riscv_expand_op ( PLUS , mode , dest , tmp , dest ) ;


<s> x = gen_rtx_LO_SUM ( GET_MODE ( x ) , gen_rtx_HIGH ( GET_MODE ( x ) , x ) , x ) ; push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return x ; } if ( GET_CODE ( x ) == LO_SUM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == HIGH ) { push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ;


<s> Align Alignment = cast < ConstantInt > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getAlignValue ( ) ; auto * Ty = cast < FixedVectorType > ( Input -> getType ( ) ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ;

Value * Store = tryCreateMaskedScatterOffset ( I , Ptr , Builder ) ;


<s> unsigned NumParts = getNumVectorRegs ( SrcTy ) ; if ( NumParts <= <NUM_LIT> ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; unsigned Log2Diff = getElSizeLog2Diff ( SrcTy , DstTy ) ; unsigned VF = SrcTy -> getVectorNumElements ( ) ; for ( unsigned P = <NUM_LIT> ; P < Log2Diff ; ++ P ) { if ( NumParts > <NUM_LIT> ) NumParts /= <NUM_LIT> ; Cost += NumParts ; } if ( VF == <NUM_LIT> && SrcTy -> getScalarSizeInBits ( ) == <NUM_LIT> && DstTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) Cost -- ; return Cost ;


<s> if ( ! isImm ( ) ) return false ; if ( ! evaluateConstantImm ( getImm ( ) , Imm , VK ) || VK != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) return false ; return ( isRV64 ( ) && isUInt < <NUM_LIT> > ( Imm ) ) || isUInt < <NUM_LIT> > ( Imm ) ;


<s> return __builtin_mve_vmlsdavxq_sv16qi ( __a , __b ) ;


<s> } else if ( LoadedVT == <STR_LIT> ) { if ( TII . isValidAutoIncImm ( LoadedVT , Val ) ) Opcode = IsZeroExt ? <STR_LIT> : <STR_LIT> ; else Opcode = IsZeroExt ? <STR_LIT> : <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && IsZeroExt ) return SelectIndexedLoadZeroExtend64 ( LD , Opcode , dl ) ; if ( LD -> getValueType ( <NUM_LIT> ) == <STR_LIT> && ExtType == <STR_LIT> ) return SelectIndexedLoadSignExtend64 ( LD , Opcode , dl ) ; if ( TII . isValidAutoIncImm ( LoadedVT , Val ) ) { SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , Base , TargetConstVal , Chain ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result ; } else { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_1 ; }


<s> return CONST_INT_P ( mask ) && CONST_INT_P ( shft_amnt ) && INTVAL ( shft_amnt ) < GET_MODE_BITSIZE ( mode ) && exact_log2 ( ( INTVAL ( mask ) >> INTVAL ( shft_amnt ) ) + <NUM_LIT> ) >= <NUM_LIT> && ( INTVAL ( mask ) & ( ( HOST_WIDE_INT_1U << INTVAL ( shft_amnt ) ) - <NUM_LIT> ) ) == <NUM_LIT> ;


if ( ! DisableA15SDOptimization ) addPass ( createA15SDOptimizerPass ( ) ) ;


<s> AU . addRequired < DataLayout > ( ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ;


<s> explicit GCNTTIImpl ( const <ISA_LIT>TargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( static_cast < const <ISA_LIT>Subtarget * > ( TM -> getSubtargetImpl ( F ) ) ) , TLI ( ST -> getTargetLowering ( ) ) , CommonTTI ( TM , F ) , IsGraphicsShader ( <STR_LIT> ( F . getCallingConv ( ) ) ) {


<s> CRIS_ASSERT ( cfun -> machine -> return_type != CRIS_RETINSN_JUMP || on_stack ) ;


<s> if ( ! assignVRegs ( VRegs , ArgLocs , ArgLocsStartIndex , VT ) ) return false ;


<s> uint16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result ;


<s> if ( Subtarget . hasAltivec ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> && Subtarget . useCRBits ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } else if ( ( Constraint == <STR_LIT> || Constraint == <STR_LIT> ) && Subtarget . hasVSX ( ) ) { if ( VT == <STR_LIT> && Subtarget . hasP8Vector ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( R . first && VT == <STR_LIT> && Subtarget . is<ISA_LIT>64 ( ) && <STR_LIT> . contains ( R . first ) ) return std :: make_pair ( TRI -> getMatchingSuperReg ( R . first , <STR_LIT> , & <STR_LIT> ) , & <STR_LIT> ) ; if ( ! R . second && StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) {


<s> if ( MI != MBB . end ( ) && isFuncletReturnInstr ( * MI ) && STI . isOSWindows ( ) ) { if ( STI . is32Bit ( ) ) return true ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( Func -> getPersonalityFn ( ) ) ) ; if ( IsSEH ) return true ; } } DebugLoc DL = MBB . findDebugLoc ( MI ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; BuildMI ( MBB , MI , DL , TII . get ( Opc ) , Reg ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } return true ;


<s> int <ISA_LIT>MachineCFGStructurizer :: getBranchNzeroOpcode ( int OldOpcode ) { switch ( OldOpcode ) { case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ;

MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( ! VT . isVector ( ) && shouldTransformMulToShiftsAddsSubs ( C -> getAPIntValue ( ) , VT , DAG , Subtarget ) ) { assert ( VT . isInteger ( ) ) ; return genConstMult ( N -> getOperand ( <NUM_LIT> ) , C -> getAPIntValue ( ) , SDLoc ( N ) , VT , TL -> getScalarShiftAmountTy ( DAG . getDataLayout ( ) , VT ) , DAG ) ; }


<s> if ( I -> isDebugValue ( ) ) continue ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) break ;


<s> static const MCPhysReg CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CalleeSavedRegsFP [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CalleeSavedRegsIntr [ ] = {


<s> SDLoc DL ( N ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op2 = N -> getOperand ( <NUM_LIT> ) ; EVT ScalarTy = Op1 . getValueType ( ) ; if ( ( ScalarTy == <STR_LIT> ) || ( ScalarTy == <STR_LIT> ) ) { Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ;

Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op2 ) ;


<s> return ( __m128i ) __builtin_ia32_pmovusdw256_mask ( ( __v8si ) __A , ( __v8hi ) _mm_setzero_si128 ( ) , __M ) ;


<s> addPass ( & PostRAHazardRecognizerID ) ; addPass ( create<ISA_LIT>InsertWaitsPass ( ) ) ; addPass ( create<ISA_LIT>ShrinkInstructionsPass ( ) ) ;

addPass ( create<ISA_LIT>LowerControlFlowPass ( ) , false ) ;


<s> if ( Subtarget . hasVSX ( ) ) { if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return false ; } else { return false ;


<s> <ISA_LIT>SEInstrInfo :: <ISA_LIT>SEInstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>InstrInfo ( STI , getUnconditionalBranch ( STI ) ) , RI ( STI ) {


<s> rtx rr ; if ( TARGET_SHMEDIA ) { int rr_regno = sh_media_register_for_return ( ) ; if ( rr_regno < <NUM_LIT> ) rr_regno = pr_reg ; rr = gen_rtx_REG ( DImode , rr_regno ) ; } else rr = gen_rtx_REG ( SImode , pr_reg ) ; emit_insn ( GEN_MOV ( rr , ra ) ) ; emit_use ( rr ) ; return ; } if ( TARGET_SH5 ) { int offset ; save_schedule schedule ; save_entry * entry ; entry = sh5_schedule_saves ( & live_regs_mask , & schedule , <NUM_LIT> ) ;


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<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & FS ) { std :: string TARGET = <STR_LIT> ;


<s> void <ISA_LIT>AsmPrinter :: refContents ( Constant * C ) {

for ( unsigned i = <NUM_LIT> , e = C -> getNumOperands ( ) ; i != e ; ++ i ) {


<s> if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( GV -> hasDLLImportLinkage ( ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { AM . GVOpFlags = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { AM . GVOpFlags = <STR_LIT> ; } return true ; } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; } if ( AM . IndexReg == <NUM_LIT> ) { assert ( AM . Scale == <NUM_LIT> && <STR_LIT> ) ; AM . IndexReg = getRegForValue ( V ) ; return AM . IndexReg != <NUM_LIT> ; }


<s> if ( ValTy -> isVectorTy ( ) && ISD == <STR_LIT> ) { const unsigned AmortizationCost = <NUM_LIT> ; static const TypeConversionCostTblEntry < <STR_LIT> > VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } } ; EVT SelCondTy = TLI -> getValueType ( CondTy ) ; EVT SelValTy = TLI -> getValueType ( ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { int Idx = ConvertCostTableLookup ( VectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ;

if ( Idx != - <NUM_LIT> ) return VectorSelectTbl [ Idx ] . Cost ;


<s> FunctionType * TrampolineTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; FunctionType * TargetFuncTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; Function * Trampoline = Function :: Create ( TrampolineTy , GlobalValue :: InternalLinkage , Twine ( <STR_LIT> ) + GlobalValue :: dropLLVMManglingEscape ( ParentFunc -> getName ( ) ) , TheModule ) ; if ( auto * C = ParentFunc -> getComdat ( ) ) Trampoline -> setComdat ( C ) ; BasicBlock * EntryBB = BasicBlock :: Create ( Context , <STR_LIT> , Trampoline ) ; IRBuilder < > Builder ( EntryBB ) ;

Value * LSDA = emitEHLSDA ( Builder , ParentFunc ) ;


<s> uint64_t NumElts = DL . getTypeSizeInBits ( I . getType ( ) ) / <NUM_LIT> ; Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; unsigned NumElts = <NUM_LIT> ; for ( unsigned ArgI = <NUM_LIT> , ArgE = I . getNumArgOperands ( ) ; ArgI < ArgE ; ++ ArgI ) { Type * ArgTy = I . getArgOperand ( ArgI ) -> getType ( ) ; if ( ! ArgTy -> isVectorTy ( ) ) break ; NumElts += DL . getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; } Info . memVT = EVT :: getVectorVT ( I . getType ( ) -> getContext ( ) , <STR_LIT> , NumElts ) ; Info . ptrVal = I . getArgOperand ( I . getNumArgOperands ( ) - <NUM_LIT> ) ; Info . offset = <NUM_LIT> ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : MF ( MF ) , SRetReturnReg ( <NUM_LIT> ) , GlobalBaseReg ( <NUM_LIT> ) , <ISA_LIT>16SPAliasReg ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , CallsEhReturn ( false ) , IsISR ( false ) , SaveS2 ( false ) , MoveF64ViaSpillFI ( - <NUM_LIT> ) {


<s> mcld :: TargetRegistry :: RegisterDiagnosticLineInfo ( mcld :: The<ISA_LIT>Target , mcld :: create<ISA_LIT>DiagLineInfo ) ;


<s> MCRegister SuperReg = TRI -> getMatchingSuperReg ( SrcReg , <STR_LIT> , & <STR_LIT> ) ; if ( VSXSelfCopyCrash && DestReg == SuperReg ) llvm_unreachable ( <STR_LIT> ) ; SrcReg = SuperReg ; } if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { MCRegister CRReg = getCRFromCRBit ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( CRReg ) ; getKillRegState ( KillSrc ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( TRI -> getEncodingValue ( CRReg ) * <NUM_LIT> + ( <NUM_LIT> - getCRBitValue ( SrcReg ) ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) ) { bool Is64Bit = <STR_LIT> . contains ( DestReg ) ; unsigned MvCode = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ShCode = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned CRNum = TRI -> getEncodingValue ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( MvCode ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; if ( CRNum == <NUM_LIT> ) return ; BuildMI ( MBB , I , DL , get ( ShCode ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( CRNum * <NUM_LIT> + <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { assert ( Subtarget . hasDirectMove ( ) && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; NumGPRtoVSRSpill ++ ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { assert ( Subtarget . hasDirectMove ( ) && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ;


<s> val = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( CONST_OK_FOR_M ( val ) ) return <NUM_LIT> ; else if ( const_ok_for_mcore ( val ) ) return <NUM_LIT> ; else if ( TARGET_HARDLIT && mcore_const_ok_for_inline ( val ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> Function * Func = Arg -> getParent ( ) ; Instruction * FirstInst = & ( Func -> getEntryBlock ( ) . front ( ) ) ; PointerType * PType = dyn_cast < PointerType > ( Arg -> getType ( ) ) ; assert ( PType && <STR_LIT> ) ; Type * StructType = PType -> getElementType ( ) ; AllocaInst * AllocA = new AllocaInst ( StructType , Arg -> getName ( ) , FirstInst ) ; AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) + <NUM_LIT> ) ) ; Arg -> replaceAllUsesWith ( AllocA ) ; Type * CvtTypes [ ] = { Type :: getInt8PtrTy ( Func -> getParent ( ) -> getContext ( ) , ADDRESS_SPACE_PARAM ) , Type :: getInt8PtrTy ( Func -> getParent ( ) -> getContext ( ) , ADDRESS_SPACE_GENERIC ) } ; Function * CvtFunc = <STR_LIT> ( Func -> getParent ( ) , <STR_LIT> , CvtTypes ) ; Value * BitcastArgs [ ] = { new BitCastInst ( Arg , Type :: getInt8PtrTy ( Func -> getParent ( ) -> getContext ( ) , ADDRESS_SPACE_GENERIC ) , Arg -> getName ( ) , FirstInst ) } ;

CallInst * CallCVT = CallInst :: Create ( CvtFunc , BitcastArgs , <STR_LIT> , FirstInst ) ;


<s> static bool isHighLatencyCPSR ( MachineInstr * Def ) { switch ( Def -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : return true ; } return false ;


<s> for ( auto I = BB -> begin ( ) , I_END = BB -> end ( ) ; I != I_END ; I ++ ) { if ( isa < SwitchInst > ( I ) ) { const SwitchInst * SwitchInstPtr = dyn_cast < SwitchInst > ( I ) ; SwitchLeafData * newSwitch = new SwitchLeafData ( SwitchInstPtr ) ;

newSwitch -> searchAndInsert ( SwitchInstPtr ) ;


<s> return createELFObjectWriter ( std :: move ( MOTW ) , OS , true ) ;


<s> void <ISA_LIT>CFGStructurizer :: showImproveSimpleJumpintoIf ( MachineBasicBlock * HeadMBB , MachineBasicBlock * TrueMBB , MachineBasicBlock * FalseMBB , MachineBasicBlock * LandMBB , bool Detail ) { dbgs ( ) << <STR_LIT> << HeadMBB -> getNumber ( ) << <STR_LIT> << HeadMBB -> size ( ) ; if ( Detail ) { dbgs ( ) << <STR_LIT> ; HeadMBB -> print ( dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ; } if ( TrueMBB ) { dbgs ( ) << <STR_LIT> << TrueMBB -> getNumber ( ) << <STR_LIT> << TrueMBB -> size ( ) << <STR_LIT> << TrueMBB -> pred_size ( ) ; if ( Detail ) { dbgs ( ) << <STR_LIT> ; TrueMBB -> print ( dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ; } } if ( FalseMBB ) { dbgs ( ) << <STR_LIT> << FalseMBB -> getNumber ( ) << <STR_LIT> << FalseMBB -> size ( ) << <STR_LIT> << FalseMBB -> pred_size ( ) ; if ( Detail ) { dbgs ( ) << <STR_LIT> ; FalseMBB -> print ( dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ; } } if ( LandMBB ) { dbgs ( ) << <STR_LIT> << LandMBB -> getNumber ( ) << <STR_LIT> << LandMBB -> size ( ) << <STR_LIT> << LandMBB -> pred_size ( ) ; if ( Detail ) { dbgs ( ) << <STR_LIT> ;


<s> if ( ! MRI . isSSA ( ) ) return ; assert ( TII -> isVOP1 ( MI . getOpcode ( ) ) || TII -> isVOP2 ( MI . getOpcode ( ) ) || TII -> isVOPC ( MI . getOpcode ( ) ) ) ; const <ISA_LIT>RegisterInfo & TRI = TII -> getRegisterInfo ( ) ; int Src0Idx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; if ( Src0 . isImm ( ) && TII -> isLiteralConstant ( Src0 , TII -> getOpSize ( MI , Src0Idx ) ) ) return ; if ( Src0 . isReg ( ) && ! isVGPR ( & Src0 , TRI , MRI ) ) return ; if ( Src0 . isReg ( ) && MRI . hasOneUse ( Src0 . getReg ( ) ) ) { unsigned Reg = Src0 . getReg ( ) ; MachineInstr * Def = MRI . getUniqueVRegDef ( Reg ) ;

if ( Def && Def -> isMoveImmediate ( ) ) {


<s> assert ( TI != LoopEnd -> end ( ) ) ; MachineInstr * Branch = & ( * TI ) ; MachineFunction * MF = LoopEnd -> getParent ( ) ; MachineRegisterInfo & MRI = LoopEnd -> getParent ( ) -> getRegInfo ( ) ; if ( Branch -> getOpcode ( ) == <STR_LIT> ) { unsigned DstReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned BackEdgeReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder HeaderPHIBuilder = BuildMI ( * ( MF ) , Branch -> getDebugLoc ( ) , get ( TargetOpcode :: PHI ) , DstReg ) ; for ( MachineBasicBlock :: pred_iterator PI = LoopEntry -> pred_begin ( ) , E = LoopEntry -> pred_end ( ) ; PI != E ; ++ PI ) { if ( * PI == LoopEnd ) {

HeaderPHIBuilder . addReg ( BackEdgeReg ) ;


<s> return ( INTVAL ( op ) % <NUM_LIT> ) == <NUM_LIT> && INTVAL ( op ) < <NUM_LIT> ; case SImode : case SFmode : return ( INTVAL ( op ) % <NUM_LIT> ) == <NUM_LIT> && INTVAL ( op ) < <NUM_LIT> ; case DImode : case DFmode : return ( INTVAL ( op ) % <NUM_LIT> ) == <NUM_LIT> && INTVAL ( op ) < <NUM_LIT> ; default : return false ;


<s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch = <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; else Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc DL ( Op ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( MF . getDataLayout ( ) ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FI , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> static void sh_canonicalize_comparison ( int * code , rtx * op0 , rtx * op1 , bool op0_preserve_value ) { enum rtx_code tmp_code = ( enum rtx_code ) * code ; sh_canonicalize_comparison ( tmp_code , * op0 , * op1 , VOIDmode , op0_preserve_value ) ;


<s> insn = emit_move_insn ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , GEN_INT ( hi ) ) ; if ( lo ) { insn = emit_insn ( gen_iorsi3 ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , GEN_INT ( lo ) ) ) ; } insn = emit_insn ( gen_addsi3 ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) ) ) ; if ( mark_frame ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( gen_rtx_REG ( SImode , dest ) , gen_rtx_PLUS ( SImode , gen_rtx_REG ( SImode , dest ) , GEN_INT ( value ) ) ) ) ;


<s> int orderNo2 = N0 . getNode ( ) -> getIROrder ( ) ; if ( orderNo - orderNo2 < <NUM_LIT> ) return SDValue ( ) ; bool opIsLive = false ; const SDNode * left = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; const SDNode * right = N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( isa < ConstantSDNode > ( left ) || isa < ConstantSDNode > ( right ) ) opIsLive = true ; if ( ! opIsLive ) for ( const SDNode * User : left -> uses ( ) ) { int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) { opIsLive = true ; break ; } } if ( ! opIsLive ) for ( const SDNode * User : right -> uses ( ) ) { int orderNo3 = User -> getIROrder ( ) ; if ( orderNo3 > orderNo ) { opIsLive = true ; break ; } }


<s> if ( ( <STR_LIT> ( V1 . getNode ( ) ) || V1 . isUndef ( ) ) && ( <STR_LIT> ( V2 . getNode ( ) ) || V2 . isUndef ( ) ) ) { SmallVector < SDValue > Ops ( Mask . size ( ) , DAG . getUNDEF ( VT . getScalarType ( ) ) ) ;

for ( int I = <NUM_LIT> , NumElts = Mask . size ( ) ; I != NumElts ; ++ I ) {


<s> using namespace llvm :: <STR_LIT> ; unsigned Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Imm == DPP_FI_1 || Imm == DPP8_FI_1 ) { O << <STR_LIT> ;


<s> static const unsigned Variants [ ] = { <ISA_LIT>AsmVariants :: VOP3 } ; return makeArrayRef ( Variants ) ; } if ( isForcedSDWA ( ) ) { static const unsigned Variants [ ] = { <ISA_LIT>AsmVariants :: SDWA , <ISA_LIT>AsmVariants :: SDWA9 } ; return makeArrayRef ( Variants ) ; } if ( isForcedDPP ( ) ) { static const unsigned Variants [ ] = { <ISA_LIT>AsmVariants :: DPP } ;


<s> static rtx gen_frame_load ( rtx reg , rtx frame_reg , int offset ) {

return gen_frame_set ( reg , frame_reg , offset , false ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getSpillTarget ( ) const { bool IsP10Variant = Subtarget . isISA3_1 ( ) || Subtarget . pairedVectorMemops ( ) ; return IsP10Variant ? <NUM_LIT> : Subtarget . hasP9Vector ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> case 'w' : case 'y' : if ( type -> isFloatingPointTy ( ) || type -> isVectorTy ( ) ) weight = CW_Register ; break ; case 'z' : weight = CW_Constant ; break ; case 'U' : if ( parsePredicateConstraint ( constraint ) != PredicateConstraint :: Invalid ) weight = CW_Register ; break ; } return weight ;


<s> unsigned getSubReg ( ) const { assert ( isReg ( ) && <STR_LIT> ) ;


<s> unsigned Size = Op . getNumOperands ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Ops . push_back ( Op . getOperand ( i ) ) ; if ( VecTy . getSizeInBits ( ) == <NUM_LIT> * Subtarget . getVectorLength ( ) ) { ArrayRef < SDValue > A ( Ops ) ; MVT SingleTy = typeSplit ( VecTy ) . first ; SDValue V0 = buildHvxVectorReg ( A . take_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ; SDValue V1 = buildHvxVectorReg ( A . drop_front ( Size / <NUM_LIT> ) , dl , SingleTy , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , V0 , V1 ) ;


<s> static __inline qword si_ilh ( signed short imm ) {

return ( ( qword ) ( vec_splat ( ( vec_short8 ) ( si_from_short ( imm ) ) , <NUM_LIT> ) ) ) ;


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDLoc dl ( GA ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; <STR_LIT> CallType = LocalDynamic ? <STR_LIT> : <STR_LIT> ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ;

Chain = DAG . getNode ( CallType , dl , NodeTys , Ops ) ;


<s> bool <ISA_LIT>Operand :: isMoveMask ( ) const {


<s> SDValue Intr = DAG . getNode ( Opc , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops . begin ( ) , Ops . size ( ) ) ; SDValue OutLo = DAG . getCopyFromReg ( Intr . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , Intr . getValue ( <NUM_LIT> ) ) ; SDValue OutHi = DAG . getCopyFromReg ( OutLo . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , OutLo . getValue ( <NUM_LIT> ) ) ; SDValue Out = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutLo , OutHi ) ; if ( ! HasChainIn ) return Out ; SDValue Vals [ ] = { Out , OutHi . getValue ( <NUM_LIT> ) } ;

return DAG . getMergeValues ( Vals , <NUM_LIT> , DL ) ;


<s> if ( StackSize ) SPReg = MRI . createVirtualRegister ( PtrRC ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetTriple ( ) . isOSBinFormatELF ( ) ) { const char * ES = <STR_LIT> ; auto * SPSymbol = MF . createExternalSymbolName ( ES ) ; unsigned Zero = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , Zero ) . addImm ( <NUM_LIT> ) ; MachineMemOperand * LoadMMO = MF . getMachineMemOperand ( MachinePointerInfo ( MF . getPSVManager ( ) . getExternalSymbolCallEntry ( ES ) ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addImm ( <NUM_LIT> ) . addExternalSymbol ( SPSymbol ) . addReg ( Zero ) . addMemOperand ( LoadMMO ) ; } else { auto & MMIW = MF . getMMI ( ) . getObjFileInfo < MachineModuleInfoWasm > ( ) ; if ( ! MMIW . hasStackPointerGlobal ( ) ) { MMIW . setStackPointerGlobal ( MMIW . getGlobals ( ) . size ( ) ) ; MMIW . addGlobal ( <STR_LIT> ) ; } BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addImm ( MMIW . getStackPointerGlobal ( ) ) ; } bool HasBP = hasBP ( MF ) ;


<s> static void nvptx_assemble_decl_begin ( FILE * file , const char * name , const char * section , const_tree type , HOST_WIDE_INT size , unsigned align ) { while ( TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; if ( TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == COMPLEX_TYPE ) type = TREE_TYPE ( type ) ; unsigned elt_size = int_size_in_bytes ( type ) ; machine_mode elt_mode = TYPE_MODE ( type ) == BLKmode ? Pmode : DImode ; elt_size |= GET_MODE_SIZE ( elt_mode ) ; elt_size &= - elt_size ; init_frag . size = elt_size ; init_frag . mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( elt_size * BITS_PER_UNIT - <NUM_LIT> ) ) - <NUM_LIT> ; init_frag . val = <NUM_LIT> ; init_frag . offset = <NUM_LIT> ; init_frag . started = false ; init_frag . remaining = ( size + elt_size - <NUM_LIT> ) / elt_size ; fprintf ( file , <STR_LIT> , section , align / BITS_PER_UNIT , elt_size * BITS_PER_UNIT ) ;


<s> Offset += <NUM_LIT> ; return ( ( unsigned ) MO2 . getImm ( ) << <NUM_LIT> ) | Reg ; } assert ( MO2 . isExpr ( ) && <STR_LIT> ) ; <STR_LIT> FixupKind ; switch ( Reg ) { case <NUM_LIT> : FixupKind = <STR_LIT> ; break ; case <NUM_LIT> : FixupKind = <STR_LIT> ; break ; default : FixupKind = <STR_LIT> ; break ; }

Fixups . push_back ( MCFixup :: create ( Offset , MO2 . getExpr ( ) , static_cast < MCFixupKind > ( FixupKind ) , MI . getLoc ( ) ) ) ;


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) || cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; if ( ST -> isThumb1Only ( ) ) return SDValue ( ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Hi , <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi . getValue ( <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ;


<s> } else if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize ; if ( TRI -> needsStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = alignTo ( FrameSize , MaxAlign ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else { NumBytes = StackSize - CSSize ; } uint64_t SEHStackAllocAmt = NumBytes ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) break ; -- MBBI ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; if ( TargetMBB ) { unsigned ReturnReg = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( STI . is64Bit ( ) ) { BuildMI ( MBB , FirstCSPop , DL , TII . get ( <STR_LIT> ) , ReturnReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( TargetMBB ) . addReg ( <NUM_LIT> ) ; } else { BuildMI ( MBB , FirstCSPop , DL , TII . get ( <STR_LIT> ) , ReturnReg ) . addMBB ( TargetMBB ) ; } TargetMBB -> setHasAddressTaken ( ) ; } if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( Uses64BitFramePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , LEAAmount ) ; -- MBBI ; } else { unsigned Opc = ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; -- MBBI ; }


<s> LLT EltTy = VecTy . getElementType ( ) ; assert ( EltTy == MRI . getType ( Dst ) ) ; B . setInstr ( MI ) ; if ( IdxVal -> Value < VecTy . getNumElements ( ) ) B . buildExtract ( Dst , Vec , IdxVal -> Value * EltTy . getSizeInBits ( ) ) ; else B . buildUndef ( Dst ) ; MI . eraseFromParent ( ) ;


<s> bool <ISA_LIT>CallLowering :: lowerCall ( MachineIRBuilder & MIRBuilder , CallLoweringInfo & Info ) const { if ( Info . CallConv != CallingConv :: C ) return false ; for ( auto & Arg : Info . OrigArgs ) { if ( ! isSupportedArgumentType ( Arg . Ty ) ) return false ; if ( Arg . Flags [ <NUM_LIT> ] . isByVal ( ) ) return false ; if ( Arg . Flags [ <NUM_LIT> ] . isSRet ( ) && ! Arg . Ty -> isPointerTy ( ) ) return false ; } if ( ! Info . OrigRet . Ty -> isVoidTy ( ) && ! isSupportedReturnType ( Info . OrigRet . Ty ) ) return false ; MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>ABIInfo & ABI = TM . getABI ( ) ; MachineInstrBuilder CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; const bool IsCalleeGlobalPIC = Info . Callee . isGlobal ( ) && TM . isPositionIndependent ( ) ; MachineInstrBuilder MIB = MIRBuilder . buildInstrNoInsert ( Info . Callee . isReg ( ) || IsCalleeGlobalPIC ? <STR_LIT> : <STR_LIT> ) ; MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; if ( IsCalleeGlobalPIC ) { Register CalleeReg = MF . getRegInfo ( ) . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) ; MachineInstr * CalleeGlobalValue = MIRBuilder . buildGlobalValue ( CalleeReg , Info . Callee . getGlobal ( ) ) ; if ( ! Info . Callee . getGlobal ( ) -> hasLocalLinkage ( ) ) CalleeGlobalValue -> getOperand ( <NUM_LIT> ) . setTargetFlags ( <STR_LIT> ) ; MIB . addUse ( CalleeReg ) ; } else MIB . add ( Info . Callee ) ;

const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


<s> return type == RAInfo :: LocType :: Register ;


<s> const TargetRegisterClass * getMatchingSuperRegClass ( const TargetRegisterClass * A , const TargetRegisterClass * B , unsigned Idx ) const override { return A ;


<s> virtual ~ SpecialTypeDescriptor ( ) {


return Kind == KindTy :: SystemRegister ;


<s> if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) + ( reload_completed | reload_in_progress ) ; else return COSTS_N_INSNS ( <NUM_LIT> ) + ( reload_completed | reload_in_progress ) ;


<s> { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , } ; bool Is64Bit = SrcVT == <STR_LIT> ; if ( I -> getType ( ) -> isDoubleTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else if ( I -> getType ( ) -> isFloatTy ( ) ) { Opcode = IsSigned ? SCvtOpc [ HasAVX512 ] [ <NUM_LIT> ] [ Is64Bit ] : UCvtOpc [ <NUM_LIT> ] [ Is64Bit ] ; } else return false ; MVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( DstVT ) ; unsigned ImplicitDefReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; unsigned ResultReg = fastEmitInst_rr ( Opcode , RC , ImplicitDefReg , true , OpReg , false ) ; updateValueMap ( I , ResultReg ) ;


<s> <ISA_LIT>MCELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter ) : MCELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) , MCII ( create<ISA_LIT>MCInstrInfo ( ) ) {


<s> return ( __m512i ) __builtin_ia32_pbroadcastw512_mask ( ( __v8hi ) __A , ( __v32hi ) _mm512_setzero_si512 ( ) , __M ) ;


<s> SchedImpl -> initialize ( this ) ; DEBUG ( unsigned maxH = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getHeight ( ) > maxH ) maxH = SUnits [ su ] . getHeight ( ) ; dbgs ( ) << <STR_LIT> << maxH << <STR_LIT> ; ) ; DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ; initQueues ( TopRoots , BotRoots ) ; bool IsTopNode = false ; while ( true ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; SUnit * SU = SchedImpl -> pickNode ( IsTopNode ) ; if ( ! SU ) break ;


<s> <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) ; <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 ( ) ;