<s> } ; if ( TM . isPositionIndependent ( ) ) { bool Indirect = STI . isGVIndirectSymbol ( GV ) ; bool UseOpcodeThatLoads = Indirect && ! STI . isThumb ( ) ; unsigned Opc = UseMovt && ! STI . isTargetELF ( ) ? ( UseOpcodeThatLoads ? ( unsigned ) <STR_LIT> : Opcodes . MOV_ga_pcrel ) : ( UseOpcodeThatLoads ? ( unsigned ) <STR_LIT> : Opcodes . LDRLIT_ga_pcrel ) ; MIB -> setDesc ( TII . get ( Opc ) ) ; int TargetFlags = <STR_LIT> ; if ( STI . isTargetDarwin ( ) ) TargetFlags |= <STR_LIT> ; if ( STI . isGVInGOT ( GV ) ) TargetFlags |= <STR_LIT> ; MIB -> getOperand ( <NUM_LIT> ) . setTargetFlags ( TargetFlags ) ; if ( Indirect ) { if ( ! UseOpcodeThatLoads ) { auto ResultReg = MIB . getReg ( <NUM_LIT> ) ; auto AddressReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( AddressReg ) ; auto InsertBefore = std :: next ( MIB -> getIterator ( ) ) ; auto MIBLoad = BuildMI ( MBB , InsertBefore , MIB -> getDebugLoc ( ) , TII . get ( Opcodes . LOAD32 ) ) . addDef ( ResultReg ) . addReg ( AddressReg ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; addGOTMemOperand ( MIBLoad ) ; if ( ! constrainSelectedInstRegOperands ( * MIBLoad , TII , TRI , RBI ) ) return false ; } else { addGOTMemOperand ( MIB ) ; } } return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } bool isReadOnly = STI . getTargetLowering ( ) -> isReadOnly ( GV ) ; if ( STI . isROPI ( ) && isReadOnly ) { unsigned Opc = UseMovt ? Opcodes . MOV_ga_pcrel : Opcodes . LDRLIT_ga_pcrel ; MIB -> setDesc ( TII . get ( Opc ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ; } if ( STI . isRWPI ( ) && ! isReadOnly ) { auto Offset = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstrBuilder OffsetMIB ;


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( BString == <NUM_LIT> || BString == <NUM_LIT> ) && ( ( Imm & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> if ( Ty -> isHalfTy ( ) || Ty -> isFloatTy ( ) || Ty -> isDoubleTy ( ) ) return true ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) return true ;


const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ;


<s> StringRef CPU = <STR_LIT> ( TT , TM . getTargetCPU ( ) ) ; StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & MTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM ) ; bool IsABICalls = STI . isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { TS . emitDirectiveAbiCalls ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! ABI . IsN64 ( ) ) TS . emitDirectiveOptionPic0 ( ) ; }

std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ;


<s> if ( ! isValidClauseInst ( MI , IsVMEM ) ) continue ; RegUse Defs , Uses ; GCNDownwardRPTracker RPT ( * LIS ) ; RPT . reset ( MI ) ; if ( ! processRegUses ( MI , Defs , Uses , RPT ) ) continue ; unsigned Length = <NUM_LIT> ; for ( ; Next != E && Length < FuncMaxClause ; ++ Next ) { if ( ! isValidClauseInst ( * Next , IsVMEM ) ) break ; if ( ! processRegUses ( * Next , Defs , Uses , RPT ) ) break ; ++ Length ; } if ( Length < <NUM_LIT> ) continue ; Changed = true ; MFI -> limitOccupancy ( LastRecordedOccupancy ) ; auto B = BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( TargetOpcode :: BUNDLE ) ) ; Ind -> insertMachineInstrInMaps ( * B ) ; for ( auto BI = I ; BI != Next ; ++ BI ) { BI -> bundleWithPred ( ) ; Ind -> removeSingleMachineInstrFromMaps ( * BI ) ; for ( MachineOperand & MO : BI -> defs ( ) ) if ( MO . readsReg ( ) ) MO . setIsInternalRead ( true ) ; } for ( auto && R : Defs ) { forAllLanes ( R . first , R . second . second , [ & R , & B ] ( unsigned SubReg ) { unsigned S = R . second . first | RegState :: EarlyClobber ; if ( ! SubReg ) S &= ~ ( RegState :: Undef | RegState :: Dead ) ; B . addDef ( R . first , S , SubReg ) ; } ) ; } for ( auto && R : Uses ) { forAllLanes ( R . first , R . second . second , [ & R , & B ] ( unsigned SubReg ) { B . addUse ( R . first , R . second . first & ~ RegState :: Kill , SubReg ) ; } ) ; } for ( auto && R : Defs ) { unsigned Reg = R . first ; Uses . erase ( Reg ) ; if ( Register :: isPhysicalRegister ( Reg ) ) continue ; LIS -> removeInterval ( Reg ) ; LIS -> createAndComputeVirtRegInterval ( Reg ) ; } for ( auto && R : Uses ) { unsigned Reg = R . first ;


<s> static bool spu_vector_alignment_reachable ( const_tree type ATTRIBUTE_UNUSED , bool is_packed ) {


<s> SMLoc getEndLoc ( ) const override { return EndLoc ;


<s> for ( auto * User : I . users ( ) ) ProcessUser ( MemOpOffsetMap , * User , Offset , false ) ; ProcessMemOpWRTCompositeSource ( SrcMem , MemOpOffsetMap , DestTy ) ;


<s> const AMDGPURegisterInfo * getRegisterInfo ( ) const override {

return & getInstrInfo ( ) -> getRegisterInfo ( ) ;


<s> if ( Coexist && ! Dependence ) return true ; if ( PromotedToDotNew ) demoteToDotOld ( I ) ; cleanUpDotCur ( ) ; if ( GlueAllocframeStore ) { useCalleesSP ( I ) ; GlueAllocframeStore = false ; } if ( ChangedOffset != INT64_MAX ) undoChangedOffset ( I ) ; if ( GlueToNewValueJump ) {


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ;

NewMIs . back ( ) -> addMemOperand ( MF , MMO ) ;


<s> if ( GET_CODE ( x ) == UNSPEC && XINT ( x , <NUM_LIT> ) == UNSPEC_TLS ) iter . skip_subrtxes ( ) ; } return false ;


<s> NopInst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Instructions . push_back ( NopInst ) ; return false ; } if ( MCID . mayLoad ( ) || MCID . mayStore ( ) ) { for ( unsigned i = <NUM_LIT> ; i < MCID . getNumOperands ( ) ; i ++ ) { const MCOperandInfo & OpInfo = MCID . OpInfo [ i ] ; if ( ( OpInfo . OperandType == MCOI :: OPERAND_MEMORY ) || ( OpInfo . OperandType == MCOI :: OPERAND_UNKNOWN ) ) { MCOperand & Op = Inst . getOperand ( i ) ; if ( Op . isImm ( ) ) { int MemOffset = Op . getImm ( ) ; if ( MemOffset < - <NUM_LIT> || MemOffset > <NUM_LIT> ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , true ) ; return false ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Expr = Op . getExpr ( ) ; if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * SR = static_cast < const MCSymbolRefExpr * > ( Expr ) ; if ( SR -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , false ) ; return false ; } } else if ( ! isEvaluated ( Expr ) ) { expandMemInst ( Inst , IDLoc , Instructions , MCID . mayLoad ( ) , false ) ; return false ; } } } }


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>leTarget ) ;

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( The<ISA_LIT>beTarget ) ;


<s> emit_move_insn ( gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , const0_rtx ) ) , const0_rtx ) ; emit_insn ( gen_blockage ( ) ) ; } dump_stack_clash_frame_info ( PROBE_INLINE , size != rounded_size ) ; } else { emit_move_insn ( r12 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r12 , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , r12 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , stack_pointer_rtx , stack_pointer_rtx , r12 , r14 ) ) ; emit_insn ( gen_blockage ( ) ) ; dump_stack_clash_frame_info ( PROBE_LOOP , size != rounded_size ) ; } } else dump_stack_clash_frame_info ( NO_PROBE_SMALL_FRAME , true ) ; if ( size != rounded_size ) { if ( size - rounded_size >= <NUM_LIT> ) { emit_move_insn ( r14 , GEN_INT ( size - rounded_size ) ) ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , r14 ) ) ) ; } else emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( rounded_size - size ) ) ) ) ; } if ( first ) { emit_move_insn ( r12 , GEN_INT ( first ) ) ; emit_insn ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , r12 ) ) ) ;


<s> int32_t ImmVal = ( int32_t ) DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned UseOpc = UseMI . getOpcode ( ) ; unsigned NewUseOpc ; unsigned UseIdx ; int CommuteIdx = - <NUM_LIT> ; bool TieOps = false ; switch ( UseOpc ) { case <STR_LIT> : TieOps = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = <STR_LIT> ; if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> ; else if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> , CommuteIdx = <NUM_LIT> ; else return false ; break ; case <STR_LIT> : TieOps = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! STI . hasLoadStoreOnCond2 ( ) ) return false ; NewUseOpc = <STR_LIT> ; if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> ; else if ( UseMI . getOperand ( <NUM_LIT> ) . getReg ( ) == Reg ) UseIdx = <NUM_LIT> , CommuteIdx = <NUM_LIT> ; else return false ; break ;


<s> if ( mode == VOIDmode ) return GEN_INT ( - <NUM_LIT> ) ; if ( cum -> nregs == <NUM_LIT> ) return NULL_RTX ; regno = x86_64_ms_abi_int_parameter_registers [ cum -> regno ] ; if ( TARGET_SSE && ( mode == SFmode || mode == DFmode ) ) { if ( named ) { if ( type == NULL_TREE || ! AGGREGATE_TYPE_P ( type ) ) regno = cum -> regno + FIRST_SSE_REG ; } else { rtx t1 , t2 ;

t1 = gen_rtx_REG ( mode , cum -> regno + FIRST_SSE_REG ) ;


<s> if ( ! c6x_flag_schedule_insns2 ) PUT_MODE ( insn , TImode ) ; else { int cycles ; this_clock = insn_get_clock ( insn ) ; if ( this_clock != prev_clock ) { PUT_MODE ( insn , TImode ) ; if ( ! first ) { cycles = this_clock - prev_clock ; cycles -= prev_implicit_nops ; if ( cycles > <NUM_LIT> ) { rtx nop = emit_nop_after ( cycles - <NUM_LIT> , prev ) ; insn_set_clock ( nop , prev_clock + prev_implicit_nops + <NUM_LIT> ) ; } } prev_clock = this_clock ; if ( last_call && insn_get_clock ( last_call ) + <NUM_LIT> <= this_clock ) { emit_label_before ( call_labels [ INSN_UID ( last_call ) ] , insn ) ; last_call = NULL_RTX ; } prev_implicit_nops = <NUM_LIT> ; } } if ( recog_memoized ( insn ) >= <NUM_LIT> && ( c6x_flag_schedule_insns2 || ! returning_call_p ( insn ) ) ) { max_cycles = get_attr_cycles ( insn ) ; if ( get_attr_type ( insn ) == TYPE_CALLP ) prev_implicit_nops = <NUM_LIT> ; } else max_cycles = <NUM_LIT> ; if ( returning_call_p ( insn ) ) last_call = insn ; if ( c6x_flag_schedule_insns2 ) { gcc_assert ( this_clock >= <NUM_LIT> ) ; if ( earliest_bb_end < this_clock + max_cycles ) earliest_bb_end = this_clock + max_cycles ; } else if ( max_cycles > <NUM_LIT> ) emit_nop_after ( max_cycles - <NUM_LIT> , insn ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalICmpImmediate ( int64_t Imm ) const {


<s> int64_t Imm = <NUM_LIT> ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;

bool IsConstant = evaluateConstantImm ( Expr , Imm , VK ) ;


<s> bool writeback = ( W == <NUM_LIT> ) | ( P == <NUM_LIT> ) ; addr |= ( U << <NUM_LIT> ) | ( Rn << <NUM_LIT> ) ; if ( writeback && ( Rn == Rt || Rn == Rt2 ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( Rt == Rt2 ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecodeT2AddrModeImm8s4 ( Inst , addr , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> } std :: string Collapsed = std :: string ( RawString ) ; Collapsed . erase ( llvm :: remove_if ( Collapsed , isspace ) , Collapsed . end ( ) ) ; StringRef FullString = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = FullString . split ( '.' ) ; unsigned DotReg = matchRegister ( DotSplit . first . lower ( ) ) ; if ( DotReg != <STR_LIT> && RegisterMatchesArch ( DotReg ) ) { if ( DotSplit . second . empty ( ) ) { RegNo = DotReg ; EndLoc = Lexer . getLoc ( ) ; if ( handleNoncontigiousRegister ( ! NeededWorkaround , StartLoc ) ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } else { RegNo = DotReg ; size_t First = RawString . find ( '.' ) ; StringRef DotString ( RawString . data ( ) + First , RawString . size ( ) - First ) ; Lexer . UnLex ( AsmToken ( AsmToken :: Identifier , DotString ) ) ; EndLoc = Lexer . getLoc ( ) ; if ( handleNoncontigiousRegister ( ! NeededWorkaround , StartLoc ) ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } } std :: pair < StringRef , StringRef > ColonSplit = StringRef ( FullString ) . split ( ':' ) ; unsigned ColonReg = matchRegister ( ColonSplit . first . lower ( ) ) ; if ( ColonReg != <STR_LIT> && RegisterMatchesArch ( DotReg ) ) { do { Lexer . UnLex ( Lookahead . pop_back_val ( ) ) ; } while ( ! Lookahead . empty ( ) && ! Lexer . is ( AsmToken :: Colon ) ) ; RegNo = ColonReg ; EndLoc = Lexer . getLoc ( ) ; if ( handleNoncontigiousRegister ( ! NeededWorkaround , StartLoc ) ) return MatchOperand_NoMatch ; return MatchOperand_Success ; } while ( ! Lookahead . empty ( ) ) { Lexer . UnLex ( Lookahead . pop_back_val ( ) ) ; } return MatchOperand_NoMatch ;


<s> void addHW64RegsAsmOperands ( MCInst & Inst , unsigned N ) const { Inst . addOperand ( MCOperand :: CreateReg ( Reg . RegNum ) ) ;


<s> if ( GetCpuIDAndInfo ( <NUM_LIT> , & EAX , text . u + <NUM_LIT> , text . u + <NUM_LIT> , text . u + <NUM_LIT> ) ) return ; GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) HasCMov = true ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = MMX ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE1 ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE2 ; if ( ECX & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSSE3 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE41 ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) <ISA_LIT>SSELevel = SSE42 ; bool IsIntel = memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; bool IsAMD = ! IsIntel && memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; HasFMA3 = IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ; HasAVX = ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ; HasAES = IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ; if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT> ;

DetectFamilyModel ( EAX , Family , Model ) ;


if ( EnableSROA ) addPass ( createSROAPass ( ) ) ;


<s> if ( Features [ KV . Value ] ) Ret += ( StringRef ( <STR_LIT> ) + KV . Key + <STR_LIT> ) . str ( ) ; else if ( TargetFeatures [ KV . Value ] ) Ret += ( StringRef ( <STR_LIT> ) + KV . Key + <STR_LIT> ) . str ( ) ;


<s> bool usesFPDPRounding ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> case UDIV : if ( TARGET_V850E && optimize_size ) * total = <NUM_LIT> ; else * total = <NUM_LIT> ; return true ; case MULT : if ( TARGET_V850E && ( GET_MODE ( x ) == SImode || GET_MODE ( x ) == HImode || GET_MODE ( x ) == QImode ) ) { if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG ) * total = <NUM_LIT> ; else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { if ( CONST_OK_FOR_O ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) * total = <NUM_LIT> ; else if ( CONST_OK_FOR_K ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) * total = <NUM_LIT> ; }


<s> if ( i == <NUM_LIT> ) return - <NUM_LIT> ; unsigned ShiftAmt = SVOp -> getMaskElt ( i ) ; if ( ShiftAmt < i ) return - <NUM_LIT> ; ShiftAmt -= i ; if ( ! isUnary ) {

for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ShiftAmt + i ) ) return - <NUM_LIT> ;


<s> Branch ( BranchType type , unsigned ccMask , const MachineOperand * target ) : Type ( type ) , CCMask ( ccMask ) , Target ( target ) {


<s> auto <STR_LIT> ( int ElemCount ) const -> Type * { assert ( ElemCount >= <NUM_LIT> ) ; IntegerType * BoolTy = Type :: getInt1Ty ( F . getContext ( ) ) ; if ( ElemCount == <NUM_LIT> ) return BoolTy ; return VectorType :: get ( BoolTy , ElemCount , false ) ;


<s> const OutputRelocSection & <ISA_LIT>GNULDBackend :: getRelaPLT ( ) const {

assert ( m_pRelaPLT != NULL && <STR_LIT> ) ;


<s> void <ISA_LIT>MachineFunctionInfo :: removeDeadFrameIndices ( MachineFrameInfo & MFI ) { for ( auto & R : SGPRToVGPRSpills ) { if ( R . first != FramePointerSaveIndex && R . first != BasePointerSaveIndex ) MFI . RemoveStackObject ( R . first ) ;


<s> unsigned Rn = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecodetGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( tm , * this ) , TM ( tm ) {


<s> unsigned OpReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; warnIfNoMacro ( IDLoc ) ; if ( SrcReg != <STR_LIT> && OpReg != <STR_LIT> ) { TOut . emitRRR ( <STR_LIT> , DstReg , SrcReg , OpReg , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , DstReg , <STR_LIT> , DstReg , IDLoc , STI ) ; return false ;


<s> } else { dbgs ( ) << <STR_LIT> ; for ( int i = <NUM_LIT> ; i < IDLast ; ++ i ) { Available [ i ] -> dump ( ) ; Pending [ i ] -> dump ( ) ; } for ( unsigned i = <NUM_LIT> ; i < DAG -> SUnits . size ( ) ; i ++ ) { const SUnit & S = DAG -> SUnits [ i ] ; if ( ! S . isScheduled ) S . dump ( DAG ) ; }


<s> int <ISA_LIT>BaseInstrInfo :: getOperandLatency ( const InstrItineraryData * ItinData , SDNode * DefNode , unsigned DefIdx , SDNode * UseNode , unsigned UseIdx ) const { if ( ! DefNode -> isMachineOpcode ( ) ) return <NUM_LIT> ; const TargetInstrDesc & DefTID = get ( DefNode -> getMachineOpcode ( ) ) ; if ( isZeroCost ( DefTID . Opcode ) ) return <NUM_LIT> ; if ( ! ItinData || ItinData -> isEmpty ( ) ) return DefTID . mayLoad ( ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! UseNode -> isMachineOpcode ( ) ) { int Latency = ItinData -> getOperandCycle ( DefTID . getSchedClass ( ) , DefIdx ) ; if ( Subtarget . isCortexA9 ( ) ) return Latency <= <NUM_LIT> ? <NUM_LIT> : Latency - <NUM_LIT> ; else return Latency <= <NUM_LIT> ? <NUM_LIT> : Latency - <NUM_LIT> ; } const TargetInstrDesc & UseTID = get ( UseNode -> getMachineOpcode ( ) ) ; const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefTID , DefIdx , DefAlign , UseTID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefTID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ; } } }


<s> static Register buildSamplerLiteral ( uint64_t samplerBitmask , Register res , const <ISA_LIT>Type * samplerTy , MachineIRBuilder & MIRBuilder , <ISA_LIT>GlobalRegistry * GR ) { auto sampler = GR -> buildConstantSampler ( res , getSamplerAddressingModeFromBitmask ( samplerBitmask ) , getSamplerParamFromBitmask ( samplerBitmask ) , getSamplerFilterModeFromBitmask ( samplerBitmask ) , MIRBuilder , samplerTy ) ;


<s> else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;


<s> const char * getPassName ( ) const override { return <STR_LIT> ;


<s> bool SlowPUSHrmm = STI -> isAtom ( ) || STI -> isSLM ( ) ; MachineInstr * DefMov = nullptr ; if ( ! SlowPUSHrmm && ( DefMov = canFoldIntoRegPush ( FrameSetup , Reg ) ) ) { Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) ) ; unsigned NumOps = DefMov -> getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = NumOps - <STR_LIT> ; i != NumOps ; ++ i ) Push -> addOperand ( DefMov -> getOperand ( i ) ) ; DefMov -> eraseFromParent ( ) ; } else { Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Reg ) . getInstr ( ) ; } } if ( ! TFL -> hasFP ( MF ) ) TFL -> BuildCFI ( MBB , std :: next ( Push ) , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , <NUM_LIT> ) ) ; MBB . erase ( MOV ) ;


<s> BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( const unsigned * Reg = ReservedCPURegs ; * Reg ; ++ Reg ) Reserved . set ( * Reg ) ; if ( Subtarget . has<ISA_LIT>64 ( ) ) { for ( const unsigned * Reg = ReservedCPU64Regs ; * Reg ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = <STR_LIT> -> begin ( ) ; Reg != <STR_LIT> -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = <STR_LIT> -> begin ( ) ; Reg != <STR_LIT> -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = <STR_LIT> -> begin ( ) ; Reg != <STR_LIT> -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } return Reserved ;


<s> <ISA_LIT>CA53Erratum843419Stub :: <ISA_LIT>CA53Erratum843419Stub ( const uint32_t * pData , size_t pSize , const char * pName , const_fixup_iterator pBegin , const_fixup_iterator pEnd ) : <ISA_LIT>CA53ErratumStub ( pData , pSize , pName , pBegin , pEnd ) {


<s> unsigned getStackAlignBaseVReg ( ) const {


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const {

return GetRelocTypeInner ( Target , Fixup , IsPCRel , Ctx ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , uint8_t OSABI ) : MCAsmBackend ( ) , OSABI ( OSABI ) {


<s> void emitTBSSSymbol ( MCSection * Section , MCSymbol * Symbol , uint64_t Size , unsigned ByteAlignment = <NUM_LIT> ) override {


<s> if ( write_symbols == DBX_DEBUG ) fprintf ( asm_out_file , <STR_LIT> , ASM_DOUBLE_CHAR ) ;


AU . addRequired < TargetPassConfig > ( ) ;


<s> <ISA_LIT>ompactSelectionDAGInfo :: ~ <ISA_LIT>ompactSelectionDAGInfo ( ) {


<s> MachineInstr * UserMI = U . MI ; MachineInstr * CPEMI = U . CPEMI ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEMI , U . getLongFormMaxDisp ( ) , U . NegOk , true ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; UserMI -> setDesc ( TII -> get ( U . getLongFormOpcode ( ) ) ) ; U . setMaxDisp ( U . getLongFormMaxDisp ( ) ) ; return <NUM_LIT> ; } unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == nullptr ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . getLongFormMaxDisp ( ) , U . NegOk ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( MachineOperand & MO : UserMI -> operands ( ) ) if ( MO . isCPI ( ) ) { MO . setIndex ( CPEs [ i ] . CPI ) ; break ; } CPEs [ i ] . RefCount ++ ; return decrementCPEReferenceCount ( CPI , CPEMI ) ? <NUM_LIT> : <NUM_LIT> ; } } return <NUM_LIT> ;


<s> assert ( & MF . front ( ) == & MBB && <STR_LIT> ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned FPReg = getFPReg ( STI ) ; unsigned SPReg = getSPReg ( STI ) ; DebugLoc DL ; determineFrameLayout ( MF ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - StackSize , MachineInstr :: FrameSetup ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; std :: advance ( MBBI , CSI . size ( ) ) ; if ( hasFP ( MF ) ) adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; const MCRegisterInfo * MRI = MF . getMMI ( ) . getContext ( ) . getRegisterInfo ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; for ( const auto & Entry : CSI ) { unsigned Reg = Entry . getReg ( ) ; int FI = Entry . getFrameIdx ( ) ; CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , MFI . getObjectOffset ( FI ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ;


<s> <STR_LIT> Opc ; SDValue Rdx = DAG . matchBinOpReduction ( ExtElt , Opc , { <STR_LIT> , <STR_LIT> } , true ) ; if ( ! Rdx ) return SDValue ( ) ; SDValue Index = ExtElt -> getOperand ( <NUM_LIT> ) ; assert ( isNullConstant ( Index ) && <STR_LIT> ) ; EVT VT = ExtElt -> getValueType ( <NUM_LIT> ) ; EVT VecVT = Rdx . getValueType ( ) ; if ( VecVT . getScalarType ( ) != VT ) return SDValue ( ) ; SDLoc DL ( ExtElt ) ; if ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) { if ( VecVT == <STR_LIT> ) { if ( Subtarget . hasSSE41 ( ) ) { Rdx = DAG . getBitcast ( <STR_LIT> , Rdx ) ; Rdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Rdx , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; Rdx = DAG . getBitcast ( <STR_LIT> , Rdx ) ; } else { Rdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Rdx , DAG . getConstant ( <NUM_LIT> , DL , VecVT ) ) ; } } if ( Rdx . getValueType ( ) == <STR_LIT> ) { Rdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Rdx , DAG . getUNDEF ( <STR_LIT> ) ) ; } Rdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Rdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Rdx = DAG . getBitcast ( <STR_LIT> , Rdx ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Rdx , Index ) ; } if ( ( VecVT . getSizeInBits ( ) % <NUM_LIT> ) != <NUM_LIT> || ! isPowerOf2_32 ( VecVT . getVectorNumElements ( ) ) ) return SDValue ( ) ; if ( VT == <STR_LIT> ) { while ( Rdx . getValueSizeInBits ( ) > <NUM_LIT> ) { unsigned HalfSize = VecVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned HalfElts = VecVT . getVectorNumElements ( ) / <NUM_LIT> ; SDValue Lo = extractSubVector ( Rdx , <NUM_LIT> , DAG , DL , HalfSize ) ; SDValue Hi = extractSubVector ( Rdx , HalfElts , DAG , DL , HalfSize ) ; Rdx = DAG . getNode ( <STR_LIT> , DL , Lo . getValueType ( ) , Lo , Hi ) ; VecVT = Rdx . getValueType ( ) ;


<s> { MO_ABS_HI , <STR_LIT> } , { MO_ABS_LO , <STR_LIT> } , } ;


<s> int RAOffset = <ISA_LIT>FI -> getRAStackOffset ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; if ( isPIC && STI . isABI_O32 ( ) ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( RegInfo -> getPICCallReg ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; ATUsed = expandRegLargeImmPair ( <STR_LIT> , - StackSize , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( NewReg ) . addImm ( NewImm ) ; if ( ATUsed ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; if ( MFI -> adjustsStack ( ) ) { expandRegLargeImmPair ( <STR_LIT> , RAOffset , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( NewImm ) . addReg ( NewReg ) ; if ( ATUsed ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; } if ( hasFP ( MF ) ) { expandRegLargeImmPair ( <STR_LIT> , FPOffset , NewReg , NewImm , MBB , MBBI ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( NewImm ) . addReg ( NewReg ) ; if ( ATUsed ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) ) if ( auto * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) if ( C -> getAPIntValue ( ) . isOneValue ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Src . getOperand ( <NUM_LIT> ) ) ;

if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) if ( auto * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) if ( C -> isNullValue ( ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ;


<s> switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'b' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' :

if ( type -> isFloatTy ( ) ) weight = CW_Register ;


<s> int i , j ; if ( tie_operand ( pat , VOIDmode ) ) return false ; if ( GET_CODE ( pat ) == MEM ) { * mem_ref = pat ; return true ; } fmt = GET_RTX_FORMAT ( GET_CODE ( pat ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( pat ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'e' ) { if ( find_mem_ref ( XEXP ( pat , i ) , mem_ref ) ) return true ;


<s> } else if ( Inst . getOpcode ( ) == <STR_LIT> ) { unsigned Rm = fieldFromInstruction16 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } return S ;


<s> for ( unsigned i = <NUM_LIT> ; i < loop -> num_nodes ; i ++ ) { bb = body [ i ] ; FOR_BB_INSNS ( bb , insn ) { rtx base = NULL_RTX ; rtx dest = NULL_RTX ; rtx offset = NULL_RTX ; bool writeback = false ; bool ldp = false ; if ( ! INSN_P ( insn ) || DEBUG_INSN_P ( insn ) ) continue ; if ( get_load_info ( insn , loop , & dest , & base , & offset , & writeback , & ldp ) ) { tag_insn_info * i = new tag_insn_info ( insn , dest , base , offset , writeback , ldp ) ; rtx tag = GEN_INT ( i -> tag ( ) ) ; tag_map . get_or_insert ( tag ) . safe_push ( i ) ; } } } if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , loop -> num ) ; tag_map . traverse < void * , dump_insn_list > ( NULL ) ; }

tag_map . traverse < void * , single_dest_per_chain > ( NULL ) ;


<s> MachineFunctionPass ( ID ) , TRI ( nullptr ) , TII ( nullptr ) , SkipThreshold ( <NUM_LIT> ) {


<s> if ( type == <NUM_LIT> && ( align & <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; return load ? DecodeVLDInstruction ( Inst , Insn , Address , Decoder ) : DecodeVSTInstruction ( Inst , Insn , Address , Decoder ) ;


<s> unsigned XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; std :: vector < SDValue > OutChains ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; analyzeInputArgs ( MF , CCInfo , Ins , false ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . getLocVT ( ) == XLenVT && <STR_LIT> ) ; SDValue ArgValue ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) ArgValue = unpackF64OnRV32DSoftABI ( DAG , Chain , VA , DL ) ; else if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) { InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ) ; unsigned ArgIndex = Ins [ i ] . OrigArgIndex ; assert ( Ins [ i ] . PartOffset == <NUM_LIT> ) ; while ( i + <NUM_LIT> != e && Ins [ i + <NUM_LIT> ] . OrigArgIndex == ArgIndex ) { CCValAssign & PartVA = ArgLocs [ i + <NUM_LIT> ] ; unsigned PartOffset = Ins [ i + <NUM_LIT> ] . PartOffset ; SDValue Address = DAG . getNode ( <STR_LIT> , DL , PtrVT , ArgValue , DAG . getIntPtrConstant ( PartOffset , DL ) ) ; InVals . push_back ( DAG . getLoad ( PartVA . getValVT ( ) , DL , Chain , Address , MachinePointerInfo ( ) ) ) ; ++ i ; } continue ; } InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( ArgGPRs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; RVFI -> setVarArgsFrameIndex ( FI ) ; if ( Idx % <NUM_LIT> ) { FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset - ( int ) XLenInBytes , true ) ;


<s> } bool Recorded = false ; for ( iterator I = AVs . begin ( ) , E = AVs . end ( ) ; I != E ; ++ I ) { unsigned SrcR = * I ; int FDi = - <NUM_LIT> , LDi = - <NUM_LIT> ; const BitTracker :: RegisterCell & AC = CMS -> lookup ( SrcR ) ; uint16_t AW = AC . width ( ) ; for ( uint16_t i = <NUM_LIT> , w = std :: min ( W , AW ) ; i < w ; ++ i ) { if ( RC [ i ] == AC [ i ] ) continue ; if ( FDi == - <NUM_LIT> ) FDi = i ; LDi = i ; } if ( FDi == - <NUM_LIT> ) continue ; uint16_t FD = FDi , LD = LDi ; uint16_t MinL = LD - FD + <NUM_LIT> ; for ( uint16_t L = MinL ; L < W ; ++ L ) { LRSMapType :: iterator F = LM . find ( L ) ; if ( F == LM . end ( ) ) continue ; RSListType & LL = F -> second ; for ( unsigned i = <NUM_LIT> , n = LL . size ( ) ; i < n ; ++ i ) { uint16_t S = LL [ i ] . second ; if ( S > FD ) continue ; uint16_t EL = L - MinL ; uint16_t LowS = ( EL < FD ) ? FD - EL : <NUM_LIT> ; if ( S < LowS ) continue ; unsigned InsR = LL [ i ] . first ; if ( ! isValidInsertForm ( VR , SrcR , InsR , L , S ) ) continue ; if ( isDebug ( ) ) {

dbgs ( ) << PrintReg ( VR , HRI ) << <STR_LIT> << PrintReg ( SrcR , HRI ) << ',' << PrintReg ( InsR , HRI ) << <STR_LIT> << L << <STR_LIT> << S << <STR_LIT> ;


<s> if ( D_REGNO_P ( regno ) ) { bool is_eh_return_reg = false ; if ( crtl -> calls_eh_return ) { unsigned j ; for ( j = <NUM_LIT> ; ; j ++ ) { unsigned test = EH_RETURN_DATA_REGNO ( j ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) is_eh_return_reg = true ; } } return ( is_eh_return_reg || ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ( is_inthandler || ! call_used_regs [ regno ] ) ) ) ; } else if ( P_REGNO_P ( regno ) ) { return ( ( df_regs_ever_live_p ( regno ) && ! fixed_regs [ regno ] && ( is_inthandler || ! call_used_regs [ regno ] ) ) || ( is_inthandler && ( ENABLE_WA_05000283 || ENABLE_WA_05000315 ) && regno == REG_P5 ) || ( ! TARGET_FDPIC && regno == PIC_OFFSET_TABLE_REGNUM && ( crtl -> uses_pic_offset_table || ( TARGET_ID_SHARED_LIBRARY && ! crtl -> is_leaf ) ) ) ) ; } else return ( ( is_inthandler || ! call_used_regs [ regno ] ) && ( df_regs_ever_live_p ( regno ) || ( ! leaf_function_p ( ) && call_used_regs [ regno ] ) ) ) ;


<s> if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return MaterializeSETB ( DL , NewEFLAGS , DAG , N -> getSimpleValueType ( <NUM_LIT> ) ) ; } } if ( CC == <STR_LIT> ) return MaterializeSETB ( DL , EFLAGS , DAG , N -> getSimpleValueType ( <NUM_LIT> ) ) ; SDValue Flags ; Flags = checkBoolTestSetCCCombine ( EFLAGS , CC ) ; if ( Flags . getNode ( ) ) { SDValue Cond = DAG . getConstant ( CC , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , Cond , Flags ) ; } return SDValue ( ) ;


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) O << TM . getRegisterInfo ( ) -> get ( MO . getReg ( ) ) . AsmName ; else assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) ) ; break ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; O << Mang -> getValueName ( GV ) ; if ( GV -> hasExternalWeakLinkage ( ) ) ExtWeakSymbols . insert ( GV ) ; } break ; case MachineOperand :: MO_ExternalSymbol : O << MO . getSymbolName ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; default : assert ( <NUM_LIT> && <STR_LIT> ) ; }


<s> BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; } } BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlags ( MachineInstr :: FrameSetup ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> int nregs ; rtx result ; rtvec rtvec ; for ( nregs = <NUM_LIT> ; size > <NUM_LIT> ; size -= UNITS_PER_WORD ) { arg_regs [ nregs ] = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , reg ++ ) , GEN_INT ( nregs * UNITS_PER_WORD ) ) ; nregs ++ ; } assert ( ARRAY_SIZE ( arg_regs ) == <NUM_LIT> ) ; rtvec = gen_rtvec ( nregs , arg_regs [ <NUM_LIT> ] , arg_regs [ <NUM_LIT> ] , arg_regs [ <NUM_LIT> ] , arg_regs [ <NUM_LIT> ] , arg_regs [ <NUM_LIT> ] , arg_regs [ <NUM_LIT> ] ) ; result = gen_rtx_PARALLEL ( mode , rtvec ) ; return result ; } return gen_rtx_REG ( mode , reg ) ;


<s> SDValue Low = Value ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue StoreLow = DAG . getTruncStore ( Chain , dl , Low , BasePtr , ST -> getPointerInfo ( ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue StoreHigh = DAG . getTruncStore ( Chain , dl , High , HighAddr , ST -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , ST -> isVolatile ( ) , ST -> isNonTemporal ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreLow , StoreHigh ) ; } Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = BasePtr ; Args . push_back ( Entry ) ; Entry . Node = Value ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ;


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ;

AU . addRequired < MachineLoopInfo > ( ) ;


<s> addPass ( create<ISA_LIT>DelaySlotFillerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return true ;


<s> bool isVK8Pair ( ) const { return Kind == Register && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( getReg ( ) ) ;


<s> case <NUM_LIT> : Imm = <NUM_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ; }


<s> bool <ISA_LIT>PacketizerList :: isLegalToPruneDependencies ( SUnit * SUI , SUnit * SUJ ) { assert ( SUI -> getInstr ( ) && SUJ -> getInstr ( ) ) ; MachineInstr & I = * SUI -> getInstr ( ) ; MachineInstr & J = * SUJ -> getInstr ( ) ; bool Coexist = ! cannotCoexist ( I , J ) ; if ( Coexist && ! Dependence ) return true ; if ( PromotedToDotNew ) demoteToDotOld ( I ) ; cleanUpDotCur ( ) ; if ( GlueAllocframeStore ) { useCalleesSP ( I ) ; GlueAllocframeStore = false ; } return false ;


<s> static const char * getRegisterName ( unsigned RegNo ) {

return <ISA_LIT>InstPrinter :: getRegisterName ( RegNo ) ;


<s> return isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( N ) -> getSExtValue ( ) ) ;


<s> const TargetInstrInfo * TII = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getRegisterInfo ( ) ; string target = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; string source = TRI -> getName ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; SExpr * load = ctx -> load ( <NUM_LIT> , source ) ; SExpr * stor = ctx -> store ( ctx -> address ( target ) , load ) ;

alfbb . addStatement ( label , TII -> getName ( MI . getOpcode ( ) ) , stor ) ;


<s> if ( C -> getOpcode ( ) != <STR_LIT> ) return false ; <STR_LIT> IntExt ; switch ( cast < ConstantSDNode > ( C -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : IntExt = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : IntExt = <STR_LIT> ; break ; default : IntExt = <STR_LIT> ; break ; } if ( N -> getExtensionType ( ) != IntExt ) return false ; if ( C -> getNumOperands ( ) < <NUM_LIT> || Loc . getNode ( ) != C -> getOperand ( <NUM_LIT> ) . getNode ( ) ) return false ; if ( MachineSDNode * L = LoadInstrForLoadIntrinsic ( C ) ) { SDNode * S = StoreInstrForLoadIntrinsic ( L , C ) ; SDValue F [ ] = { SDValue ( N , <NUM_LIT> ) , SDValue ( N , <NUM_LIT> ) , SDValue ( C , <NUM_LIT> ) , SDValue ( C , <NUM_LIT> ) } ; SDValue T [ ] = { SDValue ( L , <NUM_LIT> ) , SDValue ( S , <NUM_LIT> ) , SDValue ( L , <NUM_LIT> ) , SDValue ( S , <NUM_LIT> ) } ; ReplaceUses ( F , T , array_lengthof ( T ) ) ;


<s> assert ( isRegShiftedImm ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( RegShiftedImm . SrcReg ) ) ;

unsigned Imm = ( RegShiftedImm . ShiftImm == <NUM_LIT> ? <NUM_LIT> : RegShiftedImm . ShiftImm ) ;


<s> MVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( isAsynchronousEHPersonality ( classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ) ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Dest ) ; } unsigned ReturnReg = ( PtrVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock * DestMBB = cast < BasicBlockSDNode > ( Dest ) -> getBasicBlock ( ) ; BlockAddress * BA = BlockAddress :: get ( const_cast < Function * > ( MF . getFunction ( ) ) , const_cast < BasicBlock * > ( DestMBB -> getBasicBlock ( ) ) ) ; DestMBB -> setHasAddressTaken ( ) ;

SDValue BlockPtr = DAG . getBlockAddress ( BA , PtrVT ) ;


<s> return dyn_cast < llvm :: ConstantInt > ( val ) -> getZExtValue ( ) ;


<s> SpillCostAnalysisGraph ( const <ISA_LIT>Subtarget & s ) : STC ( s ) , yamlId ( <NUM_LIT> ) {


<s> bool OptSize = Attr . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: MinSize ) ; return OptSize && ! VT . isVector ( ) ;


<s> const MCSymbolRefExpr * SRE = cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_PCREL && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( IsLittleEndian ? <NUM_LIT> : <NUM_LIT> , Expr , static_cast < MCFixupKind > ( <STR_LIT> ) ) ) ; return <NUM_LIT> ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEB32 ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) {

return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( ) , false , false ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , computeDataLayout ( TT , is64bit ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this , is64bit ) , is64Bit ( is64bit ) { initAsmInfo ( ) ;


<s> MCStreamer & S = getParser ( ) . getStreamer ( ) ; if ( S . getTargetStreamer ( ) == nullptr ) new <ISA_LIT>TargetStreamer ( S ) ;

setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> RefinementSteps = <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , SDLoc ( Operand ) , VT , Operand ) ; } return SDValue ( ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TargetTriple , StringRef Cpu , StringRef FeatureString , const TargetMachine & TM , const TargetOptions & , CodeModel :: Model , CodeGenOpt :: Level ) : <ISA_LIT>GenSubtargetInfo ( TargetTriple , Cpu , FeatureString ) , FrameLowering ( initializeSubtargetDependencies ( Cpu , FeatureString ) ) , InstrInfo ( ) , TLInfo ( TM , * this ) , TSInfo ( ) {


<s> rtx reg = XEXP ( src , <NUM_LIT> ) ; rtx prev_dest = SET_DEST ( prev_set ) ; rtx prev_src = SET_SRC ( prev_set ) ; bool src_same = rtx_equal_p ( prev_src , reg ) ; if ( REG_P ( prev_dest ) && ! reg_set_p ( reg , prev_src ) && ! reg_set_between_p ( reg , prev_cc_outer , outer_insn ) && ( src_same || rtx_equal_p ( prev_dest , reg ) ) ) { machine_mode ccmode = GET_MODE ( src ) ; rtx modeadjusted_dccr = ( ccmode == CCmode ? dccr : gen_rtx_REG ( CCmode , CRIS_CC0_REGNUM ) ) ; rtx compare = ( src_same ? pat : gen_rtx_SET ( modeadjusted_dccr , gen_rtx_COMPARE ( ccmode , copy_rtx ( prev_src ) , const0_rtx ) ) ) ;

validate_change ( prev_cc_setter , & XVECEXP ( PATTERN ( prev_cc_setter ) , <NUM_LIT> , <NUM_LIT> ) , compare , true ) ;


<s> assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; unsigned Cost = LT . first * <NUM_LIT> ; unsigned SrcBytes = LT . second . getStoreSize ( ) ; if ( SrcBytes && Alignment && Alignment < SrcBytes ) Cost *= ( SrcBytes / Alignment ) ;


<s> return ! IN_RANGE ( int_size_in_bytes ( type ) , <NUM_LIT> , TILEPRO_NUM_RETURN_REGS * UNITS_PER_WORD ) ;


<s> static bool classof ( const MCExpr * E ) {

return E -> getKind ( ) == MCExpr :: Target ;


<s> addend += pc_len ; avr_asm_len ( <STR_LIT> , op , plen , <NUM_LIT> ) ; } while ( addend ++ < <NUM_LIT> ) avr_asm_len ( <STR_LIT> , op , plen , <NUM_LIT> ) ; } else if ( addend > <NUM_LIT> ) { if ( flag_verbose_asm || flag_print_asm_name ) avr_asm_len ( ASM_COMMENT_START <STR_LIT> , op , plen , <NUM_LIT> ) ; while ( addend -- > <NUM_LIT> ) avr_asm_len ( <STR_LIT> , op , plen , <NUM_LIT> ) ; } return <STR_LIT> ;


<s> return __builtin_mve_vshlltq_n_uv8hi ( __a , __imm ) ;


<s> <ISA_LIT>To<ISA_LIT>Stub :: <ISA_LIT>To<ISA_LIT>Stub ( const uint32_t * pData , size_t pSize , const_fixup_iterator pBegin , const_fixup_iterator pEnd ) : m_pData ( pData ) , m_Name ( <STR_LIT> ) , m_Size ( pSize ) {

for ( const_fixup_iterator it = pBegin , ie = pEnd ; it != ie ; ++ it ) addFixup ( * * it ) ;


<s> } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; findRedundantLoads ( ) ; count += remove ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; count += remove ( ) ; return count ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ;

TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;


<s> emit_insn ( gen_subhi3 ( xval , virtual_stack_vars_rtx , gen_int_mode ( avr_starting_frame_offset ( ) , Pmode ) ) ) ; return xval ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( ScratchExecCopy ) ; } unsigned StackPtrReg = FuncInfo -> getStackPtrOffsetReg ( ) ; if ( StackPtrReg == <STR_LIT> ) return ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; uint32_t NumBytes = MFI . getStackSize ( ) ; if ( NumBytes != <NUM_LIT> && hasSP ( MF ) ) { uint32_t RoundedSize = FuncInfo -> isStackRealigned ( ) ? NumBytes + MFI . getMaxAlignment ( ) : NumBytes ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( RoundedSize * ST . getWavefrontSize ( ) ) ;


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; float FPImm = MO . isDFPImm ( ) ? bit_cast < double > ( MO . getDFPImm ( ) ) : <STR_LIT> ( MO . getImm ( ) ) ;


<s> if ( crtl -> calls_eh_return && regno == MB_ABI_SUB_RETURN_ADDR_REGNUM ) return <NUM_LIT> ; if ( ! crtl -> is_leaf ) { if ( regno == MB_ABI_SUB_RETURN_ADDR_REGNUM ) return <NUM_LIT> ; if ( ( microblaze_is_interrupt_variant ( ) || save_volatiles ) && ( regno >= <NUM_LIT> && regno <= <NUM_LIT> ) ) return <NUM_LIT> ; }

if ( microblaze_is_interrupt_variant ( ) ) {


<s> const TargetRegisterClass * RC = TRI . getMinimalPhysRegClass ( Reg ) ; unsigned BytesPerReg = TRI . getRegSizeInBits ( * RC ) / <NUM_LIT> ; assert ( BytesPerReg <= <NUM_LIT> && <STR_LIT> ) ; unsigned RegIdx = ByteNumber / BytesPerReg ; assert ( RegIdx < NumOpRegs && <STR_LIT> ) ; Reg = MI -> getOperand ( OpNum + RegIdx ) . getReg ( ) ; if ( BytesPerReg == <NUM_LIT> ) { Reg = TRI . getSubReg ( Reg , ByteNumber % BytesPerReg ? <STR_LIT> : <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getPrettyRegisterName ( Reg , MRI ) ; return false ; } }

if ( Error ) printOperand ( MI , OpNum , O ) ;


<s> } break ; case <STR_LIT> : case <STR_LIT> : needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { const TargetRegisterClass * RC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: z80 , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> return ( __m64 ) __builtin_arm_wqmulwmr ( ( __v2si ) a , ( __v2si ) b ) ;


<s> Value * <ISA_LIT>IREmitter :: visitCMPP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectADDRsi64 ( SDNode * OpNode , SDValue Addr , SDValue & Base , SDValue & Offset ) {

return SelectADDRsi_imp ( OpNode , Addr , Base , Offset , <STR_LIT> ) ;


<s> Kind = MCSymbolRefExpr :: VK_WASM_TLSREL ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_WASM_TBREL ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , Kind , Ctx ) ; if ( MO . getOffset ( ) != <NUM_LIT> ) { const auto * WasmSym = cast < MCSymbolWasm > ( Sym ) ; if ( TargetFlags == <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ;

if ( WasmSym -> isFunction ( ) ) report_fatal_error ( <STR_LIT> ) ;


<s> return ( uint16x8_t ) __builtin_neon_vcgev8hf ( __a , __b ) ;


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { assert ( Size == <NUM_LIT> && <STR_LIT> ) ; auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , Size , <NUM_LIT> ) ;

MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ;


<s> static rtx arc_dwarf_register_span ( rtx rtl ) { machine_mode mode = GET_MODE ( rtl ) ; unsigned regno ; rtx p ; if ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) return NULL_RTX ; p = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ;


<s> } } if ( ! checkType ( N -> getSrcValue ( ) , <STR_LIT> ) && ! checkType ( N -> getSrcValue ( ) , <STR_LIT> ) && ! checkType ( N -> getSrcValue ( ) , <STR_LIT> ) && ! checkType ( N -> getSrcValue ( ) , <STR_LIT> ) && ! checkType ( N -> getSrcValue ( ) , <STR_LIT> ) && ! checkType ( N -> getSrcValue ( ) , <STR_LIT> ) ) {


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( - <NUM_LIT> , - <NUM_LIT> ) , RI ( ) , ST ( ST ) {


<s> unsigned Opc = MI -> getOpcode ( ) ;

if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return <STR_LIT> ;


<s> if ( Op . isImm ( ) ) O << ( int ) Op . getImm ( ) ; else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << * Op . getExpr ( ) ; }


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> BitTracker :: BitTracker ( const MachineEvaluator & E , MachineFunction & F ) : ME ( E ) , MF ( F ) , MRI ( F . getRegInfo ( ) ) , Map ( * new CellMapType ) , Trace ( false ) {


<s> EVT PtrTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( DataVT . isFloatingPoint ( ) ) Data = DAG . getNode ( <STR_LIT> , DL , DataVT . changeTypeToInteger ( ) , Data ) ; auto * MINode = cast < MemIntrinsicSDNode > ( N ) ;

return DAG . getMaskedStore ( MINode -> getChain ( ) , DL , Data , MINode -> getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( PtrTy ) , MINode -> getOperand ( <NUM_LIT> ) , MINode -> getMemoryVT ( ) , MINode -> getMemOperand ( ) , <STR_LIT> , false , false ) ;


<s> void riscv_expand_conditional_branch ( rtx label , rtx_code code , rtx op0 , rtx op1 ) { if ( FLOAT_MODE_P ( GET_MODE ( op1 ) ) ) riscv_emit_float_compare ( & code , & op0 , & op1 ) ; else riscv_emit_int_compare ( & code , & op0 , & op1 ) ; rtx condition = gen_rtx_fmt_ee ( code , VOIDmode , op0 , op1 ) ;

emit_jump_insn ( gen_condjump ( condition , label ) ) ;


<s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & ) {


<s> static rtx riscv_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { rtx addr ; if ( riscv_tls_symbol_p ( x ) ) return riscv_legitimize_tls_address ( x ) ;

if ( riscv_split_symbol ( NULL , x , mode , & addr ) ) return riscv_force_address ( addr , mode ) ;


<s> void <ISA_LIT>InstPrinter :: printComplexRotationOp ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ;

O << <STR_LIT> << ( Val * Angle ) + Remainder ;


<s> assert ( EVT :: getEVT ( SI -> getType ( ) ) == ( EVT :: getEVT ( I -> getType ( ) ) ) ) ; ++ UI ; I -> replaceAllUsesWith ( SI ) ; Instruction * First = F . getEntryBlock ( ) . begin ( ) ; SI -> insertBefore ( First ) ; I -> eraseFromParent ( ) ; } else {


<s> } for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno >= <NUM_LIT> ; regno -- ) if ( REG_NEEDS_SAVE ( regno , ifun ) ) { rtx dwarf ; insn = emit_move_insn ( gen_rtx_REG ( HImode , regno ) , mem_pop_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; dwarf = gen_rtx_SET ( Pmode , stack_pointer_rtx , plus_constant ( stack_pointer_rtx , - GET_MODE_SIZE ( Pmode ) ) ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf , REG_NOTES ( insn ) ) ; } if ( layout . stdarg_save_size ) {

insn = emit_addhi3_postreload ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - layout . stdarg_save_size ) ) ;


<s> if ( ! GV -> hasInitializer ( ) || EmitSpecialLLVMGlobal ( GV ) ) return ; const TargetData * TD = TM . getTargetData ( ) ; OutStreamer . SwitchSection ( getObjFileLowering ( ) . SectionForGlobal ( GV , Mang , TM ) ) ; MCSymbol * GVSym = GetGlobalValueSymbol ( GV ) ; Constant * C = GV -> getInitializer ( ) ; unsigned Align = ( unsigned ) TD -> getPreferredTypeAlignmentShift ( C -> getType ( ) ) ; O << <STR_LIT> << * GVSym << <STR_LIT> << * GVSym << <STR_LIT> ; switch ( GV -> getLinkage ( ) ) { case GlobalValue :: AppendingLinkage :


<s> else { const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; int NewOpcode = GetDotNewOp ( MI -> getOpcode ( ) ) ; const MCInstrDesc & desc = QII -> get ( NewOpcode ) ; DebugLoc dl ; MachineInstr * NewMI = MI -> getParent ( ) -> getParent ( ) -> CreateMachineInstr ( desc , dl ) ; bool ResourcesAvailable = ResourceTracker -> canReserveResources ( NewMI ) ; MI -> getParent ( ) -> getParent ( ) -> DeleteMachineInstr ( NewMI ) ; if ( ! ResourcesAvailable ) return false ; if ( ! CanPromoteToNewValue ( MI , PacketSU , DepReg , MIToSUnit , MII ) ) {


<s> assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; unsigned RegOpNum = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; unsigned BaseRegNum = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isImmOpnd ) { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; ImmOffset = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; LoOffset = ImmOffset & <NUM_LIT> ; HiOffset = ( ImmOffset & <NUM_LIT> ) >> <NUM_LIT> ; if ( LoOffset & <NUM_LIT> ) HiOffset ++ ; } else ExprOffset = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; TempInst . setLoc ( IDLoc ) ; TmpRegNum = ( isLoad && ( BaseRegNum != RegOpNum ) ) ? RegOpNum : AtRegNum ; TempInst . setOpcode ( <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; if ( isImmOpnd ) TempInst . addOperand ( MCOperand :: CreateImm ( HiOffset ) ) ; else { if ( ExprOffset -> getKind ( ) == MCExpr :: SymbolRef ) { SR = static_cast < const MCSymbolRefExpr * > ( ExprOffset ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( SR -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , getContext ( ) ) ; TempInst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; } else { const MCExpr * HiExpr = evaluateRelocExpr ( ExprOffset , <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; } } Instructions . push_back ( TempInst ) ; TempInst . clear ( ) ; TempInst . setOpcode ( <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; TempInst . addOperand ( MCOperand :: CreateReg ( BaseRegNum ) ) ; Instructions . push_back ( TempInst ) ;


<s> MachineIRBuilder & Builder = Helper . MIRBuilder ; Helper . Observer . changingInstr ( MI ) ; for ( unsigned I = <NUM_LIT> , IE = MI . getNumOperands ( ) ; I < IE ; I += <NUM_LIT> ) { Register Reg = MI . getOperand ( I ) . getReg ( ) ; MachineBasicBlock * Block = MI . getOperand ( I + <NUM_LIT> ) . getMBB ( ) ; Builder . setInsertPt ( * Block , Block -> getFirstTerminator ( ) ) ; MI . getOperand ( I ) . setReg ( Builder . buildPtrToInt ( S16 , Reg ) . getReg ( <NUM_LIT> ) ) ; } Register Tmp = MRI . createGenericVirtualRegister ( S16 ) ;

Builder . setInsertPt ( * MI . getParent ( ) , MI . getParent ( ) -> getFirstNonPHI ( ) ) ;


<s> return MO . getSubReg ( ) == <NUM_LIT> ? MRI . getMaxLaneMaskForVReg ( MO . getReg ( ) ) :

MRI . getTargetRegisterInfo ( ) -> getSubRegIndexLaneMask ( MO . getSubReg ( ) ) ;


<s> return <STR_LIT> ; } else if ( STI . hasAVX ( ) ) { return <STR_LIT> ; } else if ( STI . hasSSE2 ( ) ) { return <STR_LIT> ; } } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { if ( ( STI . hasAVX512 ( ) ) && ( STI . hasVLX ( ) ) ) { return <STR_LIT> ; } else if ( STI . hasAVX ( ) ) {


<s> if ( ! isGPRMem ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ; if ( ! Memory . OffsetImm ) return true ;

if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) {


<s> emitRX ( Opcode , Reg0 , MCOperand :: createImm ( Imm ) , IDLoc , Instructions ) ;


<s> Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } else { Constant * C = ConstantFP :: get ( * Context , APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; if ( VT . isVector ( ) ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mask ) ) ) ;


<s> bool isGCN3Encoding ( const MCSubtargetInfo & STI ) {

return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> void <ISA_LIT>ScheduleBlock :: initRegPressure ( MachineBasicBlock :: iterator BeginBlock , MachineBasicBlock :: iterator EndBlock ) { IntervalPressure Pressure , BotPressure ; RegPressureTracker RPTracker ( Pressure ) , BotRPTracker ( BotPressure ) ; LiveIntervals * LIS = DAG -> getLIS ( ) ; MachineRegisterInfo * MRI = DAG -> getMRI ( ) ; DAG -> initRPTracker ( TopRPTracker ) ; DAG -> initRPTracker ( BotRPTracker ) ; DAG -> initRPTracker ( RPTracker ) ; for ( SUnit * SU : ScheduledSUnits ) { RPTracker . setPos ( SU -> getInstr ( ) ) ; RPTracker . advance ( ) ; } RPTracker . closeRegion ( ) ;

TopRPTracker . addLiveRegs ( RPTracker . getPressure ( ) . LiveInRegs ) ;


<s> if ( GV -> isThreadLocal ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( GV -> hasSection ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( GV -> hasComdat ( ) ) report_fatal_error ( <STR_LIT> ) ;


<s> else { return false ; } SmallVectorImpl < CCValAssign > & PendingMembers = State . getPendingLocs ( ) ; PendingMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ! ArgFlags . isInConsecutiveRegsLast ( ) ) return true ; unsigned RegResult = State . AllocateRegBlock ( RegList , PendingMembers . size ( ) ) ; if ( RegResult ) { for ( auto & It : PendingMembers ) { It . convertToReg ( RegResult ) ;


<s> bool <ISA_LIT>_MC :: isCPSRDefined ( const MCInst & MI , const MCInstrInfo * MCII ) { const MCInstrDesc & Desc = MCII -> get ( MI . getOpcode ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) { const MCOperand & MO = MI . getOperand ( I ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> && Desc . OpInfo [ I ] . isOptionalDef ( ) ) return true ;


<s> } for ( int i = MFI . getObjectIndexBegin ( ) , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) if ( i != FramePointerSaveIndex ) MFI . setStackID ( i , TargetStackID :: Default ) ;


<s> unsigned Tile64InstrInfo :: isStoreToStackSlot ( const MachineInstr * MI , int & FrameIndex ) const {


<s> rtx ( * gen_shift ) ( rtx , rtx , rtx ) ; rtx ( * gen_and ) ( rtx , rtx , rtx ) ; rtx ( * gen_xor ) ( rtx , rtx , rtx ) ; rtx ( * gen_sub ) ( rtx , rtx , rtx ) ; if ( ! CONST_INT_P ( op2 ) ) return false ; qimode = GET_MODE ( dest ) ; shift_amount = INTVAL ( op2 ) ; if ( shift_amount > <NUM_LIT> ) return false ; gcc_assert ( code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT ) ; xor_constant = <NUM_LIT> << ( <NUM_LIT> - shift_amount - <NUM_LIT> ) ; and_constant = ( code == ASHIFT ? <NUM_LIT> - ( <NUM_LIT> << shift_amount ) : ( <NUM_LIT> << ( <NUM_LIT> - shift_amount ) ) - <NUM_LIT> ) ; switch ( qimode ) { case V16QImode : himode = V8HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv8hi3 : ( code == ASHIFTRT ) ? gen_ashrv8hi3 : gen_lshrv8hi3 ) ; gen_and = gen_andv16qi3 ; gen_xor = gen_xorv16qi3 ; gen_sub = gen_subv16qi3 ; break ; case V32QImode : himode = V16HImode ; gen_shift = ( ( code == ASHIFT ) ? gen_ashlv16hi3 : ( code == ASHIFTRT ) ? gen_ashrv16hi3 : gen_lshrv16hi3 ) ; gen_and = gen_andv32qi3 ; gen_xor = gen_xorv32qi3 ; gen_sub = gen_subv32qi3 ; break ; case V64QImode :


<s> SDLoc dl ( N ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ;

return DCI . DAG . getNode ( <STR_LIT> , dl , Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) , Op -> getOperand ( <NUM_LIT> ) ) ;


<s> ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( Flags . isByVal ( ) ) { assert ( ( j < ByValArgLocs . size ( ) ) && <STR_LIT> ) ; CCValAssign & ByValVA = ByValArgLocs [ j ++ ] ; assert ( ( VA . getValNo ( ) == ByValVA . getValNo ( ) ) && <STR_LIT> ) ; unsigned LocMemOffset = ByValVA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; SDValue MemcpyCall = CreateCopyOfByValArgument ( Arg , PtrOff , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , Flags , DAG , dl ) ; SDValue NewCallSeqStart = DAG . getCALLSEQ_START ( MemcpyCall , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesWith ( CallSeqStart . getNode ( ) , NewCallSeqStart . getNode ( ) ) ; Chain = CallSeqStart = NewCallSeqStart ; Arg = PtrOff ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned LocMemOffset = VA . getLocMemOffset ( ) ; if ( ! isTailCall ) { SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } else { CalculateTailCallArgDest ( DAG , MF , false , Arg , SPDiff , LocMemOffset , TailCallArguments ) ; } } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) {

Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ;


<s> getActionDefinitionsBuilder ( G_PHI ) . legalFor ( { p0 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_GLOBAL_VALUE ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( G_FCONSTANT ) . legalFor ( { s32 , s64 } ) ; getActionDefinitionsBuilder ( { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) . legalFor ( { s32 , s64 } ) ; computeTables ( ) ; verify ( * ST . getInstrInfo ( ) ) ;


<s> unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 ) ;

if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D2 ) ;


<s> else if ( isVSplat ( Op1Op1 , InvMask , IsLittleEndian ) && Mask . getBitWidth ( ) == InvMask . getBitWidth ( ) && Mask == ~ InvMask ) IfClr = Op1Op0 ; IsConstantMask = true ; } if ( ! IfClr . getNode ( ) ) { if ( isBitwiseInverse ( Op0Op0 , Op1Op0 ) ) { Cond = Op1Op0 ; IfSet = Op1Op1 ; IfClr = Op0Op1 ; } else if ( isBitwiseInverse ( Op0Op1 , Op1Op0 ) ) { Cond = Op1Op0 ; IfSet = Op1Op1 ; IfClr = Op0Op0 ; } else if ( isBitwiseInverse ( Op0Op0 , Op1Op1 ) ) { Cond = Op1Op1 ; IfSet = Op1Op0 ; IfClr = Op0Op1 ; } else if ( isBitwiseInverse ( Op0Op1 , Op1Op1 ) ) { Cond = Op1Op1 ; IfSet = Op1Op0 ; IfClr = Op0Op0 ; } else if ( isBitwiseInverse ( Op1Op0 , Op0Op0 ) ) { Cond = Op0Op0 ; IfSet = Op0Op1 ; IfClr = Op1Op1 ; } else if ( isBitwiseInverse ( Op1Op1 , Op0Op0 ) ) { Cond = Op0Op0 ; IfSet = Op0Op1 ; IfClr = Op1Op0 ; } else if ( isBitwiseInverse ( Op1Op0 , Op0Op1 ) ) { Cond = Op0Op1 ; IfSet = Op0Op0 ; IfClr = Op1Op1 ; } else if ( isBitwiseInverse ( Op1Op1 , Op0Op1 ) ) { Cond = Op0Op1 ; IfSet = Op0Op0 ; IfClr = Op1Op0 ; } } if ( ! IfClr . getNode ( ) ) return SDValue ( ) ; assert ( Cond . getNode ( ) && IfSet . getNode ( ) ) ; if ( IsConstantMask ) { if ( Mask . isAllOnesValue ( ) ) return IfSet ;

else if ( Mask == <NUM_LIT> ) return IfClr ;


<s> Targets . insert ( BrI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; FallsThru = false ; return true ; default : Undetermined : FallsThru = ! BrI . isUnconditionalBranch ( ) ; return false ; } if ( SimpleBranch ) { const MachineOperand & MD = BrI . getOperand ( <NUM_LIT> ) ; Register PR ( MD ) ; if ( PR . SubReg ) goto Undetermined ; assert ( Inputs . has ( PR . Reg ) ) ; const LatticeCell & PredC = Inputs . get ( PR . Reg ) ; if ( PredC . isBottom ( ) ) goto Undetermined ; uint32_t Props = PredC . properties ( ) ; bool CTrue = false , CFalse = false ; ;

if ( Props & ConstantProperties :: Zero ) CFalse = true ;


<s> SDValue In = Op1 . getOperand ( <NUM_LIT> ) ; unsigned EffBits = In . getScalarValueSizeInBits ( ) - DAG . ComputeNumSignBits ( In ) + <NUM_LIT> ; if ( EffBits <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } } CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , CmpVT , Op1 ) ; } } if ( CmpVT == <STR_LIT> && isa < ConstantSDNode > ( Op1 ) && ! is<ISA_LIT>CCSigned ( <ISA_LIT>CC ) && Op0 . hasOneUse ( ) && cast < ConstantSDNode > ( Op1 ) -> getAPIntValue ( ) . getActiveBits ( ) <= <NUM_LIT> && DAG . MaskedValueIsZero ( Op0 , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op1 ) ;


<s> OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; } if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; GlobalsEmitted = false ;


<s> Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Value * Store = tryCreateMaskedScatterOffset ( I , Ptr , Builder ) ; if ( ! Store ) Store = tryCreateMaskedScatterBase ( I , Ptr , Builder ) ; if ( ! Store ) return nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; I -> eraseFromParent ( ) ; return Store ;


<s> if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ;

for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ;


<s> static void report_non_ice ( location_t location , tree fndecl , unsigned int argno ) { error_at ( location , <STR_LIT> <STR_LIT> , argno + <NUM_LIT> , fndecl ) ;


<s> const Constant * C = CPE . Val . ConstVal ; const MCSectionCOFF * S = cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( Kind , C ) ) ; if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer . EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ;


<s> unsigned getReg ( ) const { assert ( ( Kind == k_Register || Kind == k_Memri ) && <STR_LIT> ) ;


<s> unsigned TySize = Func -> getParent ( ) -> getDataLayout ( ) . getTypeSizeInBits ( RootTy ) / <NUM_LIT> ; IRBuilder < > IRB ( CI ) ; if ( isa < ConstantInt > ( Size ) && TySize == cast < ConstantInt > ( Size ) -> getZExtValue ( ) ) { copyMemory ( Dst , Src , Ty , ValArr , IRB ) ; RemoveInstrs . push_back ( CI ) ; for ( auto Val : RemoveInstrs ) InsertIntoSet ( LazyRemovalSet , Val ) ; } else {


<s> <ISA_LIT>ArgumentUsageInfo ( ) : ImmutablePass ( ID ) {


<s> MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; SMLoc SRegLoc = getLoc ( ) ; int RegNum = tryParseRegister ( ) ; RegKind RegisterKind = RegKind :: Scalar ; if ( RegNum == - <NUM_LIT> ) { StringRef Kind ; RegisterKind = RegKind :: NeonVector ; OperandMatchResultTy Res = tryParseVectorRegister ( RegNum , Kind , RegKind :: NeonVector ) ; if ( Res == MatchOperand_ParseFail ) return true ; if ( Res == MatchOperand_Success && ! Kind . empty ( ) ) return Error ( SRegLoc , <STR_LIT> ) ; } if ( RegNum == - <NUM_LIT> ) { StringRef Kind ; RegisterKind = RegKind :: SVEDataVector ; OperandMatchResultTy Res = tryParseVectorRegister ( RegNum , Kind , RegKind :: SVEDataVector ) ; if ( Res == MatchOperand_ParseFail ) return true ; if ( Res == MatchOperand_Success && ! Kind . empty ( ) ) return Error ( SRegLoc , <STR_LIT> ) ; } if ( RegNum == - <NUM_LIT> ) {


<s> mode = GET_MODE ( dest ) ; num_ops = riscv_build_integer ( codes , value , orig_mode ) ; if ( can_create_pseudo && num_ops > <NUM_LIT> && num_ops >= riscv_split_integer_cost ( value ) ) x = riscv_split_integer ( value , mode ) ; else { codes [ <NUM_LIT> ] . value = trunc_int_for_mode ( codes [ <NUM_LIT> ] . value , mode ) ; x = GEN_INT ( codes [ <NUM_LIT> ] . value ) ; for ( i = <NUM_LIT> ; i < num_ops ; i ++ ) { if ( ! can_create_pseudo ) x = riscv_emit_set ( temp , x ) ; else x = force_reg ( mode , x ) ;

codes [ i ] . value = trunc_int_for_mode ( codes [ i ] . value , mode ) ;


<s> if ( reg != mips_epilogue . cfa_reg || offset != mips_epilogue . cfa_offset ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = alloc_reg_note ( REG_CFA_DEF_CFA , plus_constant ( Pmode , reg , offset ) , REG_NOTES ( insn ) ) ; mips_epilogue . cfa_reg = reg ;


<s> } else { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( Hi ) ) ; } if ( ! Shift ) return Result ; if ( ( unsigned ) ( Imm & <NUM_LIT> ) == Remainder ) { SDValue Ops [ ] = { SDValue ( Result , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Shift ) , getI32Imm ( <NUM_LIT> ) } ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } if ( Imm ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Shift ) , getI32Imm ( <NUM_LIT> - Shift ) ) ; } if ( ( Hi = ( Remainder >> <NUM_LIT> ) & <NUM_LIT> ) ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Hi ) ) ; }


<s> case MachineOperand :: MO_GlobalAddress : Symbol = Mang -> getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = AsmPrinter . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = AsmPrinter . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: Create ( Symbol , Kind , * Ctx ) ;

if ( ! Offset ) return MCOperand :: CreateExpr ( MCSym ) ;


<s> const TargetRegisterClass * RC ; RC = ( const TargetRegisterClass * ) & <STR_LIT> ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ;


<s> BitSize = std :: min ( BitSize , OrigBitSize ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; for ( int64_t I = BitSize / <NUM_LIT> ; I >= <NUM_LIT> ; I = I / <NUM_LIT> ) {

SDValue Tmp = DAG . getNode ( <STR_LIT> , DL , VT , Op , DAG . getConstant ( I , VT ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget . hasLZCNT ( ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> inline vector signed int vec_vcmpgtsw ( vector signed int a1 , vector signed int a2 ) {

return ( vector signed int ) __builtin_altivec_vcmpgtsw ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; EVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) {


<s> else if ( VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) ; else if ( ! rtx_equal_p ( a , b ) ) return false ; if ( TARGET_64BIT ) { if ( cfun -> machine -> call_abi == MS_ABI && ix86_function_type_abi ( type ) == SYSV_ABI ) return false ; } else { if ( ! decl || ( bind_global && flag_pic && ! flag_plt ) || ( TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P ( decl ) ) ) { if ( ix86_function_regparm ( type , NULL ) >= <NUM_LIT> && ! cfun -> machine -> arg_reg_available ) return false ; } }


<s> static void fixStackStores ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator StartMI , const TargetInstrInfo & TII , Register FP ) { for ( MachineInstr & MI :

llvm :: make_early_inc_range ( llvm :: make_range ( StartMI , MBB . end ( ) ) ) ) {


<s> } } if ( LD -> getAlignment ( ) == <NUM_LIT> ) { SDValue Low = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , BasePtr , LD -> getPointerInfo ( ) , <STR_LIT> , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , <NUM_LIT> ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue High = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , HighAddr , LD -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , <NUM_LIT> ) ; SDValue HighShifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low , HighShifted ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low . getValue ( <NUM_LIT> ) , High . getValue ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { Result , Chain } ; return DAG . getMergeValues ( Ops , DL ) ; } Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ; Entry . Node = BasePtr ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( Chain ) . setCallee ( CallingConv :: C , IntPtrTy , DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) , std :: move ( Args ) , <NUM_LIT> ) ;

std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ;


<s> int Scale = computeScale ( BasePtr -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) , MemoryTy -> getScalarSizeInBits ( ) ) ; if ( Scale == - <NUM_LIT> ) return nullptr ; if ( ! match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { BasePtr -> getType ( ) , Offsets -> getType ( ) , Input -> getType ( ) , Mask -> getType ( ) } , { BasePtr , Offsets , Input , Builder . getInt32 ( MemoryTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Mask } ) ;

else return Builder . CreateIntrinsic ( <STR_LIT> , { BasePtr -> getType ( ) , Offsets -> getType ( ) , Input -> getType ( ) } , { BasePtr , Offsets , Input , Builder . getInt32 ( MemoryTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) } ) ;


<s> } const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned Exec = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned MovExecOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; Register SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( MBB , Begin , DL , TII . get ( MovExecOpc ) , SaveExec ) . addReg ( Exec ) ; MachineBasicBlock :: iterator AfterMI = MI ; ++ AfterMI ; for ( auto I = Begin ; I != AfterMI ; I ++ ) { for ( auto & MO : I -> uses ( ) ) { if ( MO . isReg ( ) && MO . isUse ( ) ) { MRI . clearKillFlags ( MO . getReg ( ) ) ; } } } MachineBasicBlock * LoopBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * BodyBB = MF . CreateMachineBasicBlock ( ) ; MachineBasicBlock * RemainderBB = MF . CreateMachineBasicBlock ( ) ; MachineFunction :: iterator MBBI ( MBB ) ; ++ MBBI ; MF . insert ( MBBI , LoopBB ) ; MF . insert ( MBBI , BodyBB ) ; MF . insert ( MBBI , RemainderBB ) ; LoopBB -> addSuccessor ( BodyBB ) ; BodyBB -> addSuccessor ( LoopBB ) ; BodyBB -> addSuccessor ( RemainderBB ) ; RemainderBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ;

RemainderBB -> splice ( RemainderBB -> begin ( ) , & MBB , End , MBB . end ( ) ) ;


<s> return new <ISA_LIT>AssignValidGlobalNames ( ) ;


<s> assert ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) ; if ( Opcode == Instruction :: Store ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , I ) ; if ( Src -> isVectorTy ( ) ) { VectorType * VecTy = cast < VectorType > ( Src ) ; unsigned VecWidth = VecTy -> getBitWidth ( ) ; if ( useHVX ( ) && isTypeForHVX ( VecTy ) ) { unsigned RegWidth = getRegisterBitWidth ( true ) ;

Alignment = std :: min ( Alignment , RegWidth / <NUM_LIT> ) ;


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ;


<s> MachineInstr * <ISA_LIT>ExpandCondsets :: genCondTfrFor ( MachineOperand & SrcOp , MachineBasicBlock :: iterator At , unsigned DstR , unsigned DstSR , const MachineOperand & PredOp , bool PredSense , bool ReadUndef , bool ImpUse ) { MachineInstr * MI = SrcOp . getParent ( ) ; MachineBasicBlock & B = * At -> getParent ( ) ;

const DebugLoc & DL = MI -> getDebugLoc ( ) ;


<s> return isVCSrcF64 ( ) || isLiteralImm ( <STR_LIT> ) ;


<s> RegInfo & RI = RegInfos [ R ] ; if ( RI . RegClass != nullptr && ! BadRC [ R ] ) { if ( RC -> LaneMask != RI . RegClass -> LaneMask ) { BadRC . set ( R ) ; RI . RegClass = nullptr ; } } else RI . RegClass = RC ; } } for ( MCPhysReg R = <NUM_LIT> , NR = TRI . getNumRegs ( ) ; R != NR ; ++ R ) { MCPhysReg SuperR = R ; for ( MCSuperRegIterator S ( R , & TRI , false ) ; S . isValid ( ) ; ++ S ) SuperR = * S ; RegInfos [ R ] . MaxSuper = SuperR ; } for ( const uint32_t * RM : TRI . getRegMasks ( ) ) RegMasks . insert ( RM ) ; for ( const MachineBasicBlock & B : mf ) for ( const MachineInstr & In : B ) for ( const MachineOperand & Op : In . operands ( ) ) if ( Op . isRegMask ( ) ) RegMasks . insert ( Op . getRegMask ( ) ) ;


<s> while ( I2 -> isDebugValue ( ) ) ++ I2 ; unsigned I1DestReg = I1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineBasicBlock :: iterator End = I1 -> getParent ( ) -> end ( ) ; I2 != End ; ++ I2 ) { if ( I2 -> modifiesRegister ( I1DestReg , TRI ) ) break ; if ( ! isCombinableInstType ( I2 , TII , ShouldCombineAggressively ) ) continue ;

if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( I2 ) ) continue ;


<s> static int bit_size_for_clip ( HOST_WIDE_INT i ) { int rv ; for ( rv = <NUM_LIT> ; rv < <NUM_LIT> ; rv ++ ) if ( ( ( HOST_WIDE_INT ) <NUM_LIT> << rv ) > i ) return rv + <NUM_LIT> ; gcc_unreachable ( ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> if ( F == DefM . end ( ) ) continue ; DefStack & DS = F -> second ; if ( Kind == NodeAttrs :: Use ) linkRefUp < UseNode * > ( SA , RA , DS ) ; else if ( Kind == NodeAttrs :: Def ) linkRefUp < DefNode * > ( SA , RA , DS ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseUNorm ( OperandVector & Operands ) {

return parseNamedBit ( <STR_LIT> , Operands ) ;


<s> const unsigned MaxAlloca = ( <NUM_LIT> - <NUM_LIT> ) * <NUM_LIT> ; unsigned ThresholdPrivate = UnrollThresholdPrivate ; unsigned ThresholdLocal = UnrollThresholdLocal ; unsigned MaxBoost = std :: max ( ThresholdPrivate , ThresholdLocal ) ; <ISA_LIT>AS ASST = ST -> get<ISA_LIT>AS ( ) ; for ( const BasicBlock * BB : L -> getBlocks ( ) ) { const DataLayout & DL = BB -> getModule ( ) -> getDataLayout ( ) ; unsigned LocalGEPsSeen = <NUM_LIT> ; if ( llvm :: any_of ( L -> getSubLoops ( ) , [ BB ] ( const Loop * SubLoop ) { return SubLoop -> contains ( BB ) ; } ) ) continue ; for ( const Instruction & I : * BB ) { if ( const BranchInst * Br = dyn_cast < BranchInst > ( & I ) ) { if ( UP . Threshold < MaxBoost && Br -> isConditional ( ) ) { if ( L -> isLoopExiting ( Br -> getSuccessor ( <NUM_LIT> ) ) || L -> isLoopExiting ( Br -> getSuccessor ( <NUM_LIT> ) ) ) continue ; if ( dependsOnLocalPhi ( L , Br -> getCondition ( ) ) ) { UP . Threshold += UnrollThresholdIf ; DEBUG ( dbgs ( ) << <STR_LIT> << UP . Threshold << <STR_LIT> << * L << <STR_LIT> << * Br << '\n' ) ; if ( UP . Threshold >= MaxBoost ) return ; } } continue ; } const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP ) continue ; unsigned AS = GEP -> getAddressSpace ( ) ; unsigned Threshold = <NUM_LIT> ; if ( AS == ASST . PRIVATE_ADDRESS ) Threshold = ThresholdPrivate ;

else if ( AS == ASST . LOCAL_ADDRESS ) Threshold = ThresholdLocal ;


<s> Reg = signExtendToI32 ( Reg , V , From ) ; Register Result = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result ) . addReg ( Reg ) ; return Result ; }

if ( To == <STR_LIT> ) return signExtendToI32 ( Reg , V , From ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>ebTargetMachine > X ( The<ISA_LIT>Target ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > Y ( The<ISA_LIT>elTarget ) ;


<s> if ( DestVT == <STR_LIT> ) DestVT = Op0 . getValueType ( ) ; return DAG . getNode ( <STR_LIT> , dl , DestVT , DAG . getConstant ( IID , <STR_LIT> ) , Op0 , Op1 , Op2 ) ;


<s> void setNomacro ( ) { macro = false ;


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const {

return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC ) ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ;

if ( CopyVT . isVector ( ) && ! Subtarget -> isLittleEndian ( ) ) return false ;


<s> if ( B . succ_empty ( ) ) return nullptr ; auto & Prob = getAnalysis < MachineBranchProbabilityInfo > ( ) ; MachineBasicBlock * S = * std :: max_element ( B . succ_begin ( ) , B . succ_end ( ) , [ & ] ( const MachineBasicBlock * Dst0 , const MachineBasicBlock * Dst1 ) { return Prob . getEdgeWeight ( & B , Dst0 ) < Prob . getEdgeWeight ( & B , Dst1 ) ; } ) ;


<s> return <STR_LIT> ( Ty . getSizeInBits ( ) ) ;


<s> bool isToken ( ) const override { return Kind == k_Token ;


<s> static int vfp3_const_double_index ( rtx x ) { REAL_VALUE_TYPE r , m ; int sign , exponent ; unsigned HOST_WIDE_INT mantissa , mant_hi ; unsigned HOST_WIDE_INT mask ; int point_pos = <NUM_LIT> * HOST_BITS_PER_WIDE_INT - <NUM_LIT> ; bool fail ; if ( ! TARGET_VFP3 || ! CONST_DOUBLE_P ( x ) ) return - <NUM_LIT> ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - <NUM_LIT> ; sign = REAL_VALUE_NEGATIVE ( r ) ? <NUM_LIT> : <NUM_LIT> ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * <NUM_LIT> ) ; mantissa = w . elt ( <NUM_LIT> ) ;


<s> State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ; return true ; }

if ( unsigned Reg = State . AllocateReg ( RegList , <NUM_LIT> ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ;


<s> if ( SYSmvalue == - <NUM_LIT> ) return - <NUM_LIT> ; if ( ! Subtarget -> hasV7Ops ( ) && SYSmvalue >= <NUM_LIT> && SYSmvalue <= <NUM_LIT> ) return - <NUM_LIT> ; if ( Subtarget -> has8MSecExt ( ) && Flags . lower ( ) == <STR_LIT> ) { Flags = <STR_LIT> ; SYSmvalue |= <NUM_LIT> ; } if ( ! Subtarget -> has8MSecExt ( ) && ( SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue > <NUM_LIT> ) ) return - <NUM_LIT> ; if ( ! Subtarget -> hasV8MMainlineOps ( ) && ( SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> || SYSmvalue == <NUM_LIT> ) ) return - <NUM_LIT> ; if ( IsRead ) { if ( Flags . empty ( ) ) return SYSmvalue ; else return - <NUM_LIT> ; } int Mask = getMClassFlagsMask ( Flags ) ; if ( ( SYSmvalue < <NUM_LIT> && Mask == - <NUM_LIT> ) || ( SYSmvalue > <NUM_LIT> && ! Flags . empty ( ) ) ) return - <NUM_LIT> ;

if ( ! Subtarget -> hasDSP ( ) && ( Mask & <NUM_LIT> ) ) return - <NUM_LIT> ;


<s> return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : { unsigned Reg = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MIB -> setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) . addImm ( <NUM_LIT> ) ; return true ; } case <STR_LIT> : MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : MI . setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrKreg ( MIB , get ( <STR_LIT> ) , <STR_LIT> ) ;


<s> Register Reg1 = Op1 . getReg ( ) ; CmpInst :: Predicate Cond = static_cast < CmpInst :: Predicate > ( MI . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; if ( ( ! ST -> canDirectlyComparePointers ( ) || ( Cond != CmpInst :: ICMP_EQ && Cond != CmpInst :: ICMP_NE ) ) && MRI . getType ( Reg0 ) . isPointer ( ) && MRI . getType ( Reg1 ) . isPointer ( ) ) { LLT ConvT = LLT :: scalar ( ST -> getPointerSize ( ) ) ; Type * LLVMTy = IntegerType :: get ( MI . getMF ( ) -> getFunction ( ) . getContext ( ) , ST -> getPointerSize ( ) ) ;

<ISA_LIT>Type * SpirvTy = GR -> getOrCreate<ISA_LIT>Type ( LLVMTy , Helper . MIRBuilder ) ;


<s> if ( Constraint . length ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'I' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { uint64_t CVal = C -> getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( CVal ) ) Ops . push_back ( DAG . getTargetConstant ( CVal , SDLoc ( Op ) , Subtarget . getXLenVT ( ) ) ) ;


<s> vmla_n_u16 ( uint16x4_t a , uint16x4_t b , uint16_t c ) {


<s> bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , - SPOffsetFromCFA - Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; if ( StoreBackchain ) { int Offset = usePackedStack ( MF ) ? <STR_LIT> - <NUM_LIT> : <NUM_LIT> ; BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) ; } } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > CFIIndexes ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ;


<s> <ISA_LIT>elTargetMachine :: <ISA_LIT>elTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> rtx nds32_return_addr_rtx ( int count , rtx frameaddr ATTRIBUTE_UNUSED ) { if ( count != <NUM_LIT> ) return NULL_RTX ; return get_hard_reg_initial_val ( Pmode , LP_REGNUM ) ;


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Val ) ) return CreateImm ( CE -> getValue ( ) , S , E , Is<ISA_LIT>64 ) ; if ( const MCSymbolRefExpr * SRE = dyn_cast < MCSymbolRefExpr > ( Val ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_TLS ) return CreateTLSReg ( SRE , S , E , Is<ISA_LIT>64 ) ; return CreateExpr ( Val , S , E , Is<ISA_LIT>64 ) ;


<s> return frv_function_arg_1 ( cum , arg , true ) ;


<s> unsigned RegNum ; OperandMatchResultTy Res = tryParseScalarRegister ( RegNum ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ! parseOptionalToken ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , StartLoc , getLoc ( ) , getContext ( ) ) ) ; return MatchOperand_Success ; }

parseOptionalToken ( AsmToken :: Hash ) ;


<s> if ( ! AtStart ) -- BeforeI ; for ( std :: vector < CalleeSavedInfo > :: const_iterator it = CSI . begin ( ) ; it != CSI . end ( ) ; ++ it ) { loadRegFromStackSlot ( MBB , MI , it -> getReg ( ) , it -> getFrameIdx ( ) , it -> getRegClass ( ) ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; if ( AtStart ) MI = MBB . begin ( ) ; else { MI = BeforeI ; ++ MI ; }


<s> return CC_DEQmode ; case LE : return CC_DLEmode ; case LT : return CC_DLTmode ; case GE : return CC_DGEmode ; case GT : return CC_DGTmode ;


<s> static <ISA_LIT>ABIInfo Unknown ( ) { return <ISA_LIT>ABIInfo ( <STR_LIT> ) ;


<s> TYPE_MAIN_VARIANT ( node ) = node ; return build_vector_type ( node , nunits ) ;


<s> static reg_class_t arm_preferred_reload_class ( rtx x ATTRIBUTE_UNUSED , reg_class_t rclass ) { if ( TARGET_32BIT ) return rclass ; else { if ( rclass == GENERAL_REGS ) return LO_REGS ; else return rclass ; }


<s> if ( OpNo < MI -> getNumOperands ( ) ) { <STR_LIT> e = static_cast < <STR_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ;


<s> MI -> getOperand ( <NUM_LIT> ) . setMBB ( MBB ) ;


<s> DefaultSize [ <NUM_LIT> ] = <NUM_LIT> ; DefaultSize [ <NUM_LIT> ] = <NUM_LIT> ; DefaultSize [ <NUM_LIT> ] = <NUM_LIT> ; HasVertexCache = false ; ParseSubtargetFeatures ( GPU , FS ) ; DevName = GPU ;

Device = <STR_LIT> ( DevName , this , Is64bit ) ;


<s> MEM_VOLATILE_P ( memref ) = <NUM_LIT> ; emit_insn ( gen_movsi ( memref , stack_pointer_rtx ) ) ; size -= mcore_stack_increment ; } while ( size > mcore_stack_increment ) ; } if ( size ) { rtx insn ; rtx val = GEN_INT ( size ) ; if ( size > <NUM_LIT> ) {

rtx nval = gen_rtx_REG ( SImode , <NUM_LIT> ) ;