<s> decreaseLiveRegs ( Block , Block -> getInRegs ( ) ) ; addLiveRegs ( Block -> getOutRegs ( ) ) ; releaseBlockSuccs ( Block ) ; for ( const auto & RegP : LiveOutRegsNumUsages [ Block -> getID ( ) ] ) {

assert ( LiveRegsConsumers . find ( RegP . first ) == LiveRegsConsumers . end ( ) || LiveRegsConsumers [ RegP . first ] == <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isStridedAccess ( const MachineInstr & MI ) const {

return llvm :: any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) {


<s> explicit <ISA_LIT>FrameInfo ( const <ISA_LIT>Subtarget & sti ) : TargetFrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) , STI ( sti ) {


<s> if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( N ) , <STR_LIT> , AM . Disp , <NUM_LIT> ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , <NUM_LIT> ) ; else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , <NUM_LIT> ) ; else if ( AM . JT != - <NUM_LIT> ) Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , <NUM_LIT> ) ; else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , <NUM_LIT> , <NUM_LIT> ) ; else Disp = CurDAG -> getTargetConstant ( AM . Disp , SDLoc ( N ) , <STR_LIT> ) ; return true ;


<s> MCI . getOperand ( MCI . getNumOperands ( ) - <NUM_LIT> ) . setImm ( Bits . to_ulong ( ) ) ;


<s> Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; if ( Sym -> getKind ( ) == MCSymbolRefExpr :: VK_GOT ) RelocType = unsigned ( MachO :: ARM64_RELOC_POINTER_TO_GOT ) ; return true ; case FK_Data_8 : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; if ( Sym -> getKind ( ) == MCSymbolRefExpr :: VK_GOT ) RelocType = unsigned ( MachO :: ARM64_RELOC_POINTER_TO_GOT ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGEOFF12 ) ; return true ; } case <STR_LIT> : Log2Size = llvm :: Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGE21 ) ; return true ;


<s> static unsigned computeReturnSaveOffset ( const <ISA_LIT>Subtarget & STI ) {

if ( STI . isDarwinABI ( ) ) return STI . is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> const char * Sym = N -> getSymbol ( ) ; if ( isPositionIndependent ( ) || Subtarget . is64Bit ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue GAHi = DAG . getTargetExternalSymbol ( Sym , Ty , <STR_LIT> ) ; SDValue GALo = DAG . getTargetExternalSymbol ( Sym , Ty , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , GAHi ) , <NUM_LIT> ) ; SDValue MNLo = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , GALo ) , <NUM_LIT> ) ;


<s> SDValue Ops [ ] = { LdHi -> getChain ( ) , LdHi -> getBasePtr ( ) , TiedIn } ; unsigned LoadOp = <STR_LIT> ; if ( LdHi -> getMemoryVT ( ) == <STR_LIT> ) { LoadOp = LdHi -> getExtensionType ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else { assert ( LdHi -> getMemoryVT ( ) == <STR_LIT> ) ; } SDValue NewLoadHi = CurDAG -> getMemIntrinsicNode ( LoadOp , SDLoc ( LdHi ) , VTList , Ops , LdHi -> getMemoryVT ( ) , LdHi -> getMemOperand ( ) ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , NewLoadHi ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( LdHi , <NUM_LIT> ) , NewLoadHi . getValue ( <NUM_LIT> ) ) ; return true ; } LoadSDNode * LdLo = dyn_cast < LoadSDNode > ( stripBitcast ( Lo ) ) ; if ( LdLo && Lo . hasOneUse ( ) ) { SDValue TiedIn = getHi16Elt ( Hi ) ; if ( ! TiedIn || LdLo -> isPredecessorOf ( TiedIn . getNode ( ) ) ) return false ; SDVTList VTList = CurDAG -> getVTList ( VT , <STR_LIT> ) ; unsigned LoadOp = <STR_LIT> ; if ( LdLo -> getMemoryVT ( ) == <STR_LIT> ) { LoadOp = LdLo -> getExtensionType ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else { assert ( LdLo -> getMemoryVT ( ) == <STR_LIT> ) ; } TiedIn = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N ) , VT , TiedIn ) ; SDValue Ops [ ] = { LdLo -> getChain ( ) , LdLo -> getBasePtr ( ) , TiedIn } ; SDValue NewLoadLo = CurDAG -> getMemIntrinsicNode ( LoadOp , SDLoc ( LdLo ) , VTList , Ops , LdLo -> getMemoryVT ( ) , LdLo -> getMemOperand ( ) ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , NewLoadLo ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( LdLo , <NUM_LIT> ) , NewLoadLo . getValue ( <NUM_LIT> ) ) ; return true ; } return false ;


<s> void <ISA_LIT>MCInstrInfo :: setMustNotExtend ( MCExpr const & Expr , bool Val ) { <ISA_LIT>MCExpr & HExpr = const_cast < <ISA_LIT>MCExpr & > ( cast < <ISA_LIT>MCExpr > ( Expr ) ) ;


<s> Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const {


<s> return false ; } return TargetRegisterInfo :: shouldCoalesce ( MI , SrcRC , SubReg , DstRC , DstSubReg , NewRC , LIS ) ;


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget -> hasLZCNT ( ) ;


<s> int getVarArgsFrameIndex ( ) const { return VarArgsFrameIndex ;


<s> if ( FB & ( <NUM_LIT> << F ) ) STI -> ToggleFeature ( F ) ;


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( ! isBrAnalysisUnpredicatedTerminator ( I , * this ) ) break ; if ( ! I -> getDesc ( ) . isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( llvm :: next ( I ) != MBB . end ( ) ) llvm :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = GetCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ;


<s> <ISA_LIT>FunctionInfo :: <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : isThumb ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ) , hasThumb2 ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasThumb2 ( ) ) {


<s> enum machine_mode mode = TYPE_MODE ( type ) ; if ( TREE_CODE ( type ) == VECTOR_TYPE && ! VECTOR_MODE_P ( mode ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( ( size == <NUM_LIT> || size == <NUM_LIT> ) && TYPE_VECTOR_SUBPARTS ( type ) > <NUM_LIT> ) {

enum machine_mode innermode = TYPE_MODE ( TREE_TYPE ( type ) ) ;


<s> sp8_spec = sp8 ? <STR_LIT> : <STR_LIT> ; } fprintf ( f , <STR_LIT> <STR_LIT> ) ; if ( is_arch ) fprintf ( f , <STR_LIT> , arch -> name ) ; else fprintf ( f , <STR_LIT> , mcu -> name , arch -> name , sp8 ? <NUM_LIT> : <NUM_LIT> ) ; fprintf ( f , <STR_LIT> , header ) ; if ( is_device ) fprintf ( f , <STR_LIT> , help_copy_paste ) ; if ( is_device ) { fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , mcu -> name ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , mcu -> name ) ; fprintf ( f , <STR_LIT> ) ; } fprintf ( f , <STR_LIT> <STR_LIT> , mcu -> n_flash ) ; fprintf ( f , <STR_LIT> , rmw ? <STR_LIT> : <STR_LIT> ) ; fprintf ( f , <STR_LIT> , errata_skip ? <STR_LIT> : <STR_LIT> ) ; fprintf ( f , <STR_LIT> , arch -> name ) ; fprintf ( f , <STR_LIT> , ASM_RELAX_SPEC ) ; fprintf ( f , <STR_LIT> , rmw ? <STR_LIT> : <STR_LIT> ) ; fprintf ( f , <STR_LIT> , errata_skip ? <STR_LIT> : <STR_LIT> ) ; int wrap_k = str_prefix_p ( mcu -> name , <STR_LIT> ) ? <NUM_LIT> : str_prefix_p ( mcu -> name , <STR_LIT> ) ? <NUM_LIT> : ( str_prefix_p ( mcu -> name , <STR_LIT> ) || str_prefix_p ( mcu -> name , <STR_LIT> ) ) ? <NUM_LIT> : ( str_prefix_p ( mcu -> name , <STR_LIT> ) || str_prefix_p ( mcu -> name , <STR_LIT> ) || str_prefix_p ( mcu -> name , <STR_LIT> ) ) ? <NUM_LIT> : <NUM_LIT> ; fprintf ( f , <STR_LIT> ) ; if ( wrap_k ) fprintf ( f , <STR_LIT> , wrap_k ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , LINK_RELAX_SPEC ) ; fprintf ( f , <STR_LIT> , LINK_ARCH_SPEC ) ; if ( is_device ) { fprintf ( f , <STR_LIT> ) ; if ( mcu -> data_section_start != arch -> default_data_section_start ) fprintf ( f , <STR_LIT> , <NUM_LIT> + mcu -> data_section_start ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; if ( mcu -> text_section_start != <NUM_LIT> ) fprintf ( f , <STR_LIT> , <NUM_LIT> + mcu -> text_section_start ) ; fprintf ( f , <STR_LIT> ) ; }


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { sgxFunctionMagicReset ( ) ; sgxCallSiteMagicReset ( ) ; sgxCallMagicReset ( ) ; PrintModuleMacros ( OutStreamer . get ( ) ) ; const Triple & TT = TM . getTargetTriple ( ) ; if ( TT . isOSBinFormatMachO ( ) ) OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { if ( TT . getArch ( ) == Triple :: x86 ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; OutStreamer -> EmitAssignment ( S , MCConstantExpr :: create ( int64_t ( <NUM_LIT> ) , MMI -> getContext ( ) ) ) ; }


<s> rtx condition_rtx , loc_ref ; if ( ! reg_or_0_operand ( op0 , SImode ) ) op0 = copy_to_mode_reg ( SImode , op0 ) ; if ( ! reg_or_0_operand ( op1 , SImode ) ) op1 = copy_to_mode_reg ( SImode , op1 ) ;


<s> for ( StackVreg & vreg : rv . Data ) { if ( ! LIS . hasInterval ( vreg . VirtReg ) || ! LIS . isLiveInToMBB ( LIS . getInterval ( vreg . VirtReg ) , & MBB ) ) { vreg = StackVreg ( <ISA_LIT>FunctionInfo :: UnusedReg ) ; }


<s> CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; allocateHSAUserSGPRs ( CCInfo , B , MF , * TRI , * Info ) ; unsigned i = <NUM_LIT> ; const Align KernArgBaseAlign ( <NUM_LIT> ) ; const unsigned BaseOffset = Subtarget -> getExplicitKernelArgOffset ( F ) ; uint64_t ExplicitArgOffset = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { const bool IsByRef = Arg . hasByRefAttr ( ) ; Type * ArgTy = IsByRef ? Arg . getParamByRefType ( ) : Arg . getType ( ) ; unsigned AllocSize = DL . getTypeAllocSize ( ArgTy ) ; if ( AllocSize == <NUM_LIT> ) continue ; MaybeAlign ABIAlign = IsByRef ? Arg . getParamAlign ( ) : None ; if ( ! ABIAlign ) ABIAlign = DL . getABITypeAlign ( ArgTy ) ; uint64_t ArgOffset = alignTo ( ExplicitArgOffset , ABIAlign ) + BaseOffset ; ExplicitArgOffset = alignTo ( ExplicitArgOffset , ABIAlign ) + AllocSize ; if ( Arg . use_empty ( ) ) { ++ i ; continue ; } Align Alignment = commonAlignment ( KernArgBaseAlign , ArgOffset ) ; if ( IsByRef ) { unsigned ByRefAS = cast < PointerType > ( Arg . getType ( ) ) -> getAddressSpace ( ) ; assert ( VRegs [ i ] . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ByRefAS == <ISA_LIT>AS :: CONSTANT_ADDRESS ) { lowerParameterPtr ( VRegs [ i ] [ <NUM_LIT> ] , B , ArgTy , ArgOffset ) ; } else { const LLT ConstPtrTy = LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ; Register PtrReg = MRI . createGenericVirtualRegister ( ConstPtrTy ) ; lowerParameterPtr ( PtrReg , B , ArgTy , ArgOffset ) ; B . buildAddrSpaceCast ( VRegs [ i ] [ <NUM_LIT> ] , PtrReg ) ; } } else {

ArrayRef < Register > OrigArgRegs = VRegs [ i ] ;


<s> SMLoc <ISA_LIT>Operand :: getEndLoc ( ) const { return this -> EndLoc ;


<s> elt = CONST_DOUBLE_FROM_REAL_VALUE ( r_pow , DFmode ) ; RTVEC_ELT ( v , <NUM_LIT> ) = elt ; RTVEC_ELT ( v , <NUM_LIT> ) = elt ; rs6000_expand_vector_init ( scale_vec , gen_rtx_PARALLEL ( V2DFmode , v ) ) ; emit_insn ( gen_mulv2df3 ( tgt , src , scale_vec ) ) ;


<s> SramEccSetting = NewSramEccSetting ;


<s> gcc_assert ( GET_CODE ( rtlname ) == SYMBOL_REF ) ; oldname = XSTR ( rtlname , <NUM_LIT> ) ; gcc_assert ( ! mcore_dllexport_name_p ( oldname ) ) ; if ( mcore_dllimport_name_p ( oldname ) ) return ; if ( TREE_CODE ( decl ) == VAR_DECL && ! DECL_VIRTUAL_P ( decl ) && DECL_INITIAL ( decl ) ) { error ( <STR_LIT> , decl ) ;


<s> <ISA_LIT>ResourceUsageAnalysis ( ) : CallGraphSCCPass ( ID ) {


<s> std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue SplatZero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SplatTrueVal = DAG . getConstant ( ExtTrueVal , DL , XLenVT ) ; SplatZero = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatZero , VL ) ;

SplatTrueVal = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , SplatTrueVal , VL ) ;


<s> void fr30_setup_incoming_varargs ( CUMULATIVE_ARGS * arg_regs_used_so_far , enum machine_mode mode , tree type ATTRIBUTE_UNUSED , int * pretend_size , int second_time ATTRIBUTE_UNUSED ) { int size ; gcc_assert ( mode != BLKmode ) ;

if ( targetm . calls . strict_argument_naming ( arg_regs_used_so_far ) ) arg_regs_used_so_far += fr30_num_arg_regs ( mode , type ) ;


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg , false ) ; if ( ! handleAssignments ( MIRBuilder , OutArgs , Handler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( Info . CallConv ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , InArgs , Handler ) ) return false ; } if ( Info . SwiftErrorVReg ) { MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; MIRBuilder . buildCopy ( Info . SwiftErrorVReg , Register ( <STR_LIT> ) ) ; }

uint64_t CalleePopBytes = doesCalleeRestoreStack ( Info . CallConv , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ? alignTo ( Handler . StackSize , <NUM_LIT> ) : <NUM_LIT> ;


<s> return REAL_VALUES_EQUAL ( r , dconst0 ) && ! REAL_VALUE_MINUS_ZERO ( r ) ;


<s> switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> if ( ! isIdenticalOp ( MI . getOperand ( MemOpNo + <STR_LIT> ) , MO ) ) return false ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i ++ ) if ( i != ( unsigned ) ( MemOpNo + <STR_LIT> ) && isIdenticalOp ( MI . getOperand ( i ) , MO ) ) return false ; if ( MI . getOperand ( MemOpNo + <STR_LIT> ) . isImm ( ) && ! isInt < <NUM_LIT> > ( MI . getOperand ( MemOpNo + <STR_LIT> ) . getImm ( ) + AddrDispShift ) ) return false ; } return true ;


<s> } if ( count == - <NUM_LIT> ) retaddr = gen_rtx_REG ( Pmode , A0_REG ) ; else { rtx addr = plus_constant ( Pmode , frame , - <NUM_LIT> * UNITS_PER_WORD ) ; addr = memory_address ( Pmode , addr ) ; retaddr = gen_reg_rtx ( Pmode ) ; emit_move_insn ( retaddr , gen_rtx_MEM ( Pmode , addr ) ) ; } curaddr = gen_reg_rtx ( Pmode ) ; label = gen_label_rtx ( ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) {

Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < ( TARGET_32BIT ? <NUM_LIT> : <NUM_LIT> ) ) mode = TARGET_32BIT ? SImode : DImode ;


<s> InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


<s> else if ( F . hasMinSize ( ) ) OptimizationGoal = <NUM_LIT> ; else if ( F . hasOptSize ( ) ) OptimizationGoal = <NUM_LIT> ; else if ( TM . getOptLevel ( ) == CodeGenOpt :: Aggressive ) OptimizationGoal = <NUM_LIT> ; else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = <NUM_LIT> ; else OptimizationGoal = <NUM_LIT> ; if ( OptimizationGoals == - <NUM_LIT> ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = <NUM_LIT> ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F . hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> emitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> emitCOFFSymbolType ( Type ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; } emitFunctionBody ( ) ; emitXRayTable ( ) ; if ( ! ThumbIndirectPads . empty ( ) ) { OutStreamer -> emitAssemblerFlag ( MCAF_Code16 ) ; emitAlignment ( Align ( <NUM_LIT> ) ) ; for ( std :: pair < unsigned , MCSymbol * > & TIP : ThumbIndirectPads ) {

OutStreamer -> emitLabel ( TIP . second ) ;


<s> if ( MBBI == MBB -> end ( ) ) MBBI = std :: prev ( MBBI ) ; if ( MBBI != MBB -> begin ( ) ) RS . forward ( MBBI ) ; } if ( ! RS . isRegUsed ( R0 ) && ! RS . isRegUsed ( R12 ) ) return true ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( Subtarget . getRegisterInfo ( ) ) ; const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( MBB -> getParent ( ) ) ; BitVector BV = RS . getRegsAvailable ( Subtarget . is<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; for ( int i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) BV . reset ( CSRegs [ i ] ) ; if ( SR1 ) { int FirstScratchReg = BV . find_first ( ) ; * SR1 = FirstScratchReg == - <NUM_LIT> ? ( unsigned ) <STR_LIT> : FirstScratchReg ; } if ( SR2 ) {

int SecondScratchReg = BV . find_next ( * SR1 ) ;


<s> <ISA_LIT>MCInstPrinter ( const MCAsmInfo & mai , const MCInstrInfo & mii , const MCRegisterInfo & mri ) : MCInstPrinter ( mai , mii , mri ) {


<s> if ( VT . isVector ( ) ) return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; SDLoc DL ( Op ) ;

SDValue Neg = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> SDValue NandABNandA = DAG . getNode ( <STR_LIT> , DL , VT , NandAB , LHS ) ; SDValue NandABNandB = DAG . getNode ( <STR_LIT> , DL , VT , NandAB , RHS ) ; SDValue Xor = DAG . getNode ( <STR_LIT> , DL , VT , NandABNandA , NandABNandB ) ;


<s> bool nios2_symbol_ref_in_small_data_p ( rtx sym ) { tree decl ; gcc_assert ( GET_CODE ( sym ) == SYMBOL_REF ) ; decl = SYMBOL_REF_DECL ( sym ) ; if ( SYMBOL_REF_TLS_MODEL ( sym ) != <NUM_LIT> ) return false ; switch ( nios2_gpopt_option ) { case gpopt_none : return false ; case gpopt_local : if ( decl && DECL_SECTION_NAME ( decl ) ) return nios2_small_section_name_p ( DECL_SECTION_NAME ( decl ) ) ; return ( SYMBOL_REF_SMALL_P ( sym ) && ! SYMBOL_REF_EXTERNAL_P ( sym ) && ! ( decl && DECL_WEAK ( decl ) ) ) ; case gpopt_global :


<s> if ( NumInstr < SkipThreshold ) return ; DebugLoc DL = From . getDebugLoc ( ) ;

BuildMI ( * From . getParent ( ) , & From , DL , TII -> get ( AMDGPU :: S_CBRANCH_EXECZ ) ) . addOperand ( To ) . addReg ( AMDGPU :: EXEC ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( TheBlackfinTarget , createBlackfinMCInstrInfo ) ;


<s> SDValue Add = N -> getOperand ( <NUM_LIT> ) ; if ( Add . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Lo = Add . getOperand ( <NUM_LIT> ) ;

if ( ( Lo . getOpcode ( ) != <STR_LIT> ) || ( Lo . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ;


<s> static int loongarch_zero_extend_cost ( rtx op ) { if ( MEM_P ( op ) ) return <NUM_LIT> ;


<s> if ( IntImm . getActiveBits ( ) > <NUM_LIT> ) return false ; bool Success = TII -> isRxSBGMask ( IntImm . getZExtValue ( ) , BitWidth , Start , End ) ;


<s> BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; unsigned CmpOp = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MRI . constrainRegClass ( dest , TRCsp ) ; BuildMI ( BB , dl , TII -> get ( CmpOp ) ) . addReg ( dest ) . addReg ( oldval ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( exitMBB ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ;

BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) . addReg ( newval ) . addReg ( ptr ) ;


<s> return ( __m64 ) __builtin_arm_wpackdus ( ( long long ) __m1 , ( long long ) __m2 ) ;


<s> static int rws_access_reg ( rtx reg , struct reg_flags flags , int pred ) { int regno = REGNO ( reg ) ; int n = HARD_REGNO_NREGS ( REGNO ( reg ) , GET_MODE ( reg ) ) ; if ( n == <NUM_LIT> ) return rws_access_regno ( regno , flags , pred ) ; else { int need_barrier = <NUM_LIT> ; while ( -- n >= <NUM_LIT> ) need_barrier |= rws_access_regno ( regno + n , flags , pred ) ; return need_barrier ; }


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: z80 , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> <ISA_LIT>VectorPrint ( ) : MachineFunctionPass ( ID ) , QST ( nullptr ) , QII ( nullptr ) , QRI ( nullptr ) {

initialize<ISA_LIT>VectorPrintPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; unsigned StackPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( StackPtr , true ) , - stackGrowth ) ; MAI -> addInitialFrameState ( Inst ) ; unsigned InstPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst2 = MCCFIInstruction :: createOffset ( nullptr , MRI . getDwarfRegNum ( InstPtr , true ) , stackGrowth ) ;


<s> int EltIdx = MaskVals [ i ] ; if ( ( EltIdx < <NUM_LIT> || EltIdx == ( int ) i ) && ( SndLaneEltIdx < <NUM_LIT> || SndLaneEltIdx == ( int ) ( i + NumElemsInLane ) ) ) continue ; if ( ( ( unsigned ) EltIdx == ( i + NumElems ) ) && ( SndLaneEltIdx < <NUM_LIT> || ( unsigned ) SndLaneEltIdx == i + NumElems + NumElemsInLane ) ) MaskValue |= ( <NUM_LIT> << i ) ; else return false ; } if ( MaskOut ) * MaskOut = MaskValue ;


<s> if ( ST . hasArithmeticCbzFusion ( ) && isArithmeticCbzPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseAES ( ) && isAESPair ( FirstMI , SecondMI ) ) return true ; if ( ST . hasFuseLiterals ( ) && isLiteralsPair ( FirstMI , SecondMI ) ) return true ;

if ( ST . hasFuseAddress ( ) && isAddressLdStPair ( FirstMI , SecondMI ) ) return true ;


<s> Op -> BTIHint . Data = Str . data ( ) ; Op -> BTIHint . Length = Str . size ( ) ; Op -> StartLoc = S ;


<s> bool A15SDOptimizer :: usesRegClass ( MachineOperand & MO , const TargetRegisterClass * TRC ) { if ( ! MO . isReg ( ) ) return false ; unsigned Reg = MO . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return MRI -> getRegClass ( Reg ) -> hasSuperClassEq ( TRC ) ; else return TRC -> contains ( Reg ) ;


<s> auto MSRMapper = <STR_LIT> ( STI . getFeatureBits ( ) ) ; uint32_t MSRReg = MSRMapper . fromString ( Tok . getString ( ) , IsKnown ) ; assert ( IsKnown == ( MSRReg != - <NUM_LIT> ) && <STR_LIT> ) ; uint32_t PStateField = <STR_LIT> ( ) . fromString ( Tok . getString ( ) , IsKnown ) ; assert ( IsKnown == ( PStateField != - <NUM_LIT> ) && <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , MRSReg , MSRReg , PStateField , getContext ( ) ) ) ; Parser . Lex ( ) ;


<s> AttributeItemType item = Contents [ i ] ; Streamer . EmitULEB128IntValue ( item . Tag , <NUM_LIT> ) ; switch ( item . Type ) { case AttributeItemType :: NumericAttribute : Streamer . EmitULEB128IntValue ( item . IntValue , <NUM_LIT> ) ; break ; case AttributeItemType :: TextAttribute : Streamer . EmitBytes ( UppercaseString ( item . StringValue ) , <NUM_LIT> ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; break ; default :


<s> static bool isDataTypeToken ( StringRef Tok ) {

return Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> ;


return Kind == Memory && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) && getMemIndexReg ( ) >= <STR_LIT> && getMemIndexReg ( ) <= <STR_LIT> ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; unsigned Count = CSI . size ( ) ; ( void ) CC ; assert ( ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetMachO ( ) || CC == CallingConv :: PreserveMost || ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Offset = AFI -> getCalleeSavedStackSize ( ) ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; assert ( <STR_LIT> . contains ( RPI . Reg1 ) || <STR_LIT> . contains ( RPI . Reg1 ) ) ; RPI . IsGPR = <STR_LIT> . contains ( RPI . Reg1 ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; if ( ( RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) || ( ! RPI . IsGPR && <STR_LIT> . contains ( NextReg ) ) ) RPI . Reg2 = NextReg ; } assert ( ( ! RPI . isPaired ( ) || ( CSI [ i ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) ) ) && <STR_LIT> ) ; assert ( ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetMachO ( ) || CC == CallingConv :: PreserveMost || ( RPI . isPaired ( ) && ( ( RPI . Reg1 == <STR_LIT> && RPI . Reg2 == <STR_LIT> ) || RPI . Reg1 + <NUM_LIT> == RPI . Reg2 ) ) ) && <STR_LIT> ) ; RPI . FrameIdx = CSI [ i ] . getFrameIdx ( ) ; if ( Count * <NUM_LIT> != AFI -> getCalleeSavedStackSize ( ) && ! RPI . isPaired ( ) ) { Offset -= <NUM_LIT> ; assert ( MFI -> getObjectAlignment ( RPI . FrameIdx ) <= <NUM_LIT> ) ; MFI -> setObjectSize ( RPI . FrameIdx , <NUM_LIT> ) ;

} else Offset -= RPI . isPaired ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> static tree bfin_handle_l1_text_attribute ( tree * node , tree name , tree ARG_UNUSED ( args ) , int ARG_UNUSED ( flags ) , bool * no_add_attrs ) { tree decl = * node ; if ( TREE_CODE ( decl ) != FUNCTION_DECL ) { error ( <STR_LIT> , name ) ; * no_add_attrs = true ; }

else if ( DECL_SECTION_NAME ( decl ) != NULL && strcmp ( DECL_SECTION_NAME ( decl ) , <STR_LIT> ) != <NUM_LIT> ) {


<s> unsigned getSize ( ) const { return size ;


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const DataLayout * DL ) : TargetSelectionDAGInfo ( DL ) {


<s> unsigned RegN = MI . getOperand ( OpIdx ) . getReg ( ) ; unsigned Binary = <NUM_LIT> ; RegN = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegN ) ;

Binary |= ( RegN & <NUM_LIT> ) << <STR_LIT> ;


<s> unsigned NumFixedFPRs = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , E = ArgLocs . size ( ) ; I != E ; ++ I ) { SDValue ArgValue ; CCValAssign & VA = ArgLocs [ I ] ; EVT LocVT = VA . getLocVT ( ) ; if ( VA . isRegLoc ( ) ) { const TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedGPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : NumFixedFPRs += <NUM_LIT> ; RC = & <STR_LIT> ; break ; } unsigned VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; EVT PtrVT = getPointerTy ( ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; if ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) FIN = DAG . getNode ( <STR_LIT> , DL , PtrVT , FIN , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } InVals . push_back ( convertLocVTToValVT ( DAG , DL , VA , Chain , ArgValue ) ) ; } if ( IsVarArg ) { FuncInfo -> setVarArgsFirstGPR ( NumFixedGPRs ) ; FuncInfo -> setVarArgsFirstFPR ( NumFixedFPRs ) ; int64_t StackSize = CCInfo . getNextStackOffset ( ) ; FuncInfo -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; int64_t RegSaveOffset = TFL -> getOffsetOfLocalArea ( ) ; unsigned RegSaveIndex = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset , true ) ; FuncInfo -> setRegSaveFrameIndex ( RegSaveIndex ) ; if ( NumFixedFPRs < <STR_LIT> ) { SDValue MemOps [ <STR_LIT> ] ; for ( unsigned I = NumFixedFPRs ; I < <STR_LIT> ; ++ I ) { unsigned Offset = TFL -> getRegSpillOffset ( <STR_LIT> [ I ] ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , RegSaveOffset + Offset , true ) ;

SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ;


<s> if ( getPredicateSense ( MI1 , HII ) == PK_Unknown || getPredicateSense ( MI2 , HII ) == PK_Unknown ) return false ; SUnit * SU = MIToSUnit [ MI1 ] ; for ( auto I : CurrentPacketMIs ) { SUnit * PacketSU = MIToSUnit . find ( I ) -> second ; if ( PacketSU -> isSucc ( SU ) ) { for ( unsigned i = <NUM_LIT> ; i < PacketSU -> Succs . size ( ) ; ++ i ) { auto Dep = PacketSU -> Succs [ i ] ; if ( Dep . getSUnit ( ) == SU && Dep . getKind ( ) == SDep :: Data && <STR_LIT> . contains ( Dep . getReg ( ) ) ) { if ( restrictingDepExistInPacket ( I , Dep . getReg ( ) ) ) return false ; } }


<s> if ( LD -> getAlignment ( ) >= ABIAlignment ) return SDValue ( ) ; SDValue Chain = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; SDLoc DL ( Op ) ; if ( ! LD -> isVolatile ( ) ) { const GlobalValue * GV ; int64_t Offset = <NUM_LIT> ; if ( DAG . isBaseWithConstantOffset ( BasePtr ) && isWordAligned ( BasePtr -> getOperand ( <NUM_LIT> ) , DAG ) ) { SDValue NewBasePtr = BasePtr -> getOperand ( <NUM_LIT> ) ; Offset = cast < ConstantSDNode > ( BasePtr -> getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; return lowerLoadWordFromAlignedBasePlusOffset ( DL , Chain , NewBasePtr , Offset , DAG ) ; } if ( TLI . isGAPlusOffset ( BasePtr . getNode ( ) , GV , Offset ) && MinAlign ( GV -> getAlignment ( ) , <NUM_LIT> ) == <NUM_LIT> ) { SDValue NewBasePtr = DAG . getGlobalAddress ( GV , DL , BasePtr -> getValueType ( <NUM_LIT> ) ) ; return lowerLoadWordFromAlignedBasePlusOffset ( DL , Chain , NewBasePtr , Offset , DAG ) ; } } if ( LD -> getAlignment ( ) == <NUM_LIT> ) { SDValue Low = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , BasePtr , LD -> getPointerInfo ( ) , <STR_LIT> , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , <NUM_LIT> ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue High = DAG . getExtLoad ( <STR_LIT> , DL , <STR_LIT> , Chain , HighAddr , LD -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , <NUM_LIT> ) ; SDValue HighShifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low , HighShifted ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low . getValue ( <NUM_LIT> ) , High . getValue ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { Result , Chain } ; return DAG . getMergeValues ( Ops , DL ) ; } Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ;


<s> BranchInst * Term = dyn_cast < BranchInst > ( ( * I ) -> getTerminator ( ) ) ; if ( ! Term || Term -> isUnconditional ( ) ) { if ( isTopOfStack ( * I ) ) closeControlFlow ( * I ) ; continue ; } if ( I . nodeVisited ( Term -> getSuccessor ( <NUM_LIT> ) ) ) { if ( isTopOfStack ( * I ) ) closeControlFlow ( * I ) ; handleLoop ( Term ) ; continue ; } if ( isTopOfStack ( * I ) ) { PHINode * Phi = dyn_cast < PHINode > ( Term -> getCondition ( ) ) ; if ( Phi && Phi -> getParent ( ) == * I && isElse ( Phi ) ) {


<s> if ( GET_CODE ( op ) != MEM ) return <NUM_LIT> ; op = XEXP ( op , <NUM_LIT> ) ; return call_address_operand ( op , mode ) ;


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackUp ) ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , TM , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC ) ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( CopyVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ;


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ;


<s> assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; unsigned removed = <NUM_LIT> ; while ( I != REnd && removed < <NUM_LIT> ) { if ( I -> isDebugInstr ( ) ) { ++ I ; continue ; } if ( ! getAnalyzableBrOpc ( I -> getOpcode ( ) ) ) break ; I -> eraseFromParent ( ) ;


<s> if ( ! BaseT :: areFunctionArgsABICompatible ( Caller , Callee , Args ) ) return false ;

const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ;


<s> if ( ! TREE_READONLY ( decl ) && ! TARGET_SDATA_NONE ) { int size = int_size_in_bytes ( TREE_TYPE ( decl ) ) ; if ( size > <NUM_LIT> && ( unsigned HOST_WIDE_INT ) size <= g_switch_value ) return true ;


<s> if ( ! isTypeLegal ( Ty , VT ) ) return false ; if ( ! TLI . hasStandaloneRem ( VT ) ) { return false ; } RTLIB :: Libcall LC = RTLIB :: UNKNOWN_LIBCALL ; if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I8 : RTLIB :: UREM_I8 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I16 : RTLIB :: UREM_I16 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I32 : RTLIB :: UREM_I32 ; else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I64 : RTLIB :: UREM_I64 ;

else if ( VT == <STR_LIT> ) LC = isSigned ? RTLIB :: SREM_I128 : RTLIB :: UREM_I128 ;


<s> static SDValue LowerLabelRef ( SDValue HiPart , SDValue LoPart , bool isPIC , SelectionDAG & DAG ) { EVT PtrVT = HiPart . getValueType ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDLoc DL ( HiPart ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiPart , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , LoPart , Zero ) ; if ( isPIC ) Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , DL , PtrVT ) , Hi ) ;

return DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( Val ) ) ;


<s> bool Is64Bit = Subtarget . is64Bit ( ) ; MVT SPTy = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result ; if ( ! Lower ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned SPReg = TLI . getStackPointerRegisterToSaveRestore ( ) ; assert ( SPReg && <STR_LIT> <STR_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; const TargetFrameLowering & TFI = * Subtarget . getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Result = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Result = DAG . getNode ( <STR_LIT> , dl , VT , Result , DAG . getConstant ( - ( uint64_t ) Align , dl , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Result ) ; } else if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function & F = MF . getFunction ( ) ; for ( const auto & A : F . args ( ) ) { if ( A . hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } } const TargetRegisterClass * AddrRegClass = getRegClassFor ( SPTy ) ; Register Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; Result = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; } else { SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Size ) ; MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setHasWinAlloca ( true ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; Register SPReg = RegInfo -> getStackRegister ( ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , SPTy ) ; Chain = SP . getValue ( <NUM_LIT> ) ;


<s> switch ( Form ) { default : break ; case <STR_LIT> : Binary |= encodeVFPRm ( MI , <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Binary |= encodeVFPRn ( MI , <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Binary |= encodeVFPRd ( MI , <NUM_LIT> ) ; break ; } if ( Form == <STR_LIT> ) Binary |= encodeVFPRn ( MI , <NUM_LIT> ) ; else if ( Form == <STR_LIT> ) Binary |= encodeVFPRm ( MI , <NUM_LIT> ) ; emitWordLE ( Binary ) ;


<s> Operands . push_back ( <STR_LIT> ( Name , NameLoc ) ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ;


<s> static const std :: pair < const char * , RTLIB :: Libcall > NameLibcalls [ ] = { } ; for ( const auto & NameLibcall : NameLibcalls ) {

if ( NameLibcall . first != nullptr && RuntimeLibcallSignatures -> Table [ NameLibcall . second ] != unsupported ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {


<s> MachineInstrBuilder Ret = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; if ( Val != nullptr && ! isSupportedReturnType ( Val -> getType ( ) ) ) return false ; if ( ! VRegs . empty ( ) ) { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > RetInfos ; ArgInfo ArgRetInfo ( VRegs , * Val , <NUM_LIT> ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( ArgRetInfo , RetInfos , DL , F . getCallingConv ( ) ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; <ISA_LIT>OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; std :: string FuncName = F . getName ( ) . str ( ) ;

<ISA_LIT>OutgoingValueAssigner Assigner ( TLI . CCAssignFnForReturn ( ) , FuncName . c_str ( ) , true ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const {

OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ;


<s> return __builtin_mve_vcvtpq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a , __p ) ;


<s> static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_PLT , <STR_LIT> } , { MO_PIC_FLAG , <STR_LIT> } , { MO_PCREL_FLAG , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ;


<s> if ( ix86_function_regparm ( TREE_TYPE ( function ) , function ) < <NUM_LIT> ) return true ; if ( vcall_offset ) return false ;

if ( flag_pic && ! ( * targetm . binds_local_p ) ( function ) ) return false ;


<s> MI . getOperand ( FIOp ) . ChangeToImmediate ( RealOffset ) ; MI . RemoveOperand ( FIOp + <NUM_LIT> ) ; return ; case <STR_LIT> : MI . setDesc ( HII . get ( <STR_LIT> ) ) ; break ; } if ( ! HII . isValidOffset ( Opc , RealOffset , this ) ) { auto & MRI = MF . getRegInfo ( ) ; Register TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( MB , II , DL , HII . get ( <STR_LIT> ) , TmpR ) . addReg ( BP ) . addImm ( RealOffset ) ; BP = TmpR ; RealOffset = <NUM_LIT> ; IsKill = true ; } MI . getOperand ( FIOp ) . ChangeToRegister ( BP , false , false , IsKill ) ; MI . getOperand ( FIOp + <NUM_LIT> ) . ChangeToImmediate ( RealOffset ) ;


<s> static bool ShouldXformToMOVHLPS ( ShuffleVectorSDNode * Op ) { if ( Op -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i + <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i + <NUM_LIT> ) ) return false ; return true ;


<s> auto & MRI = * MIRBuilder . getMRI ( ) ; const RegClassOrRegBank & RegClassOrBank = MRI . getRegClassOrRegBank ( Dst ) ; unsigned Size ; if ( const auto * RC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ) Size = TRI . getRegSizeInBits ( * RC ) ; else Size = MRI . getType ( Dst ) . getSizeInBits ( ) ; assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; static const unsigned OpcTable [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> } ; unsigned Opc = OpcTable [ Size == <NUM_LIT> ] ; auto CSINC = MIRBuilder . buildInstr ( Opc , { Dst } , { Src1 , Src2 } ) . addImm ( Pred ) ; constrainSelectedInstRegOperands ( * CSINC , TII , TRI , RBI ) ;


<s> if ( ! VT . isVector ( ) ) return ! isa < ConstantSDNode > ( Y ) && hasAndNotCompare ( Y ) ;

if ( ! Subtarget . hasSSE1 ( ) || VT . getSizeInBits ( ) < <NUM_LIT> ) return false ;


<s> case <STR_LIT> : Limit = <NUM_LIT> ; break ; case <STR_LIT> : Limit = <NUM_LIT> ; break ; case <STR_LIT> : Limit = <NUM_LIT> ; break ; } for ( unsigned i = SIndex + <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { int NewOffset = MemOps [ i ] . Offset ; const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isNotVFP && RegNum > PRegNum ) || ( ( Count < Limit ) && RegNum == PRegNum + <NUM_LIT> ) ) && ( ! STI -> isSwift ( ) || isNotVFP || Count != <NUM_LIT> || ! ( PRegNum & <NUM_LIT> ) ) ) { Offset += Size ; PRegNum = RegNum ; ++ Count ; } else { BaseKill = Loc -> killsRegister ( Base ) ; MergeOpsUpdate ( MBB , MemOps , SIndex , i , insertAfter , SOffset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , dl , Merges ) ; MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch , MemOps , Merges ) ; return ; } if ( MemOps [ i ] . Position > MemOps [ insertAfter ] . Position ) { insertAfter = i ; Loc = MemOps [ i ] . MBBI ; }


<s> bool <ISA_LIT>TargetLowering :: isHWFalseValue ( SDValue Op ) const { if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Op ) ) { return CFP -> getValueAPF ( ) . isZero ( ) ; }

if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) {


<s> if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && VT == XLenVT ) { auto * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } }


<s> else T = DAG . getTargetConstantPool ( CPN -> getConstVal ( ) , ValTy , Align , Offset , TF ) ; assert ( cast < ConstantPoolSDNode > ( T ) -> getTargetFlags ( ) == TF && <STR_LIT> ) ;

if ( IsPositionIndependent ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , ValTy , T ) ;


<s> if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_NoMatch ; if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = Ctx . CreateTempSymbol ( ) ; Out . EmitLabel ( Sym ) ; const MCExpr * Base = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = Value == <NUM_LIT> ? Base : MCBinaryExpr :: CreateAdd ( Base , Expr , Ctx ) ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;

Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ;


<s> bool Relaxable = false ; if ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && MCID . isBranch ( ) ) || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && MCID . isBranch ( ) ) || ( llvm :: <ISA_LIT>MCInstrInfo :: getType ( * MCII , HMI ) == <STR_LIT> && HMI . getOpcode ( ) != <STR_LIT> ) ) if ( <ISA_LIT>MCInstrInfo :: isExtendable ( * MCII , HMI ) ) { Relaxable = true ; MCOperand const & Operand = HMI . getOperand ( <ISA_LIT>MCInstrInfo :: getExtendableOp ( * MCII , HMI ) ) ;

if ( <ISA_LIT>MCInstrInfo :: mustNotExtend ( * Operand . getExpr ( ) ) ) Relaxable = false ;


<s> if ( SOff && ! RI . isSGPRClass ( MRI . getRegClass ( SOff -> getReg ( ) ) ) ) { Register SGPR = readlaneVGPRToSGPR ( SOff -> getReg ( ) , MI , MRI ) ; SOff -> setReg ( SGPR ) ; }


<s> O << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << getRegisterName ( MO1 . getReg ( ) ) ; return ; }

unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ;


<s> addPass ( create<ISA_LIT>BranchSelectionPass ( ) ) ;


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<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , InstrInfo ( ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) , TSInfo ( ) {


<s> FunctionPass * llvm :: createSgxMCPass ( ) {


<s> virtual uint32_t SMRDmemriEncode ( const MachineInstr & MI , unsigned OpNo ) const { return <NUM_LIT> ;


<s> if ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) return ( uint64_t ) ( ( INT64_C ( <NUM_LIT> ) << <NUM_LIT> ) >> ( Val & <NUM_LIT> ) ) ;

return ( ( uint64_t ) INT64_C ( - <NUM_LIT> ) >> ( Val & <NUM_LIT> ) ) ;


<s> ( const TargetRegisterClass * ) & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; assert ( VA . getValVT ( ) != <STR_LIT> && <STR_LIT> ) ; int index = ArgLocs [ i ] . getValNo ( ) ; if ( index != lastInsIndex ) { <STR_LIT> Flags = Ins [ index ] . Flags ; if ( Flags . isByVal ( ) ) { unsigned CurByValIndex = CCInfo . getInRegsParamsProcessed ( ) ; ByValStoreOffset = RoundUpToAlignment ( ByValStoreOffset , Flags . getByValAlign ( ) ) ; int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , CurOrigArg , CurByValIndex , Ins [ VA . getValNo ( ) ] . PartOffset , VA . getLocMemOffset ( ) , Flags . getByValSize ( ) , true , ByValStoreOffset , TotalArgRegsSaveSize ) ; ByValStoreOffset += Flags . getByValSize ( ) ; ByValStoreOffset = std :: min ( ByValStoreOffset , <NUM_LIT> ) ; InVals . push_back ( DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ) ; CCInfo . nextInRegsParam ( ) ; } else { unsigned FIOffset = VA . getLocMemOffset ( ) ; int FI = MFI -> CreateFixedObject ( VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> , FIOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } lastInsIndex = index ; } } } if ( isVarArg ) VarArgStyleRegisters ( CCInfo , DAG , dl , Chain , CCInfo . getNextStackOffset ( ) , TotalArgRegsSaveSize ) ;

AFI -> setArgumentStackSize ( CCInfo . getNextStackOffset ( ) ) ;


<s> bool inserted = false ; if ( MO . isDef ( ) ) inserted = RegDefs . insert ( reg ) . second ; else if ( MO . isUse ( ) ) inserted = RegUses . insert ( reg ) . second ; if ( inserted ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( reg , * PDSF . TRI ) ) ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> if ( hasInlineStackProbe ( MF ) ) return <STR_LIT> ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ;

if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return <STR_LIT> ;


<s> return ( __m64 ) __builtin_ia32_psrlw ( ( __v4hi ) __m , __count ) ;


<s> } return ; } SmallVector < unsigned , <NUM_LIT> > Args ; if ( IsCall ) { parseExternFuncCallArgs ( * Outs , Args ) ; } else { assert ( F != nullptr && <STR_LIT> ) ; parseFunctionArgs ( * Ins , Args ) ; } unsigned RegsLeft = array_lengthof ( RegList8 ) , ValNo = <NUM_LIT> ; bool UsesStack = false ; for ( unsigned i = <NUM_LIT> , pos = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i ) { unsigned Size = Args [ i ] ; if ( Size == <NUM_LIT> ) continue ; MVT LocVT = ( IsCall ) ? ( * Outs ) [ pos ] . VT : ( * Ins ) [ pos ] . VT ; if ( ! UsesStack && ( Size <= RegsLeft ) ) { const MCPhysReg * RegList = ( LocVT == <STR_LIT> ) ? RegList16 : RegList8 ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) { unsigned Reg = CCInfo . AllocateReg ( ArrayRef < MCPhysReg > ( RegList , array_lengthof ( RegList8 ) ) ) ; CCInfo . addLoc ( CCValAssign :: getReg ( ValNo ++ , LocVT , Reg , LocVT , CCValAssign :: Full ) ) ; -- RegsLeft ;


<s> if ( STI . getFeatureBits ( ) [ llvm :: <STR_LIT> ] && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) { Info = <STR_LIT> <STR_LIT> ; return true ; }


<s> MCInst MaskInst ; MaskInst . setOpcode ( <STR_LIT> ) ;

MaskInst . addOperand ( MCOperand :: createReg ( AddrReg ) ) ;


<s> return ( uint8_t ) __builtin_aarch64_uqmovnhi ( __a ) ;


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ;


<s> std :: swap ( True , False ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } } } if ( isZero ( RHS ) ) { SDValue Cond = LHS ; SDValue Zero = RHS ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( CompareVT != VT ) { True = DAG . getNode ( <STR_LIT> , DL , CompareVT , True ) ; False = DAG . getNode ( <STR_LIT> , DL , CompareVT , False ) ; } switch ( CCOpcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CCOpcode = <STR_LIT> ( CCOpcode , CompareVT == <STR_LIT> ) ; Temp = True ; True = False ; False = Temp ; break ; default : break ; } SDValue SelectNode = DAG . getNode ( <STR_LIT> , DL , CompareVT , Cond , Zero , True , False , DAG . getCondCode ( CCOpcode ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectNode ) ; } SDValue HWTrue , HWFalse ; if ( CompareVT == <STR_LIT> ) { HWTrue = DAG . getConstantFP ( <NUM_LIT> , DL , CompareVT ) ; HWFalse = DAG . getConstantFP ( <NUM_LIT> , DL , CompareVT ) ; } else if ( CompareVT == <STR_LIT> ) { HWTrue = DAG . getConstant ( - <NUM_LIT> , DL , CompareVT ) ; HWFalse = DAG . getConstant ( <NUM_LIT> , DL , CompareVT ) ; } else {


<s> unsigned int i = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( aarch64_crc_builtin_data ) ; ++ i ) { aarch64_crc_builtin_datum * d = & aarch64_crc_builtin_data [ i ] ; tree argtype = aarch64_simd_builtin_std_type ( d -> mode , qualifier_unsigned ) ;

tree ftype = build_function_type_list ( usi_type , usi_type , argtype , NULL_TREE ) ;


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ;

return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ;


<s> pInst = nullptr ; } else { flushPendingLabels ( Out ) ; Out . EmitInstruction ( Inst , STI ) ;


<s> } Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> switch ( <ISA_LIT>32FunctionMask [ functionIndex ] ) { case '1' : DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; F . addFnAttr ( <STR_LIT> ) ; break ; case '.' : doneUsingMask = true ; break ; default : break ; } functionIndex ++ ; } } else { if ( needsFP ( F ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; F . addFnAttr ( <STR_LIT> ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << F . getName ( ) << <STR_LIT> ) ; F . addFnAttr ( <STR_LIT> ) ; } } } return modified ;


<s> const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { return ; } else if ( IS_VTX ( Desc ) ) { uint64_t InstWord01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t InstWord2 = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ) { InstWord2 |= <NUM_LIT> << <NUM_LIT> ; } Emit ( InstWord01 , OS ) ; Emit ( InstWord2 , OS ) ; Emit ( ( uint32_t ) <NUM_LIT> , OS ) ; } else if ( IS_TEX ( Desc ) ) { int64_t Sampler = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t SrcSelect [ <NUM_LIT> ] = { MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) , MI . getOperand ( <NUM_LIT> ) . getImm ( ) } ; int64_t Offsets [ <NUM_LIT> ] = { MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> } ; uint64_t Word01 = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint32_t Word2 = Sampler << <NUM_LIT> | SrcSelect [ ELEMENT_X ] << <NUM_LIT> | SrcSelect [ ELEMENT_Y ] << <NUM_LIT> | SrcSelect [ ELEMENT_Z ] << <NUM_LIT> | SrcSelect [ ELEMENT_W ] << <NUM_LIT> | Offsets [ <NUM_LIT> ] << <NUM_LIT> | Offsets [ <NUM_LIT> ] << <NUM_LIT> | Offsets [ <NUM_LIT> ] << <NUM_LIT> ; Emit ( Word01 , OS ) ; Emit ( Word2 , OS ) ; Emit ( ( uint32_t ) <NUM_LIT> , OS ) ; } else { uint64_t Inst = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) && ( ( Desc . TSFlags & <STR_LIT> ) || Desc . TSFlags & <STR_LIT> ) ) {

uint64_t ISAOpCode = Inst & ( <NUM_LIT> << <NUM_LIT> ) ;


<s> if ( rclass == CCREGS ) return mode == BImode ; if ( mode == PDImode || mode == V2PDImode ) return regno == REG_A0 || regno == REG_A1 ;

if ( mode == DImode ) return regno < REG_M3 ;


<s> EVT EltVT = VecVT . getVectorElementType ( ) ; unsigned InsNumElts = InsVT . getVectorNumElements ( ) ; unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; SDLoc SL ( Op ) ; for ( unsigned I = <NUM_LIT> ; I != InsNumElts ; ++ I ) { SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Ins , DAG . getConstant ( I , SL , <STR_LIT> ) ) ;

Vec = DAG . getNode ( <STR_LIT> , SL , VecVT , Vec , Elt , DAG . getConstant ( IdxVal + I , SL , <STR_LIT> ) ) ;


<s> const <ISA_LIT>Section * SHAREDUDATASection ( ) const { return SHAREDUDATASection_ ;


<s> SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> getAlignment ( ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , OffsetPtr , LD -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; return Result ; } if ( InDouble . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( InDouble . getOperand ( <NUM_LIT> ) ) ) { SDValue BV = InDouble . getOperand ( <NUM_LIT> ) ; bool BVSwap = BV . getOpcode ( ) == <STR_LIT> ; while ( ( BV . getOpcode ( ) == <STR_LIT> || BV . getOpcode ( ) == <STR_LIT> ) && ( BV . getValueType ( ) == <STR_LIT> || BV . getValueType ( ) == <STR_LIT> ) ) { BVSwap = BV . getOpcode ( ) == <STR_LIT> ; BV = BV . getOperand ( <NUM_LIT> ) ; } if ( BV . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned Offset = InDouble . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( BV . getOpcode ( ) == <STR_LIT> ) { SDValue Op0 = BV . getOperand ( Offset ) ; SDValue Op1 = BV . getOperand ( Offset + <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) && BVSwap ) std :: swap ( Op0 , Op1 ) ; return DCI . DAG . getMergeValues ( { Op0 , Op1 } , SDLoc ( N ) ) ; } SDValue Op0 , Op1 ; while ( BV . getOpcode ( ) == <STR_LIT> ) {

if ( isa < ConstantSDNode > ( BV . getOperand ( <NUM_LIT> ) ) ) {


<s> if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( VT . isVector ( ) && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; } if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ;


<s> if ( canGuaranteeTCO ( CalleeCC , getTargetMachine ( ) . Options . GuaranteedTailCallOpt ) ) return CCMatch ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } assert ( ( ! isVarArg || CalleeCC == CallingConv :: C ) && <STR_LIT> ) ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , true ) ) ; for ( const CCValAssign & ArgLoc : ArgLocs ) if ( ! ArgLoc . isRegLoc ( ) ) return false ; } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , CCAssignFnForCall ( CalleeCC , isVarArg ) , CCAssignFnForCall ( CallerCC , isVarArg ) ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( Subtarget -> hasCustomCallingConv ( ) ) { TRI -> UpdateCustomCallPreservedMask ( MF , & CallerPreserved ) ; TRI -> UpdateCustomCallPreservedMask ( MF , & CalleePreserved ) ; } if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } if ( Outs . empty ( ) ) return true ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; const <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;

if ( llvm :: any_of ( ArgLocs , [ ] ( CCValAssign & A ) {


<s> if ( isThumb1 ) return false ; const MachineOperand & BaseOP = MI -> getOperand ( <NUM_LIT> ) ; unsigned Base = BaseOP . getReg ( ) ; bool BaseKill = BaseOP . isKill ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; unsigned Opcode = MI -> getOpcode ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( MI -> getOperand ( i ) . getReg ( ) == Base ) return false ; int Bytes = getLSMultipleTransferSize ( MI ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; <STR_LIT> Mode = getLoadStoreMultipleSubMode ( Opcode ) ; if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else if ( Mode == <STR_LIT> && Offset == - Bytes ) { Mode = <STR_LIT> ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != Bytes ) && ( ( Mode != <STR_LIT> && Mode != <STR_LIT> ) || Offset != - Bytes ) ) {

if ( ! STI -> hasMinSize ( ) || ! BaseKill ) return false ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false ;


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : { MachineFunction * MF = BB -> getParent ( ) ; auto * FuncInfo = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FuncInfo -> addAllocaAdjustInst ( MI ) ; return BB ; }

default : llvm_unreachable ( <STR_LIT> ) ;


<s> static bool hasArgumentDef ( unsigned Reg , const MachineRegisterInfo & MRI ) {

for ( const auto & Def : MRI . def_instructions ( Reg ) ) if ( <STR_LIT> ( Def . getOpcode ( ) ) ) return true ;


<s> FunctionPass * createTargetRegisterAllocator ( bool Optimized ) override { return createGreedyRegisterAllocator ( ) ;


<s> bool <ISA_LIT>InstrInfo :: ReverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; Cond . front ( ) = MachineOperand :: CreateImm ( ! Cond . front ( ) . getImm ( ) ) ;


return ( ( vec_double2 ) ( si_dfm ( ( qword ) ( a ) , ( qword ) ( b ) ) ) ) ;


<s> virtual void emitARM64WinCFIContext ( ) {


<s> bool <ISA_LIT>EarlyIfConversion :: usesUndefVReg ( const MachineInstr * MI ) const { for ( ConstMIOperands MO ( MI ) ; MO . isValid ( ) ; ++ MO ) { if ( ! MO -> isReg ( ) || ! MO -> isUse ( ) ) continue ;


<s> int Offset = SignExtend32 < <NUM_LIT> > ( Insn >> <NUM_LIT> ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> if ( ( GET_CODE ( c ) == UNSPEC && ( XINT ( c , <NUM_LIT> ) == UNSPEC_TLS_OFF || XINT ( c , <NUM_LIT> ) == UNSPEC_TLS_IE ) ) || ( GET_CODE ( c ) == PLUS && GET_CODE ( XEXP ( c , <NUM_LIT> ) ) == UNSPEC && ( XINT ( XEXP ( c , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TLS_OFF || XINT ( XEXP ( c , <NUM_LIT> ) , <NUM_LIT> ) == ARC_UNSPEC_GOTOFFPC ) ) ) { arc_output_pic_addr_const ( file , c , <NUM_LIT> ) ; break ; } gcc_assert ( GET_CODE ( c ) == PLUS ) ; gcc_assert ( GET_CODE ( XEXP ( c , <NUM_LIT> ) ) == SYMBOL_REF ) ; gcc_assert ( GET_CODE ( XEXP ( c , <NUM_LIT> ) ) == CONST_INT ) ;

output_address ( VOIDmode , XEXP ( addr , <NUM_LIT> ) ) ;


<s> static void mapping ( IO & YamlIO , <ISA_LIT>FunctionInfo & MFI ) { YamlIO . mapOptional ( <STR_LIT> , MFI . CFGStackified , false ) ;


<s> EVT PackedInVT = getPackedSVEVectorVT ( InVT . getVectorElementType ( ) ) ; if ( InVT != PackedInVT ) Op = DAG . getNode ( <STR_LIT> , DL , PackedInVT , Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , PackedVT , Op ) ; if ( VT != PackedVT ) Op = DAG . getNode ( <STR_LIT> , DL , VT , Op ) ; return Op ;


<s> O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ) { O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << ImmOffs * <NUM_LIT> ; }


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const { if ( lowerLongBranch ( MI , OutMI ) ) return ;

OutMI . setOpcode ( MI -> getOpcode ( ) ) ;


<s> case <ISA_LIT>Subtarget :: O64 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: N32 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: N64 : return <STR_LIT> ; case <ISA_LIT>Subtarget :: EABI : return <STR_LIT> ; default : break ; }


<s> switch ( Subtarget -> getTargetABI ( ) ) {


<s> int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBSizes [ MBB -> getNumber ( ) ] -= delta ; MachineBasicBlock * SplitBB = next ( MachineFunction :: iterator ( MBB ) ) ; AdjustBBOffsetsAfter ( SplitBB , - delta ) ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = next ( MachineFunction :: iterator ( MBB ) ) ; DOUT << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ;

unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ;


return __builtin_mve_vcvtmq_m_uv4si ( __arm_vuninitializedq_u32 ( ) , __a , __p ) ;


<s> OS << <STR_LIT> ; Mem . Base -> print ( OS ) ; OS << <STR_LIT> ; OS << * Mem . Off ; OS << <STR_LIT> ; break ; case k_RegisterIndex : OS << <STR_LIT> << RegIdx . Index << <STR_LIT> << RegIdx . Kind << <STR_LIT> << StringRef ( RegIdx . Tok . Data , RegIdx . Tok . Length ) << <STR_LIT> ; break ; case k_Token : OS << getToken ( ) ; break ; case k_RegList : OS << <STR_LIT> ; for ( auto Reg : ( * RegList . List ) ) OS << Reg << <STR_LIT> ; OS << <STR_LIT> ; break ; case k_RegPair : OS << <STR_LIT> << RegIdx . Index << <STR_LIT> << RegIdx . Index + <NUM_LIT> << <STR_LIT> ; break ;


<s> return new <ISA_LIT>LoadStoreOptimizer ( TM ) ;


<s> if ( I == MBB . begin ( ) ) break ; -- I ; TargetInstrDesc desc = I -> getDesc ( ) ; if ( desc . hasDelaySlot ( ) || desc . isBranch ( ) || isDelayFiller ( MBB , I ) || desc . isCall ( ) || desc . isReturn ( ) || desc . isBarrier ( ) || desc . hasUnmodeledSideEffects ( ) ) break ; if ( hasImmInstruction ( I ) || delayHasHazard ( I , slot ) ) continue ; return I ; }


<s> return ( poly8x16_t ) __builtin_neon_vdup_lanev16qi ( ( int8x8_t ) __a , __b ) ;


<s> LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } else if ( SRVK == MCSymbolRefExpr :: VK_TLSLDM ) { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } else { LEA . setOpcode ( <STR_LIT> ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; LEA . addOperand ( MCOperand :: CreateExpr ( symRef ) ) ; LEA . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } EmitAndCountInstruction ( LEA ) ; if ( needsPadding ) { EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) ) ;


<s> bool isDecl = GV -> isDeclaration ( ) || GV -> hasAvailableExternallyLinkage ( ) ; if ( GV -> hasHiddenVisibility ( ) && ( ! isDecl && ! GV -> hasCommonLinkage ( ) ) ) return false ;

return ! isStatic && ( isDecl || GV -> isWeakForLinker ( ) ) ;


<s> bool GCNPassConfig :: addPreISel ( ) { <ISA_LIT>PassConfig :: addPreISel ( ) ; addPass ( create<ISA_LIT>LateCodeGenPreparePass ( ) ) ; if ( EnableAtomicOptimizations ) { addPass ( create<ISA_LIT>AtomicOptimizerPass ( ) ) ; } addPass ( & <ISA_LIT>UnifyDivergentExitNodesID ) ; if ( ! LateCFGStructurize ) {


<s> InsertNOPLoad = false ; FixFSMULD = false ; ReplaceFMULS = false ; FixAllFDIVSQRT = false ; DetectRoundChange = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ; return * this ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : MF ( MF ) , SRetReturnReg ( <NUM_LIT> ) , GlobalBaseReg ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , InArgFIRange ( std :: make_pair ( - <NUM_LIT> , <NUM_LIT> ) ) , OutArgFIRange ( std :: make_pair ( - <NUM_LIT> , <NUM_LIT> ) ) , GPFI ( <NUM_LIT> ) , DynAllocFI ( <NUM_LIT> ) , MaxCallFrameSize ( <NUM_LIT> ) , EmitNOAT ( false ) {


<s> unsigned <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) { if ( Kind != TTI :: SK_Reverse && Kind != TTI :: SK_Alternate ) return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; if ( Kind == TTI :: SK_Reverse ) { static const CostTblEntry < <STR_LIT> > NEONShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Tp ) ; int Idx = CostTableLookup ( NEONShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx == - <NUM_LIT> ) return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; return LT . first * NEONShuffleTbl [ Idx ] . Cost ; } if ( Kind == TTI :: SK_Alternate ) { static const CostTblEntry < <STR_LIT> > NEONAltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Tp ) ; int Idx = CostTableLookup ( NEONAltShuffleTbl , <STR_LIT> , LT . second ) ;


<s> if ( for_return != <NUM_LIT> || GET_MODE_SIZE ( mode ) >= <NUM_LIT> || COMPLEX_MODE_P ( mode ) || GET_MODE_SIZE ( mode ) < <NUM_LIT> ) return mode ; return SImode ;


<s> bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; else { const char * Symbol = S -> getSymbol ( ) ; <ISA_LIT>16IntrinsicHelperType IntrinsicFind = { Symbol , <STR_LIT> } ; const <STR_LIT> * Signature = <STR_LIT> ( Symbol ) ; if ( ! IsPICCall && ( Signature && ( FuncInfo -> StubsNeeded . find ( Symbol ) == FuncInfo -> StubsNeeded . end ( ) ) ) ) { FuncInfo -> StubsNeeded [ Symbol ] = Signature ; if ( <NUM_LIT> || ( Signature -> RetSig != <STR_LIT> ) ) FuncInfo -> setSaveS2 ( ) ; } const <ISA_LIT>16IntrinsicHelperType * Helper = std :: lower_bound ( std :: begin ( <ISA_LIT>16IntrinsicHelper ) , std :: end ( <ISA_LIT>16IntrinsicHelper ) , IntrinsicFind ) ; if ( Helper != std :: end ( <ISA_LIT>16IntrinsicHelper ) && * Helper == IntrinsicFind ) { <ISA_LIT>16HelperFunction = Helper -> Helper ; Need<ISA_LIT>16Helper = true ; LookupHelper = false ; } } } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , G -> getGlobal ( ) -> getName ( ) . data ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ; } if ( LookupHelper ) <ISA_LIT>16HelperFunction = get<ISA_LIT>16HelperFunction ( CLI . RetTy , CLI . getArgs ( ) , Need<ISA_LIT>16Helper ) ; } SDValue JumpTarget = Callee ; if ( IsPICCall || ! GlobalOrExternal ) { unsigned V0Reg = <STR_LIT> ; if ( Need<ISA_LIT>16Helper ) { RegsToPass . push_front ( std :: make_pair ( V0Reg , Callee ) ) ;

JumpTarget = DAG . getExternalSymbol ( <ISA_LIT>16HelperFunction , getPointerTy ( ) ) ;


<s> return ELF :: R_<ISA_LIT>_32_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_I ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_PCREL_LO12_S ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GOT_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_TLS_GD_HI20 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_JAL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_JUMP ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_RVC_BRANCH ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL_PLT ; } } switch ( Kind ) { default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_1 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_2 : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return ELF :: R_<ISA_LIT>_NONE ; case FK_Data_4 :

if ( Expr -> getKind ( ) == MCExpr :: Target && cast < <ISA_LIT>MCExpr > ( Expr ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_32_PCREL ) return ELF :: R_<ISA_LIT>_32_PCREL ;


<s> unsigned InstSize = HII -> getSize ( * MII ) ; if ( MII -> isMetaInstruction ( ) ) { ++ MII ; continue ; } if ( isHardwareLoop ( * MII ) ) { assert ( MII -> getOperand ( <NUM_LIT> ) . isMBB ( ) && <STR_LIT> ) ; MachineBasicBlock * TargetBB = MII -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; unsigned Diff = AbsoluteDifference ( InstOffset , BlockToInstOffset [ TargetBB ] ) ; if ( Diff > MaxLoopRange ) { useExtLoopInstr ( MF , MII ) ; MII = MBB . erase ( MII ) ; Changed = true ; } else {


<s> if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( TT . size ( ) >= <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ; if ( TT . size ( ) == <NUM_LIT> && std :: string ( TT . begin ( ) , TT . begin ( ) + <NUM_LIT> ) == <STR_LIT> ) return <NUM_LIT> ;


<s> static inline int andcosts ( rtx x ) { int i ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) != CONST_INT ) return <NUM_LIT> ; i = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( TARGET_SHMEDIA ) { if ( ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && CONST_OK_FOR_I16 ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) || EXTRA_CONSTRAINT_C16 ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; else return <NUM_LIT> ; } if ( i == <NUM_LIT> || i == <NUM_LIT> ) return <NUM_LIT> ; if ( CONST_OK_FOR_K08 ( i ) ) return <NUM_LIT> ; if ( CONST_OK_FOR_I08 ( i ) ) return <NUM_LIT> ;


<s> MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: iterator MBBI = MI . getIterator ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; assert ( ( TRI -> getRegSizeInBits ( Addr . Base . LoReg , * MRI ) == <NUM_LIT> || Addr . Base . LoSubReg ) && <STR_LIT> ) ; assert ( ( TRI -> getRegSizeInBits ( Addr . Base . HiReg , * MRI ) == <NUM_LIT> || Addr . Base . HiSubReg ) && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineOperand OffsetLo = createRegOrImm ( static_cast < int32_t > ( Addr . Offset ) , MI ) ; MachineOperand OffsetHi = createRegOrImm ( static_cast < int32_t > ( Addr . Offset >> <NUM_LIT> ) , MI ) ; unsigned CarryReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned DeadCarryReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned DestSub0 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned DestSub1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * LoHalf = BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . addReg ( Addr . Base . LoReg , <NUM_LIT> , Addr . Base . LoSubReg ) . add ( OffsetLo ) ; ( void ) LoHalf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; LoHalf -> dump ( ) ; ) ; MachineInstr * HiHalf = BuildMI ( * MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . addReg ( Addr . Base . HiReg , <NUM_LIT> , Addr . Base . HiSubReg ) . add ( OffsetHi ) . addReg ( CarryReg , RegState :: Kill ) ; ( void ) HiHalf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; HiHalf -> dump ( ) ; ) ; unsigned FullDestReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * FullBase = BuildMI ( * MBB , MBBI , DL , TII -> get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; ( void ) FullBase ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; FullBase -> dump ( ) ; dbgs ( ) << <STR_LIT> ; ) ; return FullDestReg ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> int AddrOffset = <STR_LIT> ( Descl . TSFlags ) ; assert ( AddrOffset != - <NUM_LIT> && <STR_LIT> ) ;


<s> const MCExpr * Val ; if ( getParser ( ) . parseExpression ( Val , End ) ) return <NUM_LIT> ; unsigned Length = <NUM_LIT> , Size = <NUM_LIT> , Type = <NUM_LIT> ; if ( const MCSymbolRefExpr * SymRef = dyn_cast < MCSymbolRefExpr > ( Val ) ) { const MCSymbol & Sym = SymRef -> getSymbol ( ) ; bool IsVarDecl ; if ( ! SemaCallback -> LookupInlineAsmIdentifier ( Sym . getName ( ) , NULL , Length , Size , Type , IsVarDecl ) ) return ErrorOperand ( Start , <STR_LIT> ) ; } unsigned CVal ; switch ( OpKind ) { default : llvm_unreachable ( <STR_LIT> ) ; case IOK_LENGTH : CVal = Length ; break ;


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ;


<s> StringRef getPrefetchName ( ) const { assert ( Kind == k_Prefetch && <STR_LIT> ) ; return StringRef ( Prefetch . Data , Prefetch . Length ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TargetMachine ) : SelectionDAGISel ( TargetMachine ) {


<s> unsigned Dim = UINT_MAX ; switch ( F -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : IdQuery = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Dim = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : IdQuery = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Dim = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : IdQuery = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : Dim = <NUM_LIT> ; break ; default : break ; } if ( Dim <= <NUM_LIT> ) {

if ( auto Node = Kernel -> getMetadata ( <STR_LIT> ) ) if ( Node -> getNumOperands ( ) == <NUM_LIT> ) MinSize = MaxSize = mdconst :: extract < ConstantInt > ( Node -> getOperand ( Dim ) ) -> getZExtValue ( ) ;


return ( uint16x4_t ) ( __a > <NUM_LIT> ) ;


<s> static bool SupportedVectorShiftWithBaseAmnt ( MVT VT , const <ISA_LIT>Subtarget & Subtarget , unsigned Opcode ) {

return SupportedVectorShiftWithImm ( VT , Subtarget , Opcode ) ;


<s> const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( FuncInfo -> isEntryFunction ( ) ) { return TFI -> hasFP ( MF ) ? FuncInfo -> getFrameOffsetReg ( ) : Register ( ) ;


<s> <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> return ; } if ( llvm :: isSurface ( * GVar ) ) { O << <STR_LIT> << llvm :: getSurfaceName ( * GVar ) << <STR_LIT> ; return ; } if ( GVar -> isDeclaration ( ) ) { emitPTXGlobalVariable ( GVar , O ) ; O << <STR_LIT> ; return ; } if ( llvm :: isSampler ( * GVar ) ) { O << <STR_LIT> << llvm :: getSamplerName ( * GVar ) ; const Constant * Initializer = NULL ; if ( GVar -> hasInitializer ( ) ) Initializer = GVar -> getInitializer ( ) ; const ConstantInt * CI = NULL ; if ( Initializer ) CI = dyn_cast < ConstantInt > ( Initializer ) ; if ( CI ) { unsigned sample = CI -> getZExtValue ( ) ; O << <STR_LIT> ; for ( int i = <NUM_LIT> , addr = ( ( sample & __CLK_ADDRESS_MASK ) >> __CLK_ADDRESS_BASE ) ; i < <NUM_LIT> ; i ++ ) { O << <STR_LIT> << i << <STR_LIT> ; switch ( addr ) { case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; } O << <STR_LIT> ; } O << <STR_LIT> ; switch ( ( sample & __CLK_FILTER_MASK ) >> __CLK_FILTER_BASE ) { case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; default : O << <STR_LIT> ; break ; } if ( ! ( ( sample & __CLK_NORMALIZED_MASK ) >> __CLK_NORMALIZED_BASE ) ) { O << <STR_LIT> ; } O << <STR_LIT> ; } O << <STR_LIT> ; return ; } if ( GVar -> hasPrivateLinkage ( ) ) { if ( ! strncmp ( GVar -> getName ( ) . data ( ) , <STR_LIT> , <NUM_LIT> ) ) return ; if ( ! strncmp ( GVar -> getName ( ) . data ( ) , <STR_LIT> , <NUM_LIT> ) ) return ; if ( GVar -> use_empty ( ) ) return ; } const Function * demotedFunc = <NUM_LIT> ; if ( ! processDemoted && canDemoteGlobalVar ( GVar , demotedFunc ) ) { O << <STR_LIT> << GVar -> getName ( ) . str ( ) << <STR_LIT> ; if ( localDecls . find ( demotedFunc ) != localDecls . end ( ) ) localDecls [ demotedFunc ] . push_back ( GVar ) ; else { std :: vector < const GlobalVariable * > temp ;


<s> return new <ISA_LIT>AsmBackend ( STI . getTargetTriple ( ) . getOS ( ) ) ;


<s> if ( GET_CODE ( x ) == LABEL_REF ) { switch ( aarch64_cmodel ) { case AARCH64_CMODEL_LARGE : return SYMBOL_FORCE_TO_MEM ; case AARCH64_CMODEL_TINY_PIC : case AARCH64_CMODEL_TINY : return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL_PIC : case AARCH64_CMODEL_SMALL : return SYMBOL_SMALL_ABSOLUTE ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_cmodel == AARCH64_CMODEL_LARGE ) return SYMBOL_FORCE_TO_MEM ; if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( SYMBOL_REF_WEAK ( x ) || INTVAL ( offset ) < - <NUM_LIT> || INTVAL ( offset ) > <NUM_LIT> ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) || ! IN_RANGE ( INTVAL ( offset ) , HOST_WIDE_INT_C ( - <NUM_LIT> ) , HOST_WIDE_INT_C ( <NUM_LIT> ) ) ) return SYMBOL_FORCE_TO_MEM ;


<s> for ( MachineBasicBlock & MBB : * MF ) { for ( MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; LLVM_DEBUG ( MI . dump ( ) ) ; if ( ! MI . allDefsAreDead ( ) ) { DebugLoc Empty ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( DL != Empty ) report_fatal_error ( <STR_LIT> + std :: to_string ( DL . getLine ( ) ) + <STR_LIT> , false ) ;

else report_fatal_error ( <STR_LIT> , false ) ;


<s> const unsigned * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned nonvolatileRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , InstrInfo ( ) , RegInfo ( ) , TLInfo ( TM , * this ) {


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> rtx_code_label * label ; rtx x ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( model ) ; bool use_acquire = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_release ( model ) ) ; bool use_release = TARGET_HAVE_LDACQ && ! ( is_mm_relaxed ( model ) || is_mm_consume ( model ) || is_mm_acquire ( model ) ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ; else old_out = new_out ; value = simplify_gen_subreg ( wmode , value , mode , <NUM_LIT> ) ; arm_emit_load_exclusive ( mode , old_out , mem , use_acquire ) ; switch ( code ) { case SET : new_out = value ; break ; case NOT : x = gen_rtx_AND ( wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } case PLUS : if ( mode == DImode ) { emit_move_insn ( new_out , old_out ) ; if ( code == PLUS ) x = gen_adddi3 ( new_out , new_out , value ) ; else x = gen_subdi3 ( new_out , new_out , value ) ; emit_insn ( x ) ; break ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ;


<s> return ( uint16x4_t ) __builtin_aarch64_ashlv4hi ( ( int16x4_t ) __a , __b ) ;


<s> case ADDRESS_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , size ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_POST_INC_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_POST_MODIFY_LO_REG_IMM3U : snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; break ; case ADDRESS_FP_IMM7U :

output_asm_insn ( <STR_LIT> , operands ) ;


<s> <ISA_LIT>MachineFunctionInfo ( const MachineFunction & MF ) {


<s> void LLVMInitializePowerPCAsmPrinter ( ) {

TargetRegistry :: RegisterAsmPrinter ( The<ISA_LIT>32Target , create<ISA_LIT>AsmPrinterPass ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : return - <NUM_LIT> ;


<s> void DecodeZeroExtendMask ( unsigned SrcScalarBits , unsigned DstScalarBits , unsigned NumDstElts , bool IsAnyExtend , SmallVectorImpl < int > & Mask ) { unsigned Scale = DstScalarBits / SrcScalarBits ;

assert ( SrcScalarBits < DstScalarBits && <STR_LIT> ) ;


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ;

unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ;


<s> for ( const CalleeSavedInfo & CSI : MF . getFrameInfo ( ) -> getCalleeSavedInfo ( ) ) if ( CSI . getReg ( ) == <STR_LIT> ) return true ;


<s> if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return TypeSplitVector ; if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getVectorElementType ( ) != <STR_LIT> ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> ResTy = parseRegOrImm ( Operands ) ; if ( ResTy == MatchOperand_Success ) return ResTy ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { const auto & Tok = Parser . getTok ( ) ; SMLoc S = Tok . getLoc ( ) ; const MCExpr * Expr = nullptr ; if ( ! Parser . parseExpression ( Expr ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateExpr ( this , Expr , S ) ) ; return MatchOperand_Success ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( this , Tok . getString ( ) , Tok . getLoc ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {


<s> static __inline vec_short8 spu_sub ( signed short a , vec_short8 b ) { return ( ( vec_short8 ) ( si_sfhi ( ( qword ) b , ( short ) a ) ) ) ;


<s> MCWasmObjectTargetWriter * MOTW = new <ISA_LIT>WasmObjectWriter ( Is64Bit ) ; return createWasmObjectWriter ( MOTW , OS ) ;


<s> unsigned getTIDReg ( ) const { return TIDReg ;


<s> switch ( GET_MODE_CLASS ( mode ) ) { default : break ; case MODE_CC : units = GET_MODE_SIZE ( CCmode ) ; break ; case MODE_FLOAT : if ( ( TARGET_SSE && mode == TFmode ) || ( TARGET_80387 && mode == XFmode ) || ( ( TARGET_80387 || TARGET_SSE2 ) && mode == DFmode ) || ( ( TARGET_80387 || TARGET_SSE ) && mode == SFmode ) ) units = GET_MODE_SIZE ( mode ) ;


<s> if ( ! MEM_P ( rtl ) ) return ; symbol = XEXP ( rtl , <NUM_LIT> ) ; if ( GET_CODE ( symbol ) != SYMBOL_REF ) return ; flags = SYMBOL_REF_FLAGS ( symbol ) ; if ( TREE_CODE ( decl ) == VAR_DECL && DECL_THREAD_LOCAL_P ( decl ) ) flags &= ~ SYMBOL_FLAG_HAS_BLOCK_INFO ; SYMBOL_REF_FLAGS ( symbol ) = flags ; symname = XSTR ( symbol , <NUM_LIT> ) ; if ( decl && DECL_P ( decl ) && DECL_EXTERNAL ( decl ) && TREE_PUBLIC ( decl ) && ( ( TREE_CODE ( decl ) == VAR_DECL && ! DECL_THREAD_LOCAL_P ( decl ) ) || TREE_CODE ( decl ) == FUNCTION_DECL ) && symname [ strlen ( symname ) - <NUM_LIT> ] != ']' ) {

char * newname = ( char * ) alloca ( strlen ( symname ) + <NUM_LIT> ) ;


<s> if ( desc . TSFlags & <STR_LIT> ) { if ( op . getImm ( ) & <NUM_LIT> ) return <STR_LIT> ; else return <STR_LIT> ; } if ( op . getImm ( ) & <NUM_LIT> ) { if ( IS_BSIDE ( desc . TSFlags ) ) return <STR_LIT> ; else return <STR_LIT> ;


<s> unsigned NumElts = SizeInBits / EltSizeInBits ; unsigned SrcEltSizeInBits = VT . getScalarSizeInBits ( ) ; unsigned NumSrcElts = SizeInBits / SrcEltSizeInBits ; APInt UndefBits ( SizeInBits , <NUM_LIT> ) ; APInt MaskBits ( SizeInBits , <NUM_LIT> ) ; auto SplitBitData = [ & ] ( ) { if ( UndefBits . getBoolValue ( ) && ! AllowUndefs ) return false ; UndefElts = SmallBitVector ( NumElts , false ) ; EltBits . resize ( NumElts , APInt ( EltSizeInBits , <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { APInt UndefEltBits = UndefBits . lshr ( i * EltSizeInBits ) ; UndefEltBits = UndefEltBits . zextOrTrunc ( EltSizeInBits ) ; if ( UndefEltBits . isAllOnesValue ( ) ) { UndefElts [ i ] = true ; continue ; } APInt Bits = MaskBits . lshr ( i * EltSizeInBits ) ; Bits = Bits . zextOrTrunc ( EltSizeInBits ) ; EltBits [ i ] = Bits . getZExtValue ( ) ; } return true ; } ; auto ExtractConstantBits = [ SizeInBits ] ( const Constant * Cst , APInt & Mask , APInt & Undefs ) { if ( ! Cst ) return false ; unsigned CstSizeInBits = Cst -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( isa < UndefValue > ( Cst ) ) { Mask = APInt :: getNullValue ( SizeInBits ) ; Undefs = APInt :: getLowBitsSet ( SizeInBits , CstSizeInBits ) ; return true ; } if ( auto * CInt = dyn_cast < ConstantInt > ( Cst ) ) { Mask = CInt -> getValue ( ) . zextOrTrunc ( SizeInBits ) ; Undefs = APInt :: getNullValue ( SizeInBits ) ; return true ; } if ( auto * CFP = dyn_cast < ConstantFP > ( Cst ) ) { Mask = CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . zextOrTrunc ( SizeInBits ) ; Undefs = APInt :: getNullValue ( SizeInBits ) ; return true ; } return false ; } ; if ( <STR_LIT> ( Op . getNode ( ) ) ) { for ( unsigned i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) { const SDValue & Src = Op . getOperand ( i ) ; if ( Src . isUndef ( ) ) { APInt Undefs = APInt :: getLowBitsSet ( SizeInBits , SrcEltSizeInBits ) ; UndefBits |= Undefs . shl ( i * SrcEltSizeInBits ) ; continue ; } auto * Cst = cast < ConstantSDNode > ( Src ) ;

APInt Bits = Cst -> getAPIntValue ( ) . zextOrTrunc ( SrcEltSizeInBits ) ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( <ISA_LIT>AsmPrinter & asmprinter ) : AsmPrinter ( asmprinter ) {


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ;


<s> static int mep_compatible_reg_class ( int r1 , int r2 ) { if ( GR_REGNO_P ( r1 ) && GR_REGNO_P ( r2 ) ) return <NUM_LIT> ;

if ( CR_REGNO_P ( r1 ) && CR_REGNO_P ( r2 ) ) return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : retType = <STR_LIT> :: V128 ; break ; case <STR_LIT> : retType = <STR_LIT> :: ExceptRef ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( MachineBasicBlock & MBB : reverse ( MF ) ) { for ( MachineInstr & MI : reverse ( MBB ) ) { if ( MI . isPosition ( ) || MI . isDebugInstr ( ) ) continue ; if ( MI . getOpcode ( ) == <STR_LIT> ) { EndToBegin [ & MI ] -> getOperand ( <NUM_LIT> ) . setImm ( int32_t ( retType ) ) ; continue ; }


<s> if ( NewOpc ) { const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; MCID = & TII -> get ( NewOpc ) ; assert ( MCID -> getNumOperands ( ) == MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> && <STR_LIT> ) ; MI -> setDesc ( * MCID ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , true ) ) ; } unsigned ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ; if ( ! MI -> hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false ; bool deadCPSR = false ; for ( unsigned i = MCID -> getNumOperands ( ) , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ;

if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) {


<s> switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> :


<s> MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst , MAI ) ;