<s> if ( Pred == <STR_LIT> ) { ++ MBIter ; continue ; } MachineInstrBuilder MIBuilder = BuildMI ( Block , MBIter , dl , TII -> get ( <STR_LIT> ) ) ; MachineBasicBlock :: iterator VPSTInsertPos = MIBuilder . getInstr ( ) ; int VPTInstCnt = <NUM_LIT> ; <STR_LIT> NextPred ; do { ++ MBIter ; NextPred = getVPTInstrPredicate ( * MBIter , PredReg ) ; } while ( NextPred != <STR_LIT> && NextPred == Pred && ++ VPTInstCnt < <NUM_LIT> ) ; switch ( VPTInstCnt ) { case <NUM_LIT> : MIBuilder . addImm ( VPTMaskValue :: T ) ; break ; case <NUM_LIT> : MIBuilder . addImm ( VPTMaskValue :: TT ) ; break ; case <NUM_LIT> : MIBuilder . addImm ( VPTMaskValue :: TTT ) ; break ; case <NUM_LIT> : MIBuilder . addImm ( VPTMaskValue :: TTTT ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } ; MachineInstr * LastMI = & * MBIter ;

finalizeBundle ( Block , VPSTInsertPos . getInstrIterator ( ) , ++ LastMI -> getIterator ( ) ) ;


<s> AsmToken :: TokenKind <ISA_LIT>AsmParser :: getTokenKind ( ) const {


<s> Match . push_back ( MatchInstruction ( Operands , Inst , ErrorInfo , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ) ; if ( Match . back ( ) == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfo ; } if ( UnsizedMemOp ) UnsizedMemOp -> Mem . Size = <NUM_LIT> ; if ( Match . back ( ) == Match_MnemonicFail ) { return Error ( IDLoc , <STR_LIT> + Mnemonic + <STR_LIT> , Op . getLocRange ( ) , MatchingInlineAsm ) ; } unsigned NumSuccessfulMatches = std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Success ) ; if ( NumSuccessfulMatches == <NUM_LIT> ) { if ( MatchedSize && isParsingInlineAsm ( ) && isParsingIntelSyntax ( ) ) for ( AsmRewrite & AR : * InstInfo -> AsmRewrites ) if ( ( AR . Loc . getPointer ( ) == UnsizedMemOp -> StartLoc . getPointer ( ) ) && ( AR . Kind == AOK_SizeDirective ) ) AR . Val = MatchedSize ; if ( ! MatchingInlineAsm ) while ( processInstruction ( Inst , Operands ) ) ; Inst . setLoc ( IDLoc ) ; if ( ! MatchingInlineAsm ) EmitInstruction ( Inst , Operands , Out ) ; Opcode = Inst . getOpcode ( ) ; return false ; } else if ( NumSuccessfulMatches > <NUM_LIT> ) { assert ( UnsizedMemOp && <STR_LIT> ) ; return Error ( UnsizedMemOp -> getStartLoc ( ) , <STR_LIT> + Mnemonic + <STR_LIT> , UnsizedMemOp -> getLocRange ( ) , MatchingInlineAsm ) ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MissingFeature ) == <NUM_LIT> ) { ErrorInfo = ErrorInfoMissingFeature ; return ErrorMissingFeature ( IDLoc , ErrorInfoMissingFeature , MatchingInlineAsm ) ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_InvalidOperand ) == <NUM_LIT> ) {

return Error ( IDLoc , <STR_LIT> , EmptyRange , MatchingInlineAsm ) ;


<s> case TYPE_R16 : case TYPE_R32 : case TYPE_R64 : case TYPE_Rv : case TYPE_MM64 : case TYPE_XMM : case TYPE_XMM32 : case TYPE_XMM64 : case TYPE_XMM128 : case TYPE_XMM256 : case TYPE_XMM512 : case TYPE_VK1 : case TYPE_VK8 : case TYPE_VK16 : case TYPE_DEBUGREG : case TYPE_CONTROLREG : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M256 : case TYPE_M512 :


<s> MemRefBegin += <STR_LIT> ( Desc ) ; const MachineOperand * BaseOp = & MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! BaseOp -> isReg ( ) ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ;

if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) != <STR_LIT> ) return false ;


<s> case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerVSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ;

case <STR_LIT> : return LowerMUL ( Op , DAG ) ;


<s> <ISA_LIT>RepoObjectWriter :: ~ <ISA_LIT>RepoObjectWriter ( ) {


<s> gcc_assert ( compute_now == ( pic_reg != NULL_RTX ) ) ; if ( ! crtl -> uses_pic_offset_table || compute_now ) { gcc_assert ( can_create_pseudo_p ( ) || ( pic_reg != NULL_RTX && REG_P ( pic_reg ) && GET_MODE ( pic_reg ) == Pmode ) ) ; if ( arm_pic_register != INVALID_REGNUM && ! compute_now && ! ( TARGET_THUMB1 && arm_pic_register > LAST_LO_REGNUM ) ) { if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = gen_rtx_REG ( Pmode , arm_pic_register ) ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) crtl -> uses_pic_offset_table = <NUM_LIT> ; } else { rtx_insn * seq , * insn ; if ( pic_reg == NULL_RTX ) pic_reg = gen_reg_rtx ( Pmode ) ; if ( ! cfun -> machine -> pic_reg ) cfun -> machine -> pic_reg = pic_reg ; if ( current_ir_type ( ) != IR_GIMPLE || currently_expanding_to_rtl ) { crtl -> uses_pic_offset_table = <NUM_LIT> ; start_sequence ( ) ; if ( TARGET_THUMB1 && arm_pic_register != INVALID_REGNUM && arm_pic_register > LAST_LO_REGNUM && ! compute_now ) emit_move_insn ( cfun -> machine -> pic_reg , gen_rtx_REG ( Pmode , arm_pic_register ) ) ; else arm_load_pic_register ( <NUM_LIT> , pic_reg ) ; seq = get_insns ( ) ; end_sequence ( ) ;

for ( insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) INSN_LOCATION ( insn ) = prologue_location ;


<s> <ISA_LIT>Gfx6CacheControl ( const GCNSubtarget & ST ) : <ISA_LIT>CacheControl ( ST ) {


<s> const MCOperand MO1 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << '[' << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) ;


<s> if ( V . getValueSizeInBits ( ) == <NUM_LIT> ) return V ; assert ( V . getValueSizeInBits ( ) == <NUM_LIT> ) ; SDValue SubRegIdx = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubVal = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , V , SubRegIdx ) , <NUM_LIT> ) ;


<s> int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ;

unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( MPO . getAddrSpace ( ) , <NUM_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return static_cast < <STR_LIT> > ( MI . getOperand ( MI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCPU ( SMLoc L ) { StringRef CPU = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; getTargetStreamer ( ) . emitTextAttribute ( <STR_LIT> , CPU ) ; if ( ! getSTI ( ) . isCPUStringValid ( CPU ) ) { Error ( L , <STR_LIT> ) ; return false ; } MCSubtargetInfo & STI = copySTI ( ) ;


<s> unsigned RegHi = RI . getSubReg ( Reg , AMDGPU :: sub1 ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_GETPC_B64 ) , Reg ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_ADD_U32 ) , RegLo ) . addReg ( RegLo ) . addTargetIndex ( AMDGPU :: TI_CONSTDATA_START ) . addReg ( AMDGPU :: SCC , RegState :: Define | RegState :: Implicit ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_ADDC_U32 ) , RegHi ) . addReg ( RegHi ) . addImm ( <NUM_LIT> ) . addReg ( AMDGPU :: SCC , RegState :: Define | RegState :: Implicit ) . addReg ( AMDGPU :: SCC , RegState :: Implicit ) ; MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: SGPR_USE : MI -> eraseFromParent ( ) ; break ;


<s> MVT VT = Ext -> getSimpleValueType ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) ) return SDValue ( ) ; MVT WideVT = Ext -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT SelVT = Sel . getSimpleValueType ( ) ; unsigned SelElts = SelVT . getVectorNumElements ( ) ; unsigned CastedElts = WideVT . getVectorNumElements ( ) ; unsigned ExtIdx = cast < ConstantSDNode > ( Ext -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( SelElts % CastedElts == <NUM_LIT> ) { ExtIdx *= ( SelElts / CastedElts ) ; } else if ( CastedElts % SelElts == <NUM_LIT> ) { unsigned IndexDivisor = CastedElts / SelElts ; if ( ExtIdx % IndexDivisor != <NUM_LIT> ) return SDValue ( ) ; ExtIdx /= IndexDivisor ; } else { llvm_unreachable ( <STR_LIT> ) ; }

unsigned NarrowingFactor = WideVT . getSizeInBits ( ) / VT . getSizeInBits ( ) ;


<s> case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int Offset = VA . getLocMemOffset ( ) ; assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( VA . getLocVT ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue SPN = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , <STR_LIT> ) ; SDValue OffsetN = DAG . getIntPtrConstant ( Offset ) ; OffsetN = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SPN , OffsetN ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , OffsetN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) {

Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ;


<s> p = strchr ( name , '@' ) ; if ( p ) return ggc_alloc_string ( name , p - name ) ; return name ;


<s> std :: vector < std :: string > max_ge ( Ax a , StepZIDS bs ) {

return D ( <STR_LIT> , R ( a ) , <STR_LIT> , <STR_LIT> , bs ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> SDValue Ops [ <NUM_LIT> ] = { Chain , FPSIdx } ; SDVTList VTs = DAG . getVTList ( IntVT ) ; return DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ;


<s> <ISA_LIT>SSELevel = SSE42 ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { <ISA_LIT>SSELevel = AVX ; ToggleFeature ( <STR_LIT> ) ; } bool IsIntel = memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; bool IsAMD = ! IsIntel && memcmp ( text . c , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ; if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasPCLMUL = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasFMA = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasMOVBE = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasPOPCNT = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasAES = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasF16C = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasRDRAND = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasCmpxchg16b = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel || IsAMD ) { unsigned Family = <NUM_LIT> ; unsigned Model = <NUM_LIT> ; <ISA_LIT>_MC :: DetectFamilyModel ( EAX , Family , Model ) ; if ( IsAMD || ( Family == <NUM_LIT> && Model >= <NUM_LIT> ) ) { IsBTMemSlow = true ; ToggleFeature ( <STR_LIT> ) ; } if ( Family == <NUM_LIT> && Model == <NUM_LIT> ) { IsUAMemFast = true ; ToggleFeature ( <STR_LIT> ) ; } if ( Family == <NUM_LIT> && ( Model == <NUM_LIT> || Model == <NUM_LIT> || Model == <NUM_LIT> ) ) { <ISA_LIT>ProcFamily = IntelAtom ; UseLeaForSP = true ; ToggleFeature ( <STR_LIT> ) ; } unsigned MaxExtLevel ; <ISA_LIT>_MC :: GetCpuIDAndInfo ( <NUM_LIT> , & MaxExtLevel , & EBX , & ECX , & EDX ) ; if ( MaxExtLevel >= <NUM_LIT> ) { <ISA_LIT>_MC :: GetCpuIDAndInfo ( <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ; if ( ( EDX >> <NUM_LIT> ) & <NUM_LIT> ) { Has<ISA_LIT>_64 = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasLZCNT = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsAMD ) { if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasSSE4A = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasXOP = true ; ToggleFeature ( <STR_LIT> ) ;


<s> if ( ( II . OutNeeds & StateWQM ) && ! ( II . Needs & StateWQM ) && ( MI . isBranch ( ) || MI . isTerminator ( ) || MI . getOpcode ( ) == <STR_LIT> ) ) { Instructions [ & MI ] . Needs = StateWQM ; II . Needs = StateWQM ; } BI . Needs |= II . Needs ; if ( ( BI . InNeeds | II . Needs ) != BI . InNeeds ) { BI . InNeeds |= II . Needs ; Worklist . push_back ( & MBB ) ; } if ( const MachineInstr * PrevMI = MI . getPrevNode ( ) ) { char InNeeds = II . Needs | II . OutNeeds ; if ( ! PrevMI -> isPHI ( ) ) { InstrInfo & PrevII = Instructions [ PrevMI ] ; if ( ( PrevII . OutNeeds | InNeeds ) != PrevII . OutNeeds ) { PrevII . OutNeeds |= InNeeds ; Worklist . push_back ( PrevMI ) ; } } } assert ( II . Needs != ( StateWQM | StateExact ) ) ; if ( II . Needs != StateWQM ) return ; for ( const MachineOperand & Use : MI . uses ( ) ) { if ( ! Use . isReg ( ) || ! Use . isUse ( ) ) continue ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Use . getReg ( ) ) ) continue ; for ( const MachineOperand & Def : MRI -> def_operands ( Use . getReg ( ) ) ) { const MachineInstr * DefMI = Def . getParent ( ) ; InstrInfo & DefII = Instructions [ DefMI ] ; if ( DefII . Needs != <NUM_LIT> ) continue ; DefII . Needs = StateWQM ;


<s> void TagStoreEdit :: emitUnrolled ( MachineBasicBlock :: iterator InsertI ) { const <ISA_LIT>InstrInfo * TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; const int64_t kMinOffset = - <NUM_LIT> * <NUM_LIT> ; const int64_t kMaxOffset = <NUM_LIT> * <NUM_LIT> ; Register BaseReg = FrameReg ; int64_t BaseRegOffsetBytes = FrameRegOffset . getBytes ( ) ; if ( BaseRegOffsetBytes < kMinOffset || BaseRegOffsetBytes + ( Size - Size % <NUM_LIT> ) > kMaxOffset ) { Register ScratchReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( * MBB , InsertI , DL , ScratchReg , BaseReg , { BaseRegOffsetBytes , <STR_LIT> } , TII ) ; BaseReg = ScratchReg ; BaseRegOffsetBytes = <NUM_LIT> ; } MachineInstr * LastI = nullptr ; while ( Size ) { int64_t InstrSize = ( Size > <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;

unsigned Opcode = InstrSize == <NUM_LIT> ? ( ZeroData ? <STR_LIT> : <STR_LIT> ) : ( ZeroData ? <STR_LIT> : <STR_LIT> ) ;


<s> struct ShuffleSourceInfo { SDValue Vec ; unsigned MinElt ; unsigned MaxElt ; SDValue ShuffleVec ; int WindowBase ; int WindowScale ; bool operator == ( SDValue OtherVec ) { return Vec == OtherVec ; } ShuffleSourceInfo ( SDValue Vec ) : Vec ( Vec ) , MinElt ( UINT_MAX ) , MaxElt ( <NUM_LIT> ) , ShuffleVec ( Vec ) , WindowBase ( <NUM_LIT> ) , WindowScale ( <NUM_LIT> ) { } } ; SmallVector < ShuffleSourceInfo , <NUM_LIT> > Sources ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . isUndef ( ) ) continue ; else if ( V . getOpcode ( ) != <STR_LIT> ) { return SDValue ( ) ; } else if ( ! isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { return SDValue ( ) ; } SDValue SourceVec = V . getOperand ( <NUM_LIT> ) ; auto Source = find ( Sources , SourceVec ) ; if ( Source == Sources . end ( ) ) Source = Sources . insert ( Sources . end ( ) , ShuffleSourceInfo ( SourceVec ) ) ; unsigned EltNo = cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Source -> MinElt = std :: min ( Source -> MinElt , EltNo ) ; Source -> MaxElt = std :: max ( Source -> MaxElt , EltNo ) ; } if ( Sources . size ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT SmallestEltTy = VT . getVectorElementType ( ) ; for ( auto & Source : Sources ) { EVT SrcEltTy = Source . Vec . getValueType ( ) . getVectorElementType ( ) ; if ( SrcEltTy . bitsLT ( SmallestEltTy ) ) SmallestEltTy = SrcEltTy ; } unsigned ResMultiplier = VT . getScalarSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; NumElts = VT . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; EVT ShuffleVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SmallestEltTy , NumElts ) ; for ( auto & Src : Sources ) { EVT SrcVT = Src . ShuffleVec . getValueType ( ) ; if ( SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) continue ; EVT EltVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = VT . getSizeInBits ( ) / EltVT . getSizeInBits ( ) ; EVT DestVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumSrcElts ) ; if ( SrcVT . getSizeInBits ( ) < VT . getSizeInBits ( ) ) { if ( <NUM_LIT> * SrcVT . getSizeInBits ( ) != VT . getSizeInBits ( ) ) return SDValue ( ) ;

Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getUNDEF ( Src . ShuffleVec . getValueType ( ) ) ) ;


<s> if ( F . hasFnAttribute ( Attribute :: OptimizeNone ) ) { F . removeAttribute ( AttributeList :: FunctionIndex , Attribute :: OptimizeNone ) ; return true ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCInstFragment * DF , const MCAsmLayout & Layout ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> std :: advance ( MBBI , CSI . size ( ) ) ; for ( const auto & Entry : CSI ) { int64_t Offset = MFI . getObjectOffset ( Entry . getFrameIdx ( ) ) ; Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , RI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFP ( MF ) ) { if ( STI . isRegisterReservedByUser ( FPReg ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; adjustReg ( MBB , MBBI , DL , FPReg , SPReg , StackSize - RVFI -> getVarArgsSaveSize ( ) , MachineInstr :: FrameSetup ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( FPReg , true ) , - RVFI -> getVarArgsSaveSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;


<s> return ( poly8x16x2_t ) { vtrn1q_p8 ( a , b ) , vtrn2q_p8 ( a , b ) } ;


<s> if ( reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ! TARGET_SINGLE_PIC_BASE ) { if ( TARGET_TOC && TARGET_MINIMAL_TOC && ( crtl -> calls_eh_return || df_regs_ever_live_p ( reg ) || ! constant_pool_empty_p ( ) ) ) return true ;

if ( ( DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN ) && flag_pic ) return true ;


<s> return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( Result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return Result ; } Result = decodeInstruction ( DecoderTableThumb232 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return checkDecodedInstruction ( MI , Size , Address , CS , Insn32 , Result ) ; } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { Result = decodeInstruction ( DecoderTableVFP32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; UpdateThumbVFPPredicate ( Result , MI ) ; return Result ; } } Result = decodeInstruction ( DecoderTableVFPV832 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { Result = decodeInstruction ( DecoderTableNEONDup32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { uint32_t NEONLdStInsn = Insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { uint32_t NEONDataInsn = Insn32 ; NEONDataInsn &= <NUM_LIT> ; NEONDataInsn |= ( NEONDataInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONDataInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTableNEONData32 , MI , NEONDataInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } uint32_t NEONCryptoInsn = Insn32 ; NEONCryptoInsn &= <NUM_LIT> ; NEONCryptoInsn |= ( NEONCryptoInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONCryptoInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTablev8Crypto32 , MI , NEONCryptoInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } uint32_t NEONv8Insn = Insn32 ; NEONv8Insn &= <NUM_LIT> ;

Result = decodeInstruction ( DecoderTablev8NEON32 , MI , NEONv8Insn , Address , this , STI ) ;


<s> static bool nds32_ict_const_p ( rtx x ) { if ( GET_CODE ( x ) == CONST ) { x = XEXP ( x , <NUM_LIT> ) ;

return nds32_indirect_call_referenced_p ( x ) ;


<s> if ( offsettable_p && ! rs6000_legitimate_offset_address_p ( mode , addr , strict_p , true ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; else if ( reg_reg_p && ! legitimate_indexed_address_p ( addr , strict_p ) ) stack = replace_equiv_address ( stack , copy_addr_to_reg ( addr ) ) ; }


<s> static rtx s390_execute_label ( rtx insn ) { if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == PARALLEL && GET_CODE ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) == UNSPEC && XINT ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_EXECUTE ) return XVECEXP ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; return NULL_RTX ;


<s> return frv_function_arg_1 ( cum , mode , type , named , false ) ;


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ;

MCOperand MCOp = LowerOperand ( MI , MO , AP ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectBRIND ( SDNode * N ) { SDLoc dl ( N ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Addr = N -> getOperand ( <NUM_LIT> ) ; if ( Addr -> getOpcode ( ) != <STR_LIT> ) return nullptr ; unsigned IntNo = cast < ConstantSDNode > ( Addr -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo != <STR_LIT> ) return nullptr ; SDValue nextAddr = Addr -> getOperand ( <NUM_LIT> ) ; SDValue CheckEventChainOut ( Addr . getNode ( ) , <NUM_LIT> ) ; if ( ! CheckEventChainOut . use_empty ( ) ) { SDValue CheckEventChainIn = Addr -> getOperand ( <NUM_LIT> ) ; SDValue NewChain = replaceInChain ( CurDAG , Chain , CheckEventChainOut , CheckEventChainIn ) ; if ( ! NewChain . getNode ( ) ) return nullptr ; Chain = NewChain ; } SDValue constOne = getI32Imm ( <NUM_LIT> , dl ) ; SDValue Glue = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , constOne , Chain ) , <NUM_LIT> ) ; Glue = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , constOne , Glue ) , <NUM_LIT> ) ; if ( nextAddr -> getOpcode ( ) == <STR_LIT> && nextAddr -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> ) {

return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , nextAddr -> getOperand ( <NUM_LIT> ) , Glue ) ;


<s> return srcBlkInfo ? srcBlkInfo -> sccNum : INVALIDSCCNUM ;


<s> xcpu2 ( unsigned i , unsigned j , unsigned k ) : tripleChange ( false , true , true , i , j , k ) {


<s> LLVMContext & Context = F . getParent ( ) -> getContext ( ) ; for ( Function :: iterator BI = F . begin ( ) , BE = F . end ( ) ; BI != BE ; ++ BI ) { for ( BasicBlock :: iterator II = BI -> begin ( ) , IE = BI -> end ( ) ; II != IE ; ++ II ) { if ( LoadInst * load = dyn_cast < LoadInst > ( II ) ) { if ( load -> hasOneUse ( ) == false ) continue ; if ( TD -> getTypeStoreSize ( load -> getType ( ) ) < MaxAggrCopySize ) continue ; User * use = * ( load -> use_begin ( ) ) ; if ( StoreInst * store = dyn_cast < StoreInst > ( use ) ) { if ( store -> getOperand ( <NUM_LIT> ) != load ) continue ; aggrLoads . push_back ( load ) ; } } else if ( MemTransferInst * intr = dyn_cast < MemTransferInst > ( II ) ) { Value * len = intr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) { if ( len_int -> getZExtValue ( ) >= MaxAggrCopySize ) { aggrMemcpys . push_back ( intr ) ; } } else { aggrMemcpys . push_back ( intr ) ; } } else if ( MemSetInst * memsetintr = dyn_cast < MemSetInst > ( II ) ) { Value * len = memsetintr -> getLength ( ) ; if ( ConstantInt * len_int = dyn_cast < ConstantInt > ( len ) ) {


<s> void addITCondCodeInvOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( unsigned ( <STR_LIT> ( getCondCode ( ) ) ) ) ) ;


<s> return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ;

CmpMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( KnownUndef [ i ] ) Mask [ i ] = SM_SentinelUndef ; else if ( ResolveKnownZeros && KnownZero [ i ] ) Mask [ i ] = SM_SentinelZero ; }


<s> bool <ISA_LIT>DAGToDAGISel :: detectOrAndInsertion ( SDValue & Op , uint64_t InsertMask ) const { if ( Op . getOpcode ( ) != <STR_LIT> ) return false ; auto * MaskNode = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! MaskNode ) return false ; uint64_t AndMask = MaskNode -> getZExtValue ( ) ; if ( InsertMask & AndMask ) return false ; uint64_t Used = allOnes ( Op . getValueType ( ) . getSizeInBits ( ) ) ; if ( Used != ( AndMask | InsertMask ) ) { APInt KnownZero , KnownOne ; CurDAG -> computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne ) ; if ( Used != ( AndMask | InsertMask | KnownZero . getZExtValue ( ) ) ) return false ;


<s> return ( int32x4_t ) __builtin_neon_vqrdmulh_nv4si ( __a , ( __builtin_neon_si ) __b ) ;


<s> DebugLoc dl = I -> getDebugLoc ( ) ; const uint16_t * SubReg = TM . getRegisterInfo ( ) -> getSubRegisters ( DstReg ) ; BuildMI ( MBB , I , dl , Mtc1Tdd , * SubReg ) . addReg ( LoReg ) ; BuildMI ( MBB , I , dl , Mtc1Tdd , * ( SubReg + <NUM_LIT> ) ) . addReg ( HiReg ) ;


<s> const MCInstrDesc & MCID2 = TII -> get ( AddSubOpc ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; unsigned TmpReg = MRI -> createVirtualRegister ( TII -> getRegClass ( MCID1 , <NUM_LIT> , TRI , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , MCID1 , TmpReg ) . addReg ( Src1Reg , getKillRegState ( Src1Kill ) ) . addReg ( Src2Reg , getKillRegState ( Src2Kill ) ) ; if ( HasLane ) MIB . addImm ( LaneImm ) ; MIB . addImm ( Pred ) . addReg ( PredReg ) ; MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , MCID2 ) . addReg ( DstReg , getDefRegState ( true ) | getDeadRegState ( DstDead ) ) ; if ( NegAcc ) { bool AccKill = MRI -> hasOneNonDBGUse ( AccReg ) ; MIB . addReg ( TmpReg , getKillRegState ( true ) ) . addReg ( AccReg , getKillRegState ( AccKill ) ) ; } else { MIB . addReg ( AccReg ) . addReg ( TmpReg , getKillRegState ( true ) ) ; } MIB . addImm ( Pred ) . addReg ( PredReg ) ; DEBUG ( { dbgs ( ) << <STR_LIT> << * MI ; dbgs ( ) << <STR_LIT> ; MachineBasicBlock :: iterator MII = MI ; MII = std :: prev ( MII ) ; MachineInstr & MI2 = * MII ; MII = std :: prev ( MII ) ; MachineInstr & MI1 = * MII ;


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> FeatureBitset Features = coalesceFeatures ( M ) ; std :: string FeatureStr = getFeatureString ( Features ) ; WasmTM -> setTargetFeatureString ( FeatureStr ) ; for ( auto & F : M ) replaceFeatures ( F , FeatureStr ) ; bool StrippedAtomics = false ; bool StrippedTLS = false ; if ( ! Features [ <STR_LIT> ] ) StrippedAtomics = stripAtomics ( M ) ; if ( ! Features [ <STR_LIT> ] ) StrippedTLS = stripThreadLocals ( M ) ; if ( StrippedAtomics && ! StrippedTLS ) stripThreadLocals ( M ) ; else if ( StrippedTLS && ! StrippedAtomics ) stripAtomics ( M ) ;

recordFeatures ( M , Features , StrippedAtomics || StrippedTLS ) ;


<s> if ( STI . isThumb1Only ( ) ) { assert ( ( is<ISA_LIT>LowRegister ( DestReg ) || isVirtualRegister ( DestReg ) ) && <STR_LIT> ) ; return emitThumb1LoadConstPool ( MBB , MBBI , dl , DestReg , SubIdx , Val , Pred , PredReg , MIFlags ) ; }

return emitThumb2LoadConstPool ( MBB , MBBI , dl , DestReg , SubIdx , Val , Pred , PredReg , MIFlags ) ;


<s> const char * getPassName ( ) const override {


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; const DataLayout * TD = MF . getTarget ( ) . getDataLayout ( ) ; bool HasFP = hasFP ( MF ) ; int stackGrowth = - TD -> getPointerSize ( <NUM_LIT> ) ; int64_t saveAreaOffset = ( HasFP ? <NUM_LIT> : <NUM_LIT> ) * stackGrowth ;


<s> <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) ;

<ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 ( ) ;


} else Record<ISA_LIT>Relocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue ) ;


<s> void <ISA_LIT>MCInstLower :: Initialize ( MCContext * C ) { Ctx = C ;


<s> if ( CanUseNEON && Op . isMemset ( ) && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return LLT :: scalar ( <NUM_LIT> ) ; if ( Op . size ( ) >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return LLT :: scalar ( <NUM_LIT> ) ; if ( Op . size ( ) >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> , Align ( <NUM_LIT> ) ) ) return LLT :: scalar ( <NUM_LIT> ) ;


<s> OutStreamer -> EmitAssignment ( SymGlob , MCConstantExpr :: create ( ATy -> getNumElements ( ) , OutContext ) ) ; if ( GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) || GV -> hasCommonLinkage ( ) ) { OutStreamer -> EmitSymbolAttribute ( SymGlob , MCSA_Weak ) ; }


<s> bool <ISA_LIT>EarlyIfConversion :: isValidCandidate ( const MachineBasicBlock * B ) const { if ( ! B ) return true ; if ( B -> isEHPad ( ) || B -> hasAddressTaken ( ) ) return false ; if ( B -> succ_empty ( ) ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugInstr ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask2 [ <NUM_LIT> ] ) ; MVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpHi ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpHi ) ;


<s> if ( isZeroVector ( Op1 ) ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op0 , N -> getOperand ( <NUM_LIT> ) ) ; unsigned SwappedCond = getSwappedCondition ( Cond ) ; if ( isValidMVECond ( SwappedCond , VT . isFloatingPoint ( ) ) ) { if ( isZeroVector ( Op0 ) ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op1 , DCI . DAG . getConstant ( SwappedCond , dl , <STR_LIT> ) ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> && Op1 -> getOpcode ( ) != <STR_LIT> ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op1 , Op0 , DCI . DAG . getConstant ( SwappedCond , dl , <STR_LIT> ) ) ; } return SDValue ( ) ;


<s> emit_cmp_and_jump_insns ( align_rtx , const2_rtx , GTU , NULL , Pmode , <NUM_LIT> , align_3_label ) ; } else { align_rtx = expand_binop ( Pmode , and_optab , scratch1 , const2_rtx , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( align_rtx , const0_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_4_label ) ; } mem = change_address ( src , QImode , out ) ; emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( ix86_gen_add3 ( out , out , const1_rtx ) ) ; if ( align != <NUM_LIT> ) { emit_label ( align_2_label ) ; emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( ix86_gen_add3 ( out , out , const1_rtx ) ) ; emit_label ( align_3_label ) ; } emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( ix86_gen_add3 ( out , out , const1_rtx ) ) ; } emit_label ( align_4_label ) ; mem = change_address ( src , SImode , out ) ; emit_move_insn ( scratch , mem ) ; emit_insn ( ix86_gen_add3 ( out , out , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_addsi3 ( tmpreg , scratch , GEN_INT ( - <NUM_LIT> ) ) ) ; emit_insn ( gen_one_cmplsi2 ( scratch , scratch ) ) ; emit_insn ( gen_andsi3 ( tmpreg , tmpreg , scratch ) ) ; emit_insn ( gen_andsi3 ( tmpreg , tmpreg , gen_int_mode ( <NUM_LIT> , SImode ) ) ) ; emit_cmp_and_jump_insns ( tmpreg , const0_rtx , EQ , <NUM_LIT> , SImode , <NUM_LIT> , align_4_label ) ; if ( TARGET_CMOVE ) {


<s> void <ISA_LIT>InstPrinter :: printMBUFOffset ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getImm ( ) ) { O << <STR_LIT> ; printU16ImmDecOperand ( MI , OpNo , O ) ;


<s> for ( const uint16_t ( & Row ) [ <NUM_LIT> ] : ReplaceableInstrsAVX512DQ ) if ( Row [ domain - <NUM_LIT> ] == opcode || ( domain == <NUM_LIT> && Row [ <NUM_LIT> ] == opcode ) ) return Row ; return nullptr ;


<s> if ( VT -> getNumElements ( ) == <NUM_LIT> && DL . getTypeSizeInBits ( VT -> getElementType ( ) ) == <NUM_LIT> ) { switch ( Kind ) { case TTI :: SK_Broadcast : case TTI :: SK_Reverse : case TTI :: SK_PermuteSingleSrc :


<s> static DecodeStatus DecodeAddiGroupBranch ( MCInst & MI , InsnType insn , uint64_t Address , const void * Decoder ) { llvm_unreachable ( <STR_LIT> ) ; return MCDisassembler :: Success ;


<s> static bool readInstruction32 ( ArrayRef < uint8_t > Bytes , uint64_t Address , uint64_t & Size , uint32_t & Insn ) { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return false ; } Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return true ;


<s> return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ; case <NUM_LIT> : return RB . getID ( ) == <STR_LIT> ? & <STR_LIT> :


<s> bool GCNTTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ; const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ;

FeatureBitset RealCallerBits = CallerBits & ~ InlineFeatureIgnoreList ;


<s> if ( ! info . valid_p ( ) ) continue ; rtx_insn * rinsn = insn -> rtl ( ) ; if ( ! can_refine_vsetvl_p ( cfg_bb , info ) ) continue ; if ( vector_config_insn_p ( rinsn ) ) { m_vector_manager -> to_refine_vsetvls . add ( rinsn ) ; continue ; } rinsn = PREV_INSN ( rinsn ) ; rtx new_pat = gen_vsetvl_pat ( VSETVL_VTYPE_CHANGE_ONLY , info , NULL_RTX ) ; change_insn ( rinsn , new_pat ) ;


<s> if ( V . getOpcode ( ) == <STR_LIT> && ( isNullConstant ( V . getOperand ( <NUM_LIT> ) ) || V . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { if ( SDValue Not = IsNOT ( V . getOperand ( <NUM_LIT> ) , DAG ) ) { Not = DAG . getBitcast ( V . getOperand ( <NUM_LIT> ) . getValueType ( ) , Not ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Not ) , V . getValueType ( ) , Not , V . getOperand ( <NUM_LIT> ) ) ; } } SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( collectConcatOps ( V . getNode ( ) , CatOps ) ) { for ( SDValue & CatOp : CatOps ) { SDValue NotCat = IsNOT ( CatOp , DAG ) ;


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << MI ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; int stackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; int spOffset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> << <STR_LIT> << spOffset << <STR_LIT> << <STR_LIT> << stackSize << <STR_LIT> ) ; int Offset = ( ( spOffset < <NUM_LIT> ) ? ( stackSize + ( - ( spOffset + <NUM_LIT> ) ) ) : ( spOffset ) ) ; Offset += MI . getOperand ( i - <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ;

MI . getOperand ( i - <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> if ( x ) { return profile_probability :: from_reg_br_prob_note ( XINT ( x , <NUM_LIT> ) ) >= profile_probability :: even ( ) ;


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> RegisterTarget < Triple :: systemz , true > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


ret . val [ <NUM_LIT> ] = __builtin_aarch64_get_qregxiv8hf ( __o , <NUM_LIT> ) ;


<s> <ISA_LIT>ISelAddressMode ( ) : BaseType ( RegBase ) , Disp ( <NUM_LIT> ) , GV ( nullptr ) , CP ( nullptr ) , BlockAddr ( nullptr ) , ES ( nullptr ) , JT ( - <NUM_LIT> ) , Align ( <NUM_LIT> ) {


<s> void printSrcIdx32 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printSrcIdx ( MI , OpNo , O ) ;


<s> GCNIterativeScheduler :: GCNIterativeScheduler ( MachineSchedContext * C , StrategyKind S ) : BaseClass ( C , llvm :: make_unique < SchedStrategyStub > ( ) ) , Context ( C ) , Strategy ( S ) , UPTracker ( * LIS ) {


<s> return ( uint32x4_t ) __builtin_neon_vcgtv4sf ( __a , __b ) ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X ;


<s> FormalArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , CCAssignFn AssignFn ) : <ISA_LIT>IncomingValueHandler ( MIRBuilder , MRI , AssignFn ) {


<s> return acle_vector_types [ <NUM_LIT> ] [ type_suffixes [ type ] . vector_type ] ;


<s> case <STR_LIT> : TrigNode = <STR_LIT> ; break ; case <STR_LIT> : TrigNode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } SDValue TrigVal = DAG . getNode ( TrigNode , SDLoc ( Op ) , VT , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , FractPart , DAG . getConstantFP ( - <NUM_LIT> , <STR_LIT> ) ) ) ; if ( Gen >= AMDGPUSubtarget :: R700 ) return TrigVal ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , TrigVal , DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>Z80MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * <NUM_LIT> ) ;

for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; i -- ) {


<s> case MachineOperand :: MO_GlobalAddress : Symbol = AP . getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = AP . GetCPISymbol ( MO . getIndex ( ) ) ; break ; }

const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: Create ( Symbol , AP . OutContext ) ;


<s> while ( ( skip = arm_get_strip_length ( * name ) ) ) name += skip ;


<s> return const_cast < <ISA_LIT>TargetLowering * > ( & TLInfo ) ;


<s> int getMTBUFOpcode ( unsigned BaseOpc , unsigned Elements ) { const MTBUFInfo * Info = getMTBUFInfoFromBaseOpcodeAndElements ( BaseOpc , Elements ) ;

return Info ? Info -> Opcode : - <NUM_LIT> ;


<s> <ISA_LIT>InsertWaitcnts ( ) : MachineFunctionPass ( ID ) , ST ( nullptr ) , TII ( nullptr ) , TRI ( nullptr ) , MRI ( nullptr ) , MLI ( nullptr ) {


<s> HardwareLoopInfo HWLoopInfo ( L ) ; if ( ! HWLoopInfo . canAnalyze ( * LI ) ) return false ; if ( ! isHardwareLoopProfitable ( L , * SE , * AC , LibInfo , HWLoopInfo ) ) return false ; if ( ! HWLoopInfo . isHardwareLoopCandidate ( * SE , * LI , * DT ) ) return false ;


<s> else PredicateValue = PredDef -> getOperand ( DefiningValueNo ) . getImm ( ) != <NUM_LIT> ; } if ( PredicateValue != InvertedPolarity ) { I . getOperand ( PredRegLoc ) . setReg ( <STR_LIT> ) ; I . getOperand ( PredRegLoc + <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; if ( I . getOperand ( <NUM_LIT> ) . isReg ( ) && I . getOperand ( <NUM_LIT> ) . isDef ( ) && isDstFullyWritten ( I ) ) { unsigned IncomeReg = I . getOperand ( IncomeArg ) . getReg ( ) ; MachineInstr * IncomeDef = MRI -> getVRegDef ( IncomeReg ) ; if ( IncomeDef -> getOpcode ( ) != <STR_LIT> ) { Register ireg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC ; if ( ireg . isVirtual ( ) ) { RC = MRI -> getRegClass ( ireg ) ; } else { RC = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) -> getClassOfPhysicalRegister ( ireg , * TRI ) ; } unsigned Undef = MRI -> createVirtualRegister ( RC ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; BuildMI ( * ( I . getParent ( ) ) , & I , DL , TII -> get ( <STR_LIT> ) , Undef ) ; I . getOperand ( IncomeArg ) . setReg ( Undef ) ; } } ++ NumReplaced ; } else { unsigned NIn = IncomeArg ; for ( MachineOperand & D : I . defs ( ) ) { assert ( D . isReg ( ) ) ; unsigned OldReg = D . getReg ( ) ; unsigned NewReg = I . getOperand ( NIn ) . getReg ( ) ; MRI -> replaceRegWith ( OldReg , NewReg ) ; ++ NIn ; } I . eraseFromParent ( ) ;


<s> int m32c_regno_ok_for_base_p ( int regno ) { if ( regno == A0_REGNO || regno == A1_REGNO || regno >= FIRST_PSEUDO_REGISTER ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result ;


<s> if ( TUNE_SB1 ) return <NUM_LIT> ; if ( TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A ) return <NUM_LIT> ; if ( TUNE_OCTEON ) return <NUM_LIT> ;

if ( TUNE_P5600 || TUNE_I6400 ) return <NUM_LIT> ;


<s> inline ShiftOpc getAM2ShiftOpc ( unsigned AM2Opc ) {

return ( ShiftOpc ) ( ( AM2Opc >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> FOR_EACH_INSN_INFO_USE ( base_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) return false ; rtx tocrel_insn = DF_REF_INSN ( base_def_link -> ref ) ; rtx tocrel_body = PATTERN ( tocrel_insn ) ; rtx base , offset ; if ( GET_CODE ( tocrel_body ) != SET ) return false ; rtx tocrel_expr = SET_SRC ( tocrel_body ) ;

if ( GET_CODE ( tocrel_expr ) == MEM ) tocrel_expr = XEXP ( tocrel_expr , <NUM_LIT> ) ;


<s> OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( Intrn ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } EmitFunctionHeader ( ) ; EmitFunctionBody ( ) ;


<s> <STR_LIT> Mode = MFI -> getMode ( ) ; uint16_t Flags = MI . getFlags ( ) ; LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; auto One = B . buildFConstant ( S32 , <NUM_LIT> ) ; auto DenominatorScaled = B . buildIntrinsic ( <STR_LIT> , { S32 , S1 } , false ) . addUse ( RHS ) . addUse ( LHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto NumeratorScaled = B . buildIntrinsic ( <STR_LIT> , { S32 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto ApproxRcp = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( DenominatorScaled . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; auto NegDivScale0 = B . buildFNeg ( S32 , DenominatorScaled , Flags ) ; if ( ! Mode . FP32Denormals ) toggleSPDenormMode ( true , B , ST , Mode ) ; auto Fma0 = B . buildFMA ( S32 , NegDivScale0 , ApproxRcp , One , Flags ) ; auto Fma1 = B . buildFMA ( S32 , Fma0 , ApproxRcp , ApproxRcp , Flags ) ; auto Mul = B . buildFMul ( S32 , NumeratorScaled , Fma1 , Flags ) ; auto Fma2 = B . buildFMA ( S32 , NegDivScale0 , Mul , NumeratorScaled , Flags ) ; auto Fma3 = B . buildFMA ( S32 , Fma2 , Fma1 , Mul , Flags ) ; auto Fma4 = B . buildFMA ( S32 , NegDivScale0 , Fma3 , NumeratorScaled , Flags ) ; if ( ! Mode . FP32Denormals ) toggleSPDenormMode ( false , B , ST , Mode ) ; auto Fmas = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( Fma4 . getReg ( <NUM_LIT> ) ) . addUse ( Fma1 . getReg ( <NUM_LIT> ) ) . addUse ( Fma3 . getReg ( <NUM_LIT> ) ) . addUse ( NumeratorScaled . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; B . buildIntrinsic ( <STR_LIT> , Res , false ) . addUse ( Fmas . getReg ( <NUM_LIT> ) ) . addUse ( RHS ) . addUse ( LHS ) . setMIFlags ( Flags ) ; MI . eraseFromParent ( ) ;


<s> reg = gen_reg_rtx ( mode ) ; loongarch_emit_binary ( code , reg , op0 , op1 ) ; return reg ;


<s> __asm__ volatile ( <STR_LIT> : [ val ] <STR_LIT> ( __drdtime . dvalue ) , [ tid ] <STR_LIT> ( __drdtime . dtimeid ) : ) ; return __drdtime ;


<s> static bool isCFAlu ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : return true ;


<s> ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ;


<s> EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaHi ) ) ; const MCExpr * TOCDeltaLo = <ISA_LIT>MCExpr :: createLo ( TOCDeltaExpr , false , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaLo ) ) ; MCSymbol * LocalEntryLabel = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( LocalEntryLabel ) ; const MCSymbolRefExpr * LocalEntryLabelExp = MCSymbolRefExpr :: create ( LocalEntryLabel , OutContext ) ;

const MCExpr * LocalOffsetExp = MCBinaryExpr :: createSub ( LocalEntryLabelExp , GlobalEntryLabelExp , OutContext ) ;


<s> MCSymbolData & SD = getAssembler ( ) . getOrCreateSymbolData ( * Symbol ) ; MCELF :: SetType ( SD , ELF :: STT_NOTYPE ) ; MCELF :: SetBinding ( SD , ELF :: STB_LOCAL ) ; SD . setExternal ( false ) ; AssignSection ( Symbol , getCurrentSection ( ) . first ) ;

const MCExpr * Value = MCSymbolRefExpr :: Create ( Start , getContext ( ) ) ;


<s> default : break ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , RHS , LHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , RHS , LHS ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; } return SDValue ( ) ;


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( const Triple & T ) { bool is64Bit = T . getArch ( ) == Triple :: x86_64 ; bool isX32 = T . isX32 ( ) ; CodePointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; SupportsDebugInformation = true ;

ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> if ( possible_target && overlaps_input_p ( possible_target ) ) possible_target = NULL_RTX ; return get_reg_target ( ) ;


<s> return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> Register getExtInstSetReg ( unsigned SetNum ) {


<s> static SDValue PerformShuffleVMOVNCombine ( ShuffleVectorSDNode * N , SelectionDAG & DAG ) { SDValue Trunc = N -> getOperand ( <NUM_LIT> ) ; EVT VT = Trunc . getValueType ( ) ; if ( Trunc . getOpcode ( ) != <STR_LIT> || ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; SDLoc DL ( Trunc ) ; if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , false ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; else if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , true ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , false , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , false , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , true , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , true , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , false , true , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , false , true , <STR_LIT> ) ; case <STR_LIT> :

return LowerFPToInt ( MI , DL , BB , TII , false , true , true , <STR_LIT> ) ;


<s> } ; if ( ! std :: all_of ( ExitBlocks . begin ( ) , ExitBlocks . end ( ) , DominatedByBB ) ) return false ; bool MadeChange = false ; SmallVector < StoreInst * , <NUM_LIT> > Stores ;

collectStores ( CurLoop , BB , Stores ) ;


<s> if ( Op . isReg ( ) ) { printRegName ( O , Op . getReg ( ) ) ; return ; } if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; return ; } if ( Op . isExpr ( ) ) { Op . getExpr ( ) -> print ( O , & MAI ) ;


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FuncInfo -> setHasSpills ( ) ; bool NonRI = false , SpillsVRS = false ; if ( LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs , NonRI , SpillsVRS ) ) FuncInfo -> setSpillsCR ( ) ; if ( SpillsVRS ) FuncInfo -> setSpillsVRSAVE ( ) ; if ( NonRI ) FuncInfo -> setHasNonRISpills ( ) ; for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; NewMIs . back ( ) -> addMemOperand ( MF , MMO ) ;


<s> const TargetRegisterClass * SrcRC , * DstRC ; std :: tie ( SrcRC , DstRC ) = getCopyRegClasses ( MI , * TRI , MRI ) ; if ( isVGPRToSGPRCopy ( SrcRC , DstRC , * TRI ) ) { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { TII -> moveToVALU ( MI ) ; break ; } MachineInstr * DefMI = MRI . getVRegDef ( SrcReg ) ; unsigned SMovOp ; int64_t Imm ; if ( isSafeToFoldImmIntoCopy ( & MI , DefMI , TII , SMovOp , Imm ) ) { MI . getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Imm ) ; MI . addImplicitDefUseOperands ( MF ) ; MI . setDesc ( TII -> get ( SMovOp ) ) ; break ; } TII -> moveToVALU ( MI ) ; } else if ( isSGPRToVGPRCopy ( SrcRC , DstRC , * TRI ) ) { tryChangeVGPRtoSGPRinCopy ( MI , TRI , TII ) ; } break ; } case <STR_LIT> : { unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isSGPRClass ( MRI . getRegClass ( Reg ) ) ) break ; if ( MI . getNumExplicitOperands ( ) == <NUM_LIT> ) { MachineBasicBlock * MBB0 = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineBasicBlock * MBB1 = MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( ! predsHasDivergentTerminator ( MBB0 , TRI ) && ! predsHasDivergentTerminator ( MBB1 , TRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI << '\n' ) ; break ; } }

SmallSet < unsigned , <NUM_LIT> > Visited ;


<s> void <ISA_LIT>ompactAsmPrinter :: printPredicateOperand ( const MachineInstr * MI , unsigned OpNum , raw_ostream & O ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; if ( CC != <STR_LIT> ) { O << <STR_LIT> << <ISA_LIT>CCToString ( CC ) ;


<s> static bool usePackedStack ( MachineFunction & MF ) { bool HasPackedStackAttr = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ; bool CallConv = MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: GHC ; bool BackChain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; bool FramAddressTaken = MF . getFrameInfo ( ) . isFrameAddressTaken ( ) ;

if ( HasPackedStackAttr && BackChain ) report_fatal_error ( <STR_LIT> ) ;


<s> rtx msp430_eh_return_stackadj_rtx ( void ) { if ( ! cfun -> machine -> eh_stack_adjust ) { rtx sa ; sa = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; cfun -> machine -> eh_stack_adjust = sa ;


<s> static int mips_arg_partial_bytes ( cumulative_args_t cum , machine_mode mode , tree type , bool named ) {


<s> return ; case <STR_LIT> : { assert ( SDValue ( N , <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; LoadSDNode * LoadNode = cast < LoadSDNode > ( N ) ; if ( ! LoadNode -> isVolatile ( ) || LoadNode -> getMemoryVT ( ) != <STR_LIT> ) { return ; } SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) , { LoadNode -> getChain ( ) , LoadNode -> getBasePtr ( ) } , LoadNode -> getMemoryVT ( ) , LoadNode -> getMemOperand ( ) ) ; SDValue Pair = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) ) ; Results . append ( { Pair , Result . getValue ( <NUM_LIT> ) } ) ; return ; } case <STR_LIT> : ReplaceExtractSubVectorResults ( N , Results , DAG ) ; return ; case <STR_LIT> : return ; case <STR_LIT> : { EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; ConstantSDNode * CN = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ; case <STR_LIT> : { SDLoc DL ( N ) ; auto Op2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ;

auto V = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , Op2 , N -> getOperand ( <NUM_LIT> ) ) ;


<s> Channel = ElemIdx % <NUM_LIT> ; if ( ElemIdx == <NUM_LIT> ) { PtrIncr = <NUM_LIT> ; } else { PtrIncr = <NUM_LIT> ; } break ; case <NUM_LIT> : Channel = ElemIdx ; PtrIncr = <NUM_LIT> ; break ; }


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ;


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> texasru_t texasru = * _TEXASRU_PTR ( TM_buff ) ; return _TEXASRU_DISALLOWED ( texasru ) ;


StackOffset SaveOffset ( Offset , <STR_LIT> ) ;


<s> auto & HRI = * HST . getRegisterInfo ( ) ; auto & HII = * HST . getInstrInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed ; Changed = DeadCodeElimination ( MF , * MDT ) . run ( ) ; const <ISA_LIT>Evaluator HE ( HRI , MRI , HII , MF ) ; BitTracker BT ( HE , MF ) ; LLVM_DEBUG ( BT . trace ( true ) ) ; BT . run ( ) ; MachineBasicBlock & Entry = MF . front ( ) ; RegisterSet AIG ;

ConstGeneration ImmG ( BT , HII , MRI ) ;


<s> uint64_t InternalAmt = ( isDestroy || Amount ) ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = RoundUpToAlignment ( Amount , StackAlign ) ; bool HasDwarfEHHandlers = ! MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) && ! MF . getMMI ( ) . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return ; Amount -= InternalAmt ; if ( Amount ) { int Offset = isDestroy ? Amount : - Amount ; if ( ! ( MF . getFunction ( ) -> optForMinSize ( ) && adjustStackWithPops ( MBB , I , DL , Offset ) ) ) BuildStackAdjustment ( MBB , I , DL , Offset , false ) ;


<s> if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCapModeOnly_32 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ; } else { if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Insn = <STR_LIT> :: read16le ( Bytes . data ( ) ) ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32CapModeOnly_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32Only_16 , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) {


<s> Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , Cst , Cst , Cst ) ; } } else if ( VT . is256BitVector ( ) ) { if ( Subtarget -> hasInt256 ( ) ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ;

Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ;


<s> static SDValue EmitTailCallStoreRetAddr ( SelectionDAG & DAG , MachineFunction & MF , SDValue Chain , SDValue RetAddrFrIdx , EVT PtrVT , unsigned SlotSize , int FPDiff , SDLoc dl ) { if ( ! FPDiff ) return Chain ; int NewReturnAddrFI = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , ( int64_t ) FPDiff - SlotSize , false ) ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewReturnAddrFI , PtrVT ) ; Chain = DAG . getStore ( Chain , dl , RetAddrFrIdx , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( NewReturnAddrFI ) , false , false , <NUM_LIT> ) ; return Chain ;


<s> AU . addRequired < TargetTransformInfoWrapperPass > ( ) ; LegacyInlinerBase :: getAnalysisUsage ( AU ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _rdpid_u32 ( void ) { return __builtin_ia32_rdpid ( ) ;


<s> SDLoc DL ( ADDENode ) ; SDValue ACCIn = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , ADDCNode -> getOperand ( <NUM_LIT> ) , ADDENode -> getOperand ( <NUM_LIT> ) ) ; MultOpc = MultOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue MAdd = CurDAG -> getNode ( MultOpc , DL , <STR_LIT> , MultNode -> getOperand ( <NUM_LIT> ) , MultNode -> getOperand ( <NUM_LIT> ) , ACCIn ) ; if ( ! SDValue ( ADDCNode , <NUM_LIT> ) . use_empty ( ) ) { SDValue LoIdx = CurDAG -> getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue LoOut = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , MAdd , LoIdx ) ;

CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( ADDCNode , <NUM_LIT> ) , LoOut ) ;


<s> const TargetRegisterInfo & TRI = * MF . getTarget ( ) . getRegisterInfo ( ) ; int64_t Offset = <NUM_LIT> ; for ( int I = MFI -> getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) Offset = std :: max ( Offset , - MFI -> getObjectOffset ( I ) ) ; for ( const uint16_t * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getMinimalPhysRegClass ( * R ) -> getSize ( ) ; Offset = RoundUpToAlignment ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! MFI -> getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = <NUM_LIT> , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = RoundUpToAlignment ( Offset + MFI -> getObjectSize ( I ) , MaxAlign ) ; if ( MFI -> adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = RoundUpToAlignment ( Offset + MFI -> getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ;

return RoundUpToAlignment ( Offset , getStackAlignment ( ) ) ;


<s> else if ( Val < <NUM_LIT> && Val >= - <NUM_LIT> ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addImm ( - Val ) . setMIFlag ( Flag ) ; else report_fatal_error ( <STR_LIT> <STR_LIT> ) ;


<s> class LLVM_LIBRARY_VISIBILITY <ISA_LIT>MCInstLower { MCContext & Ctx ; Mangler * Mang ; const MachineFunction & MF ; const TargetMachine & TM ; const MCAsmInfo & MAI ; <ISA_LIT>AsmPrinter & AsmPrinter ; public :

<ISA_LIT>MCInstLower ( Mangler * mang , const MachineFunction & MF , <ISA_LIT>AsmPrinter & asmprinter ) ;


<s> fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , alloc_offset - seh -> reg_offset [ regno ] ) ; } if ( seh -> cfa_reg != stack_pointer_rtx ) { offset = alloc_offset - seh -> cfa_offset ; gcc_assert ( ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; gcc_assert ( IN_RANGE ( offset , <NUM_LIT> , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , f ) ; print_reg ( seh -> cfa_reg , <NUM_LIT> , f ) ; fprintf ( f , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , offset ) ; }


<s> switch ( CallConv ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : case CallingConv :: C :

return LowerCCCCallTo ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , Ins , dl , DAG , InVals ) ;


<s> virtual ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> default : return ; case <STR_LIT> :: NONE : break ; case <STR_LIT> :: RNI : O << <STR_LIT> ; break ; case <STR_LIT> :: RZI : O << <STR_LIT> ; break ; case <STR_LIT> :: RMI : O << <STR_LIT> ; break ; case <STR_LIT> :: RPI : O << <STR_LIT> ; break ; case <STR_LIT> :: RN : O << <STR_LIT> ; break ; case <STR_LIT> :: RZ : O << <STR_LIT> ; break ; case <STR_LIT> :: RM : O << <STR_LIT> ; break ; case <STR_LIT> :: RP : O << <STR_LIT> ; break ; } } else {


<s> void <ISA_LIT>ScheduleDAGMI :: restoreSULinksLeft ( ) { for ( unsigned i = <NUM_LIT> , e = SUnits . size ( ) ; i != e ; ++ i ) { SUnits [ i ] . isScheduled = false ; SUnits [ i ] . WeakPredsLeft = SUnitsLinksBackup [ i ] . WeakPredsLeft ; SUnits [ i ] . NumPredsLeft = SUnitsLinksBackup [ i ] . NumPredsLeft ; SUnits [ i ] . WeakSuccsLeft = SUnitsLinksBackup [ i ] . WeakSuccsLeft ;

SUnits [ i ] . NumSuccsLeft = SUnitsLinksBackup [ i ] . NumSuccsLeft ;


<s> static bool isVINSERTIndex ( SDNode * N , unsigned vecWidth ) { assert ( ( vecWidth == <NUM_LIT> || vecWidth == <NUM_LIT> ) && <STR_LIT> ) ;

if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ;


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned CalleeSavedFrameSize = <NUM_LIT> ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; unsigned FPReg = RegInfo -> getFrameRegister ( MF ) ; for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = RegInfo -> getMinimalPhysRegClass ( Reg ) ;

SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ;


<s> std :: string FuncName = Mang -> getValueName ( F ) ; const TargetData * TD = TM . getTargetData ( ) ; O << <STR_LIT> ; const char * SectionName = PAN :: getFrameSectionName ( CurrentFnName ) . c_str ( ) ; const Section * fPDataSection = TAI -> getNamedSection ( SectionName , SectionFlags :: Writeable ) ; SwitchToSection ( fPDataSection ) ; O << PAN :: getFrameLabel ( CurrentFnName ) << <STR_LIT> ; const Type * RetType = F -> getReturnType ( ) ; unsigned RetSize = <NUM_LIT> ;

if ( RetType -> getTypeID ( ) != Type :: VoidTyID ) RetSize = TD -> getTypeAllocSize ( RetType ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) {

SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ;


<s> PredicationCode = CC ; } if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( IMod != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; ProcessorIMod = IMod ; } } return Mnemonic ;


<s> DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = TM . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock :: reverse_iterator Ins ; unsigned CRBitSpillDistance = <NUM_LIT> ; for ( Ins = MI ; Ins != MBB . rend ( ) ; Ins ++ ) { if ( Ins -> modifiesRegister ( SrcReg , TRI ) ) break ; if ( CRBitSpillDistance == MaxCRBitSpillDist ) { Ins = MI ; break ; } if ( ! Ins -> isDebugInstr ( ) ) CRBitSpillDistance ++ ; } if ( Ins == MBB . rend ( ) ) Ins = MI ;


<s> bool <ISA_LIT>InstrInfo :: isLateSourceInstr ( const MachineInstr & MI ) const { return getType ( MI ) == <STR_LIT> ;


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ;

return ( Val >= <NUM_LIT> && Val < <NUM_LIT> ) ;


<s> assert ( RC && <STR_LIT> ) ; assert ( ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) && <STR_LIT> ) ; unsigned OpCode = <STR_LIT> . hasSubClassEq ( RC ) ? <STR_LIT> : <STR_LIT> ; unsigned SelectPred = Cond [ <NUM_LIT> ] . getImm ( ) ; unsigned SubIdx ; bool SwapOps ; switch ( SelectPred ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; }

unsigned FirstReg = SwapOps ? FalseReg : TrueReg , SecondReg = SwapOps ? TrueReg : FalseReg ;


<s> RegisterAsmParser < <ISA_LIT>AsmParser > Y ( TheThumbTarget ) ; LLVMInitialize<ISA_LIT>AsmLexer ( ) ;


<s> unsigned FrameIdxReg1 = RPI . FrameIdx ; unsigned FrameIdxReg2 = RPI . FrameIdx + <NUM_LIT> ; if ( NeedsWinCFI && RPI . isPaired ( ) ) { std :: swap ( Reg1 , Reg2 ) ; std :: swap ( FrameIdxReg1 , FrameIdxReg2 ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( RPI . isPaired ( ) ) { MIB . addReg ( Reg2 , getDefRegState ( true ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdxReg2 ) , MachineMemOperand :: MOLoad , Size , Alignment ) ) ; } MIB . addReg ( Reg1 , getDefRegState ( true ) ) . addReg ( <STR_LIT> ) . addImm ( RPI . Offset ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdxReg1 ) , MachineMemOperand :: MOLoad , Size , Alignment ) ) ; if ( NeedsWinCFI ) InsertSEH ( MIB , TII , MachineInstr :: FrameDestroy ) ; } ; for ( const RegPairInfo & RPI : reverse ( RegPairs ) ) if ( RPI . isScalable ( ) ) EmitMI ( RPI ) ; if ( ReverseCSRRestoreSeq ) { for ( const RegPairInfo & RPI : reverse ( RegPairs ) ) if ( ! RPI . isScalable ( ) ) EmitMI ( RPI ) ; } else if ( homogeneousPrologEpilog ( MF , & MBB ) ) { auto MIB = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; for ( auto & RPI : RegPairs ) { MIB . addReg ( RPI . Reg1 , RegState :: Define ) ; MIB . addReg ( RPI . Reg2 , RegState :: Define ) ; } return true ; } else for ( const RegPairInfo & RPI : RegPairs ) if ( ! RPI . isScalable ( ) ) EmitMI ( RPI ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx ) : MCII ( mcii ) , Ctx ( ctx ) { ( void ) Ctx ;


<s> } default : return false ; } EVT RT = R . getValueType ( ) ; if ( RT == <STR_LIT> ) return true ; assert ( RT == <STR_LIT> ) ; const SDLoc & dl ( N ) ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , R , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , R , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) } ;

SDNode * T = CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , <STR_LIT> , Ops ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitPINSERT ( MachineInstr & MI , MachineBasicBlock * BB ) const { const unsigned dst_pos = <NUM_LIT> ; const unsigned src_pos = <NUM_LIT> ; const unsigned imm2_pos = <NUM_LIT> ; const unsigned imm3_pos = <NUM_LIT> ; assert ( MI . getNumOperands ( ) == <NUM_LIT> ) ; assert ( MI . getOperand ( dst_pos ) . isReg ( ) ) ; assert ( MI . getOperand ( src_pos ) . isReg ( ) ) ; assert ( MI . getOperand ( imm2_pos ) . isImm ( ) ) ; assert ( MI . getOperand ( imm3_pos ) . isImm ( ) ) ; const TargetInstrInfo * TII = BB -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int n = MI . getOperand ( imm2_pos ) . getImm ( ) ; int shift_imm = MI . getOperand ( imm3_pos ) . getImm ( ) ; unsigned int l_pos , r_pos ; if ( ! RI5CY_bitIntervalExtraction ( n , & l_pos , & r_pos , true ) || r_pos != <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ; } assert ( isUInt < <NUM_LIT> > ( l_pos ) ) ; assert ( isUInt < <NUM_LIT> > ( shift_imm ) ) ; unsigned opcode = <STR_LIT> ; MachineInstrBuilder pinsertMI = BuildMI ( * BB , MI , DL , TII -> get ( opcode ) ) ; pinsertMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; pinsertMI . addOperand ( MI . getOperand ( dst_pos ) ) ; pinsertMI . addOperand ( MI . getOperand ( src_pos ) ) ; pinsertMI . addImm ( l_pos ) ; pinsertMI . addImm ( shift_imm ) ; MI . eraseFromParent ( ) ;


<s> int VecNumElts = OpVT . getVectorNumElements ( ) ; int SubVecNumElts = SubVecVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ( VecNumElts ) ; for ( int i = <NUM_LIT> ; i != VecNumElts ; ++ i ) Mask [ i ] = i ; for ( int i = <NUM_LIT> ; i != SubVecNumElts ; ++ i ) Mask [ i + IdxVal ] = i + ExtIdxVal + VecNumElts ; return DAG . getVectorShuffle ( OpVT , dl , Vec , SubVec . getOperand ( <NUM_LIT> ) , Mask ) ; } } if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . getSizeInBits ( ) == SubVecVT . getSizeInBits ( ) * <NUM_LIT> ) { auto * Idx2 = dyn_cast < ConstantSDNode > ( Vec . getOperand ( <NUM_LIT> ) ) ; if ( Idx2 && Idx2 -> getZExtValue ( ) == <NUM_LIT> ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( peekThroughBitcasts ( SubVec2 ) ) ) { bool Fast ; unsigned Alignment = FirstLd -> getAlignment ( ) ; unsigned AS = FirstLd -> getAddressSpace ( ) ; const <ISA_LIT>TargetLowering * TLI = Subtarget . getTargetLowering ( ) ; if ( TLI -> allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , OpVT , AS , Alignment , & Fast ) && Fast ) { SDValue Ops [ ] = { SubVec2 , SubVec } ; if ( SDValue Ld = EltsFromConsecutiveLoads ( OpVT , Ops , dl , DAG , Subtarget , false ) ) return Ld ;


<s> MachineInstr * EC = elideCopies ( SPRMI ) ; if ( EC && EC -> isCopy ( ) && EC -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << * SPRMI ) ; unsigned FullReg = SPRMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * TRC = MRI -> getRegClass ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( TRC -> hasSuperClassEq ( MRI -> getRegClass ( FullReg ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << PrintReg ( FullReg ) << <STR_LIT> ) ; eraseInstrWithNoUses ( MI ) ; return FullReg ; } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( MI -> isRegSequence ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) { unsigned NumImplicit = <NUM_LIT> , NumTotal = <NUM_LIT> ; unsigned NonImplicitReg = ~ <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumExplicitOperands ( ) ; ++ I ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) continue ; ++ NumTotal ;

unsigned OpReg = MI -> getOperand ( I ) . getReg ( ) ;


<s> DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI ) ) ;


<s> if ( any_offset_symbol_operand ( sym , mode ) ) addend = <NUM_LIT> ; else if ( aligned_offset_symbol_operand ( sym , mode ) ) { HOST_WIDE_INT addend_lo , addend_hi ; addend_lo = ( ( addend & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; addend_hi = addend - addend_lo ; if ( addend_lo != <NUM_LIT> ) { op1 = plus_constant ( sym , addend_hi ) ; addend = addend_lo ; } else addend = <NUM_LIT> ; } else op1 = sym ; if ( reload_completed ) { gcc_assert ( addend == <NUM_LIT> ) ; if ( ia64_expand_load_address ( op0 , op1 ) ) return NULL_RTX ;


<s> else if ( msize <= <NUM_LIT> ) base_off += msize ; if ( base_off >= <NUM_LIT> ) { base_off = <NUM_LIT> - <NUM_LIT> ; base_off -= ( ( ( base_off % msize ) - ( off_val_1 % msize ) ) + msize ) % msize ; } if ( base_off <= - <NUM_LIT> ) { base_off = - <NUM_LIT> + <NUM_LIT> ; base_off += ( ( ( base_off % msize ) - ( off_val_1 % msize ) ) + msize ) % msize ; } new_off_1 = off_val_1 - base_off ; new_off_3 = off_val_3 - base_off ; if ( new_off_1 > stp_off_upper_limit || new_off_1 < stp_off_lower_limit || new_off_3 > stp_off_upper_limit || new_off_3 < stp_off_lower_limit ) return false ; replace_equiv_address_nv ( mem_1 , plus_constant ( Pmode , operands [ <NUM_LIT> ] , new_off_1 ) , true ) ; replace_equiv_address_nv ( mem_2 , plus_constant ( Pmode , operands [ <NUM_LIT> ] , new_off_1 + msize ) , true ) ; replace_equiv_address_nv ( mem_3 , plus_constant ( Pmode , operands [ <NUM_LIT> ] , new_off_3 ) , true ) ; replace_equiv_address_nv ( mem_4 , plus_constant ( Pmode , operands [ <NUM_LIT> ] , new_off_3 + msize ) , true ) ; if ( ! aarch64_mem_pair_operand ( mem_1 , mode ) || ! aarch64_mem_pair_operand ( mem_3 , mode ) ) return false ; if ( code == ZERO_EXTEND ) { mem_1 = gen_rtx_ZERO_EXTEND ( DImode , mem_1 ) ; mem_2 = gen_rtx_ZERO_EXTEND ( DImode , mem_2 ) ; mem_3 = gen_rtx_ZERO_EXTEND ( DImode , mem_3 ) ; mem_4 = gen_rtx_ZERO_EXTEND ( DImode , mem_4 ) ; } else if ( code == SIGN_EXTEND ) { mem_1 = gen_rtx_SIGN_EXTEND ( DImode , mem_1 ) ; mem_2 = gen_rtx_SIGN_EXTEND ( DImode , mem_2 ) ; mem_3 = gen_rtx_SIGN_EXTEND ( DImode , mem_3 ) ; mem_4 = gen_rtx_SIGN_EXTEND ( DImode , mem_4 ) ; } if ( load ) { operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_1 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_2 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_3 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_4 ; } else { operands [ <NUM_LIT> ] = mem_1 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_2 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_3 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = mem_4 ; operands [ <NUM_LIT> ] = temp_operands [ <NUM_LIT> ] ; } emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , plus_constant ( DImode , base , base_off ) ) ) ;

t1 = gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ;


<s> i = INTVAL ( constant ) ; if ( USE_MOVQ ( i ) ) return MOVQ ; if ( ! TARGET_COLDFIRE ) { if ( USE_MOVQ ( i ^ <NUM_LIT> ) ) return NOTB ; if ( USE_MOVQ ( i ^ <NUM_LIT> ) ) return NOTW ; if ( i == - <NUM_LIT> ) return NEGW ; } u = i ; if ( USE_MOVQ ( ( u >> <NUM_LIT> ) | ( u << <NUM_LIT> ) ) ) return SWAP ; if ( TARGET_CFV4 ) { if ( i >= <NUM_LIT> && i <= <NUM_LIT> ) return MVZ ; if ( i >= - <NUM_LIT> && i <= <NUM_LIT> ) return MVS ;


<s> getLexer ( ) . Lex ( ) ; Operands . push_back ( <STR_LIT> ( Name , S ) ) ; return MatchOperand_Success ; } case AsmToken :: EqualEqual : case AsmToken :: ExclaimEqual : case AsmToken :: GreaterEqual : case AsmToken :: GreaterGreater : case AsmToken :: LessEqual : case AsmToken :: LessLess : { Operands . push_back ( <STR_LIT> ( getLexer ( ) . getTok ( ) . getString ( ) . substr ( <NUM_LIT> , <NUM_LIT> ) , S ) ) ; Operands . push_back ( <STR_LIT> ( getLexer ( ) . getTok ( ) . getString ( ) . substr ( <NUM_LIT> , <NUM_LIT> ) , S ) ) ; getLexer ( ) . Lex ( ) ; return MatchOperand_Success ; } default : break ;


<s> switch ( Op . getNode ( ) -> getOpcode ( ) ) { case <STR_LIT> : for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) if ( UI -> getOpcode ( ) != <STR_LIT> && UI -> getOpcode ( ) != <STR_LIT> ) goto default_case ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ) { if ( C -> getAPIntValue ( ) == <NUM_LIT> ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } if ( C -> getAPIntValue ( ) . isAllOnesValue ( ) ) { Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; } } Opcode = <STR_LIT> ; NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : { bool NonFlagUse = false ; for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = Op . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; unsigned UOpNo = UI . getOperandNo ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> && User -> hasOneUse ( ) ) { UOpNo = User -> use_begin ( ) . getOperandNo ( ) ; User = * User -> use_begin ( ) ; } if ( User -> getOpcode ( ) != <STR_LIT> && User -> getOpcode ( ) != <STR_LIT> && ( User -> getOpcode ( ) != <STR_LIT> || UOpNo != <NUM_LIT> ) ) {


<s> static DecodeStatus DecodetGPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) {

if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> void addMemNegImm8OffsetOperands ( MCInst & Inst , unsigned N ) const {


<s> BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Zero64 ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , SRsrcFormatLo ) . addImm ( RsrcDataFormat & <NUM_LIT> ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , SRsrcFormatHi ) . addImm ( RsrcDataFormat >> <NUM_LIT> ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , NewSRsrc ) . addReg ( Zero64 ) . addImm ( <STR_LIT> ) . addReg ( SRsrcFormatLo ) . addImm ( <STR_LIT> ) . addReg ( SRsrcFormatHi ) . addImm ( <STR_LIT> ) ; return std :: make_tuple ( RsrcPtr , NewSRsrc ) ;


<s> const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVar ) { if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GVar = dyn_cast_or_null < GlobalVariable > ( GA -> resolveAliasedGlobal ( ) ) ; } if ( ! GVar ) { assert ( <NUM_LIT> && <STR_LIT> ) ; return SDValue ( ) ; } const Type * Ty = cast < PointerType > ( GV -> getType ( ) ) -> getElementType ( ) ;

if ( ! Ty -> isSized ( ) || isZeroLengthArray ( Ty ) ) {


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Immediate , Context ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ;

return std :: unique_ptr < <ISA_LIT>Operand > ( Op ) ;


<s> case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> << fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( Is64Bit ) { XLenVT = <STR_LIT> ; XLen = <NUM_LIT> ; }

TargetABI = <STR_LIT> ( TT , getFeatureBits ( ) , ABIName ) ;


<s> return ( ( TARGET_FPU_SINGLE != <NUM_LIT> ) ^ ( n ) ? FP_MODE_SINGLE : FP_MODE_DOUBLE ) ;


<s> if ( ! selectMUBUFOffsetImpl ( Root , RSrcReg , SOffset , Offset ) ) return { } ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( RSrcReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {

if ( SOffset ) MIB . addReg ( SOffset ) ;


<s> SDValue <STR_LIT> ( SDValue AVL ) const { if ( isLegalAVL ( AVL ) ) return AVL ;

return getNode ( <STR_LIT> , AVL . getValueType ( ) , AVL ) ;


<s> unsigned BitWidth = N1 . getValueSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , Log2_32 ( BitWidth ) ) ; if ( DAG . getTargetLoweringInfo ( ) . SimplifyDemandedBits ( N1 , DemandedMask , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } return SDValue ( ) ;


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , DL , <STR_LIT> ) ;


<s> void printUImm4Offset ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {

printUImm4Offset ( MI , OpNum , Scale , O ) ;


<s> Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Size = MRI -> getType ( DstReg ) . getSizeInBits ( ) ; const bool Is64 = Size == <NUM_LIT> ; if ( Size != STI . getWavefrontSize ( ) ) return false ; Optional < ValueAndVReg > Arg = getIConstantVRegValWithLookThrough ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( Arg . hasValue ( ) ) { const int64_t Value = Arg . getValue ( ) . Value . getSExtValue ( ) ; if ( Value == <NUM_LIT> ) {


<s> bool <ISA_LIT>Subtarget :: isPositionIndependent ( ) const { return TM . isPositionIndependent ( ) ;


<s> Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . setDesc ( get ( NewOpc ) ) ; Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst . addImplicitDefUseOperands ( * MBB . getParent ( ) ) ; MRI . replaceRegWith ( OldDstReg , ResultReg ) ; legalizeOperands ( Inst , MDT ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ;


<s> int <ISA_LIT>AsmParser :: matchRegisterName ( StringRef Name , bool is64BitReg ) { int CC ;


<s> <ISA_LIT>AsmBackend ( const Target & T ) : MCAsmBackend ( ) , TheTarget ( T ) , IsLittleEndian ( StringRef ( TheTarget . getName ( ) ) == <STR_LIT> ) , Is64Bit ( StringRef ( TheTarget . getName ( ) ) == <STR_LIT> ) {


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;


<s> <ISA_LIT>CallLowering :: <ISA_LIT>CallLowering ( const <ISA_LIT>TargetLowering & TLI ) : CallLowering ( & TLI ) {


<s> unsigned off4 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeDataRegsRegisterClass ( Inst , s2 , Address , Decoder ) ;

if ( status != MCDisassembler :: Success ) return status ;


<s> } if ( SatWidth == <NUM_LIT> && ! IsSigned && Subtarget . is64Bit ( ) ) { TmpVT = <STR_LIT> ; TmpWidth = <NUM_LIT> ; } if ( SatWidth < TmpWidth ) FpToIntOpcode = <STR_LIT> ; APInt MinInt , MaxInt ; if ( IsSigned ) { MinInt = APInt :: getSignedMinValue ( SatWidth ) . sext ( DstWidth ) ; MaxInt = APInt :: getSignedMaxValue ( SatWidth ) . sext ( DstWidth ) ; } else { MinInt = APInt :: getMinValue ( SatWidth ) . zext ( DstWidth ) ; MaxInt = APInt :: getMaxValue ( SatWidth ) . zext ( DstWidth ) ; } APFloat MinFloat ( DAG . EVTToAPFloatSemantics ( SrcVT ) ) ; APFloat MaxFloat ( DAG . EVTToAPFloatSemantics ( SrcVT ) ) ; APFloat :: opStatus MinStatus = MinFloat . convertFromAPInt ( MinInt , IsSigned , APFloat :: rmTowardZero ) ; APFloat :: opStatus MaxStatus = MaxFloat . convertFromAPInt ( MaxInt , IsSigned , APFloat :: rmTowardZero ) ; bool AreExactFloatBounds = ! ( MinStatus & APFloat :: opStatus :: opInexact ) && ! ( MaxStatus & APFloat :: opStatus :: opInexact ) ; SDValue MinFloatNode = DAG . getConstantFP ( MinFloat , dl , SrcVT ) ; SDValue MaxFloatNode = DAG . getConstantFP ( MaxFloat , dl , SrcVT ) ; if ( AreExactFloatBounds ) { if ( DstVT != TmpVT ) { SDValue MinClamped = DAG . getNode ( <STR_LIT> , dl , SrcVT , MinFloatNode , Src ) ; SDValue BothClamped = DAG . getNode ( <STR_LIT> , dl , SrcVT , MaxFloatNode , MinClamped ) ; SDValue FpToInt = DAG . getNode ( FpToIntOpcode , dl , TmpVT , BothClamped ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , FpToInt ) ; } SDValue MinClamped = DAG . getNode ( <STR_LIT> , dl , SrcVT , Src , MinFloatNode ) ; SDValue BothClamped = DAG . getNode ( <STR_LIT> , dl , SrcVT , MinClamped , MaxFloatNode ) ; SDValue FpToInt = DAG . getNode ( FpToIntOpcode , dl , DstVT , BothClamped ) ; if ( ! IsSigned ) { return FpToInt ; } SDValue ZeroInt = DAG . getConstant ( <NUM_LIT> , dl , DstVT ) ; return DAG . getSelectCC ( dl , Src , Src , ZeroInt , FpToInt , <STR_LIT> :: SETUO ) ; } SDValue MinIntNode = DAG . getConstant ( MinInt , dl , DstVT ) ; SDValue MaxIntNode = DAG . getConstant ( MaxInt , dl , DstVT ) ; SDValue FpToInt = DAG . getNode ( FpToIntOpcode , dl , TmpVT , Src ) ; if ( DstVT != TmpVT ) { FpToInt = DAG . getNode ( <STR_LIT> , dl , DstVT , FpToInt ) ;


<s> } } ; assert ( Val -> isVectorTy ( ) && <STR_LIT> ) ; Type * ScalarType = Val -> getScalarType ( ) ; if ( Index != - <NUM_LIT> ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned Width = LT . second . getVectorNumElements ( ) ; Index = Index % Width ;

if ( ScalarType -> isFloatingPointTy ( ) && Index == <NUM_LIT> ) return <NUM_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: matchAddressRecursively ( SDValue N , <ISA_LIT>ISelAddressMode & AM , unsigned Depth ) {


<s> <ISA_LIT>AddressingMode AM ( <STR_LIT> , DR ) ; if ( ! selectAddress ( Addr , AM ) || AM . Index . getNode ( ) ) return false ; getAddressOperands ( AM , Addr . getValueType ( ) , Base , Disp ) ;


<s> MachineBasicBlock * AMDGPUCFGStructurizer :: clone ( MachineBasicBlock * MBB ) { MachineFunction * Func = MBB -> getParent ( ) ; MachineBasicBlock * NewMBB = Func -> CreateMachineBasicBlock ( ) ; Func -> push_back ( NewMBB ) ; for ( MachineBasicBlock :: iterator It = MBB -> begin ( ) , E = MBB -> end ( ) ; It != E ; ++ It ) { MachineInstr * MI = Func -> CloneMachineInstr ( It ) ; NewMBB -> push_back ( MI ) ; } return NewMBB ;


<s> bool <ISA_LIT>TargetMachine :: addInstSelector ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( <ISA_LIT>CreateInstSelector ( * this ) ) ;


<s> case <STR_LIT> : return lowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( cast < BlockAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerJumpTable ( cast < JumpTableSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerConstantPool ( cast < ConstantPoolSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerSMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerUMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return lowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return lowerOR ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_LOAD ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> :

return lowerATOMIC_CMP_SWAP ( Op , DAG ) ;


<s> rtx mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; emit_move_insn ( reg , mem ) ;

return alloc_reg_note ( REG_CFA_RESTORE , reg , cfa_restores ) ;


<s> in_section = NULL ; fputs ( <STR_LIT> , stream ) ; assemble_name ( stream , funname ) ; fputs ( <STR_LIT> , stream ) ; ASM_OUTPUT_LABEL ( stream , funname ) ; fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , funname ) ; fprintf ( stream , <STR_LIT> , alpha_procedure_type == PT_STACK ? <STR_LIT> : alpha_procedure_type == PT_REGISTER ? <STR_LIT> : <STR_LIT> ) ;


<s> else Opc = isSub ? getSUBriOpcode ( Is64BitStackPtr , Offset ) : getADDriOpcode ( Is64BitStackPtr , Offset ) ; uint64_t Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; while ( Offset ) { if ( Offset > Chunk ) { unsigned Reg = <NUM_LIT> ; if ( isSub && ! isEAXLiveIn ( * MBB . getParent ( ) ) ) Reg = ( unsigned ) ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) ; else Reg = findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64BitTarget ) ; if ( Reg ) { Opc = Is64BitTarget ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , Reg ) . addImm ( Offset ) ; Opc = isSub ? getSUBrrOpcode ( Is64BitTarget ) : getADDrrOpcode ( Is64BitTarget ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addReg ( Reg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; Offset = <NUM_LIT> ; continue ; } } uint64_t ThisVal = ( Offset > Chunk ) ? Chunk : Offset ; if ( ThisVal == ( Is64BitTarget ? <NUM_LIT> : <NUM_LIT> ) ) { unsigned Reg = isSub ? ( unsigned ) ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) : findDeadCallerSavedReg ( MBB , MBBI , TRI , Is64BitTarget ) ; if ( Reg ) { Opc = isSub ? ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) : ( Is64BitTarget ? <STR_LIT> : <STR_LIT> ) ;

MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) ) . addReg ( Reg , getDefRegState ( ! isSub ) | getUndefRegState ( isSub ) ) ;


<s> void <ISA_LIT>PALMetadata :: setNumUsedAgprs ( CallingConv :: ID CC , unsigned Val ) { getHwStage ( CC ) [ <STR_LIT> ] = Val ;