<s> MachineFunction :: iterator NextBB ; MachineBasicBlock * EmptyMBBAtEnd = nullptr ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; BI = NextBB ) { NextBB = std :: next ( BI ) ; MachineBasicBlock & MBB = * BI ; bool HaveSkipBlock = false ; if ( ! ExecBranchStack . empty ( ) && ExecBranchStack . back ( ) == & MBB ) { ExecBranchStack . pop_back ( ) ; } if ( HaveKill && ExecBranchStack . empty ( ) ) { HaveKill = false ; } MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : ExecBranchStack . push_back ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; MadeChange |= skipMaskBranch ( MI , MBB ) ; break ; case <STR_LIT> : if ( MBB . isLayoutSuccessor ( MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { MI . eraseFromParent ( ) ; } else if ( HaveSkipBlock ) { MI . eraseFromParent ( ) ; } break ; case <STR_LIT> : MadeChange = true ; kill ( MI ) ; if ( ExecBranchStack . empty ( ) ) { if ( skipIfDead ( MI , * NextBB ) ) { HaveSkipBlock = true ; NextBB = std :: next ( BI ) ; BE = MF . end ( ) ; } } else { HaveKill = true ; } MI . eraseFromParent ( ) ;


<s> int64_t getSMRDEncodedOffset ( const MCSubtargetInfo & ST , int64_t ByteOffset ) { if ( hasSMEMByteOffset ( ST ) ) return ByteOffset ;


<s> return <ISA_LIT>Lowering -> SelectOptimalAddrMode ( Parent , N , Disp , Base , * CurDAG , Align ( <NUM_LIT> ) ) == <STR_LIT> ;


<s> poly_int64 first = addr . const_offset ; poly_int64 last = first + GET_MODE_SIZE ( mode ) - BYTES_PER_SVE_VECTOR ;

return ( offset_4bit_signed_scaled_p ( SVE_BYTE_MODE , first ) && offset_4bit_signed_scaled_p ( SVE_BYTE_MODE , last ) ) ;


<s> unsigned IntrID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntrID ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SelectDS_GWS ( N , IntrID ) ; return ; default : break ; } SelectCode ( N ) ;


<s> const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; assert ( ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; bool FP = hasFP ( MF ) ; long NumBytes = MFI -> getStackSize ( ) ; if ( FP ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ; } if ( NumBytes != <NUM_LIT> ) { if ( NumBytes <= <STR_LIT> ) {

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( NumBytes ) . addReg ( <STR_LIT> ) ;


<s> unsigned DMaskIdx = <STR_LIT> ( CI . I -> getOpcode ( ) , <STR_LIT> :: dmask ) ; auto MIB = BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) , DestReg ) ; for ( unsigned I = <NUM_LIT> , E = ( * CI . I ) . getNumOperands ( ) ; I != E ; ++ I ) { if ( I == DMaskIdx ) MIB . addImm ( MergedDMask ) ; else MIB . add ( ( * CI . I ) . getOperand ( I ) ) ; } assert ( CI . I -> hasOneMemOperand ( ) && CI . Paired -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * CI . Paired -> memoperands_begin ( ) ;

MachineInstr * New = MIB . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ;


<s> const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; for ( MachineBasicBlock & MBB : MF ) {


<s> bool <ISA_LIT>LegalizerInfo :: legalizePreloadedArgIntrin ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & B , <STR_LIT> ArgType ) const { B . setInstr ( MI ) ;

const <ISA_LIT>MachineFunctionInfo * MFI = B . getMF ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


return isMoveWideImm ( <NUM_LIT> , PermittedModifiers , NumModifiers ) ;


<s> static void BuildSignatureCall ( StringRef SymName , BasicBlock & BB , Function & F ) { LLVMContext & Ctx = F . getContext ( ) ; IntegerType * I16 = Type :: getInt16Ty ( Ctx ) ; FunctionType * FnType = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , { Type :: getInt8PtrTy ( Ctx ) , I16 } , false ) ;

Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( SymName , FnType ) ;


<s> char * up0 = up ; for ( ; * lo ; lo ++ , up ++ ) * up = TOUPPER ( * lo ) ;


<s> if ( ! IStart ) return ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo * MRI = & Entry -> getParent ( ) -> getRegInfo ( ) ; MachineBasicBlock :: iterator MBBI = Entry -> begin ( ) ; for ( const MCPhysReg * I = IStart ; * I ; ++ I ) { const TargetRegisterClass * RC = nullptr ; if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ;

else if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateShiftedImm ( const MCExpr * Val , unsigned ShiftAmount , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_ShiftedImm , Ctx ) ; Op -> ShiftedImm . Val = Val ; Op -> ShiftedImm . ShiftAmount = ShiftAmount ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> MachineBasicBlock :: iterator I = * MI ; int64_t Amount = getWinAllocaAmount ( MI , MRI ) ; if ( Amount == <NUM_LIT> ) { MI -> eraseFromParent ( ) ; return ; } bool Is64Bit = STI -> is64Bit ( ) ; assert ( SlotSize == <NUM_LIT> || SlotSize == <NUM_LIT> ) ; unsigned RegA = ( SlotSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; switch ( L ) { case TouchAndSub : assert ( Amount >= SlotSize ) ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( RegA , RegState :: Undef ) ; Amount -= SlotSize ; if ( ! Amount ) break ; case Sub : assert ( Amount > <NUM_LIT> ) ; if ( Amount == SlotSize ) { BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ; break ; } unsigned AmountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> eraseFromParent ( ) ; for ( ; ; ) { if ( ! MRI -> use_empty ( AmountReg ) ) break ;

MachineInstr * AmountDef = MRI -> getUniqueVRegDef ( AmountReg ) ;


<s> AU . addRequired < LoopInfo > ( ) ; AU . addPreserved < LoopInfo > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addPreserved < DominatorTreeWrapperPass > ( ) ;

AU . addRequired < ScalarEvolution > ( ) ;


<s> else if ( Reg . Group == RegAR ) RegNo = <STR_LIT> [ Reg . Num ] ; else if ( Reg . Group == RegCR ) RegNo = <STR_LIT> [ Reg . Num ] ; StartLoc = Reg . StartLoc ; EndLoc = Reg . EndLoc ;


<s> void <ISA_LIT>InstPrinter :: printMemBOption ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) {

unsigned val = MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> assert ( ( annot == <NUM_LIT> ) && <STR_LIT> ) ; return true ; } } if ( const Argument * arg = dyn_cast < Argument > ( & val ) ) { const Function * func = arg -> getParent ( ) ; std :: vector < unsigned > annot ; if ( llvm :: findAllNVVMAnnotation ( func , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISSAMPLER ] , annot ) ) { if ( std :: find ( annot . begin ( ) , annot . end ( ) , arg -> getArgNo ( ) ) != annot . end ( ) ) return true ;


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { if ( AI -> isFloatingPointOperation ( ) ) return AtomicExpansionKind :: CmpXChg ; unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( Size > <NUM_LIT> ) return AtomicExpansionKind :: None ; if ( AI -> getOperation ( ) == AtomicRMWInst :: Nand ) return AtomicExpansionKind :: LLSC ;

return ( Subtarget -> hasLSE ( ) && Size < <NUM_LIT> ) ? AtomicExpansionKind :: None : AtomicExpansionKind :: LLSC ;


<s> } if ( ! isResourceAvailable ( SU ) ) { ResourcesModel -> clearResources ( ) ; Packet . clear ( ) ; TotalPackets ++ ; startNewCycle = true ; } switch ( SU -> getInstr ( ) -> getOpcode ( ) ) { default : ResourcesModel -> reserveResources ( SU -> getInstr ( ) ) ; break ; case TargetOpcode :: EXTRACT_SUBREG : case TargetOpcode :: INSERT_SUBREG : case TargetOpcode :: SUBREG_TO_REG : case TargetOpcode :: REG_SEQUENCE : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: PROLOG_LABEL : case TargetOpcode :: EH_LABEL : case TargetOpcode :: COPY : case TargetOpcode :: INLINEASM : break ; } Packet . push_back ( SU ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << TotalPackets << <STR_LIT> ) ;


<s> <ISA_LIT>OutgoingArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , MachineInstrBuilder MIB , CCAssignFn * AssignFn , CCAssignFn * AssignFnVarArg , bool IsTailCall = false , int FPDiff = <NUM_LIT> ) : <ISA_LIT>ValueHandler ( false , MIRBuilder , MRI , AssignFn ) , MIB ( MIB ) , AssignFnVarArg ( AssignFnVarArg ) , FPDiff ( FPDiff ) , IsTailCall ( IsTailCall ) {


<s> MI . setDesc ( get ( <STR_LIT> ) ) ; } else { if ( SpecialShift32 ) { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t MB = RightShift ? ShAmt : <NUM_LIT> ; uint64_t ME = RightShift ? <NUM_LIT> : <NUM_LIT> - ShAmt ; MI . getOperand ( III . ConstantOpNo ) . ChangeToImmediate ( SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( MB ) . addImm ( ME ) ; } else { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t ME = RightShift ? ShAmt : <NUM_LIT> - ShAmt ; MI . getOperand ( III . ConstantOpNo ) . ChangeToImmediate ( SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( ME ) ; } } } else MI . getOperand ( ConstantOpNo ) . ChangeToImmediate ( Imm ) ; } else if ( III . IsCommutative ) { MI . getOperand ( ConstantOpNo ) . ChangeToImmediate ( Imm ) ; swapMIOperands ( MI , ConstantOpNo , III . ConstantOpNo ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( III . ConstantOpNo != III . ImmOpNo ) swapMIOperands ( MI , III . ConstantOpNo , III . ImmOpNo ) ; if ( ! PostRA && III . ZeroIsSpecialOrig != III . ZeroIsSpecialNew ) { if ( ! III . ZeroIsSpecialOrig ) { unsigned RegToModify = MI . getOperand ( III . ZeroIsSpecialNew ) . getReg ( ) ; const TargetRegisterClass * NewRC = MRI . getRegClass ( RegToModify ) -> hasSuperClassEq ( & <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; MRI . setRegClass ( RegToModify , NewRC ) ; } }


<s> const MCInstrDesc & InstDesc = MI . getDesc ( ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpNo ] ; assert ( MO . isImm ( ) || MO . isTargetIndex ( ) || MO . isFI ( ) || MO . isGlobal ( ) ) ;

if ( OpInfo . OperandType == MCOI :: OPERAND_IMMEDIATE ) return true ;


<s> unsigned <ISA_LIT>PALMetadata :: getType ( ) const {


<s> if ( ! getSuperRegDestIfDead ( MI , NewDestReg ) ) return nullptr ; if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return nullptr ;

MachineInstrBuilder MIB = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( New32BitOpcode ) , NewDestReg ) ;


<s> insn_info * insn2 = extract_single_source ( set2 ) ; if ( ! insn1 || ! insn2 ) return false ;


<s> if ( ! GV . hasInitializer ( ) ) { continue ; } if ( ! isa < UndefValue > ( GV . getInitializer ( ) ) ) { continue ; } if ( GV . isConstant ( ) ) { continue ; } if ( ! shouldLowerLDSToStruct ( UsedList , GV , F ) ) { continue ; } LocalVars . push_back ( & GV ) ; }


<s> case <STR_LIT> : case <STR_LIT> : BROpcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : BROpcode = <STR_LIT> ; break ; } CC = ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; BuildMI ( BB , dl , TII . get ( BROpcode ) ) . addMBB ( sinkMBB ) . addImm ( CC ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; for ( MachineBasicBlock :: succ_iterator I = BB -> succ_begin ( ) , E = BB -> succ_end ( ) ; I != E ; ++ I ) { EM -> insert ( std :: make_pair ( * I , sinkMBB ) ) ; sinkMBB -> addSuccessor ( * I ) ;


<s> if ( ! RHS ) return true ; uint32_t RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC > <NUM_LIT> || RHSC % <NUM_LIT> != <NUM_LIT> ) return true ; Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) {

int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ;


<s> void arc_set_default_type_attributes ( tree type ATTRIBUTE_UNUSED ) { gcc_unreachable ( ) ;


<s> Filler ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) {


<s> SmallVector < SDNode * , <NUM_LIT> > Queue ( <NUM_LIT> , Chain . getNode ( ) ) ; SmallSet < SDNode * , <NUM_LIT> > Visited ; while ( ! Queue . empty ( ) ) { SDNode * ChainNext = Queue . pop_back_val ( ) ; if ( ! Visited . insert ( ChainNext ) ) continue ; if ( MemSDNode * ChainLD = dyn_cast < MemSDNode > ( ChainNext ) ) { if ( isConsecutiveLS ( ChainLD , LD , VT . getStoreSize ( ) , <NUM_LIT> , DAG ) ) return true ; if ( ! Visited . count ( ChainLD -> getChain ( ) . getNode ( ) ) ) Queue . push_back ( ChainLD -> getChain ( ) . getNode ( ) ) ; } else if ( ChainNext -> getOpcode ( ) == <STR_LIT> ) { for ( const SDUse & O : ChainNext -> ops ( ) ) if ( ! Visited . count ( O . getNode ( ) ) ) Queue . push_back ( O . getNode ( ) ) ; } else LoadRoots . insert ( ChainNext ) ; }


<s> if ( ! ConstOp1 ) return ; uint64_t CmpVal = ConstOp1 -> getZExtValue ( ) ; Comparison NewC ( C ) ; uint64_t MaskVal ; ConstantSDNode * Mask = <NUM_LIT> ; if ( C . Op0 . getOpcode ( ) == <STR_LIT> ) { NewC . Op0 = C . Op0 . getOperand ( <NUM_LIT> ) ; NewC . Op1 = C . Op0 . getOperand ( <NUM_LIT> ) ; Mask = dyn_cast < ConstantSDNode > ( NewC . Op1 ) ; if ( ! Mask ) return ; MaskVal = Mask -> getZExtValue ( ) ; } else { if ( NewC . Op0 . getValueType ( ) != <STR_LIT> || NewC . CCMask == <STR_LIT> || NewC . CCMask == <STR_LIT> || NewC . ICmpType == <STR_LIT> ) return ; if ( NewC . CCMask == <STR_LIT> || NewC . CCMask == <STR_LIT> ) { if ( CmpVal == uint64_t ( - <NUM_LIT> ) ) return ; CmpVal += <NUM_LIT> ; NewC . CCMask ^= <STR_LIT> ; } MaskVal = - ( CmpVal & - CmpVal ) ; NewC . ICmpType = <STR_LIT> ; } unsigned BitSize = NewC . Op0 . getValueType ( ) . getSizeInBits ( ) ; unsigned NewCCMask , ShiftVal ; if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal >> ShiftVal , CmpVal >> ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal >>= ShiftVal ; } else if ( NewC . ICmpType != <STR_LIT> && NewC . Op0 . getOpcode ( ) == <STR_LIT> && isSimpleShift ( NewC . Op0 , ShiftVal ) && ( NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal << ShiftVal , CmpVal << ShiftVal , <STR_LIT> ) ) ) { NewC . Op0 = NewC . Op0 . getOperand ( <NUM_LIT> ) ; MaskVal <<= ShiftVal ; } else { NewCCMask = getTestUnderMaskCond ( BitSize , NewC . CCMask , MaskVal , CmpVal , NewC . ICmpType ) ; if ( ! NewCCMask ) return ; }


<s> if ( New ) { MII -> eraseFromParent ( ) ; MII = New -> getIterator ( ) ; Modified = true ; } ++ MII ; }


<s> const LLT NarrowTy = MRI . getType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; assert ( NarrowTy . isVector ( ) && <STR_LIT> ) ; if ( SrcTy . getSizeInBits ( ) > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineIRBuilder MIB ( I ) ; const RegisterBank & DstRB = * RBI . getRegBank ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; for ( unsigned OpIdx = <NUM_LIT> ; OpIdx < NumElts ; ++ OpIdx ) { unsigned Dst = I . getOperand ( OpIdx ) . getReg ( ) ; MachineInstr * Extract = emitExtractVectorElt ( Dst , DstRB , NarrowTy , SrcReg , OpIdx , MIB ) ; if ( ! Extract ) return false ; } I . eraseFromParent ( ) ; return true ;


<s> if ( isa < MemIntrinsicSDNode > ( Root ) ) return cast < MemIntrinsicSDNode > ( Root ) -> getMemoryVT ( ) ; const unsigned Opcode = Root -> getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return cast < VTSDNode > ( Root -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ;


<s> static int rs6000_darwin64_struct_check_p ( machine_mode mode , const_tree type ) {

return rs6000_darwin64_abi && ( ( mode == BLKmode && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > <NUM_LIT> ) || ( type && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) == <NUM_LIT> ) ) ? <NUM_LIT> : <NUM_LIT> ;


<s> if ( ! frame_size ) { if ( cfun -> machine -> split_stack_varargs_pointer != NULL_RTX ) { emit_move_insn ( r1 , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( STACK_POINTER_OFFSET ) ) ) ; } return ; } if ( morestack_ref == NULL_RTX ) { morestack_ref = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; SYMBOL_REF_FLAGS ( morestack_ref ) |= ( SYMBOL_FLAG_LOCAL | SYMBOL_FLAG_FUNCTION ) ; } if ( CONST_OK_FOR_K ( frame_size ) || CONST_OK_FOR_Op ( frame_size ) ) { emit_move_insn ( r1 , gen_rtx_REG ( Pmode , TP_REGNUM ) ) ; guard = gen_rtx_MEM ( Pmode , plus_constant ( Pmode , r1 , psso ) ) ; if ( frame_size > SPLIT_STACK_AVAILABLE ) { emit_move_insn ( r1 , guard ) ; if ( TARGET_64BIT ) emit_insn ( gen_adddi3 ( r1 , r1 , GEN_INT ( frame_size ) ) ) ;


<s> void printCPSOptionOperand ( const MCInst * MI , unsigned OpNum ) {


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( bool _is64Bit , uint8_t OSABI ) : MCELFObjectTargetWriter ( _is64Bit , OSABI , ELF :: EM_MIPS , false ) {


<s> if ( ! IsRAAndRetAddrIsTaken ) MBB . addLiveIn ( Reg ) ; bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } else { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;

TII . storeRegToStackSlot ( MBB , MI , Reg , IsKill , I . getFrameIdx ( ) , RC , TRI ) ;


<s> for ( int i = array_lengthof ( ArgRegs ) - <NUM_LIT> ; i >= ( int ) FirstVAReg ; -- i ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , offset , true ) ; if ( i == ( int ) FirstVAReg ) { XFI -> setVarArgsFrameIndex ( FI ) ; } offset -= StackSlotSize ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; } if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ; } else { XFI -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , LRSaveSize + CCInfo . getNextStackOffset ( ) , true ) ) ; } }


<s> processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; if ( ! usePackedStack ( MF ) ) getOrCreateFramePointerSaveIndex ( MF ) ; uint64_t StackSize = ( MFFrame . estimateStackSize ( MF ) + <STR_LIT> ) ; int64_t MaxArgOffset = <NUM_LIT> ; for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= <NUM_LIT> ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ;

if ( ! isUInt < <NUM_LIT> > ( MaxReach ) ) {


<s> if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingIncrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } else if ( ( Mode == <STR_LIT> || Mode == <STR_LIT> ) && isMatchingDecrement ( NextMBBI , Base , Bytes , <NUM_LIT> , Pred , PredReg ) ) { DoMerge = true ; } if ( DoMerge ) { if ( NextMBBI == I ) { Advance = true ; ++ I ; } MBB . erase ( NextMBBI ) ; } } if ( ! DoMerge ) return false ; unsigned NewOpc = getUpdatingLSMultipleOpcode ( Opcode , Mode ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned OpNum = <NUM_LIT> , e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . addOperand ( MI -> getOperand ( OpNum ) ) ;

( * MIB ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;


<s> } if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return <NUM_LIT> ; emit_insn ( pat ) ; return target ;


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DecodeGPRMM16RegisterClass ( Inst , Reg , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DecodeGPRMM16ZeroRegisterClass ( Inst , Reg , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; break ; } if ( DecodeGPRMM16RegisterClass ( Inst , Base , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : if ( Offset == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( - <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> explicit <ISA_LIT>SEDAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OL ) : <ISA_LIT>DAGToDAGISel ( TM , OL ) {


<s> default : break ; } if ( Opcode != <STR_LIT> ) return EVT ( ) ; const unsigned IntNo = cast < ConstantSDNode > ( Root -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo != <STR_LIT> ) return EVT ( ) ; return getPackedVectorTypeFromPredicateType ( Ctx , Root -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ) ;


<s> APInt V ( <NUM_LIT> , Val , true ) ; if ( TII -> isInlineConstant ( V ) ) return MachineOperand :: CreateImm ( Val ) ; Register Reg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * Mov = BuildMI ( * MI . getParent ( ) , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( Val ) ; ( void ) Mov ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Mov -> dump ( ) ) ; return MachineOperand :: CreateReg ( Reg , false ) ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> int fualign ( int direction , int x , int y ) {

return ( direction > <NUM_LIT> ? ( ( x + ( y - <NUM_LIT> ) ) & - y ) : ( x & ( y - <NUM_LIT> ) ) ) ;


<s> explicit <ISA_LIT>LoopIdiomRecognize ( AliasAnalysis * AA , DominatorTree * DT , LoopInfo * LF , const TargetLibraryInfo * TLI , ScalarEvolution * SE ) : AA ( AA ) , DT ( DT ) , LF ( LF ) , TLI ( TLI ) , SE ( SE ) {


<s> if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } ConstantSDNode * OrdN = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( OrdN -> getZExtValue ( ) ) ; unsigned Domain = <STR_LIT> ; if ( Subtarget -> isMClass ( ) ) {


<s> return ( GET_CODE ( x ) == LABEL_REF || GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == CONST_INT || GET_CODE ( x ) == CONST || GET_CODE ( x ) == HIGH ) ;


<s> const SymbolListType & getGlobalGOTSyms ( ) const {


<s> Sym -> setImportName ( Name ) ; getTargetStreamer ( ) -> emitImportName ( Sym , Name ) ; } } } for ( const auto & G : M . globals ( ) ) { if ( ! G . hasInitializer ( ) && G . hasExternalLinkage ( ) ) { if ( G . getValueType ( ) -> isSized ( ) ) { uint16_t Size = M . getDataLayout ( ) . getTypeAllocSize ( G . getValueType ( ) ) ; OutStreamer -> emitELFSize ( getSymbol ( & G ) , MCConstantExpr :: create ( Size , OutContext ) ) ; } } } if ( const NamedMDNode * Named = M . getNamedMetadata ( <STR_LIT> ) ) { for ( const Metadata * MD : Named -> operands ( ) ) { const auto * Tuple = dyn_cast < MDTuple > ( MD ) ; if ( ! Tuple || Tuple -> getNumOperands ( ) != <NUM_LIT> ) continue ; const MDString * Name = dyn_cast < MDString > ( Tuple -> getOperand ( <NUM_LIT> ) ) ; const MDString * Contents = dyn_cast < MDString > ( Tuple -> getOperand ( <NUM_LIT> ) ) ; if ( ! Name || ! Contents ) continue ; OutStreamer -> PushSection ( ) ; std :: string SectionName = ( <STR_LIT> + Name -> getString ( ) ) . str ( ) ; MCSectionWasm * MySection = OutContext . getWasmSection ( SectionName , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( MySection ) ; OutStreamer -> EmitBytes ( Contents -> getString ( ) ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVDUPLANE ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> ConstantSDNode * ConstantSize = dyn_cast < ConstantSDNode > ( Size ) ; const <ISA_LIT>Subtarget & Subtarget = DAG . getMachineFunction ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned ClobberSet [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; assert ( ! isBaseRegConflictPossible ( DAG , ClobberSet ) ) ; if ( DstPtrInfo . getAddrSpace ( ) >= <NUM_LIT> ) return SDValue ( ) ; if ( ( Align & <NUM_LIT> ) != <NUM_LIT> || ! ConstantSize || ConstantSize -> getZExtValue ( ) > Subtarget . getMaxInlineSizeThreshold ( ) ) { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( Src ) ; if ( const char * bzeroEntry = V && V -> isNullValue ( ) ? Subtarget . getBZeroEntry ( ) : nullptr ) { EVT IntPtr = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; Type * IntPtrTy = getDataLayout ( ) -> getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Dst ; Entry . Ty = IntPtrTy ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( bzeroEntry , IntPtr ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = DAG . getTargetLoweringInfo ( ) . LowerCallTo ( CLI ) ; return CallResult . second ; } return SDValue ( ) ; } uint64_t SizeVal = ConstantSize -> getZExtValue ( ) ; SDValue InFlag ; EVT AVT ; SDValue Count ; ConstantSDNode * ValC = dyn_cast < ConstantSDNode > ( Src ) ; unsigned BytesLeft = <NUM_LIT> ; bool TwoRepStos = false ; if ( ValC ) { unsigned ValReg ; uint64_t Val = ValC -> getZExtValue ( ) & <NUM_LIT> ; switch ( Align & <NUM_LIT> ) { case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; break ; case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; Val = ( Val << <NUM_LIT> ) | Val ; if ( Subtarget . is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) { AVT = <STR_LIT> ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveNext ( SMLoc L ) { getTargetStreamer ( ) . EmitARM64WinCFISaveNext ( ) ;


<s> output_asm_insn ( <STR_LIT> , operands ) ; if ( TARGET_16_BIT ) return <STR_LIT> ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {

return hasFP ( MF ) ? FramePtr : StackPtr ;


<s> unsigned <ISA_LIT>SEInstrInfo :: getAnalyzableBrOpc ( unsigned Opc ) const { return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> } } else { if ( bundleSize == HEXAGON_PACKET_SIZE - <NUM_LIT> && fixupCount ) return false ; } if ( DisableShuffle ) return false ; unsigned maxBundleSize = ( <ISA_LIT>MCInstrInfo :: hasImmExt ( MCB ) ) ? HEXAGON_PACKET_SIZE : HEXAGON_PACKET_SIZE - <NUM_LIT> ; if ( bhasDuplex && bundleSize >= maxBundleSize ) return false ; <ISA_LIT>MCShuffler MCS ( MCII , STI , MCB , AddMI , false ) ; if ( ! MCS . reshuffleTo ( MCB ) ) { unsigned shuffleError = MCS . getError ( ) ;


<s> <ISA_LIT>PostRABundler ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>PostRABundlerPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> setLibcallName ( RTLIB :: UDIVREM_I32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: UDIVREM_I64 , <STR_LIT> ) ; setLibcallName ( RTLIB :: SDIVREM_I8 , <STR_LIT> ) ; setLibcallName ( RTLIB :: SDIVREM_I16 , <STR_LIT> ) ; setLibcallName ( RTLIB :: SDIVREM_I32 , <STR_LIT> ) ; setLibcallName ( RTLIB :: SDIVREM_I64 , <STR_LIT> ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ;

setMaximumJumpTableSize ( std :: min ( <NUM_LIT> , getMaximumJumpTableSize ( ) ) ) ;


<s> if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> ) return false ; if ( VT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) && ( VT . getScalarSizeInBits ( ) > <NUM_LIT> || Subtarget . hasBWI ( ) ) ) return true ; bool LShift = ( VT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ; bool AShift = LShift && ( Subtarget . hasAVX512 ( ) || ( VT != <STR_LIT> && VT != <STR_LIT> ) ) ; return ( Opcode == <STR_LIT> ) ? AShift : LShift ;


<s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , BasePtr ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ;


<s> if ( GET_CODE ( op ) != MEM ) return FALSE ; max_offset = ep_memory_offset ( mode , unsigned_load ) ; mask = GET_MODE_SIZE ( mode ) - <NUM_LIT> ; addr = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == CONST ) addr = XEXP ( addr , <NUM_LIT> ) ; switch ( GET_CODE ( addr ) ) { default : break ; case SYMBOL_REF : return SYMBOL_REF_TDA_P ( addr ) ; case REG : return REGNO ( addr ) == EP_REGNUM ; case PLUS : op0 = XEXP ( addr , <NUM_LIT> ) ; op1 = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) < max_offset && INTVAL ( op1 ) >= <NUM_LIT> && ( INTVAL ( op1 ) & mask ) == <NUM_LIT> ) { if ( GET_CODE ( op0 ) == REG && REGNO ( op0 ) == EP_REGNUM ) return TRUE ; if ( GET_CODE ( op0 ) == SYMBOL_REF && SYMBOL_REF_TDA_P ( op0 ) ) return TRUE ; } break ; }


<s> getOriginalFunctionArgs ( DAG , MF . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; <STR_LIT> Ext = <STR_LIT> ; if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) { Ext = <STR_LIT> ; }

unsigned ValBase = ArgLocs [ In . getOrigArgIndex ( ) ] . getLocMemOffset ( ) ;


<s> auto MaybeZero = getConstantVRegValWithLookThrough ( MaybeSub -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ;

return MaybeZero && MaybeZero -> Value . getZExtValue ( ) == <NUM_LIT> ;


<s> static bool IsCode ( const NodeAddr < NodeBase * > BA ) {

return BA . Addr -> getType ( ) == NodeAttrs :: Code && BA . Addr -> getKind ( ) == Kind ;


<s> FunctionPass * llvm :: create<ISA_LIT>RegNumbering ( ) { return new <ISA_LIT>RegNumbering ( ) ;


<s> Register R = Op . getReg ( ) ; if ( ! R . isVirtual ( ) ) continue ; Uses . insert ( R ) ;


<s> EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addExpr ( MCSymbolRefExpr :: create ( Label , MF -> getContext ( ) ) ) ) ; unsigned LdrOpcode = IsByteEntry ? <STR_LIT> : <STR_LIT> ; EmitToStreamer ( OutStreamer , MCInstBuilder ( LdrOpcode ) . addReg ( ScratchRegW ) . addReg ( TableReg ) . addReg ( EntryReg ) . addImm ( <NUM_LIT> ) . addImm ( IsByteEntry ? <NUM_LIT> : <NUM_LIT> ) ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( DestReg ) . addReg ( DestReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ) ;


<s> pass_stv ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_stv , ctxt ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , TargetOptions Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) {


<s> case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; case <STR_LIT> : case <STR_LIT> :

Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , RHS , LHS , Flags ) ;


<s> void function_expander :: add_address_operand ( rtx x ) { m_ops . safe_grow ( m_ops . length ( ) + <NUM_LIT> ) ;

create_address_operand ( & m_ops . last ( ) , x ) ;


<s> if ( selectImpl ( I , * CoverageInfo ) ) return true ; return false ;


<s> std :: tie ( BaseReg , ImmOffset ) = getBaseWithConstantOffset ( * B . getMRI ( ) , OrigOffset ) ; unsigned C1 = <NUM_LIT> ; if ( ImmOffset != <NUM_LIT> ) { unsigned Overflow = ImmOffset & ~ MaxImm ; ImmOffset -= Overflow ; if ( ( int32_t ) Overflow < <NUM_LIT> ) { Overflow += ImmOffset ; ImmOffset = <NUM_LIT> ; } C1 = ImmOffset ; if ( Overflow != <NUM_LIT> ) { if ( ! BaseReg ) BaseReg = B . buildConstant ( S32 , Overflow ) . getReg ( <NUM_LIT> ) ; else { auto OverflowVal = B . buildConstant ( S32 , Overflow ) ; BaseReg = B . buildAdd ( S32 , BaseReg , OverflowVal ) . getReg ( <NUM_LIT> ) ; } }


<s> operands [ i + <NUM_LIT> ] = lo ; operands [ i + <NUM_LIT> ] = hi ; } if ( reg_mentioned_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || GET_CODE ( operands [ <NUM_LIT> ] ) == ZERO_EXTRACT || GET_CODE ( operands [ <NUM_LIT> ] ) == ZERO_EXTRACT ) { rtx tmp ; tmp = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = tmp ; tmp = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = tmp ; } fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ;


<s> } MachineFunction * MF = MBB . getParent ( ) ; <ISA_LIT>FunctionInfo * XFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool emitFrameMoves = <ISA_LIT>RegisterInfo :: needsFrameMoves ( * MF ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator it = CSI . begin ( ) ; it != CSI . end ( ) ; ++ it ) { MBB . addLiveIn ( it -> getReg ( ) ) ; unsigned Reg = it -> getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; storeRegToStackSlot ( MBB , MI , Reg , true , it -> getFrameIdx ( ) , RC , & RI ) ; if ( emitFrameMoves ) { MCSymbol * SaveLabel = MF -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addSym ( SaveLabel ) ;

XFI -> getSpillLabels ( ) . push_back ( std :: make_pair ( SaveLabel , * it ) ) ;


<s> static __inline qword si_rotqmbi ( qword a , qword count ) { return ( ( qword ) ( vec_srl ( ( vec_uchar16 ) ( a ) , vec_sub ( vec_splat_u8 ( <NUM_LIT> ) , vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) ) ) ) ) ;


<s> return zeroExtendToI32 ( Reg , V , <STR_LIT> ) ;


<s> static enum tls_model tls_symbolic_operand_type ( rtx addr ) { enum tls_model tls_kind = TLS_MODEL_NONE ;


<s> if ( isAssociativeAndCommutative ( Inst . getOpcode ( ) ) && hasVirtualRegDefsInBasicBlock ( Inst , Inst . getParent ( ) ) && hasReassocSibling ( Inst , Commuted ) ) return true ; return false ;


<s> unsigned ValOps = <STR_LIT> ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI . getOperand ( ValOps ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI . getOperand ( ValOps + <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; MI . eraseFromParent ( ) ;


<s> StringRef getPassName ( ) const override {


<s> Function * Stxr = <STR_LIT> ( M , Int , Tys ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntValTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( Val -> getType ( ) ) ) ; Val = Builder . CreateBitCast ( Val , IntValTy ) ; CallInst * CI = Builder . CreateCall ( Stxr , { Builder . CreateZExtOrBitCast ( Val , Stxr -> getFunctionType ( ) -> getParamType ( <NUM_LIT> ) ) , Addr } ) ; CI -> addParamAttr ( <NUM_LIT> , Attribute :: get ( Builder . getContext ( ) , Attribute :: ElementType , Val -> getType ( ) ) ) ; return CI ;


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & Subtarget ;


<s> <STR_LIT> & GetType ( std :: vector < <STR_LIT> > & Types , size_t i ) {

Types . resize ( std :: max ( i + <NUM_LIT> , Types . size ( ) ) , <STR_LIT> ) ;


<s> M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) { F -> setCallingConv ( CallingConv :: Win64 ) ; F -> addParamAttr ( <NUM_LIT> , Attribute :: AttrKind :: InReg ) ;


<s> } case <STR_LIT> : { SDLoc DL ( N ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , lowerI128ToGR128 ( DAG , N -> getOperand ( <NUM_LIT> ) ) , N -> getOperand ( <NUM_LIT> ) } ; MachineMemOperand * MMO = cast < AtomicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Res = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <STR_LIT> , MMO ) ; if ( cast < AtomicSDNode > ( N ) -> getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) Res = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Res ) , <NUM_LIT> ) ; Results . push_back ( Res ) ; break ; } case <STR_LIT> : { SDLoc DL ( N ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , lowerI128ToGR128 ( DAG , N -> getOperand ( <NUM_LIT> ) ) , lowerI128ToGR128 ( DAG , N -> getOperand ( <NUM_LIT> ) ) } ; MachineMemOperand * MMO = cast < AtomicSDNode > ( N ) -> getMemOperand ( ) ; SDValue Res = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , <STR_LIT> , MMO ) ; SDValue Success = emitSETCC ( DAG , DL , Res . getValue ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> ) ; Success = DAG . getZExtOrTrunc ( Success , DL , N -> getValueType ( <NUM_LIT> ) ) ; Results . push_back ( lowerGR128ToI128 ( DAG , Res ) ) ; Results . push_back ( Success ) ;

Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ;


<s> break ; case <STR_LIT> : Src2Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; case <STR_LIT> : Src1Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DecodePUNPCKHMask ( <NUM_LIT> , ShuffleMask ) ; break ; case <STR_LIT> : Src2Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; case <STR_LIT> : Src1Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DecodePUNPCKHMask ( <NUM_LIT> , ShuffleMask ) ; break ; case <STR_LIT> : Src2Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; case <STR_LIT> : Src1Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DecodePUNPCKHMask ( <NUM_LIT> , ShuffleMask ) ; break ; case <STR_LIT> : Src2Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; case <STR_LIT> : Src1Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DecodePUNPCKLMask ( <NUM_LIT> , ShuffleMask ) ; break ; case <STR_LIT> : Src2Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; case <STR_LIT> : Src1Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DecodePUNPCKLMask ( <NUM_LIT> , ShuffleMask ) ; break ; case <STR_LIT> : Src2Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; case <STR_LIT> : Src1Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DecodePUNPCKLMask ( <NUM_LIT> , ShuffleMask ) ; break ; case <STR_LIT> : Src2Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; case <STR_LIT> : Src1Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; DecodePUNPCKLMask ( <NUM_LIT> , ShuffleMask ) ; break ; case <STR_LIT> : DecodeSHUFPSMask ( <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , ShuffleMask ) ; Src1Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Src2Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; break ; case <STR_LIT> : Src2Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; case <STR_LIT> : DecodeSHUFPSMask ( <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , ShuffleMask ) ; Src1Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; break ; case <STR_LIT> : Src2Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; case <STR_LIT> : DecodeUNPCKLPMask ( <NUM_LIT> , ShuffleMask ) ; Src1Name = getRegName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; break ;


<s> static SDValue getVectorMaskingNode ( SDValue Op , SDValue Mask , SDValue PreservedSrc , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { MVT VT = Op . getSimpleValueType ( ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; unsigned OpcodeSelect = <STR_LIT> ; SDLoc dl ( Op ) ; if ( isAllOnesConstant ( Mask ) ) return Op ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ; case <STR_LIT> :


<s> O << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> ;


<s> if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> :


<s> SmallVector < MachineBasicBlock * , <NUM_LIT> > Worklist ( MBB -> pred_begin ( ) , MBB -> pred_end ( ) ) ; while ( ! Worklist . empty ( ) ) {

MachineBasicBlock * MBB = Worklist . pop_back_val ( ) ;


<s> if ( decl != NULL_TREE ) switch_to_section ( function_section ( decl ) ) ;

ASM_OUTPUT_FUNCTION_LABEL ( f , name , decl ) ;


return ! ( MaxSize <= <NUM_LIT> ) && ( int ) Collection . size ( ) >= MaxSize ;


<s> } else if ( NeedFP ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , FramePtrReg ) . addReg ( StackPtrReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( RoundedSize != <NUM_LIT> && hasSP ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( RoundedSize * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } unsigned ScratchExecCopy = <STR_LIT> ; for ( const <ISA_LIT>MachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; if ( ScratchExecCopy == <STR_LIT> ) { if ( LiveRegs . empty ( ) ) { LiveRegs . init ( TRI ) ; LiveRegs . addLiveIns ( MBB ) ; } ScratchExecCopy = findScratchNonCalleeSaveRegister ( MF , LiveRegs , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , ScratchExecCopy ) . addImm ( - <NUM_LIT> ) ; }

TII -> storeRegToStackSlot ( MBB , MBBI , Reg . VGPR , true , Reg . FI . getValue ( ) , & <STR_LIT> , & TII -> getRegisterInfo ( ) ) ;


<s> IncomingValueHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , CCAssignFn AssignFn ) : ValueHandler ( MIRBuilder , MRI , AssignFn ) {


<s> virtual bool isCapTableLoad ( const MCInst & Inst , int64_t & Offset ) const override { if ( Inst . getOpcode ( ) == <STR_LIT> && ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { Offset = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; } else if ( Inst . getOpcode ( ) == <STR_LIT> && Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { Offset = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ;


<s> fprintf ( file , <STR_LIT> , reg_names [ GP_REG_FIRST ] ) ; output_addr_const ( file , x ) ; return ; case ADDRESS_SYMBOLIC : output_addr_const ( file , loongarch_strip_unspec_address ( x ) ) ; return ; } if ( CONST_INT_P ( x ) ) output_addr_const ( file , x ) ; else gcc_unreachable ( ) ;


<s> EVT PtrTy = Address -> getValueType ( <NUM_LIT> ) ; if ( Subtarget . isABI_N64 ( ) ) Offset = DAG . getNode ( <STR_LIT> , DL , PtrTy , Offset ) ;

Address = DAG . getNode ( <STR_LIT> , DL , PtrTy , Address , Offset ) ;


<s> std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case R600InstrInfo :: ALU_VEC_102 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case R600InstrInfo :: ALU_VEC_120 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case R600InstrInfo :: ALU_VEC_201 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; case R600InstrInfo :: ALU_VEC_210 : std :: swap ( Src [ <NUM_LIT> ] , Src [ <NUM_LIT> ] ) ; break ; }


<s> OptionalImmIndexMap OptionalIdx ; unsigned I = <NUM_LIT> ; const MCInstrDesc & Desc = MII . get ( Inst . getOpcode ( ) ) ; for ( unsigned J = <NUM_LIT> ; J < Desc . getNumDefs ( ) ; ++ J ) { ( ( <ISA_LIT>Operand & ) * Operands [ I ++ ] ) . addRegOperands ( Inst , <NUM_LIT> ) ; } for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( ! HasMods && Op . isReg ( ) ) { Op . addRegOperands ( Inst , <NUM_LIT> ) ; } else if ( HasMods && Op . isRegOrImmWithInputMods ( ) ) { Op . addRegOrImmWithInputModsOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isDPPCtrl ( ) ) { Op . addImmOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImm ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else {


<s> assert ( MI -> mayLoad ( ) && MI -> mayStore ( ) ) ; bool Changed = false ; if ( ( AddrSpace & <STR_LIT> ) != <STR_LIT> ) { switch ( Scope ) { case <STR_LIT> : Changed |= enableSC1Bit ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> break ; } if ( kind == vector_stmt || kind == vec_to_scalar ) if ( tree cmp_type = aarch64_embedded_comparison_type ( stmt_info ) ) { if ( FLOAT_TYPE_P ( cmp_type ) ) stmt_cost += simd_costs -> fp_stmt_cost ; else stmt_cost += simd_costs -> int_stmt_cost ; } } if ( kind == scalar_stmt ) if ( tree cmp_type = aarch64_embedded_comparison_type ( stmt_info ) ) { if ( FLOAT_TYPE_P ( cmp_type ) ) stmt_cost += aarch64_tune_params . vec_costs -> scalar_fp_stmt_cost ; else stmt_cost += aarch64_tune_params . vec_costs -> scalar_int_stmt_cost ; }


<s> type_suffix_index new_type = infer_vector_type ( argno ) ; if ( new_type == NUM_TYPE_SUFFIXES ) return false ; if ( type != new_type ) { error_at ( location , <STR_LIT> <STR_LIT> , get_vector_type ( new_type ) , argno + <NUM_LIT> , fndecl , get_vector_type ( type ) ) ; return false ;


<s> Mask . reserve ( MaskWidth ) ; for ( int i = <NUM_LIT> ; i < MaskWidth ; ++ i ) { int RootIdx = i / RootRatio ; if ( RootMask [ RootIdx ] < <NUM_LIT> ) { Mask . push_back ( RootMask [ RootIdx ] ) ; continue ; } int RootMaskedIdx = RootMask [ RootIdx ] * RootRatio + i % RootRatio ; int OpIdx = RootMaskedIdx / OpRatio ; if ( OpMask [ OpIdx ] < <NUM_LIT> ) { Mask . push_back ( OpMask [ OpIdx ] ) ; continue ; } Mask . push_back ( OpMask [ OpIdx ] * OpRatio + RootMaskedIdx % OpRatio ) ; } if ( llvm :: all_of ( Mask , [ ] ( int Idx ) { return Idx == SM_SentinelUndef ; } ) ) { DCI . CombineTo ( Root . getNode ( ) , DAG . getUNDEF ( Root . getValueType ( ) ) ) ; return true ; } if ( llvm :: all_of ( Mask , [ ] ( int Idx ) { return Idx < <NUM_LIT> ; } ) ) { DCI . CombineTo ( Root . getNode ( ) , getZeroVector ( Root . getSimpleValueType ( ) , Subtarget , DAG , SDLoc ( Root ) ) ) ; return true ; } int MaskSize = Mask . size ( ) ; bool UseInput0 = std :: any_of ( Mask . begin ( ) , Mask . end ( ) , [ MaskSize ] ( int Idx ) { return <NUM_LIT> <= Idx && Idx < MaskSize ; } ) ; bool UseInput1 = std :: any_of ( Mask . begin ( ) , Mask . end ( ) , [ MaskSize ] ( int Idx ) { return MaskSize <= Idx ; } ) ; if ( UseInput0 && UseInput1 ) return false ; else if ( UseInput1 ) { std :: swap ( Input0 , Input1 ) ; ShuffleVectorSDNode :: commuteMask ( Mask ) ;


<s> Optional < <ISA_LIT>Packet > ShuffledPacket = tryAuction ( Summary ) ; if ( ! ShuffledPacket ) { reportResourceError ( Summary , <STR_LIT> ) ; return false ; } llvm :: stable_sort ( * ShuffledPacket , <STR_LIT> ) ; HVXInstsT hvxInsts ; hvxInsts . clear ( ) ; for ( const auto & I : * ShuffledPacket ) { struct CVIUnits inst ;


<s> __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( rv ) : : <STR_LIT> ) ; break ; case RVV_VXRM : __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( rv ) : : <STR_LIT> ) ; break ; case RVV_VCSR : __asm__ __volatile__ ( <STR_LIT> : <STR_LIT> ( rv ) : : <STR_LIT> ) ; break ;


<s> if ( ! determineAndHandleAssignments ( Handler , Assigner , OutArgs , MIRBuilder , Info . CallConv , Info . IsVarArg ) ) return false ; Mask = getMaskForArgs ( OutArgs , Info , * TRI , MF ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCustomCallingConv ( ) ) TRI -> UpdateCustomCallPreservedMask ( MF , & Mask ) ; MIB . addRegMask ( Mask ) ; if ( TRI -> isAnyArgRegReserved ( MF ) ) TRI -> emitReservedArgRegCallError ( MF ) ; MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) constrainOperandRegClass ( MF , * TRI , MRI , * Subtarget . getInstrInfo ( ) , * Subtarget . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( Info . CallConv ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB ) ; bool UsingReturnedArg = ! OutArgs . empty ( ) && OutArgs [ <NUM_LIT> ] . Flags [ <NUM_LIT> ] . isReturned ( ) ; <ISA_LIT>OutgoingValueAssigner Assigner ( RetAssignFn , RetAssignFn , Subtarget , false ) ; ReturnedArgCallReturnHandler ReturnedArgHandler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( UsingReturnedArg ? ReturnedArgHandler : Handler , Assigner , InArgs , MIRBuilder , Info . CallConv , Info . IsVarArg , UsingReturnedArg ? OutArgs [ <NUM_LIT> ] . Regs [ <NUM_LIT> ] : Register ( ) ) ) return false ; } if ( Info . SwiftErrorVReg ) { MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; MIRBuilder . buildCopy ( Info . SwiftErrorVReg , Register ( <STR_LIT> ) ) ; } uint64_t CalleePopBytes = doesCalleeRestoreStack ( Info . CallConv , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ? alignTo ( Assigner . StackOffset , <NUM_LIT> ) : <NUM_LIT> ; CallSeqStart . addImm ( Assigner . StackOffset ) . addImm ( <NUM_LIT> ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( Assigner . StackOffset ) . addImm ( CalleePopBytes ) ; return true ;


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> ) ; if ( ! fndecl && fntype ) fputs ( <STR_LIT> , stderr ) ; if ( incoming ) fputs ( <STR_LIT> , stderr ) ; if ( fntype ) { tree ret_type = TREE_TYPE ( fntype ) ; fprintf ( stderr , <STR_LIT> , get_tree_code_name ( TREE_CODE ( ret_type ) ) ) ; } if ( libname && GET_CODE ( libname ) == SYMBOL_REF ) fprintf ( stderr , <STR_LIT> , XSTR ( libname , <NUM_LIT> ) ) ;

if ( cfun -> returns_struct ) fprintf ( stderr , <STR_LIT> ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { bool DestCPU = <STR_LIT> . contains ( DestReg ) ; bool SrcCPU = <STR_LIT> . contains ( SrcReg ) ; if ( DestCPU && SrcCPU ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( DestCPU ) { if ( <STR_LIT> . contains ( SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( SrcReg == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; else if ( SrcReg == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; } if ( SrcCPU ) { if ( <STR_LIT> . contains ( DestReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( <STR_LIT> . contains ( DestReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( DestReg == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( DestReg == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; }


<s> void <ISA_LIT>CodeEmitter :: emitMiscArithInstruction ( const MachineInstr & MI ) { const MCInstrDesc & MCID = MI . getDesc ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; if ( MCID . Opcode == <STR_LIT> || MCID . Opcode == <STR_LIT> ) { emitWordLE ( Binary ) ; return ; } unsigned OpIdx = <NUM_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; const MachineOperand & MO = MI . getOperand ( OpIdx ++ ) ; if ( OpIdx == MCID . getNumOperands ( ) || MCID . OpInfo [ OpIdx ] . isPredicate ( ) || MCID . OpInfo [ OpIdx ] . isOptionalDef ( ) ) { Binary |= getMachineOpValue ( MI , MO ) ; emitWordLE ( Binary ) ; return ; } Binary |= getMachineOpValue ( MI , MO ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; unsigned ShiftAmt = MI . getOperand ( OpIdx ) . getImm ( ) ; if ( MCID . Opcode == <STR_LIT> ) { assert ( ShiftAmt != <NUM_LIT> && <STR_LIT> ) ; if ( ShiftAmt == <NUM_LIT> ) ShiftAmt = <NUM_LIT> ; } assert ( ShiftAmt < <NUM_LIT> && <STR_LIT> ) ; Binary |= ShiftAmt << <STR_LIT> ;


<s> subrtx_iterator :: array_type array ; int insn_count ; CLEAR_HARD_REG_SET ( modregs ) ; insn_count = <NUM_LIT> ; FOR_BB_INSNS_REVERSE ( loop -> latch , insn ) { if ( ! INSN_P ( insn ) || INSN_CODE ( insn ) <= <NUM_LIT> ) continue ; insn_count ++ ; if ( insn_count > S390_OSC_SCAN_INSN_NUM ) return false ; find_all_hard_reg_sets ( insn , & newregs , true ) ; modregs |= newregs ; set = single_set ( insn ) ; if ( ! set ) continue ; if ( MEM_P ( SET_DEST ( set ) ) && s390_decompose_address ( XEXP ( SET_DEST ( set ) , <NUM_LIT> ) , & addr_store ) ) { store_insn = insn ; break ; } }

if ( store_insn == NULL_RTX ) return false ;


<s> return getSubtargetImpl ( ) -> getInstrInfo ( ) ;


<s> bool isDPRCalleeSavedAreaFrame ( int fi ) const {

if ( fi < <NUM_LIT> || fi >= ( int ) DPRCSFrames . size ( ) ) return false ;


<s> dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , x ) ; break ; case TLS_MODEL_LOCAL_EXEC : insns = microblaze_call_tls_get_addr ( x , reg , & ret , TLS_LDM ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ;

emit_libcall_block ( insns , dest , ret , eqv ) ;


<s> virtual void PrintGlobalVariable ( const GlobalVariable * GV ) {


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) { Ops . append ( N -> op_begin ( ) , N -> op_end ( ) ) ; return true ; } if ( N -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; SDValue Sub = N -> getOperand ( <NUM_LIT> ) ; const APInt & Idx = N -> getConstantOperandAPInt ( <NUM_LIT> ) ; EVT VT = Src . getValueType ( ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectOpUndef ( Register ResVReg , const <ISA_LIT>Type * ResType , MachineInstr & I ) const { return BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( ResVReg ) . addUse ( GR . get<ISA_LIT>TypeID ( ResType ) ) . constrainAllUses ( TII , TRI , RBI ) ;


<s> auto Res = std :: make_unique < <ISA_LIT>Operand > ( OpKind :: Rhu , StartLoc , EndLoc ) ; Res -> Rhu . Val = Val ; return Res ;


<s> const SCEVConstant * PHIBasePtrIncSCEV = dyn_cast < SCEVConstant > ( PHIBasePtrSCEV -> getStepRecurrence ( * SE ) ) ; if ( ! PHIBasePtrIncSCEV ) continue ; if ( CurrentPHINode -> getNumIncomingValues ( ) == <NUM_LIT> ) { if ( ( CurrentPHINode -> getIncomingBlock ( <NUM_LIT> ) == LatchBB && CurrentPHINode -> getIncomingBlock ( <NUM_LIT> ) == PredBB ) || ( CurrentPHINode -> getIncomingBlock ( <NUM_LIT> ) == LatchBB && CurrentPHINode -> getIncomingBlock ( <NUM_LIT> ) == PredBB ) ) { if ( PHIBasePtrIncSCEV == BasePtrIncSCEV ) { if ( Form == UpdateForm && PHIBasePtrSCEV -> getStart ( ) == BasePtrStartSCEV ) { ++ PHINodeAlreadyExistsUpdate ; return true ; } if ( Form == DSForm || Form == DQForm ) { const SCEVConstant * Diff = dyn_cast < SCEVConstant > ( SE -> getMinusSCEV ( PHIBasePtrSCEV -> getStart ( ) , BasePtrStartSCEV ) ) ; if ( Diff && ! Diff -> getAPInt ( ) . urem ( Form ) ) { if ( Form == DSForm ) ++ PHINodeAlreadyExistsDS ; else ++ PHINodeAlreadyExistsDQ ; return true ; }


<s> break ; case <STR_LIT> : lowerScalarAbs ( Worklist , Inst ) ; Inst -> eraseFromParent ( ) ; continue ; case <STR_LIT> : case <STR_LIT> : BuildMI ( * MBB , Inst , Inst -> getDebugLoc ( ) , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpcode == <STR_LIT> ) { legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst -> setDesc ( NewDesc ) ; for ( unsigned i = Inst -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) { Inst -> RemoveOperand ( i ) ; addSCCDefUsersToVALUWorklist ( Inst , Worklist ) ; } } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Inst -> addImplicitDefUseOperands ( * Inst -> getParent ( ) -> getParent ( ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & OffsetWidthOp = Inst -> getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst -> RemoveOperand ( <NUM_LIT> ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; } bool HasDst = Inst -> getOperand ( <NUM_LIT> ) . isReg ( ) && Inst -> getOperand ( <NUM_LIT> ) . isDef ( ) ; unsigned NewDstReg = <STR_LIT> ; if ( HasDst ) { const TargetRegisterClass * NewDstRC = getDestEquivalentVGPRClass ( * Inst ) ; if ( ! NewDstRC ) continue ; unsigned DstReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ;

MRI . replaceRegWith ( DstReg , NewDstReg ) ;


<s> if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } }


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;

else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> void addImmSExt8Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> return new <ISA_LIT>MCAsmInfo ( TT ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ;


<s> bool isAmdCodeObjectV2 ( const MachineFunction & MF ) const { return isAmdHsaOS ( ) || isMesaKernel ( MF ) ;


<s> const InstructionMapping & SSMapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( { <STR_LIT> ( <STR_LIT> , Size ) , <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) } ) , <NUM_LIT> ) ; AltMappings . push_back ( & SSMapping ) ; const InstructionMapping & VVMapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( { <STR_LIT> ( <STR_LIT> , Size ) , <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) } ) , <NUM_LIT> ) ; AltMappings . push_back ( & VVMapping ) ; const InstructionMapping & VSMapping = getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( { <STR_LIT> ( <STR_LIT> , Size ) , <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) } ) , <NUM_LIT> ) ; AltMappings . push_back ( & VSMapping ) ; return AltMappings ; } default : break ;


printRegName ( raw_ostream & O , unsigned RegNo ) const {


<s> return findOneNVVMAnnotation ( & F , <STR_LIT> , x ) ;


<s> <ISA_LIT>AsmBackend ( ) : MCAsmBackend ( ) {


<s> mark_reg_pointer ( tp , BITS_PER_WORD ) ; return tp ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const override {


<s> const GlobalObject * GO = cast < GlobalObject > ( GV ) ; const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( GO ) ; return getAIXFuncEntryPointSymbolSDNode ( GO -> getName ( ) , GO -> isDeclaration ( ) , SC ) ; } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { const char * SymName = S -> getSymbol ( ) ; if ( ! Subtarget . isAIXABI ( ) ) return DAG . getTargetExternalSymbol ( SymName , Callee . getValueType ( ) , UsePlt ? <STR_LIT> : <NUM_LIT> ) ; const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; if ( const Function * F = dyn_cast_or_null < Function > ( Mod -> getNamedValue ( SymName ) ) ) { const XCOFF :: StorageClass SC = TargetLoweringObjectFileXCOFF :: getStorageClassForGlobal ( F ) ; return getAIXFuncEntryPointSymbolSDNode ( F -> getName ( ) , F -> isDeclaration ( ) , SC ) ; } if ( isValidAIXExternalSymSDNode ( SymName ) ) { return getAIXFuncEntryPointSymbolSDNode ( SymName , true , XCOFF :: C_EXT ) ; }

report_fatal_error ( <STR_LIT> + Twine ( SymName ) ) ;


<s> _mm_cvttsh_i64 ( __m128h __A ) { return ( long long ) __builtin_ia32_vcvttsh2si64_round ( __A , _MM_FROUND_CUR_DIRECTION ) ;


<s> mode = TYPE_MODE ( type ) ; if ( INTEGRAL_TYPE_P ( type ) ) PROMOTE_FUNCTION_MODE ( mode , unsignedp , type ) ; if ( arm_return_in_msb ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ;

if ( size % UNITS_PER_WORD != <NUM_LIT> ) {


<s> if ( ! TRI . isVirtualRegister ( Reg ) ) continue ; auto * NewRC = MRI . constrainRegClass ( Reg , TII . getRegClass ( NewMI . getDesc ( ) , Idx , & TRI , MF ) ) ; if ( ! NewRC ) {

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Idx << <STR_LIT> ;