<s> if ( ! ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ) == Bytes && llvm :: getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ) return false ;

return CheckCPSRDef ? ! definesCPSR ( MI ) : true ;


<s> break ; case <STR_LIT> : break ; } } const MachineOperand * Src1 = TII -> getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src1Mod = TII -> getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; if ( Src1 && ( ! isVGPR ( Src1 , TRI , MRI ) || ( Src1Mod && Src1Mod -> getImm ( ) != <NUM_LIT> ) ) ) return false ; if ( TII -> hasModifiersSet ( MI , <STR_LIT> :: src0_modifiers ) ) return false ; if ( TII -> hasModifiersSet ( MI , <STR_LIT> :: omod ) ) return false ;

return ! TII -> hasModifiersSet ( MI , <STR_LIT> :: clamp ) ;


<s> if ( TM -> getOptLevel ( ) > CodeGenOpt :: Less ) insertPass ( & MachineSchedulerID , & <ISA_LIT>FormMemoryClausesID ) ; insertPass ( & PHIEliminationID , & <ISA_LIT>LowerControlFlowID , false ) ; if ( EnableDCEInRA ) insertPass ( & DetectDeadLanesID , & DeadMachineInstructionElimID ) ;

TargetPassConfig :: addOptimizedRegAlloc ( ) ;


<s> static MCSubtargetInfo * createMandarinMCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ;

InitMandarinMCSubtargetInfo ( X , TT , CPU , FS ) ;


return ( __m256 ) __builtin_ia32_vbroadcastss256 ( __X ) ;


<s> unsigned numOp = MI . getDesc ( ) . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = numOp ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ;


<s> if ( NumBytes >= IMM_LOW ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( NumBytes ) . addReg ( <STR_LIT> ) ; } else if ( getUpper16 ( NumBytes ) >= IMM_LOW ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( getUpper16 ( NumBytes ) ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( getLower16 ( NumBytes ) ) . addReg ( <STR_LIT> ) ; } else { std :: string msg ; raw_string_ostream Msg ( msg ) ; Msg << <STR_LIT> << NumBytes ; llvm_report_error ( Msg . str ( ) ) ; } if ( FP ) {

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> ) ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned Width ;

return getMemOpBaseRegImmOfsWidth ( LdSt , BaseReg , Offset , Width , TRI ) ;


<s> MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned PredOpc = getCondOpcode ( Opc , invertJump ) ; MachineInstrBuilder T = BuildMI ( B , MI , DL , get ( PredOpc ) ) ; unsigned NOp = <NUM_LIT> , NumOps = MI -> getNumOperands ( ) ; while ( NOp < NumOps ) { MachineOperand & Op = MI -> getOperand ( NOp ) ; if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isImplicit ( ) ) break ; T . addOperand ( Op ) ; NOp ++ ; } unsigned PredReg , PredRegPos , PredRegFlags ; bool GotPredReg = getPredReg ( Cond , PredReg , PredRegPos , PredRegFlags ) ;


<s> void <ISA_LIT>MCAsmStreamer :: EmitInstruction ( const MCInst & Inst ) { assert ( getCurrentSection ( ) && <STR_LIT> ) ; if ( Emitter ) AddEncodingComment ( Inst ) ; if ( ShowInst ) { Inst . dump_pretty ( GetCommentOS ( ) , & MAI , InstPrinter . get ( ) , <STR_LIT> ) ; GetCommentOS ( ) << <STR_LIT> ; } if ( InstPrinter ) InstPrinter -> printInst ( & Inst , OS ) ;


<s> return __builtin_aarch64_floatunsv2siv2sf ( ( int32x2_t ) __a ) ;


<s> SmallVector < Value * , <NUM_LIT> > NewOperands ; unsigned NumOperands = C -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { Value * Operand = C -> getOperand ( i ) ; Value * NewOperand = remapConstant ( M , F , cast < Constant > ( Operand ) , Builder ) ; OperandChanged |= Operand != NewOperand ; NewOperands . push_back ( NewOperand ) ; } if ( ! OperandChanged ) { return C ; } unsigned Opcode = C -> getOpcode ( ) ; switch ( Opcode ) { case Instruction :: ICmp : return Builder . CreateICmp ( CmpInst :: Predicate ( C -> getPredicate ( ) ) , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: FCmp : assert ( false && <STR_LIT> <STR_LIT> ) ; return C ; case Instruction :: ExtractElement : return Builder . CreateExtractElement ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: InsertElement : return Builder . CreateInsertElement ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: ShuffleVector : return Builder . CreateShuffleVector ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: ExtractValue : return Builder . CreateExtractValue ( NewOperands [ <NUM_LIT> ] , C -> getIndices ( ) ) ; case Instruction :: InsertValue : return Builder . CreateInsertValue ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , C -> getIndices ( ) ) ; case Instruction :: GetElementPtr :

return cast < GEPOperator > ( C ) -> isInBounds ( ) ? Builder . CreateGEP ( cast < GEPOperator > ( C ) -> getSourceElementType ( ) , NewOperands [ <NUM_LIT> ] , makeArrayRef ( & NewOperands [ <NUM_LIT> ] , NumOperands - <NUM_LIT> ) ) : Builder . CreateInBoundsGEP ( cast < GEPOperator > ( C ) -> getSourceElementType ( ) , NewOperands [ <NUM_LIT> ] , makeArrayRef ( & NewOperands [ <NUM_LIT> ] , NumOperands - <NUM_LIT> ) ) ;


<s> const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> static machine_mode ia64_get_reg_raw_mode ( int regno ) { if ( FR_REGNO_P ( regno ) ) return XFmode ; return default_get_reg_raw_mode ( regno ) ;


<s> HasV8Ops = false ; HasVFPv2 = false ; HasVFPv3 = false ; HasVFPv4 = false ; HasFP<ISA_LIT>v8 = false ; HasNEON = false ; UseNEONForSinglePrecisionFP = false ; UseMulOps = UseFusedMulOps ; SlowFPVMLx = false ; HasVMLxForwarding = false ; SlowFPBrcc = false ; InThumbMode = false ; HasThumb2 = false ; No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; AllowsUnalignedMem = false ; Thumb2DSP = false ;


<s> break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : Kind = VK_<ISA_LIT>_HIGHEST ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }

return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr ) ;


<s> DCRegisterSema :: FinalizeBasicBlock ( ) ; clearCCSF ( ) ;


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) {


<s> Base = AM . Base ; if ( ! Base . getNode ( ) ) Base = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( Base . getOpcode ( ) == <STR_LIT> ) { int64_t FrameIndex = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Offset = CurDAG -> getTargetFrameIndex ( FrameIndex , VT ) ; Base = CurDAG -> getTargetConstant ( AM . Offset , SDLoc ( Base ) , VT ) ; return ; } else if ( Base . getValueType ( ) != VT ) { assert ( VT == <STR_LIT> && Base . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc DL ( Base ) ; SDValue Trunc = CurDAG -> getNode ( <STR_LIT> , DL , VT , Base ) ; insertDAGNode ( CurDAG , Base . getNode ( ) , Trunc ) ; Base = Trunc ; }

Offset = CurDAG -> getTargetConstant ( AM . Offset , SDLoc ( Base ) , VT ) ;


return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , b . XOR ( Tmp , b . SHL < <NUM_LIT> > ( b . AND ( A1 , A2 ) ) ) , Tmp ) ;


<s> SDLoc dl ( N ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned NumElts = SrcOps [ <NUM_LIT> ] . getValueType ( ) . getVectorNumElements ( ) ; EVT MaskVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; SDValue Mask = combineBitcastvxi1 ( DAG , MaskVT , SrcOps [ <NUM_LIT> ] , dl , Subtarget ) ; if ( ! Mask && TLI . isTypeLegal ( SrcOps [ <NUM_LIT> ] . getValueType ( ) ) ) Mask = DAG . getBitcast ( MaskVT , SrcOps [ <NUM_LIT> ] ) ; if ( Mask ) { APInt AllBits = APInt :: getNullValue ( NumElts ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , DAG . getConstant ( AllBits , dl , MaskVT ) , <STR_LIT> ) ; } } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = canonicalizeBitSelect ( N , DAG , Subtarget ) ) return R ; if ( SDValue R = combineLogicBlendIntoPBLENDV ( N , DAG , Subtarget ) ) return R ;

if ( SDValue R = combineOrShiftToFunnelShift ( N , DAG , Subtarget ) ) return R ;


<s> if ( memory_operand ( operands [ <NUM_LIT> ] , mode ) ) return register_or_zero_operand ( operands [ <NUM_LIT> ] , mode ) ; return true ;


<s> static bool isDirectJump ( const MachineInstr & MI ) {

return MI . getOpcode ( ) == <STR_LIT> ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , Reg , getPointerTy ( ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , Flag ) ;

else return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ) ;


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ;


<s> basic_block * bbs ; rtx_insn * insn ; unsigned i ; unsigned mem_count = <NUM_LIT> ; if ( s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196 && s390_tune != PROCESSOR_2827_ZEC12 ) return nunroll ; bbs = get_loop_body ( loop ) ; subrtx_iterator :: array_type array ; for ( i = <NUM_LIT> ; i < loop -> num_nodes ; i ++ ) FOR_BB_INSNS ( bbs [ i ] , insn ) if ( INSN_P ( insn ) && INSN_CODE ( insn ) != - <NUM_LIT> ) FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , NONCONST ) if ( MEM_P ( * iter ) ) mem_count += <NUM_LIT> ; free ( bbs ) ; if ( mem_count == <NUM_LIT> ) return nunroll ; switch ( loop_depth ( loop ) ) { case <NUM_LIT> : return MIN ( nunroll , <NUM_LIT> / mem_count ) ;


<s> std :: vector < unsigned > regList ; for ( auto & rec : regRecord ) {

if ( rec . fName == fName && rec . reg >= <STR_LIT> && rec . reg <= <STR_LIT> ) regList . push_back ( rec . reg ) ;


<s> if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> / <NUM_LIT> ) return false ;

return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> return __builtin_mve_vldrbq_z_sv16qi ( ( __builtin_neon_qi * ) __base , __p ) ;


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ;

SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ;


<s> bool <ISA_LIT>Subtarget :: GVIsIndirectSymbol ( GlobalValue * GV , Reloc :: Model RelocM ) const { if ( RelocM == Reloc :: Static ) return false ; bool isDecl = GV -> isDeclaration ( ) && ! GV -> isMaterializable ( ) ; if ( ! isTargetDarwin ( ) ) { if ( GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ) return false ; return true ;


<s> default : debug ( <STR_LIT> ) ; return true ; case ENCODING_REG : translateRegister ( mcInst , insn . reg ) ; return false ; case ENCODING_RM : return translateRM ( mcInst , operand , insn ) ; case ENCODING_CB : case ENCODING_CW : case ENCODING_CD : case ENCODING_CP : case ENCODING_CO : case ENCODING_CT : debug ( <STR_LIT> ) ; return true ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn ) ; return false ; case ENCODING_RB : case ENCODING_RW : case ENCODING_RD : case ENCODING_RO : translateRegister ( mcInst , insn . opcodeRegister ) ; return false ;


<s> if ( TARGET_DSBT ) { struct cgraph_local_info * this_func ; if ( ! decl ) return false ; this_func = cgraph_node :: local_info ( current_function_decl ) ; return this_func -> local ; }


<s> Op -> StartLoc = S ; Op -> EndLoc = S ; return Op ;


<s> return new <ISA_LIT>AsmBackend ( T , CPU ) ;


<s> unsigned LR = RegInfo -> getRARegister ( ) ; if ( ! DisableRedZone && ( Subtarget . is<ISA_LIT>64 ( ) || ! Subtarget . isSVR4ABI ( ) || FrameSize == <NUM_LIT> ) && FrameSize <= <NUM_LIT> && ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ) { if ( UpdateMF ) MFI . setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setStackSize ( FrameSize ) ; return FrameSize ;


<s> const Function * F = MF -> getFunction ( ) ; ghcCall = ( F ? F -> getCallingConv ( ) == CallingConv :: GHC : false ) ; } if ( ghcCall ) { return CSR_GHC_SaveList ;


<s> const MCExpr * Four = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO :: getTTypeGlobalReference ( GV , Encoding , TM , MMI , Streamer ) ;


<s> IsConstantInSmallSection ( const Constant * CN , const TargetMachine & TM ) const { return ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . useSmallSection ( ) && LocalSData && IsInSmallSection ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) -> getTypeAllocSize ( CN -> getType ( ) ) ) ) ;


<s> return MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) . needsUnwindTableEntry ( ) ;


<s> return ( OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_ ) && OpId != OP_GS_NOP ; case ID_GS_DONE : return OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_ ;


<s> Opc = UseGOTOFF ? <STR_LIT> : <STR_LIT> ; } else { DestReg1 = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg1 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg1 ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ) ; Opc = UseGOTOFF ? <STR_LIT> : <STR_LIT> ; } unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg == <NUM_LIT> ) { GlobalBaseReg = MRI . createVirtualRegister ( TLI . getRegClassFor ( VT ) ) ; AFI -> setGlobalBaseReg ( GlobalBaseReg ) ; } unsigned DestReg2 = createResultReg ( TLI . getRegClassFor ( VT ) ) ; DestReg2 = constrainOperandRegClass ( TII . get ( Opc ) , DestReg2 , <NUM_LIT> ) ; DestReg1 = constrainOperandRegClass ( TII . get ( Opc ) , DestReg1 , <NUM_LIT> ) ; GlobalBaseReg = constrainOperandRegClass ( TII . get ( Opc ) , GlobalBaseReg , <NUM_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg2 ) . addReg ( DestReg1 ) . addReg ( GlobalBaseReg ) ;

if ( ! UseGOTOFF ) MIB . addImm ( <NUM_LIT> ) ;


<s> if ( Ins . empty ( ) ) return NotStructReturn ; const <STR_LIT> & Flags = Ins [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ;

if ( Flags . isInReg ( ) || IsMCU ) return RegStructReturn ;


<s> bool mips_use_ins_ext_p ( rtx op , HOST_WIDE_INT width , HOST_WIDE_INT bitpos ) { if ( ! ISA_HAS_EXT_INS || ! register_operand ( op , VOIDmode ) || GET_MODE_BITSIZE ( GET_MODE ( op ) ) > BITS_PER_WORD ) return false ; if ( ! IN_RANGE ( width , <NUM_LIT> , GET_MODE_BITSIZE ( GET_MODE ( op ) ) - <NUM_LIT> ) ) return false ; if ( bitpos < <NUM_LIT> || bitpos + width > GET_MODE_BITSIZE ( GET_MODE ( op ) ) ) return false ; return true ;


<s> return false ; } else if ( ! <ISA_LIT>MCInstrInfo :: isBundle ( MCB ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } bool doneShuffling = false ; while ( possibleDuplexes . size ( ) > <NUM_LIT> && ( ! doneShuffling ) ) { DuplexCandidate duplexToTry = possibleDuplexes . pop_back_val ( ) ; MCInst Attempt ( MCB ) ; <ISA_LIT>MCInstrInfo :: replaceDuplex ( Context , Attempt , duplexToTry ) ; <ISA_LIT>MCShuffler MCS ( Context , false , MCII , STI , Attempt ) ; if ( MCS . size ( ) == <NUM_LIT> ) { MCS . copyTo ( MCB ) ; return false ; } doneShuffling = MCS . reshuffleTo ( MCB ) ; if ( doneShuffling ) break ;


<s> return ( __a + ( __b * __aarch64_vget_lane_any ( __c , __lane ) ) ) ;


<s> for ( SDNode :: use_iterator UI = Op -> use_begin ( ) , UE = Op -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; unsigned UOpNo = UI . getOperandNo ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> && User -> hasOneUse ( ) ) {

UOpNo = User -> use_begin ( ) . getOperandNo ( ) ;


<s> if ( isDarwinABI || is<ISA_LIT>64 ) return ( isELFv2ABI ? <NUM_LIT> : <NUM_LIT> ) * ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ;


<s> assert ( ! Op . getSubReg ( ) || ! Op . isUndef ( ) ) ; RegInterval Result ; unsigned Reg = TRI -> getEncodingValue ( <STR_LIT> ( Op . getReg ( ) , * ST ) ) ; if ( TRI -> isVGPR ( * MRI , Op . getReg ( ) ) ) { assert ( Reg >= RegisterEncoding . VGPR0 && Reg <= RegisterEncoding . VGPRL ) ; Result . first = Reg - RegisterEncoding . VGPR0 ; assert ( Result . first >= <NUM_LIT> && Result . first < SQ_MAX_PGM_VGPRS ) ; } else if ( TRI -> isSGPRReg ( * MRI , Op . getReg ( ) ) ) { assert ( Reg >= RegisterEncoding . SGPR0 && Reg < SQ_MAX_PGM_SGPRS ) ;

Result . first = Reg - RegisterEncoding . SGPR0 + NUM_ALL_VGPRS ;


<s> static enum mips_symbol_type mips_classify_symbolic_expression ( rtx x , enum mips_symbol_context context ) {


<s> Record . push_back ( VE . getMetadataOrNullID ( N -> getRawDirectory ( ) ) ) ;

Stream . EmitRecord ( bitc :: METADATA_FILE , Record , Abbrev ) ;


<s> index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

Inst . addOperand ( MCOperand :: createImm ( index ) ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateMatrixRegister ( unsigned RegNum , unsigned ElementWidth , MatrixKind Kind , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_MatrixRegister , Ctx ) ; Op -> MatrixReg . RegNum = RegNum ; Op -> MatrixReg . ElementWidth = ElementWidth ; Op -> MatrixReg . Kind = Kind ; Op -> StartLoc = S ;


<s> assert ( ResourcesModel && <STR_LIT> ) ; Packet . resize ( SchedModel -> getIssueWidth ( ) ) ; Packet . clear ( ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { if ( Subtarget -> isTargetEnvMacho ( ) ) OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( Subtarget -> isTargetCOFF ( ) ) { if ( ! Subtarget -> is64Bit ( ) ) {

MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ;


<s> SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) ) ; ReplaceUses ( N , Result_3 ) ; return Result_3 ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDNode * RsPd = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IsIntrinsic , <NUM_LIT> ) ) ; ReplaceUses ( N , RsPd ) ; return RsPd ; } assert ( <NUM_LIT> && <STR_LIT> ) ; } }


<s> explicit DynsymGOTCompare ( const <ISA_LIT>GOT & pGOT ) : m_pGOT ( pGOT ) {


<s> return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> unsigned <ISA_LIT>ABIInfo :: GetNullPtr ( ) const {


<s> MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Base . isReg ( ) ) { Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . add ( Base ) ; return Reg ; } Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , Reg ) . add ( Base ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> MSAC ( ) : MachineFunctionPass ( & ID ) {


<s> if ( II . getNumDefs ( ) >= <NUM_LIT> ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addImm ( Imm1 ) . addImm ( Imm2 ) ) ; else {

AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addImm ( Imm1 ) . addImm ( Imm2 ) ) ;


<s> return ( __m512i ) __builtin_ia32_cvttps2udq512_mask ( ( __v16sf ) __A , ( __v16si ) _mm512_undefined_epi32 ( ) , ( __mmask16 ) - <NUM_LIT> , __R ) ;


<s> unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; assert ( ( NumOps == <STR_LIT> + <NUM_LIT> || NumOps == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI -> getOperand ( NumOps - <NUM_LIT> ) ) ; bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( ! KillsSrc && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) { duplicateToTop ( Reg , ScratchFPReg , I ) ; } else { moveToTop ( Reg , I ) ; } MI -> RemoveOperand ( NumOps - <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) {

if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ;


<s> virtual void storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {

storeRegToStack ( MBB , MBBI , SrcReg , isKill , FrameIndex , RC , TRI , <NUM_LIT> ) ;


<s> if ( ! isAMXIntrinsic ( Tile ) ) return ; auto * II = cast < IntrinsicInst > ( Tile ) ; Value * Row = II -> getOperand ( <NUM_LIT> ) ; Value * Col = II -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( ST ) ; Value * Stride = Builder . getInt64 ( <NUM_LIT> ) ; Value * I8Ptr = Builder . CreateBitCast ( ST -> getOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride , Tile } ;

Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ;


<s> return MachineJumpTableInfo :: EK_Custom32 ;


<s> FunctionPass * llvm :: createCleanupLocalDynamicTLSPass ( ) {


<s> for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MBB = I -> first ; Cycles = I -> second ; if ( Cycles < Threshold ) { assert ( MBB -> size ( ) > <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock :: iterator ReturnLoc = -- MBB -> end ( ) ; while ( ReturnLoc -> isDebugValue ( ) ) -- ReturnLoc ; assert ( ReturnLoc -> isReturn ( ) && ! ReturnLoc -> isCall ( ) && <STR_LIT> ) ;

addPadding ( MBB , ReturnLoc , Threshold - Cycles ) ;


<s> return true ; } if ( L . isProperty ( ) ) return add ( L . properties ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < L . size ( ) ; ++ i ) {

const Constant * LC = L . Values [ i ] ;


<s> if ( FLOAT_MODE_P ( GET_MODE ( x ) ) ) return LOAD_FPU_REGS ; else return GENERAL_REGS ; } return rclass ;


<s> return llvm :: any_of ( MI . memoperands ( ) , [ ] ( MachineMemOperand * MMO ) { return MMO -> getFlags ( ) & MOSuppressPair ;


<s> static bool mbbHasBackEdge ( MachineBasicBlock * MBB , SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > & MBBs ) { for ( auto <ISA_LIT> = MBB -> succ_begin ( ) , SE = MBB -> succ_end ( ) ; <ISA_LIT> != SE ; ++ <ISA_LIT> ) { if ( MBBs . count ( * <ISA_LIT> ) != <NUM_LIT> ) { return true ;


<s> EndLoc = Parser . getTok ( ) . getEndLoc ( ) ; RegNo = tryParseRegister ( ) ;

return ( RegNo == ( unsigned ) - <NUM_LIT> ) ;


<s> CommentStream = & cStream ; InternalInstruction internalInstr ; dlog_t loggerFn = logger ; if ( & vStream == & nulls ( ) ) loggerFn = <NUM_LIT> ; int ret = decodeInstruction ( & internalInstr , regionReader , ( void * ) & region , loggerFn , ( void * ) & vStream , ( void * ) MII , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return Fail ; }


<s> isSGPR = false ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned hwReg = RI -> getEncodingValue ( reg ) & <NUM_LIT> ; unsigned maxUsed = hwReg + width - <NUM_LIT> ; if ( isSGPR ) { MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR ; } else { MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR ; } } } } if ( VCCUsed ) MaxSGPR += <NUM_LIT> ; if ( FlatUsed ) MaxSGPR += <NUM_LIT> ; ProgInfo . NumVGPR = MaxVGPR + <NUM_LIT> ; ProgInfo . NumSGPR = MaxSGPR + <NUM_LIT> ; if ( STM . hasSGPRInitBug ( ) ) { if ( ProgInfo . NumSGPR > <ISA_LIT>Subtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG ) { LLVMContext & Ctx = MF . getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> ) ; } ProgInfo . NumSGPR = <ISA_LIT>Subtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG ; } ProgInfo . VGPRBlocks = ( ProgInfo . NumVGPR - <NUM_LIT> ) / <NUM_LIT> ; ProgInfo . SGPRBlocks = ( ProgInfo . NumSGPR - <NUM_LIT> ) / <NUM_LIT> ; ProgInfo . FloatMode = getFPMode ( MF ) ; ProgInfo . IEEEMode = <NUM_LIT> ; ProgInfo . DX10Clamp = <NUM_LIT> ; const MachineFrameInfo * FrameInfo = MF . getFrameInfo ( ) ; ProgInfo . ScratchSize = FrameInfo -> estimateStackSize ( MF ) ; ProgInfo . FlatUsed = FlatUsed ; ProgInfo . VCCUsed = VCCUsed ; ProgInfo . CodeLen = CodeSize ; unsigned LDSAlignShift ; if ( STM . getGeneration ( ) < <ISA_LIT>Subtarget :: SEA_ISLANDS ) { LDSAlignShift = <NUM_LIT> ; } else { LDSAlignShift = <NUM_LIT> ; } unsigned LDSSpillSize = MFI -> LDSWaveSpillSize * MFI -> getMaximumWorkGroupSize ( MF ) ; ProgInfo . LDSSize = MFI -> LDSSize + LDSSpillSize ; ProgInfo . LDSBlocks = RoundUpToAlignment ( ProgInfo . LDSSize , <NUM_LIT> << LDSAlignShift ) >> LDSAlignShift ; unsigned ScratchAlignShift = <NUM_LIT> ;

ProgInfo . ScratchBlocks = RoundUpToAlignment ( ProgInfo . ScratchSize * STM . getWavefrontSize ( ) , <NUM_LIT> << ScratchAlignShift ) >> ScratchAlignShift ;


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_CALL_LO16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_HI16 : OS << <STR_LIT> ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_PCREL_LO16 : OS << <STR_LIT> ; break ; } OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ; OS << Offset ; } if ( ( Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI ) || ( Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO ) ) OS << <STR_LIT> ;

else if ( Kind != MCSymbolRefExpr :: VK_None ) OS << ')' ;


<s> return emit_insn ( gen_rtx_SET ( x , y ) ) ;


<s> static void avr_output_progmem_section_asm_op ( const char * data ) { fprintf ( asm_out_file , <STR_LIT> , data ) ;


<s> static const char * getRegisterTypeName ( unsigned RegType ) { switch ( RegType ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> MVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; bool ExtendedInMem = VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> && VA . getValVT ( ) . getSizeInBits ( ) != VA . getLocVT ( ) . getSizeInBits ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect || ExtendedInMem ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; if ( Flags . isByVal ( ) ) { unsigned Bytes = Flags . getByValSize ( ) ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI . CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , isImmutable , true ) ; return DAG . getFrameIndex ( FI , PtrVT ) ; } EVT ArgVT = Ins [ i ] . ArgVT ; bool ScalarizedAndExtendedVector = ArgVT . isVector ( ) && ! VA . getLocVT ( ) . isVector ( ) && VA . getLocVT ( ) . getSizeInBits ( ) != ArgVT . getScalarSizeInBits ( ) ; if ( Flags . isCopyElisionCandidate ( ) && VA . getLocInfo ( ) != CCValAssign :: Indirect && ! ExtendedInMem && ! ScalarizedAndExtendedVector ) { SDValue PartAddr ; if ( Ins [ i ] . PartOffset == <NUM_LIT> ) { int FI = MFI . CreateFixedObject ( ArgVT . getStoreSize ( ) , VA . getLocMemOffset ( ) , false ) ; PartAddr = DAG . getFrameIndex ( FI , PtrVT ) ; return DAG . getLoad ( ValVT , dl , Chain , PartAddr , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ;


<s> ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineBasicBlock :: iterator Ins = MBB -> begin ( ) ; DebugLoc DL ; if ( Ins != MBB -> end ( ) ) DL = Ins -> getDebugLoc ( ) ; const MachineFunction & MF = * MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ;

MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ;


<s> <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; <ISA_LIT>CC = DAG . getConstant ( CCode , dl , <STR_LIT> ) ; } return Op0 . getOperand ( <NUM_LIT> ) ; } } bool IsFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ; <STR_LIT> CondCode = Translate<ISA_LIT>CC ( CC , dl , IsFP , Op0 , Op1 , DAG ) ; if ( CondCode == <STR_LIT> ) return SDValue ( ) ; SDValue EFLAGS = EmitCmp ( Op0 , Op1 , CondCode , dl , DAG ) ; EFLAGS = ConvertCmpIfNecessary ( EFLAGS , DAG ) ; <ISA_LIT>CC = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ;


<s> if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - <NUM_LIT> ) ; return NULL ; } switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N ) ) {

return CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ;


<s> MInstToMCSymbol :: iterator LabelIt = LOHInstToLabel . find ( MI ) ; assert ( LabelIt != LOHInstToLabel . end ( ) && <STR_LIT> ) ; MCArgs . push_back ( LabelIt -> second ) ; }

OutStreamer -> emitLOHDirective ( D . getKind ( ) , MCArgs ) ;


<s> <ISA_LIT>LoopPreIncPrep ( <ISA_LIT>TargetMachine & TM ) : FunctionPass ( ID ) , TM ( & TM ) {

initialize<ISA_LIT>LoopPreIncPrepPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> Filler ( TargetMachine & tm ) : MachineFunctionPass ( & ID ) , TM ( tm ) , TII ( tm . getInstrInfo ( ) ) {


<s> SDValue Chain = Mem . getValue ( <NUM_LIT> ) ; EVT AllocStoreVTs [ ] = { Mem . getValueType ( ) , <STR_LIT> } ; SDValue AllocStoreOps [ ] = { Chain , Mem } ; SDValue AllocStore = DAG . getNode ( <STR_LIT> , dl , AllocStoreVTs , AllocStoreOps ) ; SDNodeFlags Flags = AllocStore . getNode ( ) -> getFlags ( ) ;

Flags . setIsComposite ( isComposite ) ;


<s> for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = I ++ ; if ( OptLevel != CodeGenOpt :: None && ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; MoveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; EVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; bool SrcIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering . isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ; if ( ! SrcIsSSE && ! DstIsSSE ) {

if ( N -> getOpcode ( ) == <STR_LIT> ) continue ;


<s> AU . addPreserved < MachineFunctionAnalysis > ( ) ; AU . addPreserved < StackProtector > ( ) ;

FunctionPass :: getAnalysisUsage ( AU ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const {

if ( VT . isVector ( ) && VT . getVectorNumElements ( ) == <NUM_LIT> && ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) ) return <NUM_LIT> ;


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ;

if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> if ( ! ( Encoding & dwarf :: DW_EH_PE_pcrel ) ) return MCAsmInfo :: getExprForFDESymbol ( Sym , Encoding , Streamer ) ;

MCContext & Ctx = Streamer . getContext ( ) ;


<s> void addNEONi16splatOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> auto begin ( ) const { return Data . begin ( ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const unsigned NumArgRegs = array_lengthof ( ArgRegs ) ; unsigned RegNum = State . getFirstUnallocated ( ArgRegs ) ;

if ( RegNum != NumArgRegs && ArgRegs [ RegNum ] == <STR_LIT> ) {


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; unsigned SizeEncoding = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) ;


<s> return Size > <NUM_LIT> && Size <= SSThreshold ;


<s> static DecodeStatus DecodeRRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) {

if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> const MCExpr * <ISA_LIT>TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { return MCSymbolRefExpr :: create ( MF -> getJTISymbol ( JTI , Ctx ) , Ctx ) ;


<s> break ; case CONST_INT : switch ( code ) { case 'b' : fprintf ( file , <STR_LIT> , unique_bit_in ( INTVAL ( r ) ) ) ; break ; case 'B' : fprintf ( file , <STR_LIT> , bit_size_for_clip ( INTVAL ( r ) ) ) ; break ; case 'h' : fprintf ( file , <STR_LIT> , ( ( int ) INTVAL ( r ) >> <NUM_LIT> ) & <NUM_LIT> ) ; break ; case 'U' : fprintf ( file , <STR_LIT> , bit_size_for_clip ( INTVAL ( r ) ) - <NUM_LIT> ) ; break ; case 'J' : fprintf ( file , <STR_LIT> , ( int ) INTVAL ( r ) & <NUM_LIT> ) ; break ; case 'x' : if ( INTVAL ( r ) & ~ ( HOST_WIDE_INT ) <NUM_LIT> && ! ( INTVAL ( r ) & <NUM_LIT> ) ) fprintf ( file , HOST_WIDE_INT_PRINT_HEX , INTVAL ( r ) ) ; else fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( r ) ) ; break ; case 'I' : if ( INTVAL ( r ) & ~ ( HOST_WIDE_INT ) <NUM_LIT> && conversions [ i ] . format [ j + <NUM_LIT> ] == <NUM_LIT> ) { fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( r ) ) ; fprintf ( file , <STR_LIT> , ( int ) INTVAL ( r ) & <NUM_LIT> ) ; } else fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( r ) ) ; break ; default : fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( r ) ) ; break ; } break ; case CONST_DOUBLE : fprintf ( file , <STR_LIT> , ( unsigned long ) CONST_DOUBLE_HIGH ( r ) ) ; break ; case SYMBOL_REF : real_name = targetm . strip_name_encoding ( XSTR ( r , <NUM_LIT> ) ) ; assemble_name ( file , real_name ) ; break ; case LABEL_REF : output_asm_label ( r ) ; break ; default : fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( r ) ; gcc_unreachable ( ) ; } } else { if ( conversions [ i ] . format [ j ] == '+' && ( ! code || code == 'I' ) && ISDIGIT ( conversions [ i ] . format [ j + <NUM_LIT> ] ) && GET_CODE ( patternr [ conversions [ i ] . format [ j + <NUM_LIT> ] - '0' ] ) == CONST_INT && INTVAL ( patternr [ conversions [ i ] . format [ j + <NUM_LIT> ] - '0' ] ) < <NUM_LIT> ) continue ; fputc ( conversions [ i ] . format [ j ] , file ) ; } break ; } if ( ! conversions [ i ] . pattern ) { error ( <STR_LIT> , code ? code : '-' , pattern ) ; debug_rtx ( x ) ; }


<s> <ISA_LIT>PassConfig ( TargetMachine * TM , PassManagerBase & PM ) : <ISA_LIT>PassConfig ( TM , PM ) {


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( EnableA53Fix835769 ) addPass ( create<ISA_LIT>A53Fix835769 ( ) ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ;

if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && Triple ( TM -> getTargetTriple ( ) ) . isOSBinFormatMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ;


<s> int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { uint64_t SlotSize = TD -> getPointerSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - SlotSize ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ;


<s> if ( IS_CMSE_ENTRY ( func_type ) ) asm_fprintf ( f , <STR_LIT> ) ; asm_fprintf ( f , <STR_LIT> , ( HOST_WIDE_INT ) crtl -> args . size , crtl -> args . pretend_args_size , ( HOST_WIDE_INT ) get_frame_size ( ) ) ; asm_fprintf ( f , <STR_LIT> , frame_pointer_needed , cfun -> machine -> uses_anonymous_args ) ; if ( cfun -> machine -> lr_save_eliminated ) asm_fprintf ( f , <STR_LIT> ) ;

if ( crtl -> calls_eh_return ) asm_fprintf ( f , <STR_LIT> ) ;


if ( get<ISA_LIT>Subtarget ( ) . isCheri ( ) ) addPass ( createCheriInvalidatePass ( ) ) ;


return ( poly8x16_t ) __builtin_neon_vreinterpretv16qiv8hi ( ( int16x8_t ) __a ) ;


<s> __m64_union res ; res . as_int [ <NUM_LIT> ] = __i0 ;


<s> void <ISA_LIT>InstrInfo :: getNoop ( MCInst & NopInst ) const { NopInst . setOpcode ( <STR_LIT> ) ;


<s> if ( ! Enable<ISA_LIT>LEAOpt || ! MF . getFunction ( ) -> optForSize ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) {

SmallVector < MachineInstr * , <NUM_LIT> > LEAs ;


<s> SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Shift31 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftRightHi , Or ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , IsSRA ? Shift31 : DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftRightHi ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , <NUM_LIT> , DL ) ;


<s> void <ISA_LIT>AsmParser :: SetFrameRegister ( unsigned RegNo ) { Instrumentation -> SetFrameRegister ( RegNo ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( getCoproc ( ) ) ) ;


<s> Val ( unsigned int Op , std :: vector < unsigned int > Nums ) : Op ( Op ) , Nums ( Nums ) {


<s> static bool nios2_large_unspec_reloc_p ( rtx op ) { return ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == UNSPEC && nios2_large_offset_p ( XINT ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ) ;


<s> llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; SDValue InVal ; <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) { int FI = MFI -> CreateFixedObject ( Flags . getByValSize ( ) , VA . getLocMemOffset ( ) , true ) ; InVal = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; } else { unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ;

InVal = DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override {


<s> unsigned AluCode = AluOp . getImm ( ) ; const MCOperand Op2 = Inst . getOperand ( <NUM_LIT> ) ; Value &= ~ ( <NUM_LIT> << PBitShift ) ; if ( ! LPAC :: isPostOp ( AluCode ) && ( ( Op2 . isImm ( ) && Op2 . getImm ( ) != <NUM_LIT> ) || ( Op2 . isReg ( ) && Op2 . getReg ( ) != <STR_LIT> ) || ( Op2 . isExpr ( ) ) ) ) Value |= ( <NUM_LIT> << PBitShift ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_SINT ( SDValue Op , SelectionDAG & DAG ) { std :: pair < SDValue , SDValue > Vals = FP_TO_SINTHelper ( Op , DAG ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> ) return SDValue ( ) ; return DAG . getLoad ( Op . getValueType ( ) , Op . getDebugLoc ( ) , FIST , StackSlot , NULL , <NUM_LIT> ) ;


<s> MachineMemOperand * MMO ; Register Addr = getStackAddress ( VA , MMO ) ;

MIRBuilder . buildLoad ( Val , Addr , * MMO ) ;


<s> static SDValue combineVectorInsert ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { assert ( ( ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) || ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; return SDValue ( ) ;


<s> Constant * Associated = AssociatedAndMore . first ; auto ThisId = Id ++ ; Function * CallDtors = Function :: Create ( AtExitFuncTy , Function :: PrivateLinkage , <STR_LIT> + ( Priority != UINT16_MAX ? ( Twine ( <STR_LIT> ) + Twine ( Priority ) ) : Twine ( ) ) + ( AtThisPriority . size ( ) > <NUM_LIT> ? Twine ( <STR_LIT> ) + Twine ( ThisId ) : Twine ( ) ) + ( ! Associated -> isNullValue ( ) ? ( Twine ( <STR_LIT> ) + Associated -> getName ( ) ) : Twine ( ) ) , & M ) ; BasicBlock * BB = BasicBlock :: Create ( C , <STR_LIT> , CallDtors ) ; FunctionType * VoidVoid = FunctionType :: get ( Type :: getVoidTy ( C ) , false ) ; for ( auto Dtor : reverse ( AssociatedAndMore . second ) ) CallInst :: Create ( VoidVoid , Dtor , <STR_LIT> , BB ) ; ReturnInst :: Create ( C , BB ) ; Function * RegisterCallDtors = Function :: Create ( VoidVoid , Function :: PrivateLinkage , <STR_LIT> + ( Priority != UINT16_MAX ? ( Twine ( <STR_LIT> ) + Twine ( Priority ) ) : Twine ( ) ) + ( AtThisPriority . size ( ) > <NUM_LIT> ? Twine ( <STR_LIT> ) + Twine ( ThisId ) : Twine ( ) ) + ( ! Associated -> isNullValue ( ) ? ( Twine ( <STR_LIT> ) + Associated -> getName ( ) ) : Twine ( ) ) , & M ) ; BasicBlock * EntryBB = BasicBlock :: Create ( C , <STR_LIT> , RegisterCallDtors ) ; BasicBlock * FailBB = BasicBlock :: Create ( C , <STR_LIT> , RegisterCallDtors ) ; BasicBlock * RetBB = BasicBlock :: Create ( C , <STR_LIT> , RegisterCallDtors ) ; Value * Null = ConstantPointerNull :: get ( VoidStar ) ; Value * Args [ ] = { CallDtors , Null , DsoHandle } ; Value * Res = CallInst :: Create ( AtExit , Args , <STR_LIT> , EntryBB ) ; Value * Cmp = new ICmpInst ( * EntryBB , ICmpInst :: ICMP_NE , Res , Constant :: getNullValue ( Res -> getType ( ) ) ) ; BranchInst :: Create ( FailBB , RetBB , Cmp , EntryBB ) ; CallInst :: Create ( <STR_LIT> ( & M , <STR_LIT> ) , <STR_LIT> , FailBB ) ;


<s> assert ( ( RelTy == ELF :: R_MICROBLAZE_32_PCREL || RelTy == ELF :: R_MICROBLAZE_64_PCREL ) && <STR_LIT> ) ;

return SymOffset - ( RelOffset + <NUM_LIT> ) ;


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; unsigned Reg = MO . getReg ( ) ; RegEnc |= MRI . getEncodingValue ( Reg ) ; RegEnc &= SDWA9EncValues :: SRC_VGPR_MASK ; if ( <STR_LIT> ( <STR_LIT> ( Reg ) , & MRI ) ) { RegEnc |= SDWA9EncValues :: SRC_SGPR_MASK ; }


<s> static bool second_ratio_invalid_for_first_sew_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { return calculate_vlmul ( info1 . get_sew ( ) , info2 . get_ratio ( ) ) == LMUL_RESERVED ;


<s> static void EmitGuardLoadOrStoreTst ( const MCSubtargetInfo & STI , int I , MCInst Saved [ ] , MCStreamer & Out ) { assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; Out . EmitBundleLock ( false ) ; EmitTST ( STI , Out , Reg ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] , STI ) ;


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( ! DisablePreIncPrep && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>LoopPreIncPrepPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>CTRLoops ( ) ) ; return false ;


<s> assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . Mang -> getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getHiddenGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . Mang -> getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ;


<s> if ( ! SrcIsSSE && ! DstIsSSE ) { if ( N -> getOpcode ( ) == <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) ) continue ; } MVT MemVT ; if ( N -> getOpcode ( ) == <STR_LIT> ) MemVT = DstVT ; else MemVT = SrcIsSSE ? SrcVT : DstVT ; SDValue MemTmp = CurDAG -> CreateStackTemporary ( MemVT ) ; SDLoc dl ( N ) ; SDValue Store = CurDAG -> getTruncStore ( CurDAG -> getEntryNode ( ) , dl , N -> getOperand ( <NUM_LIT> ) , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , <NUM_LIT> ) ; SDValue Result = CurDAG -> getExtLoad ( <STR_LIT> , dl , DstVT , Store , MemTmp , MachinePointerInfo ( ) , MemVT , false , false , false , <NUM_LIT> ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Result ) ; ++ I ;


<s> case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = cast < ConstantInt > ( CI . getOperand ( <NUM_LIT> ) ) ; if ( ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : { <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . ptrVal = MFI -> getBufferPSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( <NUM_LIT> ) ) ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( <NUM_LIT> ) ) ; if ( ! Vol || ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getOperand ( <NUM_LIT> ) -> getType ( ) -> getPointerElementType ( ) ) ; Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = cast < ConstantInt > ( CI . getOperand ( <NUM_LIT> ) ) ; if ( ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; }


<s> rtx init = gen_rtx_SET ( data . base , worker_bcast_sym ) ; emit_insn_after ( init , insn ) ; if ( worker_bcast_size < data . offset ) worker_bcast_size = data . offset ; }


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {

PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRPairRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> HOST_WIDE_INT mode_align = ix86_static_rtx_alignment ( mode ) ; return MAX ( mode_align , align ) ; }

else if ( ! optimize_size && TREE_CODE ( exp ) == STRING_CST && TREE_STRING_LENGTH ( exp ) >= <NUM_LIT> && align < BITS_PER_WORD ) return BITS_PER_WORD ;


<s> int Case = getThreeSrcCommuteCase ( TSFlags , SrcOpIdx1 , SrcOpIdx2 ) ; if ( Case < <NUM_LIT> ) return false ; static const uint8_t SwapMasks [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; uint8_t Imm = MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ; uint8_t NewImm = Imm & ~ ( SwapMasks [ Case ] [ <NUM_LIT> ] | SwapMasks [ Case ] [ <NUM_LIT> ] | SwapMasks [ Case ] [ <NUM_LIT> ] | SwapMasks [ Case ] [ <NUM_LIT> ] ) ; if ( Imm & SwapMasks [ Case ] [ <NUM_LIT> ] ) NewImm |= SwapMasks [ Case ] [ <NUM_LIT> ] ; if ( Imm & SwapMasks [ Case ] [ <NUM_LIT> ] ) NewImm |= SwapMasks [ Case ] [ <NUM_LIT> ] ; if ( Imm & SwapMasks [ Case ] [ <NUM_LIT> ] ) NewImm |= SwapMasks [ Case ] [ <NUM_LIT> ] ;


<s> bool SeenV1 = false ; bool SeenV2 = false ; for ( unsigned i = MaskI ; i != MaskE ; ++ i , ++ OpIdx ) { int Idx = SVOp -> getMaskElt ( i ) ; if ( Idx < <NUM_LIT> ) continue ; if ( Idx < ( int ) NumElems ) SeenV1 = true ;


<s> void <ISA_LIT>InstPrinter :: printU5ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { unsigned char Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int ) Value ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( ! skipFunction ( MF . getFunction ( ) ) ) { initialize ( MF ) ; checkingIllegalXADD ( ) ; } return false ;


<s> val = strtol ( arg , & end_ptr , <NUM_LIT> ) ; if ( errno != <NUM_LIT> || * arg == '\0' || * end_ptr != '\0' || ( val != <NUM_LIT> && val != <NUM_LIT> && val != <NUM_LIT> && val != <NUM_LIT> && val != <NUM_LIT> ) ) { error ( <STR_LIT> <STR_LIT> , arg ) ;


<s> MachineOperand Hi2 ( getSubOperand64 ( I . getOperand ( <NUM_LIT> ) , <STR_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstHi ) . add ( Hi1 ) . add ( Hi2 ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( DstLo ) . addImm ( <STR_LIT> ) . addReg ( DstHi ) . addImm ( <STR_LIT> ) ; for ( MachineOperand & MO : I . explicit_operands ( ) ) { if ( ! MO . isReg ( ) || TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; RBI . constrainGenericRegister ( MO . getReg ( ) , <STR_LIT> , MRI ) ; } I . eraseFromParent ( ) ;


<s> if ( isTailCall ) { if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( ! isTailCall && <ISA_LIT>SubTarget . isSVR4ABI ( ) && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; if ( CallOpc == <STR_LIT> ) { Chain = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> bool isUImm6Lsb0 ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> void RecordRelocation ( MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , bool & IsPCRel , uint64_t & FixedValue ) override { assert ( ! <STR_LIT> ) ;


<s> Darwin<ISA_LIT>_64AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef CPU , bool SupportsCU ) : Darwin<ISA_LIT>AsmBackend ( T , MRI , CPU , true ) , SupportsCU ( SupportsCU ) {


<s> Darwin<ISA_LIT>_64AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef CPU , MachO :: CPUSubType<ISA_LIT> st ) : Darwin<ISA_LIT>AsmBackend ( T , MRI , CPU , true ) , Subtype ( st ) {


<s> SDLoc dl ( N ) ; unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <STR_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = nullptr ; if ( FoldedLoad ) { EVT VT = * TRI . legalclasstypes_begin ( * RC ) ; auto MMOs = extractLoadMMOs ( cast < MachineSDNode > ( N ) -> memoperands ( ) , MF ) ; if ( MMOs . empty ( ) && RC == & <STR_LIT> && Subtarget . isUnalignedMem16Slow ( ) ) return false ; unsigned Alignment = std :: max < uint32_t > ( TRI . getSpillSize ( * RC ) , <NUM_LIT> ) ; bool isAligned = ! MMOs . empty ( ) && MMOs . front ( ) -> getAlignment ( ) >= Alignment ; Load = DAG . getMachineNode ( getLoadRegOpcode ( <NUM_LIT> , RC , isAligned , Subtarget ) , dl , VT , <STR_LIT> , AddrOps ) ; NewNodes . push_back ( Load ) ; DAG . setNodeMemRefs ( cast < MachineSDNode > ( Load ) , MMOs ) ; } std :: vector < EVT > VTs ; const TargetRegisterClass * DstRC = nullptr ; if ( MCID . getNumDefs ( ) > <NUM_LIT> ) { DstRC = getRegClass ( MCID , <NUM_LIT> , & RI , MF ) ;

VTs . push_back ( * TRI . legalclasstypes_begin ( * DstRC ) ) ;


<s> setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , VT , Legal ) ; setIndexedStoreAction ( im , VT , Legal ) ; } if ( HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } const MVT LongTypes [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : LongTypes ) { addRegisterClass ( VT , & <STR_LIT> ) ; setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; addAllExtLoads ( <STR_LIT> , <STR_LIT> , Legal ) ; addAllExtLoads ( <STR_LIT> , <STR_LIT> , Legal ) ; addAllExtLoads ( <STR_LIT> , <STR_LIT> , Legal ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Legal ) ; for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) { setIndexedLoadAction ( im , <STR_LIT> , Legal ) ; setIndexedStoreAction ( im , <STR_LIT> , Legal ) ;


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; return __builtin_aarch64_qtbx4v8qi ( r , __o , ( int8x8_t ) idx ) ;


<s> case Function :: PrivateLinkage : case Function :: LinkerPrivateLinkage : break ; case Function :: ExternalLinkage : emitGlobalDirective ( CurrentFnName ) ; break ; case Function :: LinkOnceAnyLinkage : case Function :: LinkOnceODRLinkage : case Function :: WeakAnyLinkage : case Function :: WeakODRLinkage : O << TAI -> getGlobalDirective ( ) << CurrentFnName << <STR_LIT> ; O << TAI -> getWeakDefDirective ( ) << CurrentFnName << <STR_LIT> ; break ; } EmitAlignment ( MF . getAlignment ( ) , F , <NUM_LIT> ) ; if ( TAI -> hasDotTypeDotSizeDirective ( ) ) { O << <STR_LIT> << CurrentFnName << <STR_LIT> ;


<s> bool hasSTM ( ) const { return HasSTM ;


<s> ++ EmittedInsts ; printInstruction ( MI ) ;


<s> if ( CCInfo . getInRegsParamsCount ( ) > <NUM_LIT> || FI . hasByvalArg ( ) ) return false ; return NextStackOffset <= FI . getIncomingArgSize ( ) ;


<s> static int sh_mode_needed ( int entity ATTRIBUTE_UNUSED , rtx_insn * insn ) { return recog_memoized ( insn ) >= <NUM_LIT> ? get_attr_fp_mode ( insn ) : FP_MODE_NONE ;


<s> return ( poly128_t ) __builtin_neon_vreinterprettiv4si ( ( int32x4_t ) __a ) ;


<s> if ( ! N0C || ! N1C ) return SDValue ( ) ; int64_t C0 = N0C -> getSExtValue ( ) ; int64_t C1 = N1C -> getSExtValue ( ) ; if ( C0 <= <NUM_LIT> || C1 <= <NUM_LIT> ) return SDValue ( ) ; int64_t Bits = std :: min ( C0 , C1 ) ; int64_t Diff = std :: abs ( C0 - C1 ) ; if ( Diff != <NUM_LIT> && Diff != <NUM_LIT> && Diff != <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue NS = ( C0 < C1 ) ? N0 -> getOperand ( <NUM_LIT> ) : N1 -> getOperand ( <NUM_LIT> ) ; SDValue NL = ( C0 > C1 ) ? N0 -> getOperand ( <NUM_LIT> ) : N1 -> getOperand ( <NUM_LIT> ) ; SDValue NA0 = DAG . getNode ( <STR_LIT> , DL , VT , NL , DAG . getConstant ( Diff , DL , VT ) ) ; SDValue NA1 = DAG . getNode ( <STR_LIT> , DL , VT , NA0 , NS ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NA1 , DAG . getConstant ( Bits , DL , VT ) ) ;


<s> break ; case <STR_LIT> : Opc = <STR_LIT> ; Reg = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; Reg = <STR_LIT> ; break ; } MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( Opc ) ) ;

MIB -> findRegisterUseOperand ( Reg ) -> setIsUndef ( ) ;


<s> <STR_LIT> Cond = StringSwitch < <STR_LIT> > ( Constraint ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; return Cond ;


<s> if ( ! EnableTailPredication ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( L -> getNumBlocks ( ) > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } assert ( L -> empty ( ) && <STR_LIT> ) ; HardwareLoopInfo HWLoopInfo ( L ) ; if ( ! HWLoopInfo . canAnalyze ( * LI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ! isHardwareLoopProfitable ( L , SE , AC , TLI , HWLoopInfo ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ;


<s> return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ; } } const Function & Fn = * DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ;

DAG . getContext ( ) -> diagnose ( BadInit ) ;


<s> return get<ISA_LIT>SubSuperRegister ( ShadowReg , VT ) ;


<s> imm |= ( Rn << <NUM_LIT> ) ; if ( Rn == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ;


<s> if ( frame_pointer_needed ) { emit_insn ( gen_movsi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; amount = offsets -> locals_base - offsets -> saved_regs ; } amount -= <NUM_LIT> * thumb1_extra_regs_pushed ( offsets , false ) ; gcc_assert ( amount >= <NUM_LIT> ) ; if ( amount ) { emit_insn ( gen_blockage ( ) ) ; if ( amount < <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ) ;


<s> <ISA_LIT>LowerModuleLDS ( ) : ModulePass ( ID ) { initialize<ISA_LIT>LowerModuleLDSPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> TargetRegistry :: RegisterAsmStreamer ( The<ISA_LIT>32Target , create<ISA_LIT>AsmStreamer ) ; TargetRegistry :: RegisterAsmStreamer ( The<ISA_LIT>64Target , create<ISA_LIT>AsmStreamer ) ;


<s> bool <ISA_LIT>AsmTypeCheck :: typeError ( SMLoc ErrorLoc , const Twine & Msg ) { if ( TypeErrorThisFunction ) return true ; if ( Unreachable ) return true ;


<s> if ( ISD == <STR_LIT> && Index == ( ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ) return <NUM_LIT> ; return Cost ; } else if ( ST -> hasQPX ( ) && Val -> getScalarType ( ) -> isFloatingPointTy ( ) ) { if ( Index == <NUM_LIT> ) return <NUM_LIT> ;


<s> PointerSize = <NUM_LIT> ; WinEHEncodingType = WinEH :: EncodingType :: Itanium ; } else { WinEHEncodingType = WinEH :: EncodingType :: <ISA_LIT> ;


<s> SDLoc dl ( N ) ; if ( ! DCI . isAfterLegalizeDAG ( ) || VT != <STR_LIT> || ! DCI . DAG . getTargetLoweringInfo ( ) . isTypeLegal ( <STR_LIT> ) ) return SDValue ( ) ; SDValue Ext = SDValue ( N , <NUM_LIT> ) ; if ( Ext . getOpcode ( ) == <STR_LIT> && Ext . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) Ext = Ext . getOperand ( <NUM_LIT> ) ; if ( Ext . getOpcode ( ) != <STR_LIT> || ! isa < ConstantSDNode > ( Ext . getOperand ( <NUM_LIT> ) ) || Ext . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) return SDValue ( ) ; if ( Ext -> use_size ( ) == <NUM_LIT> && ( Ext -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> || Ext -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) return SDValue ( ) ; SDValue Op0 = Ext . getOperand ( <NUM_LIT> ) ; EVT VecVT = Op0 . getValueType ( ) ; unsigned ResNo = Op0 . getResNo ( ) ; unsigned Lane = Ext . getConstantOperandVal ( <NUM_LIT> ) ; if ( VecVT . getVectorNumElements ( ) != <NUM_LIT> ) return SDValue ( ) ; auto OtherIt = find_if ( Op0 -> uses ( ) , [ & ] ( SDNode * V ) {

return V -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( V -> getOperand ( <NUM_LIT> ) ) && V -> getConstantOperandVal ( <NUM_LIT> ) == Lane + <NUM_LIT> && V -> getOperand ( <NUM_LIT> ) . getResNo ( ) == ResNo ;


<s> else if ( ABIName . startswith ( <STR_LIT> ) ) return <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ; else if ( ABIName . startswith ( <STR_LIT> ) ) return <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ;


<s> { MO_GOT , <STR_LIT> } , { MO_SBREL , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_SECREL , <STR_LIT> } , { MO_NONLAZY , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ;


<s> if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm < <NUM_LIT> ) Imm = <NUM_LIT> ; O << <STR_LIT> << vecelem [ Imm % <NUM_LIT> ] ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( ( Imm < <NUM_LIT> ) || ( Imm > <NUM_LIT> ) ) O << <STR_LIT> ; } else if ( <NUM_LIT> == strcmp ( Modifier , <STR_LIT> ) ) { if ( Imm < <NUM_LIT> ) Imm = <NUM_LIT> ;


<s> __inline__ static unsigned long long sh_media_MSUB_L ( unsigned long long mm , unsigned long long mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ;


<s> if ( PacketStalls ) return Latency > PacketStallCycles ; return true ;


<s> auto EC = cast < VectorType > ( A -> getType ( ) ) -> getElementCount ( ) ; auto EvenIdx = Builder . CreateSeriesVector ( EC , Zero , Two ) ; auto OddIdx = Builder . CreateSeriesVector ( EC , One , Two ) ; auto UnzipEven = Builder . CreateShuffleVector ( A , B , EvenIdx ) ; auto UnzipOdd = Builder . CreateShuffleVector ( A , B , OddIdx ) ;

return std :: make_tuple ( UnzipEven , UnzipOdd ) ;


<s> const char * getPassName ( ) const override {


<s> static int thumb2_legitimate_address_p ( machine_mode mode , rtx x , int strict_p ) { bool use_ldrd ; enum rtx_code code = GET_CODE ( x ) ; if ( arm_address_register_rtx_p ( x , strict_p ) ) return <NUM_LIT> ; use_ldrd = ( TARGET_LDRD && ( mode == DImode || mode == DFmode ) ) ; if ( code == POST_INC || code == PRE_DEC || ( ( code == PRE_INC || code == POST_DEC ) && ( use_ldrd || GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) ) ) return arm_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) ; else if ( ( code == POST_MODIFY || code == PRE_MODIFY ) && arm_address_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) ) ) { rtx addend = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; HOST_WIDE_INT offset ; if ( ! CONST_INT_P ( addend ) ) return <NUM_LIT> ; offset = INTVAL ( addend ) ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) return ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; return ( use_ldrd && offset > - <NUM_LIT> && offset < <NUM_LIT> && ( offset & <NUM_LIT> ) == <NUM_LIT> ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ; else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return <NUM_LIT> ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ;


<s> if ( ValTy -> isFloatingPointTy ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } } else if ( ST -> hasVector ( ) ) { unsigned VF = cast < FixedVectorType > ( ValTy ) -> getNumElements ( ) ; if ( Opcode == Instruction :: ICmp || Opcode == Instruction :: FCmp ) { unsigned PredicateExtraCost = <NUM_LIT> ; if ( I != nullptr ) { switch ( cast < CmpInst > ( I ) -> getPredicate ( ) ) { case CmpInst :: Predicate :: ICMP_NE : case CmpInst :: Predicate :: ICMP_UGE : case CmpInst :: Predicate :: ICMP_ULE : case CmpInst :: Predicate :: ICMP_SGE : case CmpInst :: Predicate :: ICMP_SLE : PredicateExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: FCMP_ONE : case CmpInst :: Predicate :: FCMP_ORD : case CmpInst :: Predicate :: FCMP_UEQ :


<s> SDValue Param = lowerKernargMemParameter ( DAG , <STR_LIT> , <STR_LIT> , SL , DAG . getEntryNode ( ) , Offset , <NUM_LIT> , false ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Param , DAG . getValueType ( VT ) ) ;


<s> static bool getTargetShuffleMaskIndices ( SDValue MaskNode , unsigned MaskEltSizeInBits , SmallVectorImpl < uint64_t > & RawMask ) { SmallBitVector UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( ! getTargetConstantBitsFromNode ( MaskNode , MaskEltSizeInBits , UndefElts , EltBits , false , false ) ) return false ;

for ( APInt Elt : EltBits ) RawMask . push_back ( Elt . getZExtValue ( ) ) ;


return __builtin_mve_vctp16qv8bi ( __a ) ;


<s> SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , & GA , <NUM_LIT> ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( Op , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( Op , DAG , Has<ISA_LIT>64 ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( Op , DAG , <STR_LIT> , <STR_LIT> ) ;

return getAddrGlobal ( Op , DAG , Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ;


<s> basic_block * body , bb ; body = get_loop_body ( loop ) ; for ( unsigned i = <NUM_LIT> ; i < loop -> num_nodes ; i ++ ) { bb = body [ i ] ; FOR_BB_INSNS ( bb , insn ) { rtx base = NULL_RTX ; rtx dest = NULL_RTX ; rtx offset = NULL_RTX ; bool writeback = false ; bool ldp = false ; if ( ! INSN_P ( insn ) || DEBUG_INSN_P ( insn ) ) continue ; if ( get_load_info ( insn , loop , & dest , & base , & offset , & writeback , & ldp ) ) { tag_insn_info * i = new tag_insn_info ( insn , dest , base , offset , writeback , ldp ) ; rtx tag = GEN_INT ( i -> tag ( ) ) ; tag_map . get_or_insert ( tag ) . safe_push ( i ) ; } } }


<s> void adjustRelativeBranch ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) {

signed_width ( Size + <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ;


<s> if ( Result . getNode ( ) != <NUM_LIT> ) return Result ; } DebugLoc dl = N -> getDebugLoc ( ) ; SDValue LHSL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue LHSH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RHSL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RHSH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Carry = DAG . getNode ( Opcode , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , LHSL , RHSL , Zero ) ; SDValue Lo ( Carry . getNode ( ) , <NUM_LIT> ) ; SDValue Ignored = DAG . getNode ( Opcode , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , LHSH , RHSH , Carry ) ; SDValue Hi ( Ignored . getNode ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ;


<s> int nregs = <NUM_LIT> ; int regno ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( c6x_save_reg ( regno ) ) nregs ++ ;


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( getTargetMachine ( ) . getInstrInfo ( ) ) ; return TII -> isInlineConstant ( Imm ) ;


<s> Align StackAlign = getStackAlign ( ) ; uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ; MFI . setMaxCallFrameSize ( MaxCallSize ) ;

FrameSize = alignTo ( FrameSize , StackAlign ) ;


<s> bool has64BitSupport ( ) const { return Has64BitSupport ;


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ;


<s> } unsigned SrcReg1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ;

AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ;


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> SDNode * N = DAG . getMachineNode ( MachineOpc , dl , Ty , Ops ) ;


<s> static DecodeStatus DecodeMemBarrierOption ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( Val & ~ <NUM_LIT> ) return MCDisassembler :: Fail ;

Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ;


<s> OutStreamer . EmitAssemblerFlag ( MCAF_SyntaxUnified ) ; if ( TT . isOSBinFormatELF ( ) ) emitAttributes ( ) ; if ( TT . isOSNaCl ( ) ) { if ( OutStreamer . hasRawTextSupport ( ) ) { std :: string str ; raw_string_ostream OS ( str ) ; EmitSFIHeaders ( OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; }

initializeNaClMCStreamer ( OutStreamer , OutContext , TT ) ;


<s> Instruction :: BinaryOps DivOp , RemOp ; if ( isSigned ) { ExtOp = Instruction :: SExt ; DivOp = Instruction :: SDiv ; RemOp = Instruction :: SRem ; } else { ExtOp = Instruction :: ZExt ; DivOp = Instruction :: UDiv ; RemOp = Instruction :: URem ; } Value * Dividend , * Divisor ; if ( isThreeOperand ) { Value * Op0 = getOperand ( <NUM_LIT> ) , * Op1 = getOperand ( <NUM_LIT> ) ;

IntegerType * HalfType = cast < IntegerType > ( getResultTy ( <NUM_LIT> ) ) ;


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const TargetFrameLowering * TFI = getFrameLowering ( * MF ) ;

return TFI -> hasFP ( * MF ) ? CSR_FP_SaveList : CSR_SaveList ;


<s> uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; uint64_t Index = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) && isUInt < <NUM_LIT> > ( Index ) ) ; return ( Index << <NUM_LIT> ) | ( Base << <NUM_LIT> ) | Disp ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>RegisterBankInfo :: onlyDefinesFP ( const MachineInstr & MI , const MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , unsigned Depth ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_UITOFP : case TargetOpcode :: G_EXTRACT_VECTOR_ELT :

case TargetOpcode :: G_INSERT_VECTOR_ELT :


<s> SDValue Src = ASC -> getOperand ( <NUM_LIT> ) ; SDValue FlatNullPtr = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( getTargetMachine ( ) ) ; if ( ASC -> getSrcAddressSpace ( ) == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) { unsigned DestAS = ASC -> getDestAddressSpace ( ) ; if ( DestAS == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS || DestAS == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) { unsigned NullVal = TM . getNullPointerValue ( DestAS ) ; SDValue SegmentNullPtr = DAG . getConstant ( NullVal , SL , <STR_LIT> ) ; SDValue NonNull = DAG . getSetCC ( SL , <STR_LIT> , Src , FlatNullPtr , <STR_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NonNull , Ptr , SegmentNullPtr ) ; } } if ( ASC -> getDestAddressSpace ( ) == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) {

unsigned SrcAS = ASC -> getSrcAddressSpace ( ) ;


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) ; SDValue RelAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ;

SDValue AbsAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GlobalBase , RelAddr ) ;


<s> MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> , VT ) ; return FrameAddr ;


<s> const TargetOperandInfo * OpInfo = <ISA_LIT>Insts [ Opcode ] . OpInfo ; if ( ! OpInfo ) return false ;

assert ( NumOps >= <NUM_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && OpInfo [ <NUM_LIT> ] . RegClass == <NUM_LIT> && <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return Match_RequiresNoZeroRegister ; if ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) return Match_RequiresDifferentOperands ; return Match_Success ; case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> > ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeRange0_32 ; return Match_Success ; } case <STR_LIT> : case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> >= ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeRange33_64 ; return Match_Success ; } case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> > ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeUImm6 ; return Match_Success ; } case <STR_LIT> : case <STR_LIT> : { assert ( Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; const signed Pos = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; const signed Size = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( <NUM_LIT> > ( Pos + Size ) ) || ( ( Pos + Size ) > <NUM_LIT> ) ) return Match_RequiresPosSizeRange33_64 ; return Match_Success ; }


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; FrameReg = ( RegInfo -> needsStackRealignment ( MF ) ) ? RegInfo -> getStackRegister ( ) : RegInfo -> getFrameRegister ( MF ) ;

return getFrameIndexOffset ( MF , FI ) ;


<s> MCAsmParser & Parser = getParser ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; Parser . Lex ( ) ; const MCExpr * Val = nullptr ; InlineAsmIdentifierInfo Info ; SMLoc Start = Tok . getLoc ( ) , End ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelInlineAsmIdentifier ( Val , Identifier , Info , true , End ) ) return <NUM_LIT> ; if ( ! Info . isKind ( InlineAsmIdentifierInfo :: IK_Var ) ) { Error ( Start , <STR_LIT> ) ; return <NUM_LIT> ; } unsigned CVal = <NUM_LIT> ; switch ( OpKind ) { default : llvm_unreachable ( <STR_LIT> ) ; case IOK_LENGTH : CVal = Info . Var . Length ; break ; case IOK_SIZE : CVal = Info . Var . Size ; break ;

case IOK_TYPE : CVal = Info . Var . Type ; break ;


<s> return gen_rtx_REG ( TYPE_MODE ( valtype ) , MOXIE_R0 ) ;


<s> return __builtin_ia32_vcvtqq2ph512_mask_round ( ( __v8di ) __A , _mm_setzero_ph ( ) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> static void emitRegPlusImmediate ( bool is<ISA_LIT> , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , const <ISA_LIT>BaseInstrInfo & TII , unsigned DestReg , unsigned SrcReg , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags , <STR_LIT> Pred = <STR_LIT> , unsigned PredReg = <NUM_LIT> ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , DestReg , SrcReg , NumBytes , Pred , PredReg , TII , MIFlags ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , DestReg , SrcReg , NumBytes , Pred , PredReg , TII , MIFlags ) ;


<s> addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else if ( F -> getTarget ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( TII -> getGlobalBaseReg ( F ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrSema :: translateTargetInst ( ) { unsigned Opcode = CurrentInst -> Inst . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ;


<s> } OutStreamer . EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MCPE . Val . ConstVal ) ; return ; } MachineBasicBlock :: const_instr_iterator I = MI ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { if ( emitPseudoExpansionLowering ( OutStreamer , & * I ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { emitPseudoIndirectBranch ( OutStreamer , & * I ) ; continue ;


<s> static LaneBitmask getUsedRegMask ( const MachineOperand & MO , const MachineRegisterInfo & MRI , const LiveIntervals & LIS ) { assert ( MO . isUse ( ) && MO . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) ; if ( auto SubReg = MO . getSubReg ( ) ) return MRI . getTargetRegisterInfo ( ) -> getSubRegIndexLaneMask ( SubReg ) ;

auto MaxMask = MRI . getMaxLaneMaskForVReg ( MO . getReg ( ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) { initReciprocals ( * this , Subtarget ) ; initAsmInfo ( ) ;


<s> static inline bool m32r_rtx_ok_for_offset_p ( const_rtx x ) {

return ( CONST_INT_P ( x ) && INT16_P ( INTVAL ( x ) ) ) ;


<s> if ( TM . getInstrInfo ( ) -> isMoveInstr ( * MI , src , dst , srcSR , dstSR ) ) { O << <STR_LIT> << getRegisterName ( dst ) << <STR_LIT> ; O << getRegisterName ( src ) ;


<s> case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> :


<s> return MI -> getOpcode ( ) == <STR_LIT> ;


if ( strcmp ( name , <STR_LIT> ) == <NUM_LIT> || startswith ( name , <STR_LIT> ) || startswith ( name , <STR_LIT> ) || strcmp ( name , <STR_LIT> ) == <NUM_LIT> || startswith ( name , <STR_LIT> ) || startswith ( name , <STR_LIT> ) ) flags = SECTION_SMALL ;


<s> static void mips_output_32bit_xfer ( char direction , unsigned int gpreg , unsigned int fpreg ) {

fprintf ( asm_out_file , <STR_LIT> , direction , reg_names [ gpreg ] , reg_names [ fpreg ] ) ;


<s> EVT XType = SRASrc0 . getValueType ( ) ; unsigned Size = XType . getSizeInBits ( ) - <NUM_LIT> ; if ( ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 && XType . isInteger ( ) && SRAConstant != nullptr && Size == SRAConstant -> getZExtValue ( ) ) { unsigned Opcode = Subtarget -> isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opcode , VT , ADDSrc0 ) ; return true ; } return false ;


<s> unsigned getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , int Index , Type * SubTp ) {


<s> inline vector signed int vec_cmpgt ( vector float a1 , vector float a2 ) {

return ( vector signed int ) __builtin_altivec_vcmpgtfp ( ( vector float ) a1 , ( vector float ) a2 ) ;


<s> vabal_high_u16 ( uint32x4_t a , uint16x8_t b , uint16x8_t c ) { uint32x4_t result ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


return ( TARGET_NEWABI && TARGET_BIG_ENDIAN && AGGREGATE_TYPE_P ( valtype ) && mips_fpr_return_fields ( valtype , fields ) == <NUM_LIT> ) ;


<s> if ( getLexer ( ) . getKind ( ) == AsmToken :: Percent ) { Parser . Lex ( ) ; const AsmToken & NextTok = Parser . getTok ( ) ; if ( NextTok . isNot ( AsmToken :: Identifier ) ) return true ; Str += <STR_LIT> ; Str += NextTok . getIdentifier ( ) ; Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: LParen ) return true ; } else break ; } if ( getParser ( ) . parseParenExpression ( IdVal , EndLoc ) ) return true ; while ( getLexer ( ) . getKind ( ) == AsmToken :: RParen ) Parser . Lex ( ) ; } else return true ;

Res = evaluateRelocExpr ( IdVal , Str ) ;


<s> bool ResourceAssignment :: XPathOnSideAvailable ( unsigned dstSide ) { unsigned xuse = ( dstSide == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ; return Reserved ;


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isVShiftLImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , Cnt ) && Cnt < EltSize ) return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( Op . getOperand ( <NUM_LIT> ) , VT , false , false , Cnt ) && Cnt < EltSize ) { unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , DL , <STR_LIT> ) ) ; }


<s> return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - ( TT . isOSDarwin ( ) || ReserveX18 ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> void <ISA_LIT>TargetLowering :: initializeSplitCSR ( MachineBasicBlock * Entry ) const {


<s> auto & MRI = MF . getRegInfo ( ) ; unsigned SPReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto * SPSymbol = MF . createExternalSymbolName ( <STR_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addExternalSymbol ( SPSymbol ) ; auto * LoadMMO = new MachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addImm ( <NUM_LIT> ) . addReg ( SPReg ) . addMemOperand ( LoadMMO ) ; unsigned OffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( StackSize ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( AdjustUp ? <STR_LIT> : <STR_LIT> ) , <STR_LIT> ) . addReg ( SPReg ) . addReg ( OffsetReg ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addExternalSymbol ( SPSymbol ) ; auto * MMO = new MachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ;

BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( OffsetReg ) . addReg ( <STR_LIT> ) . addMemOperand ( MMO ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseCOP2 ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ;

if ( Tok . isNot ( AsmToken :: Integer ) ) return MatchOperand_NoMatch ;


<s> GlobalsEmitted = true ; } bool ret = AsmPrinter :: doFinalization ( M ) ; clearAnnotationCache ( & M ) ; if ( auto * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ) { if ( HasDebugInfo ) { TS -> closeLastSection ( ) ; OutStreamer -> emitRawText ( <STR_LIT> ) ; }


<s> void <ISA_LIT>Subtarget :: changeLatency ( SUnit * Src , SmallVector < SDep , <NUM_LIT> > & Deps , SUnit * Dst , unsigned Lat ) const { MachineInstr & SrcI = * Src -> getInstr ( ) ; for ( auto & I : Deps ) { if ( I . getSUnit ( ) != Dst ) continue ; I . setLatency ( Lat ) ; SUnit * UpdateDst = I . getSUnit ( ) ; updateLatency ( SrcI , * UpdateDst -> getInstr ( ) , I ) ; for ( auto & PI : UpdateDst -> Preds ) { if ( PI . getSUnit ( ) != Src || ! PI . isAssignedRegDep ( ) ) continue ; PI . setLatency ( Lat ) ; updateLatency ( SrcI , * UpdateDst -> getInstr ( ) , PI ) ;


<s> EVT VT = V2 . getValueType ( ) ; SDValue V1 = IsZero ? getZeroVector ( VT , Subtarget -> hasSSE2 ( ) , Subtarget -> hasAVX2 ( ) , DAG , V2 . getDebugLoc ( ) ) : DAG . getUNDEF ( VT ) ;

unsigned NumElems = VT . getVectorNumElements ( ) ;