<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ;

AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> SETHIInst . setOpcode ( <STR_LIT> ) ; SETHIInst . addOperand ( RD ) ; SETHIInst . addOperand ( Imm ) ; OutStreamer . emitInstruction ( SETHIInst , STI ) ;


<s> } else { uint32_t High = ( Imm + <NUM_LIT> ) & ~ <NUM_LIT> ; uint32_t Low = ( Imm + <NUM_LIT> ) & <NUM_LIT> ; Imm = Low ; Overflow = High - <NUM_LIT> ; } } if ( Overflow > <NUM_LIT> && Subtarget -> getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS ) return false ; ImmOffset = CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ; if ( Overflow <= <NUM_LIT> ) SOffset = CurDAG -> getTargetConstant ( Overflow , DL , <STR_LIT> ) ; else SOffset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Overflow , DL , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DataLayout ( Subtarget . getTargetDataString ( ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> MEM_VOLATILE_P ( lraddr ) = true ; emit_move_insn ( lraddr , eh_addr ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;


<s> SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; unsigned NumElems = ResVT . getVectorNumElements ( ) ; SDValue V = Insert128BitVector ( DAG . getNode ( <STR_LIT> , dl , ResVT ) , V1 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ; return Insert128BitVector ( V , V2 , DAG . getConstant ( NumElems / <NUM_LIT> , <STR_LIT> ) , DAG , dl ) ;


<s> mem = operands [ <NUM_LIT> ] ; val = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; mem = or1k_adjust_atomic_subword ( mem , & shift , & mask ) ; if ( val != const0_rtx ) { val = convert_modes ( SImode , mode , val , <NUM_LIT> ) ; val = expand_binop ( SImode , ashl_optab , val , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } label = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label , <NUM_LIT> ) ) ; scratch = gen_reg_rtx ( SImode ) ; emit_load_locked ( SImode , scratch , mem ) ; retval = expand_binop ( SImode , and_optab , scratch , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; scratch = expand_binop ( SImode , xor_optab , scratch , retval , scratch , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; if ( val != const0_rtx ) scratch = expand_binop ( SImode , ior_optab , scratch , val , scratch , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; emit_store_conditional ( SImode , mem , scratch ) ; emit_unlikely_jump ( EQ , label ) ; or1k_finish_atomic_subword ( mode , orig_retval , retval , shift ) ;


<s> constant = ( med_defect + max_defect ) * <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ; if ( constant < - <NUM_LIT> || constant > <NUM_LIT> ) abort ( ) ; constants [ i ] = constant ; calc_defect ( x_low , constant , factor ) ; calc_defect ( x_med , constant , factor ) ; calc_defect ( x_high , constant , factor ) ; } printf ( <STR_LIT> ) ; printf ( <STR_LIT> , BIAS ) ; printf ( <STR_LIT> , max_defect , max_defect_x ) ; printf ( <STR_LIT> , min_defect , min_defect_x ) ; printf ( <STR_LIT> , max_defect2 , max_defect2_x ) ; printf ( <STR_LIT> , min_defect2 , min_defect2_x ) ; printf ( <STR_LIT> , max_defect3 , max_defect3_val , max_defect3_x ) ; printf ( <STR_LIT> , min_defect3 , min_defect3_val , min_defect3_x ) ; printf ( <STR_LIT> , calc_defect ( <NUM_LIT> , constants [ <NUM_LIT> ] , factors [ <NUM_LIT> ] ) ) ;

printf ( <STR_LIT> , calc_defect ( - <NUM_LIT> , constants [ steps ] , factors [ steps ] ) ) ;


<s> bool opCanUseLiteralConstant ( unsigned OpType ) const {

return OpType >= <STR_LIT> && OpType <= <STR_LIT> ;


<s> Value * Pair = concat ( Builder , { Lo , Hi } ) ; Value * Shift = Builder . CreateLShr ( Builder . CreateShl ( Pair , Amt ) , <NUM_LIT> ) ; Value * Trunc = Builder . CreateTrunc ( Shift , Type :: getInt32Ty ( F . getContext ( ) ) ) ; return Builder . CreateBitCast ( Trunc , Hi -> getType ( ) ) ; } if ( VecLen == <NUM_LIT> ) { Value * Sub = Builder . CreateSub ( getConstInt ( VecLen ) , Amt ) ; return vralignb ( Builder , Lo , Hi , Sub ) ; }


<s> MRI . constrainRegClass ( newval , & <STR_LIT> ) ; } unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , Ord , isThumb2 , ldrOpc , strOpc ) ; MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( dest ) . addReg ( oldval ) ) ;

BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= <NUM_LIT> ) if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || Mask [ <NUM_LIT> ] < <NUM_LIT> ) && ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) && ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) && ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || Mask [ <NUM_LIT> ] >= <NUM_LIT> ) ) { unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( SHUFPDMask , <STR_LIT> ) ) ; } if ( ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) && ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || Mask [ <NUM_LIT> ] < <NUM_LIT> ) && ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || Mask [ <NUM_LIT> ] >= <NUM_LIT> ) && ( Mask [ <NUM_LIT> ] == - <NUM_LIT> || ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) ) ) { unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) | ( ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) << <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 , DAG . getConstant ( SHUFPDMask , <STR_LIT> ) ) ;


<s> } Rsrc23 |= UINT64_C ( <NUM_LIT> ) << <STR_LIT> ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) Rsrc23 &= ~ <STR_LIT> ; return Rsrc23 ;


<s> const LLT v8s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v64s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v16s32 , v8s64 } ) setAction ( { BinOp , Ty } , Legal ) ; setAction ( { G_MUL , v16s32 } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v16s32 , v8s64 } ) setAction ( { MemOp , Ty } , Legal ) ; for ( auto Ty : { v64s8 , v32s16 , v16s32 , v8s64 } ) { setAction ( { G_INSERT , Ty } , Legal ) ; setAction ( { G_EXTRACT , <NUM_LIT> , Ty } , Legal ) ; } for ( auto Ty : { v32s8 , v16s16 , v8s32 , v4s64 , v16s8 , v8s16 , v4s32 , v2s64 } ) { setAction ( { G_INSERT , <NUM_LIT> , Ty } , Legal ) ; setAction ( { G_EXTRACT , Ty } , Legal ) ;


<s> assert ( WWMReservedFrameIndexes . empty ( ) ) ; WWMReservedFrameIndexes . resize ( WWMReservedRegs . size ( ) ) ; int I = <NUM_LIT> ; for ( Register VGPR : WWMReservedRegs ) { const TargetRegisterClass * RC = TRI . getPhysRegClass ( VGPR ) ; WWMReservedFrameIndexes [ I ++ ] = MFI . CreateSpillStackObject ( TRI . getSpillSize ( * RC ) , TRI . getSpillAlign ( * RC ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isLDSNoRetInstr ( unsigned Opcode ) const { return isLD<ISA_LIT>nstr ( Opcode ) && getOperandIdx ( Opcode , <STR_LIT> :: dst ) == - <NUM_LIT> ;


<s> reportError ( I . getLoc ( ) , Twine ( <STR_LIT> ) + ( Inner ? <STR_LIT> : <STR_LIT> ) + <STR_LIT> + <STR_LIT> + <STR_LIT> + Twine ( RI . getName ( <STR_LIT> ) ) + <STR_LIT> ) ;


<s> <ISA_LIT>FIHolder ( int FrameIndex , int StackPointerOffset ) : FI ( FrameIndex ) , SPOffset ( StackPointerOffset ) {


<s> <ISA_LIT>ExecutionDepsFix ( ) : ExecutionDepsFix ( ID , <STR_LIT> ) {


<s> return In64BitMode && ( TargetTriple . getEnvironment ( ) == Triple :: GNUX32 ) ;


<s> SmallVector < Value * , <NUM_LIT> > Args { GP , Vec } ; <STR_LIT> IntID = <STR_LIT> ; auto * Intr = <STR_LIT> ( F -> getParent ( ) , IntID , Vec -> getType ( ) ) ;

return CallInst :: Create ( Intr -> getFunctionType ( ) , Intr , Args ) ;


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const {

return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ;


<s> enum attr_i387_cw mode ; if ( CALL_P ( insn ) || ( NONJUMP_INSN_P ( insn ) && ( asm_noperands ( PATTERN ( insn ) ) >= <NUM_LIT> || GET_CODE ( PATTERN ( insn ) ) == ASM_INPUT ) ) ) return I387_CW_UNINITIALIZED ; if ( recog_memoized ( insn ) < <NUM_LIT> ) return I387_CW_ANY ; mode = get_attr_i387_cw ( insn ) ; switch ( entity ) { case I387_TRUNC : if ( mode == I387_CW_TRUNC ) return mode ; break ; case I387_FLOOR : if ( mode == I387_CW_FLOOR ) return mode ; break ; case I387_CEIL : if ( mode == I387_CW_CEIL ) return mode ; break ; case I387_MASK_PM : if ( mode == I387_CW_MASK_PM ) return mode ; break ; default : gcc_unreachable ( ) ;


<s> std :: string Func1 = addPrefix ( Func ) ; std :: string tag = getTagName ( AUTOS_SECTION ) ; return Func1 + tag + <STR_LIT> ;


<s> } if ( Op . isToken ( ) && Op . getToken ( ) == <STR_LIT> ) { GDSOnly = true ; continue ; } OptionalIdx [ Op . getImmTy ( ) ] = i ; } unsigned OffsetIdx = OptionalIdx [ AMDGPUOperand :: ImmTyOffset ] ; ( ( AMDGPUOperand & ) * Operands [ OffsetIdx ] ) . addImmOperands ( Inst , <NUM_LIT> ) ; if ( ! GDSOnly ) { unsigned GD<ISA_LIT>dx = OptionalIdx [ AMDGPUOperand :: ImmTyGDS ] ; ( ( AMDGPUOperand & ) * Operands [ GD<ISA_LIT>dx ] ) . addImmOperands ( Inst , <NUM_LIT> ) ;


<s> if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; IsScalableVector = true ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; IsScalableVector = true ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ; IsScalableVector = true ; } else if ( <STR_LIT> . contains ( DstReg , SrcReg ) ) { Opc = <STR_LIT> ;


<s> } } } else if ( Shl_0 . getOpcode ( ) == <STR_LIT> ) { SDValue Sub_0 = Shl_0 . getOperand ( <NUM_LIT> ) ; SDValue Sub_1 = Shl_0 . getOperand ( <NUM_LIT> ) ; if ( Sub_0 . getOpcode ( ) == <STR_LIT> ) { int32_t SubConst = cast < ConstantSDNode > ( Sub_0 . getNode ( ) ) -> getSExtValue ( ) ; if ( SubConst == <NUM_LIT> ) { if ( Sub_1 . getOpcode ( ) == <STR_LIT> ) { SDValue Shl2_0 = Sub_1 . getOperand ( <NUM_LIT> ) ; SDValue Shl2_1 = Sub_1 . getOperand ( <NUM_LIT> ) ; if ( Shl2_1 . getOpcode ( ) == <STR_LIT> ) { int32_t ShlConst = cast < ConstantSDNode > ( Shl_1 . getNode ( ) ) -> getSExtValue ( ) ; int32_t Shl2Const = cast < ConstantSDNode > ( Shl2_1 . getNode ( ) ) -> getSExtValue ( ) ; int32_t ValConst = <NUM_LIT> << ( ShlConst + Shl2Const ) ; SDValue Val = CurDAG -> getTargetConstant ( - ValConst , dl , <STR_LIT> ) ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Val . getNode ( ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { SDNode * Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Shl2_0 , Val ) ; ReplaceNode ( N , Result ) ; return ; } } } } } }


<s> Key . reserve ( CPU . size ( ) + FS . size ( ) ) ; Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; unsigned CPUFSWidth = Key . size ( ) ; unsigned PreferVectorWidthOverride = <NUM_LIT> ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) {


<s> return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] & RELOAD_REG_OFFSET ) != <NUM_LIT> ) ;


<s> static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) {

assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ;


<s> if ( V . getOpcode ( ) == <STR_LIT> ) { SDValue Src = V . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( ! SrcVT . isVector ( ) ) return SDValue ( ) ; if ( SDValue Not = IsNOT ( Src , DAG ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( V ) , VT , DAG . getBitcast ( SrcVT , Not ) ) ; } return SDValue ( ) ; } ; if ( SDValue Not = GetNot ( N0 ) ) { X = Not ; Y = N1 ; } else if ( SDValue Not = GetNot ( N1 ) ) {


<s> if ( Memop -> getMemoryVT ( ) == <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ; }


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ;


<s> if ( TARGET_AAPCS_BASED ) align = MIN ( align , <NUM_LIT> ) ; return align ;


<s> assert ( ! hasIntModifiers ( ) ) ; addRegOrImmWithInputModsOperands ( Inst , N ) ;


<s> partitionRegisters ( P2Rs ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( UUSetMap :: iterator I = P2Rs . begin ( ) , E = P2Rs . end ( ) ; I != E ; ++ I ) { dbgs ( ) << '#' << I -> first << <STR_LIT> ; dump_partition ( dbgs ( ) , I -> second , * TRI ) ; dbgs ( ) << '\n' ; } } ) ; bool Changed = false ; int Limit = MaxHSDR ;


<s> SDValue Lo = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , Nd . getAlignment ( ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue Hi = DAG . getLoad ( <STR_LIT> , DL , Lo . getValue ( <NUM_LIT> ) , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , std :: min ( Nd . getAlignment ( ) , <NUM_LIT> ) ) ;

if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ;


<s> <ISA_LIT>FrameInfo ( const <ISA_LIT>Subtarget & sti ) : TargetFrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , Subtarget ( sti ) {


<s> FunctionPass * llvm :: create<ISA_LIT>NaClRewritePass ( ) {

return new <ISA_LIT>NaClRewritePass ( ) ;


<s> bool <ISA_LIT>AsmParser :: reportParseError ( SMLoc Loc , const Twine & ErrorMsg ) {


<s> int t ; saved_first_instruction = first_instruction ; in_safe_group_barrier = <NUM_LIT> ; t = group_barrier_needed ( insn ) ; first_instruction = saved_first_instruction ; in_safe_group_barrier = <NUM_LIT> ; return t ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( getMemBase ( ) ) ) ; addExpr ( Inst , getMemOff ( ) ) ;


<s> } LiveMask |= ( <NUM_LIT> << getFPReg ( Op ) ) ; MI . RemoveOperand ( i ) ; -- i ; -- e ; } adjustLiveRegs ( LiveMask , MI ) ; if ( ! LiveMask ) return ; if ( SecondFPRegOp == ~ <NUM_LIT> ) { assert ( StackTop == <NUM_LIT> && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; StackTop = <NUM_LIT> ; return ; } if ( StackTop == <NUM_LIT> ) { assert ( FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry ( <NUM_LIT> ) && <STR_LIT> ) ; unsigned NewReg = ScratchFPReg ; duplicateToTop ( FirstFPRegOp , NewReg , MI ) ; FirstFPRegOp = NewReg ; } assert ( StackTop == <NUM_LIT> && <STR_LIT> ) ; if ( getStackEntry ( <NUM_LIT> ) == SecondFPRegOp ) { assert ( getStackEntry ( <NUM_LIT> ) == FirstFPRegOp && <STR_LIT> ) ; moveToTop ( FirstFPRegOp , MI ) ; } assert ( getStackEntry ( <NUM_LIT> ) == FirstFPRegOp && <STR_LIT> ) ;

assert ( getStackEntry ( <NUM_LIT> ) == SecondFPRegOp && <STR_LIT> ) ;


<s> virtual const <ISA_LIT>ompactSubtarget * getSubtargetImpl ( ) const {


<s> if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else { SecondLastInst = I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isUncondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( ( isJumpTableBranchOpcode ( SecondLastOpc ) || isIndirectBranchOpcode ( SecondLastOpc ) ) && isUncondBranchOpcode ( LastOpc ) ) { I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; }

setBooleanContents ( ZeroOrOneBooleanContent ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseUNorm ( OperandVector & Operands ) {

return parseNamedBit ( <STR_LIT> , Operands , <ISA_LIT>Operand :: ImmTyUNorm ) ;


<s> rtx operands [ <NUM_LIT> ] ; gcc_assert ( cond ) ; operands [ <NUM_LIT> ] = label ; if ( get_attr_length ( insn ) > <NUM_LIT> ) { bool spilled ; if ( current_function_saves_lr ( ) ) { operands [ <NUM_LIT> ] = regno_reg_rtx [ LINK_REGNUM ] ; spilled = false ; } else if ( ! df_regs_ever_live_p ( long_branch_regnum ) ) { operands [ <NUM_LIT> ] = regno_reg_rtx [ long_branch_regnum ] ; spilled = false ; } else { operands [ <NUM_LIT> ] = regno_reg_rtx [ long_branch_regnum ] ; spilled = true ; gcc_assert ( current_function_has_lr_slot ( ) ) ; } if ( spilled ) { if ( final_sequence ) { rtx_insn * delay = NEXT_INSN ( insn ) ; int seen ; gcc_assert ( delay ) ; final_scan_insn ( delay , asm_out_file , optimize , <NUM_LIT> , & seen ) ; PATTERN ( delay ) = gen_blockage ( ) ; INSN_CODE ( delay ) = - <NUM_LIT> ; } if ( current_function_saves_fp ( ) ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; } output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; strcpy ( str , <STR_LIT> ) ; strcat ( str , cond ) ; strcat ( str , <STR_LIT> ) ; if ( ! spilled ) strcat ( str , <STR_LIT> ) ; strcat ( str , <STR_LIT> ) ; output_asm_insn ( str , operands ) ; if ( spilled ) { if ( current_function_saves_fp ( ) ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ; } } else if ( label == pc_rtx ) { strcpy ( str , <STR_LIT> ) ; strcat ( str , cond ) ; strcat ( str , <STR_LIT> ) ; output_asm_insn ( str , operands ) ;


<s> if ( Desc . getRecurrenceType ( ) -> isFP128Ty ( ) ) return false ; RecurrenceDescriptor :: RecurrenceKind RecKind = Desc . getRecurrenceKind ( ) ; switch ( RecKind ) { default : break ; case RecurrenceDescriptor :: RK_IntegerAdd : case RecurrenceDescriptor :: RK_IntegerAnd : case RecurrenceDescriptor :: RK_IntegerOr : case RecurrenceDescriptor :: RK_IntegerXor : case RecurrenceDescriptor :: RK_FloatAdd : return true ; } if ( ( RecKind == RecurrenceDescriptor :: RK_FloatMinMax ) || ( RecKind == RecurrenceDescriptor :: RK_IntegerMinMax ) ) { switch ( Desc . getMinMaxRecurrenceKind ( ) ) { default : break ; case RecurrenceDescriptor :: MRK_SIntMax : case RecurrenceDescriptor :: MRK_SIntMin : case RecurrenceDescriptor :: MRK_UIntMax : case RecurrenceDescriptor :: MRK_UIntMin :

case RecurrenceDescriptor :: MRK_FloatMin :


<s> case <STR_LIT> : return false ; } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM ) ) { if ( TLI . getPointerTy ( ) == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg ; } return <NUM_LIT> ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = <NUM_LIT> ; if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; } else if ( Subtarget -> isPICStyleRIPRel ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) { PICBase = <STR_LIT> ; }

unsigned MCPOffset = MCP . getConstantPoolIndex ( C , Align ) ;


<s> static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset4 = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset4 , LocVT , LocInfo ) ) ; return false ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static void begin_decl_field ( void ) { if ( decl_offset == decl_chunk_size ) fprintf ( asm_out_file , <STR_LIT> ) ; else fprintf ( asm_out_file , <STR_LIT> ) ;


<s> unsigned int save_reg_mask = <NUM_LIT> ; unsigned int reg ; if ( IS_INTERRUPT ( func_type ) ) { unsigned int max_reg ; if ( ARM_FUNC_TYPE ( func_type ) == ARM_FT_FIQ ) max_reg = <NUM_LIT> ; else max_reg = <NUM_LIT> ; for ( reg = <NUM_LIT> ; reg <= max_reg ; reg ++ ) if ( regs_ever_live [ reg ] || ( ! current_function_is_leaf && call_used_regs [ reg ] ) ) save_reg_mask |= ( <NUM_LIT> << reg ) ; } else { for ( reg = <NUM_LIT> ; reg <= <NUM_LIT> ; reg ++ ) if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) save_reg_mask |= ( <NUM_LIT> << reg ) ;


<s> rtx insn ; insn = get_last_insn ( ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;

REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , frame_pattern , REG_NOTES ( insn ) ) ;


<s> llvm :: make_early_inc_range ( MRI . reg_operands ( PReg ) ) ) { if ( ! MO . isImplicit ( ) ) { if ( VReg == <STR_LIT> ) { VReg = MRI . createVirtualRegister ( RC ) ; if ( PReg == TRI . getFrameRegister ( MF ) ) { auto FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! FI -> isFrameBaseVirtual ( ) ) ; FI -> setFrameBaseVreg ( VReg ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << PReg << <STR_LIT> << VReg << <STR_LIT> << Register :: virtReg2Index ( VReg ) << <STR_LIT> ; } ) ; } }


<s> return getMemoryOpCost ( Instruction :: Store , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Load , ScalarType , SclAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) ; } if ( Opcode == Instruction :: InsertElement ) { return getMemoryOpCost ( Instruction :: Store , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Store , ScalarType , SclAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) + getMemoryOpCost ( Instruction :: Load , Val , VecAlign , <NUM_LIT> , TTI :: TargetCostKind :: TCK_RecipThroughput ) ; } } if ( Index != - <NUM_LIT> && ( Opcode == Instruction :: ExtractElement || Opcode == Instruction :: InsertElement ) ) { if ( Opcode == Instruction :: ExtractElement && ScalarType -> getScalarSizeInBits ( ) == <NUM_LIT> && cast < FixedVectorType > ( Val ) -> getNumElements ( ) > <NUM_LIT> ) return <NUM_LIT> ; std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned SizeInBits = LT . second . getSizeInBits ( ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned SubNumElts = NumElts ; Index = Index % NumElts ; if ( SizeInBits > <NUM_LIT> ) { assert ( ( SizeInBits % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSubVecs = SizeInBits / <NUM_LIT> ; SubNumElts = NumElts / NumSubVecs ; if ( SubNumElts <= Index ) { RegisterFileMoveCost += ( Opcode == Instruction :: InsertElement ? <NUM_LIT> : <NUM_LIT> ) ; Index %= SubNumElts ; } } if ( Index == <NUM_LIT> ) { if ( ScalarType -> isFloatingPointTy ( ) ) return RegisterFileMoveCost ; if ( ScalarType -> isIntegerTy ( ) && Opcode == Instruction :: ExtractElement ) return <NUM_LIT> + RegisterFileMoveCost ; } int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ;


<s> SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , DAG . getConstant ( TargetCC , <STR_LIT> ) , Flag ) ;


<s> CodeModel :: Model CM = DAG . getTarget ( ) . getCodeModel ( ) ; SDValue Result ; if ( Subtarget . isPC32DBLSymbol ( GV , CM ) ) { if ( isInt < <NUM_LIT> > ( Offset ) ) { uint64_t Anchor = Offset & ~ uint64_t ( <NUM_LIT> ) ; Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Offset -= Anchor ; if ( Offset != <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) { SDValue Full = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor + Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Full , Result ) ;


<s> auto BB = R . Begin -> getParent ( ) ; Sch . BaseClass :: startBlock ( BB ) ; Sch . BaseClass :: enterRegion ( BB , R . Begin , R . End , R . NumRegionInstrs ) ; Sch . buildSchedGraph ( Sch . AA , nullptr , nullptr , nullptr , true ) ; Sch . Topo . InitDAGTopologicalSorting ( ) ; SmallVector < SUnit * , <NUM_LIT> > BotRoots ;

Sch . findRootsAndBiasEdges ( TopRoots , BotRoots ) ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; RDA = & getAnalysis < ReachingDefAnalysis > ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Fn . getName ( ) << '\n' ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : Fn ) Modified |= InsertVPTBlocks ( MBB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return Modified ;


<s> bool evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const override {


<s> <ISA_LIT>DomainReassignment ( ) : MachineFunctionPass ( ID ) {


<s> case <STR_LIT> : case <STR_LIT> : SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) return false ; SrcReg2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpValue = <NUM_LIT> ; } else if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) { SrcReg2 = Register ( ) ; CmpValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else {


<s> const R600MachineFunctionInfo * MFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < R600MachineFunctionInfo > ( ) ;

return MFI -> ShaderType != ShaderType :: COMPUTE && usesVertexCache ( MI -> getOpcode ( ) ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; ArgInfo OrigRetInfo ( VRegs , Val -> getType ( ) ) ; setArgFlags ( OrigRetInfo , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitRetInfos ; splitToValueTypes ( OrigRetInfo , SplitRetInfos , DL , MRI , CC , [ & ] ( ArrayRef < Register > Regs , LLT LLTy , LLT PartLLT , int VTSplitIdx ) {

unpackRegsToOrigType ( MIRBuilder , Regs , VRegs [ VTSplitIdx ] , LLTy , PartLLT ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == <STR_LIT> || SVT == <STR_LIT> ) || ! isOperationLegal ( <STR_LIT> , VT ) ) break ; SmallVector < SDValue , <NUM_LIT> > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) NewOps [ i ] = getCheaperNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + <NUM_LIT> ) ; bool NegA = ! ! NewOps [ <NUM_LIT> ] ; bool NegB = ! ! NewOps [ <NUM_LIT> ] ; bool NegC = ! ! NewOps [ <NUM_LIT> ] ; unsigned NewOpc = negateFMAOpcode ( Opc , NegA != NegB , NegC , true ) ; for ( int i = <NUM_LIT> , e = Op . getNumOperands ( ) ; i != e ; ++ i ) if ( ! NewOps [ i ] ) NewOps [ i ] = Op . getOperand ( i ) ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , VT , NewOps ) ; }


<s> StringRef getPassName ( ) const override {


if ( Kind != k_VectorList ) return false ;


<s> unsigned SPReg = <STR_LIT> ; SDValue SP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; Chain = SP . getValue ( <NUM_LIT> ) ; SDValue NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SP , Size ) ;

Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ;


<s> assert ( NumV1Elements > <NUM_LIT> && <STR_LIT> ) ; if ( NumV2Elements == <NUM_LIT> ) return false ; if ( NumV1Elements == NumV2Elements ) { int LowV1Elements = <NUM_LIT> , LowV2Elements = <NUM_LIT> ; for ( int M : Mask . slice ( <NUM_LIT> , NumElements / <NUM_LIT> ) ) if ( M >= NumElements ) ++ LowV2Elements ; else if ( M >= <NUM_LIT> ) ++ LowV1Elements ; if ( LowV2Elements > LowV1Elements ) return true ; if ( LowV2Elements == LowV1Elements ) { int SumV1Indices = <NUM_LIT> , SumV2Indices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= NumElements ) SumV2Indices += i ; else if ( Mask [ i ] >= <NUM_LIT> ) SumV1Indices += i ; if ( SumV2Indices < SumV1Indices ) return true ; if ( SumV2Indices == SumV1Indices ) { int NumV1OddIndices = <NUM_LIT> , NumV2OddIndices = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= NumElements ) NumV2OddIndices += i % <NUM_LIT> ; else if ( Mask [ i ] >= <NUM_LIT> ) NumV1OddIndices += i % <NUM_LIT> ; if ( NumV2OddIndices < NumV1OddIndices ) return true ; } } }


<s> if ( ST . is64Bit ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ! ST . is64Bit ( ) && ( ST . isTargetCygMing ( ) || ST . isTargetWindows ( ) ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return Ret ;


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;

Inst . addOperand ( MCOperand :: createReg ( FPR64DecoderTable [ RegNo ] ) ) ;


<s> static DecodeStatus DecodeMemExtend ( MCInst & Inst , unsigned Imm , uint64_t Address , const MCDisassembler * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( ( Imm >> <NUM_LIT> ) & <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( Imm & <NUM_LIT> ) ) ; return Success ;


<s> MachineBasicBlock :: iterator MBBI = Entry -> begin ( ) ; for ( const MCPhysReg * I = IStart ; * I ; ++ I ) { const TargetRegisterClass * RC = nullptr ; if ( <STR_LIT> . contains ( * I ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned NewVR = MRI -> createVirtualRegister ( RC ) ; assert ( Entry -> getParent ( ) -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) && <STR_LIT> ) ; Entry -> addLiveIn ( * I ) ; BuildMI ( * Entry , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVR ) . addReg ( * I ) ; for ( auto * Exit : Exits ) BuildMI ( * Exit , Exit -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * I ) . addReg ( NewVR ) ;


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) { addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ;


<s> MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; } } if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ; unsigned IntID = IsUnmasked ? <STR_LIT> : <STR_LIT> ; SmallVector < SDValue , <NUM_LIT> > Ops { Chain , DAG . getTargetConstant ( IntID , DL , XLenVT ) } ; Ops . push_back ( Val ) ; Ops . push_back ( BasePtr ) ; if ( ! IsUnmasked ) Ops . push_back ( Mask ) ; Ops . push_back ( VL ) ;

return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , Ops , MemVT , MMO ) ;


<s> assert ( SU -> isUnbuffered ) ; if ( LastFPdOpCycleIdx == UINT_MAX ) return true ;

if ( LastFPdOpCycleIdx > getCurrCycleIdx ( ) ) return ( ( LastFPdOpCycleIdx - getCurrCycleIdx ( ) ) == <NUM_LIT> ) ;


<s> unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; } case <STR_LIT> : { if ( ! ShouldCombineAggressively ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) != <STR_LIT> ) return false ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DestReg ) ; } default : break ; } return false ;


<s> Register Hi = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto LoConst = getIConstantVRegValWithLookThrough ( Lo , MRI ) ; auto HiConst = getIConstantVRegValWithLookThrough ( Hi , MRI ) ; if ( LoConst && HiConst ) { uint64_t Val = HiConst -> Value . getZExtValue ( ) << <NUM_LIT> | LoConst -> Value . getZExtValue ( ) ; auto Instr = Builder . buildInstr ( <STR_LIT> , { Dst , & <STR_LIT> } , { Val } ) ;

if ( ! constrainSelectedInstRegOperands ( * Instr , TII , TRI , RBI ) ) return false ;


<s> TargetRegisterClass * RC = isThumb ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , * FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase ; } if ( needsLowering ) { Addr . Base . Reg = FastEmit_ri_ ( <STR_LIT> , <STR_LIT> , Addr . Base . Reg , false , Addr . Offset , <STR_LIT> ) ; Addr . Offset = <NUM_LIT> ; }


<s> if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Subtarget . hasBWI ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( Is128BitLaneRepeatedShuffle && isSingleSHUFPSMask ( RepeatedMask ) ) { SDValue CastV1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; SDValue CastV2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; SDValue ShufPS = lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , CastV1 , CastV2 , DAG ) ; return DAG . getBitcast ( <STR_LIT> , ShufPS ) ; } if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ;

if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ;


<s> case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;

const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ;


<s> StringRef SecName ; if ( Global . hasSection ( ) ) { SecName = Global . getSection ( ) ; } else { if ( Global . isConstant ( ) ) SecName = <STR_LIT> ; else SecName = Global . getInitializer ( ) -> isZeroValue ( ) ? <STR_LIT> : <STR_LIT> ; } if ( ProcessingMapDef != SecName . startswith ( <STR_LIT> ) ) continue ; SmallVector < DIGlobalVariableExpression * , <NUM_LIT> > GVs ; Global . getDebugInfo ( GVs ) ; if ( GVs . size ( ) == <NUM_LIT> ) continue ; uint32_t GVTypeId = <NUM_LIT> ; for ( auto * GVE : GVs ) { if ( SecName . startswith ( <STR_LIT> ) ) visitMapDefType ( GVE -> getVariable ( ) -> getType ( ) , GVTypeId ) ; else visitTypeEntry ( GVE -> getVariable ( ) -> getType ( ) , GVTypeId , false , false ) ; break ;


<s> case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : break ; } const MCExpr * IdVal ; SMLoc S = getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) { Error ( getLoc ( ) , <STR_LIT> ) ;


<s> BOOL hasModRMExtension ; uint8_t instructionClass ; instructionClass = contextForAttrs ( attrMask ) ; hasModRMExtension = modRMRequired ( insn -> opcodeType , instructionClass , insn -> opcode ) ; if ( hasModRMExtension ) {

if ( readModRM ( insn ) ) return - <NUM_LIT> ;


<s> NodeAddr < StmtNode * > SA = newNode ( NodeAttrs :: Code | NodeAttrs :: Stmt ) ;


<s> if ( I >= VRegStackified . size ( ) ) return false ; return VRegStackified . test ( I ) ;


<s> SmallVectorImpl < PredicatedMI > & getInsts ( ) {


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) O << ( short ) MI -> getOperand ( OpNo ) . getImm ( ) ; else printOperand ( MI , OpNo , O ) ;


<s> TargetAsmBackend * llvm :: create<ISA_LIT>_32AsmBackend ( const Target & T , const std :: string & TT ) { switch ( Triple ( TT ) . getOS ( ) ) { case Triple :: Darwin :

return new Darwin<ISA_LIT>AsmBackend ( T ) ;


<s> return isThumb1Only ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> ++ I ) { const TargetRegisterClass * RC = * I ; if ( ( VT == <STR_LIT> || isTypeLegalForClass ( * RC , VT ) ) && RC -> contains ( reg ) && ( ! BestRC || ( BestRC -> hasSubClass ( RC ) && RC -> getNumRegs ( ) > BestRC -> getNumRegs ( ) ) ) ) BestRC = RC ;


<s> assert ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) ; int ShiftAmount = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShiftAmount == <NUM_LIT> ) return shiftBy8 ( Op , DAG ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return DAG . getNode ( <STR_LIT> , Dl , VT , Victim , DAG . getConstant ( ShiftAmount , Dl , <STR_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , Dl , VT , Victim , DAG . getConstant ( ShiftAmount , Dl , <STR_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , Dl , VT , Victim , DAG . getConstant ( ShiftAmount , Dl , <STR_LIT> ) ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> bool <ISA_LIT>FastISel :: selectAtomicCmpXchg ( const AtomicCmpXchgInst * I ) { assert ( TM . getOptLevel ( ) == CodeGenOpt :: None && <STR_LIT> ) ; auto * RetPairTy = cast < StructType > ( I -> getType ( ) ) ; Type * RetTy = RetPairTy -> getTypeAtIndex ( <NUM_LIT> ) ; assert ( RetPairTy -> getTypeAtIndex ( <NUM_LIT> ) -> isIntegerTy ( <NUM_LIT> ) && <STR_LIT> ) ; MVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; const TargetRegisterClass * ResRC ; unsigned Opc , CmpOpc ; if ( VT == <STR_LIT> ) { Opc = <STR_LIT> ; CmpOpc = <STR_LIT> ; ResRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opc = <STR_LIT> ; CmpOpc = <STR_LIT> ; ResRC = & <STR_LIT> ; } else { return false ; } const MCInstrDesc & II = TII . get ( Opc ) ; const Register AddrReg = constrainOperandRegClass ( II , getRegForValue ( I -> getPointerOperand ( ) ) , II . getNumDefs ( ) ) ; const Register DesiredReg = constrainOperandRegClass ( II , getRegForValue ( I -> getCompareOperand ( ) ) , II . getNumDefs ( ) + <NUM_LIT> ) ; const Register NewReg = constrainOperandRegClass ( II , getRegForValue ( I -> getNewValOperand ( ) ) , II . getNumDefs ( ) + <NUM_LIT> ) ; const Register ResultReg1 = createResultReg ( ResRC ) ; const Register ResultReg2 = createResultReg ( & <STR_LIT> ) ; const Register ScratchReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addDef ( ResultReg1 ) . addDef ( ScratchReg ) . addUse ( AddrReg ) . addUse ( DesiredReg ) . addUse ( NewReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( CmpOpc ) ) . addDef ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) . addUse ( ResultReg1 ) . addUse ( DesiredReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addDef ( ResultReg2 ) . addUse ( <STR_LIT> ) . addUse ( <STR_LIT> ) . addImm ( <STR_LIT> ) ; assert ( ( ResultReg1 + <NUM_LIT> ) == ResultReg2 && <STR_LIT> ) ;

updateValueMap ( I , ResultReg1 , <NUM_LIT> ) ;


<s> case <NUM_LIT> : return createRegOperand ( getMCReg ( FLAT_SCR , STI ) ) ; case <NUM_LIT> : return createRegOperand ( VCC ) ; case <NUM_LIT> : return createRegOperand ( TBA ) ; case <NUM_LIT> : return createRegOperand ( TMA ) ; case <NUM_LIT> : return createRegOperand ( EXEC ) ;


<s> case MachineOperand :: MO_GlobalAddress : CalleeMCOp = MCIL . LowerSymbolOperand ( CalleeMO , MCIL . GetSymbolFromOperand ( CalleeMO ) ) ; break ; } Register ScratchReg = MI . getOperand ( ScratchIdx ) . getReg ( ) ; if ( <STR_LIT> ( ScratchReg ) ) EncodedBytes = <NUM_LIT> ; else EncodedBytes = <NUM_LIT> ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addOperand ( CalleeMCOp ) ) ; if ( Subtarget -> useIndirectThunkCalls ( ) ) report_fatal_error ( <STR_LIT> ) ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) ) ; } unsigned NumBytes = opers . getNumPatchBytes ( ) ; assert ( NumBytes >= EncodedBytes && <STR_LIT> ) ;

EmitNops ( * OutStreamer , NumBytes - EncodedBytes , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ;


<s> while ( I -> isDebugValue ( ) ) { if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; } if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ;


<s> <STR_LIT> CondCode , CondCode2 ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 ) ; if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) && ( TrueVal . getValueType ( ) == <STR_LIT> || TrueVal . getValueType ( ) == <STR_LIT> ) ) { bool swapSides = false ; if ( ! getTargetMachine ( ) . Options . NoNaNsFPMath ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : swapSides = DAG . isKnownNeverNaN ( LHS ) && ! DAG . isKnownNeverNaN ( RHS ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : swapSides = DAG . isKnownNeverNaN ( RHS ) && ! DAG . isKnownNeverNaN ( LHS ) ; break ; } } swapSides = swapSides || ( LHS == FalseVal && RHS == TrueVal ) ; if ( swapSides ) { CC = <STR_LIT> ( CC ) ; std :: swap ( LHS , RHS ) ; } if ( LHS == TrueVal && RHS == FalseVal ) { bool canTransform = true ; if ( ! getTargetMachine ( ) . Options . UnsafeFPMath && ! DAG . isKnownNeverZero ( LHS ) && ! DAG . isKnownNeverZero ( RHS ) ) { const ConstantFPSDNode * Zero ; switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : canTransform = ( Zero = dyn_cast < ConstantFPSDNode > ( RHS ) ) && ! Zero -> isNegative ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : canTransform = ( Zero = dyn_cast < ConstantFPSDNode > ( LHS ) ) && ! Zero -> isNegative ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : canTransform = ( Zero = dyn_cast < ConstantFPSDNode > ( RHS ) ) && Zero -> isNegative ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : canTransform = ( Zero = dyn_cast < ConstantFPSDNode > ( LHS ) ) && Zero -> isNegative ( ) ; break ; } } if ( canTransform ) { switch ( CC ) { default :


<s> Register Tmp = Builder . buildPtrToInt ( LLT :: scalar ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) ) . getReg ( <NUM_LIT> ) ; Helper . Observer . changingInstr ( MI ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( Tmp ) ; Helper . Observer . changedInstr ( MI ) ;


<s> if ( f . type_suffix ( <NUM_LIT> ) . bool_p && f . type_suffix ( <NUM_LIT> ) . element_bits > <NUM_LIT> ) return NULL ; unsigned int nargs = gimple_call_num_args ( f . call ) ; poly_uint64 nelts = TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( f . lhs ) ) ; vec_perm_indices indices ( builder , nargs , nelts ) ; tree perm_type = build_vector_type ( ssizetype , nelts ) ; return gimple_build_assign ( f . lhs , VEC_PERM_EXPR , gimple_call_arg ( f . call , <NUM_LIT> ) , gimple_call_arg ( f . call , nargs - <NUM_LIT> ) , vec_perm_indices_to_tree ( perm_type , indices ) ) ;


<s> bool isMem ( ) const override { return false ;


<s> LLVM_FALLTHROUGH ; case <STR_LIT> : { if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { InstructionCost MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; InstructionCost ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } InstructionCost Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; } return Cost ; } case <STR_LIT> : if ( LT . second != <STR_LIT> || isWideningInstruction ( Ty , Opcode , Args ) ) return LT . first ; return LT . first * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LT . first ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

if ( ! Ty -> getScalarType ( ) -> isFP128Ty ( ) ) return <NUM_LIT> * LT . first ;


<s> return __builtin_ia32_maxph128_mask ( __A , __B , _mm_setzero_ph ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> unsigned Arg = getRegForValue ( ArgValue ) ; if ( Arg == <NUM_LIT> ) return false ; Args . push_back ( ArgValue ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! processCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , IsVarArg ) ) return false ; MachineInstrBuilder MIB ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV ) { if ( CLI . IsPatchPoint ) MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; else return false ; } else { MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ; MIB . addGlobalAddress ( GV ) ; } for ( unsigned II = <NUM_LIT> , IE = RegArgs . size ( ) ; II != IE ; ++ II ) MIB . addReg ( RegArgs [ II ] , RegState :: Implicit ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( CC ) ) ;


return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true , true , true ) ;


<s> void HandleAssemblerFlag ( MCAssemblerFlag Flag ) {


<s> <ISA_LIT>MachObjectWriter ( uint32_t CPUType , uint32_t CPUSubtype ) : MCMachObjectTargetWriter ( true , CPUType , CPUSubtype , true ) {


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , uint8_t _OSABI ) : <ISA_LIT>AsmBackend ( T , TT ) , OSABI ( _OSABI ) {


<s> if ( ReduceLimitLdSt != - <NUM_LIT> && ( ( int ) NumLdSts >= ReduceLimitLdSt ) ) return false ; unsigned Scale = <NUM_LIT> ; bool HasImmOffset = false ; bool HasShift = false ; bool HasOffReg = true ; bool isLdStMul = false ; unsigned Opc = Entry . NarrowOpc1 ; unsigned OpNum = <NUM_LIT> ; uint8_t ImmLimit = Entry . Imm1Limit ; switch ( Entry . WideOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { Opc = Entry . NarrowOpc2 ; ImmLimit = Entry . Imm2Limit ; HasOffReg = false ; } Scale = <NUM_LIT> ; HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; HasImmOffset = true ; HasOffReg = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : HasShift = true ; OpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || Entry . WideOpc != <STR_LIT> ) return false ; bool isOK = false ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { if ( MI -> getOperand ( i ) . getReg ( ) == BaseReg ) { isOK = true ; break ; } } if ( ! isOK ) return false ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { OpNum = <NUM_LIT> ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> && ( Entry . WideOpc == <STR_LIT> || Entry . WideOpc == <STR_LIT> ) ) { Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul = true ; break ; } } unsigned OffsetReg = <NUM_LIT> ; bool OffsetKill = false ; if ( HasShift ) { OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; }


<s> bool isABI_FPXX ( ) const { return false ;


<s> static SDValue MergeInputChains ( SDNode * N1 , SDNode * N2 ) { SDValue Chain1 = N1 -> getOperand ( <NUM_LIT> ) ; SDValue Chain2 = N2 -> getOperand ( <NUM_LIT> ) ;


<s> State ( IBES_START ) , BaseReg ( <NUM_LIT> ) , IndexReg ( <NUM_LIT> ) , Scale ( <NUM_LIT> ) , Disp ( <NUM_LIT> ) , TmpReg ( <NUM_LIT> ) , TmpInteger ( <NUM_LIT> ) , isPlus ( true ) {


<s> Instruction * <ISA_LIT>ParallelDSP :: CreateSMLADCall ( LoadInst * VecLd0 , LoadInst * VecLd1 , Instruction * Acc , Instruction * InsertAfter ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; VecLd0 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; VecLd1 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Acc -> dump ( ) ) ; IRBuilder < NoFolder > Builder ( InsertAfter -> getParent ( ) , ++ BasicBlock :: iterator ( InsertAfter ) ) ; CreateLoadIns ( Builder , Acc , & VecLd0 ) ; CreateLoadIns ( Builder , Acc , & VecLd1 ) ; Value * Args [ ] = { VecLd0 , VecLd1 , Acc } ;

Function * SMLAD = <STR_LIT> ( M , <STR_LIT> ) ;


<s> } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; const char * Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL -> getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: Create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateAdd ( PCRelExpr , MCConstantExpr :: Create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . CreateTempSymbol ( ) ; OutStreamer . EmitLabel ( DotSym ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: Create ( DotSym , OutContext ) ; PCRelExpr = MCBinaryExpr :: CreateSub ( PCRelExpr , DotExpr , OutContext ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>BEAsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) { return create<ISA_LIT>AsmBackend ( T , STI , MRI , Options , false ) ;


<s> if ( ! RegNum ) { auto Entry = RegisterReqs . find ( Name . lower ( ) ) ; if ( Entry == RegisterReqs . end ( ) ) return <NUM_LIT> ; if ( Kind == Entry -> getValue ( ) . first ) RegNum = Entry -> getValue ( ) . second ;


<s> const Constant * C = GV -> getInitializer ( ) ; unsigned Align = ( unsigned ) DL . getPreferredTypeAlignmentShift ( C -> getType ( ) ) ; getTargetStreamer ( ) . emitCCTopData ( GVSym -> getName ( ) ) ; switch ( GV -> getLinkage ( ) ) { case GlobalValue :: AppendingLinkage : report_fatal_error ( <STR_LIT> ) ; case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : case GlobalValue :: ExternalLinkage : case GlobalValue :: CommonLinkage : emitArrayBound ( GVSym , GV ) ; OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_Global ) ; if ( GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) || GV -> hasCommonLinkage ( ) ) OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_Weak ) ; LLVM_FALLTHROUGH ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> Value * <ISA_LIT>TargetLowering :: emitLoadLinked ( IRBuilder < > & Builder , Value * Addr , AtomicOrdering Ord ) const { Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; Type * ValTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; bool IsAcquire = isAtLeastAcquire ( Ord ) ; if ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = llvm :: <STR_LIT> ( M , Int ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ;

Value * LoHi = Builder . CreateCall ( Ldxr , Addr , <STR_LIT> ) ;


<s> <ISA_LIT>PostLegalizerCombinerInfo ( bool EnableOpt , bool OptSize , bool MinSize , const <ISA_LIT>LegalizerInfo * LI , GISelKnownBits * KB , MachineDominatorTree * MDT ) : CombinerInfo ( false , true , LI , EnableOpt , OptSize , MinSize ) , KB ( KB ) , MDT ( MDT ) { if ( ! Generated . parseCommandLineOption ( ) ) report_fatal_error ( <STR_LIT> ) ;


<s> void setKind ( BaseKind K ) { Kind = K ;


<s> if ( st . hasV6Ops ( ) || <STR_LIT> . contains ( SrcReg ) || ! <STR_LIT> . contains ( DestReg ) ) AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ; else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ) . addReg ( DestReg , getDefRegState ( true ) ) ;


<s> for ( auto Op : Node -> operands ( ) ) if ( Op -> getNumOperands ( ) ) Printf -> push_back ( std :: make_shared < msgpack :: ScalarNode > ( cast < MDString > ( Op -> getOperand ( <NUM_LIT> ) ) -> getString ( ) ) ) ;

getRootMetadata ( <STR_LIT> ) = std :: move ( Printf ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) {


<s> bool hasTSXLDTRK ( ) const { return HasTSXLDTRK ;


<s> void setPreheader ( MachineBasicBlock * NewPreheader ) override {


<s> SpillCostAnalysisGraph ( const <ISA_LIT>Subtarget & s ) : STC ( s ) {


<s> static DecodeStatus DecodeDoubleRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t , const void * Decoder ) { static const uint16_t DoubleRegDecoderTable [ ] = {


<s> if ( ! SelectOff ( N , Reg , Off ) ) {


<s> * rECX = registers [ <NUM_LIT> ] ; * rEDX = registers [ <NUM_LIT> ] ; return false ; return true ; asm ( <STR_LIT> <STR_LIT> <STR_LIT> : <STR_LIT> ( * rEAX ) , <STR_LIT> ( * rEBX ) , <STR_LIT> ( * rECX ) , <STR_LIT> ( * rEDX ) : <STR_LIT> ( value ) ) ; return false ; __asm { mov eax , value cpuid mov esi , rEAX mov dword ptr [ esi ] , eax mov esi , rEBX mov dword ptr [ esi ] , ebx mov esi , rECX mov dword ptr [ esi ] , ecx mov esi , rEDX mov dword ptr [ esi ] , edx }


<s> int opc ; if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) opc = <STR_LIT> ; else opc = <STR_LIT> ; BuildMI ( MBB , I , DL , get ( opc ) ) . addReg ( DestReg ) . addReg ( SrcReg ) ;


<s> default : return false ; case IS_DISPATCH_ON : return true ; break ; case IS_CMP : return is_cmp ( insn ) ; case DISPATCH_VIOLATION : return dispatch_violation ( ) ; case FITS_DISPATCH_WINDOW : return fits_dispatch_window ( insn ) ;


<s> if ( ! StrImm . empty ( ) ) addStringImm ( StrImm , MIB ) ; for ( const auto & DecArg : DecArgs ) MIB . addImm ( DecArg ) ;


<s> MEE = LastMI_GRNar ; } else { MII = FirstMI_GRNar ; MEE = LastMI_GR128 ; } BitVector PhysClobbered ( getNumRegs ( ) ) ; MEE ++ ; for ( ; MII != MEE ; ++ MII ) { for ( const MachineOperand & MO : MII -> operands ( ) ) if ( MO . isReg ( ) && Register :: isPhysicalRegister ( MO . getReg ( ) ) ) { for ( MCSuperRegIterator SI ( MO . getReg ( ) , this , true ) ; SI . isValid ( ) ; ++ SI ) if ( NewRC -> contains ( * SI ) ) { PhysClobbered . set ( * SI ) ; break ; } } } unsigned const DemandedFreeGR128 = <NUM_LIT> ;

if ( PhysClobbered . count ( ) > ( NewRC -> getNumRegs ( ) - DemandedFreeGR128 ) ) return false ;


<s> static unsigned int c6x_function_arg_round_boundary ( machine_mode mode , const_tree type ) { return c6x_function_arg_boundary ( mode , type ) ;


<s> ConstantSDNode * OffsetConst = dyn_cast < ConstantSDNode > ( Offset . getNode ( ) ) ; return OffsetConst && isValidImmForSVEVecImmAddrMode ( OffsetConst -> getZExtValue ( ) , ScalarSizeInBytes ) ;


<s> return isThumb ( ) && ! hasThumb2 ( ) ;


<s> Value * <ISA_LIT>IREmitter :: visitSRA_FLAG ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> Inst . addOperand ( MCOperand :: createReg ( getMemIndexReg ( ) ) ) ;


<s> int nios2_can_use_return_insn ( void ) { if ( ! reload_completed || crtl -> profile ) return <NUM_LIT> ; return nios2_compute_frame_layout ( ) == <NUM_LIT> ;


<s> virtual void emitARM64WinCFISaveRegP ( unsigned Reg , int Offset ) {


<s> bool R ; if ( Outs [ i ] . IsFixed ) R = CC_<ISA_LIT>N ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ; else R = CC_<ISA_LIT>N_VarArg ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ;


<s> if ( GET_CODE ( op1 ) == SUBREG && subreg_lowpart_p ( op1 ) ) op1 = XEXP ( op1 , <NUM_LIT> ) ; if ( ! ( register_operand ( op1 , GET_MODE ( op1 ) ) || GET_CODE ( op1 ) == PLUS ) ) return false ; if ( ! immediate_operand ( imm , GET_MODE ( imm ) ) ) return false ; HOST_WIDE_INT val = INTVAL ( imm ) ; if ( implicit_mask > <NUM_LIT> && ( val & implicit_mask ) != implicit_mask ) return false ; op = op1 ;


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; }

const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ;


addPass ( createUnpackMachineBundles ( nullptr ) ) ;


<s> if ( <STR_LIT> . contains ( LinkReg ) ) { MI . setDesc ( MII . get ( <STR_LIT> ) ) ; return true ; } return false ;


<s> unsigned getCSRFirstUseCost ( const MachineFunction & MF ) const override {


<s> setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Legal ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; for ( MVT InnerVT : <STR_LIT> ( ) ) setLoadExtAction ( <STR_LIT> , InnerVT , VT . getSimpleVT ( ) , Expand ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ! VT . isFloatingPoint ( ) && VT . getSimpleVT ( ) != <STR_LIT> && VT . getSimpleVT ( ) != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT . getSimpleVT ( ) , Legal ) ; if ( VT . isFloatingPoint ( ) && VT . getVectorElementType ( ) != <STR_LIT> ) for ( unsigned Opcode : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Opcode , VT . getSimpleVT ( ) , Legal ) ; if ( Subtarget -> isLittleEndian ( ) ) { for ( unsigned im = ( unsigned ) <STR_LIT> ; im != ( unsigned ) <STR_LIT> ; ++ im ) {

setIndexedLoadAction ( im , VT . getSimpleVT ( ) , Legal ) ;


<s> static SDValue LowerVectorFP_TO_INT ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; if ( Op . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) { if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } const bool HasFullFP16 = static_cast < const <ISA_LIT>Subtarget & > ( DAG . getSubtarget ( ) ) . hasFullFP16 ( ) ; EVT NewTy ; const EVT OpTy = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OpTy == <STR_LIT> ) NewTy = <STR_LIT> ; else if ( OpTy == <STR_LIT> && HasFullFP16 ) NewTy = <STR_LIT> ; else if ( OpTy == <STR_LIT> && HasFullFP16 ) NewTy = <STR_LIT> ;


<s> case <NUM_LIT> : RegClassID = <STR_LIT> ; break ; case <NUM_LIT> : if ( Opc == <STR_LIT> ) RegClassID = <STR_LIT> ; else RegClassID = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } SelectBuildVector ( N , RegClassID ) ; return ;


<s> OperandMatchResultTy ResTy = ParseImm ( Operands ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; ResTy = ParseAnyRegister ( Operands ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; const MCExpr * Expr = nullptr ; if ( Parser . parseExpression ( Expr ) ) { return MatchOperand_ParseFail ; } Operands . push_back ( <STR_LIT> ( Expr , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> return __builtin_loongson_psubb_s ( s , t ) ;


<s> void addVectorIndexHOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateImm ( getVectorIndex ( ) ) ) ;


<s> OPCODE ( ICMP ) ; OPCODE ( FCMP ) ; OPCODE ( TM ) ; OPCODE ( BR_CCMASK ) ; OPCODE ( SELECT_CCMASK ) ; OPCODE ( ADJDYNALLOC ) ; OPCODE ( EXTRACT_ACCESS ) ; OPCODE ( UMUL_LOHI64 ) ; OPCODE ( SDIVREM64 ) ; OPCODE ( UDIVREM32 ) ; OPCODE ( UDIVREM64 ) ; OPCODE ( MVC ) ; OPCODE ( MVC_LOOP ) ; OPCODE ( NC ) ; OPCODE ( NC_LOOP ) ; OPCODE ( OC ) ; OPCODE ( OC_LOOP ) ; OPCODE ( XC ) ; OPCODE ( XC_LOOP ) ; OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STRCMP ) ; OPCODE ( STPCPY ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( SERIALIZE ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( ATOMIC_SWAPW ) ;


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const <ISA_LIT>TargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) {


<s> void <ISA_LIT>DAGToDAGISel :: SelectDIV_SCALE ( SDNode * N ) { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;

SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ;


<s> rtx loop_label , tmp ; if ( optimize_size || optimize < <NUM_LIT> ) return false ; gcc_assert ( MEM_P ( str ) ) ; gcc_assert ( CONST_INT_P ( target_char ) || REG_P ( target_char ) ) ; base_reg = copy_to_mode_reg ( SImode , XEXP ( str , <NUM_LIT> ) ) ; loop_label = gen_label_rtx ( ) ; ffb_result = gen_reg_rtx ( Pmode ) ; tmp = gen_reg_rtx ( SImode ) ; backup_base_reg = gen_reg_rtx ( SImode ) ; emit_move_insn ( backup_base_reg , base_reg ) ; emit_label ( loop_label ) ; emit_insn ( gen_unaligned_load_update_base_w ( base_reg , tmp , base_reg ) ) ; emit_insn ( gen_unspec_ffb ( ffb_result , tmp , target_char ) ) ; emit_cmp_and_jump_insns ( ffb_result , const0_rtx , EQ , NULL , SImode , <NUM_LIT> , loop_label ) ; target_char_ptr = expand_binop ( Pmode , add_optab , base_reg , ffb_result , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; length = expand_binop ( Pmode , sub_optab , target_char_ptr , backup_base_reg , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ;


<s> SDValue StoreVal = Store -> getValue ( ) ; MVT VT = StoreVal . getSimpleValueType ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> && VT . getVectorNumElements ( ) < <NUM_LIT> ) { VT = <STR_LIT> ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , StoreVal , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDValue NewValue = convertToScalableVector ( ContainerVT , StoreVal , DAG , Subtarget ) ;

return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , { Store -> getChain ( ) , NewValue , Store -> getBasePtr ( ) , VL } , Store -> getMemoryVT ( ) , Store -> getMemOperand ( ) ) ;


<s> static bool shouldForceImediateOperand ( StringRef Name , unsigned OperandIdx ) { switch ( OperandIdx ) { case <NUM_LIT> : return Name == <STR_LIT> || Name == <STR_LIT> ; case <NUM_LIT> : return Name == <STR_LIT> ; default : return false ;


<s> default : break ; case <STR_LIT> : Is64Bit = false ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( ! UseControlFlowSpeculationBarrier && ! UsesFullSpeculationBarrier ) { Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( MachineOperand Op : MI . defs ( ) ) for ( MCRegAliasIterator AI ( Op . getReg ( ) , TRI , true ) ; AI . isValid ( ) ; ++ AI ) RegsNeedingCSDBBeforeUse . set ( * AI ) ; BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , Is64Bit ? TII -> get ( <STR_LIT> ) : TII -> get ( <STR_LIT> ) ) . addDef ( DstReg ) . addUse ( SrcReg , RegState :: Kill ) . addUse ( Is64Bit ? MisspeculatingTaintReg : MisspeculatingTaintReg32Bit ) . addImm ( <NUM_LIT> ) ;


<s> vld1q_p16 ( const poly16_t * __a ) {

return ( poly16x8_t ) __builtin_neon_vld1v8hi ( ( const __builtin_neon_hi * ) __a ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return None ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : return LowerSymbolOperand ( MO , GetSymbolFromOperand ( MO ) ) ; case MachineOperand :: MO_MCSymbol : return LowerSymbolOperand ( MO , MO . getMCSymbol ( ) ) ; case MachineOperand :: MO_JumpTableIndex :

return LowerSymbolOperand ( MO , AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ) ;


<s> <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> for ( offset = <NUM_LIT> , chainp = & aof_pic_chain ; * chainp ; offset += <NUM_LIT> , chainp = & ( * chainp ) -> next ) if ( ( * chainp ) -> symname == XSTR ( x , <NUM_LIT> ) ) return plus_constant ( aof_pic_label , offset ) ; * chainp = ( struct pic_chain * ) xmalloc ( sizeof ( struct pic_chain ) ) ; ( * chainp ) -> next = NULL ; ( * chainp ) -> symname = XSTR ( x , <NUM_LIT> ) ;


<s> MachineBasicBlock * <ISA_LIT>ConstantIslands :: adjustJTTargetBlockForward ( unsigned JTI , MachineBasicBlock * BB , MachineBasicBlock * JTBB ) { MachineBasicBlock * TBB = nullptr , * FBB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; SmallVector < MachineOperand , <NUM_LIT> > CondPrior ; MachineFunction :: iterator BBi = BB -> getIterator ( ) ; MachineFunction :: iterator OldPrior = std :: prev ( BBi ) ; MachineFunction :: iterator OldNext = std :: next ( BBi ) ; bool B = TII -> analyzeBranch ( * BB , TBB , FBB , Cond ) ; if ( ! B && Cond . empty ( ) && BB != & MF -> front ( ) && ! TII -> analyzeBranch ( * OldPrior , TBB , FBB , CondPrior ) ) { BB -> moveAfter ( JTBB ) ; OldPrior -> updateTerminator ( BB ) ; BB -> updateTerminator ( OldNext != MF -> end ( ) ? & * OldNext : nullptr ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return nullptr ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ JTBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; for ( const MachineBasicBlock :: RegisterMaskPair & RegMaskPair : BB -> liveins ( ) ) NewBB -> addLiveIn ( RegMaskPair ) ; if ( isThumb2 ) BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . add ( predOps ( <STR_LIT> ) ) ; MF -> RenumberBlocks ( NewBB ) ; NewBB -> addSuccessor ( BB ) ; JTBB -> replaceSuccessor ( BB , NewBB ) ; if ( MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> branchTargetEnforcement ( ) ) fixupBTI ( JTI , * BB , * NewBB ) ; ++ NumJTInserted ; return NewBB ;


<s> RegisterMCAsmLexer < <ISA_LIT>AsmLexer > X ( The<ISA_LIT>_32Target ) ; RegisterMCAsmLexer < <ISA_LIT>AsmLexer > Y ( The<ISA_LIT>_64Target ) ;


<s> const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned BaseIdx = alignDown ( ST . getMaxNumSGPRs ( MF ) , <NUM_LIT> ) - <NUM_LIT> ;

unsigned BaseReg ( <STR_LIT> . getRegister ( BaseIdx ) ) ;


<s> SmallDenseSet < unsigned > SGPRsUsed ; Register SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ; if ( SGPRReg != <STR_LIT> ) { SGPRsUsed . insert ( SGPRReg ) ; -- ConstantBusLimit ; } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = VOP3Idx [ i ] ; if ( Idx == - <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) ) { if ( ! isLiteralConstantLike ( MO , get ( Opc ) . OpInfo [ Idx ] ) ) continue ; if ( LiteralLimit > <NUM_LIT> && ConstantBusLimit > <NUM_LIT> ) { -- LiteralLimit ; -- ConstantBusLimit ; continue ; } -- LiteralLimit ; -- ConstantBusLimit ; legalizeOpWithMove ( MI , Idx ) ; continue ; } if ( RI . hasAGPRs ( MRI . getRegClass ( MO . getReg ( ) ) ) && ! isOperandLegal ( MI , Idx , & MO ) ) { legalizeOpWithMove ( MI , Idx ) ; continue ; } if ( ! RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ) continue ; if ( SGPRsUsed . count ( MO . getReg ( ) ) ) continue ;


<s> uint64_t getRVVStackSize ( ) const {


<s> if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;

return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( MI . isMoveReg ( ) ) { Dest = & MI . getOperand ( <NUM_LIT> ) ; Src = & MI . getOperand ( <NUM_LIT> ) ;


<s> case OPWV232 : return MCOperand :: createImm ( getInlineImmVal32 ( Imm ) ) ; case OPW64 : case OPW256 : return MCOperand :: createImm ( getInlineImmVal64 ( Imm ) ) ; case OPW16 : case OPWV216 : return MCOperand :: createImm ( getInlineImmVal16 ( Imm ) ) ; default :


<s> StringRef RegSuffix = RegName . substr ( RI -> Name . size ( ) ) ; if ( ! RegSuffix . empty ( ) ) { if ( ! getRegNum ( RegSuffix , RegNum ) ) { Error ( Loc , <STR_LIT> ) ; return <STR_LIT> ; } RegWidth = <NUM_LIT> ; } else {

if ( ! ParseRegRange ( RegNum , RegWidth ) ) return <STR_LIT> ;


<s> case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : {

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


<s> PrevState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_CAST : case IES_PLUS : case IES_MINUS : case IES_NOT : case IES_INIT : case IES_LBRAC : case IES_LPAREN : if ( setSymRef ( SymRef , SymRefName , ErrMsg ) ) return true ; MemExpr = true ; State = IES_INTEGER ; IC . pushOperand ( IC_IMM ) ; if ( ParsingMSInlineAsm ) Info = IDInfo ;


<s> void setCalleeSavedStackSize ( unsigned Size ) { CalleeSavedStackSize = Size ;


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser ( parser ) {

setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> LLVMContext & Ctx = F . getContext ( ) ; IntegerType * I16 = Type :: getInt16Ty ( Ctx ) ; FunctionType * FnType = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , { Type :: getInt8PtrTy ( Ctx ) , I16 } , false ) ; Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( SymName , FnType ) ;

Value * FunctionName = CreateStringPtr ( BB , F . getName ( ) ) ;


<s> const MCGSites & getCallingSites ( ) const { return CallingSites ;


<s> bool isImplicitlyTypedVectorList ( ) const { return Kind == k_VectorList && VectorList . Count == NumRegs && ! VectorList . ElementKind && ! VectorList . IsSVE ;


<s> Register BaseReg = getLdStBaseOp ( MemMI ) . getReg ( ) ; int Offset = getLdStOffsetOp ( MemMI ) . getImm ( ) ; if ( MBBI == B || Offset != <NUM_LIT> ) return E ; if ( ! isTagStore ( MemMI ) ) { bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { Register DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } } ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; unsigned Count = <NUM_LIT> ; do {


<s> static bool getTargetShuffleInputs ( SDValue Op , SmallVectorImpl < SDValue > & Inputs , SmallVectorImpl < int > & Mask , const SelectionDAG & DAG , unsigned Depth = <NUM_LIT> , bool ResolveKnownElts = true ) { EVT VT = Op . getValueType ( ) ; if ( ! VT . isSimple ( ) || ! VT . isVector ( ) ) return false ; APInt KnownUndef , KnownZero ; unsigned NumElts = Op . getValueType ( ) . getVectorNumElements ( ) ;

APInt DemandedElts = APInt :: getAllOnes ( NumElts ) ;


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return <NUM_LIT> ;

return MRI -> getUniqueVRegDef ( Reg ) ;


<s> rtx TWO52 ; fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & TWO52r , fmt -> p - <NUM_LIT> , mode ) ; TWO52 = const_double_from_real_value ( TWO52r , mode ) ;


<s> assert ( Op . getValueType ( ) . isFixedLengthVector ( ) && <STR_LIT> ) ; EVT InVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ;

unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> bool <ISA_LIT>OptAddrMode :: isValidOffset ( MachineInstr * MI , int Offset ) { if ( HII -> isHVXVec ( * MI ) ) { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return HII -> isValidOffset ( MI -> getOpcode ( ) , Offset , HRI , false ) ; default : return false ; } } if ( HII -> getAddrMode ( * MI ) != <STR_LIT> ) return false ; unsigned AlignMask = <NUM_LIT> ; switch ( HII -> getMemAccessSize ( * MI ) ) { case <STR_LIT> :: DoubleWordAccess : AlignMask = <NUM_LIT> ; break ; case <STR_LIT> :: WordAccess : AlignMask = <NUM_LIT> ; break ; case <STR_LIT> :: HalfWordAccess : AlignMask = <NUM_LIT> ; break ; case <STR_LIT> :: ByteAccess : AlignMask = <NUM_LIT> ; break ; default : return false ;


<s> EVT VT = Op . getValueType ( ) ; unsigned DivOp = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Div = DAG . getNode ( DivOp , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;

SDValue Mul = DAG . getNode ( <STR_LIT> , DL , VT , Div , Op . getOperand ( <NUM_LIT> ) ) ;


<s> } frame -> nregs = nregs ; if ( size == <NUM_LIT> && nregs == <NUM_LIT> ) { frame -> padding0 = <NUM_LIT> ; frame -> padding1 = frame -> padding2 = <NUM_LIT> ; frame -> frame_pointer_offset = frame -> to_allocate = <NUM_LIT> ; frame -> outgoing_arguments_size = <NUM_LIT> ; return ; } if ( ! frame -> push_rts ) offset += frame -> nregs * <NUM_LIT> ; if ( offset == <NUM_LIT> && size == <NUM_LIT> && crtl -> outgoing_args_size == <NUM_LIT> && ! crtl -> is_leaf ) frame -> padding0 = frame -> padding1 = <NUM_LIT> ; else if ( offset & <NUM_LIT> ) frame -> padding1 = <NUM_LIT> ; else frame -> padding1 = <NUM_LIT> ; offset += frame -> padding0 + frame -> padding1 ; frame -> frame_pointer_offset = offset ;


<s> MachineIRBuilder & Builder = Helper . MIRBuilder ; LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; LLT S8 = LLT :: scalar ( <NUM_LIT> ) ; auto CarryIn = Builder . buildNot ( S1 , MI . getOperand ( <NUM_LIT> ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { auto Sbc = Builder . buildInstr ( <STR_LIT> , { S8 , S1 , S1 , S1 , S1 } , { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) , CarryIn } ) ; Builder . setInsertPt ( Builder . getMBB ( ) , std :: next ( Builder . getInsertPt ( ) ) ) ; Builder . buildCopy ( MI . getOperand ( <NUM_LIT> ) , Sbc . getReg ( <NUM_LIT> ) ) ; Builder . buildNot ( MI . getOperand ( <NUM_LIT> ) , Sbc . getReg ( <NUM_LIT> ) ) ; } else { assert ( MI . getOpcode ( ) == <STR_LIT> ) ; auto Sbc = Builder . buildInstr ( <STR_LIT> , { S8 , S1 , S1 , S1 , S1 } , { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) , CarryIn } ) ; Builder . setInsertPt ( Builder . getMBB ( ) , std :: next ( Builder . getInsertPt ( ) ) ) ; Builder . buildCopy ( MI . getOperand ( <NUM_LIT> ) , Sbc . getReg ( <NUM_LIT> ) ) ;


<s> auto Res = MaxPressure ; MaxPressure . clear ( ) ;


<s> Op -> Shifter . Val = <STR_LIT> ( ShOp , Val ) ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ;


<s> void rs6000_function_arg_advance ( cumulative_args_t cum , const function_arg_info & arg ) { rs6000_function_arg_advance_1 ( get_cumulative_args ( cum ) , arg . mode , arg . type , arg . named , <NUM_LIT> ) ;


<s> <ISA_LIT>TTI ( ) : ImmutablePass ( ID ) , TM ( <NUM_LIT> ) , ST ( <NUM_LIT> ) , TLI ( <NUM_LIT> ) {


<s> } MachineOperand & Base = Ldst . getOperand ( BasePos ) ; MachineOperand & Offset = Ldst . getOperand ( OffsetPos ) ; assert ( Base . isReg ( ) && <STR_LIT> ) ; if ( ! Offset . isImm ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } Register B = Base . getReg ( ) ; if ( Register :: isStackSlot ( B ) || ! Register :: isVirtualRegister ( B ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } for ( auto & Add : MRI -> use_nodbg_instructions ( B ) ) { int64_t Incr ; if ( ! isAddConstantOp ( Add , Incr ) ) continue ; if ( ! isValidLoadStoreOffset ( Incr ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > Uses ; MachineInstr * MoveTo = canJoinInstructions ( & Ldst , & Add , & Uses ) ; if ( ! MoveTo ) continue ; if ( ! canFixPastUses ( Uses , Add . getOperand ( <NUM_LIT> ) , B ) ) continue ; LLVM_DEBUG ( MachineInstr * First = & Ldst ; MachineInstr * Last = & Add ; if ( MDT -> dominates ( Last , First ) ) std :: swap ( First , Last ) ; dbgs ( ) << <STR_LIT> << * First << <STR_LIT> << * Last << <STR_LIT> ;


<s> void prepare_move_operands ( rtx * operands , enum machine_mode mode ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && ! reg_or_0_operand ( operands [ <NUM_LIT> ] , mode ) ) operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ;


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * Info = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( Info ) ;


<s> } std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy ) ; InstructionCost Cost = <NUM_LIT> ; if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_PermuteTwoSrc , SrcVTy , None , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_PermuteTwoSrc , MaskTy , None , <NUM_LIT> , nullptr ) ; else if ( LT . first * LT . second . getVectorNumElements ( ) > NumElem ) { auto * NewMaskTy = FixedVectorType :: get ( MaskTy -> getElementType ( ) , LT . second . getVectorNumElements ( ) ) ; Cost += getShuffleCost ( TTI :: SK_InsertSubvector , NewMaskTy , None , <NUM_LIT> , MaskTy ) ;


<s> for ( unsigned I = S , E = VecRed . getNumOperands ( ) ; I < E ; I ++ ) Ops . push_back ( VecRed -> getOperand ( I ) ) ; SDValue Red = DAG . getNode ( OpcodeA , dl , DAG . getVTList ( { <STR_LIT> , <STR_LIT> } ) , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Red , SDValue ( Red . getNode ( ) , <NUM_LIT> ) ) ; } ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N0 , N1 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ; if ( SDValue M = MakeVecReduce ( <STR_LIT> , <STR_LIT> , N1 , N0 ) ) return M ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> Value * Index = GEPToVectorIndex ( GEP ) ; if ( ! Index ) { DEBUG ( dbgs ( ) << <STR_LIT> << * GEP << '\n' ) ; return false ; } GEPVectorIdx [ GEP ] = Index ; for ( User * GEPUser : AllocaUser -> users ( ) ) { if ( ! canVectorizeInst ( cast < Instruction > ( GEPUser ) , AllocaUser ) ) return false ; WorkList . push_back ( GEPUser ) ; } } VectorType * VectorTy = arrayTypeToVecType ( AllocaTy ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * AllocaTy << <STR_LIT> << * VectorTy << '\n' ) ; for ( Value * V : WorkList ) { Instruction * Inst = cast < Instruction > ( V ) ; IRBuilder < > Builder ( Inst ) ; switch ( Inst -> getOpcode ( ) ) { case Instruction :: Load : { Type * VecPtrTy = VectorTy -> getPointerTo ( AS . PRIVATE_ADDRESS ) ; Value * Ptr = cast < LoadInst > ( Inst ) -> getPointerOperand ( ) ; Value * Index = calculateVectorIndex ( Ptr , GEPVectorIdx ) ; Value * BitCast = Builder . CreateBitCast ( Alloca , VecPtrTy ) ; Value * VecValue = Builder . CreateLoad ( BitCast ) ; Value * ExtractElement = Builder . CreateExtractElement ( VecValue , Index ) ; Inst -> replaceAllUsesWith ( ExtractElement ) ; Inst -> eraseFromParent ( ) ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; int DstIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: dst ) ; assert ( DstIdx != - <NUM_LIT> ) ; unsigned DstRCID = get ( MI -> getOpcode ( ) ) . OpInfo [ DstIdx ] . RegClass ; switch ( RI . getRegClass ( DstRCID ) -> getSize ( ) ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : { unsigned NewOpcode = getVALUOp ( * MI ) ; unsigned RegOffset ; unsigned ImmOffset ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { RegOffset = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ImmOffset = <NUM_LIT> ; } else { assert ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; ImmOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MBB -> getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS ) ImmOffset <<= <NUM_LIT> ; RegOffset = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( isUInt < <NUM_LIT> > ( ImmOffset ) ) { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , RegOffset ) . addImm ( ImmOffset ) ; ImmOffset = <NUM_LIT> ; } } unsigned SRsrc = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord0 = RegOffset ; unsigned DWord1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned DWord3 = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint64_t RsrcDataFormat = getDefaultRsrcDataFormat ( ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord2 ) . addImm ( RsrcDataFormat & <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DWord3 ) . addImm ( RsrcDataFormat >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , SRsrc ) . addReg ( DWord0 ) . addImm ( <STR_LIT> ) . addReg ( DWord1 ) . addImm ( <STR_LIT> ) . addReg ( DWord2 ) . addImm ( <STR_LIT> ) . addReg ( DWord3 ) . addImm ( <STR_LIT> ) ;

const MCInstrDesc & NewInstDesc = get ( NewOpcode ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> void tilegx_expand_smuldi3_highpart ( rtx op0 , rtx op1 , rtx op2 ) { tilegx_expand_high_multiply ( op0 , op1 , op2 , true ) ;


<s> auto OpcodeTriple = getMinMaxPair ( MI . getOpcode ( ) ) ; Register Val ; Optional < FPValueAndVReg > K0 , K1 ; if ( ! matchMed < GFCstOrSplatGFCstMatch > ( MI , MRI , OpcodeTriple , Val , K0 , K1 ) ) return false ; if ( ! K0 -> Value . isExactlyValue ( <NUM_LIT> ) || ! K1 -> Value . isExactlyValue ( <NUM_LIT> ) ) return false ; if ( ( getIEEE ( ) && getDX10Clamp ( ) && isFminnumIeee ( MI ) && isKnownNeverSNaN ( Val , MRI ) ) || isKnownNeverNaN ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ) { Reg = Val ; return true ;


<s> if ( Slot == - <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , Slot , S , <ISA_LIT>Operand :: ImmTyInterpSlot ) ) ;


<s> EmitAlignment ( <NUM_LIT> , F ) ; O << <STR_LIT> << CurrentFnName << '\n' ; O << <STR_LIT> << CurrentFnName << '\n' ; printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; if ( ( TAI -> hasDotTypeDotSizeDirective ( ) ) && Subtarget -> isLinux ( ) ) O << <STR_LIT> << CurrentFnName << <STR_LIT> ; O << CurrentFnName << <STR_LIT> ; emitFrameDirective ( MF ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue ReturnAddress ; if ( Depth ) { SDNodeFlags Flags ; Flags . setNoUnsignedWrap ( true ) ; SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ReturnAddress = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } else { unsigned Reg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ReturnAddress = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , VT ) ; } if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , ReturnAddress , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ; else if ( Subtarget -> isTargetDarwin ( ) ) return ReturnAddress ; SDNode * St ; if ( Subtarget -> hasV8_3aOps ( ) ) { St = DAG . getMachineNode ( <STR_LIT> , DL , VT , ReturnAddress ) ; } else { SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , ReturnAddress ) ; St = DAG . getMachineNode ( <STR_LIT> , DL , VT , Chain ) ;


<s> DAG . computeKnownBits ( Value , KnownZero , KnownOne ) ;

return KnownZero . countTrailingOnes ( ) >= <NUM_LIT> ;


<s> MachineRegisterInfo * MRI = & MF -> getRegInfo ( ) ; MachineConstantPool * MCP = MF -> getConstantPool ( ) ; <ISA_LIT>FunctionInfo * AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; const Function * F = MF -> getFunction ( ) ; bool isThumb = Subtarget -> isThumb ( ) ; bool isThumb2 = Subtarget -> isThumb2 ( ) ; unsigned PCLabelId = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = ( isThumb || isThumb2 ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolMBB :: Create ( F -> getContext ( ) , DispatchBB , PCLabelId , PCAdj ) ; unsigned CPI = MCP -> getConstantPoolIndex ( CPV , <NUM_LIT> ) ; const TargetRegisterClass * TRC = isThumb ? & <STR_LIT> : & <STR_LIT> ; MachineMemOperand * CPMMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * MF ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; MachineMemOperand * FIMMOSt = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( isThumb2 ) { unsigned NewVReg1 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg1 ) . addConstantPoolIndex ( CPI ) . addMemOperand ( CPMMO ) ) ; unsigned NewVReg2 = MRI -> createVirtualRegister ( TRC ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg2 ) . addReg ( NewVReg1 , RegState :: Kill ) . addImm ( <NUM_LIT> ) ) ) ; unsigned NewVReg3 = MRI -> createVirtualRegister ( TRC ) ; BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) , NewVReg3 ) . addReg ( NewVReg2 , RegState :: Kill ) . addImm ( PCLabelId ) ;

AddDefaultPred ( BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( NewVReg3 , RegState :: Kill ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( FIMMOSt ) ) ;


<s> unsigned ConstTripCount = SE . getSmallConstantTripCount ( L ) ; if ( ConstTripCount && ConstTripCount < SmallCTRLoopThreshold ) { SmallPtrSet < const Value * , <NUM_LIT> > EphValues ; CodeMetrics :: collectEphemeralValues ( L , & AC , EphValues ) ; CodeMetrics Metrics ; for ( BasicBlock * BB : L -> blocks ( ) ) Metrics . analyzeBasicBlock ( BB , * this , EphValues ) ; if ( Metrics . NumInsts <= ( <NUM_LIT> * SchedModel . getIssueWidth ( ) ) ) return false ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , IE = L -> block_end ( ) ; I != IE ; ++ I ) if ( mightUseCTR ( * I , LibInfo ) ) return false ; SmallVector < BasicBlock * , <NUM_LIT> > ExitingBlocks ; L -> getExitingBlocks ( ExitingBlocks ) ; for ( auto & BB : ExitingBlocks ) { Instruction * TI = BB -> getTerminator ( ) ;


<s> for ( i = which = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned char e = d . perm [ i ] ; gcc_assert ( e < <NUM_LIT> * nelt ) ; which |= ( e < nelt ? <NUM_LIT> : <NUM_LIT> ) ; } if ( which == <NUM_LIT> ) for ( i = <NUM_LIT> ; i < nelt ; ++ i ) d . perm [ i ] -= nelt ; d . one_vector_p = ( which != <NUM_LIT> ) ; d . target = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; d . op1 = d . op0 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; if ( ! d . one_vector_p ) d . op1 = gen_raw_REG ( d . vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; start_sequence ( ) ; ret = aarch64_expand_vec_perm_const_1 ( & d ) ;


<s> static const MCPhysReg * GetFPR ( ) { static const MCPhysReg FPR [ ] = {


<s> if ( res != target ) emit_move_insn ( target , res ) ; return ; } else if ( all_ones_operand ( negop , target_mode ) ) { rtx res = expand_simple_binop ( cmp_mode , ASHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , <NUM_LIT> , OPTAB_DIRECT ) ; if ( res != target ) emit_move_insn ( target , res ) ; return ; } } result_mode = related_int_vector_mode ( cmp_mode ) . require ( ) ; result_target = gen_reg_rtx ( result_mode ) ; if ( ! REG_P ( cmp_op1 ) ) cmp_op1 = force_reg ( GET_MODE ( cmp_op1 ) , cmp_op1 ) ; s390_expand_vec_compare ( result_target , cond , cmp_op1 , cmp_op2 ) ; if ( all_ones_operand ( then , GET_MODE ( then ) ) && const0_operand ( els , GET_MODE ( els ) ) ) { emit_move_insn ( target , gen_rtx_SUBREG ( target_mode , result_target , <NUM_LIT> ) ) ; return ; } if ( ! REG_P ( then ) ) then = force_reg ( target_mode , then ) ;

if ( ! REG_P ( els ) ) els = force_reg ( target_mode , els ) ;


<s> default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> void <ISA_LIT>LegalizerInfo :: setLegalizerInfoSSE2 ( ) { if ( ! Subtarget . hasSSE2 ( ) ) return ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ;

const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ;