<s> if ( TREE_CODE ( TREE_TYPE ( node ) ) == METHOD_TYPE && ( DECL_CONSTRUCTOR_P ( node ) || DECL_DESTRUCTOR_P ( node ) ) ) { tree overload ; for ( overload = OVL_CHAIN ( node ) ; overload ; overload = OVL_CHAIN ( overload ) ) { tree node_args ; tree func_args ; tree function = OVL_CURRENT ( overload ) ; if ( ! function || ! DECL_P ( function ) || ( DECL_CONSTRUCTOR_P ( node ) && ! DECL_CONSTRUCTOR_P ( function ) ) || ( DECL_DESTRUCTOR_P ( node ) && ! DECL_DESTRUCTOR_P ( function ) ) ) continue ; for ( node_args = DECL_ARGUMENTS ( node ) , func_args = DECL_ARGUMENTS ( function ) ; node_args && func_args ; node_args = TREE_CHAIN ( node_args ) , func_args = TREE_CHAIN ( func_args ) ) if ( TREE_TYPE ( node_args ) != TREE_TYPE ( func_args ) ) break ; if ( node_args || func_args ) { if ( ( node_args == NULL_TREE || func_args != NULL_TREE ) && strcmp ( IDENTIFIER_POINTER ( DECL_NAME ( node ) ) , <STR_LIT> ) != <NUM_LIT> ) continue ; } symbian_add_attribute ( function , attr ) ; for ( thunk = DECL_THUNKS ( function ) ; thunk ; thunk = TREE_CHAIN ( thunk ) ) if ( TREE_CODE ( thunk ) == FUNCTION_DECL ) symbian_add_attribute ( thunk , attr ) ; } } if ( TREE_CODE ( node ) == FUNCTION_DECL && DECL_VIRTUAL_P ( node ) ) { for ( thunk = DECL_THUNKS ( node ) ; thunk ; thunk = TREE_CHAIN ( thunk ) ) if ( TREE_CODE ( thunk ) == FUNCTION_DECL ) symbian_add_attribute ( thunk , attr ) ; } if ( ! TREE_PUBLIC ( node ) && ( TREE_CODE ( node ) == VAR_DECL || TREE_CODE ( node ) == FUNCTION_DECL ) ) { error ( <STR_LIT> , node , IDENTIFIER_POINTER ( name ) ) ;


<s> <ISA_LIT>FunctionInfo & AFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( const MachineBasicBlock & MBB : MF ) { memset ( LOHInfos , <NUM_LIT> , sizeof ( LOHInfos ) ) ; for ( const MachineBasicBlock * Succ : MBB . successors ( ) ) { for ( const auto & LI : Succ -> liveins ( ) ) { int RegIdx = mapRegToGPRIndex ( LI . PhysReg ) ; if ( RegIdx >= <NUM_LIT> ) LOHInfos [ RegIdx ] . OneUser = true ; } } for ( const MachineInstr & MI : make_range ( MBB . rbegin ( ) , MBB . rend ( ) ) ) {


<s> int64_t Offset = <NUM_LIT> ; for ( int I = MFI . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) Offset = std :: max ( Offset , - MFI . getObjectOffset ( I ) ) ; for ( const MCPhysReg * R = TRI . getCalleeSavedRegs ( & MF ) ; * R ; ++ R ) { unsigned Size = TRI . getSpillSize ( * TRI . getMinimalPhysRegClass ( * R ) ) ; Offset = alignTo ( Offset + Size , Size ) ; } unsigned MaxAlign = MFI . getMaxAlignment ( ) ; assert ( ! MFI . getObjectIndexEnd ( ) || MaxAlign ) ; for ( unsigned I = <NUM_LIT> , E = MFI . getObjectIndexEnd ( ) ; I != E ; ++ I ) Offset = alignTo ( Offset + MFI . getObjectSize ( I ) , MaxAlign ) ; if ( MFI . adjustsStack ( ) && hasReservedCallFrame ( MF ) ) Offset = alignTo ( Offset + MFI . getMaxCallFrameSize ( ) , std :: max ( MaxAlign , getStackAlignment ( ) ) ) ;

return alignTo ( Offset , getStackAlignment ( ) ) ;


<s> if ( ! isInt < <NUM_LIT> > ( Imm ) ) { Shift = countTrailingZeros < uint64_t > ( Imm ) ; int64_t ImmSh = static_cast < uint64_t > ( Imm ) >> Shift ; if ( isInt < <NUM_LIT> > ( ImmSh ) ) { Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; }


<s> static MCStreamer * createELFStreamer ( const Triple & T , MCContext & Ctx , MCAsmBackend & MAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) { return create<ISA_LIT>ELFStreamer ( Ctx , MAB , OS , Emitter , false , T . getArch ( ) == Triple :: thumb ) ;


<s> RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;


<s> if ( insn -> consumedDisplacement ) return <NUM_LIT> ; insn -> consumedDisplacement = TRUE ; insn -> displacementOffset = insn -> readerCursor - insn -> startLocation ; switch ( insn -> eaDisplacement ) { case EA_DISP_NONE : insn -> consumedDisplacement = FALSE ; break ; case EA_DISP_8 : if ( consumeInt8 ( insn , & d8 ) ) return - <NUM_LIT> ; insn -> displacement = d8 ; break ; case EA_DISP_16 : if ( consumeInt16 ( insn , & d16 ) ) return - <NUM_LIT> ; insn -> displacement = d16 ; break ; case EA_DISP_32 : if ( consumeInt32 ( insn , & d32 ) ) return - <NUM_LIT> ;


<s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , TargetTriple ( TM -> getTargetTriple ( ) ) , ST ( static_cast < const GCNSubtarget * > ( TM -> getSubtargetImpl ( F ) ) ) , TLI ( ST -> getTargetLowering ( ) ) {


<s> virtual const TargetData * getTargetData ( ) const {


<s> if ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && TARGET_MINIMAL_TOC && ! TARGET_RELOCATABLE ) { if ( ! toc_initialized ) { toc_initialized = <NUM_LIT> ; fprintf ( asm_out_file , <STR_LIT> , TOC_SECTION_ASM_OP ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , <NUM_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( asm_out_file , <STR_LIT> ) ; ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , MINIMAL_TOC_SECTION_ASM_OP ) ; ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; } else fprintf ( asm_out_file , <STR_LIT> , MINIMAL_TOC_SECTION_ASM_OP ) ; } else if ( ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) && ! TARGET_RELOCATABLE ) fprintf ( asm_out_file , <STR_LIT> , TOC_SECTION_ASM_OP ) ; else { fprintf ( asm_out_file , <STR_LIT> , MINIMAL_TOC_SECTION_ASM_OP ) ; if ( ! toc_initialized ) { ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; toc_initialized = <NUM_LIT> ; } }


<s> assert ( ( Imm & <NUM_LIT> ) == Imm && <STR_LIT> ) ; switch ( Imm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> void setLastInArgFI ( int FI ) { InArgFIRange . second = FI ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static int s390_split_branches ( void ) { rtx temp_reg = gen_rtx_REG ( Pmode , RETURN_REGNUM ) ; int new_literal = <NUM_LIT> , ret ; rtx insn , pat , tmp , target ; rtx * label ; shorten_branches ( get_insns ( ) ) ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( GET_CODE ( insn ) != JUMP_INSN ) continue ; pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL && XVECLEN ( pat , <NUM_LIT> ) > <NUM_LIT> ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( pat ) != SET || SET_DEST ( pat ) != pc_rtx ) continue ; if ( GET_CODE ( SET_SRC ( pat ) ) == LABEL_REF ) { label = & SET_SRC ( pat ) ; } else if ( GET_CODE ( SET_SRC ( pat ) ) == IF_THEN_ELSE ) { if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ) == LABEL_REF ) label = & XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; else if ( GET_CODE ( XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ) == LABEL_REF ) label = & XEXP ( SET_SRC ( pat ) , <NUM_LIT> ) ; else continue ; } else continue ; if ( get_attr_length ( insn ) <= <NUM_LIT> ) continue ; cfun_frame_layout . save_return_addr_p = <NUM_LIT> ; if ( ! flag_pic ) { new_literal = <NUM_LIT> ; tmp = force_const_mem ( Pmode , * label ) ; tmp = emit_insn_before ( gen_rtx_SET ( Pmode , temp_reg , tmp ) , insn ) ; INSN_ADDRESSES_NEW ( tmp , - <NUM_LIT> ) ; annotate_constant_pool_refs ( & PATTERN ( tmp ) ) ; target = temp_reg ; } else { new_literal = <NUM_LIT> ; target = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , * label ) , UNSPEC_LTREL_OFFSET ) ; target = gen_rtx_CONST ( Pmode , target ) ; target = force_const_mem ( Pmode , target ) ; tmp = emit_insn_before ( gen_rtx_SET ( Pmode , temp_reg , target ) , insn ) ; INSN_ADDRESSES_NEW ( tmp , - <NUM_LIT> ) ; annotate_constant_pool_refs ( & PATTERN ( tmp ) ) ; target = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , XEXP ( target , <NUM_LIT> ) , cfun -> machine -> base_reg ) , UNSPEC_LTREL_BASE ) ; target = gen_rtx_PLUS ( Pmode , temp_reg , target ) ;


<s> static MachineBasicBlock :: iterator getEarliestInsertPos ( MachineBasicBlock * MBB , const SmallPtrSet < const MachineInstr * , <NUM_LIT> > & BeforeSet , const SmallPtrSet < const MachineInstr * , <NUM_LIT> > & AfterSet ) { auto InsertPos = MBB -> end ( ) ; while ( InsertPos != MBB -> begin ( ) ) { if ( BeforeSet . count ( & * std :: prev ( InsertPos ) ) ) { for ( auto Pos = InsertPos , E = MBB -> begin ( ) ; Pos != E ; -- Pos ) assert ( ! AfterSet . count ( & * std :: prev ( Pos ) ) ) ; break ; }


<s> MCELFStreamer * llvm :: create<ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , bool RelaxAll ) { <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) ;

if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ;


<s> if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return * RM ;


<s> assert ( Op . getValueType ( ) == <STR_LIT> && Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;

SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Zero , Zero , LHS , RHS ) ;


<s> CopyPropagation ( DataFlowGraph & dfg ) : MDT ( dfg . getDT ( ) ) , DFG ( dfg ) , L ( dfg . getMF ( ) . getRegInfo ( ) , dfg ) {


<s> void <ISA_LIT>MachineFunctionInfo :: anchor ( ) {


<s> void addu5_0ImmOperands ( MCInst & Inst , unsigned N ) const {


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


<s> } poly_int64 offset2 = cfun -> machine -> frame . reg_offset [ regno2 ] ; if ( aarch64_sve_mode_p ( mode ) || ! satisfies_constraint_Ump ( mem ) || GP_REGNUM_P ( regno ) != GP_REGNUM_P ( regno2 ) || ( crtl -> abi -> id ( ) == ARM_PCS_SIMD && FP_REGNUM_P ( regno ) ) || maybe_ne ( ( offset2 - cfun -> machine -> frame . reg_offset [ regno ] ) , GET_MODE_SIZE ( mode ) ) ) { insn = emit_insn ( set ) ; if ( frame_related_p ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( prologue_p ) add_reg_note ( insn , REG_CFA_OFFSET , copy_rtx ( set ) ) ; else add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; } regno = regno2 ; continue ; } bool frame_related2_p = aarch64_emit_cfi_for_reg_p ( regno2 ) ; rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; if ( frame_pointer_needed ) offset2 -= cfun -> machine -> frame . below_hard_fp_saved_regs_size ; else offset2 += crtl -> outgoing_args_size ; rtx addr2 = plus_constant ( Pmode , ptr_reg , offset2 ) ; rtx mem2 = gen_frame_mem ( mode , addr2 ) ; rtx set2 = prologue_p ? gen_rtx_SET ( mem2 , reg2 ) : gen_rtx_SET ( reg2 , mem2 ) ; if ( prologue_p ) insn = emit_insn ( aarch64_gen_store_pair ( mode , mem , reg , mem2 , reg2 ) ) ; else insn = emit_insn ( aarch64_gen_load_pair ( mode , reg , mem , reg2 , mem2 ) ) ; if ( frame_related_p || frame_related2_p ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( prologue_p ) { if ( frame_related_p ) add_reg_note ( insn , REG_CFA_OFFSET , set ) ; if ( frame_related2_p ) add_reg_note ( insn , REG_CFA_OFFSET , set2 ) ; } else { if ( frame_related_p ) add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; if ( frame_related2_p ) add_reg_note ( insn , REG_CFA_RESTORE , reg2 ) ; }


insertPass ( & MachineSchedulerID , & <ISA_LIT>LoadStoreOptimizerID ) ;


<s> CONSTEXPR svst234_impl ( unsigned int vectors_per_tuple ) : full_width_access ( vectors_per_tuple ) {


<s> Parser . Lex ( ) ; SMLoc RBracS = getLoc ( ) ; if ( parseOptionalToken ( AsmToken :: RBrac ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , LBracS , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , IntS , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , RBracS , getContext ( ) ) ) ; return false ; } } } } return false ;


<s> const MCOperandInfo & MOI = this -> MII . get ( MI -> getOpcode ( ) ) . OpInfo [ OpNo ] ; if ( Op . isReg ( ) ) { bool isPtrReg = ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) ; if ( isPtrReg ) { O << getRegisterName ( Op . getReg ( ) , <STR_LIT> ) ; } else { O << getPrettyRegisterName ( Op . getReg ( ) , MRI ) ; } } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ;


<s> const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ? & <STR_LIT> :

( RC == & <STR_LIT> ? & <STR_LIT> : RC ) ) ;


<s> assert ( isParsingInlineAsm ( ) && <STR_LIT> ) ; Val = nullptr ; StringRef LineBuf ( Identifier . data ( ) ) ; void * Result = SemaCallback -> LookupInlineAsmIdentifier ( LineBuf , Info , IsUnevaluatedOperand ) ; const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Loc = Tok . getLoc ( ) ; const char * EndPtr = Tok . getLoc ( ) . getPointer ( ) + LineBuf . size ( ) ; while ( true ) { End = Tok . getEndLoc ( ) ; getLexer ( ) . Lex ( ) ;

assert ( End . getPointer ( ) <= EndPtr && <STR_LIT> ) ;


<s> SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( ! Subtarget . hasDQI ( ) || SrcVT != <STR_LIT> || Subtarget . is64Bit ( ) || ( VT != <STR_LIT> && VT != <STR_LIT> ) ) return SDValue ( ) ; unsigned NumElts = Subtarget . hasVLX ( ) ? <NUM_LIT> : <NUM_LIT> ;

MVT VecInVT = <STR_LIT> ( <STR_LIT> , NumElts ) ;


<s> if ( Subtarget . isCortexA8 ( ) && ( DDomain == <STR_LIT> || UDomain == <STR_LIT> ) ) return true ; int Latency = computeOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ; if ( Latency < <NUM_LIT> ) Latency = getInstrLatency ( ItinData , DefMI ) ; if ( Latency <= <NUM_LIT> ) return false ;

return DDomain == <STR_LIT> || DDomain == <STR_LIT> || UDomain == <STR_LIT> || UDomain == <STR_LIT> ;


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > Operands ; OperandMatchResultTy ResTy = ParseAnyRegister ( Operands ) ; if ( ResTy == MatchOperand_Success ) { assert ( Operands . size ( ) == <NUM_LIT> ) ; <ISA_LIT>Operand & Operand = static_cast < <ISA_LIT>Operand & > ( * Operands . front ( ) ) ; StartLoc = Operand . getStartLoc ( ) ; EndLoc = Operand . getEndLoc ( ) ; if ( Operand . isGPRAsmReg ( ) ) { RegNo = isGP64bit ( ) ? Operand . getGPR64Reg ( ) : Operand . getGPR32Reg ( ) ;


<s> return __builtin_mve_vshlq_m_n_sv4si ( __arm_vuninitializedq_s32 ( ) , __a , __imm , __p ) ;


<s> return true ; } if ( isCallIndirect ( MI . getOpcode ( ) ) ) return true ; if ( ! MI . isCall ( ) ) return false ; const MachineOperand & MO = getCalleeOp ( MI ) ; assert ( MO . isGlobal ( ) || MO . isSymbol ( ) ) ; if ( MO . isSymbol ( ) ) { const char * Name = MO . getSymbolName ( ) ; if ( strcmp ( Name , <STR_LIT> ) == <NUM_LIT> || strcmp ( Name , <STR_LIT> ) == <NUM_LIT> || strcmp ( Name , <STR_LIT> ) == <NUM_LIT> ) return false ; return true ;


<s> if ( mode != BLKmode ) size = GET_MODE_SIZE ( mode ) ;

else size = int_size_in_bytes ( type ) ;


<s> bool Filler :: searchRange ( MachineBasicBlock & MBB , IterTy Begin , IterTy End , RegDefsUses & RegDU , InspectMemInstr & IM , Iter Slot , IterTy & Filler ) const { bool IsReverseIter = std :: is_convertible < IterTy , ReverseIter > :: value ; for ( IterTy I = Begin ; I != End ; ) { IterTy CurrI = I ; ++ I ; if ( CurrI -> isDebugValue ( ) ) continue ; if ( terminateSearch ( * CurrI ) ) break ; assert ( ( ! CurrI -> isCall ( ) && ! CurrI -> isReturn ( ) && ! CurrI -> isBranch ( ) ) && <STR_LIT> ) ; if ( CurrI -> isKill ( ) ) { CurrI -> eraseFromParent ( ) ; if ( IsReverseIter && I != End ) I = CurrI ; continue ; } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; }

bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ;


<s> } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; Register IgnoredFrameReg ; Offset = TFL -> getFrameIndexReference ( MF , - <NUM_LIT> , IgnoredFrameReg ) . getFixed ( ) ; return getIndirectIndexBegin ( MF ) + Offset ;


<s> const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( STI . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( ! CSI . empty ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ;


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( MachineInstr * MI ) const { unsigned Opcode = MI -> getOpcode ( ) ; if ( TM . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) && getConditionalMove ( Opcode ) ) return true ;


<s> const DataLayout * getDataLayout ( ) const override {


<s> } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ) return Result ; if ( SDValue Result = PerformORCombineToSMULWBT ( N , DCI , Subtarget ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; APInt SplatBits0 , SplatBits1 ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) {

if ( SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) && SplatBits0 == ~ SplatBits1 ) {


<s> if ( ! SCEVPtr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return INVALID_SCEV ; } const SCEVAddRecExpr * AddRec = dyn_cast < SCEVAddRecExpr > ( SCEVPtr ) ; if ( ! AddRec || ! AddRec -> isAffine ( ) ) return INT_MAX ; const SCEV * Step = AddRec -> getStepRecurrence ( * SE ) ; unsigned UnrollCount = getLoopUnrollCount ( L ) ; if ( UnrollCount ) return ( UnrollCount * std :: abs ( cast < SCEVConstant > ( Step ) -> getValue ( ) -> getSExtValue ( ) ) ) ; else return ( std :: abs ( cast < SCEVConstant > ( Step ) -> getValue ( ) -> getSExtValue ( ) ) ) ;


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups , STI ) << <NUM_LIT> ; unsigned OffBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) ;

return ( OffBits & <NUM_LIT> ) | RegBits ;


<s> else if ( CONST_INT_P ( y_hi ) ) insn = emit_insn ( gen_cmpsi3_imm_carryin_CC_NVout ( scratch , x_hi , y_hi , cmp1 ) ) ; else insn = emit_insn ( gen_cmpsi3_carryin_CC_NVout ( scratch , x_hi , y_hi , cmp1 ) ) ; return SET_DEST ( single_set ( insn ) ) ; } case LE : case GT : { gcc_assert ( arm_const_double_prefer_rsbs_rsc ( y ) ) ; if ( ! const_ok_for_arm ( INTVAL ( y_lo ) ) ) y_lo = force_reg ( SImode , y_lo ) ; rtx cmp1 = gen_rtx_LTU ( DImode , arm_gen_compare_reg ( LTU , y_lo , x_lo , scratch ) , const0_rtx ) ; rtx_insn * insn = emit_insn ( gen_rscsi3_CC_NVout_scratch ( scratch , y_hi , x_hi , cmp1 ) ) ; return SET_DEST ( single_set ( insn ) ) ; } case LTU : case GEU : { if ( y_lo == const0_rtx ) { if ( ! arm_add_operand ( y_hi , SImode ) ) y_hi = force_reg ( SImode , y_hi ) ; return arm_gen_compare_reg ( code , x_hi , y_hi , NULL_RTX ) ; } if ( ! arm_add_operand ( y_lo , SImode ) ) y_lo = force_reg ( SImode , y_lo ) ; rtx cmp1 = gen_rtx_LTU ( DImode , arm_gen_compare_reg ( LTU , x_lo , y_lo , NULL_RTX ) , const0_rtx ) ; if ( ! scratch ) scratch = gen_rtx_SCRATCH ( SImode ) ; if ( ! arm_not_operand ( y_hi , SImode ) ) y_hi = force_reg ( SImode , y_hi ) ; rtx_insn * insn ; if ( y_hi == const0_rtx ) insn = emit_insn ( gen_cmpsi3_0_carryin_CC_Bout ( scratch , x_hi , cmp1 ) ) ; else if ( CONST_INT_P ( y_hi ) ) { y_hi = GEN_INT ( UINTVAL ( y_hi ) & <NUM_LIT> ) ; insn = emit_insn ( gen_cmpsi3_imm_carryin_CC_Bout ( scratch , x_hi , y_hi , cmp1 ) ) ; } else insn = emit_insn ( gen_cmpsi3_carryin_CC_Bout ( scratch , x_hi , y_hi , cmp1 ) ) ; return SET_DEST ( single_set ( insn ) ) ; } case LEU : case GTU : { gcc_assert ( arm_const_double_prefer_rsbs_rsc ( y ) ) ; if ( ! const_ok_for_arm ( INTVAL ( y_lo ) ) ) y_lo = force_reg ( SImode , y_lo ) ;


<s> <ISA_LIT>Operand ( KindTy K ) : MCParsedAsmOperand ( ) , Kind ( K ) {


<s> if ( TARGET_DEBUG_STACK ) debug_stack_info ( info ) ; if ( info -> first_fp_reg_save < <NUM_LIT> && ! TARGET_MACHO && ! TARGET_ELF ) { char * name ; int regno = info -> first_fp_reg_save - <NUM_LIT> ; if ( ( info -> savres_strategy & SAVE_INLINE_FPRS ) == <NUM_LIT> ) { bool lr = ( info -> savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR ) != <NUM_LIT> ; int sel = SAVRES_SAVE | SAVRES_FPR | ( lr ? SAVRES_LR : <NUM_LIT> ) ; name = rs6000_savres_routine_name ( regno , sel ) ;


<s> bool empty_p ( ) const { return m_state == EMPTY || m_state == HARD_EMPTY ;


<s> debug ( <STR_LIT> ) ; return true ; } mcInst . setOpcode ( insn . instructionID ) ; int index ; insn . numImmediatesTranslated = <NUM_LIT> ; for ( index = <NUM_LIT> ; index < <ISA_LIT>_MAX_OPERANDS ; ++ index ) { if ( insn . operands [ index ] . encoding != ENCODING_NONE ) { if ( translateOperand ( mcInst , insn . operands [ index ] , insn , Dis ) ) { return true ; } } }


<s> uint64_t OriginalValue = CE -> getValue ( ) ;

uint64_t InvertedValue = OriginalValue ^ ( ( ( uint64_t ) <NUM_LIT> << size ) - <NUM_LIT> ) ;


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ;

return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPUName , FS ) ;


<s> return StringRef ( Tok . Data , Tok . Length ) ;


<s> <ISA_LIT>MachObjectWriter ( uint32_t CPUType , uint32_t CPUSubtype ) : MCMachObjectTargetWriter ( true , CPUType , CPUSubtype , true ) {


<s> FixupBWInstPass ( ) : MachineFunctionPass ( ID ) {


<s> return ( I == VGPRToAGPRSpills . end ( ) ) ? ( MCPhysReg ) <STR_LIT> : I -> second . Lanes [ Lane ] ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const {

OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ;


<s> bool V2IsZero = ! V2IsUndef && <STR_LIT> ( V2 . getNode ( ) ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> && ! Is1BitVector && canWidenShuffleElements ( OrigMask , Zeroable , V2IsZero , WidenedMask ) ) { if ( SDValue Broadcast = lowerShuffleAsBroadcast ( DL , VT , V1 , V2 , OrigMask , Subtarget , DAG ) ) return Broadcast ; MVT NewEltVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) : <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; int NewNumElts = NumElements / <NUM_LIT> ; MVT NewVT = <STR_LIT> ( NewEltVT , NewNumElts ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { if ( V2IsZero ) { bool UsedZeroVector = false ; assert ( is_contained ( WidenedMask , SM_SentinelZero ) && <STR_LIT> ) ; for ( int i = <NUM_LIT> ; i != NewNumElts ; ++ i ) if ( WidenedMask [ i ] == SM_SentinelZero ) { WidenedMask [ i ] = i + NewNumElts ; UsedZeroVector = true ; } if ( UsedZeroVector ) V2 = getZeroVector ( NewVT , Subtarget , DAG , DL ) ; } V1 = DAG . getBitcast ( NewVT , V1 ) ; V2 = DAG . getBitcast ( NewVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( NewVT , DL , V1 , V2 , WidenedMask ) ) ; } } SmallVector < SDValue > Ops = { V1 , V2 } ; SmallVector < int > Mask ( OrigMask . begin ( ) , OrigMask . end ( ) ) ; if ( SDValue HOp = canonicalizeShuffleMaskWithHorizOp ( Ops , Mask , VT . getSizeInBits ( ) , DL , DAG , Subtarget ) ) return DAG . getBitcast ( VT , HOp ) ; V1 = DAG . getBitcast ( VT , Ops [ <NUM_LIT> ] ) ; V2 = DAG . getBitcast ( VT , Ops [ <NUM_LIT> ] ) ;

assert ( NumElements == ( int ) Mask . size ( ) && <STR_LIT> <STR_LIT> ) ;


<s> static DecodeStatus DecodeBranchTarget26 ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ;


<s> static DecodeStatus DecodeVST3LN ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rd = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; }


<s> if ( ! MI . mayLoadOrStore ( ) ) continue ; const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags ) ; if ( MemOpNo < <NUM_LIT> ) continue ; MemOpNo += <STR_LIT> ( Desc ) ; auto Insns = LEAs . find ( getMemOpKey ( MI , MemOpNo ) ) ; if ( Insns == LEAs . end ( ) ) continue ; MachineInstr * DefMI ; int64_t AddrDispShift ; int Dist ; if ( ! chooseBestLEA ( Insns -> second , MI , DefMI , AddrDispShift , Dist ) ) continue ; if ( Dist < <NUM_LIT> ) { DefMI -> removeFromParent ( ) ; MBB -> insert ( MachineBasicBlock :: iterator ( & MI ) , DefMI ) ; InstrPos [ DefMI ] = InstrPos [ & MI ] - <NUM_LIT> ; assert ( ( ( InstrPos [ DefMI ] == <NUM_LIT> && MachineBasicBlock :: iterator ( DefMI ) == MBB -> begin ( ) ) || InstrPos [ DefMI ] > InstrPos [ & * std :: prev ( MachineBasicBlock :: iterator ( DefMI ) ) ] ) && <STR_LIT> ) ; } MRI -> clearKillFlags ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; ++ NumSubstLEAs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) , false ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToImmediate ( AddrDispShift ) ; MI . getOperand ( MemOpNo + <STR_LIT> ) . ChangeToRegister ( <STR_LIT> , false ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; Changed = true ; } return Changed ;


<s> unsigned Op1 , Op2 ; DecodeStatus S = Decode2OpInstruction ( Insn , Op1 , Op2 ) ; if ( S != MCDisassembler :: Success ) return Decode2OpInstructionFail ( Inst , Insn , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ;

DecodeBitpOperand ( Inst , Op2 , Address , Decoder ) ;


<s> * IsIndirectCall = false ; switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ;


<s> const MCSectionELF * Sec = Context . getELFSection ( <STR_LIT> , ELF :: SHT_MIPS_ABIFLAGS , ELF :: SHF_ALLOC , <NUM_LIT> , <STR_LIT> ) ; MCSectionData & ABIShndxSD = MCA . getOrCreateSectionData ( * Sec ) ;

ABIShndxSD . setAlignment ( <NUM_LIT> ) ;


<s> static int aapcs_select_call_coproc ( CUMULATIVE_ARGS * pcum , machine_mode mode , const_tree type ) { int i ;

for ( i = <NUM_LIT> ; i < ARM_NUM_COPROC_SLOTS ; i ++ ) if ( aapcs_cp_arg_layout [ i ] . is_call_candidate ( pcum , mode , type ) ) return i ;


<s> MachineMemOperand * ValueMMO = MF . getMachineMemOperand ( MachinePointerInfo :: getUnknownStack ( MF ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , Align ( ) ) ; Builder . buildLoad ( Dst , Addr , * ValueMMO ) ; auto NextAddr = Builder . buildPtrAdd ( P , Addr , Builder . buildConstant ( S16 , Size ) ) ; MachineMemOperand * AddrStoreMMO = MF . getMachineMemOperand ( MachinePointerInfo :: getUnknownStack ( MF ) , MachineMemOperand :: <ISA_LIT>tore , <NUM_LIT> , Align ( ) ) ; Builder . buildStore ( NextAddr , VaListPtr , * AddrStoreMMO ) ; MI . eraseFromParent ( ) ;


<s> const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op ) ; return ; } O << <STR_LIT> << TRI -> getAsmName ( MO1 . getReg ( ) ) ; if ( ! MO2 . getReg ( ) ) { if ( <STR_LIT> ( MO3 . getImm ( ) ) ) O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << <STR_LIT> ( MO3 . getImm ( ) ) ;


<s> SDLoc dl ( Op ) ; if ( isAllOnesConstant ( Mask ) ) return Op ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ;


<s> static bool isEAXLiveIn ( MachineBasicBlock & MBB ) { for ( MachineBasicBlock :: RegisterMaskPair RegMask : MBB . liveins ( ) ) {


<s> return sh_media_LDHI_Q ( p , <NUM_LIT> ) | sh_media_LDLO_Q ( p , <NUM_LIT> ) ; return sh_media_LDLO_Q ( p , <NUM_LIT> ) | sh_media_LDHI_Q ( p , <NUM_LIT> ) ;


<s> if ( Loc == FIM . end ( ) ) continue ; FI . MemInstCount += Loc -> second . MemInstCount ; FI . InstCount += Loc -> second . InstCount ; FI . IAMInstCount += Loc -> second . IAMInstCount ; FI . LSMInstCount += Loc -> second . LSMInstCount ; } else if ( auto * GEP = dyn_cast < GetElementPtrInst > ( & I ) ) { TargetLoweringBase :: AddrMode AM ; auto * Ptr = GetPointerBaseWithConstantOffset ( GEP , AM . BaseOffs , * DL ) ; AM . BaseGV = dyn_cast_or_null < GlobalValue > ( const_cast < Value * > ( Ptr ) ) ; AM . HasBaseReg = ! AM . BaseGV ; if ( TLI -> isLegalAddressingMode ( * DL , AM , GEP -> getResultElementType ( ) , GEP -> getPointerAddressSpace ( ) ) ) continue ;


<s> if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ;

return IntWidth == <NUM_LIT> || IntWidth == <NUM_LIT> ;


<s> bool isSelectSupported ( SelectSupportKind Kind ) const override {

return ( Kind != ScalarCondVectorVal ) ;


<s> } case <STR_LIT> : case <STR_LIT> : { ConstantSDNode * CWidth = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CWidth ) return ; unsigned BitWidth = <NUM_LIT> ; uint32_t Width = CWidth -> getZExtValue ( ) & <NUM_LIT> ;

if ( Opc == <STR_LIT> ) KnownZero = APInt :: getHighBitsSet ( BitWidth , BitWidth - Width ) ;


<s> unsigned numcopies = numCopiesNeeded ( Instr ) ; unsigned destregnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > dest = getScalarRegisters ( destregnum ) ; DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; i ++ ) { MachineInstr * copy = BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) ; copy -> addOperand ( Instr -> getOperand ( <NUM_LIT> + i ) ) ; copies . push_back ( copy ) ; }


<s> Ops . clear ( ) ; Ops . push_back ( Chain ) ; Ops . push_back ( Arg ) ; Ops . push_back ( PtrLo ) ; Ops . push_back ( PtrHi ) ; Ops . push_back ( DAG . getConstant ( StoreOffset , <STR_LIT> ) ) ; Ops . push_back ( InFlag ) ; StoreRet = DAG . getNode ( <STR_LIT> , dl , Tys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; Chain = getChain ( StoreRet ) ; InFlag = getOutFlag ( StoreRet ) ; ArgVT = Arg . getValueType ( ) ; Size = ArgVT . getSizeInBits ( ) ;


<s> MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; while ( MBBI != MBB . begin ( ) ) { MachineInstr * MI = -- MBBI ; if ( CompleteCCUsers && ( MI -> isCompare ( ) || isLoadAndTestAsCmp ( MI ) ) && ( optimizeCompareZero ( MI , CCUsers ) || fuseCompareOperations ( MI , CCUsers ) ) ) { ++ MBBI ; MI -> eraseFromParent ( ) ; Changed = true ; CCUsers . clear ( ) ; continue ; }

if ( MI -> definesRegister ( <STR_LIT> ) ) {


<s> bool <ISA_LIT>LongBranch :: runOnMachineFunction ( MachineFunction & F ) { if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isABI_O32 ( ) && F . getInfo < <ISA_LIT>FunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; bool IsPIC = ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) ; SmallVector < MBBInfo , <NUM_LIT> > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch ) { int64_t Offset = computeOffset ( I -> Br ) ; if ( ( I -> Br -> isConditionalBranch ( ) || IsPIC ) && isInt < <NUM_LIT> > ( Offset / <NUM_LIT> ) ) continue ; if ( I -> Br -> isUnconditionalBranch ( ) && ! IsPIC && isInt < <NUM_LIT> > ( Offset / <NUM_LIT> ) ) continue ; } expandToLongBranch ( * I ) ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } }

if ( EverMadeChange ) MF -> RenumberBlocks ( ) ;


<s> <ISA_LIT>Operand ( KindTy K ) : MCParsedAsmOperand ( ) , Kind ( K ) {


<s> snprintf ( buf , sizeof ( buf ) , <STR_LIT> , priority ) ; s = get_section ( buf , SECTION_WRITE | SECTION_NOTYPE , NULL ) ;


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ;


<s> if ( ExternalSymbolSDNode * N = dyn_cast < ExternalSymbolSDNode > ( Op ) ) return DAG . getTargetExternalSymbol ( N -> getSymbol ( ) , Ty , Flag ) ; if ( BlockAddressSDNode * N = dyn_cast < BlockAddressSDNode > ( Op ) ) return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty , <NUM_LIT> , Flag ) ; if ( JumpTableSDNode * N = dyn_cast < JumpTableSDNode > ( Op ) ) return DAG . getTargetJumpTable ( N -> getIndex ( ) , Ty , Flag ) ;

if ( ConstantPoolSDNode * N = dyn_cast < ConstantPoolSDNode > ( Op ) ) return DAG . getTargetConstantPool ( N -> getConstVal ( ) , Ty , N -> getAlignment ( ) , N -> getOffset ( ) , Flag ) ;


<s> return ( float64x1_t ) { __builtin_aarch64_fmaxdf ( vget_lane_f64 ( __a , <NUM_LIT> ) , vget_lane_f64 ( __b , <NUM_LIT> ) ) } ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( getCoproc ( ) ) ) ;


<s> bool isVirtualSection ( const MCSection & Section ) const { const MCSectionMachO & SMO = static_cast < const MCSectionMachO & > ( Section ) ;

return ( SMO . getType ( ) == MCSectionMachO :: S_ZEROFILL || SMO . getType ( ) == MCSectionMachO :: S_GB_ZEROFILL || SMO . getType ( ) == MCSectionMachO :: S_THREAD_LOCAL_ZEROFILL ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , <ISA_LIT>ProcClass ( None ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TargetABI ( <ISA_LIT>_ABI_UNKNOWN ) , DL ( computeDataLayout ( initializeSubtargetDependencies ( CPU , FS ) ) ) , TSInfo ( DL ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM ) , FrameLowering ( ! isThumb1Only ( ) ? new <ISA_LIT>FrameLowering ( * this ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( * this ) ) {


<s> bool isU6Imm ( ) const { return isImm ( <NUM_LIT> , <NUM_LIT> ) ;


<s> SmallVector < EVT , <NUM_LIT> > SplitEVTs ; ComputeValueVTs ( TLI , DL , Val -> getType ( ) , SplitEVTs ) ; assert ( VRegs . size ( ) == SplitEVTs . size ( ) && <STR_LIT> ) ; SmallVector < ArgInfo , <NUM_LIT> > RetInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; for ( unsigned i = <NUM_LIT> ; i < SplitEVTs . size ( ) ; ++ i ) { ArgInfo CurArgInfo = ArgInfo { VRegs [ i ] , SplitEVTs [ i ] . getTypeForEVT ( Ctx ) } ; setArgFlags ( CurArgInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( CurArgInfo , <NUM_LIT> , RetInfos , OrigArgIndices ) ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( F , RetInfos , OrigArgIndices , Outs ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , TLI . CCAssignFnForReturn ( ) ) ; setLocInfo ( ArgLocs , Outs ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ; if ( ! RetHandler . handle ( ArgLocs , RetInfos ) ) { return false ; } } MIRBuilder . insertInstr ( Ret ) ; return true ;


<s> void addMemRegImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getMemBaseReg ( ) ) ) ;


<s> SDValue Imm = ConvertI1VectorToInteger ( Op , DAG ) ; if ( Imm . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) return DAG . getBitcast ( VT , Imm ) ; SDValue ExtVec = DAG . getBitcast ( <STR_LIT> , Imm ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } uint64_t Immediate = <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > NonConstIdx ; bool IsSplat = true ; bool HasConstElts = false ; int SplatIdx = - <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . getOpcode ( ) == <STR_LIT> ) continue ; if ( ! isa < ConstantSDNode > ( In ) ) NonConstIdx . push_back ( idx ) ; else { Immediate |= cast < ConstantSDNode > ( In ) -> getZExtValue ( ) << idx ; HasConstElts = true ; } if ( SplatIdx == - <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( SplatIdx ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; SDValue DstVec ; SDValue Imm ; if ( Immediate ) { MVT ImmVT = <STR_LIT> ( std :: max ( ( int ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; Imm = DAG . getConstant ( Immediate , dl , ImmVT ) ; } else if ( HasConstElts ) Imm = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; else Imm = DAG . getUNDEF ( VT ) ; if ( Imm . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) DstVec = DAG . getBitcast ( VT , Imm ) ; else { SDValue ExtVec = DAG . getBitcast ( <STR_LIT> , Imm ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } for ( unsigned i = <NUM_LIT> , e = NonConstIdx . size ( ) ; i != e ; ++ i ) {

unsigned InsertIdx = NonConstIdx [ i ] ;


<s> if ( ! CE ) return false ; return isValidNEONi32vmovImm ( ~ CE -> getValue ( ) ) ;


<s> if ( parseSendMsgBody ( Msg , Op , Stream ) && validateSendMsg ( Msg , Op , Stream , Loc ) ) { ImmVal = encodeMsg ( Msg . Id , Op . Id , Stream . Id ) ; } else { return MatchOperand_ParseFail ; } } else if ( parseExpr ( ImmVal ) ) {

if ( ImmVal < <NUM_LIT> || ! isUInt < <NUM_LIT> > ( ImmVal ) ) {


<s> } for ( int Hi = Idx + <NUM_LIT> ; Hi <= HalfSize ; ++ Hi ) { SDValue Insert ; int Len = Hi - Idx ; if ( isSequentialOrUndefInRange ( Mask , Idx , Len , <NUM_LIT> ) ) { Insert = V1 ; } else if ( isSequentialOrUndefInRange ( Mask , Idx , Len , Size ) ) { Insert = V2 ; } else { continue ; } if ( isUndefInRange ( Mask , Hi , HalfSize - Hi ) ) { } else if ( ( ! Base || ( Base == V1 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Hi ) ) { Base = V1 ; } else if ( ( ! Base || ( Base == V2 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Size + Hi ) ) { Base = V2 ; } else { continue ; } BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; V1 = Base ; V2 = Insert ; return true ; } }


<s> const unsigned Regs = getRegs ( Opcode ) ; if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; assert ( CI . I -> hasOneMemOperand ( ) && CI . Paired -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * CI . Paired -> memoperands_begin ( ) ; MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( std :: min ( CI . Offset0 , CI . Offset1 ) ) . addImm ( CI . GLC0 ) . addImm ( CI . SLC0 ) . addImm ( <NUM_LIT> ) . addImm ( CI . DLC0 ) . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ; moveInstsAfter ( MIB , CI . InstsToMove ) ; MachineBasicBlock :: iterator Next = std :: next ( CI . I ) ; CI . I -> eraseFromParent ( ) ; CI . Paired -> eraseFromParent ( ) ;


<s> if ( CONST_INT_P ( op ) ) { HOST_WIDE_INT ival = INTVAL ( op ) ; return ( ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> || ival == <NUM_LIT> ) ; } return false ;


<s> Val = ( Op1 . second == Op2 . second ) ? - <NUM_LIT> : <NUM_LIT> ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_NE : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> ) ; Val = ( Op1 . second != Op2 . second ) ? - <NUM_LIT> : <NUM_LIT> ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_LT : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> ) ; Val = ( Op1 . second < Op2 . second ) ? - <NUM_LIT> : <NUM_LIT> ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_LE : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> <STR_LIT> ) ; Val = ( Op1 . second <= Op2 . second ) ? - <NUM_LIT> : <NUM_LIT> ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_GT : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> ) ; Val = ( Op1 . second > Op2 . second ) ? - <NUM_LIT> : <NUM_LIT> ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; case IC_GE : assert ( Op1 . first == IC_IMM && Op2 . first == IC_IMM && <STR_LIT> <STR_LIT> ) ; Val = ( Op1 . second >= Op2 . second ) ? - <NUM_LIT> : <NUM_LIT> ; OperandStack . push_back ( std :: make_pair ( IC_IMM , Val ) ) ; break ; } } } assert ( OperandStack . size ( ) == <NUM_LIT> && <STR_LIT> ) ;

return OperandStack . pop_back_val ( ) . second ;


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( targetm . calls . must_pass_in_stack ( arg ) ) return true ;


<s> uint64_t RawVectorOstream :: current_pos ( ) const {

return static_cast < uint64_t > ( Position ) ;


<s> const StringRef SPFuncName = Twine ( Twine ( Target -> getName ( ) ) + Twine ( <STR_LIT> ) ) . toNullTerminatedStringRef ( buf ) ; const Function * SPTarget = Target -> getParent ( ) -> getFunction ( SPFuncName ) ;


<s> if ( isShiftedImm ( ) ) { Shift = ShiftedImm . ShiftAmount ; Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> ) return false ; } else { Shift = <NUM_LIT> ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( Reg ) ; if ( RC == & <STR_LIT> ) MRI . setRegClass ( Reg , & <STR_LIT> ) ; continue ; } if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; const MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Src . getReg ( ) ) || ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; const TargetRegisterClass * DstRC = MRI . getRegClass ( Dst . getReg ( ) ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( Src . getReg ( ) ) ; if ( DstRC == & <STR_LIT> && TRI -> getCommonSubClass ( SrcRC , & <STR_LIT> ) ) { I1Defs . push_back ( Dst . getReg ( ) ) ; DebugLoc DL = MI . getDebugLoc ( ) ;

MachineInstr * DefInst = MRI . getUniqueVRegDef ( Src . getReg ( ) ) ;


<s> int64_t BrImm = ( SignedValue - <NUM_LIT> ) / <NUM_LIT> ;

if ( Ctx && ! isInt < <NUM_LIT> > ( BrImm ) ) Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ;


<s> assert ( ST -> hasSSE2 ( ) && <STR_LIT> ) ; unsigned StoreOpc = ST -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; Register Xmm = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , Xmm ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( StoreOpc ) ) , CfgSS ) . addReg ( Xmm ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( StoreOpc ) ) , CfgSS , <NUM_LIT> ) . addReg ( Xmm ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( StoreOpc ) ) , CfgSS , <NUM_LIT> ) . addReg ( Xmm ) ; addFrameReference ( BuildMI ( MBB , MI , DL , TII -> get ( StoreOpc ) ) , CfgSS , <NUM_LIT> ) . addReg ( Xmm ) ;


<s> case <STR_LIT> : case <STR_LIT> : if ( Idx == <NUM_LIT> ) { unsigned NumConstants = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned Cost = <ISA_LIT>TTI :: getIntImmCost ( Imm , Ty ) ; return ( Cost <= NumConstants * TCC_Basic ) ? static_cast < unsigned > ( TCC_Free ) : Cost ; } break ; case <STR_LIT> :

if ( ( Idx < <NUM_LIT> ) || ( Imm . getBitWidth ( ) <= <NUM_LIT> && isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) ) return TCC_Free ;


<s> bool <ISA_LIT>ModuleInfo :: isReadOnlyImage ( StringRef name , uint32_t iID ) const { const StringMap < <ISA_LIT>Kernel * > :: const_iterator kiter = mKernels . find ( name ) ; if ( kiter == mKernels . end ( ) ) { return false ; }

return kiter -> second -> readOnly . count ( iID ) ;


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; uint64_t Features = STI . getFeatureBits ( ) ; Triple T ( STI . getTargetTriple ( ) ) ; unsigned EFlags = <NUM_LIT> ; if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_32R2 ; else if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ARCH_32 ; if ( T . isArch64Bit ( ) ) { if ( Features & <STR_LIT> ) EFlags |= ELF :: EF_MIPS_ABI2 ; else if ( Features & <STR_LIT> ) { EFlags |= ELF :: EF_MIPS_ABI_O32 ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : needFP ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) {


<s> SDValue WidePassThru = DAG . getBitcast ( WideVecVT , Mld -> getPassThru ( ) ) ; if ( ! Mld -> getPassThru ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WidePassThru = DAG . getVectorShuffle ( WideVecVT , dl , WidePassThru , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , ShuffleVec ) ;


<s> if ( lookup_form ( MODE_u32base_index , type ) ) { if ( type_suffix_ids [ <NUM_LIT> ] == NUM_TYPE_SUFFIXES ) { gcc_assert ( ! load_p ) ; error_at ( location , <STR_LIT> <STR_LIT> , get_vector_type ( type ) , fndecl ) ; } else error_at ( location , <STR_LIT> <STR_LIT> , fndecl ) ; } else error_at ( location , <STR_LIT> , fndecl , get_vector_type ( type ) ) ; return MODE_none ; } type_suffix_index displacement_type = infer_vector_type ( argno ) ; if ( displacement_type == NUM_TYPE_SUFFIXES ) return MODE_none ; if ( type_suffixes [ displacement_type ] . element_bits == required_bits ) { vector_type_index displacement_vector_type = type_suffixes [ displacement_type ] . vector_type ; mode_suffix_index mode = find_mode_suffix ( NUM_VECTOR_TYPES , displacement_vector_type , displacement_units ( ) ) ; if ( mode != MODE_none ) { if ( mode == MODE_s32offset && ! lookup_form ( mode , type ) && lookup_form ( MODE_u32offset , type ) ) { if ( type_suffix_ids [ <NUM_LIT> ] == NUM_TYPE_SUFFIXES ) error_at ( location , <STR_LIT> <STR_LIT> , fndecl ) ; else error_at ( location , <STR_LIT> <STR_LIT> , fndecl ) ; return MODE_none ; } return mode ;


<s> break ; case GE : if ( mep_imm4_operand ( op1 , SImode ) ) break ; tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( LT , tmp , op0 , op1 ) ) ; code = EQ ; op0 = tmp ; op1 = const0_rtx ; break ; case EQ : case NE : if ( ! mep_reg_or_imm4_operand ( op1 , SImode ) ) op1 = force_reg ( SImode , op1 ) ; break ; case LE : case GT : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != <NUM_LIT> ) { op1 = GEN_INT ( INTVAL ( op1 ) + <NUM_LIT> ) ; code = ( code == LE ? LT : GE ) ; goto restart ; } tmp = gen_reg_rtx ( SImode ) ; gcc_assert ( mep_expand_setcc_1 ( LT , tmp , op1 , op0 ) ) ; code = ( code == LE ? EQ : NE ) ; op0 = tmp ; op1 = const0_rtx ; break ; case LTU : if ( op1 == const1_rtx ) {


<s> if ( TypeQual . find ( <STR_LIT> ) != StringRef :: npos ) return ValueKind :: Pipe ; return StringSwitch < ValueKind > ( BaseTypeName ) . Case ( <STR_LIT> , ValueKind :: Sampler ) . Case ( <STR_LIT> , ValueKind :: Queue ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> <STR_LIT> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , ValueKind :: Image ) . Default ( isa < PointerType > ( Ty ) ? ( Ty -> getPointerAddressSpace ( ) == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS ? ValueKind :: DynamicSharedPointer : ValueKind :: GlobalBuffer ) :


<s> MachineInstr * MI = I ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ; bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( KillsSrc ) { moveToTop ( Reg , I ) ; if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; -- StackTop ; pushReg ( getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ) ; } else { duplicateToTop ( Reg , getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) , I ) ; } MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : FPStackOffset ( <NUM_LIT> ) , RAStackOffset ( <NUM_LIT> ) , HasLoadArgs ( false ) , HasStoreVarArgs ( false ) , GlobalBaseReg ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , SRetReturnReg ( <NUM_LIT> ) , LiveInFI ( ) {


<s> bool ix86_expand_strlen ( rtx out , rtx src , rtx eoschar , rtx align ) { rtx addr , scratch1 , scratch2 , scratch3 , scratch4 ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > <NUM_LIT> && ! TARGET_INLINE_ALL_STRINGOPS && ! optimize_insn_for_size_p ( ) && ( ! CONST_INT_P ( align ) || INTVAL ( align ) < <NUM_LIT> ) ) return false ; addr = force_reg ( Pmode , XEXP ( src , <NUM_LIT> ) ) ; scratch1 = gen_reg_rtx ( Pmode ) ; if ( TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > <NUM_LIT> && ! optimize_insn_for_size_p ( ) ) { emit_move_insn ( out , addr ) ; ix86_expand_strlensi_unroll_1 ( out , src , align ) ; emit_insn ( ix86_gen_sub3 ( out , out , addr ) ) ; }


<s> ConstantPools -> emitAll ( Streamer ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI << '\n' ) ; <ISA_LIT>MCInstLower InstLower ( OutContext , * this ) ; MCInst TmpInst ;


<s> static bool isStartChunk ( uint64_t Chunk ) { if ( Chunk == <NUM_LIT> || Chunk == UINT64_MAX ) return false ; return isMask_64 ( ~ Chunk ) ;


<s> return <ISA_LIT>Operand :: CreateImm ( <NUM_LIT> , SMLoc ( ) , <ISA_LIT>Operand :: ImmTyR128 ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << getRegisterName ( RegNo ) ;


<s> EVT NarrowVT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> || NarrowVT != <STR_LIT> ) return false ; uint64_t ShiftImm ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( ! isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , ShiftImm ) ) return false ; SDLoc dl ( N ) ;

SDValue Opd0 = Widen ( CurDAG , Op . getOperand ( <NUM_LIT> ) ) ;


return ( poly64x1_t ) __builtin_neon_vreinterpretdiv8qi ( __a ) ;


<s> } const MCExpr * Expr = getSubExpr ( ) ; if ( Expr -> getKind ( ) != MCExpr :: SymbolRef ) OS << '(' ; Expr -> print ( OS ) ; if ( Expr -> getKind ( ) != MCExpr :: SymbolRef ) OS << ')' ;


<s> } int TaggedFI = - <NUM_LIT> ; if ( OpIndex >= <NUM_LIT> ) { const MachineOperand & MO = MI . getOperand ( OpIndex ) ; if ( MO . isFI ( ) ) { int FI = MO . getIndex ( ) ; if ( FI >= <NUM_LIT> && FI < MFI . getObjectIndexEnd ( ) && FrameObjects [ FI ] . IsValid ) TaggedFI = FI ; } } if ( TaggedFI >= <NUM_LIT> ) GB . AddMember ( TaggedFI ) ; else GB . EndCurrentGroup ( ) ; } GB . EndCurrentGroup ( ) ; } const <ISA_LIT>FunctionInfo & AFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Optional < int > TBPI = AFI . getTaggedBasePointerIndex ( ) ; if ( TBPI ) { FrameObjects [ * TBPI ] . ObjectFirst = true ; FrameObjects [ * TBPI ] . GroupFirst = true ; int FirstGroupIndex = FrameObjects [ * TBPI ] . GroupIndex ; if ( FirstGroupIndex >= <NUM_LIT> ) for ( FrameObject & Object : FrameObjects ) if ( Object . GroupIndex == FirstGroupIndex ) Object . GroupFirst = true ; } llvm :: stable_sort ( FrameObjects , FrameObjectCompare ) ; int i = <NUM_LIT> ; for ( auto & Obj : FrameObjects ) { if ( ! Obj . IsValid ) break ; ObjectsToAllocate [ i ++ ] = Obj . ObjectIndex ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto & Obj : FrameObjects ) {


<s> LoadSDNode * LD = cast < LoadSDNode > ( N ) ; if ( ! isValidIndexedLoad ( LD ) ) return NULL ; MVT VT = LD -> getMemoryVT ( ) . getSimpleVT ( ) ; unsigned Opcode = <NUM_LIT> ; switch ( VT . SimpleTy ) { case <STR_LIT> :


return <STR_LIT> ( Val ) == <STR_LIT> && ( <STR_LIT> ( Val ) == <NUM_LIT> || <STR_LIT> ( Val ) == <NUM_LIT> ) ;


<s> return StringSwitch < <STR_LIT> > ( ID ) . Case ( <STR_LIT> , <STR_LIT> :: I32 ) . Case ( <STR_LIT> , <STR_LIT> :: I64 ) . Case ( <STR_LIT> , <STR_LIT> :: F32 ) . Case ( <STR_LIT> , <STR_LIT> :: F64 ) . Case ( <STR_LIT> , <STR_LIT> :: V128 ) . Case ( <STR_LIT> , <STR_LIT> :: Funcref ) . Case ( <STR_LIT> , <STR_LIT> :: Externref ) . Case ( <STR_LIT> , <STR_LIT> :: Exnref ) . Case ( <STR_LIT> , <STR_LIT> :: Void ) . Default ( <STR_LIT> :: Invalid ) ;


<s> const TargetFrameLowering * getFrameLowering ( ) const override { return & FrameLowering ;


<s> for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertCSRRestoresInBlock ( B , CSI , HRI ) ; for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertEpilogueInBlock ( B ) ; for ( auto & B : MF ) { if ( B . empty ( ) ) continue ; MachineInstr * RetI = getReturn ( B ) ; if ( ! RetI || isRestoreCall ( RetI -> getOpcode ( ) ) ) continue ; for ( auto & R : CSI ) RetI -> addOperand ( MachineOperand :: CreateReg ( R . getReg ( ) , false , true ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return MCDisassembler :: Success ;


<s> if ( ! Value ) return ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ;

for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) {


<s> for ( regno2 = regno + <NUM_LIT> ; ( saved_regs_mask & ( <NUM_LIT> << regno2 ) ) == <NUM_LIT> ; regno2 ++ ) ; reg1 = gen_rtx_REG ( SImode , regno ) ; reg2 = gen_rtx_REG ( SImode , regno2 ) ; if ( first ) { rtx insn ; first = false ; mem1 = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * num_regs ) ) ; mem2 = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * ( num_regs - <NUM_LIT> ) ) ) ; tmp0 = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * ( num_regs ) ) ) ; tmp1 = gen_rtx_SET ( mem1 , reg1 ) ; tmp2 = gen_rtx_SET ( mem2 , reg2 ) ; RTX_FRAME_RELATED_P ( tmp0 ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( tmp1 ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( tmp2 ) = <NUM_LIT> ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp0 ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp1 ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp2 ; insn = emit_insn ( par ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , dwarf ) ; } else { mem1 = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * i ) ) ; mem2 = gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * ( i + <NUM_LIT> ) ) ) ; tmp1 = gen_rtx_SET ( mem1 , reg1 ) ; tmp2 = gen_rtx_SET ( mem2 , reg2 ) ; RTX_FRAME_RELATED_P ( tmp1 ) = <NUM_LIT> ; RTX_FRAME_RELATED_P ( tmp2 ) = <NUM_LIT> ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( <NUM_LIT> ) ) ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp1 ; XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = tmp2 ; emit_insn ( par ) ; } tmp1 = gen_rtx_SET ( gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * i ) ) , reg1 ) ; tmp2 = gen_rtx_SET ( gen_frame_mem ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * ( i + <NUM_LIT> ) ) ) , reg2 ) ; RTX_FRAME_RELATED_P ( tmp1 ) = <NUM_LIT> ;


<s> EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; unsigned SP = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue StackPtr = DAG . getRegister ( SP , PtrVT ) ;

SDValue Chain = Op . getOperand ( <NUM_LIT> ) ;


<s> int i ; HARD_REG_SET x ; if ( ! TARGET_FPU ) { COPY_HARD_REG_SET ( x , reg_class_contents [ ( int ) FPU_REGS ] ) ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( x , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; } if ( TARGET_AC0 ) call_used_regs [ AC0_REGNUM ] = <NUM_LIT> ; if ( TARGET_UNIX_ASM ) { reg_names [ <NUM_LIT> ] = <STR_LIT> ;


<s> return alignTo ( FlatWorkGroupSize , getWavefrontSize ( STI ) ) / getWavefrontSize ( STI ) ;


<s> static HOST_WIDE_INT rs6000_starting_frame_offset ( void ) { if ( FRAME_GROWS_DOWNWARD ) return <NUM_LIT> ; return RS6000_STARTING_FRAME_OFFSET ;


<s> if ( Subtarget -> hasUnalignedBufferAccess ( ) ) { if ( IsFast ) { * IsFast = ( AddrSpace == <ISA_LIT>AS :: CONSTANT_ADDRESS || AddrSpace == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) ? ( Align % <NUM_LIT> == <NUM_LIT> ) : true ; } return true ; } if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ;

return VT . bitsGT ( <STR_LIT> ) && Align % <NUM_LIT> == <NUM_LIT> ;


<s> if ( Val == - <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; }

Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( Val , getContext ( ) ) , S , Tok . getEndLoc ( ) ) ) ;


<s> if ( ! ST -> hasDotProd ( ) || N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( Op0 . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned ExtOpcode = Op0 . getOpcode ( ) ; if ( ExtOpcode != <STR_LIT> && ExtOpcode != <STR_LIT> ) return SDValue ( ) ; EVT Op0VT = Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ;

if ( Op0VT != <STR_LIT> ) return SDValue ( ) ;


<s> <ISA_LIT>TTIImpl :: TTI :: MemCmpExpansionOptions <ISA_LIT>TTIImpl :: enableMemCmpExpansion ( bool OptSize , bool IsZeroCmp ) const { TTI :: MemCmpExpansionOptions Options ;


<s> bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ;

return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> unsigned Register = FCRDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> for ( StackVreg & VR : Data ) { if ( Regs . empty ( ) ) return ; if ( VR . VirtReg == <ISA_LIT>FunctionInfo :: UnusedReg ) { VR = Regs . pop_back_val ( ) ; }


<s> __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ;

return ( poly8x16_t ) __builtin_aarch64_tbx4v16qi ( ( int8x16_t ) r , __o , ( int8x16_t ) idx ) ;


<s> void onLParen ( ) { IntelExprState CurrState = State ; switch ( State ) { default : State = IES_ERROR ; break ; case IES_PLUS : case IES_MINUS : case IES_OR : case IES_AND : case IES_LSHIFT : case IES_RSHIFT : case IES_MULTIPLY : case IES_DIVIDE : case IES_LPAREN : if ( ( PrevState == IES_PLUS || PrevState == IES_MINUS || PrevState == IES_OR || PrevState == IES_AND || PrevState == IES_LSHIFT || PrevState == IES_RSHIFT || PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE || PrevState == IES_LPAREN || PrevState == IES_LBRAC ) && CurrState == IES_MINUS ) { State = IES_ERROR ;


<s> std :: string <ISA_LIT>RegisterInfo :: getPrettyName ( unsigned reg ) { std :: string s ( RegisterDescriptors [ reg ] . Name ) ;


<s> if ( Register :: isPhysicalRegister ( Reg ) ) return MIB . addReg ( TRI -> getSubReg ( Reg , SubIdx ) , State ) ;

return MIB . addReg ( Reg , State , SubIdx ) ;


<s> if ( GlueAllocframeStore ) { unsigned FrameSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; MachineOperand & MOff = I -> getOperand ( <NUM_LIT> ) ; MOff . setImm ( MOff . getImm ( ) + FrameSize + HEXAGON_LRFP_SIZE ) ; } return false ;


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) RC = MRI . getRegClass ( Reg ) ; else RC = getPhysRegClass ( Reg ) ;


<s> rtx temp_reg = gen_reg_rtx ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ; emit_move_insn ( temp_reg , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = temp_reg ; did = <NUM_LIT> ; } if ( rl78_far_p ( operands [ <NUM_LIT> ] ) ) { temp_reg = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_reg_rtx ( GET_MODE ( operands [ <NUM_LIT> ] ) ) ; did = <NUM_LIT> ;


<s> return new <ISA_LIT>Packetizer ( tm ) ;


<s> SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits + NumBits - <NUM_LIT> , OpVT ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Ops , array_lengthof ( Ops ) ) ; Op = DAG . getNode ( <STR_LIT> , dl , OpVT , Op , DAG . getConstant ( NumBits - <NUM_LIT> , OpVT ) ) ; if ( VT == <STR_LIT> ) Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ;


<s> bool CanUseDblLoad = false ; if ( ContiguousRegs && ( i < CSI . size ( ) - <NUM_LIT> ) ) { unsigned SuperRegNext = uniqueSuperReg ( CSI [ i + <NUM_LIT> ] . getReg ( ) , TRI ) ; SuperRegClass = TRI -> getMinimalPhysRegClass ( SuperReg ) ; CanUseDblLoad = ( SuperRegNext == SuperReg ) ; } if ( CanUseDblLoad ) { TII . loadRegFromStackSlot ( MBB , MI , SuperReg , CSI [ i + <NUM_LIT> ] . getFrameIdx ( ) , SuperRegClass , TRI ) ; MBB . addLiveIn ( SuperReg ) ; ++ i ; } else { ContiguousRegs = false ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; MBB . addLiveIn ( Reg ) ; } } return true ;


<s> static SDValue LowerSIGN_EXTEND_VECTOR_INREG ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDValue In = Op -> getOperand ( <NUM_LIT> ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; assert ( VT . getSizeInBits ( ) == InVT . getSizeInBits ( ) ) ; MVT InSVT = InVT . getVectorElementType ( ) ; assert ( VT . getVectorElementType ( ) . getSizeInBits ( ) > InSVT . getSizeInBits ( ) ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; SDLoc dl ( Op ) ; if ( Subtarget . hasSSE41 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue Curr = In ; MVT CurrVT = InVT ; while ( CurrVT != VT && CurrVT . getVectorElementType ( ) != <STR_LIT> ) { Curr = DAG . getNode ( <STR_LIT> , dl , CurrVT , DAG . getUNDEF ( CurrVT ) , Curr ) ; MVT CurrSVT = <STR_LIT> ( CurrVT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; CurrVT = <STR_LIT> ( CurrSVT , CurrVT . getVectorNumElements ( ) / <NUM_LIT> ) ; Curr = DAG . getBitcast ( CurrVT , Curr ) ; } SDValue SignExt = Curr ; if ( CurrVT != InVT ) {

unsigned SignExtShift = CurrVT . getVectorElementType ( ) . getSizeInBits ( ) - InSVT . getSizeInBits ( ) ;


<s> MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ; } unsigned Opc = Cond [ <NUM_LIT> ] . getImm ( ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ <NUM_LIT> ] ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ;

if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ;


<s> const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; if ( MO2 . getImm ( ) ) { O << <STR_LIT> << MO2 . getImm ( ) ; }


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addFPImm ( FPImm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , Op0IsKill * RegState :: Kill ) . addFPImm ( FPImm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ;


<s> MachineConstantPool * ConstantPool = MF . getConstantPool ( ) ; const Constant * C = ConstantInt :: get ( Type :: getInt32Ty ( MBB . getParent ( ) -> getFunction ( ) -> getContext ( ) ) , Val ) ; unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ;


<s> static void reservePrivateMemoryRegs ( const TargetMachine & TM , MachineFunction & MF , const <ISA_LIT>RegisterInfo & TRI , <ISA_LIT>MachineFunctionInfo & Info ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; bool HasStackObjects = MFI . hasStackObjects ( ) ; if ( HasStackObjects ) Info . setHasNonSpillStackObjects ( true ) ; if ( TM . getOptLevel ( ) == CodeGenOpt :: None ) HasStackObjects = true ; bool RequiresStackAccess = HasStackObjects || MFI . hasCalls ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( ST . isAmdCodeObjectV2 ( MF . getFunction ( ) ) ) { if ( RequiresStackAccess ) { unsigned PrivateSegmentBufferReg = Info . getPreloadedReg ( <STR_LIT> ) ; Info . setScratchRSrcReg ( PrivateSegmentBufferReg ) ; if ( MFI . hasCalls ( ) ) { unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; Info . setScratchWaveOffsetReg ( ReservedOffsetReg ) ;


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override {


<s> if ( Size > <NUM_LIT> ) LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; bool Ret = translateInstruction ( Instr , Insn , this ) ; if ( ! Ret ) { unsigned Flags = <STR_LIT> ; if ( Insn . hasAdSize ) Flags |= <STR_LIT> ; if ( ! Insn . mandatoryPrefix ) { if ( Insn . hasOpSize ) Flags |= <STR_LIT> ; if ( Insn . repeatPrefix == <NUM_LIT> ) Flags |= <STR_LIT> ; else if ( Insn . repeatPrefix == <NUM_LIT> && Insn . opcode != <NUM_LIT> ) Flags |= <STR_LIT> ; if ( Insn . hasLockPrefix ) Flags |= <STR_LIT> ; } Instr . setFlags ( Flags ) ; } return ( ! Ret ) ? Success : Fail ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) , Subtarget ( TT , CPU , FS , * this ) {


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; printOperand ( MI , OpNo , O ) ;


<s> break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str ) ; break ; case AARCH64_PARSE_INVALID_FEATURE : error ( <STR_LIT> , str ) ; break ; default : gcc_unreachable ( ) ; }


<s> <ISA_LIT>MachineFunction :: <ISA_LIT>MachineFunction ( const MachineFunction & MF ) : Mode ( MF . getFunction ( ) ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , IsModuleEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) { const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( MF ) ; const Function & F = MF . getFunction ( ) ; Attribute MemBoundAttr = F . getFnAttribute ( <STR_LIT> ) ; MemoryBound = MemBoundAttr . getValueAsBool ( ) ; Attribute WaveLimitAttr = F . getFnAttribute ( <STR_LIT> ) ;

WaveLimiter = WaveLimitAttr . getValueAsBool ( ) ;


<s> if ( ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) && ( ( VT != <STR_LIT> ) || ( InVT != <STR_LIT> ) ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue ZeroVec = getZeroVector ( InVT , Subtarget , DAG , dl ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Op . getOpcode ( ) == <STR_LIT> ; SDValue OpLo = getUnpackl ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; SDValue OpHi = getUnpackh ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ; EVT HVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HVT , OpHi ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpHi ) ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ;


<s> ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ;

else Base = Addr . getOperand ( <NUM_LIT> ) ;


<s> if ( ! Result . empty ( ) ) Result += <STR_LIT> ; if ( SwBits . count ( ) == <NUM_LIT> && SwInfo -> Values . empty ( ) ) { Result += SwInfo -> Name . lower ( ) ; } else if ( ( SwSet & SwInfo -> Value ) == SwInfo -> Default && ( SwInfo -> Options & OptPrintAlways ) == <NUM_LIT> ) { SwSet &= ~ SwInfo -> Value ; } else { if ( SwInfo -> Name . equals ( <STR_LIT> ) ) { Result += 'b' ; Result += std :: bitset < <NUM_LIT> > ( ( SwSet >> <NUM_LIT> ) & <NUM_LIT> ) . to_string ( ) ; } else { std :: string SwStr = tryFormatMaskedSwitch ( SwInfo , SwSet , NeedGroupName ) ; if ( NeedGroupName || SwStr . empty ( ) ) { Result += SwInfo -> Name . lower ( ) ; Result += '=' ; } if ( ! SwStr . empty ( ) ) { Result += SwStr ; } else Result += numToHexStr ( SwSet & SwInfo -> Value ) ; } } SwSet &= ~ SwInfo -> Value ; } else { bool ShallPrint = SwInfo -> Default != <NUM_LIT> || ( SwInfo -> Options & OptPrintAlways ) ;

if ( ShallPrint && ! SwInfo -> Values . empty ( ) ) {


<s> case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_BARTS : AK = GK_BARTS ; break ; case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CAICOS : AK = GK_CAICOS ; break ; case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CAYMAN : AK = GK_CAYMAN ; break ; case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_TURKS : AK = GK_TURKS ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX600 : AK = GK_GFX600 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX601 : AK = GK_GFX601 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX700 : AK = GK_GFX700 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX701 : AK = GK_GFX701 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX702 : AK = GK_GFX702 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX703 : AK = GK_GFX703 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX704 : AK = GK_GFX704 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX801 : AK = GK_GFX801 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX802 : AK = GK_GFX802 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX803 : AK = GK_GFX803 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX810 : AK = GK_GFX810 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX900 : AK = GK_GFX900 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX902 : AK = GK_GFX902 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX904 : AK = GK_GFX904 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX906 : AK = GK_GFX906 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX908 : AK = GK_GFX908 ; break ;

case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX909 : AK = GK_GFX909 ; break ;


<s> unsigned A15SDOptimizer :: getDPRLaneFromSPR ( unsigned SReg ) { unsigned DReg = TRI -> getMatchingSuperReg ( SReg , <STR_LIT> , & <STR_LIT> ) ; if ( DReg != <STR_LIT> ) return <STR_LIT> ;


<s> MVT VecIntVT = V . getSimpleValueType ( ) ; bool Is128 = VecIntVT == <STR_LIT> ; MVT VecFloatVT = Is128 ? <STR_LIT> : <STR_LIT> ; if ( VecFloatVT != Op -> getSimpleValueType ( <NUM_LIT> ) ) return SDValue ( ) ; assert ( ( VecIntVT == <STR_LIT> || VecIntVT == <STR_LIT> ) && <STR_LIT> ) ; SDValue VecCstLow = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue VecCstHigh = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue VecCstShift = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue HighShift = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstShift ) ; SDValue Low , High ; if ( Subtarget . hasSSE41 ( ) ) { MVT VecI16VT = Is128 ? <STR_LIT> : <STR_LIT> ; SDValue VecCstLowBitcast = DAG . getBitcast ( VecI16VT , VecCstLow ) ; SDValue VecBitcast = DAG . getBitcast ( VecI16VT , V ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecBitcast , VecCstLowBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue VecCstHighBitcast = DAG . getBitcast ( VecI16VT , VecCstHigh ) ; SDValue VecShiftBitcast = DAG . getBitcast ( VecI16VT , HighShift ) ; High = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecShiftBitcast , VecCstHighBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } else { SDValue VecCstMask = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue LowAnd = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstMask ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecIntVT , LowAnd , VecCstLow ) ; High = DAG . getNode ( <STR_LIT> , DL , VecIntVT , HighShift , VecCstHigh ) ; }

SDValue VecCstFAdd = DAG . getConstantFP ( APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> ) ) , DL , VecFloatVT ) ;


<s> assert ( target -> MBB && <STR_LIT> ) ; if ( target -> MBB != layout_successor ) { const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; if ( PTM . getCodeModel ( ) != CodeModel :: Large || block -> Region == target -> Region ) { unsigned Opc = block -> Region == target -> Region ? <STR_LIT> : <STR_LIT> ; AddDefaultPred ( BuildMI ( * fallthrough , fallthrough -> instr_end ( ) , DebugLoc ( ) , TII . get ( Opc ) ) ) . addMBB ( target -> MBB ) ; } else { AddDefaultPred ( BuildMI ( * fallthrough , fallthrough -> instr_end ( ) , DebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) ) . addMBB ( target -> MBB ) ; AddDefaultPred ( BuildMI ( * fallthrough , fallthrough -> instr_end ( ) , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } MachineBasicBlock :: iterator II = fallthrough -> end ( ) ; -- II ; unsigned cycles = PTM . getSubtargetImpl ( ) -> getDelaySlotCycles ( * II ) ; if ( PTM . getSubtargetImpl ( ) -> getCFLType ( ) != <ISA_LIT>Subtarget :: CFL_NON_DELAYED && ! PII . hasRegUse ( & * II ) ) { cycles = PII . moveUp ( * fallthrough , II ) ; } for ( unsigned i = <NUM_LIT> ; i < cycles ; i ++ ) { AddDefaultPred ( BuildMI ( * fallthrough , fallthrough -> instr_end ( ) , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) ) ; NOPsInserted ++ ; }


<s> bool inverted ; switch ( code ) { case UNORDERED : case UNLT : case UNLE : case UNGT : case UNGE : case UNEQ : case NE : code = reverse_condition_maybe_unordered ( code ) ; if ( ! can_invert ) { rtx tmp = gen_reg_rtx ( cmp_result_mode ) ; if ( arm_expand_vector_compare ( tmp , code , op0 , op1 , true ) ) gcc_unreachable ( ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_NOT ( cmp_result_mode , tmp ) ) ) ; return false ; } inverted = true ; break ; default : inverted = false ; break ; } switch ( code ) { case LE : case LT : if ( op1 != CONST0_RTX ( cmp_mode ) ) { code = swap_condition ( code ) ; std :: swap ( op0 , op1 ) ; } case EQ : case GE : case GT : emit_insn ( gen_neon_vc ( code , cmp_mode , target , op0 , op1 ) ) ; return inverted ; case GEU : case GTU : emit_insn ( gen_neon_vc ( code , cmp_mode , target , op0 , force_reg ( cmp_mode , op1 ) ) ) ; return inverted ; case LEU : case LTU : emit_insn ( gen_neon_vc ( swap_condition ( code ) , cmp_mode , target , force_reg ( cmp_mode , op1 ) , op0 ) ) ; return inverted ; case LTGT : case ORDERED : {


<s> static constexpr MCPhysReg llvmRegnums [ ] = { ALL_REGS } ; MCPhysReg llvmRegnum = llvmRegnums [ reg ] ; mcInst . addOperand ( MCOperand :: createReg ( llvmRegnum ) ) ;


<s> if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) GV = GA -> resolveAliasedGlobal ( false ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , getPointerTy ( ) ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) ) ; } } else if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , DebugLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { Chain , Offset } ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Args , <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ;

unsigned Reg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;


<s> Type * EltType = GV -> getType ( ) -> getElementType ( ) ; unsigned Size = TD -> getTypeAllocSize ( EltType ) ; unsigned Alignment = TD -> getPrefTypeAlignment ( EltType ) ; const GlobalVariable * Var = dyn_cast < GlobalVariable > ( GV ) ; const Constant * Init = Var -> getInitializer ( ) ; int FI = FrameInfo -> CreateStackObject ( Size , Alignment , false ) ; SDValue InitPtr = DAG . getFrameIndex ( FI , getPointerTy ( <STR_LIT> ) ) ; SmallVector < SDNode * , <NUM_LIT> > WorkList ; for ( SDNode :: use_iterator I = DAG . getEntryNode ( ) -> use_begin ( ) , E = DAG . getEntryNode ( ) -> use_end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) continue ; WorkList . push_back ( * I ) ; } SDValue Chain = LowerConstantInitializer ( Init , GV , InitPtr , DAG . getEntryNode ( ) , DAG ) ; for ( SmallVector < SDNode * , <NUM_LIT> > :: iterator I = WorkList . begin ( ) , E = WorkList . end ( ) ; I != E ; ++ I ) { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> ; i < ( * I ) -> getNumOperands ( ) ; ++ i ) { Ops . push_back ( ( * I ) -> getOperand ( i ) ) ; } DAG . UpdateNodeOperands ( * I , Ops ) ; }

return DAG . getZExtOrTrunc ( InitPtr , SDLoc ( Op ) , getPointerTy ( <STR_LIT> ) ) ;


<s> SDLoc DL ( Op ) ; unsigned Opcode ; if ( is32Bit ( VT ) ) { Op0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Opcode = <STR_LIT> ; } else if ( DAG . ComputeNumSignBits ( Op1 ) > <NUM_LIT> ) { Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; Opcode = <STR_LIT> ; } else Opcode = <STR_LIT> ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF ) const {


<s> if ( CUReg == - <NUM_LIT> ) return ~ <NUM_LIT> ; SavedRegs [ i ] = CUReg ; } std :: swap ( SavedRegs [ <NUM_LIT> ] , SavedRegs [ <NUM_LIT> ] ) ; std :: swap ( SavedRegs [ <NUM_LIT> ] , SavedRegs [ <NUM_LIT> ] ) ; std :: swap ( SavedRegs [ <NUM_LIT> ] , SavedRegs [ <NUM_LIT> ] ) ; uint32_t RenumRegs [ CU_NUM_SAVED_REGS ] ; for ( unsigned i = CU_NUM_SAVED_REGS - RegCount ; i < CU_NUM_SAVED_REGS ; ++ i ) { unsigned Countless = <NUM_LIT> ;

for ( unsigned j = CU_NUM_SAVED_REGS - RegCount ; j < i ; ++ j ) if ( SavedRegs [ j ] < SavedRegs [ i ] ) ++ Countless ;


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser ( parser ) { MCAsmParserExtension :: Initialize ( Parser ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> static bool selectMergeValues ( MachineInstrBuilder & MIB , const <ISA_LIT>BaseInstrInfo & TII , MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { assert ( TII . getSubtarget ( ) . hasVFP2 ( ) && <STR_LIT> ) ; unsigned VReg0 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg0 ; assert ( MRI . getType ( VReg0 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg0 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned VReg1 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ;

unsigned VReg2 = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> switch ( Directive ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( N ) ; ArrayRef < int > ShuffleMask = SVN -> getMask ( ) ; if ( isVectorElementSwap ( ShuffleMask , N -> getValueType ( <NUM_LIT> ) ) ) { SDValue Load = N -> getOperand ( <NUM_LIT> ) ; LoadSDNode * LD = cast < LoadSDNode > ( Load ) ; SDValue Ops [ ] = { LD -> getChain ( ) , LD -> getBasePtr ( ) } ; SDValue ESLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) , Ops , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ;


<s> auto * LoadA = cast < LoadSDNode > ( StoreA -> getValue ( ) . getOperand ( <NUM_LIT> - I ) ) ; auto * LoadB = cast < LoadSDNode > ( StoreA -> getValue ( ) . getOperand ( I ) ) ;

return ! LoadA -> isVolatile ( ) && LoadA -> getMemoryVT ( ) == LoadB -> getMemoryVT ( ) && canUseBlockOperation ( StoreA , LoadB ) ;


<s> if ( ! isShifter ( ) ) return false ; <STR_LIT> ST = <STR_LIT> ( Shifter . Val ) ; if ( ST != <STR_LIT> ) return false ; uint64_t Val = <STR_LIT> ( Shifter . Val ) ;

return ( Val == <NUM_LIT> || Val == <NUM_LIT> ) ;


<s> break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case TSV110 :


<s> unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) / <NUM_LIT> ) return false ;

return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( KnownUndef [ i ] ) Mask [ i ] = SM_SentinelUndef ; else if ( KnownZero [ i ] ) Mask [ i ] = SM_SentinelZero ;


<s> if ( auto * Ld = dyn_cast < LoadInst > ( V ) ) Ty = cast < PointerType > ( Ld -> getPointerOperandType ( ) ) -> getElementType ( ) ; const IntegerType * IntTy = dyn_cast < IntegerType > ( Ty ) ; if ( ! IntTy ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; }

return IntTy -> getBitWidth ( ) == <ISA_LIT>CodeGenPrepare :: TypeSize ;


<s> HOST_WIDE_INT low , high ; gcc_assert ( GET_CODE ( value ) == CONST_DOUBLE ) ; low = CONST_DOUBLE_LOW ( value ) ; high = CONST_DOUBLE_HIGH ( value ) ; if ( low & <NUM_LIT> ) { return ( ( ( unsigned HOST_WIDE_INT ) low <= <NUM_LIT> && high == <NUM_LIT> ) || ( ( ( low & - ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) == - ( unsigned HOST_WIDE_INT ) <NUM_LIT> ) && high == - <NUM_LIT> ) ) ; }


<s> unsigned <ISA_LIT>InsertWaitcnts :: countNumBottomBlocks ( const MachineLoop * Loop ) { unsigned Count = <NUM_LIT> ; for ( MachineBasicBlock * MBB : Loop -> blocks ( ) ) { if ( MBB -> isSuccessor ( Loop -> getHeader ( ) ) ) { Count ++ ; }


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchPredTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return <NUM_LIT> ;


<s> FrameIndexSDNode * FINode = cast < FrameIndexSDNode > ( Op ) ; unsigned FrameIndex = FINode -> getIndex ( ) ; uint64_t MaxGPUAlloc = UINT64_C ( <NUM_LIT> ) * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> ;


<s> const TargetRegisterClass * getPointerRegClass ( const MachineFunction & MF , unsigned Kind = <NUM_LIT> ) const override { return & <STR_LIT> ;


<s> LastMappingSymbols [ getPreviousSection ( ) . first ] = LastEMS ;

LastEMS = LastMappingSymbols . lookup ( Section ) ;


<s> if ( dst_regnum == STACK_POINTER_REGNUM ) return ! TARGET_WINDOWED_ABI || ( mode == SImode && register_operand ( operands [ <NUM_LIT> ] , mode ) && ! ACC_REG_P ( xt_true_regnum ( operands [ <NUM_LIT> ] ) ) ) ;

if ( ! ACC_REG_P ( dst_regnum ) ) return true ;


<s> void print ( raw_ostream & OS ) const override {


<s> return __arm_vmulhq_s32 ( __a , __b ) ;


<s> for ( auto I = OldB -> succ_begin ( ) , E = OldB -> succ_end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = * I ;

MachineBasicBlock :: iterator P , N = SB -> getFirstNonPHI ( ) ;


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerCONSTANTPOOL ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_SINT ( Op , DAG ) ;

case <STR_LIT> : return LowerSINT_TO_FP ( Op , DAG ) ;


<s> OpId = ( Val & OP_MASK_ ) >> OP_SHIFT_ ;

StreamId = ( Val & STREAM_ID_MASK_ ) >> STREAM_ID_SHIFT_ ;


<s> if ( ValTy -> isVectorTy ( ) && ISD == <STR_LIT> ) { const int AmortizationCost = <NUM_LIT> ; static const TypeConversionCostTblEntry < <STR_LIT> > VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost


<s> if ( BaseType == RegBase ) { cerr << <STR_LIT> ; if ( Base . Reg . getNode ( ) != <NUM_LIT> ) Base . Reg . getNode ( ) -> dump ( ) ; else cerr << <STR_LIT> ; cerr << '\n' ; } else { cerr << <STR_LIT> << Base . FrameIndex << '\n' ;


<s> return ( uint8x16_t ) __builtin_neon_vcgtuv16qi ( ( int8x16_t ) __b , ( int8x16_t ) __a ) ;


<s> unsigned getCheriReg ( ) const { assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_Cheri ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT> ;

assert ( RegIdx . RealRegister == <STR_LIT> || ( RegIdx . RealRegister >= <STR_LIT> && RegIdx . RealRegister <= <STR_LIT> ) ) ;


<s> REAL_VALUE_FROM_CONST_DOUBLE ( r0 , x0 ) ; for ( i = <NUM_LIT> ; i < CONST_VECTOR_NUNITS ( x ) ; i ++ ) { xi = CONST_VECTOR_ELT ( x , i ) ; if ( ! CONST_DOUBLE_P ( xi ) ) return false ;

REAL_VALUE_FROM_CONST_DOUBLE ( ri , xi ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( MachineFunction & MF ) const {


<s> while ( ! MI . getOperand ( FIOperandNo ) . isFI ( ) ) { ++ FIOperandNo ; assert ( FIOperandNo != MI . getNumOperands ( ) && <STR_LIT> ) ; } unsigned OffsetOperandNo = ( FIOperandNo == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( MI . getOpcode ( ) == TargetInstrInfo :: INLINEASM ) OffsetOperandNo = FIOperandNo - <NUM_LIT> ; int FrameIndex = MI . getOperand ( FIOperandNo ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II , SPAdj , RS ) ; return ; } if ( EnableRegisterScavenging ) if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex , SPAdj , RS ) ; return ; } MI . getOperand ( FIOperandNo ) . ChangeToRegister ( hasFP ( MF ) ? <STR_LIT> : <STR_LIT> , false ) ; bool isIXAddr = false ; switch ( OpC ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isIXAddr = true ; break ; } int Offset = MFI -> getObjectOffset ( FrameIndex ) ; if ( ! isIXAddr ) Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; else Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) << <NUM_LIT> ; Offset += MFI -> getStackSize ( ) ; if ( isInt16 ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { if ( isIXAddr ) Offset >>= <NUM_LIT> ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } unsigned SReg ; if ( EnableRegisterScavenging ) SReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; else SReg = <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , SReg ) . addReg ( SReg , false , false , true ) . addImm ( Offset ) ; unsigned OperandBase ; if ( OpC != TargetInstrInfo :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) && <STR_LIT> ) ; unsigned NewOpcode = ImmToIdxMap . find ( OpC ) -> second ;

MI . setDesc ( TII . get ( NewOpcode ) ) ;


<s> case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> :

case <STR_LIT> : return ExpandADDSUB ( Op . getNode ( ) , DAG ) ;


return isImm ( <NUM_LIT> , <NUM_LIT> ) ;


<s> case <STR_LIT> : return ; default : break ; } assert ( ! MI . mayLoad ( ) && <STR_LIT> ) ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return ; auto & TargetOp = MI . getOperand ( <NUM_LIT> ) ;

unsigned OldTargetReg = TargetOp . getReg ( ) ;


<s> CmpConstants ( unsigned CmpOpcode , unsigned FlagsOpcode , unsigned OpRegBank , unsigned OpSize ) : ComparisonOpcode ( CmpOpcode ) , ReadFlagsOpcode ( FlagsOpcode ) , OperandRegBankID ( OpRegBank ) , OperandSize ( OpSize ) {


<s> cvtVSTwbFixed ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) {

Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;


<s> if ( frv_packet . num_insns > <NUM_LIT> && GET_CODE ( insn ) == INSN && GET_MODE ( insn ) == TImode && GET_CODE ( PATTERN ( insn ) ) != COND_EXEC ) return false ; if ( get_attr_type ( insn ) != TYPE_SETLO ) if ( frv_registers_conflict_p ( PATTERN ( insn ) ) ) return false ; return state_transition ( frv_packet . dfa_state , insn ) < <NUM_LIT> ;


<s> const TargetInstrInfo * TII = MF -> getSubtarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; * TLSBaseAddrReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , ++ MachineBasicBlock :: iterator ( I ) , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * TLSBaseAddrReg ) . addReg ( <STR_LIT> ) ;


<s> TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; const MCExpr * HiSym = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HI , MCSymbolRefExpr :: create ( <STR_LIT> , MCSymbolRefExpr :: VK_None , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: createExpr ( HiSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; const MCExpr * LoSym = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , MCSymbolRefExpr :: create ( <STR_LIT> , MCSymbolRefExpr :: VK_None , MCA . getContext ( ) ) , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: createExpr ( LoSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: createReg ( RegNo ) ) ;


<s> NoAutoPaddingScope ( MCStreamer & OS ) : OS ( OS ) , OldAllowAutoPadding ( OS . getAllowAutoPadding ( ) ) {


<s> auto Instr = Builder . buildInstr ( <STR_LIT> , { MI . getOperand ( <NUM_LIT> ) , & <STR_LIT> } , { } ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! constrainSelectedInstRegOperands ( * Instr , TII , TRI , RBI ) ) return false ;