<s> BEQ = <STR_LIT> ; } else { LL = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; SC = Subtarget . has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; AND = <STR_LIT> ; NOR = <STR_LIT> ; ZERO = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned StoreVal = RegInfo . createVirtualRegister ( RC ) ; unsigned AndRes = RegInfo . createVirtualRegister ( RC ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ;


<s> Reserved . set ( AC1 ) ; Reserved . set ( AV0 ) ; Reserved . set ( AV0S ) ; Reserved . set ( AV1 ) ; Reserved . set ( AV1S ) ; Reserved . set ( V ) ; Reserved . set ( VS ) ; Reserved . set ( CYCLES ) . set ( CYCLES2 ) ; Reserved . set ( L0 ) ; Reserved . set ( L1 ) ;


<s> static void PlaceMarkers ( MachineFunction & MF , const MachineLoopInfo & MLI , const <ISA_LIT>InstrInfo & TII , MachineDominatorTree & MDT , <ISA_LIT>FunctionInfo & MFI ) { SmallVector < MachineBasicBlock * , <NUM_LIT> > ScopeTops ( MF . getNumBlockIDs ( ) + <NUM_LIT> ) ; DenseMap < const MachineInstr * , MachineInstr * > LoopTops ; DenseMap < const MachineInstr * , MachineInstr * > BlockTops ; for ( auto & MBB : MF ) { PlaceLoopMarker ( MBB , MF , ScopeTops , LoopTops , TII , MLI ) ; PlaceBlockMarker ( MBB , MF , ScopeTops , BlockTops , LoopTops , TII , MLI , MDT , MFI ) ; } SmallVector < const MachineBasicBlock * , <NUM_LIT> > Stack ; for ( auto & MBB : reverse ( MF ) ) { for ( auto & MI : reverse ( MBB ) ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : assert ( ScopeTops [ Stack . back ( ) -> getNumber ( ) ] -> getNumber ( ) <= MBB . getNumber ( ) && <STR_LIT> ) ; Stack . pop_back ( ) ; break ; case <STR_LIT> : assert ( Stack . back ( ) == & MBB && <STR_LIT> ) ;


<s> if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; else if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( TT . isOSNaCl ( ) || ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ;

else if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ) Ret += <STR_LIT> ;


<s> unsigned getNumLocalDynamicTLSAccesses ( ) const {


<s> if ( std :: next ( I ) == I -> getParent ( ) -> end ( ) ) return false ;

return std :: next ( I ) -> getOpcode ( ) == <STR_LIT> ;


<s> static void buildPrologSpill ( LivePhysRegs & LiveRegs , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const <ISA_LIT>InstrInfo * TII , Register SpillReg , Register ScratchRsrcReg , Register SPReg , int FI ) { MachineFunction * MF = MBB . getParent ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; int64_t Offset = MFI . getObjectOffset ( FI ) ;

MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectAlign ( FI ) ) ;


<s> <ISA_LIT>LongBranchStub :: ~ <ISA_LIT>LongBranchStub ( ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , ELFArch ( <NUM_LIT> ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , m_hasMemMappedGPR ( false ) , m_FeatureSetDummy ( false ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) , TSInfo ( ) { ParseSubtargetFeatures ( CPU , FS ) ;


<s> CookieSet = false ; } else if ( CookieSet && MI -> isReturn ( ) ) { BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( CookieValue ) ; CookieSet = false ; } } if ( CookieSet ) { auto I = BB . getFirstTerminator ( ) ; DebugLoc DL ; if ( I != BB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( BB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( CookieValue ) ;


<s> static DecodeStatus decodeOperand_VS_32_Deferred ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) {

const auto * DAsm = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ;


<s> TYPE_PRECISION ( fpreg_type ) = <NUM_LIT> ; layout_type ( fpreg_type ) ; ( * lang_hooks . types . register_builtin_type ) ( fpreg_type , <STR_LIT> ) ; if ( float64x_type_node != NULL_TREE && TYPE_MODE ( float64x_type_node ) == XFmode ) float80_type = float64x_type_node ; else { float80_type = make_node ( REAL_TYPE ) ; TYPE_PRECISION ( float80_type ) = <NUM_LIT> ; layout_type ( float80_type ) ; } ( * lang_hooks . types . register_builtin_type ) ( float80_type , <STR_LIT> ) ; if ( ! TARGET_HPUX ) { tree ftype ; tree const_string_type = build_pointer_type ( build_qualified_type ( char_type_node , TYPE_QUAL_CONST ) ) ; ( * lang_hooks . types . register_builtin_type ) ( float128_type_node , <STR_LIT> ) ; ftype = build_function_type_list ( float128_type_node , NULL_TREE ) ; decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_INFQ , BUILT_IN_MD , NULL , NULL_TREE ) ; ia64_builtins [ IA64_BUILTIN_INFQ ] = decl ;

decl = add_builtin_function ( <STR_LIT> , ftype , IA64_BUILTIN_HUGE_VALQ , BUILT_IN_MD , NULL , NULL_TREE ) ;


<s> for ( int R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) PopMIB2 . addReg ( <STR_LIT> + R , RegState :: Define ) ; } else { MachineInstrBuilder PopMIB = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;

for ( int Reg = <STR_LIT> ; Reg < <STR_LIT> ; ++ Reg ) PopMIB . addReg ( Reg , RegState :: Define ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , GenExecuteOnly ( EnableExecuteOnly ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) , GISel ( ) {


<s> if ( M32R_INTERRUPT_P ( m32r_compute_function_type ( current_function_decl ) ) ) return FALSE ; if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( get_frame_size ( ) ) ; return current_frame_info . total_size == <NUM_LIT> ;


<s> static const AluKind IndexToID [ ] = { AluT_X , AluT_Y , AluT_Z , AluT_W } ; SUnit * SlotedSU = PopInst ( AvailableAlus [ IndexToID [ Slot ] ] , AnyAlu ) ; if ( SlotedSU ) return SlotedSU ;

SUnit * UnslotedSU = PopInst ( AvailableAlus [ AluAny ] , AnyAlu ) ;


<s> assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( ! Subtarget -> is<ISA_LIT>64 ( ) && ! Subtarget -> isDarwin ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) Kind = MCSymbolRefExpr :: VK_PLT ; const MCSymbolRefExpr * TlsRef = MCSymbolRefExpr :: Create ( TlsGetAddr , Kind , OutContext ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; const GlobalValue * GValue = MO . getGlobal ( ) ; MCSymbol * MOSymbol = getSymbol ( GValue ) ; const MCExpr * SymVar = MCSymbolRefExpr :: Create ( MOSymbol , VK , OutContext ) ; EmitToStreamer ( OutStreamer , MCInstBuilder ( Subtarget -> is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) . addExpr ( TlsRef ) . addExpr ( SymVar ) ) ;


<s> assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ;

return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info ) ;


<s> return decodeRegisterClass ( Inst , RegNo , <STR_LIT> ) ;


<s> int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n * UNITS_PER_WORD ;


<s> if ( mode == V2DFmode ) emit_insn ( gen_vsx_concat_v2df ( target , op0 , op1 ) ) ; else emit_insn ( gen_vsx_concat_v2di ( target , op0 , op1 ) ) ; } return ; } if ( mode == V4SFmode && VECTOR_MEM_VSX_P ( mode ) ) { if ( all_same ) { rtx freg = gen_reg_rtx ( V4SFmode ) ; rtx sreg = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; rtx cvt = ( ( TARGET_XSCVDPSPN ) ? gen_vsx_xscvdpspn_scalar ( freg , sreg ) : gen_vsx_xscvdpsp_scalar ( freg , sreg ) ) ; emit_insn ( cvt ) ; emit_insn ( gen_vsx_xxspltw_v4sf_direct ( target , freg , const0_rtx ) ) ; } else { rtx dbl_even = gen_reg_rtx ( V2DFmode ) ; rtx dbl_odd = gen_reg_rtx ( V2DFmode ) ; rtx flt_even = gen_reg_rtx ( V4SFmode ) ; rtx flt_odd = gen_reg_rtx ( V4SFmode ) ; rtx op0 = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; rtx op1 = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; rtx op2 = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; rtx op3 = force_reg ( SFmode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ; emit_insn ( gen_vsx_concat_v2sf ( dbl_even , op0 , op1 ) ) ; emit_insn ( gen_vsx_concat_v2sf ( dbl_odd , op2 , op3 ) ) ; emit_insn ( gen_vsx_xvcvdpsp ( flt_even , dbl_even ) ) ; emit_insn ( gen_vsx_xvcvdpsp ( flt_odd , dbl_odd ) ) ;

rs6000_expand_extract_even ( target , flt_even , flt_odd ) ;


<s> if ( ! RM . hasValue ( ) || JIT ) return Reloc :: Static ; return * RM ;


<s> unsigned HwLen = Subtarget . getVectorLength ( ) ; assert ( VecLen <= HwLen || VecLen == <NUM_LIT> * HwLen ) ; SmallVector < SDValue , <NUM_LIT> > Bytes ; if ( VecLen <= HwLen ) { assert ( HwLen % VecLen == <NUM_LIT> ) ; unsigned BitBytes = HwLen / VecLen ; for ( SDValue V : Values ) { SDValue Ext = ! V . isUndef ( ) ? DAG . getZExtOrTrunc ( V , dl , <STR_LIT> ) : DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; for ( unsigned B = <NUM_LIT> ; B != BitBytes ; ++ B ) Bytes . push_back ( Ext ) ; } } else { for ( unsigned I = <NUM_LIT> ; I != VecLen ; I += <NUM_LIT> ) { unsigned B = <NUM_LIT> ; for ( ; B != <NUM_LIT> ; ++ B ) { if ( ! Values [ I + B ] . isUndef ( ) ) break ; } SDValue F = Values [ I + B ] ; SDValue Ext = ( B < <NUM_LIT> ) ? DAG . getZExtOrTrunc ( F , dl , <STR_LIT> ) : DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; Bytes . push_back ( Ext ) ; for ( ; B != <NUM_LIT> ; ++ B ) assert ( Values [ I + B ] . isUndef ( ) || Values [ I + B ] == F ) ; } }

MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ;


<s> static HOST_WIDE_INT spu_constant_alignment ( const_tree , HOST_WIDE_INT align ) { return MAX ( align , <NUM_LIT> ) ;


<s> static inline unsigned regmask ( machine_mode mode , unsigned regno ) { return ( ( <NUM_LIT> << GET_MODE_SIZE ( as_a < fixed_size_mode > ( mode ) ) ) - <NUM_LIT> ) << regno ;


<s> case <STR_LIT> :: tc_6792d5ff : case <STR_LIT> :: tc_9c00ce8d : case <STR_LIT> :: tc_d580173f : case <STR_LIT> :: tc_f3eaa14b : return true ; default : return false ; }


<s> void addMemSrc10PreDecOperands ( MCInst & Inst , unsigned N ) const {


<s> auto FuncTypeEntry = llvm :: make_unique < BTFTypeFunc > ( SP -> getName ( ) , ProtoTypeId ) ; uint32_t FuncTypeId = addType ( std :: move ( FuncTypeEntry ) ) ; MCSymbol * FuncLabel = Asm -> getFunctionBegin ( ) ; BTFFuncInfo FuncInfo ; FuncInfo . Label = FuncLabel ; FuncInfo . TypeId = FuncTypeId ; if ( FuncLabel -> isInSection ( ) ) { MCSection & Section = FuncLabel -> getSection ( ) ; const MCSectionELF * SectionELF = dyn_cast < MCSectionELF > ( & Section ) ; assert ( SectionELF && <STR_LIT> ) ; SecNameOff = addString ( SectionELF -> getSectionName ( ) ) ; } else { SecNameOff = addString ( <STR_LIT> ) ; } FuncInfoTable [ SecNameOff ] . push_back ( FuncInfo ) ;


<s> case CallingConv :: <ISA_LIT>_LS : case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_ES : case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : return std :: make_pair ( <NUM_LIT> , getWavefrontSize ( ) ) ; default : return std :: make_pair ( <NUM_LIT> , <NUM_LIT> * getWavefrontSize ( ) ) ;


<s> if ( GET_CODE ( op ) != MEM ) return false ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; size = GET_MODE_SIZE ( mode ) ; if ( size > UNITS_PER_WORD ) return false ; addr = XEXP ( op , <NUM_LIT> ) ; if ( ! legitimate_small_data_address_p ( addr ) ) return false ; if ( ! short_p || size == <NUM_LIT> ) return true ; align = get_symbol_alignment ( addr ) ; switch ( mode ) { case E_HImode : mask = <NUM_LIT> ; break ; default :


<s> if ( Opcode == <STR_LIT> ) { assert ( MRI -> getRegClass ( PHIInput -> getOperand ( <NUM_LIT> ) . getReg ( ) ) == & <STR_LIT> && <STR_LIT> ) ; PHIOps . push_back ( { PHIInput -> getOperand ( <NUM_LIT> ) , PHI -> getOperand ( PHIOp + <NUM_LIT> ) } ) ; } else if ( Opcode == <STR_LIT> ) { Register AccReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * PHIInput -> getParent ( ) , PHIInput , PHIInput -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , AccReg ) ; PHIOps . push_back ( { MachineOperand :: CreateReg ( AccReg , false ) , PHI -> getOperand ( PHIOp + <NUM_LIT> ) } ) ; } else if ( Opcode == <STR_LIT> ) { assert ( ChangedPHIMap . count ( PHIInput ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * PrimedAccPHI = ChangedPHIMap . lookup ( PHIInput ) ; PHIOps . push_back ( { MachineOperand :: CreateReg ( PrimedAccPHI -> getOperand ( <NUM_LIT> ) . getReg ( ) , false ) , PHI -> getOperand ( PHIOp + <NUM_LIT> ) } ) ; } }


<s> if ( ! reg_classes_intersect_p ( to , GENERAL_REGS ) ) rclass = to ; if ( rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS ) ret = ( rs6000_memory_move_cost ( mode , rclass , false ) + rs6000_memory_move_cost ( mode , GENERAL_REGS , false ) ) ; else if ( rclass == CR_REGS ) ret = <NUM_LIT> ; else if ( ( rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7 || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 ) && reg_classes_intersect_p ( rclass , LINK_OR_CTR_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; else ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; } else if ( VECTOR_MEM_VSX_P ( mode ) && reg_classes_intersect_p ( to , VSX_REGS ) && reg_classes_intersect_p ( from , VSX_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( FIRST_FPR_REGNO , mode ) ; else if ( reg_classes_intersect_p ( to , from ) ) ret = ( FLOAT128_2REG_P ( mode ) ) ? <NUM_LIT> : <NUM_LIT> ; else ret = ( rs6000_register_move_cost ( mode , GENERAL_REGS , to ) + rs6000_register_move_cost ( mode , from , GENERAL_REGS ) ) ; if ( TARGET_DEBUG_COST ) { if ( dbg_cost_ctrl == <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , ret , GET_MODE_NAME ( mode ) , reg_class_names [ from ] , reg_class_names [ to ] ) ;


<s> Asm -> emitLabelReference ( std :: get < <NUM_LIT> > ( V ) , <NUM_LIT> ) ; OS . emitIntValue ( std :: get < <NUM_LIT> > ( V ) , <NUM_LIT> ) ;


<s> NodeSet ( const ImmutableGraph & G , bool ContainsAll = false ) : G { G , V { static_cast < unsigned > ( G . nodes_size ( ) ) , ContainsAll { } bool insert ( const Node & N ) { size_type Idx = G . getNodeIndex ( N ) ; bool AlreadyExists = V . test ( Idx ) ; V . set ( Idx ) ; return ! AlreadyExists ; } void erase ( const Node & N ) { size_type Idx = G . getNodeIndex ( N ) ; V . reset ( Idx ) ; } bool contains ( const Node & N ) const { size_type Idx = G . getNodeIndex ( N ) ;


<s> return false ; } if ( getFrameIndexAddress ( AM , SDLoc ( N ) , Disp , Base ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } if ( AM . hasIndexReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! AM . hasBaseReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( getSymbolicDisplacement ( AM , SDLoc ( N ) , Disp ) ) { assert ( ! AM . Disp && <STR_LIT> ) ;


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; }


<s> if ( ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Base -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; if ( ReplaceFlags ) { if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { SDLoc dl ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; if ( GV -> getAlignment ( ) < <NUM_LIT> && ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } ImmOpnd = CurDAG -> getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , Flags ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( ImmOpnd ) ) { const Constant * C = CP -> getConstVal ( ) ; ImmOpnd = CurDAG -> getTargetConstantPool ( C , <STR_LIT> , CP -> getAlignment ( ) , <NUM_LIT> , Flags ) ; } } if ( FirstOp == <NUM_LIT> ) ( void ) CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , ImmOpnd , Base . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; else ( void ) CurDAG -> UpdateNodeOperands ( N , ImmOpnd , Base . getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ;

if ( Base . getNode ( ) -> use_empty ( ) ) CurDAG -> RemoveDeadNode ( Base . getNode ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( shiftLo >> <NUM_LIT> == <NUM_LIT> ) return Fail ; DecodeGPR32RegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rn , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rm , Addr , Decoder ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( shiftHi == <NUM_LIT> ) return Fail ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ;


<s> if ( ConstraintVT . isVector ( ) && Subtarget -> hasNEON ( ) && ( ConstraintVT . getSizeInBits ( ) == <NUM_LIT> || ConstraintVT . getSizeInBits ( ) == <NUM_LIT> ) ) return <STR_LIT> ; return <STR_LIT> ;


<s> bool <ISA_LIT>DummyPA :: checkFrameDestroy ( MachineBasicBlock & MBB , MachineInstr & MI ) { return true ;


<s> for ( MCSuperRegIterator SR ( DefMO . getReg ( ) , & RI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = DefMI . findRegisterDefOperandIdx ( * SR , false , false , & RI ) ; if ( Idx != - <NUM_LIT> ) { DefIdx = Idx ; break ; } } } MachineOperand UseMO = UseMI . getOperand ( UseIdx ) ; if ( UseMO . isImplicit ( ) ) { for ( MCSuperRegIterator SR ( UseMO . getReg ( ) , & RI ) ; SR . isValid ( ) ; ++ SR ) { int Idx = UseMI . findRegisterUseOperandIdx ( * SR , false , & RI ) ; if ( Idx != - <NUM_LIT> ) { UseIdx = Idx ; break ; } } } } return TargetInstrInfo :: getOperandLatency ( ItinData , DefMI , DefIdx , UseMI , UseIdx ) ;


<s> return ( can_create_pseudo_p ( ) ? emit_move_insn ( dest , src ) : emit_move_insn_1 ( dest , src ) ) ;


<s> else if ( VT == <STR_LIT> ) IsLegal = <STR_LIT> ( ImmInt ) != - <NUM_LIT> || Imm . isPosZero ( ) ; else if ( VT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) IsLegal = <STR_LIT> ( ImmInt ) != - <NUM_LIT> || Imm . isPosZero ( ) ; if ( ! IsLegal && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) IsLegal = <STR_LIT> ( ImmInt . getZExtValue ( ) , VT . getSizeInBits ( ) ) ; LLVM_DEBUG ( dbgs ( ) << ( IsLegal ? <STR_LIT> : <STR_LIT> ) << VT . getEVTString ( ) << <STR_LIT> ; Imm . dump ( ) ; ) ; return IsLegal ;


<s> return getWavesPerWorkGroup ( STI , FlatWorkGroupSize ) ;


<s> static HOST_WIDE_INT arg_area_size ( void ) { if ( current_function_outgoing_args_size ) { if ( current_function_outgoing_args_size >= FIXED_STACK_AREA ) return current_function_outgoing_args_size ; else return FIXED_STACK_AREA ; }


<s> assert ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ;


<s> FunctionPass * llvm :: createAMDGPUISelDag ( TargetMachine & TM ) {


<s> MachineBasicBlock :: iterator DefMI = MRI -> getVRegDef ( Reg ) ; if ( ( DefMI -> getOpcode ( ) != <STR_LIT> && DefMI -> getOpcode ( ) != <STR_LIT> ) || DefMI -> getParent ( ) != FrameSetup -> getParent ( ) ) return nullptr ;

for ( auto I = DefMI ; I != FrameSetup ; ++ I ) if ( I -> isLoadFoldBarrier ( ) ) return nullptr ;


<s> if ( SDValue Folded = foldFreeOpFromSelect ( DCI , SDValue ( N , <NUM_LIT> ) ) ) return Folded ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue RHS = Cond . getOperand ( <NUM_LIT> ) ; SDValue CC = Cond . getOperand ( <NUM_LIT> ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ; SDValue False = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . hasOneUse ( ) ) { SelectionDAG & DAG = DCI . DAG ; if ( ( DAG . isConstantValueOfAnyType ( True ) || DAG . isConstantValueOfAnyType ( True ) ) && ( ! DAG . isConstantValueOfAnyType ( False ) && ! DAG . isConstantValueOfAnyType ( False ) ) ) { SDLoc SL ( N ) ; <STR_LIT> NewCC = getSetCCInverse ( cast < CondCodeSDNode > ( CC ) -> get ( ) , LHS . getValueType ( ) . isInteger ( ) ) ; SDValue NewCond = DAG . getSetCC ( SL , Cond . getValueType ( ) , LHS , RHS , NewCC ) ; return DAG . getNode ( <STR_LIT> , SL , VT , NewCond , False , True ) ; } }

if ( VT == <STR_LIT> && Cond . hasOneUse ( ) ) {


<s> void <ISA_LIT>MCAsmStreamer :: BeginCOFFSymbolDef ( const MCSymbol * Symbol ) {


<s> switch ( CallingConv ) { default : return false ; case CallingConv :: <ISA_LIT>_StdCall : return ! Subtarget -> is64Bit ( ) ; case CallingConv :: <ISA_LIT>_FastCall : return ! Subtarget -> is64Bit ( ) ;


<s> unsigned BitWidth = VT . getSizeInBits ( ) ; ( void ) BitWidth ; assert ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> ) ; KnownBits Known = CurDAG -> computeKnownBits ( Op ) ; uint64_t NonZeroBits = ( ~ Known . Zero ) . getZExtValue ( ) ; uint64_t AndImm ; if ( isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , AndImm ) ) { assert ( ( ~ APInt ( BitWidth , AndImm ) & ~ Known . Zero ) == <NUM_LIT> ) ; Op = Op . getOperand ( <NUM_LIT> ) ; } if ( ! BiggerPattern && ! Op . hasOneUse ( ) ) return false ; uint64_t ShlImm ; if ( ! isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , ShlImm ) ) return false ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( ! isShiftedMask_64 ( NonZeroBits ) ) return false ; ShiftAmount = countTrailingZeros ( NonZeroBits ) ; MaskWidth = countTrailingOnes ( NonZeroBits >> ShiftAmount ) ; if ( ShlImm - ShiftAmount != <NUM_LIT> && ! BiggerPattern ) return false ; Src = getLeftShift ( CurDAG , Op , ShlImm - ShiftAmount ) ; return true ;


<s> static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;


<s> if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) {


<s> MachineInstrBuilder MIB = BuildMI ( MBB , I , MBB . findDebugLoc ( I ) , get ( Opcode ) , DstReg ) ; if ( Src1Reg ) { MIB . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } MIB . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( Src0Reg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && ( MMI . hasDebugInfo ( ) || F . needsUnwindTableEntry ( ) ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , InsertPos , true ) ; StackAdjustment += mergeSPUpdates ( MBB , InsertPos , false ) ;


<s> BlackfinTargetMachine :: BlackfinTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) {


<s> FunctionPass * llvm :: create<ISA_LIT>StorePairSuppressPass ( ) {

return new <ISA_LIT>StorePairSuppress ( ) ;


<s> switch ( Kind ) { case FK_Data_4 : case FK_PCRel_4 : return RT_32 ; case FK_PCRel_2 : case FK_Data_2 : return RT_16 ;


<s> } if ( ! reg_dead_after_insn ( m_ccreg , e . cstore . insn ) && ! reg_unused_after_insn ( m_ccreg , e . cstore . insn ) ) { log_msg ( <STR_LIT> ) ; log_insn ( e . cstore . insn ) ; log_return ( false , <STR_LIT> ) ; }

if ( multiple_sets ( e . setcc . insn ) ) {


<s> for ( unsigned i = <NUM_LIT> , e = II -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = II -> getOperand ( i ) ; if ( MO . isRegMask ( ) && MO . clobbersPhysReg ( <STR_LIT> ) ) { UseMI = II ; done = true ; break ; } if ( ! MO . isReg ( ) || MO . isUndef ( ) || ! MO . getReg ( ) || TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) continue ; if ( MO . getReg ( ) == <STR_LIT> ) { UseMI = II ; done = true ; break ; } }


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> SmallSet < unsigned , <NUM_LIT> > RegDefs ; SmallSet < unsigned , <NUM_LIT> > RegUses ; bool sawLoad = false ; bool sawStore = false ; if ( slot == MBB . begin ( ) ) return MBB . end ( ) ; if ( slot -> getOpcode ( ) == <STR_LIT> ) return MBB . end ( ) ; if ( slot -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator J = slot ; -- J ;

if ( J -> getOpcode ( ) == <STR_LIT> || J -> getOpcode ( ) == <STR_LIT> ) {


<s> if ( OpReg == <NUM_LIT> ) return false ; unsigned ImplicitDefReg ; if ( HasAVX ) { ImplicitDefReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: IMPLICIT_DEF ) , ImplicitDefReg ) ; } unsigned ResultReg = createResultReg ( RC ) ;


<s> static rtx m68k_function_arg ( cumulative_args_t , const function_arg_info & ) { return NULL_RTX ;


<s> } if ( ! CCMatch ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; <ISA_LIT>CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs1 , * DAG . getContext ( ) , Call ) ; CCInfo1 . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CalleeCC , true , isVarArg ) ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; <ISA_LIT>CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , RVLocs2 , * DAG . getContext ( ) , Call ) ; CCInfo2 . AnalyzeCallResult ( Ins , CCAssignFnForNode ( CallerCC , true , isVarArg ) ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } const <ISA_LIT>FunctionInfo * AFI_Caller = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( CalleeCC , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) , Call ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForNode ( CalleeCC , false , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , realArgIdx = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ realArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ realArgIdx ] ; <STR_LIT> Flags = Outs [ realArgIdx ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ;


<s> ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg2 = MIB . getReg ( <NUM_LIT> ) ; ( void ) VReg2 ; assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . add ( predOps ( <STR_LIT> ) ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const {


<s> void <ISA_LIT>SEInstrInfo :: expandRetRA ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned Opc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) ) . addReg ( <STR_LIT> ) ;


<s> if ( Subtarget -> isTargetLinux ( ) ) return new <ISA_LIT>LinuxTargetObjectFile ( ) ; if ( Subtarget -> isTargetNaCl ( ) ) return new TargetLoweringObjectFileNaCl ( ) ; if ( Subtarget -> isTargetELF ( ) ) return new TargetLoweringObjectFileELF ( ) ; if ( Subtarget -> isTargetCOFF ( ) && ! Subtarget -> isTargetEnvMacho ( ) ) return new TargetLoweringObjectFileCOFF ( ) ;


<s> if ( CSI . empty ( ) ) return false ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ; AddDefaultPred ( MIB ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return & APFloat :: IEEEdouble ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


return ( int16_t ) __builtin_aarch64_sqmovunsi ( __a ) ;


<s> MIB = BuildMI ( MBB , llvm :: next ( I ) , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( Divisor . getReg ( ) , getKillRegState ( Divisor . isKill ( ) ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Is64Bit ) MIB -> getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; Divisor . setIsKill ( false ) ; return & MBB ;


<s> const SmallVectorImpl < MachineBasicBlock * > & predecessors ( ) const {


<s> } MII = MBB -> erase ( MI ) ; -- MII ; break ; } case <STR_LIT> : case <STR_LIT> : { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int SrcReg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg != SrcReg1 ) { BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SrcReg1 ) ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addFPImm ( MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) ) ; } MII = MBB -> erase ( MI ) ; -- MII ; break ; } case <STR_LIT> : case <STR_LIT> : { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int SrcReg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addFPImm ( MI -> getOperand ( <NUM_LIT> ) . getFPImm ( ) ) ; } if ( DestReg != SrcReg2 ) { BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SrcReg2 ) ; } MII = MBB -> erase ( MI ) ; -- MII ; break ; } case <STR_LIT> : case <STR_LIT> : { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int SrcReg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; return n8_consumed_by_addr_in_p ( consumer , def_reg ) ;


<s> PredicateInstruction ( MachineInstr * MI , const SmallVectorImpl < MachineOperand > & Pred ) const { if ( Pred . size ( ) < <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ;

int i = MI -> findFirstPredOperandIdx ( ) ;


<s> for ( tree list = SH_ATTRIBUTES ( func ) ; list ; list = TREE_CHAIN ( list ) ) if ( is_attribute_p ( <STR_LIT> , get_attribute_name ( list ) ) ) return true ;


<s> MachineInstr & Instr = II ; if ( ! Instr . isPHI ( ) ) break ; int numPreds = getPHINumInputs ( Instr ) ; for ( int i = <NUM_LIT> ; i < numPreds ; ++ i ) { auto Pred = getPHIPred ( Instr , i ) ; if ( Pred == Exit ) { setPhiPred ( Instr , i , NewExit ) ; } } } return NewExit ;


<s> bool isInstSegCvt ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> <ISA_LIT>ConstantPoolValue :: <ISA_LIT>ConstantPoolValue ( GlobalValue * gv , const char * Modif ) : MachineConstantPoolValue ( ( const Type * ) Type :: getInt32Ty ( gv -> getContext ( ) ) ) , CVal ( gv ) , S ( NULL ) , LabelId ( <NUM_LIT> ) , Kind ( <STR_LIT> ) , PCAdjust ( <NUM_LIT> ) , Modifier ( Modif ) {


<s> if ( LoadSDNode * ChainLD = dyn_cast < LoadSDNode > ( ChainNext ) ) { if ( isConsecutiveLS ( ChainLD , LD , VT . getStoreSize ( ) , <NUM_LIT> , DAG ) ) return true ; if ( ! Visited . count ( ChainLD -> getChain ( ) . getNode ( ) ) ) Queue . push_back ( ChainLD -> getChain ( ) . getNode ( ) ) ; } else if ( ChainNext -> getOpcode ( ) == <STR_LIT> ) { for ( SDNode :: op_iterator O = ChainNext -> op_begin ( ) , OE = ChainNext -> op_end ( ) ; O != OE ; ++ O ) if ( ! Visited . count ( O -> getNode ( ) ) ) Queue . push_back ( O -> getNode ( ) ) ; } else LoadRoots . insert ( ChainNext ) ; } Visited . clear ( ) ;


<s> machine_mode dest_mode = GET_MODE ( dest ) ; enum rtx_code rcode = GET_CODE ( cond ) ; rtx mask ; mask = spu_emit_vector_compare ( rcode , cc_op0 , cc_op1 , dest_mode ) ;

emit_insn ( gen_selb ( dest , op2 , op1 , mask ) ) ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Immediate ) ; Op -> Imm . Val = Val ;


<s> Chain = CLI . DAG . getCopyToReg ( Chain , CLI . DL , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . CallConv ) ; assert ( Mask && <STR_LIT> ) ;

if ( Subtarget -> in<ISA_LIT>16HardFloat ( ) ) {


<s> bool empty ( ) const { return ! notEmpty ( ) ;


Owner . Addr -> addMember ( BA , * this ) ;


<s> for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { stmt = gsi_stmt ( gsi ) ; if ( is_gimple_call ( stmt ) ) { called_fn_tree = gimple_call_fndecl ( stmt ) ; if ( called_fn_tree != NULL ) { called_fn = DECL_STRUCT_FUNCTION ( called_fn_tree ) ; if ( called_fn != NULL ) called_fn -> machine -> callers_may_not_allocate_frame = true ;


<s> MVT PtrVT = <STR_LIT> ( TM . createDataLayout ( ) . getPointerSizeInBits ( ) ) ; if ( Results . size ( ) > <NUM_LIT> && ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ContextFunc ) . hasMultivalue ( ) ) { Results . clear ( ) ; Params . push_back ( PtrVT ) ; } for ( auto * Param : Ty -> params ( ) ) computeLegalValueVTs ( ContextFunc , TM , Param , Params ) ; if ( Ty -> isVarArg ( ) ) Params . push_back ( PtrVT ) ; if ( TargetFunc && TargetFunc -> getCallingConv ( ) == CallingConv :: Swift ) { MVT PtrVT = <STR_LIT> ( TM . createDataLayout ( ) . getPointerSizeInBits ( ) ) ; bool HasSwiftErrorArg = false ;


<s> case RAW_UAV_ID : case ARENA_UAV_ID : break ; case LDS_ID : if ( usesHardware ( <STR_LIT> ) ) { return DEFAULT_LDS_ID ; } break ; case SCRATCH_ID : if ( usesHardware ( <STR_LIT> ) ) { return DEFAULT_SCRATCH_ID ; } break ; case GDS_ID : assert ( <NUM_LIT> && <STR_LIT> ) ; if ( usesHardware ( <STR_LIT> ) ) { return DEFAULT_GDS_ID ; }


<s> ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregoiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregoiv2di ( __o , <NUM_LIT> ) ;


<s> ErrMsg = <STR_LIT> ; return true ; } IC . popOperator ( ) ; } else if ( ( PrevState == IES_PLUS || PrevState == IES_MINUS || PrevState == IES_OR || PrevState == IES_AND || PrevState == IES_LSHIFT || PrevState == IES_RSHIFT || PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE || PrevState == IES_LPAREN || PrevState == IES_LBRAC ) && CurrState == IES_MINUS ) { IC . pushOperand ( IC_IMM , - TmpInt ) ; } else {


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( isFrameStoreOpcode ( MI . getOpcode ( ) ) && ! MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) && isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( mop . isImm ( ) && ( mop . getImm ( ) < - <NUM_LIT> || mop . getImm ( ) > <NUM_LIT> ) ) return true ; if ( mop . isGlobal ( ) || mop . isSymbol ( ) || mop . isJTI ( ) || mop . isCPI ( ) ) return true ;


<s> if ( reg2 == HARD_Z_REGNUM ) return <NUM_LIT> ; if ( TARGET_M6811 && reg2 == HARD_Y_REGNUM && ( D_REGNO_P ( reg1 ) || X_REGNO_P ( reg1 ) ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! I -> getType ( ) -> isDoubleTy ( ) || ! V -> getType ( ) -> isFloatTy ( ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; UpdateValueMap ( I , Result ) ;


<s> bool <ISA_LIT>AsmParser :: missingFeature ( llvm :: SMLoc const & Loc , uint64_t const & ErrorInfo ) {


<s> if ( ! GVA ) return false ; if ( ! LocalSData && GV -> hasLocalLinkage ( ) ) return false ;

if ( ! ExternSData && ( ( GV -> hasExternalLinkage ( ) && GV -> isDeclaration ( ) ) || GV -> hasCommonLinkage ( ) ) ) return false ;


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( MachineInstr & MI ) const { if ( MI . getOpcode ( ) == <STR_LIT> ) { return false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( MI . getParent ( ) -> begin ( ) != MachineBasicBlock :: iterator ( MI ) ) return false ; return MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { auto DL = DAG . getDataLayout ( ) ;

const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ;


<s> static void EmitNops ( MCStreamer & OS , unsigned NumBytes , bool Is64Bit , const MCSubtargetInfo & STI ) { unsigned NopsToEmit = NumBytes ; ( void ) NopsToEmit ; while ( NumBytes ) {

NumBytes -= EmitNop ( OS , NumBytes , Is64Bit , STI ) ;


<s> if ( Mask != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N00 , DAG . getConstant ( Mask , VT ) ) ; } } if ( isSplatVector ( N1 . getNode ( ) ) ) { assert ( N0 . getValueType ( ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( N1C && ( <NUM_LIT> == N1C -> getZExtValue ( ) ) ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 , N0 ) ; } }


<s> if ( ( I -> mayStore ( ) ) && std :: next ( I ) != E && I != MBB -> begin ( ) ) { MachineBasicBlock * newBB = splitBlockAfterInstr ( I , MF ) ; newBB -> setHasAddressTaken ( ) ; break ; } if ( ( I -> mayStore ( ) ) && std :: next ( I ) == E && I != MBB -> begin ( ) ) { MachineBasicBlock * newBB = MF . CreateMachineBasicBlock ( ( I -> getParent ( ) ) -> getBasicBlock ( ) ) ; MachineFunction :: iterator It = MBB -> getIterator ( ) ; if ( It != MF . end ( ) ) MF . insert ( It , newBB ) ; else MF . push_back ( newBB ) ; newBB -> splice ( newBB -> end ( ) , I -> getParent ( ) , I ) ;


<s> if ( AGGREGATE_TYPE_P ( type ) ) return true ; size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; return size > <NUM_LIT> * <NUM_LIT> ;


<s> MCWinCOFFObjectTargetWriter * MOTW = new <ISA_LIT>WinCOFFObjectWriter ( ) ; return createWinCOFFObjectWriter ( MOTW , OS ) ;


<s> NodeCircle . push_back ( Node ) ; length ++ ;


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ;


<s> __arm_sqshll ( int64_t value , const int shift ) { return __builtin_mve_sqshll_di ( value , shift ) ;


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ;

assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> switch_to_section ( sbss_section ) ; break ; case DATA_AREA_TDA : switch_to_section ( tdata_section ) ; default : switch_to_section ( bss_section ) ; break ; } ASM_OUTPUT_ALIGN ( file , floor_log2 ( align / BITS_PER_UNIT ) ) ;


<s> MVT VT = Op1 . getSimpleValueType ( ) ; MVT EVT = VT . getVectorElementType ( ) ; unsigned n = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > ULTOp1 ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) { ConstantSDNode * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getValueType ( <NUM_LIT> ) != EVT ) return SDValue ( ) ; APInt Val = Elt -> getAPIntValue ( ) ; if ( Val == <NUM_LIT> ) return SDValue ( ) ; ULTOp1 . push_back ( DAG . getConstant ( Val - <NUM_LIT> , dl , EVT ) ) ; }

return DAG . getNode ( <STR_LIT> , dl , VT , ULTOp1 ) ;


<s> int Opcode = MI -> getOpcode ( ) ; switch ( Opcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ; case <STR_LIT> : case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false ;


<s> void <ISA_LIT>FunctionInfo :: createISRRegFI ( ) { const TargetRegisterClass * RC = & <STR_LIT> ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) ISRDataRegFI [ I ] = MF . getFrameInfo ( ) . CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ;


<s> if ( I -> mayStore ( ) ) { DebugLoc DL3 = MBB -> findDebugLoc ( I ) ; int storeOpcode = I -> getOpcode ( ) ; int loadOpcode = <NUM_LIT> ; int cmpOpcode = <NUM_LIT> ; switch ( storeOpcode ) { case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } case <STR_LIT> : { loadOpcode = <STR_LIT> ; cmpOpcode = <STR_LIT> ; break ; } default : { errs ( ) << <STR_LIT> ; check = false ; } } if ( check ) { assert ( loadOpcode != <NUM_LIT> ) ; assert ( cmpOpcode != <NUM_LIT> ) ; MachineInstr * MIload = BuildMI ( MF , DL3 , TII -> get ( loadOpcode ) ) ;


<s> return ( int64x1_t ) { __builtin_aarch64_ssri_ndi ( __a [ <NUM_LIT> ] , __b [ <NUM_LIT> ] , __c ) } ;


<s> static bool rs6000_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { return rs6000_mode_dependent_address_ptr ( addr ) ;


<s> GCNUpwardRPTracker ( const LiveIntervals & LIS_ ) : GCNRPTracker ( LIS_ ) {


<s> MCSymbol * Sym = Printer . getSymbol ( Global ) ; if ( isa < MCSymbolELF > ( Sym ) ) return Sym ; MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Sym ) ; if ( const auto * FuncTy = dyn_cast < FunctionType > ( Global -> getValueType ( ) ) ) { const MachineFunction & MF = * MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const Function & CurrentFunc = MF . getFunction ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Returns ; SmallVector < <STR_LIT> , <NUM_LIT> > Params ; <STR_LIT> iPTR = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAddr64 ( ) ? <STR_LIT> :: I64 : <STR_LIT> :: I32 ; SmallVector < MVT , <NUM_LIT> > ResultMVTs ; ComputeLegalValueVTs ( CurrentFunc , TM , FuncTy -> getReturnType ( ) , ResultMVTs ) ; if ( ResultMVTs . size ( ) <= <NUM_LIT> ) for ( MVT ResultMVT : ResultMVTs ) Returns . push_back ( <STR_LIT> ( ResultMVT ) ) ; else Params . push_back ( iPTR ) ; for ( Type * Ty : FuncTy -> params ( ) ) { SmallVector < MVT , <NUM_LIT> > ParamMVTs ;

ComputeLegalValueVTs ( CurrentFunc , TM , Ty , ParamMVTs ) ;


<s> return ! <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && usesVertexCache ( MI . getOpcode ( ) ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( StackDirection D , unsigned StackAl , int LAO , unsigned TransAl ) : TargetFrameLowering ( D , StackAl , LAO , TransAl ) {


<s> TRC = & <STR_LIT> ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { TRC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned NewReg = RegInfo . createVirtualRegister ( TRC ) ; return NewReg ;


<s> int64_t MaxValue = ( <NUM_LIT> << Info . TargetSize ) - <NUM_LIT> ; bool Evaluated = false ; int64_t Constant = <NUM_LIT> ; Evaluated = MME -> evaluateAsConstant ( Constant ) ; if ( Evaluated && Constant > <NUM_LIT> ) { return ( Constant <= MaxValue ) ; } return ( MaxValue <= High ) ; } const auto * SRE = dyn_cast < MCSymbolRefExpr > ( getImm ( ) ) ; if ( SRE ) { return true ; }

const auto * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> static ArgDescriptor allocateVGPR32Input ( CCState & CCInfo , unsigned Mask = ~ <NUM_LIT> , ArgDescriptor Arg = ArgDescriptor ( ) ) { if ( Arg . isSet ( ) ) return ArgDescriptor :: createArg ( Arg , Mask ) ; ArrayRef < MCPhysReg > ArgVGPRs = makeArrayRef ( <STR_LIT> . begin ( ) , <NUM_LIT> ) ; unsigned RegIdx = CCInfo . getFirstUnallocated ( ArgVGPRs ) ; if ( RegIdx == ArgVGPRs . size ( ) ) { int64_t Offset = CCInfo . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; return ArgDescriptor :: createStack ( Offset , Mask ) ;


<s> if ( Other . size ( ) != size ( ) ) return false ; ChainOfDependences & OtherChain = Other . getChain ( ) ; for ( int i = <NUM_LIT> ; i < size ( ) ; ++ i ) { if ( Chain [ i ] != OtherChain [ i ] ) return false ; } return true ;


<s> switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : break ; case 'P' : printMemReference ( MI , OpNo , <STR_LIT> ) ; return false ; } } printMemReference ( MI , OpNo ) ; return false ;


<s> if ( ! CE ) return false ; int64_t Value = ~ CE -> getValue ( ) ;

return ( Value >= <NUM_LIT> && Value < <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> && ( Value & <NUM_LIT> ) == <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> && ( Value & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> explicit <ISA_LIT>ompactFunctionInfo ( MachineFunction & MF ) : VarArgsRegSaveSize ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) {


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + <NUM_LIT> ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case E_V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case E_V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case E_V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case E_V8HFmode : gen = gen_neon_vtrnv8hf_internal ; break ; case E_V4HFmode : gen = gen_neon_vtrnv4hf_internal ; break ; case E_V4SImode : gen = gen_neon_vtrnv4si_internal ; break ; case E_V2SImode : gen = gen_neon_vtrnv2si_internal ; break ; case E_V2SFmode : gen = gen_neon_vtrnv2sf_internal ; break ; case E_V4SFmode : gen = gen_neon_vtrnv4sf_internal ; break ; default : gcc_unreachable ( ) ; } in0 = d -> op0 ;


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const {


<s> RegisterId SuperReg = RegInfos [ RR . Reg ] . MaxSuper ; if ( RR . Reg == SuperReg ) return RR ; const TargetRegisterClass * RC = RegInfos [ RR . Reg ] . RegClass ; LaneBitmask RCMask = RC != nullptr ? RC -> LaneMask : LaneBitmask ( <NUM_LIT> ) ; LaneBitmask Common = RR . Mask & RCMask ; uint32_t Sub = TRI . getSubRegIndex ( SuperReg , RR . Reg ) ; LaneBitmask SuperMask = TRI . composeSubRegIndexLaneMask ( Sub , Common ) ; assert ( RR . Mask . none ( ) || SuperMask . any ( ) ) ; return RegisterRef ( SuperReg , SuperMask ) ;


<s> const InstrItineraryData & getInstItineraryData ( ) const { return InstrItins ;


<s> <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == INT32_MIN ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val ) ; Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ;


<s> OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ; unsigned UsedRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { if ( Op -> isImm ( ) ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( UsedRegs [ I ] ) . addImm ( Op -> getImm ( ) ) ) ; else if ( Op -> isReg ( ) ) { if ( Op -> getReg ( ) != UsedRegs [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( UsedRegs [ I ] ) . addReg ( Op -> getReg ( ) ) ) ; else EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; }


<s> } assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ;

if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ;


<s> BlockIt MBBI = MBB . begin ( ) , E = MBB . end ( ) ;


<s> SDLoc DL ( Op ) ; LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; if ( Op . getValueType ( ) . isVector ( ) ) { assert ( Op . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned NumElements = Op . getValueType ( ) . getVectorNumElements ( ) ; assert ( NumElements != <NUM_LIT> && <STR_LIT> ) ; switch ( Load -> getAddressSpace ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( NumElements <= <NUM_LIT> ) break ; case <STR_LIT> :

return ScalarizeVectorLoad ( Op , DAG ) ;


<s> return isTargetMingw ( ) || isTargetCygwin ( ) ;


<s> unsigned InOpcode = InVec . getOpcode ( ) ; if ( OpVT == <STR_LIT> && InVec . getValueType ( ) == <STR_LIT> ) { if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , OpVT , InVec . getOperand ( <NUM_LIT> ) ) ; } if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , OpVT , InVec . getOperand ( <NUM_LIT> ) ) ; } } if ( ( InOpcode == <STR_LIT> || InOpcode == <STR_LIT> ) && OpVT . is128BitVector ( ) && InVec . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . is128BitVector ( ) ) { unsigned ExtOp = InOpcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( ExtOp , SDLoc ( N ) , OpVT , InVec . getOperand ( <NUM_LIT> ) ) ; } }


<s> bool shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const override { return true ;


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > MaskVec ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { int idx = SVOp -> getMaskElt ( i ) ; if ( idx < <NUM_LIT> ) MaskVec . push_back ( idx ) ; else if ( idx < ( int ) NumElems ) MaskVec . push_back ( idx + NumElems ) ; else MaskVec . push_back ( idx - NumElems ) ; }

return DAG . getVectorShuffle ( VT , SVOp -> getDebugLoc ( ) , SVOp -> getOperand ( <NUM_LIT> ) , SVOp -> getOperand ( <NUM_LIT> ) , & MaskVec [ <NUM_LIT> ] ) ;


<s> Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ;


<s> pextrh_u ( uint16x4_t s , int field ) {

return __builtin_loongson_pextrh_u ( s , field ) ;


<s> if ( ( <STR_LIT> ( STI ) || <STR_LIT> ( STI ) ) && ( STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA || STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; getTargetStreamer ( ) -> EmitCodeEnd ( STI ) ;


<s> ops [ <NUM_LIT> ] = op1 ; if ( op1 == const0_rtx && ( TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P ( op0 ) ) ) output_asm_insn ( <STR_LIT> , ops ) ; else if ( GET_CODE ( op0 ) == MEM && GET_CODE ( op1 ) == MEM ) output_asm_insn ( <STR_LIT> , ops ) ; else if ( REG_P ( op1 ) || ( ! REG_P ( op0 ) && GET_CODE ( op0 ) != MEM ) ) { output_asm_insn ( <STR_LIT> , ops ) ; std :: swap ( flags_compare_op0 , flags_compare_op1 ) ; return swap_condition ( code ) ;


<s> Policy . OnlyTopDown = false ; Policy . OnlyBottomUp = false ;

if ( isCyclone ( ) ) Policy . DisableLatencyHeuristic = true ;


return ( __m128i ) __builtin_ia32_pmovusdw128_mask ( ( __v4si ) __A , ( __v8hi ) _mm_setzero_si128 ( ) , __M ) ;


<s> } if ( reader -> fileName ( ) != filename ) { delete reader ; reader = new LineReader ( filename ) ; } return reader ;


<s> if ( MEM_P ( mem1 ) && MEM_P ( mem2 ) && get_memref_parts ( mem1 , & reg1 , & off1 , & size1 ) && get_memref_parts ( mem2 , & reg2 , & off2 , & size2 ) && REGNO ( reg1 ) == REGNO ( reg2 ) ) { if ( off1 + size1 == off2 ) return mem1 ; else if ( off2 + size2 == off1 ) return mem2 ; }


<s> MachineSDNode * <ISA_LIT>TargetLowering :: wrapAddr64Rsrc ( SelectionDAG & DAG , const SDLoc & DL , SDValue Ptr ) const { const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; const SDValue Ops0 [ ] = { DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , buildSMovImm32 ( DAG , DL , <NUM_LIT> ) , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , buildSMovImm32 ( DAG , DL , TII -> getDefaultRsrcDataFormat ( ) >> <NUM_LIT> ) , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) } ;

SDValue SubRegHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops0 ) , <NUM_LIT> ) ;


<s> return :: getWaitStatesSince ( IsHazard , CurrCycleInstr , IsExpiredFn ) ; } int WaitStates = <NUM_LIT> ; for ( MachineInstr * MI : EmittedInstrs ) { if ( MI ) { if ( IsHazard ( MI ) ) return WaitStates ; if ( MI -> isInlineAsm ( ) ) continue ; } ++ WaitStates ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> MachineBasicBlock :: iterator MBBI = I ; BuildMI ( MBB , MBBI , dl , TII . get ( LISInstr ) , TmpReg ) . addImm ( CalleeAmt >> <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ORIInstr ) , TmpReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( CalleeAmt & <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( ADDInstr ) , StackReg ) . addReg ( StackReg , RegState :: Kill ) . addReg ( TmpReg ) ; } } } return MBB . erase ( I ) ;


<s> static std :: string computeDataLayout ( const Triple & T , bool is64Bit ) { std :: string Ret = T . getArch ( ) == Triple :: sparcel ? <STR_LIT> : <STR_LIT> ; Ret += <STR_LIT> ; if ( ! is64Bit ) Ret += <STR_LIT> ; Ret += <STR_LIT> ;


<s> unsigned Count = <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; ++ Count ; if ( FBB ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; ++ Count ; }


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> return getTargetMachine ( ) . getInstrInfo ( ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << R << <STR_LIT> ) ; unsigned MatchingType = getMatchingLoType ( R ) ; assert ( MatchingType != ELF :: R_MIPS_NONE && <STR_LIT> ) ; auto InsertionPoint = find_best ( Sorted . begin ( ) , Sorted . end ( ) , [ & R , & MatchingType ] ( const <ISA_LIT>RelocationEntry & X ) { return isMatchingReloc ( X , R , MatchingType ) ; } , compareMatchingRelocs ) ; if ( InsertionPoint != Sorted . end ( ) ) InsertionPoint -> Matched = true ; Sorted . insert ( InsertionPoint , R ) -> Matched = true ; }

DEBUG ( dumpRelocs ( <STR_LIT> , Sorted ) ) ;


<s> <STR_LIT> ET = getShiftExtendType ( ) ; bool IsSigned = ET == <STR_LIT> || ET == <STR_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( IsSigned ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( hasShiftExtendAmount ( ) ) ) ;


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT LHSTy ) const override {


<s> case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; } return SDValue ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> <ISA_LIT>ConstantPoolValue :: addSelectionDAGCSEId ( ID ) ;


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= selectMI ( MBB , MBBI , NMBBI ) ; MBBI = NMBBI ; } return Modified ;


<s> ++ Depth ; } assert ( Depth < Stack . size ( ) && <STR_LIT> ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetPop ( ) { OS << <STR_LIT> ; <ISA_LIT>TargetStreamer :: emitDirectiveSetPop ( ) ;


<s> MachineInstr * Next = I -> getNextNode ( ) ;

MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , Next , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * TLSBaseAddrReg ) . addReg ( <STR_LIT> ) ;


<s> BRIG32_DwarfTargetObjectFile :: ~ BRIG32_DwarfTargetObjectFile ( ) {


<s> gcc_assert ( GET_CODE ( set ) == SET ) ; mem = XEXP ( set , opnum ) ; while ( SUBREG_P ( mem ) ) mem = SUBREG_REG ( mem ) ; gcc_assert ( MEM_P ( mem ) ) ;

return volatile_ok || ! MEM_VOLATILE_P ( mem ) ;


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Subtarget = const_cast < <ISA_LIT>Subtarget * > ( getSubtargetImpl ( MF -> getFunction ( ) ) ) ;


<s> count += get_attr_length ( from ) ; tmp = is_jump_table ( from ) ; if ( tmp != NULL ) { count += get_jump_table_size ( tmp ) ; new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && new_cost <= selected_cost ) { selected = tmp ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( tmp ) ; continue ; } new_cost = arm_barrier_cost ( from ) ; if ( count < max_count && new_cost <= selected_cost ) { selected = from ; selected_cost = new_cost ; selected_address = fix -> address + count ; } from = NEXT_INSN ( from ) ; } from = emit_jump_insn_after ( gen_jump ( label ) , selected ) ; JUMP_LABEL ( from ) = label ; barrier = emit_barrier_after ( from ) ; emit_label_after ( label , barrier ) ; new_fix = ( Mfix * ) obstack_alloc ( & minipool_obstack , sizeof ( * new_fix ) ) ; new_fix -> insn = barrier ; new_fix -> address = selected_address ; new_fix -> next = fix -> next ;


<s> ncrn = pcum -> aapcs_ncrn ; nregs = size / UNITS_PER_WORD ; if ( allocate_ncrn && ( ncrn + nregs <= NUM_ARG_REGS ) ) { gcc_assert ( nregs == <NUM_LIT> || nregs == <NUM_LIT> || nregs == <NUM_LIT> ) ; if ( nregs == <NUM_LIT> && ncrn % <NUM_LIT> && aarch64_function_arg_alignment ( mode , type ) == <NUM_LIT> * BITS_PER_UNIT ) { ++ ncrn ; gcc_assert ( ncrn + nregs <= NUM_ARG_REGS ) ; } if ( nregs == <NUM_LIT> || nregs == <NUM_LIT> || GET_MODE_CLASS ( mode ) == MODE_INT ) pcum -> aapcs_reg = gen_rtx_REG ( mode , R0_REGNUM + ncrn ) ; else { rtx par ; int i ; par = gen_rtx_PARALLEL ( mode , rtvec_alloc ( nregs ) ) ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { rtx tmp = gen_rtx_REG ( word_mode , R0_REGNUM + ncrn + i ) ; tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , GEN_INT ( i * UNITS_PER_WORD ) ) ; XVECEXP ( par , <NUM_LIT> , i ) = tmp ;


<s> SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ;

return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , TargetCC , Flag ) ;


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & _OS , MCCodeEmitter * _Emitter , bool RelaxAll , bool NoExecStack ) {


<s> x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == UNSPEC_VOLATILE && XINT ( x , <NUM_LIT> ) == VUNSPEC_POOL_LABEL ) { ASM_GENERATE_INTERNAL_LABEL ( buf , CSKY_CONSTPOOL_LABEL_PREFIX , INTVAL ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ) ;


<s> <ISA_LIT>ELFStreamer :: <ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter ) : MCELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) {


<s> DebugLoc DL ; int fi ; unsigned bitpos ; getStackLocPair ( fi , bitpos , loc ) ; AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , GuardsReg ) ) . addFrameIndex ( fi ) . addImm ( <NUM_LIT> ) ; AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , target_preg ) ) . addReg ( GuardsReg , RegState :: Kill ) . addImm ( bitpos ) ; InsertedInstrs += <NUM_LIT> ;


<s> else if ( fmt [ i ] == 'E' ) { int j ; for ( j = XVECLEN ( x , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( saved_regs_mentioned ( XEXP ( x , i ) ) ) return <NUM_LIT> ; } }


<s> bool UseSoftFloat = Subtarget -> mipsSEUsesSoftFloat ( ) ; <ISA_LIT>CCInfo . analyzeFormalArguments ( Ins , UseSoftFloat , FuncArg ) ; <ISA_LIT>FI -> setFormalArgInfo ( CCInfo . getNextStackOffset ( ) , <ISA_LIT>CCInfo . hasByValArg ( ) ) ; unsigned CurArgIdx = <NUM_LIT> ; <STR_LIT> ByValArg = <ISA_LIT>CCInfo . byval_begin ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; std :: advance ( FuncArg , Ins [ i ] . OrigArgIndex - CurArgIdx ) ; CurArgIdx = Ins [ i ] . OrigArgIndex ; EVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool IsRegLoc = VA . isRegLoc ( ) ; if ( Flags . isByVal ( ) ) { assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValArg != <ISA_LIT>CCInfo . byval_end ( ) ) ; copyByValRegs ( Chain , DL , OutChains , DAG , Flags , InVals , & * FuncArg , <ISA_LIT>CCInfo , * ByValArg ) ; ++ ByValArg ; continue ; } if ( IsRegLoc ) { MVT RegVT = VA . getLocVT ( ) ; unsigned ArgReg = VA . getLocReg ( ) ; const TargetRegisterClass * RC = getRegClassFor ( RegVT ) ; unsigned Reg = addLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; else if ( IsO32 && RegVT == <STR_LIT> && ValVT == <STR_LIT> ) { unsigned Reg2 = addLiveIn ( DAG . getMachineFunction ( ) , getNextIntArgReg ( ArgReg ) , RC ) ; SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , DL , Reg2 , RegVT ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArgValue , ArgValue2 ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( isDSOffsetLegal ( N0 , C1 -> getSExtValue ( ) , <NUM_LIT> ) ) { Base = N0 ; Offset = N1 ; return true ; } } if ( const ConstantSDNode * CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) { if ( isUInt < <NUM_LIT> > ( CAddr -> getZExtValue ( ) ) ) { Base = CurDAG -> getConstant ( <NUM_LIT> , <STR_LIT> ) ; Offset = Addr ; return true ;


<s> if ( ! TARGET_ABI_GNU && regno < crtl -> args . info . regs - <NUM_LIT> ) { regno = crtl -> args . info . regs - <NUM_LIT> ; if ( regno > MMIX_RETURN_VALUE_REGNUM - <NUM_LIT> ) regno = MMIX_RETURN_VALUE_REGNUM - <NUM_LIT> ; }

cfun -> machine -> highest_saved_stack_register = regno ;


<s> if ( df_regs_ever_live_p ( i ) || call_p ) { size += <NUM_LIT> ; reg_saved |= <NUM_LIT> << i ; } break ; case <NUM_LIT> : case STACK_POINTER_REGNUM : break ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case EP_REGNUM : size += <NUM_LIT> ; break ; } } else { for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) if ( df_regs_ever_live_p ( i ) && ( ( ! call_used_regs [ i ] ) || i == LINK_POINTER_REGNUM ) ) break ; if ( TARGET_PROLOG_FUNCTION && ( i == <NUM_LIT> || ( ( i >= <NUM_LIT> ) && ( i < <NUM_LIT> ) ) ) ) { if ( i == <NUM_LIT> ) { size += <NUM_LIT> ; reg_saved |= <NUM_LIT> << i ;


<s> if ( C . front ( ) != '{' || C . back ( ) != '}' ) return std :: make_pair ( false , false ) ;

StringRef :: const_iterator I , B = C . begin ( ) + <NUM_LIT> , E = C . end ( ) - <NUM_LIT> ;


return mips_expand_thread_pointer ( gen_reg_rtx ( Pmode ) ) ;


<s> SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ;

else return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;


<s> bool IsVMEM = isVMEMClauseInst ( MI ) ; if ( ! isValidClauseInst ( MI , IsVMEM ) ) continue ; RegUse Defs , Uses ; GCNDownwardRPTracker RPT ( * LIS ) ; RPT . reset ( MI ) ; if ( ! processRegUses ( MI , Defs , Uses , RPT ) ) continue ; unsigned Length = <NUM_LIT> ; for ( ; Next != E && Length < MaxClause ; ++ Next ) { if ( ! isValidClauseInst ( * Next , IsVMEM ) ) break ; if ( ! processRegUses ( * Next , Defs , Uses , RPT ) ) break ; ++ Length ; } if ( Length < <NUM_LIT> ) continue ; Changed = true ; MFI -> limitOccupancy ( LastRecordedOccupancy ) ; auto B = BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( TargetOpcode :: BUNDLE ) ) ; Ind -> insertMachineInstrInMaps ( * B ) ; for ( auto BI = I ; BI != Next ; ++ BI ) { BI -> bundleWithPred ( ) ; Ind -> removeSingleMachineInstrFromMaps ( * BI ) ; for ( MachineOperand & MO : BI -> defs ( ) ) if ( MO . readsReg ( ) ) MO . setIsInternalRead ( true ) ; } for ( auto && R : Defs ) { forAllLanes ( R . first , R . second . second , [ & R , & B ] ( unsigned SubReg ) { unsigned S = R . second . first | RegState :: EarlyClobber ; if ( ! SubReg ) S &= ~ ( RegState :: Undef | RegState :: Dead ) ; B . addDef ( R . first , S , SubReg ) ; } ) ; }


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return <STR_LIT> ;


<s> uint64_t TruncBits = <NUM_LIT> ; if ( isOpcWithIntImmediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , ShlImm ) ) { Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else if ( VT == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; TruncBits = Opd0 -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) - VT . getSizeInBits ( ) ; VT = Opd0 . getValueType ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; } else if ( BiggerPattern ) { Opd0 = N -> getOperand ( <NUM_LIT> ) ;


<s> TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } return true ; }


<s> if ( TARGET_MIPS16 && ! load_p && regno == RETURN_ADDR_REGNUM ) return false ; return mips_secondary_reload_class ( REGNO_REG_CLASS ( regno ) , GET_MODE ( mem ) , mem , load_p ) == NO_REGS ;


<s> Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = false ; Args . push_back ( Entry ) ; } else { Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; } char const * FunctionNames [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ;

CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI -> getLibcallCallingConv ( LC ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( FunctionNames [ AEABILibcall ] [ AlignVariant ] , TLI -> getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ;


<s> if ( ! TargetV ) TargetV = MaskV ; else if ( TargetV != MaskV ) return SDValue ( ) ; } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi = Lo ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; int Scale = <NUM_LIT> / Mask . size ( ) ; if ( Subtarget -> hasSSSE3 ( ) ) { Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Lo , DAG . getConstant ( Rotation * Scale , <STR_LIT> ) ) ) ;


<s> bool <ISA_LIT>PreEmitPeephole :: runOnMachineFunction ( MachineFunction & MF ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST . getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { MachineBasicBlock :: iterator MBBE = MBB . getFirstTerminator ( ) ; if ( MBBE != MBB . end ( ) ) { MachineInstr & MI = * MBBE ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Changed |= optimizeVccBranch ( MI ) ; continue ; default : break ; } } if ( ! ST . hasVGPRIndexMode ( ) ) continue ; MachineInstr * SetGPRMI = nullptr ; const unsigned Threshold = <NUM_LIT> ; unsigned Count = <NUM_LIT> ; for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MBBI != MBBE ; ) { MachineInstr & MI = * MBBI ; ++ MBBI ;

if ( Count == Threshold ) SetGPRMI = nullptr ;


<s>
for
(
auto
SU
:
TopRoots
)
{
RQ
.
push_back
(
*
new
(
Alloc
.
Allocate
(
)
)
Candidate
(
SU
,
StepNo
)
)
;
}
releaseSuccessors
(
&
DAG
.
EntrySU
,
StepNo
)
;
while
(
!
RQ
.
empty
(
)
)
{
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
StepNo
<<
<STR_LIT>
<STR_LIT>
;
for
(
auto
&
C
:
RQ
)
dbgs
(
)
<<
' '
<<
C
.
SU
->
NodeNum
<<
<STR_LIT>
<<
C
.
Priority
<<
')'
;
dbgs
(
)
<<
'\n'
;
)
;
auto
C
=
pickCandidate
(
)
;


<s> switch ( RdxDesc . getRecurrenceKind ( ) ) { case RecurKind :: Add : case RecurKind :: FAdd : case RecurKind :: And : case RecurKind :: Or : case RecurKind :: Xor : case RecurKind :: SMin : case RecurKind :: SMax : case RecurKind :: UMin : case RecurKind :: UMax : case RecurKind :: FMin : case RecurKind :: FMax : return true ; default : return false ; }


<s> if ( CurrentSCC . size ( ) == <NUM_LIT> ) continue ; InSet . insert ( CurrentSCC . begin ( ) , CurrentSCC . end ( ) ) ; MachineBasicBlock * Header = nullptr ; for ( MachineBasicBlock * MBB : CurrentSCC ) { for ( MachineBasicBlock * Pred : MBB -> predecessors ( ) ) {

if ( InSet . count ( Pred ) ) continue ;


<s> MachineInstr * Catch = & * EHPad -> begin ( ) ; assert ( <STR_LIT> ( * Catch ) ) ; Call -> getOperand ( <NUM_LIT> ) . setReg ( Catch -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto InsertPos = std :: next ( MachineBasicBlock :: iterator ( Catch ) ) ; EHPad -> insert ( InsertPos , Call -> removeFromParent ( ) ) ; BuildMI ( * EHPad , InsertPos , Call -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) ;

EHPad -> erase ( InsertPos , EHPad -> end ( ) ) ;


<s> Worklist . back ( ) = reverse ( Instr -> explicit_uses ( ) ) ;


<s> StringRef getPassName ( ) const override {


<s> static rtx frv_expand_mdpackh_builtin ( tree arglist , rtx target ) { enum insn_code icode = CODE_FOR_mdpackh ; rtx pat , op0 , op1 ; rtx arg1 = frv_read_argument ( & arglist ) ; rtx arg2 = frv_read_argument ( & arglist ) ; rtx arg3 = frv_read_argument ( & arglist ) ;

rtx arg4 = frv_read_argument ( & arglist ) ;


<s> case V4SFmode : case V8SFmode : case V16SFmode : case V2DFmode : case V4DFmode : case V8DFmode : dst = gen_reg_rtx ( GET_MODE ( SUBREG_REG ( op1 ) ) ) ; if ( GET_CODE ( op2 ) == CONST_VECTOR ) { op2 = gen_lowpart ( GET_MODE ( dst ) , op2 ) ; op2 = force_reg ( GET_MODE ( dst ) , op2 ) ; } else { op1 = operands [ <NUM_LIT> ] ; op2 = SUBREG_REG ( operands [ <NUM_LIT> ] ) ; if ( ! vector_operand ( op2 , GET_MODE ( dst ) ) ) op2 = force_reg ( GET_MODE ( dst ) , op2 ) ; } op1 = SUBREG_REG ( op1 ) ; if ( ! vector_operand ( op1 , GET_MODE ( dst ) ) ) op1 = force_reg ( GET_MODE ( dst ) , op1 ) ; emit_insn ( gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , GET_MODE ( dst ) , op1 , op2 ) ) ) ; emit_move_insn ( operands [ <NUM_LIT> ] , gen_lowpart ( mode , dst ) ) ; return ; default : break ;


<s> int i ; for ( i = <NUM_LIT> ; i < MAX_386_ENTITIES ; i ++ ) ix86_optimize_mode_switching [ i ] = <NUM_LIT> ; ix86_optimize_mode_switching [ AVX_U128 ] = <NUM_LIT> ;

g -> get_passes ( ) -> execute_pass_mode_switching ( ) ;


<s> const SmallVector < unsigned , <NUM_LIT> > & getMustSaveCRs ( ) const { return MustSaveCRs ;


return __builtin_aarch64_floatv4siv4sf ( __a ) ;


<s> unsigned PrivateAlign = <NUM_LIT> ; for ( int I = MFI -> getObjectIndexBegin ( ) , E = MFI -> getObjectIndexEnd ( ) ; I != E ; ++ I ) { if ( MFI -> isDeadObjectIndex ( I ) ) continue ; unsigned Size = MFI -> getObjectSize ( I ) ; unsigned Align = MFI -> getObjectAlignment ( I ) ; unsigned Offset = MFI -> getObjectOffset ( I ) ; assert ( Offset == <NUM_LIT> && <STR_LIT> ) ; if ( MFI -> isSpillSlotObjectIndex ( I ) ) { SpillSize = ( SpillSize + Align - <NUM_LIT> ) / Align * Align ; SpillMap [ I ] = SpillSize ; SpillSize += Size ; SpillAlign = std :: max ( SpillAlign , Align ) ; } else { PrivateSize = ( PrivateSize + Align - <NUM_LIT> ) / Align * Align ; PrivateMap [ I ] = PrivateSize ; PrivateSize += Size ; PrivateAlign = std :: max ( PrivateAlign , Align ) ; } MFI -> RemoveStackObject ( I ) ; } int PrivateIndex = - <NUM_LIT> ; int SpillIndex = - <NUM_LIT> ; if ( PrivateSize != <NUM_LIT> ) PrivateIndex = MFI -> CreateStackObject ( PrivateSize , PrivateAlign , false ) ; if ( SpillSize != <NUM_LIT> ) SpillIndex = MFI -> CreateSpillStackObject ( SpillSize , SpillAlign ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { unsigned Opc = MI . getOpcode ( ) ; int AddrIdx = <STR_LIT> ( Opc , <STR_LIT> :: address ) ; if ( AddrIdx == - <NUM_LIT> ) { continue ; } MachineOperand & Base = MI . getOperand ( AddrIdx ) ; if ( ! Base . isFI ( ) ) continue ; int Index = Base . getIndex ( ) ; MachineOperand & Offset = MI . getOperand ( AddrIdx + <NUM_LIT> ) ; int64_t OrigOffset = Offset . getImm ( ) ; if ( MFI -> isSpillSlotObjectIndex ( Index ) ) { Base . setIndex ( SpillIndex ) ; Offset . setImm ( SpillMap [ Index ] + OrigOffset ) ; } else { Base . setIndex ( PrivateIndex ) ;

Offset . setImm ( PrivateMap [ Index ] + OrigOffset ) ;


<s> EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const { if ( MI . getOpcode ( ) == <STR_LIT> ) { MCFixupKind Fixup = MCFixupKind ( <STR_LIT> ) ;


<s> return cast < Function > ( MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) ) ;


<s> const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ? & <STR_LIT> : ( RC == & <STR_LIT> ? & <STR_LIT> : RC ) ) ; return FastISel :: fastEmitInst_rr ( MachineInstOpcode , UseRC , Op0 , Op0IsKill , Op1 , Op1IsKill ) ;


<s> if ( Kind != InlineAsm :: Kind_RegUse && Kind != InlineAsm :: Kind_RegDef && Kind != InlineAsm :: Kind_RegDefEarlyClobber ) continue ; unsigned RC ; bool HasRC = InlineAsm :: hasRegClassConstraint ( Flag , RC ) ; if ( ( ! IsTiedToChangedOp && ( ! HasRC || RC != <STR_LIT> ) ) || NumRegs != <NUM_LIT> ) continue ; assert ( ( i + <NUM_LIT> < NumOps ) && <STR_LIT> ) ; SDValue V0 = N -> getOperand ( i + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( i + <NUM_LIT> ) ; unsigned Reg0 = cast < RegisterSDNode > ( V0 ) -> getReg ( ) ; unsigned Reg1 = cast < RegisterSDNode > ( V1 ) -> getReg ( ) ; SDValue PairedReg ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; if ( Kind == InlineAsm :: Kind_RegDef || Kind == InlineAsm :: Kind_RegDefEarlyClobber ) { unsigned GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; SDValue Chain = SDValue ( N , <NUM_LIT> ) ; SDNode * GU = N -> getGluedUser ( ) ; SDValue RegCopy = CurDAG -> getCopyFromReg ( Chain , dl , GPVR , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue Sub0 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue Sub1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue T0 = CurDAG -> getCopyToReg ( Sub0 , dl , Reg0 , Sub0 , RegCopy . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; GU = T1 . getNode ( ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( createGPRPairNode ( <STR_LIT> , T0 , T1 ) , <NUM_LIT> ) ;


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , RAI ( g . getRAI ( ) ) , MRI ( mri ) , Empty ( ) , Trace ( false ) {


<s> const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ; if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ;

if ( Kind . isMergeable1ByteCString ( ) ) return false ;


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; unsigned TF = MO . getTargetFlags ( ) ; switch ( MO . getType ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case MachineOperand :: MO_Register : { unsigned Reg = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { int64_t Imm = MO . getImm ( ) ; O << '#' ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF == <STR_LIT> ) ) O << <STR_LIT> ; O << Imm ; break ; } case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : { const GlobalValue * GV = MO . getGlobal ( ) ; if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; else if ( ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) || ( TF & <STR_LIT> ) ) O << <STR_LIT> ; O << * Mang -> getSymbol ( GV ) ; printOffset ( MO . getOffset ( ) , O ) ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ExternalSymbol : { O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; if ( TF == <STR_LIT> ) O << <STR_LIT> ;


<s> for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) if ( USEFUL_INSN_P ( subinsn ) && pred ( subinsn ) ) { * cache = true ; break ; }


<s> case MCK_SSrcF32 : return Operand . isSSrcF32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SoppBrTarget : return Operand . isSoppBrTarget ( ) ? Match_Success : Match_InvalidOperand ; case MCK_VReg32OrOff : return Operand . isVReg32OrOff ( ) ? Match_Success : Match_InvalidOperand ; case MCK_InterpSlot : return Operand . isInterpSlot ( ) ? Match_Success : Match_InvalidOperand ; case MCK_Attr : return Operand . isInterpAttr ( ) ? Match_Success : Match_InvalidOperand ; case MCK_AttrChan : return Operand . isAttrChan ( ) ? Match_Success : Match_InvalidOperand ; default : return Match_InvalidOperand ; }


<s> FastMathFlags FMF = FPOp -> getFastMathFlags ( ) ; bool UnsafeDiv = HasUnsafeFPMath || FMF . isFast ( ) || FMF . allowReciprocal ( ) ; if ( ST -> hasFP32Denormals ( ) || UnsafeDiv ) return false ; IRBuilder < > Builder ( FDiv . getParent ( ) , std :: next ( FDiv . getIterator ( ) ) , FPMath ) ; Builder . setFastMathFlags ( FMF ) ; Builder . SetCurrentDebugLocation ( FDiv . getDebugLoc ( ) ) ; Function * Decl = <STR_LIT> ( Mod , <STR_LIT> ) ; Value * Num = FDiv . getOperand ( <NUM_LIT> ) ; Value * Den = FDiv . getOperand ( <NUM_LIT> ) ; Value * NewFDiv = nullptr ; if ( VectorType * VT = dyn_cast < VectorType > ( Ty ) ) { NewFDiv = UndefValue :: get ( VT ) ; for ( unsigned I = <NUM_LIT> , E = VT -> getNumElements ( ) ; I != E ; ++ I ) { Value * NumEltI = Builder . CreateExtractElement ( Num , I ) ;

Value * DenEltI = Builder . CreateExtractElement ( Den , I ) ;


<s> SmallVector < unsigned , <NUM_LIT> > RegList ; unsigned StartOp = <NUM_LIT> + <NUM_LIT> ; unsigned NumOffset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : StartOp = <NUM_LIT> ; NumOffset = <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( SrcReg == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = StartOp , NumOps = MI -> getNumOperands ( ) - NumOffset ; i != NumOps ; ++ i ) RegList . push_back ( MI -> getOperand ( i ) . getReg ( ) ) ; break ; case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } OutStreamer . EmitRegSave ( RegList , Opc == <STR_LIT> ) ; } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : { unsigned CPI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;

const MachineConstantPool * MCP = MF . getConstantPool ( ) ;


<s> static __inline vec_int4 spu_xor ( vec_int4 a , signed int b ) { return ( ( vec_int4 ) ( si_xori ( ( qword ) ( a ) , ( unsigned int ) ( b ) ) ) ) ;


<s> const TargetFrameLowering * getFrameLowering ( ) const override {

return getSubtargetImpl ( ) -> getFrameLowering ( ) ;


<s> SDValue Val0 ( N , <NUM_LIT> ) ; if ( Val0 . use_empty ( ) ) return DCI . CombineTo ( N , Val0 , DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ) ;


<s> bool <ISA_LIT>HardwareLoops :: checkForImmediate ( const MachineOperand & MO , int64_t & Val ) const { if ( MO . isImm ( ) ) { Val = MO . getImm ( ) ; return true ; } if ( ! MO . isReg ( ) ) return false ; int64_t TV ; Register R = MO . getReg ( ) ; if ( ! Register :: isVirtualRegister ( R ) ) return false ; MachineInstr * DI = MRI -> getVRegDef ( R ) ; unsigned DOpc = DI -> getOpcode ( ) ; switch ( DOpc ) { case TargetOpcode :: COPY : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! checkForImmediate ( DI -> getOperand ( <NUM_LIT> ) , TV ) ) return false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & S1 = DI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & S2 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V1 , V2 ;

if ( ! checkForImmediate ( S1 , V1 ) || ! checkForImmediate ( S2 , V2 ) ) return false ;


<s> uses = BitVector ( range ) ; defs = BitVector ( range ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MII ) : InstrInfo ( MII ) {


<s> assert ( Size == <NUM_LIT> ) ; unsigned CCReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( isSCC ( CCReg , MRI ) ) { unsigned Opcode = getS_CMPOpcode ( ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) , Size ) ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; MachineInstr * Copy = BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , CCReg ) . addReg ( <STR_LIT> ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) | constrainSelectedInstRegOperands ( * Copy , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return Ret ; } assert ( Size == <NUM_LIT> || Size == <NUM_LIT> ) ; unsigned Opcode = getV_CMPOpcode ( ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) , Size ) ; MachineInstr * ICmp = BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; RBI . constrainGenericRegister ( ICmp -> getOperand ( <NUM_LIT> ) . getReg ( ) , <STR_LIT> , MRI ) ; bool Ret = constrainSelectedInstRegOperands ( * ICmp , TII , TRI , RBI ) ;


<s> const MachineOperand & MO = MI -> getOperand ( opNum ) ; if ( MO . getType ( ) == MachineOperand :: MO_Register ) { assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && <STR_LIT> ) ; O << getRegisterName ( MO . getReg ( ) ) ;


<s> while ( PredefinedFuncs [ i ] . Name ) { name_ = PredefinedFuncs [ i ] . Name ; if ( strcmp ( name , name_ ) == <NUM_LIT> ) return & PredefinedFuncs [ i ] . Signature ; i ++ ; } return <NUM_LIT> ;


<s> if ( M != CodeModel :: Small && M != CodeModel :: Kernel ) return false ;

if ( M == CodeModel :: Small && Offset < <NUM_LIT> * <NUM_LIT> * <NUM_LIT> ) return true ;


<s> if ( Kind != MemSrc ) { return false ; } if ( ! Mem . WithPreDec ) { return false ;


<s> return ( __m128d ) __builtin_ia32_extractf64x2_256_mask ( ( __v4df ) __A , __imm , ( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> MI . eraseFromParent ( ) ; return & MBB ; } if ( Val -> isReg ( ) ) MRI . clearKillFlags ( Val -> getReg ( ) ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( UseGPRIdxMode ) { MachineBasicBlock :: iterator I ( & MI ) ; MachineInstr * SetOn = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( VGPRIndexMode :: DST_ENABLE ) ; SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get ( <STR_LIT> ) ) ; } unsigned PhiReg = MRI . createVirtualRegister ( VecRC ) ; auto InsPt = loadM0FromVGPR ( TII , MBB , MI , SrcVec -> getReg ( ) , PhiReg , Offset , UseGPRIdxMode ) ; MachineBasicBlock * LoopBB = InsPt -> getParent ( ) ; if ( UseGPRIdxMode ) { BuildMI ( * LoopBB , InsPt , DL , TII -> get ( <STR_LIT> ) ) . addReg ( PhiReg , RegState :: Undef , SubReg ) . add ( * Val ) . addReg ( Dst , RegState :: ImplicitDefine ) . addReg ( PhiReg , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; } else { const MCInstrDesc & MovRelDesc = TII -> get ( getMOVRELDPseudo ( VecRC ) ) ;

BuildMI ( * LoopBB , InsPt , DL , MovRelDesc ) . addReg ( Dst , RegState :: Define ) . addReg ( PhiReg ) . add ( * Val ) . addImm ( SubReg - <STR_LIT> ) ;


<s> unsigned getStackCacheReservedBytes ( ) const {


<s> if ( fcode >= S390_OVERLOADED_BUILTIN_VAR_OFFSET ) return opflags_overloaded_builtin_var [ fcode - S390_OVERLOADED_BUILTIN_VAR_OFFSET ] ; else if ( fcode >= S390_OVERLOADED_BUILTIN_OFFSET ) gcc_unreachable ( ) ;


sprintf ( buf , <STR_LIT> , opcode , ( cbranch_predicted_p ( insn ) ^ reverse_predicted ) ? <STR_LIT> : <STR_LIT> , regop ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; bool IsKnown ; auto MRSMapper = <STR_LIT> ( ) ; uint32_t MRSReg = MRSMapper . fromString ( Tok . getString ( ) , STI . getFeatureBits ( ) , IsKnown ) ;

assert ( IsKnown == ( MRSReg != - <NUM_LIT> ) && <STR_LIT> ) ;


<s> uint16_t domain = ( MI -> getDesc ( ) . TSFlags >> <STR_LIT> ) & <NUM_LIT> ;

return std :: make_pair ( domain , domain && lookup ( MI -> getOpcode ( ) , domain ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> void <ISA_LIT>BaseRegisterInfo :: UpdateRegAllocHint ( unsigned Reg , unsigned NewReg , MachineFunction & MF ) const { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; std :: pair < unsigned , unsigned > Hint = MRI -> getRegAllocationHint ( Reg ) ;

if ( ( Hint . first == ( unsigned ) <STR_LIT> || Hint . first == ( unsigned ) <STR_LIT> ) && TargetRegisterInfo :: isVirtualRegister ( Hint . second ) ) {


<s> if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 ) ; else pat = GEN_FCN ( icode ) ( op0 ) ; if ( ! pat ) return NULL_RTX ;


<s> return needsCmpXchgNb ( PTy -> getElementType ( ) ) ? AtomicExpansionKind :: CmpXChg : AtomicExpansionKind :: None ;


<s> assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ;

unsigned OffsetIdx = MI . getNumExplicitOperands ( ) - <NUM_LIT> ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TM ( TM ) , STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , {


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const GCNSubtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ST ) , ST ( ST ) {


<s> addend = offset ; ptr_type = build_pointer_type_for_mode ( type , ptr_mode , true ) ; if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { tree real_part , imag_part , real_temp ; real_part = alpha_gimplify_va_arg_1 ( TREE_TYPE ( type ) , base , offset , pre_p ) ; real_temp = get_initialized_tmp_var ( real_part , pre_p , NULL ) ; imag_part = alpha_gimplify_va_arg_1 ( TREE_TYPE ( type ) , base , offset , pre_p ) ; return build2 ( COMPLEX_EXPR , type , real_temp , imag_part ) ; } else if ( TREE_CODE ( type ) == REAL_TYPE ) { tree fpaddend , cond , fourtyeight ; fourtyeight = build_int_cst ( TREE_TYPE ( addend ) , <NUM_LIT> * <NUM_LIT> ) ; fpaddend = fold_build2 ( MINUS_EXPR , TREE_TYPE ( addend ) , addend , fourtyeight ) ; cond = fold_build2 ( LT_EXPR , boolean_type_node , addend , fourtyeight ) ; addend = fold_build3 ( COND_EXPR , TREE_TYPE ( addend ) , cond , fpaddend , addend ) ;


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveInsn ( DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ;


<s> return create<ISA_LIT>MachObjectWriter ( OS , false , MachO :: CPU_TYPE_<ISA_LIT> , Subtype ) ;


<s> <ISA_LIT>Disassembler :: <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> return get ( Opcode ) . TSFlags & <STR_LIT> ;