<s> <ISA_LIT>CCState ( CallingConv :: ID CC , bool IsVarArg , MachineFunction & MF , SmallVectorImpl < CCValAssign > & locs , LLVMContext & C , unsigned NumNamedArgs ) : CCState ( CC , IsVarArg , MF , locs , C ) , NumNamedVarArgParams ( NumNamedArgs ) {


<s> return Opc >= <NUM_LIT> ? <STR_LIT> ( Opc ) : Opc ;


<s> return gen_rtx_MEM ( mode , gen_rtx_PLUS ( Pmode , base , frv_frame_offset_rtx ( offset ) ) ) ;


<s> return DAG . getSetCC ( DL , VT , Add , DAG . getConstant ( <NUM_LIT> , DL , OpVT ) , CC ) ; } if ( RHS . getOpcode ( ) == <STR_LIT> && isNullConstant ( RHS . getOperand ( <NUM_LIT> ) ) && RHS . hasOneUse ( ) ) { SDValue Add = DAG . getNode ( <STR_LIT> , DL , OpVT , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , VT , Add , DAG . getConstant ( <NUM_LIT> , DL , OpVT ) , CC ) ; } if ( SDValue V = combineVectorSizedSetCCEquality ( N , DAG , Subtarget ) ) return V ; } if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { if ( LHS . getOpcode ( ) == <STR_LIT> ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; } bool IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; if ( IsSEXT0 && IsVZero1 ) { assert ( VT == LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) && <STR_LIT> ) ; if ( CC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( CC == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , VT ) ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) return DAG . getNOT ( DL , LHS . getOperand ( <NUM_LIT> ) , VT ) ; assert ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && <STR_LIT> ) ; return LHS . getOperand ( <NUM_LIT> ) ; } } if ( Subtarget . hasSSE1 ( ) && ! Subtarget . hasSSE2 ( ) && VT == <STR_LIT> && LHS . getValueType ( ) == <STR_LIT> ) return LowerVSETCC ( SDValue ( N , <NUM_LIT> ) , Subtarget , DAG ) ;


<s> void setTailCallSPDelta ( int size ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! ML ) break ; if ( ! DisableInnermostLoopAlign32 ) { if ( ML -> getLoopDepth ( ) > <NUM_LIT> && ML -> getSubLoops ( ) . empty ( ) ) return Align ( <NUM_LIT> ) ; } const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = <NUM_LIT> ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> getInstSizeInBytes ( * J ) ; if ( LoopSize > <NUM_LIT> ) break ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> default : return SDValue ( ) ; case <STR_LIT> : return lowerSETVL ( Op , DAG ) ; case <STR_LIT> :


<s> RegisterMCAsmInfo < <ISA_LIT>ELFMCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ;

TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ;


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; const Align PtrAlign = Align ( PtrSize ) ; auto List = MIRBuilder . buildLoad ( PtrTy , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrAlign ) ) ;


<s> for ( unit = <NUM_LIT> ; unit < ARRAY_SIZE ( frv_unit_groups ) ; unit ++ ) { group = frv_unit_groups [ unit ] ; packet_group = & frv_packet . groups [ group ] ; if ( cursor [ group ] < packet_group -> num_insns ) { gcc_assert ( packet_group -> sorted [ cursor [ group ] ] != packet_group -> nop ) ; insns [ to ++ ] = packet_group -> sorted [ cursor [ group ] ++ ] ; }


<s> void <ISA_LIT>IncomingValueHandler :: assignValueToAddress ( Register ValVReg , Register Addr , LLT MemTy , MachinePointerInfo & MPO , CCValAssign & VA ) { auto BuildLoad = [ ] ( MachineIRBuilder & MIRBuilder , MachinePointerInfo & MPO , LLT MemTy , const DstOp & Res , Register Addr ) { MachineFunction & MF = MIRBuilder . getMF ( ) ;

auto * MMO = MF . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad , MemTy , inferAlignFromPtrInfo ( MF , MPO ) ) ;


<s> RS -> enterBasicBlock ( & Entry ) ; unsigned STmp0 = RS -> scavengeRegister ( & AMDGPU :: SGPR_32RegClass , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & AMDGPU :: SGPR_32RegClass , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( AMDGPU :: S_LOAD_DWORD_IMM ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( AMDGPU :: S_LOAD_DWORD_IMM ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( AMDGPU :: S_MUL_I32 ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( AMDGPU :: V_MUL_U32_U24_e32 ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( AMDGPU :: V_MAD_U32_U24 ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( AMDGPU :: V_ADD_I32_e32 ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else { BuildMI ( Entry , Insert , DL , get ( AMDGPU :: V_MBCNT_LO_U32_B32_e64 ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( AMDGPU :: V_MBCNT_HI_U32_B32_e64 ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addReg ( TIDReg ) ; } BuildMI ( Entry , Insert , DL , get ( AMDGPU :: V_LSHLREV_B32_e32 ) , TIDReg ) . addImm ( <NUM_LIT> ) . addReg ( TIDReg ) ; MFI -> setTIDReg ( TIDReg ) ; } unsigned LDSOffset = MFI -> LDSSize + ( FrameOffset * WorkGroupSize ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: V_ADD_I32_e32 ) , TmpReg ) . addImm ( LDSOffset ) . addReg ( TIDReg ) ; return TmpReg ;


<s> <ISA_LIT>SectionType SecTy ; const Constant * C = GV -> getInitializer ( ) ; if ( C -> isNullValue ( ) ) SecTy = UDATA ; else if ( GV -> getType ( ) -> getAddressSpace ( ) == <STR_LIT> ) SecTy = IDATA ;

else if ( GV -> getType ( ) -> getAddressSpace ( ) == <STR_LIT> ) SecTy = ROMDATA ;


return ( int16x4_t ) __builtin_aarch64_sqnegv4hi ( __a ) ;


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = CTX . getRegisterInfo ( ) -> getEncodingValue ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind ; if ( isThumb2 ( STI ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; ++ MCNumCPRelocations ; } else { EncodeAddrModeOpValues ( MI , OpIdx , Reg , Imm8 , Fixups , STI ) ; isAdd = <STR_LIT> ( Imm8 ) == <STR_LIT> ; }


<s> unsigned Idx = ISDOpc - <STR_LIT> ; Opc = OpcTable [ Idx ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } case <STR_LIT> : Opc = OpcTable [ ISDOpc - <STR_LIT> ] [ <NUM_LIT> ] ; RC = & <STR_LIT> ; RegSize = <NUM_LIT> ; break ; } if ( ! <STR_LIT> ( Imm , RegSize ) ) return <NUM_LIT> ; unsigned ResultReg = fastEmitInst_ri ( Opc , RC , LHSReg , <STR_LIT> ( Imm , RegSize ) ) ; if ( RetVT >= <STR_LIT> && RetVT <= <STR_LIT> && ISDOpc != <STR_LIT> ) { uint64_t Mask = ( RetVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;

ResultReg = emitAnd_ri ( <STR_LIT> , ResultReg , Mask ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; EVT ReqVT = VT != <STR_LIT> ? VT : VTys [ SplatSize - <NUM_LIT> ] ; if ( Val == - <NUM_LIT> ) SplatSize = <NUM_LIT> ; EVT CanonicalVT = VTys [ SplatSize - <NUM_LIT> ] ;

SDValue Elt = DAG . getConstant ( Val , <STR_LIT> ) ;


<s> static __inline unsigned int _mm_getcsr ( void ) {


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF ) const {


<s> if ( mode != BLKmode && might_split_p ) factor = ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ; else factor = <NUM_LIT> ; if ( loongarch_classify_address ( & addr , x , mode , false ) ) switch ( addr . type ) { case ADDRESS_REG : return factor ; case ADDRESS_REG_REG : return factor ; case ADDRESS_CONST_INT : return factor ; case ADDRESS_SYMBOLIC :

return factor * loongarch_symbol_insns ( addr . symbol_type , mode ) ;


<s> ReturnTypes . assign ( Sig . Returns . begin ( ) , Sig . Returns . end ( ) ) ;


return __builtin_aarch64_lroundhfsi ( __a ) ;


<s> case ENCODING_REG : translateRegister ( mcInst , insn . reg ) ; return false ; case ENCODING_WRITEMASK : return translateMaskRegister ( mcInst , insn . writemask ) ; CASE_ENCODING_RM : CASE_ENCODING_VSIB : return translateRM ( mcInst , operand , insn , Dis ) ; case ENCODING_IB : case ENCODING_IW : case ENCODING_ID : case ENCODING_IO : case ENCODING_Iv : case ENCODING_Ia : translateImmediate ( mcInst , insn . immediates [ insn . numImmediatesTranslated ++ ] , operand , insn , Dis ) ; return false ; case ENCODING_IRC : mcInst . addOperand ( MCOperand :: createImm ( insn . RC ) ) ; return false ; case ENCODING_SI : return translateSrcIndex ( mcInst , insn ) ;


<s> machine_mode h8300_select_cc_mode ( enum rtx_code cond , rtx op0 , rtx op1 ) { if ( op1 == const0_rtx && ( cond == EQ || cond == NE || cond == LT || cond == GE ) && ( GET_CODE ( op0 ) == PLUS || GET_CODE ( op0 ) == MINUS || GET_CODE ( op0 ) == NEG || GET_CODE ( op0 ) == AND || GET_CODE ( op0 ) == IOR || GET_CODE ( op0 ) == XOR || GET_CODE ( op0 ) == NOT || GET_CODE ( op0 ) == ASHIFT || GET_CODE ( op0 ) == ASHIFTRT || GET_CODE ( op0 ) == LSHIFTRT || GET_CODE ( op0 ) == MULT || GET_CODE ( op0 ) == SYMBOL_REF || GET_CODE ( op0 ) == SIGN_EXTEND || GET_CODE ( op0 ) == ZERO_EXTEND || REG_P ( op0 ) || MEM_P ( op0 ) ) ) return CCZNmode ;


<s> <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; addPass ( create<ISA_LIT>DelaySlotFillerPass ( TM ) ) ; if ( Subtarget . hasStandardEncoding ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( create<ISA_LIT>LongBranchPass ( TM ) ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) || Subtarget . allowMixed16_32 ( ) ) addPass ( create<ISA_LIT>ConstantIslandPass ( TM ) ) ; return true ;


<s> int64_t v = ( int64_t ) N -> getSExtValue ( ) ;

return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( v ) ;


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_is_named_user_abort ( void * const tdb_ptr , unsigned char * code ) { struct __htm_tdb * tdb = ( struct __htm_tdb * ) tdb_ptr ; if ( tdb -> format != <NUM_LIT> ) return <NUM_LIT> ; if ( tdb -> abort_code >= _HTM_FIRST_USER_ABORT_CODE ) {

* code = tdb -> abort_code - _HTM_FIRST_USER_ABORT_CODE ;


<s> getStreamer ( ) . emitCodeAlignment ( Alignment . value ( ) ) ;

getStreamer ( ) . emitValue ( Size , <NUM_LIT> ) ;


<s> MBB -> insert ( MI , EarlierMI ) ; MachineOperand & HighRegOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowRegOp = MI -> getOperand ( <NUM_LIT> ) ; HighRegOp . setReg ( RI . getSubReg ( HighRegOp . getReg ( ) , <STR_LIT> ) ) ; LowRegOp . setReg ( RI . getSubReg ( LowRegOp . getReg ( ) , <STR_LIT> ) ) ; MachineOperand & HighOffsetOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowOffsetOp = MI -> getOperand ( <NUM_LIT> ) ; LowOffsetOp . setImm ( LowOffsetOp . getImm ( ) + <NUM_LIT> ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; unsigned HighOpcode = getOpcodeForOffset ( NewOpcode , HighOffsetOp . getImm ( ) ) ;

unsigned LowOpcode = getOpcodeForOffset ( NewOpcode , LowOffsetOp . getImm ( ) ) ;


<s> <ISA_LIT>ConstantPoolConstant :: <ISA_LIT>ConstantPoolConstant ( const Constant * C , <STR_LIT> Kind , unsigned PCAdjust , <STR_LIT> Modifier , bool AddCurrentAddress , unsigned ID ) : <ISA_LIT>ConstantPoolValue ( C -> getType ( ) , Kind , PCAdjust , Modifier , AddCurrentAddress , ID ) , CVal ( C ) {


<s> llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : if ( Subtarget -> hasVFP2 ( ) && ! isVarArg ) { if ( ! Subtarget -> isAAPCS_ABI ( ) ) return ( Return ? RetFastCC_<ISA_LIT>_APCS : FastCC_<ISA_LIT>_APCS ) ; return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; } case CallingConv :: C : case CallingConv :: CXX_FAST_TLS : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && TM . Options . FloatABIType == FloatABI :: Hard && ! isVarArg ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else { return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; }

case CallingConv :: <ISA_LIT>_AAPCS_VFP :


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( ) ) ;


<s> const MCOperandInfo & Info = Desc . OpInfo [ i ] ; if ( Info . OperandType == <STR_LIT> ) { MCSymbol * Sym = Printer . createTempSymbol ( <STR_LIT> ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Returns ; SmallVector < <STR_LIT> , <NUM_LIT> > Params ; const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; for ( const MachineOperand & MO : MI -> defs ( ) ) Returns . push_back ( getType ( MRI . getRegClass ( MO . getReg ( ) ) ) ) ; for ( const MachineOperand & MO : MI -> explicit_uses ( ) ) if ( MO . isReg ( ) ) Params . push_back ( getType ( MRI . getRegClass ( MO . getReg ( ) ) ) ) ; if ( <STR_LIT> ( * MI ) ) Params . pop_back ( ) ; MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Sym ) ; WasmSym -> setReturns ( std :: move ( Returns ) ) ; WasmSym -> setParams ( std :: move ( Params ) ) ; WasmSym -> setType ( <STR_LIT> ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( WasmSym , MCSymbolRefExpr :: VK_<ISA_LIT>_TYPEINDEX , Ctx ) ; MCOp = MCOperand :: createExpr ( Expr ) ; break ; } } MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_FPImmediate : { const ConstantFP * Imm = MO . getFPImm ( ) ; if ( Imm -> getType ( ) -> isFloatTy ( ) ) MCOp = MCOperand :: createFPImm ( Imm -> getValueAPF ( ) . convertToFloat ( ) ) ; else if ( Imm -> getType ( ) -> isDoubleTy ( ) ) MCOp = MCOperand :: createFPImm ( Imm -> getValueAPF ( ) . convertToDouble ( ) ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; } case MachineOperand :: MO_GlobalAddress : assert ( MO . getTargetFlags ( ) == <STR_LIT> && <STR_LIT> ) ; MCOp = LowerSymbolOperand ( GetGlobalAddressSymbol ( MO ) , MO . getOffset ( ) , MO . getGlobal ( ) -> getValueType ( ) -> isFunctionTy ( ) , false ) ; break ;

case MachineOperand :: MO_ExternalSymbol :


<s> if ( ConstantEntry . isMachineConstantPoolEntry ( ) ) return nullptr ; auto * C = dyn_cast < Constant > ( ConstantEntry . Val . ConstVal ) ;

assert ( ( ! C || ConstantEntry . getType ( ) == C -> getType ( ) ) && <STR_LIT> ) ;


<s> static unsigned SubIdx2Lane ( unsigned Idx ) { switch ( Idx ) { default : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> int Lane = * MaybeLane ; if ( Lane < <NUM_LIT> ) Lane = <NUM_LIT> ;

if ( matchDupFromInsertVectorElt ( Lane , MI , MRI , MatchInfo ) ) return true ;


<s> static const MCPhysReg RegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned NbRegs = array_lengthof ( RegList ) ; SmallVector < unsigned , <NUM_LIT> > ArgsParts ; ParseFunctionArgs ( Args , ArgsParts ) ; if ( State . isVarArg ( ) ) { unsigned ValNo = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgsParts . size ( ) ; i != e ; i ++ ) { MVT ArgVT = Args [ ValNo ] . VT ; MVT LocVT = ArgVT ; CCValAssign :: LocInfo LocInfo = CCValAssign :: Full ; for ( unsigned j = <NUM_LIT> ; j < ArgsParts [ i ] ; j ++ ) {

if ( i == <NUM_LIT> && j == <NUM_LIT> ) State . addLoc ( CCValAssign :: getCustomMem ( ValNo ++ , ArgVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ;


<s> AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ;


<s> MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const override {


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ;

std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ;


<s> case CallingConv :: C : case CallingConv :: Fast : return LowerCCCArguments ( Chain , CallConv , isVarArg , Ins , dl , DAG , InVals ) ; }


<s> unsigned getInitialP<ISA_LIT>nputAddr ( const Function & F ) {

return getIntegerAttribute ( F , <STR_LIT> , <NUM_LIT> ) ;


<s> fmt = GET_RTX_FORMAT ( GET_CODE ( op ) ) ; for ( i = GET_RTX_LENGTH ( GET_CODE ( op ) ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E' ) { int j ;

for ( j = XVECLEN ( op , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( tls_symbolic_reference_mentioned_p ( XVECEXP ( op , i , j ) ) ) return true ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ( ToEltVT == <STR_LIT> || ToEltVT == <STR_LIT> ) ) NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ToEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( FromEltVT == <STR_LIT> && ToEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || ( FromEltVT != <STR_LIT> && FromVT . getVectorNumElements ( ) == NumElements ) || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> ) return SDValue ( ) ; auto isVMOVNShuffle = [ & ] ( ShuffleVectorSDNode * SVN , bool Rev ) { ArrayRef < int > M = SVN -> getMask ( ) ; unsigned NumElts = ToVT . getVectorNumElements ( ) ; if ( SVN -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) NumElts /= <NUM_LIT> ; unsigned Off0 = Rev ? NumElts : <NUM_LIT> ; unsigned Off1 = Rev ? <NUM_LIT> : NumElts ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; I += <NUM_LIT> ) { if ( M [ I ] >= <NUM_LIT> && M [ I ] != ( int ) ( Off0 + I / <NUM_LIT> ) ) return false ; if ( M [ I + <NUM_LIT> ] >= <NUM_LIT> && M [ I + <NUM_LIT> ] != ( int ) ( Off1 + I / <NUM_LIT> ) ) return false ; } return true ; } ; if ( Trunc . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( SDValue U = PerformVQDMULHCombine ( Trunc . getOperand ( <NUM_LIT> ) . getNode ( ) , DAG ) ) { DAG . ReplaceAllUsesWith ( Trunc . getOperand ( <NUM_LIT> ) , U ) ; return SDValue ( ) ; } } if ( auto * Shuffle = dyn_cast < ShuffleVectorSDNode > ( Trunc . getOperand ( <NUM_LIT> ) ) ) if ( isVMOVNShuffle ( Shuffle , false ) || isVMOVNShuffle ( Shuffle , true ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( St ) ; SDValue Ch = St -> getChain ( ) ; SDValue BasePtr = St -> getBasePtr ( ) ; Align Alignment = St -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = St -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = St -> getAAInfo ( ) ; EVT NewFromVT = EVT :: getVectorVT ( C , FromEltVT , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getSizeInBits ( ) ) , NumElements ) ;

SmallVector < SDValue , <NUM_LIT> > Stores ;


<s> if ( length == strlen ( flag -> name ) && ! strncmp ( flag -> name , token , length ) ) return flag -> flag ; }

error ( <STR_LIT> , option_name , token ) ;


<s> unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; const TargetRegisterClass * RegClass = CSI [ i - <NUM_LIT> ] . getRegClass ( ) ; MBB . addLiveIn ( Reg ) ; if ( Reg == FPReg ) continue ; if ( RegClass != & <STR_LIT> && ! isWin64 ) { CalleeFrameSize += SlotSize ; BuildMI ( MBB , MI , DL , get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) ; } else { storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) , RegClass ) ; }


<s> bool nds32_long_call_p ( rtx symbol ) { if ( nds32_indirect_call_referenced_p ( symbol ) ) return TARGET_ICT_MODEL_LARGE ; else return TARGET_CMODEL_LARGE ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> Register DestSub1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; const TargetRegisterClass * Src0RC = nullptr ; const TargetRegisterClass * Src0SubRC = nullptr ; if ( Src0 . isReg ( ) ) { Src0RC = MRI . getRegClass ( Src0 . getReg ( ) ) ; Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; } const TargetRegisterClass * Src1RC = nullptr ; const TargetRegisterClass * Src1SubRC = nullptr ; if ( Src1 . isReg ( ) ) { Src1RC = MRI . getRegClass ( Src1 . getReg ( ) ) ; Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; } MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , DestSub0 ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; LoHalf -> getOperand ( <NUM_LIT> ) . setReg ( SCCSource ) ; Worklist . insert ( LoHalf ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , DestSub1 ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) ; HiHalf -> getOperand ( <NUM_LIT> ) . setReg ( SCCSource ) ; Worklist . insert ( HiHalf ) ;

BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ;


<s> int _U_Qfunord ( long double a , long double b ) {

return ( _U_Qfcmp ( a , b , QCMP_INV | QCMP_UNORD ) != <NUM_LIT> ) ;


<s> assert ( NewPHI ) ; for ( unsigned I = <NUM_LIT> ; I < OldPHI -> getNumIncomingValues ( ) ; ++ I ) { if ( Info . NewArguments [ I ] ) NewPHI -> addIncoming ( Info . NewArguments [ I ] , OldPHI -> getIncomingBlock ( I ) ) ; else NewPHI -> addIncoming ( OldPHI -> getIncomingValue ( I ) , OldPHI -> getIncomingBlock ( I ) ) ;


<s> <ISA_LIT>InsertWaits ( TargetMachine & tm ) :

MachineFunctionPass ( ID ) , TII ( static_cast < const <ISA_LIT>InstrInfo * > ( tm . getInstrInfo ( ) ) ) , TRI ( TII -> getRegisterInfo ( ) ) {


<s> static void rs6000_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { switch ( size ) { case <NUM_LIT> : fputs ( <STR_LIT> , file ) ; break ; case <NUM_LIT> : fputs ( DOUBLE_INT_ASM_OP , file ) ;


<s> if ( TARGET_CBCOND && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && ( GET_MODE ( operands [ <NUM_LIT> ] ) == SImode || ( TARGET_ARCH64 && GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) ) && ( GET_CODE ( operands [ <NUM_LIT> ] ) != CONST_INT || SPARC_SIMM5_P ( INTVAL ( operands [ <NUM_LIT> ] ) ) ) ) { emit_cbcond_insn ( GET_CODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } if ( TARGET_ARCH64 && operands [ <NUM_LIT> ] == const0_rtx && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_MODE ( operands [ <NUM_LIT> ] ) == DImode ) {

emit_v9_brxx_insn ( GET_CODE ( operands [ <NUM_LIT> ] ) , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ;


<s> <ISA_LIT>HazardRecognizer ( const TargetInstrInfo & ) {


<s> assert ( Op -> getOperand ( <NUM_LIT> ) -> getSimpleValueType ( <NUM_LIT> ) == <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > LHS , RHS ; DAG . ExtractVectorElements ( Op -> getOperand ( <NUM_LIT> ) , LHS ) ; DAG . ExtractVectorElements ( Op -> getOperand ( <NUM_LIT> ) , RHS ) ; const SDValue & CC = Op -> getOperand ( <NUM_LIT> ) ;


<s> Parser . Lex ( ) ; auto & Id = Lexer . getTok ( ) ; if ( Id . getKind ( ) != AsmToken :: Identifier || Id . getLoc ( ) . getPointer ( ) != Name . end ( ) ) return Error ( <STR_LIT> , Id ) ; Name = StringRef ( Name . begin ( ) , Name . size ( ) + Id . getString ( ) . size ( ) ) ; Parser . Lex ( ) ; } Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , NameLoc , SMLoc :: getFromPointer ( Name . end ( ) ) , <STR_LIT> { Name } ) ) ; auto NamePair = Name . split ( '.' ) ; auto BaseName = NamePair . second . empty ( ) ? NamePair . first : NamePair . second ; while ( Lexer . isNot ( AsmToken :: EndOfStatement ) ) { auto & Tok = Lexer . getTok ( ) ; switch ( Tok . getKind ( ) ) { case AsmToken :: Identifier : { auto & Id = Lexer . getTok ( ) ; const MCExpr * Val ; SMLoc End ; if ( Parser . parsePrimaryExpr ( Val , End ) ) return Error ( <STR_LIT> , Lexer . getTok ( ) ) ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Id . getLoc ( ) , Id . getEndLoc ( ) , <STR_LIT> { Val } ) ) ; break ; } case AsmToken :: Minus : Parser . Lex ( ) ; if ( Lexer . isNot ( AsmToken :: Integer ) ) return Error ( <STR_LIT> , Lexer . getTok ( ) ) ; if ( ParseOperandStartingWithInteger ( true , Operands , BaseName ) ) return true ; break ; case AsmToken :: Integer : if ( ParseOperandStartingWithInteger ( false , Operands , BaseName ) ) return true ; break ; case AsmToken :: Real : { double Val ; if ( Tok . getString ( ) . getAsDouble ( Val , false ) ) return Error ( <STR_LIT> , Tok ) ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Tok . getLoc ( ) , Tok . getEndLoc ( ) , <STR_LIT> { Val } ) ) ; Parser . Lex ( ) ; break ; } default : return Error ( <STR_LIT> , Tok ) ; }

if ( Lexer . isNot ( AsmToken :: EndOfStatement ) ) {


<s> ArgInfo . ImplicitBufferPtr = ArgDescriptor :: createRegister ( TRI . getMatchingSuperReg ( getNextUserSGPR ( ) , <STR_LIT> , & <STR_LIT> ) ) ; NumUserSGPRs += <NUM_LIT> ; return ArgInfo . ImplicitBufferPtr . getRegister ( ) ;


<s> else if ( hard_regno < <NUM_LIT> ) return <NUM_LIT> ; else if ( hard_regno < <NUM_LIT> ) return <NUM_LIT> ; else return <NUM_LIT> ;


<s> MachineInstr * DPRMI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * SPRMI = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( DPRMI && SPRMI ) { MachineInstr * ECDef = elideCopies ( DPRMI ) ; if ( ECDef && ECDef -> isImplicitDef ( ) ) { MachineInstr * EC = elideCopies ( SPRMI ) ; if ( EC && EC -> isCopy ( ) && EC -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * SPRMI ) ; unsigned FullReg = SPRMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * TRC = MRI -> getRegClass ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( TRC -> hasSuperClassEq ( MRI -> getRegClass ( FullReg ) ) ) {


return ( __A [ <NUM_LIT> ] <= __B [ <NUM_LIT> ] ) ;


<s> Stack :: Stack ( MachineFunction & MF , size_t Size ) : TRI ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ) , MRI ( & MF . getRegInfo ( ) ) , Data ( Size , StackVreg ( <ISA_LIT>FunctionInfo :: UnusedReg ) ) {


<s> if ( ( TARGET_THUMB1 && rclass == LO_REGS ) || rclass == CC_REG ) return true ; return default_class_likely_spilled_p ( rclass ) ;


<s> const StringRef & RegName = Tok . getString ( ) ; RegNo = getRegForName ( RegName ) ; if ( RegNo ) { Parser . Lex ( ) ; return false ; } if ( RegName [ <NUM_LIT> ] != 's' && RegName [ <NUM_LIT> ] != 'v' ) return true ; bool IsVgpr = RegName [ <NUM_LIT> ] == 'v' ; unsigned RegWidth ; unsigned RegIndexInClass ; if ( RegName . size ( ) > <NUM_LIT> ) { RegWidth = <NUM_LIT> ; if ( RegName . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , RegIndexInClass ) ) return true ; Parser . Lex ( ) ; } else { int64_t RegLo , RegHi ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return true ; Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( RegLo ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return true ; Parser . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( RegHi ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: RBrac ) ) return true ; Parser . Lex ( ) ; RegWidth = ( RegHi - RegLo ) + <NUM_LIT> ; if ( IsVgpr ) { RegIndexInClass = RegLo ; } else { RegIndexInClass = RegLo / std :: min ( RegWidth , <NUM_LIT> ) ; } }

const MCRegisterInfo * TRC = getContext ( ) . getRegisterInfo ( ) ;


<s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> MF -> insert ( ++ LoopMBB -> getIterator ( ) , DoneMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( LoopMBB ) ; Register R = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , R ) . addImm ( <NUM_LIT> ) ;

BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( R , RegState :: Kill ) . addReg ( <STR_LIT> ) . addMBB ( LoopMBB ) ;


<s> const MCPhysReg * CSRegs = MRI . getCalleeSavedRegs ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumLanes ; ++ I , ++ NumVGPRSpillLanes ) { Register LaneVGPR ; unsigned VGPRIndex = ( NumVGPRSpillLanes % WaveSize ) ; if ( VGPRIndex == <NUM_LIT> && ! FuncInfo -> VGPRReservedForSGPRSpill ) { LaneVGPR = TRI -> findUnusedRegister ( MRI , & <STR_LIT> , MF ) ; if ( LaneVGPR == <STR_LIT> ) { SGPRToVGPRSpills . erase ( FI ) ; NumVGPRSpillLanes -= I ; return false ; } Optional < int > CSRSpillFI ; if ( ( FrameInfo . hasCalls ( ) || ! isEntryFunction ( ) ) && CSRegs && isCalleeSavedReg ( CSRegs , LaneVGPR ) ) { CSRSpillFI = FrameInfo . CreateSpillStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; }

SpillVGPRs . push_back ( SGPRSpillVGPRCSR ( LaneVGPR , CSRSpillFI ) ) ;


<s> RPTracker . advance ( ) ; } RPTracker . closeRegion ( ) ; TopRPTracker . addLiveRegs ( RPTracker . getPressure ( ) . LiveInRegs ) ; BotRPTracker . addLiveRegs ( RPTracker . getPressure ( ) . LiveOutRegs ) ; for ( const auto & RegMaskPair : RPTracker . getPressure ( ) . LiveInRegs ) { if ( TargetRegisterInfo :: isVirtualRegister ( RegMaskPair . RegUnit ) ) LiveInRegs . insert ( RegMaskPair . RegUnit ) ; } LiveOutRegs . clear ( ) ; for ( const auto & RegMaskPair : RPTracker . getPressure ( ) . LiveOutRegs ) { unsigned Reg = RegMaskPair . RegUnit ;

if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) && isDefBetween ( Reg , LIS -> getInstructionIndex ( BeginBlock ) . getRegSlot ( ) , LIS -> getInstructionIndex ( EndBlock ) . getRegSlot ( ) , MRI , LIS ) ) {


<s> return ( __m128 ) __builtin_ia32_rcpps ( ( __v4sf ) __A ) ;


<s> return ( TSFlags >> <NUM_LIT> ) & <NUM_LIT> ;


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned BasePtr = ( TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ) ; MI . getOperand ( i ) . ChangeToRegister ( BasePtr , false ) ; int Offset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; MI . setDesc ( TII . getMemoryInstr ( MI . getOpcode ( ) , Offset ) ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> return ( uint16x4_t ) __builtin_neon_vsubhnv4si ( ( int32x4_t ) __a , ( int32x4_t ) __b ) ;


<s> assert ( Op . getImm ( ) == <NUM_LIT> ) ; return nullptr ; } return cast < Function > ( Op . getGlobal ( ) ) ;


<s> assert ( hasVInstructions ( ) && <STR_LIT> ) ; assert ( RVVVectorLMULMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorLMULMax ) && <STR_LIT> ) ;

return PowerOf2Floor ( std :: max < unsigned > ( std :: min < unsigned > ( RVVVectorLMULMax , <NUM_LIT> ) , <NUM_LIT> ) ) ;


<s> case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 ) , GPR3 ) . addReg ( GPR3 ) ) ; Call -> addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: COPY ) , OutReg ) . addReg ( GPR3 ) ; MachineBasicBlock :: iterator Last = I ; -- Last ; ++ I ; MI -> removeFromParent ( ) ; LIS -> repairIntervalsInRange ( & MBB , First , Last , OrigRegs ) ; Changed = true ; }


<s> first_v = node_v ; while ( first_v -> prev != NULL ) first_v = first_v -> prev ; default_version_info = first_v ; while ( default_version_info != NULL ) { const tree decl2 = default_version_info -> this_node -> decl ; if ( is_function_default_version ( decl2 ) ) break ; default_version_info = default_version_info -> next ; } if ( default_version_info == NULL ) return NULL ; if ( first_v != default_version_info ) { default_version_info -> prev -> next = default_version_info -> next ; if ( default_version_info -> next ) default_version_info -> next -> prev = default_version_info -> prev ; first_v -> prev = default_version_info ; default_version_info -> next = first_v ; default_version_info -> prev = NULL ; } default_node = default_version_info -> this_node ; error_at ( DECL_SOURCE_LOCATION ( default_node -> decl ) , <STR_LIT> <STR_LIT> ) ; if ( targetm . has_ifunc_p ( ) ) { struct cgraph_function_version_info * it_v = NULL ;

struct cgraph_node * dispatcher_node = NULL ;


<s> return ( int8x8_t ) __builtin_neon_vdup_lanev8qi ( __a , __b ) ;


<s> else return pReloc . symInfo ( ) -> outSymbol ( ) -> fragRef ( ) -> offset ( ) + pReloc . target ( ) + pReloc . addend ( ) ;


return TargetTriple . getVendor ( ) == Triple :: BGP ;


<s> GlobalVariable * GV = I ++ ; if ( GV -> getType ( ) -> getAddressSpace ( ) == llvm :: ADDRESS_SPACE_GENERIC && ! llvm :: isTexture ( * GV ) && ! llvm :: isSurface ( * GV ) && ! llvm :: isSampler ( * GV ) && ! GV -> getName ( ) . startswith ( <STR_LIT> ) ) { GlobalVariable * NewGV = new GlobalVariable ( M , GV -> getType ( ) -> getElementType ( ) , GV -> isConstant ( ) , GV -> getLinkage ( ) , GV -> hasInitializer ( ) ? GV -> getInitializer ( ) : nullptr , <STR_LIT> , GV , GV -> getThreadLocalMode ( ) , llvm :: ADDRESS_SPACE_GLOBAL ) ; NewGV -> copyAttributesFrom ( GV ) ; GVMap [ GV ] = NewGV ; } } if ( GVMap . empty ( ) ) { return false ; } for ( Module :: iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) { if ( I -> isDeclaration ( ) ) { continue ; }

IRBuilder < > Builder ( I -> getEntryBlock ( ) . getFirstNonPHIOrDbg ( ) ) ;


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; return true ; } return false ;


<s> SDValue Increment = DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Alignment ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , std :: min ( <NUM_LIT> , Alignment ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getUNDEF ( RegVT ) ; NewVec = Insert128BitVector ( NewVec , Load1 , <NUM_LIT> , DAG , dl ) ; NewVec = Insert128BitVector ( NewVec , Load2 , NumElems / <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo ( N , NewVec , TF , true ) ;


<s> case V4HImode : gen = gen_neon_vrev64v4hi ; break ; case V8HFmode : gen = gen_neon_vrev64v8hf ; break ; case V4HFmode : gen = gen_neon_vrev64v4hf ; break ; default : return false ; } break ; case <NUM_LIT> : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev16v16qi ; break ; case V8QImode : gen = gen_neon_vrev16v8qi ; break ; case V8HImode : gen = gen_neon_vrev32v8hi ; break ; case V4HImode : gen = gen_neon_vrev32v4hi ; break ; case V4SImode : gen = gen_neon_vrev64v4si ; break ; case V2SImode : gen = gen_neon_vrev64v2si ; break ; case V4SFmode : gen = gen_neon_vrev64v4sf ; break ; case V2SFmode : gen = gen_neon_vrev64v2sf ; break ; default :


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent ( ) ; return BB ;


<s> case LABEL_REF : case CONST : return <NUM_LIT> ; case CONST_INT : return ( LARGE_INT ( INTVAL ( op ) ) ) ; case CONST_DOUBLE : if ( mode == SImode ) return arc_double_limm_p ( op ) ; if ( mode == SFmode ) return GET_MODE ( op ) == SFmode ; return <NUM_LIT> ; case REG : return register_operand ( op , mode ) ; case SUBREG : if ( GET_CODE ( SUBREG_REG ( op ) ) == MEM ) return address_operand ( XEXP ( SUBREG_REG ( op ) , <NUM_LIT> ) , mode ) ; else return register_operand ( op , mode ) ; case MEM : return address_operand ( XEXP ( op , <NUM_LIT> ) , mode ) ; default : return <NUM_LIT> ;


<s> rtx l , h , t , sign ; sign = ia64_unpack_sign ( operands [ <NUM_LIT> ] , unsignedp ) ; wmode = GET_MODE ( operands [ <NUM_LIT> ] ) ; l = gen_reg_rtx ( wmode ) ; h = gen_reg_rtx ( wmode ) ; ia64_unpack_assemble ( l , operands [ <NUM_LIT> ] , sign , false ) ; ia64_unpack_assemble ( h , operands [ <NUM_LIT> ] , sign , true ) ; t = expand_binop ( wmode , add_optab , l , operands [ <NUM_LIT> ] , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; t = expand_binop ( wmode , add_optab , h , t , operands [ <NUM_LIT> ] , <NUM_LIT> , OPTAB_DIRECT ) ; if ( t != operands [ <NUM_LIT> ] ) emit_move_insn ( operands [ <NUM_LIT> ] , t ) ;


<s> CurInstKind = IDOther ; CurEmitted = <NUM_LIT> ; OccupedSlotsMask = <NUM_LIT> ; InstKindLimit [ IDAlu ] = TII -> getMaxAlusPerClause ( ) ; InstKindLimit [ IDOther ] = <NUM_LIT> ; InstKindLimit [ IDFetch ] = ST . getTexVTXClauseSize ( ) ; AluInstCount = <NUM_LIT> ; FetchInstCount = <NUM_LIT> ;


<s> assert ( T < NUM_INST_CNTS ) ; if ( T >= NUM_INST_CNTS ) return ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: riscv32 > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> case 'L' : case 'M' : case 'N' : case 'O' : if ( isa < ConstantInt > ( CallOperandVal ) ) Weight = CW_Constant ; break ; default : Weight = TargetLowering :: getSingleConstraintMatchWeight ( Info , Constraint ) ; break ; } return Weight ;


<s> if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; unsigned NumSignBits = DAG . ComputeNumSignBits ( In ) ; unsigned NumPackedBits = std :: min < unsigned > ( SVT . getSizeInBits ( ) , <NUM_LIT> ) ; if ( NumSignBits > ( InSVT . getSizeInBits ( ) - NumPackedBits ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , In , DL , DAG , Subtarget ) ; KnownBits Known ; DAG . computeKnownBits ( In , Known ) ; unsigned NumLeadingZeroBits = Known . countMinLeadingZeros ( ) ;

NumPackedBits = Subtarget . hasSSE41 ( ) ? NumPackedBits : <NUM_LIT> ;


<s> EmitFStart ( CurrentFnSymForSize , CurrCodeEnd , FStartAlignment ) ; AsmPrinter :: emitFunctionEntryLabel ( ) ;


<s> if ( DstB != <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MCDisassembler :: Fail ; } SrcC = decodeCField ( Insn ) ;

DecodeGPR32RegisterClass ( Inst , SrcC , Address , Decoder ) ;


<s> machine_mode sh_hard_regno_caller_save_mode ( unsigned int regno , unsigned int nregs , machine_mode mode ) { if ( FP_REGISTER_P ( regno ) && ( mode == SFmode || mode == SCmode || ( ( mode == DFmode || mode == DCmode ) && ( ( regno - FIRST_FP_REG ) & <NUM_LIT> ) == <NUM_LIT> ) ) ) return mode ;

return choose_hard_reg_mode ( regno , nregs , NULL ) ;


<s> return by_pieces_ninsns ( size , align , MOVE_MAX_PIECES + <NUM_LIT> , op ) < ( ! speed_p ? <NUM_LIT> : ( align >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; case STORE_BY_PIECES :


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>leTarget ) ;

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( The<ISA_LIT>beTarget ) ;


<s> if ( SCHED_GROUP_P ( tmp ) != SCHED_GROUP_P ( tmp2 ) ) return SCHED_GROUP_P ( tmp2 ) ? <NUM_LIT> : - <NUM_LIT> ; return INSN_LUID ( tmp ) - INSN_LUID ( tmp2 ) ;


<s> NodeId getReachingDef ( ) const { return Ref . RD ;


<s> if ( isZero ( Elt ) ) return true ; if ( ConstantFPSDNode * CFP = dyn_cast < ConstantFPSDNode > ( Elt ) ) return CFP -> getValueAPF ( ) . isPosZero ( ) ;


<s> Error ( Loc , <STR_LIT> ) ; return <STR_LIT> ; } Tokens . push_back ( getToken ( ) ) ; lex ( ) ; RegKind = RI -> Kind ; StringRef RegSuffix = RegName . substr ( RI -> Name . size ( ) ) ; if ( ! RegSuffix . empty ( ) ) { if ( ! getRegNum ( RegSuffix , RegNum ) ) { Error ( Loc , <STR_LIT> ) ; return <STR_LIT> ; } RegWidth = <NUM_LIT> ; } else { if ( ! ParseRegRange ( RegNum , RegWidth ) ) return <STR_LIT> ; } return getRegularReg ( RegKind , RegNum , RegWidth , Loc ) ;


<s> HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasSGX = false ; HasPRFCHW = false ; HasRDSEED = false ; HasSMAP = false ; IsBTMemSlow = false ; IsSHLDSlow = false ; IsUAMemFast = false ; HasVectorUAMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasSlowDivide = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false ; SlowLEA = false ; SlowIncDec = false ;


<s> assert ( Regs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; KindTy Kind = k_RegisterList ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Regs . front ( ) . second ) ) Kind = k_DPRRegisterList ; else if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Regs . front ( ) . second ) ) Kind = k_SPRRegisterList ; array_pod_sort ( Regs . begin ( ) , Regs . end ( ) ) ; auto Op = make_unique < <ISA_LIT>Operand > ( Kind ) ; for ( SmallVectorImpl < std :: pair < unsigned , unsigned > > :: const_iterator I = Regs . begin ( ) , E = Regs . end ( ) ; I != E ; ++ I ) Op -> Registers . push_back ( I -> second ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( unsigned Kind ) const {


<s> return __builtin_aarch64_lrounduhfhi_us ( __a ) ;


<s> if ( fn == cfun ) return ( ( rs6000_isa_flags & OPTION_MASK_PCREL ) != <NUM_LIT> && TARGET_CMODEL == CMODEL_MEDIUM ) ; return rs6000_fndecl_pcrel_p ( fn -> decl ) ;


<s> default : return false ; case <STR_LIT> : { EVT PtrTy = TLI . getPointerTy ( ) ; const Value * Op1 = I . getArgOperand ( <NUM_LIT> ) ; const AllocaInst * Slot = cast < AllocaInst > ( I . getArgOperand ( <NUM_LIT> ) ) ; <ISA_LIT>AddressMode AM ; if ( ! <ISA_LIT>SelectAddress ( Slot , AM ) ) return false ; if ( ! <ISA_LIT>FastEmitStore ( PtrTy , Op1 , AM ) ) return false ; return true ; } case <STR_LIT> : { ConstantInt * CI = dyn_cast < ConstantInt > ( I . getArgOperand ( <NUM_LIT> ) ) ; const Type * Ty = I . getCalledFunction ( ) -> getReturnType ( ) ; assert ( CI && <STR_LIT> ) ; MVT VT ; if ( ! isTypeLegal ( Ty , VT ) ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( OpC ) , ResultReg ) . addImm ( CI -> isZero ( ) ? - <NUM_LIT> : <NUM_LIT> ) ; UpdateValueMap ( & I , ResultReg ) ; return true ; } case <STR_LIT> : { const DbgDeclareInst * DI = cast < DbgDeclareInst > ( & I ) ; <ISA_LIT>AddressMode AM ;

assert ( DI -> getAddress ( ) && <STR_LIT> ) ;


<s> else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ;


<s> unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; switch ( Opc ) { case G_TRUNC : case G_ADD : case G_SUB : case G_MUL : case G_LOAD : case G_STORE : case G_ZEXTLOAD : case G_SEXTLOAD : case G_GEP : case G_AND : case G_OR : case G_XOR : case G_SHL : case G_ASHR : case G_LSHR : case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; break ; case G_CONSTANT : case G_FRAME_INDEX : case G_GLOBAL_VALUE : case G_BRCOND : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr } ) ; break ; case G_ICMP : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , nullptr , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ; case G_SELECT : OperandsMapping = getOperandsMapping ( { & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] , & <STR_LIT> [ <STR_LIT> ] } ) ; break ;


<s> Shuffle = <STR_LIT> ; ShuffleVT = MaskVT ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && ( AllowFloatDomain || ! Subtarget . hasSSE41 ( ) ) ) { Shuffle = <STR_LIT> ; ShuffleVT = MaskVT ; return true ; } }

if ( ( MaskVT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && <NUM_LIT> <= EltSizeInBits && Subtarget . hasAVX ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) {


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Immediate ) ;


<s> SDLoc dl ( Op ) ; if ( VT . is512BitVector ( ) || InVT . getVectorElementType ( ) == <STR_LIT> ) return LowerSIGN_EXTEND_AVX512 ( Op , Subtarget , DAG ) ; if ( ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) && ( VT != <STR_LIT> || InVT != <STR_LIT> ) ) return SDValue ( ) ; if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; unsigned NumElems = InVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask1 [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ; SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask2 [ <NUM_LIT> ] ) ; MVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , HalfVT , OpHi ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpHi ) ;


<s> return __builtin_ia32_vcvtuqq2ph512_mask_round ( ( __v8di ) __B , _mm_setzero_ph ( ) , __A , __C ) ;


<s> explicit RedundantLdStEliminator ( MachineFunction & mf , const <ISA_LIT>RegisterInfo * tri , unsigned int tgtreg , const <ISA_LIT>MachineFunctionInfo & PMFI ) : MF ( mf ) , TRI ( tri ) , TgtReg ( tgtreg ) , NumFIs ( PMFI . getSinglePathFICnt ( ) ) , OffsetFIs ( PMFI . getSinglePathLoopCntFI ( <NUM_LIT> ) ) {


<s> ImplicitOp . setImplicit ( ) ; NewSrc = get<ISA_LIT>SubSuperRegister ( Src . getReg ( ) , <NUM_LIT> ) ; isKill = Src . isKill ( ) ; isUndef = Src . isUndef ( ) ; } else { NewSrc = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( NewSrc , RegState :: Define | RegState :: Undef , <STR_LIT> ) . addOperand ( Src ) ; isKill = true ; isUndef = false ; } return true ;


<s> unsigned Imm ; if ( ! isInt32Immediate ( N -> getOperand ( <NUM_LIT> ) , Imm ) ) return false ; SDLoc dl ( N ) ; SDValue Val = N -> getOperand ( <NUM_LIT> ) ; unsigned SH , MB , ME ; if ( isRotateAndMask ( Val . getNode ( ) , Imm , false , SH , MB , ME ) ) { Val = Val . getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { Val , getI32Imm ( SH , dl ) , getI32Imm ( MB , dl ) , getI32Imm ( ME , dl ) } ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } if ( isRunOfOnes ( Imm , MB , ME ) && Val . getOpcode ( ) != <STR_LIT> ) { SDValue Ops [ ] = { Val , getI32Imm ( <NUM_LIT> , dl ) , getI32Imm ( MB , dl ) , getI32Imm ( ME , dl ) } ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ; return true ; } if ( Imm == <NUM_LIT> ) { ReplaceUses ( SDValue ( N , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return true ; }


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const override {


<s> const char * <ISA_LIT>AsmPrinter :: getCurrentABIString ( ) const { switch ( Subtarget -> getTargetABI ( ) ) { case <ISA_LIT>Subtarget :: O32 : return <STR_LIT> ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { unsigned Opc ; DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) Opc = <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = <STR_LIT> ; else if ( RC == <STR_LIT> ) Opc = <STR_LIT> ;

else assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Vd = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned regs = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( regs == <NUM_LIT> || regs > <NUM_LIT> || ( Vd + regs ) > <NUM_LIT> ) { regs = Vd + regs > <NUM_LIT> ? <NUM_LIT> - Vd : regs ; regs = std :: max ( <NUM_LIT> , regs ) ;

regs = std :: min ( <NUM_LIT> , regs ) ;


<s> SDValue Const1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Const31 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Res ; SDValue X = ( TyX == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; SDValue Y = ( TyY == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasR2 ) { SDValue E = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Y , Const31 , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , Const31 , Const1 , X ) ; } else { SDValue SllX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Const1 ) ; SDValue SrlX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX , Const1 ) ; SDValue SrlY = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Y , Const31 ) ;

SDValue SllY = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SrlY , Const31 ) ;


<s> bool isVecListOneD ( ) const { if ( ! isSingleSpacedVectorList ( ) ) return false ; return VectorList . Count == <NUM_LIT> ;


<s> BucketElement ( const SCEVConstant * O , Instruction * I ) : Offset ( O ) , Instr ( I ) {


<s> ~ <ISA_LIT>AsmBackend ( ) override {


<s> return __builtin_mve_vclzq_m_uv4si ( __arm_vuninitializedq_u32 ( ) , __a , __p ) ;


<s> if ( I -> isReturnBlock ( ) ) { bool FoundIt = false ; for ( MBBI = I -> end ( ) ; MBBI != I -> begin ( ) ; ) { -- MBBI ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { MBBI -> eraseFromParent ( ) ; FoundIt = true ; break ; } } RemovedAllMTVRSAVEs &= FoundIt ; }


<s> __rv . __o = __builtin_neon_vld2v4si ( ( const __builtin_neon_si * ) __a ) ;


<s> return DAG . getStore ( Chain , DL , DAG . getConstant ( * CI , DL , VT ) , InitPtr , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , TD . getPrefTypeAlignment ( InitTy ) ) ; } if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( Init ) ) { EVT VT = EVT :: getEVT ( CFP -> getType ( ) ) ; PointerType * PtrTy = PointerType :: get ( CFP -> getType ( ) , <NUM_LIT> ) ; return DAG . getStore ( Chain , DL , DAG . getConstantFP ( * CFP , DL , VT ) , InitPtr , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , TD . getPrefTypeAlignment ( CFP -> getType ( ) ) ) ; } if ( StructType * ST = dyn_cast < StructType > ( InitTy ) ) { const StructLayout * SL = TD . getStructLayout ( ST ) ; EVT PtrVT = InitPtr . getValueType ( ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned I = <NUM_LIT> , N = ST -> getNumElements ( ) ; I != N ; ++ I ) {

SDValue Offset = DAG . getConstant ( SL -> getElementOffset ( I ) , DL , PtrVT ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool is64Bit ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , is64Bit ) , DataLayout ( Subtarget . getTargetDataString ( ) ) , InstrInfo ( * this ) , FrameInfo ( * this , is64Bit ) , JITInfo ( * this , is64Bit ) , TLInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , MachOWriterInfo ( * this ) { if ( getRelocationModel ( ) == Reloc :: Default ) {

if ( Subtarget . isDarwin ( ) ) setRelocationModel ( Reloc :: DynamicNoPIC ) ;


<s> bool aarch64_use_return_insn_p ( void ) { if ( ! reload_completed ) return false ; if ( crtl -> profile ) return false ;

return known_eq ( cfun -> machine -> frame . frame_size , <NUM_LIT> ) ;


<s> MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; ITState . CurPosition = ~ <NUM_LIT> ; NextSymbolIsThumb = false ;


<s> call_used_regs [ i ] = <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( tiny_reg_alloc_order ) ; i ++ ) { reg_alloc_order [ i ] = tiny_reg_alloc_order [ i ] ; } CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) ADDW_REGS ] ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) NO_LD_REGS ] ) ; }


<s> static SDValue convertIntLogicToFPLogic ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N10 = N1 . getOperand ( <NUM_LIT> ) ; EVT N00Type = N00 . getValueType ( ) ; EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; unsigned FPOpcode ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;

case <STR_LIT> : FPOpcode = <STR_LIT> ; break ;


<s> if ( Pmode == DImode ) return gen_got_load_tls_gddi ( dest , sym ) ;

else return gen_got_load_tls_gdsi ( dest , sym ) ;


<s> if ( TT . getArch ( ) == Triple :: r600 ) return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ; return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool IsSlowLEA = ST . slowLEA ( ) ; bool IsSlow3OpsLEA = ST . slow3OpsLEA ( ) ; bool LEAUsesAG = ST . LEAusesAG ( ) ; bool OptIncDec = ! ST . slowIncDec ( ) || MF . getFunction ( ) . hasOptSize ( ) ; bool UseLEAForSP = ST . useLeaForSP ( ) ; TSM . init ( & ST ) ; TII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! isLEA ( I -> getOpcode ( ) ) ) continue ; if ( optTwoAddrLEA ( I , MBB , OptIncDec , UseLEAForSP ) ) continue ; if ( IsSlowLEA ) processInstructionForSlowLEA ( I , MBB ) ; else if ( IsSlow3OpsLEA ) processInstrForSlow3OpLEA ( I , MBB , OptIncDec ) ;


<s> StringRef getToken ( ) const { assert ( Kind == Token && <STR_LIT> ) ;

return StringRef ( Tok . Data , Tok . Length ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ;


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectVSplatMaskL ( SDValue N , SDValue & Imm ) const { APInt ImmValue ; EVT EltTy = N -> getValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) N = N -> getOperand ( <NUM_LIT> ) ; if ( selectVSplat ( N . getNode ( ) , ImmValue , EltTy . getSizeInBits ( ) ) && ImmValue . getBitWidth ( ) == EltTy . getSizeInBits ( ) ) { if ( ImmValue == ~ ( ~ ImmValue & ~ ( ~ ImmValue + <NUM_LIT> ) ) ) { Imm = CurDAG -> getTargetConstant ( ImmValue . countPopulation ( ) - <NUM_LIT> , SDLoc ( N ) , EltTy ) ; return true ; } } return false ;


<s> void <ISA_LIT>PALMetadata :: setSpiPsInputEna ( unsigned Val ) {

setRegister ( PALMD :: R_A1B3_SPI_PS_INPUT_ENA , Val ) ;


<s> MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ;


<s> void AMDGPUCFGStructurizer :: insertInstrEnd ( MachineBasicBlock * MBB , int NewOpcode , DebugLoc DL ) { MachineInstr * MI = MBB -> getParent ( ) -> CreateMachineInstr ( TII -> get ( NewOpcode ) , DL ) ; MBB -> push_back ( MI ) ;


<s> bool <ISA_LIT>WinCOFFTargetStreamer :: emitFPOData ( const MCSymbol * ProcSym , SMLoc L ) { MCStreamer & OS = getStreamer ( ) ; MCContext & Ctx = OS . getContext ( ) ; auto I = AllFPOData . find ( ProcSym ) ; if ( I == AllFPOData . end ( ) ) { Ctx . reportError ( L , Twine ( <STR_LIT> ) + ProcSym -> getName ( ) ) ; return true ; } const FPOData * FPO = I -> second . get ( ) ; assert ( FPO -> Begin && FPO -> End && FPO -> PrologueEnd && <STR_LIT> ) ; MCSymbol * FrameBegin = Ctx . createTempSymbol ( ) , * FrameEnd = Ctx . createTempSymbol ( ) ; OS . EmitIntValue ( unsigned ( DebugSubsectionKind :: FrameData ) , <NUM_LIT> ) ; OS . emitAbsoluteSymbolDiff ( FrameEnd , FrameBegin , <NUM_LIT> ) ; OS . EmitLabel ( FrameBegin ) ; OS . EmitValue ( MCSymbolRefExpr :: create ( FPO -> Function , MCSymbolRefExpr :: VK_COFF_IMGREL32 , Ctx ) , <NUM_LIT> ) ; FPOStateMachine FSM ( FPO ) ; FSM . emitFrameDataRecord ( OS , FPO -> Begin ) ; for ( const FPOInstruction & Inst : FPO -> Instructions ) { switch ( Inst . Op ) { case FPOInstruction :: PushReg : FSM . CurOffset += <NUM_LIT> ; FSM . SavedRegSize += <NUM_LIT> ; FSM . RegSaveOffsets . push_back ( { Inst . RegOrOffset , FSM . CurOffset } ) ; break ; case FPOInstruction :: SetFrame : FSM . FrameReg = Inst . RegOrOffset ; FSM . FrameRegOff = FSM . CurOffset ; break ; case FPOInstruction :: StackAlign :

FSM . StackOffsetBeforeAlign = FSM . CurOffset ;


<s> if ( UserI -> getOperand ( i ) == FoldedValue ) continue ; if ( Instruction * OtherOp = dyn_cast < Instruction > ( UserI -> getOperand ( i ) ) ) { LoadInst * OtherLoad = dyn_cast < LoadInst > ( OtherOp ) ; if ( ! OtherLoad && ( isa < TruncInst > ( OtherOp ) || isa < SExtInst > ( OtherOp ) || isa < ZExtInst > ( OtherOp ) ) ) OtherLoad = dyn_cast < LoadInst > ( OtherOp -> getOperand ( <NUM_LIT> ) ) ; if ( OtherLoad && isFoldableLoad ( OtherLoad , FoldedValue ) ) return i == <NUM_LIT> ; } } return <NUM_LIT> ; } } unsigned NumOps = ( Src -> isVectorTy ( ) ? getNumVectorRegs ( Src ) : getNumberOfParts ( Src ) ) ; if ( ( ( ! Src -> isVectorTy ( ) && NumOps == <NUM_LIT> ) || ST -> hasVectorEnhancements2 ( ) ) && I != nullptr ) { if ( Opcode == Instruction :: Load && I -> hasOneUse ( ) ) { const Instruction * LdUser = cast < Instruction > ( * I -> user_begin ( ) ) ;

if ( isBswapIntrinsicCall ( LdUser ) && ( ! LdUser -> hasOneUse ( ) || ! isa < StoreInst > ( * LdUser -> user_begin ( ) ) ) ) return <NUM_LIT> ;


<s> rtx op = gen_rtx_fmt_ee ( code , SFmode , op1 , op2 ) ; emit_insn ( gen_binary_sf_op0 ( op0 , op1 , op2 , op ) ) ;


<s> if ( IPtr -> second . Switches . size ( ) == <NUM_LIT> && ( * IPtr -> second . Switches . begin ( ) ) -> Name . equals ( <STR_LIT> ) ) return false ;


<s> cfun -> machine -> force_align_arg_pointer = gen_rtx_REG ( Pmode , <NUM_LIT> ) ;

return copy_to_reg ( cfun -> machine -> force_align_arg_pointer ) ;


<s> if ( <STR_LIT> ( LD ) ) { return false ; } } else if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Op = ST -> getBasePtr ( ) . getNode ( ) ; if ( <STR_LIT> ( ST ) ) { return false ; } } else { return false ; } if ( VT != <STR_LIT> && VT != <STR_LIT> ) { return false ; } if ( Op -> getOpcode ( ) != <STR_LIT> && Op -> getOpcode ( ) != <STR_LIT> ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( VT == <STR_LIT> && RHSC != - <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != - <NUM_LIT> ) ) {


<s> return B -> empty ( ) || ( & * B -> begin ( ) == B -> getTerminator ( ) ) ;


<s> unsigned <ISA_LIT>FastISel :: <ISA_LIT>MaterializeInt ( const Constant * C , MVT VT ) { if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return <NUM_LIT> ; const TargetRegisterClass * RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; const ConstantInt * CI = cast < ConstantInt > ( C ) ; if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) {

unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> case <STR_LIT> : SDValue Src1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Src2 = Op . getOperand ( <NUM_LIT> ) ; SDValue Src3 = Op . getOperand ( <NUM_LIT> ) ; SDValue Src4 = Op . getOperand ( <NUM_LIT> ) ; if ( Src3 -> isUndef ( ) ) { copyNode = DAG . getMachineNode ( TargetOpcode :: COPY , dl , <STR_LIT> , Src2 ) ; copy = SDValue ( copyNode , <NUM_LIT> ) ; } else { copy = Src3 ; } unsigned dim = cast < ConstantSDNode > ( Src4 ) -> getZExtValue ( ) ; SDValue DimVal = DAG . getTargetConstant ( dim , dl , <STR_LIT> ) ; SDValue Val ; unsigned IRFOpcode ; bool isImmOperand ; if ( auto Scl = dyn_cast < ConstantSDNode > ( Src1 ) ) { unsigned v = Scl -> getZExtValue ( ) ; Val = DAG . getTargetConstant ( v , dl , <STR_LIT> ) ; isImmOperand = true ; } else { Val = Src1 ; isImmOperand = false ; } IRFOpcode = getIRFOpcodeForIntrin ( IntNo , isImmOperand ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = Val ;


<s> return ! ( ( is<ISA_LIT>CtrInstruction ( MI ) && is<ISA_LIT>MemInstruction ( MI0 ) ) || ( is<ISA_LIT>CtrInstruction ( MI0 ) && is<ISA_LIT>MemInstruction ( MI ) ) ) ; case <NUM_LIT> :


<s> return emitBPOSGE32 ( MI , BB ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> :


<s> if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op ; } SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( IsDouble && ( iVal & <NUM_LIT> ) != ( iVal >> <NUM_LIT> ) ) return SDValue ( ) ; SDValue NewVal = isVMOVModifiedImm ( iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMOVModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } NewVal = isVMOVModifiedImm ( ~ iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMVNModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } return SDValue ( ) ;


<s> tree loongarch_builtin_decl ( unsigned int code , bool initialize_p ATTRIBUTE_UNUSED ) { if ( code >= ARRAY_SIZE ( loongarch_builtins ) ) return error_mark_node ; return loongarch_builtin_decls [ code ] ;


<s> if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs , FloatRegsSize ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT . isFloatingPoint ( ) && ! AllocateFloatsInIntReg ) { if ( ValVT == <STR_LIT> ) { Reg = State . AllocateReg ( F32Regs , FloatRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } else { Reg = State . AllocateReg ( F64Regs , FloatRegsSize ) ; unsigned Reg2 = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( Reg2 == <STR_LIT> || Reg2 == <STR_LIT> ) State . AllocateReg ( IntRegs , IntRegsSize ) ; State . AllocateReg ( IntRegs , IntRegsSize ) ; } } else llvm_unreachable ( <STR_LIT> ) ; unsigned SizeInBytes = ValVT . getSizeInBits ( ) >> <NUM_LIT> ; unsigned Offset ;

if ( ! ArgFlags . isSRet ( ) ) Offset = State . AllocateStack ( SizeInBytes , OrigAlign ) ;


<s> const MCOperand & MO = MI -> getOperand ( opNum ) ;

if ( MO . isImm ( ) ) O << ( unsigned short int ) MO . getImm ( ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ;


<s> unsigned getMemOffsetRegShifted ( ) const { assert ( Mem . OffsetIsReg && <STR_LIT> ) ; return Mem . OffsetRegShifted ;


<s> explicit <ISA_LIT>AsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCContext & Ctx , MCStreamer & Streamer , const MCAsmInfo * T ) : AsmPrinter ( O , TM , Ctx , Streamer , T ) , AFI ( NULL ) , MCP ( NULL ) {

Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> getSImm3Lsa2Value ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) { int Value = MO . getImm ( ) ; return Value >> <NUM_LIT> ;


<s> static SDValue rebuildGatherScatter ( MaskedGatherScatterSDNode * GorS , SDValue Index , SDValue Base , SDValue Scale , SelectionDAG & DAG ) { SDLoc DL ( GorS ) ; if ( auto * Gather = dyn_cast < MaskedGatherSDNode > ( GorS ) ) { SDValue Ops [ ] = { Gather -> getChain ( ) , Gather -> getPassThru ( ) , Gather -> getMask ( ) , Base , Index , Scale } ; return DAG . getMaskedGather ( Gather -> getVTList ( ) , Gather -> getMemoryVT ( ) , DL , Ops , Gather -> getMemOperand ( ) , Gather -> getIndexType ( ) ) ; } auto * Scatter = cast < MaskedScatterSDNode > ( GorS ) ; SDValue Ops [ ] = { Scatter -> getChain ( ) , Scatter -> getValue ( ) , Scatter -> getMask ( ) , Base , Index , Scale } ; return DAG . getMaskedScatter ( Scatter -> getVTList ( ) , Scatter -> getMemoryVT ( ) , DL , Ops , Scatter -> getMemOperand ( ) , Scatter -> getIndexType ( ) ) ;


<s> <ISA_LIT>AsmPrinter :: <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> n_regs = end_reg - start_reg ; p = rtvec_alloc ( <NUM_LIT> + ( ( sel & SAVRES_LR ) ? <NUM_LIT> : <NUM_LIT> ) + ( ( sel & SAVRES_REG ) == SAVRES_VR ? <NUM_LIT> : <NUM_LIT> ) + n_regs ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , offset ++ ) = ret_rtx ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; sym = rs6000_savres_routine_sym ( info , sel ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , sym ) ; use_reg = ptr_regno_for_savres ( sel ) ; if ( ( sel & SAVRES_REG ) == SAVRES_VR ) { RTVEC_ELT ( p , offset ++ ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ;


<s> if ( ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) || ( ExtVal == <NUM_LIT> && EltTy == <STR_LIT> ) ) return Src ; APInt Mask = C -> getAPIntValue ( ) . trunc ( EltTy . getSizeInBits ( ) ) ; Dup = DAG . getNode ( <STR_LIT> , DL , UnpkOp -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( Mask . zextOrTrunc ( <NUM_LIT> ) , DL , <STR_LIT> ) ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , UnpkOp -> getValueType ( <NUM_LIT> ) , UnpkOp , Dup ) ; return DAG . getNode ( Opc , DL , N -> getValueType ( <NUM_LIT> ) , And ) ; } if ( ! EnableCombineMGatherIntrinsics ) return SDValue ( ) ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ; if ( ! Src . hasOneUse ( ) ) return SDValue ( ) ; EVT MemVT ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemVT = cast < VTSDNode > ( Src -> getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> <STR_LIT> Flags = Outs [ i ] . Flags ; EVT ArgVT = Outs [ i ] . VT ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) { if ( ! isVarArg && ! is<ISA_LIT>64 ) { nAltivecParamsAtEnd ++ ; continue ; } NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; } NumBytes += CalculateStackSlotSize ( ArgVT , Flags , PtrByteSize ) ; } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameLowering :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ;

if ( CC == CallingConv :: Fast && DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) {


<s> { int i = INTVAL ( x ) ; char dwspec ; switch ( i ) { case <NUM_LIT> : dwspec = 'b' ; break ; case <NUM_LIT> : dwspec = 's' ; break ; case <NUM_LIT> : dwspec = 'l' ; break ; default : if ( ( i % <NUM_LIT> ) != <NUM_LIT> ) internal_error ( <STR_LIT> , i ) ; else dwspec = 'l' ; break ; } fprintf ( file , <STR_LIT> , dwspec ) ; return ; } case 'f' : { int bf = ft32_as_bitfield ( INTVAL ( x ) ) ; fprintf ( file , <STR_LIT> , bf >> <NUM_LIT> , bf & <NUM_LIT> ) ;


<s> SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) {


<s> SCANode * makeRoot ( MCGNode * node , unsigned int maxdisplacment , bool hascallfreepath ) { assert ( Nodes . empty ( ) ) ; unsigned rootoccupancy = RootOccupied ? STC . getStackCacheSize ( ) : <NUM_LIT> ; CostPair occupancyCosts ( rootoccupancy , rootoccupancy ) ; CostPair spillCosts ( <NUM_LIT> , <NUM_LIT> ) ; Root = new SCANode ( node , occupancyCosts , maxdisplacment , spillCosts , hascallfreepath ) ; Root -> yId = yamlId ++ ; Nodes [ std :: make_pair ( node , occupancyCosts ) ] = Root ; return Root ;


<s> return new pass_rl78_devirt ( ctxt ) ;


<s> MachineInstr * <ISA_LIT>MachineCFGStructurizer :: getNormalBlockBranchInstr ( MachineBasicBlock * MBB ) { MachineBasicBlock :: reverse_iterator It = MBB -> rbegin ( ) ; MachineInstr * MI = & * It ;

if ( MI && ( isCondBranch ( MI ) || isUncondBranch ( MI ) ) ) return MI ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> SDLoc dl ( Op ) ; auto * C = cast < ConstantSDNode > ( ScaleOp ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; EVT MaskVT = Mask . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . isUndef ( ) || <STR_LIT> ( Mask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; SDValue Ops [ ] = { Src , Base , Scale , Index , Disp , Segment , Mask , Chain } ; SDNode * Res = DAG . getMachineNode ( Opc , dl , VTs , Ops ) ; SDValue RetOps [ ] = { SDValue ( Res , <NUM_LIT> ) , SDValue ( Res , <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps , dl ) ;


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MBBI ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; for ( const auto & Info : CSI ) { unsigned Reg = Info . getReg ( ) ; int64_t Offset = MFI -> getObjectOffset ( Info . getFrameIdx ( ) ) - getOffsetOfLocalArea ( ) ;

unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ;


assert ( Kind == k_MatrixRegister && <STR_LIT> ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue VL = getDefaultScalableVLOps ( VT , DL , DAG , Subtarget ) . second ; return DAG . getNode ( <STR_LIT> , DL , VT , VL ) ; } if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue VL = getDefaultScalableVLOps ( VT , DL , DAG , Subtarget ) . second ; return DAG . getNode ( <STR_LIT> , DL , VT , VL ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( SplatVal . getValueType ( ) == XLenVT && <STR_LIT> ) ; MVT InterVT = VT . changeVectorElementType ( <STR_LIT> ) ;

SplatVal = DAG . getNode ( <STR_LIT> , DL , XLenVT , SplatVal , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerVECREDUCE_SEQ_FADD ( SDValue ScalarOp , SelectionDAG & DAG ) const { SDLoc DL ( ScalarOp ) ; SDValue AccOp = ScalarOp . getOperand ( <NUM_LIT> ) ; SDValue VecOp = ScalarOp . getOperand ( <NUM_LIT> ) ; EVT SrcVT = VecOp . getValueType ( ) ; EVT ResVT = SrcVT . getVectorElementType ( ) ; EVT ContainerVT = SrcVT ; if ( SrcVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( DAG , SrcVT ) ; VecOp = convertToScalableVector ( DAG , ContainerVT , VecOp ) ; } SDValue Pg = getPredicateForVector ( DAG , DL , SrcVT ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; AccOp = DAG . getNode ( <STR_LIT> , DL , ContainerVT , DAG . getUNDEF ( ContainerVT ) , AccOp , Zero ) ; SDValue Rdx = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Pg , AccOp , VecOp ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , Rdx , Zero ) ;


<s> static bool resolveTargetShuffleInputs ( SDValue Op , SmallVectorImpl < SDValue > & Inputs , SmallVectorImpl < int > & Mask , SelectionDAG & DAG , unsigned Depth ) { unsigned NumElts = Op . getValueType ( ) . getVectorNumElements ( ) ;

APInt DemandedElts = APInt :: getAllOnesValue ( NumElts ) ;


<s> return getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 ;


<s> if ( InstTy == InstType :: Ambiguous && OpSize == <NUM_LIT> ) return true ; return false ;


<s> StringRef getPassName ( ) const override {


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> const <STR_LIT> * DimInfo = <STR_LIT> ( ImageDimIntr -> Dim ) ; int NumGradients = BaseOpcode -> Gradients ? DimInfo -> NumGradients : <NUM_LIT> ;

int NumCoords = BaseOpcode -> Coordinates ? DimInfo -> NumCoords : <NUM_LIT> ;


<s> BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; } else if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: Static ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; } else { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( Subtarget . isABI_N32 ( ) ) { const GlobalValue * FName = MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ;


<s> static void fixup_6 ( const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) {

unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( LHS . getValueType ( ) . isInteger ( ) ) {

const ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ;


<s> case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { bool HasAVX = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX ( ) ; bool HasAVX512 = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ; if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; }


<s> static tree m68hc11_handle_page0_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { tree decl = * node ; if ( TREE_STATIC ( decl ) || DECL_EXTERNAL ( decl ) ) { DECL_SECTION_NAME ( decl ) = build_string ( <NUM_LIT> , <STR_LIT> ) ; } else {

warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name ) ) ;


<s> return selectInterpP1F16 ( I ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return constrainCopyLikeIntrin ( I , <STR_LIT> ) ; case <STR_LIT> : return selectWritelane ( I ) ; case <STR_LIT> : return selectDivScale ( I ) ; case <STR_LIT> : return selectIntrinsicIcmp ( I ) ; case <STR_LIT> : return selectBallot ( I ) ; case <STR_LIT> : return selectRelocConstant ( I ) ; case <STR_LIT> : return selectGroupStaticSize ( I ) ; case <STR_LIT> : return selectReturnAddress ( I ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( IsPairwise || ! ST -> hasVOP3PInsts ( ) || OrigTy . getScalarSizeInBits ( ) != <NUM_LIT> ) return BaseT :: getArithmeticReductionCost ( Opcode , Ty , IsPairwise ) ;

std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : CalleeSavedFrameSize ( <NUM_LIT> ) , ReturnAddrIndex ( <NUM_LIT> ) {


<s> return static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ;


<s> if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( RPI . isPaired ( ) ) { MIB . addReg ( Reg2 , getDefRegState ( true ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx + <NUM_LIT> ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ) ; } MIB . addReg ( Reg1 , getDefRegState ( true ) ) . addReg ( <STR_LIT> ) . addImm ( RPI . Offset ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , RPI . FrameIdx ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ) ; } ; if ( ReverseCSRRestoreSeq ) for ( const RegPairInfo & RPI : reverse ( RegPairs ) ) EmitMI ( RPI ) ;

else for ( const RegPairInfo & RPI : RegPairs ) EmitMI ( RPI ) ;


<s> return __aarch64_vget_lane_any ( __a , __b ) ;


<s> rtx pat = gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_fmt_ee ( code , GET_MODE ( operands [ <NUM_LIT> ] ) , x , const0_rtx ) ) ; if ( mode == SImode || ( code == NE && TARGET_VIS3 ) ) { rtx clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( mode == SImode ? CCmode : CCXmode , SPARC_ICC_REG ) ) ; pat = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , pat , clobber ) ) ; } emit_insn ( pat ) ; return true ; } if ( TARGET_ARCH64 && mode == DImode && ! ( ( code == LTU || code == GTU ) && TARGET_VIS3 ) && gen_v9_scc ( operands [ <NUM_LIT> ] , code , x , y ) ) return true ;


<s> Token += getLexer ( ) . getTok ( ) . getString ( ) ; StringRef DimId = Token ; if ( DimId . startswith ( <STR_LIT> ) ) DimId = DimId . substr ( <NUM_LIT> ) ; const <STR_LIT> * DimInfo = <STR_LIT> ( DimId ) ; if ( ! DimInfo ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , DimInfo -> Encoding , S , <ISA_LIT>Operand :: ImmTyDim ) ) ;


<s> return false ; case TargetOpcode :: G_VAARG : return legalizeVaArg ( MI , MRI , MIRBuilder ) ;


<s> void ApplyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const {


<s> printIfSet ( MI , OpNo , O , <STR_LIT> ) ;


<s> static inline void aarch64_sub_sp ( rtx temp1 , rtx temp2 , poly_int64 delta , bool frame_related_p ) {


<s> bool CustomListScheduler :: DelayForLiveRegsBottomUp ( SUnit * SU , SmallVector < unsigned , <NUM_LIT> > & LRegs ) {


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , PRI ( g . getPRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , LiveMap ( g . getPRI ( ) ) , NoRegs ( g . getPRI ( ) ) {


<s> } if ( ! isIdentityValue ( OrigMI . getOpcode ( ) , OldOpndValue ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } CombOldVGPR = getRegSubRegPair ( * Src1 ) ;

if ( ! isOfRegClass ( CombOldVGPR , <STR_LIT> , * MRI ) ) {


<s> return true ; } if ( Opcode == <STR_LIT> ) { const GlobalValue * Global = MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; const uint32_t * RegMask = MI . getOperand ( <NUM_LIT> ) . getRegMask ( ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addGlobalAddress ( Global ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( Opcode == <STR_LIT> ) { const uint32_t * RegMask = MI . getOperand ( <NUM_LIT> ) . getRegMask ( ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( CCValid ) . addImm ( CCMask ) . addRegMask ( RegMask ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; }


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>BranchRelaxation ( ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) ) ; }

addPass ( create<ISA_LIT>Packetizer ( NoOpt ) ) ;


<s> <ISA_LIT>TargetELFStreamer :: <ISA_LIT>TargetELFStreamer ( ) {


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) {

return new <ISA_LIT>TargetELFStreamer ( S , STI ) ;


<s> static void m68k_coff_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) {


Value = ( top << <NUM_LIT> ) | ( middle << <NUM_LIT> ) | ( bottom << <NUM_LIT> ) ;


<s> if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>RemoveExtendOps ( <ISA_LIT>TargetMachine & TM ) {

return new <ISA_LIT>RemoveExtendArgs ( ) ;


<s> else { registered_function & rfn = add_function ( instance , name , m_overload_type , NULL_TREE , required_extensions , true , m_direct_overloads ) ; m_overload_names . put ( name , & rfn ) ; }


<s> if ( TheTriple . isOSWindows ( ) && TheTriple . getEnvironment ( ) != Triple :: ELF ) return createWinCOFFStreamer ( Ctx , MAB , * _Emitter , _OS , RelaxAll ) ;

return createELFStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll , NoExecStack ) ;


current_frame_info . initialized = reload_completed ;


<s> else temp = exact_log2 ( opint [ <NUM_LIT> ] & - opint [ <NUM_LIT> ] ) ; return build_int_cst ( long_integer_type_node , temp ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>AnnotateUniformValues ( ) {

return new <ISA_LIT>AnnotateUniformValues ( ) ;


<s> static uint32_t getConstantPermuteMask ( uint32_t C ) { uint32_t ZeroByteMask = <NUM_LIT> ; if ( ! ( C & <NUM_LIT> ) ) ZeroByteMask |= <NUM_LIT> ; if ( ! ( C & <NUM_LIT> ) ) ZeroByteMask |= <NUM_LIT> ; if ( ! ( C & <NUM_LIT> ) ) ZeroByteMask |= <NUM_LIT> ; if ( ! ( C & <NUM_LIT> ) ) ZeroByteMask |= <NUM_LIT> ; uint32_t NonZeroByteMask = ~ ZeroByteMask ; if ( ( NonZeroByteMask & C ) != NonZeroByteMask ) return <NUM_LIT> ; return C ;


<s> raw_svector_ostream ( Str ) << DEPOTNAME << getFunctionNumber ( ) ;

return OutContext . getOrCreateSymbol ( Str ) ;


<s> assert ( ! Out . Flags . isByVal ( ) && <STR_LIT> ) ; assert ( ! Out . Flags . isNest ( ) && <STR_LIT> ) ; assert ( Out . IsFixed && <STR_LIT> ) ; if ( Out . Flags . isInAlloca ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInConsecutiveRegs ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInConsecutiveRegsLast ( ) ) fail ( DL , DAG , <STR_LIT> ) ; }


<s> assert ( Kind == k_Token && <STR_LIT> ) ; return Tok . IsSuffix ;


<s> auto IsHazardDefFn = [ TII ] ( const MachineInstr & MI ) { return TII -> isVALU ( MI ) ;


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , uint8_t OSABI , const MCSubtargetInfo & STI ) : <ISA_LIT>AsmBackend ( T , STI ) , OSABI ( OSABI ) {


<s> assert ( isa < ConstantDataSequential > ( Operand ) && <STR_LIT> ) ; assert ( cast < ConstantDataSequential > ( Operand ) -> isCString ( ) && <STR_LIT> ) ; StringRef ReflectArg = cast < ConstantDataSequential > ( Operand ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( ReflectArg == <STR_LIT> ) { if ( auto * Flag = mdconst :: extract_or_null < ConstantInt > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) ReflectVal = Flag -> getSExtValue ( ) ; } Call -> replaceAllUsesWith ( ConstantInt :: get ( Call -> getType ( ) , ReflectVal ) ) ; ToRemove . push_back ( Call ) ; }

for ( Instruction * I : ToRemove ) I -> eraseFromParent ( ) ;


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : FramePointerSaveIndex ( <NUM_LIT> ) , ReturnAddrSaveIndex ( <NUM_LIT> ) , BasePointerSaveIndex ( <NUM_LIT> ) , PICBasePointerSaveIndex ( <NUM_LIT> ) , HasSpills ( false ) , HasNonRISpills ( false ) , SpillsCR ( false ) , SpillsVRSAVE ( false ) , LRStoreRequired ( false ) , MinReservedArea ( <NUM_LIT> ) , TailCallSPDelta ( <NUM_LIT> ) , HasFastCall ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , VarArgsStackOffset ( <NUM_LIT> ) , VarArgsNumGPR ( <NUM_LIT> ) , VarArgsNumFPR ( <NUM_LIT> ) , CRSpillFrameIndex ( <NUM_LIT> ) , MF ( MF ) , UsesPICBase ( <NUM_LIT> ) {


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;

PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ;


<s> else State . PreAnalyzeFormalArgument ( Info . Ty , Flags ) ; return CallLowering :: IncomingValueAssigner :: assignArg ( ValNo , OrigVT , ValVT , LocVT , LocInfo , Info , Flags , State ) ;


<s> if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return <STR_LIT> ;


<s> SmallSet < const MachineBasicBlock * , <NUM_LIT> > Visited ; MachineBasicBlock * B = & MBB ; do { if ( ! Visited . insert ( B ) . second ) return MBB . end ( ) ; auto E = B -> end ( ) ; for ( ; It != E ; ++ It ) { if ( TII -> mayReadEXEC ( * MRI , * It ) ) break ; } if ( It != E ) return It ; if ( B -> succ_size ( ) != <NUM_LIT> ) return MBB . end ( ) ; MachineBasicBlock * Succ = * B -> succ_begin ( ) ; It = Succ -> begin ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerAND ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) . isVector ( ) ) return LowerVectorAND ( Op , DAG ) ;

return tryLowerTo<ISA_LIT>Cmp ( Op , DAG ) ;


<s> if ( FuncInfo -> hasSpilledVGPRs ( ) ) return false ;

for ( int I = FrameInfo -> getObjectIndexBegin ( ) , E = FrameInfo -> getObjectIndexEnd ( ) ; I != E ; ++ I ) {


<s> unsigned Opc = MI . getOpcode ( ) ; unsigned PredOpc = HII -> getCondOpcode ( Opc , ! Cond ) ; MachineInstrBuilder MB = BuildMI ( B , Where , DL , HII -> get ( PredOpc ) ) ; unsigned Ox = <NUM_LIT> , NP = MI . getNumOperands ( ) ; while ( Ox < NP ) { MachineOperand & MO = MI . getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) break ; Ox ++ ; } MB . addReg ( DefOp . getReg ( ) , getRegState ( DefOp ) , DefOp . getSubReg ( ) ) ;

MB . addReg ( PredOp . getReg ( ) , PredOp . isUndef ( ) ? RegState :: Undef : <NUM_LIT> , PredOp . getSubReg ( ) ) ;


<s> const MachineOperand * BaseOp = getBaseAndOffset ( LdSt , Offset , AccessSize ) ; if ( ! BaseOp || ! BaseOp -> isReg ( ) ) return false ; BaseOps . push_back ( BaseOp ) ;


<s> static void rs6000_function_arg_advance ( cumulative_args_t cum , machine_mode mode , const_tree type , bool named ) {

rs6000_function_arg_advance_1 ( get_cumulative_args ( cum ) , mode , type , named , <NUM_LIT> ) ;


<s> void c4x_emit_libcall3 ( rtx libcall , enum rtx_code code , enum machine_mode mode , rtx * operands ) {

c4x_emit_libcall ( libcall , code , mode , mode , <NUM_LIT> , operands ) ;


<s> Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = dyn_cast < ConstantInt > ( CI . getOperand ( <NUM_LIT> ) ) ; if ( ! Vol || ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getOperand ( <NUM_LIT> ) -> getType ( ) -> getPointerElementType ( ) ) ; Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align . reset ( ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ; const ConstantInt * Vol = cast < ConstantInt > ( CI . getOperand ( <NUM_LIT> ) ) ; if ( ! Vol -> isZero ( ) ) Info . flags |= MachineMemOperand :: MOVolatile ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Info . ptrVal = MFI -> getGWSPSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) ) ; Info . memVT = <STR_LIT> ; Info . size = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOStore ; if ( IntrID == <STR_LIT> ) Info . flags = MachineMemOperand :: MOLoad ;


<s> DOUT << <STR_LIT> << idx ; idx = ( idx - GOToffset ) * <NUM_LIT> ; DOUT << <STR_LIT> << idx << <STR_LIT> ; break ; case <STR_LIT> : idx = ( unsigned char * ) MR -> getResultPointer ( ) - & GOTBase [ GOToffset * <NUM_LIT> ] ; idx = getLower16 ( idx ) ; DOUT << <STR_LIT> << idx << <STR_LIT> ; DOUT << <STR_LIT> << ( void * ) MR -> getResultPointer ( ) << <STR_LIT> << ( void * ) & GOTBase [ GOToffset * <NUM_LIT> ] << <STR_LIT> ; break ; case <STR_LIT> : idx = ( unsigned char * ) MR -> getResultPointer ( ) - & GOTBase [ GOToffset * <NUM_LIT> ] ; idx = getUpper16 ( idx ) ; DOUT << <STR_LIT> << idx << <STR_LIT> ; DOUT << <STR_LIT> << ( void * ) MR -> getResultPointer ( ) << <STR_LIT> << ( void * ) & GOTBase [ GOToffset * <NUM_LIT> ] << <STR_LIT> ; break ; case <STR_LIT> :


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override {


<s> case <STR_LIT> : case <STR_LIT> : return Value ; case <STR_LIT> : case <STR_LIT> : return ( Value & <NUM_LIT> ) << <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : return ( ( Value >> <NUM_LIT> ) + ( ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) & <NUM_LIT> ;


<s> SDValue Op = V . getOperand ( M / Scale ) ; if ( Op . isUndef ( ) ) Mask [ i ] = SM_SentinelUndef ; else if ( <STR_LIT> ( Op ) ) Mask [ i ] = SM_SentinelZero ; continue ; } if ( ( V . getNumOperands ( ) % Size ) == <NUM_LIT> ) { int Scale = V -> getNumOperands ( ) / Size ; bool AllUndef = true ; bool AllZero = true ; for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) { SDValue Op = V . getOperand ( ( M * Scale ) + j ) ; AllUndef &= Op . isUndef ( ) ; AllZero &= <STR_LIT> ( Op ) ; } if ( AllUndef ) Mask [ i ] = SM_SentinelUndef ; else if ( AllZero ) Mask [ i ] = SM_SentinelZero ; continue ; } } assert ( VT . getVectorNumElements ( ) == Mask . size ( ) && <STR_LIT> ) ; return true ;