<s> int64_t Res ; if ( SD . getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } if ( ! Symbol -> getVariableValue ( ) -> EvaluateAsRelocatable ( Target , & Layout , & Fixup ) ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> ) ; return RecordRelocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue ) ; } if ( Symbol -> isInSection ( ) ) { if ( Section . hasAttribute ( MachO :: S_ATTR_DEBUG ) ) Base = nullptr ; } if ( Base ) { Index = Base -> getIndex ( ) ; IsExtern = <NUM_LIT> ; if ( Base != & SD ) Value += Layout . getSymbolOffset ( & SD ) - Layout . getSymbolOffset ( Base ) ; } else if ( Symbol -> isInSection ( ) ) { if ( ! Section . hasAttribute ( MachO :: S_ATTR_DEBUG ) && Log2Size != <NUM_LIT> ) Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> ) ; const MCSectionData & SymSD = Asm . getSectionData ( SD . getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ; IsExtern = <NUM_LIT> ; Value += Writer -> getSymbolAddress ( & SD , Layout ) ; if ( IsPCRel ) Value -= Writer -> getFragmentAddress ( Fragment , Layout ) + Fixup . getOffset ( ) + ( <NUM_LIT> << Log2Size ) ; } else { if ( SD . getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD . getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , <STR_LIT> + Symbol -> getName ( ) + <STR_LIT> ) ; } } if ( ( Type == MachO :: ARM64_RELOC_BRANCH26 || Type == MachO :: ARM64_RELOC_PAGE21 || Type == MachO :: ARM64_RELOC_PAGEOFF12 ) && Value ) { assert ( ( Value & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachO :: any_relocation_info MRE ; MRE . r_word0 = FixupOffset ; MRE . r_word1 = ( ( Index << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsExtern << <NUM_LIT> ) | ( Type << <NUM_LIT> ) ) ; Writer -> addRelocation ( Fragment -> getParent ( ) , MRE ) ; Type = MachO :: ARM64_RELOC_ADDEND ; Index = Value ; IsPCRel = <NUM_LIT> ; Log2Size = <NUM_LIT> ; IsExtern = <NUM_LIT> ; Value = <NUM_LIT> ; } FixedValue = Value ; MachO :: any_relocation_info MRE ;


<s> FunctionPass * llvm :: create<ISA_LIT>PreLegalizerPass ( ) {


<s> return <ISA_LIT>MaskedVMem && ST . isTypeForHVX ( DataType ) ;


<s> uint64_t Bytes = CSize -> getZExtValue ( ) ; if ( Bytes == <NUM_LIT> ) return SDValue ( ) ; if ( auto * CByte = dyn_cast < ConstantSDNode > ( Byte ) ) { uint64_t ByteVal = CByte -> getZExtValue ( ) ; if ( ByteVal == <NUM_LIT> || ByteVal == <NUM_LIT> ? Bytes <= <NUM_LIT> && countPopulation ( Bytes ) <= <NUM_LIT> : Bytes <= <NUM_LIT> ) { unsigned Size1 = Bytes == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> << findLastSet ( Bytes ) ; unsigned Size2 = Bytes - Size1 ; SDValue Chain1 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size1 , Align , DstPtrInfo ) ; if ( Size2 == <NUM_LIT> ) return Chain1 ; Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , DL , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( Align , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; }


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext & ctx ) : MCII ( mcii ) {


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; Register OldDstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = Inst . getOpcode ( ) ; assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; unsigned NewOpc = Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; Inst . RemoveOperand ( <NUM_LIT> ) ; Inst . setDesc ( get ( NewOpc ) ) ;

Inst . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( mode ) ) ; } else if ( imod && ! M ) { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( imod ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( iflags ) ) ; if ( mode ) S = MCDisassembler :: SoftFail ; } else if ( ! imod && M ) { Inst . setOpcode ( <STR_LIT> ) ;


<s> MFI -> LDSSize += Size ; } else { Offset = MFI -> LocalMemoryObjects [ GV ] ; } return DAG . getConstant ( Offset , getPointerTy ( G -> getAddressSpace ( ) ) ) ; } case <STR_LIT> : { MachineFrameInfo * FrameInfo = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; Type * EltType = GV -> getType ( ) -> getElementType ( ) ; unsigned Size = TD -> getTypeAllocSize ( EltType ) ; unsigned Alignment = TD -> getPrefTypeAlignment ( EltType ) ; const GlobalVariable * Var = dyn_cast < GlobalVariable > ( GV ) ; const Constant * Init = Var -> getInitializer ( ) ; int FI = FrameInfo -> CreateStackObject ( Size , Alignment , false ) ; SDValue InitPtr = DAG . getFrameIndex ( FI , getPointerTy ( <STR_LIT> ) ) ; SmallVector < SDNode * , <NUM_LIT> > WorkList ; for ( SDNode :: use_iterator I = DAG . getEntryNode ( ) -> use_begin ( ) , E = DAG . getEntryNode ( ) -> use_end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) continue ; WorkList . push_back ( * I ) ; } SDValue Chain = LowerConstantInitializer ( Init , GV , InitPtr , DAG . getEntryNode ( ) , DAG ) ; for ( SmallVector < SDNode * , <NUM_LIT> > :: iterator I = WorkList . begin ( ) , E = WorkList . end ( ) ; I != E ; ++ I ) { SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; for ( unsigned i = <NUM_LIT> ; i < ( * I ) -> getNumOperands ( ) ; ++ i ) { Ops . push_back ( ( * I ) -> getOperand ( i ) ) ; } DAG . UpdateNodeOperands ( * I , Ops . data ( ) , Ops . size ( ) ) ;


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; default : return <NUM_LIT> ;


<s> EVT MemVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EntrySize * <NUM_LIT> ) ; Addr = DAG . getExtLoad ( <STR_LIT> , DL , PTy , Chain , Addr , MachinePointerInfo :: getJumpTable ( ) , MemVT , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; if ( ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) || isN64 ( ) ) { Addr = DAG . getNode ( <STR_LIT> , DL , PTy , Addr , getPICJumpTableRelocBase ( Table , DAG ) ) ;


<s> const MCOperand & MO = MI -> getOperand ( opNum ) ; if ( MO . getImm ( ) ) { O << <STR_LIT> ; }


<s> for ( unsigned int pi = <NUM_LIT> ; group . preds [ pi ] != NUM_PREDS ; ++ pi ) if ( group . types [ <NUM_LIT> ] [ <NUM_LIT> ] == NUM_TYPE_SUFFIXES ) { gcc_assert ( mode32 != MODE_none && mode64 != MODE_none ) ; build_one ( b , signature , group , mode32 , <NUM_LIT> , pi , force_direct_overloads ) ; build_one ( b , signature , group , mode64 , <NUM_LIT> , pi , force_direct_overloads ) ; } else for ( unsigned int ti = <NUM_LIT> ; group . types [ ti ] [ <NUM_LIT> ] != NUM_TYPE_SUFFIXES ; ++ ti ) {

unsigned int bits = type_suffixes [ group . types [ ti ] [ <NUM_LIT> ] ] . element_bits ;


<s> RepeatedMask . assign ( LaneSize , - <NUM_LIT> ) ; int Size = Mask . size ( ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { assert ( Mask [ i ] == SM_SentinelUndef || Mask [ i ] >= <NUM_LIT> ) ; if ( Mask [ i ] < <NUM_LIT> ) continue ; if ( ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) return false ; int LocalM = Mask [ i ] < Size ? Mask [ i ] % LaneSize : Mask [ i ] % LaneSize + LaneSize ; if ( RepeatedMask [ i % LaneSize ] < <NUM_LIT> ) RepeatedMask [ i % LaneSize ] = LocalM ; else if ( RepeatedMask [ i % LaneSize ] != LocalM ) return false ; } return true ;


<s> rtx reg = crtl -> return_rtx ; if ( reg && ix86_check_avx256_register ( reg ) ) return AVX_U128_DIRTY ; return AVX_U128_CLEAN ;


<s> CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result ; if ( GV ) { int64_t GlobalOffset = <NUM_LIT> ; if ( OpFlags == <STR_LIT> && <STR_LIT> ( Offset , M ) ) { std :: swap ( GlobalOffset , Offset ) ; } Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , GlobalOffset , OpFlags ) ; } else { Result = DAG . getTargetExternalSymbol ( ExternalSym , PtrVT , OpFlags ) ; } if ( ForCall && ! NeedsLoad && ! HasPICReg && Offset == <NUM_LIT> ) return Result ; Result = DAG . getNode ( getGlobalWrapperKind ( GV , OpFlags ) , dl , PtrVT , Result ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; if ( ( LHS -> getKind ( ) != MCExpr :: SymbolRef ) || ! CE ) return std :: make_pair ( ( const MCSymbolRefExpr * ) <NUM_LIT> , ( int64_t ) <NUM_LIT> ) ; return std :: make_pair ( cast < MCSymbolRefExpr > ( LHS ) , CE -> getValue ( ) ) ;


<s> insn = emit_move_insn ( reg , pic_ref ) ; REG_NOTES ( insn ) = gen_rtx_EXPR_LIST ( REG_EQUAL , orig , REG_NOTES ( insn ) ) ; return reg ; } else if ( GET_CODE ( orig ) == CONST ) { rtx base , offset ; if ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS && XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) == pic_offset_table_rtx ) return orig ; if ( reg == <NUM_LIT> ) { gcc_assert ( ! reload_in_progress && ! reload_completed ) ; reg = gen_reg_rtx ( Pmode ) ; } gcc_assert ( GET_CODE ( XEXP ( orig , <NUM_LIT> ) ) == PLUS ) ; base = legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg ) ; offset = legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , base == reg ? <NUM_LIT> : reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( SMALL_INT ( offset ) ) return plus_constant ( base , INTVAL ( offset ) ) ; else if ( ! reload_in_progress && ! reload_completed ) offset = force_reg ( Pmode , offset ) ;


<s> uint8x16x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3rv16qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint8x16_t ) __builtin_aarch64_get_qregciv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint8x16_t ) __builtin_aarch64_get_qregciv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint8x16_t ) __builtin_aarch64_get_qregciv16qi ( __o , <NUM_LIT> ) ; return ret ;


<s> OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) ; <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; for ( auto & I : TOC ) { MCSectionXCOFF * TCEntry ; if ( I . first . second == MCSymbolRefExpr :: VariantKind :: VK_<ISA_LIT>_AIX_TLSGDM ) { SmallString < <NUM_LIT> > Name ; StringRef Prefix = <STR_LIT> ; Name += Prefix ; Name += I . first . first -> getName ( ) ; MCSymbol * S = OutContext . getOrCreateSymbol ( Name ) ; TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( S , TM ) ) ; } else { TCEntry = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getSectionForTOCEntry ( I . first . first , TM ) ) ; } OutStreamer -> SwitchSection ( TCEntry ) ; OutStreamer -> emitLabel ( I . second ) ; if ( TS != nullptr ) TS -> emitTCEntry ( * I . first . first , I . first . second ) ;


<s> } ; if ( parseRegister ( YamlMFI . ScratchRSrcReg , MFI -> ScratchRSrcReg ) || parseRegister ( YamlMFI . ScratchWaveOffsetReg , MFI -> ScratchWaveOffsetReg ) || parseRegister ( YamlMFI . FrameOffsetReg , MFI -> FrameOffsetReg ) || parseRegister ( YamlMFI . StackPtrOffsetReg , MFI -> StackPtrOffsetReg ) ) return true ; if ( MFI -> ScratchRSrcReg != <STR_LIT> && ! <STR_LIT> . contains ( MFI -> ScratchRSrcReg ) ) { return diagnoseRegisterClass ( YamlMFI . ScratchRSrcReg ) ; } if ( MFI -> ScratchWaveOffsetReg != <STR_LIT> && ! <STR_LIT> . contains ( MFI -> ScratchWaveOffsetReg ) ) { return diagnoseRegisterClass ( YamlMFI . ScratchWaveOffsetReg ) ; } if ( MFI -> FrameOffsetReg != <STR_LIT> && ! <STR_LIT> . contains ( MFI -> FrameOffsetReg ) ) {

return diagnoseRegisterClass ( YamlMFI . FrameOffsetReg ) ;


<s> case G_SDIV : case G_UDIV : case G_SREM : case G_UREM : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; break ; case G_FADD : case G_FSUB : case G_FMUL : case G_FDIV : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; OperandsMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ; break ; } case G_FCONSTANT : { unsigned Size = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; const RegisterBankInfo :: ValueMapping * FPRValueMapping = Size == <NUM_LIT> ? & <STR_LIT> [ <STR_LIT> ] : & <STR_LIT> [ <STR_LIT> ] ;

OperandsMapping = getOperandsMapping ( { FPRValueMapping , nullptr } ) ;


<s> stub_iterator stub_begin ( ) const {


<s> int VAddr0Idx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: vaddr0 ) ; unsigned NewAddrDwords = Info -> VAddrDwords ; const TargetRegisterClass * RC ; if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else if ( Info -> VAddrDwords == <NUM_LIT> ) { RC = & <STR_LIT> ; } else { RC = & <STR_LIT> ; NewAddrDwords = <NUM_LIT> ; } unsigned VgprBase = <NUM_LIT> ; bool IsUndef = true ; bool IsKill = NewAddrDwords == Info -> VAddrDwords ; for ( unsigned i = <NUM_LIT> ; i < Info -> VAddrDwords ; ++ i ) { const MachineOperand & Op = MI . getOperand ( VAddr0Idx + i ) ; unsigned Vgpr = TRI -> getHWRegIndex ( Op . getReg ( ) ) ; if ( i == <NUM_LIT> ) { VgprBase = Vgpr ; } else if ( VgprBase + i != Vgpr ) return ;

if ( ! Op . isUndef ( ) ) IsUndef = false ;


<s> unsigned int call_properties ( const function_instance & ) const override {


<s> } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>ParamManager & PM = MFI -> getParamManager ( ) ; SDValue Flag ; const <ISA_LIT>Subtarget & ST = getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . useParamSpaceForDeviceArgs ( ) ) { assert ( Outs . size ( ) < <NUM_LIT> && <STR_LIT> ) ; if ( Outs . size ( ) == <NUM_LIT> ) { unsigned ParamSize = OutVals [ <NUM_LIT> ] . getValueType ( ) . getSizeInBits ( ) ; unsigned Param = PM . addReturnParam ( ParamSize ) ; const std :: string & ParamName = PM . getParamName ( Param ) ; SDValue ParamValue = DAG . getTargetExternalSymbol ( ParamName . c_str ( ) , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , ParamValue , OutVals [ <NUM_LIT> ] ) ; } } else { for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { EVT RegVT = Outs [ i ] . VT ; const TargetRegisterClass * TRC ; unsigned RegType ;


<s> static machine_mode arc_preferred_simd_mode ( scalar_mode mode ) {


<s> if ( Convert ) { SDValue SR = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , <STR_LIT> , Flag ) ; if ( Shift ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; if ( Invert ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; return SR ; } else { SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;

SDValue Ops [ ] = { One , Zero , TargetCC , Flag } ;


<s> if ( Features . test ( FeatureISAVersion8_0_1 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion8_0_2 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion8_0_3 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion8_0_4 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ;

if ( Features . test ( FeatureISAVersion8_1_0 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { return new <ISA_LIT>InstPrinter ( MAI , MRI , SyntaxVariant ) ;


<s> bool <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( ! get<ISA_LIT>Subtarget ( ) . has<ISA_LIT>64 ( ) ) PM . add ( create<ISA_LIT>EmitGPRestorePass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> if ( DA -> isUniform ( & I ) ) setUniformMetadata ( I . getParent ( ) -> getTerminator ( ) ) ;


<s> bool <ISA_LIT>LDBackend :: initTargetStubs ( ) { if ( getStubFactory ( ) != NULL ) { getStubFactory ( ) -> addPrototype ( new <ISA_LIT>AbsoluteStub ( config ( ) . isCodeIndep ( ) ) ) ; return true ;


<s> if ( ! CI -> isIntegerCast ( ) ) return false ; const DataLayout & DL = getDataLayout ( ) ; unsigned SBW = DL . getTypeSizeInBits ( CI -> getSrcTy ( ) ) ; unsigned DBW = DL . getTypeSizeInBits ( CI -> getDestTy ( ) ) ; if ( DBW != <NUM_LIT> || SBW >= DBW ) return false ; const LoadInst * LI = dyn_cast < const LoadInst > ( CI -> getOperand ( <NUM_LIT> ) ) ;


<s> const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned Reg = MO1 . getReg ( ) ; printRegName ( O , Reg ) ; assert ( MO2 . isImm ( ) && <STR_LIT> ) ;

printRegImmShift ( O , <STR_LIT> ( MO2 . getImm ( ) ) , <STR_LIT> ( MO2 . getImm ( ) ) , UseMarkup ) ;


<s> if ( GET_CODE ( seq ) == SEQUENCE ) { int i = XVECLEN ( seq , <NUM_LIT> ) ; while ( -- i >= <NUM_LIT> ) RTX_FRAME_RELATED_P ( XVECEXP ( seq , <NUM_LIT> , i ) ) = <NUM_LIT> ; return emit_insn ( seq ) ; }


<s> DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known2 , Depth + <NUM_LIT> ) ; Known . Zero &= Known2 . Zero ; Known . One &= Known2 . One ;


<s> int MemRefBegin = <STR_LIT> ( Desc . TSFlags , MemOp -> getOpcode ( ) ) ; if ( MemRefBegin < <NUM_LIT> ) return false ; MemRefBegin += <STR_LIT> ( Desc ) ; BaseReg = MemOp -> getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) ; if ( MemOp -> getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( MemOp -> getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; const MachineOperand & DispMO = MemOp -> getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! DispMO . isImm ( ) ) return false ;


<s> if ( ( SrcMBB . getNumber ( ) >= TrueMBB -> getNumber ( ) ) || mustRetainExeczBranch ( * FalseMBB , * TrueMBB ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MI . eraseFromParent ( ) ; SrcMBB . removeSuccessor ( TrueMBB ) ;


<s> virtual StringRef getPassName ( ) const override {


<s> SDValue WideVec = DAG . getNode ( <STR_LIT> , DL , WideVecVT , StVal ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) ShuffleVec [ i ] = TLI . isBigEndian ( ) ? ( i + <NUM_LIT> ) * SizeRatio - <NUM_LIT> : i * SizeRatio ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , DL , WideVec , DAG . getUNDEF ( WideVec . getValueType ( ) ) , ShuffleVec . data ( ) ) ; MVT StoreType = <STR_LIT> ; for ( unsigned tp = <STR_LIT> ; tp < <STR_LIT> ; ++ tp ) { MVT Tp = ( <STR_LIT> ) tp ; if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) <= NumElems * ToEltSz ) StoreType = Tp ; } if ( ! TLI . isTypeLegal ( StoreType ) ) return SDValue ( ) ; EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType , VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ; assert ( StoreVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue ShuffWide = DAG . getNode ( <STR_LIT> , DL , StoreVecVT , Shuff ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; SDValue Increment = DAG . getConstant ( StoreType . getSizeInBits ( ) / <NUM_LIT> , TLI . getPointerTy ( ) ) ; SDValue BasePtr = St -> getBasePtr ( ) ; unsigned E = ( ToEltSz * NumElems ) / StoreType . getSizeInBits ( ) ; for ( unsigned I = <NUM_LIT> ; I < E ; I ++ ) { SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , StoreType , ShuffWide , DAG . getIntPtrConstant ( I ) ) ; SDValue Ch = DAG . getStore ( St -> getChain ( ) , DL , SubVec , BasePtr , St -> getPointerInfo ( ) , St -> isVolatile ( ) , St -> isNonTemporal ( ) , St -> getAlignment ( ) ) ;

BasePtr = DAG . getNode ( <STR_LIT> , DL , BasePtr . getValueType ( ) , BasePtr , Increment ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( mergedOpcode ( MI . getOpcode ( ) , false ) == <NUM_LIT> ) return false ;

const MachineMemOperand * MemOperand = * MI . memoperands_begin ( ) ;


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . getAttributes ( ) . hasFnAttr ( Attribute :: Naked ) ) { return Chain ; } const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

unsigned RetOpc = AFI -> isInterruptOrSignalHandler ( ) ? <STR_LIT> : <STR_LIT> ;


<s> case CCValAssign :: BCvt : if ( VA . getLocVT ( ) . isInteger ( ) && VA . getValVT ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ;

else if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ;


<s> if ( gmask ) for ( i = GMASK_LEN ; i >= <NUM_LIT> ; i -- ) { machine_mode save_mode = SImode ;

if ( TARGET_LL64 && ( ( i - <NUM_LIT> ) % <NUM_LIT> == <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ) ) {


<s> bool isFMAFasterThanFMulAndFAdd ( EVT ) const override {


<s> Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue LoVal = Addr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( LoVal . getOperand ( <NUM_LIT> ) ) || isa < GlobalAddressSDNode > ( LoVal . getOperand ( <NUM_LIT> ) ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = LoVal . getOperand ( <NUM_LIT> ) ;


<s> unsigned Reg , Imm12 ; bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; if ( ! MO . isReg ( ) || ( MO . getReg ( ) == <STR_LIT> && MO2 . isExpr ( ) ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm12 = <NUM_LIT> ;


<s> A = A . addAttribute ( C , AttributeSet :: FunctionIndex , <STR_LIT> ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: NoInline ) ; Value * F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T , nullptr ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & I ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( & I ) ) { FunctionType * FT = CI -> getFunctionType ( ) ; Function * F_ = CI -> getCalledFunction ( ) ; if ( needsFPReturnHelper ( * FT ) && ! ( F_ && isIntrinsicInline ( F_ ) ) ) { Modified = true ; F . addFnAttr ( <STR_LIT> ) ; } if ( F_ && ! isIntrinsicInline ( F_ ) ) { if ( needsFPReturnHelper ( * F_ ) ) { Modified = true ; F . addFnAttr ( <STR_LIT> ) ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( needsFPHelperFromSig ( * F_ ) ) { assureFPCallStub ( * F_ , M , TM ) ; Modified = true ; } } } }


<s> LDSAlignShift = <NUM_LIT> ; } unsigned LDSBlocks = RoundUpToAlignment ( MFI -> LDSSize , <NUM_LIT> << LDSAlignShift ) >> LDSAlignShift ; unsigned ScratchAlignShift = <NUM_LIT> ; unsigned ScratchBlocks = RoundUpToAlignment ( KernelInfo . ScratchSize * STM . getWavefrontSize ( ) , <NUM_LIT> << ScratchAlignShift ) >> ScratchAlignShift ; if ( MFI -> getShaderType ( ) == ShaderType :: COMPUTE ) { OutStreamer . EmitIntValue ( R_00B848_COMPUTE_PGM_RSRC1 , <NUM_LIT> ) ;

const uint32_t ComputePGMRSrc1 = S_00B848_VGPRS ( KernelInfo . NumVGPR / <NUM_LIT> ) | S_00B848_SGPRS ( KernelInfo . NumSGPR / <NUM_LIT> ) | S_00B848_PRIORITY ( KernelInfo . Priority ) | S_00B848_FLOAT_MODE ( KernelInfo . FloatMode ) | S_00B848_PRIV ( KernelInfo . Priv ) | S_00B848_DX10_CLAMP ( KernelInfo . DX10Clamp ) | S_00B848_IEEE_MODE ( KernelInfo . DebugMode ) | S_00B848_IEEE_MODE ( KernelInfo . IEEEMode ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: EndOfStatement ) ) { if ( Tok . isNot ( AsmToken :: Identifier ) && Tok . isNot ( AsmToken :: String ) ) { Error ( L , <STR_LIT> ) ; return false ; }

MCSymbol * Func = getParser ( ) . getContext ( ) . GetOrCreateSymbol ( Tok . getIdentifier ( ) ) ;


<s> drop_front ( mangledName , N - <NUM_LIT> ) ; return true ; }


<s> unsigned <ISA_LIT>CodeEmitter :: getJumpOffset16OpValue ( const MachineInstr & MI , unsigned OpNo ) const {


<s> if ( Ty . second ) Ty . second -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ;


<s> while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= selectMI ( MBB , MBBI , NMBBI ) ; MBBI = NMBBI ; }


<s> if ( s390_function_arg_size ( mode , type ) > <NUM_LIT> ) return false ; if ( TARGET_SOFT_FLOAT ) return false ; if ( ! type ) return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode ; if ( ! s390_single_field_struct_p ( REAL_TYPE , type , false ) ) return false ;


<s> const SDValue One = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; SDVTList ScaleVT = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue DenominatorScaled = DAG . getNode ( <STR_LIT> , SL , ScaleVT , RHS , RHS , LHS ) ; SDValue NumeratorScaled = DAG . getNode ( <STR_LIT> , SL , ScaleVT , LHS , RHS , LHS ) ; SDValue ApproxRcp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenominatorScaled ) ; SDValue NegDivScale0 = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , DenominatorScaled ) ; const unsigned Denorm32Reg = <STR_LIT> :: ID_MODE | ( <NUM_LIT> << <STR_LIT> :: OFFSET_SHIFT_ ) | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ; const SDValue BitField = DAG . getTargetConstant ( Denorm32Reg , SL , <STR_LIT> ) ; if ( ! Subtarget -> hasFP32Denormals ( ) ) { SDVTList BindParamVTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue EnableDenorm ; if ( Subtarget -> hasDenormModeInst ( ) ) { const SDValue EnableDenormValue = getSPDenormModeValue ( FP_DENORM_FLUSH_NONE , DAG , SL , Subtarget ) ; EnableDenorm = DAG . getNode ( <STR_LIT> , SL , BindParamVTs , DAG . getEntryNode ( ) , EnableDenormValue ) ; } else { const SDValue EnableDenormValue = DAG . getConstant ( FP_DENORM_FLUSH_NONE , SL , <STR_LIT> ) ; EnableDenorm = DAG . getNode ( <STR_LIT> , SL , BindParamVTs , DAG . getEntryNode ( ) , EnableDenormValue , BitField ) ; } SDValue Ops [ <NUM_LIT> ] = {

NegDivScale0 , EnableDenorm . getValue ( <NUM_LIT> ) , EnableDenorm . getValue ( <NUM_LIT> ) } ;


<s> const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOT , getContext ( ) ) ; MCSymbol * PCSym = getContext ( ) . CreateTempSymbol ( ) ; Streamer . EmitLabel ( PCSym ) ; const MCExpr * PC = MCSymbolRefExpr :: Create ( PCSym , getContext ( ) ) ;

return MCBinaryExpr :: CreateSub ( Res , PC , getContext ( ) ) ;


<s> static void emitSPUpdate ( bool is<ISA_LIT> , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , DebugLoc dl , const <ISA_LIT>BaseInstrInfo & TII , int NumBytes , unsigned MIFlags = MachineInstr :: NoFlags , <STR_LIT> Pred = <STR_LIT> , unsigned PredReg = <NUM_LIT> ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT> , NumBytes , Pred , PredReg , TII , MIFlags ) ;

else emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT> , NumBytes , Pred , PredReg , TII , MIFlags ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; const MCRegisterInfo & MCRI = * MF . getMMI ( ) . getContext ( ) . getRegisterInfo ( ) ; int DwarfSGPR = MCRI . getDwarfRegNum ( SGPR , false ) ; SmallString < <NUM_LIT> > CFIInst ; raw_svector_ostream OSCFIInst ( CFIInst ) ; SmallString < <NUM_LIT> > Block ; raw_svector_ostream OSBlock ( Block ) ; OSCFIInst << uint8_t ( dwarf :: DW_CFA_expression ) ; encodeULEB128 ( DwarfSGPR , OSCFIInst ) ; for ( <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill : VGPRSpills ) { encodeDwarfRegisterLocation ( MCRI . getDwarfRegNum ( Spill . VGPR , false ) , OSBlock ) ; OSBlock << uint8_t ( dwarf :: DW_OP_bit_piece ) ; const unsigned SGPRBitSize = <NUM_LIT> ; encodeULEB128 ( SGPRBitSize , OSBlock ) ; encodeULEB128 ( SGPRBitSize * Spill . Lane , OSBlock ) ; } encodeULEB128 ( Block . size ( ) , OSCFIInst ) ; OSCFIInst << Block ; buildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createEscape ( nullptr , OSCFIInst . str ( ) ) ) ;


<s> if ( ! TFI . hasFP ( MF ) ) report_fatal_error ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ; else { const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned FrameReg = RegInfo -> getPtrSizedFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( FrameReg == <STR_LIT> || FrameReg == <STR_LIT> ) && <STR_LIT> ) ;


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: AExt : case CCValAssign :: ZExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , true ) ) return false ; SrcReg = TmpReg ; break ; } case CCValAssign :: SExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , false ) ) return false ; SrcReg = TmpReg ; break ; } } } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , RetRegs [ i ] ) . addReg ( SrcReg ) ; } } } MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ;

for ( unsigned i = <NUM_LIT> , e = RetRegs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RetRegs [ i ] , RegState :: Implicit ) ;


<s> if ( type != <NUM_LIT> ? FLOAT_TYPE_P ( type ) : GET_MODE_CLASS ( mode ) == MODE_FLOAT ) return ! BYTES_BIG_ENDIAN ; return mips_pad_arg_upward ( mode , type ) ;


<s> <ISA_LIT>ELFStreamer :: <ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter ) : MCELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) {

RegInfoRecord = new <ISA_LIT>RegInfoRecord ( this , Context ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveArch ( SMLoc L ) { StringRef Arch = getParser ( ) . parseStringToEndOfStatement ( ) . trim ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> ) return Error ( L , <STR_LIT> ) ; bool WasThumb = isThumb ( ) ; Triple T ; MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( <STR_LIT> , ( <STR_LIT> + <STR_LIT> ( ID ) ) . str ( ) ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; FixModeAfterArchChange ( WasThumb , L ) ;

getTargetStreamer ( ) . emitArch ( ID ) ;


<s> <ISA_LIT>RegisterAliasInfo ( const TargetRegisterInfo & TRI ) : RegisterAliasInfo ( TRI ) {


<s> bool hasFPU ( ) const { return HasFPU ;


<s> int NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> && NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( int i = <NUM_LIT> , j = NumElems / <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ; int BitI1 = Mask [ i + <NUM_LIT> ] ; if ( ! isUndefOrEqual ( BitI , j ) ) return false ;

if ( ! isUndefOrEqual ( BitI1 , j ) ) return false ;


<s> TOut . emitR ( <STR_LIT> , ATReg , IDLoc , STI ) ; if ( useTraps ( ) ) { TOut . emitRRI ( <STR_LIT> , DstReg , ATReg , <NUM_LIT> , IDLoc , STI ) ; } else { MCContext & Context = TOut . getStreamer ( ) . getContext ( ) ; MCSymbol * BrTarget = Context . createTempSymbol ( ) ; MCOperand LabelOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( BrTarget , Context ) ) ; TOut . emitRRX ( <STR_LIT> , DstReg , ATReg , LabelOp , IDLoc , STI ) ; if ( AssemblerOptions . back ( ) -> isReorder ( ) ) TOut . emitNop ( IDLoc , STI ) ;

TOut . emitII ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IDLoc , STI ) ;


Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ;


<s> aarch64_simd_builtin_datum * d = & aarch64_simd_builtin_data [ fcode - AARCH64_SIMD_PATTERN_START ] ; enum insn_code icode = d -> code ; builtin_simd_arg args [ SIMD_MAX_BUILTIN_ARGS + <NUM_LIT> ] ; int num_args = insn_data [ d -> code ] . n_operands ; int is_void = <NUM_LIT> ; int k ; is_void = ! ! ( d -> qualifiers [ <NUM_LIT> ] & qualifier_void ) ; num_args += is_void ; for ( k = <NUM_LIT> ; k < num_args ; k ++ ) { int qualifiers_k = k ; int operands_k = k - is_void ; int expr_args_k = k - <NUM_LIT> ; if ( d -> qualifiers [ qualifiers_k ] & qualifier_lane_index ) args [ k ] = SIMD_ARG_LANE_INDEX ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_lane_pair_index ) args [ k ] = SIMD_ARG_LANE_PAIR_INDEX ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_lane_quadtup_index ) args [ k ] = SIMD_ARG_LANE_QUADTUP_INDEX ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_struct_load_store_lane_index ) args [ k ] = SIMD_ARG_STRUCT_LOAD_STORE_LANE_INDEX ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_immediate ) args [ k ] = SIMD_ARG_CONSTANT ;

else if ( d -> qualifiers [ qualifiers_k ] & qualifier_maybe_immediate ) {


<s> bool <ISA_LIT>InstrInfo :: readsLDSSrcReg ( const MachineInstr & MI ) const { if ( ! isALUInstr ( MI . getOpcode ( ) ) ) { return false ; } for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( ! I -> isReg ( ) || ! I -> isUse ( ) || TargetRegisterInfo :: isVirtualRegister ( I -> getReg ( ) ) ) continue ; if ( <STR_LIT> . contains ( I -> getReg ( ) ) ) return true ; } return false ;


<s> return packBits ( Vmcnt , Waitcnt , getVmcntBitShift ( ) , getVmcntBitWidth ( ) ) ;


<s> if ( NoAliases || ! printAliasInstr ( NewMI , Address , STI , O ) ) printInstruction ( NewMI , Address , STI , O ) ;


<s> rtx body ; if ( ! TARGET_FIX_ERR_A53_835769 ) return false ; if ( ! INSN_P ( insn ) || recog_memoized ( insn ) < <NUM_LIT> ) return false ; attr_type = get_attr_type ( insn ) ; if ( ! is_madd_op ( attr_type ) ) return false ; prev = aarch64_prev_real_insn ( insn ) ; extract_constrain_insn_cached ( insn ) ; if ( ! prev || ! has_memory_op ( prev ) ) return false ;


<s> llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Add : case AtomicRMWInst :: Sub : case AtomicRMWInst :: UMax : return APInt :: getMinValue ( BitWidth ) ; case AtomicRMWInst :: UMin : return APInt :: getMaxValue ( BitWidth ) ; case AtomicRMWInst :: Max : return APInt :: getSignedMinValue ( BitWidth ) ; case AtomicRMWInst :: Min :

return APInt :: getSignedMaxValue ( BitWidth ) ;


<s> unsigned Lo32 = Lo_32 ( Imm ) ; auto getI32Imm = [ CurDAG , dl ] ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ; } ; auto getI64Imm = [ CurDAG , dl ] ( uint64_t Imm ) { return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ; } ; InstCnt = <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ) ; InstCnt = <NUM_LIT> ; SDNode * Result = nullptr ; if ( ( LZ + FO + TZ ) > <NUM_LIT> ) { APInt SignedInt34 = APInt ( <NUM_LIT> , ( Imm >> TZ ) & <NUM_LIT> ) ; APInt Extended = SignedInt34 . sext ( <NUM_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI64Imm ( * Extended . getRawData ( ) ) ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( TZ ) , getI32Imm ( LZ ) ) ; } if ( ( LZ + TO ) > <NUM_LIT> ) { APInt SignedInt34 = APInt ( <NUM_LIT> , ( Imm >> ( <NUM_LIT> - LZ ) ) & <NUM_LIT> ) ; APInt Extended = SignedInt34 . sext ( <NUM_LIT> ) ;


<s> static DecodeStatus DecodeT2Imm7S4 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { if ( Val == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( INT32_MIN ) ) ; else { int imm = Val & <NUM_LIT> ;

if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ;


<s> return getSubtargetImpl ( ) -> getTargetLowering ( ) ;


<s> fprintf ( asm_out_file , TARGET_UNIX_ASM ? <STR_LIT> : <STR_LIT> ) ; output_addr_const_pdp11 ( asm_out_file , x ) ; fprintf ( asm_out_file , <STR_LIT> ) ; return true ;


<s> if ( FirstDbgValue ) { BB -> splice ( RegionBegin , BB , FirstDbgValue ) ; RegionBegin = FirstDbgValue ; } for ( std :: vector < std :: pair < MachineInstr * , MachineInstr * > > :: iterator DI = DbgValues . end ( ) , DE = DbgValues . begin ( ) ; DI != DE ; -- DI ) {

std :: pair < MachineInstr * , MachineInstr * > P = * std :: prev ( DI ) ;


<s> <ISA_LIT>RepoObjectWriter :: ~ <ISA_LIT>RepoObjectWriter ( ) {


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> if ( RepPrefix ) EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) ) ; InstrumentMOV ( Inst , Operands , Ctx , MII , Out ) ;

RepPrefix = ( Inst . getOpcode ( ) == <STR_LIT> ) ;


<s> assert ( <NUM_LIT> <= FirstIndex && FirstIndex < <NUM_LIT> && <STR_LIT> ) ; int FirstElt = Mask [ FirstIndex ] ; if ( all_of ( Mask , [ FirstElt ] ( int M ) { return M < <NUM_LIT> || M == FirstElt ; } ) ) return ( FirstElt << <NUM_LIT> ) | ( FirstElt << <NUM_LIT> ) | ( FirstElt << <NUM_LIT> ) | FirstElt ; unsigned Imm = <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ; Imm |= ( Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : Mask [ <NUM_LIT> ] ) << <NUM_LIT> ;


<s> return ( UseReg && ( I -> modifiesRegister ( UseReg , TRI ) ) ) || I -> modifiesRegister ( DestReg , TRI ) || I -> readsRegister ( DestReg , TRI ) || I -> hasUnmodeledSideEffects ( ) || I -> isInlineAsm ( ) || I -> isDebugValue ( ) ;


<s> while ( Size > <NUM_LIT> ) { if ( ( Size - MOV128SZ >= <NUM_LIT> ) && isYMMLoadOpcode ( LoadInst -> getOpcode ( ) ) ) { Size = Size - MOV128SZ ; buildCopy ( LoadInst , getYMMtoXMMLoadOpcode ( LoadInst -> getOpcode ( ) ) , LdDisp , StoreInst , getYMMtoXMMStoreOpcode ( StoreInst -> getOpcode ( ) ) , StDisp , MOV128SZ , LMMOffset , SMMOffset ) ; LdDisp += MOV128SZ ; StDisp += MOV128SZ ; LMMOffset += MOV128SZ ; SMMOffset += MOV128SZ ; continue ; } if ( Size - MOV64SZ >= <NUM_LIT> ) { Size = Size - MOV64SZ ; buildCopy ( LoadInst , <STR_LIT> , LdDisp , StoreInst , <STR_LIT> , StDisp , MOV64SZ , LMMOffset , SMMOffset ) ; LdDisp += MOV64SZ ; StDisp += MOV64SZ ; LMMOffset += MOV64SZ ; SMMOffset += MOV64SZ ; continue ; } if ( Size - MOV32SZ >= <NUM_LIT> ) { Size = Size - MOV32SZ ; buildCopy ( LoadInst , <STR_LIT> , LdDisp , StoreInst , <STR_LIT> , StDisp , MOV32SZ , LMMOffset , SMMOffset ) ; LdDisp += MOV32SZ ; StDisp += MOV32SZ ; LMMOffset += MOV32SZ ; SMMOffset += MOV32SZ ; continue ; }


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter ) : MCELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) , State ( EMS_None ) {


<s> const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC ) return false ; unsigned SubReg = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Offset / <NUM_LIT> , DstSize / <NUM_LIT> ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubReg ) ; if ( ! SrcRC ) return false ; SrcReg = constrainOperandRegClass ( * MF , TRI , * MRI , TII , RBI , I , * SrcRC , I . getOperand ( <NUM_LIT> ) ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; BuildMI ( * BB , & I , DL , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( SrcReg , <NUM_LIT> , SubReg ) ; I . eraseFromParent ( ) ; return true ;


<s> void printlea64mem ( const MachineInstr * MI , unsigned OpNo ) { O << <STR_LIT> ; printLeaMemReference ( MI , OpNo ) ;


<s> break ; } if ( ! ( Op -> getOperand ( i ) . isUndef ( ) || isNullConstant ( Op -> getOperand ( i ) ) ) ) return SDValue ( ) ; } if ( ! isPowerOf2_32 ( Delta ) || Delta == <NUM_LIT> ) return SDValue ( ) ; for ( unsigned i = Delta ; i < NumElts ; i ++ ) { if ( i % Delta == <NUM_LIT> ) { if ( Op -> getOperand ( i ) != ExtValue ) return SDValue ( ) ;

} else if ( ! ( isNullConstant ( Op -> getOperand ( i ) ) || Op -> getOperand ( i ) . isUndef ( ) ) ) return SDValue ( ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>RegStackify ( ) ) ; addPass ( create<ISA_LIT>RegColoring ( ) ) ; } TargetPassConfig :: addPostRegAlloc ( ) ; addPass ( create<ISA_LIT>PEI ( ) ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( FPOffset ) ; } if ( MFI -> adjustsStack ( ) ) {

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( RAOffset ) ;


<s> bool isVecListDPairSpaced ( ) const { if ( isSingleSpacedVectorList ( ) ) return false ;

return ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( VectorList . RegNum ) ) ;


<s> static unsigned int mips_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( ST_REG_P ( regno ) ) return ( GET_MODE_SIZE ( mode ) + <NUM_LIT> ) / <NUM_LIT> ; if ( FP_REG_P ( regno ) ) { if ( MSA_SUPPORTED_MODE_P ( mode ) ) return <NUM_LIT> ;

return ( GET_MODE_SIZE ( mode ) + UNITS_PER_FPREG - <NUM_LIT> ) / UNITS_PER_FPREG ;


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const { llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ;


<s> unsigned getReg213Opcode ( ) const {


<s> static alias_set_type set = - <NUM_LIT> ;

if ( set == - <NUM_LIT> ) set = new_alias_set ( ) ;


<s> static int ix86_avx_u128_mode_exit ( void ) {


<s> bool shouldBuildLookupTables ( ) const {


<s> return ( TYPE_MODE ( type ) == BLKmode || ( ( TARGET_HITACHI || sh_attr_renesas_p ( fndecl ) ) && TREE_CODE ( type ) == RECORD_TYPE ) ) ; }


<s> for ( unsigned i = <NUM_LIT> ; i != NumArgs ; i ++ ) { MVT ArgVT = Outs [ i ] . VT ; <STR_LIT> ArgFlags = Outs [ i ] . Flags ;

Type * OrigTy = CLI ? CLI -> getArgs ( ) [ Outs [ i ] . OrigArgIndex ] . Ty : nullptr ;


<s> if ( CONST_INT_P ( op2 ) ) { HOST_WIDE_INT n = trunc_int_for_mode ( INTVAL ( op2 ) , DImode ) ; return tilegx_expand_const_muldi ( op0 , op1 , n ) ; } return false ;


<s> bool <ISA_LIT>Operand :: isU16Imm ( ) const { return isImm ( ) && isUInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) { if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( getCurrentABIString ( ) ) ) ;

if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ;


<s> int regno , padding ; function_arg_slotno ( cum , mode , type , arg . named , false , & regno , & padding ) ; cum -> words += padding ; if ( TARGET_ARCH32 ) cum -> words += CEIL_NWORDS ( GET_MODE_SIZE ( mode ) ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {


<s> TargetRegistry :: RegisterMCSubtargetInfo ( T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( T , create<ISA_LIT>MCCodeEmitter ) ;

TargetRegistry :: RegisterMCInstPrinter ( T , create<ISA_LIT>MCInstPrinter ) ;


<s> if ( RVFI -> getLibCallStackSize ( ) ) return <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( StackSize ) && ( CSI . size ( ) > <NUM_LIT> ) ) {

return <NUM_LIT> - getStackAlign ( ) . value ( ) ;


<s> for ( MachineInstr * MI : LowerToCopyInstrs ) {

for ( unsigned i = MI -> getNumExplicitOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; i -- ) MI -> RemoveOperand ( i ) ;


<s> Type * DstTy = I -> getType ( ) ; if ( ! isTypeLegal ( DstTy , DstVT ) ) return false ; if ( DstVT != <STR_LIT> ) return false ; Value * Src = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Src -> getType ( ) ; if ( ! isTypeLegal ( SrcTy , SrcVT ) ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ;

unsigned SrcReg = getRegForValue ( Src ) ;


<s> } } else { for ( unsigned I = <NUM_LIT> ; I != VecLen ; I += <NUM_LIT> ) { unsigned B = <NUM_LIT> ; for ( ; B != <NUM_LIT> ; ++ B ) { if ( ! Values [ I + B ] . isUndef ( ) ) break ; } SDValue F = Values [ I + B ] ; AllT &= IsTrue ( F ) ; AllF &= IsFalse ( F ) ; SDValue Ext = ( B < <NUM_LIT> ) ? DAG . getZExtOrTrunc ( F , dl , <STR_LIT> ) : DAG . getUNDEF ( <STR_LIT> ) ; Bytes . push_back ( Ext ) ; for ( ; B != <NUM_LIT> ; ++ B ) assert ( Values [ I + B ] . isUndef ( ) || Values [ I + B ] == F ) ; } } if ( AllT ) return DAG . getNode ( <STR_LIT> , dl , VecTy ) ; if ( AllF ) return DAG . getNode ( <STR_LIT> , dl , VecTy ) ; MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue ByteVec = buildHvxVectorReg ( Bytes , dl , ByteTy , DAG ) ;

return DAG . getNode ( <STR_LIT> , dl , VecTy , ByteVec ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Op1 = U -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( Op1 ) ) { if ( Imm -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) return false ; if ( U -> getOpcode ( ) == <STR_LIT> && Imm -> getAPIntValue ( ) . getBitWidth ( ) == <NUM_LIT> && Imm -> getAPIntValue ( ) . isIntN ( <NUM_LIT> ) ) return false ; if ( U -> getOpcode ( ) == <STR_LIT> && ( Imm -> getAPIntValue ( ) == UINT8_MAX || Imm -> getAPIntValue ( ) == UINT16_MAX || Imm -> getAPIntValue ( ) == UINT32_MAX ) ) return false ; if ( ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) && ( - Imm -> getAPIntValue ( ) ) . isSignedIntN ( <NUM_LIT> ) ) return false ; } if ( Op1 . getOpcode ( ) == <STR_LIT> ) { SDValue Val = Op1 . getOperand ( <NUM_LIT> ) ; if ( Val . getOpcode ( ) == <STR_LIT> ) return false ; } if ( U -> getOpcode ( ) == <STR_LIT> || U -> getOpcode ( ) == <STR_LIT> ) { if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isOneConstant ( U -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) return false ; if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isOneConstant ( U -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) return false ; } if ( U -> getOpcode ( ) == <STR_LIT> ) { SDValue U0 = U -> getOperand ( <NUM_LIT> ) ; SDValue U1 = U -> getOperand ( <NUM_LIT> ) ; if ( U0 . getOpcode ( ) == <STR_LIT> ) { auto * C = dyn_cast < ConstantSDNode > ( U0 . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getSExtValue ( ) == - <NUM_LIT> ) return false ; } if ( U1 . getOpcode ( ) == <STR_LIT> ) { auto * C = dyn_cast < ConstantSDNode > ( U1 . getOperand ( <NUM_LIT> ) ) ; if ( C && C -> getSExtValue ( ) == - <NUM_LIT> ) return false ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isa < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) ) return false ; break ; } } if ( Root -> getOpcode ( ) == <STR_LIT> && isNullConstant ( Root -> getOperand ( <NUM_LIT> ) ) && ( Root -> getOperand ( <NUM_LIT> ) . isUndef ( ) || <STR_LIT> ( Root -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) ) return false ;


<s> { RTLIB :: OEQ_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OGE ] = { { RTLIB :: OGE_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OGT ] = { { RTLIB :: OGT_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OLE ] = { { RTLIB :: OLE_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_OLT ] = { { RTLIB :: OLT_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: O_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB :: OLT_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGT ] = { { RTLIB :: OLE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULE ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULT ] = { { RTLIB :: OGE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNE ] = { { RTLIB :: UNE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNO ] = { { RTLIB :: UO_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ONE ] = { { RTLIB :: OGT_F32 , CmpInst :: BAD_ICMP_PREDICATE } , { RTLIB :: OLT_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ;

FCmp32Libcalls [ CmpInst :: FCMP_UEQ ] = {


<s> int KCacheBank = MI -> getOperand ( OpNo - <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> << KCacheBank << <STR_LIT> ; int KCacheAddr = MI -> getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; int LineSize = ( KCacheMode == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; O << KCacheAddr * <NUM_LIT> << <STR_LIT> << KCacheAddr * <NUM_LIT> + LineSize ; }


<s> void emitARM64WinCFISaveFPLRX ( int Offset ) override { OS << <STR_LIT> << Offset << <STR_LIT> ;


<s> BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , TmpExec ) ; BuildMI ( MBB , I , DL , TII -> get ( MovExecOpc ) , SaveExec ) . addReg ( Exec ) ; MachineBasicBlock * LoopBB ; MachineBasicBlock * RemainderBB ; std :: tie ( LoopBB , RemainderBB ) = splitBlockForLoop ( MI , MBB , false ) ; const MachineOperand * Idx = TII -> getNamedOperand ( MI , <STR_LIT> :: idx ) ; auto InsPt = emitLoadM0FromVGPRLoop ( TII , MRI , MBB , * LoopBB , DL , * Idx , InitResultReg , DstReg , PhiReg , TmpExec , Offset , UseGPRIdxMode , IsIndirectSrc ) ; MachineBasicBlock :: iterator First = RemainderBB -> begin ( ) ; BuildMI ( * RemainderBB , First , DL , TII -> get ( MovExecOpc ) , Exec ) . addReg ( SaveExec ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & <STR_LIT> ;


<s> } if ( PassName == <STR_LIT> ) { PM . addPass ( <ISA_LIT>UseNativeCallsPass ( ) ) ; return true ; } if ( PassName == <STR_LIT> ) { PM . addPass ( <ISA_LIT>PromoteAllocaPass ( * this ) ) ; return true ; } if ( PassName == <STR_LIT> ) { PM . addPass ( <ISA_LIT>PromoteAllocaToVectorPass ( * this ) ) ; return true ; } if ( PassName == <STR_LIT> ) { PM . addPass ( <ISA_LIT>LowerKernelAttributesPass ( ) ) ; return true ; } if ( PassName == <STR_LIT> ) { PM . addPass ( <ISA_LIT>PropagateAttributesEarlyPass ( * this ) ) ; return true ; } return false ; } ) ; PB . registerAnalysisRegistrationCallback ( [ ] ( FunctionAnalysisManager & FAM ) { FAM . registerPass ( [ & ] { return <ISA_LIT>AA ( ) ; } ) ; } ) ; PB . registerParseAACallback ( [ ] ( StringRef AAName , AAManager & AAM ) { if ( AAName == <STR_LIT> ) { AAM . registerFunctionAnalysis < <ISA_LIT>AA > ( ) ; return true ; } return false ; } ) ; PB . registerPipelineStartEPCallback ( [ this ] ( ModulePassManager & PM , PassBuilder :: OptimizationLevel Level ) { FunctionPassManager FPM ; FPM . addPass ( <ISA_LIT>PropagateAttributesEarlyPass ( * this ) ) ; FPM . addPass ( <ISA_LIT>UseNativeCallsPass ( ) ) ; if ( EnableLibCallSimplify && Level != PassBuilder :: OptimizationLevel :: O0 ) FPM . addPass ( <ISA_LIT>SimplifyLibCallsPass ( * this ) ) ; PM . addPass ( createModuleToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ;


<s> static bool aarch64_register_saved_on_entry ( int regno ) {

return cfun -> machine -> frame . reg_offset [ regno ] >= <NUM_LIT> ;


<s> else if ( Flags . isZExt ( ) ) ArgVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgVal , DAG . getValueType ( ObjectVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , ObjectVT , ArgVal ) ;


<s> explicit <ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) {


<s> for ( const auto & I : M . named_metadata ( ) ) EnumerateNamedMDNode ( & I ) ;


<s> if ( GET_MODE ( inputs [ i ] ) != TFmode ) continue ; const char * constraint = constraints [ noutputs + i ] ; bool allows_mem , allows_reg ; bool ok = parse_input_constraint ( & constraint , i , ninputs , noutputs , <NUM_LIT> , constraints . address ( ) , & allows_mem , & allows_reg ) ; gcc_assert ( ok ) ; if ( ! f_constraint_p ( constraint ) ) continue ; gcc_assert ( allows_reg ) ; rtx fprx2 ; if ( s390_hard_fp_reg_p ( inputs [ i ] ) ) { fprx2 = gen_rtx_REG ( FPRX2mode , REGNO ( inputs [ i ] ) ) ; rtx v1 = gen_rtx_REG ( V2DFmode , REGNO ( inputs [ i ] ) + <NUM_LIT> ) ; rtx v2 = gen_rtx_REG ( V2DFmode , REGNO ( inputs [ i ] ) ) ; emit_insn ( gen_vec_permiv2df ( v1 , v2 , v1 , GEN_INT ( <NUM_LIT> ) ) ) ; } else {


<s> if ( Instruction * I = simplifyNvvmIntrinsic ( & II , IC ) ) { return I ; } return None ;


<s> assert ( ! FirstMI . hasOrderedMemoryRef ( ) && ! TII -> isLdStPairSuppressed ( FirstMI ) && <STR_LIT> ) ; unsigned OpcA = FirstMI . getOpcode ( ) ; unsigned OpcB = MI . getOpcode ( ) ; if ( OpcA == OpcB ) return true ; bool IsValidLdStrOpc , PairIsValidLdStrOpc ; unsigned NonSExtOpc = getMatchingNonSExtOpcode ( OpcA , & IsValidLdStrOpc ) ; assert ( IsValidLdStrOpc && <STR_LIT> ) ; if ( NonSExtOpc == getMatchingNonSExtOpcode ( OpcB , & PairIsValidLdStrOpc ) ) {

Flags . setSExtIdx ( NonSExtOpc == ( unsigned ) OpcA ? <NUM_LIT> : <NUM_LIT> ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ;

Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ;


<s> break ; case CmpInst :: FCMP_OGT : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_OGE : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_OLT : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_OLE : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_ONE : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case CmpInst :: FCMP_ORD : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_UNO : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_UEQ : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case CmpInst :: FCMP_UGT : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_UGE : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_ULT : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_ULE : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_UNE : CondCode = <STR_LIT> ;


<s> return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ; if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . isVector ( ) ) {

if ( SDValue R = PromoteMaskArithmetic ( N , DAG , Subtarget ) ) return R ;


<s> static int const_costs_int ( HOST_WIDE_INT value , int zero_cost ) { if ( CONST_OK_FOR_I ( value ) ) return zero_cost ; else if ( CONST_OK_FOR_J ( value ) ) return <NUM_LIT> ;

else if ( CONST_OK_FOR_K ( value ) ) return <NUM_LIT> ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>32Target ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>32LETarget ( ) , create<ISA_LIT>LEDisassembler ) ;

TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>64Target ( ) , create<ISA_LIT>Disassembler ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SDValue Operands [ ] = { MaskedOff , Node -> getOperand ( NF + <NUM_LIT> ) , Node -> getOperand ( NF + <NUM_LIT> ) , Node -> getOperand ( NF + <NUM_LIT> ) , Node -> getOperand ( NF + <NUM_LIT> ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( NF + <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ;

unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ;


<s> for ( IntrinsicInst * ConvertToUse : ConvertToUses ) { for ( User * User : ConvertToUse -> users ( ) ) { auto * IntrUser = dyn_cast < IntrinsicInst > ( User ) ; if ( IntrUser && IntrUser -> getIntrinsicID ( ) == <STR_LIT> ) { const auto * IntrUserVTy = cast < ScalableVectorType > ( IntrUser -> getType ( ) ) ;

if ( IntrUserVTy -> getElementCount ( ) . getKnownMinValue ( ) > PTrueVTy -> getElementCount ( ) . getKnownMinValue ( ) ) return true ;


<s> if ( Vec . getValueType ( ) != VT ) return SDValue ( ) ; SDValue Idx = SplatVal . getOperand ( <NUM_LIT> ) ; if ( Idx . getValueType ( ) != Subtarget . getXLenVT ( ) ) return SDValue ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) {

ContainerVT = getContainerForFixedLengthVector ( DAG , VT , Subtarget ) ;


<s> qword q ; unsigned long long l [ <NUM_LIT> ] ; } x ; x . q = q ; return ( x . l [ <NUM_LIT> ] ) ;


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) if ( SDValue V = PerformSRACombine ( N , DAG ) ) return V ;

if ( N -> getOpcode ( ) != <STR_LIT> ) if ( SDValue V = performShiftToAllZeros ( N , DAG , Subtarget ) ) return V ;


<s> EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ) ; } } return Chain ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>TargetMachine & tm , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TM ( tm ) , TII ( tii ) {

StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ;


<s> unsigned Num = <NUM_LIT> ; if ( ! STI . is64Bit ( ) && ! isInt < <NUM_LIT> > ( Val ) ) report_fatal_error ( <STR_LIT> ) ; <STR_LIT> Seq = <STR_LIT> ( Val , STI . getFeatureBits ( ) ) ; assert ( ! Seq . empty ( ) ) ; for ( <STR_LIT> & Inst : Seq ) { if ( ++ Num == Seq . size ( ) ) Result = DstReg ; if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } else if ( Inst . Opc == <STR_LIT> ) {

BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addReg ( <STR_LIT> ) . setMIFlag ( Flag ) ;


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; unsigned DivOp = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Div = DAG . getNode ( DivOp , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;

SDValue Mul = DAG . getNode ( <STR_LIT> , DL , VT , Div , Op . getOperand ( <NUM_LIT> ) ) ;


<s> const TargetData * TD = TM . getTargetData ( ) ; if ( ! GVar -> hasInitializer ( ) ) return ; if ( EmitSpecialLLVMGlobal ( GVar ) ) return ; std :: string name = Mang -> getValueName ( GVar ) ; Constant * C = GVar -> getInitializer ( ) ; unsigned Size = TD -> getTypePaddedSize ( C -> getType ( ) ) ; unsigned Align = TD -> getPreferredAlignmentLog ( GVar ) ; SwitchToSection ( TAI -> SectionForGlobal ( GVar ) ) ;

printVisibility ( name , GVar -> getVisibility ( ) ) ;


<s> EVT ScalarVT = VT . getScalarType ( ) ; return ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> || ( ScalarVT == <STR_LIT> && Subtarget -> has16BitInsts ( ) ) ) ;


<s> NewBB -> addSuccessor ( Succ ) ; } measureFunction ( BlockOffsets , & * MBB ) ; ++ NumSplit ; return true ; } MachineInstr & OldBranch = * MI ; DebugLoc dl = OldBranch . getDebugLoc ( ) ; int InstrSizeDiff = - TII -> getInstSizeInBytes ( OldBranch ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * NextMBB = & * std :: next ( MBB ) ; assert ( MBB -> isSuccessor ( NextMBB ) && <STR_LIT> ) ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; Cond . push_back ( MI -> getOperand ( <NUM_LIT> ) ) ; TII -> reverseBranchCondition ( Cond ) ; MI = BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( NextMBB ) . addOperand ( Cond [ <NUM_LIT> ] ) ; InstrSizeDiff += TII -> getInstSizeInBytes ( * MI ) ; ++ MI ; }

MI = BuildMI ( * MBB , MI , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( DestBB ) ;


<s> bool IsAGPR = TRI -> isAGPRClass ( DstRC ) ; for ( unsigned I = <NUM_LIT> , N = MI . getNumOperands ( ) ; I != N ; I += <NUM_LIT> ) { Register SrcReg = MI . getOperand ( I ) . getReg ( ) ; unsigned SrcSubReg = MI . getOperand ( I ) . getSubReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; assert ( TRI -> isSGPRClass ( SrcRC ) && <STR_LIT> ) ; SrcRC = TRI -> getSubRegClass ( SrcRC , SrcSubReg ) ; const TargetRegisterClass * NewSrcRC = TRI -> getEquivalentVGPRClass ( SrcRC ) ; Register TmpReg = MRI . createVirtualRegister ( NewSrcRC ) ; BuildMI ( * MI . getParent ( ) , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , TmpReg ) . add ( MI . getOperand ( I ) ) ; if ( IsAGPR ) { const TargetRegisterClass * NewSrcRC = TRI -> getEquivalentAGPRClass ( SrcRC ) ; Register TmpAReg = MRI . createVirtualRegister ( NewSrcRC ) ; unsigned Opc = NewSrcRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MI . getParent ( ) , & MI , MI . getDebugLoc ( ) , TII -> get ( Opc ) , TmpAReg ) . addReg ( TmpReg , RegState :: Kill ) ;


<s> assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) {

Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ;


<s> else if ( decl && flag_unit_at_a_time ) { cgraph_node * local_info_node = cgraph_node :: local_info_node ( CONST_CAST_TREE ( decl ) ) ; if ( local_info_node && local_info_node -> local ) return ARM_PCS_AAPCS_LOCAL ; } } else if ( user_convention && user_pcs != arm_pcs_default ) sorry ( <STR_LIT> ) ; return arm_pcs_default ;


<s> static void mips_set_frame_expr ( rtx frame_pattern ) { rtx insn ; insn = get_last_insn ( ) ;

RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; SDLoc DL ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue CPAddr ; bool IsPositionIndependent = isPositionIndependent ( ) || Subtarget -> isROPI ( ) || Subtarget -> isPIP ( ) ; if ( ! IsPositionIndependent ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; if ( ! IsPositionIndependent ) return Result ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , PtrVT , Result , PICLabel ) ;


<s> <ISA_LIT>Argument ( bool ) : IsRegister ( true ) , RegisterName ( ) {


<s> unsigned LocalGEPsSeen = <NUM_LIT> ; if ( llvm :: any_of ( L -> getSubLoops ( ) , [ BB ] ( const Loop * SubLoop ) { return SubLoop -> contains ( BB ) ; } ) ) continue ; for ( const Instruction & I : * BB ) { if ( const BranchInst * Br = dyn_cast < BranchInst > ( & I ) ) { if ( UP . Threshold < MaxBoost && Br -> isConditional ( ) ) { BasicBlock * Succ0 = Br -> getSuccessor ( <NUM_LIT> ) ; BasicBlock * Succ1 = Br -> getSuccessor ( <NUM_LIT> ) ; if ( ( L -> contains ( Succ0 ) && L -> isLoopExiting ( Succ0 ) ) || ( L -> contains ( Succ1 ) && L -> isLoopExiting ( Succ1 ) ) ) continue ; if ( dependsOnLocalPhi ( L , Br -> getCondition ( ) ) ) { UP . Threshold += UnrollThresholdIf ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << UP . Threshold << <STR_LIT> << * L << <STR_LIT> << * Br << '\n' ) ; if ( UP . Threshold >= MaxBoost ) return ; } } continue ; } const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP ) continue ; unsigned AS = GEP -> getAddressSpace ( ) ; unsigned Threshold = <NUM_LIT> ; if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) Threshold = ThresholdPrivate ; else if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) Threshold = ThresholdLocal ; else continue ; if ( UP . Threshold >= Threshold ) continue ; if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { const Value * Ptr = GEP -> getPointerOperand ( ) ; const AllocaInst * Alloca = dyn_cast < AllocaInst > ( GetUnderlyingObject ( Ptr , DL ) ) ; if ( ! Alloca || ! Alloca -> isStaticAlloca ( ) ) continue ; Type * Ty = Alloca -> getAllocatedType ( ) ; unsigned AllocaSize = Ty -> isSized ( ) ? DL . getTypeAllocSize ( Ty ) : <NUM_LIT> ; if ( AllocaSize > MaxAlloca ) continue ; } else if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) {


<s> RegisterRef RD = CI -> getOperand ( <NUM_LIT> ) ; RegisterRef RP = CI -> getOperand ( <NUM_LIT> ) ; MachineOperand & S1 = CI -> getOperand ( <NUM_LIT> ) , & S2 = CI -> getOperand ( <NUM_LIT> ) ; bool Done = false ; if ( S1 . isReg ( ) ) { RegisterRef RS = S1 ; MachineInstr * RDef = getReachingDefForPred ( RS , CI , RP . Reg , true ) ; if ( ! RDef || ! HII -> isPredicable ( * RDef ) ) { Done = coalesceRegisters ( RD , RegisterRef ( S1 ) ) ; if ( Done ) { UpdRegs . insert ( RD . Reg ) ; UpdRegs . insert ( S1 . getReg ( ) ) ; } } } if ( ! Done && S2 . isReg ( ) ) { RegisterRef RS = S2 ; MachineInstr * RDef = getReachingDefForPred ( RS , CI , RP . Reg , false ) ; if ( ! RDef || ! HII -> isPredicable ( * RDef ) ) { Done = coalesceRegisters ( RD , RegisterRef ( S2 ) ) ; if ( Done ) { UpdRegs . insert ( RD . Reg ) ; UpdRegs . insert ( S2 . getReg ( ) ) ; } } } Changed |= Done ; } return Changed ;


<s> unsigned type = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rs = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rs , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Shift = <STR_LIT> ; switch ( type ) { case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> : Shift = <STR_LIT> ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } Offsets = GEP -> getOperand ( <NUM_LIT> ) ; assert ( Ty -> getVectorNumElements ( ) == Offsets -> getType ( ) -> getVectorNumElements ( ) ) ; if ( Offsets -> getType ( ) -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; if ( ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; else if ( ! ( Offsets -> getType ( ) -> getVectorNumElements ( ) == <NUM_LIT> && Offsets -> getType ( ) -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) return nullptr ; if ( Ty != Offsets -> getType ( ) ) { if ( ( Ty -> getScalarSizeInBits ( ) < Offsets -> getType ( ) -> getScalarSizeInBits ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseSVEVectorWithOffset ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; const SMLoc S = getLoc ( ) ; StringRef Kind ; int RegNum = tryMatchSVEVectorRegister ( Parser . getTok ( ) , Kind , false ) ; if ( RegNum == - <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; if ( Kind . empty ( ) ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: SVEVector , S , getLoc ( ) , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , false , S , getContext ( ) ) ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { return MatchOperand_Success ; } Parser . Lex ( ) ; SMLoc SS = getLoc ( ) ; const AsmToken & TokE = Parser . getTok ( ) ; if ( TokE . isNot ( AsmToken :: Identifier ) ) { return MatchOperand_NoMatch ; } StringRef value = TokE . getString ( ) ;

const char * extTypeName = getGPROffsetExtTypeName ( value ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Elts ; MVT SVT = VT . getVectorElementType ( ) ; unsigned SVTBits = SVT . getSizeInBits ( ) ; APInt One ( SVTBits , <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Op = Amt -> getOperand ( i ) ; if ( Op -> isUndef ( ) ) { Elts . push_back ( Op ) ; continue ; } ConstantSDNode * ND = cast < ConstantSDNode > ( Op ) ; APInt C ( SVTBits , ND -> getAPIntValue ( ) . getZExtValue ( ) ) ; uint64_t ShAmt = C . getZExtValue ( ) ; if ( ShAmt >= SVTBits ) { Elts . push_back ( DAG . getUNDEF ( SVT ) ) ; continue ; } Elts . push_back ( DAG . getConstant ( One . shl ( ShAmt ) , dl , SVT ) ) ; } return DAG . getBuildVector ( VT , dl , Elts ) ; } if ( VT == <STR_LIT> ) { Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getNode ( <STR_LIT> , dl , VT , Amt , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; Amt = DAG . getBitcast ( <STR_LIT> , Amt ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Amt ) ; } if ( VT == <STR_LIT> && ! Subtarget . hasAVX2 ( ) ) { SDValue Z = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue Lo = DAG . getBitcast ( <STR_LIT> , getUnpackl ( DAG , dl , VT , Amt , Z ) ) ;

SDValue Hi = DAG . getBitcast ( <STR_LIT> , getUnpackh ( DAG , dl , VT , Amt , Z ) ) ;


<s> if ( insn . spec -> operands [ index ] . encoding != ENCODING_NONE ) { if ( translateOperand ( mcInst , insn . spec -> operands [ index ] , insn ) ) {


<s> EndbrOpcode = SubTarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ( MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! I -> isCall ( ) ) continue ; if ( IsCallReturnTwice ( I -> getOperand ( <NUM_LIT> ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } }


<s> case <STR_LIT> : InstrOffs = MI -> getOperand ( Idx + <NUM_LIT> ) . getImm ( ) ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : { const MachineOperand & OffOp = MI -> getOperand ( Idx + <NUM_LIT> ) ; InstrOffs = <STR_LIT> ( OffOp . getImm ( ) ) ; if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs = - InstrOffs ; Scale = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = Idx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs = - InstrOffs ;


<s> static HOST_WIDE_INT avr_starting_frame_offset ( void ) { return <NUM_LIT> + avr_outgoing_args_size ( ) ;


<s> Micro<ISA_LIT>SizeReduce :: Micro<ISA_LIT>SizeReduce ( ) : MachineFunctionPass ( ID ) {


<s> Top . init ( DAG , SchedModel ) ; Bot . init ( DAG , SchedModel ) ; const InstrItineraryData * Itin = DAG -> getSchedModel ( ) -> getInstrItineraries ( ) ; const TargetMachine & TM = DAG -> MF . getTarget ( ) ; Top . HazardRec = TM . getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ;

Bot . HazardRec = TM . getInstrInfo ( ) -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ;


<s> if ( MI . getNumOperands ( ) != <NUM_LIT> ) { assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; const TargetRegisterClass * RC = TII -> getOpRegClass ( MI , <NUM_LIT> ) ; unsigned Size = RC -> getSize ( ) ; Result . Named . LGKM = Size > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; } else { Result . Named . LGKM = <NUM_LIT> ;


<s> unsigned MOp , FOp ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : MOp = <STR_LIT> ; FOp = <STR_LIT> ; break ; case <STR_LIT> : MOp = <STR_LIT> ; FOp = <STR_LIT> ; break ; } const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; MachineOperand MSrc = MI -> getOperand ( <NUM_LIT> ) ; unsigned VSrc = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineOperand & Disp = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand ZeroDisp = MachineOperand :: CreateImm ( <NUM_LIT> ) ; bool hasDisp = Disp . isGlobal ( ) || Disp . isImm ( ) ; if ( hasDisp && MSrc . isReg ( ) ) MSrc . setIsKill ( false ) ;

MachineInstrBuilder MIM = BuildMI ( * BB , MI , DL , TII -> get ( MOp ) ) . addOperand ( MSrc ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addDisp ( hasDisp ? Disp : ZeroDisp , <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> case CCValAssign :: Full : break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachinePointerInfo DstInfo = MachinePointerInfo :: getStack ( MF , Offset ) ; SDValue PtrOffset = DAG . getConstant ( Offset , SL , <STR_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , StackPtr , PtrOffset ) ; SDValue Store = DAG . getStore ( Chain , SL , ArgVal , Ptr , DstInfo , <NUM_LIT> , MachineMemOperand :: MODereferenceable ) ; return Store ;


<s> unsigned BrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( <ISA_LIT>Pred ) . addReg ( <STR_LIT> ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } else if ( TruncInst * TI = dyn_cast < TruncInst > ( BI -> getCondition ( ) ) ) { MVT SourceVT ; if ( TI -> hasOneUse ( ) && TI -> getParent ( ) == I -> getParent ( ) && ( isLoadTypeLegal ( TI -> getOperand ( <NUM_LIT> ) -> getType ( ) , SourceVT ) ) ) { unsigned TstOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; Register OpReg = getRegForValue ( TI -> getOperand ( <NUM_LIT> ) ) ; OpReg = constrainOperandRegClass ( TII . get ( TstOpc ) , OpReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TstOpc ) ) . addReg ( OpReg ) . addImm ( <NUM_LIT> ) ) ; unsigned CCMode = <STR_LIT> ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; CCMode = <STR_LIT> ; } unsigned BrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( BrOpc ) ) . addMBB ( TBB ) . addImm ( CCMode ) . addReg ( <STR_LIT> ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; fastEmitBranch ( Target , DbgLoc ) ;


<s> static char prid_str [ <NUM_LIT> ] ;

sprintf ( prid_str , <STR_LIT> , cpucfg_cache [ <NUM_LIT> ] ) ;


<s> for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned j , e = d -> perm [ i ] & ( nelt / <NUM_LIT> - <NUM_LIT> ) ; unsigned which = ( ( d -> perm [ i ] ^ i ) & ( nelt / <NUM_LIT> ) ) * eltsz ; for ( j = <NUM_LIT> ; j < eltsz ; ++ j ) { rperm [ ! ! which ] [ ( i * eltsz + j ) ^ which ] = GEN_INT ( e * eltsz + j ) ; rperm [ ! which ] [ ( i * eltsz + j ) ^ ( which ^ <NUM_LIT> ) ] = m128 ; } } vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( <NUM_LIT> , rperm [ <NUM_LIT> ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; h = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , d -> op0 ) ; emit_insn ( gen_avx2_pshufbv32qi3 ( h , op , vperm ) ) ; hp = gen_reg_rtx ( V4DImode ) ;


<s> <ISA_LIT>AAResult run ( Function & F , AnalysisManager < Function > & AM ) {

return <ISA_LIT>AAResult ( F . getParent ( ) -> getDataLayout ( ) ) ;


<s> int getNumNamedVarArgParams ( ) const { return NumNamedVarArgParams ;


<s> void <ISA_LIT>MachineFunctionInfo :: anchor ( ) {


<s> bool trace ( ) const { return Trace ;


<s> bool <ISA_LIT>Subtarget :: enablePostRAScheduler ( ) const {


<s> unsigned <ISA_LIT>TTI :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy ) const { std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( ValTy ) ; MVT MTy = LT . second ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry < MVT > SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < MVT > AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ;

static const CostTblEntry < MVT > AVX2CostTbl [ ] = {


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_NONE : return <NUM_LIT> ; case FK_Data_1 : return <NUM_LIT> ; case FK_Data_2 : return <NUM_LIT> ; case FK_Data_4 : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> :


<s> OS << static_cast < uint8_t > ( ( Binary >> <NUM_LIT> ) & <NUM_LIT> ) ; OS << static_cast < uint8_t > ( ( Binary >> <NUM_LIT> ) & <NUM_LIT> ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << '\n' ) ;


<s> for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) compute_local_backward_infos ( bb ) ; if ( dump_file ) m_vector_manager -> dump ( dump_file ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> ) ; for ( const bb_info * bb : crtl -> ssa -> bbs ( ) ) emit_local_forward_vsetvls ( bb ) ; if ( dump_file ) m_vector_manager -> dump ( dump_file ) ;


<s> return ( ModImm >> <NUM_LIT> ) & <NUM_LIT> ;


<s> static inline vec_float4 vec_andc ( vec_float4 a , vec_bint4 b ) {

return ( spu_andc ( a , ( vec_float4 ) ( b ) ) ) ;


<s> addDefsUsesToList ( * MBBI , RegDefsToMove , PhysRegUsesToMove ) ; continue ; } addToListsIfDependent ( * MBBI , RegDefsToMove , PhysRegUsesToMove , InstsToMove ) ; continue ; } if ( MBBI -> hasOrderedMemoryRef ( ) ) return false ; int Swizzled = <STR_LIT> ( MBBI -> getOpcode ( ) , <STR_LIT> :: swz ) ; if ( Swizzled != - <NUM_LIT> && MBBI -> getOperand ( Swizzled ) . getImm ( ) ) return false ; if ( addToListsIfDependent ( * MBBI , RegDefsToMove , PhysRegUsesToMove , InstsToMove ) ) continue ; if ( & * MBBI == & * Paired . I ) { if ( TRI -> hasAGPRs ( getDataRegClass ( * MBBI ) ) != IsAGPR ) return false ; if ( IsAGPR && CI . InstClass == DS_WRITE ) return false ; if ( canMoveInstsAcrossMemOp ( * MBBI , InstsToMove , AA ) ) { if ( CI . InstClass != MIMG ) offsetsCanBeCombined ( CI , * STM , Paired , true ) ; return true ; } return false ; } if ( ! memAccessesCanBeReordered ( * CI . I , * MBBI , AA ) || ! canMoveInstsAcrossMemOp ( * MBBI , InstsToMove , AA ) ) break ; } return false ;


if ( opts -> x_flag_prefetch_loop_arrays < <NUM_LIT> && ! opts -> x_optimize_size && aarch64_tune_params . prefetch -> default_opt_level >= <NUM_LIT> && opts -> x_optimize >= aarch64_tune_params . prefetch -> default_opt_level ) opts -> x_flag_prefetch_loop_arrays = <NUM_LIT> ;


<s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const { return MachineJumpTableInfo :: EK_Inline ;


<s> return arg . type && TREE_CODE ( TYPE_SIZE ( arg . type ) ) != INTEGER_CST ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerAtomicRMW ( SDValue Op , SelectionDAG & DAG ) const {


<s> bool R600InstrInfo :: isTrig ( const MachineInstr & MI ) const { return get ( MI . getOpcode ( ) ) . TSFlags & <STR_LIT> ;


<s> unsigned int NeedWait = <NUM_LIT> ; if ( ScoreToWait == - <NUM_LIT> ) { NeedWait = CNT_MASK ( T ) ; setScoreLB ( T , getScoreUB ( T ) ) ; return NeedWait ; } const int32_t LB = getScoreLB ( T ) ; const int32_t UB = getScoreUB ( T ) ; if ( ( UB >= ScoreToWait ) && ( ScoreToWait > LB ) ) { if ( T == VM_CNT && hasPendingFlat ( ) ) { NeedWait = CNT_MASK ( T ) ; setScoreLB ( T , getScoreUB ( T ) ) ; } else if ( counterOutOfOrder ( T ) ) { NeedWait = CNT_MASK ( T ) ; setScoreLB ( T , getScoreUB ( T ) ) ;


<s> case BinaryOperator :: Sub : return <STR_LIT> ; case BinaryOperator :: UDiv : return <STR_LIT> ; case BinaryOperator :: SDiv : return <STR_LIT> ; default : return Instruction :: getOpcodeName ( Opcode ) ; }


<s> void DecodePSHUFHWMask ( unsigned NumElts , unsigned Imm , SmallVectorImpl < int > & ShuffleMask ) {

for ( unsigned l = <NUM_LIT> ; l != NumElts ; l += <NUM_LIT> ) {


<s> default : return MatchOperand_NoMatch ; case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: Identifier : break ; } const MCExpr * IdVal ; SMLoc StartLoc = getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return MatchOperand_ParseFail ; if ( auto * CE = dyn_cast < MCConstantExpr > ( IdVal ) ) { if ( StartLoc . getPointer ( ) [ <NUM_LIT> ] != '0' ) {


<s> unsigned <ISA_LIT>ExpandCondsets :: getCondTfrOpcode ( const MachineOperand & SO , bool IfTrue ) { using namespace <ISA_LIT> ; if ( SO . isReg ( ) ) { unsigned PhysR ; RegisterRef RS = SO ; if ( TargetRegisterInfo :: isVirtualRegister ( RS . Reg ) ) { const TargetRegisterClass * VC = MRI -> getRegClass ( RS . Reg ) ; assert ( VC -> begin ( ) != VC -> end ( ) && <STR_LIT> ) ; PhysR = * VC -> begin ( ) ; } else { assert ( TargetRegisterInfo :: isPhysicalRegister ( RS . Reg ) ) ; PhysR = RS . Reg ; } unsigned PhysS = ( RS . Sub == <NUM_LIT> ) ? PhysR : TRI -> getSubReg ( PhysR , RS . Sub ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( PhysS ) ; switch ( TRI -> getRegSizeInBits ( * RC ) ) { case <NUM_LIT> : return IfTrue ? A2_tfrt : A2_tfrf ; case <NUM_LIT> : return IfTrue ? A2_tfrpt : A2_tfrpf ; } llvm_unreachable ( <STR_LIT> ) ; } if ( SO . isImm ( ) || SO . isFPImm ( ) ) return IfTrue ? C2_cmoveit : C2_cmoveif ; llvm_unreachable ( <STR_LIT> ) ;


<s> bool <ISA_LIT>InvISelDAG :: SelectThumbAddrModeRI5S1 ( SDValue N , SDValue & Base , SDValue & Offset ) { return SelectThumbAddrModeRI ( N , Base , Offset , <NUM_LIT> ) ;


<s> return Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> || Tok == <STR_LIT> ;


<s> typedef std :: map < unsigned , RegisterBump > InductionMap ; InductionMap IndMap ; typedef MachineBasicBlock :: instr_iterator instr_iterator ; for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { MachineInstr * Phi = & * I ; for ( unsigned i = <NUM_LIT> , n = Phi -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { if ( Phi -> getOperand ( i + <NUM_LIT> ) . getMBB ( ) != Latch ) continue ; unsigned PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ; MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ; unsigned UpdOpc = DI -> getOpcode ( ) ; bool isAdd = ( UpdOpc == <STR_LIT> || UpdOpc == <STR_LIT> ) ; if ( isAdd ) { unsigned IndReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Opnd2 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V ; if ( MRI -> getVRegDef ( IndReg ) == Phi && checkForImmediate ( Opnd2 , V ) ) { unsigned UpdReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ; } } } } SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineBasicBlock * TB = nullptr , * FB = nullptr ; bool NotAnalyzed = TII -> AnalyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; if ( NotAnalyzed ) return false ; unsigned PredR , PredPos , PredRegFlags ; if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) return false ;

MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ;


<s> FunctionPass * llvm :: createMachineInstPrint ( ) { return new MachineInstPrint ( ) ;


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const DataLayout & DL ) : TargetSelectionDAGInfo ( & DL ) {


<s> } if ( CALL_P ( insn ) || ( TARGET_MIPS16 ? simplejump_p ( insn ) : JUMP_P ( insn ) ) ) length += TARGET_MIPS16 ? <NUM_LIT> : <NUM_LIT> ; if ( ! cfun -> machine -> ignore_hazard_length_p && INSN_P ( insn ) && INSN_CODE ( insn ) >= <NUM_LIT> ) switch ( get_attr_hazard ( insn ) ) { case HAZARD_NONE : break ; case HAZARD_DELAY :


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( unsigned RegNo , SMLoc S , SMLoc E ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Register ) ; Op -> Reg . Num = RegNo ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ;


<s> MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPt , InsertPt -> getDebugLoc ( ) , TII -> get ( Opc ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( Count ) ; if ( ! IsDo ) MIB . add ( Start -> getOperand ( <NUM_LIT> ) ) ; if ( LoLoop . IsTailPredicationLegal ( ) ) { SmallVector < MachineInstr * , <NUM_LIT> > Killed ; SmallVector < MachineInstr * , <NUM_LIT> > Dead ; if ( auto * Def = RDA -> getReachingMIDef ( Start , Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Killed . push_back ( Def ) ; while ( ! Killed . empty ( ) ) { MachineInstr * Def = Killed . back ( ) ; Killed . pop_back ( ) ; Dead . push_back ( Def ) ; for ( auto & MO : Def -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isKill ( ) ) continue ; MachineInstr * Kill = RDA -> getReachingMIDef ( Def , MO . getReg ( ) ) ; if ( Kill && RDA -> getNumUses ( Kill , MO . getReg ( ) ) == <NUM_LIT> ) Killed . push_back ( Kill ) ; } }

for ( auto * MI : Dead ) MI -> eraseFromParent ( ) ;


<s> assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ;

unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) ) << <NUM_LIT> ;


<s> bool <ISA_LIT>AdvSIMDScalar :: runOnMachineFunction ( MachineFunction & mf ) { bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; const TargetMachine & TM = mf . getTarget ( ) ; MRI = & mf . getRegInfo ( ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; for ( MachineFunction :: iterator I = mf . begin ( ) , E = mf . end ( ) ; I != E ; ++ I ) if ( processMachineBasicBlock ( I ) ) Changed = true ; return Changed ;


<s> if ( Inactive . isUndef ( ) ) { LowerToCopyInstrs . push_back ( & MI ) ; } else { unsigned Reg = Inactive . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { for ( MachineInstr & DefMI : MRI -> def_instructions ( Reg ) ) markInstruction ( DefMI , StateWWM , Worklist ) ; } } } SetInactiveInstrs . push_back ( & MI ) ; continue ; } else if ( TII -> isDisableWQM ( MI ) ) { BBI . Needs |= StateExact ; if ( ! ( BBI . InNeeds & StateExact ) ) { BBI . InNeeds |= StateExact ; Worklist . push_back ( & MBB ) ; } GlobalFlags |= StateExact ; III . Disabled = StateWQM | StateWWM ; continue ; } else { if ( Opcode == <STR_LIT> ) { LiveMaskQueries . push_back ( & MI ) ; } else if ( WQMOutputs ) { for ( const MachineOperand & MO : MI . defs ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( Reg ) && TRI -> hasVectorRegisters ( TRI -> getPhysRegClass ( Reg ) ) ) { Flags = StateWQM ; break ; } } } if ( ! Flags ) continue ; } markInstruction ( MI , Flags , Worklist ) ; GlobalFlags |= Flags ; } }


<s> llvm_unreachable ( <STR_LIT> ) ; } const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: Create ( Symbol , Kind , * Ctx ) ; if ( ! Offset ) return MCOperand :: CreateExpr ( MCSym ) ; assert ( Offset > <NUM_LIT> ) ; const MCConstantExpr * OffsetExpr = MCConstantExpr :: Create ( Offset , * Ctx ) ; const MCBinaryExpr * AddExpr = MCBinaryExpr :: CreateAdd ( MCSym , OffsetExpr , * Ctx ) ;

return MCOperand :: CreateExpr ( AddExpr ) ;


<s> static bool lessCore ( const <ISA_LIT>Instr & A , const <ISA_LIT>Instr & B ) { return ( <STR_LIT> ( A . Core , B . Core ) ) ;


<s> O << ( uint32_t ) MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>64Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>64Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>64Target , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>64Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>Target , create<ISA_LIT>MCObjectStreamer ) ; TargetRegistry :: RegisterELFStreamer ( The<ISA_LIT>64Target , create<ISA_LIT>MCObjectStreamer ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , unsigned syntaxVariant ) : MCInstPrinter ( MAI , MII , MRI ) , SyntaxVariant ( syntaxVariant ) {


MCInstLowering . Lower ( MI , TmpInst ) ;


<s> machine_mode mode = GET_MODE ( operand0 ) ; rtx xa , xa2 , dxa , TWO52 , tmp , half , mhalf , one , res , mask ; rtx_code_label * label ; TWO52 = ix86_gen_TWO52 ( mode ) ; res = copy_to_reg ( operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa2 = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , TWO52 , xa2 , <NUM_LIT> , OPTAB_DIRECT ) ; dxa = expand_simple_binop ( mode , MINUS , xa2 , xa , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; half = force_reg ( mode , const_double_from_real_value ( dconsthalf , mode ) ) ; one = expand_simple_binop ( mode , PLUS , half , half , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; mhalf = expand_simple_binop ( mode , MINUS , half , one , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGT , dxa , half , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , tmp , one ) ) ) ; xa2 = expand_simple_binop ( mode , MINUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; tmp = ix86_expand_sse_compare_mask ( UNGE , mhalf , dxa , false ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_AND ( mode , tmp , one ) ) ) ; xa2 = expand_simple_binop ( mode , PLUS , xa2 , tmp , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ;

ix86_sse_copysign_to_positive ( res , xa2 , res , mask ) ;


<s> assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; for ( int i = ( Size - <NUM_LIT> ) * <NUM_LIT> ; i >= <NUM_LIT> ; i -= <NUM_LIT> ) EmitByte ( ( Val >> i ) & <NUM_LIT> , CurByte , OS ) ;


<s> <ISA_LIT>Operand ( KindTy Kind_ , const <ISA_LIT>AsmParser * AsmParser_ ) : Kind ( Kind_ ) , AsmParser ( AsmParser_ ) {


<s> <ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , bool IsLittle ) : MCAsmBackend ( IsLittle ? <STR_LIT> : <STR_LIT> ) , TheTriple ( TT ) , IsLittle ( IsLittle ) {