<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) , Subtarget ( ST ) {


<s> size_t Start = <NUM_LIT> , Next = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( Start , Next ) ; Operands . push_back ( <STR_LIT> ( Mnemonic , NameLoc ) ) ; if ( Next != StringRef :: npos ) { size_t Dot = Name . find ( '.' , Next + <NUM_LIT> ) ; StringRef Format = Name . slice ( Next , Dot ) ; if ( Dot == StringRef :: npos ) Operands . push_back ( <STR_LIT> ( Format , NameLoc ) ) ; else { if ( Name . startswith ( <STR_LIT> ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , NameLoc ) ) ; int Cc = ConvertCcString ( Format ) ; if ( Cc == - <NUM_LIT> ) { return Error ( NameLoc , <STR_LIT> ) ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( MCConstantExpr :: Create ( Cc , getContext ( ) ) , NameLoc , E ) ) ; } else { return parseMathOperation ( Name , NameLoc , Operands ) ; } Format = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( <STR_LIT> ( Format , NameLoc ) ) ; } setFpFormat ( Format ) ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . EatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) {


<s> rtx srcreg = gen_rtx_REG ( Pmode , ret_regs [ fkind ] ) ; emit_move_insn ( srcreg , postinc ) ; } if ( ! crtl -> is_leaf ) all = true ; expand_epilogue_reg_restore ( spreg , all , true ) ; if ( fkind == EXCPT_HANDLER ) emit_insn ( gen_addsi3 ( spreg , spreg , GEN_INT ( <NUM_LIT> ) ) ) ;

emit_jump_insn ( gen_return_internal ( gen_rtx_REG ( Pmode , ret_regs [ fkind ] ) ) ) ;


<s> default : { errs ( ) << <STR_LIT> ; errs ( ) << <STR_LIT> << Opc << <STR_LIT> ; errs ( ) << <STR_LIT> ; Op . getNode ( ) -> dump ( ) ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerLOAD ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG , <ISA_LIT>TM . getSubtargetImpl ( ) ) ; case <STR_LIT> : return LowerConstantFP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( VT == <STR_LIT> ) return LowerI8Math ( Op , DAG , Opc , * this ) ; break ; } case <STR_LIT> :


<s> for ( Clone & C : Clones ) if ( C . OrigF == OrigF && FeaturesNeeded == C . FeatureMask ) return C . NewF ; return nullptr ;


<s> bool Changed = false ; for ( auto * U : F . users ( ) ) { auto * CI = dyn_cast < CallInst > ( U ) ; if ( ! CI ) continue ; Changed |= <ISA_LIT>CommonSubtarget :: get ( TM , F ) . makeLIDRangeMetadata ( CI ) ;


<s> static SDValue LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG , const TargetLowering & TLI ) { EVT VT = Op . getValueType ( ) ; SDValue lhs = Op . getOperand ( <NUM_LIT> ) ; SDValue rhs = Op . getOperand ( <NUM_LIT> ) ; SDValue trueval = Op . getOperand ( <NUM_LIT> ) ; SDValue falseval = Op . getOperand ( <NUM_LIT> ) ; SDValue condition = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue compare = DAG . getNode ( <STR_LIT> , dl , TLI . getSetCCResultType ( Op . getValueType ( ) ) , lhs , rhs , condition ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , falseval , trueval , compare ) ;


<s> SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue NonConstantVal ; SDValue CCOp ; bool SwapSelectOps ;

if ( ! isConditionalZeroOrAllOnes ( Slct . getNode ( ) , AllOnes , CCOp , SwapSelectOps , NonConstantVal , DAG ) ) return SDValue ( ) ;


<s> return __builtin_mve_vmovltq_m_uv8hi ( __arm_vuninitializedq_u32 ( ) , __a , __p ) ;


<s> dbgs ( ) << <STR_LIT> << maxH << <STR_LIT> ; ) ; DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ; initQueues ( TopRoots , BotRoots ) ;


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , <NUM_LIT> ) ;

MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectMOVRELDOffset ( SDValue Index , SDValue & Base , SDValue & Offset ) const { return selectMOVRELOffsetImpl ( Index , Base , Offset , true ) ;


<s> <ISA_LIT>ModuleDAGToDAGISel ( ) : MachineFunctionPass ( ID ) {


<s> return StringRef ( SysReg . Data , SysReg . Length ) ;


<s> const IntrinsicInst * II = dyn_cast < IntrinsicInst > ( I ) ; if ( II && ( II -> getIntrinsicID ( ) == <STR_LIT> || II -> getIntrinsicID ( ) == <STR_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * II << <STR_LIT> ) ; return false ; } return true ;


<s> auto * WasmSym = cast < MCSymbolWasm > ( Printer . getSymbol ( Global ) ) ; if ( <STR_LIT> ( Global -> getAddressSpace ( ) ) && ! WasmSym -> getType ( ) ) { const MachineFunction & MF = * MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const Function & CurrentFunc = MF . getFunction ( ) ; SmallVector < MVT , <NUM_LIT> > VTs ; computeLegalValueVTs ( CurrentFunc , TM , Global -> getValueType ( ) , VTs ) ; if ( VTs . size ( ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; bool Mutable = true ; <STR_LIT> Type = <STR_LIT> ( VTs [ <NUM_LIT> ] ) ; WasmSym -> setType ( <STR_LIT> ) ; WasmSym -> setGlobalType ( <STR_LIT> { uint8_t ( Type ) , Mutable } ) ; } return WasmSym ; } const auto * FuncTy = cast < FunctionType > ( Global -> getValueType ( ) ) ; const MachineFunction & MF = * MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const Function & CurrentFunc = MF . getFunction ( ) ; SmallVector < MVT , <NUM_LIT> > ResultMVTs ; SmallVector < MVT , <NUM_LIT> > ParamMVTs ; const auto * const F = dyn_cast < Function > ( Global ) ; computeSignatureVTs ( FuncTy , F , CurrentFunc , TM , ParamMVTs , ResultMVTs ) ; auto Signature = signatureFromMVTs ( ResultMVTs , ParamMVTs ) ; bool InvokeDetected = false ; auto * WasmSym = Printer . getMCSymbolForFunction ( F , WasmEnableEmException || WasmEnableEmSjLj , Signature . get ( ) , InvokeDetected ) ;

WasmSym -> setSignature ( Signature . get ( ) ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> USItype res = <NUM_LIT> ; while ( den < num && bit && ! ( den & ( <NUM_LIT> << <NUM_LIT> ) ) ) { den <<= <NUM_LIT> ; bit <<= <NUM_LIT> ; } while ( bit ) { if ( num >= den ) { num -= den ; res |= bit ;


<s> for ( SUnit :: succ_iterator I = SU -> Preds . begin ( ) , E = SU -> Preds . end ( ) ; I != E ; ++ I ) {

unsigned PredReadyCycle = I -> getSUnit ( ) -> TopReadyCycle ;


<s> std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( Opcode == Instruction :: Store && Src -> isVectorTy ( ) && Alignment != <NUM_LIT> && Src -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { int AmortizationCost = <NUM_LIT> ; return LT . first * <NUM_LIT> * AmortizationCost ;


<s> fold = error_mark_node ; } switch ( TYPE_MODE ( type0 ) ) { case E_QQmode : id = AVR_BUILTIN_ROUNDHR ; break ; case E_HQmode : id = AVR_BUILTIN_ROUNDR ; break ; case E_SQmode : id = AVR_BUILTIN_ROUNDLR ; break ; case E_DQmode : id = AVR_BUILTIN_ROUNDLLR ; break ; case E_UQQmode : id = AVR_BUILTIN_ROUNDUHR ; break ; case E_UHQmode : id = AVR_BUILTIN_ROUNDUR ; break ; case E_USQmode : id = AVR_BUILTIN_ROUNDULR ; break ; case E_UDQmode : id = AVR_BUILTIN_ROUNDULLR ; break ; case E_HAmode : id = AVR_BUILTIN_ROUNDHK ; break ; case E_SAmode : id = AVR_BUILTIN_ROUNDK ; break ; case E_DAmode : id = AVR_BUILTIN_ROUNDLK ; break ; case E_TAmode : id = AVR_BUILTIN_ROUNDLLK ; break ; case E_UHAmode : id = AVR_BUILTIN_ROUNDUHK ; break ; case E_USAmode : id = AVR_BUILTIN_ROUNDUK ; break ; case E_UDAmode : id = AVR_BUILTIN_ROUNDULK ; break ; case E_UTAmode : id = AVR_BUILTIN_ROUNDULLK ; break ; default : error_at ( loc , <STR_LIT> , <STR_LIT> ) ; fold = error_mark_node ; break ; } fold = targetm . builtin_decl ( id , true ) ; if ( fold != error_mark_node ) fold = build_function_call_vec ( loc , vNULL , fold , & args , NULL ) ; break ; case AVR_BUILTIN_COUNTLSFX : if ( args . length ( ) != <NUM_LIT> ) { error_at ( loc , <STR_LIT> , <STR_LIT> , ( int ) args . length ( ) ) ; fold = error_mark_node ; break ; } type0 = TREE_TYPE ( args [ <NUM_LIT> ] ) ; if ( ! FIXED_POINT_TYPE_P ( type0 ) ) { error_at ( loc , <STR_LIT> , <STR_LIT> ) ; fold = error_mark_node ; } switch ( TYPE_MODE ( type0 ) ) { case E_QQmode : id = AVR_BUILTIN_COUNTLSHR ; break ; case E_HQmode : id = AVR_BUILTIN_COUNTLSR ; break ; case E_SQmode : id = AVR_BUILTIN_COUNTLSLR ; break ; case E_DQmode : id = AVR_BUILTIN_COUNTLSLLR ; break ; case E_UQQmode : id = AVR_BUILTIN_COUNTLSUHR ; break ; case E_UHQmode : id = AVR_BUILTIN_COUNTLSUR ; break ; case E_USQmode : id = AVR_BUILTIN_COUNTLSULR ; break ; case E_UDQmode : id = AVR_BUILTIN_COUNTLSULLR ; break ; case E_HAmode : id = AVR_BUILTIN_COUNTLSHK ; break ; case E_SAmode : id = AVR_BUILTIN_COUNTLSK ; break ; case E_DAmode : id = AVR_BUILTIN_COUNTLSLK ; break ; case E_TAmode : id = AVR_BUILTIN_COUNTLSLLK ; break ; case E_UHAmode : id = AVR_BUILTIN_COUNTLSUHK ; break ; case E_USAmode : id = AVR_BUILTIN_COUNTLSUK ; break ; case E_UDAmode : id = AVR_BUILTIN_COUNTLSULK ; break ; case E_UTAmode : id = AVR_BUILTIN_COUNTLSULLK ; break ; default : error_at ( loc , <STR_LIT> , <STR_LIT> ) ; fold = error_mark_node ; break ; }


<s> MVT VT ; if ( ! isLoadTypeLegal ( AI -> getType ( ) , VT ) ) return <NUM_LIT> ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = TLI . getRegClassFor ( VT ) ;

Register ResultReg = createResultReg ( RC ) ;


<s> bool <ISA_LIT>TargetAsmInfo < BaseTAI > :: LowerToBSwap ( CallInst * CI ) const { if ( CI -> getNumOperands ( ) != <NUM_LIT> || CI -> getType ( ) != CI -> getOperand ( <NUM_LIT> ) -> getType ( ) || ! CI -> getType ( ) -> isInteger ( ) ) return false ; const IntegerType * Ty = dyn_cast < IntegerType > ( CI -> getType ( ) ) ; if ( ! Ty || Ty -> getBitWidth ( ) % <NUM_LIT> != <NUM_LIT> ) return false ;


<s> const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , VK , Ctx ) ; if ( Offset != <NUM_LIT> ) { if ( IsFunc ) report_fatal_error ( <STR_LIT> ) ; if ( IsGlob ) report_fatal_error ( <STR_LIT> ) ; Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ;


<s> if ( mi . definesRegister ( <STR_LIT> ) ) break ; } if ( miI == BB -> end ( ) ) for ( const auto * SBB : BB -> successors ( ) ) if ( SBB -> isLiveIn ( <STR_LIT> ) ) return false ;

SelectItr -> addRegisterKilled ( <STR_LIT> , TRI ) ;


<s> compute_bb_for_insn ( ) ; if ( TARGET_SEH && current_function_has_exception_handlers ( ) ) ix86_seh_fixup_eh_fallthru ( ) ; if ( optimize && optimize_function_for_speed_p ( cfun ) ) { if ( TARGET_SSE2 ) ix86_split_stlf_stall_load ( ) ; if ( TARGET_PAD_SHORT_FUNCTION ) ix86_pad_short_function ( ) ;

else if ( TARGET_PAD_RETURNS ) ix86_pad_returns ( ) ;


<s> void <ISA_LIT>FrameLowering :: restoreWinEHStackPointersInParent ( MachineFunction & MF ) const { bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( MF . getFunction ( ) . getPersonalityFn ( ) ) ) ; for ( MachineBasicBlock & MBB : MF ) {

bool NeedsRestore = MBB . isEHPad ( ) && ! MBB . isEHFuncletEntry ( ) ;


<s> MachineFunctionPass * llvm :: create<ISA_LIT>PrologEpilogPass ( ) { return new <ISA_LIT>PrologEpilogPass ( ) ;


<s> return ; } Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getAddrModeSBit ( MI , MCID ) ; unsigned NumDefs = MCID . getNumDefs ( ) ; unsigned OpIdx = <NUM_LIT> ; if ( NumDefs ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; else if ( ImplicitRd ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRd ) << <STR_LIT> ) ; if ( MCID . Opcode == <STR_LIT> ) { unsigned Lo16 = getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) ; Binary |= Lo16 & <NUM_LIT> ; Binary |= ( ( Lo16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( MCID . Opcode == <STR_LIT> ) { unsigned Hi16 = ( getMovi32Value ( MI , MI . getOperand ( OpIdx ) , <STR_LIT> ) >> <NUM_LIT> ) ; Binary |= Hi16 & <NUM_LIT> ; Binary |= ( ( Hi16 >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { uint32_t v = ~ MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int32_t lsb = CountTrailingZeros_32 ( v ) ; int32_t msb = ( <NUM_LIT> - CountLeadingZeros_32 ( v ) ) - <NUM_LIT> ; Binary |= ( msb & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } else if ( ( MCID . Opcode == <STR_LIT> ) || ( MCID . Opcode == <STR_LIT> ) ) { Binary |= getMachineOpValue ( MI , OpIdx ++ ) ; uint32_t lsb = MI . getOperand ( OpIdx ++ ) . getImm ( ) ; uint32_t widthm1 = MI . getOperand ( OpIdx ++ ) . getImm ( ) - <NUM_LIT> ; Binary |= ( widthm1 & <NUM_LIT> ) << <NUM_LIT> ; Binary |= ( lsb & <NUM_LIT> ) << <NUM_LIT> ; emitWordLE ( Binary ) ; return ; } if ( MCID . getOperandConstraint ( OpIdx , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; bool isUnary = MCID . TSFlags & <STR_LIT> ; if ( ! isUnary ) { if ( ImplicitRn ) Binary |= ( get<ISA_LIT>RegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else { Binary |= getMachineOpValue ( MI , OpIdx ) << <STR_LIT> ; ++ OpIdx ; } }

const MachineOperand & MO = MI . getOperand ( OpIdx ) ;


<s> <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCInstLowering ( OutContext , * this ) , SM ( * this ) , <ISA_LIT>FI ( nullptr ) {


<s> compute_bb_for_insn ( ) ; df_clear_flags ( DF_LR_RUN_DCE ) ; df_analyze ( ) ; thread_prologue_and_epilogue_insns ( ) ; qiregs . n_allocated = <NUM_LIT> ; hiregs . n_allocated = <NUM_LIT> ; siregs . n_allocated = <NUM_LIT> ; diregs . n_allocated = <NUM_LIT> ; qiregs . mode = QImode ; hiregs . mode = HImode ; siregs . mode = SImode ; diregs . mode = DImode ; for ( insn = get_insns ( ) ; insn ; insn = next ) { next = NEXT_INSN ( insn ) ; if ( ! NONDEBUG_INSN_P ( insn ) || asm_noperands ( insn ) >= <NUM_LIT> || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) continue ; qiregs . n_in_use = <NUM_LIT> ; hiregs . n_in_use = <NUM_LIT> ; siregs . n_in_use = <NUM_LIT> ; diregs . n_in_use = <NUM_LIT> ; extract_insn ( insn ) ; enum attr_subregs_ok s_ok = get_attr_subregs_ok ( insn ) ; for ( int i = <NUM_LIT> ; i < recog_data . n_operands ; i ++ ) { rtx op = recog_data . operand [ i ] ; if ( GET_CODE ( op ) != SUBREG ) continue ; rtx inner = SUBREG_REG ( op ) ; machine_mode outer_mode = GET_MODE ( op ) ; machine_mode inner_mode = GET_MODE ( inner ) ; gcc_assert ( s_ok ) ; if ( s_ok && ( GET_MODE_PRECISION ( inner_mode ) >= GET_MODE_PRECISION ( outer_mode ) ) ) continue ; gcc_assert ( SCALAR_INT_MODE_P ( outer_mode ) ) ; struct reg_replace * r = ( outer_mode == QImode ? & qiregs : outer_mode == HImode ? & hiregs : outer_mode == SImode ? & siregs : & diregs ) ; rtx new_reg = get_replacement ( r ) ; if ( recog_data . operand_type [ i ] != OP_OUT ) {


<s> const MachineBasicBlock & B = * MF . getBlockNumbered ( Edge . second ) ; MachineBasicBlock :: const_iterator It = B . begin ( ) , End = B . end ( ) ; while ( It != End && It -> isPHI ( ) ) { const MachineInstr * PI = & * It ++ ; InstrExec . insert ( PI ) ; visitPHI ( PI ) ; } if ( BlockScanned [ Edge . second ] ) continue ; BlockScanned [ Edge . second ] = true ; while ( It != End && ! It -> isBranch ( ) ) { const MachineInstr * MI = & * It ++ ; InstrExec . insert ( MI ) ; visitNonBranch ( MI ) ; } if ( It == End ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) && B . isSuccessor ( Next ) ) { int ThisN = B . getNumber ( ) ; int NextN = Next -> getNumber ( ) ; FlowQ . push ( CFGEdge ( ThisN , NextN ) ) ; } } else { visitBranchesFrom ( It ) ; } } if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( CellMapType :: iterator I = Map . begin ( ) , E = Map . end ( ) ; I != E ; ++ I ) dbgs ( ) << PrintReg ( I -> first , & ME . TRI ) << <STR_LIT> << I -> second << <STR_LIT> ; }


<s> auto * SrcVTy = dyn_cast < FixedVectorType > ( SrcTy ) ; if ( ! SrcVTy ) return getMemoryOpCost ( Opcode , SrcTy , Alignment , AddressSpace , CostKind ) ; unsigned NumElem = SrcVTy -> getNumElements ( ) ; auto * MaskTy = FixedVectorType :: get ( Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , NumElem ) ; if ( ( IsLoad && ! isLegalMaskedLoad ( SrcVTy , Alignment ) ) || ( IsStore && ! isLegalMaskedStore ( SrcVTy , Alignment ) ) ) { APInt DemandedElts = APInt :: getAllOnes ( NumElem ) ; InstructionCost MaskSplitCost = getScalarizationOverhead ( MaskTy , DemandedElts , false , true ) ; InstructionCost ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) ; InstructionCost BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; InstructionCost MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; InstructionCost ValueSplitCost = getScalarizationOverhead ( SrcVTy , DemandedElts , IsLoad , IsStore ) ; InstructionCost MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , Alignment , AddressSpace , CostKind ) ; return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ;


<s> if ( isInt < <NUM_LIT> > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , nullptr ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ; }


<s> return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>AsmParser :: validatetSTMRegList ( const MCInst & Inst , const OperandVector & Operands , unsigned ListNo ) { const <ISA_LIT>Operand & Op = static_cast < const <ISA_LIT>Operand & > ( * Operands [ ListNo ] ) ; bool HasWritebackToken = Op . isToken ( ) && Op . getToken ( ) == <STR_LIT> ; bool ListContainsSP = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; bool ListContainsPC = listContainsReg ( Inst , ListNo , <STR_LIT> ) ; if ( ListContainsSP && ListContainsPC ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( ListContainsSP ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; else if ( ListContainsPC ) return Error ( Operands [ ListNo + HasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ;


<s> static MCSymbolizer * create<ISA_LIT>Symbolizer ( const Triple & , LLVMOpInfoCallback , LLVMSymbolLookupCallback , void * DisInfo , MCContext * Ctx , std :: unique_ptr < MCRelocationInfo > && RelInfo ) {

return new <ISA_LIT>Symbolizer ( * Ctx , std :: move ( RelInfo ) , DisInfo ) ;


<s> Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( ShadowRegI8 ) ) ; const MCExpr * Disp = MCConstantExpr :: Create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; EmitInstruction ( Out , Inst ) ; } EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI8 ) . addReg ( ShadowRegI8 ) ) ; MCSymbol * DoneSym = Ctx . CreateTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: Create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( AddressRegI32 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( ScratchRegI32 ) . addImm ( <NUM_LIT> ) ) ;


<s> } assert ( G -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! hasDefinedInitializer ( GV ) ) { unsigned Offset = MFI -> allocateLDSGlobal ( DL , * cast < GlobalVariable > ( GV ) ) ; return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ; } } const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ;

DAG . getContext ( ) -> diagnose ( BadInit ) ;


<s> if ( ValVT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , Dl , ValLoc , ValArg , DAG . getIntPtrConstant ( <NUM_LIT> , Dl ) ) ; if ( ( ValVT == <STR_LIT> && ( ValLoc == <STR_LIT> || ValLoc == <STR_LIT> ) ) || ( ValVT == <STR_LIT> && ( ValLoc == <STR_LIT> || ValLoc == <STR_LIT> ) ) ) { EVT TempValLoc = ValVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue ValToCopy = DAG . getBitcast ( TempValLoc , ValArg ) ; if ( ValLoc == <STR_LIT> ) ValToCopy = DAG . getNode ( <STR_LIT> , Dl , ValLoc , ValToCopy ) ; return ValToCopy ;


<s> auto IsHazardFn = [ TII ] ( const MachineInstr & I ) { if ( ! <ISA_LIT>InstrInfo :: isMIMG ( I ) ) return false ; const <STR_LIT> * Info = <STR_LIT> ( I . getOpcode ( ) ) ; return Info -> MIMGEncoding == <STR_LIT> && TII -> getInstSizeInBytes ( I ) >= <NUM_LIT> ; } ; return NSAtoVMEMWaitStates - getWaitStatesSince ( IsHazardFn , <NUM_LIT> ) ;


<s> LaneVGPR = TRI -> findUnusedRegister ( MRI , & <STR_LIT> , MF ) ; if ( LaneVGPR == <STR_LIT> ) { SGPRToVGPRSpills . erase ( FI ) ; NumVGPRSpillLanes -= I ; return false ; } SpillVGPRs . push_back ( LaneVGPR ) ; for ( MachineBasicBlock & BB : MF ) BB . addLiveIn ( LaneVGPR ) ; } else { LaneVGPR = SpillVGPRs . back ( ) ; } SpillLanes . push_back ( SpilledReg ( LaneVGPR , VGPRIndex ) ) ; }


<s> CONSTEXPR multi_vector_function ( unsigned int vectors_per_tuple ) : m_vectors_per_tuple ( vectors_per_tuple ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerCONCAT_VECTORS ( SDValue Op , SelectionDAG & DAG ) const { SDNode * Node = Op . getNode ( ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumOperands = Node -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) { SDValue SubOp = Node -> getOperand ( i ) ; EVT VVT = SubOp . getNode ( ) -> getValueType ( <NUM_LIT> ) ; EVT EltVT = VVT . getVectorElementType ( ) ; unsigned NumSubElem = VVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumSubElem ; ++ j ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SubOp , DAG . getIntPtrConstant ( j ) ) ) ; } } return DAG . getNode ( <STR_LIT> , dl , Node -> getValueType ( <NUM_LIT> ) , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ;


<s> Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = F . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( * F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ;

Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ;


<s> const char * str2 ; str2 = targetm . strip_name_encoding ( str ) ; if ( str2 [ <NUM_LIT> ] != '.' ) fputs ( user_label_prefix , file ) ; fputs ( str2 , file ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; std :: string LowerID = Tok . getString ( ) . lower ( ) ; <STR_LIT> ShOp = StringSwitch < <STR_LIT> > ( LowerID ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( ShOp == <STR_LIT> ) return MatchOperand_NoMatch ; SMLoc S = Tok . getLoc ( ) ; Parser . Lex ( ) ;

bool Hash = getLexer ( ) . is ( AsmToken :: Hash ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : <ISA_LIT>InstPrinterBase ( MAI , MII , MRI ) {


<s> while ( ! WorkStack . empty ( ) ) { APInt Val = WorkStack . pop_back_val ( ) ; if ( Val == <NUM_LIT> || Val == <NUM_LIT> ) continue ; if ( Steps >= MaxSteps ) return false ; if ( Val . isPowerOf2 ( ) ) { ++ Steps ; continue ; } APInt Floor = APInt ( BitWidth , <NUM_LIT> ) << Val . logBase2 ( ) ; APInt Ceil = Val . isNegative ( ) ? APInt ( BitWidth , <NUM_LIT> ) : APInt ( BitWidth , <NUM_LIT> ) << C . ceilLogBase2 ( ) ; if ( ( Val - Floor ) . ule ( Ceil - Val ) ) { WorkStack . push_back ( Floor ) ; WorkStack . push_back ( Val - Floor ) ; } else { WorkStack . push_back ( Ceil ) ; WorkStack . push_back ( Ceil - Val ) ; } ++ Steps ; } unsigned RegisterSize = DAG . getTargetLoweringInfo ( ) . getRegisterType ( * DAG . getContext ( ) , VT ) . getSizeInBits ( ) ; Steps *= ( VT . getSizeInBits ( ) != RegisterSize ) * <NUM_LIT> ; if ( Steps > <NUM_LIT> ) return false ; return true ;


<s> if ( TBBI == analyzedBlocks . end ( ) || FBBI == analyzedBlocks . end ( ) ) return ; unsigned headCount = MPI ? MPI -> getExecutionCount ( head . MBB ) : <NUM_LIT> ; BBInfo infoTBB = TBBI -> second ; BBInfo infoFBB = FBBI -> second ; if ( infoTBB . MBB -> isSuccessor ( infoFBB . MBB ) || infoFBB . MBB -> isSuccessor ( infoTBB . MBB ) ) { if ( infoTBB . MBB -> isSuccessor ( infoFBB . MBB ) ) { BBInfo tmp = infoTBB ; infoTBB = infoFBB ; infoFBB = tmp ; } if ( ! ( canPredicateBlock ( infoFBB ) && canMergeBlock ( infoTBB , head ) ) ) return ; unsigned maxNumSideEntries = <NUM_LIT> + ( infoFBB . MBB -> pred_size ( ) == <NUM_LIT> ) ; if ( infoTBB . MBB -> pred_size ( ) > maxNumSideEntries ) return ; candidateMap . insert ( std :: make_pair ( headCount , IfConvertible ( IF_TRIANGLE , head , infoTBB , infoFBB ) ) ) ; } else { MachineBasicBlock * tailMBB = getCommonSuccessor ( * infoTBB . MBB , * infoFBB . MBB ) ; const bool canConvertTBB = canPredicateBlock ( infoTBB ) && canMergeBlock ( infoTBB , head ) ; const bool canConvertFBB = canPredicateBlock ( infoFBB ) && canMergeBlock ( infoFBB , head ) ; if ( ! canConvertTBB && ! canConvertFBB ) return ; if ( ! tailMBB ) { candidateMap . insert ( std :: make_pair ( headCount , IfConvertible ( IF_OPEN , head , infoTBB , infoFBB ) ) ) ; } else { if ( ! canConvertTBB || ! canConvertFBB ) return ;

std :: map < MachineBasicBlock * , BBInfo > :: iterator tailMBBI = analyzedBlocks . find ( tailMBB ) ;


<s> if ( Count & <NUM_LIT> ) OW -> Write8 ( <NUM_LIT> ) ; return true ; } const uint32_t nopEncoding = hasNOP ( ) ? <ISA_LIT>v6T2_NopEncoding : <ISA_LIT>v4_NopEncoding ; uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( nopEncoding ) ; switch ( Count % <NUM_LIT> ) { default : break ; case <NUM_LIT> : OW -> Write8 ( <NUM_LIT> ) ; break ; case <NUM_LIT> : OW -> Write16 ( <NUM_LIT> ) ; break ; case <NUM_LIT> : OW -> Write16 ( <NUM_LIT> ) ; OW -> Write8 ( <NUM_LIT> ) ; break ; } return true ;


<s> return ( mode == SImode || ( TARGET_64BIT && mode == DImode ) ) ;


<s> static SDValue canonicalizeBitSelect ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) || ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue N0 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; bool UseVPTERNLOG = ( Subtarget . hasAVX512 ( ) && VT . is512BitVector ( ) ) || Subtarget . hasVLX ( ) ; if ( ! ( Subtarget . hasXOP ( ) || UseVPTERNLOG || ! N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) || ! N1 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) return SDValue ( ) ;


<s> Value * Ptr = Constant :: getNullValue ( Subtarget -> is64Bit ( ) ? Type :: getInt8PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) : Type :: getInt32PtrTy ( * DAG . getContext ( ) , <NUM_LIT> ) ) ; SDValue TlsArray = Subtarget -> is64Bit ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : ( Subtarget -> isTargetWindowsGNU ( ) ? DAG . getIntPtrConstant ( <NUM_LIT> ) : DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ) ; SDValue ThreadPointer = DAG . getLoad ( getPointerTy ( ) , dl , Chain , TlsArray , MachinePointerInfo ( Ptr ) , false , false , false , <NUM_LIT> ) ; SDValue IDX = DAG . getExternalSymbol ( <STR_LIT> , getPointerTy ( ) ) ; if ( Subtarget -> is64Bit ( ) ) IDX = DAG . getExtLoad ( <STR_LIT> , dl , getPointerTy ( ) , Chain , IDX , MachinePointerInfo ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; else IDX = DAG . getLoad ( getPointerTy ( ) , dl , Chain , IDX , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue Scale = DAG . getConstant ( Log2_64_Ceil ( TD -> getPointerSize ( ) ) , getPointerTy ( ) ) ; IDX = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , IDX , Scale ) ; SDValue res = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , ThreadPointer , IDX ) ; res = DAG . getLoad ( getPointerTy ( ) , dl , Chain , res , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , <STR_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , TGA ) ;

return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , res , Offset ) ;


<s> LowerVAARG ( SDValue Op , SelectionDAG & DAG ) const { llvm_unreachable ( <STR_LIT> ) ; SDNode * Node = Op . getNode ( ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; const Value * V = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ;

SDValue VAList = DAG . getLoad ( getPointerTy ( ) , dl , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , MachinePointerInfo ( V ) , false , false , false , <NUM_LIT> ) ;


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;

return Infos [ Kind - FirstTargetFixupKind ] ;


<s> return ( bool ) ( get_prefer_mask_policy ( ) & <NUM_LIT> || ( get_prefer_mask_policy ( ) >> <NUM_LIT> & <NUM_LIT> ) ) ;


<s> bool sopkIsZext ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> explicit FrepLoop ( MachineLoop * ML ) {


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> <ISA_LIT>AddressSanitizer ( const MCSubtargetInfo & STI ) : <ISA_LIT>AsmInstrumentation ( STI ) , RepPrefix ( false ) {


<s> SDNode * LD = N -> getOperand ( LoadIdx ) . getNode ( ) ; if ( LD -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; LoadSDNode * LoadSDN = cast < LoadSDNode > ( LD ) ; EVT MemVT = LoadSDN -> getMemoryVT ( ) ; if ( MemVT != VT . getVectorElementType ( ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = LD -> use_begin ( ) , UE = LD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == <NUM_LIT> ) continue ; if ( * UI != N ) return SDValue ( ) ; } SDValue Addr = LD -> getOperand ( <NUM_LIT> ) ; SDValue Vector = N -> getOperand ( <NUM_LIT> ) ; for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || UI . getUse ( ) . getResNo ( ) != Addr . getResNo ( ) ) continue ; if ( User -> isPredecessorOf ( LD ) || LD -> isPredecessorOf ( User ) ) continue ; if ( User -> isPredecessorOf ( Vector . getNode ( ) ) ) continue ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint32_t IncVal = CInc -> getZExtValue ( ) ; unsigned NumBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( IncVal != NumBytes ) continue ; Inc = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } if ( LoadSDN -> isPredecessorOf ( Vector . getNode ( ) ) ) continue ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LD -> getOperand ( <NUM_LIT> ) ) ; if ( IsLaneOp ) { Ops . push_back ( Vector ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; } Ops . push_back ( Addr ) ; Ops . push_back ( Inc ) ; EVT Tys [ <NUM_LIT> ] = { VT , <STR_LIT> , <STR_LIT> } ; SDVTList SDTys = DAG . getVTList ( Tys ) ; unsigned NewOp = IsLaneOp ? <STR_LIT> : <STR_LIT> ; SDValue UpdN = DAG . getMemIntrinsicNode ( NewOp , SDLoc ( N ) , SDTys , Ops , MemVT , LoadSDN -> getMemOperand ( ) ) ;


<s> if ( ! MI -> isFullCopy ( ) ) return MI ;

if ( ! TRI -> isVirtualRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return NULL ;


<s> <ISA_LIT>EL_AsmBackend ( const Target & T , Triple :: OSType _OSType ) : <ISA_LIT>AsmBackend ( T ) , OSType ( _OSType ) {


<s> assert ( ! SrcReg2 && <STR_LIT> ) ; bool IsLogical = ( Compare . getDesc ( ) . TSFlags & <STR_LIT> ) != <NUM_LIT> ;

return Value == <NUM_LIT> && ! IsLogical && removeIPMBasedCompare ( Compare , SrcReg , MRI , & RI ) ;


<s> bool LEAusesAG ( ) const { return LEAUsesAG ;


<s> if ( ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( In . getOperand ( <NUM_LIT> ) ) ) {

if ( Idx -> isZero ( ) && In . getValueSizeInBits ( ) <= <NUM_LIT> ) return In . getOperand ( <NUM_LIT> ) ;


<s> if ( ALTIVEC_OR_VSX_VECTOR_MODE ( mode2 ) ) return false ; if ( SCALAR_FLOAT_MODE_P ( mode1 ) ) return SCALAR_FLOAT_MODE_P ( mode2 ) ; if ( SCALAR_FLOAT_MODE_P ( mode2 ) ) return false ;


<s> Op -> Reg . RegNum = RegNum ; Op -> StartLoc = Start ; Op -> EndLoc = End ; return Op ;


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false , false ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { const MachineFunction & MF = * MBB . getParent ( ) ; assert ( MF . getFrameInfo ( ) . getObjectSize ( FrameIndex ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Opc = getStoreRegOpcode ( SrcReg , RC , TRI , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ;

addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIndex ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> unsigned Flag = ELF :: EF_CPU0_NOREORDER ; Flag |= ELF :: EF_CPU0_ARCH_32R2 ;


<s> unsigned <ISA_LIT>FastISel :: emitLogicalOp ( unsigned ISDOpc , MVT RetVT , const Value * LHS , const Value * RHS ) { if ( isa < ConstantInt > ( LHS ) && ! isa < ConstantInt > ( RHS ) ) std :: swap ( LHS , RHS ) ; unsigned Opc ; switch ( ISDOpc ) { case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Register LHSReg = getRegForValue ( LHS ) ; if ( ! LHSReg ) return <NUM_LIT> ; unsigned RHSReg ;

if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) ) RHSReg = materializeInt ( C , <STR_LIT> ) ;


for ( first_reg = <NUM_LIT> ; first_reg <= <NUM_LIT> ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ;


<s> getT2Imm8s4OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {

int32_t Imm8 = MI . getOperand ( OpIdx ) . getImm ( ) ;


<s> const MachineOperand & MO1 = MI -> getOperand ( OpNo ) ; const MachineOperand & MO2 = MI -> getOperand ( OpNo + <NUM_LIT> ) ;

O << getRegisterName ( MO1 . getReg ( ) ) << <STR_LIT> << MO2 . getImm ( ) ;


<s> const PtrToIntOperator * SubRHS = dyn_cast < PtrToIntOperator > ( Sub -> getOperand ( <NUM_LIT> ) ) ; if ( ! SubLHS || ! SubRHS ) return nullptr ; if ( SubLHS -> getPointerAddressSpace ( ) != <NUM_LIT> || SubRHS -> getPointerAddressSpace ( ) != <NUM_LIT> ) return nullptr ; const auto * GOLHS = dyn_cast < GlobalObject > ( SubLHS -> getPointerOperand ( ) ) ; const auto * GVRHS = dyn_cast < GlobalVariable > ( SubRHS -> getPointerOperand ( ) ) ;

if ( ! GOLHS || ! GVRHS ) return nullptr ;


<s> rtx pat ; rtx op0 = nds32_read_argument ( exp , <NUM_LIT> ) ; rtx op1 = nds32_read_argument ( exp , <NUM_LIT> ) ; int op0_num = return_p ? <NUM_LIT> : <NUM_LIT> ; int op1_num = return_p ? <NUM_LIT> : <NUM_LIT> ; if ( return_p ) target = nds32_legitimize_target ( icode , target ) ; op0 = nds32_legitimize_argument ( icode , op0_num , op0 ) ; op1 = nds32_legitimize_argument ( icode , op1_num , op1 ) ; if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( op0 , op1 ) ;


<s> bool IsNonEntryFunc = ! <STR_LIT> ( F -> getCallingConv ( ) ) ; auto & InfoCache = static_cast < <ISA_LIT>InformationCache & > ( A . getInfoCache ( ) ) ; bool NeedsQueuePtr = false ; auto CheckAddrSpaceCasts = [ & ] ( Instruction & I ) { unsigned SrcAS = static_cast < AddrSpaceCastInst & > ( I ) . getSrcAddressSpace ( ) ; if ( castRequiresQueuePtr ( SrcAS ) ) { NeedsQueuePtr = true ; return false ; } return true ; } ; bool HasApertureRegs = InfoCache . hasApertureRegs ( * F ) ; if ( ! HasApertureRegs ) { bool UsedAssumedInformation = false ; A . checkForAllInstructions ( CheckAddrSpaceCasts , * this , { Instruction :: AddrSpaceCast } , UsedAssumedInformation ) ; } if ( NeedsQueuePtr ) return true ;

if ( ! IsNonEntryFunc && HasApertureRegs ) return false ;


<s> MVT VT ; if ( ! isTypeSupported ( I -> getType ( ) , VT ) ) return false ; unsigned CondMovOpc ; const TargetRegisterClass * RC ; if ( VT . isInteger ( ) && ! VT . isVector ( ) && VT . getSizeInBits ( ) <= <NUM_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) { CondMovOpc = <STR_LIT> ; RC = & <STR_LIT> ; } else if ( VT == <STR_LIT> ) {


<s> int FI = MFI . CreateFixedObject ( FrameObjSize , FrameObjOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrTy ) ; InVals . push_back ( FIN ) ; if ( ! ByVal . NumRegs ) return ; MVT RegTy = <STR_LIT> ( CC . regSize ( ) * <NUM_LIT> ) ; const TargetRegisterClass * RC = getRegClassFor ( RegTy ) ; for ( unsigned I = <NUM_LIT> ; I < ByVal . NumRegs ; ++ I ) { unsigned ArgReg = ByValArgRegs [ ByVal . FirstIdx + I ] ; unsigned VReg = addLiveIn ( MF , ArgReg , RC ) ; unsigned Offset = I * CC . regSize ( ) ; SDValue StorePtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , FIN , DAG . getConstant ( Offset , DL , PtrTy ) ) ; SDValue Store = DAG . getStore ( Chain , DL , DAG . getRegister ( VReg , RegTy ) , StorePtr , MachinePointerInfo ( FuncArg , Offset ) ) ;


<s> EVT VT = Op . getValueType ( ) ; APInt Demanded = APInt :: getLowBitsSet ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , true , true ) ; if ( TLI . SimplifyDemandedBits ( Node24 , OpIdx , Demanded , DCI , TLO ) ) return true ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; int vvvv ; if ( insn -> vectorExtensionType == TYPE_EVEX ) vvvv = ( v2FromEVEX4of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) << <NUM_LIT> | vvvvFromEVEX3of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) vvvv = vvvvFromVEX3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) vvvv = vvvvFromVEX2of2 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else if ( insn -> vectorExtensionType == TYPE_XOP ) vvvv = vvvvFromXOP3of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ; else return - <NUM_LIT> ; if ( insn -> mode != MODE_64BIT ) vvvv &= <NUM_LIT> ; insn -> vvvv = static_cast < Reg > ( vvvv ) ;


<s> NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] ; if ( isZeroOrOneOrUndef ( Mask [ <NUM_LIT> ] ) && isZeroOrOneOrUndef ( Mask [ <NUM_LIT> ] ) ) return Src0 ; assert ( NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == - <NUM_LIT> ) ; assert ( NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == <NUM_LIT> || NewMask [ <NUM_LIT> ] == - <NUM_LIT> ) ; NewMask [ <NUM_LIT> ] = NewMask [ <NUM_LIT> ] == - <NUM_LIT> ? - <NUM_LIT> : NewMask [ <NUM_LIT> ] - <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerVAARG ( SDValue Op , SelectionDAG & DAG , int VarArgsFrameIndex , int VarArgsStackOffset , unsigned VarArgsNumGPR , unsigned VarArgsNumFPR , const <ISA_LIT>Subtarget & Subtarget ) { assert ( <NUM_LIT> && <STR_LIT> ) ; return SDValue ( ) ;


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { if ( ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) addPass ( createGlobalMergePass ( TM , <NUM_LIT> ) ) ; return false ;


<s> c = ia64_safe_itanium_class ( next ) ; if ( ( c == ITANIUM_CLASS_ST || c == ITANIUM_CLASS_STF ) && ia64_st_address_bypass_p ( insn , next ) ) { has_mem_op_consumer_p = true ; break ; } else if ( ( c == ITANIUM_CLASS_LD || c == ITANIUM_CLASS_FLD || c == ITANIUM_CLASS_FLDP ) && ia64_ld_address_bypass_p ( insn , next ) ) { has_mem_op_consumer_p = true ; break ; }


<s> default : return <ISA_LIT>TargetLowering :: LowerOperation ( Op , DAG ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : { SDValue Result = LowerLOAD ( Op , DAG ) ; assert ( ( ! Result . getNode ( ) || Result . getNode ( ) -> getNumValues ( ) == <NUM_LIT> ) && <STR_LIT> ) ; return Result ; } case <STR_LIT> :


<s> return __builtin_loongson_paddd_u ( s , t ) ;


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= expandMI ( MBB , MBBI , NMBBI ) ; MBBI = NMBBI ; } MBB . sortUniqueLiveIns ( ) ; return Modified ;


<s> if ( CC == CallingConv :: <ISA_LIT>_KERNEL || CC == CallingConv :: SPIR_KERNEL ) { if ( ! F . arg_empty ( ) ) KernargSegmentPtr = true ; WorkGroupIDX = true ; WorkItemIDX = true ; } else if ( CC == CallingConv :: <ISA_LIT>_PS ) { P<ISA_LIT>nputAddr = <STR_LIT> ( F ) ; } if ( ! isEntryFunction ( ) ) { ScratchRSrcReg = <STR_LIT> ; ScratchWaveOffsetReg = <STR_LIT> ; FrameOffsetReg = <STR_LIT> ; StackPtrOffsetReg = <STR_LIT> ; ArgInfo . PrivateSegmentBuffer = ArgDescriptor :: createRegister ( ScratchRSrcReg ) ; ArgInfo . PrivateSegmentWaveByteOffset = ArgDescriptor :: createRegister ( ScratchWaveOffsetReg ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) ImplicitArgPtr = true ; } else { if ( F . hasFnAttribute ( <STR_LIT> ) ) { KernargSegmentPtr = true ; MaxKernArgAlign = std :: max ( ST . getAlignmentForImplicitArgPtr ( ) , MaxKernArgAlign ) ; } } if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDX = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDY = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDZ = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDX = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDY = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDZ = true ; const MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; bool HasStackObjects = FrameInfo . hasStackObjects ( ) ; if ( isEntryFunction ( ) ) { if ( WorkItemIDZ ) WorkItemIDY = true ; PrivateSegmentWaveByteOffset = true ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 && ( CC == CallingConv :: <ISA_LIT>_HS || CC == CallingConv :: <ISA_LIT>_GS ) ) ArgInfo . PrivateSegmentWaveByteOffset = ArgDescriptor :: createRegister ( <STR_LIT> ) ;


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; if ( RC == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIdx ) . addReg ( <STR_LIT> ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIdx ) . addReg ( <STR_LIT> ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIdx ) . addReg ( <STR_LIT> ) ; else abort ( ) ;


<s> static DecodeStatus DecodeUImm6Lsl2 ( MCInst & Inst , unsigned Value , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( Value << <NUM_LIT> ) ) ; return MCDisassembler :: Success ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: fixOneOperandFPComparison ( const MCInst & MI , unsigned EncodedValue , const MCSubtargetInfo & STI ) const {

EncodedValue &= ~ ( <NUM_LIT> << <NUM_LIT> ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: riscv32 > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;

RegisterTarget < Triple :: riscv64 > Y ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> return ( __m256i ) __builtin_ia32_pmovsxwq256 ( ( __v8hi ) __X ) ;


<s> const TargetRegisterClass * <ISA_LIT>SERegisterInfo :: intRegClass ( unsigned Size ) const {

if ( Size == <NUM_LIT> ) return & <STR_LIT> ;


<s> assert ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( DestReg ) && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << TargetMBB . getNumber ( ) << <STR_LIT> ) ; for ( auto & Use : MI . uses ( ) ) { if ( Use . isReg ( ) && Register :: isVirtualRegister ( Use . getReg ( ) ) ) { MachineInstr * DefInst = MRI -> getVRegDef ( Use . getReg ( ) ) ; if ( DefInst -> isPHI ( ) && DefInst -> getParent ( ) == MI . getParent ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ;


<s> bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! R . isVirtual ( ) ) continue ; if ( ! isPredicate ( R ) ) continue ; for ( auto U = MRI -> use_begin ( R ) ; U != MRI -> use_end ( ) ; ++ U ) if ( U -> getParent ( ) -> isPHI ( ) ) return false ; }


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( Subtarget . hasStdExtF ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;

for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , <STR_LIT> , Expand ) ;


<s> if ( Mode == OperandMode_NSA && trySkipToken ( AsmToken :: LBrac ) ) { unsigned Prefix = Operands . size ( ) ; for ( ; ; ) { auto Loc = getLoc ( ) ; ResTy = parseReg ( Operands ) ; if ( ResTy == MatchOperand_NoMatch ) Error ( Loc , <STR_LIT> ) ; if ( ResTy != MatchOperand_Success ) return MatchOperand_ParseFail ; RBraceLoc = getLoc ( ) ; if ( trySkipToken ( AsmToken :: RBrac ) ) break ; if ( ! skipToken ( AsmToken :: Comma , <STR_LIT> ) ) { return MatchOperand_ParseFail ; }


<s> SimpleShape ( ) : Shape ( SK_Simple ) , Inner ( nullptr ) {


<s> Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( Hi ) ) ; } if ( ! Shift ) return Result ; if ( Imm ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Shift ) , getI32Imm ( <NUM_LIT> - Shift ) ) ; } if ( ( Hi = ( Remainder >> <NUM_LIT> ) & <NUM_LIT> ) ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Hi ) ) ; } if ( ( Lo = Remainder & <NUM_LIT> ) ) {

Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Lo ) ) ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> <ISA_LIT>Operand ( const <ISA_LIT>Operand & o ) : MCParsedAsmOperand ( ) {


<s> ArrayRef < int > PermMask = SVOp -> getMask ( ) ; unsigned PFIndexes [ <NUM_LIT> ] ; bool isFourElementShuffle = true ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> && isFourElementShuffle ; ++ i ) { unsigned EltNo = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j != <NUM_LIT> ; ++ j ) { if ( PermMask [ i * <NUM_LIT> + j ] < <NUM_LIT> ) continue ; unsigned ByteSource = PermMask [ i * <NUM_LIT> + j ] ; if ( ( ByteSource & <NUM_LIT> ) != j ) { isFourElementShuffle = false ; break ; } if ( EltNo == <NUM_LIT> ) { EltNo = ByteSource / <NUM_LIT> ; } else if ( EltNo != ByteSource / <NUM_LIT> ) { isFourElementShuffle = false ; break ; } } PFIndexes [ i ] = EltNo ; } if ( isFourElementShuffle ) { unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost < <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V1 ; EVT EltVT = V1 . getValueType ( ) . getVectorElementType ( ) ; unsigned BytesPerElement = EltVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > ResultMask ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) { unsigned SrcElt = PermMask [ i ] < <NUM_LIT> ? <NUM_LIT> : PermMask [ i ] ; for ( unsigned j = <NUM_LIT> ; j != BytesPerElement ; ++ j ) ResultMask . push_back ( DAG . getConstant ( SrcElt * BytesPerElement + j , <STR_LIT> ) ) ; } SDValue VPermMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & ResultMask [ <NUM_LIT> ] , ResultMask . size ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 , VPermMask ) ;


<s> unsigned StackProbeSize = ( MFI . getStackProtectorIndex ( ) > <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;

if ( F -> hasFnAttribute ( <STR_LIT> ) ) F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ;


<s> void <ISA_LIT>InstPrinter :: printMemOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {


<s> return AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS || AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ;


<s> OS << <STR_LIT> << Reg << <STR_LIT> << Offset << <STR_LIT> ;


<s> return __builtin_aarch64_sqshlu_nv16qi_uss ( __a , __b ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {


<s> inline bool <ISA_LIT>DAGToDAGISel :: SelectAnyImm2 ( SDValue & N , SDValue & R ) { return SelectAnyImmediate ( N , R , <NUM_LIT> ) ;


<s> assert ( MF -> getConstantPool ( ) -> getConstants ( ) . empty ( ) && <STR_LIT> ) ;


<s> static void ix86_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( size <= <NUM_LIT> * PROBE_INTERVAL ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size , last ; struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , PROBE_INTERVAL ) ;

emit_move_insn ( sr . reg , GEN_INT ( - first ) ) ;


<s> void <ISA_LIT>AsmPrinter :: emitSrcInText ( StringRef filename , unsigned line ) { std :: stringstream temp ; LineReader * reader = this -> getReader ( filename . str ( ) ) ; temp << <STR_LIT> ; temp << filename . str ( ) ; temp << <STR_LIT> ; temp << line ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> AM . IndexReg = IndexOp ; AM . Scale = cast < ConstantSDNode > ( ScaleOp ) -> getZExtValue ( ) ; unsigned AddrSpace = Parent -> getPointerInfo ( ) . getAddrSpace ( ) ; if ( AddrSpace == <STR_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <STR_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <STR_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDLoc DL ( BasePtr ) ; MVT VT = BasePtr . getSimpleValueType ( ) ; if ( matchVectorAddress ( BasePtr , AM ) ) return false ; getAddressOperands ( AM , DL , VT , Base , Scale , Index , Disp , Segment ) ; return true ;


<s> return __builtin_mve_vcmpeqq_n_v8hi ( __a , __b ) ;


<s> switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return combineExtractVectorElt ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineExtractVectorElt_SSE ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineInsertSubvector ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineSelect ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineBitcast ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineCMov ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineAdd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineADC ( N , DAG , DCI ) ; case <STR_LIT> : return combineMul ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShift ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineAnd ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineOr ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineXor ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineLoad ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineMaskedLoad ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineMaskedStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ;


<s> bool isThumbOne ( ) const { return isThumb ( ) && ( STI . getFeatureBits ( ) & <STR_LIT> ) == <NUM_LIT> ;


<s> static <ISA_LIT>Operand * CreateVectorIndex ( unsigned Idx , SMLoc S , SMLoc E , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_VectorIndex ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , BTF ( nullptr ) {


<s> printInstruction ( MI ) ; return ; } MCInst TmpInst ; switch ( MI -> getOpcode ( ) ) { case TargetInstrInfo :: DBG_LABEL : case TargetInstrInfo :: EH_LABEL : case TargetInstrInfo :: GC_LABEL : printLabel ( MI ) ; return ; case TargetInstrInfo :: INLINEASM : O << '\t' ; printInlineAsm ( MI ) ; return ; case TargetInstrInfo :: DECLARE : printDeclare ( MI ) ; return ; case TargetInstrInfo :: IMPLICIT_DEF : printImplicitDef ( MI ) ; return ; case <STR_LIT> : { MCSymbol * PICBase = GetPICBaseSymbol ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateMCValue ( MCValue :: get ( PICBase ) ) ) ; printInstruction ( & TmpInst ) ; OutStreamer . EmitLabel ( PICBase ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . getOperand ( <NUM_LIT> ) = MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; printInstruction ( & TmpInst ) ; O << <STR_LIT> ; printInstruction ( MI ) ; return ; } } O << <STR_LIT> ; TmpInst . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; switch ( MO . getType ( ) ) { default : O . flush ( ) ;

errs ( ) << <STR_LIT> << i << <STR_LIT> << * MI ;


<s> return S [ R - <STR_LIT> ] ; } if ( R >= <STR_LIT> && R <= <STR_LIT> ) { static const char * S [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return S [ R - <STR_LIT> ] ; }


<s> Ops . reserve ( NumOps - <NUM_LIT> ) ;

for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) Ops . push_back ( Op . getOperand ( I ) ) ;


<s> unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned add = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( add ) ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Offset = Op . getOperand ( <NUM_LIT> ) ; SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Frame = DAG . getRegister ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , getPointerTy ( ) ) ;

unsigned StoreAddrReg = ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ;


<s> const GlobalValue * GV = cast < GlobalValue > ( M -> getNamedValue ( ThunkIt -> Name ) ) ; MachineInstr * BL = isThumb ? BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( IndirectCall . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( IndirectCall . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addGlobalAddress ( GV ) : BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addGlobalAddress ( GV ) ; int ImpLROpIdx = - <NUM_LIT> ; int ImpSPOpIdx = - <NUM_LIT> ; for ( unsigned OpIdx = BL -> getNumExplicitOperands ( ) ; OpIdx < BL -> getNumOperands ( ) ; OpIdx ++ ) { MachineOperand Op = BL -> getOperand ( OpIdx ) ; if ( ! Op . isReg ( ) ) continue ; if ( Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) ) ImpLROpIdx = OpIdx ; if ( Op . getReg ( ) == <STR_LIT> && ! Op . isDef ( ) ) ImpSPOpIdx = OpIdx ; } assert ( ImpLROpIdx != - <NUM_LIT> ) ; assert ( ImpSPOpIdx != - <NUM_LIT> ) ; int FirstOpIdxToRemove = std :: max ( ImpLROpIdx , ImpSPOpIdx ) ; int SecondOpIdxToRemove = std :: min ( ImpLROpIdx , ImpSPOpIdx ) ; BL -> RemoveOperand ( FirstOpIdxToRemove ) ; BL -> RemoveOperand ( SecondOpIdxToRemove ) ; BL -> copyImplicitOps ( MF , IndirectCall ) ; MF . moveCallSiteInfo ( & IndirectCall , BL ) ; BL -> addOperand ( MachineOperand :: CreateReg ( Reg , false , true , RegIsKilled ) ) ; MBB . erase ( MBBI ) ;


<s> bool <ISA_LIT>TargetLowering :: allowFMA ( MachineFunction & MF , CodeGenOpt :: Level OptLevel ) const { const Function * F = MF . getFunction ( ) ; const TargetOptions & TO = MF . getTarget ( ) . Options ;

if ( FMAContractLevelOpt . getNumOccurrences ( ) > <NUM_LIT> ) {


<s> return new <ISA_LIT>Rematerialize ( ) ;


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) return MatchOperand_NoMatch ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Integer ) ) return MatchOperand_NoMatch ; unsigned IntVal = Tok . getIntVal ( ) ; unsigned Reg = matchRegisterByNumber ( IntVal , <STR_LIT> ) ; <ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printV4F64 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << '(' ; printF64 ( MI , OpNo + <NUM_LIT> , O ) ; O << <STR_LIT> ; printF64 ( MI , OpNo + <NUM_LIT> , O ) ; O << <STR_LIT> ; printF64 ( MI , OpNo + <NUM_LIT> , O ) ; O << <STR_LIT> ; printF64 ( MI , OpNo + <NUM_LIT> , O ) ; O << ')' ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & TT , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {

return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> const std :: vector < MachineInstr * > & getAllocaAdjustInsts ( ) { return AllocaAdjustInsts ;


<s> struct ix86_address parts ; rtx base , index , disp ; HOST_WIDE_INT scale ; addr_space_t seg ; if ( ix86_decompose_address ( addr , & parts ) <= <NUM_LIT> ) return false ; base = parts . base ; index = parts . index ; disp = parts . disp ; scale = parts . scale ; seg = parts . seg ; if ( base ) { rtx reg = ix86_validate_address_register ( base ) ; if ( reg == NULL_RTX ) return false ; if ( ( strict && ! REG_OK_FOR_BASE_STRICT_P ( reg ) ) || ( ! strict && ! REG_OK_FOR_BASE_NONSTRICT_P ( reg ) ) ) return false ; } if ( index ) { rtx reg = ix86_validate_address_register ( index ) ; if ( reg == NULL_RTX ) return false ; if ( ( strict && ! REG_OK_FOR_INDEX_STRICT_P ( reg ) ) || ( ! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P ( reg ) ) ) return false ; } if ( base && index && GET_MODE ( base ) != GET_MODE ( index ) ) return false ; if ( seg != ADDR_SPACE_GENERIC && ( ( base && GET_MODE ( base ) != word_mode ) || ( index && GET_MODE ( index ) != word_mode ) ) ) return false ; if ( scale != <NUM_LIT> ) { if ( ! index ) return false ; if ( scale != <NUM_LIT> && scale != <NUM_LIT> && scale != <NUM_LIT> ) return false ; } if ( disp ) { if ( GET_CODE ( disp ) == CONST && GET_CODE ( XEXP ( disp , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) != UNSPEC_MACHOPIC_OFFSET ) switch ( XINT ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : gcc_assert ( flag_pic ) ; if ( ! TARGET_64BIT ) goto is_legitimate_pic ; return false ; case UNSPEC_GOTPCREL : case UNSPEC_PCREL : gcc_assert ( flag_pic ) ; goto is_legitimate_pic ; case UNSPEC_GOTTPOFF : case UNSPEC_GOTNTPOFF : case UNSPEC_INDNTPOFF : case UNSPEC_NTPOFF :


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , <ISA_LIT>TargetMachine & TM , unsigned StackAlignOverride ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , PICStyle ( PICStyles :: None ) , TargetTriple ( TT ) , StackAlignOverride ( StackAlignOverride ) , In64BitMode ( TargetTriple . getArch ( ) == Triple :: x86_64 ) , In32BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) != Triple :: CODE16 ) , In16BitMode ( TargetTriple . getArch ( ) == Triple :: x86 && TargetTriple . getEnvironment ( ) == Triple :: CODE16 ) , DL ( computeDataLayout ( * this ) ) , TSInfo ( DL ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM ) , FrameLowering ( TargetFrameLowering :: StackGrowsDown , getStackAlignment ( ) , is64Bit ( ) ? - <NUM_LIT> : - <NUM_LIT> ) , JITInfo ( hasSSE1 ( ) ) {


<s> assert ( ( ! CurrI -> isCall ( ) && ! CurrI -> isReturn ( ) && ! CurrI -> isBranch ( ) ) && <STR_LIT> ) ; if ( CurrI -> isKill ( ) ) { CurrI -> eraseFromParent ( ) ; continue ; } if ( delayHasHazard ( * CurrI , RegDU , IM ) ) continue ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned Opcode = ( * Slot ) . getOpcode ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * CurrI ) == <NUM_LIT> && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ; Filler = CurrI ; return true ; } return false ;


<s> MachineBasicBlock * EntryBB = & MF -> front ( ) ; unsigned AR = FuncInfo -> CreateReg ( <STR_LIT> ) ; unsigned MaxA = MFI -> getMaxAlignment ( ) ; auto & HII = * HST . getInstrInfo ( ) ; BuildMI ( EntryBB , DebugLoc ( ) , HII . get ( <STR_LIT> ) , AR ) . addImm ( MaxA ) ;

MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setStackAlignBaseVReg ( AR ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TargetMachine ) : SelectionDAGISel ( TargetMachine ) {


<s> std :: string PA ( SumBase base , bool sub_p0 , bool p0_align , bool sub_p1 , bool p1_align ) { std :: string result ; switch ( base ) { case SumBase :: Zero : result = <STR_LIT> ;


for ( const StringRef & Label : OperatorLabels ) if ( FreeLabels . find ( Label ) == FreeLabels . end ( ) ) Error ( SMLoc :: getFromPointer ( Label . begin ( ) ) , <STR_LIT> , SMRange ( SMLoc :: getFromPointer ( Label . begin ( ) ) , SMLoc :: getFromPointer ( Label . end ( ) ) ) ) ;


<s> static void force_into_acc ( rtx src , rtx before ) { machine_mode mode = GET_MODE ( src ) ; rtx move ; if ( REG_P ( src ) && REGNO ( src ) < <NUM_LIT> ) return ; move = mode == QImode ? gen_movqi ( A , src ) : gen_movhi ( AX , src ) ;


<s> FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MRI . setPhysRegUnused ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; BPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , BPOffset , true ) ;

FI -> setBasePointerSaveIndex ( BPSI ) ;


<s> struct frv_packet_group * packet_group ; packet_group = & frv_packet . groups [ frv_unit_groups [ frv_insn_unit ( insn ) ] ] ;

packet_group -> insns [ packet_group -> num_insns ++ ] = insn ;


<s> const MachineOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ;

if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ;


<s> if ( FoldAsLoadDefReg == <NUM_LIT> ) return nullptr ; if ( MI . mayLoad ( ) ) { FoldAsLoadDefReg = <NUM_LIT> ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = <NUM_LIT> ; bool FoundSrcOperand = false ;

for ( unsigned i = <NUM_LIT> , e = MI . getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) {


<s> AFI -> setHasSpills ( true ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { assert ( false && <STR_LIT> ) ;


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; SmallVector < ArgInfo , <NUM_LIT> > RetInfos ; ArgInfo ArgRetInfo ( VRegs , * Val , <NUM_LIT> ) ; setArgFlags ( ArgRetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( ArgRetInfo , RetInfos , DL , F . getCallingConv ( ) ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ;

<ISA_LIT>OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret ) ;


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return Opcode == Instruction :: PHI ? <NUM_LIT> : <NUM_LIT> ;


<s> return false ; } MachineInstr * FirstVCTP = * VCTPs . begin ( ) ; for ( MachineInstr * VCTP : VCTPs ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * VCTP ) ; if ( VCTP -> getOpcode ( ) != FirstVCTP -> getOpcode ( ) || VCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) != FirstVCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } Register CountReg = FirstVCTP -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! CountReg . isVirtual ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MachineInstr * Phi = LookThroughCOPY ( MRI -> getVRegDef ( CountReg ) , MRI ) ; if ( ! Phi || Phi -> getOpcode ( ) != TargetOpcode :: PHI || Phi -> getNumOperands ( ) != <NUM_LIT> || ( Phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getLoopLatch ( ) && Phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) != ML -> getLoopLatch ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } CountReg = Phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) == ML -> getLoopLatch ( ) ? Phi -> getOperand ( <NUM_LIT> ) . getReg ( ) : Phi -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

MachineBasicBlock * MBB = LoopStart -> getParent ( ) ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfoFn X ( The<ISA_LIT>LETarget , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn Y ( The<ISA_LIT>BETarget , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn A ( TheThumbLETarget , create<ISA_LIT>MCAsmInfo ) ; RegisterMCAsmInfoFn B ( TheThumbBETarget , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>LETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>BETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( TheThumbLETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( TheThumbBETarget , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>LETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>BETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( TheThumbLETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( TheThumbBETarget , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>LETarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>BETarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( TheThumbLETarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCRegInfo ( TheThumbBETarget , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>LETarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>BETarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( TheThumbLETarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( TheThumbBETarget , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>LETarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( The<ISA_LIT>BETarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( TheThumbLETarget , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterMCInstrAnalysis ( TheThumbBETarget , create<ISA_LIT>MCInstrAnalysis ) ;

TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>LETarget , create<ISA_LIT>LEMCCodeEmitter ) ;


<s> explicit Entry ( const SortRegion * R ) : TheRegion ( R ) , NumBlocksLeft ( R -> getNumBlocks ( ) ) {


<s> if ( Index -> hasOneUse ( ) ) return false ; unsigned IndexOpcode = Index -> getOpcode ( ) ; if ( IndexOpcode == <STR_LIT> || IndexOpcode == <STR_LIT> ) return false ; } if ( Base -> hasOneUse ( ) ) return false ; return true ;


<s> return PopInst ( AvailableAlus [ AluPredX ] ) ; } if ( ! AvailableAlus [ AluDiscarded ] . empty ( ) ) { OccupedSlotsMask |= <NUM_LIT> ; return PopInst ( AvailableAlus [ AluDiscarded ] ) ; } if ( ! AvailableAlus [ AluT_XYZW ] . empty ( ) ) { OccupedSlotsMask |= <NUM_LIT> ; return PopInst ( AvailableAlus [ AluT_XYZW ] ) ; } } bool TransSlotOccuped = OccupedSlotsMask & <NUM_LIT> ; if ( ! TransSlotOccuped ) { if ( ! AvailableAlus [ AluTrans ] . empty ( ) ) { OccupedSlotsMask |= <NUM_LIT> ;

return PopInst ( AvailableAlus [ AluTrans ] ) ;


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;

assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;


<s> NextMI = skipDebugInstructionsForward ( NextMI , MBBEnd ) ; for ( const auto & MO : LastTrackedMI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register Reg = MO . getReg ( ) ;


<s> } if ( LastCMOV == & MI && NextMIIt != ThisMBB -> end ( ) && NextMIIt -> getOpcode ( ) == MI . getOpcode ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { return EmitLoweredCascadedSelect ( MI , * NextMIIt , ThisMBB ) ; } const BasicBlock * LLVM_BB = ThisMBB -> getBasicBlock ( ) ; MachineFunction * F = ThisMBB -> getParent ( ) ; MachineBasicBlock * FalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ThisMBB -> getIterator ( ) ; F -> insert ( It , FalseMBB ) ; F -> insert ( It , SinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; if ( ! LastCMOV -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( LastCMOV , ThisMBB , TRI ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( FalseMBB ) ;


<s> rtx mem = gen_rtx_MEM ( word_mode , addr ) ; MEM_VOLATILE_P ( mem ) = <NUM_LIT> ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ;


<s> } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ; } if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: iterator I = prior ( NextMII ) ; MI = & * I ; } } ProcessNext : bool DefCPSR = false ; LiveCPSR = UpdateCPSRDef ( * MI , LiveCPSR , DefCPSR ) ; if ( MI -> getDesc ( ) . isCall ( ) ) { CPSRDef = <NUM_LIT> ;


<s> if ( skipFunction ( * MF . getFunction ( ) ) || No<ISA_LIT>CFOpt . getValue ( ) ) return false ; return false ;


<s> live_regs_mask = calc_live_regs ( & reg_count ) ; parms = DECL_ARGUMENTS ( decl ) ; for ( ; parms ; parms = TREE_CHAIN ( parms ) ) { if ( GET_CODE ( DECL_RTL ( parms ) ) == MEM && XEXP ( DECL_RTL ( parms ) , <NUM_LIT> ) != const0_rtx && ! CONSTANT_P ( XEXP ( DECL_RTL ( parms ) , <NUM_LIT> ) ) ) parm_size += GET_MODE_SIZE ( GET_MODE ( DECL_RTL ( parms ) ) ) ; } fprintf ( file , <STR_LIT> , name , ( reg_count * <NUM_LIT> + get_frame_size ( ) + crtl -> args . pretend_args_size ) ) ; fprintf ( file , <STR_LIT> , reg_count * <NUM_LIT> ) ; fprintf ( file , <STR_LIT> , live_regs_mask ) ; fprintf ( file , <STR_LIT> , get_frame_size ( ) - parm_size ) ;

fprintf ( file , <STR_LIT> , parm_size ) ;


<s> SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; if ( Narrow ) std :: transform ( Regs . begin ( ) , Regs . end ( ) , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ; SDValue RegSeq = createQTuple ( Regs ) ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned LaneNo = cast < ConstantSDNode > ( N -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Ops [ ] = { RegSeq , CurDAG -> getTargetConstant ( LaneNo , dl , <STR_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ;

SDNode * St = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ST -> isLittle ( ) ) return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op ) ; if ( Op . isUndef ( ) ) return DCI . DAG . getUNDEF ( VT ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) ) ;


<s> bool isImm32 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> auto * STy = dyn_cast < StructType > ( Val -> getType ( ) ) ; IRBuilder < > Builder ( & * II ) ; Ptr = Builder . CreateBitCast ( Ptr , STy -> getElementType ( <NUM_LIT> ) -> getPointerTo ( ) ) ;

for ( unsigned i = <NUM_LIT> ; i < STy -> getNumElements ( ) ; ++ i ) {


<s> if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { const APInt & XorC = Op1 . getConstantOperandAPInt ( <NUM_LIT> ) ; EVT VT = Op0 . getValueType ( ) ; SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ XorC , SDLoc ( Op1 ) , VT ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , NewXor , DAG . getConstant ( C -> getAPIntValue ( ) + <NUM_LIT> , SDLoc ( N ) , VT ) ) ; } } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , false ) && shouldUseHorizontalOp ( Op0 == Op1 , DAG , Subtarget ) ) { auto HSUBBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ;


<s> if ( auto * Const = dyn_cast < ConstantInt > ( CI -> getOperand ( <NUM_LIT> ) ) ) if ( Const -> isNegative ( ) ) return false ; if ( auto * Const = dyn_cast < ConstantInt > ( CI -> getOperand ( <NUM_LIT> ) ) ) if ( Const -> isNegative ( ) ) return false ; bool NegImm = cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) -> isNegative ( ) ; bool IsDecreasing = ( ( Opc == Instruction :: Sub ) && ! NegImm ) || ( ( Opc == Instruction :: Add ) && NegImm ) ;


<s> Value * Op = I -> getOperand ( <NUM_LIT> ) ; Type * SrcTy = Op -> getType ( ) ; EVT SrcEVT = TLI . getValueType ( DL , SrcTy , true ) ; EVT DestEVT = TLI . getValueType ( DL , DestTy , true ) ; if ( ! SrcEVT . isSimple ( ) ) return false ; if ( ! DestEVT . isSimple ( ) ) return false ; MVT SrcVT = SrcEVT . getSimpleVT ( ) ; MVT DestVT = DestEVT . getSimpleVT ( ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Op ) ; if ( ! SrcReg ) return false ; bool SrcIsKill = hasTrivialKill ( Op ) ; unsigned ResultReg ; if ( SrcVT == <STR_LIT> ) { uint64_t Mask = <NUM_LIT> ; switch ( DestVT . SimpleTy ) { default : return false ; case <STR_LIT> : Mask = <NUM_LIT> ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Hi = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi . getValue ( <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ;


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; }


<s> SDValue Val = N -> getOperand ( <NUM_LIT> ) ; EVT ValVT = Val . getValueType ( ) ; if ( VT == <STR_LIT> && ValVT == <STR_LIT> ) { if ( SDValue Res = implicitlyClearTop ( Val , DAG ) ) {

DCI . CombineTo ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Val ) ;


<s> return XnackSetting != TargetIDSetting :: Unsupported ;


<s> Triple Triple ( TT ) ; std :: string Ret = <STR_LIT> ; if ( Triple . getArch ( ) == Triple :: amdgcn ) { Ret += <STR_LIT> ; }


return ( __m256 ) __builtin_ia32_vcvtneeph2ps256 ( ( const __v16hf * ) __A ) ;


<s> bool ConstantPool :: empty ( ) { return Entries . empty ( ) ;


<s> const MCOperand & MO = MI . getOperand ( Op ) ; if ( MO . isExpr ( ) ) { const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind = MCFixupKind ( FK_Data_4 ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , Kind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } return MO . getImm ( ) ;


<s> void setScoreLB ( InstCounterType T , unsigned Val ) {


<s> if ( ! func_optimize ) func_optimize = old_optimize ; memset ( & func_options , <NUM_LIT> , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; memset ( & func_options_set , <NUM_LIT> , sizeof ( func_options_set ) ) ; cl_optimization_restore ( & func_options , & func_options_set , TREE_OPTIMIZATION ( func_optimize ) ) ; tree old_target = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( old_target == NULL_TREE ) old_target = target_option_default_node ; cl_target_option_restore ( & func_options , & func_options_set , TREE_TARGET_OPTION ( old_target ) ) ; new_target = ix86_valid_target_attribute_tree ( fndecl , args , & func_options , & func_options_set , flags == <NUM_LIT> ) ; new_optimize = build_optimization_node ( & func_options , & func_options_set ) ; if ( new_target == error_mark_node ) ret = false ; else if ( new_target ) { if ( DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) == NULL_TREE && DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) == NULL_TREE ) { target_attribute_cache [ <NUM_LIT> ] = copy_list ( args ) ; target_attribute_cache [ <NUM_LIT> ] = new_target ; target_attribute_cache [ <NUM_LIT> ] = old_optimize != new_optimize ? new_optimize : NULL_TREE ; }

DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = new_target ;


<s> return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; uint64_t Mask = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ; ++ I ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ;


<s> const MCInstrDesc & Desc = UseMI -> getDesc ( ) ; const MCOperandInfo * OpInfo = Desc . OpInfo ; if ( ! OpInfo || UseOpIdx >= Desc . getNumOperands ( ) ) return false ; uint8_t OpTy = OpInfo [ UseOpIdx ] . OperandType ; if ( OpTy < <STR_LIT> || OpTy > <STR_LIT> ) return false ; if ( OpToFold . isImm ( ) && TII -> isInlineConstant ( OpToFold , OpTy ) && TII -> isOperandLegal ( * UseMI , UseOpIdx , & OpToFold ) ) { UseMI -> getOperand ( UseOpIdx ) . ChangeToImmediate ( OpToFold . getImm ( ) ) ; return true ; } if ( ! OpToFold . isReg ( ) ) return false ;

Register UseReg = OpToFold . getReg ( ) ;


<s> return std :: make_unique < <ISA_LIT>Operand > ( Val , S , E ) ;


<s> <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & st ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> ) , ST ( st ) {


<s> case <STR_LIT> : return EmitCustomSelect ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return EmitCustomAtomic ( MI , MBB ) ; case <STR_LIT> : MI -> eraseFromParent ( ) ; return MBB ; }


<s> if ( CC == CallingConv :: Intel_OCL_BI ) { if ( IsWin64 && HasAVX512 ) return CSR_Win64_Intel_OCL_BI_AVX512_RegMask ; if ( Is64Bit && HasAVX512 ) return CSR_64_Intel_OCL_BI_AVX512_RegMask ; if ( IsWin64 && HasAVX ) return CSR_Win64_Intel_OCL_BI_AVX_RegMask ; if ( Is64Bit && HasAVX ) return CSR_64_Intel_OCL_BI_AVX_RegMask ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_RegMask ; } if ( CC == CallingConv :: GHC || CC == CallingConv :: HiPE ) return CSR_NoRegs_RegMask ;

if ( ! Is64Bit ) return CSR_32_RegMask ;


<s> if ( ! isUs ) { if ( ! RS ) report_fatal_error ( <STR_LIT> + Twine ( Offset ) ) ; unsigned ScratchReg = RS -> scavengeRegister ( <STR_LIT> , II , SPAdj ) ; loadConstant ( MBB , II , ScratchReg , Offset , dl ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addReg ( ScratchReg , RegState :: Kill ) ; break ; case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( isKill ) ) . addReg ( FramePtr ) . addReg ( ScratchReg , RegState :: Kill ) ; break ; case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addReg ( ScratchReg , RegState :: Kill ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addImm ( Offset ) ; break ; case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( isKill ) ) . addReg ( FramePtr ) . addImm ( Offset ) ; break ; case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addImm ( Offset ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } } else { bool isU6 = isImmU6 ( Offset ) ; if ( ! isU6 && ! isImmU16 ( Offset ) ) report_fatal_error ( <STR_LIT> + Twine ( Offset ) ) ; switch ( MI . getOpcode ( ) ) { int NewOpcode ; case <STR_LIT> : NewOpcode = ( isU6 ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , II , dl , TII . get ( NewOpcode ) , Reg ) . addImm ( Offset ) ; break ; case <STR_LIT> : NewOpcode = ( isU6 ) ? <STR_LIT> : <STR_LIT> ;

BuildMI ( MBB , II , dl , TII . get ( NewOpcode ) ) . addReg ( Reg , getKillRegState ( isKill ) ) . addImm ( Offset ) ;


<s> <ISA_LIT>IRPeephole ( ) : FunctionPass ( ID ) {


<s> LinearizedRegion :: ~ LinearizedRegion ( ) {


<s> ASM_OUTPUT_ALIGN ( file , floor_log2 ( align / BITS_PER_UNIT ) ) ; last_assemble_variable_decl = decl ; ASM_DECLARE_OBJECT_NAME ( file , name , decl ) ;


<s> int insns1 , insns2 ; struct four_ints tmp_sequence ; if ( TARGET_ARM ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) { int consecutive_zeros = <NUM_LIT> ; if ( ! ( val & ( <NUM_LIT> << i ) ) ) { while ( ( i < <NUM_LIT> ) && ! ( val & ( <NUM_LIT> << i ) ) ) { consecutive_zeros += <NUM_LIT> ; i += <NUM_LIT> ; } if ( consecutive_zeros > best_consecutive_zeros ) { best_consecutive_zeros = consecutive_zeros ; best_start = i - consecutive_zeros ; } i -= <NUM_LIT> ; } } } insns1 = optimal_immediate_sequence_1 ( code , val , return_sequence , best_start ) ; if ( best_start != <NUM_LIT> && ( ( HOST_WIDE_INT_1U << best_start ) < val ) ) { insns2 = optimal_immediate_sequence_1 ( code , val , & tmp_sequence , <NUM_LIT> ) ; if ( insns2 <= insns1 ) { * return_sequence = tmp_sequence ; insns1 = insns2 ; }


<s> auto RegName = [ ] ( unsigned Reg ) { if ( Reg ) return <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; else return <STR_LIT> ; } ; switch ( Kind ) { case KindTy :: Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ; case KindTy :: Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case KindTy :: SystemRegister : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; case KindTy :: SpecialCapRegister :

OS << <STR_LIT> << getSpecialCapReg ( ) << '>' ;


<s> MCSection * getExplicitSectionGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const override { return DataSection ;


<s> TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Val ; Entry . Ty = Val . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . IsZExt = true ; Args . push_back ( Entry ) ; Entry . Node = Exponent ; Entry . Ty = Exponent . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . IsZExt = true ; Args . push_back ( Entry ) ; Type * LCRTy = Val . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue TCChain = InChain ; const auto * F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool IsTC = TLI . isInTailCallPosition ( DAG , Op . getNode ( ) , TCChain ) && F -> getReturnType ( ) == LCRTy ; if ( IsTC ) InChain = TCChain ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setCallee ( CallingConv :: <ISA_LIT>_AAPCS_VFP , LCRTy , Callee , std :: move ( Args ) ) . setTailCall ( IsTC ) ; std :: pair < SDValue , SDValue > CI = TLI . LowerCallTo ( CLI ) ;

return ! CI . second . getNode ( ) ? DAG . getRoot ( ) : CI . first ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerUINT_TO_FP_i32 ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Bias = DAG . getConstantFP ( BitsToDouble ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Load = getShuffleVectorZeroOrUndef ( Load , <NUM_LIT> , true , Subtarget , DAG ) ; Load = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Bias ) ) ) ; Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; EVT DestVT = Op . getValueType ( ) ;


<s> bool IsMinSize = MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ; if ( IsMinSize ) return SDValue ( ) ; SDValue StVal = S -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( ! VT . isVector ( ) || VT . getVectorNumElements ( ) < <NUM_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , S ) ; if ( ReplacedSplat != SDValue ( ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> isVolatile ( ) , S -> isNonTemporal ( ) , S -> getAlignment ( ) ) ;

SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OL ) : SelectionDAGISel ( TM , OL ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {