<s> selectingMemOp = true ; if ( Parent && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> ) { unsigned AddrSpace = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) . getAddrSpace ( ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; if ( AddrSpace == <NUM_LIT> ) AM . Segment = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; } if ( MatchAddress ( N , AM ) ) return false ; if ( Subtarget -> isTargetNaCl64 ( ) ) { LegalizeAddressingModeForNaCl ( N , AM ) ; } MVT VT = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) { if ( ! AM . Base_Reg . getNode ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } if ( ! AM . IndexReg . getNode ( ) ) AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; getAddressOperands ( AM , Base , Scale , Index , Disp , Segment ) ; if ( Subtarget -> isTargetNaCl64 ( ) ) { assert ( Base . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Index . getValueType ( ) != <STR_LIT> ) { Index = CurDAG -> getZExtOrTrunc ( Index , SDLoc ( Index ) , <STR_LIT> ) ; if ( Parent && ( Index -> getNodeId ( ) == - <NUM_LIT> || Index -> getNodeId ( ) > Parent -> getNodeId ( ) ) ) { CurDAG -> RepositionNode ( Parent , Index . getNode ( ) ) ; Index -> setNodeId ( Parent -> getNodeId ( ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( i ) ;

for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) ShuffleMask . push_back ( NElts + i ) ;


<s> bool <ISA_LIT>ExpandPseudo :: expandAtomicArithmeticOp ( unsigned Width , unsigned ArithOpcode , Block & MBB , BlockIt MBBI ) { return expandAtomic ( MBB , MBBI , [ & ] ( MachineInstr & MI ) { auto Op1 = MI . getOperand ( <NUM_LIT> ) ; auto Op2 = MI . getOperand ( <NUM_LIT> ) ; unsigned LoadOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned StoreOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; buildMI ( MBB , MBBI , LoadOpcode ) . addOperand ( Op1 ) . addOperand ( Op2 ) ; buildMI ( MBB , MBBI , ArithOpcode ) . addOperand ( Op1 ) . addOperand ( Op1 ) . addOperand ( Op2 ) ; buildMI ( MBB , MBBI , StoreOpcode ) . addOperand ( Op2 ) . addOperand ( Op1 ) ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> case IES_LBRAC : case IES_RBRAC : case IES_INTEGER : case IES_REGISTER : case IES_INIT : case IES_OFFSET : State = IES_MINUS ; if ( CurrState == IES_REGISTER || CurrState == IES_RPAREN || CurrState == IES_INTEGER || CurrState == IES_RBRAC || CurrState == IES_OFFSET ) IC . pushOperator ( IC_MINUS ) ; else if ( PrevState == IES_REGISTER && CurrState == IES_MULTIPLY ) { ErrMsg = <STR_LIT> ; return true ; } else IC . pushOperator ( IC_NEG ) ; if ( CurrState == IES_REGISTER && PrevState != IES_MULTIPLY ) { if ( ! BaseReg ) { BaseReg = TmpReg ; } else { if ( IndexReg ) { ErrMsg = <STR_LIT> ; return true ;


<s> if ( isTypeSupported ( ZE -> getType ( ) , RetVT ) ) IntExtVal = ZE ; else RetVT = VT ; } else if ( const auto * SE = dyn_cast < SExtInst > ( I -> use_begin ( ) -> getUser ( ) ) ) { if ( isTypeSupported ( SE -> getType ( ) , RetVT ) ) IntExtVal = SE ; else RetVT = VT ; WantZExt = false ; } } unsigned ResultReg = emitLoad ( VT , RetVT , Addr , WantZExt , createMachineMemOperandFor ( I ) ) ; if ( ! ResultReg ) return false ; if ( IntExtVal ) { unsigned Reg = lookUpRegForValue ( IntExtVal ) ; auto * MI = MRI . getUniqueVRegDef ( Reg ) ; if ( ! MI ) { if ( RetVT == <STR_LIT> && VT <= <STR_LIT> ) { if ( WantZExt ) { std :: prev ( FuncInfo . InsertPt ) -> eraseFromParent ( ) ; ResultReg = std :: prev ( FuncInfo . InsertPt ) -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , ResultReg , true , <STR_LIT> ) ; } updateValueMap ( I , ResultReg ) ; return true ; } while ( MI ) { Reg = <NUM_LIT> ; for ( auto & Opnd : MI -> uses ( ) ) { if ( Opnd . isReg ( ) ) { Reg = Opnd . getReg ( ) ; break ; } } MI -> eraseFromParent ( ) ; MI = nullptr ;

if ( Reg ) MI = MRI . getUniqueVRegDef ( Reg ) ;


<s> static bool frv_print_operand_punct_valid_p ( unsigned char code ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerImplicitParameter ( SelectionDAG & DAG , EVT VT , const SDLoc & DL , unsigned DwordOffset ) const { unsigned ByteOffset = DwordOffset * <NUM_LIT> ; PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ; assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ;

return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getConstant ( ByteOffset , DL , <STR_LIT> ) , MachinePointerInfo ( ConstantPointerNull :: get ( PtrType ) ) , false , false , false , <NUM_LIT> ) ;


<s> if ( ! IN_RANGE ( index , <NUM_LIT> , <NUM_LIT> ) ) return NULL ; struct loongarch_address_info info ; if ( ( loongarch_classify_address ( & info , x , mode , false ) && ! ( info . type == ADDRESS_REG_REG ) ) || ! loongarch_legitimate_address_p ( mode , x , false ) ) return NULL ;

const char * const insn [ ] [ <NUM_LIT> ] = {


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> static bool expand_perm_with_rot ( const struct expand_vec_perm_d & d ) { if ( d . nelt != <NUM_LIT> ) return false ; if ( d . op0 == d . op1 && is_reverse_perm_mask ( d ) ) { if ( d . testing_p ) return true ; rtx tmp = gen_reg_rtx ( d . vmode ) ; rtx op0_reg = force_reg ( GET_MODE ( d . op0 ) , d . op0 ) ; emit_insn ( gen_vpdi4_2 ( d . vmode , tmp , op0_reg , op0_reg ) ) ;

if ( d . vmode == V4SImode ) emit_insn ( gen_rotlv4si3_di ( d . target , tmp ) ) ;


<s> if ( ImmOp . getFPImm ( ) -> isNullValue ( ) ) return nullptr ; const APFloat & ImmValAPF = ImmOp . getFPImm ( ) -> getValueAPF ( ) ; int Imm = DefSize == <NUM_LIT> ? <STR_LIT> ( ImmValAPF ) : <STR_LIT> ( ImmValAPF ) ; if ( Imm == - <NUM_LIT> ) return nullptr ; ImmOp . ChangeToImmediate ( Imm ) ; unsigned MovOpc = DefSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; I . setDesc ( TII . get ( MovOpc ) ) ; constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; return & I ;


<s> return DAG . getNode ( <STR_LIT> , dl , VT , ff1 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoAtDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetAtDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSet<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNo<ISA_LIT>16Directive ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveSetNoMicro<ISA_LIT> ( ) ; Parser . eatToEndOfStatement ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveSetMicro<ISA_LIT> ( ) ; Parser . eatToEndOfStatement ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R2 ( ) ; return false ; } else if ( Tok . getString ( ) == <STR_LIT> ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return reportParseError ( <STR_LIT> ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetDsp ( ) ; return false ; } else { parseSetAssignment ( ) ; return false ;


<s> } else if ( TheTriple . isWindowsMSVCEnvironment ( ) ) { MAI = new <ISA_LIT>MCAsmInfoMicrosoft ( TheTriple ) ; } else if ( TheTriple . isOSCygMing ( ) || TheTriple . isWindowsItaniumEnvironment ( ) ) { MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ; unsigned StackPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , MRI . getDwarfRegNum ( StackPtr , true ) , - stackGrowth ) ; MAI -> addInitialFrameState ( Inst ) ; unsigned InstPtr = is64Bit ? <STR_LIT> : <STR_LIT> ; MCCFIInstruction Inst2 = MCCFIInstruction :: createOffset ( nullptr , MRI . getDwarfRegNum ( InstPtr , true ) , stackGrowth ) ;


<s> bool iss4Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false , false ) ;


<s> const MachineOperand * M0Reg = TII -> getNamedOperand ( * I , AMDGPU :: OpName :: m0 ) ; unsigned DestReg0 = TII -> getNamedOperand ( * I , AMDGPU :: OpName :: vdst ) -> getReg ( ) ; unsigned DestReg1 = TII -> getNamedOperand ( * Paired , AMDGPU :: OpName :: vdst ) -> getReg ( ) ; unsigned Offset0 = TII -> getNamedOperand ( * I , AMDGPU :: OpName :: offset ) -> getImm ( ) & <NUM_LIT> ; unsigned Offset1 = TII -> getNamedOperand ( * Paired , AMDGPU :: OpName :: offset ) -> getImm ( ) & <NUM_LIT> ; unsigned NewOffset0 = Offset0 / EltSize ; unsigned NewOffset1 = Offset1 / EltSize ; unsigned Opc = ( EltSize == <NUM_LIT> ) ? AMDGPU :: DS_READ2_B32 : AMDGPU :: DS_READ2_B64 ; bool UseST64 = ( NewOffset0 % <NUM_LIT> == <NUM_LIT> ) && ( NewOffset1 % <NUM_LIT> == <NUM_LIT> ) ; if ( UseST64 ) { NewOffset0 /= <NUM_LIT> ; NewOffset1 /= <NUM_LIT> ; Opc = ( EltSize == <NUM_LIT> ) ? AMDGPU :: DS_READ2ST64_B32 : AMDGPU :: DS_READ2ST64_B64 ; } assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Read2Desc = TII -> get ( Opc ) ; const TargetRegisterClass * SuperRC = ( EltSize == <NUM_LIT> ) ? & AMDGPU :: VReg_64RegClass : & AMDGPU :: VReg_128RegClass ; unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; DebugLoc DL = I -> getDebugLoc ( ) ; MachineInstrBuilder Read2 = BuildMI ( * MBB , I , DL , Read2Desc , DestReg ) . addImm ( <NUM_LIT> ) . addOperand ( * AddrReg ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addOperand ( * M0Reg ) . addMemOperand ( * I -> memoperands_begin ( ) ) . addMemOperand ( * Paired -> memoperands_begin ( ) ) ;

LIS -> InsertMachineInstrInMaps ( Read2 ) ;


<s> fprintf ( dump_file , <STR_LIT> , INTVAL ( t ) ) ;

for ( unsigned i = <NUM_LIT> ; i < insn_info . length ( ) ; i ++ ) dump_insn_slim ( dump_file , insn_info [ i ] -> insn ) ;


<s> else if ( ( unsigned int ) align_functions < max_align ) align = align_functions ; else align = max_align ; ofs = prev_in_use = <NUM_LIT> ; i = get_insns ( ) ; if ( GET_CODE ( i ) == NOTE ) i = next_nonnote_insn ( i ) ; ldgp = alpha_function_needs_gp ? <NUM_LIT> : <NUM_LIT> ; while ( i ) { next = ( * next_group ) ( i , & in_use , & len ) ; if ( GET_CODE ( i ) == CODE_LABEL ) { unsigned int new_align = <NUM_LIT> << label_to_alignment ( i ) ; if ( new_align >= align ) { align = new_align < max_align ? new_align : max_align ; ofs = <NUM_LIT> ; } else if ( ofs & ( new_align - <NUM_LIT> ) ) ofs = ( ofs | ( new_align - <NUM_LIT> ) ) + <NUM_LIT> ; gcc_assert ( ! len ) ; } else if ( in_use == <NUM_LIT> ) { if ( len < <NUM_LIT> ) { ofs = <NUM_LIT> ; align = <NUM_LIT> ; len = <NUM_LIT> ; } } else if ( ( int ) align < len ) { unsigned int new_log_align = len > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; rtx prev , where ; where = prev = prev_nonnote_insn ( i ) ; if ( ! where || GET_CODE ( where ) != CODE_LABEL ) where = i ; if ( ! ( TARGET_EXPLICIT_RELOCS && prev && GET_CODE ( prev ) == CALL_INSN ) ) { emit_insn_before ( gen_realign ( GEN_INT ( new_log_align ) ) , where ) ; align = <NUM_LIT> << new_log_align ; ofs = <NUM_LIT> ; } } else if ( ldgp > <NUM_LIT> ) ldgp -= len ; else if ( ofs + len > ( int ) align ) { int nop_count = ( align - ofs ) / <NUM_LIT> ; rtx where ; where = prev_nonnote_insn ( i ) ; if ( where ) { if ( GET_CODE ( where ) == CODE_LABEL ) { rtx where2 = prev_nonnote_insn ( where ) ; if ( where2 && GET_CODE ( where2 ) == JUMP_INSN ) where = where2 ; } else if ( GET_CODE ( where ) == INSN ) where = i ; } else where = i ;

do emit_insn_before ( ( * next_nop ) ( & prev_in_use ) , where ) ;


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) : FastISel ( FuncInfo , LibInfo ) , TM ( FuncInfo . MF -> getTarget ( ) ) , TII ( * TM . getInstrInfo ( ) ) , TLI ( * TM . getTargetLowering ( ) ) , <ISA_LIT>SubTarget ( * ( ( static_cast < const <ISA_LIT>TargetMachine * > ( & TM ) ) -> getSubtargetImpl ( ) ) ) , Context ( & FuncInfo . Fn -> getContext ( ) ) {


<s> if ( value != <NUM_LIT> ) return <NUM_LIT> ; if ( ! REG_P ( addr ) ) return <NUM_LIT> ; if ( REGNO ( addr ) == ( unsigned ) HARD_FRAME_POINTER_REGNUM ) return <NUM_LIT> ; if ( ( TARGET_THUMB || ! frame_pointer_needed ) && REGNO ( addr ) == SP_REGNUM ) return <NUM_LIT> ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == SET && REGNO ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) ) == REGNO ( addr ) && GET_CODE ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) && REGNO ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) == ( unsigned ) HARD_FRAME_POINTER_REGNUM && CONST_INT_P ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) ) { value = INTVAL ( XEXP ( XEXP ( PATTERN ( insn ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; break ; } }


<s> if ( VT . isVector ( ) ) return LowerVectorFP_TO_INT ( Op , DAG ) ; if ( ! Subtarget -> hasFP64 ( ) && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { RTLIB :: Libcall LC ;

if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;


<s> static section * pa_function_section ( tree decl , enum node_frequency freq , bool startup , bool exit ) { if ( ! targetm_common . have_named_sections ) return text_section ; if ( decl && DECL_SECTION_NAME ( decl ) == NULL && DECL_CONTEXT ( decl ) != NULL_TREE && TREE_CODE ( DECL_CONTEXT ( decl ) ) == FUNCTION_DECL && DECL_SECTION_NAME ( DECL_CONTEXT ( decl ) ) == NULL ) return function_section ( DECL_CONTEXT ( decl ) ) ;

return default_function_section ( decl , freq , startup , exit ) ;


<s> switch ( Lmul ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> CC = <STR_LIT> ; RHS = DAG . getSelectCC ( dl , LHS , LHS , RHS , LHS , CC ) ; break ; case <STR_LIT> : CC = <STR_LIT> ; RHS = DAG . getSelectCC ( dl , LHS , LHS , LHS , RHS , CC ) ; break ; } if ( NegateFCC ( LHS , RHS , CC ) ) std :: swap ( TrueV , FalseV ) ; SDValue TargetCC = DAG . getConstant ( CC , dl , <STR_LIT> ) ; SDValue Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , TargetCC ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { TrueV , FalseV , TargetCC , Flag } ; return DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ;


<s> return new <ISA_LIT>OptimizePICCall ( ) ;


<s> uint32_t getMinVersion ( ) const { return minVersion ;


<s> FormalArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI ) : IncomingArgHandler ( MIRBuilder , MRI ) {


<s> void <ISA_LIT>InstrInfo :: expandLDZ ( MachineIRBuilder & Builder ) const { auto & MI = * Builder . getInsertPt ( ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( DestReg ) ) { MI . setDesc ( Builder . getTII ( ) . get ( <STR_LIT> ) ) ; } else if ( <STR_LIT> . contains ( DestReg ) ) { MI . setDesc ( Builder . getTII ( ) . get ( <STR_LIT> ) ) ; MI . addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } else {


<s> void <ISA_LIT>DAGToDAGISel :: selectVLSEGFFMask ( SDNode * Node ) { SDLoc DL ( Node ) ; unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned NF = Node -> getNumValues ( ) - <NUM_LIT> ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; unsigned ScalarSize = VT . getScalarSizeInBits ( ) ; MVT XLenVT = Subtarget -> getXLenVT ( ) ; <ISA_LIT>VLMUL LMUL = getLMUL ( VT ) ; SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ;

SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ;

TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ;


<s> static DecodeStatus DecodeGPRPF64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo >= <NUM_LIT> || RegNo & <NUM_LIT> ) return MCDisassembler :: Fail ; MCRegister Reg = <STR_LIT> + RegNo ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> Filler ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) {


<s> arm_simd_types [ Int16x8_t ] . eltype = intHI_type_node ; arm_simd_types [ Int32x2_t ] . eltype = intSI_type_node ; arm_simd_types [ Int32x4_t ] . eltype = intSI_type_node ; arm_simd_types [ Int64x2_t ] . eltype = intDI_type_node ; arm_simd_types [ Uint8x8_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint8x16_t ] . eltype = unsigned_intQI_type_node ; arm_simd_types [ Uint16x4_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint16x8_t ] . eltype = unsigned_intHI_type_node ; arm_simd_types [ Uint32x2_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint32x4_t ] . eltype = unsigned_intSI_type_node ; arm_simd_types [ Uint64x2_t ] . eltype = unsigned_intDI_type_node ; arm_simd_types [ Poly8x8_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly8x16_t ] . eltype = arm_simd_polyQI_type_node ; arm_simd_types [ Poly16x4_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Poly16x8_t ] . eltype = arm_simd_polyHI_type_node ; arm_simd_types [ Float16x4_t ] . eltype = arm_fp16_type_node ; arm_simd_types [ Float16x8_t ] . eltype = arm_fp16_type_node ; arm_simd_types [ Float32x2_t ] . eltype = float_type_node ; arm_simd_types [ Float32x4_t ] . eltype = float_type_node ; for ( i = <NUM_LIT> ; i < nelts ; i ++ ) { tree eltype = arm_simd_types [ i ] . eltype ; enum machine_mode mode = arm_simd_types [ i ] . mode ; if ( arm_simd_types [ i ] . itype == NULL ) arm_simd_types [ i ] . itype = build_distinct_type_copy ( build_vector_type ( eltype , GET_MODE_NUNITS ( mode ) ) ) ; tdecl = add_builtin_type ( arm_simd_types [ i ] . name , arm_simd_types [ i ] . itype ) ; TYPE_NAME ( arm_simd_types [ i ] . itype ) = tdecl ;

SET_TYPE_STRUCTURAL_EQUALITY ( arm_simd_types [ i ] . itype ) ;


<s> OPCODE ( CLC ) ; OPCODE ( CLC_LOOP ) ; OPCODE ( STPCPY ) ; OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( STRICT_VFCMPE ) ; OPCODE ( STRICT_VFCMPES ) ; OPCODE ( VFCMPH ) ; OPCODE ( STRICT_VFCMPH ) ; OPCODE ( STRICT_VFCMPHS ) ; OPCODE ( VFCMPHE ) ; OPCODE ( STRICT_VFCMPHE ) ; OPCODE ( STRICT_VFCMPHES ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( STRICT_VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( STRICT_VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ;


<s> GShlE_match < ADDR_P , CARRYIN_P > m_GShlE ( Register & CarryOut , const ADDR_P & Addr , const CARRYIN_P & CarryIn ) {


<s> fprintf ( file , <STR_LIT> ) ; return true ; case UNSPEC_PLT : output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> ) ; return true ; case UNSPEC_PLTOFF : output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> ) ; return true ; case UNSPEC_TLSGD : output_addr_const ( file , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> ) ; return true ; case UNSPEC_TLSLDM : assemble_name ( file , get_some_local_dynamic_name ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerINTRINSIC_WO_CHAIN ( SDValue Op , SelectionDAG & DAG ) const { switch ( cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> : return LowerDSPIntr ( Op , DAG , <STR_LIT> , true , true ) ; case <STR_LIT> :


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return true ;


<s> const DebugLoc & DL = I . getDebugLoc ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Size = MRI -> getType ( DstReg ) . getSizeInBits ( ) ; const bool Is64 = Size == <NUM_LIT> ; if ( Size != STI . getWavefrontSize ( ) ) return false ; Optional < ValueAndVReg > Arg = getConstantVRegValWithLookThrough ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI , true ) ; if ( Arg . hasValue ( ) ) { const int64_t Value = Arg . getValue ( ) . Value ; if ( Value == <NUM_LIT> ) { unsigned Opcode = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( Opcode ) , DstReg ) . addImm ( <NUM_LIT> ) ; } else if ( Value == - <NUM_LIT> ) { Register SrcReg = Is64 ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; } else return false ;


<s> addPass ( create<ISA_LIT>VectorRegMerger ( ) ) ;


<s> if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( ! TLI . isTypeLegal ( SrcVT ) ) return false ; Register InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; if ( SrcVT == <STR_LIT> ) { updateValueMap ( I , InputReg ) ; return true ; } Register ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , InputReg , <STR_LIT> ) ; if ( ! ResultReg ) return false ; updateValueMap ( I , ResultReg ) ;


<s> void FPOStateMachine :: emitFrameDataRecord ( MCStreamer & OS , MCSymbol * Label ) { unsigned CurFlags = Flags ; if ( Label == FPO -> Begin ) CurFlags |= FrameData :: IsFunctionStart ; FrameFunc . clear ( ) ; raw_svector_ostream FuncOS ( FrameFunc ) ; const MCRegisterInfo * MRI = OS . getContext ( ) . getRegisterInfo ( ) ; assert ( ( StackAlign == <NUM_LIT> || FrameReg != <NUM_LIT> ) && <STR_LIT> ) ; StringRef CFAVar = StackAlign == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( FrameReg ) {

FuncOS
<<
CFAVar
<<
' '
<<
printFPOReg
(
MRI
,
FrameReg
)
<<
' '
<<
FrameRegOff
<<
<STR_LIT>
;


<s> if ( AS2 == ADDRESS_SPACE_UNINITIALIZED ) return AS1 ; return AS1 == AS2 ? AS1 : ( unsigned ) AddressSpace :: ADDRESS_SPACE_GENERIC ;


<s> EVT SrcElVT = SrcVT . getScalarType ( ) ; EVT DstElVT = DstVT . getScalarType ( ) ; if ( SrcElVT . getSizeInBits ( ) < <NUM_LIT> || SrcElVT . getSizeInBits ( ) > <NUM_LIT> ) return false ; if ( DstElVT . getSizeInBits ( ) < <NUM_LIT> || DstElVT . getSizeInBits ( ) > <NUM_LIT> ) return false ; if ( SrcVT . is512BitVector ( ) || Subtarget . hasVLX ( ) ) return SrcElVT . getSizeInBits ( ) >= <NUM_LIT> || Subtarget . hasBWI ( ) ; return false ;


<s> if ( Constraint . length ( ) > <NUM_LIT> ) return ; else TargetLowering :: LowerAsmOperandForConstraint ( Op , Constraint , Ops , DAG ) ;


<s> return <STR_LIT> ; case TargetOpcode :: G_LSHR : return <STR_LIT> ; case TargetOpcode :: G_ASHR : return <STR_LIT> ; default : return GenericOpc ; } } break ; case <STR_LIT> : switch ( OpSize ) { case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return <STR_LIT> ; case TargetOpcode :: G_FSUB : return <STR_LIT> ; case TargetOpcode :: G_FMUL : return <STR_LIT> ; case TargetOpcode :: G_FDIV : return <STR_LIT> ; default : return GenericOpc ; } case <NUM_LIT> : switch ( GenericOpc ) { case TargetOpcode :: G_FADD : return <STR_LIT> ; case TargetOpcode :: G_FSUB : return <STR_LIT> ; case TargetOpcode :: G_FMUL : return <STR_LIT> ; case TargetOpcode :: G_FDIV : return <STR_LIT> ; case TargetOpcode :: G_OR : return <STR_LIT> ; default :


<s> SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , <STR_LIT> , dl , DAG . getEntryNode ( ) , FudgePtr , MachinePointerInfo :: getConstantPool ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Fild , Fudge ) ;

return DAG . getNode ( <STR_LIT> , dl , DstVT , Add , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> const MCInstrDesc & Desc = TII -> get ( Opcode ) ; BuildMI ( MBB , MBBI , DL , Desc , DstReg ) . addReg ( DstReg , RegState :: Undef ) . addReg ( DstReg , RegState :: Undef ) ; MBBI -> eraseFromParent ( ) ; return true ;


<s> void <ISA_LIT>XCOFFMCAsmInfo :: anchor ( ) {


<s> void <ISA_LIT>InstPrinter :: printBrtarget ( MCInst const * MI , unsigned OpNo , raw_ostream & O ) const { MCOperand const & MO = MI -> getOperand ( OpNo ) ; assert ( MO . isExpr ( ) ) ;

MCExpr const & Expr = * MO . getExpr ( ) ;


<s> function_sym_iterator ( object :: elf_symbol_iterator It , object :: elf_symbol_iterator End , PredicateTy P ) : conditional_iterator < object :: elf_symbol_iterator > ( It , End , P ) {


<s> const DataLayout * getDataLayout ( ) const override { return & DL ;


<s> _mm512_permutex_epi64 ( __m512i __X , const int __I ) { return ( __m512i ) __builtin_ia32_permdi512_mask ( ( __v8di ) __X , __I , ( __v8di ) _mm512_undefined_si512 ( ) , ( __mmask8 ) ( - <NUM_LIT> ) ) ;


<s> while ( -- numregs ) ; ca -> call_cookie |= CALL_COOKIE_INT_REG ( ca -> arg_count [ ( int ) SH_ARG_INT ] - <NUM_LIT> , <NUM_LIT> ) ; } else if ( dwords > numregs ) { int pushregs = numregs ; if ( TARGET_SHCOMPACT ) ca -> stack_regs += numregs ; while ( pushregs < NPARM_REGS ( SImode ) - <NUM_LIT> && ( CALL_COOKIE_INT_REG_GET ( ca -> call_cookie , NPARM_REGS ( SImode ) - pushregs ) == <NUM_LIT> ) ) { ca -> call_cookie &= ~ CALL_COOKIE_INT_REG ( NPARM_REGS ( SImode ) - pushregs , <NUM_LIT> ) ; pushregs ++ ; } if ( numregs == NPARM_REGS ( SImode ) ) ca -> call_cookie |= CALL_COOKIE_INT_REG ( <NUM_LIT> , <NUM_LIT> ) | CALL_COOKIE_STACKSEQ ( numregs - <NUM_LIT> ) ; else ca -> call_cookie |= CALL_COOKIE_STACKSEQ ( numregs ) ; } } if ( GET_SH_ARG_CLASS ( mode2 ) == SH_ARG_FLOAT && ( named || ! ca -> prototype_p ) ) { if ( mode2 == SFmode && ca -> free_single_fp_reg ) ca -> free_single_fp_reg = <NUM_LIT> ; else if ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) { int numfpregs = MIN ( ( GET_MODE_SIZE ( mode2 ) + <NUM_LIT> ) / <NUM_LIT> * <NUM_LIT> , NPARM_REGS ( SFmode ) - ca -> arg_count [ ( int ) SH_ARG_FLOAT ] ) ; ca -> arg_count [ ( int ) SH_ARG_FLOAT ] += numfpregs ; if ( TARGET_SHCOMPACT && ! ca -> prototype_p ) { if ( ca -> outgoing && numregs > <NUM_LIT> ) do { ca -> call_cookie |= ( CALL_COOKIE_INT_REG ( ca -> arg_count [ ( int ) SH_ARG_INT ] - numregs + ( ( numfpregs - <NUM_LIT> ) / <NUM_LIT> ) , <NUM_LIT> + ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] - numfpregs ) / <NUM_LIT> ) ) ; } while ( numfpregs -= <NUM_LIT> ) ; } else if ( mode2 == SFmode && ( named ) && ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) ) ca -> free_single_fp_reg = FIRST_FP_PARM_REG - numfpregs + ca -> arg_count [ ( int ) SH_ARG_FLOAT ] + <NUM_LIT> ; } } return ; }

if ( ( TARGET_HITACHI || ca -> renesas_abi ) && TARGET_FPU_DOUBLE ) {


<s> OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) ) { OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . EmitRawText ( StringRef ( M . getModuleInlineAsm ( ) ) ) ; OutStreamer . AddBlankLine ( ) ; OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ; }


return Kind == k_VectorIndex && VectorIndex . Val < <NUM_LIT> ;


<s> return <STR_LIT> + std :: to_string ( sgx_call_magic_labels_index - <NUM_LIT> ) ;


<s> SMLoc ArchLoc = Parser . getTok ( ) . getLoc ( ) ; getLexer ( ) . Lex ( ) ; unsigned ID = <STR_LIT> ( Arch ) ; if ( ID == <STR_LIT> ) { Error ( ArchLoc , <STR_LIT> + Arch + <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } getTargetStreamer ( ) . emitObjectArch ( ID ) ;

if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) {


<s> unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG . getConstant ( NumBits , TLI . getShiftAmountTy ( SrcOp . getValueType ( ) ) ) ) ) ;


<s> if ( parseVectorLane ( LaneKind , LaneIndex , E ) != MatchOperand_Success ) return MatchOperand_ParseFail ; while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) || Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { if ( ! Spacing ) Spacing = <NUM_LIT> ; else if ( Spacing == <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc AfterMinusLoc = Parser . getTok ( ) . getLoc ( ) ; int EndReg = tryParseRegister ( ) ; if ( EndReg == - <NUM_LIT> ) { Error ( AfterMinusLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) EndReg = getDRegFromQReg ( EndReg ) + <NUM_LIT> ; if ( Reg == EndReg ) continue ; if ( ! <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( EndReg ) ) { Error ( AfterMinusLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Reg > EndReg ) { Error ( AfterMinusLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } VectorLaneTy NextLaneKind ; unsigned NextLaneIndex ; if ( parseVectorLane ( NextLaneKind , NextLaneIndex , E ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind || LaneIndex != NextLaneIndex ) { Error ( AfterMinusLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Count += EndReg - Reg ; Reg = EndReg ; continue ; } Parser . Lex ( ) ; RegLoc = Parser . getTok ( ) . getLoc ( ) ; int OldReg = Reg ; Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg ) ) { if ( ! Spacing ) Spacing = <NUM_LIT> ; else if ( Spacing == <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Reg = getDRegFromQReg ( Reg ) ; if ( Reg != OldReg + <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } ++ Reg ; Count += <NUM_LIT> ; VectorLaneTy NextLaneKind ; unsigned NextLaneIndex ; SMLoc LaneLoc = Parser . getTok ( ) . getLoc ( ) ; if ( parseVectorLane ( NextLaneKind , NextLaneIndex , E ) != MatchOperand_Success ) return MatchOperand_ParseFail ; if ( NextLaneKind != LaneKind || LaneIndex != NextLaneIndex ) { Error ( LaneLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } continue ; } if ( ! Spacing ) Spacing = <NUM_LIT> + ( Reg == OldReg + <NUM_LIT> ) ; if ( Reg != OldReg + Spacing ) { Error ( RegLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } ++ Count ; VectorLaneTy NextLaneKind ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , Subtarget ( STI ) , RI ( STI ) {


<s> for ( unsigned Reg : { RegA , RegB } ) { if ( RI . isSubRegisterEq ( <STR_LIT> , Reg ) ) DE = true ;

else if ( RI . isSubRegisterEq ( <STR_LIT> , Reg ) ) HL = true ;


<s> static bool bfin_can_use_doloop_p ( const widest_int & , const widest_int & iterations_max , unsigned int , bool ) { if ( ! flag_unsafe_loop_optimizations && wi :: geu_p ( iterations_max , <NUM_LIT> ) ) return false ;


raw_svector_ostream ( Name ) << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << uid ;


<s> if ( TARGET_32BIT ) { if ( rs6000_alignment_flags == MASK_ALIGN_NATURAL ) return true ; if ( rs6000_alignment_flags == MASK_ALIGN_POWER ) return true ; return false ; } else {


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , Triple :: OSType _OSType ) : <ISA_LIT>AsmBackend ( T ) , OSType ( _OSType ) {


<s> DenseSet < unsigned > * LiveOuts = InnerRegion -> getLiveOuts ( ) ; SmallVector < unsigned , <NUM_LIT> > OldLiveOuts ; bool IsSingleBB = InnerRegion -> getEntry ( ) == InnerRegion -> getExit ( ) ; for ( auto OLI : * LiveOuts ) { OldLiveOuts . push_back ( OLI ) ; } for ( auto LI : OldLiveOuts ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( LI , TRI ) ) ; if ( ! containsDef ( CodeBB , InnerRegion , LI ) || ( ! IsSingleBB && ( getDefInstr ( LI ) -> getParent ( ) == LRegion -> getExit ( ) ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; unsigned Reg = LI ;

if ( Reg != InnerRegion -> getBBSelectRegOut ( ) ) {


<s> mips_multi_member empty ; memset ( & empty , <NUM_LIT> , sizeof ( empty ) ) ; return mips_multi_members . safe_push ( empty ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediate64 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediate16 ( Op . getImm ( ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( ! isUInt < <NUM_LIT> > ( Op . getImm ( ) ) && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { printImmediate32 ( Op . getImm ( ) , STI , O ) ; break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : printImmediateV216 ( Op . getImm ( ) , STI , O ) ; break ; case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_PCREL : O << formatDec ( Op . getImm ( ) ) ; break ; case MCOI :: OPERAND_REGISTER : O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; unsigned RCBits = <STR_LIT> ( MRI . getRegClass ( RCID ) ) ; if ( RCBits == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , STI , O ) ; else if ( RCBits == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , STI , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else { O << <STR_LIT> ; } switch ( MI -> getOpcode ( ) ) { default : break ;


<s> MachineBasicBlock * BB = I . getParent ( ) ; BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ;

for ( Register Reg : { DstReg , Src0Reg , Src1Reg } ) MRI -> setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ;


<s> if ( Subtarget -> hasSSE41 ( ) ) { SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } MVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; MVT EVT = ( <STR_LIT> ) ( VT . getSimpleVT ( ) + <NUM_LIT> ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; MVT MaskVT = <STR_LIT> ( <NUM_LIT> ) ;

SmallVector < SDValue , <NUM_LIT> > IdxVec ;


<s> return __builtin_aarch64_fixuns_trunchfhi_us ( __a ) ;


<s> <ISA_LIT>LongBranch ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) , ABI ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ) , LongBranchSeqSize ( ! IsPIC ? <NUM_LIT> : ( ABI == <ISA_LIT>Subtarget :: N64 ? <NUM_LIT> : <NUM_LIT> ) ) {


<s> bool Changed = false ; for ( Function & F : M ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( expandMemIntrinsicUses ( F ) ) Changed = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Changed |= makeLIDRangeMetadata ( F ) ;


<s> return ( ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> || ty == <STR_LIT> ) ;


<s> unsigned j = <NUM_LIT> ; if ( attr & RS6000_BTC_QUAD && d -> code != MMA_BUILTIN_DISASSEMBLE_ACC_INTERNAL && d -> code != VSX_BUILTIN_DISASSEMBLE_PAIR_INTERNAL ) j = <NUM_LIT> ; for ( ; j < ( unsigned ) insn_data [ icode ] . n_operands ; j ++ ) { machine_mode mode = insn_data [ icode ] . operand [ j ] . mode ; if ( gimple_func && mode == XOmode ) op [ nopnds ++ ] = build_pointer_type ( vector_quad_type_node ) ; else if ( gimple_func && mode == OOmode && d -> code == VSX_BUILTIN_ASSEMBLE_PAIR ) op [ nopnds ++ ] = build_pointer_type ( vector_pair_type_node ) ; else op [ nopnds ++ ] = builtin_mode_to_type [ mode ] [ <NUM_LIT> ] ; } } switch ( nopnds ) { case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> : type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ; break ; case <NUM_LIT> :

type = build_function_type_list ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , NULL_TREE ) ;


<s> return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode ( ) ;


<s> unsigned Kind = Fixup . getKind ( ) ; switch ( Modifier ) { case MCSymbolRefExpr :: VK_None : if ( IsPCRel ) return getPCRelReloc ( Kind ) ; return getAbsoluteReloc ( Kind ) ; case MCSymbolRefExpr :: VK_NTPOFF : assert ( ! IsPCRel && <STR_LIT> ) ; return getTLSLEReloc ( Kind ) ; case MCSymbolRefExpr :: VK_GOT : if ( IsPCRel && Kind == <STR_LIT> ) return ELF :: R_390_GOTENT ; llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_PLT : assert ( IsPCRel && <STR_LIT> ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;

return new <ISA_LIT>MCAsmBackend ( OSABI ) ;


<s> static std :: unique_ptr < AMDGPUOperand > CreateImm ( int64_t Val , SMLoc Loc , enum ImmTy Type = ImmTyNone , bool IsFPImm = false ) { auto Op = llvm :: make_unique < AMDGPUOperand > ( Immediate ) ; Op -> Imm . Val = Val ; Op -> Imm . IsFPImm = IsFPImm ;


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; if ( Subtarget . hasSSE3 ( ) ) { if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ;


<s> for ( unsigned OI = <NUM_LIT> , OE = MI . getNumOperands ( ) ; OI < OE ; ++ OI ) { assert ( MI . getOperand ( OI ) . isReg ( ) && <STR_LIT> ) ; switch ( MI . getOperand ( OI ) . getReg ( ) ) {


<s> void printRegister ( const MachineOperand & MO , bool R0AsZero ) { unsigned RegNo = MO . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( RegNo ) && <STR_LIT> ) ;


<s> const MachineOperand & MO = MI . getOperand ( i ) ;

if ( ( MO . isReg ( ) && MO . isImplicit ( ) ) || MO . isRegMask ( ) ) NewMI . addOperand ( MF , MO ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>MachObjectWriter ( raw_ostream & OS , bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) {

return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( Is64Bit , CPUType , CPUSubtype ) , OS , false ) ;


<s> } Phi -> setIncomingValue ( i , BoolFalse ) ; Value * PhiArg = handleLoopCondition ( Incoming , Broken , L ) ; NewPhi -> addIncoming ( PhiArg , From ) ; } BasicBlock * IDom = DT -> getNode ( Parent ) -> getIDom ( ) -> getBlock ( ) ; for ( unsigned i = <NUM_LIT> , e = Phi -> getNumIncomingValues ( ) ; i != e ; ++ i ) { Value * Incoming = Phi -> getIncomingValue ( i ) ; if ( Incoming != BoolTrue ) continue ; BasicBlock * From = Phi -> getIncomingBlock ( i ) ; if ( From == IDom ) { CallInst * OldEnd = dyn_cast < CallInst > ( Parent -> getFirstInsertionPt ( ) ) ; if ( OldEnd && OldEnd -> getCalledFunction ( ) == EndCf ) { Value * Args [ ] = { OldEnd -> getArgOperand ( <NUM_LIT> ) , NewPhi } ; Ret = CallInst :: Create ( ElseBreak , Args , <STR_LIT> , OldEnd ) ; continue ; } } TerminatorInst * Insert = From -> getTerminator ( ) ; Value * PhiArg = CallInst :: Create ( Break , Broken , <STR_LIT> , Insert ) ; NewPhi -> setIncomingValue ( i , PhiArg ) ; } eraseIfUnused ( Phi ) ; return Ret ; } else if ( Instruction * Inst = dyn_cast < Instruction > ( Cond ) ) { BasicBlock * Parent = Inst -> getParent ( ) ; Instruction * Insert ; if ( L -> contains ( Inst ) ) { Insert = Parent -> getTerminator ( ) ; } else { Insert = L -> getHeader ( ) -> getFirstNonPHIOrDbgOrLifetime ( ) ; }


<s> bool isMem ( ) const override { return false ;


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { unsigned PowerOfTwo = <NUM_LIT> ; SDValue NewMulConst ; if ( canExtractShiftFromMul ( N , <NUM_LIT> , PowerOfTwo , NewMulConst ) ) { HandleSDNode Handle ( N ) ; replaceDAGValue ( N . getOperand ( <NUM_LIT> ) , NewMulConst ) ; BaseReg = Handle . getValue ( ) ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , PowerOfTwo ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } } <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return false ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal ) , SDLoc ( N ) , <STR_LIT> ) ; return true ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const { const MCOperand & MCOp = Inst . getOperand ( OpNo ) ;

if ( MCOp . isReg ( ) || MCOp . isImm ( ) ) return getMachineOpValue ( Inst , MCOp , Fixups , SubtargetInfo ) ;


<s> void BTFDebug :: processDeclAnnotations ( DINodeArray Annotations , uint32_t BaseTypeId , int ComponentIdx ) { if ( ! Annotations ) return ; for ( const Metadata * Annotation : Annotations -> operands ( ) ) { const MDNode * MD = cast < MDNode > ( Annotation ) ; const MDString * Name = cast < MDString > ( MD -> getOperand ( <NUM_LIT> ) ) ; if ( ! Name -> getString ( ) . equals ( <STR_LIT> ) ) continue ;

const MDString * Value = cast < MDString > ( MD -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( CallerF . getReturnType ( ) -> is<ISA_LIT>_FP80Ty ( ) && ! RetTy -> is<ISA_LIT>_FP80Ty ( ) ) return false ; CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; bool IsCalleeWin64 = Subtarget . isCallingConvWin64 ( CalleeCC ) ; bool IsCallerWin64 = Subtarget . isCallingConvWin64 ( CallerCC ) ; if ( IsCalleeWin64 != IsCallerWin64 ) return false ; if ( DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) { if ( canGuaranteeTCO ( CalleeCC ) && CCMatch ) return true ; return false ; } const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; if ( RegInfo -> needsStackRealignment ( MF ) ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; LLVMContext & C = * DAG . getContext ( ) ; if ( isVarArg && ! Outs . empty ( ) ) { if ( IsCalleeWin64 || IsCallerWin64 ) return false ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) if ( ! ArgLocs [ i ] . isRegLoc ( ) ) return false ; } bool Unused = false ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) { if ( ! Ins [ i ] . Used ) { Unused = true ; break ; } } if ( Unused ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CalleeCC , false , MF , RVLocs , C ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , RetCC_<ISA_LIT> , RetCC_<ISA_LIT> ) ) return false ; const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( ! CCMatch ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } unsigned StackArgsSize = <NUM_LIT> ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; if ( IsCalleeWin64 ) CCInfo . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; return <NUM_LIT> ;


<s> __ev64_opaque__ t ; t = __ev_mwhssf ( a , b ) ; return __ev_mwsmian ( t , ( ( __ev64_s32__ ) { <NUM_LIT> , <NUM_LIT> } ) ) ;


<s> const uint8_t * <ISA_LIT>To<ISA_LIT>Stub :: getContent ( ) const { return reinterpret_cast < const uint8_t * > ( m_pData ) ;


<s> if ( std :: next ( I ) != End || ! I . getOperand ( ) . getParent ( ) -> isPHI ( ) ) return false ; MachineInstr * OnePhi = I . getOperand ( ) . getParent ( ) ; for ( unsigned j = <NUM_LIT> , f = OnePhi -> getNumOperands ( ) ; j != f ; ++ j ) { const MachineOperand & OPO = OnePhi -> getOperand ( j ) ; if ( ! OPO . isReg ( ) || ! OPO . isDef ( ) ) continue ; unsigned OPReg = OPO . getReg ( ) ; use_nodbg_iterator nextJ ; for ( use_nodbg_iterator J = MRI -> use_nodbg_begin ( OPReg ) ; J != End ; J = nextJ ) { nextJ = std :: next ( J ) ; MachineOperand & Use = J . getOperand ( ) ; MachineInstr * UseMI = Use . getParent ( ) ;


<s> if ( isa < AddOperator > ( Op ) && ( ! isa < Instruction > ( Op ) || FuncInfo . MBBMap [ cast < Instruction > ( Op ) -> getParent ( ) ] == FuncInfo . MBB ) && isa < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . Offset = TmpOffset ; if ( <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const AllocaInst * AI = cast < AllocaInst > ( Obj ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { Addr . BaseType = Address :: FrameIndexBase ; Addr . Base . FI = SI -> second ; return true ; } break ; } } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( Obj ) ) { unsigned Tmp = <ISA_LIT>MaterializeGV ( GV , TLI . getValueType ( Obj -> getType ( ) ) ) ; if ( Tmp == <NUM_LIT> ) return false ; Addr . Base . Reg = Tmp ; return true ; }

if ( Addr . Base . Reg == <NUM_LIT> ) Addr . Base . Reg = getRegForValue ( Obj ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ;

TargetRegistry :: RegisterELFStreamer ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCELFStreamer ) ;


<s> tree addr ; if ( ! MEM_P ( pat ) ) return false ; addr = MEM_EXPR ( pat ) ; if ( ! addr ) return false ; if ( TREE_CODE ( addr ) == MEM_REF || TREE_CODE ( addr ) == VAR_DECL ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( addr ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; } if ( TREE_CODE ( addr ) == MEM_REF ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , <NUM_LIT> ) ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ; attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( TREE_OPERAND ( addr , <NUM_LIT> ) ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return true ;


<s> Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; UseDataRegionDirectives = true ; SupportsDebugInformation = true ; ExceptionsType = ( TheTriple . isOSDarwin ( ) && ! TheTriple . isWatchABI ( ) ) ? ExceptionHandling :: SjLj : ExceptionHandling :: DwarfCFI ; UseIntegratedAssembler = true ;


<s> Candidates . remove_if ( [ Reg , this ] ( const Candidate & C ) { return C . MI -> readsRegister ( Reg , TRI ) ; } ) ;


<s> auto & HST = static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; auto & HRI = * HST . getRegisterInfo ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; MachineBasicBlock * PrologB = & MF . front ( ) , * EpilogB = nullptr ; if ( EnableShrinkWrapping ) findShrunkPrologEpilog ( MF , PrologB , EpilogB ) ; bool PrologueStubs = false ; insertCSRSpillsInBlock ( * PrologB , CSI , HRI , PrologueStubs ) ; insertPrologueInBlock ( * PrologB , PrologueStubs ) ; if ( EpilogB ) { insertCSRRestoresInBlock ( * EpilogB , CSI , HRI ) ; insertEpilogueInBlock ( * EpilogB ) ; } else { for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertCSRRestoresInBlock ( B , CSI , HRI ) ; for ( auto & B : MF ) if ( B . isReturnBlock ( ) ) insertEpilogueInBlock ( B ) ; for ( auto & B : MF ) { if ( B . empty ( ) ) continue ; MachineInstr * RetI = getReturn ( B ) ; if ( ! RetI || isRestoreCall ( RetI -> getOpcode ( ) ) ) continue ; for ( auto & R : CSI ) RetI -> addOperand ( MachineOperand :: CreateReg ( R . getReg ( ) , false , true ) ) ; } } if ( EpilogB ) { unsigned MaxBN = <NUM_LIT> ; for ( auto & B : MF ) if ( B . getNumber ( ) >= <NUM_LIT> ) MaxBN = std :: max ( MaxBN , unsigned ( B . getNumber ( ) ) ) ; BitVector DoneT ( MaxBN + <NUM_LIT> ) , DoneF ( MaxBN + <NUM_LIT> ) , Path ( MaxBN + <NUM_LIT> ) ; updateExitPaths ( * EpilogB , EpilogB , DoneT , DoneF , Path ) ;


<s> const unsigned MMOpc = Subtarget . has<ISA_LIT>32r6 ( ) ? <STR_LIT> : <STR_LIT> ; const unsigned Opc = Subtarget . inMicro<ISA_LIT>Mode ( ) ? MMOpc : <STR_LIT> ;

return BuildMI ( MBB , MI , DL , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> unsigned addr = <NUM_LIT> ; addr |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addr |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( DecodeGPR8RegisterClass ( Inst , reg , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( addr ) ) ; return MCDisassembler :: Success ;


<s> MCInstPrinter ( MAI , MRI ) { setAvailableFeatures ( STI . getFeatureBits ( ) ) ;


<s> else if ( GET_CODE ( operands [ i ] ) == MEM && ( GET_CODE ( XEXP ( operands [ i ] , <NUM_LIT> ) ) == POST_INC ) ) { rtx addr = XEXP ( operands [ i ] , <NUM_LIT> ) ; operands [ i ] = low [ i ] = gen_rtx_MEM ( SImode , addr ) ; if ( which_alternative == <NUM_LIT> && i == <NUM_LIT> ) { addr = XEXP ( operands [ i ] , <NUM_LIT> ) ; operands [ i + <NUM_LIT> ] = low [ i + <NUM_LIT> ] = gen_rtx_MEM ( SImode , addr ) ; } } else { low [ i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , DImode ) ; operands [ i ] = operand_subword ( operands [ i ] , <NUM_LIT> , <NUM_LIT> , DImode ) ; } }


<s> void arc_initialize_trampoline ( rtx tramp ATTRIBUTE_UNUSED , rtx fnaddr ATTRIBUTE_UNUSED , rtx cxt ATTRIBUTE_UNUSED ) {


<s> OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ;


<s> } unsigned Type = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Type = ELF :: R_ARM_MOVT_PREL ; break ; case <STR_LIT> : Type = ELF :: R_ARM_MOVW_PREL_NC ; break ; }


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; } else { <ISA_LIT>FunctionInfo * AFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ;

SDValue Chain = Result . getValue ( <NUM_LIT> ) ;


<s> EquivalenceClasses < Chain * > EC ; for ( auto & I : AllChains ) EC . insert ( I . get ( ) ) ; for ( auto & I : AllChains ) for ( auto & J : AllChains ) if ( I != J && I -> rangeOverlapsWith ( * J ) ) EC . unionSets ( I . get ( ) , J . get ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << EC . getNumClasses ( ) << <STR_LIT> ) ; std :: vector < std :: vector < Chain * > > V ; for ( auto I = EC . begin ( ) , E = EC . end ( ) ; I != E ; ++ I ) { std :: vector < Chain * > Cs ( EC . member_begin ( I ) , EC . member_end ( ) ) ; if ( Cs . empty ( ) ) continue ; V . push_back ( std :: move ( Cs ) ) ; } llvm :: sort ( V . begin ( ) , V . end ( ) , [ ] ( const std :: vector < Chain * > & A , const std :: vector < Chain * > & B ) { return A . front ( ) -> startsBefore ( B . front ( ) ) ; } ) ;


<s> assert ( NumOperands == <NUM_LIT> && <STR_LIT> ) ; unsigned Op0 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; unsigned Op1 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; bool KillsOp0 = MI . killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ;


<s> if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ) Ret += <STR_LIT> ; else if ( ABI != <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; Ret += <STR_LIT> ; Ret += <STR_LIT> ; if ( TT . isOSNaCl ( ) || ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS16 ) Ret += <STR_LIT> ; else if ( ABI == <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ;


<s> uint64_t Val = - MaxAlign ; unsigned AndOp = getANDriOpcode ( Uses64BitFramePtr , Val ) ;

MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( AndOp ) , Reg ) . addReg ( Reg ) . addImm ( Val ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> static scalar_int_mode aarch64_sve_element_int_mode ( machine_mode mode ) { poly_uint64 vector_bits = ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ? BITS_PER_SVE_VECTOR : GET_MODE_BITSIZE ( mode ) ) ; unsigned int elt_bits = vector_element_size ( vector_bits , GET_MODE_NUNITS ( mode ) ) ;

return int_mode_for_size ( elt_bits , <NUM_LIT> ) . require ( ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == VT && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == VT && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; ArrayRef < int > LoMask = Mask . slice ( <NUM_LIT> , Mask . size ( ) / <NUM_LIT> ) ; ArrayRef < int > HiMask = Mask . slice ( Mask . size ( ) / <NUM_LIT> ) ; int NumElements = VT . getVectorNumElements ( ) ; int SplitNumElements = NumElements / <NUM_LIT> ; MVT ScalarVT = VT . getScalarType ( ) ; MVT SplitVT = <STR_LIT> ( ScalarVT , NumElements / <NUM_LIT> ) ; SDValue LoV1 = DAG . getNode ( <STR_LIT> , DL , SplitVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue HiV1 = DAG . getNode ( <STR_LIT> , DL , SplitVT , V1 , DAG . getIntPtrConstant ( SplitNumElements ) ) ;

SDValue LoV2 = DAG . getNode ( <STR_LIT> , DL , SplitVT , V2 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; bool Narrow = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ;

if ( Narrow ) transform ( Regs , Regs . begin ( ) , WidenVector ( * CurDAG ) ) ;


<s> return new <ISA_LIT>TargetAsmStreamer ( S , OS ) ;


<s> nAltivecParamsAtEnd = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { <STR_LIT> Flags = Outs [ i ] . Flags ; EVT ArgVT = Outs [ i ] . VT ; if ( ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> || ArgVT == <STR_LIT> ) { if ( ! isVarArg && ! is<ISA_LIT>64 ) { nAltivecParamsAtEnd ++ ; continue ; } NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; } NumBytes += CalculateStackSlotSize ( ArgVT , Flags , PtrByteSize ) ; } if ( nAltivecParamsAtEnd ) { NumBytes = ( ( NumBytes + <NUM_LIT> ) / <NUM_LIT> ) * <NUM_LIT> ; NumBytes += <NUM_LIT> * nAltivecParamsAtEnd ; } NumBytes = std :: max ( NumBytes , <ISA_LIT>FrameLowering :: getMinCallFrameSize ( is<ISA_LIT>64 , true ) ) ; if ( CC == CallingConv :: Fast && DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) { unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; NumBytes = ( NumBytes + AlignMask ) & ~ AlignMask ;


<s> <ISA_LIT>PreAllocateWWMRegs ( ) : MachineFunctionPass ( ID ) {


<s> op = reg_equiv_memory_loc ( REGNO ( tmp ) ) ; if ( op == <NUM_LIT> ) return <NUM_LIT> ; } }


<s> root -> dump ( dbgs ( ) , <NUM_LIT> , true ) ; dbgs ( ) << <STR_LIT> ;


<s> GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA ) ; std :: pair < SDValue , SDValue > CallResult = lowerTLSCall ( GOTEntry , dl , DAG ) ; return CallResult . first ; } if ( Model == TLSModel :: LocalDynamic ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue GOTPtr ; if ( is64bit ) { SDValue GOTReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTReg , TGA ) ; } else { GOTPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; } SDValue GOTEntry = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOTPtr , TGA ) ; std :: pair < SDValue , SDValue > CallResult = lowerTLSCall ( GOTEntry , dl , DAG ) ; SDValue TLSAddr = CallResult . first ; SDValue Chain = CallResult . second ; SDValue DtvOffsetHi = DAG . getNode ( <STR_LIT> , dl , PtrVT , Chain , TLSAddr , TGA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DtvOffsetHi , TGA ) ; }


<s> return __builtin_aarch64_frint32zdf ( __a ) ;


<s> for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return true ; } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && isCalleeSavedRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ; return false ;


<s> gcc_assert ( CONST_INT_P ( exp ) ) ; if ( standard_sse_constant_p ( exp , V2DImode ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; return ix86_cost -> sse_load [ <NUM_LIT> ] ;


<s> return parseAddress ( Operands , BDVMem , <STR_LIT> , ADDR64Reg ) ;


<s> static inline uint8_t encodeAdvSIMDModImmType5 ( uint64_t Imm ) {


<s> if ( ! mi_match ( Src , MRI , m_OneNonDBGUse ( m_any_of ( m_GAShr ( m_Reg ( ShiftSrc ) , m_ICst ( ShiftImm ) ) , m_GLShr ( m_Reg ( ShiftSrc ) , m_ICst ( ShiftImm ) ) ) ) ) ) return false ; if ( ShiftImm < <NUM_LIT> || ShiftImm + Width > Ty . getSizeInBits ( ) ) return false ; MatchInfo = [ = ] ( MachineIRBuilder & B ) { auto Cst1 = B . buildConstant ( Ty , ShiftImm ) ; auto Cst2 = B . buildConstant ( Ty , Width ) ; B . buildInstr ( TargetOpcode :: G_SBFX , { Dst } , { ShiftSrc , Cst1 , Cst2 } ) ;


<s> case ELF :: R_<ISA_LIT>_64_32S : case ELF :: R_<ISA_LIT>_64_64 : return false ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { switch ( RelTy ) { case ELF :: R_386_PC32 : return true ; case ELF :: R_386_32 : return false ; default : llvm_unreachable ( <STR_LIT> ) ; } } return <NUM_LIT> ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineFunction & MF = * MBB -> getParent ( ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; MachineOperand & OffsetMO = MI -> getOperand ( <NUM_LIT> ) ; uint64_t Offset = ( MFFrame . getMaxCallFrameSize ( ) + <STR_LIT> + OffsetMO . getImm ( ) ) ; unsigned NewOpcode = getOpcodeForOffset ( <STR_LIT> , Offset ) ; assert ( NewOpcode && <STR_LIT> ) ;


<s> if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ;

else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV ) ;


<s> using namespace TargetOpcode ; const LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; const LLT V2S16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT S64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT P1 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; const LLT P2 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; setAction ( { G_ADD , S32 } , Legal ) ; setAction ( { G_AND , S32 } , Legal ) ; setAction ( { G_BITCAST , V2S16 } , Legal ) ; setAction ( { G_BITCAST , <NUM_LIT> , S32 } , Legal ) ; setAction ( { G_BITCAST , S32 } , Legal ) ; setAction ( { G_BITCAST , <NUM_LIT> , V2S16 } , Legal ) ; setAction ( { G_CONSTANT , S1 } , Legal ) ; setAction ( { G_CONSTANT , S32 } , Legal ) ;

setAction ( { G_CONSTANT , S64 } , Legal ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {


<s> if ( FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN && DECL_NAME ( current_function_decl ) && MAIN_NAME_P ( DECL_NAME ( current_function_decl ) ) && DECL_FILE_SCOPE_P ( current_function_decl ) ) { cfun -> machine -> force_align_arg_pointer = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; return copy_to_reg ( cfun -> machine -> force_align_arg_pointer ) ; }


<s> do { FromBits *= <NUM_LIT> ; EVT OutVT = <STR_LIT> ( <STR_LIT> ( FromBits ) , <STR_LIT> / FromBits ) ; PackedOp = DAG . getNode ( UnpackHigh , SDLoc ( PackedOp ) , OutVT , PackedOp ) ; } while ( FromBits != ToBits ) ;


<s> Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> bool isMemMode5 ( ) const { if ( ! isMemory ( ) || Mem . OffsetIsReg || Mem . OffsetRegShifted || Mem . Writeback || Mem . Negative ) return false ; if ( ! Mem . Offset ) return true ;

const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Mem . Offset ) ;


<s> static void force_into_acc ( rtx src , rtx_insn * before ) { machine_mode mode = GET_MODE ( src ) ; rtx move ; if ( REG_P ( src ) && REGNO ( src ) < <NUM_LIT> ) return ;

move = mode == QImode ? gen_movqi ( A , src ) : gen_movhi ( AX , src ) ;


<s> if ( CouldCall ) HintNum |= <NUM_LIT> ; if ( CouldJump ) HintNum |= <NUM_LIT> ; assert ( HintNum != <NUM_LIT> && <STR_LIT> ) ; auto MBBI = MBB . begin ( ) ; if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) return ; BuildMI ( MBB , MBB . begin ( ) , MBB . findDebugLoc ( MBB . begin ( ) ) , TII -> get ( <STR_LIT> ) ) . addImm ( HintNum ) ;


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return & FrameLowering ;


<s> if ( kind1 != kind2 ) return <NUM_LIT> ; if ( ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type2 ) ) ) return <NUM_LIT> ;


<s> if ( bitmap_bit_p ( edge_components , <NUM_LIT> ) && bitmap_bit_p ( DF_LIVE_IN ( e -> dest ) , <NUM_LIT> ) ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , e -> dest -> index ) ;

bitmap_clear_bit ( components , <NUM_LIT> ) ;


<s> if ( match ( I , m_Select ( m_Cmp ( CurrentPred , m_Value ( ) , m_Value ( ) ) , m_Value ( ) , m_Value ( ) ) ) ) VecPred = CurrentPred ; } if ( CmpInst :: isIntPredicate ( VecPred ) ) { static const auto ValidMinMaxTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; } static const TypeConversionCostTblEntry VectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * AmortizationCost


<s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; assert ( Op . isImm ( ) || Op . isExpr ( ) ) ; if ( Op . isImm ( ) ) {


<s> enum m32r_function_type fn_type = m32r_compute_function_type ( current_function_decl ) ; if ( M32R_INTERRUPT_P ( fn_type ) ) fprintf ( file , <STR_LIT> , ASM_COMMENT_START ) ; if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( size ) ;


<s> std :: vector < const GlobalVariable * > Items = ExternalVarDefs ; if ( ! Items . size ( ) ) return ; OutStreamer . AddComment ( <STR_LIT> ) ; OutStreamer . AddBlankLine ( ) ;

for ( unsigned j = <NUM_LIT> ; j < Items . size ( ) ; j ++ ) OutStreamer . EmitRawText ( MAI -> getGlobalDirective ( ) + Twine ( Mang -> getSymbol ( Items [ j ] ) -> getName ( ) ) ) ;


<s> case CONST_VECTOR : case CONST_DOUBLE : case CONST_INT : case CONST_WIDE_INT : if ( reg_class_subset_p ( GENERAL_REGS , rclass ) && legitimate_reload_constant_p ( op ) ) return GENERAL_REGS ; else if ( reg_class_subset_p ( ADDR_REGS , rclass ) && legitimate_reload_constant_p ( op ) ) return ADDR_REGS ; else if ( reg_class_subset_p ( FP_REGS , rclass ) && legitimate_reload_fp_constant_p ( op ) ) return FP_REGS ; else if ( reg_class_subset_p ( VEC_REGS , rclass ) && legitimate_reload_vector_constant_p ( op ) ) return VEC_REGS ; return NO_REGS ; case CONST : if ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) { if ( flag_pic && reg_class_subset_p ( ADDR_REGS , rclass ) ) return ADDR_REGS ; else return NO_REGS ; } case LABEL_REF : case SYMBOL_REF : if ( ! legitimate_reload_constant_p ( op ) ) return NO_REGS ;


<s> bool ir_p ( rtx op ) { if ( GET_CODE ( op ) != MEM ) return false ; return ( REG_P ( XEXP ( op , <NUM_LIT> ) ) && z8k_reg_ok_for_base_p ( XEXP ( op , <NUM_LIT> ) ) ) || ( reload_in_progress && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == REG && REGNO ( op ) >= FIRST_PSEUDO_REGISTER ) ;


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) {

return new <ISA_LIT>TargetELFStreamer ( S , STI ) ;


<s> if ( IsStrict ) { Src = DAG . getNode ( <STR_LIT> , dl , { <STR_LIT> , <STR_LIT> } , { Chain , Src } ) ; Chain = Src . getValue ( <NUM_LIT> ) ; } else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; } SDValue Conv ; unsigned Opc = <STR_LIT> ; switch ( Op . getSimpleValueType ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = IsSigned ? <STR_LIT> : ( Subtarget . hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ) ; break ; case <STR_LIT> : assert ( ( IsSigned || Subtarget . hasFPCVT ( ) ) && <STR_LIT> ) ;

Opc = IsSigned ? <STR_LIT> : <STR_LIT> ;


<s> if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; } OutOps . push_back ( Op0 ) ;


<s> <ISA_LIT>ELFWriterInfo :: <ISA_LIT>ELFWriterInfo ( bool is64Bit_ , bool isLittleEndian_ ) : TargetELFWriterInfo ( is64Bit_ , isLittleEndian_ ) {


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_store_si128 ( __m128i * __P , __m128i __B ) { assert ( ( ( unsigned long ) __P & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> CalleeSaveStackSlotSize = <NUM_LIT> ; CommentString = <STR_LIT> ;


<s> if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return getZeroVector ( N -> getSimpleValueType ( <NUM_LIT> ) , Subtarget , DAG , SDLoc ( N ) ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , DAG , Subtarget ) ) return Res ; } return SDValue ( ) ;


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) {

TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target , create<ISA_LIT>Disassembler ) ;


<s> case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgIn = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; CFRegNode . push_back ( ArgIn . getValue ( ArgIn -> getNumValues ( ) - <NUM_LIT> ) ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > StackSlotSize ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , LRSaveSize + VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; ArgIn = DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } const ArgDataPair ADP = { ArgIn , Ins [ i ] . Flags } ; ArgData . push_back ( ADP ) ; } if ( isVarArg ) { static const MCPhysReg ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FirstVAReg = CCInfo . getFirstUnallocated ( ArgRegs , array_lengthof ( ArgRegs ) ) ; if ( FirstVAReg < array_lengthof ( ArgRegs ) ) { int offset = <NUM_LIT> ; for ( int i = array_lengthof ( ArgRegs ) - <NUM_LIT> ; i >= ( int ) FirstVAReg ; -- i ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , offset , true ) ; if ( i == ( int ) FirstVAReg ) { XFI -> setVarArgsFrameIndex ( FI ) ; } offset -= StackSlotSize ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; CFRegNode . push_back ( Val . getValue ( Val -> getNumValues ( ) - <NUM_LIT> ) ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; } } else { XFI -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , LRSaveSize + CCInfo . getNextStackOffset ( ) , true ) ) ; }


<s> if ( Overflow != <NUM_LIT> ) { MachineBasicBlock :: iterator OldInsPt = B . getInsertPt ( ) ; MachineBasicBlock & OldMBB = B . getMBB ( ) ; B . setInstr ( * OffsetDef ) ; if ( ! BaseReg ) { BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( BaseReg ) . addImm ( Overflow ) ; } else { Register OverflowVal = MRI -> createVirtualRegister ( & <STR_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( OverflowVal ) . addImm ( Overflow ) ; Register NewBaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; TII . getAddNoCarry ( B . getMBB ( ) , B . getInsertPt ( ) , B . getDebugLoc ( ) , NewBaseReg ) . addReg ( BaseReg ) . addReg ( OverflowVal , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; BaseReg = NewBaseReg ; } B . setInsertPt ( OldMBB , OldInsPt ) ; } return std :: make_tuple ( BaseReg , ImmOffset , TotalConstOffset ) ;


<s> static DecodeStatus DecodeQQRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = QQDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseSVEPattern ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc SS = getLoc ( ) ; const AsmToken & TokE = getTok ( ) ; bool IsHash = TokE . is ( AsmToken :: Hash ) ; if ( ! IsHash && TokE . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int64_t Pattern ; if ( IsHash ) { Lex ( ) ; const MCExpr * ImmVal ; SS = getLoc ( ) ; if ( Parser . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; auto * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return MatchOperand_ParseFail ; Pattern = MCE -> getValue ( ) ; } else { auto Pat = <STR_LIT> ( TokE . getString ( ) ) ; if ( ! Pat ) return MatchOperand_NoMatch ; Lex ( ) ; Pattern = Pat -> Encoding ; assert ( Pattern >= <NUM_LIT> && Pattern < <NUM_LIT> ) ;


<s> return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ;


<s> int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ;


<s> VariantKind getKind ( ) const { return Kind ;


<s> return true ; case <STR_LIT> : CC = <STR_LIT> ; std :: swap ( LHS , RHS ) ; return true ; case <STR_LIT> : CC = <STR_LIT> ; std :: swap ( LHS , RHS ) ;


<s> } else if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ; } else if ( VT == <STR_LIT> ) { if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return Op ; } return SDValue ( ) ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int SpillSlotOffset = getOffsetOfLocalArea ( ) + <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( hasFP ( MF ) ) { SpillSlotOffset -= SlotSize ; MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; Register FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i < e ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } }


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ;


<s> x = avoid_constant_pool_reference ( x ) ; if ( UNARY_P ( x ) ) { rtx x0 = mips16e_collect_propagate_value ( XEXP ( x , <NUM_LIT> ) , reg_values ) ; return simplify_gen_unary ( GET_CODE ( x ) , GET_MODE ( x ) , x0 , GET_MODE ( XEXP ( x , <NUM_LIT> ) ) ) ; } if ( ARITHMETIC_P ( x ) ) {


<s> const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const int SMovRelWaitStates = <NUM_LIT> ; auto IsHazardFn = [ TII ] ( MachineInstr * MI ) { return TII -> isSALU ( * MI ) ;


<s> for ( unsigned int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ( LEGACY_SSE_REGNO_P ( regno ) || ( TARGET_64BIT && ( REX_SSE_REGNO_P ( regno ) || ( TARGET_AVX512F && EXT_REX_SSE_REGNO_P ( regno ) ) ) ) ) && ! TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) return NULL ;


<s> SMLoc S = Token . getLoc ( ) ; if ( Token . isNot ( AsmToken :: Dollar ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Token . is ( AsmToken :: Identifier ) ) { if ( searchSymbolAlias ( Operands ) ) return MatchOperand_Success ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MatchOperand_NoMatch ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; OperandMatchResultTy ResTy = MatchAnyRegisterWithoutDollar ( Operands , S ) ; if ( ResTy == MatchOperand_Success ) { Parser . Lex ( ) ; Parser . Lex ( ) ; } return ResTy ;


<s> MachineInstr & BLR = * MBBI ; assert ( isBLR ( BLR ) ) ; unsigned BLOpcode ; Register Reg ; bool RegIsKilled ; switch ( BLR . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : BLOpcode = <STR_LIT> ; Reg = BLR . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> ) ; RegIsKilled = BLR . getOperand ( <NUM_LIT> ) . isKill ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } DebugLoc DL = BLR . getDebugLoc ( ) ; MachineFunction & MF = * MBBI -> getMF ( ) ; MCContext & Context = MBB . getParent ( ) -> getContext ( ) ; auto ThunkIt = llvm :: find_if ( SLSBLRThunks , [ Reg ] ( auto T ) { return T . Reg == Reg ; } ) ; assert ( ThunkIt != std :: end ( SLSBLRThunks ) ) ; MCSymbol * Sym = Context . getOrCreateSymbol ( ThunkIt -> Name ) ; MachineInstr * BL = BuildMI ( MBB , MBBI , DL , TII -> get ( BLOpcode ) ) . addSym ( Sym ) ; int ImpLROpIdx = - <NUM_LIT> ; int ImpSPOpIdx = - <NUM_LIT> ; for ( unsigned OpIdx = BL -> getNumExplicitOperands ( ) ; OpIdx < BL -> getNumOperands ( ) ; OpIdx ++ ) { MachineOperand Op = BL -> getOperand ( OpIdx ) ; if ( ! Op . isReg ( ) ) continue ; if ( Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) ) ImpLROpIdx = OpIdx ; if ( Op . getReg ( ) == <STR_LIT> && ! Op . isDef ( ) ) ImpSPOpIdx = OpIdx ; } assert ( ImpLROpIdx != - <NUM_LIT> ) ;


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; int64_t ElementBits = VT . getScalarSizeInBits ( ) ;

if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ;


<s> <ISA_LIT>TargetMachOStreamer ( MCStreamer & S ) : <ISA_LIT>TargetStreamer ( S ) {


<s> else if ( SecondOpcode == <STR_LIT> ) { if ( ! FirstMI ) return true ; if ( FirstMI -> definesRegister ( <STR_LIT> ) ) switch ( FirstMI -> getOpcode ( ) ) { case <STR_LIT> : return ( ! <ISA_LIT>InstrInfo :: hasShiftedReg ( * FirstMI ) ) ; case <STR_LIT> : case <STR_LIT> : return ( ! <ISA_LIT>InstrInfo :: hasExtendedReg ( * FirstMI ) ) ;


<s> const char * getPassName ( ) const override {


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SDNode * CallNode , const Type * RetTy ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , IsO32 , CCInfo ) ; <ISA_LIT>CCInfo . analyzeCallResult ( Ins , getTargetMachine ( ) . Options . UseSoftFloat , CallNode , RetTy ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = DAG . getCopyFromReg ( Chain , DL , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ;


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ;

while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> op1 = scratch ; } tmp [ <NUM_LIT> ] = op0 ; tmp [ <NUM_LIT> ] = op1 ; ix86_expand_vector_move_misalign ( mode , tmp ) ; return ; } if ( mode == V1TImode && SUBREG_P ( op1 ) && GET_MODE ( SUBREG_REG ( op1 ) ) == TImode && TARGET_64BIT && TARGET_SSE && can_create_pseudo_p ( ) ) { rtx tmp = gen_reg_rtx ( V2DImode ) ; rtx lo = gen_reg_rtx ( DImode ) ; rtx hi = gen_reg_rtx ( DImode ) ; emit_move_insn ( lo , gen_lowpart ( DImode , SUBREG_REG ( op1 ) ) ) ; emit_move_insn ( hi , gen_highpart ( DImode , SUBREG_REG ( op1 ) ) ) ; emit_insn ( gen_vec_concatv2di ( tmp , lo , hi ) ) ; emit_move_insn ( op0 , gen_lowpart ( V1TImode , tmp ) ) ; return ; } if ( can_create_pseudo_p ( ) && ! ix86_hardreg_mov_ok ( op0 , op1 ) ) { rtx tmp = gen_reg_rtx ( GET_MODE ( op0 ) ) ; emit_move_insn ( tmp , op1 ) ; emit_move_insn ( op0 , tmp ) ; return ; } if ( can_create_pseudo_p ( ) && ! register_operand ( op0 , mode ) && ! register_operand ( op1 , mode ) ) { rtx tmp = gen_reg_rtx ( GET_MODE ( op0 ) ) ; emit_move_insn ( tmp , op1 ) ; emit_move_insn ( op0 , tmp ) ; return ; } emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ;


<s> if ( RegNum == <NUM_LIT> ) RegNum = matchReqRegisterNameAlias ( Name , RegKind :: SVEVector ) ;


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReplaceableInstrsAVX2 ) ; i != e ; ++ i ) if ( ReplaceableInstrsAVX2 [ i ] [ domain - <NUM_LIT> ] == opcode ) return ReplaceableInstrsAVX2 [ i ] ;


<s> bool SNITCHFrepLoops :: isInvalidLoopOperation ( const MachineInstr * MI ) const { bool validInstr = true ;

for ( auto MO : MI -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) . isVirtual ( ) ) if ( MRI -> getRegClass ( MO . getReg ( ) ) != & <STR_LIT> || MRI -> getRegClass ( MO . getReg ( ) ) != & <STR_LIT> ) validInstr = false ;


<s> auto * CCMask = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! CCValid || ! CCMask ) return SDValue ( ) ; int CCValidVal = CCValid -> getZExtValue ( ) ; int CCMaskVal = CCMask -> getZExtValue ( ) ; SDValue Select = N -> getOperand ( <NUM_LIT> ) ; if ( Select -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto * SelectCCValid = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; auto * SelectCCMask = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! SelectCCValid || ! SelectCCMask ) return SDValue ( ) ; int SelectCCValidVal = SelectCCValid -> getZExtValue ( ) ; int SelectCCMaskVal = SelectCCMask -> getZExtValue ( ) ; auto * TrueVal = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; auto * FalseVal = dyn_cast < ConstantSDNode > ( Select -> getOperand ( <NUM_LIT> ) ) ; if ( ! TrueVal || ! FalseVal ) return SDValue ( ) ; if ( TrueVal -> getZExtValue ( ) != <NUM_LIT> && FalseVal -> getZExtValue ( ) == <NUM_LIT> ) ; else if ( TrueVal -> getZExtValue ( ) == <NUM_LIT> && FalseVal -> getZExtValue ( ) != <NUM_LIT> ) SelectCCMaskVal ^= SelectCCValidVal ;


<s> int NumV2Inputs = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , isV2 ) ; if ( NumV2Inputs == <NUM_LIT> ) return lowerV8I16SingleInputVectorShuffle ( DL , V1 , Mask , Subtarget , DAG ) ; assert ( NumV1Inputs > <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V1 , V2 , Mask , Subtarget , DAG ) ) return V ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( Subtarget -> hasSSSE3 ( ) ) if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Rotate ; if ( NumV1Inputs + NumV2Inputs <= <NUM_LIT> ) return lowerV8I16BasicBlendVectorShuffle ( DL , V1 , V2 , Mask , Subtarget , DAG ) ; if ( shouldLowerAsInterleaving ( Mask ) ) { int EMask [ <NUM_LIT> ] , OMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { EMask [ i ] = Mask [ <NUM_LIT> * i ] ; OMask [ i ] = Mask [ <NUM_LIT> * i + <NUM_LIT> ] ; EMask [ i + <NUM_LIT> ] = - <NUM_LIT> ; OMask [ i + <NUM_LIT> ] = - <NUM_LIT> ; } SDValue Evens = DAG . getVectorShuffle ( <STR_LIT> , DL , V1 , V2 , EMask ) ; SDValue Odds = DAG . getVectorShuffle ( <STR_LIT> , DL , V1 , V2 , OMask ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Evens , Odds ) ; } int LoBlendMask [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; int HiBlendMask [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { LoBlendMask [ i ] = Mask [ i ] ;

HiBlendMask [ i ] = Mask [ i + <NUM_LIT> ] ;


<s> mode = GET_MODE ( opnd ) ; reg = opnd ; if ( GET_CODE ( reg ) == SUBREG ) { gcc_assert ( SUBREG_BYTE ( reg ) == <NUM_LIT> ) ; reg = SUBREG_REG ( reg ) ; } if ( GET_CODE ( reg ) != REG || REGNO ( reg ) > A7_REG || REGNO ( reg ) + hard_regno_nregs ( A7_REG , mode ) <= A7_REG ) return opnd ; gcc_assert ( REGNO ( reg ) + hard_regno_nregs ( A7_REG , mode ) - <NUM_LIT> == A7_REG ) ; cfun -> machine -> need_a7_copy = false ; start_sequence ( ) ; tmp = gen_reg_rtx ( mode ) ; switch ( mode ) { case E_DFmode : case E_DImode : emit_insn ( gen_movsi_internal ( gen_rtx_SUBREG ( SImode , tmp , <NUM_LIT> ) , gen_raw_REG ( SImode , A7_REG ) ) ) ; break ; case E_SFmode : emit_insn ( gen_movsf_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case E_SImode : emit_insn ( gen_movsi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case E_HImode : emit_insn ( gen_movhi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; case E_QImode : emit_insn ( gen_movqi_internal ( tmp , gen_raw_REG ( mode , A7_REG ) ) ) ; break ; default : gcc_unreachable ( ) ; } cfun -> machine -> set_frame_ptr_insn = emit_insn ( gen_set_frame_ptr ( ) ) ; if ( mode == DFmode || mode == DImode ) emit_insn ( gen_movsi_internal ( gen_rtx_SUBREG ( SImode , tmp , <NUM_LIT> ) , gen_rtx_REG ( SImode , A7_REG - <NUM_LIT> ) ) ) ; entry_insns = get_insns ( ) ; end_sequence ( ) ; if ( cfun -> machine -> vararg_a7 ) { cfun -> machine -> vararg_a7_copy = entry_insns ; } else { push_topmost_sequence ( ) ;

emit_insn_after ( entry_insns , get_insns ( ) ) ;


<s> llvm :: StringRef DataLayout = <STR_LIT> ;


<s> unsigned TmpReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( BB , I , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( Reg , RegState :: Kill ) . addReg ( Reg , RegState :: Kill ) ;


<s> for ( MachineBasicBlock :: instr_iterator it = BB -> begin ( ) ; it != BB -> end ( ) ; it ++ ) {


<s> static_assert ( B > <NUM_LIT> , <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < B > ( maskTrailingOnes < decltype ( InsnS ) > ( B ) & InsnS ) ) ) ;


<s> MVT EVT = VT . getVectorElementType ( ) ; unsigned n = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > ULTOp1 ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) { ConstantSDNode * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getValueType ( <NUM_LIT> ) != EVT ) return SDValue ( ) ; APInt Val = Elt -> getAPIntValue ( ) ; if ( Val == <NUM_LIT> ) return SDValue ( ) ; ULTOp1 . push_back ( DAG . getConstant ( Val - <NUM_LIT> , EVT ) ) ; } return DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , ULTOp1 . data ( ) , ULTOp1 . size ( ) ) ;


<s> if ( isa < CatchReturnInst > ( BB -> getTerminator ( ) ) ) return OverdefinedState ; int CommonState = OverdefinedState ; for ( BasicBlock * SuccBB : successors ( BB ) ) { auto SuccStartState = InitialStates . find ( SuccBB ) ;

if ( SuccStartState == InitialStates . end ( ) ) return OverdefinedState ;


<s> void <ISA_LIT>InstPrinter :: printPrefetchOp ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) {

unsigned prfop = MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> AU . addRequired < EdgeBundles > ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static MCOperand lowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym , const AsmPrinter & AP ) { MCContext & Ctx = AP . OutContext ; <ISA_LIT>MCExpr :: VariantKind Kind ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case <STR_LIT> :

Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( bool Is64Bit , uint8_t OSABI ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , ELF :: EM_NONE , true ) {


<s> if ( ! FixupBWInsts || skipFunction ( MF . getFunction ( ) ) ) return false ; this -> MF = & MF ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; PSI = & getAnalysis < ProfileSummaryInfoWrapperPass > ( ) . getPSI ( ) ; MBFI = ( PSI && PSI -> hasProfileSummary ( ) ) ? & getAnalysis < LazyMachineBlockFrequencyInfoPass > ( ) . getBFI ( ) :


<s> unsigned NumCSI = CSI . size ( ) ; if ( NumCSI <= <NUM_LIT> ) return false ;

unsigned Threshold = isOptSize ( MF ) ? SpillFuncThresholdOs - <NUM_LIT> : SpillFuncThreshold ;


<s> int ImmVal = <STR_LIT> ( FPVal ) ; if ( ImmVal != - <NUM_LIT> ) { SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } EVT VMovVT ; unsigned iVal = FPVal . bitcastToAPInt ( ) . getZExtValue ( ) ; SDValue NewVal = isNEONModifiedImm ( iVal , <NUM_LIT> , <NUM_LIT> , DAG , VMovVT , false , VMOVModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } NewVal = isNEONModifiedImm ( ~ iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , VMovVT , false , VMVNModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } return SDValue ( ) ;


<s> static void xtensa_init_builtins ( void ) { tree ftype , decl ; ftype = build_function_type_list ( unsigned_intDI_type_node , unsigned_intSI_type_node , unsigned_intSI_type_node , NULL_TREE ) ; decl = add_builtin_function ( <STR_LIT> , ftype , XTENSA_BUILTIN_UMULSIDI3 , BUILT_IN_MD , <STR_LIT> , NULL_TREE ) ;


<s> void <ISA_LIT>PostLegalizerLowering :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ;


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG ) return ne ? <STR_LIT> : <STR_LIT> ; else if ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> && ! mep_vliw_function_p ( cfun -> decl ) ) return ne ? <STR_LIT> : <STR_LIT> ;

else return ne ? <STR_LIT> : <STR_LIT> ;


<s> void <ISA_LIT>ConstantIslands :: scanFunctionJumpTables ( ) { for ( MachineBasicBlock & MBB : * MF ) {

for ( MachineInstr & I : MBB ) if ( I . isBranch ( ) && ( I . getOpcode ( ) == <STR_LIT> || I . getOpcode ( ) == <STR_LIT> ) ) T2JumpTables . push_back ( & I ) ;


<s> if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= <NUM_LIT> || scale > <NUM_LIT> || ( scale & ( scale - <NUM_LIT> ) ) != <NUM_LIT> ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( vectype ) ) { case E_V8DFmode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DF : IX86_BUILTIN_SCATTERDIV8DF ; break ; case E_V8DImode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DI : IX86_BUILTIN_SCATTERDIV8DI ; break ; case E_V16SFmode : code = si ? IX86_BUILTIN_SCATTERSIV16SF : IX86_BUILTIN_SCATTERALTDIV16SF ; break ; case E_V16SImode : code = si ? IX86_BUILTIN_SCATTERSIV16SI : IX86_BUILTIN_SCATTERALTDIV16SI ; break ; case E_V4DFmode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DF : IX86_BUILTIN_SCATTERDIV4DF ; else return NULL_TREE ; break ; case E_V4DImode : if ( TARGET_AVX512VL ) code = si ? IX86_BUILTIN_SCATTERALTSIV4DI : IX86_BUILTIN_SCATTERDIV4DI ; else return NULL_TREE ;