<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DL ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) :

std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameLowering ( * this , Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( * this , Subtarget ) ) {


<s> return isMem16 ( ) && isSrcIdx ( ) ;


<s> return lookupRelaxTableImpl ( InstrRelaxTable , ShortOp ) ;


<s> void replaceFeatures ( Function & F , const std :: string & Features ) {


<s> if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: <ISA_LIT>_SVE_VectorCall ) return CSR_<ISA_LIT>_SVE_AAPCS_SaveList ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: SwiftTail ) return CSR_<ISA_LIT>_AAPCS_SwiftTail_SaveList ;

if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: PreserveMost ) return CSR_<ISA_LIT>_RT_MostRegs_SaveList ;


<s> void <ISA_LIT>AsmPrinter :: emitArrayBound ( MCSymbol * Sym , const GlobalVariable * GV ) { assert ( ( ( GV -> hasExternalLinkage ( ) || GV -> hasWeakLinkage ( ) ) || GV -> hasLinkOnceLinkage ( ) ) && <STR_LIT> ) ;

if ( ArrayType * ATy = dyn_cast < ArrayType > ( cast < PointerType > ( GV -> getType ( ) ) -> getElementType ( ) ) ) {


<s> unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ;


<s> SDLoc DL ( Op ) ; SDValue Pred = DAG . getSetCC ( DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Pred , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , <ISA_LIT>DataLayout , TT , getCPU ( CPU ) , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , SubTarget ( TT , std :: string ( getCPU ( CPU ) ) , std :: string ( FS ) , * this ) { this -> TLOF = std :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ;

adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ;


<s> machine -> use_eh_return_p = <NUM_LIT> ; machine -> naked_p = <NUM_LIT> ; machine -> fp_as_gp_p = <NUM_LIT> ;

machine -> strict_aligned_p = <NUM_LIT> ;


<s> unsigned NewOpc = Ctlz ? <STR_LIT> : <STR_LIT> ; bool ZeroUndef = Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ; if ( Src . getValueType ( ) == <STR_LIT> ) { SDValue NewOpr = DAG . getNode ( NewOpc , SL , <STR_LIT> , Src ) ; if ( ! ZeroUndef ) { const SDValue Const32 = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; NewOpr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , NewOpr , Const32 ) ; } return NewOpr ; } SDValue Lo , Hi ; std :: tie ( Lo , Hi ) = split64BitValue ( Src , DAG ) ; SDValue OprLo = DAG . getNode ( NewOpc , SL , <STR_LIT> , Lo ) ; SDValue OprHi = DAG . getNode ( NewOpc , SL , <STR_LIT> , Hi ) ; unsigned AddOpc = ZeroUndef ? <STR_LIT> : <STR_LIT> ; const SDValue Const32 = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; if ( Ctlz ) OprLo = DAG . getNode ( AddOpc , SL , <STR_LIT> , OprLo , Const32 ) ; else OprHi = DAG . getNode ( AddOpc , SL , <STR_LIT> , OprHi , Const32 ) ; SDValue NewOpr ; NewOpr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , OprLo , OprHi ) ;


<s> Value * <ISA_LIT>IREmitter :: visitPCMPGT ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> bool memreg_operand ( rtx op , machine_mode mode ATTRIBUTE_UNUSED ) {

return MEM_P ( op ) && REG_P ( XEXP ( op , <NUM_LIT> ) ) ;


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << '$' << StringRef ( <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << * getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : { MCSymbol * BA = GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; O << BA -> getName ( ) ; break ; } case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << MO . getIndex ( ) ;

if ( MO . getOffset ( ) ) O << <STR_LIT> << MO . getOffset ( ) ;


<s> shmask = vec_cmple ( lshift , shmax ) ; result = vec_sl ( ( __v8hu ) __A , lshift ) ; result = vec_sel ( ( __v8hu ) shmask , result , shmask ) ;


<s> case ROTATERT : return ( mode == SImode ) ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ; case PLUS : case MINUS : if ( ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && power_of_two_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , SImode ) ) || ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == MULT && power_of_two_operand ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , SImode ) ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; case COMPARE : case NEG : case NOT : return COSTS_N_INSNS ( <NUM_LIT> ) ; case MULT : if ( CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { int const_size = thumb1_size_rtx_costs ( XEXP ( x , <NUM_LIT> ) , CONST_INT , SET ) ; if ( arm_arch6m && arm_m_profile_small_mul ) return COSTS_N_INSNS ( <NUM_LIT> ) ; else return COSTS_N_INSNS ( <NUM_LIT> ) + const_size ; } return COSTS_N_INSNS ( <NUM_LIT> ) ; case SET : words = ARM_NUM_INTS ( GET_MODE_SIZE ( GET_MODE ( SET_DEST ( x ) ) ) ) ; return COSTS_N_INSNS ( words ) + COSTS_N_INSNS ( <NUM_LIT> ) * ( satisfies_constraint_J ( SET_SRC ( x ) ) || satisfies_constraint_K ( SET_SRC ( x ) ) || ( ( words > <NUM_LIT> ) && MEM_P ( SET_SRC ( x ) ) ) ) ; case CONST_INT : if ( outer == SET ) { if ( ( unsigned HOST_WIDE_INT ) INTVAL ( x ) < <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( INTVAL ( x ) >= - <NUM_LIT> && INTVAL ( x ) <= - <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; if ( thumb_shiftable_const ( INTVAL ( x ) ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; return COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( ( outer == PLUS || outer == COMPARE ) && INTVAL ( x ) < <NUM_LIT> && INTVAL ( x ) > - <NUM_LIT> ) return <NUM_LIT> ; else if ( ( outer == IOR || outer == XOR || outer == AND ) && INTVAL ( x ) < <NUM_LIT> && INTVAL ( x ) >= - <NUM_LIT> ) return COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( outer == AND ) { int i ; for ( i = <NUM_LIT> ; i <= <NUM_LIT> ; i ++ ) if ( ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << i ) - <NUM_LIT> == INTVAL ( x ) || ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << i ) - <NUM_LIT> == ~ INTVAL ( x ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( outer == ASHIFT || outer == ASHIFTRT || outer == LSHIFTRT ) return <NUM_LIT> ; return COSTS_N_INSNS ( <NUM_LIT> ) ; case CONST : case CONST_DOUBLE : case LABEL_REF : case SYMBOL_REF : return COSTS_N_INSNS ( <NUM_LIT> ) ; case UDIV : case UMOD : case DIV : case MOD : return <NUM_LIT> ;


<s> unsigned Width = <NUM_LIT> - Srl_imm ; int LSB = Srl_imm - Shl_imm ; if ( LSB < <NUM_LIT> ) return NULL ; SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( LSB , <STR_LIT> ) , CurDAG -> getTargetConstant ( Width , <STR_LIT> ) , getAL ( CurDAG ) , Reg0 } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops , <NUM_LIT> ) ; } } return NULL ;


<s> break ; } if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) ; addFullAddress ( MIB , AM ) . addImm ( Signed ? ( uint64_t ) CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; if ( MMO ) MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return true ; } } Register ValReg = getRegForValue ( Val ) ;

if ( ValReg == <NUM_LIT> ) return false ;


<s> bool Filler :: runOnMachineBasicBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; for ( Iter I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! hasUnoccupiedSlot ( & * I ) ) continue ; ++ FilledSlots ; Changed = true ; if ( ! DisableDelaySlotFiller && ( TM . getOptLevel ( ) != CodeGenOpt :: None ) ) { if ( searchBackward ( MBB , I ) ) continue ; if ( I -> isTerminator ( ) ) { if ( searchSuccBBs ( MBB , I ) ) continue ; } else if ( searchForward ( MBB , I ) ) { continue ; } } const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; BuildMI ( MBB , std :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIBundleBuilder ( MBB , I , std :: next ( I , <NUM_LIT> ) ) ; } return Changed ;


<s> if ( Subtarget -> hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) return <STR_LIT> ; } else if ( ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> && Subtarget -> hasSSE2 ( ) ) { return <STR_LIT> ;


<s> inline SDValue getI32Imm ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , <STR_LIT> ) ;


<s> break ; case PLUS : if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG || GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == SUBREG ) { v850_print_operand ( file , XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; fprintf ( file , <STR_LIT> ) ; v850_print_operand ( file , XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } else { v850_print_operand ( file , XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; fprintf ( file , <STR_LIT> ) ; v850_print_operand ( file , XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; } break ; case SYMBOL_REF : { const char * off_name = NULL ; const char * reg_name = NULL ; if ( SYMBOL_REF_ZDA_P ( addr ) ) { off_name = <STR_LIT> ; reg_name = <STR_LIT> ; } else if ( SYMBOL_REF_SDA_P ( addr ) ) { off_name = <STR_LIT> ; reg_name = <STR_LIT> ; } else if ( SYMBOL_REF_TDA_P ( addr ) ) { off_name = <STR_LIT> ; reg_name = <STR_LIT> ; } if ( off_name ) fprintf ( file , <STR_LIT> , off_name ) ; output_addr_const ( file , addr ) ; if ( reg_name ) fprintf ( file , <STR_LIT> , reg_name ) ; } break ; case CONST : if ( special_symbolref_operand ( addr , VOIDmode ) ) { rtx x = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; const char * off_name ; const char * reg_name ; if ( SYMBOL_REF_ZDA_P ( x ) ) { off_name = <STR_LIT> ; reg_name = <STR_LIT> ; } else if ( SYMBOL_REF_SDA_P ( x ) ) { off_name = <STR_LIT> ; reg_name = <STR_LIT> ; } else if ( SYMBOL_REF_TDA_P ( x ) ) { off_name = <STR_LIT> ; reg_name = <STR_LIT> ; } else gcc_unreachable ( ) ; fprintf ( file , <STR_LIT> , off_name ) ; output_addr_const ( file , addr ) ; fprintf ( file , <STR_LIT> , reg_name ) ; } else output_addr_const ( file , addr ) ;


<s> static DecodeStatus DecodeSPERCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) {

return decodeRegisterClass ( Inst , RegNo , SPERegs ) ;


<s> } else { return MRI -> getRegClass ( Reg ) == RC ; }


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitFILL_FW ( MachineInstr & MI , MachineBasicBlock * BB ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Wd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Fs = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt1 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; unsigned Wt2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt1 ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt2 ) . addReg ( Wt1 ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wt2 ) . addImm ( <NUM_LIT> ) ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> else return NULL_RTX ; if ( GET_MODE ( extended_op ) != SImode ) return NULL_RTX ; set_of_reg s = sh_find_set_of_reg ( extended_op , insn , prev_nonnote_nondebug_insn_bb ) ; if ( s . set_src == NULL_RTX ) return NULL_RTX ; if ( t_reg_operand ( s . set_src , VOIDmode ) || negt_reg_operand ( s . set_src , VOIDmode ) ) return extended_op ; else if ( sh_is_logical_t_store_expr ( s . set_src , s . insn ) ) return extended_op ;


<s> MachineConstEvaluator ( MachineFunction & Fn ) : TRI ( * Fn . getSubtarget ( ) . getRegisterInfo ( ) ) , MF ( Fn ) , CX ( Fn . getFunction ( ) -> getContext ( ) ) {


<s> jclass cls ; jmethodID mid ; JavaVMInitArgs vm_args ; JavaVMOption options [ <NUM_LIT> ] ; options [ <NUM_LIT> ] . optionString = <STR_LIT> ; options [ <NUM_LIT> ] . optionString = <STR_LIT> ; options [ <NUM_LIT> ] . optionString = <STR_LIT> ; options [ <NUM_LIT> ] . optionString = <STR_LIT> ; vm_args . version = <NUM_LIT> ; vm_args . options = options ; vm_args . nOptions = <NUM_LIT> ; vm_args . ignoreUnrecognized = JNI_TRUE ; fprintf ( stdout , <STR_LIT> , className , methodName ) ;

res = JNI_CreateJavaVM ( & jvm , ( void * * ) & env , & vm_args ) ;


<s> unsigned getNumberOfParts ( Type * Tp ) { return BaseT :: getNumberOfParts ( Tp ) ;


<s> if ( GET_CODE ( const_vector ) == SYMBOL_REF ) const_vector = get_pool_constant ( const_vector ) ; gcc_assert ( GET_CODE ( const_vector ) == CONST_VECTOR ) ; rtx new_mem ; enum machine_mode mode = GET_MODE ( const_vector ) ; if ( mode == V1TImode ) return ; else if ( mode == V16QImode ) { rtx vals = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) XVECEXP ( vals , <NUM_LIT> , ( ( i + <NUM_LIT> ) % <NUM_LIT> ) ) = XVECEXP ( const_vector , <NUM_LIT> , i ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; new_mem = force_const_mem ( mode , new_const_vector ) ; } else if ( ( mode == V8HImode ) || ( mode == V8HFmode ) ) { rtx vals = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) XVECEXP ( vals , <NUM_LIT> , ( ( i + <NUM_LIT> ) % <NUM_LIT> ) ) = XVECEXP ( const_vector , <NUM_LIT> , i ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; new_mem = force_const_mem ( mode , new_const_vector ) ; } else if ( ( mode == V4SImode ) || ( mode == V4SFmode ) ) { rtx vals = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) XVECEXP ( vals , <NUM_LIT> , ( ( i + <NUM_LIT> ) % <NUM_LIT> ) ) = XVECEXP ( const_vector , <NUM_LIT> , i ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; new_mem = force_const_mem ( mode , new_const_vector ) ; } else if ( ( mode == V2DImode ) || ( mode == V2DFmode ) ) { rtx vals = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) XVECEXP ( vals , <NUM_LIT> , ( ( i + <NUM_LIT> ) % <NUM_LIT> ) ) = XVECEXP ( const_vector , <NUM_LIT> , i ) ; rtx new_const_vector = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; new_mem = force_const_mem ( mode , new_const_vector ) ; } else {


<s> Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - Imm ) ) ; return Success ;


<s> S = MCDisassembler :: SoftFail ; } if ( mask == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( pred & <NUM_LIT> ) { unsigned LowBit = mask & - mask ; unsigned BitsAboveLowBit = <NUM_LIT> & ( - LowBit << <NUM_LIT> ) ;


<s> return VmCnt != ~ <NUM_LIT> || ExpCnt != ~ <NUM_LIT> || LgkmCnt != ~ <NUM_LIT> ;


<s> else if ( TARGET_HPUX && GET_MODE ( * op0 ) == TFmode ) { enum qfcmp_magic { QCMP_INV = <NUM_LIT> , QCMP_UNORD = <NUM_LIT> , QCMP_EQ = <NUM_LIT> , QCMP_LT = <NUM_LIT> , QCMP_GT = <NUM_LIT> } ; int magic ; enum rtx_code ncode ; rtx ret ; gcc_assert ( cmptf_libfunc && GET_MODE ( * op1 ) == TFmode ) ; switch ( code ) { case EQ : magic = QCMP_EQ ; ncode = NE ; break ; case NE : magic = QCMP_EQ ; ncode = EQ ; break ; case UNORDERED : magic = QCMP_UNORD ; ncode = NE ; break ; case ORDERED : magic = QCMP_UNORD ; ncode = EQ ; break ; case LT : magic = QCMP_LT | QCMP_INV ; ncode = NE ; break ; case LE : magic = QCMP_LT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case GT : magic = QCMP_GT | QCMP_INV ; ncode = NE ; break ; case GE : magic = QCMP_GT | QCMP_EQ | QCMP_INV ; ncode = NE ; break ; case UNLT : magic = QCMP_LT | QCMP_UNORD ; ncode = NE ; break ; case UNLE : magic = QCMP_LT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNGT : magic = QCMP_GT | QCMP_UNORD ; ncode = NE ; break ; case UNGE : magic = QCMP_GT | QCMP_EQ | QCMP_UNORD ; ncode = NE ; break ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } start_sequence ( ) ; ret = emit_library_call_value ( cmptf_libfunc , <NUM_LIT> , LCT_CONST , DImode , <NUM_LIT> , * op0 , TFmode , * op1 , TFmode , GEN_INT ( magic ) , DImode ) ; cmp = gen_reg_rtx ( BImode ) ; emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( ncode , BImode , ret , const0_rtx ) ) ) ; rtx_insn * insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ; code = NE ; } else { cmp = gen_reg_rtx ( BImode ) ;

emit_insn ( gen_rtx_SET ( cmp , gen_rtx_fmt_ee ( code , BImode , * op0 , * op1 ) ) ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T , Triple :: OSType OSType ) : MCAsmBackend ( ) , OSType ( OSType ) {


<s> for ( auto & MO : MI -> operands ( ) ) { const MCOperand MCOp = LowerOperand ( MO ) ;


<s> if ( ! LDBase ) { if ( Elt . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; LDBase = cast < LoadSDNode > ( Elt . getNode ( ) ) ; LastLoadedElt = i ; continue ; } if ( Elt . getOpcode ( ) == <STR_LIT> ) continue ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . isConsecutiveLoad ( LD , LDBase , EltVT . getSizeInBits ( ) / <NUM_LIT> , i ) ) return SDValue ( ) ; LastLoadedElt = i ; } if ( LastLoadedElt == NumElems - <NUM_LIT> ) { SDValue NewLd = SDValue ( ) ; if ( DAG . InferPtrAlignment ( LDBase -> getBasePtr ( ) ) >= <NUM_LIT> ) NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , <NUM_LIT> ) ; NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ; DAG . UpdateNodeOperands ( NewChain . getNode ( ) , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ; }


<s> case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> HOST_WIDE_INT hi , lo ; if ( lowest_bit_set < <NUM_LIT> ) { lo = ( low_bits >> lowest_bit_set ) << shift ; hi = ( ( high_bits << ( <NUM_LIT> - lowest_bit_set ) ) << shift ) ; } else { lo = <NUM_LIT> ; hi = ( ( high_bits >> ( lowest_bit_set - <NUM_LIT> ) ) << shift ) ;


<s> static int rs6000_hard_regno_mode_ok ( int regno , enum machine_mode mode ) { if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( regno + HARD_REGNO_NREGS ( regno , mode ) - <NUM_LIT> ) ; if ( FP_REGNO_P ( regno ) ) return ( GET_MODE_CLASS ( mode ) == MODE_FLOAT && FP_REGNO_P ( regno + HARD_REGNO_NREGS ( regno , mode ) - <NUM_LIT> ) ) || ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) ; if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( XER_REGNO_P ( regno ) ) return mode == PSImode ;

if ( ALTIVEC_REGNO_P ( regno ) ) return ALTIVEC_VECTOR_MODE ( mode ) ;


<s> HiOffset = ( ImmOffset & <NUM_LIT> ) >> <NUM_LIT> ; if ( LoOffset & <NUM_LIT> ) HiOffset ++ ; } else ExprOffset = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; TempInst . setLoc ( IDLoc ) ; TmpRegNum = ( isLoad && ( BaseRegNum != RegOpNum ) ) ? RegOpNum : AtRegNum ; TempInst . setOpcode ( <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; if ( isImmOpnd ) TempInst . addOperand ( MCOperand :: CreateImm ( HiOffset ) ) ; else { if ( ExprOffset -> getKind ( ) == MCExpr :: SymbolRef ) { SR = static_cast < const MCSymbolRefExpr * > ( ExprOffset ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( SR -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , getContext ( ) ) ; TempInst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; } else { const MCExpr * HiExpr = evaluateRelocExpr ( ExprOffset , <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateExpr ( HiExpr ) ) ; } } Instructions . push_back ( TempInst ) ; TempInst . clear ( ) ; TempInst . setOpcode ( <STR_LIT> ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; TempInst . addOperand ( MCOperand :: CreateReg ( BaseRegNum ) ) ; Instructions . push_back ( TempInst ) ; TempInst . clear ( ) ; TempInst . setOpcode ( Inst . getOpcode ( ) ) ; TempInst . addOperand ( MCOperand :: CreateReg ( RegOpNum ) ) ; TempInst . addOperand ( MCOperand :: CreateReg ( TmpRegNum ) ) ; if ( isImmOpnd ) TempInst . addOperand ( MCOperand :: CreateImm ( LoOffset ) ) ; else { if ( ExprOffset -> getKind ( ) == MCExpr :: SymbolRef ) { const MCSymbolRefExpr * LoExpr = MCSymbolRefExpr :: Create ( SR -> getSymbol ( ) . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , getContext ( ) ) ;

TempInst . addOperand ( MCOperand :: CreateExpr ( LoExpr ) ) ;


<s> return getSingleExitNode ( MF ) != nullptr ;


<s> if ( Cmp -> getOpcode ( ) != <STR_LIT> || ! isNullConstant ( Cmp -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue CSInc = Cmp -> getOperand ( <NUM_LIT> ) ; while ( CSInc . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( CSInc . getOperand ( <NUM_LIT> ) ) && CSInc . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && CSInc -> hasOneUse ( ) ) CSInc = CSInc . getOperand ( <NUM_LIT> ) ; if ( CSInc . getOpcode ( ) != <STR_LIT> || ! isNullConstant ( CSInc . getOperand ( <NUM_LIT> ) ) || ! isNullConstant ( CSInc . getOperand ( <NUM_LIT> ) ) || ! CSInc -> hasOneUse ( ) ) return SDValue ( ) ; CC = ( <STR_LIT> ) CSInc . getConstantOperandVal ( <NUM_LIT> ) ; return CSInc . getOperand ( <NUM_LIT> ) ;


<s> auto ID = Intrinsic -> getIntrinsicID ( ) ; if ( ID == <STR_LIT> ) { return true ; } } } return false ;


<s> static unsigned int frv_function_arg_boundary ( machine_mode mode ATTRIBUTE_UNUSED , const_tree type ATTRIBUTE_UNUSED ) {


<s> const auto Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; if ( IsMachO ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: EndOfStatement ) ) { if ( Tok . isNot ( AsmToken :: Identifier ) && Tok . isNot ( AsmToken :: String ) ) { Error ( L , <STR_LIT> ) ; return false ; } MCSymbol * Func = getParser ( ) . getContext ( ) . GetOrCreateSymbol ( Tok . getIdentifier ( ) ) ; getParser ( ) . getStreamer ( ) . EmitThumbFunc ( Func ) ; Parser . Lex ( ) ; return false ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ;


<s> for ( auto * F : Functions ) { DominatorTree * DT = & getAnalysis < DominatorTreeWrapperPass > ( * F ) . getDomTree ( ) ; BasicBlock * Root = DT -> getRoot ( ) ; ReversePostOrderTraversal < BasicBlock * > RPOT ( Root ) ; for ( auto * BB : RPOT ) for ( Instruction & I : make_early_inc_range ( * BB ) ) Changed |= optimizeIntrinsic ( & I ) ; }


<s> std :: string CPUName = std :: string ( CPU ) ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ;


<s> <STR_LIT> getRestoreGPRRegs ( ) const { return RestoreGPRRegs ;


<s> DeadCodeElimination ( DataFlowGraph & dfg , MachineRegisterInfo & mri ) : Trace ( false ) , DFG ( dfg ) , MRI ( mri ) , LV ( mri , dfg ) {


<s> else if ( TARGET_FLOAT128 && ( mode == KFmode || mode == IFmode ) ) return true ; else return default_scalar_mode_supported_p ( mode ) ;


<s> return IC . replaceInstUsesWith ( II , Extract ) ; } auto * IntrPG = dyn_cast < IntrinsicInst > ( Pg ) ; if ( ! IntrPG ) return None ; if ( IntrPG -> getIntrinsicID ( ) != <STR_LIT> ) return None ; const auto PTruePattern = cast < ConstantInt > ( IntrPG -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned Idx ; switch ( PTruePattern ) { default : return None ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; case <STR_LIT> : Idx = <NUM_LIT> ; break ; } if ( IsAfter ) ++ Idx ; auto * PgVTy = cast < ScalableVectorType > ( Pg -> getType ( ) ) ; if ( Idx >= PgVTy -> getMinNumElements ( ) ) return None ; auto * IdxTy = Type :: getInt64Ty ( II . getContext ( ) ) ; auto * Extract = ExtractElementInst :: Create ( Vec , ConstantInt :: get ( IdxTy , Idx ) ) ; Extract -> insertBefore ( & II ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Expression ) ; Op -> Expr . Val = Val ;


<s> if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ; return Tmp . first ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Src ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) { ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; } SDValue Store = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MPI , SlotAlign ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MPI , SlotAlign , MachineMemOperand :: MOLoad ) ; Chain = Fild . getValue ( <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( OpNo ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF ) , PtrVT ) ; Align CPAlignment = cast < ConstantPoolSDNode > ( FudgePtr ) -> getAlign ( ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Offset = DAG . getSelect ( dl , Zero . getValueType ( ) , SignSet , Four , Zero ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , FudgePtr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <STR_LIT> , CPAlignment ) ;

Chain = Fudge . getValue ( <NUM_LIT> ) ;


<s> if ( ! Subtarget -> is64Bit ( ) ) Entry . isSRet = true ; Entry . isReturned = false ; Args . push_back ( Entry ) ; RetTyABI = Type :: getVoidTy ( * DAG . getContext ( ) ) ; } assert ( Op -> getNumOperands ( ) >= numArgs && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = numArgs ; i != e ; ++ i ) { Chain = LowerF128_LibCallArg ( Chain , Args , Op . getOperand ( i ) , SDLoc ( Op ) , DAG ) ; } TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( SDLoc ( Op ) ) . setChain ( Chain ) . setCallee ( CallingConv :: C , RetTyABI , Callee , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; if ( RetTyABI == RetTy ) return CallInfo . first ; assert ( RetTy -> isFP128Ty ( ) && <STR_LIT> ) ; Chain = CallInfo . second ;

return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , Chain , RetPtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPhysRegClass ( unsigned Reg ) const { assert ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; static const TargetRegisterClass * const BaseClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ; for ( const TargetRegisterClass * BaseClass : BaseClasses ) { if ( BaseClass -> contains ( Reg ) ) { return BaseClass ;


<s> bool NeedsWinCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) && MF . getFunction ( ) . needsUnwindTableEntry ( ) ; DebugLoc DL ; SmallVector < RegPairInfo , <NUM_LIT> > RegPairs ; bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( NeedShadowCallStackProlog ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( NeedsWinCFI ) BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; MBB . addLiveIn ( <STR_LIT> ) ; } for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; unsigned Size , Align ; switch ( RPI . Type ) { case RegPairInfo :: GPR : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR64 : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR128 : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg1 , TRI ) ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << printReg ( Reg2 , TRI ) ; dbgs ( ) << <STR_LIT> << RPI . FrameIdx ; if ( RPI . isPaired ( ) ) dbgs ( ) << <STR_LIT> << RPI . FrameIdx + <NUM_LIT> ; dbgs ( ) << <STR_LIT> ) ; assert ( ( ! NeedsWinCFI || ! ( Reg1 == <STR_LIT> && Reg2 == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned FrameIdxReg1 = RPI . FrameIdx ; unsigned FrameIdxReg2 = RPI . FrameIdx + <NUM_LIT> ; if ( NeedsWinCFI && RPI . isPaired ( ) ) {


<s> EVT VT = TLI . getValueType ( DL , Ty , true ) ;

return VT . isSimple ( ) ? VT . getSimpleVT ( ) . SimpleTy : <STR_LIT> ;


<s> for ( ValueRotInfo & VRI : ValueRotsVec ) { unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) ; ++ i ) { if ( ! Bits [ i ] . hasValue ( ) || Bits [ i ] . getValue ( ) != VRI . V ) continue ; if ( RLAmt [ i ] != VRI . RLAmt ) continue ; Mask |= ( <NUM_LIT> << i ) ; } unsigned ANDIMask = ( Mask & UINT16_MAX ) , ANDISMask = Mask >> <NUM_LIT> ; assert ( ( ANDIMask != <NUM_LIT> || ANDISMask != <NUM_LIT> ) && <STR_LIT> ) ; bool NeedsRotate = VRI . RLAmt != <NUM_LIT> ; unsigned NumAndInsts = ( unsigned ) NeedsRotate + ( unsigned ) ( ANDIMask != <NUM_LIT> ) + ( unsigned ) ( ANDISMask != <NUM_LIT> ) + ( unsigned ) ( ANDIMask != <NUM_LIT> && ANDISMask != <NUM_LIT> ) + ( unsigned ) ( bool ) Res ; DEBUG ( dbgs ( ) << <STR_LIT> << VRI . V . getNode ( ) << <STR_LIT> << VRI . RLAmt << <STR_LIT> << <STR_LIT> << NumAndInsts << <STR_LIT> << VRI . NumGroups << <STR_LIT> ) ; if ( NumAndInsts >= VRI . NumGroups ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( InstCnt ) * InstCnt += NumAndInsts ; SDValue VRot ; if ( VRI . RLAmt ) { SDValue Ops [ ] = { VRI . V , getI32Imm ( VRI . RLAmt ) , getI32Imm ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> ) } ; VRot = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { VRot = VRI . V ; }


<s> if ( ! Offset -> isDivergent ( ) ) { SDValue Ops [ ] = { Rsrc , Offset , CachePolicy } ; if ( VT . isVector ( ) && VT . getVectorNumElements ( ) == <NUM_LIT> ) { EVT WidenedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , <NUM_LIT> ) ; auto WidenedOp = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( WidenedVT ) , Ops , WidenedVT , MF . getMachineMemOperand ( MMO , <NUM_LIT> , WidenedVT . getStoreSize ( ) ) ) ; auto Subvector = DAG . getNode ( <STR_LIT> , DL , VT , WidenedOp , DAG . getVectorIdxConstant ( <NUM_LIT> , DL ) ) ; return Subvector ; } return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , DAG . getVTList ( VT ) , Ops , VT , MMO ) ; } SmallVector < SDValue , <NUM_LIT> > Loads ; unsigned NumLoads = <NUM_LIT> ; MVT LoadVT = VT . getSimpleVT ( ) ; unsigned NumElts = LoadVT . isVector ( ) ? LoadVT . getVectorNumElements ( ) : <NUM_LIT> ; assert ( ( LoadVT . getScalarType ( ) == <STR_LIT> || LoadVT . getScalarType ( ) == <STR_LIT> ) ) ; if ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) {


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI , bool Is64Bit ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , ELF :: EM_LOONGARCH , true ) {


<s> void <ISA_LIT>GenInsert :: buildOrderingBT ( RegisterOrdering & RB , RegisterOrdering & RO ) const { BitValueOrdering BVO ( RB ) ; RegisterCellLexCompare LexCmp ( BVO , * CMS ) ; using SortableVectorType = std :: vector < unsigned > ; SortableVectorType VRs ; for ( auto & I : RB ) VRs . push_back ( I . first ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemSrcValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { unsigned Bits = <NUM_LIT> ; const MCOperand & RegOp = MI . getOperand ( OpIdx ) ; const MCOperand & ImmOp = MI . getOperand ( OpIdx + <NUM_LIT> ) ;

Bits |= ( getMachineOpValue ( MI , RegOp , Fixups , STI ) << <NUM_LIT> ) ;


<s> const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI -> getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI -> getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( PossibleOffset ) && ( ! STI . privateMemoryResourceIsRangeChecked ( ) || KnownBits -> signBitIsZero ( LHS . getReg ( ) ) ) ) { if ( LHSDef -> getOpcode ( ) == <STR_LIT> ) FI = LHSDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; else VAddr = LHS . getReg ( ) ; Offset = PossibleOffset ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { FI = RootDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; } } Register SOffset = FI . hasValue ( ) ? Info -> getStackPtrOffsetReg ( ) : Info -> getScratchWaveOffsetReg ( ) ;

return { { [ = ] ( MachineInstrBuilder & MIB ) {


<s> unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; if ( SpillToVGPR ) { for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = VGPRSpills [ i ] ; bool VGPRDefined = true ; if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; } } else { Register TmpVGPR = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; RS -> setRegUsed ( TmpVGPR ) ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; unsigned PerVGPR = <NUM_LIT> ; unsigned NumVGPRs = ( NumSubRegs + ( PerVGPR - <NUM_LIT> ) ) / PerVGPR ; int64_t VGPRLanes = ( <NUM_LIT> << std :: min ( PerVGPR , NumSubRegs ) ) - <NUM_LIT> ; for ( unsigned Offset = <NUM_LIT> ; Offset < NumVGPRs ; ++ Offset ) { unsigned TmpVGPRFlags = RegState :: Undef ; for ( unsigned i = Offset * PerVGPR , e = std :: min ( ( Offset + <NUM_LIT> ) * PerVGPR , NumSubRegs ) ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; MachineInstrBuilder WriteLane = BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , TmpVGPR ) . addReg ( SubReg , SubKillState ) . addImm ( i % PerVGPR ) . addReg ( TmpVGPR , TmpVGPRFlags ) ; TmpVGPRFlags = <NUM_LIT> ; if ( NumSubRegs > <NUM_LIT> ) { unsigned SuperKillState = <NUM_LIT> ; if ( i + <NUM_LIT> == NumSubRegs ) SuperKillState |= getKillRegState ( IsKill ) ; WriteLane . addReg ( SuperReg , RegState :: Implicit | SuperKillState ) ;


<s> } if ( ! NeedWait ) return false ; if ( Counts . Named . EXP == <NUM_LIT> ) ExpInstrTypesSeen = <NUM_LIT> ; BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WAITCNT ) ) . addImm ( ( Counts . Named . VM & <NUM_LIT> ) | ( ( Counts . Named . EXP & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Counts . Named . LGKM & <NUM_LIT> ) << <NUM_LIT> ) ) ; LastOpcodeType = OTHER ; LastInstWritesM0 = false ;


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else return false ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , DL , <STR_LIT> ) ; return true ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ;


<s> if ( LI . getAlign ( ) >= <NUM_LIT> ) return false ; if ( ! canWidenScalarExtLoad ( LI ) ) return false ; int64_t Offset = <NUM_LIT> ; auto * Base = GetPointerBaseWithConstantOffset ( LI . getPointerOperand ( ) , Offset , * DL ) ; if ( ! isDWORDAligned ( Base ) ) return false ; int64_t Adjust = Offset & <NUM_LIT> ; if ( Adjust == <NUM_LIT> ) { LI . setAlignment ( Align ( <NUM_LIT> ) ) ; return true ; } IRBuilder < > IRB ( & LI ) ; IRB . SetCurrentDebugLocation ( LI . getDebugLoc ( ) ) ;

unsigned AS = LI . getPointerAddressSpace ( ) ;


<s> void LinearizedRegion :: storeMBBLiveOuts ( MachineBasicBlock * MBB , const MachineRegisterInfo * MRI , const TargetRegisterInfo * TRI , PHILinearize & PHIInfo , RegionMRT * TopRegion ) { for ( auto & II : * MBB ) { for ( auto & RI : II . defs ( ) ) { storeLiveOutRegRegion ( TopRegion , RI . getReg ( ) , RI . getParent ( ) , MRI , TRI , PHIInfo ) ; } for ( auto & IRI : II . implicit_operands ( ) ) { if ( IRI . isDef ( ) ) {

storeLiveOutRegRegion ( TopRegion , IRI . getReg ( ) , IRI . getParent ( ) , MRI , TRI , PHIInfo ) ;


<s> bool isDFMT ( ) const { return isImmTy ( ImmTyDFMT ) && isUInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> if ( isMesaKernel ( F ) ) return <NUM_LIT> ; return <STR_LIT> ( F , <STR_LIT> , <NUM_LIT> ) ;


<s> std :: swap ( d -> op0 , d -> op1 ) ; location = d -> perm . length ( ) . to_constant ( ) - location ; } offset = GEN_INT ( location ) ;

emit_set_insn ( d -> target , gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( <NUM_LIT> , d -> op0 , d -> op1 , offset ) , UNSPEC_EXT ) ) ;


<s> bool exist ( R && Range , const T & Val ) { auto It = llvm :: find ( Range , Val ) ; return It != std :: end ( Range ) ;


<s> unsigned const O = ( F >> <STR_LIT> ) & <STR_LIT> ; MCOperand const & MCO = MCI . getOperand ( O ) ; assert ( ( <ISA_LIT>MCInstrInfo :: isNewValue ( MCII , MCI ) || <ISA_LIT>MCInstrInfo :: hasNewValue ( MCII , MCI ) ) && MCO . isReg ( ) ) ;


<s> virtual void EmitARM64WinCFISaveRegPX ( unsigned Reg , int Offset ) {


<s> return ( __m128d ) __builtin_ia32_expanddf128_maskz ( ( __v2df ) __A , ( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! STI . hasVSX ( ) ) return false ; LIS = & getAnalysis < LiveIntervals > ( ) ; TII = STI . getInstrInfo ( ) ; bool Changed = false ; if ( DisableVSXFMAMutate ) return Changed ; for ( MachineFunction :: iterator I = MF . begin ( ) ; I != MF . end ( ) ; ) { MachineBasicBlock & B = * I ++ ;

if ( processBlock ( B ) ) Changed = true ;


<s> else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <STR_LIT> , false ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else FIOffset = TFI -> getFrameIndexOffset ( MF , FrameIndex ) ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } if ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . isImm ( ) ) { int Imm = ( int ) ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; int Offset = FIOffset + Imm ; assert ( ( ! Is64Bit || isInt < <NUM_LIT> > ( ( long long ) FIOffset + Imm ) ) && <STR_LIT> ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else { uint64_t Offset = FIOffset + ( uint64_t ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getOffset ( ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . setOffset ( Offset ) ; }


<s> else MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ; } , addZeroImm , addZeroImm , addZeroImm , } } ;


<s> Register Reg ; if ( VT == LLT :: scalar ( <NUM_LIT> ) ) { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> int res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( dg ) , <STR_LIT> ( dh ) ) ; return res ;


<s> SDValue Op = N -> getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) , OpVT = Op . getValueType ( ) ; if ( Op . getOpcode ( ) == <STR_LIT> && VT . getVectorElementType ( ) . getSizeInBits ( ) == OpVT . getVectorElementType ( ) . getSizeInBits ( ) ) {

return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , Op ) ;


<s> rtx tmp = gen_reg_rtx ( pred_mode ) ; aarch64_emit_unspec_cond ( tmp , code , pred_mode , pred , op0 , op1 ) ;

emit_set_insn ( target , gen_rtx_AND ( pred_mode , gen_rtx_NOT ( pred_mode , tmp ) , ptrue ) ) ;


<s> TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> :

return BrOffset >= - <NUM_LIT> && BrOffset <= <NUM_LIT> ;


<s> SDNode * VLD = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( VLD -> getOpcode ( ) != <STR_LIT> ) return false ; unsigned NumVecs = <NUM_LIT> ; unsigned NewOpc = <NUM_LIT> ; unsigned IntNo = cast < ConstantSDNode > ( VLD -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo == <STR_LIT> ) { NumVecs = <NUM_LIT> ; NewOpc = <STR_LIT> ; } else if ( IntNo == <STR_LIT> ) { NumVecs = <NUM_LIT> ; NewOpc = <STR_LIT> ; } else if ( IntNo == <STR_LIT> ) { NumVecs = <NUM_LIT> ; NewOpc = <STR_LIT> ; } else { return false ; } unsigned VLDLaneNo = cast < ConstantSDNode > ( VLD -> getOperand ( NumVecs + <NUM_LIT> ) ) -> getZExtValue ( ) ; for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) == NumVecs ) continue ; SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || VLDLaneNo != cast < ConstantSDNode > ( User -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) return false ; } EVT Tys [ <NUM_LIT> ] ; unsigned n ; for ( n = <NUM_LIT> ; n < NumVecs ; ++ n ) Tys [ n ] = VT ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( makeArrayRef ( Tys , NumVecs + <NUM_LIT> ) ) ; SDValue Ops [ ] = { VLD -> getOperand ( <NUM_LIT> ) , VLD -> getOperand ( <NUM_LIT> ) } ; MemIntrinsicSDNode * VLDMemInt = cast < MemIntrinsicSDNode > ( VLD ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( NewOpc , SDLoc ( VLD ) , SDTys , Ops , VLDMemInt -> getMemoryVT ( ) , VLDMemInt -> getMemOperand ( ) ) ; for ( SDNode :: use_iterator UI = VLD -> use_begin ( ) , UE = VLD -> use_end ( ) ; UI != UE ; ++ UI ) { unsigned ResNo = UI . getUse ( ) . getResNo ( ) ; if ( ResNo == NumVecs ) continue ; SDNode * User = * UI ;

DCI . CombineTo ( User , SDValue ( VLDDup . getNode ( ) , ResNo ) ) ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>CommonSubtarget ( TT , getFeatureBits ( ) ) , InstrInfo ( * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) , FMA ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , DX10Clamp ( false ) , HasVertexCache ( false ) , <ISA_LIT>ALUInst ( false ) , FP64 ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , Gen ( <ISA_LIT> ) , TLInfo ( TM , initializeSubtargetDependencies ( TT , GPU , FS ) ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , AS ( <STR_LIT> ( TT ) ) {


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> <ISA_LIT>MachineFunctionInfo :: <ISA_LIT>MachineFunctionInfo ( const MachineFunction & MF ) : <ISA_LIT>MachineFunction ( MF ) , TIDReg ( <STR_LIT> ) , HasSpilledVGPRs ( false ) , P<ISA_LIT>nputAddr ( <NUM_LIT> ) , NumUserSGPRs ( <NUM_LIT> ) , LDSWaveSpillSize ( <NUM_LIT> ) {


<s> if ( ! checkForImmediate ( S1 , V1 ) || ! checkForImmediate ( S3 , V3 ) ) return false ; unsigned Sub2 = DI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Sub4 = DI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Sub2 == <STR_LIT> && Sub4 == <STR_LIT> ) TV = V1 | ( V3 << <NUM_LIT> ) ; else if ( Sub2 == <STR_LIT> && Sub4 == <STR_LIT> ) TV = V3 | ( V1 << <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; break ; } default : return false ; } switch ( MO . getSubReg ( ) ) { case <STR_LIT> : Val = TV & <NUM_LIT> ; break ; case <STR_LIT> : Val = ( TV >> <NUM_LIT> ) & <NUM_LIT> ; break ; default : Val = TV ; break ; }


<s> copySTI ( ) . setFeatureBits ( FeatureBits ) ; setAvailableFeatures ( ComputeAvailableFeatures ( FeatureBits ) ) ; ParserOptions = ParserOptionsStack . pop_back_val ( ) ;


<s> bool isMachineVerifierClean ( ) const override {


<s> void <ISA_LIT>DelaySlotFiller :: insertNOPAfter ( MachineBasicBlock & MBB , const MachineBasicBlock :: iterator I ) { MachineBasicBlock :: iterator NI = std :: next ( I ) ; TII -> insertNoop ( MBB , NI ) ;


<s> assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; if ( IndexVT == <STR_LIT> ) return SDValue ( ) ; MVT OrigVT = VT ; if ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && ! IndexVT . is512BitVector ( ) ) { unsigned Factor = std :: min ( <NUM_LIT> / VT . getSizeInBits ( ) , <NUM_LIT> / IndexVT . getSizeInBits ( ) ) ; unsigned NumElts = VT . getVectorNumElements ( ) * Factor ; VT = <STR_LIT> ( VT . getVectorElementType ( ) , NumElts ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , NumElts ) ; MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; PassThru = ExtendToType ( PassThru , VT , DAG ) ; Index = ExtendToType ( Index , IndexVT , DAG ) ; Mask = ExtendToType ( Mask , MaskVT , DAG , true ) ; }

SDValue Ops [ ] = { N -> getChain ( ) , PassThru , Mask , N -> getBasePtr ( ) , Index , N -> getScale ( ) } ;


<s> bool isForcedVOP3 ( ) const { return ForcedEncodingSize == <NUM_LIT> ;


<s> int64_t Value = CE -> getValue ( ) ;

return Value >= <NUM_LIT> && Value < <NUM_LIT> ;


<s> switch ( mode ) { case CCmode : return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C | CC_FLAG_V ; case CCZNCmode :


<s> if ( scaleShuffleElements ( SVN0 -> getMask ( ) , <NUM_LIT> , ShuffleMask0 ) && scaleShuffleElements ( SVN1 -> getMask ( ) , <NUM_LIT> , ShuffleMask1 ) ) { SDValue Op00 = SVN0 -> getOperand ( <NUM_LIT> ) ; SDValue Op01 = SVN0 -> getOperand ( <NUM_LIT> ) ; SDValue Op10 = SVN1 -> getOperand ( <NUM_LIT> ) ; SDValue Op11 = SVN1 -> getOperand ( <NUM_LIT> ) ; if ( ( Op00 == Op11 ) && ( Op01 == Op10 ) ) { std :: swap ( Op10 , Op11 ) ; ShuffleVectorSDNode :: commuteMask ( ShuffleMask1 ) ; } if ( ( Op00 == Op10 ) && ( Op01 == Op11 ) ) { SmallVector < int , <NUM_LIT> > ShuffleMask ; ShuffleMask . append ( ShuffleMask0 . begin ( ) , ShuffleMask0 . end ( ) ) ; ShuffleMask . append ( ShuffleMask1 . begin ( ) , ShuffleMask1 . end ( ) ) ; SDLoc DL ( N ) ; SDValue Res = DAG . getNode ( Opcode , DL , VT , Op00 , Op01 ) ;

Res = DAG . getBitcast ( <STR_LIT> , Res ) ;


<s> explicit <ISA_LIT>GenericMCSymbolRefExpr ( const MCSymbolRefExpr * _SymExpr ) : SymExpr ( _SymExpr ) {


<s> bool <ISA_LIT>TTIImpl :: shouldMaximizeVectorBandwidth ( bool OptSize ) const {


<s> bool MetadataStreamerV3 :: emitTo ( <ISA_LIT>TargetStreamer & TargetStreamer ) { return TargetStreamer . EmitHSAMetadata ( * HSAMetadataDoc , true ) ;


<s> static __inline vec_double2 spu_rlqw ( vec_double2 a , int count ) {

return ( ( vec_double2 ) ( si_rotqbi ( ( qword ) ( a ) , si_from_int ( count ) ) ) ) ;


<s> else return false ; if ( offset == const0_rtx ) return true ; switch ( * symbol_type ) { case SYMBOL_ABSOLUTE : case SYMBOL_PCREL : case SYMBOL_TLS_LE : return sext_hwi ( INTVAL ( offset ) , <NUM_LIT> ) == INTVAL ( offset ) ; default : return false ;


<s> } } if ( TARGET_V9 && TARGET_ARCH64 && GET_MODE ( x ) == DImode && ! ( TARGET_VIS3 && ( code == GTU || code == LTU ) ) && gen_v9_scc ( operands [ <NUM_LIT> ] , code , x , y ) ) return true ; if ( code == GTU || code == LEU ) { if ( ( GET_CODE ( x ) == REG || GET_CODE ( x ) == SUBREG ) && ( GET_CODE ( y ) == REG || GET_CODE ( y ) == SUBREG ) ) { tem = x ; x = y ; y = tem ; code = swap_condition ( code ) ; } } if ( code == LTU || ( ! TARGET_VIS3 && code == GEU ) ) { emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_fmt_ee ( code , GET_MODE ( operands [ <NUM_LIT> ] ) , gen_compare_reg_1 ( code , x , y ) , const0_rtx ) ) ) ;


<s> void setArgRegsSaveSize ( unsigned s ) {


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , PtrVT ) ;

while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , DL , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> bool <ISA_LIT>MCExpr :: EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout ) const { return getSubExpr ( ) -> EvaluateAsRelocatable ( Res , Layout ) ;


<s> for ( LoadSDNode * LD : LoadsToReplace ) { SDLoc SL ( LD ) ; SDValue NewLoad = CurDAG -> getLoad ( <STR_LIT> , SL , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getMemOperand ( ) ) ; SDValue BitCast = CurDAG -> getNode ( <STR_LIT> , SL , <STR_LIT> , NewLoad ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLoad . getValue ( <NUM_LIT> ) ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , BitCast ) ; Modified = true ; } for ( StoreSDNode * ST : StoresToReplace ) { SDValue NewValue = CurDAG -> getNode ( <STR_LIT> , SDLoc ( ST ) , <STR_LIT> , ST -> getValue ( ) ) ; const SDValue StoreOps [ ] = { ST -> getChain ( ) , NewValue , ST -> getBasePtr ( ) , ST -> getOffset ( ) } ; CurDAG -> UpdateNodeOperands ( ST , StoreOps ) ; Modified = true ; } if ( Modified ) CurDAG -> RemoveDeadNodes ( ) ;


<s> void EmitFunctionEntryLabel ( ) override {


<s> SDNode * Extract = * UI ; if ( Extract -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( Extract -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SDValue ( ) ; if ( ! Extract -> hasOneUse ( ) ) return SDValue ( ) ; if ( Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> && Extract -> use_begin ( ) -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; ExtractedElements |= <NUM_LIT> << cast < ConstantSDNode > ( Extract -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; DebugLoc dl = InputVector . getDebugLoc ( ) ; SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ;

SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> if ( ! searchRange ( MBB , ReverseIter ( Slot ) , MBB . rend ( ) , RegDU , MemDU , Slot , Filler ) ) return false ; MBB . splice ( std :: next ( Slot ) , & MBB , std :: next ( Filler ) . base ( ) ) ; MIBundleBuilder ( MBB , Slot , std :: next ( Slot , <NUM_LIT> ) ) ; ++ UsefulSlots ; return true ;


<s> NewBldVec [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else if ( C -> isExactlyValue ( <NUM_LIT> ) ) { RemapSwizzle [ i ] = <NUM_LIT> ; NewBldVec [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } } if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) continue ; for ( unsigned j = <NUM_LIT> ; j < i ; j ++ ) { if ( NewBldVec [ i ] == NewBldVec [ j ] ) { NewBldVec [ i ] = DAG . getUNDEF ( NewBldVec [ i ] . getValueType ( ) ) ;


<s> bool IndexIs256 = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; if ( IndexIs128 || IndexIs256 ) { unsigned IndexOffset = insn . sibIndex - ( insn . addressSize == <NUM_LIT> ? SIB_INDEX_RAX : SIB_INDEX_EAX ) ; SIBIndex IndexBase = IndexIs256 ? SIB_INDEX_YMM0 : SIB_INDEX_XMM0 ; insn . sibIndex = ( SIBIndex ) ( IndexBase + ( insn . sibIndex == SIB_INDEX_NONE ? <NUM_LIT> : IndexOffset ) ) ; } if ( insn . sibIndex != SIB_INDEX_NONE ) { switch ( insn . sibIndex ) { default : debug ( <STR_LIT> ) ; return true ; case SIB_INDEX_ ## x : \ indexReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; EA_BASES_32BIT EA_BASES_64BIT REGS_XMM REGS_YMM } } else { indexReg = MCOperand :: CreateReg ( <NUM_LIT> ) ; } scaleAmount = MCOperand :: CreateImm ( insn . sibScale ) ; } else { switch ( insn . eaBase ) { case EA_BASE_NONE : if ( insn . eaDisplacement == EA_DISP_NONE ) { debug ( <STR_LIT> ) ; return true ; } if ( insn . mode == MODE_64BIT ) { pcrel = insn . startLocation + insn . displacementOffset + insn . displacementSize ; tryAddingPcLoadReferenceComment ( insn . startLocation + insn . displacementOffset , insn . displacement + pcrel , Dis ) ; baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; }

else baseReg = MCOperand :: CreateReg ( <NUM_LIT> ) ;


<s> return ( vector unsigned int ) __builtin_altivec_vspltw ( ( vector signed int ) a1 , a2 ) ;


<s> Type * MemAccessTy = ( isa < LoadInst > ( I ) ? I -> getType ( ) : I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; bool IsFPAccess = MemAccessTy -> isFloatingPointTy ( ) ; bool IsVectorAccess = MemAccessTy -> isVectorTy ( ) ; if ( ! IsVectorAccess && isa < StoreInst > ( I ) ) { Value * DataOp = I -> getOperand ( <NUM_LIT> ) ; if ( isa < ExtractElementInst > ( DataOp ) ) IsVectorAccess = true ; } if ( ! IsVectorAccess && isa < LoadInst > ( I ) && I -> hasOneUse ( ) ) { User * LoadUser = * I -> user_begin ( ) ; if ( isa < InsertElementInst > ( LoadUser ) ) IsVectorAccess = true ; } if ( ! isUInt < <NUM_LIT> > ( Offset ) && ( IsFPAccess || IsVectorAccess ) ) return false ;


<s> bool <ISA_LIT>FastISel :: SelectFPTrunc ( const Instruction * I ) { if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! ( I -> getType ( ) -> isFloatTy ( ) && V -> getType ( ) -> isDoubleTy ( ) ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ; UpdateValueMap ( I , Result ) ;


<s> return rs6000_darwin64_abi && ( ( mode == BLKmode && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) > <NUM_LIT> ) || ( type && TREE_CODE ( type ) == RECORD_TYPE && int_size_in_bytes ( type ) == <NUM_LIT> ) ) ? <NUM_LIT> : <NUM_LIT> ;


<s> for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT VT = VA . getValVT ( ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VT , InFlag ) . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const {

return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) , IsLittle , Is64Bit ) ;


return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> bool andOp = false ; if ( base -> getOpcode ( ) == Instruction :: Shl ) { shift = dyn_cast < Constant > ( base -> getOperand ( <NUM_LIT> ) ) ; } else if ( base -> getOpcode ( ) == Instruction :: And ) { mask = dyn_cast < Constant > ( base -> getOperand ( <NUM_LIT> ) ) ; andOp = true ; } else { if ( mDebug ) { dbgs ( ) << <STR_LIT> ; } return false ; } src = dyn_cast < Instruction > ( base -> getOperand ( <NUM_LIT> ) ) ; if ( ! src ) { if ( mDebug ) { dbgs ( ) << <STR_LIT> ; } return false ; }


<s> return ( int8x16_t ) __builtin_aarch64_sqabsv16qi ( __a ) ;


<s> else if ( TheTriple . isOSBinFormatCOFF ( ) ) MAI = new <ISA_LIT>MCAsmInfoCOFF ( ) ; else { assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ; MAI = new <ISA_LIT>MCAsmInfoELF ( TheTriple ) ; } unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ;


<s> return ( unsigned ) ( imm & <NUM_LIT> ) ;


<s> const TargetFrameLowering * getFrameLowering ( ) const override {


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveVariantPCS ( MCSymbol * Symbol ) { getStreamer ( ) . getAssembler ( ) . registerSymbol ( * Symbol ) ;

cast < MCSymbolELF > ( Symbol ) -> setOther ( ELF :: STO_AARCH64_VARIANT_PCS ) ;


ggc_add_rtx_root ( branch_cmp , sizeof ( branch_cmp ) / sizeof ( rtx ) ) ;


<s> return ( int8x8_t ) __builtin_neon_vshrn_nv8hi ( __a , __b ) ;


<s> bool enableShrinkWrapping ( const MachineFunction & MF ) const override {


<s> else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { if ( is_ha != NULL ) * is_ha = true ; * count = <NUM_LIT> ; new_mode = GET_MODE_INNER ( mode ) ; } else if ( type && composite_p ) { int ag_count = aapcs_vfp_sub_candidate ( type , & new_mode ) ;


<s> CASE ( MemoryModel , Simple ) CASE ( MemoryModel , GLSL450 ) CASE ( MemoryModel , OpenCL ) CASE ( MemoryModel , VulkanKHR ) break ;


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , SMLoc NameLoc , OperandVector & Operands ) { llvm_unreachable ( <STR_LIT> ) ;


<s> return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ;


<s> clobbers . safe_push ( gen_rtx_REG ( SImode , TA_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , TA_REGNUM ) ; return NULL ;


<s> if ( EnableCondOpt ) addPass ( create<ISA_LIT>ConditionOptimizerPass ( ) ) ;

if ( EnableCCMP ) addPass ( create<ISA_LIT>ConditionalCompares ( ) ) ;


return ( __m512i ) __builtin_ia32_vpconflictsi_512_mask ( ( __v16si ) __A , ( __v16si ) _mm512_setzero_si512 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> for ( MCSuperRegIterator Super ( Reg , this ) ; Super . isValid ( ) ; ++ Super ) if ( RC -> contains ( * Super ) ) return * Super ;


<s> MCSubtargetInfo STI = getSubtargetInfo ( ) ; MCInst TmpInst ; MCInstLowering . Lower ( MI , TmpInst ) ;

OutStreamer -> emitInstruction ( TmpInst , STI ) ;


<s> O << ( short ) MI -> getOperand ( OpNo ) . getImm ( ) ;


<s> static bool isVZIPMask ( ArrayRef < int > M , EVT VT , unsigned & WhichResult ) { unsigned EltSz = VT . getScalarSizeInBits ( ) ; if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ;

unsigned Idx = WhichResult * NumElts / <NUM_LIT> ;


<s> if ( ! CI -> isTailCall ( ) ) return false ; ImmutableCallSite CS ( CI ) ; CallingConv :: ID CalleeCC = CS . getCallingConv ( ) ; if ( ! mayTailCallThisCC ( CalleeCC ) ) return false ;


<s> if ( ! Cand . isValid ( ) ) return ;

if ( TryCand . Reason != NodeOrder && TryCand . Reason != NoCand ) return ;


<s> printSysRegOperand ( <STR_LIT> ( ) , MI , OpNum , O ) ;


<s> bool shouldMaximizeVectorBandwidth ( ) const {


<s> static inline unsigned getT1tRm ( uint32_t insn ) { return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> int i , regno ; rtx op ; op = frv_read_argument ( call , index ) ; if ( GET_CODE ( op ) != CONST_INT || INTVAL ( op ) < <NUM_LIT> || INTVAL ( op ) > IACC_LAST - IACC_FIRST || ( ( INTVAL ( op ) * <NUM_LIT> ) & ( GET_MODE_SIZE ( mode ) - <NUM_LIT> ) ) != <NUM_LIT> ) { error ( <STR_LIT> ) ; op = const0_rtx ; } regno = INTVAL ( op ) + IACC_FIRST ;

for ( i = <NUM_LIT> ; i < HARD_REGNO_NREGS ( regno , mode ) ; i ++ ) global_regs [ regno + i ] = <NUM_LIT> ;


<s> bool <ISA_LIT>InstPrinter :: printGetPCX ( const MCInst * MI , unsigned opNum , raw_ostream & O ) { assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; if ( BW < W || ! HBS :: isEqual ( RC , <NUM_LIT> , SC , BN , W ) ) continue ; if ( ! validateReg ( RS , NewOpc , <NUM_LIT> ) ) continue ; Register NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; auto MIB = BuildMI ( B , At , DL , HII . get ( NewOpc ) , NewR ) . addReg ( RS . Reg , <NUM_LIT> , RS . Sub ) ; if ( NewOpc == <STR_LIT> ) MIB . addImm ( ( <NUM_LIT> << W ) - <NUM_LIT> ) ; else if ( NewOpc == <STR_LIT> ) MIB . addImm ( W ) . addImm ( <NUM_LIT> ) ; HBS :: replaceSubWithSub ( RD . Reg , RD . Sub , NewR , <NUM_LIT> , MRI ) ;

BT . put ( BitTracker :: RegisterRef ( NewR ) , RC ) ;


<s> if ( ! reload_completed || frame_pointer_needed ) return <NUM_LIT> ; if ( crtl -> args . pops_args && crtl -> args . size >= <NUM_LIT> ) return <NUM_LIT> ;


<s> break ; case <STR_LIT> : if ( ! CuMode ) { if ( ( Op & <STR_LIT> ) != <STR_LIT> ) VMCnt |= true ; if ( ( Op & <STR_LIT> ) != <STR_LIT> ) VSCnt |= true ; } break ; case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( ( AddrSpace & <STR_LIT> ) != <STR_LIT> ) { switch ( Scope ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LGKMCnt |= IsCrossAddrSpaceOrdering ; break ; case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( ( AddrSpace & <STR_LIT> ) != <STR_LIT> ) { switch ( Scope ) { case <STR_LIT> : case <STR_LIT> : LGKMCnt |= IsCrossAddrSpaceOrdering ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } } if ( VMCnt || LGKMCnt ) { unsigned WaitCntImmediate = <STR_LIT> ( IV , VMCnt ? <NUM_LIT> : getVmcntBitMask ( IV ) , getExpcntBitMask ( IV ) , LGKMCnt ? <NUM_LIT> : getLgkmcntBitMask ( IV ) ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addImm ( WaitCntImmediate ) ; Changed = true ; } if ( VSCnt ) { BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) . addImm ( <NUM_LIT> ) ; Changed = true ; } if ( Pos == Position :: AFTER ) -- MI ;


<s> if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ; VectorVal = convertToScalableVector ( ContainerVT , VectorVal , DAG , Subtarget ) ; } MVT M1VT = getLMUL1VT ( VectorVal . getSimpleValueType ( ) ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Mask , VL ;

std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ;


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) O << getRegisterName ( Op . getReg ( ) ) ; else if ( Op . isImm ( ) ) O << Op . getImm ( ) ; else if ( Op . isExpr ( ) ) O << * Op . getExpr ( ) ; else assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> <ISA_LIT>MachObjectWriter ( bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) : MCMachObjectTargetWriter ( Is64Bit , CPUType , CPUSubtype ) {


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( MVT VT ) const override {

if ( VT . getScalarSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> ) return TypeWidenVector ;


<s> bool isSVEPredicateReg ( ) const { return Kind == k_Register && Reg . Kind == RegKind :: SVEPredicate && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectGlobalValueConstantOffset ( SDValue Addr , SDValue & IntPtr ) { if ( ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( Addr ) ) { IntPtr = CurDAG -> getIntPtrConstant ( Cst -> getZExtValue ( ) / <NUM_LIT> , SDLoc ( Addr ) , true ) ; return true ; }


<s> for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } return AsmPrinter :: doFinalization ( M ) ;


<s> auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = IsOptNone ? nullptr : & getAnalysis < MachineDominatorTree > ( ) ;

<ISA_LIT>PreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , MDT ) ;


<s> MCSymbol * DoClearBss = Context . getOrCreateSymbol ( <STR_LIT> ) ; OS . emitRawComment ( <STR_LIT> ) ; OS . emitRawComment ( <STR_LIT> ) ;

OS . emitSymbolAttribute ( DoCopyData , MCSA_Global ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> DECL_ALIGN ( fndecl ) = FUNCTION_BOUNDARY_P ( TREE_TARGET_OPTION ( callee_tree ) -> x_target_flags ) ;


<s> for ( std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > v : Variants ) { Temp = Scheduler . scheduleVariant ( v . first , v . second ) ; if ( Temp . MaxVGPRUsage < Best . MaxVGPRUsage ) Best = Temp ; } } ScheduledSUnits = Best . SUs ; ScheduledSUnitsInv . resize ( SUnits . size ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ( unsigned ) SUnits . size ( ) ; i != e ; ++ i ) { ScheduledSUnitsInv [ ScheduledSUnits [ i ] ] = i ; } moveLowLatencies ( ) ; assert ( TopRPTracker . getPos ( ) == RegionBegin && <STR_LIT> ) ; TopRPTracker . setPos ( CurrentTop ) ; for ( std :: vector < unsigned > :: iterator I = ScheduledSUnits . begin ( ) , E = ScheduledSUnits . end ( ) ; I != E ; ++ I ) { SUnit * SU = & SUnits [ * I ] ; scheduleMI ( SU , true ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SU -> NodeNum << <STR_LIT> << * SU -> getInstr ( ) ) ;


<s> fprintf ( dump_file , <STR_LIT> ) ; dump_swap_insn_table ( insn_entry ) ; } unsigned e = get_max_uid ( ) , i ; for ( i = <NUM_LIT> ; i < e ; ++ i ) { if ( ! insn_entry [ i ] . is_relevant ) continue ; swap_web_entry * root = ( swap_web_entry * ) ( & insn_entry [ i ] ) -> unionfind_root ( ) ; if ( insn_entry [ i ] . is_live_in || insn_entry [ i ] . is_live_out || ( insn_entry [ i ] . contains_subreg && insn_entry [ i ] . special_handling != SH_SUBREG ) || insn_entry [ i ] . is_128_int || insn_entry [ i ] . is_call || ! ( insn_entry [ i ] . is_swappable || insn_entry [ i ] . is_swap ) ) root -> web_not_optimizable = <NUM_LIT> ; else if ( ( insn_entry [ i ] . is_load || insn_entry [ i ] . is_store ) && ! insn_entry [ i ] . is_swap && ! insn_entry [ i ] . is_swappable ) root -> web_not_optimizable = <NUM_LIT> ; else if ( insn_entry [ i ] . is_load && insn_entry [ i ] . is_swap ) { rtx insn = insn_entry [ i ] . insn ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref def ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! chain_contains_only_swaps ( insn_entry , link , FOR_LOADS ) ) { root -> web_not_optimizable = <NUM_LIT> ; break ; } } } else if ( insn_entry [ i ] . is_store && insn_entry [ i ] . is_swap ) { rtx insn = insn_entry [ i ] . insn ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * link = DF_REF_CHAIN ( use ) ; if ( ! chain_contains_only_swaps ( insn_entry , link , FOR_STORES ) ) { root -> web_not_optimizable = <NUM_LIT> ; break ; } }


if ( ! aarch64_sve_inc_dec_immediate_p ( x , & factor , & nelts_per_vq ) ) gcc_unreachable ( ) ;


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> unsigned <ISA_LIT>InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> arcCC = ISDCCto<ISA_LIT>CC ( CC ) ; assert ( LHS . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , LHS , RHS , DAG . getConstant ( arcCC , dl , <STR_LIT> ) ) ;


<s> SmallVector < MachineOperand * > DefTiles ; for ( MachineOperand & MO : KeyMI -> operands ( ) ) { if ( ! isTilePhysReg ( MO ) ) continue ; if ( MO . isDef ( ) ) DefTiles . push_back ( & MO ) ; else ShapedTiles . push_back ( & MO ) ; } ShapedTiles . append ( DefTiles ) ;


<s> int <ISA_LIT>TTIImpl :: getInterleavedMemoryOpCost ( unsigned Opcode , Type * VecTy , unsigned Factor , ArrayRef < unsigned > Indices , unsigned Alignment , unsigned AddressSpace , TTI :: TargetCostKind CostKind , bool UseMaskForCond , bool UseMaskForGaps ) { if ( UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , CostKind , UseMaskForCond , UseMaskForGaps ) ; assert ( isa < VectorType > ( VecTy ) && <STR_LIT> ) ;

std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , VecTy ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> exception_nesting ++ ; if ( trap_pending ) goto close_shadow ; break ; case NOTE_INSN_EH_REGION_END : exception_nesting -- ; if ( trap_pending ) goto close_shadow ; break ; case NOTE_INSN_EPILOGUE_BEG : if ( trap_pending && alpha_tp >= ALPHA_TP_FUNC ) goto close_shadow ; break ; } } else if ( trap_pending ) { if ( alpha_tp == ALPHA_TP_FUNC ) { if ( GET_CODE ( i ) == JUMP_INSN && GET_CODE ( PATTERN ( i ) ) == RETURN ) goto close_shadow ; } else if ( alpha_tp == ALPHA_TP_INSN ) { if ( optimize > <NUM_LIT> ) { struct shadow_summary sum ; sum . used . i = <NUM_LIT> ; sum . used . fp = <NUM_LIT> ; sum . used . mem = <NUM_LIT> ; sum . defd = sum . used ; switch ( GET_CODE ( i ) ) { case INSN : if ( GET_CODE ( PATTERN ( i ) ) == USE || GET_CODE ( PATTERN ( i ) ) == CLOBBER ) break ; summarize_insn ( PATTERN ( i ) , & sum , <NUM_LIT> ) ; if ( ( sum . defd . i & shadow . defd . i ) || ( sum . defd . fp & shadow . defd . fp ) ) { goto close_shadow ; } shadow . used . i |= sum . used . i ; shadow . used . fp |= sum . used . fp ; shadow . used . mem |= sum . used . mem ; shadow . defd . i |= sum . defd . i ; shadow . defd . fp |= sum . defd . fp ; shadow . defd . mem |= sum . defd . mem ; if ( ( sum . defd . i & shadow . used . i ) || ( sum . defd . fp & shadow . used . fp ) || ( sum . defd . mem & shadow . used . mem ) ) { gcc_assert ( get_attr_trap ( i ) != TRAP_YES || ( ! ( sum . defd . i & sum . used . i ) && ! ( sum . defd . fp & sum . used . fp ) ) ) ; goto close_shadow ; } break ; case JUMP_INSN : case CALL_INSN : case CODE_LABEL : goto close_shadow ; default : gcc_unreachable ( ) ; } } else { close_shadow : n = emit_insn_before ( gen_trapb ( ) , i ) ; PUT_MODE ( n , TImode ) ; PUT_MODE ( i , TImode ) ; trap_pending = <NUM_LIT> ; shadow . used . i = <NUM_LIT> ; shadow . used . fp = <NUM_LIT> ; shadow . used . mem = <NUM_LIT> ; shadow . defd = shadow . used ; }


<s> gtop = build ( COMPONENT_REF , TREE_TYPE ( f_gtop ) , valist , f_gtop , NULL_TREE ) ; ftop = build ( COMPONENT_REF , TREE_TYPE ( f_ftop ) , valist , f_ftop , NULL_TREE ) ; goff = build ( COMPONENT_REF , TREE_TYPE ( f_goff ) , valist , f_goff , NULL_TREE ) ; foff = build ( COMPONENT_REF , TREE_TYPE ( f_foff ) , valist , f_foff , NULL_TREE ) ; t = make_tree ( TREE_TYPE ( ovfl ) , virtual_incoming_args_rtx ) ; if ( cum -> stack_words > <NUM_LIT> ) t = build ( PLUS_EXPR , TREE_TYPE ( ovfl ) , t , build_int_cst ( NULL_TREE , cum -> stack_words * UNITS_PER_WORD ) ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( ovfl ) , ovfl , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( gtop ) , virtual_incoming_args_rtx ) ; t = build ( MODIFY_EXPR , TREE_TYPE ( gtop ) , gtop , t ) ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; t = make_tree ( TREE_TYPE ( ftop ) , virtual_incoming_args_rtx ) ; fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - <NUM_LIT> ; fpr_offset &= ~ ( UNITS_PER_FPVALUE - <NUM_LIT> ) ; if ( fpr_offset ) t = build ( PLUS_EXPR , TREE_TYPE ( ftop ) , t , build_int_cst ( NULL_TREE , - fpr_offset ) ) ;

t = build ( MODIFY_EXPR , TREE_TYPE ( ftop ) , ftop , t ) ;


<s> const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ;

return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> return ; default : gcc_unreachable ( ) ; } } temp = gen_reg_rtx ( imode ) ; if ( imode == GET_MODE ( same ) ) temp2 = same ; else if ( GET_MODE_SIZE ( imode ) >= UNITS_PER_WORD ) temp2 = simplify_gen_subreg ( imode , same , GET_MODE ( same ) , <NUM_LIT> ) ; else temp2 = lowpart_subreg ( imode , same , GET_MODE ( same ) ) ; emit_move_insn ( temp , temp2 ) ; switch ( vmode ) { case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : mips_emit_move ( target , gen_rtx_VEC_DUPLICATE ( vmode , temp ) ) ; break ; case E_V4SFmode : emit_insn ( gen_msa_splati_w_f_scalar ( target , temp ) ) ; break ; case E_V2DFmode : emit_insn ( gen_msa_splati_d_f_scalar ( target , temp ) ) ; break ; default : gcc_unreachable ( ) ; } } else { emit_move_insn ( target , CONST0_RTX ( vmode ) ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { rtx temp = gen_reg_rtx ( imode ) ; emit_move_insn ( temp , XVECEXP ( vals , <NUM_LIT> , i ) ) ; switch ( vmode ) { case E_V16QImode : emit_insn ( gen_vec_setv16qi ( target , temp , GEN_INT ( i ) ) ) ; break ; case E_V8HImode :

emit_insn ( gen_vec_setv8hi ( target , temp , GEN_INT ( i ) ) ) ;


<s> static std :: unique_ptr < TargetLoweringObjectFile > createTLOF ( ) {

return std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , DL ( <STR_LIT> ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) {


<s> assert ( Map . find ( NameLibcall . first ) == Map . end ( ) && <STR_LIT> ) ; Map [ NameLibcall . first ] = NameLibcall . second ; } } Map [ <STR_LIT> ] = RTLIB :: FPEXT_F16_F32 ; Map [ <STR_LIT> ] = RTLIB :: FPROUND_F32_F16 ;

Map [ <STR_LIT> ] = RTLIB :: RETURN_ADDRESS ;


<s> if ( Signed ) { if ( K0 -> getAPIntValue ( ) . sge ( K1 -> getAPIntValue ( ) ) ) return SDValue ( ) ; } else { if ( K0 -> getAPIntValue ( ) . uge ( K1 -> getAPIntValue ( ) ) ) return SDValue ( ) ; } EVT VT = K0 -> getValueType ( <NUM_LIT> ) ; unsigned Med3Opc = Signed ? <STR_LIT> : <STR_LIT> ; if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasMed3_16 ( ) ) ) { return DAG . getNode ( Med3Opc , SL , VT , Op0 . getOperand ( <NUM_LIT> ) , SDValue ( K0 , <NUM_LIT> ) , SDValue ( K1 , <NUM_LIT> ) ) ; } if ( VT == <STR_LIT> ) { MVT NVT = <STR_LIT> ; unsigned ExtOp = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Tmp1 = DAG . getNode ( ExtOp , SL , NVT , Op0 -> getOperand ( <NUM_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( ExtOp , SL , NVT , Op0 -> getOperand ( <NUM_LIT> ) ) ; SDValue Tmp3 = DAG . getNode ( ExtOp , SL , NVT , Op1 ) ;

SDValue Med3 = DAG . getNode ( Med3Opc , SL , NVT , Tmp1 , Tmp2 , Tmp3 ) ;


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand ( MCOp ) ;


<s> if ( Subtarget -> hasAddr64 ( ) ) { SDValue SRsrc , VAddr , SOffset , Offset , SLC ; if ( SelectMUBUFAddr64 ( Mem -> getBasePtr ( ) , SRsrc , VAddr , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , VAddr , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } } if ( ! CmpSwap ) { SDValue SRsrc , SOffset , Offset , SLC ; if ( SelectMUBUFOffset ( Mem -> getBasePtr ( ) , SRsrc , SOffset , Offset , SLC ) ) { unsigned Opcode = Is32 ? <STR_LIT> : <STR_LIT> ; SDValue CmpVal = Mem -> getOperand ( <NUM_LIT> ) ; SDValue GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue Ops [ ] = { CmpVal , SRsrc , SOffset , Offset , GLC , SLC , Mem -> getChain ( ) } ; CmpSwap = CurDAG -> getMachineNode ( Opcode , SL , Mem -> getVTList ( ) , Ops ) ; } }


<s> SDValue Sub = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( - C -> getAPIntValue ( ) , DL , C -> getValueType ( <NUM_LIT> ) ) ) ; Results . push_back ( Sub ) ; } break ; } default : { SDValue Res = LowerOperation ( SDValue ( N , <NUM_LIT> ) , DAG ) ; for ( unsigned I = <NUM_LIT> , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; break ; }


<s> DefCycle = RegNo / <NUM_LIT> ; if ( DefCycle < <NUM_LIT> ) DefCycle = <NUM_LIT> ; DefCycle += <NUM_LIT> ; } else if ( Subtarget . isCortexA9 ( ) ) { DefCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; DefCycle += <NUM_LIT> ; } else { DefCycle = RegNo + <NUM_LIT> ; }


<s> } if ( ! ( REG_P ( op ) && HARD_REGISTER_P ( op ) ) ) continue ; op_alt = recog_op_alt ; win = ! n_alternatives ; alternative_mask preferred = get_preferred_alternatives ( insn ) ; for ( j = <NUM_LIT> ; j < n_alternatives ; j ++ , op_alt += n_operands ) { if ( ! TEST_BIT ( preferred , j ) ) continue ; if ( op_alt [ i ] . anything_ok || ( op_alt [ i ] . matches != - <NUM_LIT> && operands_match_p ( recog_data . operand [ i ] , recog_data . operand [ op_alt [ i ] . matches ] ) ) || reg_fits_class_p ( op , op_alt [ i ] . cl , offset , mode ) ) { win = true ; break ; }


<s> SmallSet < int64_t , <NUM_LIT> > Literals ; for ( unsigned i = <NUM_LIT> , n = MIs . size ( ) ; i < n ; i ++ ) { MachineInstr & MI = * MIs [ i ] ; if ( ! isALUInstr ( MI . getOpcode ( ) ) ) continue ; for ( const auto & Src : getSrcs ( MI ) ) { if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ;

if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) {


<s> if ( ! MO1 . isReg ( ) ) { printOperand ( MI , Op ) ; return ; } assert ( TargetRegisterInfo :: isPhysicalRegister ( MO1 . getReg ( ) ) ) ; if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { <STR_LIT> Mode = <STR_LIT> ( MO2 . getImm ( ) ) ; if ( MO1 . getReg ( ) == <STR_LIT> ) { bool isFLDM = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ; O << <STR_LIT> ( Mode , isFLDM ) ; } else O << <STR_LIT> ( Mode ) ; return ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << TM . getRegisterInfo ( ) -> get ( MO1 . getReg ( ) ) . AsmName ; if ( <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> ; return ;


<s> return std :: max ( Log2 ( std :: max ( PostAlign , Align ) ) , internalKnownBits ( ) ) ;


<s> if ( MO . isImm ( ) ) return ( getMachineOpValue ( MI , MO , Fixups ) & <NUM_LIT> ) | RegBits ;

if ( isSVR4ABI ( ) && is64BitMode ( ) ) Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> if ( Trunc . getOpcode ( ) != <STR_LIT> || ! N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SDValue ( ) ; SDLoc DL ( Trunc ) ; if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; else if ( isVMOVNTruncMask ( N -> getMask ( ) , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , Trunc . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> bool Changed = false ; for ( auto * InnerML : * ML ) Changed |= processPostOrderLoops ( InnerML ) ;

return Changed | fixBackwardsWLS ( ML ) ;


<s> return __builtin_mve_vrev64q_uv16qi ( __a ) ;


<s> unsigned int val8 = UINTVAL ( xval8 ) & GET_MODE_MASK ( QImode ) ; if ( ( pop_mask & ( <NUM_LIT> << popcount_hwi ( val8 ) ) ) == <NUM_LIT> ) return false ; } return true ;


<s> const unsigned NumElts = VVT . getVectorNumElements ( ) ; const MVT EltVT = VVT . getVectorElementType ( ) ; if ( VVT . is512BitVector ( ) ) { if ( Subtarget -> hasAVX512 ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } if ( Subtarget -> hasBWI ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) { case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; } } if ( VVT . is256BitVector ( ) || VVT . is128BitVector ( ) ) {

if ( Subtarget -> hasVLX ( ) ) if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) switch ( NumElts ) {


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = DebugLoc ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( is64bit ) { unsigned LocalReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; } else { unsigned LocalReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , dl , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( LocalReg ) ; BuildMI ( MBB , MI , dl , MF . getTarget ( ) . getInstrInfo ( ) -> get ( <STR_LIT> ) , LocalReg ) . addImm ( MF . getFunctionNumber ( ) ) ; }


<s> if ( aarch64_simd_types [ i ] . mode == mode && aarch64_simd_types [ i ] . q == q ) return aarch64_simd_types [ i ] . itype ; if ( aarch64_simd_tuple_types [ i ] [ <NUM_LIT> ] != NULL_TREE ) for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) if ( aarch64_simd_tuple_modes [ i ] [ j ] == mode && aarch64_simd_types [ i ] . q == q ) return aarch64_simd_tuple_types [ i ] [ j ] ; } return NULL_TREE ;


<s> for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineInstr & MI = * I ; MachineOperand * ExecUse = MI . findRegisterUseOperand ( AMDGPU :: EXEC ) ; if ( ExecUse ) continue ; for ( const MachineOperand & Def : MI . operands ( ) ) { if ( ! Def . isReg ( ) || ! Def . isDef ( ) || ! TargetRegisterInfo :: isVirtualRegister ( Def . getReg ( ) ) ) continue ; const TargetRegisterClass * RC = MRI . getRegClass ( Def . getReg ( ) ) ; if ( ! TRI -> isSGPRClass ( RC ) ) continue ; LiveInterval & LI = LIS -> getInterval ( Def . getReg ( ) ) ;

for ( unsigned i = <NUM_LIT> , e = LI . size ( ) - <NUM_LIT> ; i != e ; ++ i ) {


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; O << '[' ;


<s> void <ISA_LIT>AsmPrinter :: printSOImmOperand ( const MachineInstr * MI , int OpNum ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ;

printSOImm ( O , MO . getImm ( ) , VerboseAsm , MAI ) ;


<s> sav = build3 ( COMPONENT_REF , TREE_TYPE ( f_sav ) , unshare_expr ( valist ) , f_sav , NULL_TREE ) ; words = crtl -> args . info . words ; n_gpr = crtl -> args . info . regno ; n_fpr = crtl -> args . info . sse_regno ; if ( cfun -> va_list_gpr_size ) { type = TREE_TYPE ( gpr ) ; t = build2 ( MODIFY_EXPR , type , gpr , build_int_cst ( type , n_gpr * <NUM_LIT> ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } if ( TARGET_SSE && cfun -> va_list_fpr_size ) { type = TREE_TYPE ( fpr ) ; t = build2 ( MODIFY_EXPR , type , fpr , build_int_cst ( type , n_fpr * <NUM_LIT> + <NUM_LIT> * X86_64_REGPARM_MAX ) ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; } type = TREE_TYPE ( ovf ) ; if ( cfun -> machine -> split_stack_varargs_pointer == NULL_RTX ) ovf_rtx = crtl -> args . internal_arg_pointer ; else ovf_rtx = cfun -> machine -> split_stack_varargs_pointer ; t = make_tree ( type , ovf_rtx ) ; if ( words != <NUM_LIT> ) t = fold_build_pointer_plus_hwi ( t , words * UNITS_PER_WORD ) ; if ( chkp_function_instrumented_p ( current_function_decl ) ) chkp_expand_bounds_reset_for_mem ( ovf , t ) ; t = build2 ( MODIFY_EXPR , type , ovf , t ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ;

if ( ix86_varargs_gpr_size || ix86_varargs_fpr_size ) {


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const { return <STR_LIT> ( funcInfo , libInfo ) ;


<s> if ( MF -> getFunction ( ) . getCallingConv ( ) != CallingConv :: CXX_FAST_TLS ) return nullptr ; if ( ! MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return nullptr ; bool SaveR2 = ! getReservedRegs ( * MF ) . test ( <STR_LIT> ) ; if ( Subtarget . hasAltivec ( ) ) return SaveR2 ? CSR_SVR464_R2_Altivec_ViaCopy_SaveList : CSR_SVR464_Altivec_ViaCopy_SaveList ; else return SaveR2 ? CSR_SVR464_R2_ViaCopy_SaveList : CSR_SVR464_ViaCopy_SaveList ;


<s> if ( const Function * F = dyn_cast < Function > ( GO ) ) if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( * F ) . genExecuteOnly ( ) && SK . isText ( ) ) return true ; return false ;


<s> static int mn10300_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t iclass , bool in ATTRIBUTE_UNUSED ) { enum reg_class rclass = ( enum reg_class ) iclass ; if ( rclass == FP_REGS ) return <NUM_LIT> ;


<s> if ( C . Flags & UnsafeRegsDead ) return false ; C . initLRU ( TRI ) ; LiveRegUnits LRU = C . LRU ; return ( ! LRU . available ( <STR_LIT> ) || ! LRU . available ( <STR_LIT> ) ) ; } ; if ( ! ( FlagsSetInAll & UnsafeRegsDead ) ) { llvm :: erase_if ( RepeatedSequenceLocs , CantGuaranteeValueAcrossCall ) ; if ( RepeatedSequenceLocs . size ( ) < <NUM_LIT> ) return outliner :: OutlinedFunction ( ) ; } unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; OutlinerCosts Costs ( Subtarget ) ; unsigned FrameID = MachineOutlinerDefault ; unsigned NumBytesToCreateFrame = Costs . FrameDefault ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs . FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs . CallTailCall ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs . FrameThunk ; SetCandidateCallInfo ( MachineOutlinerThunk , Costs . CallThunk ) ; } else { unsigned NumBytesNoStackCalls = <NUM_LIT> ; std :: vector < outliner :: Candidate > CandidatesWithoutStackFixups ; for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { C . initLRU ( TRI ) ; const auto Last = C . getMBB ( ) -> rbegin ( ) ; const bool LRIsAvailable = C . getMBB ( ) -> isReturnBlock ( ) && ! Last -> isCall ( ) ? isLRAvailable ( TRI , Last , ( MachineBasicBlock :: reverse_iterator ) C . front ( ) ) : C . LRU . available ( <STR_LIT> ) ; if ( LRIsAvailable ) { FrameID = MachineOutlinerNoLRSave ; NumBytesNoStackCalls += Costs . CallNoLRSave ; C . setCallInfo ( MachineOutlinerNoLRSave , Costs . CallNoLRSave ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( findRegisterToSaveLRTo ( C ) ) {


<s> static SDValue LowerXOR ( SDValue Op , SelectionDAG & DAG ) { SDValue Sel = Op . getOperand ( <NUM_LIT> ) ; SDValue Other = Op . getOperand ( <NUM_LIT> ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) std :: swap ( Sel , Other ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) return Op ; <STR_LIT> CC = cast < CondCodeSDNode > ( Sel . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue RHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue TVal = Sel . getOperand ( <NUM_LIT> ) ; SDValue FVal = Sel . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Sel ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return Op ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TVal ) ; if ( ! CFVal || ! CTVal ) return Op ; if ( CTVal -> isAllOnesValue ( ) && CFVal -> isNullValue ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , true ) ; } if ( CTVal -> isNullValue ( ) && CFVal -> isAllOnesValue ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , CCVal , DAG , dl ) ; FVal = Other ; TVal = DAG . getNode ( <STR_LIT> , dl , Other . getValueType ( ) , Other , DAG . getConstant ( - <NUM_LIT> , dl , Other . getValueType ( ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , Sel . getValueType ( ) , FVal , TVal , CCVal , Cmp ) ;


<s> if ( M < <NUM_LIT> ) { PSHUFBMask [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; continue ; } if ( Zeroable [ i / NumEltBytes ] ) { PSHUFBMask [ i ] = ZeroMask ; continue ; } SDValue SrcV = ( M >= Size ? V2 : V1 ) ; if ( V && V != SrcV ) return SDValue ( ) ; V = SrcV ; M %= Size ; if ( ( M / LaneSize ) != ( ( i / NumEltBytes ) / LaneSize ) ) return SDValue ( ) ; M = M % LaneSize ; M = M * NumEltBytes + ( i % NumEltBytes ) ; PSHUFBMask [ i ] = DAG . getConstant ( M , DL , <STR_LIT> ) ; } assert ( V && <STR_LIT> ) ; MVT I8VT = <STR_LIT> ( <STR_LIT> , NumBytes ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , I8VT , DAG . getBitcast ( I8VT , V ) , DAG . getBuildVector ( I8VT , DL , PSHUFBMask ) ) ) ;


<s> unsigned RegisterPair = CPPairDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( RegisterPair ) ) ; return MCDisassembler :: Success ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> uint64_t Ceil = Log2Ceil == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> << Log2Ceil ; if ( C - Floor <= Ceil - C ) { SDValue Op0 = genConstMult ( X , Floor , DL , VT , ShiftTy , DAG ) ; SDValue Op1 = genConstMult ( X , C - Floor , DL , VT , ShiftTy , DAG ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op0 , Op1 ) ; }

SDValue Op0 = genConstMult ( X , Ceil , DL , VT , ShiftTy , DAG ) ;


<s> if ( MI . isDebugValue ( ) ) { MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; } assert ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isThumbFunction ( ) && <STR_LIT> ) ; if ( rewriteFrameIndex ( MI , FIOperandNum , FrameReg , Offset , TII ) ) return ; assert ( Offset && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; int PIdx = MI . findFirstPredOperandIdx ( ) ; if ( PIdx != - <NUM_LIT> ) removeOperands ( MI , PIdx ) ; if ( MI . mayLoad ( ) ) { Register TmpReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) { if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , TmpReg , FrameReg , Offset , false , TII , * this ) ; else { emitLoadConstPool ( MBB , II , dl , TmpReg , <NUM_LIT> , Offset ) ; UseRR = true ; } } else { emitThumbRegPlusImmediate ( MBB , II , dl , TmpReg , FrameReg , Offset , TII , * this ) ; } MI . setDesc ( TII . get ( UseRR ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( TmpReg , false , false , true ) ; if ( UseRR ) MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( FrameReg , false , false , false ) ; } else if ( MI . mayStore ( ) ) { VReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; bool UseRR = false ; if ( Opcode == <STR_LIT> ) {

if ( FrameReg == <STR_LIT> || STI . genExecuteOnly ( ) ) emitThumbRegPlusImmInReg ( MBB , II , dl , VReg , FrameReg , Offset , false , TII , * this ) ;


<s> else { unsigned int true_time = mips_mult_zero_zero_cost ( state , true ) ; unsigned int false_time = mips_mult_zero_zero_cost ( state , false ) ; mips_tuning_info . fast_mult_zero_zero_p = ( true_time <= false_time ) ;


<s> return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy ) ;


<s> switch ( Node -> getOpcode ( ) ) { case <STR_LIT> : { unsigned NumOps = Node -> getNumOperands ( ) ; if ( Node -> getOperand ( NumOps - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) -- NumOps ; for ( unsigned i = InlineAsm :: Op_FirstOperand ; i != NumOps ; ) { if ( FuncInfo -> hasClobberLR ( ) ) break ; unsigned Flags = cast < ConstantSDNode > ( Node -> getOperand ( i ) ) -> getZExtValue ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; ++ i ; switch ( InlineAsm :: getKind ( Flags ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Kind_RegDef : case InlineAsm :: Kind_RegUse : case InlineAsm :: Kind_Imm : case InlineAsm :: Kind_Clobber : case InlineAsm :: Kind_Mem : { for ( ; NumVals ; -- NumVals , ++ i ) { } break ; } case InlineAsm :: Kind_RegDefEarlyClobber : { for ( ; NumVals ; -- NumVals , ++ i ) { unsigned Reg = cast < RegisterSDNode > ( Node -> getOperand ( i ) ) -> getReg ( ) ; const <ISA_LIT>RegisterInfo * QRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getTarget ( ) . getRegisterInfo ( ) ) ; if ( Reg == QRI -> getRARegister ( ) ) { FuncInfo -> setHasClobberLR ( true ) ; break ; } } break ;