<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand ( MCOp ) ;


<s> SDVTList SDTys = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue VLDDup = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , SDTys , Ops , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , VLDDup . getValue ( <NUM_LIT> ) ) ; return VLDDup ; } return SDValue ( ) ;


<s> void OrderedRegisterList :: remove ( unsigned VR ) { iterator L = llvm :: lower_bound ( Seq , VR , Ord ) ; if ( L != Seq . end ( ) ) Seq . erase ( L ) ;


<s> void GCNRPTracker :: printLiveRegs ( raw_ostream & OS , const LiveRegSet & LiveRegs , const MachineRegisterInfo & MRI ) { const TargetRegisterInfo * TRI = MRI . getTargetRegisterInfo ( ) ; for ( unsigned I = <NUM_LIT> , E = MRI . getNumVirtRegs ( ) ; I != E ; ++ I ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( I ) ;


<s> int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; if ( BaseOp1 . isFI ( ) ) { assert ( ( ! BaseOp1 . isIdenticalTo ( BaseOp2 ) || Offset1 <= Offset2 ) && <STR_LIT> ) ; const MachineFrameInfo & MFI = FirstLdSt . getParent ( ) -> getParent ( ) -> getFrameInfo ( ) ; return shouldClusterFI ( MFI , BaseOp1 . getIndex ( ) , Offset1 , FirstOpc , BaseOp2 . getIndex ( ) , Offset2 , SecondOpc ) ; }

assert ( Offset1 <= Offset2 && <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ; case 'X' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << Twine :: utohexstr ( MO . getImm ( ) ) ; return false ; case 'x' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << <STR_LIT> << Twine :: utohexstr ( MO . getImm ( ) & <NUM_LIT> ) ; return false ; case 'd' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) ; return false ; case 'm' : if ( ( MO . getType ( ) ) != MachineOperand :: MO_Immediate ) return true ; O << MO . getImm ( ) - <NUM_LIT> ; return false ; case 'z' : { if ( MO . getType ( ) == MachineOperand :: MO_Immediate && MO . getImm ( ) == <NUM_LIT> ) { O << <STR_LIT> ; return false ; } break ;


<s> case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG , Subtarget ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return DAG . getIntPtrConstant ( <NUM_LIT> * <NUM_LIT> ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return LowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG , Subtarget ) ; case <STR_LIT> : return ExpandBITCAST ( Op . getNode ( ) , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op . getNode ( ) , DAG , Subtarget ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTTZ ( Op . getNode ( ) , DAG , Subtarget ) ;

case <STR_LIT> : return LowerCTPOP ( Op . getNode ( ) , DAG , Subtarget ) ;


<s> return ( __m128h ) __builtin_ia32_movaps128_mask ( ( __v4sf ) _mm_conj_pch ( __A ) , ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> if ( MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> && ! MO . isDead ( ) ) return true ; }


<s> if ( ! TARGET_HAVE_TLS ) return false ;

if ( GET_CODE ( x ) != SYMBOL_REF ) return false ;


<s> if ( STI . hasMOPS ( ) ) return EmitMOPS ( <STR_LIT> , DAG , DL , Chain , Dst , Src , Size , Alignment , isVolatile , DstPtrInfo , SrcPtrInfo ) ;


<s> for ( unsigned i = BBNum + <NUM_LIT> , e = MF -> getNumBlockIDs ( ) ; i < e ; ++ i ) { unsigned LogAlign = MF -> getBlockNumbered ( i ) -> getAlignment ( ) ; unsigned Offset = BBInfo [ i - <NUM_LIT> ] . postOffset ( LogAlign ) ; unsigned KnownBits = BBInfo [ i - <NUM_LIT> ] . postKnownBits ( LogAlign ) ;

if ( i > BBNum + <NUM_LIT> && BBInfo [ i ] . Offset == Offset && BBInfo [ i ] . KnownBits == KnownBits ) break ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RegisterInfo ( ) {


<s> unsigned uid2 = INSN_UID ( def_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_load && insn_entry [ uid2 ] . is_swap ) ; rtx body = PATTERN ( def_insn ) ; gcc_assert ( ( GET_CODE ( body ) == SET ) && ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT || pattern_is_rotate64 ( body ) ) && MEM_P ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; enum machine_mode mode = GET_MODE ( src_exp ) ; rtx lvx = rs6000_gen_lvx ( mode , SET_DEST ( body ) , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( lvx , def_insn ) ; rtx new_body = PATTERN ( new_insn ) ; gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_SRC ( new_body ) ) ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( def_insn ) ) ; df_insn_rescan ( new_insn ) ; df_insn_delete ( def_insn ) ; remove_insn ( def_insn ) ; def_insn -> set_deleted ( ) ;

mark_swaps_for_removal ( insn_entry , uid ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) return false ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MF . exposesReturnsTwice ( ) || ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> case E_QImode : return TARGET_64BIT || ! TARGET_PARTIAL_REG_STALL ; case E_DImode : return TARGET_64BIT ; default : return false ;


<s> bool is64Bit = TheTriple . getArch ( ) == Triple :: x86_64 ; MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) { if ( is64Bit ) MAI = new <ISA_LIT>_64MCAsmInfoDarwin ( TheTriple ) ; else MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; } else if ( TheTriple . getOS ( ) == Triple :: Win32 ) { MAI = new <ISA_LIT>MCAsmInfoMicrosoft ( TheTriple ) ; } else if ( TheTriple . getOS ( ) == Triple :: MinGW32 || TheTriple . getOS ( ) == Triple :: Cygwin ) { MAI = new <ISA_LIT>MCAsmInfoGNUCOFF ( TheTriple ) ; } else { MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ; } int stackGrowth = is64Bit ? - <NUM_LIT> : - <NUM_LIT> ;

MachineLocation Dst ( MachineLocation :: VirtualFP ) ;


<s> bool <ISA_LIT>InstrInfo :: isMovDualGroup ( const MachineInstr & MI , unsigned * pSrcG , unsigned * pDstG ) const { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ;


<s> case CONST : if ( CONST_GP_P ( x ) ) return <NUM_LIT> ; if ( mips_symbolic_constant_p ( x , SYMBOL_CONTEXT_LEA , & symbol_type ) ) return mips_symbol_insns ( symbol_type , MAX_MACHINE_MODE ) ; split_const ( x , & x , & offset ) ; if ( offset != <NUM_LIT> ) { int n = mips_const_insns ( x ) ; if ( n != <NUM_LIT> ) { if ( SMALL_INT ( offset ) ) return n + <NUM_LIT> ; else if ( ! targetm . cannot_force_const_mem ( GET_MODE ( x ) , x ) ) return n + <NUM_LIT> + mips_build_integer ( codes , INTVAL ( offset ) ) ; } } return <NUM_LIT> ; case SYMBOL_REF : case LABEL_REF : return mips_symbol_insns ( mips_classify_symbol ( x , SYMBOL_CONTEXT_LEA ) , MAX_MACHINE_MODE ) ;


<s> static rtx aarch64_bit_representation ( rtx x ) { if ( CONST_DOUBLE_P ( x ) ) x = gen_lowpart ( int_mode_for_mode ( GET_MODE ( x ) ) . require ( ) , x ) ;


<s> return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , E , false , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HI : return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , E , false , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HA : return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HA , E , false , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHER , E , false , Ctx ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHERA : return <ISA_LIT>MCExpr :: Create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HIGHERA , E , false , Ctx ) ;

case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST :


<s> static <STR_LIT> changeTestCCTo<ISA_LIT>CC ( <STR_LIT> CC ) { switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> newBB -> addSuccessor ( MBB , BranchProbability :: getOne ( ) ) ; MF -> insert ( MachineFunction :: iterator ( MBB ) , newBB ) ; return newBB ;


<s> const MCOperand & MCOp = Inst . getOperand ( OpNo ) ; if ( MCOp . isImm ( ) ) return getMachineOpValue ( Inst , MCOp , Fixups , SubtargetInfo ) ;

Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MCOp . getExpr ( ) , Kind ) ) ;


<s> Func -> push_back ( NewMBB ) ; for ( const MachineInstr & It : * MBB ) NewMBB -> push_back ( Func -> CloneMachineInstr ( & It ) ) ; return NewMBB ;


<s> HasNopl = CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ;


<s> gcc_assert ( i == <NUM_LIT> ) ; * factor = <NUM_LIT> ; * offset = <NUM_LIT> ;


<s> for ( Value * Obj : Objs ) { auto * A = dyn_cast < const Argument > ( Obj ) ; if ( ! A || ! A -> onlyReadsMemory ( ) || ! A -> hasNoAliasAttr ( ) ) return false ; } return true ;


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) ) return std :: max ( ( VT . getSizeInBits ( ) / ( Subtarget . isABI_O32 ( ) ? <NUM_LIT> : <NUM_LIT> ) ) , <NUM_LIT> ) ; return <ISA_LIT>TargetLowering :: getNumRegisters ( Context , VT ) ;


<s> unsigned <ISA_LIT>TTIImpl :: getMaxInterleaveFactor ( unsigned VF ) { return useHVX ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> return RegInfo . lookup ( Reg ) . Encoded ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RI = TM . getRegisterInfo ( ) ; return ( DisableFramePointerElim ( MF ) || RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: findCommutedOpIndices ( const MachineInstr & MI , unsigned & SrcOpIdx1 , unsigned & SrcOpIdx2 ) const { unsigned op1 , op2 ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : op1 = <NUM_LIT> ; op2 = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : op1 = <NUM_LIT> ; op2 = <NUM_LIT> ; break ; default : return false ;


<s> int NumGradients = BaseOpcode -> Gradients ? DimInfo -> NumGradients : <NUM_LIT> ; int NumCoords = BaseOpcode -> Coordinates ? DimInfo -> NumCoords : <NUM_LIT> ; int NumLCM = BaseOpcode -> LodOrClampOrMip ? <NUM_LIT> : <NUM_LIT> ; int NumVAddr = BaseOpcode -> NumExtraArgs + NumGradients + NumCoords + NumLCM ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ;


<s> getGlobalLinkName ( GV , Name ) ; if ( TM . getRelocationModel ( ) != Reloc :: Static ) { if ( GV -> hasHiddenVisibility ( ) ) HiddenGVStubs . insert ( Name ) ; else GVStubs . insert ( Name ) ; printSuffixedName ( Name , <STR_LIT> ) ; return ; }


<s> } else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstantFP ( APF . convertToDouble ( ) , dl , <STR_LIT> ) ) ) ; return ; } SelectCode ( N ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy Res = MatchOperand_NoMatch ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { Parser . Lex ( ) ; isParenExpr = true ; } if ( getLexer ( ) . getKind ( ) != AsmToken :: Dollar ) { if ( parseMemOffset ( IdVal , isParenExpr ) ) return MatchOperand_ParseFail ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( Mnemonic . getToken ( ) == <STR_LIT> || Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = parseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ;


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> unsigned Num ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return ; emit<ISA_LIT>Nops ( * OutStreamer , Num , Subtarget ) ; return ; } auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> emitLabel ( CurSled ) ; OutStreamer -> emitBytes ( <STR_LIT> ) ; emit<ISA_LIT>Nops ( * OutStreamer , <NUM_LIT> , Subtarget ) ; recordSled ( CurSled , MI , SledKind :: FUNCTION_ENTER , <NUM_LIT> ) ;


<s> HTScope = new ScopedHTType :: ScopeTy ( ScopedHT ) ;


<s> const char * <ISA_LIT>InstPrinter :: getRegisterName ( unsigned RegNo ) { return getRegisterName ( RegNo , <STR_LIT> ) ;


<s> Triple TheTriple ( TT ) ; return createELFStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll , NoExecStack ) ;


<s> Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstrBuilder BalInstr = BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ; MachineInstrBuilder DADDiuInstr = BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; if ( Subtarget . has<ISA_LIT>32r6 ( ) ) { LongBrMBB -> insert ( Pos , DADDiuInstr ) ; LongBrMBB -> insert ( Pos , BalInstr ) ; } else { LongBrMBB -> insert ( Pos , BalInstr ) ; LongBrMBB -> insert ( Pos , DADDiuInstr ) ; LongBrMBB -> rbegin ( ) -> bundleWithPred ( ) ; } Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . has<ISA_LIT>64r6 ( ) ) { BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BalTgtMBB -> rbegin ( ) -> bundleWithPred ( ) ;


<s> assert ( Src0Idx != - <NUM_LIT> && <STR_LIT> ) ; MachineOperand & Src0 = MI -> getOperand ( Src0Idx ) ; if ( ! Src0 . isReg ( ) ) return nullptr ; int Src1Idx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: src1 ) ; if ( Src1Idx == - <NUM_LIT> ) return nullptr ; MachineOperand & Src1 = MI -> getOperand ( Src1Idx ) ; if ( isVOP2 ( MI -> getOpcode ( ) ) && ( ! isOperandLegal ( MI , Src0Idx , & Src1 ) || ! isOperandLegal ( MI , Src1Idx , & Src0 ) ) ) { return nullptr ; } if ( ! Src1 . isReg ( ) ) { if ( NewMI || ! Src1 . isImm ( ) || ( ! isVOP2 ( MI -> getOpcode ( ) ) && ! isVOP3 ( MI -> getOpcode ( ) ) ) ) { return nullptr ; } if ( MachineOperand * Src0Mods = getNamedOperand ( * MI , <STR_LIT> :: src0_modifiers ) ) { MachineOperand * Src1Mods = getNamedOperand ( * MI , <STR_LIT> :: src1_modifiers ) ; int Src0ModsVal = Src0Mods -> getImm ( ) ; if ( ! Src1Mods && Src0ModsVal != <NUM_LIT> ) return nullptr ; int Src1ModsVal = Src1Mods -> getImm ( ) ; assert ( ( Src1ModsVal == <NUM_LIT> ) && <STR_LIT> ) ; Src1Mods -> setImm ( Src0ModsVal ) ; Src0Mods -> setImm ( Src1ModsVal ) ; } unsigned Reg = Src0 . getReg ( ) ; unsigned SubReg = Src0 . getSubReg ( ) ; if ( Src1 . isImm ( ) ) Src0 . ChangeToImmediate ( Src1 . getImm ( ) ) ; else llvm_unreachable ( <STR_LIT> ) ; Src1 . ChangeToRegister ( Reg , false ) ; Src1 . setSubReg ( SubReg ) ;


<s> if ( ! isInt < <NUM_LIT> > ( Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; unsigned ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; TII -> movImm32 ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( FrameReg ) . addReg ( ScratchReg , RegState :: Kill ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ; FrameRegIsKill = true ;


<s> if ( ! isValidCoprocessorNumber ( Val , featureBits ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return MCDisassembler :: Success ;


<s> I . addOperand ( * MF , MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; return constrainSelectedInstRegOperands ( I , TII , TRI , RBI ) ; } Register Src0Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( HasCarryIn ) { BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } unsigned NoCarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; unsigned CarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , & I , DL , TII . get ( HasCarryIn ? CarryOpc : NoCarryOpc ) , Dst0Reg ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Dst1Reg ) . addReg ( <STR_LIT> ) ; if ( ! MRI -> getRegClassOrNull ( Dst1Reg ) ) MRI -> setRegClass ( Dst1Reg , & <STR_LIT> ) ;

if ( ! RBI . constrainGenericRegister ( Dst0Reg , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Src0Reg , <STR_LIT> , * MRI ) || ! RBI . constrainGenericRegister ( Src1Reg , <STR_LIT> , * MRI ) ) return false ;


<s> unsigned <ISA_LIT>ELFWriterInfo :: getAbsoluteLabelMachineRelTy ( ) const { llvm_unreachable ( <STR_LIT> <STR_LIT> ) ;


<s> if ( count > single_width ) emit_insn ( ( mode == DImode ? gen_ashrsi3 : gen_ashrdi3 ) ( low [ <NUM_LIT> ] , low [ <NUM_LIT> ] , GEN_INT ( count - single_width ) ) ) ; } else { if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( ( mode == DImode ? gen_x86_shrd_1 : gen_x86_64_shrd ) ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; emit_insn ( ( mode == DImode ? gen_ashrsi3 : gen_ashrdi3 ) ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , GEN_INT ( count ) ) ) ; } } else { if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; ( mode == DImode ? split_di : split_ti ) ( operands , <NUM_LIT> , low , high ) ; emit_insn ( ( mode == DImode ? gen_x86_shrd_1 : gen_x86_64_shrd ) ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_insn ( ( mode == DImode ? gen_ashrsi3 : gen_ashrdi3 ) ( high [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; if ( TARGET_CMOVE && scratch ) { emit_move_insn ( scratch , high [ <NUM_LIT> ] ) ; emit_insn ( ( mode == DImode ? gen_ashrsi3 : gen_ashrdi3 ) ( scratch , scratch , GEN_INT ( single_width - <NUM_LIT> ) ) ) ; emit_insn ( ( mode == DImode ? gen_x86_shift_adj_1 : gen_x86_64_shift_adj ) ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , scratch ) ) ; } else emit_insn ( gen_x86_shift_adj_3 ( low [ <NUM_LIT> ] , high [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ;


<s> static bool isAllActivePredicate ( Value * Pred ) { Value * UncastedPred ;

if ( match ( Pred , m_Intrinsic < <STR_LIT> > ( m_Intrinsic < <STR_LIT> > ( m_Value ( UncastedPred ) ) ) ) ) if ( cast < ScalableVectorType > ( Pred -> getType ( ) ) -> getMinNumElements ( ) <= cast < ScalableVectorType > ( UncastedPred -> getType ( ) ) -> getMinNumElements ( ) ) Pred = UncastedPred ;


<s> unsigned <ISA_LIT>InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Opc ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ;


<s> virtual bool runOnMachineFunction ( MachineFunction & MF ) { const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; const <ISA_LIT>RegisterInfo * <ISA_LIT>RI = TM -> getRegisterInfo ( ) ; MachineRegisterInfo & RI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned StackAlignment = <ISA_LIT>RI -> getStackAlignment ( ) ; for ( unsigned RegNum = TargetRegisterInfo :: FirstVirtualRegister ;

RegNum < RI . getLastVirtReg ( ) ; ++ RegNum ) if ( RI . getRegClass ( RegNum ) -> getAlignment ( ) > StackAlignment ) {


<s> AS . FLAT_ADDRESS = <NUM_LIT> ; AS . PRIVATE_ADDRESS = <NUM_LIT> ;


<s> <ISA_LIT>AsmPrinter :: <ISA_LIT>AsmPrinter ( llvm :: TargetMachine & TM , std :: unique_ptr < llvm :: MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCInstLowering ( OutContext , * this ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , TargetMachine & TM , bool is64Bit ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , Is64Bit ( is64Bit ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( * TM . getDataLayout ( ) ) , FrameLowering ( * this ) {


<s> assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ;

return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> return __builtin_mve_vrndaq_fv8hf ( __a ) ;


<s> bool inImplicitITBlock ( ) { return inITBlock ( ) && ! ITState . IsExplicit ;


<s> rtx base_reg , val ; n = INTVAL ( xop1 ) ; if ( mode == DImode || mode == DFmode ) { low_n = n & <NUM_LIT> ; n &= ~ <NUM_LIT> ; if ( low_n > <NUM_LIT> ) { n += <NUM_LIT> ; low_n -= <NUM_LIT> ; } } else { low_n = ( ( mode ) == TImode ? <NUM_LIT> : n >= <NUM_LIT> ? ( n & <NUM_LIT> ) : - ( ( - n ) & <NUM_LIT> ) ) ; n -= low_n ; } base_reg = gen_reg_rtx ( SImode ) ; val = force_operand ( plus_constant ( Pmode , xop0 , n ) , NULL_RTX ) ; emit_move_insn ( base_reg , val ) ; x = plus_constant ( Pmode , base_reg , low_n ) ; } else if ( xop0 != XEXP ( x , <NUM_LIT> ) || xop1 != XEXP ( x , <NUM_LIT> ) ) x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } else if ( GET_CODE ( x ) == MINUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ;

if ( CONSTANT_P ( xop0 ) ) xop0 = force_reg ( SImode , xop0 ) ;


<s> <ISA_LIT>Peephole ( ) : MachineFunctionPass ( ID ) {


<s> assert ( MO . isSymbol ( ) && <STR_LIT> ) ; Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; TM . getNameWithPrefix ( Name , GV , Mang ) ;


<s> return BaseT :: getIntrinsicInstrCost ( IID , RetTy , Args , FMF , VF ) ;


return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseCCSelect ( ) || hasFuseLiterals ( ) ;


__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> if ( ! static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) -> canRealignStack ( MF ) ) return ; unsigned NumSpills = <NUM_LIT> ; for ( ; NumSpills < <NUM_LIT> ; ++ NumSpills ) if ( ! SavedRegs . test ( <STR_LIT> + NumSpills ) ) break ; if ( NumSpills < <NUM_LIT> ) return ; MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setNumAlignedDPRCS2Regs ( NumSpills ) ; SavedRegs . set ( <STR_LIT> ) ;


<s> assert ( LHS . getValueType ( ) == RHS . getValueType ( ) ) ; <STR_LIT> <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , <ISA_LIT>CC , false , CmpVT , dl , DAG ) ; return DAG . getSExtOrTrunc ( Cmp , dl , Op . getValueType ( ) ) ; } assert ( LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> || LHS . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; <STR_LIT> CC1 , CC2 ; bool ShouldInvert ; changeVectorFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 , ShouldInvert ) ; bool NoNaNs = getTargetMachine ( ) . Options . NoNaNsFPMath ; SDValue Cmp = EmitVectorComparison ( LHS , RHS , CC1 , NoNaNs , CmpVT , dl , DAG ) ;

if ( ! Cmp . getNode ( ) ) return SDValue ( ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( ) ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> mclass1 = GET_MODE_CLASS ( mode1 ) ; mclass2 = GET_MODE_CLASS ( mode2 ) ; if ( mclass1 != mclass2 ) return false ; if ( ! TARGET_V9 ) return true ; if ( mclass1 != MODE_FLOAT && mclass1 != MODE_VECTOR_INT ) return true ; size1 = GET_MODE_SIZE ( mode1 ) ; size2 = GET_MODE_SIZE ( mode2 ) ; if ( ( size1 > <NUM_LIT> && size2 == <NUM_LIT> ) || ( size2 > <NUM_LIT> && size1 == <NUM_LIT> ) ) return false ;


<s> void thumb_set_return_address ( rtx source , rtx scratch ) { arm_stack_offsets * offsets ; HOST_WIDE_INT delta ; HOST_WIDE_INT limit ; int reg ; rtx addr ; unsigned long mask ; emit_use ( source ) ; offsets = arm_get_frame_offsets ( ) ; mask = offsets -> saved_regs_mask ; if ( mask & ( <NUM_LIT> << LR_REGNUM ) ) { limit = <NUM_LIT> ; if ( frame_pointer_needed ) { delta = offsets -> soft_frame - offsets -> saved_args ; reg = THUMB_HARD_FRAME_POINTER_REGNUM ; if ( TARGET_THUMB1 ) limit = <NUM_LIT> ; } else { delta = offsets -> outgoing_args - offsets -> saved_args ; reg = SP_REGNUM ; } if ( TARGET_THUMB1 && TARGET_BACKTRACE ) delta -= <NUM_LIT> ; delta -= <NUM_LIT> ; addr = gen_rtx_REG ( SImode , reg ) ;


<s> DebugLoc dl = I -> getDebugLoc ( ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ; BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( LoReg ) ; if ( FP64 ) BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( HiReg ) ;

else BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( HiReg ) ;


<s> ChildIteratorType ( aedges :: iterator i ) : I ( i ) {


<s> bool DstDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; unsigned AccReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src2Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Src1Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Src2Kill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned LaneImm = HasLane ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; unsigned NextOp = HasLane ? <NUM_LIT> : <NUM_LIT> ; <STR_LIT> Pred = ( <STR_LIT> ) MI -> getOperand ( NextOp ) . getImm ( ) ; unsigned PredReg = MI -> getOperand ( ++ NextOp ) . getReg ( ) ; const MCInstrDesc & MCID1 = TII -> get ( MulOpc ) ; const MCInstrDesc & MCID2 = TII -> get ( AddSubOpc ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; unsigned TmpReg = MRI -> createVirtualRegister ( TII -> getRegClass ( MCID1 , <NUM_LIT> , TRI , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , MCID1 , TmpReg ) . addReg ( Src1Reg , getKillRegState ( Src1Kill ) ) . addReg ( Src2Reg , getKillRegState ( Src2Kill ) ) ; if ( HasLane ) MIB . addImm ( LaneImm ) ;

MIB . addImm ( Pred ) . addReg ( PredReg ) ;


<s> static bool isUNPCKLMask ( ArrayRef < int > Mask , MVT VT , bool HasInt256 , bool V2IsSplat = false ) { assert ( VT . getSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . is256BitVector ( ) && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; assert ( ( ! VT . is512BitVector ( ) || VT . getScalarType ( ) . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ;

unsigned NumLaneElts = NumElts / NumLanes ;


<s> switch ( Opc ) { case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; } return None ;


<s> unsigned V2 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V1 ) ; emitWordLE ( Binary ) ; Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( V2 ) ;


<s> UnsignedMap RegMap ; for ( IFMapType :: iterator I = IFMap . begin ( ) , E = IFMap . end ( ) ; I != E ; ++ I ) { unsigned VR = I -> first ; const TargetRegisterClass * RC = MRI -> getRegClass ( VR ) ; Register NewVR = MRI -> createVirtualRegister ( RC ) ; RegMap [ VR ] = NewVR ; } for ( IFMapType :: iterator I = IFMap . begin ( ) , E = IFMap . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = MRI -> getVRegDef ( I -> first ) ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned NewR = RegMap [ I -> first ] ; bool R32 = MRI -> getRegClass ( NewR ) == & <STR_LIT> ; const MCInstrDesc & D = R32 ? HII -> get ( <STR_LIT> ) : HII -> get ( <STR_LIT> ) ; IFRecord IF = I -> second [ <NUM_LIT> ] . first ; unsigned Wdh = IF . Wdh , Off = IF . Off ; unsigned InsS = <NUM_LIT> ; if ( R32 && MRI -> getRegClass ( IF . InsR ) == & <STR_LIT> ) { InsS = <STR_LIT> ; if ( Off >= <NUM_LIT> ) { InsS = <STR_LIT> ; Off -= <NUM_LIT> ; } } MachineBasicBlock :: iterator At = MI ;

if ( MI -> isPHI ( ) ) At = B . getFirstNonPHI ( ) ;


<s> <ISA_LIT>AsmPrinter ( raw_ostream & O , TargetMachine & TM , const TargetAsmInfo * T , bool F ) : AsmPrinter ( O , TM , T , F ) {


<s> return determineSVEStackObjectOffsets ( MFI , MinCSFrameIndex , MaxCSFrameIndex , true ) ;


<s> if ( TARGET_HAVE_MVE ) return arm_mode_to_pred_mode ( mode ) ; return default_get_mask_mode ( mode ) ;


<s> result |= SOFFSET ; } return result ; } switch ( Opc ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SBASE ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ADDR ; }


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> const TargetRegisterClass * RC = getRegClassForReg ( MRI , Reg ) ; assert ( RC && <STR_LIT> ) ; return hasVGPRs ( RC ) ;


<s> if ( insn_entry [ i ] . is_load ) { if ( GET_CODE ( body ) == SET ) { rtx rhs = SET_SRC ( body ) ; if ( GET_CODE ( rhs ) != MEM ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( rhs , <NUM_LIT> ) ) == AND ) return <NUM_LIT> ; * special = SH_NOSWAP_LD ; return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( insn_entry [ i ] . is_store ) { if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) != UNSPEC ) { rtx lhs = SET_DEST ( body ) ; if ( GET_CODE ( lhs ) != MEM ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( lhs , <NUM_LIT> ) ) == AND ) return <NUM_LIT> ; * special = SH_NOSWAP_ST ; return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == UNSPEC && XINT ( SET_SRC ( body ) , <NUM_LIT> ) == UNSPEC_VSX_CVDPSPN ) { df_ref def ;

struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ;


<s> if ( ! MRI -> isAllocatable ( Reg ) || getPhysRegBank ( Reg , SubReg ) != Bank ) continue ; for ( unsigned I = <NUM_LIT> ; CSRegs [ I ] ; ++ I ) if ( TRI -> isSubRegisterEq ( Reg , CSRegs [ I ] ) && ! LRM -> isPhysRegUsed ( CSRegs [ I ] ) ) return <STR_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg ) << '\n' ) ; if ( ! LRM -> checkInterference ( LI , Reg ) ) return Reg ;


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; return X ;


<s> return <NUM_LIT> ; case <STR_LIT> : return Emiti1Ext ( SrcReg , DestVT , isZExt ) ; case <STR_LIT> : if ( DestVT == <STR_LIT> ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; Imm = <NUM_LIT> ; break ; case <STR_LIT> : if ( DestVT == <STR_LIT> ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; Imm = <NUM_LIT> ; break ; case <STR_LIT> : assert ( DestVT == <STR_LIT> && <STR_LIT> ) ; Opc = isZExt ? <STR_LIT> : <STR_LIT> ; Imm = <NUM_LIT> ; break ; }

if ( DestVT == <STR_LIT> || DestVT == <STR_LIT> ) DestVT = <STR_LIT> ;


<s> OS << <STR_LIT> << Reg << <STR_LIT> << Offset << <STR_LIT> ;


<s> SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; unsigned RegNo ; bool TryRegParse = getTok ( ) . is ( AsmToken :: Percent ) || ( isParsingIntelSyntax ( ) && getTok ( ) . is ( AsmToken :: Identifier ) ) ; if ( ! TryRegParse || ParseRegister ( RegNo , StartLoc , EndLoc ) ) return true ; Parser . clearPendingErrors ( ) ;

Res = <STR_LIT> ( RegNo , Parser . getContext ( ) ) ;


<s> if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; MCSymbol * Symbol = getContext ( ) . getOrCreateSymbol ( Name ) ; if ( parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; unsigned LocalMemorySize = <STR_LIT> :: getLocalMemorySize ( & getSTI ( ) ) ; int64_t Size ; SMLoc SizeLoc = getLexer ( ) . getLoc ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Size ) ) return true ; if ( Size < <NUM_LIT> ) return Error ( SizeLoc , <STR_LIT> ) ; if ( Size > LocalMemorySize ) return Error ( SizeLoc , <STR_LIT> ) ; int64_t Alignment = <NUM_LIT> ; if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Lex ( ) ; SMLoc AlignLoc = getLexer ( ) . getLoc ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Alignment ) ) return true ; if ( Alignment < <NUM_LIT> || ! isPowerOf2_64 ( Alignment ) ) return Error ( AlignLoc , <STR_LIT> ) ; if ( Alignment >= <NUM_LIT> << <NUM_LIT> ) return Error ( AlignLoc , <STR_LIT> ) ; }

if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ;


<s> InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( ( TargetTriple . getTriple ( ) . find ( <STR_LIT> ) != std :: string :: npos ) || ( isTargetIOS ( ) && isMClass ( ) ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( ! isTargetIOS ( ) ) { IsR9Reserved = ReserveR9 ; } else { IsR9Reserved = ReserveR9 | ! HasV6Ops ; SupportsTailCall = ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } if ( ! isThumb ( ) || hasThumb2 ( ) ) PostRAScheduler = true ; switch ( Align ) { case DefaultAlign : AllowsUnalignedMem = ( ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) ) ) || ( hasV6Ops ( ) && isTargetDarwin ( ) ) ) ; break ; case StrictAlign : AllowsUnalignedMem = false ; break ; case NoStrictAlign : AllowsUnalignedMem = true ; break ; } switch ( IT ) { case DefaultIT :

RestrictIT = hasV8Ops ( ) ? true : false ;


<s> if ( val == <NUM_LIT> || val == <NUM_LIT> || val == <NUM_LIT> ) return <NUM_LIT> ; else return <NUM_LIT> ;


<s> bool broadcast_perm = true ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) { nd . perm [ i ] = d -> perm [ i ] & mask ; if ( nd . perm [ i ] != i ) identity_perm = false ; if ( nd . perm [ i ] ) broadcast_perm = false ; } if ( identity_perm ) { if ( ! d -> testing_p ) emit_move_insn ( d -> target , d -> op0 ) ; return true ; } else if ( broadcast_perm && TARGET_AVX2 ) { rtx ( * gen ) ( rtx , rtx ) = NULL ; switch ( d -> vmode ) { case E_V64QImode : if ( TARGET_AVX512BW ) gen = gen_avx512bw_vec_dupv64qi_1 ; break ; case E_V32QImode : gen = gen_avx2_pbroadcastv32qi_1 ; break ; case E_V32HImode : if ( TARGET_AVX512BW ) gen = gen_avx512bw_vec_dupv32hi_1 ; break ; case E_V16HImode : gen = gen_avx2_pbroadcastv16hi_1 ; break ; case E_V16SImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv16si_1 ; break ; case E_V8SImode : gen = gen_avx2_pbroadcastv8si_1 ; break ; case E_V16QImode : gen = gen_avx2_pbroadcastv16qi ; break ; case E_V8HImode : gen = gen_avx2_pbroadcastv8hi ; break ; case E_V16SFmode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv16sf_1 ; break ; case E_V8SFmode : gen = gen_avx2_vec_dupv8sf_1 ; break ; case E_V8DFmode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv8df_1 ; break ; case E_V8DImode : if ( TARGET_AVX512F ) gen = gen_avx512f_vec_dupv8di_1 ; break ; default : break ; } if ( gen != NULL ) { if ( ! d -> testing_p ) emit_insn ( gen ( d -> target , d -> op0 ) ) ; return true ; } } if ( expand_vselect ( d -> target , d -> op0 , nd . perm , nelt , d -> testing_p ) ) return true ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { nd . perm [ i ] = d -> perm [ i ] & mask ; nd . perm [ i + <NUM_LIT> ] = ( d -> perm [ i + <NUM_LIT> ] & mask ) + nelt ; } if ( expand_vselect_vconcat ( d -> target , d -> op0 , d -> op0 , nd . perm , nelt , d -> testing_p ) ) return true ;


<s> rtx vd = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; rtx vs1 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; rtx vs2 = expand_normal ( CALL_EXPR_ARG ( exp , arg_offset ++ ) ) ; if ( VECTOR_MODE_P ( GET_MODE ( vs1 ) ) ) { if ( ! vd_accum_p ) add_input_operand ( mode , vd ) ; add_input_operand ( mode , vs1 ) ; add_input_operand ( mode , vs2 ) ; if ( vd_accum_p ) add_input_operand ( mode , vd ) ; add_input_operand ( mode , vd ) ; } else { add_input_operand ( GET_MODE_INNER ( mode ) , vs1 ) ; if ( vd_accum_p ) { add_input_operand ( mode , vs2 ) ; add_input_operand ( mode , vd ) ; } else { add_input_operand ( mode , vd ) ; add_input_operand ( mode , vs2 ) ; } add_input_operand ( mode , vd ) ;


<s> switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( SSECC == <NUM_LIT> ) { unsigned CC0 , CC1 ; unsigned CombineOpc ; if ( SetCCOpcode == <STR_LIT> ) { CC0 = <NUM_LIT> ; CC1 = <NUM_LIT> ; CombineOpc = <STR_LIT> ; } else { assert ( SetCCOpcode == <STR_LIT> ) ; CC0 = <NUM_LIT> ; CC1 = <NUM_LIT> ; CombineOpc = <STR_LIT> ; } SDValue Cmp0 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( CC0 , <STR_LIT> ) ) ; SDValue Cmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( CC1 , <STR_LIT> ) ) ; return DAG . getNode ( CombineOpc , dl , VT , Cmp0 , Cmp1 ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , Op0 , Op1 , DAG . getConstant ( SSECC , <STR_LIT> ) ) ; } if ( VT . is256BitVector ( ) && ! Subtarget -> hasInt256 ( ) ) return Lower256IntVSETCC ( Op , DAG ) ; unsigned Opc ; bool Swap = false , Invert = false , FlipSigns = false ; switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Invert = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; Invert = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; FlipSigns = true ; break ;


<s> if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) align = <NUM_LIT> ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; }


<s> return isInlinableIntLiteral ( Val ) ; }


<s> return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return NoConv ; default :


<s> MCOperand <ISA_LIT>AsmPrinter :: GetSymbolRef ( const MachineOperand & MO , const MCSymbol * Symbol ) { const MCExpr * Expr ; switch ( MO . getTargetFlags ( ) ) { default : { Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , OutContext ) ; switch ( MO . getTargetFlags ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> :


<s> if ( reg_class_subset_p ( rclass , GENERAL_REGS ) ) rclass = GENERAL_REGS ; return rclass ;


<s> if ( ! multiple_operation_profitable_p ( false , count , <NUM_LIT> ) ) { rtx seq ; start_sequence ( ) ; for ( i = <NUM_LIT> ; i < count ; i ++ ) emit_move_insn ( gen_rtx_REG ( SImode , regs [ i ] ) , mems [ i ] ) ; if ( wback_offset != <NUM_LIT> ) emit_move_insn ( basereg , plus_constant ( Pmode , basereg , wback_offset ) ) ; seq = get_insns ( ) ; end_sequence ( ) ; return seq ; }

result = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( count + ( wback_offset != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ) ;


<s> f_hi = expand_binop ( SImode , lshr_optab , fnaddr , GEN_INT ( <NUM_LIT> ) , NULL , true , OPTAB_DIRECT ) ; f_lo = expand_binop ( SImode , and_optab , fnaddr , GEN_INT ( <NUM_LIT> ) , NULL , true , OPTAB_DIRECT ) ; chain = force_operand ( chain , NULL ) ; c_hi = expand_binop ( SImode , lshr_optab , chain , GEN_INT ( <NUM_LIT> ) , NULL , true , OPTAB_DIRECT ) ; c_lo = expand_binop ( SImode , and_optab , chain , GEN_INT ( <NUM_LIT> ) , NULL , true , OPTAB_DIRECT ) ; tramp [ <NUM_LIT> ] = expand_binop ( SImode , ior_optab , f_hi , gen_int_mode ( movhi_r13 , SImode ) , f_hi , true , OPTAB_DIRECT ) ; tramp [ <NUM_LIT> ] = expand_binop ( SImode , ior_optab , c_hi , gen_int_mode ( movhi_r11 , SImode ) , c_hi , true , OPTAB_DIRECT ) ; tramp [ <NUM_LIT> ] = expand_binop ( SImode , ior_optab , f_lo , gen_int_mode ( ori_r13_r13 , SImode ) , f_lo , true , OPTAB_DIRECT ) ; tramp [ <NUM_LIT> ] = expand_binop ( SImode , ior_optab , c_lo , gen_int_mode ( ori_r11_r11 , SImode ) , c_lo , true , OPTAB_DIRECT ) ; tramp [ <NUM_LIT> ] = gen_int_mode ( jr_r13 , SImode ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { rtx mem = adjust_address ( m_tramp , SImode , i * <NUM_LIT> ) ;


<s> for ( auto const & Arg : F -> args ( ) ) { const AttributeList & Attrs = F -> getAttributes ( ) ; if ( Attrs . hasParamAttribute ( i , Attribute :: ByVal ) || Attrs . hasParamAttribute ( i , Attribute :: SwiftSelf ) || Attrs . hasParamAttribute ( i , Attribute :: SwiftError ) || Attrs . hasParamAttribute ( i , Attribute :: InAlloca ) || Attrs . hasParamAttribute ( i , Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) ) return false ; if ( ! Subtarget -> hasSIMD128 ( ) && ArgTy -> isVectorTy ( ) ) return false ; unsigned Opc ; const TargetRegisterClass * RC ; switch ( getSimpleType ( ArgTy ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; default : return false ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( i ) ; updateValueMap ( & Arg , ResultReg ) ; ++ i ; } MRI . addLiveIn ( <STR_LIT> ) ;

auto * MFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ;


<s> case <NUM_LIT> : op = recog_data . operand [ i ] ; gcc_assert ( GET_CODE ( op ) != SYMBOL_REF && ( GET_CODE ( op ) != CONST || ( GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == MINUS && XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) == sparc_got ( ) && GET_CODE ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST ) ) ) ; case <NUM_LIT> : default : return <NUM_LIT> ;


<s> static rtx_insn * arm_pic_static_addr ( rtx orig , rtx reg ) { rtx l1 , labelno , offset_rtx ; gcc_assert ( flag_pic ) ; labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ;


<s> Register ReadAgainReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , HiReg ) . addImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) . addReg ( <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , LoReg ) . addImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) . addReg ( <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ReadAgainReg ) . addImm ( <STR_LIT> ( <STR_LIT> ) -> Encoding ) . addReg ( <STR_LIT> ) ; BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( HiReg ) . addReg ( ReadAgainReg ) . addMBB ( LoopMBB ) ; LoopMBB -> addSuccessor ( LoopMBB ) ; LoopMBB -> addSuccessor ( DoneMBB ) ; MI . eraseFromParent ( ) ; return DoneMBB ;


<s> rtx reg = operands [ <NUM_LIT> ] ; HOST_WIDE_INT sign = <NUM_LIT> ; HOST_WIDE_INT amount ; rtx ( * gen_add ) ( rtx , rtx , rtx ) ; if ( val < <NUM_LIT> ) { val = - val ; sign = - <NUM_LIT> ; } switch ( mode ) { case E_HImode : gen_add = gen_addhi3 ; break ; case E_SImode :


<s> <ISA_LIT>SEInstrInfo :: <ISA_LIT>SEInstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>InstrInfo ( STI , STI . getRelocationModel ( ) == Reloc :: PIC_ ? <STR_LIT> : <STR_LIT> ) , RI ( ) {


<s> if ( N . getOpcode ( ) == <STR_LIT> || CurDAG -> isBaseWithConstantOffset ( N ) ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> << Shift , - <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ; return true ;


<s> for ( MachineBasicBlock :: iterator MI = MBB -> begin ( ) , MIe = MBB -> end ( ) ; MI != MIe ; ++ MI ) { if ( ! MI -> getFlag ( MachineInstr :: FrameSetup ) ) continue ; if ( MI -> getOpcode ( ) == <STR_LIT> && SpecialRegs . count ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { ReturnInfoInsts . insert ( MI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ; MI -> dump ( ) ) ; unsigned reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock :: iterator UMI = MI ; bool found = false ; while ( ++ UMI != MIe && ! found ) { for ( unsigned i = <NUM_LIT> ; i < UMI -> getNumOperands ( ) ; i ++ ) { const MachineOperand & MO = UMI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == reg ) { assert ( UMI -> getFlag ( MachineInstr :: FrameSetup ) ) ; ReturnInfoInsts . insert ( UMI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ; UMI -> dump ( ) ) ; found = true ; break ; } } } continue ; } if ( MI -> getOpcode ( ) == <STR_LIT> && SpecialRegs . count ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { ReturnInfoInsts . insert ( MI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ; MI -> dump ( ) ) ; unsigned reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock :: iterator DMI = prior ( MI ) ; bool found = false ; while ( ! found ) { if ( DMI -> definesRegister ( reg ) ) { assert ( DMI -> getFlag ( MachineInstr :: FrameSetup ) ) ; ReturnInfoInsts . insert ( DMI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ; DMI -> dump ( ) ) ; found = true ;


<s> static std :: string getRetvalLabel ( const std :: string & Func ) { std :: string Func1 = addPrefix ( Func ) ;

std :: string tag = getTagName ( RET_LABEL ) ;


<s> for ( SmallVector < MachineInstr * , <NUM_LIT> > :: iterator si = StackStores . begin ( ) , se = StackStores . end ( ) ; si != se ; ++ si ) { MachineInstr * Store = * si ; unsigned Opc = Store -> getOpcode ( ) ; MachineBasicBlock & MBB = * Ret -> getParent ( ) ; int FI = Store -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( ZeroedLocations . count ( FI ) ) continue ; ZeroedLocations . insert ( FI ) ; if ( Opc == <STR_LIT> ) { MachineInstrBuilder MIB ( F , Ret ) ; BuildMI ( MBB , Ret , Ret -> getDebugLoc ( ) , InstrInfo -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( Store -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addMemOperand ( InstrInfo -> GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { BuildMI ( MBB , Ret , Ret -> getDebugLoc ( ) , InstrInfo -> get ( Opc ) ) . addReg ( <STR_LIT> ) . addFrameIndex ( FI ) . addImm ( Store -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addMemOperand ( InstrInfo -> GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isVOPC ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> rtx insn = emit_call_insn ( pat ) ; rtx * fusage = & CALL_INSN_FUNCTION_USAGE ( insn ) ;

clobber_reg ( fusage , gen_rtx_REG ( word_mode , IP0_REGNUM ) ) ;


<s> unsigned RegNo = CTX . getRegisterInfo ( ) -> getEncodingValue ( Reg . getReg ( ) ) ; unsigned Align = <NUM_LIT> ; switch ( Imm . getImm ( ) ) { default : break ; case <NUM_LIT> :


<s> return ( __m128 ) __builtin_ia32_cmpnltss ( ( __v4sf ) __A , ( __v4sf ) __B ) ;


<s> static inline bool pdp11_saved_regno ( unsigned regno ) { return ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ;


<s> const char * Sym = MFI -> getImageHandleSymbol ( Index ) ; std :: string * SymNamePtr = nvTM . getManagedStrPool ( ) -> getManagedString ( Sym ) ; MCOp = GetSymbolRef ( OutContext . getOrCreateSymbol ( StringRef ( SymNamePtr -> c_str ( ) ) ) ) ;


<s> SDValue SubRegEven = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubRegOdd = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDNode * Hi64 = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , StNode -> getValue ( ) , SubRegEven ) ; SDNode * Lo64 = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , dl , <STR_LIT> , StNode -> getValue ( ) , SubRegOdd ) ; unsigned alignment = StNode -> getAlignment ( ) ; if ( alignment > <NUM_LIT> ) alignment = <NUM_LIT> ;


<s> if ( ConstantBlock > - <NUM_LIT> && ( ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) || ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) ) ) { SDValue Result ; if ( isa < Constant > ( LoadNode -> getMemOperand ( ) -> getValue ( ) ) || isa < ConstantSDNode > ( Ptr ) ) { return constBufferLoad ( LoadNode , LoadNode -> getAddressSpace ( ) , DAG ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG . getConstant ( LoadNode -> getAddressSpace ( ) - AMDGPUA<ISA_LIT> . CONSTANT_BUFFER_0 , DL , <STR_LIT> ) ) ; } if ( ! VT . isVector ( ) ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue MergedValues [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( MergedValues , DL ) ; } if ( LoadNode -> getExtensionType ( ) == <STR_LIT> ) { EVT MemVT = LoadNode -> getMemoryVT ( ) ;

assert ( ! MemVT . isVector ( ) && ( MemVT == <STR_LIT> || MemVT == <STR_LIT> ) ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) ;


<s> if ( Subtarget -> has<ISA_LIT>32 ( ) && ! Subtarget -> has<ISA_LIT>32r6 ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && selectMADD ( N , & DAG ) ) return SDValue ( N , <NUM_LIT> ) ;


<s> const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ;

if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;


<s> SDNode * Tile64DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ;

return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ;


<s> if ( ! Icmp1 ) return false ; auto * Icmp2 = dyn_cast < ICmpInst > ( I . getOperand ( <NUM_LIT> ) ) ; if ( ! Icmp2 ) return false ; Value * Icmp1Op0 = Icmp1 -> getOperand ( <NUM_LIT> ) ; Value * Icmp2Op0 = Icmp2 -> getOperand ( <NUM_LIT> ) ; if ( Icmp1Op0 != Icmp2Op0 ) return false ; PassThroughInfo Info ( Icmp1 , & I , <NUM_LIT> ) ; PassThroughs . push_back ( Info ) ;


<s> unsigned int ccvt ; if ( TARGET_64BIT ) return ( ix86_function_type_abi ( type ) == SYSV_ABI ? X86_64_REGPARM_MAX : X86_64_MS_REGPARM_MAX ) ; ccvt = ix86_get_callcvt ( type ) ; regparm = ix86_regparm ; if ( ( ccvt & IX86_CALLCVT_REGPARM ) != <NUM_LIT> ) { attr = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) ; if ( attr ) { regparm = TREE_INT_CST_LOW ( TREE_VALUE ( TREE_VALUE ( attr ) ) ) ; return regparm ; } } else if ( ( ccvt & IX86_CALLCVT_FASTCALL ) != <NUM_LIT> ) return <NUM_LIT> ; else if ( ( ccvt & IX86_CALLCVT_THISCALL ) != <NUM_LIT> ) return <NUM_LIT> ; if ( decl && TREE_CODE ( decl ) == FUNCTION_DECL ) { cgraph_node * target = cgraph_node :: get ( decl ) ; if ( target ) target = target -> function_symbol ( ) ; if ( target && opt_for_fn ( target -> decl , optimize ) && ! ( profile_flag && ! flag_fentry ) ) { cgraph_local_info * i = & target -> local ; if ( i && i -> local && i -> can_change_signature ) { int local_regparm , globals = <NUM_LIT> , regno ;


<s> void rs6000_emit_le_vsx_load ( rtx dest , rtx source , machine_mode mode ) { rtx tmp , permute_mem , permute_reg ; if ( mode == TImode || mode == V1TImode ) { mode = V2DImode ; dest = gen_lowpart ( V2DImode , dest ) ; source = adjust_address ( source , V2DImode , <NUM_LIT> ) ; } tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( dest ) : dest ; permute_mem = rs6000_gen_le_vsx_permute ( source , mode ) ; permute_reg = rs6000_gen_le_vsx_permute ( tmp , mode ) ; emit_insn ( gen_rtx_SET ( tmp , permute_mem ) ) ;

emit_insn ( gen_rtx_SET ( dest , permute_reg ) ) ;


<s> if ( Cond . isUndef ( ) ) { CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; return ; } const GCNSubtarget * ST = static_cast < const GCNSubtarget * > ( Subtarget ) ; const <ISA_LIT>RegisterInfo * TRI = ST -> getRegisterInfo ( ) ; bool UseSCCBr = isCBranchSCC ( N ) && isUniformBr ( N ) ; unsigned BrOp = UseSCCBr ? <STR_LIT> : <STR_LIT> ; unsigned CondReg = UseSCCBr ? ( unsigned ) <STR_LIT> : TRI -> getVCC ( ) ; SDLoc SL ( N ) ; if ( ! UseSCCBr ) { Cond = SDValue ( CurDAG -> getMachineNode ( ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , CurDAG -> getRegister ( ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) , Cond ) , <NUM_LIT> ) ;


<s> FOR_EACH_SUBRTX_VAR ( iter , array , PATTERN ( x ) , ALL ) { rtx sub = * iter ; if ( sub && GET_CODE ( sub ) == UNSPEC ) { int unspec_val = XINT ( sub , <NUM_LIT> ) ; switch ( unspec_val ) { case UNSPEC_PACISP :


<s> rtx x ; x = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( x , gen_rtx_AND ( SImode , gen_rtx_NOT ( SImode , mask ) , oldval ) ) ) ;

x = expand_simple_binop ( SImode , IOR , newval , x , x , <NUM_LIT> , OPTAB_LIB_WIDEN ) ;


<s> expandShiftParts ( Op . getNode ( ) , Lo , Hi , DAG ) ;

return DAG . getMergeValues ( { Lo , Hi } , SDLoc ( Op ) ) ;


<s> else { rtx temp2 = create_temp_reg_if_possible ( Pmode , op0 ) ; emit_insn ( gen_mov_address_step1 ( temp , op1 ) ) ; emit_insn ( gen_mov_address_step2 ( temp2 , temp , op1 ) ) ; emit_insn ( gen_mov_address_step3 ( op0 , temp2 , op1 ) ) ; } }


Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - Imm ) ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { SDValue Op0 , Op1 ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_m : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ; }


<s> return __builtin_aarch64_smin_nanpv4sf ( a , b ) ;


<s> unsigned A15SDOptimizer :: createVExt ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator InsertBefore , const DebugLoc & DL , unsigned Ssub0 , unsigned Ssub1 ) { Register Out = MRI -> createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , Out ) . addReg ( Ssub0 ) . addReg ( Ssub1 ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMW_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMW_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMH_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMH_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMB_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMB_AUTOINC_MAX ) ;


<s> unsigned SrcSubReg = TRI . getSubReg ( SrcReg , SubReg ) ; unsigned DestSubReg = TRI . getSubReg ( DestReg , SubReg ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestSubReg ) . addReg ( SrcSubReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) . addReg ( DestReg , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; } ; bool DstVRF = <STR_LIT> . contains ( DestReg ) ; bool DstSRF = <STR_LIT> . contains ( DestReg ) ; bool DstIRF = <STR_LIT> . contains ( DestReg ) ; bool DstVPRF = <STR_LIT> . contains ( DestReg ) ; bool DstSPRF = <STR_LIT> . contains ( DestReg ) ; bool DstZRF = <STR_LIT> . contains ( DestReg ) ; bool DstARF = <STR_LIT> . contains ( DestReg ) ; bool DstDRF = <STR_LIT> . contains ( DestReg ) ; bool DstADRF = <STR_LIT> . contains ( DestReg ) ; bool DstHSRF = <STR_LIT> . contains ( DestReg ) ; bool SrcVRF = <STR_LIT> . contains ( SrcReg ) ; bool SrcSRF = <STR_LIT> . contains ( SrcReg ) ; bool SrcIRF = <STR_LIT> . contains ( SrcReg ) ; bool SrcVPRF = <STR_LIT> . contains ( SrcReg ) ; bool SrcSPRF = <STR_LIT> . contains ( SrcReg ) ; bool SrcZRF = <STR_LIT> . contains ( SrcReg ) ; bool SrcARF = <STR_LIT> . contains ( SrcReg ) ; bool SrcDRF = <STR_LIT> . contains ( SrcReg ) ; bool SrcADRF = <STR_LIT> . contains ( SrcReg ) ; if ( SrcSRF && DstSRF ) { CopyRegWithDataType ( <STR_LIT> ) ; return ; } if ( SrcZRF && DstZRF ) { CopySubRegWithDataType ( <STR_LIT> , <STR_LIT> ) ; CopySubRegWithDataType ( <STR_LIT> , <STR_LIT> ) ; return ; } if ( SrcIRF && DstIRF ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( DestReg , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } if ( SrcSPRF && DstSPRF ) { CopyReg ( <STR_LIT> ) ; return ; } if ( SrcVPRF && DstVPRF ) { CopyReg ( <STR_LIT> ) ; return ; } if ( SrcVRF && DstVRF ) { CopyReg ( <STR_LIT> ) ; return ; } if ( SrcARF && DstARF ) { CopySubReg ( <STR_LIT> , <STR_LIT> ) ; CopySubReg ( <STR_LIT> , <STR_LIT> ) ; CopySubReg ( <STR_LIT> , <STR_LIT> ) ; CopySubReg ( <STR_LIT> , <STR_LIT> ) ; return ; } if ( SrcDRF && DstDRF ) { CopySubReg ( <STR_LIT> , <STR_LIT> ) ; CopySubReg ( <STR_LIT> , <STR_LIT> ) ; return ; } if ( SrcSRF && DstVRF ) {


<s> bool <ISA_LIT>AsmParser :: processInstruction ( MCInst & Inst , const OperandVector & Ops ) {


<s> const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

if ( Subtarget -> getDarwinVers ( ) > <NUM_LIT> ) return PrivateGlobalPrefix ;


<s> case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) ) ; return ; case MachineOperand :: MO_JumpTableIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_ExternalSymbol : { std :: string Name ( TAI -> getGlobalPrefix ( ) ) ; Name += MO . getSymbolName ( ) ; if ( TM . getRelocationModel ( ) != Reloc :: Static ) { GVStubs [ Name ] = Name + <STR_LIT> ; Name += <STR_LIT> ; } O << Name ; return ; }

case MachineOperand :: MO_GlobalAddress : {


return ( __m128d ) __builtin_ia32_cvtps2pd128_mask ( ( __v4sf ) __A , ( __v2df ) _mm_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrWithOffset . first ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( PtrWithOffset . second ) ; } , } } ;


<s> BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: COPY ) , NewSuperReg ) . addReg ( SuperReg . getReg ( ) , <NUM_LIT> , SuperReg . getSubReg ( ) ) ; BuildMI ( * MBB , MI , DL , get ( TargetOpcode :: COPY ) , SubReg ) . addReg ( NewSuperReg , <NUM_LIT> , SubIdx ) ;


<s> unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ; } else {

BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> case PseudoSourceValue :: JumpTable : case PseudoSourceValue :: GlobalValueCallEntry : case PseudoSourceValue :: ExternalSymbolCallEntry : case PseudoSourceValue :: TargetCustom : return <ISA_LIT>AS :: CONSTANT_ADDRESS ;


<s> unsigned MaxUserSGPRs = <NUM_LIT> + <NUM_LIT> + <NUM_LIT> + <NUM_LIT> + <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ; unsigned MaxSystemSGPRs = <NUM_LIT> + <NUM_LIT> + <NUM_LIT> + <NUM_LIT> + <NUM_LIT> ; return MaxUserSGPRs + MaxSystemSGPRs ;


<s> if ( reg == <STR_LIT> ) { MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; lastCheck -> insert ( CI , cmpInst ) ; MachineInstr * copyMoveM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( reg ) ; lastCheck -> insert ( CI , copyMoveM ) ; MachineInstr * copyMoveD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;

lastCheck -> insert ( CI , copyMoveD ) ;


<s> if ( Domain == <STR_LIT> ) { unsigned Opcode = TID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return false ; } else if ( Domain == <STR_LIT> ) { if ( TID . mayStore ( ) || TID . mayLoad ( ) ) return false ; } else {


<s> auto * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) continue ; if ( L -> getNumBackEdges ( ) != <NUM_LIT> ) continue ; auto * Header = L -> getHeader ( ) ; auto PI = pred_begin ( Header ) , PE = pred_end ( Header ) ; while ( ( PI != PE ) && ( * PI == Preheader ) ) ++ PI ; assert ( PI != PE ) ; auto BackBB = * PI ; for ( auto & I : BB ) { if ( ! isa < GetElementPtrInst > ( I ) ) continue ; auto & GEP = cast < GetElementPtrInst > ( I ) ; if ( GEP . getType ( ) != GEP . getOperand ( <NUM_LIT> ) -> getType ( ) ) continue ; if ( auto * I = dyn_cast < Instruction > ( GEP . getOperand ( <NUM_LIT> ) ) ) if ( ! DT . dominates ( I , Preheader -> getTerminator ( ) ) ) continue ; if ( GEP . getNumOperands ( ) > <NUM_LIT> ) continue ; if ( GEP . getPointerAddressSpace ( ) != <NUM_LIT> ) continue ; if ( ! DT . dominates ( & GEP , BackBB ) ) continue ; auto * Idx = GEP . getOperand ( <NUM_LIT> ) ; auto * S = SE . getSCEV ( Idx ) ; if ( isa < SCEVIntegralCastExpr > ( S ) ) S = cast < SCEVIntegralCastExpr > ( S ) -> getOperand ( ) ; if ( auto * SA = dyn_cast < SCEVAddRecExpr > ( S ) ) { auto * Start = SA -> getStart ( ) ; if ( ! Start ) continue ; auto * StartValue = SCEVs [ Start ] ; if ( ! StartValue ) continue ; if ( auto * I = dyn_cast < Instruction > ( StartValue ) ) if ( ! DT . dominates ( I , Preheader -> getTerminator ( ) ) ) continue ;

auto Rec = SA -> getStepRecurrence ( SE ) ;


<s> assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) && <STR_LIT> ) ; const uint32_t * RegMask = F -> getTarget ( ) . getRegisterInfo ( ) -> getCallPreservedMask ( CallingConv :: C ) ; if ( Subtarget -> is64Bit ( ) ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else if ( F -> getTarget ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ;


<s> static bool isDisp8 ( int Value ) { return Value == ( signed char ) Value ;


<s> case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> :


<s> MRI = & MF . getRegInfo ( ) ; ST = & MF . getSubtarget < GCNSubtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsIEEEMode = ST -> enableIEEEBit ( MF ) ; bool HasNSZ = MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineBasicBlock * MBB : depth_first ( & MF ) ) { MachineBasicBlock :: iterator I , Next ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; tryFoldInst ( TII , & MI ) ; if ( ! TII -> isFoldableCopy ( MI ) ) { if ( IsIEEEMode || ( ! HasNSZ && ! MI . getFlag ( MachineInstr :: FmNsz ) ) || ! tryFoldOMod ( MI ) ) tryFoldClamp ( MI ) ; continue ; } MachineOperand & OpToFold = MI . getOperand ( <NUM_LIT> ) ; bool FoldingImm = OpToFold . isImm ( ) || OpToFold . isFI ( ) ; if ( ! FoldingImm && ! OpToFold . isReg ( ) ) continue ; if ( OpToFold . isReg ( ) && ! TargetRegisterInfo :: isVirtualRegister ( OpToFold . getReg ( ) ) ) continue ;

MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ;


<s> if ( auto * BC = dyn_cast < BitCastOperator > ( U . getUser ( ) ) ) findUses ( BC , F , Uses , ConstantBCs ) ; else if ( auto * A = dyn_cast < GlobalAlias > ( U . getUser ( ) ) ) findUses ( A , F , Uses , ConstantBCs ) ; else if ( U . get ( ) -> getType ( ) != F . getType ( ) ) { CallBase * CB = dyn_cast < CallBase > ( U . getUser ( ) ) ; if ( ! CB ) continue ; Value * Callee = CB -> getCalledOperand ( ) ; if ( Callee != V ) continue ; if ( isa < Constant > ( U . get ( ) ) ) { auto C = ConstantBCs . insert ( cast < Constant > ( U . get ( ) ) ) ; if ( ! C . second ) continue ; } Uses . push_back ( std :: make_pair ( & U , & F ) ) ; }


<s> <ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) {


<s> case <STR_LIT> : return LowerMUL_LOHI ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; default :


<s> return ( hi19 << <NUM_LIT> ) | ( lo2 << <NUM_LIT> ) ;


<s> if ( RC == & <STR_LIT> && isCondInst ( MI ) ) return true ; else if ( RC != & <STR_LIT> && ! QII -> mayBeNewStore ( MI ) ) return false ; else { int NewOpcode = QII -> GetDotNewOp ( MI ) ; const MCInstrDesc & desc = QII -> get ( NewOpcode ) ; DebugLoc dl ; MachineInstr * NewMI = MI -> getParent ( ) -> getParent ( ) -> CreateMachineInstr ( desc , dl ) ;

bool ResourcesAvailable = ResourceTracker -> canReserveResources ( NewMI ) ;


<s> unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;

SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> int getStackPointerBias ( ) override final { return <NUM_LIT> ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( SDValue ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } unsigned RetAddrOffset = <NUM_LIT> ; if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>MachineFunctionInfo * SFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = SFI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , PtrVT ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; RetAddrOffset = <NUM_LIT> ; } RetOps [ <NUM_LIT> ] = Chain ;

RetOps [ <NUM_LIT> ] = DAG . getConstant ( RetAddrOffset , DL , <STR_LIT> ) ;


<s> Aux [ <NUM_LIT> + i * <NUM_LIT> + <NUM_LIT> ] = Dimension [ i ] ; Aux [ <NUM_LIT> + i * <NUM_LIT> + <NUM_LIT> ] = Dimension [ i ] >> <NUM_LIT> ; size = size * Dimension [ i ] ; } } HasAux = true ; Aux [ <NUM_LIT> ] = size & <NUM_LIT> ; Aux [ <NUM_LIT> ] = size >> <NUM_LIT> ; DIType BaseType = CTy . getTypeDerivedFrom ( ) ; PopulateDebugInfo ( BaseType , TypeNo , HasAux , Aux , TagName ) ;


<s> if ( TYPE_MODE ( type ) == BLKmode ) {

HOST_WIDE_INT size = int_size_in_bytes ( type ) ;


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return C_RegisterClass ; default :


<s> case <STR_LIT> : case <STR_LIT> : { KnownBits LHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; KnownBits RHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned TrailZ = LHSKnown . countMinTrailingZeros ( ) + RHSKnown . countMinTrailingZeros ( ) ; Known . Zero . setLowBits ( std :: min ( TrailZ , <NUM_LIT> ) ) ; unsigned LHSValBits = <NUM_LIT> - std :: max ( LHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned RHSValBits = <NUM_LIT> - std :: max ( RHSKnown . countMinSignBits ( ) , <NUM_LIT> ) ; unsigned MaxValBits = std :: min ( LHSValBits + RHSValBits , <NUM_LIT> ) ; if ( MaxValBits >= <NUM_LIT> ) break ; bool Negative = false ; if ( Opc == <STR_LIT> ) { bool LHSNegative = ! ! ( LHSKnown . One & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool LHSPositive = ! ! ( LHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSNegative = ! ! ( RHSKnown . One & ( <NUM_LIT> << <NUM_LIT> ) ) ; bool RHSPositive = ! ! ( RHSKnown . Zero & ( <NUM_LIT> << <NUM_LIT> ) ) ; if ( ( ! LHSNegative && ! LHSPositive ) || ( ! RHSNegative && ! RHSPositive ) ) break ; Negative = ( LHSNegative && RHSPositive ) || ( LHSPositive && RHSNegative ) ; } if ( Negative ) Known . One . setHighBits ( <NUM_LIT> - MaxValBits ) ; else Known . Zero . setHighBits ( <NUM_LIT> - MaxValBits ) ; break ; } case <STR_LIT> : { ConstantSDNode * CMask = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CMask ) return ; KnownBits LHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; KnownBits RHSKnown = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned Sel = CMask -> getZExtValue ( ) ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; I += <NUM_LIT> ) { unsigned SelBits = Sel & <NUM_LIT> ; if ( SelBits < <NUM_LIT> ) {


<s> return ! ( rotr32 ( ~ <NUM_LIT> , getSOImmValRotate ( First ) ) & First ) ;


<s> sandboxBaseDisp ( Inst , II , Inst . getOperand ( MemIdx ) . getReg ( ) , Out , STI ) ; } else { Out . EmitBundleLock ( false ) ; Out . EmitInstruction ( getAddrInstr ( Inst , II , MemIdx , Target ) , STI ) ; emitBicMask ( kSandboxMask , Target , Pred , PredReg , Out , STI ) ; MCInst SandboxedInst ; SandboxedInst . setOpcode ( sandboxOpcode ( Inst . getOpcode ( ) ) ) ; SandboxedInst . addOperand ( Inst . getOperand ( RegIdx ) ) ;

SandboxedInst . addOperand ( MCOperand :: CreateReg ( Target ) ) ;


<s> static HARD_REG_SET sparc_zero_call_used_regs ( HARD_REG_SET need_zeroed_hardregs ) { for ( unsigned int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { if ( regno >= SPARC_FCC_REG || ( regno >= SPARC_FIRST_FP_REG && ! TARGET_VIS ) ) CLEAR_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ; else if ( regno >= SPARC_FIRST_V9_FP_REG && ( regno & <NUM_LIT> ) ) ; else { machine_mode mode ; rtx reg ; if ( regno < SPARC_FIRST_FP_REG ) { reg = regno_reg_rtx [ regno ] ; mode = GET_MODE ( reg ) ; } else { mode = regno < SPARC_FIRST_V9_FP_REG ? SFmode : DFmode ; reg = gen_raw_REG ( mode , regno ) ;


<s> const <ISA_LIT>FloatMCExpr * <ISA_LIT>FloatMCExpr :: create ( VariantKind Kind , APFloat Flt , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>FloatMCExpr ( Kind , Flt ) ;


<s> OutStreamer -> EmitLabel ( CurrentFnSym ) ;


<s> if ( ! InVirtReg ) continue ; if ( Arg . hasAttribute ( Attribute :: SExt ) ) VRX . insert ( std :: make_pair ( InVirtReg , ExtType ( ExtType :: SExt , Width ) ) ) ; else if ( Arg . hasAttribute ( Attribute :: ZExt ) ) VRX . insert ( std :: make_pair ( InVirtReg , ExtType ( ExtType :: ZExt , Width ) ) ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: getAddr ( NodeTy * N , SelectionDAG & DAG ) const { DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> | <STR_LIT> ) ;

SDValue ADRP = DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) ;


<s> int LROffset = <ISA_LIT>FrameLowering :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; RASI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , LROffset , true ) ; FI -> setReturnAddrSaveIndex ( RASI ) ; }

return DAG . getFrameIndex ( RASI , PtrVT ) ;


<s> emit_move_insn ( op0 , result ) ; return true ; } else if ( flag_pic ) { if ( reload_in_progress ) df_set_regs_ever_live ( PIC_OFFSET_TABLE_REGNUM , true ) ; result = expand_pic_symbol_ref ( mode , op1 ) ; if ( TARGET_PIC_DATA_TEXT_REL && GET_CODE ( op0 ) == REG && REGNO ( op0 ) >= FIRST_PSEUDO_REGISTER ) result = force_reg ( SImode , result ) ; emit_move_insn ( op0 , result ) ; return true ; } } if ( GET_CODE ( op1 ) == PLUS && GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == CONST ) { rtx p0 , p1 = NULL , result , temp ; p0 = XEXP ( XEXP ( op1 , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( p0 ) == PLUS ) { p1 = XEXP ( p0 , <NUM_LIT> ) ; p0 = XEXP ( p0 , <NUM_LIT> ) ; }


<s> int dst_offset = first_time ? <NUM_LIT> : <NUM_LIT> ; int dst_inc_amount = dst_offset + bytes - <NUM_LIT> ; int src_inc_amount = bytes - ( got_extra ? <NUM_LIT> : <NUM_LIT> ) ; int last_shift ; rtx my_operands [ <NUM_LIT> ] ; if ( ! got_extra ) output_asm_insn ( <STR_LIT> , operands ) ; if ( bytes >= <NUM_LIT> ) { bytes -= <NUM_LIT> ; output_asm_insn ( <STR_LIT> , operands ) ; my_operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; my_operands [ <NUM_LIT> ] = GEN_INT ( dst_offset ) ; my_operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; output_asm_insn ( <STR_LIT> , my_operands ) ; if ( bytes > <NUM_LIT> ) { dst_offset += <NUM_LIT> ; last_shift = <NUM_LIT> ; } } else last_shift = <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { my_operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; my_operands [ <NUM_LIT> ] = GEN_INT ( last_shift ) ; output_asm_insn ( <STR_LIT> , my_operands ) ; my_operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; my_operands [ <NUM_LIT> ] = GEN_INT ( dst_offset ) ;


<s> if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; Register DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; if ( RVEVT . isVector ( ) && RVEVT . getVectorElementCount ( ) . isVector ( ) && ! Subtarget -> isLittleEndian ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; if ( RVVT == <STR_LIT> ) return false ; MVT DestVT = VA . getValVT ( ) ; if ( RVVT != DestVT ) { if ( RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; bool IsZExt = Outs [ <NUM_LIT> ] . Flags . isZExt ( ) ; SrcReg = emitIntExt ( RVVT , SrcReg , DestVT , IsZExt ) ; if ( SrcReg == <NUM_LIT> ) return false ; } if ( Subtarget -> isTargetILP32 ( ) && RV -> getType ( ) -> isPointerTy ( ) ) SrcReg = emitAnd_ri ( <STR_LIT> , SrcReg , <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , DestReg ) . addReg ( SrcReg ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; }

MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) ;


<s> explicit <ISA_LIT>IntelAsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , const TargetAsmInfo * T , bool V ) : AsmPrinter ( O , TM , T , V ) {


<s> if ( isDarwin ( ) ) HasLazyResolverStubs = true ; if ( TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasQPX || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU = true ; IsQPXStackUnaligned = QPXStackUnaligned ;

StackAlignment = getPlatformStackAlignment ( ) ;


<s> if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { EVT PtrVT = getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ; Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , PtrVT ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , Addr , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) { return false ;


<s> bool <ISA_LIT>InstructionSelector :: selectCopy ( MachineInstr & I , MachineRegisterInfo & MRI ) const { Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned DstSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ; const RegisterBank & DstRegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; const RegisterBank & SrcRegBank = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; if ( Register :: isPhysicalRegister ( DstReg ) ) { assert ( I . isCopy ( ) && <STR_LIT> ) ; if ( DstSize > SrcSize && SrcRegBank . getID ( ) == <STR_LIT> && DstRegBank . getID ( ) == <STR_LIT> ) { const TargetRegisterClass * SrcRC = getRegClass ( MRI . getType ( SrcReg ) , SrcRegBank ) ; const TargetRegisterClass * DstRC = getRegClassFromGRPhysReg ( DstReg ) ; if ( SrcRC != DstRC ) { Register ExtSrc = MRI . createVirtualRegister ( DstRC ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( ExtSrc ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( getSubRegIndex ( SrcRC ) ) ; I . getOperand ( <NUM_LIT> ) . setReg ( ExtSrc ) ; } } return true ; } assert ( ( ! Register :: isPhysicalRegister ( SrcReg ) || I . isCopy ( ) ) && <STR_LIT> ) ; assert ( ( DstSize == SrcSize || ( Register :: isPhysicalRegister ( SrcReg ) && DstSize <= RBI . getSizeInBits ( SrcReg , MRI , TRI ) ) ) && <STR_LIT> ) ; const TargetRegisterClass * DstRC = getRegClass ( MRI . getType ( DstReg ) , DstRegBank ) ; if ( SrcRegBank . getID ( ) == <STR_LIT> && DstRegBank . getID ( ) == <STR_LIT> && SrcSize > DstSize && Register :: isPhysicalRegister ( SrcReg ) ) {

const TargetRegisterClass * SrcRC = getRegClassFromGRPhysReg ( SrcReg ) ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Memory . OffsetRegNum ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ;


<s> MultipleShape ( ) : LabeledShape ( SK_Multiple ) , Breaks ( <NUM_LIT> ) , UseSwitch ( false ) {


<s> getTargetStreamer ( ) . EmitARM64WinCFINop ( ) ; return false ;


<s> struct ix86_address parts ; int ok ; if ( REG_P ( operands [ <NUM_LIT> ] ) || ( SImode_address_operand ( operands [ <NUM_LIT> ] , VOIDmode ) && REG_P ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ) return false ; ok = ix86_decompose_address ( operands [ <NUM_LIT> ] , & parts ) ; gcc_assert ( ok ) ; if ( ( parts . base != NULL_RTX ) + ( parts . index != NULL_RTX ) + ( parts . disp != NULL_RTX ) + ( parts . scale > <NUM_LIT> ) < <NUM_LIT> ) return false ; if ( parts . disp && flag_pic && ! LEGITIMATE_PIC_OPERAND_P ( parts . disp ) ) return false ; regno0 = true_regnum ( operands [ <NUM_LIT> ] ) ; regno1 = INVALID_REGNUM ; regno2 = INVALID_REGNUM ; if ( parts . base ) regno1 = true_regnum ( parts . base ) ;

if ( parts . index ) regno2 = true_regnum ( parts . index ) ;


<s> return ( __m64 ) __builtin_ia32_cvtps2pi ( ( __v4sf ) __A ) ;


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ;

uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) & <NUM_LIT> , <NUM_LIT> ) ;


<s> for ( unsigned k = <NUM_LIT> , eee = AddrMI -> getNumOperands ( ) ; k != eee ; ++ k ) { const MachineOperand & MO = AddrMI -> getOperand ( k ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) != BaseReg ) { OptOk = false ; break ; } if ( MO . isUse ( ) && ! MO . isKill ( ) && MO . getReg ( ) != IdxReg ) { OptOk = false ; break ; } } if ( ! OptOk ) continue ; for ( -- PrevI ; PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ; -- PrevI ) ; MachineInstr * LeaMI = PrevI ; if ( ( LeaMI -> getOpcode ( ) != <STR_LIT> && LeaMI -> getOpcode ( ) != <STR_LIT> ) || LeaMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) OptOk = false ; if ( ! OptOk ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> << * AddrMI << <STR_LIT> << * LeaMI ) ; unsigned Opc = ByteOk ? <STR_LIT> : <STR_LIT> ; MachineInstr * NewJTMI = BuildMI ( MBB , MI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( IdxReg , getKillRegState ( IdxRegKill ) ) . addJumpTableIndex ( JTI , JTOP . getTargetFlags ( ) ) . addImm ( MI -> getOperand ( JTOpIdx + <NUM_LIT> ) . getImm ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> << * NewJTMI ) ; unsigned NewSize = TII -> GetInstSizeInBytes ( NewJTMI ) ; unsigned OrigSize = TII -> GetInstSizeInBytes ( AddrMI ) ; OrigSize += TII -> GetInstSizeInBytes ( LeaMI ) ; OrigSize += TII -> GetInstSizeInBytes ( MI ) ; AddrMI -> eraseFromParent ( ) ; LeaMI -> eraseFromParent ( ) ; MI -> eraseFromParent ( ) ; int delta = OrigSize - NewSize ; BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; adjustBBOffsetsAfter ( MBB ) ; ++ NumTBs ; MadeChange = true ; } } return MadeChange ;


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int OpNum , const char * Modifier ) { const MachineOperand & MO = MI -> getOperand ( OpNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && <STR_LIT> ) ; O << TM . getRegisterInfo ( ) -> get ( MO . getReg ( ) ) . AsmName ; return ; case MachineOperand :: MO_Immediate : if ( ! Modifier || strcmp ( Modifier , <STR_LIT> ) ) O << '#' ; O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isMemOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; std :: string Name = Mang -> getValueName ( MO . getGlobal ( ) ) ; assert ( MO . getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isCallOp ) O << '#' ; else if ( isMemOp ) O << '&' ; O << Name ; return ; } case MachineOperand :: MO_ExternalSymbol : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; std :: string Name ( TAI -> getGlobalPrefix ( ) ) ; Name += MO . getSymbolName ( ) ;


<s> const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ;

return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , ExtVT , V1 , V2 ) ; } if ( VT . isFloatingPoint ( ) && V2Index != <NUM_LIT> ) return SDValue ( ) ; V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ; if ( ExtVT != VT ) V2 = DAG . getBitcast ( VT , V2 ) ; if ( V2Index != <NUM_LIT> ) { if ( VT . isFloatingPoint ( ) || VT . getVectorNumElements ( ) <= <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > V2Shuffle ( Mask . size ( ) , <NUM_LIT> ) ; V2Shuffle [ V2Index ] = <NUM_LIT> ; V2 = DAG . getVectorShuffle ( VT , DL , V2 , DAG . getUNDEF ( VT ) , V2Shuffle ) ; } else { V2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getConstant ( V2Index * EltVT . getSizeInBits ( ) / <NUM_LIT> , DL , DAG . getTargetLoweringInfo ( ) . getScalarShiftAmountTy ( DAG . getDataLayout ( ) , VT ) ) ) ; V2 = DAG . getBitcast ( VT , V2 ) ; }


<s> if ( ( mode == HImode && TARGET_H8300H && amount >= <NUM_LIT> ) || ( mode == HImode && TARGET_H8300S && amount == <NUM_LIT> ) || ( mode == SImode && TARGET_H8300H && amount >= <NUM_LIT> ) || ( mode == SImode && TARGET_H8300S && amount >= <NUM_LIT> ) ) { amount = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> - amount ; length += <NUM_LIT> ; } if ( TARGET_H8300S ) amount = amount / <NUM_LIT> + amount % <NUM_LIT> ;


<s> <ISA_LIT>GISelActualAccessor ( CallLowering * CL ) : CL ( CL ) {


<s> return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> , <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsUnalignedMemoryAccesses ( EVT VT , unsigned , bool * Fast ) const { if ( Fast ) * Fast = true ;


<s> static MCInstPrinter * createMCInstPrinter ( const Triple & , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { assert ( SyntaxVariant == <NUM_LIT> ) ;

return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> return ( PHI . getNumOperands ( ) - <NUM_LIT> ) / <NUM_LIT> ;


<s> enum reg_class mcore_secondary_reload_class ( enum reg_class class , enum machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { if ( TEST_HARD_REG_BIT ( reg_class_contents [ class ] , <NUM_LIT> ) && ! mcore_r15_operand_p ( x ) ) return LRW_REGS ; return NO_REGS ;


<s> if ( TARGET_64BIT ) return false ; return ( decl && ! TREE_PUBLIC ( decl ) ) ;


<s> return ( int32x4_t ) __builtin_neon_vmovlsv4hi ( __a ) ;


<s> ( void ) State . AllocateReg ( CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ) ; } return false ; } if ( ! ArgFlags . isHva ( ) || ArgFlags . isHvaStart ( ) ) { ( void ) State . AllocateReg ( CC_<ISA_LIT>_64_VectorCallGetGPRs ( ) ) ; if ( unsigned Reg = State . AllocateReg ( CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ) ) { if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ;


<s> void llvm :: createSplat2ShuffleMask ( MVT VT , SmallVectorImpl < int > & Mask , bool Lo ) { assert ( Mask . empty ( ) && <STR_LIT> ) ; int NumElts = VT . getVectorNumElements ( ) ; for ( int i = <NUM_LIT> ; i < NumElts ; ++ i ) { int Pos = i / <NUM_LIT> ; Pos += ( Lo ? <NUM_LIT> : NumElts / <NUM_LIT> ) ;


<s> case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformFMACombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformINTRINSIC_WO_CHAINCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformINSERTPSCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DAG , Subtarget ) ; }


return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , IsPatchPoint , Outs , OutVals , Ins , dl , DAG , InVals , CS ) ;


<s> DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; llvm_unreachable ( <STR_LIT> ) ; return Count ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override {


<s> <ISA_LIT>EHRestoreStackPointer ( ) : MachineFunctionPass ( ID ) {


<s> SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned Opc , <ISA_LIT>CC = ~ <NUM_LIT> ; LookThroughSetCC ( LHS , RHS , CC , <ISA_LIT>CC ) ; SDValue CompareFlag ; if ( LHS . getValueType ( ) . isInteger ( ) ) { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; Opc = LHS . getValueType ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = IntCondCCodeToICC ( CC ) ; } else { if ( ! hasHardQuad && LHS . getValueType ( ) == <STR_LIT> ) { if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = FPCondCCodeToFCC ( CC ) ; CompareFlag = TLI . LowerF128Compare ( LHS , RHS , <ISA_LIT>CC , dl , DAG ) ; Opc = <STR_LIT> ; } else { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; Opc = <STR_LIT> ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = FPCondCCodeToFCC ( CC ) ;