<s> SDValue <ISA_LIT>TargetLowering :: BuildSDIVPow2 ( SDNode * N , const APInt & Divisor , SelectionDAG & DAG , SmallVectorImpl < SDNode * > & Created ) const { AttributeList Attr = DAG . getMachineFunction ( ) . getFunction ( ) . getAttributes ( ) ; if ( isIntDivCheap ( N -> getValueType ( <NUM_LIT> ) , Attr ) ) return SDValue ( N , <NUM_LIT> ) ; assert ( ( Divisor . isPowerOf2 ( ) || Divisor . isNegatedPowerOf2 ( ) ) && <STR_LIT> ) ; if ( ! Subtarget . canUseCMOV ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && ! ( Subtarget . is64Bit ( ) && VT == <STR_LIT> ) ) return SDValue ( ) ; unsigned Lg2 = Divisor . countTrailingZeros ( ) ; if ( Lg2 == <NUM_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; APInt Lg2Mask = APInt :: getLowBitsSet ( VT . getSizeInBits ( ) , Lg2 ) ; SDValue Pow2MinusOne = DAG . getConstant ( Lg2Mask , DL , VT ) ; SDValue Cmp = DAG . getSetCC ( DL , <STR_LIT> , N0 , Zero , <STR_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , VT , N0 , Pow2MinusOne ) ; SDValue CMov = DAG . getNode ( <STR_LIT> , DL , VT , Cmp , Add , N0 ) ; Created . push_back ( Cmp . getNode ( ) ) ; Created . push_back ( Add . getNode ( ) ) ; Created . push_back ( CMov . getNode ( ) ) ; SDValue SRA = DAG . getNode ( <STR_LIT> , DL , VT , CMov , DAG . getConstant ( Lg2 , DL , <STR_LIT> ) ) ; if ( Divisor . isNonNegative ( ) ) return SRA ; Created . push_back ( SRA . getNode ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zero , SRA ) ;


<s> } else NumBytes = StackSize - CSSize ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = prior ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> getDesc ( ) . isTerminator ( ) ) break ; -- MBBI ; } DL = MBBI -> getDebugLoc ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; if ( CSSize ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( CSSize ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> InductionMap IndMap ; typedef MachineBasicBlock :: instr_iterator instr_iterator ; for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { MachineInstr * Phi = & * I ; for ( unsigned i = <NUM_LIT> , n = Phi -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { if ( Phi -> getOperand ( i + <NUM_LIT> ) . getMBB ( ) != Latch ) continue ; unsigned PhiOpReg = Phi -> getOperand ( i ) . getReg ( ) ; MachineInstr * DI = MRI -> getVRegDef ( PhiOpReg ) ; unsigned UpdOpc = DI -> getOpcode ( ) ; bool isAdd = ( UpdOpc == <STR_LIT> || UpdOpc == <STR_LIT> ) ; if ( isAdd ) { unsigned IndReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Opnd2 = DI -> getOperand ( <NUM_LIT> ) ; int64_t V ; if ( MRI -> getVRegDef ( IndReg ) == Phi && checkForImmediate ( Opnd2 , V ) ) { unsigned UpdReg = DI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; IndMap . insert ( std :: make_pair ( UpdReg , std :: make_pair ( IndReg , V ) ) ) ; } } } } SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineBasicBlock * TB = nullptr , * FB = nullptr ; bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; if ( NotAnalyzed ) return false ; unsigned PredR , PredPos , PredRegFlags ; if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) return false ; MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ; if ( ! PredI -> isCompare ( ) ) return false ; unsigned CmpReg1 = <NUM_LIT> , CmpReg2 = <NUM_LIT> ; int CmpImm = <NUM_LIT> , CmpMask = <NUM_LIT> ; bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ;


<s> void emitRRR ( unsigned Opcode , unsigned Reg0 , unsigned Reg1 , unsigned Reg2 , SMLoc IDLoc , SmallVectorImpl < MCInst > & Instructions ) { emitRRX ( Opcode , Reg0 , Reg1 , MCOperand :: createReg ( Reg2 ) , IDLoc , Instructions ) ;


<s> if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; unsigned Reg0 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg1IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Reg2IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ChangeReg0 = false ; if ( Reg0 == Reg1 ) { assert ( MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) && <STR_LIT> ) ; Reg2IsKill = false ; ChangeReg0 = true ; } unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg1 ) ;


<s> LDSection * getExIdxSection ( ) const { return m_pExIdxSection ;


<s> MachineInstr & MI = * I ; unsigned NumOperands = MI . getDesc ( ) . getNumOperands ( ) ; assert ( NumOperands == <NUM_LIT> && <STR_LIT> ) ; unsigned Op0 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; unsigned Op1 = getFPReg ( MI . getOperand ( NumOperands - <NUM_LIT> ) ) ; bool KillsOp0 = MI . killsRegister ( <STR_LIT> + Op0 ) ; bool KillsOp1 = MI . killsRegister ( <STR_LIT> + Op1 ) ; moveToTop ( Op0 , I ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( getSTReg ( Op1 ) ) ; MI . removeOperand ( <NUM_LIT> ) ; MI . setDesc ( TII -> get ( getConcreteOpcode ( MI . getOpcode ( ) ) ) ) ; MI . dropDebugNumber ( ) ; if ( KillsOp0 ) freeStackSlotAfter ( I , Op0 ) ;

if ( KillsOp1 && Op0 != Op1 ) freeStackSlotAfter ( I , Op1 ) ;


<s> unsigned ElementWidth = KindRes -> second ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( Reg , RegKind :: NeonVector , ElementWidth , S , getLoc ( ) , getContext ( ) ) ) ; if ( ! Kind . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Kind , false , S , getContext ( ) ) ) ; return tryParseVectorIndex ( Operands ) == MatchOperand_ParseFail ;


<s> RLo = DAG . getNode ( <STR_LIT> , dl , ExVT , RLo , DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ) ; RHi = DAG . getNode ( <STR_LIT> , dl , ExVT , RHi , DAG . getConstant ( <NUM_LIT> , dl , ExVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , RLo , RHi ) ; } if ( VT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && ! Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; static const int UnpackMask [ ] = { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ; SDValue Aodds = DAG . getVectorShuffle ( VT , dl , A , A , UnpackMask ) ; SDValue Bodds = DAG . getVectorShuffle ( VT , dl , B , B , UnpackMask ) ; SDValue Evens = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A , B ) ; SDValue Odds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Aodds , Bodds ) ; Evens = DAG . getBitcast ( VT , Evens ) ; Odds = DAG . getBitcast ( VT , Odds ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl , Evens , Odds , ShufMask ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; MVT MulVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; if ( Subtarget . hasSSE41 ( ) && DAG . ComputeNumSignBits ( A ) > <NUM_LIT> && DAG . ComputeNumSignBits ( B ) > <NUM_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getBitcast ( MulVT , A ) , DAG . getBitcast ( MulVT , B ) ) ; } APInt LowerBitsMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; bool ALoIsZero = DAG . MaskedValueIsZero ( A , LowerBitsMask ) ; bool BLoIsZero = DAG . MaskedValueIsZero ( B , LowerBitsMask ) ; APInt UpperBitsMask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; bool AHiIsZero = DAG . MaskedValueIsZero ( A , UpperBitsMask ) ; bool BHiIsZero = DAG . MaskedValueIsZero ( B , UpperBitsMask ) ; SDValue Alo = DAG . getBitcast ( MulVT , A ) ; SDValue Blo = DAG . getBitcast ( MulVT , B ) ; SDValue Zero = getZeroVector ( VT , Subtarget , DAG , dl ) ; SDValue AloBlo = Zero ; if ( ! ALoIsZero && ! BLoIsZero ) AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , Alo , Blo ) ;


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( After ) , <STR_LIT> , IPM , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ;


<s> if ( ! ST -> hasMVEIntegerOps ( ) ) return false ; if ( L -> getNumBlocks ( ) > <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } assert ( L -> isInnermost ( ) && <STR_LIT> ) ; HardwareLoopInfo HWLoopInfo ( L ) ; if ( ! HWLoopInfo . canAnalyze ( * LI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } if ( ! isHardwareLoopProfitable ( L , SE , AC , TLI , HWLoopInfo ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ;


<s> cost [ vect_prologue ] = cost [ vect_body ] = cost [ vect_epilogue ] = <NUM_LIT> ; return cost ;


<s> MI -> removeFromParent ( ) ; MBB -> insert ( I , MI ) ; }


<s> if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( SDValue V = combineToExtendBoolVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ;

if ( VT . isVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return R ;


<s> RTVEC_ELT ( v , i ) = gen_lowpart ( inner_mode , x ) ; } gcc_assert ( arglist == NULL ) ; if ( ! target || ! register_operand ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ;

ix86_expand_vector_init ( true , target , gen_rtx_PARALLEL ( tmode , v ) ) ;


<s> void clearParamsAndResults ( ) { Params . clear ( ) ; Results . clear ( ) ;


<s> if ( isTypeLegal ( Ty , VT ) ) return true ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return true ;


<s> static bool spu_vector_alignment_reachable ( const_tree type ATTRIBUTE_UNUSED , bool is_packed ) { if ( is_packed ) return false ; return true ;


<s> const SmallVectorImpl < const MachineInstr * > & getWaitingQueueFor ( const MachineInstr * MI ) const {

assert ( WaitingQueues . count ( MI ) && <STR_LIT> ) ;


<s> MIB . addDef ( PhysReg , RegState :: Implicit ) ; MIRBuilder . buildCopy ( ValVReg , PhysReg ) ;


<s> ArrayRef < MachineConstantPoolEntry > Constants = MI . getParent ( ) -> getParent ( ) -> getConstantPool ( ) -> getConstants ( ) ; const MachineConstantPoolEntry & ConstantEntry = Constants [ Op . getIndex ( ) ] ; if ( ConstantEntry . isMachineConstantPoolEntry ( ) ) return nullptr ;

const Constant * C = ConstantEntry . Val . ConstVal ;


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr & Old = * I ; DebugLoc dl = Old . getDebugLoc ( ) ; unsigned Amount = Old . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned Opc = Old . getOpcode ( ) ; int PIdx = Old . findFirstPredOperandIdx ( ) ; <STR_LIT> Pred = ( PIdx == - <NUM_LIT> ) ? <STR_LIT> : ( <STR_LIT> ) Old . getOperand ( PIdx ) . getImm ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned PredReg = Old . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , - Amount , MachineInstr :: NoFlags , Pred , PredReg ) ; } else { unsigned PredReg = Old . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ; emitSPUpdate ( is<ISA_LIT> , MBB , I , dl , TII , Amount , MachineInstr :: NoFlags , Pred , PredReg ) ; } }


<s> DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return nullptr ; } std :: pair < bool , SDNode * > Ret = selectNode ( Node ) ; if ( Ret . first ) return Ret . second ; switch ( Opcode ) { default : break ; case <STR_LIT> : return getGlobalBaseReg ( ) ; case <STR_LIT> :


<s> RegisterRef RR = TA . Addr -> getRegRef ( * this ) ; NodeAddr < T > TAP ; RegisterAggr Defs ( TRI ) ; for ( auto I = DS . top ( ) , E = DS . bottom ( ) ; I != E ; I . down ( ) ) { RegisterRef QR = I -> Addr -> getRegRef ( * this ) ; bool Alias = Defs . hasAliasOf ( QR ) ; bool Cover = Defs . insert ( QR ) . hasCoverOf ( RR ) ; if ( Alias ) { if ( Cover ) break ; continue ; } NodeAddr < DefNode * > RDA = * I ; if ( TAP . Id == <NUM_LIT> ) {


<s> SDValue U = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 ) ; SDValue UH = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , U , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; UH = DAG . getZExtOrTrunc ( UH , DL , <STR_LIT> ) ; U = DAG . getZExtOrTrunc ( U , DL , <STR_LIT> ) ; SDValue E = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UH , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; E = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , DAG . getConstant ( ExpMask , DL , <STR_LIT> ) ) ; E = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , DAG . getConstant ( - ExpBiasf64 + ExpBiasf16 , DL , <STR_LIT> ) ) ; SDValue M = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UH , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; M = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , M , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue MaskedSig = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , UH , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; MaskedSig = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedSig , U ) ; SDValue Lo40Set = DAG . getSelectCC ( DL , MaskedSig , Zero , Zero , One , <STR_LIT> ) ; M = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , M , Lo40Set ) ; SDValue I = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getSelectCC ( DL , M , Zero , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Zero , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue N = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , M , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , E , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ;

SDValue OneSubExp = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , One , E ) ;


<s> LLVMContext & Context = TheModule -> getContext ( ) ; Type * FieldTys [ ] = { Type :: getInt8PtrTy ( Context ) , Type :: getInt8PtrTy ( Context ) , getEHLinkRegistrationType ( ) , Type :: getInt32Ty ( Context ) , Type :: getInt32Ty ( Context ) } ; SEHRegistrationTy = StructType :: create ( FieldTys , <STR_LIT> ) ; return SEHRegistrationTy ;


<s> return <STR_LIT> ; case <STR_LIT> : return MI && isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ? <STR_LIT> : <NUM_LIT> ; case <STR_LIT> : return MI && isInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ? <STR_LIT> : <NUM_LIT> ;


<s> assert ( DstVT . isFloatingPoint ( ) && <STR_LIT> ) ; if ( SrcEltSize == <NUM_LIT> ) { MVT IntVT = DstVT . changeVectorElementTypeToInteger ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue ZeroSplat = DAG . getNode ( <STR_LIT> , DL , IntVT , DAG . getUNDEF ( IntVT ) , Zero , VL ) ; SDValue One = DAG . getConstant ( <ISA_LIT>ISDExtOpc == <STR_LIT> ? <NUM_LIT> : - <NUM_LIT> , DL , XLenVT ) ; SDValue OneSplat = DAG . getNode ( <STR_LIT> , DL , IntVT , DAG . getUNDEF ( IntVT ) , One , VL ) ; Src = DAG . getNode ( <STR_LIT> , DL , IntVT , Src , OneSplat , ZeroSplat , VL ) ; } else if ( DstEltSize > ( <NUM_LIT> * SrcEltSize ) ) { MVT IntVT = <STR_LIT> ( <STR_LIT> ( DstEltSize / <NUM_LIT> ) , DstVT . getVectorElementCount ( ) ) ; Src = DAG . getNode ( <ISA_LIT>ISDExtOpc , DL , IntVT , { Src , Mask , VL } ) ; } Result = DAG . getNode ( <ISA_LIT>ISDOpc , DL , DstVT , { Src , Mask , VL } ) ; } else { assert ( SrcVT . isFloatingPoint ( ) && DstVT . isInteger ( ) && <STR_LIT> ) ; if ( DstEltSize > ( <NUM_LIT> * SrcEltSize ) ) { assert ( SrcVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT InterimFVT = <STR_LIT> ( <STR_LIT> , DstVT . getVectorElementCount ( ) ) ; Src = DAG . getNode ( <STR_LIT> , DL , InterimFVT , { Src , Mask , VL } ) ; } Result = DAG . getNode ( <ISA_LIT>ISDOpc , DL , DstVT , { Src , Mask , VL } ) ; } } else { if ( SrcVT . isInteger ( ) ) { assert ( DstVT . isFloatingPoint ( ) && <STR_LIT> ) ; MVT InterimFVT = DstVT ;

if ( SrcEltSize > ( <NUM_LIT> * DstEltSize ) ) {


<s> if ( IsPS && ( HasExports || MustExport ) ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> :: ET_NULL ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ;


<s> SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , Index . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; SDValue VMask = getMaskNode ( Mask , MaskVT , & Subtarget , DAG , dl ) ;

SDValue Ops [ ] = { VMask , Base , Scale , Index , Disp , Segment , Chain } ;


<s> return COREV_EXPAND_HWLP_PSEUDO_NAME ;


<s> return ( int16x4_t ) __builtin_neon_vpadalsv8qi ( __a , __b ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( getGPRMM16Reg ( ) ) ) ;


<s> unsigned getWAReg ( unsigned VReg ) const { auto I = Register :: virtReg2Index ( VReg ) ; assert ( I < WARegs . size ( ) ) ;


<s> unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : return VTBits ; case <STR_LIT> : { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; unsigned Tmp = DAG . ComputeNumSignBits ( Src , Depth + <NUM_LIT> ) ; Tmp += VTBits - Src . getScalarValueSizeInBits ( ) ; return Tmp ; } case <STR_LIT> : { unsigned SrcBits = Op . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) ; unsigned Tmp0 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; unsigned Tmp1 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ;

unsigned Tmp = std :: min ( Tmp0 , Tmp1 ) ;


<s> void setSRetReturnReg ( unsigned Reg ) { SRetReturnReg = Reg ;


<s> unsigned <ISA_LIT>InstrInfo :: getMachineOutlinerMBBFlags ( MachineBasicBlock & MBB ) const { unsigned Flags = <NUM_LIT> ; if ( std :: any_of ( MBB . begin ( ) , MBB . end ( ) , [ ] ( MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) Flags |= MachineOutlinerMBBFlags :: HasCalls ;

LiveRegUnits LRU ( getRegisterInfo ( ) ) ;


<s> static const MCPhysReg GPRList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( GPRList ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR16List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR16List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ;


<s> if ( ! <ISA_LIT>ComputeAddress ( MTI . getRawDest ( ) , Dest ) || ! <ISA_LIT>ComputeAddress ( MTI . getRawSource ( ) , Src ) ) return false ; unsigned Alignment = MTI . getAlignment ( ) ; if ( <ISA_LIT>TryEmitSmallMemCpy ( Dest , Src , Len , Alignment ) ) return true ; } } if ( ! MTI . getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; if ( MTI . getSourceAddressSpace ( ) > <NUM_LIT> || MTI . getDestAddressSpace ( ) > <NUM_LIT> ) return false ; const char * IntrMemName = isa < MemCpyInst > ( I ) ? <STR_LIT> : <STR_LIT> ; return SelectCall ( & I , IntrMemName ) ; } case <STR_LIT> : { const MemSetInst & MSI = cast < MemSetInst > ( I ) ; if ( MSI . isVolatile ( ) ) return false ; if ( ! MSI . getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; if ( MSI . getDestAddressSpace ( ) > <NUM_LIT> ) return false ; return SelectCall ( & I , <STR_LIT> ) ; } case <STR_LIT> : { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) ; return true ; }


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectAddrRegImm11 ( SDValue Addr , SDValue & Base , SDValue & Offset ) const {

if ( selectAddrFrameIndex ( Addr , Base , Offset ) ) return true ;


<s> vrsqrtss_f32 ( float32_t a , float32_t b ) {


<s> DefClamp -> setImm ( <NUM_LIT> ) ; MRI -> replaceRegWith ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . eraseFromParent ( ) ;

if ( TII -> convertToThreeAddress ( * Def , nullptr , nullptr ) ) Def -> eraseFromParent ( ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & ST ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> , Align ( <NUM_LIT> ) ) , STI ( ST ) {


<s> void <ISA_LIT>LinuxAsmPrinter :: EmitStartOfAsmFile ( Module & M ) { if ( Subtarget . isELFv2ABI ( ) ) { <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer . getTargetStreamer ( ) ) ; if ( TS ) TS -> emitAbiVersion ( <NUM_LIT> ) ; } if ( Subtarget . is<ISA_LIT>64 ( ) || TM . getRelocationModel ( ) != Reloc :: PIC_ ) return AsmPrinter :: EmitStartOfAsmFile ( M ) ;

assert ( TM . getCodeModel ( ) != CodeModel :: Small && <STR_LIT> ) ;


<s> if ( ( ( NumElements == <NUM_LIT> && ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) ) || ( NumElements == <NUM_LIT> && ( ElemSize == <NUM_LIT> || ElemSize == <NUM_LIT> ) ) || ( NumElements == <NUM_LIT> && ElemSize == <NUM_LIT> ) ) && ElemSize / <NUM_LIT> <= Alignment ) return true ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ;


<s> float * f = fvf ; int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) f [ i ] = g [ i ] + h [ i ] ;

f [ <NUM_LIT> ] = g [ <NUM_LIT> ] + h [ <NUM_LIT> ] ;


<s> OperandMatchResultTy parseADDR32 ( OperandVector & Operands ) {

return parseRegister ( Operands , RegGR , <STR_LIT> , GR32Reg ) ;


<s> default : { std :: string msg ; raw_string_ostream Msg ( msg ) ; Msg << <STR_LIT> << ObjectVT . getEVTString ( ) ; llvm_report_error ( Msg . str ( ) ) ; } case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( ArgRegs [ ArgRegIdx ] , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , NULL , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } InVals . push_back ( ArgVal ) ; Chain = ArgVal . getOperand ( <NUM_LIT> ) ; } if ( isVarArg ) { SmallVector < SDValue , <NUM_LIT> - <NUM_LIT> + <NUM_LIT> > MemOps ; for ( ; ArgRegIdx != NumArgRegs ; ++ ArgRegIdx ) { VarArgsFrameIndex = MFI -> CreateFixedObject ( StackSlotSize , ArgOffset ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; SDValue ArgVal = DAG . getRegister ( ArgRegs [ ArgRegIdx ] , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Chain , dl , ArgVal , FIN , NULL , <NUM_LIT> ) ; Chain = Store . getOperand ( <NUM_LIT> ) ;


<s> unsigned Imm = MI . getOperand ( NumOperands - <NUM_LIT> ) . getImm ( ) ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( AdjustBlendMask ( Imm , ImmWidth , Is256 ? <NUM_LIT> : <NUM_LIT> ) ) validDomains |= <NUM_LIT> ; if ( ! Is256 || Subtarget . hasAVX2 ( ) ) validDomains |= <NUM_LIT> ; } return validDomains ; } ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return GetBlendDomains ( <NUM_LIT> , false ) ; }


<s> std :: vector < std :: string > max2_vtr_movh ( Bx a , Ax b , ArRn1 c , ArStep1 cs ) { return D ( <STR_LIT> , R ( a ) , R ( b ) , <STR_LIT> , <STR_LIT> , R ( a ) , MemARS ( c , cs ) ) ;


<s> if ( CC == CallingConv :: GHC || CC == CallingConv :: HiPE ) return CSR_NoRegs_RegMask ; if ( ! Is64Bit ) return CSR_32_RegMask ;

if ( CC == CallingConv :: Cold ) return CSR_MostRegs_64_RegMask ;


<s> CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ;


<s> total_frame_size = cfun -> machine -> total_size ; if ( frame_pointer_needed ) { pru_add3_frame_adjust ( stack_pointer_rtx , hard_frame_pointer_rtx , - cfun -> machine -> save_reg_size , REG_CFA_ADJUST_CFA ) ; save_offset = <NUM_LIT> ; sp_adjust = total_frame_size - cfun -> machine -> save_regs_offset ; } else if ( ! UBYTE_INT ( total_frame_size ) ) { pru_add_to_sp ( cfun -> machine -> save_regs_offset , REG_CFA_ADJUST_CFA ) ; save_offset = <NUM_LIT> ;


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : if ( ! MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) return <NUM_LIT> ; FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; case <STR_LIT> :


<s> static bool areOnlyUsersOf ( SDNode * N , ArrayRef < SDValue > ValidUsers ) { for ( SDNode :: use_iterator I = N -> use_begin ( ) , E = N -> use_end ( ) ; I != E ; ++ I ) if ( llvm :: all_of ( ValidUsers , [ & I ] ( SDValue V ) { return V . getNode ( ) != * I ; } ) ) return false ;


<s> if ( TMCID . isReturn ( ) || TMCID . isCall ( ) ) return false ; const MCInstrDesc & FMCID = prior ( FMBB . end ( ) ) -> getDesc ( ) ; if ( FMCID . isReturn ( ) || FMCID . isCall ( ) ) return false ; if ( ( NumTCycles + NumFCycles ) > <NUM_LIT> ) return false ;

return ! mayStall ( TMBB ) && ! mayStall ( FMBB ) ;


<s> static DecodeStatus decodeBDAddr64Disp12Operand ( MCInst & Inst , uint64_t Field , uint64_t Address , const MCDisassembler * Decoder ) {

return decodeBDAddr12Operand ( Inst , Field , <STR_LIT> ) ;


<s> static rtx csky_function_arg ( cumulative_args_t pcum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int reg = pcum -> reg ; machine_mode mode = arg . mode ; if ( FUNCTION_VARG_MODE_P ( mode ) && ! pcum -> is_stdarg ) { reg = pcum -> freg ; if ( reg < CSKY_NPARM_FREGS ) return gen_rtx_REG ( mode , CSKY_FIRST_VFP_REGNUM + reg ) ;


Pos = ( ( ( Pos ^ <NUM_LIT> ) + <NUM_LIT> ) ^ <NUM_LIT> ) ;


<s> for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) OW -> Write8 ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplatUimm8 ( SDValue N , SDValue & Imm ) const { llvm_unreachable ( <STR_LIT> ) ; return false ;


<s> int NumEltsPerLane = NumElts / NumLanes ; SmallVector < int , <NUM_LIT> > SrcLaneMask ( NumLanes , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > PermMask ( NumElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; int SrcLane = M / NumEltsPerLane ; int DstLane = i / NumEltsPerLane ; if ( ! isUndefOrEqual ( SrcLaneMask [ DstLane ] , SrcLane ) ) return SDValue ( ) ; SrcLaneMask [ DstLane ] = SrcLane ; PermMask [ i ] = ( DstLane * NumEltsPerLane ) + ( M % NumEltsPerLane ) ; } SmallVector < int , <NUM_LIT> > LaneMask ( NumElts , SM_SentinelUndef ) ; for ( int DstLane = <NUM_LIT> ; DstLane != NumLanes ; ++ DstLane ) { int SrcLane = SrcLaneMask [ DstLane ] ; if ( <NUM_LIT> <= SrcLane ) for ( int j = <NUM_LIT> ; j != NumEltsPerLane ; ++ j ) { LaneMask [ ( DstLane * NumEltsPerLane ) + j ] = ( SrcLane * NumEltsPerLane ) + j ; } } int NumIdentityLanes = <NUM_LIT> ; bool OnlyShuffleLowestLane = true ; for ( int i = <NUM_LIT> ; i != NumLanes ; ++ i ) {

if ( isSequentialOrUndefInRange ( PermMask , i * NumEltsPerLane , NumEltsPerLane , i * NumEltsPerLane ) ) NumIdentityLanes ++ ;


<s> void <ISA_LIT>TargetELFStreamer :: EmitAMDKernelCodeT ( const amd_kernel_code_t & Header ) { MCStreamer & OS = getStreamer ( ) ; OS . PushSection ( ) ; OS . EmitBytes ( StringRef ( ( const char * ) & Header , sizeof ( Header ) ) ) ;


<s> <ISA_LIT>TargetObjectFile & TLOF = ( <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GOT , GPRelNode ) ; } SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , & GA , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; } else { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ;

SDValue ResNode = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , GA , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , VecPred , CostKind , I ) ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( isa < FixedVectorType > ( ValTy ) && ISD == <STR_LIT> ) { const int AmortizationCost = <NUM_LIT> ; if ( VecPred == CmpInst :: BAD_ICMP_PREDICATE && I && I -> getType ( ) == ValTy ) { CmpInst :: Predicate CurrentPred ; if ( match ( I , m_Select ( m_Cmp ( CurrentPred , m_Value ( ) , m_Value ( ) ) , m_Value ( ) , m_Value ( ) ) ) ) VecPred = CurrentPred ; } if ( CmpInst :: isIntPredicate ( VecPred ) || VecPred == CmpInst :: FCMP_OLE || VecPred == CmpInst :: FCMP_OLT || VecPred == CmpInst :: FCMP_OGT || VecPred == CmpInst :: FCMP_OGE || VecPred == CmpInst :: FCMP_OEQ || VecPred == CmpInst :: FCMP_UNE ) { static const auto ValidMinMaxTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const auto ValidFP16MinMaxTys = { <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) || ( ST -> hasFullFP16 ( ) && any_of ( ValidFP16MinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) ) return LT . first ; } static const TypeConversionCostTblEntry VectorSelectTbl [ ] = {


<s> } unsigned Op0Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op0Reg == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1Reg == <NUM_LIT> ) return false ; unsigned Op2Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2Reg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) . addReg ( Op0Reg ) . addReg ( Op0Reg ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( Op1Reg ) . addReg ( Op2Reg ) ; UpdateValueMap ( I , ResultReg ) ;


<s> Module * M = At -> getParent ( ) -> getParent ( ) -> getParent ( ) ; Function * PMF = <STR_LIT> ( M , <STR_LIT> ) ; Value * P = PV . P , * Q = PV . Q , * P0 = P ; unsigned IC = PV . IterCount ; if ( PV . M != nullptr ) P0 = P = B . CreateXor ( P , PV . M ) ; auto * BMI = ConstantInt :: get ( P -> getType ( ) , APInt :: getLowBitsSet ( <NUM_LIT> , IC ) ) ; if ( PV . IterCount != <NUM_LIT> ) P = B . CreateAnd ( P , BMI ) ; if ( PV . Inv ) { auto * QI = dyn_cast < ConstantInt > ( PV . Q ) ; assert ( QI && QI -> getBitWidth ( ) <= <NUM_LIT> ) ;

unsigned M = ( <NUM_LIT> << PV . IterCount ) - <NUM_LIT> ;


<s> if ( isToken ( AsmToken :: Identifier ) && peekToken ( ) . is ( AsmToken :: LParen ) ) { while ( parseCnt ( Waitcnt ) && ! isToken ( AsmToken :: EndOfStatement ) ) ; } else {


<s> static rtx gen_compare_reg_1 ( enum rtx_code code , rtx x , rtx y ) { machine_mode mode ; rtx cc_reg ; if ( GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_CC ) return x ; mode = SELECT_CC_MODE ( code , x , y ) ; if ( TARGET_V9 && GET_MODE_CLASS ( GET_MODE ( x ) ) == MODE_FLOAT ) { int reg ; static int next_fcc_reg = <NUM_LIT> ; static rtx prev_args [ <NUM_LIT> ] [ <NUM_LIT> ] ; for ( reg = <NUM_LIT> ; reg < <NUM_LIT> ; reg ++ ) if ( prev_args [ reg ] [ <NUM_LIT> ] == x && prev_args [ reg ] [ <NUM_LIT> ] == y ) break ; if ( reg == <NUM_LIT> ) { reg = next_fcc_reg ; prev_args [ reg ] [ <NUM_LIT> ] = x ; prev_args [ reg ] [ <NUM_LIT> ] = y ; next_fcc_reg = ( next_fcc_reg + <NUM_LIT> ) & <NUM_LIT> ; } cc_reg = gen_rtx_REG ( mode , reg + SPARC_FIRST_V9_FCC_REG ) ;


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS ) , DataLayout ( <STR_LIT> ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , ELFWriterInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> Value * Ptr = I -> getArgOperand ( <NUM_LIT> ) ; unsigned Alignment = cast < ConstantInt > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; auto * Ty = cast < VectorType > ( Input -> getType ( ) ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ;

Value * Store = tryCreateMaskedScatterOffset ( I , Ptr , Builder ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = TID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI != <NUM_LIT> ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; unsigned InstSize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned NumEntries = getNumJTEntries ( JT , JTI ) ; if ( Opc == <STR_LIT> && ( NumEntries & <NUM_LIT> ) ) ++ NumEntries ; return NumEntries * EntrySize + InstSize ; }


<s> for ( const auto & MMO : MI -> memoperands ( ) ) { const auto & IsSyncScopeInclusion = MMI -> isSyncScopeInclusion ( S<ISA_LIT>D , MMO -> getSyncScopeID ( ) ) ; if ( ! IsSyncScopeInclusion ) { reportUnknownSyncScope ( MI ) ; return None ; } S<ISA_LIT>D = IsSyncScopeInclusion . getValue ( ) ? S<ISA_LIT>D : MMO -> getSyncScopeID ( ) ; Ordering = isStrongerThan ( Ordering , MMO -> getOrdering ( ) ) ? Ordering : MMO -> getOrdering ( ) ; FailureOrdering = isStrongerThan ( FailureOrdering , MMO -> getFailureOrdering ( ) ) ? FailureOrdering : MMO -> getFailureOrdering ( ) ;

if ( ! ( MMO -> getFlags ( ) & MachineMemOperand :: MONonTemporal ) ) IsNonTemporal = false ;


<s> auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; auto Subtarget = TLI . getSubtarget ( ) ; if ( Subtarget -> isThumb1Only ( ) ) return false ; if ( F . arg_empty ( ) ) return true ; if ( F . isVarArg ( ) ) return false ; auto & MF = MIRBuilder . getMF ( ) ; auto & MBB = MIRBuilder . getMBB ( ) ; auto DL = MF . getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { if ( ! isSupportedType ( DL , TLI , Arg . getType ( ) ) ) return false ; if ( Arg . hasPassPointeeByValueCopyAttr ( ) ) return false ; } CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; FormalArgHandler ArgHandler ( MIRBuilder , MIRBuilder . getMF ( ) . getRegInfo ( ) , AssignFn ) ;

SmallVector < ArgInfo , <NUM_LIT> > SplitArgInfos ;


<s> StringRef IDVal = DirectiveID . getString ( ) ;

if ( IDVal == <STR_LIT> ) return parseDirectiveAttribute ( ) ;


<s> if ( ( GA . getOpcode ( ) != <STR_LIT> ) || ( GB . getOpcode ( ) != <STR_LIT> ) ) return - <NUM_LIT> ; Register DestReg = GA . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! GB . readsRegister ( DestReg ) ) return - <NUM_LIT> ; if ( DestReg != <STR_LIT> && DestReg != <STR_LIT> ) return - <NUM_LIT> ; const MachineOperand & CmpOp = GA . getOperand ( <NUM_LIT> ) ; if ( ! CmpOp . isImm ( ) ) return - <NUM_LIT> ; int V = CmpOp . getImm ( ) ; if ( V == - <NUM_LIT> ) return DestReg == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( ! isUInt < <NUM_LIT> > ( V ) ) return - <NUM_LIT> ;


<s> else { unsigned int_offset = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( load_pair && ( code == POST_INC || code == POST_DEC ) ) int_offset *= <NUM_LIT> ; * offset = GEN_INT ( int_offset ) ; } return true ; } else if ( addr . type == ADDRESS_REG_IMM || addr . type == ADDRESS_REG_REG ) { if ( ! iv_p ( insn , addr . base , loop ) ) return false ; * base = addr . base ;


<s> Optional < int > getMaskPos ( unsigned Opc ) { auto PosOpt = <STR_LIT> ( Opc ) ; if ( PosOpt ) return * PosOpt ; if ( isVVPBinaryOp ( Opc ) ) return <NUM_LIT> ; switch ( Opc ) {


<s> else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ;

State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> return __builtin_neon_vmulfv8hf ( __a , __b ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , PTM ( tm ) , RI ( tm , * this ) , PST ( * tm . getSubtargetImpl ( ) ) {


<s> static DecodeStatus DecodeVecShiftR64Imm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { return DecodeVecShiftRImm ( Inst , Imm , <NUM_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMOV64Imm32 ( SDValue N , SDValue & Imm ) { if ( const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { uint64_t ImmVal = CN -> getZExtValue ( ) ; if ( ( uint32_t ) ImmVal != ( uint64_t ) ImmVal ) return false ; Imm = CurDAG -> getTargetConstant ( ImmVal , SDLoc ( N ) , <STR_LIT> ) ; return true ;


<s> u16 s = ( ar_arp -> ar [ a . Index ( ) / <NUM_LIT> ] >> ( <NUM_LIT> - <NUM_LIT> * ( a . Index ( ) % <NUM_LIT> ) ) ) & <NUM_LIT> ;


<s> SDValue Value = SN -> getValue ( ) ; if ( Value . getValueType ( ) == <STR_LIT> || Value . getValueType ( ) == <STR_LIT> ) { EVT MemVT = SN -> getMemoryVT ( ) ; unsigned Alignment = SN -> getAlignment ( ) ; if ( Alignment >= MemVT . getStoreSize ( ) ) return Op ; EVT ScalarVT = Value . getValueType ( ) . getScalarType ( ) , ScalarMemVT = MemVT . getScalarType ( ) ; unsigned Stride = ScalarMemVT . getStoreSize ( ) ; SDValue Stores [ <NUM_LIT> ] ; for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) { SDValue Ex = DAG . getNode ( <STR_LIT> , dl , ScalarVT , Value , DAG . getConstant ( Idx , dl , getVectorIdxTy ( DAG . getDataLayout ( ) ) ) ) ; SDValue Store ; if ( ScalarVT != ScalarMemVT ) Store = DAG . getTruncStore ( StoreChain , dl , Ex , BasePtr , SN -> getPointerInfo ( ) . getWithOffset ( Idx * Stride ) , ScalarMemVT , MinAlign ( Alignment , Idx * Stride ) , SN -> getMemOperand ( ) -> getFlags ( ) , SN -> getAAInfo ( ) ) ; else Store = DAG . getStore ( StoreChain , dl , Ex , BasePtr , SN -> getPointerInfo ( ) . getWithOffset ( Idx * Stride ) , MinAlign ( Alignment , Idx * Stride ) , SN -> getMemOperand ( ) -> getFlags ( ) , SN -> getAAInfo ( ) ) ; if ( Idx == <NUM_LIT> && SN -> isIndexed ( ) ) { assert ( SN -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; Store = DAG . getIndexedStore ( Store , dl , BasePtr , SN -> getOffset ( ) , SN -> getAddressingMode ( ) ) ; } BasePtr = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , DAG . getConstant ( Stride , dl , BasePtr . getValueType ( ) ) ) ;


<s> bool IsRightShift ; switch ( IID ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = false ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = false ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = true ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = true ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = false ; break ; } if ( IsRightShift && ShiftAmount <= - <NUM_LIT> && ShiftAmount >= - ( int ) ElemBits ) { SDLoc dl ( N ) ; return DAG . getNode ( Opcode , dl , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( - ShiftAmount , dl , <STR_LIT> ) ) ;

} else if ( ! IsRightShift && ShiftAmount >= <NUM_LIT> && ShiftAmount < ElemBits ) {


<s> bool isU3Imm ( ) const { return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ; return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( ST -> isThumb2 ( ) ) {


<s> StringRef Kind ; RegNum = tryMatchVectorRegister ( Kind , false ) ; if ( ! Kind . empty ( ) ) { Error ( SRegLoc , <STR_LIT> ) ; return false ; } IsVector = true ; } if ( RegNum == static_cast < unsigned > ( - <NUM_LIT> ) ) { Parser . eatToEndOfStatement ( ) ; Error ( SRegLoc , <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . isNot ( AsmToken :: EndOfStatement ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return false ; } Parser . Lex ( ) ; auto pair = std :: make_pair ( IsVector , RegNum ) ; if ( ! RegisterReqs . insert ( std :: make_pair ( Name , pair ) ) . second ) Warning ( L , <STR_LIT> + Name + <STR_LIT> ) ; return true ;


<s> case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; }


<s> if ( Stack . back ( ) . first != BB ) return ; if ( L && L -> getHeader ( ) == BB ) { SmallVector < BasicBlock * , <NUM_LIT> > Latches ; L -> getLoopLatches ( Latches ) ; std :: vector < BasicBlock * > Preds ; for ( pred_iterator PI = pred_begin ( BB ) , PE = pred_end ( BB ) ; PI != PE ; ++ PI ) {

if ( std :: find ( Latches . begin ( ) , Latches . end ( ) , * PI ) == Latches . end ( ) ) Preds . push_back ( * PI ) ;


<s> } const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: <ISA_LIT>_RegCall == F -> getCallingConv ( ) ) ) return <STR_LIT> ; if ( ( ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) || ( ! F && M . getRtLibUseGOT ( ) ) ) && is64Bit ( ) ) return <STR_LIT> ; if ( ! is64Bit ( ) && ! GV && TM . getRelocationModel ( ) == Reloc :: Static ) return <STR_LIT> ;


<s> for ( auto I = std :: next ( DefMI . getIterator ( ) ) ; ; ++ I ) { assert ( I != DefBB -> end ( ) ) ; if ( I -> isDebugInstr ( ) ) continue ; if ( ++ NumInst > MaxInstScan ) return true ; for ( const MachineOperand & Op : I -> operands ( ) ) { if ( ! Op . isReg ( ) ) continue ; Register Reg = Op . getReg ( ) ; if ( Op . isUse ( ) ) { if ( Reg == VReg && -- NumUse == <NUM_LIT> ) return false ;

} else if ( TRI -> regsOverlap ( Reg , <STR_LIT> ) ) return true ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createSysReg ( StringRef Str , SMLoc S , unsigned Encoding , bool IsRV64 ) { auto Op = make_unique < <ISA_LIT>Operand > ( SystemRegister ) ; Op -> SysReg . Data = Str . data ( ) ; Op -> SysReg . Length = Str . size ( ) ; Op -> SysReg . Encoding = Encoding ;


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! def_link || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_load || ! insn_entry [ uid2 ] . is_swap ) return false ; rtx body = PATTERN ( def_insn ) ; if ( GET_CODE ( body ) != SET || GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT || GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) != MEM ) return false ; rtx mem = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; rtx base_reg = XEXP ( mem , <NUM_LIT> ) ; df_ref base_use ; insn_info = DF_INSN_INFO_GET ( def_insn ) ;


return ( ( qword ) ( vec_sra ( ( vec_short8 ) ( a ) , ( vec_ushort8 ) vec_or ( neg_b , mask ) ) ) ) ;


<s> FOR_EACH_INSN_INFO_USE ( src_use , insn_info ) { if ( ! rtx_equal_p ( DF_REF_REG ( src_use ) , src_reg ) ) continue ; struct df_link * link = DF_REF_CHAIN ( src_use ) ; if ( ! link || link -> next ) break ; rtx_insn * swap_insn = DF_REF_INSN ( link -> ref ) ; if ( ! insn_is_swap_p ( swap_insn ) || insn_is_load_p ( swap_insn ) || insn_is_store_p ( swap_insn ) ) break ; to_delete [ INSN_UID ( swap_insn ) ] . replace = true ; to_delete [ INSN_UID ( swap_insn ) ] . replace_insn = swap_insn ; XEXP ( mem , <NUM_LIT> ) = and_operation ; SET_SRC ( body ) = src_reg ; INSN_CODE ( insn ) = - <NUM_LIT> ; df_insn_rescan ( insn ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( insn ) ) ;


<s> auto Target = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ;

EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const {


<s> void emit_vlmax_op ( unsigned icode , rtx dest , rtx src , rtx len , machine_mode mask_mode ) { emit_pred_op ( icode , NULL_RTX , dest , src , len , mask_mode , true ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; AttributeSet FnAttrs = MF -> getFunction ( ) -> getAttributes ( ) ; bool <ISA_LIT>16Attr = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; bool No<ISA_LIT>16Attr = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; assert ( ! ( <ISA_LIT>16Attr && No<ISA_LIT>16Attr ) && <STR_LIT> ) ;

if ( <ISA_LIT>16Attr ) Subtarget = & <ISA_LIT>16Subtarget ;


<s> if ( ! STy || ( STy -> getNumElements ( ) == <NUM_LIT> ) ) return false ; auto ElemTy = dyn_cast < VectorType > ( STy -> getElementType ( <NUM_LIT> ) ) ; if ( ! ElemTy || ! ElemTy -> isScalable ( ) ) return false ; return std :: equal ( STy -> element_begin ( ) , STy -> element_end ( ) , STy -> element_begin ( ) ) ;


<s> KnownBits Known = DAG . computeKnownBits ( Value ) ;

return Known . countMinTrailingZeros ( ) >= <NUM_LIT> ;


<s> Value * <ISA_LIT>IREmitter :: visitVEXT ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . needsStackRealignment ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ) ; } else { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB = AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; } } else llvm_unreachable ( <STR_LIT> ) ;


<s> CodeModel :: Model M = TM . getCodeModel ( ) ; if ( Subtarget -> is64Bit ( ) ) { if ( ! <STR_LIT> ( Val , M , AM . hasSymbolicDisplacement ( ) ) ) return true ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase && ! isDispSafeForFrameIndex ( Val ) ) return true ; else if ( Subtarget -> isTargetNaCl64 ( ) && ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase || AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) && ( Val > <NUM_LIT> || Val < - <NUM_LIT> ) && selectingMemOp ) return true ; } AM . Disp = Val ; return false ;


<s> virtual void initialize ( ScheduleDAGMI * dag ) {


<s> if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { const ConstantSDNode * CRHS = dyn_cast < ConstantSDNode > ( RHS ) ; if ( CRHS ) { if ( SDValue Split = splitBinaryBitConstantOp ( DCI , SDLoc ( N ) , <STR_LIT> , LHS , CRHS ) ) return Split ; } } if ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> LCC = cast < CondCodeSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; <STR_LIT> RCC = cast < CondCodeSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue X = LHS . getOperand ( <NUM_LIT> ) ; SDValue Y = RHS . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) != <STR_LIT> || Y . getOperand ( <NUM_LIT> ) != X ) return SDValue ( ) ; if ( LCC == <STR_LIT> ) { if ( X != LHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; if ( RCC == <STR_LIT> ) { const ConstantFPSDNode * C1 = dyn_cast < ConstantFPSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C1 || ! C1 -> isInfinity ( ) || C1 -> isNegative ( ) ) return SDValue ( ) ; const uint32_t Mask = <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ; static_assert ( ( ( ~ ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) & <NUM_LIT> ) == Mask , <STR_LIT> ) ;


<s> if ( ! Mode . allFP32Denormals ( ) ) toggleSPDenormMode ( true , B , ST , Mode ) ; auto Fma0 = B . buildFMA ( S32 , NegDivScale0 , ApproxRcp , One , Flags ) ; auto Fma1 = B . buildFMA ( S32 , Fma0 , ApproxRcp , ApproxRcp , Flags ) ; auto Mul = B . buildFMul ( S32 , NumeratorScaled , Fma1 , Flags ) ; auto Fma2 = B . buildFMA ( S32 , NegDivScale0 , Mul , NumeratorScaled , Flags ) ; auto Fma3 = B . buildFMA ( S32 , Fma2 , Fma1 , Mul , Flags ) ; auto Fma4 = B . buildFMA ( S32 , NegDivScale0 , Fma3 , NumeratorScaled , Flags ) ; if ( ! Mode . allFP32Denormals ( ) ) toggleSPDenormMode ( false , B , ST , Mode ) ; auto Fmas = B . buildIntrinsic ( <STR_LIT> , { S32 } , false ) . addUse ( Fma4 . getReg ( <NUM_LIT> ) ) . addUse ( Fma1 . getReg ( <NUM_LIT> ) ) . addUse ( Fma3 . getReg ( <NUM_LIT> ) ) . addUse ( NumeratorScaled . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ;

B . buildIntrinsic ( <STR_LIT> , Res , false ) . addUse ( Fmas . getReg ( <NUM_LIT> ) ) . addUse ( RHS ) . addUse ( LHS ) . setMIFlags ( Flags ) ;


<s> SDValue LHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS , Zero ) ; SDValue RHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , RHS , Zero ) ; SDValue DIVREM = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( HalfVT , HalfVT ) , LHS_Lo , RHS_Lo ) ; SDValue Res [ <NUM_LIT> ] = { DAG . getNode ( <STR_LIT> , DL , VT , DIVREM . getValue ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , VT , DIVREM . getValue ( <NUM_LIT> ) ) } ; return DAG . getMergeValues ( Res , DL ) ; } SDValue LHSign = DAG . getSelectCC ( DL , LHS , Zero , NegOne , Zero , <STR_LIT> ) ; SDValue RHSign = DAG . getSelectCC ( DL , RHS , Zero , NegOne , Zero , <STR_LIT> ) ; SDValue DSign = DAG . getNode ( <STR_LIT> , DL , VT , LHSign , RHSign ) ; SDValue RSign = LHSign ; LHS = DAG . getNode ( <STR_LIT> , DL , VT , LHS , LHSign ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , RHS , RHSign ) ; LHS = DAG . getNode ( <STR_LIT> , DL , VT , LHS , LHSign ) ; RHS = DAG . getNode ( <STR_LIT> , DL , VT , RHS , RHSign ) ; SDValue Div = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , VT ) , LHS , RHS ) ; SDValue Rem = Div . getValue ( <NUM_LIT> ) ; Div = DAG . getNode ( <STR_LIT> , DL , VT , Div , DSign ) ; Rem = DAG . getNode ( <STR_LIT> , DL , VT , Rem , RSign ) ;


<s> unsigned Rt2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Qd = ( ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qd , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && ! Subtarget . hasBWI ( ) ) return false ; if ( Subtarget . hasAVX512 ( ) && ( Subtarget . useAVX512Regs ( ) || ! VT . is512BitVector ( ) ) ) return true ; bool LShift = VT . is128BitVector ( ) || VT . is256BitVector ( ) ; bool AShift = LShift && VT != <STR_LIT> && VT != <STR_LIT> ;

return ( Opcode == <STR_LIT> ) ? AShift : LShift ;


<s> bool isThumb = TT . getArch ( ) == Triple :: thumb || TT . getArch ( ) == Triple :: thumbeb || TT . getSubArch ( ) == Triple :: <ISA_LIT>SubArch_v7m || TT . getSubArch ( ) == Triple :: <ISA_LIT>SubArch_v6m ; if ( ! M . getModuleInlineAsm ( ) . empty ( ) && isThumb ) OutStreamer . EmitAssemblerFlag ( MCAF_Code16 ) ;


<s> if ( ! Subtarget . is64Bit ( ) ) { getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 } , { p0 } ) . maxScalar ( <NUM_LIT> , s32 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { s32 , p0 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_LSHR , G_ASHR , G_SDIV } ) . legalFor ( { s8 , s16 , s32 } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) ; } setAction ( { G_BRCOND , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 } ) { setAction ( { G_ZEXT , Ty } , Legal ) ; setAction ( { G_SEXT , Ty } , Legal ) ; setAction ( { G_ANYEXT , Ty } , Legal ) ; } setAction ( { G_ANYEXT , s128 } , Legal ) ; setAction ( { G_ICMP , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { G_ICMP , <NUM_LIT> , Ty } , Legal ) ; for ( const auto & Ty : { s16 , s32 , s64 } ) { setAction ( { G_MERGE_VALUES , Ty } , Legal ) ; setAction ( { G_UNMERGE_VALUES , <NUM_LIT> , Ty } , Legal ) ; } for ( const auto & Ty : { s8 , s16 , s32 } ) { setAction ( { G_MERGE_VALUES , <NUM_LIT> , Ty } , Legal ) ; setAction ( { G_UNMERGE_VALUES , Ty } , Legal ) ; }


<s> return TSFlags & UsesMaskPolicyMask ;


<s> if ( tryInlineAsm ( N ) ) return ; break ; } case <STR_LIT> : ReplaceNode ( N , getGlobalBaseReg ( ) ) ; return ; case <STR_LIT> : case <STR_LIT> : { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) break ; SDValue DivLHS = N -> getOperand ( <NUM_LIT> ) ; SDValue DivRHS = N -> getOperand ( <NUM_LIT> ) ; SDValue TopPart ; if ( N -> getOpcode ( ) == <STR_LIT> ) { TopPart = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , DivLHS , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> return ( AuxiliaryData >> <NUM_LIT> ) & <NUM_LIT> ;


<s> RTVEC_ELT ( r , <NUM_LIT> ) = GEN_INT ( <NUM_LIT> << ( <NUM_LIT> - cr_reg [ <NUM_LIT> ] ) ) ; RTVEC_ELT ( p , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , reg , gen_rtx_UNSPEC ( SImode , r , UNSPEC_MOVESI_FROM_CR ) ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , p ) ) ; return ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> unsigned int flags = aarch64_call_properties ( d ) ; if ( flags & FLAG_RAISE_FP_EXCEPTIONS ) return true ; if ( flags & ( FLAG_READ_MEMORY | FLAG_WRITE_MEMORY ) ) return true ;


<s> for ( i = <NUM_LIT> ; i < XVECLEN ( exp , <NUM_LIT> ) ; i ++ ) s390_output_pool_entry ( XVECEXP ( exp , <NUM_LIT> , i ) , inner_mode , i == <NUM_LIT> ? align : GET_MODE_BITSIZE ( inner_mode ) ) ; } break ; default : gcc_unreachable ( ) ; }


{ MO_PAGE , <STR_LIT> } , { MO_PAGEOFF , <STR_LIT> } , { MO_G3 , <STR_LIT> } , { MO_G2 , <STR_LIT> } , { MO_G1 , <STR_LIT> } , { MO_G0 , <STR_LIT> } , { MO_HI12 , <STR_LIT> } } ;


<s> if ( ! isPairableLdStInst ( FirstLdSt ) || ! isPairableLdStInst ( SecondLdSt ) ) return false ; unsigned FirstOpc = FirstLdSt . getOpcode ( ) ; unsigned SecondOpc = SecondLdSt . getOpcode ( ) ; if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ; if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ; if ( BaseOp1 . isFI ( ) ) {

assert ( ( ! BaseOp1 . isIdenticalTo ( BaseOp2 ) || Offset1 >= Offset2 ) && <STR_LIT> ) ;


if ( KindID == <NUM_LIT> ) KindID = llvm :: getNextAvailablePluginDiagnosticKind ( ) ;


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ;

const MCExpr * Expr = MO . getExpr ( ) ;


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> if ( tmp == operands [ <NUM_LIT> ] ) return true ; operands [ <NUM_LIT> ] = tmp ; return false ; } } if ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) || input_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ; if ( CONST_INT_P ( operands [ <NUM_LIT> ] ) || GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_DOUBLE || GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_VECTOR ) { if ( alpha_split_const_mov ( mode , operands ) ) return true ; }

tmp = force_const_mem ( mode , operands [ <NUM_LIT> ] ) ;


<s> if ( auto ContentsOr = getELFFile ( ) . getSectionContentsAsArray < uint8_t > ( * * NotesOr ) ) return const_varsize_item_iterator < ELFNote > ( * ContentsOr ) ; } return const_varsize_item_iterator < ELFNote > ( ) ;


<s> SDValue PoolAddr ; PoolAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue GlobalAddr = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , PoolAddr , MachinePointerInfo :: getConstantPool ( ) , false , true , true , <NUM_LIT> ) ; if ( GN -> getOffset ( ) != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GlobalAddr , DAG . getConstant ( GN -> getOffset ( ) , PtrVT ) ) ; return GlobalAddr ; } if ( Alignment == <NUM_LIT> ) { const PointerType * GVPtrTy = cast < PointerType > ( GV -> getType ( ) ) ; if ( GVPtrTy -> getElementType ( ) -> isSized ( ) ) { Alignment = getDataLayout ( ) -> getABITypeAlignment ( GVPtrTy -> getElementType ( ) ) ; } else { Alignment = <NUM_LIT> ; } } unsigned char HiFixup , LoFixup ; bool UseGOT = getSubtarget ( ) -> GVIsIndirectSymbol ( GV , RelocM ) ; if ( UseGOT ) { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; Alignment = <NUM_LIT> ; } else { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ;


<s> const MachineOperand & MO = MI . getOperand ( OpNo ) ;

if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO ) ;


<s> if ( SaveRA ) BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( MaxCallFrameSize + <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( SetupFP ) { BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( MaxCallFrameSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( MaxCallFrameSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } }


<s> if ( ! matchHalf ( SelfR , RC , <NUM_LIT> , H2 ) || ! matchHalf ( SelfR , RC , <NUM_LIT> , H1 ) ) return false ;

if ( H1 . Reg != L1 . Reg || H1 . Sub != L1 . Sub || H1 . Low || ! L1 . Low ) return false ;


<s> return aarch64_sve_vector_inc_dec_immediate_p ( x , NULL , NULL ) ;


<s> if ( TREE_CODE ( type ) == ARRAY_TYPE && TYPE_MODE ( TREE_TYPE ( type ) ) == QImode ) { if ( align < BITS_PER_WORD ) align = BITS_PER_WORD ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register FPReg = getFPReg ( STI ) ; Register SPReg = getSPReg ( STI ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; DebugLoc DL ; if ( ! MBB . empty ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; MBBI = MBB . getFirstTerminator ( ) ; while ( MBBI != MBB . begin ( ) && std :: prev ( MBBI ) -> getFlag ( MachineInstr :: FrameDestroy ) ) -- MBBI ; } const auto & CSI = getNonLibcallCSI ( MF , MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = getStackSizeWithRVVPadding ( MF ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; uint64_t RVVStackSize = RVFI -> getRVVStackSize ( ) ; if ( RI -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } else { if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , LastFrameDestroy , DL , RVVStackSize , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = getStackSizeWithRVVPadding ( MF ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ;


<s> for ( MachineOperand & Use : MI . operands ( ) ) { if ( Use . isReg ( ) && ( ( Use . readsReg ( ) && RegDefs . count ( Use . getReg ( ) ) ) || ( Use . isDef ( ) && RegDefs . count ( Use . getReg ( ) ) ) || ( Use . isDef ( ) && Use . getReg ( ) . isPhysical ( ) && PhysRegUses . count ( Use . getReg ( ) ) ) ) ) { Insts . push_back ( & MI ) ; addDefsUsesToList ( MI , RegDefs , PhysRegUses ) ; return true ; } } return false ;


<s> case <STR_LIT> : case TargetOpcode :: COPY : if ( isPredReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { RegisterSubReg RD = MI . getOperand ( <NUM_LIT> ) ; if ( RD . R . isVirtual ( ) ) PredGPRs . insert ( RD ) ;


<s> SmallVector < BasicBlock * , <NUM_LIT> > Latches ; L -> getLoopLatches ( Latches ) ; std :: vector < BasicBlock * > Preds ; for ( pred_iterator PI = pred_begin ( BB ) , PE = pred_end ( BB ) ; PI != PE ; ++ PI ) { if ( std :: find ( Latches . begin ( ) , Latches . end ( ) , * PI ) == Latches . end ( ) ) Preds . push_back ( * PI ) ; } BB = llvm :: SplitBlockPredecessors ( BB , Preds , <STR_LIT> , nullptr , DT , LI , false ) ;


<s> const <ISA_LIT>ArchEnum & get<ISA_LIT>ArchVersion ( ) const { return <ISA_LIT>ArchVersion ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCRegisterInfo & mri , MCContext & ctx ) : <ISA_LIT>MCCodeEmitter ( mcii ) , MRI ( mri ) {


<s> void EmitThumbFunc ( MCSymbol * Func ) override {

getAssembler ( ) . setIsThumbFunc ( Func ) ;


<s> else Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemOpCallTo ( SDValue Chain , SDValue StackPtr , SDValue Arg , SDLoc dl , SelectionDAG & DAG , const CCValAssign & VA , <STR_LIT> Flags ) const { unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , dl ) ; return DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo :: getStack ( LocMemOffset ) , false , false , <NUM_LIT> ) ;


<s> for ( auto <ISA_LIT> : phiInfoElementGetSources ( Info ) ) { assert ( ( <ISA_LIT> . second != SourceMBB || SourceReg == <ISA_LIT> . first ) ) ; }

phiInfoElementGetSources ( Info ) . insert ( PHISourceT ( SourceReg , SourceMBB ) ) ;


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , DebugLoc dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , <STR_LIT> ) ; return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false , MachinePointerInfo ( <NUM_LIT> ) , MachinePointerInfo ( <NUM_LIT> ) ) ;


<s> case <STR_LIT> : if ( IsFunction ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isGlobalType ( Target ) ) return <STR_LIT> ; if ( isFunctionType ( Target ) ) return <STR_LIT> ; if ( IsFunction ) return <STR_LIT> ; if ( isEventType ( Target ) ) return <STR_LIT> ; return <STR_LIT> ; case FK_Data_4 :


<s> unsigned SrcSelect [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; unsigned CT [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Value * Offset [ <NUM_LIT> ] = {

ConstantInt :: get ( Int32Type , <NUM_LIT> ) , ConstantInt :: get ( Int32Type , <NUM_LIT> ) , ConstantInt :: get ( Int32Type , <NUM_LIT> ) } ;


<s> return false ; } Type * aType = inst -> getType ( ) ; bool isVector = aType -> isVectorTy ( ) ; if ( isVector ) { return false ; } int numEle = <NUM_LIT> ; if ( aType -> getScalarType ( ) != Type :: getInt32Ty ( inst -> getContext ( ) ) ) { return false ; } if ( isVector ) { const VectorType * VT = dyn_cast < VectorType > ( aType ) ; numEle = VT -> getNumElements ( ) ; if ( numEle > <NUM_LIT> || numEle == <NUM_LIT> ) { return false ; } } BinaryOperator * ShiftInst = dyn_cast < BinaryOperator > ( inst -> getOperand ( <NUM_LIT> ) ) ; if ( ! ShiftInst || ! ShiftInst -> isShift ( ) ) { return false ; } if ( ShiftInst -> getOpcode ( ) == Instruction :: Shl ) { return false ; } bool isSigned = ShiftInst -> isArithmeticShift ( ) ; Constant * AndMask = dyn_cast < Constant > ( inst -> getOperand ( <NUM_LIT> ) ) ; Constant * ShrVal = dyn_cast < Constant > ( ShiftInst -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndMask || ! ShrVal ) { return false ; } Constant * newMaskConst ; Constant * shiftValConst ; if ( isVector ) { std :: vector < Constant * > maskVals ; std :: vector < Constant * > shiftVals ; ConstantVector * AndMaskVec = dyn_cast < ConstantVector > ( AndMask ) ; ConstantVector * ShrValVec = dyn_cast < ConstantVector > ( ShrVal ) ; Type * scalarType = AndMaskVec -> getType ( ) -> getScalarType ( ) ; assert ( AndMaskVec -> getNumOperands ( ) == ShrValVec -> getNumOperands ( ) && <STR_LIT> <STR_LIT> <STR_LIT> ) ; for ( size_t x = <NUM_LIT> , y = AndMaskVec -> getNumOperands ( ) ; x < y ; ++ x ) { ConstantInt * AndCI = dyn_cast < ConstantInt > ( AndMaskVec -> getOperand ( x ) ) ; ConstantInt * ShiftIC = dyn_cast < ConstantInt > ( ShrValVec -> getOperand ( x ) ) ; if ( ! AndCI || ! ShiftIC ) { return false ; } uint32_t maskVal = ( uint32_t ) AndCI -> getZExtValue ( ) ; if ( ! isMask_32 ( maskVal ) ) { return false ; } maskVal = ( uint32_t ) CountTrailingOnes_32 ( maskVal ) ; uint32_t shiftVal = ( uint32_t ) ShiftIC -> getZExtValue ( ) ; if ( maskVal >= <NUM_LIT> || shiftVal >= <NUM_LIT> ) { return false ; } if ( maskVal > ( <NUM_LIT> - shiftVal ) ) {


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ; for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) {


<s> gpr_size = ( gpr_reg_num * reg_size + <NUM_LIT> ) & ~ <NUM_LIT> ; } else if ( fpr_size ) offset = - ( int ) ( next_cum . fregno - FP_ARG_MIN_REG ) * UNITS_PER_FP_WORD - ( int ) ( GP_ARG_NUM_REG * reg_size ) ; if ( gpr_size + fpr_size ) { rtx reg_save_area = assign_stack_local ( BLKmode , gpr_size + fpr_size , <NUM_LIT> ) ; gcc_assert ( MEM_P ( reg_save_area ) ) ; reg_save_area = XEXP ( reg_save_area , <NUM_LIT> ) ; if ( GET_CODE ( reg_save_area ) == PLUS ) { gcc_assert ( XEXP ( reg_save_area , <NUM_LIT> ) == virtual_stack_vars_rtx ) ; gcc_assert ( CONST_INT_P ( XEXP ( reg_save_area , <NUM_LIT> ) ) ) ; offset += INTVAL ( XEXP ( reg_save_area , <NUM_LIT> ) ) ; } else gcc_assert ( reg_save_area == virtual_stack_vars_rtx ) ; } cfun -> machine -> varargs_save_offset = offset ; save_area = plus_constant ( Pmode , virtual_stack_vars_rtx , offset ) ; } } else { first_reg_offset = next_cum . words ; save_area = crtl -> args . internal_arg_pointer ; if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) && targetm . calls . must_pass_in_stack ( arg ) ) first_reg_offset += rs6000_arg_size ( TYPE_MODE ( arg . type ) , arg . type ) ; } set = get_varargs_alias_set ( ) ; if ( ! no_rtl && first_reg_offset < GP_ARG_NUM_REG && cfun -> va_list_gpr_size ) { int n_gpr , nregs = GP_ARG_NUM_REG - first_reg_offset ; if ( va_list_gpr_counter_field ) n_gpr = cfun -> va_list_gpr_size ; else n_gpr = ( cfun -> va_list_gpr_size + reg_size - <NUM_LIT> ) / reg_size ; if ( nregs > n_gpr ) nregs = n_gpr ; mem = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , save_area , first_reg_offset * reg_size ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , set ) ; set_mem_align ( mem , BITS_PER_WORD ) ; rs6000_move_block_from_reg ( GP_ARG_MIN_REG + first_reg_offset , mem , nregs ) ; } if ( DEFAULT_ABI == ABI_V4 && TARGET_HARD_FLOAT && ! no_rtl && next_cum . fregno <= FP_ARG_V4_MAX_REG && cfun -> va_list_fpr_size ) { int fregno = next_cum . fregno , nregs ; rtx cr1 = gen_rtx_REG ( CCmode , CR1_REGNO ) ; rtx lab = gen_label_rtx ( ) ; int off = ( GP_ARG_NUM_REG * reg_size ) + ( ( fregno - FP_ARG_MIN_REG ) * UNITS_PER_FP_WORD ) ; emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_NE ( VOIDmode , cr1 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , lab ) , pc_rtx ) ) ) ; for ( nregs = <NUM_LIT> ; fregno <= FP_ARG_V4_MAX_REG && nregs < cfun -> va_list_fpr_size ; fregno ++ , off += UNITS_PER_FP_WORD , nregs ++ ) { mem = gen_rtx_MEM ( TARGET_HARD_FLOAT ? DFmode : SFmode , plus_constant ( Pmode , save_area , off ) ) ; MEM_NOTRAP_P ( mem ) = <NUM_LIT> ;


<s> if ( VT == <STR_LIT> ) return Subtarget -> hasDSP ( ) ? & <STR_LIT> : & <STR_LIT> ; return TargetLowering :: getRepRegClassFor ( VT ) ;


<s> assert ( fi < NumFIs && <STR_LIT> ) ; return fi + OffsetFIs ;


<s> MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , FrameInfo . getObjectSize ( FrameIndex ) , FrameInfo . getObjectAlign ( FrameIndex ) ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; assert ( SrcReg != <STR_LIT> && <STR_LIT> ) ; assert ( SrcReg != <STR_LIT> && SrcReg != <STR_LIT> && SrcReg != <STR_LIT> && <STR_LIT> ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( Register :: isVirtualRegister ( SrcReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getStackPtrOffsetReg ( ) , RegState :: Implicit ) ; if ( RI . spillSGPRToVGPR ( ) ) FrameInfo . setStackID ( FrameIndex , TargetStackID :: SGPRSpill ) ; return ; } unsigned Opcode = RI . hasAGPRs ( RC ) ? getAGPRSpillSaveOpcode ( SpillSize ) : getVGPRSpillSaveOpcode ( SpillSize ) ; MFI -> setHasSpilledVGPRs ( ) ; auto MIB = BuildMI ( MBB , MI , DL , get ( Opcode ) ) ; if ( RI . hasAGPRs ( RC ) ) {


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) {

if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) {


<s> <ISA_LIT>COFFMachineModuleInfo :: ~ <ISA_LIT>COFFMachineModuleInfo ( ) {


<s> return isImm ( ) && isAcceptableSymbolRef ( getImm ( ) ) ;


<s> case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; default : cpu = <STR_LIT> ; break ; } } if ( has_features == <NUM_LIT> && startswith ( buf , <STR_LIT> ) ) { const char * p ; p = strchr ( buf , ':' ) ; if ( p == NULL ) continue ; p ++ ; while ( * p != <NUM_LIT> ) { int i ; while ( ISSPACE ( * p ) ) p ++ ; for ( i = <NUM_LIT> ; ! ISSPACE ( p [ i ] ) && p [ i ] != <NUM_LIT> ; i ++ ) ; if ( i == <NUM_LIT> && startswith ( p , <STR_LIT> ) ) has_dfp = <NUM_LIT> ; else if ( i == <NUM_LIT> && startswith ( p , <STR_LIT> ) ) has_te = <NUM_LIT> ; else if ( i == <NUM_LIT> && startswith ( p , <STR_LIT> ) ) has_vx = <NUM_LIT> ; else if ( i == <NUM_LIT> && startswith ( p , <STR_LIT> ) ) has_highgprs = <NUM_LIT> ; p += i ; } has_features = <NUM_LIT> ; } }


<s> if ( prev && GET_CODE ( PATTERN ( prev ) ) == SET && MEM_P ( SET_SRC ( PATTERN ( prev ) ) ) ) { HARD_REG_SET sets ; CLEAR_HARD_REG_SET ( sets ) ; note_stores ( PATTERN ( prev ) , record_hard_reg_sets , & sets ) ; if ( ! hard_reg_set_intersect_p ( delay_sets , uses ) && hard_reg_set_intersect_p ( uses , sets ) ) { next_insn = mips_break_sequence ( insn ) ; continue ; } } if ( mips_orphaned_high_part_p ( & htab , SEQ_END ( insn ) ) ) { next_insn = mips_break_sequence ( insn ) ; continue ; } } FOR_EACH_SUBINSN ( subinsn , insn ) if ( INSN_P ( subinsn ) ) { if ( mips_orphaned_high_part_p ( & htab , subinsn ) ) { PATTERN ( subinsn ) = gen_nop ( ) ; INSN_CODE ( subinsn ) = CODE_FOR_nop ; } mips_avoid_hazard ( last_insn , subinsn , & hilo_delay , & delayed_reg , lo_reg , & fs_delay ) ; } last_insn = insn ; } else { if ( mips_orphaned_high_part_p ( & htab , insn ) ) delete_insn ( insn ) ; else if ( recog_memoized ( insn ) == CODE_FOR_r10k_cache_barrier && last_insn && JUMP_P ( SEQ_BEGIN ( last_insn ) ) && INSN_ANNULLED_BRANCH_P ( SEQ_BEGIN ( last_insn ) ) ) delete_insn ( insn ) ; else { mips_avoid_hazard ( last_insn , insn , & hilo_delay , & delayed_reg , lo_reg , & fs_delay ) ; if ( fs_delay ) { rtx_insn * next = next_active_insn ( insn ) ; if ( next && USEFUL_INSN_P ( next ) && GET_CODE ( PATTERN ( next ) ) == SEQUENCE && mips_breakable_sequence_p ( next ) ) { last_insn = insn ; next_insn = mips_break_sequence ( next ) ; continue ; } } last_insn = insn ; } } } }


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> unsigned BaseReg = Base . getReg ( ) ; unsigned IndexReg = Index . getReg ( ) ; if ( STI . hasFeature ( <STR_LIT> ) && BaseReg == <NUM_LIT> && IndexReg == <NUM_LIT> && Disp . isImm ( ) && Disp . getImm ( ) < <NUM_LIT> ) return true ; if ( ( BaseReg != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) || ( IndexReg != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) ) return true ; return false ;


<s> static StringRef get_amd_kernel_code_t_FieldName ( int index ) {

return get_amd_kernel_code_t_FldNames ( ) [ index + <NUM_LIT> ] ;


<s> static rtx c6x_function_value ( const_tree type , const_tree func ATTRIBUTE_UNUSED , bool outgoing ATTRIBUTE_UNUSED ) { if ( TARGET_BIG_ENDIAN && type && AGGREGATE_TYPE_P ( type ) ) { HOST_WIDE_INT size = int_size_in_bytes ( type ) ; if ( size > <NUM_LIT> ) { rtx reg1 = gen_rtx_REG ( SImode , REG_A4 + <NUM_LIT> ) ; rtx reg2 = gen_rtx_REG ( SImode , REG_A4 ) ; rtvec vec = gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , reg1 , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , reg2 , GEN_INT ( <NUM_LIT> ) ) ) ;

return gen_rtx_PARALLEL ( TYPE_MODE ( type ) , vec ) ;


<s> value_rtx = convert_to_mode ( Pmode , value_rtx , <NUM_LIT> ) ; emit_library_call ( wrd_memset_libfunc , LCT_NORMAL , VOIDmode , <NUM_LIT> , dst_reg , Pmode , value_rtx , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> <NUM_LIT> ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ; if ( rem == <NUM_LIT> ) return ; dst = replace_equiv_address_nv ( dst , dst_reg ) ; bytes -= rem ;

emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , convert_to_mode ( QImode , value_rtx , <NUM_LIT> ) ) ;


<s> assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Base == <NUM_LIT> ? <NUM_LIT> : Regs [ Base ] ) ) ; Inst . addOperand ( MCOperand :: createImm ( Disp ) ) ;


<s> BranchSize = BrOffset ; MaxLogAlign = std :: max ( MaxLogAlign , Src -> getLogAlignment ( ) ) ; int DestBlock = Dest -> getNumber ( ) ; BranchSize += BlockSizes [ DestBlock ] . first ; for ( unsigned i = DestBlock + <NUM_LIT> , e = Src -> getNumber ( ) ; i < e ; ++ i ) { BranchSize += BlockSizes [ i ] . first ; MaxLogAlign = std :: max ( MaxLogAlign , Fn . getBlockNumbered ( i ) -> getLogAlignment ( ) ) ; } NeedExtraAdjustment = ( FirstImpreciseBlock >= <NUM_LIT> ) && ( DestBlock >= FirstImpreciseBlock ) ; } else { unsigned StartBlock = Src -> getNumber ( ) ; BranchSize = BlockSizes [ StartBlock ] . first - BrOffset ; MaxLogAlign = std :: max ( MaxLogAlign , Dest -> getLogAlignment ( ) ) ; for ( unsigned i = StartBlock + <NUM_LIT> , e = Dest -> getNumber ( ) ; i != e ; ++ i ) { BranchSize += BlockSizes [ i ] . first ; MaxLogAlign = std :: max ( MaxLogAlign , Fn . getBlockNumbered ( i ) -> getLogAlignment ( ) ) ; } NeedExtraAdjustment = ( FirstImpreciseBlock >= <NUM_LIT> ) && ( Src -> getNumber ( ) >= FirstImpreciseBlock ) ; }

if ( NeedExtraAdjustment ) BranchSize += ( <NUM_LIT> << MaxLogAlign ) - <NUM_LIT> ;


<s> BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm ) ; } else { Register Tmp = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addDef ( Tmp ) . addUse ( StoreVal ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; BuildMI ( * BB , I , DL , TII -> get ( <STR_LIT> ) ) . addUse ( Tmp ) . addUse ( Address ) . addImm ( Imm + ( IsLittle ? <NUM_LIT> : <NUM_LIT> ) ) ; }


<s> for ( i = <NUM_LIT> ; ; i ++ ) { unsigned int test = EH_RETURN_DATA_REGNO ( i ) ; if ( test == INVALID_REGNUM ) break ; if ( test == regno ) return true ; } } if ( fixed_regs [ regno ] ) return false ; if ( regno == FRAME_POINTER_REGNUM && frame_pointer_needed ) return false ; if ( interrupt_handler ) {

if ( df_regs_ever_live_p ( regno ) ) return true ;


<s> case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : OutMO = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP ) ; return true ; case MachineOperand :: MO_JumpTableIndex : OutMO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; return true ; case MachineOperand :: MO_ConstantPoolIndex : OutMO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; return true ; case MachineOperand :: MO_BlockAddress : OutMO = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; return true ;


<s> int <ISA_LIT>TargetLowering :: getScalingFactorCost ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) return AM . Scale != <NUM_LIT> && AM . Scale != <NUM_LIT> ; return - <NUM_LIT> ;


<s> AU . addRequired < DivergenceAnalysis > ( ) ; AU . setPreservesAll ( ) ;


<s> unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SrcReg == <STR_LIT> && TargetRegisterInfo :: isVirtualRegister ( DstReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( DstReg , & <STR_LIT> ) ; return nullptr ; } if ( DstReg == <STR_LIT> && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ;

addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ;


<s> SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; for ( const SDNode * User : N -> uses ( ) ) {

if ( isI32Insn ( User , N ) ) continue ;


<s> cvtSDWA ( Inst , Operands , false ) ;


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> bool stripThreadLocals ( Module & M ) { bool Stripped = false ; for ( auto & GV : M . globals ( ) ) { if ( GV . isThreadLocal ( ) ) { Stripped = true ; GV . setThreadLocal ( false ) ;


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned NumArgs = F -> arg_size ( ) ; bool isVoidFunc = ( F -> getReturnType ( ) -> getTypeID ( ) == Type :: VoidTyID ) ; if ( isVoidFunc ) FuncInfo -> setReservedFrameCount ( NumArgs ) ; else FuncInfo -> setReservedFrameCount ( NumArgs + <NUM_LIT> ) ;


<s> const ConstantSDNode * C2Node = cast < ConstantSDNode > ( ConstNode ) ; const int64_t C1 = C1Node -> getSExtValue ( ) ; const APInt C1C2 = C1Node -> getAPIntValue ( ) * C2Node -> getAPIntValue ( ) ;

if ( ! isLegalAddImmediate ( C1 ) || isLegalAddImmediate ( C1C2 . getSExtValue ( ) ) ) return true ;


<s> int SubRegIdx [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( OrigRegSize < TargetRegSize && OrigRegSize < <NUM_LIT> ) { NewReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , SetPos , SetLoc , TII -> get ( <STR_LIT> ) , NewReg ) . addReg ( Reg ) ; if ( & SetBRC == & <STR_LIT> ) return NewReg ; Reg = NewReg ; OrigRegSize = <NUM_LIT> ; } NewReg = MRI -> createVirtualRegister ( & SetBRC ) ; if ( OrigRegSize < TargetRegSize ) { BuildMI ( MBB , SetPos , SetLoc , TII -> get ( TargetOpcode :: SUBREG_TO_REG ) , NewReg ) . addImm ( <NUM_LIT> ) . addReg ( Reg ) . addImm ( SubRegIdx [ OrigRegSize ] ) ; } else if ( OrigRegSize > TargetRegSize ) { if ( TargetRegSize == <NUM_LIT> && ! Subtarget -> is64Bit ( ) ) { MRI -> constrainRegClass ( Reg , & <STR_LIT> ) ; } BuildMI ( MBB , SetPos , SetLoc , TII -> get ( TargetOpcode :: COPY ) , NewReg ) . addReg ( Reg , <NUM_LIT> , SubRegIdx [ TargetRegSize ] ) ; } else { BuildMI ( MBB , SetPos , SetLoc , TII -> get ( TargetOpcode :: COPY ) , NewReg ) . addReg ( Reg ) ; } return NewReg ; } ; unsigned & CondReg = CondRegs [ <STR_LIT> ] ; if ( ! CondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc , <STR_LIT> ) ; unsigned ExtCondReg = AdjustReg ( CondReg ) ; Register ZeroReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , SetPos , SetLoc , TII -> get ( <STR_LIT> ) , ZeroReg ) ;


<s> if ( GET_CODE ( x ) == AND && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ( factor == <NUM_LIT> || INTVAL ( XEXP ( x , <NUM_LIT> ) ) == <NUM_LIT> * factor || INTVAL ( XEXP ( x , <NUM_LIT> ) ) == <NUM_LIT> * factor ) ) { index = XEXP ( x , <NUM_LIT> ) ; * size = ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; } else { index = x ;


<s> if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ; if ( BitWidth <= <NUM_LIT> ) return & <STR_LIT> ;


<s> if ( TARGET_DIRECT_MOVE_64BIT && ! reload_completed && ( ! SUBREG_P ( dest ) || ! sf_subreg_operand ( dest , mode ) ) && SUBREG_P ( source ) && sf_subreg_operand ( source , mode ) ) {

rtx inner_source = SUBREG_REG ( source ) ;


<s> if ( ! MI -> hasOneMemOperand ( ) ) return ; const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; unsigned AlignmentHint = <NUM_LIT> ; if ( MMO -> getAlign ( ) >= Align ( <NUM_LIT> ) ) AlignmentHint = <NUM_LIT> ; else if ( MMO -> getAlign ( ) >= Align ( <NUM_LIT> ) ) AlignmentHint = <NUM_LIT> ; if ( AlignmentHint == <NUM_LIT> ) return ; LoweredMI . setOpcode ( Opcode ) ; LoweredMI . addOperand ( MCOperand :: createImm ( AlignmentHint ) ) ;


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue MAdd = matchPMADDWD ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( SDValue MAdd = matchPMADDWD_2 ( DAG , Op0 , Op1 , SDLoc ( N ) , VT , Subtarget ) ) return MAdd ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , DAG , Subtarget , true ) ) { auto HADDBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { Op0 , Op1 } , HADDBuilder ) ; } if ( VT . isVector ( ) ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Op1 , SExt ) ; } if ( Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && TLI . isTypeLegal ( Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) {


<s> for ( unsigned i = <NUM_LIT> , e = InitList -> getNumOperands ( ) ; i != e ; ++ i ) if ( const Function * F = dyn_cast < Function > ( InitList -> getOperand ( i ) -> stripPointerCasts ( ) ) ) Result . insert ( F -> getName ( ) ) ;


<s> if ( FeatureBitSet . any ( ) && ( FeatureBitSet & FeatureBits ) . none ( ) ) return false ; return Value == Other ;


<s> dremap . target = gen_reg_rtx ( V4DImode ) ; dremap . op0 = gen_lowpart ( V4DImode , d -> op0 ) ; dremap . op1 = dremap . op0 ; dremap . one_operand_p = true ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { unsigned int cnt = <NUM_LIT> ; for ( j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) if ( ( contents [ i ] & ( <NUM_LIT> << j ) ) != <NUM_LIT> ) dremap . perm [ <NUM_LIT> * i + cnt ++ ] = j ; for ( ; cnt < <NUM_LIT> ; ++ cnt ) dremap . perm [ <NUM_LIT> * i + cnt ] = <NUM_LIT> ; } dfinal = * d ; dfinal . op0 = gen_lowpart ( dfinal . vmode , dremap . target ) ; dfinal . op1 = dfinal . op0 ; dfinal . one_operand_p = true ;

for ( i = <NUM_LIT> , j = <NUM_LIT> ; i < nelt ; ++ i ) {


<s> break ; case RTLIB :: MEMSET : BaseName = <STR_LIT> ; break ; case RTLIB :: MEMMOVE : BaseName = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } std :: string prefix = PAN :: getTagName ( PAN :: PREFIX_SYMBOL ) ;

std :: string LibCallName = prefix + BaseName ;


<s> assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> ) { unsigned TCOpcode = STI . isThumb ( ) ? ( STI . isTargetIOS ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = prior ( MBBI ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) NewMI -> addOperand ( MBBI -> getOperand ( i ) ) ; MBB . erase ( MBBI ) ; MBBI = NewMI ;


<s> int64_t Imm = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Imm == <STR_LIT> ( MI -> getOpcode ( ) ) ) return ;


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc S = getLoc ( ) ; const MCExpr * Expr ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; } if ( parseSymbolicImmVal ( Expr ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind ELFRefKind ; MCSymbolRefExpr :: VariantKind DarwinRefKind ; int64_t Addend ; if ( classifySymbolRef ( Expr , ELFRefKind , DarwinRefKind , Addend ) ) {

if ( DarwinRefKind == MCSymbolRefExpr :: VK_None && ELFRefKind == <ISA_LIT>MCExpr :: VK_INVALID ) {


<s> isTailCall = false ; switch ( CallConv ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : case CallingConv :: C : return LowerCCCCallTo ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; case CallingConv :: <ISA_LIT>_INTR :


<s> void addMemoryRegisterOffset16Operands ( MCInst & Inst , unsigned N ) {

addMemoryRegisterOffsetOperands ( Inst , N , Mem . ShiftVal == <NUM_LIT> ) ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {

return new TargetPassConfig ( * this , PM ) ;


<s> else arm_block_move_unaligned_straight ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , interleave_factor ) ; } else { if ( length > <NUM_LIT> ) arm_block_move_unaligned_loop ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , <NUM_LIT> , <NUM_LIT> ) ; else arm_block_move_unaligned_straight ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , length , <NUM_LIT> ) ;


<s> MCSection * <ISA_LIT>TargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const { assert ( false && <STR_LIT> <STR_LIT> ) ;


<s> switch ( OldOpcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> vmaxnm_f32 ( float32x2_t a , float32x2_t b ) { return ( float32x2_t ) __builtin_neon_vmaxnmv2sf ( a , b ) ;


<s> } if ( MFI . hasVarSizedObjects ( ) || MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getStackSizeSVE ( ) || MF . getSubtarget ( ) . getRegisterInfo ( ) -> hasStackRealignment ( MF ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ; FrameReg = <STR_LIT> ; return getStackOffset ( MF , MFI . getObjectOffset ( FI ) ) ;


<s> for ( unsigned i = <NUM_LIT> , e = Insts . size ( ) ; i != e ; ++ i ) JCE . emitWordBE ( Insts [ i ] ) ; sys :: Memory :: InvalidateInstructionCache ( Addr , <NUM_LIT> * Insts . size ( ) ) ; if ( ! sys :: Memory :: setRangeExecutable ( Addr , <NUM_LIT> * Insts . size ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; return Addr ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res ;


<s> <ISA_LIT>CodeEmitter ( TargetMachine & tm , JITCodeEmitter & mce ) : MachineFunctionPass ( ID ) , JTI ( nullptr ) , II ( ( const <ISA_LIT>BaseInstrInfo * ) tm . getInstrInfo ( ) ) , TD ( tm . getDataLayout ( ) ) , TM ( tm ) , MCE ( mce ) , MCPEs ( nullptr ) , MJTEs ( nullptr ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) , IsThumb ( false ) {