<s> SDValue TP = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; unsigned char TF = ( RM == Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , PtrVT , Offset , TF ) ; SDValue Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; if ( RM == Reloc :: PIC_ ) { SDValue GOT = LowerGLOBAL_OFFSET_TABLE ( Sym , DAG ) ; Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOT , Sym ) ; } SDValue LoadOffset = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Sym , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , TP , LoadOffset ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitJumpTableInfo ( ) {


<s> LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) > <NUM_LIT> ) return SDValue ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ;

<ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;


<s> rtx sfunc_symbol ( const char * name ) { rtx sym = gen_rtx_SYMBOL_REF ( Pmode , name ) ; SYMBOL_REF_FLAGS ( sym ) = SYMBOL_FLAG_FUNCTION | SYMBOL_FLAG_LOCAL ; if ( TARGET_SHORT_CALLS ) ; else if ( can_create_pseudo_p ( ) ) sym = copy_to_mode_reg ( Pmode , sym ) ;

else gcc_assert ( ! reload_in_progress || reload_completed ) ;


<s> const MachineInstr * L2 = * Entry . second . begin ( ) ; const MachineInstr * L1 = Entry . first ; if ( ! MDT -> dominates ( L2 , L1 ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * L2 << '\n' << * L1 << '\n' ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> << * L2 << '\n' << * L1 << '\n' ) ; SmallVector < const MachineInstr * , <NUM_LIT> > Args ;


<s> return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; }


<s> ExtType = <STR_LIT> ; switch ( V . getNode ( ) -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : { LoadSDNode * LoadNode = cast < LoadSDNode > ( V . getNode ( ) ) ; if ( ( LoadNode -> getMemoryVT ( ) == <STR_LIT> && width == <NUM_LIT> ) || ( LoadNode -> getMemoryVT ( ) == <STR_LIT> && width == <NUM_LIT> ) ) { ExtType = LoadNode -> getExtensionType ( ) ; return true ; } return false ; } case <STR_LIT> : { VTSDNode * TypeNode = cast < VTSDNode > ( V . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; if ( ( TypeNode -> getVT ( ) == <STR_LIT> && width == <NUM_LIT> ) || ( TypeNode -> getVT ( ) == <STR_LIT> && width == <NUM_LIT> ) ) { ExtType = <STR_LIT> ; return true ;


<s> getActionDefinitionsBuilder ( { G_ADD , G_SUB } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_UADDE , G_USUBO , G_USUBE } ) . lowerFor ( { { s32 , s1 } } ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForCartesianProduct ( { p0 , s32 } , { p0 } ) ; getActionDefinitionsBuilder ( { G_ZEXTLOAD , G_SEXTLOAD } ) . legalForTypesWithMemSize ( { { s32 , p0 , <NUM_LIT> } , { s32 , p0 , <NUM_LIT> } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_SELECT ) . legalForCartesianProduct ( { p0 , s32 } , { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( { G_AND , G_OR , G_XOR } ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UREM , G_UDIV } ) . legalFor ( { s32 } ) . minScalar ( <NUM_LIT> , s32 ) . libcallFor ( { s64 } ) ; getActionDefinitionsBuilder ( { G_SHL , G_ASHR , G_LSHR } ) . legalFor ( { s32 , s32 } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_ICMP ) . legalFor ( { { s32 , s32 } } ) . minScalar ( <NUM_LIT> , s32 ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ;

getActionDefinitionsBuilder ( G_GEP ) . legalFor ( { { p0 , s32 } } ) ;


<s> if ( isImm ( ) && ! isa < MCConstantExpr > ( getImm ( ) ) ) return true ; if ( ! isGPRMem ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . ShiftType != <STR_LIT> ) return false ; if ( Memory . OffsetRegNum ) return true ; if ( ! Memory . OffsetImm ) return true ;

int64_t Val = Memory . OffsetImm -> getValue ( ) ;


<s> unsigned toDREG ( unsigned Reg , unsigned From = <STR_LIT> ) {

MCRegisterClass const * Class = & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ;


<s> case <STR_LIT> : { if ( AllowsUnaligned ) { if ( Fast ) * Fast = Subtarget -> hasV7Ops ( ) ; return true ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || isLittleEndian ( ) ) ) { if ( Fast ) * Fast = true ; return true ; } return false ;


<s> auto * RHSC = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHSC || RHSC -> getZExtValue ( ) != <NUM_LIT> || LHS -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; <STR_LIT> NewCC = <STR_LIT> ( <STR_LIT> ( LHS -> getConstantOperandVal ( <NUM_LIT> ) ) ) ; SDLoc DL ( N ) ;

return getSETCC ( NewCC , LHS -> getOperand ( <NUM_LIT> ) , DL , DAG ) ;


<s> switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> :

KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ;


<s> if ( ( ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) || ( FlagI . getOpcode ( ) == <STR_LIT> && OI . getOpcode ( ) == <STR_LIT> ) ) && OI . getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI . getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) return true ; return false ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


return ( poly8x16_t ) __builtin_neon_vreinterpretv16qiv2di ( __a ) ;


<s> case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_CALL ; break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOT : Type = ELF :: R_<ISA_LIT>_GOT_BREL ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : Type = ELF :: R_<ISA_LIT>_TLS_GD32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TPOFF : Type = ELF :: R_<ISA_LIT>_TLS_LE32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_ABS32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTOFF : Type = ELF :: R_<ISA_LIT>_GOTOFF32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TARGET1 : Type = ELF :: R_<ISA_LIT>_TARGET1 ; break ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_CALL ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVT_ABS ; break ; case <STR_LIT> :


<s> offset += size ; if ( ACCUMULATE_OUTGOING_ARGS && ( ! current_function_is_leaf || current_function_calls_alloca ) ) { offset += current_function_outgoing_args_size ; frame -> outgoing_arguments_size = current_function_outgoing_args_size ; } else frame -> outgoing_arguments_size = <NUM_LIT> ; if ( ! current_function_is_leaf || current_function_calls_alloca ) frame -> padding2 = ( ( offset + preferred_alignment - <NUM_LIT> ) & - preferred_alignment ) - offset ; else frame -> padding2 = <NUM_LIT> ; offset += frame -> padding2 ; frame -> stack_pointer_offset = offset ; frame -> to_allocate = ( size + frame -> padding1 + frame -> padding2 + frame -> outgoing_arguments_size + frame -> va_arg_size ) ; if ( ( ! frame -> to_allocate && frame -> nregs <= <NUM_LIT> ) || ( TARGET_64BIT && frame -> to_allocate >= ( HOST_WIDE_INT ) <NUM_LIT> ) ) frame -> save_regs_using_mov = false ; if ( TARGET_RED_ZONE && current_function_sp_is_unchanging && current_function_is_leaf ) { frame -> red_zone_size = frame -> to_allocate ; if ( frame -> save_regs_using_mov ) frame -> red_zone_size += frame -> nregs * UNITS_PER_WORD ; if ( frame -> red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE ) frame -> red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE ; } else frame -> red_zone_size = <NUM_LIT> ; frame -> to_allocate -= frame -> red_zone_size ; frame -> stack_pointer_offset -= frame -> red_zone_size ; fprintf ( stderr , <STR_LIT> , frame -> nregs ) ; fprintf ( stderr , <STR_LIT> , size ) ; fprintf ( stderr , <STR_LIT> , stack_alignment_needed ) ; fprintf ( stderr , <STR_LIT> , frame -> padding1 ) ; fprintf ( stderr , <STR_LIT> , frame -> va_arg_size ) ; fprintf ( stderr , <STR_LIT> , frame -> padding2 ) ; fprintf ( stderr , <STR_LIT> , frame -> to_allocate ) ; fprintf ( stderr , <STR_LIT> , frame -> red_zone_size ) ;

fprintf ( stderr , <STR_LIT> , frame -> frame_pointer_offset ) ;


<s> Register AddOpc = isUInt < <NUM_LIT> > ( SI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * SI . getParent ( ) , SI , SI . getDebugLoc ( ) , TII -> get ( AddOpc ) , AddrReg ) . addReg ( SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( SI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( * SI . getParent ( ) , SI , SI . getDebugLoc ( ) , TII -> get ( getMappedOp ( SI . getOpcode ( ) ) ) ) . addReg ( SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( AddrReg ) . addImm ( <NUM_LIT> ) ; SI . eraseFromParent ( ) ;


<s> case EQ : case NE : case GT : case GE : case LT : case LE : case GTU : case GEU :


<s> case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX703 : AK = GK_GFX703 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX704 : AK = GK_GFX704 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX801 : AK = GK_GFX801 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX802 : AK = GK_GFX802 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX803 : AK = GK_GFX803 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX810 : AK = GK_GFX810 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX900 : AK = GK_GFX900 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX902 : AK = GK_GFX902 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX904 : AK = GK_GFX904 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX906 : AK = GK_GFX906 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX908 : AK = GK_GFX908 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX909 : AK = GK_GFX909 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1010 : AK = GK_GFX1010 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1011 : AK = GK_GFX1011 ; break ;

case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1012 : AK = GK_GFX1012 ; break ;


<s> bool VGPRDefined = true ; if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; auto MIB = BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; if ( i == <NUM_LIT> && NumSubRegs > <NUM_LIT> ) { MIB . addReg ( SuperReg , RegState :: ImplicitDefine ) ; } } } else { Register TmpVGPR = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; RS -> setRegUsed ( TmpVGPR ) ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; unsigned PerVGPR = <NUM_LIT> ; unsigned NumVGPRs = ( NumSubRegs + ( PerVGPR - <NUM_LIT> ) ) / PerVGPR ; int64_t VGPRLanes = ( <NUM_LIT> << std :: min ( PerVGPR , NumSubRegs ) ) - <NUM_LIT> ; for ( unsigned Offset = <NUM_LIT> ; Offset < NumVGPRs ; ++ Offset ) { unsigned TmpVGPRFlags = RegState :: Undef ; for ( unsigned i = Offset * PerVGPR , e = std :: min ( ( Offset + <NUM_LIT> ) * PerVGPR , NumSubRegs ) ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; MachineInstrBuilder WriteLane = BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , TmpVGPR ) . addReg ( SubReg , SubKillState ) . addImm ( i % PerVGPR ) . addReg ( TmpVGPR , TmpVGPRFlags ) ; TmpVGPRFlags = <NUM_LIT> ; if ( NumSubRegs > <NUM_LIT> ) { unsigned SuperKillState = <NUM_LIT> ; if ( i + <NUM_LIT> == NumSubRegs ) SuperKillState |= getKillRegState ( IsKill ) ; WriteLane . addReg ( SuperReg , RegState :: Implicit | SuperKillState ) ; } } buildSGPRSpillLoadStore ( MI , Index , Offset , EltSize , TmpVGPR , VGPRLanes , RS , false ) ; }


<s> if ( isScaledConstantInRange ( N , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Val ) ) { if ( AddSub == <STR_LIT> ) Val *= - <NUM_LIT> ; Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; Opc = CurDAG -> getTargetConstant ( Val , SDLoc ( Op ) , <STR_LIT> ) ;


<s> void addMOVZMovAliasOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> range = INTVAL ( op ) ; if ( ! IN_RANGE ( range , - <NUM_LIT> , <NUM_LIT> ) ) return false ; return ( range % <NUM_LIT> ) == <NUM_LIT> ; } case PRE_INC : case POST_INC : case PRE_DEC : case POST_DEC : return REG_P ( XEXP ( op , <NUM_LIT> ) ) ; default :


<s> unsigned getParamSize ( unsigned Param ) const {

return DL -> getTypeStoreSize ( getParamType ( Param ) ) ;


<s> unsigned i , elt ; rtx t0 , t1 ; if ( ! ( TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI ) ) return false ; if ( d -> vmode != V8QImode ) return false ; if ( ! d -> one_vector_p ) return false ; elt = d -> perm [ <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( d -> perm [ i ] != elt ) return false ; if ( d -> testing_p ) return true ; t0 = gen_reg_rtx ( V8QImode ) ; if ( elt < <NUM_LIT> ) emit_insn ( gen_loongson_punpcklbh ( t0 , d -> op0 , d -> op0 ) ) ; else emit_insn ( gen_loongson_punpckhbh ( t0 , d -> op0 , d -> op0 ) ) ; elt &= <NUM_LIT> ; elt *= <NUM_LIT> ; t1 = gen_reg_rtx ( V4HImode ) ; emit_insn ( gen_loongson_pshufh ( t1 , gen_lowpart ( V4HImode , t0 ) , force_reg ( SImode , GEN_INT ( elt ) ) ) ) ; emit_move_insn ( d -> target , gen_lowpart ( V8QImode , t1 ) ) ;


<s> VectorComponents = <NUM_LIT> ; } else if ( ( AMDGPU :: R600_Reg64RegClass . contains ( DestReg ) || AMDGPU :: R600_Reg64VerticalRegClass . contains ( DestReg ) ) && ( AMDGPU :: R600_Reg64RegClass . contains ( SrcReg ) || AMDGPU :: R600_Reg64VerticalRegClass . contains ( SrcReg ) ) ) { VectorComponents = <NUM_LIT> ; } if ( VectorComponents > <NUM_LIT> ) { for ( unsigned I = <NUM_LIT> ; I < VectorComponents ; I ++ ) { unsigned SubRegIndex = RI . getSubRegFromChannel ( I ) ; buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , RI . getSubReg ( DestReg , SubRegIndex ) , RI . getSubReg ( SrcReg , SubRegIndex ) ) . addReg ( DestReg , RegState :: Define | RegState :: Implicit ) ; } } else { MachineInstr * NewMI = buildDefaultInstruction ( MBB , MI , AMDGPU :: MOV , DestReg , SrcReg ) ; NewMI -> getOperand ( getOperandIdx ( * NewMI , AMDGPU :: OpName :: src0 ) ) . setIsKill ( KillSrc ) ; }


<s> } else { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isUInt < <NUM_LIT> > ( CN -> getZExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } } } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> case E_SFmode : return <NUM_LIT> ; case E_DFmode : return <NUM_LIT> ; case E_XFmode : return <NUM_LIT> ; case E_TImode : return SPEC_MODE_INVALID ; default : return SPEC_MODE_INVALID ; }


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_clwb ( void * __A ) {


<s> switch ( VT . getVectorNumElements ( ) ) { default : return EVT ( ) ; case <NUM_LIT> : return VT . changeVectorElementType ( <STR_LIT> ) ; case <NUM_LIT> : return VT . changeVectorElementType ( <STR_LIT> ) ;


<s> bool isKrait ( ) const { return <ISA_LIT>ProcFamily == Krait ;


<s> static SDValue widenSubVector ( SDValue Vec , bool ZeroNewElements , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG , const SDLoc & dl , unsigned WideSizeInBits ) { assert ( Vec . getValueSizeInBits ( ) < WideSizeInBits && ( WideSizeInBits % Vec . getScalarValueSizeInBits ( ) ) == <NUM_LIT> && <STR_LIT> ) ; unsigned WideNumElts = WideSizeInBits / Vec . getScalarValueSizeInBits ( ) ; MVT SVT = Vec . getSimpleValueType ( ) . getScalarType ( ) ; MVT VT = <STR_LIT> ( SVT , WideNumElts ) ;

return widenSubVector ( VT , Vec , ZeroNewElements , Subtarget , DAG , dl ) ;


<s> flag_omit_frame_pointer = <NUM_LIT> ; flag_no_function_cse = <NUM_LIT> ; flag_split_wide_types = <NUM_LIT> ; init_machine_status = rl78_init_machine_status ; if ( TARGET_ALLREGS ) { int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) fixed_regs [ i ] = <NUM_LIT> ; } if ( TARGET_ES0 && strcmp ( lang_hooks . name , <STR_LIT> ) && strcmp ( lang_hooks . name , <STR_LIT> ) && strcmp ( lang_hooks . name , <STR_LIT> ) && strcmp ( lang_hooks . name , <STR_LIT> ) && strcmp ( lang_hooks . name , <STR_LIT> ) ) error ( <STR_LIT> ) ; switch ( rl78_cpu_type ) { case CPU_UNINIT : rl78_cpu_type = CPU_G14 ; if ( rl78_mul_type == MUL_UNINIT ) rl78_mul_type = MUL_NONE ; break ; case CPU_G10 : switch ( rl78_mul_type ) { case MUL_UNINIT : rl78_mul_type = MUL_NONE ; break ; case MUL_NONE : break ; case MUL_G13 : error ( <STR_LIT> ) ; break ; case MUL_G14 : error ( <STR_LIT> ) ; break ; }


<s> unsigned int elbytes = GET_MODE_SIZE ( elmode ) ; poly_uint64 nunits = exact_div ( BYTES_PER_SVE_VECTOR , elbytes ) ; machine_mode mode = aarch64_sve_data_mode ( elmode , nunits ) . require ( ) ; vectype = build_vector_type_for_mode ( eltype , mode ) ; gcc_assert ( VECTOR_MODE_P ( TYPE_MODE ( vectype ) ) && TYPE_MODE ( vectype ) == mode && TYPE_MODE_RAW ( vectype ) == mode && TYPE_ALIGN ( vectype ) == <NUM_LIT> && known_eq ( wi :: to_poly_offset ( TYPE_SIZE ( vectype ) ) , BITS_PER_SVE_VECTOR ) ) ; num_zr = <NUM_LIT> ;


<s> void <ISA_LIT>CompilationCallback ( ) { llvm_unreachable ( <STR_LIT> ) ;


<s> void <ISA_LIT>AsmPrinter :: printFPConstant ( const ConstantFP * Fp , raw_ostream & O ) { APFloat APF = APFloat ( Fp -> getValueAPF ( ) ) ; bool ignored ; unsigned int numHex ; const char * lead ; if ( Fp -> getType ( ) -> getTypeID ( ) == Type :: FloatTyID ) { numHex = <NUM_LIT> ; lead = <STR_LIT> ; APF . convert ( APFloat :: IEEEsingle ( ) , APFloat :: rmNearestTiesToEven , & ignored ) ; } else if ( Fp -> getType ( ) -> getTypeID ( ) == Type :: DoubleTyID ) { numHex = <NUM_LIT> ; lead = <STR_LIT> ; APF . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmNearestTiesToEven , & ignored ) ; } else llvm_unreachable ( <STR_LIT> ) ; APInt API = APF . bitcastToAPInt ( ) ; std :: string hexstr ( utohexstr ( API . getZExtValue ( ) ) ) ; O << lead ; if ( hexstr . length ( ) < numHex ) O << std :: string ( numHex - hexstr . length ( ) , '0' ) ; O << utohexstr ( API . getZExtValue ( ) ) ;


<s> unsigned char ix86_memtag_tag_size ( ) { return IX86_HWASAN_TAG_SIZE ;


<s> LowerBRCOND ( SDValue Op , SelectionDAG & DAG ) const { return Op ;


<s> int imm = Val & <NUM_LIT> ; if ( Val == <NUM_LIT> ) imm = INT32_MIN ; else if ( ! ( Val & <NUM_LIT> ) ) imm *= - <NUM_LIT> ;

Inst . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> for ( auto BB = L -> block_begin ( ) , BE = L -> block_end ( ) ; BB != BE ; ++ BB ) if ( ! VisitedBlocks . count ( * BB ) ) Worklist . push_back ( * BB ) ; if ( auto PreHeader = L -> getLoopPreheader ( ) ) if ( ! VisitedBlocks . count ( PreHeader ) ) Worklist . push_back ( PreHeader ) ; while ( ! Worklist . empty ( ) ) { auto BB = Worklist . pop_back_val ( ) ; LoopOptimized |= Optimize_PreWhileConversion ( BB ) ; LoopOptimized |= Optimize_PostWhileConversion ( BB ) ; LoopOptimized |= Transform_StructAddressing ( BB ) ; VisitedBlocks . insert ( BB ) ; }


<s> <ISA_LIT>MCInst Nop ; StringRef NoAnnot ; Nop . setOpcode ( <STR_LIT> ) ; Nop . setPacketStart ( MI -> isPacketStart ( ) ) ; printInst ( & Nop , O , NoAnnot ) ; } if ( MI -> isPacketEnd ( ) ) O << PacketPadding << endPacket ; printInstruction ( MI , O ) ;


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & TMBB , unsigned NumTCycles , unsigned ExtraTCycles , MachineBasicBlock & FMBB , unsigned NumFCycles , unsigned ExtraFCycles , BranchProbability Probability ) const {

return nonDbgBBSize ( & TMBB ) <= <NUM_LIT> && nonDbgBBSize ( & FMBB ) <= <NUM_LIT> ;


<s> <ISA_LIT>ELFStreamer ( const Triple & T , MCContext & Context , std :: unique_ptr < MCAsmBackend > MAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > Emitter ) : MCELFStreamer ( Context , std :: move ( MAB ) , OS , std :: move ( Emitter ) ) {


<s> if ( ! HeadTail . second . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( String . substr ( HeadTail . first . size ( ) , <NUM_LIT> ) , Loc ) ) ; String = HeadTail . second ; } while ( ! String . empty ( ) ) ;


<s> EVT VT = Op . getValueType ( ) ; EVT MaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ;


<s> Emitter ( TargetMachine & tm , CodeEmitter & mce , const <ISA_LIT>InstrInfo & ii , const TargetData & td ) : MachineFunctionPass ( & ID ) , JTI ( <NUM_LIT> ) , II ( & ii ) , TD ( & td ) , TM ( tm ) , MCE ( mce ) , MCPEs ( <NUM_LIT> ) , MJTEs ( <NUM_LIT> ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) {


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateIndReg ( unsigned RegNum , SMLoc S , SMLoc E ) {

return make_unique < <ISA_LIT>Operand > ( k_IndReg , RegNum , S , E ) ;


<s> if ( direction == MEM_ACCESS_DIR_NEG ) n = - <NUM_LIT> * n - <NUM_LIT> ; } if ( n < - <NUM_LIT> || n > <NUM_LIT> ) return NULL_RTX ; if ( n < <NUM_LIT> ) n = <NUM_LIT> + n ; switch ( get_attr_type ( insn ) ) { case TYPE_LOAD : reg = SET_DEST ( PATTERN ( insn ) ) ; break ; case TYPE_STORE : reg = SET_SRC ( PATTERN ( insn ) ) ; break ; default : gcc_unreachable ( ) ; }

gcc_assert ( REG_P ( reg ) || GET_CODE ( reg ) == SUBREG ) ;


<s> MachineInstr * Xor = nullptr ; if ( ! SimpleIf ) { Xor = BuildMI ( MBB , I , DL , TII -> get ( XorOpc ) , SaveExecReg ) . addReg ( Tmp ) . addReg ( CopyReg ) ; setImpSCCDefDead ( * Xor , ImpDefSCC . isDead ( ) ) ; } MachineInstr * SetExec = BuildMI ( MBB , I , DL , TII -> get ( MovTermOpc ) , Exec ) . addReg ( Tmp , RegState :: Kill ) ; MachineInstr * NewBr = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! LIS ) { MI . eraseFromParent ( ) ; return ; } LIS -> InsertMachineInstrInMaps ( * CopyExec ) ; LIS -> ReplaceMachineInstrInMaps ( MI , * And ) ; if ( ! SimpleIf ) LIS -> InsertMachineInstrInMaps ( * Xor ) ; LIS -> InsertMachineInstrInMaps ( * SetExec ) ; LIS -> InsertMachineInstrInMaps ( * NewBr ) ; LIS -> removeAllRegUnitsForPhysReg ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; LIS -> removeInterval ( SaveExecReg ) ; LIS -> createAndComputeVirtRegInterval ( SaveExecReg ) ;

LIS -> createAndComputeVirtRegInterval ( Tmp ) ;


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const CmpInst :: Predicate Pred = minMaxToCompare ( MI . getOpcode ( ) ) ; MachineInstr * Sel = buildExpandedScalarMinMax ( B , Pred , Dst , Src0 , Src1 ) ;

Register CmpReg = Sel -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & Inst , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {


<s> <ISA_LIT>elTargetMachine :: <ISA_LIT>elTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> } ScheduledSUnits = Best . SUs ; ScheduledSUnitsInv . resize ( SUnits . size ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ( unsigned ) SUnits . size ( ) ; i != e ; ++ i ) { ScheduledSUnitsInv [ ScheduledSUnits [ i ] ] = i ; } moveLowLatencies ( ) ; assert ( TopRPTracker . getPos ( ) == RegionBegin && <STR_LIT> ) ; TopRPTracker . setPos ( CurrentTop ) ; for ( std :: vector < unsigned > :: iterator I = ScheduledSUnits . begin ( ) , E = ScheduledSUnits . end ( ) ; I != E ; ++ I ) { SUnit * SU = & SUnits [ * I ] ; scheduleMI ( SU , true ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SU -> NodeNum << <STR_LIT> << * SU -> getInstr ( ) ) ; } assert ( CurrentTop == CurrentBottom && <STR_LIT> ) ; placeDebugValues ( ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> << printMBBReference ( * begin ( ) -> getParent ( ) ) << <STR_LIT> ; dumpSchedule ( ) ;


<s> static DecodeStatus DecodeFPR8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = FPR8DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> unsigned <ISA_LIT>TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) {

return BaseT :: getIntrinsicInstrCost ( ICA , CostKind ) ;


<s> machine_mode cmp_mode ; bool maskcmp = false ; rtx x ; if ( GET_MODE_SIZE ( cmp_ops_mode ) == <NUM_LIT> ) { cmp_mode = mode_for_size ( GET_MODE_NUNITS ( cmp_ops_mode ) , MODE_INT , <NUM_LIT> ) ; gcc_assert ( cmp_mode != BLKmode ) ; maskcmp = true ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; if ( ! nonimmediate_operand ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp && ( code == GT || code == EQ ) ) { rtx ( * gen ) ( rtx , rtx , rtx ) ; switch ( cmp_ops_mode ) { case V64QImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv64qi3 : gen_avx512bw_eqv64qi3_1 ; break ; case V32HImode : gcc_assert ( TARGET_AVX512BW ) ; gen = code == GT ? gen_avx512bw_gtv32hi3 : gen_avx512bw_eqv32hi3_1 ; break ; case V16SImode : gen = code == GT ? gen_avx512f_gtv16si3 : gen_avx512f_eqv16si3_1 ; break ; case V8DImode : gen = code == GT ? gen_avx512f_gtv8di3 : gen_avx512f_eqv8di3_1 ; break ; default : gen = NULL ; } if ( gen ) { emit_insn ( gen ( dest , cmp_op0 , cmp_op1 ) ) ; return dest ; } }

x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ;


<s> ldi :: fixup ( Size , Fixup , Value , Ctx ) ;


<s> unsigned NumElem = SrcVTy -> getNumElements ( ) ; auto * MaskTy = FixedVectorType :: get ( Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , NumElem ) ; if ( ( IsLoad && ! isLegalMaskedLoad ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ( IsStore && ! isLegalMaskedStore ( SrcVTy , MaybeAlign ( Alignment ) ) ) || ! isPowerOf2_32 ( NumElem ) ) { APInt DemandedElts = APInt :: getAllOnesValue ( NumElem ) ; int MaskSplitCost = getScalarizationOverhead ( MaskTy , DemandedElts , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt8Ty ( SrcVTy -> getContext ( ) ) , nullptr , CostKind ) ; int BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; int MaskCmpCost = NumElem * ( BranchCost + ScalarCompareCost ) ; int ValueSplitCost = getScalarizationOverhead ( SrcVTy , DemandedElts , IsLoad , IsStore ) ;

int MemopCost = NumElem * BaseT :: getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ;


<s> void <ISA_LIT>InstPrinter :: printVectorListFour ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> write64 ( <NUM_LIT> ) ;


<s> const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return false ; const auto * FII = llvm :: find_if ( FixedCSRFIMap , [ & ] ( auto P ) { return P . first == Reg ; } ) ; if ( FII == std :: end ( FixedCSRFIMap ) ) return false ; FrameIdx = FII -> second ; return true ;


<s> return RI . isSGPRClass ( DstRC ) ? <STR_LIT> : <STR_LIT> ; } else if ( DstRC -> getSize ( ) == <NUM_LIT> && RI . isSGPRClass ( DstRC ) ) { return <STR_LIT> ; } else if ( DstRC -> getSize ( ) == <NUM_LIT> && ! RI . isSGPRClass ( DstRC ) ) { return <STR_LIT> ;


<s> if ( loop_depth > <NUM_LIT> || ! entered_at_top ) return false ; if ( arc_lpcwidth != <NUM_LIT> && ( wi :: gtu_p ( iterations_max , ( ( <NUM_LIT> << arc_lpcwidth ) - <NUM_LIT> ) ) || wi :: eq_p ( iterations_max , <NUM_LIT> ) ) ) return false ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getUserCost ( const User * U , ArrayRef < const Value * > Operands , TTI :: TargetCostKind CostKind ) { if ( isa < CastInst > ( U ) || isa < LoadInst > ( U ) || isa < StoreInst > ( U ) ) return BaseT :: getUserCost ( U , Operands , CostKind ) ; if ( U -> getType ( ) -> isVectorTy ( ) ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , U -> getType ( ) ) ;

return LT . first * BaseT :: getUserCost ( U , Operands , CostKind ) ;


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , PCRelFlagVal } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;

return Infos [ Kind - FirstTargetFixupKind ] ;


<s> errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( nullptr ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgIn = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; CFRegNode . push_back ( ArgIn . getValue ( ArgIn -> getNumValues ( ) - <NUM_LIT> ) ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > StackSlotSize ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , LRSaveSize + VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; ArgIn = DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } const ArgDataPair ADP = { ArgIn , Ins [ i ] . Flags } ; ArgData . push_back ( ADP ) ; } if ( isVarArg ) { static const MCPhysReg ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FirstVAReg = CCInfo . getFirstUnallocated ( ArgRegs , array_lengthof ( ArgRegs ) ) ; if ( FirstVAReg < array_lengthof ( ArgRegs ) ) { int offset = <NUM_LIT> ; for ( int i = array_lengthof ( ArgRegs ) - <NUM_LIT> ; i >= ( int ) FirstVAReg ; -- i ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , offset , true ) ; if ( i == ( int ) FirstVAReg ) { XFI -> setVarArgsFrameIndex ( FI ) ; } offset -= StackSlotSize ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; CFRegNode . push_back ( Val . getValue ( Val -> getNumValues ( ) - <NUM_LIT> ) ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOps . push_back ( Store ) ; } } else { XFI -> setVarArgsFrameIndex ( MFI -> CreateFixedObject ( <NUM_LIT> , LRSaveSize + CCInfo . getNextStackOffset ( ) , true ) ) ;


<s> cfun -> machine -> callee_saved_reg_size = <NUM_LIT> ;

for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ! call_used_or_fixed_reg_p ( regno ) ) cfun -> machine -> callee_saved_reg_size += <NUM_LIT> ;


<s> static SDValue LowerXALUO ( SDValue Op , SelectionDAG & DAG ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) ) return SDValue ( ) ; <STR_LIT> CC ; SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( CC , Op , DAG ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;

SDValue FVal = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) -> supportSwiftError ( ) && MF -> getFunction ( ) . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return CSR_<ISA_LIT>_AAPCS_SwiftError_SaveList ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: PreserveMost ) return CSR_<ISA_LIT>_RT_MostRegs_SaveList ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) return CSR_Darwin_<ISA_LIT>_AAPCS_SaveList ;


<s> SDLoc DL ( N ) ; SDValue X = N0 . getOperand ( <NUM_LIT> ) ; if ( DAG . MaskedValueIsZero ( X , APInt :: getBitsSetFrom ( VT . getSizeInBits ( ) , <NUM_LIT> ) ) ) { X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Setnp = getSETCC ( <STR_LIT> , Flags , DL , DAG ) ; return DAG . getZExtOrTrunc ( Setnp , DL , N -> getValueType ( <NUM_LIT> ) ) ; } if ( VT == <STR_LIT> ) { SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) ; X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; SDValue Parity = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getZExtOrTrunc ( Parity , DL , N -> getValueType ( <NUM_LIT> ) ) ; } assert ( VT == <STR_LIT> && <STR_LIT> ) ;

SDValue Hi16 = DAG . getNode ( <STR_LIT> , DL , VT , X , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> static int arm_arg_partial_bytes ( cumulative_args_t pcum_v , machine_mode mode , tree type , bool named ) { CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; int nregs = pcum -> nregs ; if ( pcum -> pcs_variant <= ARM_PCS_AAPCS_LOCAL ) { aapcs_layout_arg ( pcum , mode , type , named ) ; return pcum -> aapcs_partial ; } if ( TARGET_IWMMXT_ABI && arm_vector_mode_supported_p ( mode ) ) return <NUM_LIT> ; if ( NUM_ARG_REGS > nregs && ( NUM_ARG_REGS < nregs + ARM_NUM_REGS2 ( mode , type ) ) && pcum -> can_split ) return ( NUM_ARG_REGS - nregs ) * UNITS_PER_WORD ; return <NUM_LIT> ;


<s> const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; if ( TM -> getRelocationModel ( ) != Reloc :: PIC_ ) return false ; LLVMContext * Context = & MF . getFunction ( ) -> getContext ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * Context , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; unsigned Align = TM -> getDataLayout ( ) -> getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF . getConstantPool ( ) -> getConstantPoolIndex ( CPV , Align ) ; MachineBasicBlock & FirstMBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; DebugLoc DL = FirstMBB . findDebugLoc ( MBBI ) ; unsigned GlobalBaseReg = AFI -> getGlobalBaseReg ( ) ; unsigned Opc = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ? <STR_LIT> : <STR_LIT> ; const TargetInstrInfo & TII = * TM -> getInstrInfo ( ) ; MachineInstrBuilder MIB = BuildMI ( FirstMBB , MBBI , DL , TII . get ( Opc ) , GlobalBaseReg ) . addConstantPoolIndex ( Idx ) ; if ( Opc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; return true ;


<s> <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) for ( std :: map < const char * , const llvm :: <STR_LIT> * > :: const_iterator it = <ISA_LIT>FI -> StubsNeeded . begin ( ) ; it != <ISA_LIT>FI -> StubsNeeded . end ( ) ; ++ it ) { const char * Symbol = it -> first ; const llvm :: <STR_LIT> * Signature = it -> second ;

if ( StubsNeeded . find ( Symbol ) == StubsNeeded . end ( ) ) StubsNeeded [ Symbol ] = Signature ;


<s> bool SPScope :: isHeader ( const PredicatedBlock * block ) const { return getHeader ( ) == block ;


<s> unsigned char code ; code = * dp ++ ; decoder = unw_decode_table [ inside_body ] [ code >> <NUM_LIT> ] ; dp = ( * decoder ) ( dp , code , arg ) ;


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const DataLayout & DL ) : TargetSelectionDAGInfo ( & DL ) {


<s> xops [ <NUM_LIT> ] = GEN_INT ( PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; output_asm_insn ( <STR_LIT> , xops ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , loop_lab ) ; fputc ( '\n' , asm_out_file ) ; return <STR_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerShiftRightParts ( SDValue Op , SelectionDAG & DAG , bool IsSRA ) const { DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) , Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; SDValue Not = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( - <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftLeft1Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeft1Hi , Not ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Shamt ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftRightHi = DAG . getNode ( IsSRA ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , Hi , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Shift31 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftRightHi , Or ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , IsSRA ? Shift31 : DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftRightHi ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , <NUM_LIT> , DL ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ;


<s> return ( MI . getOpcode ( ) == <STR_LIT> ) ;


<s> if ( TT . isOSBinFormatMachO ( ) ) return new <ISA_LIT>_MachoTargetObjectFile ( ) ; return new <ISA_LIT>_ELFTargetObjectFile ( ) ;


<s> if ( MO . isReg ( ) ) { printRegName ( O , MO . getReg ( ) ) ; } else if ( MO . isExpr ( ) ) { O << * MO . getExpr ( ) ; } else if ( MO . isImm ( ) ) { printImmOperand ( MI , OpNo , O ) ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> bool RHSTrunc = N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ; if ( ! RHSTrunc && ! <STR_LIT> ( N1 . getNode ( ) ) ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Narrow -> getOpcode ( ) , VT ) ) return SDValue ( ) ; N0 = N0 -> getOperand ( <NUM_LIT> ) ; if ( RHSTrunc ) N1 = N1 -> getOperand ( <NUM_LIT> ) ; else N1 = DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ; SDValue Op = DAG . getNode ( Narrow -> getOpcode ( ) , DL , VT , N0 , N1 ) ;


<s> SDLoc DL ( N ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; unsigned Opcode = N -> getOpcode ( ) ; bool ConsumeCarry = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; bool ProduceCarry = ConsumeCarry || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool IsAdd = Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * Lo0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub0 ) ; SDNode * Hi0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub1 ) ; SDNode * Lo1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub0 ) ; SDNode * Hi1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub1 ) ; SDVTList VTList = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; static const unsigned OpcMap [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ; unsigned Opc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ;

unsigned CarryOpc = OpcMap [ <NUM_LIT> ] [ N -> isDivergent ( ) ] [ IsAdd ] ;


<s> bool isSurface ( const Value & val ) { if ( const GlobalValue * gv = dyn_cast < GlobalValue > ( & val ) ) { unsigned annot ;

if ( findOneNVVMAnnotation ( gv , <STR_LIT> , annot ) ) {


<s> cfun -> machine -> callee_saved_reg_size = <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( df_regs_ever_live_p ( regno ) && ( ! call_used_regs [ regno ] ) ) cfun -> machine -> callee_saved_reg_size += <NUM_LIT> ;

cfun -> machine -> size_for_adjusting_sp = crtl -> args . pretend_args_size + cfun -> machine -> local_vars_size + ( ACCUMULATE_OUTGOING_ARGS ? crtl -> outgoing_args_size : <NUM_LIT> ) ;


<s> if ( CPU . empty ( ) ) CPU = <STR_LIT> ;

return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ;


<s> switch ( Mode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> DEBUG ( { NodeAddr < StmtNode * > ReachingIA = RDN . Addr -> getOwner ( * DFG ) ; dbgs ( ) << <STR_LIT> << Print < NodeAddr < InstrNode * >> ( ReachingIA , * DFG ) << <STR_LIT> ; } ) ; NodeId ReachedID = RDN . Addr -> getReachedDef ( ) ; if ( ! ReachedID ) return ReachedDefMI ; NodeAddr < DefNode * > ReachedDN = DFG -> addr < DefNode * > ( ReachedID ) ;

NodeAddr < StmtNode * > ReachedIA = ReachedDN . Addr -> getOwner ( * DFG ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) {

if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> break ; case llvm :: ELF :: R_HEX_12_X : bitMask = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_32_6_X : bitMask = <NUM_LIT> ; shift = <NUM_LIT> ; effectiveBits = <NUM_LIT> ; break ; case llvm :: ELF :: R_HEX_16_X : case llvm :: ELF :: R_HEX_11_X : case llvm :: ELF :: R_HEX_10_X : case llvm :: ELF :: R_HEX_9_X : case llvm :: ELF :: R_HEX_8_X : case llvm :: ELF :: R_HEX_7_X : case llvm :: ELF :: R_HEX_6_X : bitMask = FINDBITMASK ( pReloc . target ( ) ) ; break ; default : fatal ( diag :: unsupported_relocation ) << static_cast < int > ( pReloc . type ( ) ) << <STR_LIT> ; } if ( ( shift != <NUM_LIT> ) && ( result % alignment != <NUM_LIT> ) ) return Relocator :: BadReloc ; result >>= shift ; if ( effectiveBits ) { uint32_t range = <NUM_LIT> << effectiveBits ; if ( result > ( range - <NUM_LIT> ) ) return Relocator :: Overflow ; }

pReloc . target ( ) |= ApplyMask < uint32_t > ( bitMask , result ) ;


<s> bool <ISA_LIT>FrameLowering :: needsSPWriteback ( const MachineFunction & MF ) const {


<s> for ( long i = <NUM_LIT> ; i < __builtin_popcountl ( __M ) ; i ++ ) { c = __builtin_clzl ( m ) ; p = ( p << <NUM_LIT> ) | c ; m ^= ( mask >> c ) ; } result = __builtin_bpermd ( p , __X ) ; } else { p = <NUM_LIT> - __builtin_popcountl ( __M ) ; result = <NUM_LIT> ; while ( m != <NUM_LIT> ) { unsigned long t ; c = __builtin_clzl ( m ) ; t = ( __X & ( mask >> c ) ) >> ( p - c ) ; m ^= ( mask >> c ) ; result |= ( t ) ;


<s> } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const override ; bool mayNeedRelaxation ( const MCInst & Inst ) const override ; bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override ; void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override ; bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const override ; MCObjectWriter * createObjectWriter ( raw_pwrite_stream & OS ) const override { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value , bool IsPCRel ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned Size = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ;


<s> } unsigned NumOperands = MI . getNumOperands ( ) ; SmallVector < unsigned , <NUM_LIT> > OpSize ( NumOperands ) ; SmallVector < PartialMappingIdx , <NUM_LIT> > OpRegBankIdx ( NumOperands ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumOperands ; ++ Idx ) { auto & MO = MI . getOperand ( Idx ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; LLT Ty = MRI . getType ( MO . getReg ( ) ) ; OpSize [ Idx ] = Ty . getSizeInBits ( ) ; if ( Ty . isVector ( ) || isPreISelGenericFloatingPointOpcode ( Opc ) ) OpRegBankIdx [ Idx ] = PMI_FirstFPR ; else OpRegBankIdx [ Idx ] = PMI_FirstGPR ; } unsigned Cost = <NUM_LIT> ; switch ( Opc ) { case TargetOpcode :: G_SITOFP : case TargetOpcode :: G_UITOFP : OpRegBankIdx = { PMI_FirstFPR , PMI_FirstGPR } ; break ; case TargetOpcode :: G_FPTOSI : case TargetOpcode :: G_FPTOUI : OpRegBankIdx = { PMI_FirstGPR , PMI_FirstFPR } ; break ; case TargetOpcode :: G_FCMP : OpRegBankIdx = { PMI_FirstGPR , PMI_None , PMI_FirstFPR , PMI_FirstFPR } ; break ; case TargetOpcode :: G_BITCAST : if ( OpRegBankIdx [ <NUM_LIT> ] != OpRegBankIdx [ <NUM_LIT> ] ) Cost = copyCost ( * <ISA_LIT>GenRegisterBankInfo :: PartMappings [ OpRegBankIdx [ <NUM_LIT> ] ] . RegBank , * <ISA_LIT>GenRegisterBankInfo :: PartMappings [ OpRegBankIdx [ <NUM_LIT> ] ] . RegBank , OpSize [ <NUM_LIT> ] ) ;


<s> const auto & MFI = MF . getFrameInfo ( ) ; return StackOffset :: getFixed ( ObjectOffset + ( int64_t ) MFI . getStackSize ( ) ) ;


<s> static void nds32_relax_group ( void ) { rtx_insn * insn ; compute_bb_for_insn ( ) ; df_chain_add_problem ( DF_DU_CHAIN | DF_UD_CHAIN ) ; df_insn_rescan_all ( ) ; df_analyze ( ) ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; calculate_dominance_info ( CDI_DOMINATORS ) ; insn = get_insns ( ) ; gcc_assert ( NOTE_P ( insn ) ) ; for ( insn = next_active_insn ( insn ) ; insn ; insn = next_active_insn ( insn ) ) { if ( NONJUMP_INSN_P ( insn ) ) { if ( recog_memoized ( insn ) == CODE_FOR_sethi && nds32_symbolic_operand ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) , SImode ) && ! nds32_ict_const_p ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ) ) nds32_group_insns ( insn ) ; else if ( recog_memoized ( insn ) == CODE_FOR_tls_ie ) nds32_group_tls_insn ( insn ) ; else if ( TARGET_FPU_SINGLE && recog_memoized ( insn ) == CODE_FOR_move_addr && ! nds32_ict_const_p ( XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ) ) { nds32_group_float_insns ( insn ) ; } } else if ( CALL_P ( insn ) && recog_memoized ( insn ) == CODE_FOR_tls_desc ) { nds32_group_tls_insn ( insn ) ; } } df_insn_rescan_all ( ) ; df_finish_pass ( false ) ;


<s> static bool riscv_cannot_copy_insn_p ( rtx_insn * insn ) { return recog_memoized ( insn ) >= <NUM_LIT> && get_attr_cannot_copy ( insn ) ;


<s> int <ISA_LIT>TTIImpl :: getVectorInstrCost ( unsigned Opcode , Type * ValTy , unsigned Index ) { switch ( Opcode ) { case Instruction :: ExtractElement : case Instruction :: InsertElement : { unsigned EltSize = DL . getTypeSizeInBits ( cast < VectorType > ( ValTy ) -> getElementType ( ) ) ; if ( EltSize < <NUM_LIT> ) { return BaseT :: getVectorInstrCost ( Opcode , ValTy , Index ) ;


<s> static void rs6000_option_override ( void ) {

( void ) rs6000_option_override_internal ( true ) ;


<s> case TargetStackID :: Default : case TargetStackID :: <ISA_LIT>Vector :


<s> MCAsmBackend * llvm :: create<ISA_LIT>_64AsmBackend ( const Target & T , StringRef TT ) { Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return new Darwin<ISA_LIT>_64AsmBackend ( T ) ; if ( TheTriple . isOSWindows ( ) ) return new Windows<ISA_LIT>AsmBackend ( T , true ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ; return new ELF<ISA_LIT>_64AsmBackend ( T , OSABI ) ;


<s> SDLoc dl ( N ) ; if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> && Subtarget . hasInt256 ( ) ) if ( ! <STR_LIT> ( N00 . getNode ( ) ) ) return SDValue ( ) ; if ( N00 . getValueType ( ) == <STR_LIT> && ExtraVT . getSizeInBits ( ) < <NUM_LIT> ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N00 , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp ) ;


<s> SDValue <ISA_LIT>TargetLowering :: combineINT_TO_FP ( SDNode * N , DAGCombinerInfo & DCI ) const { if ( DCI . Level != BeforeLegalizeTypes ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; LLVMContext & Ctx = * DAG . getContext ( ) ; unsigned Opcode = N -> getOpcode ( ) ; EVT OutVT = N -> getValueType ( <NUM_LIT> ) ; Type * OutLLVMTy = OutVT . getTypeForEVT ( Ctx ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OutScalarBits = OutLLVMTy -> getScalarSizeInBits ( ) ; unsigned InScalarBits = Op -> getValueType ( <NUM_LIT> ) . getScalarSizeInBits ( ) ;

if ( OutLLVMTy -> isVectorTy ( ) && OutScalarBits > InScalarBits && OutScalarBits <= <NUM_LIT> ) {


<s> Ops1 [ i ] = DAG . getNode ( <STR_LIT> , DL , ScalarVT , Op1 , Idx ) ; } Op0 = DAG . getBuildVector ( Pow2VT , DL , Ops0 ) ; Op1 = DAG . getBuildVector ( Pow2VT , DL , Ops1 ) ; } SDValue Res = SplitOpsAndApply ( DAG , Subtarget , DL , Pow2VT , { Op0 , Op1 } , AVGBuilder ) ; if ( NumElemsPow2 == NumElems ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } ; if ( IsConstVectorInRange ( Operands [ <NUM_LIT> ] , <NUM_LIT> , ScalarVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) && Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> && Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) { SDValue VecOnes = DAG . getConstant ( <NUM_LIT> , DL , InVT ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , InVT , Operands [ <NUM_LIT> ] , VecOnes ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] ) ; return AVGSplitter ( Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT> ] ) ; } auto FindAddLike = [ & ] ( SDValue V , SDValue & Op0 , SDValue & Op1 ) { if ( <STR_LIT> == V . getOpcode ( ) ) { Op0 = V . getOperand ( <NUM_LIT> ) ; Op1 = V . getOperand ( <NUM_LIT> ) ; return true ; } if ( <STR_LIT> != V . getOpcode ( ) ) return false ; V = V . getOperand ( <NUM_LIT> ) ; if ( V . getValueType ( ) != VT || <STR_LIT> != V . getOpcode ( ) || ! DAG . haveNoCommonBitsSet ( V . getOperand ( <NUM_LIT> ) , V . getOperand ( <NUM_LIT> ) ) ) return false ; Op0 = V . getOperand ( <NUM_LIT> ) ;


<s> virtual bool gate ( function * ) { return ( optimize > <NUM_LIT> && ! BYTES_BIG_ENDIAN && TARGET_VSX && rs6000_optimize_swaps ) ;


<s> } else if ( Op . Type == <ISA_LIT>Operand :: ImmTyOMod<ISA_LIT> ) { res = parseOModOperand ( Operands ) ; } else if ( Op . Type == <ISA_LIT>Operand :: ImmTySdwaDstSel || Op . Type == <ISA_LIT>Operand :: ImmTySdwaSrc0Sel || Op . Type == <ISA_LIT>Operand :: ImmTySdwaSrc1Sel ) { res = parseSDWASel ( Operands , Op . Name , Op . Type ) ;

} else if ( Op . Type == <ISA_LIT>Operand :: ImmTySdwaDstUnused ) {


<s> <ISA_LIT>COFFMachineModuleInfo ( const MachineModuleInfo & ) {


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override {

auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , <NUM_LIT> ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( FrameLabel ) ; MachineLocation SPDst ( MachineLocation :: VirtualFP ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP , - FrameSize * <NUM_LIT> ) ; Moves . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ; if ( LRSavedOnEntry ) { MachineLocation CSDst ( MachineLocation :: VirtualFP , <NUM_LIT> ) ; MachineLocation CSSrc ( <STR_LIT> ) ; Moves . push_back ( MachineMove ( FrameLabel , CSDst , CSSrc ) ) ; } } if ( saveLR ) { int LRSpillOffset = MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) ; storeToStack ( MBB , MBBI , <STR_LIT> , LRSpillOffset + FrameSize * <NUM_LIT> , dl , TII ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * SaveLRLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( SaveLRLabel ) ; MachineLocation CSDst ( MachineLocation :: VirtualFP , LRSpillOffset ) ; MachineLocation CSSrc ( <STR_LIT> ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( SaveLRLabel , CSDst , CSSrc ) ) ; } } } if ( FP ) { int FPSpillOffset = MFI -> getObjectOffset ( XFI -> getFPSpillSlot ( ) ) ; storeToStack ( MBB , MBBI , <STR_LIT> , FPSpillOffset + FrameSize * <NUM_LIT> , dl , TII ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * SaveR10Label = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( SaveR10Label ) ; MachineLocation CSDst ( MachineLocation :: VirtualFP , FPSpillOffset ) ; MachineLocation CSSrc ( <STR_LIT> ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( SaveR10Label , CSDst , CSSrc ) ) ; } unsigned FramePtr = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addImm ( <NUM_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * FrameLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( FrameLabel ) ; MachineLocation SPDst ( FramePtr ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ;


<s> return __builtin_ia32_vcvtuw2ph512_mask_round ( ( __v32hi ) __A , _mm512_setzero_ph ( ) , ( __mmask32 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


return new <ISA_LIT>ExpandHardenedPseudos ( ) ;


<s>
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
&
I
:
Outputs
)
dbgs
(
)
<<
' '
<<
I
.
second
;
dbgs
(
)
<<
'\n'
;
}
}
)
;
for
(
const
MachineOperand
&
MO
:
MI
.
operands
(
)
)
{
if
(
!
MO
.
isReg
(
)
||
!
MO
.
isDef
(
)
)
continue
;
RegisterSubReg
DefR
(
MO
)
;
if
(
!
DefR
.
Reg
.
isVirtual
(
)
)
continue
;
bool
Changed
=
false
;
if
(
!
Eval
)
{
const
LatticeCell
&
T
=
Cells
.
get
(
DefR
.
Reg
)
;
Changed
=
!
T
.
isBottom
(
)
;
Cells
.
update
(
DefR
.
Reg
,
Bottom
)
;


<s> EVT SrcElementVT = SrcVT . getVectorElementType ( ) ; if ( SrcElementVT == <STR_LIT> && ! Subtarget -> hasFullFP16 ( ) ) { MVT F32VT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( Op . getOpcode ( ) , SDLoc ( Op ) , DstVT , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , F32VT , SrcVal ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> for ( auto PHII : PHIs ) { rewriteRegionEntryPHI ( Region , IfMBB , * PHII ) ;


<s> Size = LastTagStore . Offset - FirstTagStore . Offset + LastTagStore . Size ; DL = TagStores [ <NUM_LIT> ] . MI -> getDebugLoc ( ) ; Register Reg ; FrameRegOffset = TFI -> resolveFrameOffsetReference ( * MF , FirstTagStore . Offset , false , false , Reg , false , true ) ; FrameReg = Reg ; FrameRegUpdate = None ; mergeMemRefs ( TagStores , CombinedMemRefs ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( const auto & Instr : TagStores ) { dbgs ( ) << <STR_LIT> << * Instr . MI ; } ) ; const int kSetTagLoopThreshold = <NUM_LIT> ; if ( Size < kSetTagLoopThreshold ) { if ( TagStores . size ( ) < <NUM_LIT> ) return ;


<s> MaxAlign = std :: max ( MaxAlign , Align ) ; Offset = ( Offset + Align - <NUM_LIT> ) / Align * Align ; if ( StackGrowsDown ) { DEBUG ( dbgs ( ) << <STR_LIT> << FrameIdx << <STR_LIT> << - Offset << <STR_LIT> ) ; MFI -> setObjectOffset ( FrameIdx , - Offset ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << FrameIdx << <STR_LIT> << Offset << <STR_LIT> ) ; MFI -> setObjectOffset ( FrameIdx , Offset ) ;

Offset += MFI -> getObjectSize ( FrameIdx ) ;


<s> emit_insn ( gen_load_toc_v4_PIC_1 ( lab ) ) ; emit_move_insn ( tmp1 , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; emit_insn ( gen_load_toc_v4_PIC_3b ( tmp2 , tmp1 , got , lab ) ) ; emit_insn ( gen_load_toc_v4_PIC_3c ( dest , tmp2 , got , lab ) ) ; } else if ( TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == <NUM_LIT> ) { emit_insn ( gen_load_toc_v4_pic_si ( ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; } else if ( TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == <NUM_LIT> ) { char buf [ <NUM_LIT> ] ; rtx temp0 = ( fromprolog ? gen_rtx_REG ( Pmode , <NUM_LIT> ) : gen_reg_rtx ( Pmode ) ) ; if ( fromprolog ) { rtx symF , symL ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symF = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , rs6000_pic_labelno ) ; symL = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; emit_insn ( gen_load_toc_v4_PIC_1 ( symF ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; emit_insn ( gen_load_toc_v4_PIC_2 ( temp0 , dest , symL , symF ) ) ; } else { rtx tocsym , lab ; tocsym = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( toc_label_name ) ) ; need_toc_init = <NUM_LIT> ; lab = gen_label_rtx ( ) ; emit_insn ( gen_load_toc_v4_PIC_1b ( tocsym , lab ) ) ; emit_move_insn ( dest , gen_rtx_REG ( Pmode , LR_REGNO ) ) ; if ( TARGET_LINK_STACK ) emit_insn ( gen_addsi3 ( dest , dest , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( temp0 , gen_rtx_MEM ( Pmode , dest ) ) ; }

emit_insn ( gen_addsi3 ( dest , temp0 , dest ) ) ;


<s> void <ISA_LIT>TargetStreamer :: emitIntTextAttribute ( unsigned Attribute , unsigned IntValue , StringRef StringValue ) { llvm_unreachable ( <STR_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> v = ~ v ; if ( v && ! ( v & ( v - <NUM_LIT> ) ) ) { int bit = <NUM_LIT> - __builtin_clz ( v ) ; imm = CurDAG -> getTargetConstant ( bit , <STR_LIT> ) ; return true ;


<s> <ISA_LIT>AsmBackend ( const Target & T , bool isLittle ) : MCAsmBackend ( ) , TheTarget ( T ) , IsLittleEndian ( isLittle ) {


<s> bool s390_return_addr_from_memory ( ) { return cfun_gpr_save_slot ( RETURN_REGNUM ) == SAVE_SLOT_STACK ;


<s> unsigned EltSizeInBits = MaskVT . getScalarSizeInBits ( ) ; if ( MaskVT . is128BitVector ( ) ) { if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) && AllowFloatDomain ) { V2 = V1 ; Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) && AllowFloatDomain ) { V2 = V1 ; Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) && Subtarget . hasSSE2 ( ) && ( AllowFloatDomain || ! Subtarget . hasSSE41 ( ) ) ) { std :: swap ( V1 , V2 ) ; Shuffle = <STR_LIT> ; SrcVT = DstVT = MaskVT ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && ( AllowFloatDomain || ! Subtarget . hasSSE41 ( ) ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = MaskVT ; return true ; } } if ( ( MaskVT == <STR_LIT> || MaskVT == <STR_LIT> ) && Subtarget . hasSSE2 ( ) ) { if ( matchVectorShuffleWithPACK ( MaskVT , SrcVT , V1 , V2 , Shuffle , Mask , DAG , Subtarget ) ) { DstVT = MaskVT ;


<s> ToErase -> eraseFromParent ( ) ; ToErase = nullptr ; } if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) continue ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefInst = MRI -> getUniqueVRegDef ( SrcReg ) ; if ( ! DefInst ) continue ; bool IsCandidate = false ; const GlobalValue * GVal = nullptr ; if ( DefInst -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ;


<s> return PerformVDIVCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformIntrinsicCombine ( N , DCI . DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformExtendCombine ( N , DCI . DAG , Subtarget ) ; case <STR_LIT> : return PerformCMOVCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformBRCONDCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformLOADCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformVLDCombine ( N , DCI ) ; case <STR_LIT> : return Perform<ISA_LIT>BUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : return PerformPREDICATE_CASTCombine ( N , DCI ) ; case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getHighBitsSet ( BitWidth , <NUM_LIT> ) ; if ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned BitWidth = N -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) ; APInt DemandedMask = APInt :: getLowBitsSet ( BitWidth , <NUM_LIT> ) ; if ( ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , DemandedMask , DCI ) ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned LowWidth = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; APInt LowMask = APInt :: getLowBitsSet ( LowWidth , <NUM_LIT> ) ; unsigned HighWidth = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; APInt HighMask = APInt :: getHighBitsSet ( HighWidth , <NUM_LIT> ) ; if ( ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , LowMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , HighMask , DCI ) ) ) return SDValue ( ) ; break ; } case <STR_LIT> : { unsigned HighWidth = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; APInt HighMask = APInt :: getHighBitsSet ( HighWidth , <NUM_LIT> ) ; unsigned LowWidth = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ; APInt LowMask = APInt :: getLowBitsSet ( LowWidth , <NUM_LIT> ) ;

if ( ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , HighMask , DCI ) ) || ( SimplifyDemandedBits ( N -> getOperand ( <NUM_LIT> ) , LowMask , DCI ) ) ) return SDValue ( ) ;


<s> Relocation :: Type getCopyRelType ( ) const {


<s> SDValue V = Insert128BitVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT> , DAG , dl ) ;

return Insert128BitVector ( V , V2 , NumElems / <NUM_LIT> , DAG , dl ) ;


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> explicit <ISA_LIT>16DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>DAGToDAGISel ( TM ) {


<s> for ( uint16_t i = <NUM_LIT> ; i < W ; ++ i ) { const BitTracker :: BitValue & BV = RC [ i ] ; if ( BV . is ( <NUM_LIT> ) || BV . is ( <NUM_LIT> ) ) continue ; return false ; }


<s> <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( GetOppositeBranchCondition ( CC ) ) ;


<s> assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) return true ; Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpcode ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; return false ;


if ( ! TARGET_GCC_ABI ) target_flags |= MASK_DISABLE_CALLT ;


<s> const MCInstrDesc & Desc = MII . get ( Opcode ) ; const int ImmIdx = <STR_LIT> ( Opcode , <STR_LIT> :: imm ) ; if ( ! ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> ) ) && ImmIdx == - <NUM_LIT> ) return true ; const int Src0Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src0 ) ; const int Src1Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src1 ) ; const int Src2Idx = <STR_LIT> ( Opcode , <STR_LIT> :: src2 ) ; const int OpIndices [ ] = { Src0Idx , Src1Idx , Src2Idx , ImmIdx } ; unsigned NumExprs = <NUM_LIT> ; unsigned NumLiterals = <NUM_LIT> ; uint32_t LiteralValue ; for ( int OpIdx : OpIndices ) { if ( OpIdx == - <NUM_LIT> ) continue ; const MCOperand & MO = Inst . getOperand ( OpIdx ) ; if ( ! MO . isImm ( ) && ! MO . isExpr ( ) ) continue ; if ( ! <STR_LIT> ( Desc , OpIdx ) ) continue ; if ( OpIdx == Src2Idx && ( Desc . TSFlags & <STR_LIT> ) && getFeatureBits ( ) [ <STR_LIT> ] ) { Error ( getConstLoc ( Operands ) , <STR_LIT> ) ; return false ; } if ( MO . isImm ( ) && ! isInlineConstant ( Inst , OpIdx ) ) { uint32_t Value = static_cast < uint32_t > ( MO . getImm ( ) ) ; if ( NumLiterals == <NUM_LIT> || LiteralValue != Value ) { LiteralValue = Value ; ++ NumLiterals ; } } else if ( MO . isExpr ( ) ) { ++ NumExprs ; } } NumLiterals += NumExprs ; if ( ! NumLiterals ) return true ; if ( ImmIdx == - <NUM_LIT> && ! getFeatureBits ( ) [ <STR_LIT> ] ) { Error ( getLitLoc ( Operands ) , <STR_LIT> ) ; return false ; }


<s> const Constant * C = CPE . Val . ConstVal ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( Kind , C ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) {

if ( Sym -> isUndefined ( ) ) OutStreamer -> EmitSymbolAttribute ( Sym , MCSA_Global ) ;


<s> reg_class_t csky_secondary_reload ( bool in_p ATTRIBUTE_UNUSED , rtx x , reg_class_t rclass , machine_mode mode , secondary_reload_info * sri ATTRIBUTE_UNUSED ) { int regno = - <NUM_LIT> ; if ( GET_CODE ( x ) == SIGN_EXTEND ) { int off = <NUM_LIT> ; x = XEXP ( x , <NUM_LIT> ) ; if ( reg_renumber ) regno = true_regnum ( x ) ;


<s> case MEM : case CONST_INT : return REG_P ( dst ) ; case VEC_SELECT : return REG_P ( dst ) && REG_P ( XEXP ( src , <NUM_LIT> ) ) && GET_MODE ( XEXP ( src , <NUM_LIT> ) ) == ( mode == DImode ? V2DImode : V4SImode ) && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == PARALLEL && XVECLEN ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) == <NUM_LIT> && CONST_INT_P ( XVECEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; if ( GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != mode && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; return true ;


<s> if ( Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == <NUM_LIT> || Val == - <NUM_LIT> ) return true ; return false ;


<s> auto Node = Func . getParent ( ) -> getNamedMetadata ( <STR_LIT> ) ; if ( ! Node || ! Node -> getNumOperands ( ) ) return ; auto Op0 = Node -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getNumOperands ( ) <= <NUM_LIT> ) return ; Kern [ <STR_LIT> ] = std :: make_shared < msgpack :: ScalarNode > ( <STR_LIT> ) ; auto LanguageVersion = std :: make_shared < msgpack :: ArrayNode > ( ) ; LanguageVersion -> push_back ( std :: make_shared < msgpack :: ScalarNode > ( mdconst :: extract < ConstantInt > ( Op0 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ) ; LanguageVersion -> push_back ( std :: make_shared < msgpack :: ScalarNode > ( mdconst :: extract < ConstantInt > ( Op0 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ) ; Kern [ <STR_LIT> ] = std :: move ( LanguageVersion ) ;


<s> return __builtin_aarch64_lrounduv4sfv4si_us ( __a ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> static SDValue isScalarToVec ( SDValue Op ) { if ( Op . getOpcode ( ) == <STR_LIT> ) return Op ; if ( Op . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Op = Op . getOperand ( <NUM_LIT> ) ;


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_FUNCTION_ENTER ( const MachineInstr & MI , <ISA_LIT>MCInstLower & MCIL ) { auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ;

recordSled ( CurSled , MI , SledKind :: FUNCTION_ENTER ) ;


<s> x . i [ <NUM_LIT> ] = <NUM_LIT> << <NUM_LIT> ; aabs = vec_and ( ( vec_uint4 ) a , sign_mask ) ; babs = vec_and ( ( vec_uint4 ) b , sign_mask ) ; biteq = ( vec_uint4 ) vec_cmpeq ( ( vec_uint4 ) aabs , ( vec_uint4 ) babs ) ; biteq = vec_and ( biteq , ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) biteq , x . v ) ) ; a_gt = ( vec_uint4 ) vec_cmpgt ( aabs , nan_mask ) ; ahi_inf = ( vec_uint4 ) vec_cmpeq ( aabs , nan_mask ) ;

anan = ( vec_uint4 ) vec_or ( a_gt , vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_gt , x . v ) , ahi_inf ) ) ;


<s> const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) , Align ( <NUM_LIT> ) , false , false , false , MachinePointerInfo ( DstSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return nullptr ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> switch ( LC ) { case RTLIB :: MEMCPY : AEABILibcall = AEABI_MEMCPY ; break ; case RTLIB :: MEMMOVE : AEABILibcall = AEABI_MEMMOVE ; break ; case RTLIB :: MEMSET : AEABILibcall = AEABI_MEMSET ; if ( ConstantSDNode * ConstantSrc = dyn_cast < ConstantSDNode > ( Src ) ) if ( ConstantSrc -> getZExtValue ( ) == <NUM_LIT> ) AEABILibcall = AEABI_MEMCLR ; break ; default : return SDValue ( ) ; } enum { ALIGN1 = <NUM_LIT> , ALIGN4 , ALIGN8 } AlignVariant ; if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN8 ; else if ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) AlignVariant = ALIGN4 ; else AlignVariant = ALIGN1 ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; if ( AEABILibcall == AEABI_MEMCLR ) { Entry . Node = Size ; Args . push_back ( Entry ) ; } else if ( AEABILibcall == AEABI_MEMSET ) { Entry . Node = Size ; Args . push_back ( Entry ) ; if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else if ( Src . getValueType ( ) . bitsLT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . IsSExt = false ; Args . push_back ( Entry ) ; } else { Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; } char const * FunctionNames [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setLibCallee ( TLI -> getLibcallCallingConv ( LC ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalFunctionSymbol ( FunctionNames [ AEABILibcall ] [ AlignVariant ] ) , std :: move ( Args ) ) . setDiscardResult ( ) ;

std :: pair < SDValue , SDValue > CallResult = TLI -> LowerCallTo ( CLI ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitGlobalVariable ( const GlobalVariable * GV ) { assert ( GV -> isConstant ( ) && <STR_LIT> ) ;


<s> for ( int i = ( Size - <NUM_LIT> ) * <NUM_LIT> ; i >= <NUM_LIT> ; i -= <NUM_LIT> ) EmitByte ( ( Val >> i ) & <NUM_LIT> , CurByte , OS ) ;


<s> } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; printExpr ( Op . getExpr ( ) , O , MAI ) ; }


<s> SDValue SEW = CurDAG -> getTargetConstant ( ScalarSize , DL , XLenVT ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue MaskedOff = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SDValue Operands [ ] = { MaskedOff , Node -> getOperand ( NF + <NUM_LIT> ) , Node -> getOperand ( NF + <NUM_LIT> ) , Node -> getOperand ( NF + <NUM_LIT> ) , Node -> getOperand ( NF + <NUM_LIT> ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( NF + <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Load = CurDAG -> getMachineNode ( P -> Pseudo , DL , <STR_LIT> , <STR_LIT> , Operands ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NF ; ++ I ) ReplaceUses ( SDValue ( Node , I ) , CurDAG -> getTargetExtractSubreg ( getSubregIndexByEVT ( VT , I ) , DL , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( Node , NF ) , SDValue ( Load , <NUM_LIT> ) ) ; CurDAG -> RemoveDeadNode ( Node ) ;


<s> eol = in_comment ; in_comment = <NUM_LIT> ; for ( ; * ptr ; ptr ++ ) { if ( * ptr == '\n' ) { ptr ++ ; break ; } if ( ptr [ <NUM_LIT> ] == '*' && ptr [ <NUM_LIT> ] == '/' ) { in_comment = <NUM_LIT> ; ptr += <NUM_LIT> ; break ; } } kind = K_comment ; } else break ; } break ; case '"' : kind = K_string ; while ( * ptr ) if ( * ptr == '"' ) { ptr ++ ; break ; } else if ( * ptr ++ == '\\' ) ptr ++ ; break ; case '.' : if ( * ptr < '0' || * ptr > '9' ) { kind = K_dotted ; ws = not_comment ; goto ident ; } case '0' ... '9' : kind = K_number ; goto ident ; break ; case '$' : case '%' : kind = K_ident ; goto ident ; case 'a' ... 'z' : case 'A' ... 'Z' : case '_' : kind = K_symbol ; ident : for ( ; * ptr ; ptr ++ ) { if ( * ptr >= 'A' && * ptr <= 'Z' ) continue ; if ( * ptr >= 'a' && * ptr <= 'z' ) continue ; if ( * ptr >= '0' && * ptr <= '9' ) continue ; if ( * ptr == '_' || * ptr == '$' ) continue ; if ( * ptr == '.' && kind != K_dotted ) continue ; if ( ( * ptr == '+' || * ptr == '-' ) && kind == K_number && ( ptr [ - <NUM_LIT> ] == 'e' || ptr [ - <NUM_LIT> ] == 'E' || ptr [ - <NUM_LIT> ] == 'p' || ptr [ - <NUM_LIT> ] == 'P' ) ) continue ; break ; } if ( * ptr == ':' ) { ptr ++ ; kind = K_label ; } break ; } if ( alloc == num ) { alloc *= <NUM_LIT> ; toks = XRESIZEVEC ( Token , toks , alloc ) ; } Token * tok = toks + num ; tok -> kind = kind ; tok -> space = ws ; tok -> end = <NUM_LIT> ;


<s> RegisterAggr & RegisterAggr :: insert ( const RegisterAggr & RG ) {


<s> unsigned NOps = MI -> getNumOperands ( ) ; assert ( NOps == <NUM_LIT> ) ; OS << '\t' << MAI -> getCommentString ( ) << <STR_LIT> ; OS << cast < MDLocalVariable > ( MI -> getOperand ( NOps - <NUM_LIT> ) . getMetadata ( ) ) -> getName ( ) ; OS << <STR_LIT> ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; OS << '[' ; printOperand ( MI , <NUM_LIT> , OS ) ; OS << '+' ; printOperand ( MI , <NUM_LIT> , OS ) ;


<s> APInt Demanded = APInt :: getLowBitsSet ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , true , true ) ; if ( TLI . SimplifyDemandedBits ( Op , Demanded , KnownZero , KnownOne , TLO ) ) DCI . CommitTargetLoweringOpt ( TLO ) ;


<s> obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; switch ( offload_abi ) { case OFFLOAD_ABI_LP64 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; case OFFLOAD_ABI_ILP32 : obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } obstack_ptr_grow ( & argv_obstack , target_so_filename ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , rename_section_opt ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; char * * new_argv = XOBFINISH ( & argv_obstack , char * * ) ; fork_execute ( new_argv [ <NUM_LIT> ] , new_argv , false ) ; obstack_free ( & argv_obstack , NULL ) ; size_t symbol_name_len = strlen ( target_so_filename ) ; char * symbol_name = XALLOCAVEC ( char , symbol_name_len + <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < symbol_name_len ; i ++ ) { char c = target_so_filename [ i ] ; if ( ! ISALNUM ( c ) ) c = '_' ; symbol_name [ i ] = c ; } symbol_name [ symbol_name_len ] = '\0' ; char * opt_for_objcopy [ <NUM_LIT> ] ; opt_for_objcopy [ <NUM_LIT> ] = XALLOCAVEC ( char , sizeof ( <STR_LIT> ) + symbol_name_len + strlen ( symbols [ <NUM_LIT> ] ) ) ; opt_for_objcopy [ <NUM_LIT> ] = XALLOCAVEC ( char , sizeof ( <STR_LIT> ) + symbol_name_len + strlen ( symbols [ <NUM_LIT> ] ) ) ; opt_for_objcopy [ <NUM_LIT> ] = XALLOCAVEC ( char , sizeof ( <STR_LIT> ) + symbol_name_len + strlen ( symbols [ <NUM_LIT> ] ) ) ; sprintf ( opt_for_objcopy [ <NUM_LIT> ] , <STR_LIT> , symbol_name , symbols [ <NUM_LIT> ] ) ; sprintf ( opt_for_objcopy [ <NUM_LIT> ] , <STR_LIT> , symbol_name , symbols [ <NUM_LIT> ] ) ; sprintf ( opt_for_objcopy [ <NUM_LIT> ] , <STR_LIT> , symbol_name , symbols [ <NUM_LIT> ] ) ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , target_so_filename ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , opt_for_objcopy [ <NUM_LIT> ] ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ;


<s> for ( auto * Ld1 : Loads ) { if ( Ld0 == Ld1 ) continue ; if ( AreSequentialAccesses < LoadInst > ( Ld0 , Ld1 , * DL , * SE ) ) { LoadPairs [ Ld0 ] = Ld1 ; if ( BaseLoads . count ( Ld0 ) ) { LoadInst * Base = BaseLoads [ Ld0 ] ; BaseLoads [ Ld1 ] = Base ; SequentialLoads [ Base ] . push_back ( Ld1 ) ;


<s> PadShortFunc ( ) : MachineFunctionPass ( ID ) , Threshold ( <NUM_LIT> ) , TM ( nullptr ) , TII ( nullptr ) {


<s> bool <ISA_LIT>ExpandSDMA :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ;

for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ;


<s> const InstrItineraryData & getInstrItineraryData ( ) const {


<s> if ( ! TARGET_ABI_GNU && regno < current_function_args_info . regs - <NUM_LIT> ) { regno = current_function_args_info . regs - <NUM_LIT> ; if ( regno > MMIX_RETURN_VALUE_REGNUM - <NUM_LIT> ) regno = MMIX_RETURN_VALUE_REGNUM - <NUM_LIT> ; } cfun -> machine -> highest_saved_stack_register = regno ;


<s> if ( _U_Qfcmp ( a , b , <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; return ( _U_Qfcmp ( a , b , <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : - <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; }


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const <ISA_LIT>FrameLowering * <ISA_LIT>FI = static_cast < const <ISA_LIT>FrameLowering * > ( Subtarget . getFrameLowering ( ) ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; Register InputPtrReg = Info . addKernargSegmentPtr ( TRI ) ; CCInfo . AllocateReg ( InputPtrReg ) ; Register VReg = MF . addLiveIn ( InputPtrReg , & <STR_LIT> ) ; MRI . setType ( VReg , LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ) ; } if ( Info . hasDispatchID ( ) ) { Register DispatchIDReg = Info . addDispatchID ( TRI ) ; MF . addLiveIn ( DispatchIDReg , & <STR_LIT> ) ; CCInfo . AllocateReg ( DispatchIDReg ) ; } if ( Info . hasFlatScratchInit ( ) && ! getSubtarget ( ) -> isAmdPalOS ( ) ) { Register FlatScratchInitReg = Info . addFlatScratchInit ( TRI ) ; MF . addLiveIn ( FlatScratchInitReg , & <STR_LIT> ) ; CCInfo . AllocateReg ( FlatScratchInitReg ) ; }


<s> } } SmallVector < MachineInstr * , <NUM_LIT> > ToDelete ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; MachineInstr * Try = & MI , * EndTry = BeginToEnd [ Try ] ; if ( EndTry -> getOpcode ( ) == <STR_LIT> ) continue ; MachineBasicBlock * TryBB = Try -> getParent ( ) ; MachineBasicBlock * Cont = EndTry -> getParent ( ) ; int64_t RetType = Try -> getOperand ( <NUM_LIT> ) . getImm ( ) ; for ( auto B = Try -> getIterator ( ) , E = std :: next ( EndTry -> getIterator ( ) ) ;

B != TryBB -> begin ( ) && E != Cont -> end ( ) && std :: prev ( B ) -> getOpcode ( ) == <STR_LIT> && E -> getOpcode ( ) == <STR_LIT> && std :: prev ( B ) -> getOperand ( <NUM_LIT> ) . getImm ( ) == RetType ;


<s> if ( ST -> hasAVX2 ( ) ) { int Idx = CostTableLookup < MVT > ( AVX2CostTable , array_lengthof ( AVX2CostTable ) , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX2CostTable [ Idx ] . Cost ; } static const CostTblEntry < MVT > SSE2UniformConstCostTable [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( Op2Info == TargetTransformInfo :: OK_UniformConstantValue && ST -> hasSSE2 ( ) ) { int Idx = CostTableLookup < MVT > ( SSE2UniformConstCostTable , array_lengthof ( SSE2UniformConstCostTable ) , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSE2UniformConstCostTable [ Idx ] . Cost ; } static const CostTblEntry < MVT > SSE2CostTable [ ] = {


<s> static const unsigned HiRegList [ ] = { <STR_LIT> , <STR_LIT> } ; static const unsigned LoRegList [ ] = { <STR_LIT> , <STR_LIT> } ; unsigned Reg = State . AllocateReg ( HiRegList , LoRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ;

State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , <STR_LIT> , LocInfo ) ) ;


<s> MachineOperand VdSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VdSrc ) ; } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) ; MachineOperand VmSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VmSrc ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( SrcIsKill ) ) ;


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return SDValue ( ) ; if ( ( EltVT . getSizeInBits ( ) == <NUM_LIT> || EltVT . getSizeInBits ( ) == <NUM_LIT> ) && isa < ConstantSDNode > ( N2 ) ) { unsigned Opc ; if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( VT == <STR_LIT> ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; if ( N1 . getValueType ( ) != <STR_LIT> ) N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; if ( N2 . getValueType ( ) != <STR_LIT> ) N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) ) ; return DAG . getNode ( Opc , dl , VT , N0 , N1 , N2 ) ; } else if ( EltVT == <STR_LIT> && isa < ConstantSDNode > ( N2 ) ) { N2 = DAG . getIntPtrConstant ( cast < ConstantSDNode > ( N2 ) -> getZExtValue ( ) << <NUM_LIT> ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N0 , N1 , N2 ) ; } else if ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && isa < ConstantSDNode > ( N2 ) ) {


<s> set_offset ( XER_REGNO , m64 -> xer + <NUM_LIT> ) ; set_offset ( LINK_REGISTER_REGNUM , m64 -> lr + <NUM_LIT> ) ; set_offset ( COUNT_REGISTER_REGNUM , m64 -> ctr + <NUM_LIT> ) ; if ( is_vector ) set_offset ( VRSAVE_REGNO , & m64 -> vrsave ) ; if ( m64 -> exception == <NUM_LIT> || m64 -> exception == <NUM_LIT> || m64 -> exception == <NUM_LIT> || ( m64 -> exception == <NUM_LIT> && ! ( m64 -> srr1 & <NUM_LIT> ) ) ) return_addr = m64 -> srr0 + <NUM_LIT> ; else return_addr = m64 -> srr0 ; } else { struct gcc_mcontext32 * m = uctx -> mcontext ; int i ; float_vector_state = & m -> fvs ; new_cfa = m -> gpr [ <NUM_LIT> ] ; set_offset ( CR2_REGNO , & m -> cr ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) set_offset ( i , m -> gpr + i ) ; set_offset ( XER_REGNO , & m -> xer ) ; set_offset ( LINK_REGISTER_REGNUM , & m -> lr ) ; set_offset ( COUNT_REGISTER_REGNUM , & m -> ctr ) ; if ( is_vector ) set_offset ( VRSAVE_REGNO , & m -> vrsave ) ; if ( m -> exception == <NUM_LIT> || m -> exception == <NUM_LIT> || m -> exception == <NUM_LIT> || ( m -> exception == <NUM_LIT> && ! ( m -> srr1 & <NUM_LIT> ) ) ) return_addr = m -> srr0 + <NUM_LIT> ; else return_addr = m -> srr0 ;


<s> FOR_EACH_BB_FN ( bb , cfun ) { FOR_BB_INSNS ( bb , insn ) { if ( single_set ( insn ) && nds32_symbol_load_store_p ( insn ) ) { rtx pattern = PATTERN ( insn ) ; rtx mem ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; if ( GET_CODE ( SET_SRC ( pattern ) ) == REG ) mem = SET_DEST ( pattern ) ; else mem = SET_SRC ( pattern ) ; if ( GET_CODE ( mem ) == MEM ) symbol_count ++ ; } } }


<s> ByValArgInfo ( ) : FirstIdx ( <NUM_LIT> ) , NumRegs ( <NUM_LIT> ) , Address ( <NUM_LIT> ) {


<s> r = REAL_VALUE_ATOF ( <STR_LIT> , DFmode ) ; value_fp0 = r ;


<s> DiagnosticInfoUnsupported BadIntrin ( DAG . getMachineFunction ( ) . getFunction ( ) , <STR_LIT> , DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadIntrin ) ;


<s> void <ISA_LIT>InstPrinter :: printMemRegImm34 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { printS34ImmOperand ( MI , OpNo , O ) ; O << '(' ; printOperand ( MI , OpNo + <NUM_LIT> , O ) ; O << ')' ;


<s> const char * directive = ASM_LONG ; if ( TARGET_64BIT ) directive = ASM_QUAD ; gcc_assert ( ! TARGET_64BIT ) ; fprintf ( file , <STR_LIT> , directive , LPREFIX , value ) ;


<s> case k_PostIndexRegister : OS << <STR_LIT> << ( PostIdxReg . isAdd ? <STR_LIT> : <STR_LIT> ) << PostIdxReg . RegNum ; if ( PostIdxReg . ShiftTy != <STR_LIT> ) OS << <STR_LIT> ( PostIdxReg . ShiftTy ) << <STR_LIT> << PostIdxReg . ShiftImm ; OS << <STR_LIT> ; break ; case k_ProcIFlags : { OS << <STR_LIT> ; unsigned IFlags = getProcIFlags ( ) ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( IFlags & ( <NUM_LIT> << i ) ) OS << <STR_LIT> ( <NUM_LIT> << i ) ; OS << <STR_LIT> ; break ; } case k_Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case k_ShifterImmediate : OS << <STR_LIT> << ( ShifterImm . isASR ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ShifterImm . Imm << <STR_LIT> ; break ; case k_ShiftedRegister : OS << <STR_LIT> << RegShiftedReg . SrcReg << <STR_LIT> << <STR_LIT> ( RegShiftedReg . ShiftTy ) << <STR_LIT> << RegShiftedReg . ShiftReg << <STR_LIT> ; break ; case k_ShiftedImmediate : OS << <STR_LIT> << RegShiftedImm . SrcReg << <STR_LIT> << <STR_LIT> ( RegShiftedImm . ShiftTy ) << <STR_LIT> << RegShiftedImm . ShiftImm << <STR_LIT> ; break ; case k_RotateImmediate : OS << <STR_LIT> << <STR_LIT> << ( RotImm . Imm * <NUM_LIT> ) << <STR_LIT> ; break ; case k_BitfieldDescriptor : OS << <STR_LIT> << <STR_LIT> << Bitfield . LSB << <STR_LIT> << Bitfield . Width << <STR_LIT> ; break ; case k_RegisterList : case k_DPRRegisterList : case k_SPRRegisterList : { OS << <STR_LIT> ; const SmallVectorImpl < unsigned > & RegList = getRegList ( ) ; for ( SmallVectorImpl < unsigned > :: const_iterator I = RegList . begin ( ) , E = RegList . end ( ) ; I != E ; ) { OS << * I ; if ( ++ I < E ) OS << <STR_LIT> ; } OS << <STR_LIT> ; break ; } case k_VectorList : OS << <STR_LIT> << VectorList . Count << <STR_LIT> << VectorList . RegNum << <STR_LIT> ; break ; case k_VectorListAllLanes : OS << <STR_LIT> << VectorList . Count << <STR_LIT> << VectorList . RegNum << <STR_LIT> ; break ; case k_VectorListIndexed : OS << <STR_LIT> << VectorList . LaneIndex << <STR_LIT> << VectorList . Count << <STR_LIT> << VectorList . RegNum << <STR_LIT> ; break ; case k_Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case k_VectorIndex : OS << <STR_LIT> << getVectorIndex ( ) << <STR_LIT> ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: lanai > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerAND ( Op , DAG ) ; case <STR_LIT> : return LowerOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG ) ; case <STR_LIT> : return LowerFSINCOS ( Op , DAG ) ; case <STR_LIT> :


<s> Blocks . remove ( Inner ) ; GetBlocksOut ( Inner , NextEntries , & Blocks ) ; BlockSet JustInner ; JustInner . insert ( Inner ) ; for ( const auto & iter : NextEntries ) Solipsize ( iter , Branch :: Direct , Simple , JustInner ) ; } return Simple ;


<s> bool <ISA_LIT>GlobalRegistry :: isScalarOfType ( Register VReg , unsigned TypeOpcode ) const {

<ISA_LIT>Type * Type = get<ISA_LIT>TypeForVReg ( VReg ) ;


<s> setAttrs ( NodeAttrs :: set_flags ( getAttrs ( ) , F ) ) ;


<s> if ( TII -> usesFPDPRounding ( MI ) ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> :


<s> return ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; }


<s> FunctionPass * llvm :: create<ISA_LIT>RemoveExtendOps ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>RemoveExtendArgs ( ) ;


<s> if ( STI . isTargetCygMing ( ) ) { Symbol = <STR_LIT> ; } else { Symbol = <STR_LIT> ; } } else if ( STI . isTargetCygMing ( ) ) Symbol = <STR_LIT> ; else Symbol = <STR_LIT> ; MachineInstrBuilder CI ; MachineBasicBlock :: iterator ExpansionMBBI = std :: prev ( MBBI ) ; if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( Symbol ) ; CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addReg ( <STR_LIT> ) ; } else { CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addExternalSymbol ( Symbol ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setManipulatesSP ( true ) ; unsigned sp = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getCopyFromReg ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , sp , Op . getValueType ( ) ) ;


<s> MCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( TT ) ; unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ;

MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( <NUM_LIT> , Reg , <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Align , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) { * Fast = true ; } return true ;