<s> hasAddend = true ; Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; break ; case R_<ISA_LIT>_64_GOT32 : case R_<ISA_LIT>_64_GOT64 : case R_<ISA_LIT>_64_GOTPC32 : case R_<ISA_LIT>_64_GOTPC64 : case R_<ISA_LIT>_64_GOTPLT64 : hasAddend = true ; Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOT , Ctx ) ; break ; case R_<ISA_LIT>_64_PLT32 : hasAddend = true ; Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_PLT , Ctx ) ; break ; case R_<ISA_LIT>_64_GLOB_DAT : case R_<ISA_LIT>_64_JUMP_SLOT : Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; break ; case R_<ISA_LIT>_64_GOTPCREL : case R_<ISA_LIT>_64_GOTPCREL64 : hasAddend = true ; Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , Ctx ) ; break ;


<s> void SLSBLRThunkInserter :: insertThunks ( MachineModuleInfo & MMI ) { for ( auto T : SLSBLRThunks ) createThunkFunction ( MMI , T . Name , ComdatThunks ) ;


<s> bool <ISA_LIT>TargetObjectFile :: IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const {

const GlobalVariable * GVA = dyn_cast < GlobalVariable > ( GV ) ;


<s> if ( got == registersMsrToSlvMap . end ( ) ) { return false ;


<s> if ( opts -> x_flag_align_jumps && ! opts -> x_str_align_jumps ) opts -> x_str_align_jumps = aarch64_tune_params . jump_align ; if ( opts -> x_flag_align_functions && ! opts -> x_str_align_functions ) opts -> x_str_align_functions = aarch64_tune_params . function_align ; } aarch64_pcrelative_literal_loads = false ; if ( opts -> x_pcrelative_literal_loads == <NUM_LIT> ) aarch64_pcrelative_literal_loads = true ; if ( aarch64_cmodel == AARCH64_CMODEL_TINY || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC ) aarch64_pcrelative_literal_loads = true ; if ( flag_mlow_precision_sqrt ) flag_mrecip_low_precision_sqrt = true ;


<s> __v16qi result = ( __v16qi ) __A ; result [ __N & <NUM_LIT> ] = __D ; return ( __m128i ) result ;


<s> FlatWorkGroupSizes = ST . getFlatWorkGroupSizes ( F ) ; WavesPerEU = ST . getWavesPerEU ( F ) ; Occupancy = ST . computeOccupancy ( F , getLDSSize ( ) ) ; CallingConv :: ID CC = F . getCallingConv ( ) ; const bool HasCalls = F . hasFnAttribute ( <STR_LIT> ) ; const bool UseFixedABI = <ISA_LIT>TargetMachine :: EnableFixedFunctionABI && ( ! isEntryFunction ( ) || HasCalls ) ; if ( CC == CallingConv :: <ISA_LIT>_KERNEL || CC == CallingConv :: SPIR_KERNEL ) { if ( ! F . arg_empty ( ) ) KernargSegmentPtr = true ; WorkGroupIDX = true ; WorkItemIDX = true ; } else if ( CC == CallingConv :: <ISA_LIT>_PS ) { P<ISA_LIT>nputAddr = <STR_LIT> ( F ) ; } if ( ! isEntryFunction ( ) ) { ScratchRSrcReg = <STR_LIT> ; FrameOffsetReg = <STR_LIT> ; StackPtrOffsetReg = <STR_LIT> ; ArgInfo . PrivateSegmentBuffer = ArgDescriptor :: createRegister ( ScratchRSrcReg ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) ImplicitArgPtr = true ; } else { if ( F . hasFnAttribute ( <STR_LIT> ) ) { KernargSegmentPtr = true ; MaxKernArgAlign = std :: max ( ST . getAlignmentForImplicitArgPtr ( ) , MaxKernArgAlign ) ; } } if ( UseFixedABI ) { WorkGroupIDX = true ; WorkGroupIDY = true ; WorkGroupIDZ = true ; WorkItemIDX = true ; WorkItemIDY = true ; WorkItemIDZ = true ; ImplicitArgPtr = true ; } else { if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDX = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDY = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkGroupIDZ = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDX = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDY = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDZ = true ; }

bool HasStackObjects = F . hasFnAttribute ( <STR_LIT> ) ;


<s> uint8_t getIORegisterOffset ( ) const { return hasMemMappedGPR ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> if ( TARGET_MINI_REGISTERS ? CSKY_CONST_OK_FOR_J ( val + <NUM_LIT> ) : CSKY_CONST_OK_FOR_Uk ( val + <NUM_LIT> ) ) { op1 = GEN_INT ( val + <NUM_LIT> ) ; code = code == LE ? LT : GE ; } break ; default : break ; } } if ( CONSTANT_P ( op1 ) && GET_CODE ( op1 ) != CONST_INT ) op1 = force_reg ( GET_MODE ( op1 ) , op1 ) ; invert = false ; switch ( code ) { case EQ : code = NE ; invert = true ; case NE : if ( GET_CODE ( op1 ) == CONST_INT && ( TARGET_MINI_REGISTERS ? ! csky_literal_K_operand ( op1 , SImode ) : ! csky_literal_I_operand ( op1 , SImode ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case LE : code = GT ; invert = true ; case GT : if ( GET_CODE ( op1 ) == CONST_INT ) op1 = force_reg ( SImode , op1 ) ; break ; case GE : code = LT ; invert = true ; case LT : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != <NUM_LIT> && ( TARGET_MINI_REGISTERS ? ! csky_literal_J_operand ( op1 , SImode ) : ! csky_literal_Uk_operand ( op1 , SImode ) ) ) op1 = force_reg ( SImode , op1 ) ; break ; case GTU : gcc_assert ( GET_CODE ( op1 ) != CONST_INT || INTVAL ( op1 ) != <NUM_LIT> ) ; code = LEU ; invert = true ; case LEU : if ( GET_CODE ( op1 ) == CONST_INT && INTVAL ( op1 ) != <NUM_LIT> ) op1 = force_reg ( SImode , op1 ) ;


<s> inline vector float vec_ceil ( vector float a1 ) {

return ( vector float ) __builtin_altivec_vrfip ( ( vector float ) a1 ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugValue ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ;

MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: PerformStoreCombine ( SDNode * N , DAGCombinerInfo & DCI ) const {


<s> if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; Defs . insert ( R ) ; }


<s> if ( OpVT != <STR_LIT> && OpVT != <STR_LIT> ) return SDValue ( ) ; assert ( ArgVT == <STR_LIT> ) ; SDLoc DL ( Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ;

return SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , OpVT , Op , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> Immed = std :: abs ( Immed ) ; bool IsLegal = ( ( Immed >> <NUM_LIT> ) == <NUM_LIT> || ( ( Immed & <NUM_LIT> ) == <NUM_LIT> && Immed >> <NUM_LIT> == <NUM_LIT> ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Immed << <STR_LIT> << ( IsLegal ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ) ; return IsLegal ;


<s> SDValue Base = ST -> getBasePtr ( ) ; SDValue Offset = ST -> getOffset ( ) ; SDValue Value = ST -> getValue ( ) ; int32_t Inc = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; EVT StoredVT = ST -> getMemoryVT ( ) ; EVT ValueVT = Value . getValueType ( ) ; bool IsValidInc = HII -> isValidAutoIncImm ( StoredVT , Inc ) ; unsigned Opcode = <NUM_LIT> ; assert ( StoredVT . isSimple ( ) ) ; switch ( StoredVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isAlignedMemNode ( ST ) ) {

if ( ST -> isNonTemporal ( ) ) Opcode = IsValidInc ? <STR_LIT> : <STR_LIT> ;


<s> if ( mode != SFmode && GET_MODE_CLASS ( mode ) != MODE_INT ) return true ;

if ( ! SUBREG_P ( src ) || ! sf_subreg_operand ( src , mode ) ) return true ;


<s> return ( uint16x4_t ) __builtin_neon_vcgtv4hi ( __a , __b ) ;


<s> MachineInstr & Terminator = * ( -- From -> terminators ( ) . end ( ) ) ; if ( ! Terminator . isUnconditionalBranch ( ) ) { unsigned BrOpc = BBUtils -> isBBInRange ( & Terminator , To , <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( From , Terminator . getDebugLoc ( ) , TII -> get ( BrOpc ) ) ; MIB . addMBB ( To ) ; MIB . addImm ( <STR_LIT> :: AL ) ; MIB . addReg ( <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << DEBUG_PREFIX << <STR_LIT> << From -> getName ( ) << <STR_LIT> << To -> getName ( ) << <STR_LIT> << * MIB . getInstr ( ) ) ; } } ; if ( BBPrevious -> isSuccessor ( BB ) ) FixFallthrough ( BBPrevious , BB ) ; if ( AfterNext && After -> isSuccessor ( AfterNext ) ) FixFallthrough ( After , AfterNext ) ; if ( BBNext && BB -> isSuccessor ( BBNext ) ) FixFallthrough ( BB , BBNext ) ;

BBUtils -> adjustBBOffsetsAfter ( After ) ;


<s> __inline__ static void sh_media_SYNCO ( void ) { __asm__ __volatile__ ( <STR_LIT> ) ;


<s> TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MF -> RenumberBlocks ( ) ; scanFunction ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; dumpBBs ( ) ; ) ; bool MadeChange = false ; while ( relaxBranchInstructions ( ) ) MadeChange = true ;


<s> return ( __m64 ) __builtin_ia32_psraw ( ( __v4hi ) __m , ( long long ) __count ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <NUM_LIT> ) {


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , false , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; assert ( FIST . getNode ( ) && <STR_LIT> ) ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FIST ;


<s> continue ; } ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . shl ( ShiftAmt ) , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> getOpcode ( ) == <STR_LIT> ) { Elts . push_back ( CurrentOp ) ; continue ; } ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . lshr ( ShiftAmt ) , ElementType ) ) ; } break ; case <STR_LIT> : for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { SDValue CurrentOp = SrcOp -> getOperand ( i ) ; if ( CurrentOp -> getOpcode ( ) == <STR_LIT> ) { Elts . push_back ( CurrentOp ) ; continue ; } ND = cast < ConstantSDNode > ( CurrentOp ) ; const APInt & C = ND -> getAPIntValue ( ) ; Elts . push_back ( DAG . getConstant ( C . ashr ( ShiftAmt ) , ElementType ) ) ;


<s> unsigned SPDenormMode = Enable ? FP_DENORM_FLUSH_NONE : Mode . fpDenormModeSPValue ( ) ; if ( ST . hasDenormModeInst ( ) ) { uint32_t DPDenormModeDefault = Mode . fpDenormModeDPValue ( ) ; uint32_t NewDenormModeValue = SPDenormMode | ( DPDenormModeDefault << <NUM_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addImm ( NewDenormModeValue ) ; } else { unsigned SPDenormModeBitField = <STR_LIT> :: ID_MODE | ( <NUM_LIT> << <STR_LIT> :: OFFSET_SHIFT_ ) | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ;

B . buildInstr ( <STR_LIT> ) . addImm ( SPDenormMode ) . addImm ( SPDenormModeBitField ) ;


<s> void <ISA_LIT>BrCCMCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const {


<s> return cast < Function > ( M -> getOrInsertFunction ( getName ( IntrID ) , getType ( M -> getContext ( ) , IntrID ) , AList ) ) ;


<s> if ( String . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , regNum ) ) return - <NUM_LIT> ; return regNum ;


<s> auto Registers = getRegisters ( ) ; if ( Registers . getMap ( ) . empty ( ) ) return ; raw_string_ostream OS ( Blob ) ; <STR_LIT> :: Writer EW ( OS , <STR_LIT> :: little ) ; for ( auto I : Registers . getMap ( ) ) { EW . write ( uint32_t ( I . first . getUInt ( ) ) ) ; EW . write ( uint32_t ( I . second . getUInt ( ) ) ) ;


<s> static void ( * const * pdtor ) ( void ) = & __DTOR_LIST__ + <NUM_LIT> ; while ( pdtor < & __DTOR_END__ ) if ( * pdtor ++ != NULL ) pdtor [ - <NUM_LIT> ] ( ) ; if ( __deregister_frame_info ) __deregister_frame_info ( __EH_FRAME_BEGIN__ ) ;


if ( SUColors . size ( ) == <NUM_LIT> && SUColorsPending . size ( ) == <NUM_LIT> ) PendingColoring [ SU -> NodeNum ] = * SUColors . begin ( ) ;


<s> return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> void addMem256Operands ( MCInst & Inst , unsigned N ) const { addMemOperands ( Inst , N ) ;


<s> const MCSection * getSectionForConstant ( SectionKind Kind ) const override { return ReadOnlySection ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_MBLAZE , false ) {


<s> Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } case AsmToken :: Percent : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( parseRelocOperand ( IdVal ) ) return true ;


<s> switch ( N . getOpcode ( ) ) { default : break ; case <STR_LIT> : { int64_t Val = cast < ConstantSDNode > ( N ) -> getSExtValue ( ) ; int64_t Imm = <NUM_LIT> ; bool Match = ( is12Bit ? isImmZExt12 ( AM . Disp + Val , Imm ) : isImmSExt20 ( AM . Disp + Val , Imm ) ) ; if ( Match ) { AM . Disp = Imm ; return false ; } break ; } case <STR_LIT> : if ( AM . BaseType == <STR_LIT> && AM . Base . Reg . getNode ( ) == <NUM_LIT> ) { AM . BaseType = <STR_LIT> ; AM . Base . FrameIndex = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; return false ; } break ; case <STR_LIT> : { <ISA_LIT>RRIAddressMode Backup = AM ; if ( MatchAddress ( N . getNode ( ) -> getOperand ( <NUM_LIT> ) , AM , is12Bit , Depth + <NUM_LIT> ) ) { AM = Backup ; break ; } if ( AM . IndexReg . getNode ( ) || AM . isRI ) { AM = Backup ; break ; } if ( AM . BaseType == <STR_LIT> && ( ! AM . Base . Reg . getNode ( ) || AM . Base . Reg . getNode ( ) -> hasOneUse ( ) ) ) { AM = Backup ; break ; } SDValue RHS = N . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Zero = CurDAG -> getConstant ( <NUM_LIT> , N . getValueType ( ) ) ; SDValue Neg = CurDAG -> getNode ( <STR_LIT> , dl , N . getValueType ( ) , Zero , RHS ) ; AM . IndexReg = Neg ; if ( Zero . getNode ( ) -> getNodeId ( ) == - <NUM_LIT> || Zero . getNode ( ) -> getNodeId ( ) > N . getNode ( ) -> getNodeId ( ) ) { CurDAG -> RepositionNode ( N . getNode ( ) , Zero . getNode ( ) ) ; Zero . getNode ( ) -> setNodeId ( N . getNode ( ) -> getNodeId ( ) ) ; } if ( Neg . getNode ( ) -> getNodeId ( ) == - <NUM_LIT> || Neg . getNode ( ) -> getNodeId ( ) > N . getNode ( ) -> getNodeId ( ) ) { CurDAG -> RepositionNode ( N . getNode ( ) , Neg . getNode ( ) ) ; Neg . getNode ( ) -> setNodeId ( N . getNode ( ) -> getNodeId ( ) ) ;


<s> void avr_register_target_pragmas ( void ) { int i ; gcc_assert ( ADDR_SPACE_GENERIC == ADDR_SPACE_RAM ) ; for ( i = <NUM_LIT> ; i < ADDR_SPACE_COUNT ; i ++ ) { gcc_assert ( i == avr_addrspace [ i ] . id ) ; if ( ! ADDR_SPACE_GENERIC_P ( i ) ) c_register_addr_space ( avr_addrspace [ i ] . name , avr_addrspace [ i ] . id ) ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( Mangler * mang , const MachineFunction & mf , <ISA_LIT>AsmPrinter & asmprinter ) : Ctx ( mf . getContext ( ) ) , Mang ( mang ) , AsmPrinter ( asmprinter ) {


<s> void <ISA_LIT>ELFStreamer :: emitCFIEndProcImpl ( MCDwarfFrameInfo & Frame ) { Frame . End = getContext ( ) . createTempSymbol ( ) ; MCELFStreamer :: emitLabel ( Frame . End ) ;


<s> case VK_<ISA_LIT>_TLS_LDM_LO10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDM_ADD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDM_CALL : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDO_HIX22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDO_LOX10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LDO_ADD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_IE_HI22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_IE_LO10 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_IE_LD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_IE_LDX : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_IE_ADD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LE_HIX22 : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLS_LE_LOX10 : OS << <STR_LIT> ; break ; } return closeParen ;


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitADD ( Register DefReg , MachineOperand & LHS , MachineOperand & RHS , MachineIRBuilder & MIRBuilder ) const { assert ( LHS . isReg ( ) && RHS . isReg ( ) && <STR_LIT> ) ; MachineRegisterInfo & MRI = MIRBuilder . getMF ( ) . getRegInfo ( ) ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ;

bool Is32Bit = MRI . getType ( LHS . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> break ; default : break ; } if ( GET_CODE ( x ) == MINUS && sparc_pic_register_p ( XEXP ( x , <NUM_LIT> ) ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == LO_SUM && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_MOVE_PIC_LABEL ) { x = XVECEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( x ) == LABEL_REF || ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ) ;


<s> return ( int64x2_t ) __builtin_neon_vshlsv2di ( __a , __b ) ;


<s> bool has<ISA_LIT>XE ( ) const { return <ISA_LIT>ArchVersion >= <ISA_LIT>XE ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; if ( ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasMVEFloatOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; return VT . changeVectorElementTypeToInteger ( ) ;


<s> if ( ( offset & <NUM_LIT> ) != <NUM_LIT> ) return false ; extra = GET_MODE_SIZE ( mode ) - UNITS_PER_WORD ; if ( extra < <NUM_LIT> ) extra = <NUM_LIT> ;

if ( GET_CODE ( addr ) == LO_SUM ) offset = ( ( offset & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( - amount ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - amount ) ; } else if ( amount > <NUM_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( amount ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( amount ) ; } else {


<s> bool sh_extending_set_of_reg :: can_use_as_unextended_reg ( void ) const { if ( ( ext_code == SIGN_EXTEND || ext_code == ZERO_EXTEND ) && ( from_mode == QImode || from_mode == HImode ) && set_src != NULL ) return arith_reg_operand ( XEXP ( set_src , <NUM_LIT> ) , from_mode ) ;


<s> const RegisterBankInfo :: InstructionMapping & <ISA_LIT>RegisterBankInfo :: getInstrMappingForLoad ( const MachineInstr & MI ) const { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; SmallVector < const ValueMapping * , <NUM_LIT> > OpdsMapping ( MI . getNumOperands ( ) ) ; unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , * TRI ) ; LLT LoadTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; Register PtrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;


<s> case CONST_VECTOR : case CONST_DOUBLE : return x == CONST0_RTX ( GET_MODE ( x ) ) ? <NUM_LIT> : <NUM_LIT> ; case CONST : if ( loongarch_symbolic_constant_p ( x , & symbol_type ) ) return loongarch_symbol_insns ( symbol_type , MAX_MACHINE_MODE ) ; split_const ( x , & x , & offset ) ; if ( offset != <NUM_LIT> ) { int n = loongarch_const_insns ( x ) ; if ( n != <NUM_LIT> ) { if ( IMM12_INT ( offset ) ) return n + <NUM_LIT> ; else if ( ! targetm . cannot_force_const_mem ( GET_MODE ( x ) , x ) ) return n + <NUM_LIT> + loongarch_integer_cost ( INTVAL ( offset ) ) ; }


<s> Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( areCandidatesToMergeOrPair ( FirstMI , MI , Flags , TII ) && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI . mayLoadOrStore ( ) && <STR_LIT> ) ; Register MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; bool MIIsUnscaled = TII -> isUnscaledLdSt ( MI ) ; if ( IsUnscaled != MIIsUnscaled ) { int MemSize = getMemScale ( MI ) ; if ( MIIsUnscaled ) { if ( MIOffset % MemSize ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } if ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg ( ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( ModifiedRegUnits . available ( getLdStRegOp ( MI ) . getReg ( ) ) && ! ( MI . mayLoad ( ) && ! UsedRegUnits . available ( getLdStRegOp ( MI ) . getReg ( ) ) ) && ! mayAlias ( MI , MemInsns , AA ) ) {


<s> static int mep_multiple_address_regions ( tree list , bool check_section_attr ) { tree a ; int count_sections = <NUM_LIT> ; int section_attr_count = <NUM_LIT> ;

for ( a = list ; a ; a = TREE_CHAIN ( a ) ) {


<s> if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> && regno >= ARC_FIRST_SIMD_VR_REG && regno <= ARC_LAST_SIMD_VR_REG ) return <NUM_LIT> ;

return CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ;


<s> ++ It , ++ SccNum ) { const std :: vector < MachineBasicBlock * > & SccNext = * It ; for ( MachineBasicBlock * MBB : SccNext ) { OrderedBlks . push_back ( MBB ) ; recordSccnum ( MBB , SccNum ) ; } }


<s> unsigned HandlerReg = <STR_LIT> ; SDValue OutChains [ ] = { DAG . getCopyToReg ( Chain , dl , StackReg , Stack ) , DAG . getCopyToReg ( Chain , dl , HandlerReg , Handler ) } ; Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OutChains ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , DAG . getRegister ( StackReg , <STR_LIT> ) , DAG . getRegister ( HandlerReg , <STR_LIT> ) ) ;


<s> } if ( MemVT . getSizeInBits ( ) > Subtarget . getPreferVectorWidth ( ) ) return false ; if ( MemVT == <STR_LIT> ) return false ; return true ;


<s> case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerSPONENTRY ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerSPLAT_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorOR ( Op , DAG ) ; case <STR_LIT> : return LowerXOR ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> :


<s> } ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto V : * Sources ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; if ( auto * I = dyn_cast < Instruction > ( V ) ) InsertZExt ( I , I ) ; else if ( auto * Arg = dyn_cast < Argument > ( V ) ) { BasicBlock & BB = Arg -> getParent ( ) -> front ( ) ; InsertZExt ( Arg , & * BB . getFirstInsertionPt ( ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } Promoted . insert ( V ) ; }


<s> DiagnosticInfoUnsupported ( SDLoc DLoc , const Function & Fn , const Twine & Desc , SDValue Value ) : DiagnosticInfo ( getKindID ( ) , DS_Error ) , DLoc ( DLoc . getDebugLoc ( ) ) , Description ( Desc ) , Fn ( Fn ) , Value ( Value ) {


<s> const auto & ST = MF . getSubtarget < GCNSubtarget > ( ) ; llvm :: sort ( Regions . begin ( ) , Regions . end ( ) , [ & ST , TargetOcc ] ( const Region * R1 , const Region * R2 ) { return R2 -> MaxPressure . less ( ST , R1 -> MaxPressure , TargetOcc ) ;


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI ;


<s> } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ;

setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ;


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const {

return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> Type * StructType = PType -> getElementType ( ) ; unsigned AS = Func -> getParent ( ) -> getDataLayout ( ) . getAllocaAddrSpace ( ) ; AllocaInst * AllocA = new AllocaInst ( StructType , AS , Arg -> getName ( ) , FirstInst ) ; AllocA -> setAlignment ( Func -> getParamAlignment ( Arg -> getArgNo ( ) ) ) ; Arg -> replaceAllUsesWith ( AllocA ) ;

Value * ArgInParam = new AddrSpaceCastInst ( Arg , PointerType :: get ( StructType , ADDRESS_SPACE_PARAM ) , Arg -> getName ( ) , FirstInst ) ;


<s> void <ISA_LIT>InstrInfo :: setExecutionDomain ( MachineInstr * MI , unsigned Domain ) const { assert ( Domain > <NUM_LIT> && Domain < <NUM_LIT> && <STR_LIT> ) ; uint16_t dom = ( MI -> getDesc ( ) . TSFlags >> <STR_LIT> ) & <NUM_LIT> ; assert ( dom && <STR_LIT> ) ; const unsigned * table = lookup ( MI -> getOpcode ( ) , dom ) ; assert ( table && <STR_LIT> ) ; MI -> setDesc ( get ( table [ Domain - <NUM_LIT> ] ) ) ;


<s> void <ISA_LIT>PassConfig :: addMachineSSAOptimization ( ) {

TargetPassConfig :: addMachineSSAOptimization ( ) ;


<s> const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_ADD ) . legalFor ( { s32 } ) ;

getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForCartesianProduct ( { p0 , s32 } , { p0 } ) ;


<s> SDValue AMDGPUTargetLowering :: LowerINT_TO_FP64 ( SDValue Op , SelectionDAG & DAG , bool Signed ) const { SDLoc SL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BC , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CvtHi = DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , SL , <STR_LIT> , Hi ) ; SDValue CvtLo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ;

SDValue LdExp = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , CvtHi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> if ( regno < <NUM_LIT> ) return regno ; if ( IS_VFP_REGNUM ( regno ) ) { if ( VFP_REGNO_OK_FOR_SINGLE ( regno ) ) return <NUM_LIT> + regno - FIRST_VFP_REGNUM ; else return <NUM_LIT> + ( regno - FIRST_VFP_REGNUM ) / <NUM_LIT> ; }

if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return <NUM_LIT> + regno - FIRST_IWMMXT_GR_REGNUM ;


<s> skipNonTerminators ( Position , * BI ) ; for ( unsigned BTI = <NUM_LIT> , BTE = BI -> NumTerminators ; BTI != BTE ; ++ BTI ) { skipTerminator ( Position , * TI , true ) ; ++ TI ; } }


<s> info = m_vector_manager -> vector_insn_infos [ insn -> uid ( ) ] ; return ; }

if ( fault_first_load_p ( insn -> rtl ( ) ) && info . update_fault_first_load_avl ( insn ) ) return ;


<s> } else { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * BalTgtMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) ; } assert ( LongBrMBB -> size ( ) + BalTgtMBB -> size ( ) == LongBranchSeqSize ) ; } else { Pos = LongBrMBB -> begin ( ) ; LongBrMBB -> addSuccessor ( TgtMBB ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) ) ; assert ( LongBrMBB -> size ( ) == LongBranchSeqSize ) ; } if ( I . Br -> isUnconditionalBranch ( ) ) {

assert ( I . Br -> getDesc ( ) . getNumOperands ( ) == <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>CodeEmitter :: getMachineOpValue ( const MachineInstr & MI , const MachineOperand & MO ) { if ( MO . isReg ( ) ) return <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , <STR_LIT> , true , false ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , <STR_LIT> ) ; else if ( MO . isCPI ( ) ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Reloc = ( ( TID . TSFlags & <STR_LIT> ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; emitConstPoolAddress ( MO . getIndex ( ) , Reloc ) ; } else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , <STR_LIT> ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , <STR_LIT> ) ; else { errs ( ) << MO ; llvm_unreachable ( <NUM_LIT> ) ; } return <NUM_LIT> ;


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue Lane = Op . getOperand ( <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Lane ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getValueType ( VT ) ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Op ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> auto & Table = MemUnfoldTable -> Table ; auto I = std :: lower_bound ( Table . begin ( ) , Table . end ( ) , MemOp ) ; if ( I != Table . end ( ) && I -> KeyOp == MemOp ) return & * I ; return nullptr ;


<s> FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_ABS_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_ABS_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_TLSGD : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_TLSLDM : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_DTP_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_DTP_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOTTPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_TP_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_TP_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOT_LO16 : FixupKind = <STR_LIT> ; break ; } Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) ) ) ; return <NUM_LIT> ;


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;

assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;


<s> SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; uint64_t COffsetVal = cast < ConstantSDNode > ( N1 ) -> getZExtValue ( ) ; if ( isUInt < <NUM_LIT> > ( COffsetVal ) ) { Addr = N0 ; OffsetVal = COffsetVal ; } } VAddr = Addr ;

Offset = CurDAG -> getTargetConstant ( OffsetVal , SDLoc ( ) , <STR_LIT> ) ;


<s> O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS -> getInstruction ( ) ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { sz = PtrVT . getSizeInBits ( ) ; } else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ;


<s> bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( Val , Valid ) ; if ( Valid ) O << StringRef ( Name . str ( ) ) . upper ( ) ; else O << <STR_LIT> << Val ;


<s> O << <ISA_LIT>RegisterInfo :: stripRegisterPrefix ( RegName ) ; return ; } case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_ConstantPoolIndex : O << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; return ; case MachineOperand :: MO_BlockAddress : GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { PrintSymbolOperand ( MO , O ) ; return ; } default :

O << <STR_LIT> << ( unsigned ) MO . getType ( ) << <STR_LIT> ;


<s> MachineOperand & Op = MI . getOperand ( I ) ; if ( ! Op . isImm ( ) && ! ( Op . isReg ( ) && ! TRI -> isVGPR ( * MRI , Op . getReg ( ) ) ) ) continue ; if ( Desc . OpInfo [ I ] . RegClass == - <NUM_LIT> || ! TRI -> hasVGPRs ( TRI -> getRegClass ( Desc . OpInfo [ I ] . RegClass ) ) ) continue ; unsigned VGPR = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto Copy = BuildMI ( * MI . getParent ( ) , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , VGPR ) ; if ( Op . isImm ( ) ) Copy . addImm ( Op . getImm ( ) ) ;

else if ( Op . isReg ( ) ) Copy . addReg ( Op . getReg ( ) , Op . isKill ( ) ? RegState :: Kill : <NUM_LIT> , Op . getSubReg ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printS5ImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { int Value = MI -> getOperand ( OpNo ) . getImm ( ) ;

Value = SignExtend32 < <NUM_LIT> > ( Value ) ;


<s> LSBaseSDNode * BN = cast < LSBaseSDNode > ( Op . getNode ( ) ) ; assert ( BN -> isUnindexed ( ) ) ; MVT MemTy = BN -> getMemoryVT ( ) . getSimpleVT ( ) ; if ( ! isHvxPairTy ( MemTy ) ) return Op ; const SDLoc & dl ( Op ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; MVT SingleTy = typeSplit ( MemTy ) . first ; SDValue Chain = BN -> getChain ( ) ; SDValue Base0 = BN -> getBasePtr ( ) ; SDValue Base1 = DAG . getMemBasePlusOffset ( Base0 , HwLen , dl ) ; MachineMemOperand * MOp0 = nullptr , * MOp1 = nullptr ; if ( MachineMemOperand * MMO = BN -> getMemOperand ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ;

MOp0 = MF . getMachineMemOperand ( MMO , <NUM_LIT> , HwLen ) ;


<s> if ( ! target || ! register_operand ( target , mode ) ) target = gen_reg_rtx ( mode ) ; if ( pa_expand_compare_and_swap_loop ( mem , target , val , NULL_RTX ) ) return target ; } return NULL_RTX ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ;


<s> int FrameAddrIndex = FuncInfo -> getFAIndex ( ) ; if ( ! FrameAddrIndex ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; FrameAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , <NUM_LIT> , false ) ; FuncInfo -> setFAIndex ( FrameAddrIndex ) ; } return DAG . getFrameIndex ( FrameAddrIndex , VT ) ; } unsigned FrameReg = RegInfo -> getPtrSizedFrameRegister ( DAG . getMachineFunction ( ) ) ; SDLoc dl ( Op ) ;

unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>InsertWaits ( TargetMachine & tm ) { return new <ISA_LIT>InsertWaits ( tm ) ;


<s> MachineLocation <ISA_LIT>AsmPrinter :: getDebugValueLocation ( const MachineInstr * MI ) const { MachineLocation Location ; assert ( MI -> getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) Location . set ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; else { DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; }


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> } } if ( Index != - <NUM_LIT> && ( Opcode == Instruction :: ExtractElement || Opcode == Instruction :: InsertElement ) ) { std :: pair < InstructionCost , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Val ) ; if ( ! LT . second . isVector ( ) ) return <NUM_LIT> ; unsigned NumElts = LT . second . getVectorNumElements ( ) ; unsigned SubNumElts = NumElts ; Index = Index % NumElts ; if ( LT . second . getSizeInBits ( ) > <NUM_LIT> ) { assert ( ( LT . second . getSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; unsigned NumSubVecs = LT . second . getSizeInBits ( ) / <NUM_LIT> ; SubNumElts = NumElts / NumSubVecs ; if ( SubNumElts <= Index ) { RegisterFileMoveCost += ( Opcode == Instruction :: InsertElement ? <NUM_LIT> : <NUM_LIT> ) ; Index %= SubNumElts ; } } if ( Index == <NUM_LIT> ) { if ( ScalarType -> isFloatingPointTy ( ) ) return RegisterFileMoveCost ; if ( ScalarType -> isIntegerTy ( ) && Opcode == Instruction :: ExtractElement ) return <NUM_LIT> + RegisterFileMoveCost ; } int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; MVT MScalarTy = LT . second . getScalarType ( ) ; if ( ST -> useSLMArithCosts ( ) ) if ( auto * Entry = CostTableLookup ( SLMCostTbl , ISD , MScalarTy ) ) return Entry -> Cost + RegisterFileMoveCost ; if ( ( MScalarTy == <STR_LIT> && ST -> hasSSE2 ( ) ) || ( MScalarTy . isInteger ( ) && ST -> hasSSE41 ( ) ) ) return <NUM_LIT> + RegisterFileMoveCost ;

if ( MScalarTy == <STR_LIT> && ST -> hasSSE41 ( ) && Opcode == Instruction :: InsertElement ) return <NUM_LIT> + RegisterFileMoveCost ;


<s> fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ;


<s> inline static bool isLocalToFunc ( std :: string & FuncName , std :: string & VarName ) { if ( VarName . find ( FuncName + <STR_LIT> ) != std :: string :: npos || VarName . find ( FuncName + <STR_LIT> ) != std :: string :: npos ) return true ;


<s> static void GetMemOperands ( const MachineInstr * MI , unsigned long & baseReg , unsigned long & indexReg ) { if ( ! MI -> memoperands_empty ( ) && ! ( ( MI -> getFlags ( ) & MachineInstr :: FrameSetup ) || ( MI -> getFlags ( ) & MachineInstr :: FrameDestroy ) ) ) { int index = getMemLocation ( MI ) ; baseReg = MI -> getOperand ( index ) . getReg ( ) ; indexReg = MI -> getOperand ( index + <NUM_LIT> ) . getReg ( ) ; } else { baseReg = <STR_LIT> ;


<s> return ( ( qword ) ( vec_sll ( ( vec_uchar16 ) ( a ) , x ) ) ) ;


<s> if ( RC == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) . addFrameIndex ( FrameIdx ) . addReg ( <STR_LIT> ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) . addFrameIndex ( FrameIdx ) . addReg ( <STR_LIT> ) ; else if ( RC == <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) . addFrameIndex ( FrameIdx ) . addReg ( <STR_LIT> ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( ! EnableBasePointer ) return false ;

bool CantUseFP = needsStackRealignment ( MF ) ;


<s> const int NumBytes = VT . getSizeInBits ( ) / <NUM_LIT> ; const int NumEltBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; assert ( ( Subtarget . hasSSSE3 ( ) && VT . is128BitVector ( ) ) || ( Subtarget . hasAVX2 ( ) && VT . is256BitVector ( ) ) || ( Subtarget . hasBWI ( ) && VT . is512BitVector ( ) ) ) ; SmallVector < SDValue , <NUM_LIT> > PSHUFBMask ( NumBytes ) ; SDValue ZeroMask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue V ; for ( int i = <NUM_LIT> ; i < NumBytes ; ++ i ) { int M = Mask [ i / NumEltBytes ] ; if ( M < <NUM_LIT> ) { PSHUFBMask [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; continue ; } if ( Zeroable [ i / NumEltBytes ] ) { PSHUFBMask [ i ] = ZeroMask ; continue ; } SDValue SrcV = ( M >= Size ? V2 : V1 ) ; if ( V && V != SrcV ) return SDValue ( ) ; V = SrcV ;


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { assert ( Expr && <STR_LIT> ) ; if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;

else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;


<s> } } else { rtx move = mode == QImode ? gen_movqi ( to , from ) : gen_movhi ( to , from ) ; EM ( move ) ; if ( where == NULL_RTX ) emit_insn ( move ) ; else if ( before ) emit_insn_before ( move , where ) ; else { rtx note = find_reg_note ( where , REG_EH_REGION , NULL_RTX ) ; if ( note != NULL_RTX ) { add_reg_note ( move , REG_EH_REGION , XEXP ( note , <NUM_LIT> ) ) ; remove_note ( where , note ) ; } emit_insn_after ( move , where ) ; }

if ( before ) record_content ( to , from ) ;


<s> void <ISA_LIT>AsmPrinter :: printHex32 ( unsigned int Value ) { O << <STR_LIT> ; for ( int i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) O << utohexstr ( ( Value & ( <NUM_LIT> << ( i * <NUM_LIT> ) ) ) >> ( i * <NUM_LIT> ) ) ;


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalizeOps ( ) && <STR_LIT> ( In . getNode ( ) ) && In . hasOneUse ( ) ) { auto * Ld = cast < LoadSDNode > ( In ) ; if ( Ld -> isSimple ( ) ) { MVT SVT = In . getSimpleValueType ( ) . getVectorElementType ( ) ; <STR_LIT> Ext = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; EVT MemVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , VT . getVectorNumElements ( ) ) ; if ( TLI . isLoadExtLegal ( Ext , VT , MemVT ) ) { SDValue Load = DAG . getExtLoad ( Ext , SDLoc ( N ) , VT , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , MemVT , Ld -> getOriginalAlign ( ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ;

DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ;


<s> const char * SpillFun = getSpillFunctionFor ( MaxReg , SK_ToMem ) ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; MachineInstr * SaveRegsCall = BuildMI ( MBB , MI , DL , HII . get ( <STR_LIT> ) ) . addExternalSymbol ( SpillFun ) ; addCalleeSaveRegistersAsImpOperand ( SaveRegsCall , MaxReg , false ) ; for ( unsigned I = <NUM_LIT> ; I < CSI . size ( ) ; ++ I ) MBB . addLiveIn ( CSI [ I ] . getReg ( ) ) ; return true ; } for ( unsigned i = <NUM_LIT> , n = CSI . size ( ) ; i < n ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsKill = ! HRI . isEHReturnCalleeSaveReg ( Reg ) ;


return ( poly64x2_t ) __builtin_neon_vreinterpretv2div4si ( __a ) ;


<s> unsigned ConstCount ; BankSwizzle TransBS = ALU_VEC_012_SCL_210 ; for ( unsigned i = <NUM_LIT> , e = IG . size ( ) ; i < e ; ++ i ) { IGSrcs . push_back ( ExtractSrcs ( * IG [ i ] , PV , ConstCount ) ) ; unsigned Op = getOperandIdx ( IG [ i ] -> getOpcode ( ) , <STR_LIT> :: bank_swizzle ) ; ValidSwizzle . push_back ( ( <ISA_LIT>InstrInfo :: BankSwizzle ) IG [ i ] -> getOperand ( Op ) . getImm ( ) ) ; } std :: vector < std :: pair < int , unsigned >> TransOps ; if ( ! isLastAluTrans ) return FindSwizzleForVectorSlot ( IGSrcs , ValidSwizzle , TransOps , TransBS ) ; TransOps = std :: move ( IGSrcs . back ( ) ) ; IGSrcs . pop_back ( ) ; ValidSwizzle . pop_back ( ) ; static const <ISA_LIT>InstrInfo :: BankSwizzle TransSwz [ ] = { ALU_VEC_012_SCL_210 , ALU_VEC_021_SCL_122 , ALU_VEC_120_SCL_212 , ALU_VEC_102_SCL_221 } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) {


<s> auto One = B . buildFConstant ( S64 , <NUM_LIT> ) ; auto DivScale0 = B . buildIntrinsic ( <STR_LIT> , { S64 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ; auto NegDivScale0 = B . buildFNeg ( S64 , DivScale0 . getReg ( <NUM_LIT> ) , Flags ) ; auto Rcp = B . buildIntrinsic ( <STR_LIT> , { S64 } , false ) . addUse ( DivScale0 . getReg ( <NUM_LIT> ) ) . setMIFlags ( Flags ) ; auto Fma0 = B . buildFMA ( S64 , NegDivScale0 , Rcp , One , Flags ) ; auto Fma1 = B . buildFMA ( S64 , Rcp , Fma0 , Rcp , Flags ) ; auto Fma2 = B . buildFMA ( S64 , NegDivScale0 , Fma1 , One , Flags ) ;

auto DivScale1 = B . buildIntrinsic ( <STR_LIT> , { S64 , S1 } , false ) . addUse ( LHS ) . addUse ( RHS ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flags ) ;


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {


<s> return ( N -> getOpcode ( ) == <STR_LIT> && N -> hasOneUse ( ) ) ; } ; if ( ! N -> hasOneUse ( ) || ! N -> getSimpleValueType ( <NUM_LIT> ) . bitsGE ( <STR_LIT> ) || ! isORCandidate ( N -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; auto isSetCCCandidate = [ ] ( SDValue N ) { return N -> getOpcode ( ) == <STR_LIT> && N -> hasOneUse ( ) && <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isNullConstant ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) && N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . bitsGE ( <STR_LIT> ) ; } ; SDNode * OR = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDValue LHS = OR -> getOperand ( <NUM_LIT> ) ; SDValue RHS = OR -> getOperand ( <NUM_LIT> ) ; SmallVector < SDNode * , <NUM_LIT> > ORNodes ; while ( ( ( isORCandidate ( LHS ) && isSetCCCandidate ( RHS ) ) || ( isORCandidate ( RHS ) && isSetCCCandidate ( LHS ) ) ) ) { ORNodes . push_back ( OR ) ; OR = ( LHS -> getOpcode ( ) == <STR_LIT> ) ? LHS . getNode ( ) : RHS . getNode ( ) ; LHS = OR -> getOperand ( <NUM_LIT> ) ; RHS = OR -> getOperand ( <NUM_LIT> ) ; } if ( ! ( isSetCCCandidate ( LHS ) && isSetCCCandidate ( RHS ) ) || ! isORCandidate ( SDValue ( OR , <NUM_LIT> ) ) ) return SDValue ( ) ; EVT VT = OR -> getValueType ( <NUM_LIT> ) ; SDValue NewLHS = lower<ISA_LIT>CmpEqZeroToCtlzSrl ( LHS , VT , DAG ) ;


<s> default : return false ; } break ; case <NUM_LIT> : switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vrev32v16qi ; break ; case E_V8QImode : gen = gen_neon_vrev32v8qi ; break ; case E_V8HImode : gen = gen_neon_vrev64v8hi ; break ; case E_V4HImode : gen = gen_neon_vrev64v4hi ; break ; case E_V8HFmode : gen = gen_neon_vrev64v8hf ; break ; case E_V4HFmode : gen = gen_neon_vrev64v4hf ; break ; default : return false ; } break ; case <NUM_LIT> : switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vrev16v16qi ; break ; case E_V8QImode : gen = gen_neon_vrev16v8qi ; break ; case E_V8HImode : gen = gen_neon_vrev32v8hi ; break ; case E_V4HImode : gen = gen_neon_vrev32v4hi ; break ; case E_V4SImode : gen = gen_neon_vrev64v4si ; break ; case E_V2SImode : gen = gen_neon_vrev64v2si ; break ; case E_V4SFmode : gen = gen_neon_vrev64v4sf ; break ; case E_V2SFmode : gen = gen_neon_vrev64v2sf ; break ; default : return false ; } break ; default : return false ; } for ( i = <NUM_LIT> ; i < nelt ; i += diff + <NUM_LIT> ) for ( j = <NUM_LIT> ; j <= diff ; j += <NUM_LIT> ) { gcc_assert ( i + j < nelt ) ;

if ( d -> perm [ i + j ] != i + diff - j ) return false ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( N -> getMaskElt ( i + <NUM_LIT> ) , i ) ) return false ; return true ;


<s> static int bfin_memory_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t rclass , bool in ATTRIBUTE_UNUSED ) { if ( ! reg_class_subset_p ( rclass , DPREGS ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> return ( __m64 ) __builtin_arm_wsrad ( __m , __count ) ;


<s> return ( MCInstD . TSFlags >> SecondImmOpStart ) & <ISA_LIT>II :: SecondImmOpMask ;


if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return make_vector < unsigned > ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> ) ;


<s> if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) > <NUM_LIT> ) return SDValue ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetRegisterInfo * RegInfo = getTargetMachine ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) ;

return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , SDLoc ( Op ) , RegInfo -> getFrameRegister ( MF ) , <STR_LIT> ) ;


<s> switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( Subtarget -> hasAVX512 ( ) ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( SrcReg ) ; return ResultReg ; } case <STR_LIT> : return fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; case <STR_LIT> : return fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , true , <STR_LIT> ) ; case <STR_LIT> : return SrcReg ; case <STR_LIT> : { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) , ResultReg ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg ) . addImm ( <STR_LIT> ) ; return ResultReg ; } } } unsigned Opc = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( Subtarget -> hasAVX512 ( ) ) return <NUM_LIT> ; VT = <STR_LIT> ; LLVM_FALLTHROUGH ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : { if ( isUInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else if ( isInt < <NUM_LIT> > ( Imm ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; break ; } }

if ( VT == <STR_LIT> && Opc == <STR_LIT> ) {


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true , false ) ;

SDValue FIST = Vals . first , StackSlot = Vals . second ;


<s> void addBiasedOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isBiased ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Biased . Val ) ) ;


<s> MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . makeFrame ( <STR_LIT> , StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( ! CSI . empty ( ) ) { const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const CalleeSavedInfo & I : CSI ) { int64_t Offset = MFI . getObjectOffset ( I . getFrameIdx ( ) ) ; Register Reg = I . getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ;

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetNoOddSPReg ( ) { <ISA_LIT>TargetStreamer :: emitDirectiveSetNoOddSPReg ( ) ; OS << <STR_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFROUND64 ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; SDValue A = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue AbsA = DAG . getNode ( <STR_LIT> , SL , VT , A ) ;

SDValue AdjustedA = DAG . getNode ( <STR_LIT> , SL , VT , AbsA , DAG . getConstantFP ( <NUM_LIT> , SL , VT ) ) ;


<s> Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'c' : if ( type -> isIntegerTy ( ) ) weight = CW_SpecificReg ; break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'N' : case 'O' : case 'P' : if ( isa < ConstantInt > ( CallOperandVal ) ) weight = CW_Constant ; break ; case 'R' : weight = CW_Memory ; break ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> int32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result ;


<s> auto MIB = BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( createTypeVReg ( CurMF -> getRegInfo ( ) ) ) . addImm ( static_cast < uint32_t > ( SC ) ) . addUse ( get<ISA_LIT>TypeID ( BaseType ) ) ;

return restOfCreate<ISA_LIT>Type ( LLVMTy , MIB ) ;


<s> Streamer . visitUsedExpr ( * getSubExpr ( ) ) ;


<s> static void rs6000_move_block_from_reg ( int regno , rtx x , int nregs ) { int i ; machine_mode reg_mode = TARGET_32BIT ? SImode : DImode ; if ( nregs == <NUM_LIT> ) return ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { rtx tem = adjust_address_nv ( x , reg_mode , i * GET_MODE_SIZE ( reg_mode ) ) ; if ( reload_completed ) { if ( ! strict_memory_address_p ( reg_mode , XEXP ( tem , <NUM_LIT> ) ) ) tem = NULL_RTX ; else tem = simplify_gen_subreg ( reg_mode , x , BLKmode , i * GET_MODE_SIZE ( reg_mode ) ) ;


<s> const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ;

OutStreamer . EmitRawText ( <STR_LIT> + Twine ( getRegisterName ( stackReg ) ) + <STR_LIT> + Twine ( stackSize ) + <STR_LIT> + Twine ( getRegisterName ( returnReg ) ) ) ;


<s> static void rl78_insert_attributes ( tree decl , tree * attributes ATTRIBUTE_UNUSED ) {

if ( TARGET_ES0 && TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && TREE_ADDRESSABLE ( decl ) && TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) == ADDR_SPACE_GENERIC ) {


<s> if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) WrapperKind = <STR_LIT> ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetExternalSymbol ( Sym , PtrVT , OpFlag ) ; SDLoc DL ( Op ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ;

if ( isPositionIndependent ( ) && ! Subtarget . is64Bit ( ) ) {


<s> if ( num_suffix == <NUM_LIT> ) sprintf ( buffer , <STR_LIT> , funcname , modename ) ; else sprintf ( buffer , <STR_LIT> , funcname , modename , num_suffix ) ;

set_optab_libfunc ( optable , mode , buffer ) ;


<s> bool <ISA_LIT>AsmParser :: emit ( MCInst & Inst , SMLoc const & Loc , MCStreamer & Out ) const { Inst . setLoc ( Loc ) ; Out . emitInstruction ( Inst , STI ) ; return false ;


<s> static bool isDGEMM ( unsigned Opcode ) { return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> static DecodeStatus DecodeMemoryValue ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Register = ( Insn >> <NUM_LIT> ) & <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateReg ( Register + <NUM_LIT> ) ) ; unsigned Offset = ( Insn & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Offset ) ) ) ;


<s> if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { if ( STI . hasE2 ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { assert ( DestReg < <STR_LIT> ) ; assert ( DestReg < <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , RegState :: Define ) . addReg ( SrcReg , RegState :: Define ) . addReg ( DestReg , getKillRegState ( true ) ) . addReg ( DestReg , getKillRegState ( true ) ) . addReg ( SrcReg , getKillRegState ( true ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , RegState :: Define | getDeadRegState ( KillSrc ) ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; } return ; } unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2df && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v3df && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v2df && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3df && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ;


<s> RegisterTarget < Triple :: loongarch32 , false > X ( getThe<ISA_LIT>32Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: loongarch64 , false > Y ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;

bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;


<s> case <STR_LIT> : { SDValue MulLHS = N -> getOperand ( <NUM_LIT> ) ; SDValue MulRHS = N -> getOperand ( <NUM_LIT> ) ; SDNode * Mul = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , MulLHS , MulRHS ) ; Mul = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( Mul , <NUM_LIT> ) , MulLHS , MulRHS ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , SDValue ( Mul , <NUM_LIT> ) , MulRHS , MulLHS ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue MulLHS = N -> getOperand ( <NUM_LIT> ) ; SDValue MulRHS = N -> getOperand ( <NUM_LIT> ) ;

unsigned OldOpcode = N -> getOpcode ( ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectScalarSSELoad ( SDNode * Root , SDValue N , SDValue & Base , SDValue & Scale , SDValue & Index , SDValue & Disp , SDValue & Segment , SDValue & PatternNodeWithChain ) { if ( N . getOpcode ( ) == <STR_LIT> ) { PatternNodeWithChain = N . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( PatternNodeWithChain . getNode ( ) ) && PatternNodeWithChain . hasOneUse ( ) && IsProfitableToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) && IsLegalToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) ) { LoadSDNode * LD = cast < LoadSDNode > ( PatternNodeWithChain ) ; if ( ! SelectAddr ( Root , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ) return false ; return true ; } } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getNode ( ) -> hasOneUse ( ) && <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getNode ( ) ) && N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . hasOneUse ( ) && IsProfitableToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) && IsLegalToFold ( N . getOperand ( <NUM_LIT> ) , N . getNode ( ) , Root ) ) { LoadSDNode * LD = cast < LoadSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( ! SelectAddr ( Root , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ) return false ; PatternNodeWithChain = SDValue ( LD , <NUM_LIT> ) ;


<s> assert ( Fixup . getOffset ( ) + Size <= Data . size ( ) && <STR_LIT> ) ; int64_t SignedValue = static_cast < int64_t > ( Value ) ; if ( ( Target . isAbsolute ( ) || IsResolved ) && getFixupKindInfo ( Fixup . getKind ( ) ) . Flags & MCFixupKindInfo :: FKF_IsPCRel ) { if ( Size > <NUM_LIT> && ! isIntN ( Size * <NUM_LIT> , SignedValue ) ) Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> + Twine ( SignedValue ) + <STR_LIT> + Twine ( Size ) + ( ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; } else { assert ( ( Size == <NUM_LIT> || isIntN ( Size * <NUM_LIT> + <NUM_LIT> , SignedValue ) ) && <STR_LIT> ) ; }

for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) Data [ Fixup . getOffset ( ) + i ] = uint8_t ( Value >> ( i * <NUM_LIT> ) ) ;


<s> DebugLoc DL = Op . getDebugLoc ( ) ; SDValue Base ; int64_t Offset ; if ( ! LD -> isVolatile ( ) && IsWordAlignedBasePlusConstantOffset ( BasePtr , Base , Offset ) ) { if ( Offset % <NUM_LIT> == <NUM_LIT> ) { return DAG . getLoad ( getPointerTy ( ) , DL , Chain , BasePtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } SDValue LowOffset = DAG . getConstant ( Offset & ~ <NUM_LIT> , <STR_LIT> ) ; SDValue HighOffset = DAG . getConstant ( ( Offset & ~ <NUM_LIT> ) + <NUM_LIT> , <STR_LIT> ) ; SDValue LowShift = DAG . getConstant ( ( Offset & <NUM_LIT> ) * <NUM_LIT> , <STR_LIT> ) ; SDValue HighShift = DAG . getConstant ( <NUM_LIT> - ( Offset & <NUM_LIT> ) * <NUM_LIT> , <STR_LIT> ) ; SDValue LowAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Base , LowOffset ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Base , HighOffset ) ; SDValue Low = DAG . getLoad ( getPointerTy ( ) , DL , Chain , LowAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue High = DAG . getLoad ( getPointerTy ( ) , DL , Chain , HighAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue LowShifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Low , LowShift ) ;

SDValue HighShifted = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , High , HighShift ) ;


<s> rtx inc ; if ( amount == <NUM_LIT> ) return ; inc = GEN_INT ( amount ) ; if ( ! CONST_OK_FOR_K ( amount ) ) { rtx reg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; inc = emit_move_insn ( reg , inc ) ; if ( in_prologue ) F ( inc ) ; inc = reg ; } inc = emit_insn ( gen_addsi3_clobber_flags ( stack_pointer_rtx , stack_pointer_rtx , inc ) ) ;


<s> <ISA_LIT>AsmPrinter :: <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> if ( isBaseRegConflictPossible ( DAG , ClobberSet ) ) return SDValue ( ) ; if ( ! Subtarget . hasERMSB ( ) && ! ( Align & <NUM_LIT> ) ) { if ( Align & <NUM_LIT> ) Repeats . AVT = <STR_LIT> ; else if ( Align & <NUM_LIT> ) Repeats . AVT = <STR_LIT> ; else Repeats . AVT = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( Repeats . BytesLeft ( ) > <NUM_LIT> && DAG . getMachineFunction ( ) . getFunction ( ) . optForMinSize ( ) ) { Repeats . AVT = <STR_LIT> ; } } bool Use64BitRegs = Subtarget . isTarget64BitLP64 ( ) ; SDValue InFlag ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , DAG . getIntPtrConstant ( Repeats . Count ( ) , dl ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Use64BitRegs ? <STR_LIT> : <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , DAG . getValueType ( Repeats . AVT ) , InFlag } ; SDValue RepMovs = DAG . getNode ( <STR_LIT> , dl , Tys , Ops ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; if ( Repeats . BytesLeft ( ) ) {

unsigned Offset = Repeats . Size - Repeats . BytesLeft ( ) ;


<s> if ( ! ia64_dconst_0_5_rtx ) { REAL_VALUE_TYPE rv ; real_from_string ( & rv , <STR_LIT> ) ;

ia64_dconst_0_5_rtx = const_double_from_real_value ( rv , DFmode ) ;


<s> if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { if ( isSingleInputShuffleMask ( Mask ) ) { int PSHUFDMask [ ] = { - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) { PSHUFDMask [ <NUM_LIT> * i ] = <NUM_LIT> * RepeatedMask [ i ] ; PSHUFDMask [ <NUM_LIT> * i + <NUM_LIT> ] = <NUM_LIT> * RepeatedMask [ i ] + <NUM_LIT> ; } return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } } if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DL , DAG ) ) ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ;

if ( ! ( Subtarget -> hasAVX2 ( ) && ( isShuffleMaskInputInPlace ( <NUM_LIT> , Mask ) || isShuffleMaskInputInPlace ( <NUM_LIT> , Mask ) ) ) ) if ( SDValue Result = lowerVectorShuffleByMerging128BitLanes ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Result ;


<s> if ( Fixup . getKind ( ) == FK_SecRel_4 || Fixup . getKind ( ) == FK_SecRel_8 ) { assert ( Value == <NUM_LIT> ) ; } else if ( Fixup . getKind ( ) == FK_Data_4 || Fixup . getKind ( ) == FK_Data_8 ) { unsigned Size = Fixup . getKind ( ) == FK_Data_4 ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { unsigned Idx = IsLittleEndian ? i : Size - i - <NUM_LIT> ; Data [ Fixup . getOffset ( ) + Idx ] = uint8_t ( Value >> ( i * <NUM_LIT> ) ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - <NUM_LIT> ) / <NUM_LIT> ) ; if ( IsLittleEndian ) { Data [ Fixup . getOffset ( ) + <NUM_LIT> ] = Value & <NUM_LIT> ; Data [ Fixup . getOffset ( ) + <NUM_LIT> ] = Value >> <NUM_LIT> ; } else {


<s> initialize<ISA_LIT>MovCoalescerPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( SrcReg , SrcLoReg , SrcHiReg ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ;

buildMI ( MBB , MBBI , OpLo ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcLoReg , getKillRegState ( SrcIsKill ) ) ;


<s> return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) + offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress :

return LowerSymbolOperand ( MO , MOTy , offset ) ;


<s> static void inputOne ( IO & YamlIO , StringRef Key , BBNumberMap & SrcToUnwindDest ) {

YamlIO . mapRequired ( Key . str ( ) . c_str ( ) , SrcToUnwindDest [ std :: atoi ( Key . str ( ) . c_str ( ) ) ] ) ;


<s> printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> ) ; printf ( <STR_LIT> , ARCH ) ; create_insn_code_compression_table ( ) ; find_sequences ( s , best_solution ) ; printf ( <STR_LIT> <STR_LIT> , ARCH , ARCH ) ; const char * comma_separator = <STR_LIT> ; ExpressionTreeMap :: iterator i ( best_solution . begin ( ) ) ; for ( ; i != best_solution . end ( ) ; ++ i ) { ExpressionTree * s = ( * i ) . second ; const MUL_TYPE n = ( * i ) . first ; if ( n == <NUM_LIT> || n == <NUM_LIT> ) { continue ; } if ( ! tilepro_emit ( n , num_ops ( s ) ) ) continue ; if ( ! tilegx_emit ( n , num_ops ( s ) ) ) continue ; printf ( <STR_LIT> , comma_separator ) ; const MUL_TYPE int_min = INT32_MIN ; const MUL_TYPE int_min = INT64_MIN ; if ( n == int_min ) { printf ( <STR_LIT> , n + <NUM_LIT> , ( unsigned ) n ) ;

printf ( <STR_LIT> , n + <NUM_LIT> , ( unsigned MUL_TYPE ) n ) ;


<s> for ( MachineInstr * DeadMI : DeadInstrs ) DeadMI -> eraseFromParent ( ) ;


<s> MCOp = GetSymbolRef ( GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = GetSymbolRef ( getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand :: MO_FPImmediate : { const ConstantFP * Cnt = MO . getFPImm ( ) ; const APFloat & Val = Cnt -> getValueAPF ( ) ; switch ( Cnt -> getType ( ) -> getTypeID ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; break ; case Type :: FloatTyID : MCOp = MCOperand :: createExpr ( <ISA_LIT>FloatMCExpr :: createConstantFPSingle ( Val , OutContext ) ) ; break ; case Type :: DoubleTyID :

MCOp = MCOperand :: createExpr ( <ISA_LIT>FloatMCExpr :: createConstantFPDouble ( Val , OutContext ) ) ;


<s> const MCInstrDesc & MCID = MI . getDesc ( ) ; int CondNo = getCondSrcNoFromDesc ( MCID ) ; if ( CondNo < <NUM_LIT> ) return <STR_LIT> ; CondNo += MCID . getNumDefs ( ) ;

return static_cast < <STR_LIT> > ( MI . getOperand ( CondNo ) . getImm ( ) ) ;


<s> if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) < UNITS_PER_WORD ) return word_mode ;


<s> bool <ISA_LIT>FrameLowering :: canUseAsEpilogue ( const MachineBasicBlock & MBB ) const { const MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * TmpMBB = const_cast < MachineBasicBlock * > ( & MBB ) ; const auto * RVFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! RVFI -> useSaveRestoreLibCalls ( * MF ) ) return true ;

if ( MBB . succ_size ( ) > <NUM_LIT> ) return false ;


<s> unsigned NumSubElem = VVT . getVectorNumElements ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumSubElem ; ++ j ) { Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SubOp , DAG . getIntPtrConstant ( j , dl ) ) ) ; } } return DAG . getNode ( <STR_LIT> , dl , Node -> getValueType ( <NUM_LIT> ) , Ops ) ;


<s> unsigned FrameReg = RegInfo -> getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , PtrVT ) ;

while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , DL , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> DirectXPassConfig ( DirectXTargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> static __inline qword si_ilh ( signed short imm ) {

return ( ( qword ) ( vec_splat ( ( vec_short8 ) ( si_from_short ( imm ) ) , <NUM_LIT> ) ) ) ;


<s> if ( eatTerm ( S , <STR_LIT> ) ) return eatLengthPrefixedName ( S ) ; return StringRef ( ) ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; Reserved . set ( <STR_LIT> ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; Reserved . set ( <STR_LIT> ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; Register BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <NUM_LIT> ) ; for ( MCSubRegIterator I ( BasePtr , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) { if ( ( Imm . getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) return TTI :: TCC_Basic ; return <NUM_LIT> * TTI :: TCC_Basic ; } } return <NUM_LIT> * TTI :: TCC_Basic ;


<s> if ( VT . getSimpleVT ( ) . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 -> getOpcode ( ) != <STR_LIT> && ! ( Op0 -> isMachineOpcode ( ) && Op0 -> getMachineOpcode ( ) == <STR_LIT> ) ) return SDValue ( ) ; uint64_t idx = cast < ConstantSDNode > ( Op0 -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Op0 -> getOpcode ( ) == <STR_LIT> ) { if ( Op0 -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) != idx && idx != <NUM_LIT> ) return SDValue ( ) ; } else if ( Op0 -> getMachineOpcode ( ) == <STR_LIT> ) { if ( idx != <STR_LIT> ) return SDValue ( ) ; idx = <NUM_LIT> ;


<s> ReverseIter Filler ; RegDU . init ( Slot ) ; MachineBasicBlock :: iterator SlotI = Slot ;

if ( ! searchRange ( MBB , ++ SlotI . getReverse ( ) , MBB . rend ( ) , RegDU , MemDU , Slot , Filler ) ) return false ;


<s> return ( __a + ( __b * __aarch64_vget_lane_any ( __c , __lane ) ) ) ;


return - ( <NUM_LIT> << <NUM_LIT> ) * stackSlotSize ( ) ;


<s> if ( Opcode == Instruction :: Store && Src -> isVectorTy ( ) && Alignment != <NUM_LIT> && Src -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { unsigned AmortizationCost = <NUM_LIT> ; return LT . first * <NUM_LIT> * AmortizationCost ; } if ( Src -> isVectorTy ( ) && Src -> getVectorElementType ( ) -> isIntegerTy ( <NUM_LIT> ) && Src -> getVectorNumElements ( ) < <NUM_LIT> ) { unsigned NumVecElts = Src -> getVectorNumElements ( ) ; unsigned NumVectorizableInstsToAmortize = NumVecElts * <NUM_LIT> ; return NumVectorizableInstsToAmortize * NumVecElts * <NUM_LIT> ; } return LT . first ;


<s> unsigned TmpReg2 ; if ( Imm ) { TmpReg2 = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg2 ) . addReg ( TmpReg1 ) . addImm ( Shift ) . addImm ( <NUM_LIT> - Shift ) ; } else TmpReg2 = TmpReg1 ; unsigned TmpReg3 , Hi , Lo ; if ( ( Hi = ( Remainder >> <NUM_LIT> ) & <NUM_LIT> ) ) { TmpReg3 = createResultReg ( RC ) ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg3 ) . addReg ( TmpReg2 ) . addImm ( Hi ) ;


<s> switch ( pReloc . type ( ) ) { case llvm :: ELF :: R_<ISA_LIT>_THM_CALL : { uint64_t dest = pTargetSymValue + pReloc . addend ( ) + <NUM_LIT> ; int64_t branch_offset = static_cast < int64_t > ( dest ) - pSource ; if ( m_bUsingThumb2 ) { if ( ( branch_offset > <ISA_LIT>GNULDBackend :: THM2_MAX_FWD_BRANCH_OFFSET ) || ( branch_offset < <ISA_LIT>GNULDBackend :: THM2_MAX_BWD_BRANCH_OFFSET ) ) { result = true ; break ; } } else { if ( ( branch_offset > <ISA_LIT>GNULDBackend :: THM_MAX_FWD_BRANCH_OFFSET ) || ( branch_offset < <ISA_LIT>GNULDBackend :: THM_MAX_BWD_BRANCH_OFFSET ) ) { result = true ; break ; } } break ; }

case llvm :: ELF :: R_<ISA_LIT>_THM_JUMP24 : {


<s> U -> replaceUsesOfWith ( Old , New ) ; } else if ( isAssignTypeInstr ( U ) ) { IRB -> SetInsertPoint ( U ) ; SmallVector < Value * , <NUM_LIT> > Args = { New , U -> getOperand ( <NUM_LIT> ) } ; IRB -> CreateIntrinsic ( <STR_LIT> , { New -> getType ( ) } , Args ) ; U -> eraseFromParent ( ) ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> case <NUM_LIT> : if ( AM . Scale == <NUM_LIT> ) { return isImmUs ( AM . BaseOffs ) ; } return AM . Scale == <NUM_LIT> && AM . BaseOffs == <NUM_LIT> ; case <NUM_LIT> : case <NUM_LIT> : if ( AM . Scale == <NUM_LIT> ) { return isImmUs2 ( AM . BaseOffs ) ; } return AM . Scale == <NUM_LIT> && AM . BaseOffs == <NUM_LIT> ; default : if ( AM . Scale == <NUM_LIT> ) { return isImmUs4 ( AM . BaseOffs ) ; }


<s> if ( ! TARGET_64BIT ) { for ( i = FIRST_REX_INT_REG ; i <= LAST_REX_INT_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; for ( i = FIRST_REX_SSE_REG ; i <= LAST_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; for ( i = FIRST_EXT_REX_SSE_REG ; i <= LAST_EXT_REX_SSE_REG ; i ++ ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ; } c_mask = ( TARGET_64BIT_MS_ABI ? ( <NUM_LIT> << <NUM_LIT> ) : TARGET_64BIT ? ( <NUM_LIT> << <NUM_LIT> ) : ( <NUM_LIT> << <NUM_LIT> ) ) ; CLEAR_HARD_REG_SET ( reg_class_contents [ ( int ) CLOBBERED_REGS ] ) ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( call_used_regs [ i ] > <NUM_LIT> ) call_used_regs [ i ] = ! ! ( call_used_regs [ i ] & c_mask ) ; if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) GENERAL_REGS ] , i ) && call_used_regs [ i ] ) SET_HARD_REG_BIT ( reg_class_contents [ ( int ) CLOBBERED_REGS ] , i ) ; }

if ( ! TARGET_MMX ) for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( reg_class_contents [ ( int ) MMX_REGS ] , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> , reg_names [ i ] = <STR_LIT> ;


<s> assert ( <STR_LIT> ( Update -> getOperand ( <NUM_LIT> ) . getImm ( ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Update -> getOpcode ( ) == <STR_LIT> ) Value = - Value ; unsigned NewOpc = getPostIndexedOpcode ( I -> getOpcode ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( Update -> getOperand ( <NUM_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addOperand ( I -> getOperand ( <NUM_LIT> ) ) . addImm ( Value ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override {


<s> rtx x = find_reg_note ( insn , REG_BR_PROB , <NUM_LIT> ) ; if ( x ) { return profile_probability :: from_reg_br_prob_note ( XINT ( x , <NUM_LIT> ) ) >= profile_probability :: even ( ) ; } return <NUM_LIT> ;


<s> return new <ISA_LIT>Disassembler ( STI , Ctx , std :: move ( MCII ) ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: MatchAddressRecursively ( SDValue N , <ISA_LIT>ISelAddressMode & AM , unsigned Depth ) { bool is64Bit = Subtarget -> is64Bit ( ) ; DebugLoc dl = N . getDebugLoc ( ) ;


<s> BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addDef ( <STR_LIT> ) . addUse ( <STR_LIT> , RegState :: Undef ) . addUse ( <STR_LIT> ) ; MIB . addUse ( <STR_LIT> , RegState :: Implicit ) ; } else {


<s> void SwitchMode ( ) { uint64_t FB = ComputeAvailableFeatures ( STI . ToggleFeature ( <STR_LIT> ) ) ; setAvailableFeatures ( FB ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createFCCReg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { return CreateReg ( Index , RegKind_FCC , RegInfo , S , E , Parser ) ;


<s> return ( __m128 ) __builtin_ia32_loadups128_mask ( ( __v4sf * ) __P , ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> std :: pair < unsigned , MVT > LT = getTypeLegalizationCost ( ValTy ) ; MVT MTy = LT . second ; int ISD = InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; const <ISA_LIT>Subtarget & ST = TLI -> getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; static const <ISA_LIT>CostTblEntry SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const <ISA_LIT>CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const <ISA_LIT>CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST . hasAVX2 ( ) ) { int Idx = FindInTable ( AVX2CostTbl , array_lengthof ( AVX2CostTbl ) , ISD , MTy ) ;

if ( Idx != - <NUM_LIT> ) return LT . first * AVX2CostTbl [ Idx ] . Cost ;


<s> SmallVector < int , <NUM_LIT> > Mask ; for ( int M : SVN -> getMask ( ) ) Mask . push_back ( M ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && V2 . getOpcode ( ) == <STR_LIT> ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ; } else if ( V1 . getOpcode ( ) != <STR_LIT> || V2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! V1 -> hasOneUse ( ) || ! V2 -> hasOneUse ( ) ) return SDValue ( ) ; SDValue LHS = V1 -> getOperand ( <NUM_LIT> ) , RHS = V1 -> getOperand ( <NUM_LIT> ) ; if ( ( V2 -> getOperand ( <NUM_LIT> ) != LHS || V2 -> getOperand ( <NUM_LIT> ) != RHS ) && ( V2 -> getOperand ( <NUM_LIT> ) != RHS || V2 -> getOperand ( <NUM_LIT> ) != LHS ) ) return SDValue ( ) ;

if ( ! ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) return SDValue ( ) ;


<s> uint64_t FullValue = fullValue ( Disassembler , MI , SignExtend64 ( tmp , Bits ) ) ; uint32_t Extended = FullValue + Address ; if ( ! Disassembler . tryAddingSymbolicOperand ( MI , Extended , Address , true , <NUM_LIT> , <NUM_LIT> ) ) <ISA_LIT>MCInstrInfo :: addConstant ( MI , Extended , Disassembler . getContext ( ) ) ;


<s> if ( FP64FP16InputDenormals ) return FP_DENORM_FLUSH_OUT ; if ( FP64FP16OutputDenormals ) return FP_DENORM_FLUSH_IN ; return FP_DENORM_FLUSH_IN_FLUSH_OUT ;


<s> bool hasUnalignedScratchAccess ( ) const {


<s> CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : CC = <STR_LIT> ; break ; } Cond [ <NUM_LIT> ] . setImm ( CC ) ; return false ;


<s> int i = <NUM_LIT> ; if ( ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) || ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) ) { O << * CurrentFnSym << <STR_LIT> << paramIndex ; return ; } for ( I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , i ++ ) {


<s> case E_V2BFmode : case E_V4HFmode : case E_V4BFmode : case E_V2SFmode : for ( int i = <NUM_LIT> ; i < nunits ; ++ i ) { rtx x = XVECEXP ( op , <NUM_LIT> , i ) ; int v = real_to_target ( NULL , CONST_DOUBLE_REAL_VALUE ( x ) , REAL_MODE_FORMAT ( innermode ) ) ; wide_int wv = wi :: shwi ( v , innermode_bits ) ; val = wi :: insert ( val , wv , innermode_bits * i , innermode_bits ) ; } break ; default : gcc_unreachable ( ) ; }


<s> pushClobbers ( IA , DefM ) ; pushDefs ( IA , DefM ) ;


<s> return enableNamedBit ( MI , <STR_LIT> :: DLC ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( GPRDecoderTable [ Register ] ) ) ; unsigned Offset = ( Insn & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Offset ) ) ) ; return MCDisassembler :: Success ;


<s> const std :: vector < MachineBasicBlock * > & MBBs = ( * MJTEs ) [ JTIndex ] . MBBs ; for ( unsigned i = <NUM_LIT> , e = MBBs . size ( ) ; i != e ; ++ i ) { if ( IsPIC ) emitMachineBasicBlock ( MBBs [ i ] , <STR_LIT> , JTBase ) ; else emitMachineBasicBlock ( MBBs [ i ] , <STR_LIT> ) ; emitWordLE ( <NUM_LIT> ) ;


<s> static void lm32_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & arg , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int first_anon_arg ; tree fntype ; fntype = TREE_TYPE ( current_function_decl ) ; if ( stdarg_p ( fntype ) ) first_anon_arg = * cum + LM32_FIRST_ARG_REG ; else {

int size = arg . promoted_size_in_bytes ( ) ;


<s> LHS = B . buildAdd ( S32 , LHS , LHSign ) . getReg ( <NUM_LIT> ) ; RHS = B . buildAdd ( S32 , RHS , RHSign ) . getReg ( <NUM_LIT> ) ; LHS = B . buildXor ( S32 , LHS , LHSign ) . getReg ( <NUM_LIT> ) ; RHS = B . buildXor ( S32 , RHS , RHSign ) . getReg ( <NUM_LIT> ) ; Register UDivRem = MRI . createGenericVirtualRegister ( S32 ) ; legalizeUDIV_UREM32Impl ( B , UDivRem , LHS , RHS , IsRem ) ; if ( IsRem ) {


<s> unsigned getMaxCallFrameSize ( ) const { return MaxCallFrameSize ;


<s> rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; }

emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ;


<s> if ( ! nextLEB ( Val , Bytes , Size , Signed ) ) return false ; MI . addOperand ( MCOperand :: createImm ( Val ) ) ; return true ;


<s> const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;

return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , DL , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( VaListSize , DL , <STR_LIT> ) , <NUM_LIT> , false , false , false , MachinePointerInfo ( DestSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> for ( unsigned J = <NUM_LIT> , E = BBInfo . size ( ) ; J != E ; ++ J ) { const BasicBlockInfo & BBI = BBInfo [ J ] ;

dbgs ( ) << format ( <STR_LIT> , BBI . Offset , J ) << <STR_LIT> << unsigned ( BBI . KnownBits ) << <STR_LIT> << unsigned ( BBI . Unalign ) << <STR_LIT> << unsigned ( BBI . PostAlign ) << format ( <STR_LIT> , BBInfo [ J ] . Size ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPop ( ) {


<s> switch ( Opcode ) { default : return TTI :: TCC_Free ; case Instruction :: GetElementPtr : if ( Idx == <NUM_LIT> ) return <NUM_LIT> * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( BitSize == <NUM_LIT> ) return TTI :: TCC_Free ; if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Instruction :: ICmp : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; if ( isUInt < <NUM_LIT> > ( - Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; } break ; case Instruction :: Mul : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) <= <NUM_LIT> ) { if ( isInt < <NUM_LIT> > ( Imm . getSExtValue ( ) ) ) return TTI :: TCC_Free ; }


<s> if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ;


<s> if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtV ( ) ) return false ;

return any_of ( MF , [ & TII ] ( const MachineBasicBlock & MBB ) {


return ( __m128i ) __builtin_ia32_pmovdw128_mask ( ( __v4si ) __A , ( __v8hi ) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return ( __m64 ) __builtin_arm_wcmpgtuh ( ( __v4hi ) __m1 , ( __v4hi ) __m2 ) ;


return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize = <NUM_LIT> ; uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; }

uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ;


<s> assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT> ) ; return Reg - <STR_LIT> + <STR_LIT> ;


<s> else if ( TARGET_SPE && align >= <NUM_LIT> ) clear_step = <NUM_LIT> ; else clear_step = <NUM_LIT> ; if ( optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; if ( ! optimize_size && bytes > <NUM_LIT> * clear_step ) return <NUM_LIT> ; for ( offset = <NUM_LIT> ; bytes > <NUM_LIT> ; offset += clear_bytes , bytes -= clear_bytes ) { machine_mode mode = BLKmode ; rtx dest ; if ( bytes >= <NUM_LIT> && TARGET_ALTIVEC && align >= <NUM_LIT> ) { clear_bytes = <NUM_LIT> ; mode = V4SImode ; } else if ( bytes >= <NUM_LIT> && TARGET_SPE && align >= <NUM_LIT> ) { clear_bytes = <NUM_LIT> ; mode = V2SImode ; } else if ( bytes >= <NUM_LIT> && TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { clear_bytes = <NUM_LIT> ; mode = DImode ; if ( offset == <NUM_LIT> && align < <NUM_LIT> ) { rtx addr ; addr = XEXP ( orig_dest , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } } }

else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) {


<s> return ( uint8x16_t ) __builtin_neon_vmvnv16qi ( ( int8x16_t ) __a ) ;


<s> return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ;


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( MachineFunction :: iterator I = llvm :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } else NumBytes = StackSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes ) {


<s> assert ( F . isVarArg ( ) && <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( F . getCallingConv ( ) , true , MF , ArgLocs , F . getContext ( ) ) ; SmallVector < MVT , <NUM_LIT> > RegParmTypes ; RegParmTypes . push_back ( <STR_LIT> ) ; RegParmTypes . push_back ( <STR_LIT> ) ; SmallVectorImpl < ForwardedRegister > & Forwards = FuncInfo -> getForwardedMustTailRegParms ( ) ; CCInfo . analyzeMustTailForwardedRegisters ( Forwards , RegParmTypes , AssignFn ) ; if ( ! CCInfo . isAllocated ( <STR_LIT> ) ) { unsigned X8VReg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ;

Forwards . push_back ( ForwardedRegister ( X8VReg , <STR_LIT> , <STR_LIT> ) ) ;