<s> bool <ISA_LIT>InstrInfo :: isConditionalALU32 ( const MachineInstr * MI ) const { const <ISA_LIT>RegisterInfo & QRI = getRegisterInfo ( ) ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurReg ) . addReg ( CurRegLo ) . addImm ( <STR_LIT> ) . addReg ( CurRegHi ) . addImm ( <STR_LIT> ) ; Register NewCondReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , NewCondReg ) . addReg ( CurReg ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx , <NUM_LIT> ) ) ; if ( CondReg == <STR_LIT> ) CondReg = NewCondReg ; else { Register AndReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( LoopBB , I , DL , TII . get ( AndOpc ) , AndReg ) . addReg ( CondReg ) . addReg ( NewCondReg ) ; CondReg = AndReg ; } } auto SRsrcRC = TRI -> getEquivalentSGPRClass ( MRI . getRegClass ( VRsrc ) ) ; Register SRsrc = MRI . createVirtualRegister ( SRsrcRC ) ; auto Merge = BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrc ) ; unsigned Channel = <NUM_LIT> ; for ( Register Piece : ReadlanePieces ) { Merge . addReg ( Piece ) . addImm ( TRI -> getSubRegFromChannel ( Channel ++ ) ) ; } Rsrc . setReg ( SRsrc ) ; Rsrc . setIsKill ( true ) ; Register SaveExec = MRI . createVirtualRegister ( BoolXExecRC ) ; MRI . setSimpleHint ( SaveExec , CondReg ) ; BuildMI ( LoopBB , I , DL , TII . get ( SaveExecOpc ) , SaveExec ) . addReg ( CondReg , RegState :: Kill ) ; I = LoopBB . end ( ) ;

BuildMI ( LoopBB , I , DL , TII . get ( XorTermOpc ) , Exec ) . addReg ( Exec ) . addReg ( SaveExec ) ;


<s> * loc = gen_rtx_LO_SUM ( Pmode , pic_offset_table_rtx , * loc ) ; iter . skip_subrtxes ( ) ; } else if ( GET_CODE ( * loc ) == LO_SUM ) iter . skip_subrtxes ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue TargetCC ;

SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , TargetCC , DAG , dl ) ;


<s> MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue ByteVec = DAG . getNode ( <STR_LIT> , dl , ByteTy , VecV ) ; SDValue ByteSub = createHvxPrefixPred ( SubV , dl , BitBytes , false , DAG ) ; SDValue ByteIdx ; auto * IdxN = dyn_cast < ConstantSDNode > ( IdxV . getNode ( ) ) ; if ( ! IdxN || ! IdxN -> isNullValue ( ) ) { ByteIdx = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , IdxV , DAG . getConstant ( BitBytes , dl , <STR_LIT> ) ) ; ByteVec = DAG . getNode ( <STR_LIT> , dl , ByteTy , ByteVec , ByteIdx ) ; }

MVT BoolTy = <STR_LIT> ( <STR_LIT> , HwLen ) ;


<s> if ( offset >= insn -> bytes . size ( ) ) return true ;


<s> assert ( Kind == k_Barrier && <STR_LIT> ) ;

return StringRef ( Barrier . Data , Barrier . Length ) ;


<s> bool addRegAssignmentOptimized ( ) override {


<s> return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> bool CustomExpandInst ( const MCInst & Inst , MCStreamer & Out ) { return CustomExpandInstNaCl<ISA_LIT> ( * STI , Inst , Out , State ) ;


<s> const unsigned CondReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * DestMBB = I . getOperand ( <NUM_LIT> ) . getMBB ( ) ; MachineInstr & TestInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( CondReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addMBB ( DestMBB ) ; constrainSelectedInstRegOperands ( TestInst , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return true ;


<s> ITState . Cond = <STR_LIT> ( ITState . Cond ) ; } else {

ITState . Mask ^= <NUM_LIT> << ( <NUM_LIT> - ITState . CurPosition ) ;


<s> SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT VecVT = Op . getSimpleValueType ( ) ; unsigned MinElts = VecVT . getVectorMinNumElements ( ) ; SDValue VLMax = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( MinElts , DL , XLenVT ) ) ; int64_t ImmValue = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; SDValue DownOffset , UpOffset ; if ( ImmValue >= <NUM_LIT> ) { DownOffset = DAG . getConstant ( ImmValue , DL , XLenVT ) ;

UpOffset = DAG . getNode ( <STR_LIT> , DL , XLenVT , VLMax , DownOffset ) ;


<s> else if ( IntNo == <STR_LIT> ) Opc = <STR_LIT> ; else return ; SDLoc dl ( N ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue LongMul = DAG . getNode ( Opc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Lo , Hi ) ; Results . push_back ( LongMul . getValue ( <NUM_LIT> ) ) ; Results . push_back ( LongMul . getValue ( <NUM_LIT> ) ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> bool <ISA_LIT>DAGToDAGISel :: selectShiftMask ( SDValue N , unsigned ShiftWidth , SDValue & ShAmt ) { if ( N . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { const APInt & AndMask = N -> getConstantOperandAPInt ( <NUM_LIT> ) ;

assert ( isPowerOf2_32 ( ShiftWidth ) && <STR_LIT> ) ;


<s> if ( LABEL_REF_P ( x ) ) return false ;

const_tree decl = SYMBOL_REF_DECL ( x ) ;


<s> uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == <NUM_LIT> ) return ; Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = <NUM_LIT> ; if ( Opcode == getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , DL , TII . get ( getSUBriOpcode ( Is64Bit , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } else { assert ( Opcode == getCallFrameDestroyOpcode ( ) ) ; Amount -= CalleeAmt ; if ( Amount ) { unsigned Opc = getADDriOpcode ( Is64Bit , Amount ) ; New = BuildMI ( MF , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } }


<s> } namespace { class <ISA_LIT>MCAsmBackend : public MCAsmBackend { uint8_t OSABI ; public : <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( osABI ) { } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override ; bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override ; std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>ObjectWriter ( OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ;


<s> set = single_set ( insn ) ; if ( set && ! MEM_P ( SET_DEST ( set ) ) && reg_overlap_mentioned_p ( reg , SET_DEST ( set ) ) ) return true ; while ( ( insn = NEXT_INSN ( insn ) ) ) { rtx set ; if ( ! INSN_P ( insn ) ) continue ; code = GET_CODE ( insn ) ; if ( code == CODE_LABEL ) return <NUM_LIT> ; if ( code == JUMP_INSN ) return false ; else if ( code == INSN && GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) { rtx_sequence * seq = as_a < rtx_sequence * > ( PATTERN ( insn ) ) ; int i ; int retval = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < seq -> len ( ) ; i ++ ) { rtx_insn * this_insn = seq -> insn ( i ) ; rtx set = single_set ( this_insn ) ; if ( CALL_P ( this_insn ) ) code = CALL_INSN ; else if ( JUMP_P ( this_insn ) ) { if ( INSN_ANNULLED_BRANCH_P ( this_insn ) ) return false ;


<s> MFI -> setHasCalls ( true ) ; return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , AbsAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; } switch ( getTargetMachine ( ) . getCodeModel ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : return makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , DAG ) ; case CodeModel :: Medium : { SDValue H44 = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 , DAG ) ; H44 = DAG . getNode ( <STR_LIT> , DL , VT , H44 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue L44 = withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 , DAG ) ; L44 = DAG . getNode ( <STR_LIT> , DL , VT , L44 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , H44 , L44 ) ; } case CodeModel :: Large : { SDValue Hi = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM , DAG ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;

SDValue Lo = makeHiLoPair ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , DAG ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU ) { return new <ISA_LIT>AsmBackend ( T , TT . getOS ( ) , true , false ) ;


<s> return ( __m128 ) __builtin_ia32_gatherdiv4sf256 ( src , base , ( __v4di ) index , mask , scale ) ;


<s> static DecodeStatus DecodeHPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) {

return DecodeSPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitEndOfAsmFile ( Module & M ) { <ISA_LIT>TargetStreamer * TS = static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; for ( const auto & Symbol : OutContext . getSymbols ( ) ) if ( ! Symbol . second -> isDefined ( ) ) {


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { return tryParseRegister ( RegNo , StartLoc , EndLoc ) != MatchOperand_Success ;


<s> return false ; } if ( DefInstr -> getOpcode ( ) == AMDGPU :: PHI ) { bool Explicit = false ; for ( MachineInstr :: const_mop_iterator I = DefInstr -> operands_begin ( ) , E = DefInstr -> operands_end ( ) ; I != E ; ++ I ) { const MachineOperand & MO = * I ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) { continue ;


<s> unsigned <ISA_LIT>EarlyIfConversion :: countPredicateDefs ( const MachineBasicBlock * B ) const { unsigned PredDefs = <NUM_LIT> ; for ( auto & MI : * B ) { for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( MRI -> getRegClass ( R ) == & <STR_LIT> ) PredDefs ++ ; }


<s> case Instruction :: AShr : case Instruction :: Shl : if ( Opd2Info != TTI :: OK_UniformValue && Opd2Info != TTI :: OK_UniformConstantValue ) Cost = VTy -> getNumElements ( ) * ( TargetTransformInfo :: TCC_Basic + getArithmeticInstrCost ( Opcode , VTy -> getElementType ( ) ) + TargetTransformInfo :: TCC_Basic ) ; break ; } } return Cost ;


<s> auto I = Begin ; MaxInstNum = std :: max ( MaxInstNum , <NUM_LIT> ) ; for ( ; I != End && MaxInstNum ; ++ I , -- MaxInstNum ) { if ( ! I -> isDebugValue ( ) && LIS ) OS << LIS -> getInstructionIndex ( * I ) ; OS << '\t' << * I ; } if ( I != End ) { OS << <STR_LIT> ; I = std :: prev ( End ) ; if ( ! I -> isDebugValue ( ) && LIS ) OS << LIS -> getInstructionIndex ( * I ) ; OS << '\t' << * I ; } if ( End != BB -> end ( ) ) { OS << <STR_LIT> ; if ( LIS ) OS << LIS -> getInstructionIndex ( * End ) << '\t' ; OS << * End ; }


<s> RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; default : return false ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( i ) ; updateValueMap ( & Arg , ResultReg ) ; ++ i ; } MRI . addLiveIn ( <STR_LIT> ) ; auto * MFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; for ( auto const & Arg : F -> args ( ) ) { <STR_LIT> ArgTy = getLegalType ( getSimpleType ( Arg . getType ( ) ) ) ; if ( ArgTy == <STR_LIT> ) { MFI -> clearParamsAndResults ( ) ; return false ; } MFI -> addParam ( ArgTy ) ; } if ( ! F -> getReturnType ( ) -> isVoidTy ( ) ) { <STR_LIT> RetTy = getLegalType ( getSimpleType ( F -> getReturnType ( ) ) ) ; if ( RetTy == <STR_LIT> ) { MFI -> clearParamsAndResults ( ) ;


<s> EVT VT = Op . getValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { EVT HalfVT = <STR_LIT> ( VT . getVectorElementType ( ) . getSimpleVT ( ) , <NUM_LIT> ) ; SDValue Lo = DAG . getBuildVector ( HalfVT , SL , { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ) ; SDValue Hi = DAG . getBuildVector ( HalfVT , SL , { Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) } ) ; SDValue CastLo = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Lo ) ; SDValue CastHi = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Hi ) ; SDValue Blend = DAG . getBuildVector ( <STR_LIT> , SL , { CastLo , CastHi } ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Blend ) ;


<s> ++ OpIdx ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; ++ OpIdx ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { MI . addOperand ( MCOperand :: CreateImm ( decodeRotate ( insn ) ) ) ; ++ OpIdx ; }


<s> lowerLongBranchLUi ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( <STR_LIT> ) ; OutMI . addOperand ( LowerOperand ( MI -> getOperand ( <NUM_LIT> ) ) ) ; OutMI . addOperand ( createSub ( MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) , <ISA_LIT>MCExpr :: CEK_ABS_HI ) ) ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Register ) ; Op -> Reg . RegNum = RegNo ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> static bool breaksSMEMSoftClause ( MachineInstr * MI ) {

return ! <ISA_LIT>InstrInfo :: isSMRD ( * MI ) ;


<s> <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( true , OSABI , ELF :: EM_<ISA_LIT> , true ) {


<s> if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetLinux ( ) ) return CSR_<ISA_LIT>_AAPCS_RegMask ; return nullptr ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Token ) ; Op -> Tok = Str ; Op -> StartLoc = S ; Op -> EndLoc = S ;


<s> auto I = Reachable . find ( From ) ;

if ( I == Reachable . end ( ) ) return false ;


<s> return Operand . isGLC ( ) ? Match_Success : Match_InvalidOperand ; case MCK_idxen : return Operand . isIdxen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_offen : return Operand . isOffen ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SSrc32 : return Operand . isSSrc32 ( ) ? Match_Success : Match_InvalidOperand ; case MCK_SoppBrTarget : return Operand . isSoppBrTarget ( ) ? Match_Success : Match_InvalidOperand ;


<s> return __builtin_ia32_comisdgt ( ( __v2df ) __A , ( __v2df ) __B ) ;


<s> } EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) && isHorizontalBinOp ( Op0 , Op1 , false ) ) { auto HSUBBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; return SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { Op0 , Op1 } , HSUBBuilder ) ; } if ( SDValue V = combineIncDecVector ( N , DAG ) ) return V ; if ( SDValue V = combineSubToSubus ( N , DAG , Subtarget ) ) return V ;

return combineAddOrSubToADCOrSBB ( N , DAG ) ;


<s> static __inline unsigned long long sh_media_MADD_L ( unsigned long long mm , unsigned long long mn ) { typedef float v2si __attribute__ ( ( mode ( V2SI ) ) ) ; return ( unsigned long long ) __builtin_addv2si3 ( ( v2si ) mm , ( v2si ) mn ) ;


<s> <ISA_LIT>TileConfig ( ) : MachineFunctionPass ( ID ) {


<s> OperandMatchResultTy tryParseRegister ( unsigned & , SMLoc & , SMLoc & ) override { llvm_unreachable ( <STR_LIT> ) ;


<s> static DecodeStatus DecodeLoadIntPair ( MCInst & Inst , unsigned insn , uint64_t Address , const MCDisassembler * Decoder ) {

return DecodeMem ( Inst , insn , Address , Decoder , true , DecodeIntPairRegisterClass ) ;


<s> EVT LoVT , HiVT ; SDValue Lo , Hi ; unsigned NumElements = ResVT . getVectorNumElements ( ) ; assert ( ! ( NumElements & <NUM_LIT> ) && <STR_LIT> ) ; LoVT = HiVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ResVT . getVectorElementType ( ) , NumElements / <NUM_LIT> ) ; EVT InNVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SrcVT . getVectorElementType ( ) , LoVT . getVectorNumElements ( ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , InNVT , Src , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , DL , InNVT , Src , DAG . getIntPtrConstant ( InNVT . getVectorNumElements ( ) ) ) ; Lo = DAG . getNode ( N -> getOpcode ( ) , DL , LoVT , Lo ) ; Hi = DAG . getNode ( N -> getOpcode ( ) , DL , HiVT , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , ResVT , Lo , Hi ) ;


<s> return <STR_LIT> + std :: to_string ( a . Index ( ) ) ;


<s> unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isSGPRClass ( MRI . getRegClass ( DstReg ) ) ) return false ; if ( ! MRI . hasOneUse ( DstReg ) ) return false ; MachineInstr & CopyUse = * MRI . use_instr_begin ( DstReg ) ; if ( ! CopyUse . isCopy ( ) ) return false ; if ( TargetRegisterInfo :: isPhysicalRegister ( CopyUse . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; const TargetRegisterClass * SrcRC , * DstRC ; std :: tie ( SrcRC , DstRC ) = getCopyRegClasses ( CopyUse , * TRI , MRI ) ; if ( ! isSGPRToVGPRCopy ( SrcRC , DstRC , * TRI ) ) return false ; if ( tryChangeVGPRtoSGPRinCopy ( CopyUse , TRI , TII ) ) return true ; unsigned SubReg = CopyUse . getOperand ( <NUM_LIT> ) . getSubReg ( ) ; if ( SubReg != <STR_LIT> ) return false ; MRI . setRegClass ( DstReg , DstRC ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( CopyUse . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; for ( unsigned I = <NUM_LIT> , N = MI . getNumOperands ( ) ; I != N ; I += <NUM_LIT> ) { unsigned SrcReg = MI . getOperand ( I ) . getReg ( ) ; unsigned SrcSubReg = MI . getOperand ( I ) . getSubReg ( ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( SrcReg ) ; assert ( TRI -> isSGPRClass ( SrcRC ) && <STR_LIT> ) ;

SrcRC = TRI -> getSubRegClass ( SrcRC , SrcSubReg ) ;


<s> if ( isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; Chain = DAG . getStore ( Chain , dl , Value , StackSlot , PseudoSourceValue :: getFixedStack ( SSFI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , StackSlot , DAG . getValueType ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) } ; Value = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; Chain = Value . getValue ( <NUM_LIT> ) ; SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; } SDValue Ops [ ] = { Chain , Value , StackSlot } ; SDValue FIST = DAG . getNode ( Opc , dl , <STR_LIT> , Ops , <NUM_LIT> ) ;

return std :: make_pair ( FIST , StackSlot ) ;


<s> bool iss8_0Imm64 ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , true , false ) ;


<s> emitARM64WinUnwindCode ( Win64EH :: UOP_SaveFRegPX , Reg , Offset ) ;


<s> if ( is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , s2 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; return MCDisassembler :: Success ;


<s> if ( SU ) { OccupedSlotsMask |= <NUM_LIT> ; return SU ; } } for ( int Chan = <NUM_LIT> ; Chan > - <NUM_LIT> ; -- Chan ) { bool isOccupied = OccupedSlotsMask & ( <NUM_LIT> << Chan ) ; if ( ! isOccupied ) { SUnit * SU = AttemptFillSlot ( Chan , false ) ; if ( SU ) { OccupedSlotsMask |= ( <NUM_LIT> << Chan ) ; InstructionsGroupCandidate . push_back ( SU -> getInstr ( ) ) ; return SU ; } }


<s> bool <ISA_LIT>TTIImpl :: isLegalToVectorizeMemChain ( unsigned ChainSizeInBytes , Align Alignment , unsigned AddrSpace ) const {

return ( AddrSpace != <ISA_LIT>AS :: PRIVATE_ADDRESS ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const {


<s> offset = rs6000_machopic_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( SMALL_INT ( offset ) ) return plus_constant ( Pmode , base , INTVAL ( offset ) ) ; else if ( ! reload_completed ) offset = force_reg ( Pmode , offset ) ; else { rtx mem = force_const_mem ( Pmode , orig ) ; return machopic_legitimize_pic_address ( mem , Pmode , reg ) ; } } return gen_rtx_PLUS ( Pmode , base , offset ) ;


<s> theCurLine = <NUM_LIT> ; fstr . open ( filename . c_str ( ) ) ; theFileName = filename ;


<s> bool ShouldPrint = false ; if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . hasSSE2 ( ) ) { addPass ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; ShouldPrint = true ; } if ( UseVZeroUpper ) { addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ;


<s> if ( SrcReg != <STR_LIT> ) BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , false , false , true ) . addImm ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( SrcReg ) * <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , false , false , MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) , FrameIndex ) ; MBB . erase ( II ) ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) {

MCSubtargetInfo * X = new MCSubtargetInfo ( ) ;


<s> if ( immediate_operand ( * scalar_op , Pmode ) ) { if ( ! rtx_equal_p ( * scalar_op , const0_rtx ) ) * scalar_op = force_reg ( Pmode , * scalar_op ) ; * scalar_op = gen_rtx_SIGN_EXTEND ( scalar_mode , * scalar_op ) ; return false ; } if ( CONST_INT_P ( * scalar_op ) ) * scalar_op = force_reg ( scalar_mode , * scalar_op ) ; rtx tmp = gen_reg_rtx ( vector_mode ) ; <STR_LIT> ( code_for_pred_broadcast ( vector_mode ) , tmp , * scalar_op , vl , mask_mode ) ; emit_vector_func ( operands , tmp ) ; return true ;


if ( GET_CODE ( elt_mem ) != MEM || GET_CODE ( elt_reg ) != REG || REGNO ( elt_reg ) != GP_REGNUM ) return false ;


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } if ( ! <STR_LIT> . contains ( SrcReg ) ) { reportIllegalCopy ( this , MBB , MI , DL , DestReg , SrcReg , KillSrc ) ; return ; } BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( RC == & <STR_LIT> ) { if ( DestReg == <STR_LIT> ) { if ( <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } return ; } if ( ! <STR_LIT> . contains ( SrcReg ) ) { reportIllegalCopy ( this , MBB , MI , DL , DestReg , SrcReg , KillSrc ) ; return ; } BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } if ( DestReg == <STR_LIT> ) { assert ( <STR_LIT> . contains ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } unsigned EltSize = <NUM_LIT> ; unsigned Opcode = <STR_LIT> ; if ( RI . isSGPRClass ( RC ) ) { if ( RC -> getSize ( ) > <NUM_LIT> ) { Opcode = <STR_LIT> ; EltSize = <NUM_LIT> ; } else { Opcode = <STR_LIT> ;


<s> LoadSDNode * LN = cast < LoadSDNode > ( Op . getNode ( ) ) ; SDValue LoadChain = LN -> getChain ( ) ; SDValue BasePtr = LN -> getBasePtr ( ) ; if ( Op . getValueType ( ) == <STR_LIT> || Op . getValueType ( ) == <STR_LIT> ) { EVT MemVT = LN -> getMemoryVT ( ) ; unsigned Alignment = LN -> getAlignment ( ) ; if ( Alignment >= MemVT . getStoreSize ( ) ) return Op ; EVT ScalarVT = Op . getValueType ( ) . getScalarType ( ) , ScalarMemVT = MemVT . getScalarType ( ) ; unsigned Stride = ScalarMemVT . getStoreSize ( ) ; SDValue Vals [ <NUM_LIT> ] , LoadChains [ <NUM_LIT> ] ; for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) { SDValue Load ; if ( ScalarVT != ScalarMemVT ) Load = DAG . getExtLoad ( LN -> getExtensionType ( ) , dl , ScalarVT , LoadChain , BasePtr , LN -> getPointerInfo ( ) . getWithOffset ( Idx * Stride ) , ScalarMemVT , MinAlign ( Alignment , Idx * Stride ) , LN -> getMemOperand ( ) -> getFlags ( ) , LN -> getAAInfo ( ) ) ; else Load = DAG . getLoad ( ScalarVT , dl , LoadChain , BasePtr , LN -> getPointerInfo ( ) . getWithOffset ( Idx * Stride ) , MinAlign ( Alignment , Idx * Stride ) , LN -> getMemOperand ( ) -> getFlags ( ) , LN -> getAAInfo ( ) ) ; if ( Idx == <NUM_LIT> && LN -> isIndexed ( ) ) { assert ( LN -> getAddressingMode ( ) == <STR_LIT> && <STR_LIT> ) ; Load = DAG . getIndexedLoad ( Load , dl , BasePtr , LN -> getOffset ( ) , LN -> getAddressingMode ( ) ) ; } Vals [ Idx ] = Load ; LoadChains [ Idx ] = Load . getValue ( <NUM_LIT> ) ; BasePtr = DAG . getNode ( <STR_LIT> , dl , BasePtr . getValueType ( ) , BasePtr , DAG . getConstant ( Stride , dl , BasePtr . getValueType ( ) ) ) ; } SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadChains ) ; SDValue Value = DAG . getBuildVector ( Op . getValueType ( ) , dl , Vals ) ; if ( LN -> isIndexed ( ) ) { SDValue RetOps [ ] = { Value , Vals [ <NUM_LIT> ] . getValue ( <NUM_LIT> ) , TF } ; return DAG . getMergeValues ( RetOps , dl ) ; } SDValue RetOps [ ] = { Value , TF } ;


<s> char * ptr = clean_name ; if ( ! ISALPHA ( * name ) ) * ptr ++ = '$' ; memcpy ( ptr , name , len + <NUM_LIT> ) ; clean_symbol_name ( clean_name ) ; fputs ( clean_name , file ) ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ; RegisterAsmInfo < <ISA_LIT>MCAsmInfo > A ( The<ISA_LIT>Target ) ;


<s> case VK_<ISA_LIT>_PC22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_PC10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_GOT22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_GOT10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_GOT13 : return false ; case VK_<ISA_LIT>_13 : return false ; case VK_Sparc_WDI<ISA_LIT>30 : return false ; case VK_<ISA_LIT>_WPLT30 : return false ; case VK_Sparc_R_DI<ISA_LIT>32 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_GD_HI22 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_GD_LO10 : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_GD_ADD : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_GD_CALL : OS << <STR_LIT> ; return true ; case VK_<ISA_LIT>_TLS_LDM_HI22 : OS << <STR_LIT> ; return true ;

case VK_<ISA_LIT>_TLS_LDM_LO10 : OS << <STR_LIT> ; return true ;


<s> static __inline qword si_xorhi ( qword a , unsigned short b ) { return ( ( qword ) ( vec_xor ( ( vec_ushort8 ) ( a ) , vec_splat ( ( vec_ushort8 ) ( si_from_ushort ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> aarch64_init_simd_builtin_types ( ) ; aarch64_init_simd_builtin_scalar_types ( ) ; tree lane_check_fpr = build_function_type_list ( void_type_node , size_type_node , size_type_node , intSI_type_node , NULL ) ; aarch64_builtin_decls [ AARCH64_SIMD_BUILTIN_LANE_CHECK ] = add_builtin_function ( <STR_LIT> , lane_check_fpr , AARCH64_SIMD_BUILTIN_LANE_CHECK , BUILT_IN_MD , NULL , NULL_TREE ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( aarch64_simd_builtin_data ) ; i ++ , fcode ++ ) { bool print_type_signature_p = false ; char type_signature [ SIMD_MAX_BUILTIN_ARGS ] = { <NUM_LIT> } ; aarch64_simd_builtin_datum * d = & aarch64_simd_builtin_data [ i ] ; char namebuf [ <NUM_LIT> ] ; tree ftype = NULL ; tree fndecl = NULL ; d -> fcode = fcode ; int op_num = insn_data [ d -> code ] . n_operands - <NUM_LIT> ; int arg_num = d -> qualifiers [ <NUM_LIT> ] & qualifier_void ? op_num + <NUM_LIT> : op_num ; tree return_type = void_type_node , args = void_list_node ; tree eltype ; for ( ; op_num >= <NUM_LIT> ; arg_num -- , op_num -- ) { machine_mode op_mode = insn_data [ d -> code ] . operand [ op_num ] . mode ; enum aarch64_type_qualifiers qualifiers = d -> qualifiers [ arg_num ] ;

if ( qualifiers & qualifier_unsigned ) {


<s> SmallVector < std :: pair < unsigned , std :: string > , <NUM_LIT> > MapAndConstraints ; unsigned MatchResult = MatchInstructionImpl ( Operands , Kind , Inst , MapAndConstraints , ErrorInfo , false ) ; switch ( MatchResult ) { default : break ; case Match_Success : { Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst ) ; return false ; } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ;


<s> } EVT ValTy = Op . getValueType ( ) ; unsigned GOTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; unsigned OFSTFlag = Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue BAGOTOffset = DAG . getTargetBlockAddress ( BA , ValTy , <NUM_LIT> , GOTFlag ) ; BAGOTOffset = DAG . getNode ( <STR_LIT> , dl , ValTy , GetGlobalReg ( DAG , ValTy ) , BAGOTOffset ) ; SDValue BALOOffset = DAG . getTargetBlockAddress ( BA , ValTy , <NUM_LIT> , OFSTFlag ) ;

SDValue Load = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , BAGOTOffset , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> emit_insn ( gen_x86_fnstcw_1 ( stored_mode ) ) ; emit_move_insn ( reg , stored_mode ) ; if ( TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size ) { switch ( mode ) { case I387_CW_TRUNC : emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_TRUNC ; break ; case I387_CW_FLOOR : emit_insn ( gen_andhi3 ( reg , reg , GEN_INT ( ~ <NUM_LIT> ) ) ) ; emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_FLOOR ; break ; case I387_CW_CEIL : emit_insn ( gen_andhi3 ( reg , reg , GEN_INT ( ~ <NUM_LIT> ) ) ) ; emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_CEIL ; break ; case I387_CW_MASK_PM : emit_insn ( gen_iorhi3 ( reg , reg , GEN_INT ( <NUM_LIT> ) ) ) ; slot = SLOT_CW_MASK_PM ; break ; default : gcc_unreachable ( ) ; } }


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> EVT LoadVT = VT ; if ( VT . isFloatingPoint ( ) ) LoadVT = VT . changeTypeToInteger ( ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ;

SDValue Load = DAG . getNode ( <STR_LIT> , DL , { LoadVT , <STR_LIT> } , Ops ) ;


<s> <STR_LIT> ShOpcVal = <STR_LIT> ( N ) ; if ( ShOpcVal == <STR_LIT> ) return false ; BaseReg = N . getOperand ( <NUM_LIT> ) ; unsigned ShImmVal = <NUM_LIT> ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { ShReg = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; ShImmVal = RHS -> getZExtValue ( ) & <NUM_LIT> ; } else { ShReg = N . getOperand ( <NUM_LIT> ) ; if ( ! isShifterOpProfitable ( N , ShOpcVal , ShImmVal ) ) return false ; } Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( ShOpcVal , ShImmVal ) , <STR_LIT> ) ; return true ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : TM ( TM ) , STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , {


<s> char value = MI -> getOperand ( OpNo ) . getImm ( ) ; value = ( value << ( <NUM_LIT> - <NUM_LIT> ) ) >> ( <NUM_LIT> - <NUM_LIT> ) ; O << ( int ) value ;


<s> if ( parseOptionalToken ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Integer ) ) { if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_ParseFail ; SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Expr , S , E , getContext ( ) ) ) ;


<s> else if ( mode == CCVIALLmode || mode == CCVIANYmode ) return reverse_condition ( code ) ;


<s> if ( ST -> hasSSE41 ( ) ) { int Idx = CostTableLookup ( SSE41AltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSE41AltShuffleTbl [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > SSSE3AltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( ST -> hasSSSE3 ( ) ) { int Idx = CostTableLookup ( SSSE3AltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSSE3AltShuffleTbl [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > SSEAltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; int Idx = CostTableLookup ( SSEAltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSEAltShuffleTbl [ Idx ] . Cost ;

return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index , SubTp ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MF . callsUnwindInit ( ) || MF . hasEHFunclets ( ) || MF . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) {

RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> break ; case CmpInst :: FCMP_ORD : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_UNO : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_UEQ : CondCode = <STR_LIT> ; CondCode2 = <STR_LIT> ; break ; case CmpInst :: FCMP_UGT : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_UGE : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_ULT : CondCode = <STR_LIT> ; break ; case CmpInst :: FCMP_ULE : CondCode = <STR_LIT> ;


return __builtin_ia32_cvtsd2si ( ( __v2df ) __A ) ;


<s> <ISA_LIT>AsmInstrumentation :: <ISA_LIT>AsmInstrumentation ( const MCSubtargetInfo * & STI ) : STI ( STI ) {


<s> unsigned AluCode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;

return LPAC :: isPostOp ( AluCode ) && usesGivenOffset ( MI , AddOffset ) ;


<s> V2DstIndex = i ; } } if ( V1DstIndex == - <NUM_LIT> && V2DstIndex == - <NUM_LIT> ) return SDValue ( ) ; unsigned V2SrcIndex = <NUM_LIT> ; if ( V1DstIndex != - <NUM_LIT> ) { V2SrcIndex = Mask [ V1DstIndex ] ; V2DstIndex = V1DstIndex ; V2 = V1 ; } else { V2SrcIndex = Mask [ V2DstIndex ] - <NUM_LIT> ; } if ( ! V1UsedInPlace ) V1 = DAG . getUNDEF ( <STR_LIT> ) ; unsigned InsertPSMask = V2SrcIndex << <NUM_LIT> | V2DstIndex << <NUM_LIT> | ZMask ; assert ( ( InsertPSMask & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( InsertPSMask , DL , <STR_LIT> ) ) ;


<s> iterator begin ( ) const { return Masks . begin ( ) ;


<s> static HOST_WIDE_INT arg_area_size ( void ) {


<s> CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = T . getArch ( ) == Triple :: ppc64le ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; DollarIsPC = true ;


<s> } if ( Filled ) { MachineBasicBlock :: instr_iterator DSI ( I ) ; if ( InMicro<ISA_LIT>Mode && TII -> GetInstSizeInBytes ( std :: next ( DSI ) ) == <NUM_LIT> && DSI -> isCall ( ) ) { DSI -> setDesc ( TII -> get ( getEquivalentCallShort ( DSI -> getOpcode ( ) ) ) ) ; } continue ; } } unsigned Opcode = I -> getOpcode ( ) ; if ( InMicro<ISA_LIT>Mode ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : if ( ( ( unsigned ) I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) == <STR_LIT> ) { I = replaceWithCompactBranch ( MBB , I , I -> getDebugLoc ( ) ) ; continue ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : I = replaceWithCompactJump ( MBB , I , I -> getDebugLoc ( ) ) ; continue ; default : break ; } } BuildMI ( MBB , std :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIBundleBuilder ( MBB , I , std :: next ( I , <NUM_LIT> ) ) ; } return Changed ;


<s> else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ;

if ( StackAlignOverride ) stackAlignment = StackAlignOverride ;


<s> output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; } val -= <NUM_LIT> ; } else if ( val >= <NUM_LIT> ) { val = val - <NUM_LIT> ; } if ( val > <NUM_LIT> ) { while ( -- val >= <NUM_LIT> ) { if ( GET_MODE ( operands [ <NUM_LIT> ] ) != QImode ) { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; } if ( D_REG_P ( operands [ <NUM_LIT> ] ) ) output_asm_insn ( <STR_LIT> , operands ) ; if ( GET_MODE ( operands [ <NUM_LIT> ] ) != QImode || DA_REG_P ( operands [ <NUM_LIT> ] ) ) output_asm_insn ( <STR_LIT> , operands ) ; } } else { while ( ++ val <= <NUM_LIT> ) { if ( GET_MODE ( operands [ <NUM_LIT> ] ) != QImode ) output_asm_insn ( <STR_LIT> , operands ) ; if ( D_REG_P ( operands [ <NUM_LIT> ] ) ) output_asm_insn ( <STR_LIT> , operands ) ;


<s> if ( Opt == <STR_LIT> ) { PrintAliases = false ; return true ; } return false ;


<s> for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( nios2_fpu_insn ) ; i ++ ) if ( cfg -> code [ i ] >= <NUM_LIT> ) nios2_set_fpu_custom_code ( ( enum n2fpu_code ) i , cfg -> code [ i ] , override ) ;

if ( cfg -> set_sp_constants ) flag_single_precision_constant = <NUM_LIT> ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx ) : MCII ( mcii ) , Ctx ( ctx ) {


<s> assert ( Fixup . getOffset ( ) + Size <= Data . size ( ) && <STR_LIT> ) ; int64_t SignedValue = static_cast < int64_t > ( Value ) ; if ( ( Target . isAbsolute ( ) || IsResolved ) && getFixupKindInfo ( Fixup . getKind ( ) ) . Flags & MCFixupKindInfo :: FKF_IsPCRel ) { if ( Size > <NUM_LIT> && ! isIntN ( Size * <NUM_LIT> , SignedValue ) ) Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> + Twine ( SignedValue ) + <STR_LIT> + Twine ( Size ) + ( ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; } else { assert ( ( Size == <NUM_LIT> || isIntN ( Size * <NUM_LIT> + <NUM_LIT> , SignedValue ) ) && <STR_LIT> ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {


<s> state_transition ( curr_state , insn ) ;

state -> insns_left = targetm . sched . variable_issue ( <NUM_LIT> , false , insn , state -> insns_left ) ;


<s> Value * Ptr = I . getPointerOperand ( ) ; if ( ! DA -> isUniform ( Ptr ) ) return ; if ( Instruction * PtrI = dyn_cast < Instruction > ( Ptr ) ) setUniformMetadata ( PtrI ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;

setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ;


<s> static ScheduleDAGInstrs * create<ISA_LIT>MachineScheduler ( MachineSchedContext * C ) { ScheduleDAGMILive * DAG = new ScheduleDAGMILive ( C , llvm :: make_unique < <ISA_LIT>PreRASchedStrategy > ( C ) ) ; DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI ) ) ;


<s> vpaddlq_u32 ( uint32x4_t a ) { uint64x2_t result ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> virtual BlackfinTargetLowering * getTargetLowering ( ) const {

return const_cast < BlackfinTargetLowering * > ( & TLInfo ) ;


<s> bool <ISA_LIT>LegalizerInfo :: legalizeExtractVectorElt ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & B ) const { Optional < ValueAndVReg > MaybeIdxVal = getConstantVRegValWithLookThrough ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! MaybeIdxVal ) return true ; const int64_t IdxVal = MaybeIdxVal -> Value . getSExtValue ( ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Vec = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT VecTy = MRI . getType ( Vec ) ;

LLT EltTy = VecTy . getElementType ( ) ;


<s> int cost ; if ( TARGET_THUMB ) { switch ( code ) { case MULT : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; default : * total = thumb_rtx_costs ( x , code , outer_code ) ; return true ; } } switch ( code ) { case MULT : if ( mode == DImode && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == GET_CODE ( XEXP ( x , <NUM_LIT> ) ) ) && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == ZERO_EXTEND || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SIGN_EXTEND ) ) { * total = <NUM_LIT> ; return true ; } if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT ) { * total = <NUM_LIT> ; return true ; } if ( mode == DImode ) { cost = <NUM_LIT> ; nonreg_cost = <NUM_LIT> ; } else { cost = <NUM_LIT> ;


<s> EVT DstTy = TLI -> getValueType ( Dst ) ; if ( ! SrcTy . isSimple ( ) || ! DstTy . isSimple ( ) ) return TargetTransformInfo :: getCastInstrCost ( Opcode , Dst , Src ) ; static const TypeConversionCostTblEntry < MVT > ConversionTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ;

int Idx = ConvertCostTableLookup < MVT > ( ConversionTbl , array_lengthof ( ConversionTbl ) , ISD , DstTy . getSimpleVT ( ) , SrcTy . getSimpleVT ( ) ) ;


<s> unsigned StackAlignment = TFI . getStackAlignment ( ) ; uint64_t AlignMask = StackAlignment - <NUM_LIT> ; int64_t Offset = StackSize ; unsigned SlotSize = Subtarget . getSlotSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask ) ) ;


<s> void llvm :: addPredicatedMveVpredROp ( MachineInstrBuilder & MIB , unsigned Cond , unsigned Inactive ) { addPredicatedMveVpredNOp ( MIB , Cond ) ; MIB . addReg ( Inactive ) ;


<s> case <STR_LIT> : PrintUnsigned = true ; break ; } int32_t Rotated = <STR_LIT> ( Bits , Rot ) ; if ( <STR_LIT> ( Rotated ) == Op . getImm ( ) ) { O << <STR_LIT> << markup ( <STR_LIT> ) ; if ( PrintUnsigned ) O << static_cast < uint32_t > ( Rotated ) ; else O << Rotated ; O << markup ( <STR_LIT> ) ; return ;


<s> static bool arm_block_set_vect ( rtx dstbase , unsigned HOST_WIDE_INT length , unsigned HOST_WIDE_INT value , unsigned HOST_WIDE_INT align ) { if ( ( ( align & <NUM_LIT> ) != <NUM_LIT> || ( length & <NUM_LIT> ) != <NUM_LIT> ) && ( ! unaligned_access || BYTES_BIG_ENDIAN ) ) return false ; if ( ( align & <NUM_LIT> ) == <NUM_LIT> ) return arm_block_set_aligned_vect ( dstbase , length , value , align ) ; else return arm_block_set_unaligned_vect ( dstbase , length , value , align ) ;


<s> if ( ReportErrors ) Context . reportError ( Loc , Msg ) ;


<s> virtual const TargetRegisterInfo & getRegisterInfo ( ) const {


<s> if ( TagName != <STR_LIT> ) O << <STR_LIT> << TagName ; for ( int i = <NUM_LIT> ; i < Num ; i ++ ) O << <STR_LIT> << Aux [ i ] ;


<s> const GlobalValue * gv = mo . getGlobal ( ) ; TM . getNameWithPrefix ( name , gv , Mang ) ; } else { assert ( mo . isSymbol ( ) && <STR_LIT> ) ; Mangler :: getNameWithPrefix ( name , mo . getSymbolName ( ) , ap . getDataLayout ( ) ) ; }

return ap . OutContext . getOrCreateSymbol ( name ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return <STR_LIT> ;


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>FunctionInfo * AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . hardenSlsRetBr ( ) && isIndirectControlFlowNotComingBack ( MI ) ) return false ; if ( ST . hardenSlsBlr ( ) && isIndirectCall ( MI ) ) return false ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ; } return true ;


<s> frv_finish_packet ( handle_packet ) ; frv_start_packet_block ( ) ; } if ( INSN_P ( insn ) ) switch ( GET_CODE ( PATTERN ( insn ) ) ) { case USE : case CLOBBER : break ; default : if ( CALL_P ( insn ) && frv_cpu_type == FRV_CPU_TOMCAT ) frv_finish_packet ( handle_packet ) ; eh_insn_p = ( find_reg_note ( insn , REG_EH_REGION , NULL ) != NULL ) ; if ( eh_insn_p && ! frv_issues_to_branch_unit_p ( insn ) ) frv_finish_packet ( handle_packet ) ; if ( ! frv_pack_insn_p ( insn ) ) { frv_finish_packet ( handle_packet ) ; while ( ! frv_pack_insn_p ( insn ) ) state_transition ( frv_packet . dfa_state , <NUM_LIT> ) ; } frv_add_insn_to_packet ( insn ) ; if ( code == CALL_INSN || code == JUMP_INSN || eh_insn_p ) frv_finish_packet ( handle_packet ) ; break ; }


<s> Arg = DAG . getBitcast ( <STR_LIT> , Arg ) ; SDValue Lo , Hi ; Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Lo ) ) ;

RegsToPass . push_back ( std :: make_pair ( NextVA . getLocReg ( ) , Hi ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> LLVM_DEBUG ( ( L ? dbgs ( ) << <STR_LIT> << PrintMB ( HB ) : dbgs ( ) << <STR_LIT> ) << <STR_LIT> ) ; bool Changed = false ; if ( L ) {

for ( MachineLoop :: iterator I = L -> begin ( ) , E = L -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ;


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; unsigned Rn = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; uint32_t Binary = getAddrMode2OffsetOpValue ( MI , OpIdx + <NUM_LIT> , Fixups , STI ) ; Binary |= Rn << <NUM_LIT> ; return Binary ;


<s> FrameReg = <STR_LIT> ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } if ( RegInfo -> needsStackRealignment ( MF ) && ! isFixed ) { if ( hasBP ( MF ) ) FrameReg = <STR_LIT> ; else FrameReg = <STR_LIT> ; return StackOffset :: getFixed ( FrameOffset + MF . getFrameInfo ( ) . getStackSize ( ) ) ; } FrameReg = RegInfo -> getFrameRegister ( MF ) ;

return StackOffset :: getFixed ( FrameOffset ) ;


<s> InsnType Rs = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; InsnType Rt = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t Imm = SignExtend64 ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ; bool HasRs = false ; if ( Rs >= Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else MI . setOpcode ( <STR_LIT> ) ; if ( HasRs ) MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ; MI . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , Rt ) ) ) ; MI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return MCDisassembler :: Success ;


<s> EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT != <STR_LIT> && DstVT != <STR_LIT> ) return false ; if ( ! TLI . isTypeLegal ( SrcVT ) ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; if ( SrcVT == <STR_LIT> ) { UpdateValueMap ( I , InputReg ) ; return true ; } if ( ! Subtarget -> is64Bit ( ) ) { const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , CopyReg ) . addReg ( InputReg ) ; InputReg = CopyReg ; } unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , InputReg , true , <STR_LIT> ) ; if ( ! ResultReg ) return false ; UpdateValueMap ( I , ResultReg ) ;


<s> return false ; } if ( ( SymbolName != CurrentFn -> getName ( ) ) ) { reportParseError ( <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitDirectiveEnd ( SymbolName ) ; CurrentFn = nullptr ; return false ; } if ( IDVal == <STR_LIT> ) { SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > TmpReg ; OperandMatchResultTy ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail ) { reportParseError ( <STR_LIT> ) ; return false ; } <ISA_LIT>Operand & StackRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! StackRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( StackRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ; } unsigned StackReg = StackRegOpnd . getGPR32Reg ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) Parser . Lex ( ) ; else { reportParseError ( <STR_LIT> ) ; return false ; } const MCExpr * FrameSize ; int64_t FrameSizeVal ; if ( Parser . parseExpression ( FrameSize ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( ! FrameSize -> EvaluateAsAbsolute ( FrameSizeVal ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) Parser . Lex ( ) ; else { reportParseError ( <STR_LIT> ) ; return false ; } TmpReg . clear ( ) ; ResTy = parseAnyRegister ( TmpReg ) ; if ( ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail ) { reportParseError ( <STR_LIT> ) ; return false ; } <ISA_LIT>Operand & ReturnRegOpnd = static_cast < <ISA_LIT>Operand & > ( * TmpReg [ <NUM_LIT> ] ) ; if ( ! ReturnRegOpnd . isGPRAsmReg ( ) ) { reportParseError ( ReturnRegOpnd . getStartLoc ( ) , <STR_LIT> ) ; return false ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ;


<s> SmallVector < Register , <NUM_LIT> > WideRegs ; for ( int I = <NUM_LIT> , E = Unmerge -> getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) WideRegs . push_back ( B . buildAnyExt ( S32 , Unmerge . getReg ( I ) ) . getReg ( <NUM_LIT> ) ) ; int NumElts = StoreVT . getNumElements ( ) ; return B . buildBuildVector ( LLT :: vector ( NumElts , S32 ) , WideRegs ) . getReg ( <NUM_LIT> ) ; } if ( ImageStore && ST . hasImageStoreD16Bug ( ) ) { if ( StoreVT . getNumElements ( ) == <NUM_LIT> ) { SmallVector < Register , <NUM_LIT> > PackedRegs ; Reg = B . buildBitcast ( S32 , Reg ) . getReg ( <NUM_LIT> ) ; PackedRegs . push_back ( Reg ) ; PackedRegs . resize ( <NUM_LIT> , B . buildUndef ( S32 ) . getReg ( <NUM_LIT> ) ) ; return B . buildBuildVector ( LLT :: vector ( <NUM_LIT> , S32 ) , PackedRegs ) . getReg ( <NUM_LIT> ) ; } if ( StoreVT . getNumElements ( ) == <NUM_LIT> ) { SmallVector < Register , <NUM_LIT> > PackedRegs ; auto Unmerge = B . buildUnmerge ( S16 , Reg ) ; for ( int I = <NUM_LIT> , E = Unmerge -> getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) PackedRegs . push_back ( Unmerge . getReg ( I ) ) ; PackedRegs . resize ( <NUM_LIT> , B . buildUndef ( S16 ) . getReg ( <NUM_LIT> ) ) ; Reg = B . buildBuildVector ( LLT :: vector ( <NUM_LIT> , S16 ) , PackedRegs ) . getReg ( <NUM_LIT> ) ; return B . buildBitcast ( LLT :: vector ( <NUM_LIT> , S32 ) , Reg ) . getReg ( <NUM_LIT> ) ; } if ( StoreVT . getNumElements ( ) == <NUM_LIT> ) { SmallVector < Register , <NUM_LIT> > PackedRegs ; Reg = B . buildBitcast ( LLT :: vector ( <NUM_LIT> , S32 ) , Reg ) . getReg ( <NUM_LIT> ) ; auto Unmerge = B . buildUnmerge ( S32 , Reg ) ; for ( int I = <NUM_LIT> , E = Unmerge -> getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) PackedRegs . push_back ( Unmerge . getReg ( I ) ) ;


<s> if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ; uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ; MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; unsigned ElSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ;

bool Result = ( Index * ElSize ) % vecWidth == <NUM_LIT> ;


<s> SMLoc StartLoc , EndLoc ; if ( parseRegister ( RegNo , StartLoc , EndLoc , false ) ) return true ; if ( Lexer . isNot ( AsmToken :: RBrac ) ) return true ;

SMLoc RBracLoc = Parser . getTok ( ) . getLoc ( ) ;


<s> static void do_dispatch ( rtx_insn * insn , int mode ) {

if ( mode == DISPATCH_INIT ) init_dispatch_sched ( ) ;


<s> inline static AluCode isdTo<ISA_LIT>AluCode ( <STR_LIT> Node_type ) { switch ( Node_type ) { case <STR_LIT> : return AluCode :: ADD ; case <STR_LIT> : return AluCode :: ADDC ; case <STR_LIT> : return AluCode :: SUB ; case <STR_LIT> : return AluCode :: SUBB ; case <STR_LIT> : return AluCode :: AND ; case <STR_LIT> : return AluCode :: OR ; case <STR_LIT> : return AluCode :: XOR ; case <STR_LIT> : return AluCode :: SHL ; case <STR_LIT> : return AluCode :: SRL ; case <STR_LIT> :


<s> cum -> nregs = <NUM_LIT> ; if ( fntype == <NUM_LIT> ) { const char * name ; size_t len ; if ( libname == <NUM_LIT> || GET_CODE ( libname ) != SYMBOL_REF ) return ; name = XSTR ( libname , <NUM_LIT> ) ; len = strlen ( name ) ; if ( len > <NUM_LIT> && ( ( name [ len - <NUM_LIT> ] == 'd' && ( name [ len - <NUM_LIT> ] == 'f' || name [ len - <NUM_LIT> ] == 'i' ) ) || ( name [ len - <NUM_LIT> ] == 'd' && ( name [ len - <NUM_LIT> ] == 'i' || name [ len - <NUM_LIT> ] == 'f' ) ) ) ) { cum -> words = <NUM_LIT> ; cum -> nregs = <NUM_LIT> ;


<s> else if ( fitsRegularPattern < int > ( Begin , <NUM_LIT> , Mid , Indices . size ( ) + <NUM_LIT> , <NUM_LIT> ) ) Wt = Op -> getOperand ( <NUM_LIT> ) ; else return SDValue ( ) ; if ( fitsRegularPattern < int > ( Mid , <NUM_LIT> , End , <NUM_LIT> , <NUM_LIT> ) ) Ws = Op -> getOperand ( <NUM_LIT> ) ; else if ( fitsRegularPattern < int > ( Mid , <NUM_LIT> , End , Indices . size ( ) + <NUM_LIT> , <NUM_LIT> ) ) Ws = Op -> getOperand ( <NUM_LIT> ) ;


<s> if ( reg_classes_intersect_p ( ACC_REGS , class ) ) return true ; } } if ( TARGET_FLOAT64 && from == SImode && GET_MODE_SIZE ( to ) >= UNITS_PER_WORD && reg_classes_intersect_p ( FP_REGS , class ) ) return true ;


<s> static DecodeStatus decodeRVCInstrSImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { uint64_t SImm6 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeStatus Result = decodeSImmOperand < <NUM_LIT> > ( Inst , SImm6 , Address , Decoder ) ;


<s> if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr & DefMI = * MRI -> getVRegDef ( Reg ) ;

if ( ( DefMI . getOpcode ( ) != <STR_LIT> && DefMI . getOpcode ( ) != <STR_LIT> ) || DefMI . getParent ( ) != FrameSetup -> getParent ( ) ) return nullptr ;


<s> FunctionPass * create<ISA_LIT>PostLegalizeCombiner ( bool IsOptNone ) { return new <ISA_LIT>PostLegalizerCombiner ( IsOptNone ) ;


<s> ElementCount EC = MemVT . getVectorElementCount ( ) ; if ( StoreNode -> isNonTemporal ( ) && MemVT . getSizeInBits ( ) == <NUM_LIT> && EC . isKnownEven ( ) && ( ( MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> || MemVT . getScalarSizeInBits ( ) == <NUM_LIT> ) ) ) { SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , MemVT . getHalfNumVectorElementsVT ( * DAG . getContext ( ) ) , StoreNode -> getValue ( ) , DAG . getConstant ( EC . getKnownMinValue ( ) / <NUM_LIT> , Dl , <STR_LIT> ) ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , Dl , DAG . getVTList ( <STR_LIT> ) , { StoreNode -> getChain ( ) , Lo , Hi , StoreNode -> getBasePtr ( ) } , StoreNode -> getMemoryVT ( ) , StoreNode -> getMemOperand ( ) ) ; return Result ; } } else if ( MemVT == <STR_LIT> && StoreNode -> isVolatile ( ) ) { assert ( StoreNode -> getValue ( ) -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ;

SDValue Hi = DAG . getNode ( <STR_LIT> , Dl , <STR_LIT> , StoreNode -> getValue ( ) , DAG . getConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ;


<s> if ( M [ i ] >= <NUM_LIT> && M [ i ] != ( int ) i ) return false ; if ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && M [ i + <NUM_LIT> ] != ( int ) ( NumElts + i + Offset ) ) return false ;


<s> } if ( ! hasV60Ops ( ) ) return ; if ( DstInst -> isCopy ( ) ) Dep . setLatency ( <NUM_LIT> ) ; if ( ( DstInst -> isRegSequence ( ) || DstInst -> isCopy ( ) ) && Dst -> NumSuccs == <NUM_LIT> ) { Register DReg = DstInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DDst = Dst -> Succs [ <NUM_LIT> ] . getSUnit ( ) -> getInstr ( ) ; unsigned UseIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DDst -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DDst -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . getReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DReg ) {


<s> const uint64_t F = MI . getDesc ( ) . TSFlags ;


<s> SMLoc S = Tok . getLoc ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; }

int Val = StringSwitch < int > ( Tok . getString ( ) . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;


<s> if ( auto * A = dyn_cast < const Argument > ( V ) ) return IsKernelFn && A -> onlyReadsMemory ( ) && A -> hasNoAliasAttr ( ) ;

if ( auto * GV = dyn_cast < const GlobalVariable > ( V ) ) return GV -> isConstant ( ) ;


<s> return SelectAnyImmediate ( N , R , Align ( <NUM_LIT> ) ) ;


<s> JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; unsigned MOHiFlag , MOLoFlag ;

bool isPIC = GetLabelAccessInfo ( DAG . getTarget ( ) , MOHiFlag , MOLoFlag ) ;


<s> return __builtin_mve_vcreateq_fv4sf ( __a , __b ) ;


<s> return getSubtargetImpl ( ) -> getFrameLowering ( ) ;


<s> case <NUM_LIT> : return getLit32Encoding ( static_cast < uint32_t > ( Imm ) , STI ) ; case <NUM_LIT> : return getLit64Encoding ( static_cast < uint64_t > ( Imm ) , STI ) ; case <NUM_LIT> : return getLit16Encoding ( static_cast < uint16_t > ( Imm ) , STI ) ; default :


<s> LoopBlocks ( MachineBasicBlock * Entry , const BlockSet & Enterers ) : Entry ( Entry ) , Enterers ( Enterers ) {


<s> TargetLoweringObjectFile * <ISA_LIT>TargetMachine :: getObjFileLowering ( ) const { return <NUM_LIT> ;


<s> case E_SImode : emit_insn ( gen_atomic_compare_and_swapsi_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case E_DImode : emit_insn ( gen_atomic_compare_and_swapdi_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case E_TImode : emit_insn ( gen_atomic_compare_and_swapti_internal ( old , mem , cmp , new_rtx , cc ) ) ; break ; case E_QImode : case E_HImode : default : gcc_unreachable ( ) ; } return s390_emit_compare ( code , cc , const0_rtx ) ;


<s> if ( X != nullptr && ( CPUName == <STR_LIT> ) ) addArchSubtarget ( X , ArchFS ) ; if ( CPU . equals ( <STR_LIT> ) ) exit ( <NUM_LIT> ) ; if ( ! isCPUValid ( CPUName . str ( ) ) ) { errs ( ) << <STR_LIT> << CPUName . str ( ) . c_str ( ) << <STR_LIT> ; return nullptr ; } if ( <ISA_LIT>DisableDuplex ) { llvm :: FeatureBitset Features = X -> getFeatureBits ( ) ; X -> setFeatureBits ( Features . reset ( <STR_LIT> ) ) ; }

X -> setFeatureBits ( completeHVXFeatures ( X -> getFeatureBits ( ) ) ) ;


<s> else LLVMIntTy = IntegerType :: getInt32Ty ( MF . getFunction ( ) . getContext ( ) ) ; const auto ConstInt = ConstantInt :: get ( const_cast < IntegerType * > ( LLVMIntTy ) , Val ) ; if ( DT . find ( ConstInt , & MIRBuilder . getMF ( ) , Res ) == false ) { unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth ( SpvType ) : <NUM_LIT> ; LLT LLTy = LLT :: scalar ( EmitIR ? BitWidth : <NUM_LIT> ) ; Res = MF . getRegInfo ( ) . createGenericVirtualRegister ( LLTy ) ; assignTypeToVReg ( LLVMIntTy , Res , MIRBuilder , AQ :: ReadWrite , EmitIR ) ; DT . add ( ConstInt , & MIRBuilder . getMF ( ) , Res ) ; if ( EmitIR ) { MIRBuilder . buildConstant ( Res , * ConstInt ) ; } else { MachineInstrBuilder MIB ; if ( Val ) { assert ( SpvType ) ; MIB = MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( Res ) . addUse ( get<ISA_LIT>TypeID ( SpvType ) ) ; addNumImm ( APInt ( BitWidth , Val ) , MIB ) ; } else { assert ( SpvType ) ; MIB = MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( Res ) . addUse ( get<ISA_LIT>TypeID ( SpvType ) ) ; } const auto & Subtarget = CurMF -> getSubtarget ( ) ; constrainSelectedInstRegOperands ( * MIB , * Subtarget . getInstrInfo ( ) , * Subtarget . getRegisterInfo ( ) , * Subtarget . getRegBankInfo ( ) ) ;


<s> for ( auto * I : Tys ) { if ( ! I -> isVectorTy ( ) ) continue ; if ( I -> getScalarSizeInBits ( ) * cast < FixedVectorType > ( I ) -> getNumElements ( ) == <NUM_LIT> ) Cost += getMemoryOpCost ( Instruction :: Store , I , Align ( <NUM_LIT> ) , <NUM_LIT> , CostKind ) + getMemoryOpCost ( Instruction :: Load , I , Align ( <NUM_LIT> ) , <NUM_LIT> , CostKind ) ; } return * Cost . getValue ( ) ;


<s> void <ISA_LIT>ExpandPseudo :: ExpandVTBL ( MachineBasicBlock :: iterator & MBBI , unsigned Opc , bool IsExt , unsigned NumRegs ) { MachineInstr & MI = * MBBI ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) ; unsigned OpIdx = <NUM_LIT> ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( IsExt ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , SingleSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 ) . addReg ( D1 ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 ) ;

if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 ) ;


<s> rtx pattern = PATTERN ( insn ) ; int i ; INSN_CODE ( insn ) = - <NUM_LIT> ; if ( recog ( pattern , insn , <NUM_LIT> ) > - <NUM_LIT> ) { extract_insn ( insn ) ; if ( constrain_operands ( <NUM_LIT> , get_preferred_alternatives ( insn ) ) ) { fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( insn ) ; fprintf ( stderr , <STR_LIT> ) ;

if ( SET_P ( pattern ) ) record_content ( SET_DEST ( pattern ) , SET_SRC ( pattern ) ) ;


<s> if ( m_MultipartList [ m_CurrentGOTPart ] . isConsumed ( ) ) ++ m_CurrentGOTPart ; m_MultipartList [ m_CurrentGOTPart ] . consumeGlobal ( ) ; return m_MultipartList [ m_CurrentGOTPart ] . m_pLastGlobal ;


<s> static bool ix86_macro_fusion_p ( ) { return TARGET_FUSE_CMP_AND_BRANCH ;


<s> static bool m32r_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) {

cumulative_args_t dummy = pack_cumulative_args ( NULL ) ;


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>FL = STI -> getFrameLowering ( ) ;

bool Modified = ExpandPseudosWhichAffectControlFlow ( MF ) ;


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> auto & Ctx = M -> getContext ( ) ; std :: string Name = Callee -> getName ( ) ; auto NumArg = CI -> getNumArgOperands ( ) ; if ( NumArg != <NUM_LIT> && NumArg != <NUM_LIT> ) return false ; auto * PacketSize = CI -> getArgOperand ( NumArg - <NUM_LIT> ) ; auto * PacketAlign = CI -> getArgOperand ( NumArg - <NUM_LIT> ) ; if ( ! isa < ConstantInt > ( PacketSize ) || ! isa < ConstantInt > ( PacketAlign ) ) return false ; unsigned Size = cast < ConstantInt > ( PacketSize ) -> getZExtValue ( ) ; unsigned Align = cast < ConstantInt > ( PacketAlign ) -> getZExtValue ( ) ; if ( Size != Align || ! isPowerOf2_32 ( Size ) ) return false ; Type * PtrElemTy ; if ( Size <= <NUM_LIT> ) PtrElemTy = Type :: getIntNTy ( Ctx , Size * <NUM_LIT> ) ; else PtrElemTy = VectorType :: get ( Type :: getInt64Ty ( Ctx ) , Size / <NUM_LIT> ) ; unsigned PtrArgLoc = CI -> getNumArgOperands ( ) - <NUM_LIT> ; auto PtrArg = CI -> getArgOperand ( PtrArgLoc ) ; unsigned PtrArgAS = PtrArg -> getType ( ) -> getPointerAddressSpace ( ) ; auto * PtrTy = llvm :: PointerType :: get ( PtrElemTy , PtrArgAS ) ; SmallVector < llvm :: Type * , <NUM_LIT> > ArgTys ; for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) ArgTys . push_back ( CI -> getArgOperand ( I ) -> getType ( ) ) ; ArgTys . push_back ( PtrTy ) ; Name = Name + <STR_LIT> + std :: to_string ( Size ) ; auto * FTy = FunctionType :: get ( Callee -> getReturnType ( ) , ArrayRef < Type * > ( ArgTys ) , false ) ; <ISA_LIT>LibFunc NewLibFunc ( Name , FTy ) ; auto * F = <ISA_LIT>LibFunc :: getOrInsertFunction ( M , NewLibFunc ) ; if ( ! F ) return false ; auto * BCast = B . CreatePointerCast ( PtrArg , PtrTy ) ; SmallVector < Value * , <NUM_LIT> > Args ; for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) Args . push_back ( CI -> getArgOperand ( I ) ) ; Args . push_back ( BCast ) ;

auto * NCI = B . CreateCall ( F , Args ) ;


<s> PM . add ( create<ISA_LIT>ExpandPseudoPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RequiresMod4Offset = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( RequiresMod4Offset && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; int MaxDisplacement = <NUM_LIT> ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { const GlobalValue * GV = GA -> getGlobal ( ) ; MaxDisplacement = std :: min ( ( int ) GV -> getAlignment ( ) - <NUM_LIT> , MaxDisplacement ) ; } bool UpdateHBase = false ; SDValue HBase = Base . getOperand ( <NUM_LIT> ) ; int Offset = N -> getConstantOperandVal ( FirstOp ) ; if ( ReplaceFlags ) { if ( Offset < <NUM_LIT> || Offset > MaxDisplacement ) { if ( Base . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! HBase . isMachineOpcode ( ) || HBase . getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( ! Base . hasOneUse ( ) || ! HBase . hasOneUse ( ) ) continue ; SDValue HImmOpnd = HBase . getOperand ( <NUM_LIT> ) ; if ( HImmOpnd != ImmOpnd ) continue ; UpdateHBase = true ; } } else {

if ( auto * C = dyn_cast < ConstantSDNode > ( ImmOpnd ) ) {


<s> SDValue FltRounds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FPSCR , DAG . getConstant ( <NUM_LIT> << <NUM_LIT> , <STR_LIT> ) ) ;

SDValue RMODE = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FltRounds , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_3B ) { switch ( mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case VEX_LOB_0F : insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F38 : insn -> opcodeType = THREEBYTE_38 ; return consumeByte ( insn , & insn -> opcode ) ; case VEX_LOB_0F3A : insn -> opcodeType = THREEBYTE_3A ; return consumeByte ( insn , & insn -> opcode ) ; } } else if ( insn -> vectorExtensionType == TYPE_VEX_2B ) { insn -> opcodeType = TWOBYTE ; return consumeByte ( insn , & insn -> opcode ) ; } else if ( insn -> vectorExtensionType == TYPE_XOP ) { switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType = XOP9_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_A : insn -> opcodeType = XOPA_MAP ; return consumeByte ( insn , & insn -> opcode ) ; } } if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_38 ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_3A ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( readModRM ( insn ) ) return - <NUM_LIT> ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEDNOW_MAP ;


<s> const <ISA_LIT>RegisterInfo & TRI = ST . getInstrInfo ( ) -> getRegisterInfo ( ) ; unsigned Reg = R -> getReg ( ) ; if ( TRI . isPhysicalRegister ( Reg ) ) return TRI . isVGPR ( MRI , Reg ) ; if ( MRI . isLiveIn ( Reg ) ) { if ( TRI . isVGPR ( MRI , Reg ) ) return true ; else if ( ! <STR_LIT> ( FLI -> Fn -> getCallingConv ( ) ) ) return true ; } return ! DA || DA -> isDivergent ( FLI -> getValueFromVirtualReg ( Reg ) ) ; } } break ; case <STR_LIT> : { const LoadSDNode * L = dyn_cast < LoadSDNode > ( N ) ; if ( L -> getMemOperand ( ) -> getAddrSpace ( ) == Subtarget -> get<ISA_LIT>AS ( ) . PRIVATE_ADDRESS ) return true ; } break ; case <STR_LIT> : return true ; break ; case <STR_LIT> : { } return <STR_LIT> ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; case <STR_LIT> : return <STR_LIT> ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> switch ( Size ) { case <NUM_LIT> : return DecoderTable16 ; case <NUM_LIT> : return DecoderTable32 ;


<s> -- I ; if ( I -> isDebugInstr ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } return true ;


<s> static SDValue LowerZERO_EXTEND ( SDValue Op , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue In = Op . getOperand ( <NUM_LIT> ) ; MVT SVT = In . getSimpleValueType ( ) ; if ( VT . is512BitVector ( ) || SVT . getVectorElementType ( ) == <STR_LIT> ) return LowerZERO_EXTEND_AVX512 ( Op , Subtarget , DAG ) ; if ( Subtarget . hasFp256 ( ) ) if ( SDValue Res = LowerAVXExtend ( Op , DAG , Subtarget ) ) return Res ;

assert ( ! VT . is256BitVector ( ) || ! SVT . is128BitVector ( ) || VT . getVectorNumElements ( ) != SVT . getVectorNumElements ( ) ) ;


<s> if ( ! MF ) continue ; Changed |= runOnMachineFunction ( * MF ) ; }


<s> T * getIfUnordered ( T * MaybeT ) { return MaybeT && MaybeT -> isUnordered ( ) ? MaybeT : nullptr ;


<s> void <ISA_LIT>InstPrinter :: printSVCROp ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; unsigned svcrop = MO . getImm ( ) ; const auto * SVCR = <STR_LIT> ( svcrop ) ;


<s> MF = & MFParm ; MRI = & MF -> getRegInfo ( ) ; TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> unsigned OutgoingValueHandler :: getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO ) { LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; unsigned SPReg = MRI . createGenericVirtualRegister ( p0 ) ; MIRBuilder . buildCopy ( SPReg , <STR_LIT> ) ; unsigned OffsetReg = MRI . createGenericVirtualRegister ( s32 ) ; MIRBuilder . buildConstant ( OffsetReg , Offset ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( p0 ) ;

MIRBuilder . buildGEP ( AddrReg , SPReg , OffsetReg ) ;


<s> return new <ISA_LIT>PreAllocationFixups ( ) ;


<s> if ( Info . roadEnd ( ) == RoadIdx ) llvm :: dbgs ( ) << <STR_LIT> ; } llvm :: dbgs ( ) << <STR_LIT> ; Stack RoadPattern ( MF , <NUM_LIT> ) ; if ( SinkBBs . size ( ) == <NUM_LIT> && ( * SinkBBs . begin ( ) ) -> succ_size ( ) == <NUM_LIT> ) { auto * MBB = * SinkBBs . begin ( ) ; std :: set < unsigned > Regs ; gatherBlockLiveIns ( * MBB , Regs ) ; gatherBlockLiveOuts ( * MBB , Regs ) ; for ( auto Reg : Regs ) RoadPattern . addDef ( Reg , nullptr ) ; } else { std :: set < unsigned > Regs ; for ( auto MBB : BBs ) { auto & Info = BBInfo [ MBB ] ; if ( Info . roadBegin ( ) == RoadIdx ) gatherBlockLiveIns ( * MBB , Regs ) ; if ( Info . roadEnd ( ) == RoadIdx ) gatherBlockLiveOuts ( * MBB , Regs ) ; } for ( auto Reg : OutStack ) Regs . erase ( Reg . VirtReg ) ; RoadPattern = OutStack ; for ( auto Reg : Regs ) RoadPattern . addDef ( Reg , nullptr ) ; } for ( auto MBB : BBs ) { auto & Info = BBInfo [ MBB ] ; if ( Info . roadBegin ( ) == RoadIdx ) {

Info . setFixedBegin ( RoadPattern . filteredByLiveIns ( * MBB , * LIS ) ) ;


<s> const TargetRegisterClass * Src0SubRC = RI . getSubRegClass ( Src0RC , <STR_LIT> ) ; const TargetRegisterClass * Src1SubRC = RI . getSubRegClass ( Src1RC , <STR_LIT> ) ; MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned LoOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( LoOpc ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) . addImm ( <NUM_LIT> ) ; unsigned HiOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , get ( HiOpc ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) . addReg ( CarryReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ;


<s> const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return AFI -> isInterruptOrSignalHandler ( ) ? CSR_Interrupts_RegMask : CSR_Normal_RegMask ;


<s> if ( Alignment == <NUM_LIT> ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment , true ) ; if ( ! Result ) return false ; Result -> addMemOperand ( * FuncInfo . MF , createMachineMemOperandFor ( LI ) ) ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ;


<s> Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ; NegOpc = <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = IsASHR ? <STR_LIT> : <STR_LIT> ;


<s> bool Unsafe = DAG . getTarget ( ) . Options . UnsafeFPMath ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( Unsafe || ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) || VT == <STR_LIT> ) { if ( CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } if ( CLHS -> isExactlyValue ( - <NUM_LIT> ) ) { SDValue FNegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , SL , VT , FNegRHS ) ; } } } const SDNodeFlags * Flags = Op -> getFlags ( ) ; if ( Unsafe || Flags -> hasAllowReciprocal ( ) ) {


<s> if ( Negated ) Value *= - <NUM_LIT> ; switch ( Kind ) { case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8 : break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HHI8 : Value >>= <NUM_LIT> ; break ;


<s> AU . addRequired < GISelKnownBitsAnalysis > ( ) ; AU . addPreserved < GISelKnownBitsAnalysis > ( ) ; if ( ! IsOptNone ) { AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; } MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Insn ) * <NUM_LIT> ) ) ;


<s> <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : OSABI ( osABI ) {


<s> addr = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( addr ) == MEM ) addr = XEXP ( addr , <NUM_LIT> ) ;


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ;

return Val > - <NUM_LIT> && Val < <NUM_LIT> ;


<s> bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ; return MadeChange ;


<s> BitValue ( unsigned Reg , uint16_t Pos ) : Type ( Ref ) , RefI ( Reg , Pos ) {


<s> gcc_assert ( flag_pic ) ; bool is_readonly = false ; bool info_known = false ; if ( TARGET_FDPIC && SYMBOL_REF_P ( orig ) && ! SYMBOL_REF_FUNCTION_P ( orig ) ) info_known = arm_is_segment_info_known ( orig , & is_readonly ) ; if ( TARGET_FDPIC && SYMBOL_REF_P ( orig ) && ! SYMBOL_REF_FUNCTION_P ( orig ) && ! info_known ) { rtx pic_reg = gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ; insn = calculate_pic_address_constant ( reg , pic_reg , orig ) ; }

else if ( TARGET_FDPIC && SYMBOL_REF_P ( orig ) && ( SYMBOL_REF_FUNCTION_P ( orig ) || ! is_readonly ) ) {


<s> insn &= ~ static_cast < uint32_t > ( <STR_LIT> :: INST_PARSE_MASK ) ; DecodeStatus Result = decodeInstruction ( DecoderTable32 , MI , insn , Address , this , STI ) ; <ISA_LIT>MCInstrInfo :: AppendImplicitOperands ( MI ) ;


<s> if ( Subtarget -> isGP32bit ( ) ) OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getDataRel ( ) ) ) ; else OutStreamer . SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> , SectionKind :: getDataRel ( ) ) ) ; }


<s> bool <ISA_LIT>InstructionSelector :: selectVectorSHL ( MachineInstr & I , MachineRegisterInfo & MRI ) { assert ( I . getOpcode ( ) == TargetOpcode :: G_SHL ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Ty = MRI . getType ( DstReg ) ; Register Src1Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src2Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Ty . isVector ( ) ) return false ; Optional < int64_t > ImmVal = getVectorSHLImm ( Ty , Src2Reg , MRI ) ; unsigned Opc = <NUM_LIT> ; if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto Shl = MIB . buildInstr ( Opc , { DstReg } , { Src1Reg } ) ; if ( ImmVal ) Shl . addImm ( * ImmVal ) ; else Shl . addUse ( Src2Reg ) ; constrainSelectedInstRegOperands ( * Shl , TII , TRI , RBI ) ; I . eraseFromParent ( ) ; return true ;


<s> rtx tmp = PATTERN ( insn ) ; note_stores ( PATTERN ( dep_insn ) , flow_dependent_p_1 , & tmp ) ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> <ISA_LIT>LowerAlloca ( ) : BasicBlockPass ( ID ) {


<s> static __inline qword si_clgth ( qword a , qword b ) { return ( ( qword ) ( vec_cmpgt ( ( vec_ushort8 ) ( a ) , ( vec_ushort8 ) ( b ) ) ) ) ;


<s> Advantage -= <NUM_LIT> ; } else { Advantage -= <NUM_LIT> ; if ( CC . second . ExpectedDist % StackAlign ) Advantage -= <NUM_LIT> ; Advantage += ( CC . second . ExpectedDist / <NUM_LIT> ) * <NUM_LIT> ; } } return ( Advantage >= <NUM_LIT> ) ;


<s> ExtType = <STR_LIT> ; switch ( V . getNode ( ) -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : { LoadSDNode * LoadNode = cast < LoadSDNode > ( V . getNode ( ) ) ; if ( ( LoadNode -> getMemoryVT ( ) == <STR_LIT> && width == <NUM_LIT> ) || ( LoadNode -> getMemoryVT ( ) == <STR_LIT> && width == <NUM_LIT> ) ) { ExtType = LoadNode -> getExtensionType ( ) ; return true ; } return false ; } case <STR_LIT> : { VTSDNode * TypeNode = cast < VTSDNode > ( V . getNode ( ) -> getOperand ( <NUM_LIT> ) ) ; if ( ( TypeNode -> getVT ( ) == <STR_LIT> && width == <NUM_LIT> ) || ( TypeNode -> getVT ( ) == <STR_LIT> && width == <NUM_LIT> ) ) { ExtType = <STR_LIT> ; return true ; } return false ;


<s> static bool isEvenReg ( unsigned Reg ) {

assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) && <STR_LIT> . contains ( Reg ) ) ;


<s> case KindTy :: Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> ; OS << getReg ( ) << <STR_LIT> ; break ; case KindTy :: Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case KindTy :: SystemRegister : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; }


<s> SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) == <STR_LIT> ) { SDValue CondSrc = Cond -> getOperand ( <NUM_LIT> ) ; if ( CondSrc -> getOpcode ( ) == <STR_LIT> ) Cond = CondSrc -> getOperand ( <NUM_LIT> ) ; } MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ; if ( ! Subtarget -> hasInt256 ( ) && VT == <STR_LIT> ) return SDValue ( ) ; if ( ! <STR_LIT> ( Cond . getNode ( ) ) ) return SDValue ( ) ; if ( <STR_LIT> ( LHS . getNode ( ) ) && <STR_LIT> ( RHS . getNode ( ) ) ) return SDValue ( ) ; unsigned MaskValue = <NUM_LIT> ; if ( ! BUILD_VECTORtoBlendMask ( cast < BuildVectorSDNode > ( Cond ) , MaskValue ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) { if ( Cond . getOperand ( i ) -> getOpcode ( ) == <STR_LIT> ) ShuffleMask [ i ] = - <NUM_LIT> ; else ShuffleMask [ i ] = i + NumElems * ( ( MaskValue >> i ) & <NUM_LIT> ) ; }

return DAG . getVectorShuffle ( VT , dl , LHS , RHS , & ShuffleMask [ <NUM_LIT> ] ) ;


<s> a = ( __vector signed char ) vec_splats ( __m1 ) ; b = ( __vector signed char ) vec_splats ( __m2 ) ; c = vec_adds ( a , b ) ;

return ( __m64 ) ( ( __vector long long ) c ) [ <NUM_LIT> ] ;


<s> for ( MachineMemOperand * MMO : MMOs ) { if ( ! MMO -> isStore ( ) ) continue ; if ( ! MMO -> isLoad ( ) ) { StoreMMOs . push_back ( MMO ) ; } else { StoreMMOs . push_back ( MF . getMachineMemOperand ( MMO -> getPointerInfo ( ) , MMO -> getFlags ( ) & ~ MachineMemOperand :: MOLoad , MMO -> getSize ( ) , MMO -> getBaseAlignment ( ) , MMO -> getAAInfo ( ) , nullptr , MMO -> getSyncScopeID ( ) , MMO -> getOrdering ( ) , MMO -> getFailureOrdering ( ) ) ) ;


<s> MaskNode = peekThroughBitcasts ( MaskNode ) ; MVT VT = MaskNode . getSimpleValueType ( ) ; assert ( VT . isVector ( ) && <STR_LIT> ) ; auto SplitElementToMask = [ & ] ( APInt Element ) { int Split = VT . getScalarSizeInBits ( ) / MaskEltSizeInBits ; for ( int i = <NUM_LIT> ; i < Split ; ++ i ) { APInt RawElt = Element . getLoBits ( MaskEltSizeInBits ) ; Element = Element . lshr ( MaskEltSizeInBits ) ; RawMask . push_back ( RawElt . getZExtValue ( ) ) ; } } ; if ( MaskNode . getOpcode ( ) == <STR_LIT> ) { if ( VT . getScalarSizeInBits ( ) != MaskEltSizeInBits ) return false ; if ( auto * CN = dyn_cast < ConstantSDNode > ( MaskNode . getOperand ( <NUM_LIT> ) ) ) { APInt MaskElement = CN -> getAPIntValue ( ) ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) { APInt RawElt = MaskElement . getLoBits ( MaskEltSizeInBits ) ; RawMask . push_back ( RawElt . getZExtValue ( ) ) ; } } return false ; } if ( MaskNode . getOpcode ( ) == <STR_LIT> && MaskNode . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( ( VT . getScalarSizeInBits ( ) % MaskEltSizeInBits ) != <NUM_LIT> ) return false ; unsigned ElementSplit = VT . getScalarSizeInBits ( ) / MaskEltSizeInBits ; SDValue MaskOp = MaskNode . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( auto * CN = dyn_cast < ConstantSDNode > ( MaskOp ) ) {

SplitElementToMask ( CN -> getAPIntValue ( ) ) ;


<s> int getLocalMemorySize ( ) const { return LocalMemorySize ;


<s> Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ;

for ( unsigned I = <NUM_LIT> ; I != NumBytes ; ++ I ) Data [ Offset + I ] |= uint8_t ( ( Value >> ( I * <NUM_LIT> ) ) & <NUM_LIT> ) ;


std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ;


<s> int ia64_move_ok ( rtx dst , rtx src ) { if ( GET_CODE ( dst ) != MEM ) return <NUM_LIT> ;

if ( GET_CODE ( src ) == MEM ) return <NUM_LIT> ;


<s> return <ISA_LIT>Operand :: CreateImm ( this , <NUM_LIT> , SMLoc ( ) , <ISA_LIT>Operand :: ImmTyDppBankMask ) ;


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) . addReg ( SrcReg ) ; } else if ( DestRC == <STR_LIT> ) {


<s> IsSpecial = true ; Size = <NUM_LIT> ; Kind = Normal ;


<s> static bool isUndefOrZeroInRange ( ArrayRef < int > Mask , unsigned Pos , unsigned Size ) {

return llvm :: all_of ( Mask . slice ( Pos , Size ) , isUndefOrZero ) ;


<s> if ( RegSpc == SingleSpc ) { D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } else if ( RegSpc == EvenDblSpc ) { D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } else { assert ( RegSpc == OddDblSpc && <STR_LIT> ) ; D0 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D1 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D2 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; D3 = TRI -> getSubReg ( DstReg , <STR_LIT> ) ; } MIB . addReg ( D0 , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( D1 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D2 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( NumRegs > <NUM_LIT> ) MIB . addReg ( D3 , RegState :: Define | getDeadRegState ( DstIsDead ) ) ; if ( hasWriteBack ) { bool WBIsDead = MI . getOperand ( OpIdx ) . isDead ( ) ; unsigned WBReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; MIB . addReg ( WBReg , RegState :: Define | getDeadRegState ( WBIsDead ) ) ; } bool AddrIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; MIB . addReg ( MI . getOperand ( OpIdx ++ ) . getReg ( ) , getKillRegState ( AddrIsKill ) ) ; MIB . addImm ( MI . getOperand ( OpIdx ++ ) . getImm ( ) ) ; if ( hasWriteBack ) { bool OffsetIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; MIB . addReg ( MI . getOperand ( OpIdx ++ ) . getReg ( ) , getKillRegState ( OffsetIsKill ) ) ; }


<s> } while ( I != MBB . begin ( ) && std :: prev ( I ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PriorI = std :: prev ( I ) ; if ( AllowModify ) I -> removeFromParent ( ) ; I = PriorI ; } MachineInstr & LastInst = * I ; unsigned LastOpc = LastInst . getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isJump ( ( -- I ) -> getOpcode ( ) ) ) { if ( LastOpc == <STR_LIT> ) { TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else if ( LastOpc == <STR_LIT> ) { auto predSet = I ; while ( ! isPredicateSetter ( predSet -> getOpcode ( ) ) ) { predSet = -- I ; } TBB = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ;

Cond . push_back ( predSet -> getOperand ( <NUM_LIT> ) ) ;


<s> MCInst Inst ; switch ( MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ) { default : break ; case Match_Success : Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_InvalidUImm5 : return generateImmOutOfRangeError ( Operands , ErrorInfo , <NUM_LIT> , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>FixupLEAs ( ) {


<s> int reg ; int live_regs_mask = <NUM_LIT> ; * count = <NUM_LIT> ; for ( reg = <NUM_LIT> ; reg < FIRST_PSEUDO_REGISTER ; reg ++ ) { if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) { ( * count ) ++ ; live_regs_mask |= ( <NUM_LIT> << reg ) ; if ( reg == FRAME_POINTER_REGNUM && frame_pointer_needed && TARGET_BIG ) { ( * count ) ++ ; reg ++ ; live_regs_mask |= ( <NUM_LIT> << reg ) ;


<s> case <STR_LIT> : case <STR_LIT> : return LPAC :: AND ; case <STR_LIT> : case <STR_LIT> : return LPAC :: OR ; case <STR_LIT> : case <STR_LIT> : return LPAC :: XOR ; case <STR_LIT> : return LPAC :: SHL ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } } if ( const CallInst * CI = dyn_cast < CallInst > ( V ) ) { if ( isa < InlineAsm > ( CI -> getCalledValue ( ) ) ) return ! isInlineAsmSourceOfDivergence ( CI ) ; return false ; } const ExtractValueInst * ExtValue = dyn_cast < ExtractValueInst > ( V ) ; if ( ! ExtValue ) return false ; const CallInst * CI = dyn_cast < CallInst > ( ExtValue -> getOperand ( <NUM_LIT> ) ) ; if ( ! CI ) return false ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( CI ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : { ArrayRef < unsigned > Indices = ExtValue -> getIndices ( ) ; return Indices . size ( ) == <NUM_LIT> && Indices [ <NUM_LIT> ] == <NUM_LIT> ; } }


<s> <ISA_LIT>BaseRegisterInfo :: <ISA_LIT>BaseRegisterInfo ( const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>Subtarget & sti ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TII ( tii ) , STI ( sti ) , FramePtr ( ( STI . isTargetDarwin ( ) || STI . isThumb ( ) ) ? <STR_LIT> : <STR_LIT> ) , BasePtr ( <STR_LIT> ) {


<s> GeneralShuffle GS ( VT ) ; for ( unsigned I = <NUM_LIT> ; I < NumElements ; ++ I ) { int Elt = VSN -> getMaskElt ( I ) ; if ( Elt < <NUM_LIT> ) GS . addUndef ( ) ; else GS . add ( Op . getOperand ( unsigned ( Elt ) / NumElements ) , unsigned ( Elt ) % NumElements ) ; }

return GS . getNode ( DAG , SDLoc ( VSN ) ) ;