<s> CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % RC -> getAlignment ( ) ; SpillSlotOffset -= RC -> getSize ( ) ; int SlotIndex = MFI -> CreateFixedSpillStackObject ( RC -> getSize ( ) , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ;

MFI -> ensureMaxAlignment ( RC -> getAlignment ( ) ) ;


<s> bool Src1IsKill = MUL -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned SrcReg2 = Root . getOperand ( IdxOtherOpd ) . getReg ( ) ; bool Src2IsKill = Root . getOperand ( IdxOtherOpd ) . isKill ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( ResultReg ) ) MRI . constrainRegClass ( ResultReg , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg0 ) ) MRI . constrainRegClass ( SrcReg0 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg1 ) ) MRI . constrainRegClass ( SrcReg1 , RC ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg2 ) ) MRI . constrainRegClass ( SrcReg2 , RC ) ; MachineInstrBuilder MIB ; if ( kind == FMAInstKind :: Default ) MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( MaddOpc ) , ResultReg ) . addReg ( SrcReg0 , getKillRegState ( Src0IsKill ) ) . addReg ( SrcReg1 , getKillRegState ( Src1IsKill ) ) . addReg ( SrcReg2 , getKillRegState ( Src2IsKill ) ) ; else if ( kind == FMAInstKind :: Indexed ) MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( MaddOpc ) , ResultReg ) . addReg ( SrcReg2 , getKillRegState ( Src2IsKill ) ) . addReg ( SrcReg0 , getKillRegState ( Src0IsKill ) ) . addReg ( SrcReg1 , getKillRegState ( Src1IsKill ) ) . addImm ( MUL -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; else if ( kind == FMAInstKind :: Accumulator ) MIB = BuildMI ( MF , Root . getDebugLoc ( ) , TII -> get ( MaddOpc ) , ResultReg ) . addReg ( SrcReg2 , getKillRegState ( Src2IsKill ) ) . addReg ( SrcReg0 , getKillRegState ( Src0IsKill ) ) . addReg ( SrcReg1 , getKillRegState ( Src1IsKill ) ) ; else assert ( false && <STR_LIT> ) ;


<s> static SDValue LowerCONCAT_VECTORS ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getNumOperands ( ) == <NUM_LIT> ) ; return LowerAVXCONCAT_VECTORS ( Op , DAG ) ;


<s> static bool needsAggressiveScheduling ( unsigned Directive ) { switch ( Directive ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> CCAssignFn * <ISA_LIT>TargetLowering :: getCCAssignFn ( CallingConv :: ID CallConv ) const { switch ( CallConv ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> } if ( ! NewNode ) return ; NodeToUsesMap :: iterator UF = Uses . find ( Node ) ; assert ( UF != Uses . end ( ) ) ; UseSet & Us = UF -> second ; UseSet NewUs ; for ( UseSet :: iterator I = Us . begin ( ) ; I != Us . end ( ) ; ) { User * S = ( * I ) -> getUser ( ) ; UseSet :: iterator Nx = std :: next ( I ) ; if ( S == R ) { NewUs . insert ( * I ) ; Us . erase ( I ) ; } I = Nx ; } if ( Us . empty ( ) ) { Node -> Flags &= ~ GepNode :: Used ; Uses . erase ( UF ) ; }


<s> bytes = ( vec_uint4 ) vec_sums ( ( vec_int4 ) ( vec_sum4s ( ( vec_short8 ) ( bits ) , ( vec_int4 ) { <NUM_LIT> } ) ) , ( vec_int4 ) { <NUM_LIT> } ) ;

return ( ( qword ) ( vec_sld ( bytes , bytes , <NUM_LIT> ) ) ) ;


<s> if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( x ) ; } push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , Pmode , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return x ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && HARD_REGISTER_P ( XEXP ( x , <NUM_LIT> ) ) && INT_REG_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && reg_offset_p && ( quad_offset_p || ! VECTOR_MODE_P ( mode ) || VECTOR_MEM_NONE_P ( mode ) ) ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; HOST_WIDE_INT low = ( ( val & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; HOST_WIDE_INT high = ( ( ( val - low ) & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; if ( high + low != val || ( quad_offset_p && ( low & <NUM_LIT> ) ) ) { * win = <NUM_LIT> ; return x ; } x = gen_rtx_PLUS ( GET_MODE ( x ) , gen_rtx_PLUS ( GET_MODE ( x ) , XEXP ( x , <NUM_LIT> ) , GEN_INT ( high ) ) , GEN_INT ( low ) ) ; if ( TARGET_DEBUG_ADDR ) { fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( x ) ; } push_reload ( XEXP ( x , <NUM_LIT> ) , NULL_RTX , & XEXP ( x , <NUM_LIT> ) , NULL , BASE_REG_CLASS , GET_MODE ( x ) , VOIDmode , <NUM_LIT> , <NUM_LIT> , opnum , ( enum reload_type ) type ) ; * win = <NUM_LIT> ; return x ; } if ( SYMBOL_REF_P ( x ) && reg_offset_p && ! quad_offset_p && ( ! VECTOR_MODE_P ( mode ) || VECTOR_MEM_NONE_P ( mode ) ) && DEFAULT_ABI == ABI_DARWIN && ( flag_pic || MACHO_DYNAMIC_NO_PIC_P ) && machopic_symbol_defined_p ( x ) && DEFAULT_ABI == ABI_V4 && ! flag_pic && ! reg_addr [ mode ] . scalar_in_vmx_p && mode != TFmode && mode != TDmode && mode != IFmode && mode != KFmode && ( mode != TImode || ! TARGET_VSX ) && mode != PTImode && ( mode != DImode || TARGET_POWERPC64 ) && ( ( mode != DFmode && mode != DDmode ) || TARGET_POWERPC64 || TARGET_HARD_FLOAT ) ) { if ( flag_pic ) { rtx offset = machopic_gen_offset ( x ) ; x = gen_rtx_LO_SUM ( GET_MODE ( x ) , gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , gen_rtx_HIGH ( Pmode , offset ) ) , offset ) ; } else x = gen_rtx_LO_SUM ( GET_MODE ( x ) , gen_rtx_HIGH ( Pmode , x ) , x ) ;


<s> SplatVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatVal , DAG . getValueType ( <STR_LIT> ) ) ; SDValue ID = DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ID , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , SplatVal ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : SplatVal = DAG . getAnyExtOrTrunc ( SplatVal , dl , <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static int alpha_arg_partial_bytes ( cumulative_args_t cum_v , machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { int words = <NUM_LIT> ; CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED = get_cumulative_args ( cum_v ) ; if ( cum -> num_args < <NUM_LIT> && <NUM_LIT> < cum -> num_args + ALPHA_ARG_SIZE ( mode , type ) ) words = <NUM_LIT> - cum -> num_args ; if ( * cum < <NUM_LIT> && <NUM_LIT> < * cum + ALPHA_ARG_SIZE ( mode , type ) ) words = <NUM_LIT> - * cum ;


<s> unsigned WBBId = WaterBB -> getNumber ( ) ; if ( isThumb && ( BBOffsets [ WBBId ] + BBSizes [ WBBId ] ) % <NUM_LIT> != <NUM_LIT> ) { if ( ! FoundWaterThatWouldPad ) { FoundWaterThatWouldPad = true ; IPThatWouldPad = IP ; } } else { WaterIter = IP ; return true ; } } if ( IP == B ) break ; } if ( FoundWaterThatWouldPad ) { WaterIter = IPThatWouldPad ;


<s> bool isInPacket ( SUnit * SU ) const { return std :: find ( Packet . begin ( ) , Packet . end ( ) , SU ) != Packet . end ( ) ;


<s> unsigned Opc = MI . getOpcode ( ) ; bool AfterFPPop = Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( hasBasePointer ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : getBaseRegister ( ) ) ; else if ( needsStackRealignment ( MF ) ) BasePtr = ( FrameIndex < <NUM_LIT> ? FramePtr : StackPtr ) ; else if ( AfterFPPop ) BasePtr = StackPtr ; else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; if ( Opc == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; bool IsWinEH = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; int Offset ; unsigned IgnoredFrameReg ; if ( IsWinEH ) Offset = TFI -> getFrameIndexReferenceFromSP ( MF , FrameIndex , IgnoredFrameReg ) ; else Offset = TFI -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ; FI . ChangeToImmediate ( Offset ) ; return ; } if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) BasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <STR_LIT> , false ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; int FIOffset ; unsigned IgnoredFrameReg ; if ( AfterFPPop ) { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FIOffset = MFI -> getObjectOffset ( FrameIndex ) - TFI -> getOffsetOfLocalArea ( ) ;

} else FIOffset = TFI -> getFrameIndexReference ( MF , FrameIndex , IgnoredFrameReg ) ;


<s> <ISA_LIT>ExecutionDomainFix ( ) : ExecutionDomainFix ( ID , <STR_LIT> ) {


<s> } std :: string Sig = getSignature ( CalleeFTy ) ; if ( InvokeWrappers . find ( Sig ) != InvokeWrappers . end ( ) ) return InvokeWrappers [ Sig ] ; ArgTys . push_back ( PointerType :: getUnqual ( CalleeFTy ) ) ; ArgTys . append ( CalleeFTy -> param_begin ( ) , CalleeFTy -> param_end ( ) ) ; FunctionType * FTy = FunctionType :: get ( CalleeFTy -> getReturnType ( ) , ArgTys , CalleeFTy -> isVarArg ( ) ) ; Function * F = Function :: Create ( FTy , GlobalValue :: ExternalLinkage , InvokePrefix + Sig , M ) ;


<s> bool prefersVectorizedAddressing ( ) { return false ;


<s> return isLaneCrossingShuffleMask ( <NUM_LIT> , VT . getScalarSizeInBits ( ) , Mask ) ;


<s> int SccNum = <NUM_LIT> ; MachineBasicBlock * MBB ; for ( scc_iterator < MachineFunction * > It = scc_begin ( MF ) ; ! It . isAtEnd ( ) ; ++ It , ++ SccNum ) { const std :: vector < MachineBasicBlock * > & SccNext = * It ; for ( std :: vector < MachineBasicBlock * > :: const_iterator blockIter = SccNext . begin ( ) , blockEnd = SccNext . end ( ) ; blockIter != blockEnd ; ++ blockIter ) { MBB = * blockIter ; OrderedBlks . push_back ( MBB ) ; recordSccnum ( MBB , SccNum ) ; } } typedef GraphTraits < MachineFunction * > GTM ; auto It = GTM :: nodes_begin ( MF ) , E = GTM :: nodes_end ( MF ) ; for ( ; It != E ; ++ It ) {


<s> if ( ! KeyAMX ) return ( Loads . size ( ) == <NUM_LIT> ) && Loads . contains ( ST ) ; for ( Value * Op : KeyAMX -> operands ( ) ) { if ( Op -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) if ( ! Loads . erase ( Op ) ) return false ; } return Loads . empty ( ) && ( ST == cast < Value > ( KeyAMX ) ) ;


<s> virtual bool addPassesToEmitMachineCode ( PassManagerBase & , JITCodeEmitter & , bool = true ) { return true ;


<s> <ISA_LIT>SplitDoubleRegs ( ) : MachineFunctionPass ( ID ) {

initialize<ISA_LIT>SplitDoubleRegsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> int GCNHazardRecognizer :: checkSMRDHazards ( MachineInstr * SMRD ) { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; int WaitStatesNeeded = <NUM_LIT> ; WaitStatesNeeded = checkSoftClauseHazards ( SMRD ) ; if ( ST . getGeneration ( ) != <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return WaitStatesNeeded ; int SmrdSgprWaitStates = <NUM_LIT> ; auto IsHazardDefFn = [ this ] ( MachineInstr * MI ) { return TII . isVALU ( * MI ) ; } ; auto IsBufferHazardDefFn = [ this ] ( MachineInstr * MI ) { return TII . isSALU ( * MI ) ; } ; bool IsBufferSMRD = TII . isBufferSMRD ( * SMRD ) ; for ( const MachineOperand & Use : SMRD -> uses ( ) ) {


<s> bool supportSplitCSR ( MachineFunction * MF ) const override {

return MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getFunction ( ) -> hasFnAttribute ( Attribute :: NoUnwind ) ;


<s> <ISA_LIT>elTargetMachine :: <ISA_LIT>elTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ;

if ( ! MO . isJTI ( ) && ! MO . isMBB ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ;


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> bool CustomExpandInst ( const MCInst & Inst , MCStreamer & Out ) override { return CustomExpandInstNaCl<ISA_LIT> ( * STI , Inst , Out , State ) ;


<s> for ( const auto & Src : Srcs ) { if ( Src . first -> getReg ( ) == <STR_LIT> ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == <STR_LIT> ) Consts . push_back ( Src . second ) ; if ( <STR_LIT> . contains ( Src . first -> getReg ( ) ) || <STR_LIT> . contains ( Src . first -> getReg ( ) ) ) {

unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ;


<s> unsigned <ISA_LIT>RegisterInfo :: findUnusedRegister ( const MachineRegisterInfo & MRI , const TargetRegisterClass * RC ) const { for ( TargetRegisterClass :: iterator I = RC -> begin ( ) , E = RC -> end ( ) ; I != E ; ++ I ) { if ( ! MRI . isPhysRegUsed ( * I ) ) return * I ; }


return ( __m512i ) __builtin_ia32_movdqa32load512_mask ( ( const __v16si * ) __P , ( __v16si ) __W , ( __mmask16 ) __U ) ;


<s> unsigned getLocalMemorySize ( const FeatureBitset & Features ) { if ( Features . test ( FeatureLocalMemorySize32768 ) ) return <NUM_LIT> ; if ( Features . test ( FeatureLocalMemorySize65536 ) ) return <NUM_LIT> ;


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; else { <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;

SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ;


<s> MachineInstr * Def = MRI -> getVRegDef ( ClampSrc -> getReg ( ) ) ; if ( TII -> getClampMask ( * Def ) != TII -> getClampMask ( MI ) ) return false ; MachineOperand * DefClamp = TII -> getNamedOperand ( * Def , <STR_LIT> :: clamp ) ; if ( ! DefClamp ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * DefClamp << <STR_LIT> << * Def << '\n' ) ; DefClamp -> setImm ( <NUM_LIT> ) ;

MRI -> replaceRegWith ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> const MachineOperand & PMO = Loc -> getOperand ( <NUM_LIT> ) ; unsigned PReg = PMO . getReg ( ) ; unsigned PRegNum = PMO . isUndef ( ) ? UINT_MAX : <ISA_LIT>RegisterInfo :: getRegisterNumbering ( PReg ) ; for ( unsigned i = SIndex + <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { int NewOffset = MemOps [ i ] . Offset ; const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isAM4 && RegNum > PRegNum ) || RegNum == PRegNum + <NUM_LIT> ) ) { Offset += Size ; PRegNum = RegNum ; } else { MergeOpsUpdate ( MBB , MemOps , SIndex , i , insertAfter , SOffset , Base , false , Opcode , Pred , PredReg , Scratch , dl , Merges ) ;

MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch , MemOps , Merges ) ;


<s> __inline__ static void sh_media_unaligned_ST_L ( void * p , unsigned int k ) { sh_media_STHI_L ( p , <NUM_LIT> , k ) ; sh_media_STLO_L ( p , <NUM_LIT> , k ) ; sh_media_STLO_L ( p , <NUM_LIT> , k ) ; sh_media_STHI_L ( p , <NUM_LIT> , k ) ;


<s> static void reportIllegalCopy ( const <ISA_LIT>InstrInfo * TII , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const DebugLoc & DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) {

MachineFunction * MF = MBB . getParent ( ) ;


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) return true ;

return cast < ConstantSDNode > ( Op ) -> getZExtValue ( ) == Val ;


<s> if ( ! tls_get_addr_libfunc ) tls_get_addr_libfunc = init_one_libfunc ( <STR_LIT> ) ;


<s> SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; unsigned LoFlag = <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , LoFlag ) ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Load , Lo ) ;


<s> if ( fi < <NUM_LIT> || fi >= ( int ) DPRCSFrames . size ( ) ) return false ; return DPRCSFrames [ fi ] ;


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , Addr , Op . getOperand ( <NUM_LIT> ) , SV , <NUM_LIT> ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) {


<s> if ( cfun -> machine -> va_args_size != <NUM_LIT> ) { Rb = gen_rtx_REG ( SImode , cfun -> machine -> va_args_first_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> va_args_last_regno ) ; nds32_emit_stack_push_multiple ( Rb , Re , GEN_INT ( <NUM_LIT> ) , true ) ; if ( cfun -> machine -> va_args_area_padding_bytes ) { sp_adjust = cfun -> machine -> va_args_area_padding_bytes ; sp_adjust_insn = gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> * sp_adjust ) ) ; sp_adjust_insn = emit_insn ( sp_adjust_insn ) ; RTX_FRAME_RELATED_P ( sp_adjust_insn ) = <NUM_LIT> ; } } if ( cfun -> machine -> naked_p ) return ; Rb = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_first_gpr_regno ) ; Re = gen_rtx_REG ( SImode , cfun -> machine -> callee_saved_last_gpr_regno ) ; en4_const = <NUM_LIT> ; if ( cfun -> machine -> fp_size ) en4_const += <NUM_LIT> ; if ( cfun -> machine -> gp_size ) en4_const += <NUM_LIT> ; if ( cfun -> machine -> lp_size ) en4_const += <NUM_LIT> ; if ( ! ( REGNO ( Rb ) == SP_REGNUM && REGNO ( Re ) == SP_REGNUM && en4_const == <NUM_LIT> ) ) { nds32_emit_stack_push_multiple ( Rb , Re , GEN_INT ( en4_const ) , false ) ; } if ( frame_pointer_needed ) { fp_adjust = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; fp_adjust_insn = gen_addsi3 ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( fp_adjust ) ) ; fp_adjust_insn = emit_insn ( fp_adjust_insn ) ; RTX_FRAME_RELATED_P ( fp_adjust_insn ) = <NUM_LIT> ; }

sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes ;


<s> return ( __m128i ) __builtin_ia32_pmovsqb128_mask ( ( __v2di ) __A , ( __v16qi ) _mm_setzero_si128 ( ) , __M ) ;


<s> loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; switch ( RC -> getSize ( ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . needsStackRealignment ( MF ) ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Align >= <NUM_LIT> && getRegisterInfo ( ) . canRealignStack ( MF ) ) {


<s> llvm_unreachable ( <STR_LIT> ) ; break ; } case <STR_LIT> : emitPseudoInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitDataProcessingInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitMiscLoadStoreInstruction ( MI ) ; break ; case <STR_LIT> : emitLoadStoreMultipleInstruction ( MI ) ; break ; case <STR_LIT> : emitMulFrmInstruction ( MI ) ; break ; case <STR_LIT> : emitExtendInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscArithInstruction ( MI ) ; break ; case <STR_LIT> : emitBranchInstruction ( MI ) ; break ; case <STR_LIT> : emitMiscBranchInstruction ( MI ) ; break ; case <STR_LIT> : case <STR_LIT> : emitVFPArithInstruction ( MI ) ; break ;


<s> else return cached_can_issue_more ; if ( ( load_store_pendulum == <NUM_LIT> ) || ( * pn_ready <= <NUM_LIT> ) ) return cached_can_issue_more ; if ( load_store_pendulum == <NUM_LIT> ) { pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) ) { tmp = ready [ pos ] ; for ( i = pos ; i < * pn_ready - <NUM_LIT> ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ * pn_ready - <NUM_LIT> ] = tmp ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( tmp ) ) INSN_PRIORITY ( tmp ) ++ ; break ; } pos -- ; } } else if ( load_store_pendulum == - <NUM_LIT> ) { pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) && ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ pos ] ) ) { INSN_PRIORITY ( ready [ pos ] ) ++ ; load_store_pendulum -- ; break ; } pos -- ; } } else if ( load_store_pendulum == - <NUM_LIT> ) { int first_store_pos = - <NUM_LIT> ; pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_store_insn ( ready [ pos ] , & str_mem ) ) { rtx str_mem2 ; if ( first_store_pos == - <NUM_LIT> ) first_store_pos = pos ; if ( is_store_insn ( last_scheduled_insn , & str_mem2 ) && adjacent_mem_locations ( str_mem , str_mem2 ) ) { tmp = ready [ pos ] ; for ( i = pos ; i < * pn_ready - <NUM_LIT> ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ * pn_ready - <NUM_LIT> ] = tmp ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( tmp ) ) INSN_PRIORITY ( tmp ) ++ ; first_store_pos = - <NUM_LIT> ;


<s> return static_cast < MCELFStreamer & > ( Streamer ) ;


<s> explicit <ISA_LIT>MCExpr ( VariantKind Kind , const MCExpr * Expr ) : Kind ( Kind ) , Expr ( Expr ) {


<s> static DecodeStatus Decode2RInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned Op1 , Op2 ; DecodeStatus S = Decode2OpInstruction ( Insn , Op1 , Op2 ) ; if ( S == MCDisassembler :: Success ) { DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op2 , Address , Decoder ) ;


<s> unsigned int arm_dbx_register_number ( unsigned int regno ) { if ( regno < <NUM_LIT> ) return regno ; if ( IS_FPA_REGNUM ( regno ) ) return ( TARGET_AAPCS_BASED ? <NUM_LIT> : <NUM_LIT> ) + regno - FIRST_FPA_REGNUM ;

if ( IS_VFP_REGNUM ( regno ) ) return <NUM_LIT> + regno - FIRST_VFP_REGNUM ;


<s> BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitLo ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , FlatScrInitHi ) . addReg ( FlatScrInitHi ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FlatScrInitLo ) . addImm ( int16_t ( <STR_LIT> :: ID_FLAT_SCR_LO | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ) ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( FlatScrInitHi ) . addImm ( int16_t ( <STR_LIT> :: ID_FLAT_SCR_HI | ( <NUM_LIT> << <STR_LIT> :: WIDTH_M1_SHIFT_ ) ) ) ; return ; }

BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FlatScrInitLo ) . addReg ( ScratchWaveOffsetReg ) ;


<s> tmp = gen_frame_mem ( V4SImode , plus_constant ( Pmode , virtual_incoming_args_rtx , offset ) ) ; emit_move_insn ( tmp , gen_rtx_REG ( V4SImode , FIRST_ARG_REGNUM + regno ) ) ; offset += <NUM_LIT> ; } * pretend_size = offset + STACK_POINTER_OFFSET ;


<s> return isLegalAddImmediate ( Immed ) ;


<s> if ( ResolveKnownElts ) resolveTargetShuffleAndZeroables ( Mask , KnownUndef , KnownZero ) ; return true ; } if ( getFauxShuffleMask ( Op , DemandedElts , Mask , Inputs , DAG , Depth , ResolveKnownElts ) ) { KnownUndef = KnownZero = APInt :: getNullValue ( Mask . size ( ) ) ; for ( int i = <NUM_LIT> , e = Mask . size ( ) ; i != e ; ++ i ) { int M = Mask [ i ] ;

if ( SM_SentinelUndef == M ) KnownUndef . setBit ( i ) ;


<s> inline unsigned getThumbImmValShift ( unsigned Imm ) {

if ( ( Imm & ~ <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ;


<s> if ( IsDouble || ! ST -> useNEONForSinglePrecisionFP ( ) ) { return Op ; } SDLoc DL ( Op ) ; SDValue NewVal = DAG . getTargetConstant ( ImmVal , DL , <STR_LIT> ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewVal ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } if ( ! ST -> hasNEON ( ) || ( ! IsDouble && ! ST -> useNEONForSinglePrecisionFP ( ) ) ) return SDValue ( ) ; EVT VMovVT ; uint64_t iVal = FPVal . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( IsDouble && ( iVal & <NUM_LIT> ) != ( iVal >> <NUM_LIT> ) ) return SDValue ( ) ; SDValue NewVal = isNEONModifiedImm ( iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMOVModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ; if ( IsDouble ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; SDValue VecFConstant = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecConstant ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VecFConstant , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } NewVal = isNEONModifiedImm ( ~ iVal & <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , DAG , SDLoc ( Op ) , VMovVT , false , VMVNModImm ) ; if ( NewVal != SDValue ( ) ) { SDLoc DL ( Op ) ; SDValue VecConstant = DAG . getNode ( <STR_LIT> , DL , VMovVT , NewVal ) ;


<s> void <ISA_LIT>AsmParser :: emitLoadStoreSymbol ( MCInst & Inst , unsigned Opcode , SMLoc IDLoc , MCStreamer & Out , bool HasTmpReg ) {

MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ;


<s> ix86_compute_frame_layout ( & frame ) ;

return ( frame . stack_pointer_offset == UNITS_PER_WORD && ( frame . nregs + frame . nsseregs ) == <NUM_LIT> ) ;


<s> int Opcode = isU6 ? <STR_LIT> : <STR_LIT> ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opcode ) ) . addImm ( Amount ) ; } else { assert ( Old -> getOpcode ( ) == <STR_LIT> ) ; int Opcode = isU6 ? <STR_LIT> : <STR_LIT> ; New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( Opcode ) , <STR_LIT> ) . addImm ( Amount ) ; }


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Vcc = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( Vcc ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addReg ( Reg ) ; Skip ( MI , MI . getOperand ( <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ;

RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ;


<s> unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; }


<s> if ( ! TARGET_HARD_FLOAT ) { COPY_HARD_REG_SET ( x , reg_class_contents [ ( int ) FP_REGS ] ) ;

for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) if ( TEST_HARD_REG_BIT ( x , i ) ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ;


<s> } else if ( Name . startswith_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = VSRegs [ IntVal ] ; } else if ( Name . startswith_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = VRegs [ IntVal ] ; } else if ( Name . startswith_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) { RegNo = CRRegs [ IntVal ] ; } else return true ; getParser ( ) . Lex ( ) ; return false ; }


<s> AU . addPreservedID ( MachineLoopInfoID ) ; AU . addPreservedID ( MachineDominatorsID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> __attribute__ ( ( __always_inline__ , __gnu_inline__ , __artificial__ ) ) vtst_p8 ( poly8x8_t a , poly8x8_t b ) { return ( uint8x8_t ) ( ( ( ( uint8x8_t ) a ) & ( ( uint8x8_t ) b ) ) != <NUM_LIT> ) ;


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return MF -> getTarget ( ) . getTargetAsmInfo ( ) -> getInlineAsmLength ( AsmStr ) ;


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( arg . end_marker_p ( ) || ! arg . named ) return NULL_RTX ;

return gen_rtx_UNSPEC ( arg . mode , gen_rtvec ( <NUM_LIT> , GEN_INT ( cum -> count ) ) , UNSPEC_ARG_REG ) ;


<s> return ( uint64x1_t ) { __builtin_aarch64_uqshldi_uus ( __a [ <NUM_LIT> ] , __b [ <NUM_LIT> ] ) } ;


<s> static void adjustBranch ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) { unsigned_width ( Size + <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ;

<STR_LIT> :: adjustBranchTarget ( Value ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , OutVT , Opnds ) ; } ; if ( VT . getSizeInBits ( ) < <NUM_LIT> && ! ( <NUM_LIT> % VT . getSizeInBits ( ) ) ) { unsigned Scale = <NUM_LIT> / VT . getSizeInBits ( ) ; EVT ExVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , <NUM_LIT> / SVT . getSizeInBits ( ) ) ; SDValue Ex = ExtendVecSize ( DL , N0 , Scale * InVT . getSizeInBits ( ) ) ; SDValue SExt = DAG . getNode ( Opcode , DL , ExVT , Ex ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SExt , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } if ( ! Subtarget . hasSSE41 ( ) || VT . is128BitVector ( ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) { SDValue ExOp = ExtendVecSize ( DL , N0 , VT . getSizeInBits ( ) ) ; return Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( ExOp , DL , VT ) : DAG . getZeroExtendVectorInReg ( ExOp , DL , VT ) ; } if ( ! Subtarget . hasInt256 ( ) && ! ( VT . getSizeInBits ( ) % <NUM_LIT> ) ) { unsigned NumVecs = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumSubElts = <NUM_LIT> / SVT . getSizeInBits ( ) ; EVT SubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumSubElts ) ; EVT InSubVT = EVT :: getVectorVT ( * DAG . getContext ( ) , InSVT , NumSubElts ) ; SmallVector < SDValue , <NUM_LIT> > Opnds ; for ( unsigned i = <NUM_LIT> , Offset = <NUM_LIT> ; i != NumVecs ; ++ i , Offset += NumSubElts ) { SDValue SrcVec = DAG . getNode ( <STR_LIT> , DL , InSubVT , N0 , DAG . getIntPtrConstant ( Offset , DL ) ) ; SrcVec = ExtendVecSize ( DL , SrcVec , <NUM_LIT> ) ;

SrcVec = Opcode == <STR_LIT> ? DAG . getSignExtendVectorInReg ( SrcVec , DL , SubVT ) : DAG . getZeroExtendVectorInReg ( SrcVec , DL , SubVT ) ;


<s> bool isShiftOrExtend ( ) const { return Kind == k_ShiftExtend ;


<s> bool AMDGPUDAGToDAGISel :: SelectMUBUFAddr32 ( SDValue Addr , SDValue & SRsrc , SDValue & VAddr , SDValue & SOffset , SDValue & Offset , SDValue & Offen , SDValue & Idxen , SDValue & GLC , SDValue & SLC , SDValue & TFE ) const { GLC = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; TFE = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; Idxen = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; Offen = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return SelectMUBUFScratch ( Addr , SRsrc , VAddr , SOffset , Offset ) ;


<s> assert ( Kind == k_SysReg && <STR_LIT> ) ;


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , Triple :: OSType _OSType ) : <ISA_LIT>AsmBackend ( T ) , OSType ( _OSType ) {


<s> switch ( Opc ) { case <STR_LIT> : { MCOperand adj_name = LowerOperand ( unloweredName , <NUM_LIT> ) ; if ( base . getReg ( ) == ( target . getReg ( ) ) ) { instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( atReg ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( adj_name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( atReg ) ; instr2 . addOperand ( base ) ; instr2 . addOperand ( name ) ; instr3 = move ; } else { two_instructions = true ; instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( target ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( adj_name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( target ) ; instr2 . addOperand ( base ) ; instr2 . addOperand ( name ) ; } break ; } case <STR_LIT> : { MCOperand adj_name = LowerOperand ( unloweredName , <NUM_LIT> ) ; instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( atReg ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( adj_name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( target ) ; instr2 . addOperand ( base ) ; instr2 . addOperand ( name ) ; instr3 . setOpcode ( <STR_LIT> ) ; instr3 . addOperand ( target ) ; instr3 . addOperand ( atReg ) ; instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; instr3 . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { assert ( base . getReg ( ) != target . getReg ( ) ) ; two_instructions = true ; MCOperand adj_name = LowerOperand ( unloweredName , <NUM_LIT> ) ; instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( target ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( adj_name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( target ) ; instr2 . addOperand ( base ) ; instr2 . addOperand ( name ) ; break ; } case <STR_LIT> : { MCOperand adj_name = LowerOperand ( unloweredName , <NUM_LIT> ) ; instr1 . setOpcode ( <STR_LIT> ) ; instr1 . addOperand ( target ) ; instr1 . addOperand ( base ) ; instr1 . addOperand ( name ) ; instr2 . setOpcode ( <STR_LIT> ) ; instr2 . addOperand ( atReg ) ;


<s> case <STR_LIT> : { assert ( Subtarget . hasSSE41 ( ) && <STR_LIT> ) ; if ( SDValue Masked = lowerShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; if ( Subtarget . hasBWI ( ) && Subtarget . hasVLX ( ) ) { MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( BlendMask , DL , IntegerType ) ; return getVectorMaskingNode ( V2 , MaskNode , V1 , Subtarget , DAG ) ; } if ( Subtarget . hasVLX ( ) ) if ( SDValue BitBlend = lowerShuffleAsBitBlend ( DL , VT , V1 , V2 , Mask , DAG ) ) return BitBlend ; int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; MVT BlendVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; if ( ! <STR_LIT> ( V1 . getNode ( ) ) && <STR_LIT> ( V2 . getNode ( ) ) ) { ShuffleVectorSDNode :: commuteMask ( Mask ) ; std :: swap ( V1 , V2 ) ; } SmallVector < SDValue , <NUM_LIT> > VSELECTMask ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) VSELECTMask . push_back ( Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] < Size ? - <NUM_LIT> : <NUM_LIT> , DL , <STR_LIT> ) ) ; V1 = DAG . getBitcast ( BlendVT , V1 ) ; V2 = DAG . getBitcast ( BlendVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getSelect ( DL , BlendVT , DAG . getBuildVector ( BlendVT , DL , VSELECTMask ) , V1 , V2 ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool OptForSize = DAG . shouldOptForSize ( ) ; if ( ! OptForSize ) { if ( SDValue Masked = lowerShuffleAsBitMask ( DL , VT , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Masked ; } MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ;


<s> LLVM_DEBUG ( errs ( ) << CSR_RegMask [ <NUM_LIT> ] << <STR_LIT> ) ;


<s> if ( isMicro<ISA_LIT> ( STI ) ) { if ( is<ISA_LIT>32r6 ( STI ) ) { NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; } else NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode == - <NUM_LIT> ) NewOpcode = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NewOpcode != - <NUM_LIT> ) { if ( Fixups . size ( ) > N ) Fixups . pop_back ( ) ; Opcode = NewOpcode ; TmpInst . setOpcode ( NewOpcode ) ;

Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;


<s> <ISA_LIT>elTargetMachine :: <ISA_LIT>elTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , JIT , true ) {


return getWavefrontSize ( ) == <NUM_LIT> ;


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize = <NUM_LIT> ;


<s> unsigned CmpXchgNbWidth = Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned OpWidth = MemType -> getPrimitiveSizeInBits ( ) ; if ( OpWidth == CmpXchgNbWidth ) return true ;


<s> unsigned ImmIdx = <NUM_LIT> ; int InstrOffs = <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : return false ; case <STR_LIT> : { ImmIdx = FrameRegIdx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI . getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } if ( NumBits > <NUM_LIT> ) { MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset = - ImmedOffset ; else ImmedOffset |= <NUM_LIT> << NumBits ; } ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset = <NUM_LIT> ; return true ; } ImmedOffset = ImmedOffset & Mask ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset = - ImmedOffset ;


<s> if ( ! REG_P ( x_op0 ) || ! REG_P ( y_op0 ) ) return false ; if ( GET_MODE ( x_op0 ) != GET_MODE ( y_op0 ) ) return false ; if ( REG_P ( x_op1 ) ) return REG_P ( y_op1 ) && GET_MODE ( x_op1 ) == GET_MODE ( y_op1 ) ; return rtx_equal_p ( x_op1 , y_op1 ) ;


<s> if ( Reloc == <STR_LIT> ) RelocCST = PICBaseOffset ; else if ( Reloc == <STR_LIT> ) RelocCST = PCAdj ; MCE . addRelocation ( MachineRelocation :: getConstPool ( MCE . getCurrentPCOffset ( ) , Reloc , CPI , RelocCST ) ) ; if ( Reloc == <STR_LIT> ) MCE . emitDWordLE ( Disp ) ;

else MCE . emitWordLE ( ( int32_t ) Disp ) ;


<s> MinInstAlignment = <NUM_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ;


<s> if ( operandsHaveModifiers ( Operands ) ) { cvtVOP3 ( Inst , Operands ) ; } else { cvtId ( Inst , Operands ) ;


<s> __inline extern double frexp ( double x , int * exp ) { double float_exponent ; int int_exponent ; double mantissa ; __asm ( <STR_LIT> : <STR_LIT> ( float_exponent ) : <STR_LIT> ( x ) ) ; int_exponent = ( int ) float_exponent ;

__asm ( <STR_LIT> : <STR_LIT> ( mantissa ) : <STR_LIT> ( x ) ) ;


<s> switch ( src_mode ) { case E_V16QImode : gen = gen_aarch64_split_simd_movv16qi ; break ; case E_V8HImode : gen = gen_aarch64_split_simd_movv8hi ; break ; case E_V4SImode : gen = gen_aarch64_split_simd_movv4si ; break ; case E_V2DImode : gen = gen_aarch64_split_simd_movv2di ; break ; case E_V8HFmode : gen = gen_aarch64_split_simd_movv8hf ; break ; case E_V4SFmode : gen = gen_aarch64_split_simd_movv4sf ; break ; case E_V2DFmode : gen = gen_aarch64_split_simd_movv2df ; break ;


<s> unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( Op ) ; updateValueMap ( I , ResultReg ) ; return true ;


<s> assert ( ! ( Subtarget . isFP64bit ( ) && ! Subtarget . useOddSPReg ( ) ) ) ; BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( LoReg ) ; if ( Subtarget . hasMTHC1 ( ) ) { BuildMI ( MBB , I , dl , get ( isMicro<ISA_LIT> ? ( FP64 ? <STR_LIT> : <STR_LIT> ) : ( FP64 ? <STR_LIT> : <STR_LIT> ) ) , DstReg ) . addReg ( DstReg ) . addReg ( HiReg ) ; } else if ( Subtarget . isABI_FPXX ( ) ) llvm_unreachable ( <STR_LIT> ) ; else BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( HiReg ) ;


<s> void setVTYPE ( <STR_LIT> L , unsigned S , bool TA , bool MA ) { assert ( isValid ( ) && ! isUnknown ( ) && <STR_LIT> ) ;


<s> const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; if ( TLOF -> IsConstantInSmallSection ( DAG . getDataLayout ( ) , N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return Subtarget . hasSym32 ( ) ? getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) : getAddrNonPICSym64 ( N , SDLoc ( N ) , Ty , DAG ) ; }

return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ;


<s> <ISA_LIT>PrepareModule ( ) : ModulePass ( ID ) {


<s> enum machine_mode mode ; tree type = TREE_TYPE ( field ) ; if ( TARGET_64BIT || TARGET_ALIGN_DOUBLE ) return computed ;

mode = TYPE_MODE ( TREE_CODE ( type ) == ARRAY_TYPE ? get_inner_array_type ( type ) : type ) ;


<s> case PROCESSOR_K8 : case PROCESSOR_AMDFAM10 : case PROCESSOR_GENERIC : case PROCESSOR_BTVER1 : return <NUM_LIT> ; case PROCESSOR_BDVER1 : case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : case PROCESSOR_ZNVER1 : case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : return <NUM_LIT> ; default : return <NUM_LIT> ; }


<s> case ADDRESS_GOTOFF : case ADDRESS_PLT : case ADDRESS_TLS : if ( info . regA ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( info . regA ) ] ) ; output_addr_const ( file , info . symbol ) ; if ( type == ADDRESS_GOTOFF ) { fputs ( <STR_LIT> , file ) ; } else if ( type == ADDRESS_PLT ) { fputs ( <STR_LIT> , file ) ; } else if ( type == ADDRESS_SYMBOLIC_TXT_REL ) { if ( info . offset != NULL && CONST_INT_P ( info . offset ) && INTVAL ( info . offset ) > <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , info . offset ) ; } fputs ( <STR_LIT> , file ) ; } else if ( type == ADDRESS_TLS ) { switch ( info . tls_type ) { case TLS_GD : fputs ( <STR_LIT> , file ) ;


return getMemOpBaseRegImmOfsWidth ( LdSt , BaseReg , Offset , Width , TRI ) ;


<s> for ( unsigned i = <NUM_LIT> , n = PN -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) { unsigned PredR = PN -> getOperand ( i ) . getReg ( ) ; MachineBasicBlock * PredB = PN -> getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; if ( PredB == Latch ) continue ; NewPN -> addOperand ( MachineOperand :: CreateReg ( PredR , false ) ) ; NewPN -> addOperand ( MachineOperand :: CreateMBB ( PredB ) ) ; } for ( int i = PN -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; i -= <NUM_LIT> ) { MachineBasicBlock * PredB = PN -> getOperand ( i + <NUM_LIT> ) . getMBB ( ) ; if ( PredB != Latch ) { PN -> RemoveOperand ( i + <NUM_LIT> ) ; PN -> RemoveOperand ( i ) ; } } PN -> addOperand ( MachineOperand :: CreateReg ( NewPR , false ) ) ; PN -> addOperand ( MachineOperand :: CreateMBB ( NewPH ) ) ; } } else { assert ( Header -> pred_size ( ) == <NUM_LIT> ) ; for ( instr_iterator I = Header -> instr_begin ( ) , E = Header -> instr_end ( ) ; I != E && I -> isPHI ( ) ; ++ I ) { MachineInstr * PN = & * I ; for ( unsigned i = <NUM_LIT> , n = PN -> getNumOperands ( ) ; i < n ; i += <NUM_LIT> ) {

MachineOperand & MO = PN -> getOperand ( i + <NUM_LIT> ) ;


<s> switch ( SC ) { case <STR_LIT> :: Workgroup : case <STR_LIT> :: CrossWorkgroup : case <STR_LIT> :: Function : return true ; default :


<s> MachineInstrBuilder CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; if ( Callee . isReg ( ) ) return false ; MachineInstrBuilder MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; MIB . add ( Callee ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; TargetLowering :: ArgListTy FuncOrigArgs ; FuncOrigArgs . reserve ( OrigArgs . size ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; unsigned i = <NUM_LIT> ; for ( auto & Arg : OrigArgs ) { TargetLowering :: ArgListEntry Entry ; Entry . Ty = Arg . Ty ; FuncOrigArgs . push_back ( Entry ) ; splitToValueTypes ( Arg , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Outs . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; const char * Call = Callee . isSymbol ( ) ? Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! RetHandler . handle ( ArgLocs , ArgInfos ) ) { return false ; } CallSeqStart . addImm ( ABI . GetCalleeAllocdArgSizeInBytes ( CallConv ) ) . addImm ( <NUM_LIT> ) ; MIRBuilder . insertInstr ( MIB ) ; if ( OrigRet . Reg ) { ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > OrigRetIndices ; splitToValueTypes ( OrigRet , <NUM_LIT> , ArgInfos , OrigRetIndices ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Ins ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigRetIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Ins . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ;


<s> bool <ISA_LIT>RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ;

if ( CantUseSP ( MFI ) ) return MRI -> canReserveReg ( BasePtr ) ;


<s> MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else if ( Rs != <NUM_LIT> && Rs < Rt ) { MI . setOpcode ( <STR_LIT> ) ; HasRs = true ; } else MI . setOpcode ( <STR_LIT> ) ;

if ( HasRs ) MI . addOperand ( MCOperand :: CreateReg ( getReg ( Decoder , <STR_LIT> , Rs ) ) ) ;


<s> bool <ISA_LIT>TTIImpl :: useReductionIntrinsic ( unsigned Opcode , Type * Ty , TTI :: ReductionFlags Flags ) const { return ST -> hasMVEIntegerOps ( ) ;


<s> } if ( Addr . isFIBase ( ) ) { unsigned FI = Addr . getFI ( ) ; int64_t Offset = Addr . getOffset ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ( <NUM_LIT> ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ; return true ;


<s> if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; default : break ; }


<s> void <ISA_LIT>LowerKernelArgs :: handlePointerParam ( Argument * Arg ) { assert ( ! Arg -> hasByValAttr ( ) && <STR_LIT> ) ;

Instruction * FirstInst = Arg -> getParent ( ) -> getEntryBlock ( ) . begin ( ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , const TargetOptions & Options ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ProcFamily ( Others ) , stackAlignment ( <NUM_LIT> ) , CPUString ( CPU ) , TargetTriple ( TT ) , Options ( Options ) , TargetABI ( <ISA_LIT>_ABI_APCS ) { initializeEnvironment ( ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getCSRFirstUseCost ( const MachineFunction & MF ) const {

if ( MF . getFunction ( ) . doesNotRecurse ( ) ) {


<s> return IN_RANGE ( mask_low_and_shift_len ( mode , mask , shift ) , <NUM_LIT> , maxlen ) ;


<s> ELF<ISA_LIT>_IAMCUAsmBackend ( const Target & T , uint8_t OSABI , const MCSubtargetInfo & STI ) : ELF<ISA_LIT>AsmBackend ( T , OSABI , STI ) {


<s> } for ( <ISA_LIT>EvexToVexCompressTableEntry Entry : <ISA_LIT>EvexToVex256CompressTable ) { AddTableEntry ( EvexToVex256Table , Entry . EvexOpcode , Entry . VexOpcode ) ; }


<s> Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( CLI . MPI , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; Chain = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) , <STR_LIT> , MMO ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getConstant ( NumBytes , getPointerTy ( ) , true ) , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) , true ) , InFlag , dl ) ;


<s> bool <ISA_LIT>FrameLowering :: expandStoreVec2 ( MachineBasicBlock & B , MachineBasicBlock :: iterator It , MachineRegisterInfo & MRI , const <ISA_LIT>InstrInfo & HII , SmallVectorImpl < unsigned > & NewRegs ) const { MachineFunction & MF = * B . getParent ( ) ; auto & MFI = MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MachineInstr * MI = & * It ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; LivePhysRegs LPR ( HRI ) ; LPR . addLiveIns ( B ) ; SmallVector < std :: pair < MCPhysReg , const MachineOperand * > , <NUM_LIT> > Clobbers ; for ( auto R = B . begin ( ) ; R != It ; ++ R ) { Clobbers . clear ( ) ; LPR . stepForward ( * R , Clobbers ) ; } DebugLoc DL = MI -> getDebugLoc ( ) ; Register SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcLo = HRI . getSubReg ( SrcR , <STR_LIT> ) ; Register SrcHi = HRI . getSubReg ( SrcR , <STR_LIT> ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool NeedsAligna = needsAligna ( MF ) ; unsigned Size = HRI . getSpillSize ( <STR_LIT> ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned StoreOpc ; auto UseAligned = [ & ] ( unsigned NeedAlign , unsigned HasAlign ) { return ! NeedsAligna && ( NeedAlign <= HasAlign ) ; } ; if ( LPR . contains ( SrcLo ) ) { StoreOpc = UseAligned ( NeedAlign , HasAlign ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( StoreOpc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcLo , getKillRegState ( IsKill ) ) . cloneMemRefs ( * MI ) ; } if ( LPR . contains ( SrcHi ) ) {


<s> if ( Size >= <NUM_LIT> && Subtarget . hasAVX ( ) && ( Subtarget . getPreferVectorWidth ( ) >= <NUM_LIT> ) ) { return <STR_LIT> ; } if ( Subtarget . hasSSE2 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= <NUM_LIT> ) ) return <STR_LIT> ; if ( Subtarget . hasSSE1 ( ) && ( Subtarget . is64Bit ( ) || Subtarget . hasX87 ( ) ) && ( Subtarget . getPreferVectorWidth ( ) >= <NUM_LIT> ) ) return <STR_LIT> ; } else if ( ( ! IsMemset || ZeroMemset ) && ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return <STR_LIT> ; } }

if ( Subtarget . is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ;


<s> for ( auto I = MBB . rbegin ( ) ; I != MBB . rend ( ) ; ++ I ) { MachineInstr * NewMI = nullptr ; MachineInstr * MI = & * I ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : if ( MachineLoop * ML = MLI -> getLoopFor ( & MBB ) ) { if ( ML -> begin ( ) == ML -> end ( ) && ! OptForSize ) NewMI = tryReplaceLoad ( <STR_LIT> , MI ) ; } break ; case <STR_LIT> : NewMI = tryReplaceLoad ( <STR_LIT> , MI ) ; break ; case <STR_LIT> : case <STR_LIT> :


<s> if ( regs_ever_live [ <NUM_LIT> ] || frame_pointer_needed ) { save_regs [ <NUM_LIT> ] = <NUM_LIT> ; sp_size += REG_PARM_STACK_SPACE ( <NUM_LIT> ) ; } if ( flag_pic && current_function_uses_pic_offset_table ) { save_regs [ PIC_OFFSET_TABLE_REGNUM ] = <NUM_LIT> ; nregs ++ ; } if ( frame_pointer_needed ) save_regs [ FRAME_POINTER_REGNUM ] = save_regs [ <NUM_LIT> ] = <NUM_LIT> ; else if ( regs_ever_live [ FRAME_POINTER_REGNUM ] ) save_regs [ FRAME_POINTER_REGNUM ] = <NUM_LIT> ; for ( regno = FIRST_EXTENDED_REGISTER + <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) { save_regs [ regno ] = <NUM_LIT> ; nxregs ++ ; } for ( regno = <NUM_LIT> ; regno < FRAME_POINTER_REGNUM ; regno ++ ) if ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) { save_regs [ regno ] = <NUM_LIT> ; nregs ++ ; } if ( nregs >= <NUM_LIT> && save_regs [ <NUM_LIT> ] && ! save_regs [ FRAME_POINTER_REGNUM ] ) sp_size += <NUM_LIT> ; nregs += save_regs [ <NUM_LIT> ] + save_regs [ FRAME_POINTER_REGNUM ] ; if ( nxregs > <NUM_LIT> && ( nregs & <NUM_LIT> ) != <NUM_LIT> ) sp_size += <NUM_LIT> ; sp_size += <NUM_LIT> * nregs ; sp_size += <NUM_LIT> * nxregs ;


<s> MCSubtargetInfo & STI = copySTI ( ) ; std :: vector < std :: string > ArchFeatures ( <ISA_LIT>Features . begin ( ) , <ISA_LIT>Features . end ( ) ) ; STI . setDefaultFeatures ( <STR_LIT> , <STR_LIT> , join ( ArchFeatures . begin ( ) , ArchFeatures . end ( ) , <STR_LIT> ) ) ; SmallVector < StringRef , <NUM_LIT> > RequestedExtensions ; if ( ! ExtensionString . empty ( ) ) ExtensionString . split ( RequestedExtensions , '+' ) ; ExpandCryptoAEK ( ID , RequestedExtensions ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( auto Name : RequestedExtensions ) { bool EnableFeature = true ; if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } for ( const auto & Extension : ExtensionMap ) { if ( Extension . Name != Name ) continue ; if ( Extension . Features . none ( ) ) report_fatal_error ( <STR_LIT> + Name ) ; FeatureBitset ToggleFeatures = EnableFeature ? ( ~ Features & Extension . Features ) : ( Features & Extension . Features ) ; FeatureBitset Features = ComputeAvailableFeatures ( STI . ToggleFeature ( ToggleFeatures ) ) ; setAvailableFeatures ( Features ) ; break ; }


<s> short <ISA_LIT>InstrInfo :: getNonExtOpcode ( const MachineInstr & MI ) const { short NonExtOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NonExtOpcode >= <NUM_LIT> ) return NonExtOpcode ; if ( MI . getDesc ( ) . mayLoad ( ) || MI . getDesc ( ) . mayStore ( ) ) { switch ( getAddrMode ( MI ) ) { case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; default : return - <NUM_LIT> ; } } return - <NUM_LIT> ;


<s> XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; } reg = gen_rtx_REG ( SImode , FP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; reg = gen_rtx_REG ( SImode , GP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; reg = gen_rtx_REG ( SImode , LP_REGNUM ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; pop_rtx = gen_rtx_SET ( reg , mem ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = pop_rtx ; RTX_FRAME_RELATED_P ( pop_rtx ) = <NUM_LIT> ; offset = offset + <NUM_LIT> ; par_index ++ ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; adjust_sp_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , offset + imm8u ) ) ; XVECEXP ( parallel_insn , <NUM_LIT> , par_index ) = adjust_sp_rtx ; if ( frame_pointer_needed ) { rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , const0_rtx ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ;


<s> if ( ! BI || ! BI -> isConditional ( ) ) return false ; Cond = dyn_cast < ICmpInst > ( BI -> getCondition ( ) ) ; if ( ! Cond ) return false ; Value * B1Op0 = Cond -> getOperand ( <NUM_LIT> ) ; auto Cond1Op = Cond -> getPredicate ( ) ; if ( B1Op0 != B2Op0 ) return false ; if ( Cond1Op == ICmpInst :: ICMP_SGT || Cond1Op == ICmpInst :: ICMP_SGE ) { if ( Cond2Op != ICmpInst :: ICMP_SLT && Cond1Op != ICmpInst :: ICMP_SLE ) return false ; } else if ( Cond1Op == ICmpInst :: ICMP_SLT || Cond1Op == ICmpInst :: ICMP_SLE ) { if ( Cond2Op != ICmpInst :: ICMP_SGT && Cond1Op != ICmpInst :: ICMP_SGE ) return false ; } else { return false ;


<s> MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { assert ( MemVT == <STR_LIT> ) ; assert ( StoreNode -> getAlignment ( ) >= <NUM_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , BitShift ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , BitShift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getBuildVector ( <STR_LIT> , DL , Src ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && VT . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DWordAddr ) ; if ( StoreNode -> isIndexed ( ) ) { llvm_unreachable ( <STR_LIT> ) ; } else { Chain = DAG . getStore ( Chain , DL , Value , Ptr , StoreNode -> getMemOperand ( ) ) ; } return Chain ; } }

if ( AS != <ISA_LIT>AS :: PRIVATE_ADDRESS ) return SDValue ( ) ;


<s> void eliminateFrameIndex ( MachineBasicBlock :: iterator MI , int SPAdj , unsigned FIOperandNum , RegScavenger * RS = nullptr ) const override {


<s> const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst -> setDesc ( NewDesc ) ; for ( unsigned i = Inst -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == AMDGPU :: SCC ) Inst -> RemoveOperand ( i ) ; } if ( Opcode == AMDGPU :: S_SEXT_I32_I8 || Opcode == AMDGPU :: S_SEXT_I32_I16 ) { unsigned Size = ( Opcode == AMDGPU :: S_SEXT_I32_I8 ) ? <NUM_LIT> : <NUM_LIT> ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Size ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } addDescImplicitUseDef ( NewDesc , Inst ) ; if ( Opcode == AMDGPU :: S_BFE_I32 || Opcode == AMDGPU :: S_BFE_U32 ) { const MachineOperand & OffsetWidthOp = Inst -> getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst -> RemoveOperand ( <NUM_LIT> ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } const TargetRegisterClass * NewDstRC = getOpRegClass ( * Inst , <NUM_LIT> ) ; switch ( Opcode ) { case AMDGPU :: COPY : case AMDGPU :: PHI :


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> else cond = <STR_LIT> ; break ; case GE : if ( cc_mode == CCNZmode ) cond = <STR_LIT> ; else cond = <STR_LIT> ; break ; case GT : cond = <STR_LIT> ; break ; case LE : if ( cc_mode == CCFPmode || cc_mode == CCFPEmode ) cond = <STR_LIT> ; else cond = <STR_LIT> ; break ; case LT : if ( cc_mode == CCFPmode || cc_mode == CCFPEmode ) cond = <STR_LIT> ; else if ( cc_mode == CCNZmode ) cond = <STR_LIT> ; else cond = <STR_LIT> ; break ; case GEU : cond = <STR_LIT> ; break ; case GTU : cond = <STR_LIT> ; break ; case LEU : cond = <STR_LIT> ; break ; case LTU : cond = <STR_LIT> ; break ; case UNORDERED : cond = <STR_LIT> ; break ; case ORDERED : cond = <STR_LIT> ; break ; case UNGE : cond = <STR_LIT> ; break ; case UNGT : cond = <STR_LIT> ; break ; case UNLE : cond = <STR_LIT> ; break ; case UNLT : cond = <STR_LIT> ; break ;


<s> BlockOrderList & getOrderedList ( ) { return blockList ;


<s> SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue UDIVREM = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , VT ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( UDIVREM . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { SDValue Op = SDValue ( N , <NUM_LIT> ) ; SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; EVT HalfVT = VT . getHalfSizedIntegerVT ( * DAG . getContext ( ) ) ; SDValue one = DAG . getConstant ( <NUM_LIT> , HalfVT ) ; SDValue zero = DAG . getConstant ( <NUM_LIT> , HalfVT ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue LHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS , zero ) ; SDValue LHS_Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS , one ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , RHS , zero ) ; SDValue RHS_Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , RHS , one ) ; SDValue DIV_Part = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS_Hi , RHS_Lo ) ; SDValue REM_Part = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS_Hi , RHS_Lo ) ; SDValue REM_Hi = zero ; SDValue REM_Lo = DAG . getSelectCC ( DL , RHS_Hi , zero , REM_Part , LHS_Hi , <STR_LIT> ) ; SDValue DIV_Hi = DAG . getSelectCC ( DL , RHS_Hi , zero , DIV_Part , zero , <STR_LIT> ) ; SDValue DIV_Lo = zero ; const unsigned halfBitWidth = HalfVT . getSizeInBits ( ) ; for ( unsigned i = <NUM_LIT> ; i < halfBitWidth ; ++ i ) { SDValue POS = DAG . getConstant ( halfBitWidth - i - <NUM_LIT> , HalfVT ) ; SDValue HBit ; if ( halfBitWidth == <NUM_LIT> && Subtarget -> hasBFE ( ) ) { HBit = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS_Lo , POS , one ) ; } else { HBit = DAG . getNode ( <STR_LIT> , DL , HalfVT , LHS_Lo , POS ) ; HBit = DAG . getNode ( <STR_LIT> , DL , HalfVT , HBit , one ) ; } SDValue Carry = DAG . getNode ( <STR_LIT> , DL , HalfVT , REM_Lo , DAG . getConstant ( halfBitWidth - <NUM_LIT> , HalfVT ) ) ; REM_Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , REM_Hi , one ) ; REM_Hi = DAG . getNode ( <STR_LIT> , DL , HalfVT , REM_Hi , Carry ) ; REM_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , REM_Lo , one ) ;

REM_Lo = DAG . getNode ( <STR_LIT> , DL , HalfVT , REM_Lo , HBit ) ;


<s> else emit_insn ( gen_addhi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( fsize ) ) ) ; } if ( pdp11_saved_regno ( AC4_REGNUM ) || pdp11_saved_regno ( AC5_REGNUM ) ) { for ( regno = AC0_REGNUM ; regno <= AC3_REGNUM ; regno ++ ) if ( pdp11_saved_regno ( regno ) ) { via_ac = gen_rtx_REG ( DFmode , regno ) ; break ; } } for ( regno = AC5_REGNUM ; regno >= AC0_REGNUM ; regno -- ) if ( pdp11_saved_regno ( regno ) ) { x = gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ; x = gen_frame_mem ( DFmode , x ) ; reg = gen_rtx_REG ( DFmode , regno ) ; if ( LOAD_FPU_REG_P ( regno ) ) emit_move_insn ( reg , x ) ;


<s> unsigned disp15 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned n_0 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned n_1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned n = ( n_0 << <NUM_LIT> ) | ( n_1 << <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeDataRegsRegisterClass ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; Inst . addOperand ( MCOperand :: createImm ( n ) ) ;

Inst . addOperand ( MCOperand :: createImm ( disp15 ) ) ;


<s> for ( unsigned i = <NUM_LIT> , n = Vector . size ( ) ; i < n ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) ) Vector [ i ] = BT :: RegisterRef ( MO ) ; }


<s> if ( generateSignBits ( V ) ) return false ; auto * I = cast < Instruction > ( V ) ; if ( I -> hasOneUse ( ) && isSink ( * I -> use_begin ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; return true ; }

if ( isa < OverflowingBinaryOperator > ( I ) ) return false ;


<s> if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { if ( Ty -> isSized ( ) ) { unsigned A = DL . getABITypeAlignment ( Ty ) ; if ( ( AM . BaseOffs % A ) != <NUM_LIT> ) return false ; if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs >> Log2_32 ( A ) ) ) return false ; } if ( AM . BaseGV ) return false ; int Scale = AM . Scale ; if ( Scale < <NUM_LIT> ) Scale = - Scale ; switch ( Scale ) { case <NUM_LIT> : break ; default :


<s> if ( mode != SImode ) { if ( register_operand ( dst , mode ) ) { emit_move_insn ( simplify_gen_subreg ( SImode , dst , mode , <NUM_LIT> ) , src ) ; return <NUM_LIT> ; } else { src = force_reg ( SImode , src ) ; src = gen_lowpart_SUBREG ( mode , src ) ; operands [ <NUM_LIT> ] = src ; } } } if ( ! ( reload_in_progress | reload_completed ) && ! xtensa_valid_move ( mode , operands ) ) operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = xtensa_copy_incoming_a7 ( operands [ <NUM_LIT> ] ) ; if ( reload_in_progress ) { operands [ <NUM_LIT> ] = fixup_subreg_mem ( operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = fixup_subreg_mem ( operands [ <NUM_LIT> ] ) ;


<s> assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( Op ) ; SDValue WideVec = WidenVector ( Op . getOperand ( <NUM_LIT> ) , DAG ) ;

EVT WideTy = WideVec . getValueType ( ) ;


<s> if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return nullptr ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return nullptr ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . parseAbsoluteExpression ( ScaleVal ) ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return nullptr ; } Scale = ( unsigned ) ScaleVal ; } } } else if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t Value ; if ( getParser ( ) . parseAbsoluteExpression ( Value ) ) return nullptr ; if ( Value != <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; Scale = <NUM_LIT> ; } } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ;


<s> SysAlias ( const char * N , uint16_t E , FeatureBitset F ) :

Name ( N ) , Encoding ( E ) , FeaturesRequired ( F ) { }


<s> return make_unique < <ISA_LIT>Operand > ( RegNum , Val , S , E ) ;


<s> MemRefBegin += <STR_LIT> ( Desc ) ; const MachineOperand * BaseOp = & MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! BaseOp -> isReg ( ) ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; if ( MemOp . getOperand ( MemRefBegin + <STR_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; const MachineOperand & DispMO = MemOp . getOperand ( MemRefBegin + <STR_LIT> ) ; if ( ! DispMO . isImm ( ) ) return false ; Offset = DispMO . getImm ( ) ; if ( ! BaseOp -> isReg ( ) ) return false ; OffsetIsScalable = false ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( StackGrowsDown , sti . getStackAlignment ( ) , <NUM_LIT> , Align ( <NUM_LIT> ) ) , STI ( sti ) {


<s> bool mips_mem_fits_mode_p ( machine_mode mode , rtx x ) {

return ( MEM_P ( x ) && MEM_SIZE_KNOWN_P ( x ) && MEM_SIZE ( x ) == GET_MODE_SIZE ( mode ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const {


<s> } uint64_t CurVal = <NUM_LIT> ; bool micro<ISA_LIT>LEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == <STR_LIT> ? ( micro<ISA_LIT>LEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = Endian == <STR_LIT> ? ( micro<ISA_LIT>LEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - <NUM_LIT> - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false , false ) ;


<s> MachineInstr * RLL = getDef ( SrcReg , MRI ) ; if ( RLL && RLL -> getOpcode ( ) == <STR_LIT> ) { LGFR = RLL ; RLL = getDef ( LGFR -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; } if ( ! RLL || ! isShift ( RLL , <STR_LIT> , <NUM_LIT> ) ) return false ; MachineInstr * SRL = getDef ( RLL -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! SRL || ! isShift ( SRL , <STR_LIT> , <STR_LIT> ) ) return false ; MachineInstr * IPM = getDef ( SRL -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( ! IPM || IPM -> getOpcode ( ) != <STR_LIT> ) return false ; if ( IPM -> getParent ( ) != Compare -> getParent ( ) ) return false ; MachineBasicBlock :: iterator MBBI = IPM , MBBE = Compare ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) { MachineInstr * MI = MBBI ;

if ( MI -> modifiesRegister ( <STR_LIT> , TRI ) ) return false ;


<s> return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , VT , GA -> getOffset ( ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! useAM3 ) { needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; if ( needsLowering && isThumb2 ) needsLowering = ! ( Subtarget -> hasV6T2Ops ( ) && Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> ) ; } else { needsLowering = ( Addr . Offset > <NUM_LIT> || Addr . Offset < - <NUM_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : needsLowering = ( ( Addr . Offset & <NUM_LIT> ) != Addr . Offset ) ; break ; } if ( needsLowering && Addr . BaseType == Address :: FrameIndexBase ) { TargetRegisterClass * RC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , * FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ;


<s> unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode ( I -> getOpcode ( ) ) : getPostIndexedOpcode ( I -> getOpcode ( ) ) ; MachineInstrBuilder MIB ; if ( ! isPairedLdSt ( * I ) ) { MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } else { int Scale = getMemScale ( * I ) ; MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . add ( getLdStRegOp ( * Update ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStRegOp ( * I , <NUM_LIT> ) ) . add ( getLdStBaseOp ( * I ) ) . addImm ( Value / Scale ) . setMemRefs ( I -> memoperands_begin ( ) , I -> memoperands_end ( ) ) ; } ( void ) MIB ; if ( IsPreIdx ) { ++ NumPreFolded ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { ++ NumPostFolded ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>64Target ( ) ) ;


<s> Opcode = <STR_LIT> ; } else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> auto NumBits = Info . TargetSize + Info . TargetOffset ; auto NumBytes = ( NumBits / <NUM_LIT> ) + ( ( NumBits % <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ;

assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ;


<s> static void sh_output_function_epilogue ( FILE * ) {


<s> TargetRegistry :: RegisterMachOStreamer ( * T , createMachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; } for ( Target * T : { & getThe<ISA_LIT>leTarget ( ) , & getTheARM64Target ( ) } ) TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>leAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>beTarget ( ) , create<ISA_LIT>beAsmBackend ) ;


<s> assert ( MIb . mayLoadOrStore ( ) && <STR_LIT> ) ; if ( MIa . hasUnmodeledSideEffects ( ) || MIb . hasUnmodeledSideEffects ( ) || MIa . hasOrderedMemoryRef ( ) || MIb . hasOrderedMemoryRef ( ) ) return false ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ;

const MachineOperand * BaseOpA = nullptr , * BaseOpB = nullptr ;


<s> void adds6_0ExtOperands ( MCInst & Inst , unsigned N ) const { addSignedImmOperands ( Inst , N ) ;


<s> SMLoc getStartLoc ( ) const { return Start ;


<s> return ; case MachineOperand :: MO_Immediate : if ( ! Modifier || strcmp ( Modifier , <STR_LIT> ) ) O << '#' ; O << MO . getImm ( ) ; return ; case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isMemOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; uint64_t Offset = MO . getOffset ( ) ; if ( ! Modifier || strcmp ( Modifier , <STR_LIT> ) ) O << ( isMemOp ? '&' : '#' ) ; if ( Offset ) O << '(' << Offset << '+' ; getSymbol ( MO . getGlobal ( ) ) -> print ( O , MAI ) ;


<s> <STR_LIT> Ext = Ld -> getExtensionType ( ) ; bool Fast ; unsigned Alignment = Ld -> getAlignment ( ) ; if ( RegVT . is256BitVector ( ) && ! DCI . isBeforeLegalizeOps ( ) && Ext == <STR_LIT> && ( ( Ld -> isNonTemporal ( ) && ! Subtarget . hasInt256 ( ) && Alignment >= <NUM_LIT> ) || ( TLI . allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , RegVT , * Ld -> getMemOperand ( ) , & Fast ) && ! Fast ) ) ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue ( ) ; SDValue Ptr = Ld -> getBasePtr ( ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Alignment , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; Ptr = DAG . getMemBasePlusOffset ( Ptr , <NUM_LIT> , dl ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , MinAlign ( Alignment , <NUM_LIT> ) , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getNode ( <STR_LIT> , dl , RegVT , Load1 , Load2 ) ; return DCI . CombineTo ( N , NewVec , TF , true ) ; } if ( Ext == <STR_LIT> && ! Subtarget . hasAVX512 ( ) && RegVT . isVector ( ) && RegVT . getScalarType ( ) == <STR_LIT> && DCI . isBeforeLegalize ( ) ) { unsigned NumElts = RegVT . getVectorNumElements ( ) ; EVT IntVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumElts ) ; if ( TLI . isTypeLegal ( IntVT ) ) { SDValue IntLoad = DAG . getLoad ( IntVT , dl , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getPointerInfo ( ) , Alignment , Ld -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue BoolVec = DAG . getBitcast ( RegVT , IntLoad ) ; return DCI . CombineTo ( N , BoolVec , IntLoad . getValue ( <NUM_LIT> ) , true ) ;


<s> else if ( CM != CodeModel :: Small && CM != CodeModel :: Large ) report_fatal_error ( <STR_LIT> ) ; if ( TheTriple . isOSDarwin ( ) ) RM = Reloc :: PIC_ ; else if ( RM == Reloc :: Default || RM == Reloc :: DynamicNoPIC ) RM = Reloc :: Static ; MCCodeGenInfo * X = new MCCodeGenInfo ( ) ;

X -> initMCCodeGenInfo ( RM , CM , OL ) ;


<s> if ( isGuaranteedValidSetBounds ( MI ) ) return true ; return false ;


<s> unsigned Opc = IsSub ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( AbsOffset ) ;

MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> case CortexA57 : MaxInterleaveFactor = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; break ; case CortexA65 : break ; case CortexA72 : case CortexA73 : case CortexA75 : case CortexA76 : PrefFunctionAlignment = <NUM_LIT> ; break ; case Cyclone : CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case ExynosM1 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case ExynosM3 : MaxInterleaveFactor = <NUM_LIT> ; MaxJumpTableSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ;


<s> case <STR_LIT> : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , <NUM_LIT> ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: SReg_32RegClass , AMDGPU :: SReg_32RegClass . getRegister ( NumUserSGPRs + <NUM_LIT> ) , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: SReg_32RegClass , AMDGPU :: SReg_32RegClass . getRegister ( NumUserSGPRs + <NUM_LIT> ) , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: SReg_32RegClass , AMDGPU :: SReg_32RegClass . getRegister ( NumUserSGPRs + <NUM_LIT> ) , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR0 , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR1 , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR2 , VT ) ; } } } return SDValue ( ) ;


<s> CN -> getValueAPF ( ) . convertToInteger ( IntVal , APFloat :: rmTowardZero , & IsExact ) ; if ( ! IsExact || ! IntVal . isPowerOf2 ( ) ) return false ;

unsigned FBits = IntVal . logBase2 ( ) ;


<s> return ( uint16x8_t ) __builtin_aarch64_urhaddv8hi ( ( int16x8_t ) __a , ( int16x8_t ) __b ) ;


<s> std :: string ArchFS = <STR_LIT> ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) { ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ;


<s> bool BExtended = false ; for ( MCInst :: iterator B = MCI . begin ( ) + <ISA_LIT>MCInstrInfo :: bundleInstructionsOffset ; B != MCI . end ( ) ; ++ B ) { MCInst const * Inst = B -> getInst ( ) ; if ( JumpInst == Inst ) continue ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( * Inst ) ) { BExtended = true ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> << JumpInst -> getOpcode ( ) << <STR_LIT> << Inst -> getOpcode ( ) << <STR_LIT> ) ; if ( isOrderedCompoundPair ( * Inst , BExtended , * JumpInst , JExtended ) ) { MCInst * CompoundInsn = getCompoundInsn ( Context , * Inst , * JumpInst ) ; if ( CompoundInsn ) { DEBUG ( dbgs ( ) << <STR_LIT> << Inst -> getOpcode ( ) << <STR_LIT> << JumpInst -> getOpcode ( ) << <STR_LIT> << CompoundInsn -> getOpcode ( ) << <STR_LIT> ) ;


<s> arm_init_simd_builtin_scalar_types ( ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( neon_builtin_data ) ; i ++ , fcode ++ ) { arm_builtin_datum * d = & neon_builtin_data [ i ] ; arm_init_builtin ( fcode , d , <STR_LIT> ) ; }


<s> unsigned FromReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ToReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . getRegClass ( FromReg ) != MRI . getRegClass ( ToReg ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; return ReplaceDominatedUses ( MBB , MI , FromReg , ToReg , MRI , MDT , LIS ) ;


<s> { OPTION_MASK_P9_VECTOR , OTHER_P9_VECTOR_MASKS , <STR_LIT> } , { OPTION_MASK_P8_VECTOR , OTHER_P8_VECTOR_MASKS , <STR_LIT> } , { OPTION_MASK_VSX , OTHER_VSX_VECTOR_MASKS , <STR_LIT> } , } ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( flags ) ; i ++ ) { HOST_WIDE_INT no_flag = flags [ i ] . no_flag ; if ( ( rs6000_isa_flags & no_flag ) == <NUM_LIT> && ( rs6000_isa_flags_explicit & no_flag ) != <NUM_LIT> ) { HOST_WIDE_INT dep_flags = flags [ i ] . dep_flags ; HOST_WIDE_INT set_flags = ( rs6000_isa_flags_explicit & rs6000_isa_flags & dep_flags ) ; if ( set_flags ) { for ( j = <NUM_LIT> ; j < ARRAY_SIZE ( rs6000_opt_masks ) ; j ++ ) if ( ( set_flags & rs6000_opt_masks [ j ] . mask ) != <NUM_LIT> ) { set_flags &= ~ rs6000_opt_masks [ j ] . mask ; error ( <STR_LIT> , flags [ i ] . name , rs6000_opt_masks [ j ] . name ) ; } gcc_assert ( ! set_flags ) ;


<s> inline vector unsigned short vec_vmaxuh ( vector unsigned short a1 , vector unsigned short a2 ) { return ( vector unsigned short ) __builtin_altivec_vmaxuh ( ( vector signed short ) a1 , ( vector signed short ) a2 ) ;


<s> if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return nullptr ; if ( isa < UndefValue > ( COp ) ) { Indexes [ I ] = - <NUM_LIT> ; continue ; } uint32_t Index = cast < ConstantInt > ( COp ) -> getZExtValue ( ) ; Index &= Size - <NUM_LIT> ; Indexes [ I ] = Index ;


<s> vld1q_dup_p8 ( const poly8_t * __a ) {

return ( poly8x16_t ) __builtin_neon_vld1_dupv16qi ( ( const __builtin_neon_qi * ) __a ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mii , MCContext & ctx ) : MII ( mii ) , Ctx ( ctx ) {


<s> int x = avr_map ( f , i ) ; if ( x <= <NUM_LIT> ) { x = avr_map ( ginv , x ) ; if ( x > <NUM_LIT> ) return f_ginv ; } f_ginv . map = ( f_ginv . map << <NUM_LIT> ) + x ; } if ( <NUM_LIT> == avr_map_metric ( f_ginv . map , MAP_NONFIXED_0_7 ) ) { f_ginv . cost = <NUM_LIT> + ( val_used_p && ! val_const_p ) ; } else { rtx xop [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = all_regs_rtx [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = gen_int_mode ( f_ginv . map , SImode ) ; xop [ <NUM_LIT> ] = all_regs_rtx [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = val_used_p ? xop [ <NUM_LIT> ] : const0_rtx ; avr_out_insert_bits ( xop , & f_ginv . cost ) ; f_ginv . cost += val_const_p && val_used_p ? <NUM_LIT> : <NUM_LIT> ; }


<s> switch ( mmmmmFromXOP2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) { default : dbgprintf ( insn , <STR_LIT> , mmmmmFromVEX2of3 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) ) ; return - <NUM_LIT> ; case XOP_MAP_SELECT_8 : insn -> opcodeType = XOP8_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_9 : insn -> opcodeType = XOP9_MAP ; return consumeByte ( insn , & insn -> opcode ) ; case XOP_MAP_SELECT_A : insn -> opcodeType = XOPA_MAP ; return consumeByte ( insn , & insn -> opcode ) ; } } if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_38 ; } else if ( current == <NUM_LIT> ) { dbgprintf ( insn , <STR_LIT> , current ) ; if ( consumeByte ( insn , & current ) ) return - <NUM_LIT> ; insn -> opcodeType = THREEBYTE_3A ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectInlineAsmMemoryOperand ( const SDValue & Op , unsigned ConstraintID , std :: vector < SDValue > & OutOps ) { switch ( ConstraintID ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_Q : OutOps . push_back ( Op ) ; return false ; }


<s> return _mm512_inserti32x4 ( _mm512_setzero_si512 ( ) , __A , <NUM_LIT> ) ;


<s> if ( ! reg ) return false ; if ( modes_too && ( GET_MODE ( in ) != GET_MODE ( reg ) ) ) return false ; return ( REGNO ( in ) == REGNO ( reg ) ) ; case SCRATCH : case CC0 : case PC : case CONST_INT : case CONST_DOUBLE : return false ; default : break ; } if ( code == SET && ! reg ) return mep_mentioned_p ( SET_DEST ( in ) , reg , modes_too ) ; fmt = GET_RTX_FORMAT ( code ) ; for ( i = GET_RTX_LENGTH ( code ) - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( fmt [ i ] == 'E' ) { register int j ; for ( j = XVECLEN ( in , i ) - <NUM_LIT> ; j >= <NUM_LIT> ; j -- ) if ( mep_mentioned_p ( XVECEXP ( in , i , j ) , reg , modes_too ) ) return true ; } else if ( fmt [ i ] == 'e' && mep_mentioned_p ( XEXP ( in , i ) , reg , modes_too ) ) return true ; }


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; EVT ExtraVT = cast < VTSDNode > ( N1 ) -> getVT ( ) ; SDLoc dl ( N ) ; if ( VT == <STR_LIT> && ( N0 . getOpcode ( ) == <STR_LIT> || N0 . getOpcode ( ) == <STR_LIT> ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> && Subtarget . hasInt256 ( ) ) if ( ! <STR_LIT> ( N00 . getNode ( ) ) ) return SDValue ( ) ; if ( N00 . getValueType ( ) == <STR_LIT> && ExtraVT . getSizeInBits ( ) < <NUM_LIT> ) { SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N00 , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp ) ; } }


<s> void <ISA_LIT>BankConflictHazardRecognizer :: AdvanceCycle ( ) {


<s> { MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_NC , <STR_LIT> } , { MO_TLS , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } } ;


static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ;


<s> if ( isVEXTMask ( ShuffleMask , VT , ReverseVEXT , Imm ) ) { if ( ReverseVEXT ) std :: swap ( V1 , V2 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG . getConstant ( Imm , <STR_LIT> ) ) ; } if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; if ( isVREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 ) ; unsigned WhichResult ; if ( isVTRNMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( isVUZPMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( isVZIPMask ( ShuffleMask , VT , WhichResult ) ) return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , VT ) , V1 , V2 ) . getValue ( WhichResult ) ; if ( VT . getVectorNumElements ( ) == <NUM_LIT> && ( VT . is128BitVector ( ) || VT . is64BitVector ( ) ) ) { unsigned PFIndexes [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { if ( ShuffleMask [ i ] < <NUM_LIT> ) PFIndexes [ i ] = <NUM_LIT> ; else PFIndexes [ i ] = ShuffleMask [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ;

unsigned Cost = ( PFEntry >> <NUM_LIT> ) ;


<s> if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { ImmDisp = Tok . getIntVal ( ) ; AsmToken ImmDispToken = Parser . Lex ( ) ; if ( isParsingInlineAsm ( ) ) InstInfo -> AsmRewrites -> emplace_back ( AOK_ImmPrefix , ImmDispToken . getLoc ( ) ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { const MCExpr * Disp = MCConstantExpr :: create ( ImmDisp , getContext ( ) ) ; return <STR_LIT> ( getPointerWidth ( ) , SegReg , Disp , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , ImmDispToken . getEndLoc ( ) , Size ) ; } } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression ( SegReg , Start , ImmDisp , false , Size ) ;


<s> unsigned Reg = UnusedReg ; <ISA_LIT>Regs . resize ( MF . getRegInfo ( ) . getNumVirtRegs ( ) , Reg ) ;


<s> return ; } for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * child_fma ; rtx fma_rtx , * accum_rtx_p ; if ( ! is_fmul_fmac_insn ( chain -> insn , false ) ) continue ; fma_rtx = SET_SRC ( PATTERN ( chain -> insn ) ) ; if ( GET_CODE ( fma_rtx ) == NEG ) fma_rtx = XEXP ( fma_rtx , <NUM_LIT> ) ; accum_rtx_p = & XEXP ( fma_rtx , <NUM_LIT> ) ; if ( ! REG_P ( * accum_rtx_p ) ) accum_rtx_p = & XEXP ( * accum_rtx_p , <NUM_LIT> ) ; if ( accum_rtx_p != chain -> loc ) continue ; if ( this -> get_fma_node ( chain -> insn ) ) continue ; child_fma = new fma_node ( node , chain ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> explicit <ISA_LIT>AsmPrinter ( raw_ostream & O , <ISA_LIT>TargetMachine & TM , const TargetAsmInfo * T , CodeGenOpt :: Level OL , bool V ) : AsmPrinter ( O , TM , T , OL , V ) , DbgInfo ( O , T ) {


<s> else if ( unsigned_p ) return aarch64_lookup_simd_builtin_type ( mode , qualifier_unsigned ) ;

else return aarch64_lookup_simd_builtin_type ( mode , qualifier_none ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ST ) , Subtarget ( ST ) {


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;


<s> MachineBasicBlock * SB = * B -> succ_begin ( ) ; MachineLoop * L = MLI -> getLoopFor ( SB ) ;

return L && SB == L -> getHeader ( ) && MDT -> dominates ( B , SB ) ;


<s> SmallVector < PHISourceT , <NUM_LIT> > ElimiatedSources ; for ( auto <ISA_LIT> : Sources ) {

if ( <ISA_LIT> . first == SourceReg && ( <ISA_LIT> . second == nullptr || <ISA_LIT> . second == SourceMBB ) ) {


<s> void <ISA_LIT>TargetStreamer :: emitObjectArch ( unsigned Arch ) {


<s> } hi = trunc_int_for_mode ( value & <NUM_LIT> , SImode ) ; lo = value & <NUM_LIT> ; insn = emit_move_insn ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , GEN_INT ( hi ) ) ; if ( lo ) { insn = emit_insn ( gen_iorsi3 ( gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) , GEN_INT ( lo ) ) ) ; } insn = emit_insn ( gen_addsi3 ( gen_rtx_REG ( SImode , dest ) , gen_rtx_REG ( SImode , src ) , gen_rtx_REG ( SImode , REGSAVE_CONTROL_TEMP ) ) ) ; if ( mark_frame ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( gen_rtx_REG ( SImode , dest ) , gen_rtx_PLUS ( SImode , gen_rtx_REG ( SImode , dest ) , GEN_INT ( value ) ) ) ) ;


<s> return ! ( TARGET_HITACHI || ca -> renesas_abi ) && ! TARGET_SH5 ;


<s> RegisterAsmInfoFn A ( The<ISA_LIT>Target , createMCAsmInfo ) ; TargetRegistry :: RegisterCodeEmitter ( The<ISA_LIT>Target , llvm :: create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterAsmBackend ( The<ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ;

TargetRegistry :: RegisterObjectStreamer ( The<ISA_LIT>Target , createMCStreamer ) ;