<s> typedef SmallVector < MachineDomTreeNode * , <NUM_LIT> > DTNodeVectType ; DTNodeVectType Cn ( GTN :: child_begin ( N ) , GTN :: child_end ( N ) ) ; for ( DTNodeVectType :: iterator I = Cn . begin ( ) , E = Cn . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * SB = ( * I ) -> getBlock ( ) ; if ( ! Deleted . count ( SB ) ) Changed |= visitBlock ( SB , L ) ; } if ( MLI -> getLoopFor ( B ) != L ) return Changed ; FlowPattern FP ;

if ( ! matchFlowPattern ( B , L , FP ) ) return Changed ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> return __builtin_ia32_vcvtpd2ph128_mask ( ( __v2df ) __B , _mm_setzero_ph ( ) , __A ) ;


<s> void addMemNoOffsetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ;


<s> for ( const auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCI ) ) { auto MI = I . getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isDuplex ( MCII , * MI ) ) return true ; }


<s> switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned OffsetIdx = MI . getNumExplicitOperands ( ) - <NUM_LIT> ; assert ( MI . getOperand ( OffsetIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MachineOperand & OffsetOpnd = MI . getOperand ( OffsetIdx ) ; assert ( LocalStackSize % Scale == <NUM_LIT> ) ;

OffsetOpnd . setImm ( OffsetOpnd . getImm ( ) + LocalStackSize / Scale ) ;


<s> MachineInstr * <ISA_LIT>InstrInfo :: convertToThreeAddress ( MachineFunction :: iterator & MBB , MachineInstr & MI , LiveVariables * LV ) const { switch ( MI . getOpcode ( ) ) { default : break ; case CASE_WIDEOP_OPCODE_LMULS ( FWADD_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( FWSUB_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WADD_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WADDU_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUB_WV ) : case CASE_WIDEOP_OPCODE_LMULS ( WSUBU_WV ) : { unsigned NewOpc ; switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( FWSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADD_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WADDU_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUB_WV ) CASE_WIDEOP_CHANGE_OPCODE_LMULS ( WSUBU_WV ) } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( NewOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; MIB . copyImplicitOps ( MI ) ; if ( LV ) { unsigned NumOps = MI . getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) { MachineOperand & Op = MI . getOperand ( I ) ; if ( Op . isReg ( ) && Op . isKill ( ) ) LV -> replaceKillInstruction ( Op . getReg ( ) , MI , * MIB ) ; } } return MIB ;


<s> unsigned MadeChange = false ; for ( std :: vector < CPEntry > & CPEs : CPEntries ) { for ( CPEntry & CPE : CPEs ) { if ( CPE . RefCount == <NUM_LIT> && CPE . CPEMI ) { removeDeadCPEMI ( CPE . CPEMI ) ; CPE . CPEMI = nullptr ;


<s> if ( TRI -> regsOverlap ( MOReg , Reg ) ) { if ( MO . isUse ( ) ) Ref . Use = true ; else if ( MO . isDef ( ) ) Ref . Def = true ; } } } }


<s> case V16QImode : gen = gen_aarch64_zip2v16qi ; break ; case V8QImode : gen = gen_aarch64_zip2v8qi ; break ; case V8HImode : gen = gen_aarch64_zip2v8hi ; break ; case V4HImode : gen = gen_aarch64_zip2v4hi ; break ; case V4SImode : gen = gen_aarch64_zip2v4si ; break ; case V2SImode : gen = gen_aarch64_zip2v2si ; break ; case V2DImode : gen = gen_aarch64_zip2v2di ; break ; case V4SFmode : gen = gen_aarch64_zip2v4sf ; break ; case V2SFmode : gen = gen_aarch64_zip2v2sf ; break ; case V2DFmode : gen = gen_aarch64_zip2v2df ; break ; default : return false ; } } else { switch ( vmode ) { case V16QImode : gen = gen_aarch64_zip1v16qi ; break ; case V8QImode : gen = gen_aarch64_zip1v8qi ; break ; case V8HImode : gen = gen_aarch64_zip1v8hi ; break ; case V4HImode : gen = gen_aarch64_zip1v4hi ; break ; case V4SImode : gen = gen_aarch64_zip1v4si ; break ; case V2SImode : gen = gen_aarch64_zip1v2si ; break ;

case V2DImode : gen = gen_aarch64_zip1v2di ; break ;


<s> if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> getLastNonDebugInstr ( ) ) && BMI -> isUnconditionalBranch ( ) ) { MachineBasicBlock * NewDest = getDestBlock ( * BMI ) ; if ( isBlockInRange ( MI , * NewDest ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; changeBranchDestBlock ( * BMI , * DestBB ) ; int NewSize = insertInvertedConditionalBranch ( * MBB , MI . getIterator ( ) , MI . getDebugLoc ( ) , MI , * NewDest ) ; int OldSize = TII -> getInstSizeInBytes ( MI ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += ( NewSize - OldSize ) ; MI . eraseFromParent ( ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock * TBB , * FBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; TII -> analyzeBranch ( * MBB , TBB , FBB , Cond , false ) ; MachineBasicBlock * NewBB = splitBlockBeforeInstr ( MI ) ; int delta = TII -> getInstSizeInBytes ( MBB -> back ( ) ) ;

BlockInfo [ MBB -> getNumber ( ) ] . Size -= delta ;


<s> bool enableVPU ( ) const { return EnableVPU ;


<s> if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return Op -> getOperand ( <NUM_LIT> ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , VT , Op -> getOperand ( <NUM_LIT> ) ) ; }


<s> emit_move_insn ( reg , mem ) ; return alloc_reg_note ( REG_CFA_RESTORE , reg , cfa_restores ) ;


return ( uint8x16_t ) __builtin_aarch64_popcountv16qi ( ( int8x16_t ) __a ) ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( TLI . getVarArgsFrameOffset ( ) , <STR_LIT> ) ) ;

const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> addPass ( createAtomicExpandPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( <NUM_LIT> , true , true , false , true ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ;


<s> bool <ISA_LIT>FastISel :: selectSelect ( const Instruction * I ) { assert ( isa < SelectInst > ( I ) && <STR_LIT> ) ; MVT VT ; if ( ! isTypeSupported ( I -> getType ( ) , VT ) ) return false ; unsigned Opc ; const TargetRegisterClass * RC ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; } const SelectInst * SI = cast < SelectInst > ( I ) ; const Value * Cond = SI -> getCondition ( ) ; <STR_LIT> CC = <STR_LIT> ; <STR_LIT> ExtraCC = <STR_LIT> ; if ( optimizeSelect ( SI ) ) return true ; if ( foldXALUIntrinsic ( CC , I , Cond ) ) { unsigned CondReg = getRegForValue ( Cond ) ; if ( ! CondReg ) return false ; } else if ( isa < CmpInst > ( Cond ) && cast < CmpInst > ( Cond ) -> hasOneUse ( ) && isValueAvailable ( Cond ) ) { const auto * Cmp = cast < CmpInst > ( Cond ) ;

CmpInst :: Predicate Predicate = optimizeCmpPredicate ( Cmp ) ;


<s> if ( MaybeDotNew . is ( AsmToken :: TokenKind :: Identifier ) && MaybeDotNew . getString ( ) . equals_lower ( <STR_LIT> ) ) splitIdentifier ( Operands ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( RParen , Begin ) ) ; return false ; } if ( previousEqual ( Operands , <NUM_LIT> , <STR_LIT> ) && previousEqual ( Operands , <NUM_LIT> , <STR_LIT> ) ) { if ( WarnMissingParenthesis ) Warning ( Begin , <STR_LIT> ) ; static char const * LParen = <STR_LIT> ; static char const * RParen = <STR_LIT> ; Operands . insert ( Operands . end ( ) - <NUM_LIT> , <ISA_LIT>Operand :: CreateToken ( LParen , Begin ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( Register , Begin , End ) ) ; const AsmToken & MaybeDotNew = Lexer . getTok ( ) ; if ( MaybeDotNew . is ( AsmToken :: TokenKind :: Identifier ) && MaybeDotNew . getString ( ) . equals_lower ( <STR_LIT> ) ) splitIdentifier ( Operands ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( RParen , Begin ) ) ; return false ; } break ; }


<s> Info . opc = <STR_LIT> ; const EVT VT = TLI . getMemValueType ( DL , CI . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; ElementCount EC = VT . getVectorElementCount ( ) ; for ( unsigned I = <NUM_LIT> ; I < NumVecs ; ++ I ) assert ( VT == TLI . getMemValueType ( DL , CI . getArgOperand ( I ) -> getType ( ) ) && <STR_LIT> ) ;

Info . memVT = EVT :: getVectorVT ( CI . getType ( ) -> getContext ( ) , VT . getScalarType ( ) , EC * NumVecs ) ;


<s> void printMemOffs8 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << <STR_LIT> ;


<s> enum rtx_code c = GET_CODE ( x ) ; if ( c == REG ) return <NUM_LIT> ; if ( c == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> if ( IndexVT == <STR_LIT> ) return SDValue ( ) ; MVT OrigVT = VT ; if ( Subtarget . hasAVX512 ( ) && ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && ! IndexVT . is512BitVector ( ) ) { unsigned Factor = std :: min ( <NUM_LIT> / VT . getSizeInBits ( ) , <NUM_LIT> / IndexVT . getSizeInBits ( ) ) ; unsigned NumElts = VT . getVectorNumElements ( ) * Factor ; VT = <STR_LIT> ( VT . getVectorElementType ( ) , NumElts ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , NumElts ) ; MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; PassThru = ExtendToType ( PassThru , VT , DAG ) ; Index = ExtendToType ( Index , IndexVT , DAG ) ; Mask = ExtendToType ( Mask , MaskVT , DAG , true ) ; } SDValue Ops [ ] = { N -> getChain ( ) , PassThru , Mask , N -> getBasePtr ( ) , Index , N -> getScale ( ) } ; SDValue NewGather = DAG . getTargetMemSDNode < <ISA_LIT>MaskedGatherSDNode > ( DAG . getVTList ( VT , MaskVT , <STR_LIT> ) , Ops , dl , N -> getMemoryVT ( ) , N -> getMemOperand ( ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , OrigVT , NewGather , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; return DAG . getMergeValues ( { Extract , NewGather . getValue ( <NUM_LIT> ) } , dl ) ;


<s> int one_bit_count ; unsigned HOST_WIDE_INT mask = GET_MODE_MASK ( SImode ) ;

one_bit_count = popcount_hwi ( ( unsigned HOST_WIDE_INT ) ( ival ) & mask ) ;


<s> default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Identifier : { if ( ! tryParseRegisterWithWriteBack ( Operands ) ) return false ; int Res = tryParseShiftRegister ( Operands ) ; if ( Res == <NUM_LIT> ) return false ; else if ( Res == - <NUM_LIT> ) return true ; if ( Mnemonic == <STR_LIT> && Parser . getTok ( ) . getString ( ) == <STR_LIT> ) { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } case AsmToken :: Integer : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return parseMemory ( Operands ) ; case AsmToken :: LCurly : return parseRegisterList ( Operands ) ; case AsmToken :: Hash : { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; bool isNegative = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! CE ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int32_t Val = CE -> getValue ( ) ; if ( isNegative && Val == <NUM_LIT> ) ImmVal = MCConstantExpr :: Create ( INT32_MIN , getContext ( ) ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ;


return ( uint64_t ) __builtin_aarch64_reduc_plus_scal_v2di ( ( int64x2_t ) __a ) ;


<s> const MCExpr * getMemShiftAmount ( ) const {

assert ( Mem . OffsetIsReg && Mem . OffsetRegShifted && <STR_LIT> ) ;


<s> ASM_OUTPUT_ALIGN ( asm_out_file , TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; } for ( i = <NUM_LIT> ; i < n_deferred_plabels ; i ++ ) { ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( deferred_plabels [ i ] . internal_label ) ) ; assemble_integer ( deferred_plabels [ i ] . symbol , TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> , TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( InstrPtr -> getOpcode ( ) == Instruction :: ExtractElement ) {

auto Arg0 = InstrPtr -> getOperand ( <NUM_LIT> ) ;


<s> assert ( Kind == KindImm && <STR_LIT> ) ;


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , PRI ( g . getPRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , LiveMap ( g . getPRI ( ) ) , NoRegs ( g . getPRI ( ) ) {


<s> if ( IsUnscaled ) Offset /= OffsetStride ; return Offset <= <NUM_LIT> && Offset >= - <NUM_LIT> ;


<s> bool enableIndirectBrExpand ( ) const override {

return useRetpolineIndirectBranches ( ) ;


<s> for ( x = REG_NOTES ( insn ) ; x ; x = XEXP ( x , <NUM_LIT> ) ) { if ( REG_NOTE_KIND ( x ) == REG_DEAD || REG_NOTE_KIND ( x ) == REG_UNUSED ) { rtx note = XEXP ( x , <NUM_LIT> ) ; if ( REG_P ( note ) && GET_MODE ( note ) == mode ) reg_weight -- ;


<s> SDValue Op1 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDValue Op2 = convertToScalableVector ( ContainerVT , Op . getOperand ( <NUM_LIT> ) , DAG , Subtarget ) ; SDLoc DL ( Op ) ; SDValue Mask , VL ; std :: tie ( Mask , VL ) = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) ; SDValue Select = DAG . getNode ( <STR_LIT> , DL , ContainerVT , CC , Op1 , Op2 , VL ) ;

return convertFromScalableVector ( VT , Select , DAG , Subtarget ) ;


<s> EVT PtrVT = Src . getValueType ( ) ; if ( Size > <NUM_LIT> * <NUM_LIT> ) return DAG . getNode ( Loop , DL , <STR_LIT> , Chain , Dst , Src , DAG . getConstant ( Size , DL , PtrVT ) , DAG . getConstant ( Size / <NUM_LIT> , DL , PtrVT ) ) ;

return DAG . getNode ( Sequence , DL , <STR_LIT> , Chain , Dst , Src , DAG . getConstant ( Size , DL , PtrVT ) ) ;


<s> switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_ADDRSPACE_CAST : return legalizeAddrSpaceCast ( MI , MRI , MIRBuilder ) ; default : return false ; } llvm_unreachable ( <STR_LIT> ) ;


<s> int incdec1 ; int index0 ; int index1 ; int disp0 ; int disp1 ; if ( MEM_VOLATILE_P ( op0 ) && MEM_VOLATILE_P ( op1 ) ) return <NUM_LIT> ; c4x_S_address_parse ( op0 , & base0 , & incdec0 , & index0 , & disp0 ) ; c4x_S_address_parse ( op1 , & base1 , & incdec1 , & index1 , & disp1 ) ; if ( store0 && store1 ) {


<s> virtual <ISA_LIT>TargetLowering * getTargetLowering ( ) const {

return const_cast < <ISA_LIT>TargetLowering * > ( & TLInfo ) ;


<s> return ; default : gcc_unreachable ( ) ; } } temp = gen_reg_rtx ( imode ) ; if ( imode == GET_MODE ( same ) ) temp2 = same ; else if ( GET_MODE_SIZE ( imode ) >= UNITS_PER_WORD ) temp2 = simplify_gen_subreg ( imode , same , GET_MODE ( same ) , <NUM_LIT> ) ; else temp2 = lowpart_subreg ( imode , same , GET_MODE ( same ) ) ; emit_move_insn ( temp , temp2 ) ; switch ( vmode ) { case E_V16QImode : case E_V8HImode : case E_V4SImode : case E_V2DImode : mips_emit_move ( target , gen_rtx_VEC_DUPLICATE ( vmode , temp ) ) ; break ; case E_V4SFmode : emit_insn ( gen_msa_splati_w_f_scalar ( target , temp ) ) ; break ; case E_V2DFmode : emit_insn ( gen_msa_splati_d_f_scalar ( target , temp ) ) ; break ; default : gcc_unreachable ( ) ; } } else { emit_move_insn ( target , CONST0_RTX ( vmode ) ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { rtx temp = gen_reg_rtx ( imode ) ; emit_move_insn ( temp , XVECEXP ( vals , <NUM_LIT> , i ) ) ; switch ( vmode ) { case E_V16QImode : emit_insn ( gen_vec_setv16qi ( target , temp , GEN_INT ( i ) ) ) ; break ; case E_V8HImode : emit_insn ( gen_vec_setv8hi ( target , temp , GEN_INT ( i ) ) ) ; break ; case E_V4SImode : emit_insn ( gen_vec_setv4si ( target , temp , GEN_INT ( i ) ) ) ; break ; case E_V2DImode : emit_insn ( gen_vec_setv2di ( target , temp , GEN_INT ( i ) ) ) ; break ; case E_V4SFmode : emit_insn ( gen_vec_setv4sf ( target , temp , GEN_INT ( i ) ) ) ; break ; case E_V2DFmode : emit_insn ( gen_vec_setv2df ( target , temp , GEN_INT ( i ) ) ) ; break ; default : gcc_unreachable ( ) ; } } } return ;


<s> const TargetRegisterInfo & getRegisterInfo ( ) const { return RI ;


<s> } else { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; } Offset = OffImm ; } else { <STR_LIT> AddSub = <STR_LIT> ; if ( OffImm < <NUM_LIT> ) { AddSub = <STR_LIT> ; OffImm = - OffImm ; } int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = <STR_LIT> ( AddSub , OffImm ) ; } EvenReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OddReg = Op1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( EvenReg == OddReg ) return false ; BaseReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isT2 ) OffReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = llvm :: getInstrPredicate ( Op0 , PredReg ) ; dl = Op0 -> getDebugLoc ( ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( MI ) ; } else { if ( ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ; }


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>leTargetMachine > X ( The<ISA_LIT>leTarget ) ; RegisterTargetMachine < <ISA_LIT>beTargetMachine > Y ( The<ISA_LIT>beTarget ) ;

RegisterTargetMachine < <ISA_LIT>leTargetMachine > Z ( TheARM64Target ) ;


<s> void SNITCHFrepLoops :: removeIfDead ( MachineInstr * MI ) { SmallVector < MachineInstr * , <NUM_LIT> > DeadPhis ; if ( isDead ( MI , DeadPhis ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; MachineRegisterInfo :: use_iterator nextI ; for ( MachineRegisterInfo :: use_iterator I = MRI -> use_begin ( Reg ) , E = MRI -> use_end ( ) ; I != E ; I = nextI ) { nextI = std :: next ( I ) ; MachineOperand & Use = * I ; MachineInstr * UseMI = I -> getParent ( ) ; if ( UseMI == MI ) continue ;

if ( Use . isDebug ( ) ) UseMI -> getOperand ( <NUM_LIT> ) . setReg ( <NUM_LIT> ) ;


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { MBB . erase ( I ) ;


<s> const DIType * PType = stripQualifiers ( cast < DIType > ( ParentType ) ) ; const DIType * CType = stripQualifiers ( cast < DIType > ( ChildType ) ) ; if ( isa < DIDerivedType > ( CType ) ) return false ; if ( const auto * PtrTy = dyn_cast < DIDerivedType > ( PType ) ) { if ( PtrTy -> getTag ( ) != dwarf :: DW_TAG_pointer_type ) return false ; return stripQualifiers ( PtrTy -> getBaseType ( ) ) == CType ; } const auto * PTy = dyn_cast < DICompositeType > ( PType ) ; const auto * CTy = dyn_cast < DICompositeType > ( CType ) ; assert ( PTy && CTy && <STR_LIT> ) ;


<s> unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = getFixupKindNumBytes ( Fixup . getKind ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) {

unsigned Idx = Endian == <STR_LIT> ? i : ( NumBytes - <NUM_LIT> - i ) ;


<s> } if ( ! DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; unsigned VecSize = VecVT . getSizeInBits ( ) ; unsigned EltSize = EltVT . getSizeInBits ( ) ; auto * Idx = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( EltSize <= <NUM_LIT> && EltVT . isByteSized ( ) && VecSize > <NUM_LIT> && VecSize % <NUM_LIT> == <NUM_LIT> && Idx ) { EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VecVT ) ; unsigned BitIndex = Idx -> getZExtValue ( ) * EltSize ; unsigned EltIdx = BitIndex / <NUM_LIT> ; unsigned LeftoverBitIdx = BitIndex % <NUM_LIT> ; SDLoc SL ( N ) ; SDValue Cast = DAG . getNode ( <STR_LIT> , SL , NewVT , Vec ) ; DCI . AddToWorklist ( Cast . getNode ( ) ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cast , DAG . getConstant ( EltIdx , SL , <STR_LIT> ) ) ; DCI . AddToWorklist ( Elt . getNode ( ) ) ; SDValue Srl = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Elt , DAG . getConstant ( LeftoverBitIdx , SL , <STR_LIT> ) ) ; DCI . AddToWorklist ( Srl . getNode ( ) ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , SL , EltVT . changeTypeToInteger ( ) , Srl ) ; DCI . AddToWorklist ( Trunc . getNode ( ) ) ; return DAG . getNode ( <STR_LIT> , SL , EltVT , Trunc ) ; } return SDValue ( ) ;


<s> MachineIRBuilder MIB ( I ) ; Register TargetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register ScratchReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto JumpTableInst = MIB . buildInstr ( <STR_LIT> , { TargetReg , ScratchReg } , { JTAddr , Index } ) . addJumpTableIndex ( JTI ) ; MIB . buildInstr ( <STR_LIT> , { } , { TargetReg } ) ; I . eraseFromParent ( ) ;

return constrainSelectedInstRegOperands ( * JumpTableInst , TII , TRI , RBI ) ;


<s> while ( llvm :: next ( I ) != MBB . end ( ) ) llvm :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> BranchCode = static_cast < <STR_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ;

if ( OldBranchCode == BranchCode ) continue ;


<s> bool Modified = false ; for ( MfIterator MFI = MF . begin ( ) ; MFI != MF . end ( ) ; ++ MFI ) {

Modified |= combineMemAluInBasicBlock ( & * MFI ) ;


<s> tree function_resolver :: resolve ( ) { return shape -> resolve ( * this ) ;


<s> return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'f' :

if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ;


<s> bool hfp = frame_pointer_needed || stack_realign_fp ; unsigned i , count ; unsigned regno ; for ( count = i = MIN_REGS ; i < MAX_REGS ; ++ i ) { regno = REG_ORDER [ i ] ; if ( regno == BP_REG && hfp ) continue ; if ( ! ix86_save_reg ( regno , false , false ) ) break ; ++ count ; } return count ;


<s> virtual SDValue LowerCall ( CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { CLI . Callee . dump ( ) ;


<s> return __builtin_mve_vmlaldavq_uv8hi ( __a , __b ) ;


<s> int <ISA_LIT>InstrInfo :: getMaxValue ( const MachineInstr * MI ) const { const uint64_t F = MI -> getDesc ( ) . TSFlags ; unsigned isSigned = ( F >> <STR_LIT> ) & <STR_LIT> ;

unsigned bits = ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> AU . addRequired < CallGraph > ( ) ;


if ( isConstantImm ( ) && isShiftedInt < Bits , ShiftLeftAmount > ( getConstantImm ( ) ) ) return true ;


<s> Xor = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , SaveExecReg ) . addReg ( Tmp ) . addReg ( CopyReg ) ; setImpSCCDefDead ( * Xor , ImpDefSCC . isDead ( ) ) ; } MachineInstr * SetExec = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Tmp , RegState :: Kill ) ; MachineInstr * NewBr = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; if ( ! LIS ) { MI . eraseFromParent ( ) ; return ; } LIS -> InsertMachineInstrInMaps ( * CopyExec ) ; LIS -> ReplaceMachineInstrInMaps ( MI , * And ) ; if ( ! SimpleIf ) LIS -> InsertMachineInstrInMaps ( * Xor ) ; LIS -> InsertMachineInstrInMaps ( * SetExec ) ; LIS -> InsertMachineInstrInMaps ( * NewBr ) ; LIS -> removeAllRegUnitsForPhysReg ( <STR_LIT> ) ; MI . eraseFromParent ( ) ; LIS -> removeInterval ( SaveExecReg ) ;

LIS -> createAndComputeVirtRegInterval ( SaveExecReg ) ;


<s> ASESet = <NUM_LIT> ; if ( P . hasDSP ( ) ) ASESet |= <STR_LIT> ; if ( P . hasDSPR2 ( ) ) ASESet |= <STR_LIT> ; if ( P . hasMSA ( ) ) ASESet |= <STR_LIT> ; if ( P . inMicro<ISA_LIT>Mode ( ) ) ASESet |= <STR_LIT> ;

if ( P . in<ISA_LIT>16Mode ( ) ) ASESet |= <STR_LIT> ;


<s> if ( sh_multcost >= <NUM_LIT> ) return sh_multcost ; if ( TARGET_SHMEDIA ) return TARGET_SMALLCODE ? <NUM_LIT> : <NUM_LIT> ; if ( TARGET_SH2 ) { if ( TARGET_SMALLCODE ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( TARGET_SMALLCODE ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Module & M , const std :: string & FS , bool isThumb ) : Subtarget ( M , FS , isThumb ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? ( isThumb ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> ) ) :


<s> bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const {

if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ;


<s> const TargetRegisterClass * RegClass = CSI [ i ] . getRegClass ( ) ; if ( RegClass == & <STR_LIT> ) loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RegClass ) ; } unsigned LowReg = MFI -> getLowReg ( ) , HighReg = MFI -> getHighReg ( ) ; unsigned StartOffset = RegSpillOffsets [ LowReg ] ; if ( StartOffset ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , get ( ( LowReg == HighReg ? <STR_LIT> : <STR_LIT> ) ) ) ; MIB . addReg ( LowReg , RegState :: Define ) ;

if ( LowReg != HighReg ) MIB . addReg ( HighReg , RegState :: Define ) ;


<s> case <STR_LIT> : return PerformUINT_TO_FPCombine ( N , DAG ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFP_TO_SINTCombine ( N , DAG ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return <NUM_LIT> ; if ( getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) return <NUM_LIT> ; } if ( isXNACKEnabled ( ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> if ( AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == nullptr ) { AM . Base_Reg = AM . IndexReg ; AM . Scale = <NUM_LIT> ; } } if ( TM . getCodeModel ( ) == CodeModel :: Small && Subtarget -> is64Bit ( ) && AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base_Reg . getNode ( ) == nullptr && AM . IndexReg . getNode ( ) == nullptr && AM . SymbolFlags == <STR_LIT> && AM . hasSymbolicDisplacement ( ) ) AM . Base_Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; return false ;


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) || ( Opc == <STR_LIT> ) ) { if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> bool SelectAddrModeIndexed8 ( SDValue N , SDValue & Base , SDValue & OffImm ) { return SelectAddrModeIndexed ( N , <NUM_LIT> , Base , OffImm ) ;


<s> EVT VT128 = EVT :: getVectorVT ( * Context , OpVT . getVectorElementType ( ) , OpVT . getVectorNumElements ( ) / <NUM_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT128 , Op . getOperand ( <NUM_LIT> ) ) ; return Insert128BitVector ( DAG . getUNDEF ( OpVT ) , Op , <NUM_LIT> , DAG , dl ) ; } if ( OpVT == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; assert ( OpVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AnyExt ) ) ;


<s>
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<s> if ( RB . getID ( ) == <STR_LIT> ) { if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ;


<s> if ( asm_noperands ( insn ) >= <NUM_LIT> ) return false ; rtx pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == CLOBBER || GET_CODE ( pat ) == USE ) return false ; if ( TARGET_FDPIC && GET_CODE ( pat ) == PARALLEL ) { rtx t = XVECEXP ( pat , <NUM_LIT> , XVECLEN ( pat , <NUM_LIT> ) - <NUM_LIT> ) ;

if ( GET_CODE ( t ) == USE && unspec_caller_rtx_p ( XEXP ( t , <NUM_LIT> ) ) ) return true ;


<s> if ( auto * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , Subtarget -> getXLenVT ( ) ) ;


<s> for ( ; I != E ; ++ I ) SequenceSize += getInstSizeInBytes ( * I ) ; unsigned CallOverhead = <NUM_LIT> ; for ( auto & C : RepeatedSequenceLocs ) C . setCallInfo ( MachineOutlinerDefault , CallOverhead ) ; unsigned FrameOverhead = <NUM_LIT> ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . getMF ( ) -> getSubtarget ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) FrameOverhead = <NUM_LIT> ;

return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , FrameOverhead , MachineOutlinerDefault ) ;


<s> MCSymbol * HandlerLabel = MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; unsigned LoadOpcode = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned LoadOperandsBeginIdx = <NUM_LIT> ; FM . recordFaultingOp ( FaultMaps :: FaultingLoad , HandlerLabel ) ; MCInst LoadMI ; LoadMI . setOpcode ( LoadOpcode ) ; LoadMI . addOperand ( MCOperand :: createReg ( LoadDefRegister ) ) ; for ( auto I = MI . operands_begin ( ) + LoadOperandsBeginIdx , E = MI . operands_end ( ) ; I != E ; ++ I ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , * I ) ) LoadMI . addOperand ( MaybeOperand . getValue ( ) ) ;

OutStreamer -> EmitInstruction ( LoadMI , getSubtargetInfo ( ) ) ;


<s> return ( STI . getFeatureBits ( ) & <STR_LIT> ) != <NUM_LIT> ;


<s> if ( Subtarget . useRetpoline ( ) ) return false ; return TargetLowering :: areJTsAllowed ( Fn ) ;


<s> unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= DataSize && <STR_LIT> ) ;

for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> TailCallArgumentInfo ( ) : FrameIdx ( <NUM_LIT> ) {


<s> if ( SubIdx == <STR_LIT> ) return RC ; LaneBitmask :: Type Mask = getSubRegIndexLaneMask ( SubIdx ) . getAsInteger ( ) ; unsigned Count = countPopulation ( Mask ) ; if ( isSGPRClass ( RC ) ) { switch ( Count ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> :


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> void addGR32orGR64Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; unsigned RegNo = getReg ( ) ;

if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( RegNo ) ) RegNo = getGR32FromGR64 ( RegNo ) ;


<s> static SDValue PerformAddCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ;

SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ;


<s> void EmitCOFFSecRel32 ( MCSymbol const * Symbol , uint64_t Offset ) override {


<s> ret . val [ <NUM_LIT> ] = __builtin_aarch64_get_dregxiv4hf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = __builtin_aarch64_get_dregxiv4hf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = __builtin_aarch64_get_dregxiv4hf ( __o , <NUM_LIT> ) ;


<s> } else BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BalTgtMBB -> rbegin ( ) -> bundleWithPred ( ) ; } else { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB , <STR_LIT> ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( Subtarget . has<ISA_LIT>64r6 ( ) ) BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; else BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ;


<s> std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; IRBuilder < > Builder ( Bitcast ) ; Value * Stride = Builder . getInt64 ( <NUM_LIT> ) ; Value * I8Ptr = Builder . CreateBitCast ( LD -> getOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Bitcast -> replaceAllUsesWith ( NewInst ) ;


<s> static DecodeStatus DecodeBranchTarget26 ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) {

int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) * <NUM_LIT> + <NUM_LIT> ;


<s> getTargetStreamer ( ) . emitARM64WinCFINop ( ) ;


tree ftype_cmse_nonsecure_caller = build_function_type_list ( unsigned_type_node , NULL ) ;


<s> RC . add ( intToConst ( A2 ) ) ; Result = RC ; return true ; } LatticeCell LS1 ; if ( ! getCell ( R1 , Inputs , LS1 ) ) return false ; if ( LS1 . isBottom ( ) || LS1 . isProperty ( ) ) return false ; APInt A , ResA ; for ( unsigned i = <NUM_LIT> ; i < LS1 . size ( ) ; ++ i ) {

bool Eval = constToInt ( LS1 . Values [ i ] , A ) && evaluateANDii ( A , A2 , ResA ) ;


<s> dbgs ( ) << <STR_LIT> << Print < RegisterRef > ( RR , * this ) << <STR_LIT> << * MI << <STR_LIT> << MI -> getParent ( ) -> getNumber ( ) << '\n' ; llvm_unreachable ( nullptr ) ; } DefM [ RR . Reg ] . push ( DA ) ; for ( RegisterRef A : getAliasSet ( RR . Reg ) ) { assert ( A != RR ) ; DefM [ A . Reg ] . push ( DA ) ; }

for ( NodeAddr < NodeBase * > T : Rel ) Visited . insert ( T . Id ) ;


<s> <ISA_LIT>TargetObjectFile & getObjFileLowering ( ) const { return ( <ISA_LIT>TargetObjectFile & ) AsmPrinter :: getObjFileLowering ( ) ;


<s> errs ( ) << <STR_LIT> << <STR_LIT> << MI -> getOpcode ( ) << <STR_LIT> << Value ; if ( ShiftBy ) errs ( ) << <STR_LIT> << ( <NUM_LIT> << ShiftBy ) << <STR_LIT> ; assert ( false && <STR_LIT> ) ; } }


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveFPLR ( SMLoc L ) { int64_t Offset ; if ( parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveFPLR ( Offset ) ; return false ;


<s> std :: vector < std :: string > load_ps01 ( Imm4 a ) { return D ( <STR_LIT> , a , <STR_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; bool IsKill = ! IsRAAndRetAddrIsTaken ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( * EntryBlock , MI , Reg , IsKill , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; }


<s> else memindex = <NUM_LIT> , regindex = <NUM_LIT> , offset = ( index + <NUM_LIT> ) * - <NUM_LIT> ;

if ( GET_CODE ( x ) == SET && GET_CODE ( XEXP ( x , regindex ) ) == REG && GET_CODE ( XEXP ( x , memindex ) ) == MEM && h8300_stack_offset_p ( XEXP ( XEXP ( x , memindex ) , <NUM_LIT> ) , offset ) ) return REGNO ( XEXP ( x , regindex ) ) ;


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; } } EVT VecTy ; if ( isLoad ) VecTy = N -> getValueType ( <NUM_LIT> ) ; else VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint64_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ; } else if ( NumBytes >= <NUM_LIT> * <NUM_LIT> ) { continue ; } EVT Tys [ <NUM_LIT> ] ; unsigned NumResultVecs = ( isLoad ? NumVecs : <NUM_LIT> ) ; unsigned n ; for ( n = <NUM_LIT> ; n < NumResultVecs ; ++ n ) Tys [ n ] = VecTy ; Tys [ n ++ ] = <STR_LIT> ; Tys [ n ] = <STR_LIT> ; SDVTList SDTys = DAG . getVTList ( Tys , NumResultVecs + <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ;

Ops . push_back ( N -> getOperand ( AddrOpIdx ) ) ;


<s> else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! CC_<ISA_LIT>32 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( ! CC_<ISA_LIT>64 ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ) return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset = State . AllocateStack ( ArgFlags . getByValSize ( ) , <NUM_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> uint64_t SrcB = fieldFromInstruction ( insn , <ISA_LIT>II :: SpuSrcBStart , <ISA_LIT>II :: SpuSrcBSize ) ; uint64_t Dest = fieldFromInstruction ( insn , <ISA_LIT>II :: SpuDestStart , <ISA_LIT>II :: SpuDestSize ) ; uint64_t OpType = fieldFromInstruction ( insn , <ISA_LIT>II :: SpuOpTypeStart , <ISA_LIT>II :: SpuOpTypeSize ) ; uint64_t Switches = fieldFromInstruction ( insn , <ISA_LIT>II :: SpuSwitchesStart , <ISA_LIT>II :: SpuSwitchesSize ) ; uint64_t Predicate = fieldFromInstruction ( insn , <ISA_LIT>II :: SpuPredicateStart , <ISA_LIT>II :: SpuPredicateSize ) ; bool Polarity = ( bool ) fieldFromInstruction ( insn , <ISA_LIT>II :: SpuPolarityBit , <NUM_LIT> ) ;


<s> SDValue Ops [ ] = { DAG . getEntryNode ( ) , Rsrc , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , { } , { } , { } , DAG . getConstant ( CachePolicy , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , } ; setBufferOffsets ( Offset , DAG , & Ops [ <NUM_LIT> ] , NumLoads > <NUM_LIT> ? <NUM_LIT> * NumLoads : <NUM_LIT> ) ; uint64_t InstOffset = cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> getZExtValue ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumLoads ; ++ i ) { Ops [ <NUM_LIT> ] = DAG . getConstant ( InstOffset + <NUM_LIT> * i , DL , <STR_LIT> ) ; Loads . push_back ( DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTList , Ops , LoadVT , MMO ) ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , VT , Loads ) ; return Loads [ <NUM_LIT> ] ;


<s> const MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ;

if ( const BasicBlock * B = Pred -> getBasicBlock ( ) ) if ( isa < SwitchInst > ( B -> getTerminator ( ) ) ) return false ;


<s> any_addr_mask = <NUM_LIT> ; for ( rc = FIRST_RELOAD_REG_CLASS ; rc <= LAST_RELOAD_REG_CLASS ; rc ++ ) { addr_mask = <NUM_LIT> ; reg = reload_reg_map [ rc ] . reg ; if ( reg >= <NUM_LIT> && rs6000_hard_regno_mode_ok_p [ m ] [ reg ] ) { bool small_int_vsx_p = ( small_int_p && ( rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX ) ) ; nregs = rs6000_hard_regno_nregs [ m ] [ reg ] ; addr_mask |= RELOAD_REG_VALID ; if ( small_int_vsx_p ) addr_mask |= RELOAD_REG_INDEXED ; else if ( nregs > <NUM_LIT> || m == BLKmode || complex_p ) addr_mask |= RELOAD_REG_MULTIPLE ; else addr_mask |= RELOAD_REG_INDEXED ; if ( TARGET_UPDATE && ( rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR ) && msize <= <NUM_LIT> && ! VECTOR_MODE_P ( m2 ) && ! FLOAT128_VECTOR_P ( m2 ) && ! complex_p && ! small_int_vsx_p && ( m2 != DFmode || ! TARGET_UPPER_REGS_DF ) && ( m2 != SFmode || ! TARGET_UPPER_REGS_SF ) && ! ( TARGET_E500_DOUBLE && msize == <NUM_LIT> ) ) { addr_mask |= RELOAD_REG_PRE_INCDEC ; switch ( m ) { default : addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case E_DImode : if ( TARGET_POWERPC64 ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; case E_DFmode : case E_DDmode : if ( TARGET_DF_INSN ) addr_mask |= RELOAD_REG_PRE_MODIFY ; break ; } } } if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize <= <NUM_LIT> && ( rc == RELOAD_REG_GPR || ( ( msize == <NUM_LIT> || m2 == SFmode ) && ( rc == RELOAD_REG_FPR || ( rc == RELOAD_REG_VMX && TARGET_P9_DFORM_SCALAR ) ) ) ) ) addr_mask |= RELOAD_REG_OFFSET ; else if ( ( addr_mask != <NUM_LIT> ) && ! indexed_only_p && msize == <NUM_LIT> && TARGET_P9_DFORM_VECTOR && ( ALTIVEC_OR_VSX_VECTOR_MODE ( m2 ) || ( m2 == TImode && TARGET_VSX_TIMODE ) ) ) {


<s> result = ( __vector __m64 ) vec_cts ( temp , <NUM_LIT> ) ; return ( ( __m64 ) __builtin_unpack_vector_int128 ( ( __vector __int128 ) result , <NUM_LIT> ) ) ;


<s> const char * output_move_const_double ( rtx * operands ) { int code = standard_68881_constant_p ( operands [ <NUM_LIT> ] ) ; if ( code != <NUM_LIT> ) { static char buf [ <NUM_LIT> ] ; sprintf ( buf , <STR_LIT> , code & <NUM_LIT> ) ; return buf ; } return <STR_LIT> ;


<s> } APInt MaskedHighBits = APInt :: getHighBitsSet ( X . getValueSizeInBits ( ) , MaskLZ ) ; APInt KnownZero , KnownOne ; DAG . ComputeMaskedBits ( X , MaskedHighBits , KnownZero , KnownOne ) ; if ( MaskedHighBits != KnownZero ) return true ; EVT VT = N . getValueType ( ) ; if ( ReplacingAnyExtend ) { assert ( X . getValueType ( ) != VT ) ; SDValue NewX = DAG . getNode ( <STR_LIT> , X . getDebugLoc ( ) , VT , X ) ; InsertDAGNode ( DAG , N , NewX ) ; X = NewX ; } DebugLoc DL = N . getDebugLoc ( ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , <STR_LIT> ) ; SDValue NewSRL = DAG . getNode ( <STR_LIT> , DL , VT , X , NewSRLAmt ) ; SDValue NewSHLAmt = DAG . getConstant ( AMShiftAmt , <STR_LIT> ) ; SDValue NewSHL = DAG . getNode ( <STR_LIT> , DL , VT , NewSRL , NewSHLAmt ) ; InsertDAGNode ( DAG , N , NewSRLAmt ) ; InsertDAGNode ( DAG , N , NewSRL ) ; InsertDAGNode ( DAG , N , NewSHLAmt ) ; InsertDAGNode ( DAG , N , NewSHL ) ; DAG . ReplaceAllUsesWith ( N , NewSHL ) ; AM . Scale = <NUM_LIT> << AMShiftAmt ;


<s> case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerTRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , VarArgsFrameIndex , VarArgsStackOffset , VarArgsNumGPR , VarArgsNumFPR , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG , VarArgsFrameIndex , VarArgsStackOffset , VarArgsNumGPR , VarArgsNumFPR , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerFORMAL_ARGUMENTS ( Op , DAG , VarArgsFrameIndex , VarArgsStackOffset , VarArgsNumGPR , VarArgsNumFPR , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerCALL ( Op , DAG , <ISA_LIT>SubTarget , getTargetMachine ( ) ) ;

case <STR_LIT> : return LowerRET ( Op , DAG , getTargetMachine ( ) ) ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override {

Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> return ( Offset >= <ISA_LIT>_MEMD_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMD_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMW_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMW_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMH_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMH_AUTOINC_MAX && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) { return ( Offset >= <ISA_LIT>_MEMB_AUTOINC_MIN && Offset <= <ISA_LIT>_MEMB_AUTOINC_MAX ) ;


<s> static inline bool isLoopStart ( MachineInstr & MI ) {

return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ;


<s> bool lastInITBlock ( ) { return ITState . CurPosition == <NUM_LIT> - countTrailingZeros ( ITState . Mask ) ;


<s> return _mm_cmpeq_pi8 ( __m1 , __m2 ) ;


<s> return <STR_LIT> + std :: to_string ( sgx_callsite_magic_index_public - <NUM_LIT> ) ;


<s> std :: string rv ; raw_string_ostream OS ( rv ) ; auto OpPrinter = [ & OS , & MI , this ] ( const MachineOperand & Operand ) { if ( Operand . isReg ( ) ) { if ( Operand . isUndef ( ) ) OS << <STR_LIT> ; else OS << printReg ( Operand . getReg ( ) ) ; if ( auto DbgVar = findDebugValue ( MI , Operand . getReg ( ) ) ) OS << <STR_LIT> << DbgVar -> getName ( ) << <STR_LIT> ; } else { OS << Operand ; } } ; auto CommaOpPrinter = [ & OS , & OpPrinter ] ( const MachineOperand & Operand ) { OS << <STR_LIT> ; OpPrinter ( Operand ) ; } ; OS << <STR_LIT> ; OpPrinter ( * MI . defs ( ) . begin ( ) ) ; llvm :: for_each ( drop_begin ( MI . defs ( ) , <NUM_LIT> ) , CommaOpPrinter ) ; OS << <STR_LIT> << TII -> getName ( MI . getOpcode ( ) ) << <STR_LIT> ; auto Uses = MI . uses ( ) ; if ( Uses . begin ( ) != Uses . end ( ) ) { OpPrinter ( * MI . uses ( ) . begin ( ) ) ; llvm :: for_each ( drop_begin ( MI . uses ( ) , <NUM_LIT> ) , CommaOpPrinter ) ; } OS . flush ( ) ; return OS . str ( ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; EVT VT = Op0 . getValueType ( ) ;

SDValue NewXor = DAG . getNode ( <STR_LIT> , Op1 . getDebugLoc ( ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ XorC , VT ) ) ;


<s> if ( ! Subtarget -> hasFlatInstOffsets ( ) ) { return AM . BaseOffs == <NUM_LIT> && AM . Scale == <NUM_LIT> ;


<s> if ( fn == AARCH64_SIMD_BUILTIN_UNOP_sqrtv4sf ) return aarch64_builtin_decls [ AARCH64_BUILTIN_RSQRT_V4SF ] ; return NULL_TREE ;


<s> if ( ByValSize == <NUM_LIT> ) { State . addLoc ( CCValAssign :: getMem ( ValNo , <STR_LIT> , State . getNextStackOffset ( ) , RegVT , LocInfo ) ) ; return false ; } const unsigned StackSize = alignTo ( ByValSize , PtrAlign ) ; unsigned Offset = State . AllocateStack ( StackSize , PtrAlign ) ; for ( const unsigned E = Offset + StackSize ; Offset < E ; Offset += PtrAlign . value ( ) ) { if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; else { State . addLoc ( CCValAssign :: getMem ( ValNo , <STR_LIT> , Offset , <STR_LIT> , LocInfo ) ) ; break ; } } return false ; } switch ( ValVT . SimpleTy ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : assert ( Is<ISA_LIT>64 && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : { const unsigned Offset = State . AllocateStack ( PtrAlign . value ( ) , PtrAlign ) ; if ( ValVT . getFixedSizeInBits ( ) < RegVT . getFixedSizeInBits ( ) ) LocInfo = ArgFlags . isSExt ( ) ? CCValAssign :: LocInfo :: SExt : CCValAssign :: LocInfo :: ZExt ; if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , RegVT , LocInfo ) ) ; return false ; } case <STR_LIT> : case <STR_LIT> : { const unsigned StoreSize = LocVT . getStoreSize ( ) ; const unsigned Offset = State . AllocateStack ( Is<ISA_LIT>64 ? <NUM_LIT> : StoreSize , Align ( <NUM_LIT> ) ) ; unsigned FReg = State . AllocateReg ( FPR ) ; if ( FReg ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , FReg , LocVT , LocInfo ) ) ; for ( unsigned I = <NUM_LIT> ; I < StoreSize ; I += PtrAlign . value ( ) ) { if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) { assert ( FReg && <STR_LIT> ) ; if ( State . isVarArg ( ) ) { State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; } } else { State . addLoc ( FReg ? CCValAssign :: getCustomMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) : CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; break ; } } return false ; } } return true ;


<s> } if ( const MCBinaryExpr * BExpr = dyn_cast < MCBinaryExpr > ( Expr ) ) { const MCSymbol * LHSSym = getSingleMCSymbol ( BExpr -> getLHS ( ) ) ; const MCSymbol * RHSSym = getSingleMCSymbol ( BExpr -> getRHS ( ) ) ; if ( LHSSym ) return LHSSym ; if ( RHSSym ) return RHSSym ; return nullptr ; } if ( const MCUnaryExpr * UExpr = dyn_cast < MCUnaryExpr > ( Expr ) ) return getSingleMCSymbol ( UExpr -> getSubExpr ( ) ) ; return nullptr ;


<s> case <STR_LIT> : return - <NUM_LIT> <= BrOffset && BrOffset <= <NUM_LIT> ; case <STR_LIT> : return true ;


<s> named_parm_regs = ( sh_round_reg ( * get_cumulative_args ( ca ) , mode ) + ( mode == BLKmode ? CEIL ( int_size_in_bytes ( type ) , UNITS_PER_WORD ) : CEIL ( GET_MODE_SIZE ( mode ) , UNITS_PER_WORD ) ) ) ; anon_parm_regs = NPARM_REGS ( SImode ) - named_parm_regs ;


<s> const unsigned * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const unsigned CalleeSavedRegs [ ] = { <NUM_LIT> } ; return CalleeSavedRegs ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , MI , dl , TII -> get ( Opc ) ) ; unsigned NumArgs = MI -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumArgs ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! ( Op . isReg ( ) && Op . isImplicit ( ) ) ) MIB . addOperand ( Op ) ; } if ( MI -> hasOneMemOperand ( ) ) MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( ) ; return BB ;


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target32 ( ) , create<ISA_LIT>Disassembler ) ;

TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target64 ( ) , create<ISA_LIT>Disassembler ) ;


<s> outs ( ) << <STR_LIT> ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , MBBE = MF . end ( ) ; MBB != MBBE ; ++ MBB ) { for ( MachineBasicBlock :: iterator MI = MBB -> begin ( ) , ME = MBB -> getFirstTerminator ( ) ; MI != ME ; ++ MI ) { outs ( ) << <STR_LIT> ; MI -> print ( outs ( ) , & ( MF . getTarget ( ) ) , false ) ; } outs ( ) << <STR_LIT> ; for ( MachineBasicBlock :: iterator MI = MBB -> getFirstTerminator ( ) , ME = MBB -> end ( ) ; MI != ME ; ++ MI ) { outs ( ) << <STR_LIT> ; MI -> print ( outs ( ) , & ( MF . getTarget ( ) ) , false ) ;


<s> } case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , XLenVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : assert ( Op . getValueType ( ) == XLenVT && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return lowerScalarSplat ( Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getSimpleValueType ( ) , DL , DAG , Subtarget ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : { SDValue Scalar = Op . getOperand ( <NUM_LIT> ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) { Scalar = DAG . getNode ( <STR_LIT> , DL , XLenVT , Scalar ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Scalar , Op . getOperand ( <NUM_LIT> ) ) ; } assert ( Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue VL = getVLOperand ( Op ) ; SDValue SplattedVal = splatSplitI64WithVL ( DL , VT , SDValue ( ) , Scalar , VL , DAG ) ; if ( Op . getOperand ( <NUM_LIT> ) . isUndef ( ) ) return SplattedVal ; SDValue SplattedIdx = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , VL ) ; MVT MaskVT = getMaskTypeFor ( VT ) ; SDValue Mask = getAllOnesMask ( VT , VL , DL , DAG ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; SDValue SelectCond = DAG . getNode ( <STR_LIT> , DL , MaskVT , VID , SplattedIdx , DAG . getCondCode ( <STR_LIT> ) , Mask , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectCond , SplattedVal , Vec , VL ) ; }


<s> sigstk . ss_sp = ( char * ) xmalloc ( SIGSTKSZ ) ; sigstk . ss_size = SIGSTKSZ ; sigstk . ss_flags = <NUM_LIT> ; if ( sigaltstack ( & sigstk , NULL ) < <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> ) ; sigemptyset ( & sact . sa_mask ) ; sact . sa_flags = SA_ONSTACK | SA_SIGINFO ; sact . sa_sigaction = segv_handler ;

if ( sigaction ( SIGSEGV , & sact , <NUM_LIT> ) < <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( The<ISA_LIT>Target ) ;


<s> bool AMDGPUCFGStructurizer :: isReturnBlock ( MachineBasicBlock * MBB ) { MachineInstr * MI = getReturnInstr ( MBB ) ; bool IsReturn = ( MBB -> succ_size ( ) == <NUM_LIT> ) ;


<s> const Function * F = A -> getParent ( ) ; CallingConv :: ID CC = F -> getCallingConv ( ) ; switch ( CC ) { case CallingConv :: <ISA_LIT>_KERNEL : case CallingConv :: SPIR_KERNEL : return true ; case CallingConv :: <ISA_LIT>_VS : case CallingConv :: <ISA_LIT>_LS : case CallingConv :: <ISA_LIT>_HS : case CallingConv :: <ISA_LIT>_ES : case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_Gfx : return F -> getAttributes ( ) . hasParamAttribute ( A -> getArgNo ( ) , Attribute :: InReg ) || F -> getAttributes ( ) . hasParamAttribute ( A -> getArgNo ( ) , Attribute :: ByVal ) ; default : return false ;


<s> EVT VmovVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , EncodedVal ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ;


<s> static const char * avr_out_movqi_mr_r_reg_disp_tiny ( rtx_insn * insn , rtx op [ ] , int * plen ) { rtx dest = op [ <NUM_LIT> ] ; rtx src = op [ <NUM_LIT> ] ; rtx x = XEXP ( dest , <NUM_LIT> ) ; if ( reg_overlap_mentioned_p ( src , XEXP ( x , <NUM_LIT> ) ) ) { avr_asm_len ( <STR_LIT> CR_TAB TINY_ADIW ( % I0 , % J0 , % o0 ) CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } else { avr_asm_len ( TINY_ADIW ( % I0 , % J0 , % o0 ) CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; }

if ( ! reg_unused_after ( insn , XEXP ( x , <NUM_LIT> ) ) ) avr_asm_len ( TINY_SBIW ( % I0 , % J0 , % o0 ) , op , plen , <NUM_LIT> ) ;


<s> virtual void loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , unsigned DestReg , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const {

loadRegFromStack ( MBB , MBBI , DestReg , FrameIndex , RC , TRI , <NUM_LIT> ) ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> int Cost = BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , I ) ;

return vectorCostAdjustment ( Cost , Opcode , ValTy , nullptr ) ;


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;

return getDirectBrEncoding ( MI , OpNo , Fixups , STI ) ;


<s> void printTBAddrMode ( const MCInst * MI , unsigned OpNum ) {


<s> void emitFileDirective ( StringRef Filename ) override {


<s> if ( Subtarget . hasSSE2 ( ) && ( Subtarget . getPreferVectorWidth ( ) >= <NUM_LIT> ) ) return <STR_LIT> ; if ( Subtarget . hasSSE1 ( ) && ( Subtarget . is64Bit ( ) || Subtarget . hasX87 ( ) ) && ( Subtarget . getPreferVectorWidth ( ) >= <NUM_LIT> ) ) return <STR_LIT> ; } else if ( ( ( Op . isMemcpy ( ) && ! Op . isMemcpyStrSrc ( ) ) || Op . isZeroMemset ( ) ) && Op . size ( ) >= <NUM_LIT> && ! Subtarget . is64Bit ( ) && Subtarget . hasSSE2 ( ) ) { return <STR_LIT> ; } } if ( Subtarget . is64Bit ( ) && Op . size ( ) >= <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT> ;


<s> return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : { SDValue Scalar = Op . getOperand ( <NUM_LIT> ) ; EVT ScalarTy = Scalar . getValueType ( ) ; if ( ( ScalarTy == <STR_LIT> ) || ( ScalarTy == <STR_LIT> ) ) Scalar = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Scalar ) ;

return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Scalar ) ;


<s> void <ISA_LIT>TargetLowering :: insertCopiesSplitCSR ( MachineBasicBlock * Entry , const SmallVectorImpl < MachineBasicBlock * > & Exits ) const { const <ISA_LIT>RegisterInfo * TRI = getSubtarget ( ) -> getRegisterInfo ( ) ; const MCPhysReg * IStart = TRI -> getCalleeSavedRegsViaCopy ( Entry -> getParent ( ) ) ; if ( ! IStart ) return ; const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ; MachineRegisterInfo * MRI = & Entry -> getParent ( ) -> getRegInfo ( ) ;

MachineBasicBlock :: iterator MBBI = Entry -> begin ( ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;


<s> bool Was16 = isCode16 ( StartInfo . getTargetTriple ( ) ) ;

if ( ! EndInfo || Was16 != isCode16 ( EndInfo -> getTargetTriple ( ) ) ) {


<s>
if
(
MO2
.
getReg
(
)
)
{
O
<<
' '
<<
getRegisterName
(
MO2
.
getReg
(
)
)
;
assert
(
<STR_LIT>
(
MO3
.
getImm
(
)
)
==
<NUM_LIT>
)
;
}
else
if
(
ShOpc
!=
<STR_LIT>
)
{
O
<<
<STR_LIT>
<<
<STR_LIT>
(
MO3
.
getImm
(
)
)
;


<s> case <STR_LIT> : return ELF :: R_MIPS_PC21_S2 ; case <STR_LIT> : return ELF :: R_MIPS_PC26_S2 ; case <STR_LIT> : return ELF :: R_MIPS_PCHI16 ; case <STR_LIT> : return ELF :: R_MIPS_PCLO16 ; } llvm_unreachable ( <STR_LIT> ) ; } switch ( Kind ) { case <STR_LIT> : case FK_Data_8 : return ELF :: R_MIPS_64 ; case FK_DTPRel_4 : return ELF :: R_MIPS_TLS_DTPREL32 ; case FK_DTPRel_8 : return ELF :: R_MIPS_TLS_DTPREL64 ; case FK_TPRel_4 : return ELF :: R_MIPS_TLS_TPREL32 ; case FK_TPRel_8 : return ELF :: R_MIPS_TLS_TPREL64 ; case FK_GPRel_4 : if ( is64Bit ( ) ) { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL32 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_64 , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_NONE , Type ) ; return Type ; } return ELF :: R_MIPS_GPREL32 ; case <STR_LIT> : return ELF :: R_MIPS_GPREL16 ; case <STR_LIT> : return ELF :: R_MIPS_26 ; case <STR_LIT> : return ELF :: R_MIPS_CALL16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MICROMIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MICROMIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MICROMIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; return Type ; }


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;

SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , VT ) ;


<s> const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; uint64_t StackSize = MFI . getStackSize ( ) - <NUM_LIT> - <ISA_LIT>FI -> getIncomingArgSize ( ) ; if ( StackSize == <NUM_LIT> ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; return ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> return ( int16x4_t ) __builtin_aarch64_srshr_nv4hi ( __a , __b ) ;


<s> if ( ( TheTriple . getArch ( ) == Triple :: mips ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) IsLittleEndian = false ; if ( ( TheTriple . getArch ( ) == Triple :: mips64el ) || ( TheTriple . getArch ( ) == Triple :: mips64 ) ) { PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } if ( ( TheTriple . getArch ( ) == Triple :: mipsel ) || ( TheTriple . getArch ( ) == Triple :: mips ) ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; } AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ;


<s> SDValue EltIdx = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = InputVector . getValueType ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( InputVector ) ; if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getBitcast ( VT , InputVector ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MMXSrc ) ; } if ( VT == <STR_LIT> && InputVector . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( EltIdx ) && isa < ConstantSDNode > ( InputVector . getOperand ( <NUM_LIT> ) ) ) { uint64_t ExtractedElt = N -> getConstantOperandVal ( <NUM_LIT> ) ; auto * InputC = cast < ConstantSDNode > ( InputVector . getOperand ( <NUM_LIT> ) ) ; const APInt & InputValue = InputC -> getAPIntValue ( ) ; uint64_t Res = InputValue [ ExtractedElt ] ; return DAG . getConstant ( Res , dl , <STR_LIT> ) ; }

if ( SDValue SAD = combineBasicSADPattern ( N , DAG , Subtarget ) ) return SAD ;


<s> unsigned & OpIdx = NumOpsAdded ; OpIdx = <NUM_LIT> ; unsigned RdRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; assert ( NumOps >= <NUM_LIT> && ( RdRegClassID == <STR_LIT> || RdRegClassID == <STR_LIT> ) && <STR_LIT> ) ; unsigned RnRegClassID = OpInfo [ <NUM_LIT> ] . RegClass ; bool TwoReg = ( RnRegClassID == <STR_LIT> || RnRegClassID == <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RdRegClassID , decodeRs ( insn ) ) ) ) ; ++ OpIdx ; if ( TwoReg ) { assert ( NumOps >= <NUM_LIT> && <STR_LIT> ) ; int Idx ; if ( ( Idx = TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) ) != - <NUM_LIT> ) { MI . addOperand ( MI . getOperand ( Idx ) ) ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RnRegClassID , decodeRn ( insn ) ) ) ) ; } ++ OpIdx ; } if ( Opcode == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RnRegClassID , decodeRn ( insn ) ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; ++ OpIdx ;

if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) MI . addOperand ( MCOperand :: CreateImm ( getIImm3Imm8 ( insn ) ) ) ;


<s> return ( __m256i ) __builtin_ia32_cvtmask2w256 ( __A ) ;


return ( int16x4_t ) __builtin_neon_vreinterpretv4hiv2sf ( __a ) ;


<s> return build_int_cst ( build_pointer_type ( type ) , TYPE_ALIGN ( type ) ) ;


<s> Sym = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; return true ; } else if ( AM . CP ) { Sym = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; return true ; } else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Sym = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; return true ; } else if ( AM . MCSym ) { assert ( ! AM . Disp && <STR_LIT> ) ;

assert ( AM . SymbolFlags == <NUM_LIT> && <STR_LIT> ) ;


<s> MachineLoop * HeaderLoop = MLI . getLoopFor ( Header ) ; if ( HeaderLoop && MBB . getNumber ( ) > LoopBottom ( HeaderLoop ) -> getNumber ( ) ) { InsertPos = Header -> begin ( ) ; while ( InsertPos -> getOpcode ( ) != <STR_LIT> ) ++ InsertPos ; } else { InsertPos = Header -> getFirstTerminator ( ) ; while ( InsertPos != Header -> begin ( ) && IsChild ( prev ( InsertPos ) , MFI ) && prev ( InsertPos ) -> getOpcode ( ) != <STR_LIT> && prev ( InsertPos ) -> getOpcode ( ) != <STR_LIT> && prev ( InsertPos ) -> getOpcode ( ) != <STR_LIT> ) -- InsertPos ; } BuildMI ( * Header , InsertPos , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; InsertPos = MBB . begin ( ) ; while ( InsertPos != MBB . end ( ) && InsertPos -> getOpcode ( ) == <STR_LIT> ) ++ InsertPos ; BuildMI ( MBB , InsertPos , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) ;


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case VK_<ISA_LIT>_None : break ; case VK_<ISA_LIT>_GPREL : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT_CALL : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TLSGD : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOTTPREL : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TPREL_HI : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_TPREL_LO : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GPOFF_HI : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GPOFF_LO : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT_DISP : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT_PAGE : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_GOT_OFST : OS << <STR_LIT> ; break ; } OS << * Symbol ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ; OS << Offset ; } if ( Kind == VK_<ISA_LIT>_GPOFF_HI || Kind == VK_<ISA_LIT>_GPOFF_LO ) OS << <STR_LIT> ; else if ( Kind != VK_<ISA_LIT>_None ) OS << ')' ;


<s> if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return Fail ; } if ( Bytes . size ( ) >= <NUM_LIT> ) { uint64_t Insn64 ; if ( ! readInstruction64 ( Bytes , Address , Size , Insn64 ) ) return Fail ; Result = decodeInstruction ( DecoderTable64 , Instr , Insn64 , Address , this , STI ) ; if ( Result == MCDisassembler :: Success ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return MCDisassembler :: Success ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; } uint32_t Insn32 ; if ( ! readInstruction32 ( Bytes , Address , Size , Insn32 ) ) {


<s> void <ISA_LIT>InstPrinterBase :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ;


<s> return DFmode ; case <NUM_LIT> : if ( TARGET_FLOAT128_KEYWORD ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ; else return VOIDmode ; case <NUM_LIT> : return VOIDmode ; default : gcc_unreachable ( ) ; } } else {


<s> switch ( MBBI -> getOpcode ( ) ) { default : return <NUM_LIT> ; case TargetOpcode :: PATCHABLE_RET : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ;

for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) {


<s> assert ( Offset && <STR_LIT> ) ; if ( StartOffset > Offset ) { LowGPR = Reg ; StartOffset = Offset ; } } } ZFI -> setLowSavedGPR ( LowGPR ) ; ZFI -> setHighSavedGPR ( HighGPR ) ; if ( IsVarArg ) { unsigned FirstGPR = ZFI -> getVarArgsFirstGPR ( ) ; if ( FirstGPR < <STR_LIT> ) { unsigned Reg = <STR_LIT> [ FirstGPR ] ; unsigned Offset = RegSpillOffsets [ Reg ] ; if ( StartOffset > Offset ) { LowGPR = Reg ; StartOffset = Offset ; } } } if ( LowGPR ) { assert ( LowGPR != HighGPR && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; addSavedGPR ( MBB , MIB , LowGPR , false ) ; addSavedGPR ( MBB , MIB , HighGPR , false ) ; MIB . addReg ( <STR_LIT> ) . addImm ( StartOffset ) ;

for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) {


<s> if ( TARGET_64BIT && CASE_VECTOR_MODE == DImode ) directive = ASM_QUAD ; gcc_assert ( ! TARGET_64BIT ) ; if ( TARGET_64BIT || TARGET_VXWORKS_RTP ) fprintf ( file , <STR_LIT> , directive , LPREFIX , value , LPREFIX , rel ) ; else if ( HAVE_AS_GOTOFF_IN_DATA ) fprintf ( file , ASM_LONG <STR_LIT> , LPREFIX , value ) ; else if ( TARGET_MACHO ) {


<s> if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) && ! Binary ) llvm_unreachable ( <STR_LIT> ) ; const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; int Size = <NUM_LIT> ;

EmitInstruction ( Binary , Size , OS ) ;


<s> const char * vax_output_conditional_branch ( enum rtx_code code ) { switch ( code ) { case EQ : return <STR_LIT> ; case NE : return <STR_LIT> ; case GT : return <STR_LIT> ; case LT : return <STR_LIT> ; case GTU : return <STR_LIT> ; case LTU : return <STR_LIT> ; case GE : return <STR_LIT> ; case LE : return <STR_LIT> ; case GEU : return <STR_LIT> ; case LEU : return <STR_LIT> ;


<s> bool hasRetAddrStack ( ) const { return HasRetAddrStack ;


<s> switch ( BLR . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : BLOpcode = <STR_LIT> ; Reg = BLR . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> ) ; RegIsKilled = BLR . getOperand ( <NUM_LIT> ) . isKill ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; default : llvm_unreachable ( <STR_LIT> ) ; } DebugLoc DL = BLR . getDebugLoc ( ) ; MachineFunction & MF = * MBBI -> getMF ( ) ; MCContext & Context = MBB . getParent ( ) -> getContext ( ) ; auto ThunkIt = llvm :: find_if ( SLSBLRThunks , [ Reg ] ( auto T ) { return T . Reg == Reg ; } ) ; assert ( ThunkIt != std :: end ( SLSBLRThunks ) ) ; MCSymbol * Sym = Context . getOrCreateSymbol ( ThunkIt -> Name ) ; MachineInstr * BL = BuildMI ( MBB , MBBI , DL , TII -> get ( BLOpcode ) ) . addSym ( Sym ) ; int ImpLROpIdx = - <NUM_LIT> ; int ImpSPOpIdx = - <NUM_LIT> ; for ( unsigned OpIdx = BL -> getNumExplicitOperands ( ) ; OpIdx < BL -> getNumOperands ( ) ; OpIdx ++ ) { MachineOperand Op = BL -> getOperand ( OpIdx ) ; if ( ! Op . isReg ( ) ) continue ; if ( Op . getReg ( ) == <STR_LIT> && Op . isDef ( ) ) ImpLROpIdx = OpIdx ; if ( Op . getReg ( ) == <STR_LIT> && ! Op . isDef ( ) ) ImpSPOpIdx = OpIdx ; } assert ( ImpLROpIdx != - <NUM_LIT> ) ; assert ( ImpSPOpIdx != - <NUM_LIT> ) ; int FirstOpIdxToRemove = std :: max ( ImpLROpIdx , ImpSPOpIdx ) ; int SecondOpIdxToRemove = std :: min ( ImpLROpIdx , ImpSPOpIdx ) ; BL -> removeOperand ( FirstOpIdxToRemove ) ; BL -> removeOperand ( SecondOpIdxToRemove ) ; BL -> copyImplicitOps ( MF , BLR ) ;


<s> MemInsns . push_back ( & MI ) ; continue ; } } int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } if ( MayLoad && TRI -> isSuperOrSubRegisterEq ( Reg , getLdStRegOp ( MI ) . getReg ( ) ) ) { LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( ! ModifiedRegUnits . available ( BaseReg ) ) return E ; if ( ModifiedRegUnits . available ( getLdStRegOp ( MI ) . getReg ( ) ) && ! ( MI . mayLoad ( ) && ! UsedRegUnits . available ( getLdStRegOp ( MI ) . getReg ( ) ) ) && ! mayAlias ( MI , MemInsns , AA ) ) { Flags . setMergeForward ( false ) ; Flags . clearRenameReg ( ) ; return MBBI ; } if ( ! ( MayLoad && ! UsedRegUnits . available ( getLdStRegOp ( FirstMI ) . getReg ( ) ) ) && ! mayAlias ( FirstMI , MemInsns , AA ) ) { if ( ModifiedRegUnits . available ( getLdStRegOp ( FirstMI ) . getReg ( ) ) ) { Flags . setMergeForward ( true ) ; Flags . clearRenameReg ( ) ; return MBBI ;


<s> MachineBasicBlock * <ISA_LIT>16TargetLowering :: emitFEXT_T8I816_ins ( unsigned BtOpc , unsigned CmpOpc , MachineInstr & MI , MachineBasicBlock * BB ) const { if ( DontExpandCondPseudos16 ) return BB ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned regX = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

unsigned regY = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> static bool isSimpleBD12Move ( const MachineInstr * MI , unsigned Flag ) { const MCInstrDesc & MCID = MI -> getDesc ( ) ;

return ( ( MCID . TSFlags & Flag ) && isUInt < <NUM_LIT> > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) ;


<s> SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result_1 , <NUM_LIT> ) ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_3 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_2 ;


<s> b . append_name ( <STR_LIT> ) ; if ( ! overloaded_p ) { b . append_name ( operand_suffixes [ instance . op_info -> op ] ) ; b . append_name ( type_suffixes [ instance . type . index ] . vector ) ; } if ( overloaded_p && instance . pred == PRED_TYPE_m ) return b . finish_name ( ) ; b . append_name ( predication_suffixes [ instance . pred ] ) ;


<s> } MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( Name ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( L , <STR_LIT> ) ; return false ; } Lex ( ) ; const MCExpr * Expr ; if ( getParser ( ) . parseExpression ( Expr ) ) { Error ( L , <STR_LIT> ) ;


<s> MCInst JMPInst ; JMPInst . setOpcode ( <STR_LIT> ) ; JMPInst . addOperand ( Op ) ; Out . EmitInstruction ( JMPInst , STI ) ; Out . EmitCodeAlignment ( kNaCl<ISA_LIT>InstructionBundleSize ) ; Out . EmitLabel ( RetTarget ) ; } else { Out . EmitBundleLock ( true ) ; MCInst CALLInst ; CALLInst . setOpcode ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; CALLInst . addOperand ( Op ) ; Out . EmitInstruction ( CALLInst , STI ) ; Out . EmitBundleUnlock ( ) ; }


<s> SmallPtrSet < MachineInstr * , <NUM_LIT> > Remove ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { LoLoop . Start , LoLoop . Dec , LoLoop . End , LoLoop . InsertPt } ; SmallVector < MachineInstr * , <NUM_LIT> > Chain = { Def } ; while ( ! Chain . empty ( ) ) { MachineInstr * MI = Chain . back ( ) ; Chain . pop_back ( ) ; MachineInstr * IT = nullptr ; if ( TII -> getPredicate ( * MI ) != <STR_LIT> ) { auto PrevMI = std :: prev ( MI -> getIterator ( ) ) ; auto NextMI = std :: next ( MI -> getIterator ( ) ) ; if ( PrevMI -> getOpcode ( ) == <STR_LIT> && TII -> getPredicate ( * NextMI ) == <STR_LIT> ) IT = & * PrevMI ; else return ; } if ( RDA -> isSafeToRemove ( MI , Remove , Ignore ) ) { for ( auto & MO : MI -> operands ( ) ) {

if ( ! MO . isReg ( ) || ! MO . isUse ( ) || MO . getReg ( ) == <NUM_LIT> ) continue ;


<s> case BPF_BUILTIN_PRESERVE_FIELD_INFO : { rettype = build_function_type_list ( unsigned_type_node , type , unsigned_type_node , NULL ) ; int len = snprintf ( name , sizeof ( name ) , <STR_LIT> , <STR_LIT> ) ; len = snprintf ( name + len , sizeof ( name ) - len , <STR_LIT> , pfi_count ++ ) ;


<s> MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) { const Triple & TT = STI . getTargetTriple ( ) ; if ( TT . isOSBinFormatELF ( ) ) return new <ISA_LIT>TargetELFStreamer ( S ) ;

if ( TT . isOSBinFormatCOFF ( ) ) return new <ISA_LIT>TargetWinCOFFStreamer ( S ) ;


<s> m_pGOTSymbol = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Create ( * ( m_pGOT -> begin ( ) ) , <NUM_LIT> ) , ResolveInfo :: Hidden ) ; }


<s> printOperand ( MI , i ) ; if ( i != e - <NUM_LIT> ) O << <STR_LIT> ; }


<s> <ISA_LIT>AbstractMemberAccessLegacyPass ( <ISA_LIT>TargetMachine * TM = nullptr ) : FunctionPass ( ID ) , TM ( TM ) {


<s> static rtx aarch64_legitimize_address ( rtx x , rtx , machine_mode mode ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { rtx base = XEXP ( x , <NUM_LIT> ) ; rtx offset_rtx XEXP ( x , <NUM_LIT> ) ; HOST_WIDE_INT offset = INTVAL ( offset_rtx ) ; if ( GET_CODE ( base ) == PLUS ) { rtx op0 = XEXP ( base , <NUM_LIT> ) ; rtx op1 = XEXP ( base , <NUM_LIT> ) ; op0 = force_reg ( Pmode , op0 ) ; op1 = force_reg ( Pmode , op1 ) ; if ( REG_POINTER ( op1 ) ) std :: swap ( op0 , op1 ) ; if ( virt_or_elim_regno_p ( REGNO ( op0 ) ) ) { base = expand_binop ( Pmode , add_optab , op0 , offset_rtx , NULL_RTX , true , OPTAB_DIRECT ) ; return gen_rtx_PLUS ( Pmode , base , op1 ) ; } base = expand_binop ( Pmode , add_optab , op0 , op1 , NULL_RTX , true , OPTAB_DIRECT ) ; x = gen_rtx_PLUS ( Pmode , base , offset_rtx ) ; } HOST_WIDE_INT base_offset ; if ( GET_MODE_SIZE ( mode ) > <NUM_LIT> || mode == TImode ) base_offset = ( ( offset + <NUM_LIT> * GET_MODE_SIZE ( mode ) ) & ~ ( ( <NUM_LIT> * GET_MODE_SIZE ( mode ) ) - <NUM_LIT> ) ) ; else if ( offset & ( GET_MODE_SIZE ( mode ) - <NUM_LIT> ) ) base_offset = ( offset + <NUM_LIT> ) & ~ <NUM_LIT> ; else base_offset = offset & ~ <NUM_LIT> ; if ( base_offset != <NUM_LIT> ) { base = plus_constant ( Pmode , base , base_offset ) ; base = force_operand ( base , NULL_RTX ) ; return plus_constant ( Pmode , base , offset - base_offset ) ; }


<s> if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; get<ISA_LIT>16SPRefReg ( Parent , Alias ) ; } else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Opnd0 = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( Opnd0 ) || isa < GlobalAddressSDNode > ( Opnd0 ) || isa < JumpTableSDNode > ( Opnd0 ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Opnd0 ; return true ; } } const LSBaseSDNode * LS = dyn_cast < LSBaseSDNode > ( Parent ) ; if ( LS && ( LS -> getMemoryVT ( ) == <STR_LIT> || LS -> getMemoryVT ( ) == <STR_LIT> ) && Subtarget . hasFPIdx ( ) ) return false ; }


<s> ImmutablePass * llvm :: create<ISA_LIT>TargetTransformInfoPass ( const <ISA_LIT>TargetMachine * TM ) { return new <ISA_LIT>TTI ( TM ) ;


<s> EVT ValVT = VA . getValVT ( ) ; switch ( ValVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RC = <STR_LIT> ; break ; case <STR_LIT> : RC = <STR_LIT> ; break ; case <STR_LIT> : RC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RC = <STR_LIT> ; break ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , ValVT ) ; InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned ArgSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( ArgSize , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } SmallVector < CCValAssign , <NUM_LIT> > ByValArgLocs ; CCState CCByValInfo ( CallConv , isVarArg , getTargetMachine ( ) , ByValArgLocs , * DAG . getContext ( ) ) ; CCByValInfo . AllocateStack ( CCInfo . getNextStackOffset ( ) , PtrByteSize ) ; CCByValInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>_SVR4_ByVal ) ; unsigned MinReservedArea = CCByValInfo . getNextStackOffset ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MinReservedArea = std :: max ( MinReservedArea , <ISA_LIT>FrameInfo :: getMinCallFrameSize ( false , false ) ) ; unsigned TargetAlign = DAG . getMachineFunction ( ) . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; unsigned AlignMask = TargetAlign - <NUM_LIT> ; MinReservedArea = ( MinReservedArea + AlignMask ) & ~ AlignMask ; FI -> setMinReservedArea ( MinReservedArea ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; if ( isVarArg ) { static const unsigned GPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ;

const unsigned NumGPArgRegs = array_lengthof ( GPArgRegs ) ;


<s> MVT CastTy = tyVector ( Vec . getValueType ( ) . getSimpleVT ( ) , ElemTy ) ; return DAG . getBitcast ( CastTy , Vec ) ;


<s> bool AMDGPUDAGToDAGISel :: isCPLoad ( const LoadSDNode * N ) const { MachineMemOperand * MMO = N -> getMemOperand ( ) ;

if ( checkType ( N -> getSrcValue ( ) , <STR_LIT> ) ) {


<s> Addr . Base . FI = MFI . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; if ( ! <ISA_LIT>EmitStore ( <STR_LIT> , SrcReg , Addr ) ) return <NUM_LIT> ; unsigned LoadOpc = <STR_LIT> ; if ( SrcVT == <STR_LIT> ) { Addr . Offset = <NUM_LIT> ; if ( ! IsSigned ) LoadOpc = <STR_LIT> ; else if ( <ISA_LIT>SubTarget . hasLFIWAX ( ) ) LoadOpc = <STR_LIT> ; }

const TargetRegisterClass * RC = & <STR_LIT> ;


<s> continue ; } if ( theArgs [ i ] -> use_empty ( ) ) { if ( ObjectVT . isVector ( ) ) { EVT EltVT = ObjectVT . getVectorElementType ( ) ; unsigned NumElts = ObjectVT . getVectorNumElements ( ) ; for ( unsigned vi = <NUM_LIT> ; vi < NumElts ; ++ vi ) { InVals . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT ) ) ; } } else { InVals . push_back ( DAG . getNode ( <STR_LIT> , dl , ObjectVT ) ) ; } continue ; } if ( PAL . hasAttribute ( i + <NUM_LIT> , Attribute :: ByVal ) == false ) { if ( ObjectVT . isVector ( ) ) { unsigned NumElts = ObjectVT . getVectorNumElements ( ) ; EVT EltVT = ObjectVT . getVectorElementType ( ) ; unsigned Offset = <NUM_LIT> ; for ( unsigned vi = <NUM_LIT> ; vi < NumElts ; ++ vi ) { SDValue A = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; SDValue B = DAG . getIntPtrConstant ( Offset ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , A , B ) ; Value * SrcValue = Constant :: getNullValue ( PointerType :: get ( EltVT . getTypeForEVT ( F -> getContext ( ) ) , llvm :: ADDRESS_SPACE_PARAM ) ) ; SDValue Ld = DAG . getLoad ( EltVT , dl , Root , Addr , MachinePointerInfo ( SrcValue ) , false , false , false , TD -> getABITypeAlignment ( EltVT . getTypeForEVT ( F -> getContext ( ) ) ) ) ; Offset += EltVT . getStoreSizeInBits ( ) / <NUM_LIT> ; InVals . push_back ( Ld ) ; } continue ; } if ( isABI || isKernel ) { SDValue Arg = getParamSymbol ( DAG , idx , getPointerTy ( ) ) ; Value * srcValue = Constant :: getNullValue ( PointerType :: get ( ObjectVT . getTypeForEVT ( F -> getContext ( ) ) , llvm :: ADDRESS_SPACE_PARAM ) ) ; SDValue p = DAG . getLoad ( ObjectVT , dl , Root , Arg , MachinePointerInfo ( srcValue ) , false , false , false , TD -> getABITypeAlignment ( ObjectVT . getTypeForEVT ( F -> getContext ( ) ) ) ) ; if ( p . getNode ( ) ) p . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ; InVals . push_back ( p ) ; } else { SDValue Arg = getParamSymbol ( DAG , idx , ObjectVT ) ; SDValue p = DAG . getNode ( <STR_LIT> , dl , ObjectVT , Arg ) ; if ( p . getNode ( ) ) p . getNode ( ) -> setIROrder ( idx + <NUM_LIT> ) ;


<s> Register ScopeReg = buildI32Constant ( Scope , I ) ; MachineBasicBlock & BB = * I . getParent ( ) ;

return BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addUse ( ScopeReg ) . addUse ( MemSemReg ) . constrainAllUses ( TII , TRI , RBI ) ;


<s> void <ISA_LIT>InstrInfo :: genAlternativeCodeSequence ( MachineInstr & Root , MachineCombinerPattern :: MC_PATTERN Pattern , SmallVectorImpl < MachineInstr * > & InsInstrs , SmallVectorImpl < MachineInstr * > & DelInstrs , DenseMap < unsigned , unsigned > & InstIdxForVirtReg ) const { MachineRegisterInfo & MRI = Root . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; MachineInstr * Prev = nullptr ; switch ( Pattern ) { case MachineCombinerPattern :: MC_REASSOC_AX_BY : case MachineCombinerPattern :: MC_REASSOC_XA_BY :

Prev = MRI . getUniqueVRegDef ( Root . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N1 ) -> getMemOperand ( ) ; SDValue Ops0 [ ] = { N2 , LD -> getBasePtr ( ) , LD -> getChain ( ) } ; SDNode * ResNode = CurDAG -> SelectNodeTo ( Op , Opc , VT , <STR_LIT> , <STR_LIT> , Ops0 ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemRefs0 , MemRefs0 + <NUM_LIT> ) ; ReplaceUses ( SDValue ( N1 . getNode ( ) , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N1 . getNode ( ) , <NUM_LIT> ) , SDValue ( ResNode , <NUM_LIT> ) ) ;


<s> if ( SDValue Result = AddCombineToVPADDL ( N , N0 , N1 , DCI , Subtarget ) ) return Result ;

if ( N0 . getNode ( ) -> hasOneUse ( ) ) if ( SDValue Result = combineSelectAndUse ( N , N0 , N1 , DCI ) ) return Result ;


<s> opts -> x_explicit_arch = ptr -> x_explicit_arch ; selected_arch = aarch64_get_arch ( ptr -> x_explicit_arch ) ;

opts -> x_aarch64_override_tune_string = ptr -> x_aarch64_override_tune_string ;


<s> for ( auto MII = MF . begin ( ) -> begin ( ) , MIE = MF . begin ( ) -> end ( ) ; MII != MIE ; ) { MachineInstr * MI = & * MII ++ ; if ( MI -> isImplicitDef ( ) && MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) { LiveInterval & LI = LIS . getInterval ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; LIS . removeVRegDefAt ( LI , LIS . getInstructionIndex ( * MI ) . getRegSlot ( ) ) ;

LIS . RemoveMachineInstrFromMaps ( * MI ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;


<s> return ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> || ET == <STR_LIT> ;


<s> explicit <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , false ) {


<s> inline int vec_any_nge ( vector float a1 , vector float a2 ) {


<s> emitBinary ( OutStreamer , <STR_LIT> , RS1 , Imm , RD , STI ) ;


<s> SmallVector < int , <NUM_LIT> > M ; N -> getMask ( M ) ; return :: isUNPCKH_v_undef_Mask ( M , N -> getValueType ( <NUM_LIT> ) ) ;


<s> NeedMask = false ; RLAmt . resize ( Bits . size ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) ; ++ i ) if ( Bits [ i ] . hasValue ( ) ) { unsigned VBI = Bits [ i ] . getValueBitIndex ( ) ; if ( i >= VBI ) RLAmt [ i ] = i - VBI ; else RLAmt [ i ] = Bits . size ( ) - ( VBI - i ) ; } else if ( Bits [ i ] . isZero ( ) ) { NeedMask = true ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetNoMicro<ISA_LIT> ( ) {


<s> <ISA_LIT>FixupVectorISel ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>FixupVectorISelPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> if ( const MachineOperand * MO = MI . findRegisterDefOperand ( <STR_LIT> ) ) if ( ! MO -> isDead ( ) ) return true ; return false ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {


<s> __o = __builtin_aarch64_ld2di ( ( const __builtin_aarch64_simd_di * ) __a ) ;

ret . val [ <NUM_LIT> ] = ( uint64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ;


<s> void addIndirectSymAddr ( void * SymAddr , intptr_t IndSymAddr ) { Sym2IndirectSymMap . insert ( std :: make_pair ( SymAddr , IndSymAddr ) ) ;


attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveRegP ( SMLoc L ) { unsigned Reg ; int64_t Offset ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; getTargetStreamer ( ) . EmitARM64WinCFISaveRegP ( Reg , Offset ) ; return false ;


<s> static BOOL isPrefixAtLocation ( struct InternalInstruction * insn , uint8_t prefix , uint64_t location ) { if ( insn -> prefixPresent [ prefix ] == <NUM_LIT> && insn -> prefixLocations [ prefix ] == location ) return TRUE ;


<s> return __builtin_mve_vbrsrq_n_sv4si ( __a , __b ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( Size , Size ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , PseudoSourceValue :: getFixedStack ( SSFI ) , <NUM_LIT> ) ; SDVTList Tys ; bool useSSE = isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ; if ( useSSE ) Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; else Tys = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ;


<s> OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return false ; } if ( SelectADDRri ( Op . getNode ( ) , Op , Op0 , Op1 ) ) { OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; return false ; } break ;


<s> unsigned <ISA_LIT>FrameLowering :: getOpcGlobSet ( const MachineFunction & MF ) { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAddr64 ( ) ? <STR_LIT> : <STR_LIT> ;


<s> return X . getValueType ( ) . isScalarInteger ( ) ;


<s> assert ( ! IsLittleEndian && <STR_LIT> ) ; CodePointerSize = CalleeSaveStackSlotSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ;


<s> switch ( MsgId ) { case ID_GS_PreGFX11 : return ( OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_ ) && OpId != OP_GS_NOP ; case ID_GS_DONE_PreGFX11 :

return OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_ ;


<s> static <ISA_LIT>Operand * CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Register ) ; Op -> Reg . RegNum = RegNum ;


<s> SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; bool isF64 = ArgVT == <STR_LIT> ; const char * LibcallName = isF64 ? <STR_LIT> : <STR_LIT> ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = isF64 ? ( Type * ) StructType :: get ( ArgTy , ArgTy , nullptr ) : ( Type * ) VectorType :: get ( ArgTy , <NUM_LIT> ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) ) ;

std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ;