<s> bool <ISA_LIT>LoadStoreOpt :: findMatchingStore ( MachineBasicBlock :: iterator I , unsigned Limit , MachineBasicBlock :: iterator & StoreI ) { MachineBasicBlock :: iterator B = I -> getParent ( ) -> begin ( ) ; MachineBasicBlock :: iterator MBBI = I ; MachineInstr & LoadMI = * I ; Register BaseReg = getLdStBaseOp ( LoadMI ) . getReg ( ) ; if ( MBBI == B ) return false ; ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; unsigned Count = <NUM_LIT> ; do { -- MBBI ; MachineInstr & MI = * MBBI ; if ( ! MI . isTransient ( ) ) ++ Count ; if ( MI . mayStore ( ) && isMatchingStore ( LoadMI , MI ) && BaseReg == getLdStBaseOp ( MI ) . getReg ( ) && isLdOffsetInRangeOfSt ( LoadMI , MI , TII ) && ModifiedRegUnits . available ( getLdStRegOp ( MI ) . getReg ( ) ) ) { StoreI = MBBI ; return true ; } if ( MI . isCall ( ) ) return false ; LiveRegUnits :: accumulateUsedDefed ( MI , ModifiedRegUnits , UsedRegUnits , TRI ) ; if ( ! ModifiedRegUnits . available ( BaseReg ) ) return false ; if ( MI . mayStore ( ) && mayAlias ( LoadMI , MI , AA ) ) return false ; } while ( MBBI != B && Count < Limit ) ; return false ;


<s> void printARID8Mem ( const MCInst * MI , unsigned opNum , raw_ostream & O ) { printARIDMem ( MI , opNum , O ) ;


<s> static unsigned getMOVrrOpcode ( ) {


<s> break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOpStore ( Node , DataN , DataN . getOperand ( <NUM_LIT> ) , DataN . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOpStore ( Node , DataN , DataN . getOperand ( <NUM_LIT> ) , DataN . getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; } if ( SDNode * ResNode = SelectIndexedStore ( Node ) ) return ResNode ; } break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; else if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ; break ; case <STR_LIT> : if ( SDNode * ResNode = SelectIndexedBinOpLoad ( Node , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return ResNode ;


<s> static void initializePassOnce ( PassRegistry & Registry ) { const char * Name = <STR_LIT> ;

PassInfo * PI = new PassInfo ( Name , <STR_LIT> , & <ISA_LIT>SplitTFRCondSets :: ID , nullptr , false , false ) ;


<s> int32_t <ISA_LIT>SplitDoubleRegs :: profit ( unsigned Reg ) const { assert ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) ; const MachineInstr * DefI = MRI -> getVRegDef ( Reg ) ; switch ( DefI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return profit ( DefI ) ; default : break ; }


<s> int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , Op . getDebugLoc ( ) , getPointerTy ( ) , Offset ) ; return DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , getPointerTy ( ) , Result ) ;


<s> const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; bool HasBP = RegInfo -> hasBasePointer ( MF ) ; unsigned BPReg = HasBP ? ( unsigned ) RegInfo -> getBaseRegister ( MF ) : FPReg ; unsigned BP8Reg = HasBP ? ( unsigned ) <STR_LIT> : FP8Reg ; for ( MachineBasicBlock & MBB : MF ) for ( MachineBasicBlock :: iterator MBBI = MBB . end ( ) ; MBBI != MBB . begin ( ) ; ) { -- MBBI ; for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand ( I ) ; if ( ! MO . isReg ( ) ) continue ; switch ( MO . getReg ( ) ) { case <STR_LIT> : MO . setReg ( FPReg ) ; break ; case <STR_LIT> : MO . setReg ( FP8Reg ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = QQQQPRDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> SDValue GLC , TFE ; return SelectMUBUFAddr64 ( Addr , SRsrc , VAddr , SOffset , Offset , GLC , SLC , TFE ) ;


<s> Out . emitLabel ( TmpLabel ) ; const <ISA_LIT>MCExpr * SymbolHi = <ISA_LIT>MCExpr :: create ( Symbol , VKHi , Ctx ) ; emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addOperand ( TmpReg ) . addExpr ( SymbolHi ) ) ;

const MCExpr * RefToLinkTmpLabel = <ISA_LIT>MCExpr :: create ( MCSymbolRefExpr :: create ( TmpLabel , Ctx ) , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO , Ctx ) ;


<s> bool doMBBSchedRegionsTopDown ( ) const override { return true ;


<s> LLVM_READNONE static StringRef getGPUOrDefault ( const Triple & TT , StringRef GPU ) {


<s> TREE_STATIC ( decl ) = <NUM_LIT> ; DECL_IGNORED_P ( decl ) = <NUM_LIT> ; if ( USE_HIDDEN_LINKONCE ) { cgraph_node :: create ( decl ) -> set_comdat_group ( DECL_ASSEMBLER_NAME ( decl ) ) ; targetm . asm_out . unique_section ( decl , <NUM_LIT> ) ; switch_to_section ( get_named_section ( decl , NULL , <NUM_LIT> ) ) ; targetm . asm_out . globalize_label ( asm_out_file , thunk_label ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name ( asm_out_file , thunk_label ) ; putc ( '\n' , asm_out_file ) ; ASM_DECLARE_FUNCTION_NAME ( asm_out_file , thunk_label , decl ) ; } else { switch_to_section ( text_section ) ; ASM_OUTPUT_LABEL ( asm_out_file , thunk_label ) ; } DECL_INITIAL ( decl ) = make_node ( BLOCK ) ; current_function_decl = decl ; allocate_struct_function ( decl , false ) ; init_function_start ( decl ) ; cfun -> is_thunk = true ; first_function_block_is_cold = false ; final_start_function ( emit_barrier ( ) , asm_out_file , <NUM_LIT> ) ; if ( flag_asynchronous_unwind_tables && flag_dwarf2_cfi_asm ) { fputs ( <STR_LIT> , asm_out_file ) ; fprintf ( asm_out_file , <STR_LIT> , regno ) ; for ( i = <NUM_LIT> ; i < FPR15_REGNUM ; i ++ ) fprintf ( asm_out_file , <STR_LIT> , reg_names [ i ] ) ; }


<s> if ( last < <NUM_LIT> ) { warning ( <NUM_LIT> , <STR_LIT> , dash + <NUM_LIT> ) ; return ; } * dash = '-' ; if ( first > last ) { warning ( <NUM_LIT> , <STR_LIT> , str , dash + <NUM_LIT> ) ; return ; } for ( int i = first ; i <= last ; ++ i ) fixed_regs [ i ] = call_used_regs [ i ] = <NUM_LIT> ; if ( ! comma ) break ; * comma = ',' ; str = comma + <NUM_LIT> ; }


<s> case <STR_LIT> : { unsigned Rt = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Rt2 = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rt2 != Rt + <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Rt2 = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rt2 != Rt + <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : case <STR_LIT> : { unsigned lsb = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned widthm1 = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( widthm1 >= <NUM_LIT> - lsb ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : { unsigned Rn = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool hasWritebackToken = ( static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> isToken ( ) && static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) -> getToken ( ) == <STR_LIT> ) ; bool listContainsBase ; if ( checkLowRegisterList ( Inst , <NUM_LIT> , Rn , <NUM_LIT> , listContainsBase ) && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> + hasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( ! listContainsBase && ! hasWritebackToken && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( listContainsBase && hasWritebackToken ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : { if ( listContainsReg ( Inst , <NUM_LIT> , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ;


<s> if ( MBB . succ_size ( ) != <NUM_LIT> ) return false ; const MachineBasicBlock * Succ = * MBB . succ_begin ( ) ;

return ( Succ -> pred_size ( ) == <NUM_LIT> ) && MBB . isLayoutSuccessor ( Succ ) ;


<s> if ( ! SplatVal ) return false ; if ( SplatVal -> getSExtValue ( ) != ( <NUM_LIT> << Scale ) ) return false ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; SDValue Mask = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Mask . getOpcode ( ) != <STR_LIT> ) return false ; SplatVal = dyn_cast < ConstantSDNode > ( Mask . getOperand ( <NUM_LIT> ) ) ; if ( ! SplatVal ) return false ;

if ( SplatVal -> getZExtValue ( ) == <NUM_LIT> ) {


<s> <ISA_LIT>Z80ELFObjectWriter :: <ISA_LIT>Z80ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_NONE , true ) {


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ; return ( Value >= <NUM_LIT> && Value < <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << C << <STR_LIT> << ( IsLegal ? <STR_LIT> : <STR_LIT> ) ) ; return IsLegal ;


<s> } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( isFP64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableMicro<ISA_LIT>FP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Result = readInstruction32 ( Bytes , Address , Size , Insn , IsBigEndian , false ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Size = <NUM_LIT> ; if ( hasCOP3 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCOP3_32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( hasCHERI ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTableCHERI32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( has<ISA_LIT>32r6 ( ) && isGP64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32r6_64r6_GP6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( has<ISA_LIT>32r6 ( ) && isPTR64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32r6_64r6_PTR6432 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( has<ISA_LIT>32r6 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32r6_64r632 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } if ( has<ISA_LIT>2 ( ) && isPTR64 ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;

Result = decodeInstruction ( DecoderTable<ISA_LIT>32_64_PTR6432 , Instr , Insn , Address , this , STI ) ;


<s> static bool isUnalignedMemmoryAccess ( uint64_t MemSize , uint64_t AlignInBits ) { assert ( isPowerOf2_64 ( MemSize ) && <STR_LIT> ) ; assert ( isPowerOf2_64 ( AlignInBits ) && <STR_LIT> ) ;

if ( MemSize > AlignInBits ) return true ;


<s> if ( VT == <STR_LIT> && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'v' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'y' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( Constraint == <STR_LIT> ) { return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } std :: pair < unsigned , const TargetRegisterClass * > R = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;

if ( R . first && VT == <STR_LIT> && <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) && <STR_LIT> . contains ( R . first ) ) {


<s> case <STR_LIT> : SwapVector [ VecIdx ] . IsLoad = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SwapVector [ VecIdx ] . IsLoad = <NUM_LIT> ; SwapVector [ VecIdx ] . IsSwap = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SwapVector [ VecIdx ] . IsLoad = <NUM_LIT> ; SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; break ; case <STR_LIT> : SwapVector [ VecIdx ] . IsStore = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SwapVector [ VecIdx ] . IsStore = <NUM_LIT> ; SwapVector [ VecIdx ] . IsSwap = <NUM_LIT> ; break ; case <STR_LIT> : if ( isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; else if ( isScalarVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isScalarVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; break ; case <STR_LIT> : { if ( isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; else if ( isVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) && isScalarVecReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; SwapVector [ VecIdx ] . SpecialHandling = SHValues :: SH_COPYWIDEN ; } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SwapVector [ VecIdx ] . IsSwappable = <NUM_LIT> ; SwapVector [ VecIdx ] . SpecialHandling = SHValues :: SH_SPLAT ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> SDLoc dl ( Op ) ; auto IsZero = [ ] ( SDValue PassThru ) { return ( <STR_LIT> ( PassThru . getNode ( ) ) || ( PassThru -> getOpcode ( ) == <STR_LIT> && isNullConstant ( PassThru -> getOperand ( <NUM_LIT> ) ) ) ) ; } ; if ( IsZero ( PassThru ) ) return Op ;

SDValue ZeroVec = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> MachineInstr * CPEMI = U . CPEMI ; unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock * NewMBB ; unsigned UserOffset = GetOffsetOf ( UserMI ) + ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; int result = LookForExistingCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; unsigned ID = AFI -> createConstPoolEntryUId ( ) ; if ( ! LookForWater ( U , UserOffset , & NewMBB ) ) { DOUT << <STR_LIT> ; CreateNewWater ( CPUserIndex , UserOffset , & NewMBB ) ; } MachineBasicBlock * NewIsland = MF . CreateMachineBasicBlock ( ) ; MF . insert ( NewMBB , NewIsland ) ;

UpdateForInsertedWaterBlock ( NewIsland ) ;


<s> MachineBasicBlock * LoopHeader = LoopRep -> getHeader ( ) ; MachineBasicBlock * LoopLatch = LoopRep -> getLoopLatch ( ) ; if ( ! LoopHeader || ! LoopLatch ) return nullptr ; MachineInstr * BranchMI = getLoopendBlockBranchInstr ( LoopLatch ) ; if ( ! BranchMI || ! isUncondBranch ( BranchMI ) ) return nullptr ; MachineBasicBlock * DummyExitBlk = FuncRep -> CreateMachineBasicBlock ( ) ; FuncRep -> push_back ( DummyExitBlk ) ; SHOWNEWBLK ( DummyExitBlk , <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * BranchMI << <STR_LIT> ; ) ; LLVMContext & Ctx = LoopHeader -> getParent ( ) -> getFunction ( ) . getContext ( ) ; Ctx . emitError ( <STR_LIT> ) ;


<s> llvm :: sort ( WUsers ) ; WUsers . erase ( std :: unique ( WUsers . begin ( ) , WUsers . end ( ) ) , WUsers . end ( ) ) ; while ( ! WUsers . empty ( ) ) if ( WeakTrackingVH WU = WUsers . pop_back_val ( ) ) { if ( PHINode * PN = dyn_cast < PHINode > ( WU ) ) { for ( int I = <NUM_LIT> , E = PN -> getNumIncomingValues ( ) ; I < E ; ++ I ) if ( PN -> getIncomingValue ( I ) == CE ) { BasicBlock * PredBB = PN -> getIncomingBlock ( I ) ; if ( PredBB -> getTerminator ( ) -> getNumSuccessors ( ) > <NUM_LIT> ) PredBB = SplitEdge ( PredBB , PN -> getParent ( ) ) ;

Instruction * InsertPos = PredBB -> getTerminator ( ) ;


<s> if ( to == CALLER_SAVE_REGS || to == POINTER_REGS ) to = GENERAL_REGS ; if ( from == CALLER_SAVE_REGS || from == POINTER_REGS ) from = GENERAL_REGS ; if ( ( from == GENERAL_REGS && to == STACK_REG ) || ( to == GENERAL_REGS && from == STACK_REG ) ) return regmove_cost -> GP2GP ; if ( to == STACK_REG || from == STACK_REG ) return aarch64_register_move_cost ( mode , from , GENERAL_REGS ) + aarch64_register_move_cost ( mode , GENERAL_REGS , to ) ;

if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> ) {


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( ( getMachineOpValue ( MI , MO , Fixups , STI ) >> <NUM_LIT> ) & <NUM_LIT> ) | RegBits ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ; return RegBits ;


<s> if ( TARGET_64BIT && ix86_abi == MS_ABI ) return false ; return TARGET_FLOAT_RETURNS_IN_80387 ; case XMM0_REG : case XMM1_REG : return TARGET_SSE ; case MM0_REG : if ( TARGET_MACHO || TARGET_64BIT ) return false ; return TARGET_MMX ;


return ( int32x2_t ) __builtin_neon_vreinterpretv2sidi ( __a ) ;


<s> if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = GetCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; unsigned JNCC = GetCondBranchFromCond ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; MBB . addSuccessor ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ; else if ( ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) || ( OldBranchCode == <STR_LIT> && BranchCode == <STR_LIT> ) ) BranchCode = <STR_LIT> ;


<s> if ( ia64_except_unwind_info ( & global_options ) != UI_TARGET ) return ; fputs ( <STR_LIT> , file ) ;


<s> void Warning ( SMLoc L , const Twine & Msg ) { Parser . Warning ( L , Msg ) ;


<s> Set . erase ( front ( ) ) ; Uses . pop ( ) ;


<s> void addMSA128AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getMSA128Reg ( ) ) ) ;


<s> return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) , <NUM_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateImm ( encoding ) ) ;


<s> case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { if ( OpNum == <NUM_LIT> ) NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; else NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; } break ; case <STR_LIT> : isFloat = true ; case <STR_LIT> :


<s> if ( ! ST . hasBulkMemory ( ) ) return SDValue ( ) ; SDValue MemIdx = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; auto LenMVT = ST . hasAddr64 ( ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Chain , MemIdx , MemIdx , Dst , Src , DAG . getZExtOrTrunc ( Size , DL , LenMVT ) } ) ;


<s> bool nds32_valid_CVs2_p ( rtx op ) { HOST_WIDE_INT ival = const_vector_to_hwint ( op ) ; return ( ival < ( <NUM_LIT> << <NUM_LIT> ) ) && ( ival >= - ( <NUM_LIT> << <NUM_LIT> ) ) ;


<s> unsigned getNumFixupKinds ( ) const { return <STR_LIT> ;


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override {

return & InstrInfo . getRegisterInfo ( ) ;


<s> unsigned Directive = static_cast < const <ISA_LIT>Subtarget * > ( STI ) -> getDarwinDirective ( ) ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> ) { const InstrItineraryData * II = static_cast < const <ISA_LIT>Subtarget * > ( STI ) -> getInstrItineraryData ( ) ;

return new ScoreboardHazardRecognizer ( II , DAG ) ;


<s> const static MCFixupKindInfo Infos [ <STR_LIT> ] = {


<s> const uint64_t Mask = * MaskVal ; MachineBasicBlock * BB = I . getParent ( ) ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank * DstRB = RBI . getRegBank ( DstReg , * MRI , TRI ) ; const RegisterBank * SrcRB = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const bool IsVGPR = DstRB -> getID ( ) == <STR_LIT> ; unsigned NewOpc = IsVGPR ? <STR_LIT> : <STR_LIT> ; unsigned MovOpc = IsVGPR ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass & RegRC = IsVGPR ? <STR_LIT> : <STR_LIT> ; LLT Ty = MRI -> getType ( DstReg ) ; const TargetRegisterClass * DstRC = TRI . getRegClassForTypeOnBank ( Ty , * DstRB , * MRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForTypeOnBank ( Ty , * SrcRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) || ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , * MRI ) ) return false ; const DebugLoc & DL = I . getDebugLoc ( ) ; Register ImmReg = MRI -> createVirtualRegister ( & RegRC ) ;

BuildMI ( * BB , & I , DL , TII . get ( MovOpc ) , ImmReg ) . addImm ( Mask ) ;


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> if ( TARGET_64BIT ) { bool lu32i [ <NUM_LIT> ] = { ( value & LU32I_B ) == <NUM_LIT> , ( value & LU32I_B ) == LU32I_B } ; bool lu52i [ <NUM_LIT> ] = { ( value & LU52I_B ) == <NUM_LIT> , ( value & LU52I_B ) == LU52I_B } ; int sign31 = ( value & ( <NUM_LIT> << <NUM_LIT> ) ) >> <NUM_LIT> ; if ( lu32i [ sign31 ] && lu52i [ sign31 ] ) return cost ; else if ( lu32i [ sign31 ] ) { codes [ cost ] . method = METHOD_LU52I ; codes [ cost ] . value = ( value >> <NUM_LIT> ) << <NUM_LIT> ; return cost + <NUM_LIT> ; } codes [ cost ] . method = METHOD_LU32I ; codes [ cost ] . value = ( ( value << <NUM_LIT> ) >> <NUM_LIT> ) << <NUM_LIT> ;


<s> static MCInstrAnalysis * create<ISA_LIT>InstrAnalysis ( const MCInstrInfo * Info ) { return new <ISA_LIT>MCInstrAnalysis ( Info ) ;


<s> <ISA_LIT>ExpandCoreVHwlpPseudo ( ) : MachineFunctionPass ( ID ) {


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( STI . hasBWI ( ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( STI . hasBWI ( ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( isStackAligned ) return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ) ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( STI . is64Bit ( ) ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> : <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; } case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) : ( HasVLX ? <STR_LIT> : HasAVX512 ? <STR_LIT> : <STR_LIT> ) ; case <NUM_LIT> :


<s> if ( I ) { Opcode = I -> getOpcode ( ) ; U = I ; InMBB = I -> getParent ( ) == FuncInfo . MBB -> getBasicBlock ( ) ; } else if ( const ConstantExpr * C = dyn_cast < ConstantExpr > ( V ) ) { Opcode = C -> getOpcode ( ) ; U = C ; } switch ( Opcode ) { default : break ; case Instruction :: BitCast : if ( InMBB ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: IntToPtr : if ( InMBB && TLI . getValueType ( DL , U -> getOperand ( <NUM_LIT> ) -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; case Instruction :: PtrToInt : if ( InMBB && TLI . getValueType ( DL , U -> getType ( ) ) == TLI . getPointerTy ( DL ) ) return <ISA_LIT>SelectCallAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; break ; } if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( V ) ) { if ( TM . getCodeModel ( ) != CodeModel :: Small ) return false ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( AM . Base . Reg != <NUM_LIT> || AM . IndexReg != <NUM_LIT> ) ) return false ; if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ) if ( GVar -> isThreadLocal ( ) ) return false ; AM . GV = GV ; if ( Subtarget -> isPICStyleRIPRel ( ) ) { assert ( AM . Base . Reg == <NUM_LIT> && AM . IndexReg == <NUM_LIT> ) ; AM . Base . Reg = <STR_LIT> ; } else { AM . GVOpFlags = Subtarget -> classifyLocalReference ( nullptr ) ; }


<s> int Offset = MFI -> getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI -> getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; if ( ! noImmForm && isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = is64Bit ? G8RC : GPRC ; unsigned SRegHi = MF . getRegInfo ( ) . createVirtualRegister ( RC ) , SReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SRegHi ) . addImm ( Offset >> <NUM_LIT> ) ;

BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addReg ( SRegHi , RegState :: Kill ) . addImm ( Offset ) ;


<s> CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ;

SDValue Result = DAG . getBlockAddress ( BA , getPointerTy ( ) , true , OpFlags ) ;


<s> return DL . getValueOrABITypeAlignment ( GV -> getPointerAlignment ( DL ) , GV -> getValueType ( ) ) ;


<s> auto MIB = BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( I . getNumMemOperands ( ) ) addMemoryOperands ( * I . memoperands_begin ( ) , MIB ) ;

bool Result = MIB . constrainAllUses ( TII , TRI , RBI ) ;


<s> RxSBGOperands RxSBG [ ] = { RxSBGOperands ( Opcode , N -> getOperand ( <NUM_LIT> ) ) , RxSBGOperands ( Opcode , N -> getOperand ( <NUM_LIT> ) ) } ; unsigned Count [ ] = { <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) while ( expandRxSBG ( RxSBG [ I ] ) ) Count [ I ] += <NUM_LIT> ; if ( Count [ <NUM_LIT> ] == <NUM_LIT> && Count [ <NUM_LIT> ] == <NUM_LIT> ) return <NUM_LIT> ; unsigned I = Count [ <NUM_LIT> ] > Count [ <NUM_LIT> ] ? <NUM_LIT> : <NUM_LIT> ; SDValue Op0 = N -> getOperand ( I ^ <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && ( RxSBG [ I ] . Mask & <NUM_LIT> ) == <NUM_LIT> ) if ( LoadSDNode * Load = dyn_cast < LoadSDNode > ( Op0 . getNode ( ) ) ) if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return <NUM_LIT> ; if ( Opcode == <STR_LIT> && detectOrAndInsertion ( Op0 , RxSBG [ I ] . Mask ) ) Opcode = <STR_LIT> ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { convertTo ( SDLoc ( N ) , <STR_LIT> , Op0 ) , convertTo ( SDLoc ( N ) , <STR_LIT> , RxSBG [ I ] . Input ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Start , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . End , <STR_LIT> ) , CurDAG -> getTargetConstant ( RxSBG [ I ] . Rotate , <STR_LIT> ) } ; N = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , <STR_LIT> , Ops ) ;

return convertTo ( SDLoc ( N ) , VT , SDValue ( N , <NUM_LIT> ) ) . getNode ( ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU ) { const uint8_t ABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new ELF<ISA_LIT>AsmBackend ( T , TT . getTriple ( ) , ABI ) ;


<s> inline hashval_t bundle_state_hasher :: hash ( const value_type * state ) { unsigned result , i ; for ( result = i = <NUM_LIT> ; i < dfa_state_size ; i ++ ) result += ( ( ( unsigned char * ) state -> dfa_state ) [ i ] << ( ( i % CHAR_BIT ) * <NUM_LIT> + CHAR_BIT ) ) ;


<s> while ( insn != BB_HEAD ( bb ) && ! NONDEBUG_INSN_P ( insn ) ) insn = PREV_INSN ( insn ) ; if ( insn == BB_HEAD ( bb ) || INSN_CODE ( insn ) != CODE_FOR_cbranchsi4_insn ) continue ; cmp = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; op0 = XEXP ( cmp , <NUM_LIT> ) ; op1 = XEXP ( cmp , <NUM_LIT> ) ; if ( ! CONST_INT_P ( op1 ) || INTVAL ( op1 ) != <NUM_LIT> ) continue ; gcc_assert ( insn != BB_HEAD ( bb ) ) ; for ( prev = PREV_INSN ( insn ) ; ( ! insn_clobbered && prev != BB_HEAD ( bb ) && ( NOTE_P ( prev ) || DEBUG_INSN_P ( prev ) || ( ( set = single_set ( prev ) ) != NULL && get_attr_conds ( prev ) == CONDS_NOCOND ) ) ) ; prev = PREV_INSN ( prev ) ) { if ( reg_set_p ( op0 , prev ) ) insn_clobbered = true ; }


if ( ! JUMP_P ( insn ) || recog_memoized ( insn ) != CODE_FOR_loop_end ) return NULL_RTX ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( <ISA_LIT>MachineFunction * MFI , SDValue Op , SelectionDAG & DAG ) const { const DataLayout & DL = DAG . getDataLayout ( ) ; GlobalAddressSDNode * G = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = G -> getGlobal ( ) ; if ( G -> getAddressSpace ( ) == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS ) { assert ( G -> getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! hasDefinedInitializer ( GV ) ) { unsigned Offset = MFI -> allocateLDSGlobal ( DL , * GV ) ; return DAG . getConstant ( Offset , SDLoc ( Op ) , Op . getValueType ( ) ) ; } } const Function & Fn = DAG . getMachineFunction ( ) . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , SDLoc ( Op ) . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadInit ) ; return SDValue ( ) ;


<s> incoming_address = gen_rtx_REG ( Pmode , PIC_FUNCTION_ADDR_REGNUM ) ; emit_insn ( gen_loadgp ( offset , incoming_address ) ) ; if ( ! TARGET_EXPLICIT_RELOCS ) emit_insn ( gen_loadgp_blockage ( ) ) ;


<s> assert ( isUInt < <NUM_LIT> > ( Imm ) && <STR_LIT> ) ; auto Imm5 = Imm & <NUM_LIT> ; auto Ry = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; if ( DecodeFPR32RegisterClass ( Inst , Ry , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( FPR32DecoderTable [ Ry + Imm5 ] ) ) ;


<s> rtx insn_set ; rtx dep_set ; int timings ; if ( ! TARGET_AM33 ) return <NUM_LIT> ; insn_set = single_set ( insn ) ; if ( ! insn_set ) return cost ; dep_set = single_set ( dep ) ; if ( ! dep_set ) return cost ; if ( mn10300_tune_cpu == PROCESSOR_AM34 && set_is_load_p ( dep_set ) && set_is_store_p ( insn_set ) ) cost += <NUM_LIT> ; else if ( mn10300_tune_cpu == PROCESSOR_AM34 && ! set_is_store_p ( insn_set ) && ! JUMP_P ( insn ) && GET_MODE_CLASS ( GET_MODE ( SET_SRC ( dep_set ) ) ) == MODE_FLOAT && GET_MODE_CLASS ( GET_MODE ( SET_SRC ( insn_set ) ) ) == MODE_FLOAT ) cost += <NUM_LIT> ;


<s> static void EraseBBsAndChildren ( const Container & MBBs ) { SmallVector < MachineBasicBlock * , <NUM_LIT> > WL ( MBBs . begin ( ) , MBBs . end ( ) ) ; while ( ! WL . empty ( ) ) { MachineBasicBlock * MBB = WL . pop_back_val ( ) ; SmallVector < MachineBasicBlock * , <NUM_LIT> > Preds ( MBB -> pred_begin ( ) , MBB -> pred_end ( ) ) ; for ( auto * Pred : Preds ) Pred -> removeSuccessor ( MBB ) ;

SmallVector < MachineBasicBlock * , <NUM_LIT> > Succs ( MBB -> succ_begin ( ) , MBB -> succ_end ( ) ) ;


<s> Type * GCNTTIImpl :: getMemcpyLoopLoweringType ( LLVMContext & Context , Value * Length , unsigned SrcAddrSpace , unsigned DestAddrSpace , unsigned SrcAlign , unsigned DestAlign ) const { unsigned MinAlign = std :: min ( SrcAlign , DestAlign ) ; if ( MinAlign == <NUM_LIT> ) return Type :: getInt16Ty ( Context ) ; if ( SrcAddrSpace == <ISA_LIT>AS :: LOCAL_ADDRESS || SrcAddrSpace == <ISA_LIT>AS :: REGION_ADDRESS || DestAddrSpace == <ISA_LIT>AS :: LOCAL_ADDRESS || DestAddrSpace == <ISA_LIT>AS :: REGION_ADDRESS ) { return FixedVectorType :: get ( Type :: getInt32Ty ( Context ) , <NUM_LIT> ) ; }


<s> if ( MI == MBB . end ( ) ) continue ; int newOpcode = reverseOpcode ( MI -> getOpcode ( ) ) ; if ( newOpcode == <STR_LIT> ) continue ; BuildMI ( MBB , MI , MBB . findDebugLoc ( MI ) , TII -> get ( newOpcode ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; MI -> eraseFromParent ( ) ;


<s> <ISA_LIT>TargetMachine64 :: <ISA_LIT>TargetMachine64 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> Diagnostic += <STR_LIT> + std :: to_string ( Min ) + <STR_LIT> + std :: to_string ( Max ) + <STR_LIT> ; if ( Ctx ) { Ctx -> reportFatalError ( Fixup . getLoc ( ) , Diagnostic ) ; } else { llvm_unreachable ( Diagnostic . c_str ( ) ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ;

for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) {


<s> if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) || ( Reg == ExcludedReg ) ) return ;

if ( MO . isDef ( ) ) RegDefs . insert ( Reg ) ;


<s> InstSeq generateInstSeq ( int64_t Val , bool IsRV64 ) { <STR_LIT> Res ; generateInstSeqImpl ( Val , IsRV64 , Res ) ; if ( Val > <NUM_LIT> && Res . size ( ) > <NUM_LIT> ) { assert ( IsRV64 && <STR_LIT> ) ; unsigned ShiftAmount = countLeadingZeros ( ( uint64_t ) Val ) ; Val <<= ShiftAmount ; Val |= maskTrailingOnes < uint64_t > ( ShiftAmount ) ; <STR_LIT> TmpSeq ; generateInstSeqImpl ( Val , IsRV64 , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , ShiftAmount ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; Val &= maskTrailingZeros < uint64_t > ( ShiftAmount ) ; TmpSeq . clear ( ) ; generateInstSeqImpl ( Val , IsRV64 , TmpSeq ) ; TmpSeq . push_back ( <STR_LIT> ( <STR_LIT> , ShiftAmount ) ) ; if ( TmpSeq . size ( ) < Res . size ( ) ) Res = TmpSeq ; } return Res ;


<s> static DecodeStatus decodeOperand_SReg_32 ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler * Decoder ) {

auto DAsm = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ;


<s> static DecodeStatus DecodeFGRCCRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ;

Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ;


<s> llvm :: RegisterTarget < llvm :: Triple :: mos > X ( llvm :: getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val == std :: numeric_limits < int32_t > :: min ( ) ) || ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) ;


<s> else while ( expandAddress ( AM , true ) || ( AM . Index . getNode ( ) && expandAddress ( AM , false ) ) ) continue ; if ( AM . Form == <STR_LIT> && ! shouldUseLA ( AM . Base . getNode ( ) , AM . Disp , AM . Index . getNode ( ) ) ) return false ; if ( ! isValidDisp ( AM . DR , AM . Disp ) ) return false ; if ( AM . isDynAlloc ( ) && ! AM . IncludesDynAlloc ) return false ;


<s> case OPWV232 : return TTMP_64RegClassID ; case OPW128 : return TTMP_128RegClassID ; case OPW256 : return TTMP_256RegClassID ; case OPW512 : return TTMP_512RegClassID ; }


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != Idx ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != Idx ) ) return false ; Idx += <NUM_LIT> ; } }

if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ;


<s> if ( ! MBB . getBasicBlock ( ) ) return false ; VectorNode . push_back ( createNode ( & MBB ) ) ; } if ( ! isValidModel ) return false ; <ISA_LIT>_DEBUG ( <STR_LIT> + to_string ( VectorNode . size ( ) ) + <STR_LIT> ) ; <ISA_LIT>_DEBUG ( <STR_LIT> ) ; <ISA_LIT>_DEBUG ( <STR_LIT> ) ; for ( auto & MBB : * MF ) { if ( ! MBB . getBasicBlock ( ) ) return false ; <ISA_LIT>_DEBUG ( <STR_LIT> + to_string ( MBB . getNumber ( ) ) + <STR_LIT> ) ; vector < CostLeaf * > val = * VectorNode [ MBB . getNumber ( ) ] -> getChildren ( ) ; for ( auto child : MBB . successors ( ) ) { if ( ! child -> getBasicBlock ( ) ) continue ; <ISA_LIT>_DEBUG ( <STR_LIT> + to_string ( child -> getNumber ( ) ) + <STR_LIT> ) ; if ( std :: find ( val . begin ( ) , val . end ( ) , VectorNode [ child -> getNumber ( ) ] ) == val . end ( ) ) VectorNode [ MBB . getNumber ( ) ] -> pushChild ( VectorNode [ child -> getNumber ( ) ] ) ; } } <ISA_LIT>_DEBUG ( <STR_LIT> ) ; <ISA_LIT>_DEBUG ( <STR_LIT> ) ; for ( auto & Node : VectorNode ) { if ( Node -> getType ( ) == nodeType :: LOOP ) { <ISA_LIT>_DEBUG ( <STR_LIT> + to_string ( Node -> getMachinBB ( ) -> getNumber ( ) ) + <STR_LIT> ) ; Loop * Lp = LI . getLoopFor ( Node -> getMachinBB ( ) -> getBasicBlock ( ) ) ; SmallVector < BasicBlock * , <NUM_LIT> > Latches ; SmallVector < BasicBlock * , <NUM_LIT> > Exits ; Lp -> getLoopLatches ( Latches ) ; BasicBlock * Latch = Latches [ <NUM_LIT> ] ; Lp -> getExitBlocks ( Exits ) ; BasicBlock * Exit = Exits [ <NUM_LIT> ] ; if ( ! Exit || ! Latch ) assert ( <NUM_LIT> && <STR_LIT> ) ; for ( auto & Node1 : VectorNode ) { if ( Node1 -> getType ( ) == nodeType :: NODE || Node1 -> getType ( ) == nodeType :: SWITCH_BRANCH ) { if ( Node1 -> getBasicBlock ( ) == Exit ) { Node1 -> setType ( nodeType :: EXIT ) ; <ISA_LIT>_DEBUG ( <STR_LIT> + to_string ( Node1 -> getMachinBB ( ) -> getNumber ( ) ) + <STR_LIT> ) ;


<s> poly_int64 xstormy16_push_rounding ( poly_int64 bytes ) { return ( bytes + <NUM_LIT> ) & ~ <NUM_LIT> ;


<s> return ( REG_P ( x ) && ( strict ? REG_OK_FOR_BASE_STRICT_P ( x ) : REG_OK_FOR_BASE_NONSTRICT_P ( x ) ) ) ;


<s> for ( MachineOperand & Use : MI . operands ( ) ) {

if ( Use . isReg ( ) && ( ( Use . readsReg ( ) && RegDefs . count ( Use . getReg ( ) ) ) || ( Use . isDef ( ) && RegDefs . count ( Use . getReg ( ) ) ) || ( Use . isDef ( ) && TargetRegisterInfo :: isPhysicalRegister ( Use . getReg ( ) ) && PhysRegUses . count ( Use . getReg ( ) ) ) ) ) {


static const std :: pair < unsigned , const char * > TargetFlags [ ] = {


<s> bool Changed = false ; for ( auto & MF : M ) { Changed |= runOnFunction ( MF ) ;


<s> SDValue SplattedVal = splatSplitI64WithVL ( DL , VT , Scalar , VL , DAG ) ; SDValue SplattedIdx = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , VL ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , MaskVT , VL ) ; SDValue VID = DAG . getNode ( <STR_LIT> , DL , VT , Mask , VL ) ; SDValue SelectCond = DAG . getNode ( <STR_LIT> , DL , MaskVT , VID , SplattedIdx , DAG . getCondCode ( <STR_LIT> ) , Mask , VL ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectCond , SplattedVal , Vec , VL ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned NumOps = Op . getNumOperands ( ) ; bool IsMasked = NumOps == <NUM_LIT> ; unsigned OpOffset = IsMasked ? <NUM_LIT> : <NUM_LIT> ; SDValue Scalar = Op . getOperand ( <NUM_LIT> + OpOffset ) ; if ( Scalar . getValueType ( ) . bitsLE ( XLenVT ) ) break ; if ( auto * CVal = dyn_cast < ConstantSDNode > ( Scalar ) ) if ( isInt < <NUM_LIT> > ( CVal -> getSExtValue ( ) ) ) break ; MVT VT = Op . getSimpleValueType ( ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> && Scalar . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT I32VT = <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) * <NUM_LIT> ) ; SDValue Vec = DAG . getBitcast ( I32VT , Op . getOperand ( <NUM_LIT> + OpOffset ) ) ; SDValue ScalarLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue ScalarHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Scalar , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue VL = Op . getOperand ( NumOps - <NUM_LIT> ) ; SDValue I32VL = DAG . getNode ( <STR_LIT> , DL , XLenVT , VL , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; MVT I32MaskVT = <STR_LIT> ( <STR_LIT> , I32VT . getVectorElementCount ( ) ) ; SDValue I32Mask = DAG . getNode ( <STR_LIT> , DL , I32MaskVT , VL ) ; if ( IntNo == <STR_LIT> || IntNo == <STR_LIT> ) {

Vec = DAG . getNode ( <STR_LIT> , DL , I32VT , Vec , ScalarHi , I32Mask , I32VL ) ;


<s> PostOptimizer ( Relooper * ParentInit ) : Parent ( ParentInit ) {


<s> return ; } MachineBasicBlock :: const_instr_iterator I = MI -> getIterator ( ) ; MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ;

Lower<ISA_LIT>MachineInstrToMCInst ( & * I , TmpInst , * this ) ;


<s> BasicBlock * Latch = L -> getLoopLatch ( ) ; for ( Instruction & I : reverse ( * Latch ) ) { if ( I . getOpcode ( ) != Instruction :: Add ) continue ; if ( AllAdds . count ( & I ) ) continue ; const auto * Ty = I . getType ( ) ; if ( ! Ty -> isIntegerTy ( <NUM_LIT> ) && ! Ty -> isIntegerTy ( <NUM_LIT> ) ) continue ; Reduction R ( & I ) ; if ( ! Search ( & I , R ) ) continue ; if ( ! CreateParallelPairs ( R ) ) continue ; InsertParallelMACs ( R ) ; Changed = true ; AllAdds . insert ( R . getAdds ( ) . begin ( ) , R . getAdds ( ) . end ( ) ) ; }


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ;

if ( Size != <NUM_LIT> || isOpSuitableForLDPSTP ( LI ) ) return AtomicExpansionKind :: None ;


<s> bool isu9_0Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false , false ) ;


<s> case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; case <STR_LIT> : return LowerReductionToSVE ( <STR_LIT> , Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ; } } SDLoc dl ( Op ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return getReductionSDNode ( <STR_LIT> , dl , Op , DAG ) ; case <STR_LIT> : return getReductionSDNode ( <STR_LIT> , dl , Op , DAG ) ; case <STR_LIT> : return getReductionSDNode ( <STR_LIT> , dl , Op , DAG ) ; case <STR_LIT> : return getReductionSDNode ( <STR_LIT> , dl , Op , DAG ) ; case <STR_LIT> : return getReductionSDNode ( <STR_LIT> , dl , Op , DAG ) ; case <STR_LIT> : { return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Src ) ; } case <STR_LIT> : { return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Src ) ; }


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHSaveXMM ( SMLoc Loc ) { unsigned Reg = <NUM_LIT> ; int64_t Off ; if ( parseSEHRegisterNumber ( <STR_LIT> , Reg ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; getParser ( ) . Lex ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( Off ) ) return true ;

if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : return false ; default : break ; } } const auto checkNoAlias = [ this , Load ] ( auto I ) -> bool { return I && AA -> isNoAlias ( I -> getPointerOperand ( ) , Load -> getPointerOperand ( ) ) ; } ; if ( checkNoAlias ( dyn_cast < AtomicCmpXchgInst > ( DefInst ) ) || checkNoAlias ( dyn_cast < AtomicRMWInst > ( DefInst ) ) ) return false ; return true ; } ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Load << '\n' ) ; while ( ! WorkList . empty ( ) ) { MemoryAccess * MA = WorkList . pop_back_val ( ) ;

if ( ! Visited . insert ( MA ) . second ) continue ;


<s> if ( Idx != ( unsigned ) Invert ) Cond = invert ( Cond ) ; } return Cond ;


<s> return _inet_lnaof ( in << SHIFT_BITS ) ;


<s> else { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; } else { fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ; fputs ( <STR_LIT> , f ) ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> <ISA_LIT>AsmBackendDarwin ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , MachO :: CPUSubType<ISA_LIT> st ) : <ISA_LIT>AsmBackend ( T , STI , <STR_LIT> ) , MRI ( MRI ) , Subtype ( st ) {


<s> return ( uint32x2_t ) __builtin_neon_vcgtv2sf ( __b , __a ) ;


<s> unsigned TZ = countTrailingZeros ( ITState . Mask ) ; if ( ++ ITState . CurPosition == <NUM_LIT> - TZ ) ITState . CurPosition = ~ <NUM_LIT> ;


<s> LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : printImmediateV216 ( Op . getImm ( ) , STI , O ) ; break ; case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_PCREL : O << formatDec ( Op . getImm ( ) ) ; break ; case MCOI :: OPERAND_REGISTER : O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; unsigned RCBits = <STR_LIT> ( MRI . getRegClass ( RCID ) ) ; if ( RCBits == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , STI , O ) ; else if ( RCBits == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , STI , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else { O << <STR_LIT> ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


return __builtin_aarch64_lfloorhfdi ( __a ) ;


<s> bool <ISA_LIT>TargetLowering :: NeedToConvertToMemOp ( SDValue Op , unsigned & MemOp ) { if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; if ( isDirectLoad ( Op . getOperand ( <NUM_LIT> ) ) ) { if ( Op . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) return false ; else MemOp = <NUM_LIT> ; } if ( isDirectLoad ( Op . getOperand ( <NUM_LIT> ) ) ) {


<s> if ( ( * o ) -> isStore ( ) && ( * o ) -> getValue ( ) ) if ( const FixedStackPseudoSourceValue * Value = dyn_cast < const FixedStackPseudoSourceValue > ( ( * o ) -> getValue ( ) ) ) { FrameIndex = Value -> getFrameIndex ( ) ; MMO = * o ; return true ; } }


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( Reg ) ; if ( <STR_LIT> -> contains ( Reg ) ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( TFI -> hasFP ( * MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getFrameRegister ( * MF ) ) ) ; if ( MFI -> adjustsStack ( ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getRARegister ( ) ) ) ;

OutStreamer . EmitRawText ( <STR_LIT> + Twine :: utohexstr ( CPUBitmask ) ) ;


<s> SDValue getI32Imm ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , <STR_LIT> ) ;


<s> CodeGenOpt :: Level OptLevel = getTargetMachine ( ) . getOptLevel ( ) ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : return PerformADDCombine ( N , DCI , STI , OptLevel ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformSHLCombine ( N , DCI , OptLevel ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : return PerformREMCombine ( N , DCI , OptLevel ) ;


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) {


<s> if ( b < <NUM_LIT> ) b = - b ; res = udivmodsi4 ( a , b , <NUM_LIT> ) ; if ( neg ) res = - res ; return res ;


<s> function_checker :: function_checker ( location_t location , const function_instance & instance , tree fndecl , tree fntype , unsigned int nargs , tree * args ) : function_call_info ( location , instance , fndecl ) , m_fntype ( fntype ) , m_nargs ( nargs ) , m_args ( args ) , m_base_arg ( pred != PRED_none ? <NUM_LIT> : <NUM_LIT> ) {


<s> tmp = * ( _Unwind_Word * ) ptr ; if ( ! tmp ) return <NUM_LIT> ; tmp += ptr ; tmp = * ( _Unwind_Word * ) tmp ; tmp += ptr ; return tmp ;


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; const MCExpr * ShiftAmount ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( ShiftAmount ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ShiftAmount ) ; if ( ! CE ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int64_t Val = CE -> getValue ( ) ; if ( Val != <NUM_LIT> && Val != <NUM_LIT> && Val != <NUM_LIT> && Val != <NUM_LIT> ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } E = Parser . getTok ( ) . getLoc ( ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreateRotImm ( Val , S , E ) ) ;


<s> case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return <ISA_LIT>SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return <ISA_LIT>SelectDivRem ( I ) ; case Instruction :: Select : return <ISA_LIT>SelectSelect ( I ) ; case Instruction :: Trunc : return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return <ISA_LIT>SelectSIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( DL , I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( DL , I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ;

if ( DstVT . bitsLT ( SrcVT ) ) return <ISA_LIT>SelectTrunc ( I ) ;


( out_mode == N ## Imode && out_n == C \ && in_mode == N ## Imode && in_n == C ) if ( AARCH64_CHECK_BUILTIN_MODE ( <NUM_LIT> , H ) ) return aarch64_builtin_decls [ AARCH64_SIMD_BUILTIN_UNOPU_bswapv4hi ] ;


<ISA_LIT>ConstantPoolValue :: print ( O ) ;


<s> break ; default : { if ( InCPMode && AFI -> isThumbFunction ( ) ) InCPMode = false ; } }


<s> MIRBuilder . getMRI ( ) -> addLiveIn ( PhysReg ) ; MIRBuilder . getMBB ( ) . addLiveIn ( PhysReg ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSPE4DisEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { assert ( MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) ; uint32_t RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( MO . isImm ( ) ) ; uint32_t Imm = getMachineOpValue ( MI , MO , Fixups , STI ) >> <NUM_LIT> ;

return reverseBits ( Imm | RegBits ) >> <NUM_LIT> ;


<s> static DecodeStatus DecodeQTripleRegisterClass ( llvm :: MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) {

return DecodeRegisterClassByID ( Inst , RegNo , <STR_LIT> , Decoder ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIdx ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg ) . addFrameIndex ( FrameIdx ) . addMemOperand ( MMO ) ; else llvm_unreachable ( <STR_LIT> ) ;


<s> break ; case FK_Data_8 : case <STR_LIT> : FullSize = <NUM_LIT> ; break ; case FK_Data_4 : default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; bool micro<ISA_LIT>LEByteOrder = needsMMLEByteOrder ( ( unsigned ) Kind ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( micro<ISA_LIT>LEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittle ? ( micro<ISA_LIT>LEByteOrder ? calculateMMLEIndex ( i ) : i ) : ( FullSize - <NUM_LIT> - i ) ; Data [ Offset + Idx ] = ( uint8_t ) ( ( CurVal >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> unsigned ValSize = ValTy . getSizeInBits ( ) ; const RegisterBank * VecRB = RBI . getRegBank ( VecReg , * MRI , TRI ) ; const RegisterBank * ValRB = RBI . getRegBank ( ValReg , * MRI , TRI ) ; const RegisterBank * IdxRB = RBI . getRegBank ( IdxReg , * MRI , TRI ) ; assert ( VecTy . getElementType ( ) == ValTy ) ; if ( IdxRB -> getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * VecRC = TRI . getRegClassForTypeOnBank ( VecTy , * VecRB ) ; const TargetRegisterClass * ValRC = TRI . getRegClassForTypeOnBank ( ValTy , * ValRB ) ; if ( ! RBI . constrainGenericRegister ( VecReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( ValReg , * ValRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; if ( VecRB -> getID ( ) == <STR_LIT> && ValSize != <NUM_LIT> ) return false ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , VecRC , IdxReg , ValSize / <NUM_LIT> ) ; const bool IndexMode = VecRB -> getID ( ) == <STR_LIT> && STI . useVGPRIndexMode ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( ! IndexMode ) { BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ; const MCInstrDesc & RegWriteOp = TII . getIndirectRegWriteMovRelPseudo ( VecSize , ValSize , VecRB -> getID ( ) == <STR_LIT> ) ; BuildMI ( * BB , MI , DL , RegWriteOp , DstReg ) . addReg ( VecReg ) . addReg ( ValReg ) . addImm ( SubReg ) ; MI . eraseFromParent ( ) ; return true ; } const MCInstrDesc & GPRIDXDesc = TII . getIndirectGPRIDXPseudo ( TRI . getRegSizeInBits ( * VecRC ) , false ) ; BuildMI ( * BB , MI , DL , GPRIDXDesc , DstReg ) . addReg ( VecReg ) . addReg ( ValReg ) . addReg ( IdxReg ) . addImm ( SubReg ) ;


<s> int arg_offset = <NUM_LIT> ; if ( base -> use_mask_predication_p ( ) ) { if ( use_real_mask_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_all_one_mask_operand ( mask_mode ( ) ) ; } if ( ! function_returns_void_p ( ) && base -> has_merge_operand_p ( ) ) { if ( use_real_merge_p ( pred ) ) add_input_operand ( arg_offset ++ ) ; else add_vundef_operand ( mode ) ; } for ( int argno = arg_offset ; argno < call_expr_nargs ( exp ) ; argno ++ ) add_input_operand ( argno ) ; if ( base -> apply_tail_policy_p ( ) ) add_input_operand ( Pmode , get_tail_policy_for_pred ( pred ) ) ;

if ( base -> apply_mask_policy_p ( ) ) add_input_operand ( Pmode , get_mask_policy_for_pred ( pred ) ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext & ctx , bool IsLittle ) : MCII ( mcii ) , STI ( sti ) , Ctx ( ctx ) , IsLittleEndian ( IsLittle ) {


<s> if ( ! featureBits [ <STR_LIT> ] && ! featureBits [ <STR_LIT> ] ) return MCDisassembler :: Fail ; } DecodeStatus S = MCDisassembler :: Success ; if ( unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG ( Inst . getOpcode ( ) ) ) Inst . addOperand ( MCOperand :: createReg ( Sysreg ) ) ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned addr = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) | ( fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) | ( Rn << <NUM_LIT> ) ; if ( Writeback ) { if ( ! Check ( S , DecodeGPRnopcRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeT2AddrModeImm7s4 ( Inst , addr , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> return false ; } if ( ! isABI_O32 ( ) ) { reportParseError ( <STR_LIT> + Directive + <STR_LIT> ) ; return false ; } FpABI = <STR_LIT> :: XX ; return true ; } if ( Lexer . is ( AsmToken :: Integer ) ) { unsigned Value = Parser . getTok ( ) . getIntVal ( ) ; Parser . Lex ( ) ; if ( Value != <NUM_LIT> && Value != <NUM_LIT> ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Value == <NUM_LIT> ) { if ( ! isABI_O32 ( ) ) { reportParseError ( <STR_LIT> + Directive + <STR_LIT> ) ; return false ; } FpABI = <STR_LIT> :: S32 ; } else FpABI = <STR_LIT> :: S64 ; return true ;


<s> bool isIntDivCheap ( EVT VT , AttributeList Attr ) const override { return true ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ;


<s> if ( SuccID == S -> getID ( ) ) return ; } if ( Succ -> isHighLatencyBlock ( ) ) ++ NumHighLatencySuccessors ; Succs . push_back ( Succ ) ; for ( <ISA_LIT>ScheduleBlock * P : Preds ) { if ( SuccID == P -> getID ( ) ) assert ( <STR_LIT> ) ; }


<s> llvm_unreachable ( <STR_LIT> ) ; } int count = <NUM_LIT> ; for ( int i = MI . getNumOperands ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) count += RegSize ;


<s> if ( UseSoftFloat || ( VT != <STR_LIT> && VT != <STR_LIT> ) ) return false ;

return Imm . isZero ( ) || Imm . isNegZero ( ) ;


<s> return VT1 == <STR_LIT> && VT2 == <STR_LIT> && Subtarget . is64Bit ( ) ;


<s> TargetJITInfo :: LazyResolverFn <ISA_LIT>JITInfo :: getLazyResolverFunction ( JITCompilerFn F ) {


<s> unsigned char MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; bool useSubstituteMnemonic = false ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; useSubstituteMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( useSubstituteMnemonic ) { printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; printAnnotation ( O , Annot ) ; return ; } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( <NUM_LIT> - SH == ME ) { O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> << ( unsigned int ) SH ; printAnnotation ( O , Annot ) ; return ; } } if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { unsigned char TH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; O << <STR_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) O << <STR_LIT> ; if ( TH == <NUM_LIT> ) O << <STR_LIT> ; O << <STR_LIT> ; bool IsBookE = STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( IsBookE && TH != <NUM_LIT> && TH != <NUM_LIT> ) O << ( unsigned int ) TH << <STR_LIT> ; printOperand ( MI , <NUM_LIT> , O ) ;


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2v4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int16x4_t ) __builtin_aarch64_get_dregoiv4hi ( __o , <NUM_LIT> ) ; return ret ;


<s> static int mips_binary_cost ( rtx x , int single_cost , int double_cost , bool speed ) { int cost ; if ( GET_MODE_SIZE ( GET_MODE ( x ) ) == UNITS_PER_WORD * <NUM_LIT> ) cost = double_cost ; else cost = single_cost ;

return ( cost + set_src_cost ( XEXP ( x , <NUM_LIT> ) , speed ) + rtx_cost ( XEXP ( x , <NUM_LIT> ) , GET_CODE ( x ) , <NUM_LIT> , speed ) ) ;


<s> static unsigned getIntelMemOperandSize ( StringRef OpStr ) { unsigned Size = StringSwitch < unsigned > ( OpStr ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , <NUM_LIT> ) . Cases ( <STR_LIT> , <STR_LIT> , - <NUM_LIT> ) . Default ( <NUM_LIT> ) ;


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; bool Done = rewrite<ISA_LIT>FrameIndex ( MI , i , BaseReg , Off , TII ) ;


<s> else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ;

else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ;


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ;

InitializeELF ( TM . Options . UseInitArray ) ;


<s> HasConstElts = true ; } if ( SplatIdx < <NUM_LIT> ) SplatIdx = idx ; else if ( In != Op . getOperand ( SplatIdx ) ) IsSplat = false ; } if ( IsSplat ) { SDValue Cond = Op . getOperand ( SplatIdx ) ; assert ( Cond . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Cond . getOpcode ( ) != <STR_LIT> ) Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( VT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { SDValue Select = DAG . getSelect ( dl , <STR_LIT> , Cond , DAG . getAllOnesConstant ( dl , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Select = DAG . getBitcast ( <STR_LIT> , Select ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Select , Select ) ; } else { MVT ImmVT = <STR_LIT> ( std :: max ( ( unsigned ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; SDValue Select = DAG . getSelect ( dl , ImmVT , Cond , DAG . getAllOnesConstant ( dl , ImmVT ) , DAG . getConstant ( <NUM_LIT> , dl , ImmVT ) ) ; MVT VecVT = VT . getSizeInBits ( ) >= <NUM_LIT> ? VT : <STR_LIT> ; Select = DAG . getBitcast ( VecVT , Select ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Select , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } } SDValue DstVec ; if ( HasConstElts ) { if ( VT == <STR_LIT> && ! Subtarget . is64Bit ( ) ) { SDValue ImmL = DAG . getConstant ( Lo_32 ( Immediate ) , dl , <STR_LIT> ) ; SDValue ImmH = DAG . getConstant ( Hi_32 ( Immediate ) , dl , <STR_LIT> ) ; ImmL = DAG . getBitcast ( <STR_LIT> , ImmL ) ; ImmH = DAG . getBitcast ( <STR_LIT> , ImmH ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ImmL , ImmH ) ; } else { MVT ImmVT = <STR_LIT> ( std :: max ( ( unsigned ) VT . getSizeInBits ( ) , <NUM_LIT> ) ) ; SDValue Imm = DAG . getConstant ( Immediate , dl , ImmVT ) ; MVT VecVT = VT . getSizeInBits ( ) >= <NUM_LIT> ? VT : <STR_LIT> ; DstVec = DAG . getBitcast ( VecVT , Imm ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , VT , DstVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } } else DstVec = DAG . getUNDEF ( VT ) ; for ( unsigned i = <NUM_LIT> , e = NonConstIdx . size ( ) ; i != e ; ++ i ) {

unsigned InsertIdx = NonConstIdx [ i ] ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;

if ( ! Subtarget . isSingleFloat ( ) ) for ( unsigned FReg = ( <STR_LIT> ) + <NUM_LIT> ; FReg < <STR_LIT> ; FReg += <NUM_LIT> ) Reserved . set ( FReg ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const Triple & TT ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TT ( TT ) { <ISA_LIT>_MC :: initLLVMToCVRegMapping ( this ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PointerType * PtrTy = cast < PointerType > ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( PtrTy -> getElementType ( ) ) ;

Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ;


<s> ix86_builtins [ ( int ) code ] = decl ; ix86_builtins_isa [ ( int ) code ] . set_and_not_built_p = false ; } else { deferred_isa_values2 |= mask ; ix86_builtins [ ( int ) code ] = NULL_TREE ; ix86_builtins_isa [ ( int ) code ] . tcode = tcode ; ix86_builtins_isa [ ( int ) code ] . name = name ; ix86_builtins_isa [ ( int ) code ] . leaf_p = false ;

ix86_builtins_isa [ ( int ) code ] . nothrow_p = false ;


<s> assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else { SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; } assert ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_None ) ; OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) OS << '+' ;


<s> OperandMatchResultTy Res ; if ( AllowImm ) { Res = parseRegOrImm ( Operands , SP3Abs ) ; } else { Res = parseReg ( Operands ) ; } if ( Res != MatchOperand_Success ) { return ( SP3Neg || Neg || SP3Abs || Abs ) ? MatchOperand_ParseFail : Res ; } if ( SP3Abs && ! skipToken ( AsmToken :: Pipe , <STR_LIT> ) ) return MatchOperand_ParseFail ; if ( Abs && ! skipToken ( AsmToken :: RParen , <STR_LIT> ) ) return MatchOperand_ParseFail ; if ( Neg && ! skipToken ( AsmToken :: RParen , <STR_LIT> ) ) return MatchOperand_ParseFail ; <ISA_LIT>Operand :: Modifiers Mods ;


<s> if ( GVA -> hasLocalLinkage ( ) ) return false ; if ( ( ( GVA -> hasExternalLinkage ( ) && GVA -> isDeclaration ( ) ) || GVA -> hasCommonLinkage ( ) ) ) return false ; Type * Ty = GVA -> getValueType ( ) ; return isInSmallSection ( GVA -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( Ty ) ) ;


<s> unsigned SuperReg = AMDGPU :: R600_Reg128RegClass . getRegister ( Index ) ; Reserved . set ( SuperReg ) ; for ( unsigned Chan = <NUM_LIT> ; Chan < StackWidth ; ++ Chan ) { unsigned Reg = AMDGPU :: R600_TReg32RegClass . getRegister ( ( <NUM_LIT> * Index ) + Chan ) ; Reserved . set ( Reg ) ;


<s> <ISA_LIT>PLT0 :: <ISA_LIT>PLT0 ( SectionData & pParent ) : PLT :: Entry < sizeof ( arm_plt0 ) > ( pParent ) {


<s> if ( Offset <= <NUM_LIT> ) Loop -> eraseFromParent ( ) ; else Loop -> getOperand ( <NUM_LIT> ) . setImm ( Offset - <NUM_LIT> ) ; return Offset - <NUM_LIT> ; } assert ( Loop -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned LoopCount = Loop -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoopEnd = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , HRI ) ; PrevInsts . clear ( ) ; PrevInsts . push_back ( NewCmp ) ; PrevInsts . push_back ( NewAdd ) ; if ( Iter == MaxIter ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( Loop -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( NewLoopCount ) ; if ( Iter == <NUM_LIT> ) Loop -> eraseFromParent ( ) ;

Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ;


<s> return __builtin_ia32_comineq ( ( __v4sf ) __A , ( __v4sf ) __B ) ;


<s> bool hasAllWUsers ( SDNode * Node ) const {

return hasAllNBitUsers ( Node , <NUM_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } return Reg ;


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetBlockAddressSymbol ( const MachineOperand & MO ) const {


<s> const TargetRegisterInfo * <ISA_LIT>Subtarget :: getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ;


<s> const Function * F = MF -> getFunction ( ) ; Type * Rt = F -> getReturnType ( ) ; if ( ! Rt -> isVoidTy ( ) || ! F -> arg_empty ( ) ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; bool First = true ; for ( const Argument & A : F -> args ( ) ) { OS << ( First ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> <STR_LIT> << toString ( A . getType ( ) ) ; First = false ; } if ( ! Rt -> isVoidTy ( ) ) { OS << ( First ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> <STR_LIT> << toString ( Rt ) ; First = false ; } OutStreamer -> EmitRawText ( OS . str ( ) ) ; } AsmPrinter :: EmitFunctionBodyStart ( ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , unsigned DstReg , unsigned SrcReg , bool KillSrc ) const { assert ( <STR_LIT> . contains ( DstReg , SrcReg ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ;


<s> case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerCALL ( Op , DAG ) ; case <STR_LIT> : return LowerRET ( Op , DAG ) ;


<s> return ( int32x4_t ) __builtin_neon_vreinterpretv4siv4si ( ( int32x4_t ) __a ) ;


<s> if ( use_ldrd && GET_CODE ( x ) == POST_MODIFY && GET_CODE ( addend ) == REG ) return <NUM_LIT> ; return ( ( use_ldrd || GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) && arm_legitimate_index_p ( mode , addend , outer , strict_p ) ) ; } else if ( reload_completed && ( code == LABEL_REF || ( code == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ) ) return <NUM_LIT> ; else if ( mode == TImode ) return <NUM_LIT> ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ;


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const {


<s> if ( ! BiggerPattern && ! Op . hasOneUse ( ) ) return false ; uint64_t ShlImm ; if ( ! isOpcWithIntImmediate ( Op . getNode ( ) , <STR_LIT> , ShlImm ) ) return false ; Op = Op . getOperand ( <NUM_LIT> ) ; if ( ! isShiftedMask_64 ( NonZeroBits ) ) return false ; ShiftAmount = countTrailingZeros ( NonZeroBits ) ; MaskWidth = countTrailingOnes ( NonZeroBits >> ShiftAmount ) ; if ( ShlImm - ShiftAmount != <NUM_LIT> && ! BiggerPattern ) return false ;

Src = getLeftShift ( CurDAG , Op , ShlImm - ShiftAmount ) ;


<s> __o = __builtin_aarch64_ld2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregoidi_pss ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly64x1_t ) __builtin_aarch64_get_dregoidi_pss ( __o , <NUM_LIT> ) ;


<s> int Offset = getFrameIndexReferencePreferSP ( MF , Info . PSPSymFrameIdx , SPReg , true ) ;

assert ( Offset >= <NUM_LIT> && SPReg == TRI -> getStackRegister ( ) ) ;


<s> rtx addr , align ; addr = force_reg ( Pmode , XEXP ( mem , <NUM_LIT> ) ) ; align = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( - GET_MODE_SIZE ( SImode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; ac -> memsi = gen_rtx_MEM ( SImode , align ) ; MEM_VOLATILE_P ( ac -> memsi ) = MEM_VOLATILE_P ( mem ) ; set_mem_alias_set ( ac -> memsi , ALIAS_SET_MEMORY_BARRIER ) ; set_mem_align ( ac -> memsi , GET_MODE_BITSIZE ( SImode ) ) ;

byteoffset = expand_simple_binop ( Pmode , AND , addr , GEN_INT ( GET_MODE_SIZE ( SImode ) - <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ;


<s> void warn_once_call_ms2sysv_xlogues ( const char * feature ) { static bool warned_once = false ; if ( ! warned_once ) { warning ( <NUM_LIT> , <STR_LIT> , feature ) ; warned_once = true ; }


<s> assert ( ImgRsrc ) ; auto PSV = ImagePSVs . try_emplace ( ImgRsrc , llvm :: make_unique < <ISA_LIT>ImagePseudoSourceValue > ( TII ) ) ; return PSV . first -> second . get ( ) ;


<s> SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; Register VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; CFRegNode . push_back ( Val . getValue ( Val -> getNumValues ( ) - <NUM_LIT> ) ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) ) ; MemOps . push_back ( Store ) ; } } else { XFI -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( <NUM_LIT> , LRSaveSize + CCInfo . getNextStackOffset ( ) , true ) ) ; } } if ( ! CFRegNode . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CFRegNode ) ; for ( SmallVectorImpl < ArgDataPair > :: const_iterator ArgDI = ArgData . begin ( ) , ArgDE = ArgData . end ( ) ; ArgDI != ArgDE ; ++ ArgDI ) { if ( ArgDI -> Flags . isByVal ( ) && ArgDI -> Flags . getByValSize ( ) ) { unsigned Size = ArgDI -> Flags . getByValSize ( ) ; Align Alignment = std :: max ( Align ( StackSlotSize ) , ArgDI -> Flags . getNonZeroByValAlign ( ) ) ; int FI = MFI . CreateStackObject ( Size , Alignment , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( FIN ) ;

MemOps . push_back ( DAG . getMemcpy ( Chain , dl , FIN , ArgDI -> SDV , DAG . getConstant ( Size , dl , <STR_LIT> ) , Alignment , false , false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ) ;


<s> if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = gen_rtx_MEM ( mode0 , copy_to_mode_reg ( Pmode , op0 ) ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( pat ) emit_insn ( pat ) ;


<s> if ( IMemI -> getIntrinsicID ( ) == <STR_LIT> || IMemI -> getIntrinsicID ( ) == <STR_LIT> ) return IMemI -> getArgOperand ( <NUM_LIT> ) ;

if ( IMemI -> getIntrinsicID ( ) == <STR_LIT> ) return IMemI -> getArgOperand ( <NUM_LIT> ) ;


<s> char * P = static_cast < char * > ( T ) ; Blocks . push_back ( P ) ; assert ( ( Blocks . size ( ) < ( <NUM_LIT> << ( <NUM_LIT> * sizeof ( NodeId ) - BitsPerIndex ) ) ) && <STR_LIT> ) ;


<s> } assert ( LoadSize % MaxNonSmrdLoadSize == <NUM_LIT> ) ; MachineInstr * RepairInst = getOtherVRegDef ( MRI , DstReg , MI ) ; Register BasePtrReg = SrcRegs [ <NUM_LIT> ] ; LLT PtrTy = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MRI . setType ( BasePtrReg , PtrTy ) ; MachineIRBuilder B ( MI ) ; unsigned SplitElts = MaxNonSmrdLoadSize / LoadTy . getScalarType ( ) . getSizeInBits ( ) ; const LLT LoadSplitTy = LLT :: vector ( SplitElts , LoadTy . getScalarType ( ) ) ; ApplyRegBankMapping O ( * this , MRI , & <STR_LIT> ) ; GISelObserverWrapper Observer ( & O ) ; B . setChangeObserver ( Observer ) ; LegalizerHelper Helper ( B . getMF ( ) , Observer , B ) ; if ( Helper . fewerElementsVector ( MI , <NUM_LIT> , LoadSplitTy ) != LegalizerHelper :: Legalized ) return false ; MachineInstr * LegalizedInst = getOtherVRegDef ( MRI , DstReg , * RepairInst ) ; Register TmpReg = MRI . createGenericVirtualRegister ( MRI . getType ( DstReg ) ) ; LegalizedInst -> getOperand ( <NUM_LIT> ) . setReg ( TmpReg ) ; B . setInsertPt ( * RepairInst -> getParent ( ) , RepairInst ) ; for ( unsigned DefIdx = <NUM_LIT> , e = DefRegs . size ( ) ; DefIdx != e ; ++ DefIdx ) { Register IdxReg = B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , DefIdx ) . getReg ( <NUM_LIT> ) ; MRI . setRegBank ( IdxReg , <STR_LIT> ) ; B . buildExtractVectorElement ( DefRegs [ DefIdx ] , TmpReg , IdxReg ) ; } MRI . setRegBank ( DstReg , <STR_LIT> ) ; return true ;


<s> RegisterTarget < Triple :: bpf > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Other ; case 'Q' : return C_Memory ; } } else if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) {


<s> } MachineInstr * Def = MRI -> getUniqueVRegDef ( Op . getReg ( ) ) ; if ( ! Def || Def -> getParent ( ) != MI . getParent ( ) || ! ( Def -> isFullCopy ( ) || ( Def -> getOpcode ( ) == MI . getOpcode ( ) ) ) ) return ; for ( auto I = Def -> getIterator ( ) ; I != MI . getIterator ( ) ; ++ I ) if ( I -> modifiesRegister ( <STR_LIT> , TRI ) && ! ( I -> isCopy ( ) && I -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) ) return ; for ( const auto & SrcOp : Def -> explicit_operands ( ) ) if ( SrcOp . isReg ( ) && SrcOp . isUse ( ) && ( TargetRegisterInfo :: isVirtualRegister ( SrcOp . getReg ( ) ) || SrcOp . getReg ( ) == <STR_LIT> ) ) Src . push_back ( SrcOp ) ;


<s> return FtzEnabled ; } else { const Function * F = MF . getFunction ( ) ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) return F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printPCRelImmOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {


<s> BuildMI ( MBB , I , DL , SMovB32 , RsrcLo ) . addReg ( GitPtrLo ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; const MCInstrDesc & LoadDwordX4 = TII -> get ( <STR_LIT> ) ; auto MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable , <NUM_LIT> , <NUM_LIT> ) ; unsigned Offset = Fn . getCallingConv ( ) == CallingConv :: <ISA_LIT>_CS ? <NUM_LIT> : <NUM_LIT> ; const GCNSubtarget & Subtarget = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned EncodedOffset = <STR_LIT> ( Subtarget , Offset ) ; BuildMI ( MBB , I , DL , LoadDwordX4 , ScratchRsrcReg ) . addReg ( Rsrc01 ) . addImm ( EncodedOffset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) . addMemOperand ( MMO ) ; return ; } if ( ST . isMesaGfxShader ( Fn ) || ( PreloadedPrivateBufferReg == <STR_LIT> ) ) { assert ( ! ST . isAmdHsaOrMesa ( Fn ) ) ; const MCInstrDesc & SMovB32 = TII -> get ( <STR_LIT> ) ; Register Rsrc2 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; Register Rsrc3 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; uint64_t Rsrc23 = TII -> getScratchRsrcWords23 ( ) ; if ( MFI -> hasImplicitBufferPtr ( ) ) { Register Rsrc01 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; if ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) {

const MCInstrDesc & Mov64 = TII -> get ( <STR_LIT> ) ;


<s> O << TAI -> getGlobalDirective ( ) << name ;


<s> Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; }


<s> TextAlignFillValue = <NUM_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; PCSymbol = <STR_LIT> ; HasLEB128 = true ; AbsoluteDebugSectionOffsets = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: Dwarf ; AbsoluteEHSectionOffsets = false ;

if ( T . getOS ( ) == Triple :: OpenBSD && T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = <NUM_LIT> ;


<s> unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ;

MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( <NUM_LIT> , Reg , <NUM_LIT> ) ;


<s> blk -> push_back ( newInstr ) ; MachineInstrBuilder ( * MF , newInstr ) . addReg ( regNum , false ) ; SHOWNEWINSTR ( newInstr ) ;


<s> for ( Locs :: const_iterator HI = HandlerDataLocs . begin ( ) , HE = HandlerDataLocs . end ( ) ; HI != HE ; ++ HI ) Parser . Note ( * HI , <STR_LIT> ) ;


<s> LoadsToReplace . push_back ( LD ) ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( & Node ) ) { SDValue Value = ST -> getValue ( ) ; if ( Value . getValueType ( ) != <STR_LIT> || ST -> isTruncatingStore ( ) ) continue ; StoresToReplace . push_back ( ST ) ; } } for ( LoadSDNode * LD : LoadsToReplace ) { SDLoc SL ( LD ) ; SDValue NewLoad = CurDAG -> getLoad ( <STR_LIT> , SL , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getMemOperand ( ) ) ; SDValue BitCast = CurDAG -> getNode ( <STR_LIT> , SL , <STR_LIT> , NewLoad ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLoad . getValue ( <NUM_LIT> ) ) ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , BitCast ) ; Modified = true ; }

for ( StoreSDNode * ST : StoresToReplace ) {


<s> else Kind = k_SPRRegisterList ; } if ( Kind == k_RegisterList && Regs . back ( ) . second == <STR_LIT> ) Kind = k_RegisterListWithAPSR ; assert ( llvm :: is_sorted ( Regs ) && <STR_LIT> ) ; auto Op = std :: make_unique < <ISA_LIT>Operand > ( Kind ) ; for ( const auto & P : Regs ) Op -> Registers . push_back ( P . second ) ; Op -> StartLoc = StartLoc ; Op -> EndLoc = EndLoc ;


<s> int SubRegIdx [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( OrigRegSize < TargetRegSize && OrigRegSize < <NUM_LIT> ) { NewReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , SetPos , SetLoc , TII -> get ( <STR_LIT> ) , NewReg ) . addReg ( Reg ) ; if ( & SetBRC == & <STR_LIT> ) return NewReg ; Reg = NewReg ; OrigRegSize = <NUM_LIT> ; } NewReg = MRI -> createVirtualRegister ( & SetBRC ) ; if ( OrigRegSize < TargetRegSize ) { BuildMI ( MBB , SetPos , SetLoc , TII -> get ( TargetOpcode :: SUBREG_TO_REG ) , NewReg ) . addImm ( <NUM_LIT> ) . addReg ( Reg ) . addImm ( SubRegIdx [ OrigRegSize ] ) ; } else if ( OrigRegSize > TargetRegSize ) { if ( TargetRegSize == <NUM_LIT> && ! Subtarget -> is64Bit ( ) ) { MRI -> constrainRegClass ( Reg , & <STR_LIT> ) ; } BuildMI ( MBB , SetPos , SetLoc , TII -> get ( TargetOpcode :: COPY ) , NewReg ) . addReg ( Reg , <NUM_LIT> , SubRegIdx [ TargetRegSize ] ) ; } else { BuildMI ( MBB , SetPos , SetLoc , TII -> get ( TargetOpcode :: COPY ) , NewReg ) . addReg ( Reg ) ; } return NewReg ; } ; unsigned & CondReg = CondRegs [ <STR_LIT> ] ; if ( ! CondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc , <STR_LIT> ) ;

unsigned ExtCondReg = AdjustReg ( CondReg ) ;


<s> SDValue ValV = Op . getOperand ( <NUM_LIT> ) ; SDValue IdxV = Op . getOperand ( <NUM_LIT> ) ; const SDLoc & dl ( Op ) ; MVT VecTy = ty ( VecV ) ; MVT ElemTy = VecTy . getVectorElementType ( ) ;

if ( ElemTy == <STR_LIT> ) return insertHvxSubvectorPred ( VecV , ValV , IdxV , dl , DAG ) ;


<s> gcc_assert ( reg < m_nregs ) ; return m_regs [ reg ] ;


<s> Chain = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue RetValue = Chain . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , RetValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) RetValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , RetValue ) ; InVals . push_back ( RetValue ) ; } return Chain ;


<s> int floating_exact_log2 ( rtx x ) { REAL_VALUE_TYPE r , r1 ; int exp ; REAL_VALUE_FROM_CONST_DOUBLE ( r , x ) ; if ( REAL_VALUES_LESS ( r , dconst1 ) ) return <NUM_LIT> ; exp = real_exponent ( & r ) ; real_2expN ( & r1 , exp ) ; if ( REAL_VALUES_EQUAL ( r1 , r ) ) return exp ; return <NUM_LIT> ;


<s> inline rtx base_reg_disp :: reg ( void ) const {


<s> if ( TLI . isPositionIndependent ( ) ) return <NUM_LIT> ; if ( GV -> isThreadLocal ( ) ) return <NUM_LIT> ; unsigned ResultReg = createResultReg ( Subtarget -> hasAddr64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ;

unsigned Opc = Subtarget -> hasAddr64 ( ) ? <STR_LIT> : <STR_LIT> ;


<s> Repo<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI ) : <ISA_LIT>AsmBackend ( T , STI ) {


<s> unsigned getVariadicFPRSize ( ) const { return VariadicFPRSize ;


<s> MachineFunctionProperties getRequiredProperties ( ) const override {

return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ;


<s> if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp + <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , <NUM_LIT> ) ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; break ; } case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; CurOp ++ ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ++ ) ; if ( <STR_LIT> ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; CurOp ++ ; if ( HasVEX_4VOp3 ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; break ; case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : VEX_4V = getVEXRegisterEncoding ( MI , <NUM_LIT> ) ; if ( <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; break ; default : break ; } EmitSegmentOverridePrefix ( TSFlags , CurByte , MemOperand , MI , OS ) ; unsigned char LastByte = VEX_PP | ( VEX_L << <NUM_LIT> ) | ( VEX_4V << <NUM_LIT> ) ; if ( VEX_B && VEX_X && ! VEX_W && ! XOP && ( VEX_5M == <NUM_LIT> ) ) { EmitByte ( <NUM_LIT> , CurByte , OS ) ; EmitByte ( LastByte | ( VEX_R << <NUM_LIT> ) , CurByte , OS ) ; return ; }

EmitByte ( XOP ? <NUM_LIT> : <NUM_LIT> , CurByte , OS ) ;


<s> if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return ; <ISA_LIT>FunctionInfo * PFI = Entry -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ;


<s> static bool isUndefOrZero ( int Val ) { return ( Val == SM_SentinelUndef || Val == SM_SentinelZero ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; if ( CallConv == CallingConv :: Fast ) { CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32_Fast ) ; } else { CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32 ) ; } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; break ; } default : DEBUG ( dbgs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI . CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ) ; } } if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { unsigned Reg = <ISA_LIT>MFI -> getSRetReturnReg ( ) ;


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; unsigned Opc = getCMovFromCond ( ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) , MRI . getRegClass ( DstReg ) -> getSize ( ) , false ) ;

BuildMI ( MBB , I , DL , get ( Opc ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) ;


<s> unsigned getDPRCalleeSavedAreaSize ( ) const {


<s> explicit pushI ( unsigned i , bool checkLimits = true ) : i ( i ) {


<s> SelectionDAGISel :: runOnFunction ( Fn ) ;


<s> SDValue VDup = N -> getOperand ( <NUM_LIT> ) ; if ( VDup -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue VMov = N -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) == <STR_LIT> ) VMov = VMov -> getOperand ( <NUM_LIT> ) ; if ( VMov -> getOpcode ( ) != <STR_LIT> || ! isZeroVector ( VMov ) ) return SDValue ( ) ; SDLoc dl ( N ) ; SDValue Negate = DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DCI . DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , VDup -> getOperand ( <NUM_LIT> ) ) ; return DCI . DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , Negate ) ;


<s> if ( Tok . isNot ( AsmToken :: Integer ) ) return Error ( L , <STR_LIT> ) ; int64_t Val = Parser . getTok ( ) . getIntVal ( ) ; if ( Val == <NUM_LIT> ) Parser . Lex ( ) ; else if ( Val == <NUM_LIT> ) Parser . Lex ( ) ; else return Error ( L , <STR_LIT> ) ;

if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ;


<s> bool <ISA_LIT>LegalizerInfo :: legalizeFMad ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & B ) const { LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; assert ( Ty . isScalar ( ) ) ; MachineFunction & MF = B . getMF ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) && ! MFI -> getMode ( ) . allFP32Denormals ( ) ) return true ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) && ! MFI -> getMode ( ) . allFP64FP16Denormals ( ) ) return true ; MachineIRBuilder HelperBuilder ( MI ) ;


<s> void <ISA_LIT>InstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DstReg , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; unsigned Opcode ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;