<s> } if ( IsV3 && Size >= <NUM_LIT> ) { V4Ty = VectorType :: get ( VT -> getVectorElementType ( ) , <NUM_LIT> ) ; AdjustedArgTy = V4Ty ; } ArgPtr = Builder . CreateBitCast ( ArgPtr , AdjustedArgTy -> getPointerTo ( AS ) , ArgPtr -> getName ( ) + <STR_LIT> ) ; LoadInst * Load = Builder . CreateAlignedLoad ( AdjustedArgTy , ArgPtr , AdjustedAlign ) ; Load -> setMetadata ( LLVMContext :: MD_invariant_load , MDNode :: get ( Ctx , { } ) ) ; MDBuilder MDB ( Ctx ) ; if ( isa < PointerType > ( ArgTy ) ) { if ( Arg . hasNonNullAttr ( ) ) Load -> setMetadata ( LLVMContext :: MD_nonnull , MDNode :: get ( Ctx , { } ) ) ; uint64_t DerefBytes = Arg . getDereferenceableBytes ( ) ; if ( DerefBytes != <NUM_LIT> ) { Load -> setMetadata ( LLVMContext :: MD_dereferenceable , MDNode :: get ( Ctx , MDB . createConstant ( ConstantInt :: get ( Builder . getInt64Ty ( ) , DerefBytes ) ) ) ) ; } uint64_t DerefOrNullBytes = Arg . getDereferenceableOrNullBytes ( ) ; if ( DerefOrNullBytes != <NUM_LIT> ) { Load -> setMetadata ( LLVMContext :: MD_dereferenceable_or_null , MDNode :: get ( Ctx , MDB . createConstant ( ConstantInt :: get ( Builder . getInt64Ty ( ) , DerefOrNullBytes ) ) ) ) ; } unsigned ParamAlign = Arg . getParamAlignment ( ) ; if ( ParamAlign != <NUM_LIT> ) { Load -> setMetadata ( LLVMContext :: MD_align , MDNode :: get ( Ctx , MDB . createConstant ( ConstantInt :: get ( Builder . getInt64Ty ( ) , ParamAlign ) ) ) ) ; } } if ( DoShiftOpt ) { Value * ExtractBits = OffsetDiff == <NUM_LIT> ? Load : Builder . CreateLShr ( Load , OffsetDiff * <NUM_LIT> ) ; IntegerType * ArgIntTy = Builder . getIntNTy ( Size ) ; Value * Trunc = Builder . CreateTrunc ( ExtractBits , ArgIntTy ) ;

Value * NewVal = Builder . CreateBitCast ( Trunc , ArgTy , Arg . getName ( ) + <STR_LIT> ) ;


<s> assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Disp << <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; return MCDisassembler :: Success ;


<s> switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; }

const MCInstrDesc & II = TII . get ( Opc ) ;


<s> if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( CCR ) ) return Flags ;

if ( SDValue R = checkBoolTestSetCCCombine ( CCR , CC ) ) return R ;


<s> case <STR_LIT> : return ELF :: R_MIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MIPS_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MIPS_TLS_GOTTPREL ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_TPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_TLS_DTPREL_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_DISP ; case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; return Type ; } case <STR_LIT> : { unsigned Type = ( unsigned ) ELF :: R_MIPS_NONE ; Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; return Type ; } case <STR_LIT> : return ELF :: R_MIPS_HIGHER ; case <STR_LIT> : return ELF :: R_MIPS_HIGHEST ; case <STR_LIT> : return ELF :: R_MIPS_GOT_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_GOT_LO16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_HI16 ; case <STR_LIT> : return ELF :: R_MIPS_CALL_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_26_S1 ; case <STR_LIT> : return ELF :: R_MICROMIPS_HI16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_LO16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_CALL16 ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT_DISP ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT_PAGE ; case <STR_LIT> : return ELF :: R_MICROMIPS_GOT_OFST ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_GD ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_LDM ; case <STR_LIT> : return ELF :: R_MICROMIPS_TLS_DTPREL_HI16 ; case <STR_LIT> :

return ELF :: R_MICROMIPS_TLS_DTPREL_LO16 ;


<s> return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> void <ISA_LIT>TargetStreamer :: emitPersonalityIndex ( unsigned Index ) {


<s> if ( TARGET_ALTIVEC && testing_p ) return true ; if ( ( vmode == V2SFmode && TARGET_PAIRED_FLOAT ) || ( vmode == V2SImode && TARGET_SPE ) || ( ( vmode == V2DFmode || vmode == V2DImode ) && VECTOR_MEM_VSX_P ( vmode ) ) ) { if ( testing_p ) {


<s> Register IdxReg = Idx -> isReg ( ) ? Idx -> getReg ( ) : Register ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > ToRemove ; bool IdxOn = true ; if ( ! MI . isIdenticalTo ( First ) ) return false ; for ( MachineBasicBlock :: instr_iterator I = std :: next ( First . getIterator ( ) ) , E = MI . getIterator ( ) ; I != E ; ++ I ) { if ( I -> isBundle ( ) ) continue ; switch ( I -> getOpcode ( ) ) { case <STR_LIT> : return false ; case <STR_LIT> : IdxOn = false ; ToRemove . push_back ( & * I ) ; break ; default : if ( I -> modifiesRegister ( <STR_LIT> , TRI ) ) return false ; if ( IdxReg && I -> modifiesRegister ( IdxReg , TRI ) ) return false ; if ( llvm :: any_of ( I -> operands ( ) , [ & MRI , this ] ( const MachineOperand & MO ) { return MO . isReg ( ) && TRI -> isVectorRegister ( MRI , MO . getReg ( ) ) ;


<s> for ( ; * template ; template ++ ) if ( * template == '\n' ) count ++ ;


<s> unsigned HOST_WIDE_INT bit2 = ( val + bit1 ) & ~ val ; unsigned HOST_WIDE_INT val1 = ( val + bit1 ) & val ; unsigned HOST_WIDE_INT bit3 = val1 & - val1 ;

return rs6000_is_valid_and_mask ( GEN_INT ( val + bit3 - bit2 ) , mode ) ;


<s> int i ; if ( dest_start < src_start ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , dest_start + i ) ; ops [ <NUM_LIT> ] = gen_rtx_REG ( SImode , src_start + i ) ; output_asm_insn ( <STR_LIT> , ops ) ; } } else {

for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) {


<s> static DecodeStatus DecodeVecShiftR32ImmNarrow ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) {

return DecodeVecShiftRImm ( Inst , Imm | <NUM_LIT> , <NUM_LIT> ) ;


<s> encode_pattern_1 ( XEXP ( x , <NUM_LIT> ) ) ; encode_pattern_1 ( XEXP ( x , <NUM_LIT> ) ) ; break ; case LO_SUM : * patternp ++ = 'L' ; encode_pattern_1 ( XEXP ( x , <NUM_LIT> ) ) ; encode_pattern_1 ( XEXP ( x , <NUM_LIT> ) ) ; break ; case HIGH : * patternp ++ = 'H' ; encode_pattern_1 ( XEXP ( x , <NUM_LIT> ) ) ; break ; case SYMBOL_REF : * patternp ++ = 's' ; break ; case LABEL_REF : * patternp ++ = 'l' ; break ; case CONST_INT : case CONST_DOUBLE : * patternp ++ = 'i' ; break ;


<s> } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) ) { PatternNodeWithChain = N . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( PatternNodeWithChain . getNode ( ) ) && IsProfitableToFold ( PatternNodeWithChain , N . getNode ( ) , Root ) && IsLegalToFold ( PatternNodeWithChain , N . getNode ( ) , Root , OptLevel ) && hasSingleUsesFromRoot ( Root , N . getNode ( ) ) ) { LoadSDNode * LD = cast < LoadSDNode > ( PatternNodeWithChain ) ; return selectAddr ( LD , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ; } } if ( N . getOpcode ( ) == <STR_LIT> && N . getNode ( ) -> hasOneUse ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getNode ( ) -> hasOneUse ( ) ) { PatternNodeWithChain = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( PatternNodeWithChain . getNode ( ) ) && IsProfitableToFold ( PatternNodeWithChain , N . getNode ( ) , Root ) && IsLegalToFold ( PatternNodeWithChain , N . getNode ( ) , Root , OptLevel ) && hasSingleUsesFromRoot ( Root , N . getNode ( ) ) ) { LoadSDNode * LD = cast < LoadSDNode > ( PatternNodeWithChain ) ; return selectAddr ( LD , LD -> getBasePtr ( ) , Base , Scale , Index , Disp , Segment ) ; } }


<s> rtx src = operands [ <NUM_LIT> ] ; unsigned int size = INTVAL ( operands [ <NUM_LIT> ] ) ; unsigned int pos = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( GET_CODE ( dst ) == SUBREG ) { pos += SUBREG_BYTE ( dst ) * BITS_PER_UNIT ; dst = SUBREG_REG ( dst ) ; } if ( GET_CODE ( src ) == SUBREG ) src = SUBREG_REG ( src ) ; switch ( GET_MODE ( dst ) ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : { machine_mode srcmode , dstmode ;

rtx ( * pinsr ) ( rtx , rtx , rtx , rtx ) ;


<s> if ( Offset0 % Size != <NUM_LIT> || Offset1 % Size != <NUM_LIT> ) return false ;

if ( ! isUInt < <NUM_LIT> > ( Offset0 / Size ) || ! isUInt < <NUM_LIT> > ( Offset1 / Size ) ) return false ;


<s> Type * Ty = STy -> getTypeAtIndex ( i ) ; Elems . push_back ( cast < Constant > ( PrepareValueForMemSet ( IRB , Val , Ty ) ) ) ; } return ConstantStruct :: get ( STy , Elems ) ; } else if ( ArrayType * ATy = dyn_cast < ArrayType > ( ToType ) ) {


<s> Function * Caller = CS . getCaller ( ) ; if ( ! Callee || Callee -> isDeclaration ( ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; if ( CS . isNoInline ( ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; TargetTransformInfo & TTI = TTIWP -> getTTI ( * Callee ) ; if ( ! TTI . areInlineCompatible ( Caller , Callee ) ) return llvm :: InlineCost :: getNever ( <STR_LIT> ) ; if ( CS . hasFnAttr ( Attribute :: AlwaysInline ) ) { auto IsViable = isInlineViable ( * Callee ) ; if ( IsViable . isSuccess ( ) ) return llvm :: InlineCost :: getAlways ( <STR_LIT> ) ; return llvm :: InlineCost :: getNever ( IsViable . getFailureReason ( ) ) ; } if ( isWrapperOnlyCall ( CS ) ) return llvm :: InlineCost :: getAlways ( <STR_LIT> ) ;


<s> return VT == <STR_LIT> || VT == <STR_LIT> || VT . isVector ( ) || ( VT == <STR_LIT> && Subtarget . hasFP16 ( ) ) ;


<s> Inst . setOpcode ( <STR_LIT> ) ; break ; default : return MCDisassembler :: Fail ; } return DecodeT2LoadLabel ( Inst , Insn , Address , Decoder ) ; } if ( Rt == <NUM_LIT> ) { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : return MCDisassembler :: Fail ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; default : break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : break ; case <STR_LIT> : if ( ! hasV7Ops ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : if ( ! hasV7Ops || ! hasMP ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; }

if ( ! Check ( S , DecodeT2AddrModeImm12 ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> bool has<ISA_LIT>64r2 ( ) const { return ( STI . getFeatureBits ( ) & <STR_LIT> ) ;


<s> ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o , <NUM_LIT> ) ; return ret ;


<s> } EVT VT = Op . getValueType ( ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; if ( Convert ) { SDValue SR = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , <STR_LIT> , Flag ) ; if ( Shift ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; if ( Invert ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; return SR ; } else { SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , VT ) ;

SDValue Ops [ ] = { One , Zero , TargetCC , Flag } ;


<s> start_sequence ( ) ; emit_insn ( gen_rtx_SET ( m_ccreg , gen_rtx_fmt_ee ( EQ , SImode , src_reg , const0_rtx ) ) ) ; if ( GET_MODE ( dst_reg ) == SImode ) emit_move_insn ( dst_reg , m_ccreg ) ; else if ( GET_MODE ( dst_reg ) == DImode ) { emit_move_insn ( gen_lowpart ( SImode , dst_reg ) , m_ccreg ) ; emit_move_insn ( gen_highpart ( SImode , dst_reg ) , const0_rtx ) ; } else gcc_unreachable ( ) ; rtx i = get_insns ( ) ; end_sequence ( ) ; return i ;


<s> case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ;

case MachineOperand :: MO_ConstantPoolIndex :


<s> static SDNode * SelectInt64 ( SelectionDAG * CurDAG , SDNode * N ) {


<s> unsigned getVmcntBitMask ( const IsaVersion & Version ) { unsigned VmcntLo = ( <NUM_LIT> << getVmcntBitWidthLo ( ) ) - <NUM_LIT> ; if ( Version . Major < <NUM_LIT> ) return VmcntLo ; unsigned VmcntHi = ( ( <NUM_LIT> << getVmcntBitWidthHi ( ) ) - <NUM_LIT> ) << getVmcntBitWidthLo ( ) ; return VmcntLo | VmcntHi ;


<s> MIArgs :: MIArgs ( MachineInstr & MI , const LiveIntervals & LIS , SlotIndex LIIndex ) { auto regUses = llvm :: make_filter_range ( MI . uses ( ) , [ ] ( const MachineOperand & Op ) { return Op . isReg ( ) ; } ) ; for ( auto Arg : regUses ) { auto Vreg = Arg . isUndef ( ) ? <ISA_LIT>FunctionInfo :: UnusedReg : Arg . getReg ( ) ; bool Killed = Arg . isUndef ( ) ? true : isKilled ( MI , Arg . getReg ( ) , LIS , LIIndex ) ; Args . emplace_back ( StackVreg ( Vreg ) , Killed ) ; }


<s> return create<ISA_LIT>MachineScheduler ( C ) ;


<s> if ( Match . back ( ) == Match_MnemonicFail ) { ArrayRef < SMRange > Ranges = MatchingInlineAsm ? EmptyRanges : Op . getLocRange ( ) ; return Error ( IDLoc , <STR_LIT> + Mnemonic + <STR_LIT> , Ranges , MatchingInlineAsm ) ; } unsigned NumSuccessfulMatches = std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Success ) ; if ( NumSuccessfulMatches == <NUM_LIT> ) { if ( ! validateInstruction ( Inst , Operands ) ) return true ; if ( ! MatchingInlineAsm ) while ( processInstruction ( Inst , Operands ) ) ; Inst . setLoc ( IDLoc ) ; if ( ! MatchingInlineAsm ) EmitInstruction ( Inst , Operands , Out ) ; Opcode = Inst . getOpcode ( ) ; return false ; } else if ( NumSuccessfulMatches > <NUM_LIT> ) { assert ( UnsizedMemOp && <STR_LIT> ) ; ArrayRef < SMRange > Ranges = MatchingInlineAsm ? EmptyRanges : UnsizedMemOp -> getLocRange ( ) ; return Error ( UnsizedMemOp -> getStartLoc ( ) , <STR_LIT> + Mnemonic + <STR_LIT> , Ranges , MatchingInlineAsm ) ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MissingFeature ) == <NUM_LIT> ) { ErrorInfo = ErrorInfoMissingFeature ; return ErrorMissingFeature ( IDLoc , ErrorInfoMissingFeature , MatchingInlineAsm ) ; }

if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_InvalidOperand ) == <NUM_LIT> ) {


<s> unsigned Encoding = StringSwitch < unsigned > ( RegName . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ;

if ( Encoding == ~ <NUM_LIT> ) return MatchOperand_NoMatch ;


<s> if ( is_ha != NULL ) * is_ha = true ; * count = <NUM_LIT> ; new_mode = GET_MODE_INNER ( mode ) ; } else if ( type && composite_p ) { int ag_count = aapcs_vfp_sub_candidate ( type , & new_mode ) ; if ( ag_count > <NUM_LIT> && ag_count <= HA_MAX_NUM_FLDS ) { if ( is_ha != NULL ) * is_ha = true ; * count = ag_count ; }


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ;


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) && TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) { if ( TRI . regsOverlap ( Reg , MO . getReg ( ) ) ) return true ; } else if ( MO . getReg ( ) == Reg && TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { LaneBitmask Overlap = TRI . getSubRegIndexLaneMask ( SubReg ) & TRI . getSubRegIndexLaneMask ( MO . getSubReg ( ) ) ; if ( Overlap . any ( ) ) return true ;


<s> const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; DebugLoc DL ; if ( Reg == <STR_LIT> ) BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? <STR_LIT> : <STR_LIT> ) ) ;

else BuildMI ( MBB , MI , DL , TII . get ( Is24Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg ) ;


<s> return new Micro<ISA_LIT>SizeReduce ( ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( Mods . getModifiersOperand ( ) ) ) ; assert ( isRegKind ( ) ) ;


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( DecodeRegListOperand ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; default : Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: createReg ( Reg + <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ;


<s> printRegister ( MO , false , OS ) ; } else if ( MO . isImm ( ) ) {


<s> PM -> add ( create<ISA_LIT>HardwareLoops ( ) ) ;


<s> if ( isProperty ( ) ) { os << <STR_LIT> ; uint32_t Ps = properties ( ) ; if ( Ps & ConstantProperties :: Zero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NonZero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: Finite ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: Infinity ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NaN ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: PosOrZero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NegOrZero ) os << <STR_LIT> ; os << '}' ; return ; } os << <STR_LIT> ; if ( isBottom ( ) ) { os << <STR_LIT> ; } else if ( isTop ( ) ) { os << <STR_LIT> ; } else { for ( unsigned i = <NUM_LIT> ; i < size ( ) ; ++ i ) { const Constant * C = Values [ i ] ; if ( i != <NUM_LIT> ) os << <STR_LIT> ; C -> print ( os ) ; } }


<s> bool worker = mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ;

bool large_vector = ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) && nvptx_mach_vector_length ( ) != PTX_WARP_SIZE ;


<s> void <ISA_LIT>ConditionalCompares :: updateDomTree ( ArrayRef < MachineBasicBlock * > Removed ) { MachineDomTreeNode * HeadNode = DomTree -> getNode ( CmpConv . Head ) ;

for ( MachineBasicBlock * RemovedMBB : Removed ) {


<s> if ( ! Subtarget -> hasSSE3 ( ) ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . is128BitVector ( ) && NumElems != <NUM_LIT> ) || ( VT . is256BitVector ( ) && NumElems != <NUM_LIT> ) || ( VT . is512BitVector ( ) && NumElems != <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( Mask [ i ] , i + <NUM_LIT> ) || ! isUndefOrEqual ( Mask [ i + <NUM_LIT> ] , i + <NUM_LIT> ) ) return false ;


<s> EHSecName += FnSecName ; } const MCSymbolELF * Group = FnSection . getGroup ( ) ; if ( Group ) Flags |= ELF :: SHF_GROUP ; MCSectionELF * EHSection = getContext ( ) . getELFSection ( EHSecName , Type , Flags , <NUM_LIT> , Group , FnSection . getUniqueID ( ) , nullptr , & FnSection ) ; assert ( EHSection && <STR_LIT> ) ;


<s> AMDGPUDevice :: ~ AMDGPUDevice ( ) {


<s> const Value * Src = N -> getSrcValue ( ) ; if ( ! Src ) return <STR_LIT> :: LOCAL ; if ( const PointerType * PT = dyn_cast < PointerType > ( Src -> getType ( ) ) ) { switch ( PT -> getAddressSpace ( ) ) {


<s> return isTargetDarwin ( ) || ( TargetTriple . getEnvironment ( ) == Triple :: MachO ) ;


<s> <ISA_LIT>DebugFixup ( ) : MachineFunctionPass ( ID ) {


<s> static DecodeStatus DecodeFPZeroOperand ( llvm :: MCInst & Inst , unsigned RmBits , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; return MCDisassembler :: Success ;


<s> APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( getTargetConstantBitsFromNode ( N1 , <NUM_LIT> , UndefElts , EltBits , true , false ) ) { unsigned <ISA_LIT>Opc = getTargetVShiftUniformOpcode ( N -> getOpcode ( ) , false ) ; return getTargetVShiftByConstNode ( <ISA_LIT>Opc , SDLoc ( N ) , VT . getSimpleVT ( ) , N0 , EltBits [ <NUM_LIT> ] . getZExtValue ( ) , DAG ) ; } APInt KnownUndef , KnownZero ;

const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ;


<s> TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; FindInstrPairs ( MDT -> getRootNode ( ) , nullptr , nullptr ) ; assert ( Setups . size ( ) == Branches . size ( ) && Setups . size ( ) == LoopNums . size ( ) ) ; if ( Setups . empty ( ) ) return false ; while ( ! Setups . empty ( ) ) { ProcessHardwareLoop ( Setups . pop_back_val ( ) , Branches . pop_back_val ( ) , LoopNums . pop_back_val ( ) , MF ) ;


<s> EVT VT = Op . getValueType ( ) ; DAG . computeKnownBits ( Op , Known ) ; return ( VT . getSizeInBits ( ) - Known . countMinLeadingZeros ( ) ) <= <NUM_LIT> ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateRegPair ( const <ISA_LIT>Operand & MOP , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { auto Op = llvm :: make_unique < <ISA_LIT>Operand > ( k_RegPair , Parser ) ; Op -> RegIdx . Index = MOP . RegIdx . Index ; Op -> RegIdx . RegInfo = MOP . RegIdx . RegInfo ; Op -> RegIdx . Kind = MOP . RegIdx . Kind ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ;


<s> assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Disp << <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( GP0Regs [ Base ] ) ) ;


<s> MachineOperand & MaskOp = Instr . getOperand ( <NUM_LIT> ) ; assert ( MaskOp . isImm ( ) && <STR_LIT> ) ;

MachineBasicBlock :: iterator Iter = ++ Instr . getIterator ( ) , End = Instr . getParent ( ) -> end ( ) ;


<s> bool <ISA_LIT>Subtarget :: useConstantIslands ( ) {

DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>16ConstantIslands << <STR_LIT> ) ;


<s> return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitMSACBranchPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> :


<s> emitFileDirective ( const std :: string & name ) { O << <STR_LIT> ;


<s> static void moxie_operand_lossage ( const char * msgid , rtx op ) { debug_rtx ( op ) ;

output_operand_lossage ( <STR_LIT> , msgid ) ;


<s> for ( unsigned int i = <NUM_LIT> ; i < pieces . length ( ) ; ++ i ) res += pieces [ i ] . num_zr ;


<s> return MatchOperand_ParseFail ; } else if ( res == MatchOperand_NoMatch ) { res = parseStringWithPrefix ( <STR_LIT> , Value ) ; if ( res == MatchOperand_ParseFail ) { return MatchOperand_ParseFail ; } else if ( res == MatchOperand_NoMatch ) { res = parseStringWithPrefix ( <STR_LIT> , Value ) ; if ( res != MatchOperand_Success ) { return res ; } } } int64_t Int ; Int = StringSwitch < int64_t > ( Value ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( <NUM_LIT> ) ; Parser . Lex ( ) ;


<s> const MCFixupKindInfo & Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; switch ( ( unsigned int ) Fixup . getKind ( ) ) { case <STR_LIT> : case <STR_LIT> : { Value = static_cast < uint64_t > ( static_cast < int64_t > ( Value ) / <NUM_LIT> ) ; if ( ! APInt ( <NUM_LIT> , Value ) . isSignedIntN ( Info . TargetSize ) ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ;


<s> unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t Offset = <NUM_LIT> * ( Subtarget . isLittle ( ) ? N : ( <NUM_LIT> - N ) ) ; assert ( Subtarget . isGP64bit ( ) || Subtarget . hasMTHC1 ( ) || ! Subtarget . isFP64bit ( ) ) ; const TargetRegisterClass * RC = FP64 ? & <STR_LIT> : & <STR_LIT> ; const TargetRegisterClass * RC2 = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getMoveF64ViaSpillFI ( RC ) ; TII . storeRegToStack ( MBB , I , SrcReg , I -> getOperand ( <NUM_LIT> ) . isKill ( ) , FI , RC , & TRI , <NUM_LIT> ) ; TII . loadRegFromStack ( MBB , I , DstReg , FI , RC2 , & TRI , Offset ) ; return true ;


<s> raw_svector_ostream Err ( ErrStr ) ; if ( ! parseAmdKernelCodeField ( ID , getParser ( ) , Header , Err ) ) { return TokError ( Err . str ( ) ) ; } Lex ( ) ; if ( ID == <STR_LIT> ) { if ( G_00B848_WGP_MODE ( Header . compute_pgm_resource_registers ) && ! isGFX10 ( ) ) return TokError ( <STR_LIT> ) ;


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & _STI , MCAsmParser & _Parser ) : MCTargetAsmParser ( ) , Parser ( _Parser ) {


<s> if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) return false ; else if ( RHSC < <NUM_LIT> && RHSC >= - <NUM_LIT> ) return false ; } unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; OffReg = N . getOperand ( <NUM_LIT> ) ; <STR_LIT> ShOpcVal = <STR_LIT> ( OffReg . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { ShOpcVal = <STR_LIT> ( Base . getOpcode ( ) ) ; if ( ShOpcVal == <STR_LIT> ) std :: swap ( Base , OffReg ) ; } if ( ShOpcVal == <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( OffReg . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( ShAmt < <NUM_LIT> && isShifterOpProfitable ( OffReg , ShOpcVal , ShAmt ) ) OffReg = OffReg . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } ShImm = CurDAG -> getTargetConstant ( ShAmt , <STR_LIT> ) ; return true ;


<s> SMLoc getLoc ( ) const { return getParser ( ) . getTok ( ) . getLoc ( ) ;


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( DestRC == <STR_LIT> ) {

BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ;


<s> std :: vector < std :: string > add_p1 ( Ax b ) {

return D ( <STR_LIT> , <STR_LIT> , R ( b ) ) ;


<s> } if ( isCallIndirect ( MI ) ) return true ; if ( ! MI . isCall ( ) ) return false ; const MachineOperand & MO = MI . getOperand ( getCalleeOpNo ( MI ) ) ; assert ( MO . isGlobal ( ) ) ;

const auto * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TM ( TM ) , STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , ForCodeSize ( ) , AvailableFeatures ( ) {


<s> for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { Register DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; } } ModifiedRegUnits . clear ( ) ; UsedRegUnits . clear ( ) ; ++ MBBI ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) {


<s> Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; <STR_LIT> BranchCode = GetCondFromBranchOpc ( SecondLastOpc ) ; if ( BranchCode != <STR_LIT> && IsBRU ( LastInst -> getOpcode ( ) ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; }

if ( IsBRU ( SecondLastInst -> getOpcode ( ) ) && IsBRU ( LastInst -> getOpcode ( ) ) ) {


<s> bool <ISA_LIT>GOT :: hasGOT1 ( ) const {

return ( ( ! m_GOT . empty ( ) ) || ( ! m_GOTPLT . empty ( ) ) ) ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { for ( Target * T : { & The<ISA_LIT>LETarget , & The<ISA_LIT>BETarget , & TheThumbLETarget , & TheThumbBETarget } ) { RegisterMCAsmInfoFn X ( * T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstrAnalysis ( * T , create<ISA_LIT>MCInstrAnalysis ) ; TargetRegistry :: RegisterELFStreamer ( * T , createELFStreamer ) ; TargetRegistry :: RegisterCOFFStreamer ( * T , create<ISA_LIT>WinCOFFStreamer ) ; TargetRegistry :: RegisterMachOStreamer ( * T , create<ISA_LIT>MachOStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>TargetAsmStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( * T , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCRelocationInfo ( * T , create<ISA_LIT>MCRelocationInfo ) ; } for ( Target * T : { & The<ISA_LIT>LETarget , & TheThumbLETarget } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>LEMCCodeEmitter ) ;

for ( Target * T : { & The<ISA_LIT>BETarget , & TheThumbBETarget } ) TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>BEMCCodeEmitter ) ;


<s> if ( GET_CODE ( x ) == MINUS ) return symbol_mentioned_p ( XEXP ( x , <NUM_LIT> ) ) && label_mentioned_p ( XEXP ( x , <NUM_LIT> ) ) ;


<s> MachineBasicBlock :: const_instr_iterator E = MI -> getParent ( ) -> instr_end ( ) ; do { MCInst TmpInst ;

MCInstLowering . Lower ( MI , TmpInst ) ;


<s> return isMem64 ( ) && isMemIndexReg ( <STR_LIT> , <STR_LIT> ) ;


<s> return Error ( IDLoc , <STR_LIT> ) ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ;


<s> delete static_cast < <ISA_LIT>Section * > ( LSDASection ) ; delete static_cast < <ISA_LIT>Section * > ( EHFrameSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfAbbrevSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfInfoSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfLineSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfFrameSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfPubTypesSection ) ; delete static_cast < const <ISA_LIT>Section * > ( DwarfDebugInlineSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfStrSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfLocSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfARangesSection ) ; delete static_cast < <ISA_LIT>Section * > ( DwarfRangesSection ) ;

delete static_cast < <ISA_LIT>Section * > ( DwarfMacinfoSection ) ;


<s> static void adjustCodeGenOpts ( const Triple & TT , Reloc :: Model RM , CodeModel :: Model & CM ) { if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ;

else if ( CM == CodeModel :: JITDefault ) CM = RM == Reloc :: PIC_ ? CodeModel :: Small : CodeModel :: Medium ;


<s> return instr -> getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const {

return isSimpleMove ( MI , FrameIndex , <STR_LIT> ) ;


<s> if ( ptx_name ) maybe_unlink ( ptx_name ) ;


<s> else if ( I -> getOperand ( k ) . isCImm ( ) ) { tempOs << <STR_LIT> << I -> getOperand ( k ) . getCImm ( ) ; } else if ( I -> getOperand ( k ) . isMBB ( ) ) { tempOs << <STR_LIT> << I -> getOperand ( k ) . getMBB ( ) -> getFullName ( ) << <STR_LIT> << I -> getOperand ( k ) . getMBB ( ) -> getNumber ( ) << <STR_LIT> << I -> getOperand ( k ) . getType ( ) ; } else if ( I -> getOperand ( k ) . isSymbol ( ) ) { tempOs << <STR_LIT> << I -> getOperand ( k ) . getSymbolName ( ) << <STR_LIT> << I -> getOperand ( k ) . getType ( ) ; } else if ( I -> getOperand ( k ) . isMCSymbol ( ) ) { tempOs << <STR_LIT> << I -> getOperand ( k ) . getSymbolName ( ) << <STR_LIT> << I -> getOperand ( k ) . getSymbolName ( ) ; } else if ( I -> getOperand ( k ) . isFPImm ( ) ) { tempOs << <STR_LIT> << I -> getOperand ( k ) . getFPImm ( ) << <STR_LIT> << I -> getOperand ( k ) . getType ( ) ; } else if ( I -> getOperand ( k ) . isBlockAddress ( ) ) { tempOs << <STR_LIT> << I -> getOperand ( k ) . getBlockAddress ( ) << <STR_LIT> << I -> getOperand ( k ) . getType ( ) ; } else if ( I -> getOperand ( k ) . isGlobal ( ) ) { tempOs << <STR_LIT> << I -> getOperand ( k ) . getGlobal ( ) << <STR_LIT> << I -> getOperand ( k ) . getType ( ) ;


<s> unsigned EncodedBytes = <NUM_LIT> ; const MachineOperand & CalleeMO = Opers . getCallTarget ( ) ; if ( CalleeMO . isImm ( ) ) { uint64_t CallTarget = CalleeMO . getImm ( ) ; if ( CallTarget ) { unsigned ScratchIdx = - <NUM_LIT> ; unsigned ScratchReg = <NUM_LIT> ; do { ScratchIdx = Opers . getNextScratchIdx ( ScratchIdx + <NUM_LIT> ) ; ScratchReg = MI . getOperand ( ScratchIdx ) . getReg ( ) ; } while ( ScratchReg == <STR_LIT> ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( CallTarget & <NUM_LIT> ) ) ; EncodedBytes += <NUM_LIT> ; if ( CallTarget >> <NUM_LIT> ) { EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchReg ) . addImm ( CallTarget >> <NUM_LIT> ) ) ; EncodedBytes += <NUM_LIT> ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx ) : MCII ( mcii ) , CTX ( ctx ) {


<s> unsigned Wtemp3 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wtemp2 ) . addReg ( Wtemp ) . addReg ( Rtemp2 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wtemp3 ) . addReg ( Wtemp2 ) . addReg ( Rtemp2 ) . addImm ( <NUM_LIT> ) ; WPHI = Wtemp3 ; } if ( IsFGR64 ) { unsigned Wtemp2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wtemp2 ) . addReg ( WPHI ) . addReg ( WPHI ) ; WPHI = Wtemp2 ; } BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( WPHI ) . addReg ( WPHI ) ; MI . eraseFromParent ( ) ; return BB ;


<s> bool <ISA_LIT>O0PreLegalizerCombiner :: runOnMachineFunction ( MachineFunction & MF ) { if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ;

auto & TPC = getAnalysis < TargetPassConfig > ( ) ;


<s> bool hasLFIWAX ( ) const { return HasLFIWAX ;


<s> bool <ISA_LIT>InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { switch ( MI . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( IsSMRD != <ISA_LIT>InstrInfo :: isSMRD ( * MI ) ) break ; addClauseInst ( * MI ) ; } if ( ClauseDefs . none ( ) ) return <NUM_LIT> ;

if ( MEM -> mayStore ( ) ) return <NUM_LIT> ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > A ( The<ISA_LIT>Target ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > B ( The<ISA_LIT>64Target ) ;


<s> case _UVRSC_VFP : { _uw start = discriminator >> <NUM_LIT> ; _uw count = discriminator & <NUM_LIT> ; struct vfp_regs tmp ; _uw * sp ; _uw * dest ; if ( ( representation != _UVRSD_VFPX && representation != _UVRSD_DOUBLE ) || start + count > <NUM_LIT> ) return _UVRSR_FAILED ; if ( vrs -> demand_save_flags & DEMAND_SAVE_VFP ) { vrs -> demand_save_flags &= ~ DEMAND_SAVE_VFP ; __gnu_Unwind_Save_VFP ( & vrs -> vfp ) ; } __gnu_Unwind_Save_VFP ( & tmp ) ; sp = ( _uw * ) vrs -> core . r [ R_SP ] ; dest = ( _uw * ) & tmp . d [ start ] ; count *= <NUM_LIT> ; while ( count -- ) * ( dest ++ ) = * ( sp ++ ) ; if ( representation == _UVRSD_VFPX ) sp ++ ;


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; auto GetPackNode = [ ] ( SDValue V ) { V = peekThroughBitcasts ( V ) ; return V . getOpcode ( ) == <STR_LIT> ? V : SDValue ( ) ; } ; if ( SDValue V1Pack = GetPackNode ( V1 ) ) if ( SDValue V2Pack = GetPackNode ( V2 ) ) return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V1Pack . getOperand ( <NUM_LIT> ) : V1Pack . getOperand ( <NUM_LIT> ) , Mask [ <NUM_LIT> ] == <NUM_LIT> ? V2Pack . getOperand ( <NUM_LIT> ) : V2Pack . getOperand ( <NUM_LIT> ) ) ) ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ;

if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ;


<s> if ( ! ( LM & <NUM_LIT> ) && ( Bank < NUM_VGPR_BANKS ) ) { if ( countPopulation ( LM ) >= NUM_VGPR_BANKS ) continue ; ShiftedBank = ( Bank + countTrailingZeros ( LM ) ) % NUM_VGPR_BANKS ; } else if ( ! ( LM & <NUM_LIT> ) && ( Bank >= SGPR_BANK_OFFSET ) ) { if ( countPopulation ( LM ) / <NUM_LIT> >= NUM_SGPR_BANKS ) continue ; ShiftedBank = SGPR_BANK_OFFSET + ( Bank - SGPR_BANK_OFFSET + ( countTrailingZeros ( LM ) >> <NUM_LIT> ) ) % NUM_SGPR_BANKS ; } } unsigned Mask = getRegBankMask ( R , Op . getSubReg ( ) , ( Reg == R ) ? ShiftedBank : - <NUM_LIT> ) ; StallCycles += countPopulation ( UsedBanks & Mask ) ; UsedBanks |= Mask ; OperandMasks . push_back ( OperandMask ( Op . getReg ( ) , Op . getSubReg ( ) , Mask ) ) ;


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_i32gather_epi64 ( long long int const * base , __m128i index , const int scale ) { __v2di src = __extension__ ( __v2di ) { <NUM_LIT> , <NUM_LIT> } ; __v2di mask = __extension__ ( __v2di ) { ~ <NUM_LIT> , ~ <NUM_LIT> } ;

return ( __m128i ) __builtin_ia32_gathersiv2di ( src , base , ( __v4si ) index , mask , scale ) ;


<s> if ( ! MCSDX . check ( ) ) { errInfo . setError ( <STR_LIT> ) ; errInfo . setShuffleError ( MCSDX . getError ( ) ) ; addErrInfo ( errInfo ) ; return false ; }


<s> return hasTinyEncoding ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DataLayout ( <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) {


<s> assert ( isVPTPred ( ) && <STR_LIT> ) ;


<s> void EncodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups ) const {


<s> return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> int CFGStructurizer < PassT > :: patternMatch ( BlockT * curBlk ) { int numMatch = <NUM_LIT> ; int curMatch ; if ( DEBUGME ) { errs ( ) << <STR_LIT> << curBlk -> getNumber ( ) << <STR_LIT> ;


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( VEXPANDMask , DL , IntegerType ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ;

SDValue VMask = getMaskNode ( MaskNode , <STR_LIT> ( <STR_LIT> , NumElts ) , Subtarget , DAG , DL ) ;


<s> COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ;

OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ;


<s> void <ISA_LIT>DbgInfo :: EmitFileDirective ( Module & M ) { GlobalVariable * CU = M . getNamedGlobal ( <STR_LIT> ) ; if ( CU ) { DICompileUnit DIUnit ( CU ) ; std :: string Dir , FN ; O << <STR_LIT> << DIUnit . getDirectory ( Dir ) << <STR_LIT> << DIUnit . getFilename ( FN ) << <STR_LIT> ; }


<s> if ( SUnit * SU = Top . pickOnlyChoice ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; IsTopNode = true ; return SU ; } SchedCandidate BotCand ; CandResult BotResult = pickNodeFromQueue ( Bot , DAG -> getBotRPTracker ( ) , BotCand ) ; assert ( BotResult != NoCand && <STR_LIT> ) ; if ( BotResult == SingleExcess || BotResult == SingleCritical ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; IsTopNode = false ; return BotCand . SU ; } SchedCandidate TopCand ; CandResult TopResult = pickNodeFromQueue ( Top , DAG -> getTopRPTracker ( ) , TopCand ) ; assert ( TopResult != NoCand && <STR_LIT> ) ; if ( TopResult == SingleExcess || TopResult == SingleCritical ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ; return <NUM_LIT> ;


<s> unsigned GCNSubtarget :: getConstantBusLimit ( unsigned Opcode ) const { if ( getGeneration ( ) < GFX10 ) return <NUM_LIT> ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; }


<s> rtx inner = XEXP ( addr , <NUM_LIT> ) ; if ( GET_CODE ( inner ) == UNSPEC && XINT ( inner , <NUM_LIT> ) == UNSPEC_GOT ) return XVECEXP ( inner , <NUM_LIT> , <NUM_LIT> ) ;


<s> <STR_LIT> ExtType = LD -> getExtensionType ( ) ; bool InsertTo64 = false ; if ( VT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else if ( ExtType == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = true ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> || VT . is64BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT . is128BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else return nullptr ; SDValue Chain = LD -> getChain ( ) ; SDValue Base = LD -> getBasePtr ( ) ; ConstantSDNode * OffsetOp = cast < ConstantSDNode > ( LD -> getOffset ( ) ) ; int OffsetVal = ( int ) OffsetOp -> getZExtValue ( ) ; SDLoc dl ( N ) ; SDValue Offset = CurDAG -> getTargetConstant ( OffsetVal , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Base , Offset , Chain } ; SDNode * Res = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , DstVT , <STR_LIT> , Ops ) ; Done = true ; SDValue LoadedVal = SDValue ( Res , <NUM_LIT> ) ; if ( InsertTo64 ) {

SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ;


<s> int64_t Offset = Addr . getOffset ( ) ; if ( ( ( Offset < <NUM_LIT> ) || ( Offset & ( ScaleFactor - <NUM_LIT> ) ) ) && ! isInt < <NUM_LIT> > ( Offset ) ) ImmediateOffsetNeedsLowering = true ; else if ( Offset > <NUM_LIT> && ! ( Offset & ( ScaleFactor - <NUM_LIT> ) ) && ! isUInt < <NUM_LIT> > ( Offset / ScaleFactor ) ) ImmediateOffsetNeedsLowering = true ; if ( ! ImmediateOffsetNeedsLowering && Addr . getOffset ( ) && Addr . getOffsetReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( Addr . isRegBase ( ) && Addr . getOffsetReg ( ) && ! Addr . getReg ( ) ) RegisterOffsetNeedsLowering = true ; if ( ( ImmediateOffsetNeedsLowering || Addr . getOffsetReg ( ) ) && Addr . isFIBase ( ) ) { unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( Addr . getFI ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( ResultReg ) ; } if ( RegisterOffsetNeedsLowering ) { unsigned ResultReg = <NUM_LIT> ; if ( Addr . getReg ( ) ) { if ( Addr . getExtendType ( ) == <STR_LIT> || Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitAddSub_rx ( true , <STR_LIT> , Addr . getReg ( ) , false , Addr . getOffsetReg ( ) , false , Addr . getExtendType ( ) , Addr . getShift ( ) ) ; else ResultReg = emitAddSub_rs ( true , <STR_LIT> , Addr . getReg ( ) , false , Addr . getOffsetReg ( ) , false , <STR_LIT> , Addr . getShift ( ) ) ;


<s> return const_cast < <ISA_LIT>TargetLowering * > ( & TLInfo ) ;


<s> CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue ; if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( Subtarget , DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { const unsigned XLenInBytes = <NUM_LIT> ; const MVT XLenVT = <STR_LIT> ; ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) { const Register Reg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( ArgRegs [ I ] , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; OutChains . push_back ( Store ) ;


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; if ( Desc . getSize ( ) != <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } const uint32_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; emitConstant ( Binary , Desc . getSize ( ) , OS ) ; ++ MCNumEmitted ;


<s> if ( arc_hazard ( insn , succ0 ) ) { emit_insn_before ( gen_nopv ( ) , succ0 ) ;


<s> __o = __builtin_aarch64_set_qregciv4si ( __o , ( int32x4_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> void addRegGxRCNoR0Operands ( MCInst & Inst , unsigned N ) const { if ( is<ISA_LIT>64 ( ) ) addRegG8RCNoX0Operands ( Inst , N ) ;

else addRegGPRCNoR0Operands ( Inst , N ) ;


<s> Value * OldSP = getReg ( <STR_LIT> ) ; Value * OpSizeVal = ConstantInt :: get ( IntegerType :: get ( * Ctx , OldSP -> getType ( ) -> getIntegerBitWidth ( ) ) , OpSize ) ; Value * NewSP = Builder -> CreateSub ( OldSP , OpSizeVal ) ; Value * SPPtr = Builder -> CreateIntToPtr ( NewSP , Val -> getType ( ) -> getPointerTo ( ) ) ; Builder -> CreateStore ( Val , SPPtr ) ; setReg ( <STR_LIT> , NewSP ) ;


<s> if ( isPackingSupportOpcode ( Op . getOpcode ( ) ) ) return Legal ;

if ( isVVPOr<ISA_LIT>C ( Op . getOpcode ( ) ) ) return Custom ;


<s> SDValue <ISA_LIT>TargetLowering :: EmitHigh ( SDValue Op , SelectionDAG & DAG ) const {


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> while ( auto * DTy = dyn_cast < DIDerivedType > ( Ty ) ) { if ( ! SkipDIDerivedTag ( DTy -> getTag ( ) ) ) break ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) {


<s> SDValue <ISA_LIT>TargetLowering :: performClassCombine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; SDValue Mask = N -> getOperand ( <NUM_LIT> ) ;

if ( const ConstantSDNode * CMask = dyn_cast < ConstantSDNode > ( Mask ) ) {


<s> explicit <ISA_LIT>16FrameLowering ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>FrameLowering ( STI ) {


<s> } case <STR_LIT> : { if ( ! MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) return false ; break ; } case <STR_LIT> : { unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg != <STR_LIT> ) return false ; Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; isLdStMul = true ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { OpNum = <NUM_LIT> ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> && ( Entry . WideOpc == <STR_LIT> || Entry . WideOpc == <STR_LIT> ) ) { Opc = Entry . NarrowOpc2 ; OpNum = <NUM_LIT> ; } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul = true ; break ; } } unsigned OffsetReg = <NUM_LIT> ; bool OffsetKill = false ; bool OffsetInternal = false ; if ( HasShift ) { OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; OffsetInternal = MI -> getOperand ( <NUM_LIT> ) . isInternalRead ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; } unsigned OffsetImm = <NUM_LIT> ; if ( HasImmOffset ) { OffsetImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned MaxOffset = ( ( <NUM_LIT> << ImmLimit ) - <NUM_LIT> ) * Scale ; if ( ( OffsetImm & ( Scale - <NUM_LIT> ) ) || OffsetImm > MaxOffset ) return false ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , TII -> get ( Opc ) ) ; if ( Entry . WideOpc == <STR_LIT> ) MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: Define | RegState :: Dead ) ; if ( ! isLdStMul ) { MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( HasImmOffset ) MIB . addImm ( OffsetImm / Scale ) ; assert ( ( ! HasShift || OffsetReg ) && <STR_LIT> ) ; if ( HasOffReg ) MIB . addReg ( OffsetReg , getKillRegState ( OffsetKill ) | getInternalReadRegState ( OffsetInternal ) ) ; } for ( unsigned e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . addOperand ( MI -> getOperand ( OpNum ) ) ; MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ;

DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ;


<s> addPass ( create<ISA_LIT>PreLegalizerCombiner ( ) ) ; if ( EnableGISelLoadStoreOptPreLegal ) addPass ( new LoadStoreOpt ( ) ) ; }


<s> if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; EVT VT = Extract -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! VT . isSimple ( ) || ! ( VT . getVectorElementType ( ) . getSizeInBits ( ) > <NUM_LIT> ) ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . useBWIRegs ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX ( ) ) RegSize = <NUM_LIT> ; if ( RegSize / VT . getVectorNumElements ( ) < <NUM_LIT> ) return SDValue ( ) ; unsigned BinOp = <NUM_LIT> ; SDValue Root = matchBinOpReduction ( Extract , BinOp , { <STR_LIT> } ) ; if ( Root && ( Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> ) ) Root = Root . getOperand ( <NUM_LIT> ) ; if ( ! Root || ( Root . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ;


<s> void AMDGPUPassConfig :: addCodeGenPrepare ( ) { const AMDGPUSubtarget & ST = * getAMDGPUTargetMachine ( ) . getSubtargetImpl ( ) ; if ( ST . isPromoteAllocaEnabled ( ) ) { addPass ( createAMDGPUPromoteAlloca ( ST ) ) ; addPass ( createSROAPass ( ) ) ; } TargetPassConfig :: addCodeGenPrepare ( ) ;


<s> int OMod ; std :: tie ( RegOp , OMod ) = isOMod ( MI ) ; if ( OMod == <STR_LIT> || ! RegOp -> isReg ( ) || RegOp -> getSubReg ( ) != <STR_LIT> || ! MRI -> hasOneNonDBGUser ( RegOp -> getReg ( ) ) ) return false ; MachineInstr * Def = MRI -> getVRegDef ( RegOp -> getReg ( ) ) ; MachineOperand * DefOMod = TII -> getNamedOperand ( * Def , <STR_LIT> :: omod ) ; if ( ! DefOMod || DefOMod -> getImm ( ) != <STR_LIT> ) return false ;

if ( TII -> hasModifiersSet ( * Def , <STR_LIT> :: clamp ) ) return false ;


<s> void setVarArgsFrameIndex ( int idx ) {


<s> for ( i = <NUM_LIT> ; i < nunits ; i ++ ) { element = CONST_VECTOR_ELT ( op , i ) ; if ( ! CONST_INT_P ( element ) ) return false ; if ( value != INTVAL ( element ) ) return false ; } } else if ( CONST_INT_P ( op ) ) { if ( ! SCALAR_INT_MODE_P ( mode ) ) return false ; value = INTVAL ( op ) ; if ( ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) { if ( ! ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] & RELOAD_REG_VALID ) ) return false ; if ( EASY_VECTOR_15 ( value ) ) return false ; } } else return false ; if ( ( mode == V4SImode || mode == V8HImode ) && ! IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) && EASY_VECTOR_15 ( value ) ) return false ; if ( mode == V16QImode ) * num_insns_ptr = <NUM_LIT> ;

else if ( IN_RANGE ( value , - <NUM_LIT> , <NUM_LIT> ) ) * num_insns_ptr = <NUM_LIT> ;


<s> rtx op3 = operands [ <NUM_LIT> ] ; if ( GET_CODE ( op0 ) == SUBREG ) op0 = SUBREG_REG ( op0 ) ; if ( GET_CODE ( op1 ) == SUBREG ) op1 = SUBREG_REG ( op1 ) ; if ( GET_CODE ( op2 ) == SUBREG ) op2 = SUBREG_REG ( op2 ) ; if ( GET_CODE ( op1 ) == REG ) regs ++ ; if ( GET_CODE ( op2 ) == REG ) regs ++ ; if ( regs != <NUM_LIT> ) return <NUM_LIT> ; if ( GET_CODE ( op0 ) == REG && GET_CODE ( op3 ) == MEM && reg_mentioned_p ( op0 , XEXP ( op3 , <NUM_LIT> ) ) ) return <NUM_LIT> ;


<s> if ( reg == <STR_LIT> ) return false ; if ( ! ImmInRange ( MI , Entry ) ) return false ; if ( ReduceToLwp && ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; return true ;


<s> EVT VT = Op . getValueType ( ) ; if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V1 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V2 ; else if ( ( BVN = dyn_cast < BuildVectorSDNode > ( V2 . getNode ( ) ) ) && isCommonSplatElement ( BVN ) ) V3 = V1 ; else return SDValue ( ) ; SDValue CommonSplat = BVN -> getOperand ( <NUM_LIT> ) ; SDValue Result ; if ( VT . getSimpleVT ( ) == <STR_LIT> ) { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ; case <STR_LIT> : Result = DAG . getNode ( <STR_LIT> , dl , VT , V3 , CommonSplat ) ; break ;


<s> default : return Op ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> size_t Instruction = <NUM_LIT> ; size_t Last = <ISA_LIT>MCInstrInfo :: bundleSize ( HMB ) - <NUM_LIT> ; for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; verifyInstructionPredicates ( HMI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits ( Instruction , Last , HMB , HMI ) , Instruction ) ; * Extended = <ISA_LIT>MCInstrInfo :: isImmext ( HMI ) ; * Addend += HEXAGON_INSTR_SIZE ;


<s> B2IMap Bool2IntMap ; bool Changed = false ; for ( auto & BB : F ) { for ( auto & I : BB ) { if ( ReturnInst * R = dyn_cast < ReturnInst > ( & I ) ) if ( F . getReturnType ( ) -> isIntegerTy ( <NUM_LIT> ) ) Changed |= runOnUse ( R -> getOperandUse ( <NUM_LIT> ) , PromotablePHINodes , Bool2IntMap ) ; if ( CallInst * CI = dyn_cast < CallInst > ( & I ) ) for ( auto & U : CI -> operands ( ) ) if ( U -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) Changed |= runOnUse ( U , PromotablePHINodes , Bool2IntMap ) ; } }


<s> dst = JUMP_LABEL ( insn ) ; src = NULL_RTX ; } switch ( num ) { case COND_MOV_INSN : case COND_CLR_INSN : if ( cond ) c_insn = gen_movt0 ( dst , src , dst ) ; else c_insn = gen_movt0 ( dst , dst , src ) ; break ; case COND_INC_INSN : if ( cond ) c_insn = gen_incscc ( dst , dst ) ; else c_insn = gen_incscc_false ( dst , dst ) ; break ; case COND_DEC_INSN : if ( cond ) c_insn = gen_decscc ( dst , dst ) ; else c_insn = gen_decscc_false ( dst , dst ) ; break ; case COND_BRANCH_INSN : if ( cond ) c_insn = gen_branch_true ( dst ) ; else c_insn = gen_branch_false ( dst ) ; break ; default : return NULL ; } if ( rtx_length [ GET_CODE ( c_insn ) ] >= <NUM_LIT> && rtx_length [ GET_CODE ( insn ) ] >= <NUM_LIT> ) { REG_NOTES ( c_insn ) = REG_NOTES ( insn ) ;


<s> return isMem256 ( ) && isMemIndexReg ( <STR_LIT> , <STR_LIT> ) ;


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIx ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) . addMetadata ( MDPtr ) ;


<s> FullFS += FS ; ParseSubtargetFeatures ( GPU , GPU , FullFS ) ; if ( Gen == <ISA_LIT>Subtarget :: INVALID ) { Gen = TT . getOS ( ) == Triple :: AMDHSA ? <ISA_LIT>Subtarget :: SEA_ISLANDS : <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ; } assert ( ! hasFP64 ( ) || ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) ) ; assert ( hasAddr64 ( ) || hasFlat ( ) ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) && ! FlatForGlobal ) { ToggleFeature ( <STR_LIT> ) ; FlatForGlobal = true ; }

if ( ! hasFlat ( ) && ! FS . contains ( <STR_LIT> ) && FlatForGlobal ) {


<s> static bool vax_mode_dependent_address_p ( const_rtx x , addr_space_t as ATTRIBUTE_UNUSED ) { rtx xfoo0 , xfoo1 ; if ( GET_CODE ( x ) != PLUS ) return false ; xfoo0 = XEXP ( x , <NUM_LIT> ) ; xfoo1 = XEXP ( x , <NUM_LIT> ) ; if ( CONST_INT_P ( xfoo0 ) && REG_P ( xfoo1 ) ) return false ; if ( CONST_INT_P ( xfoo1 ) && REG_P ( xfoo0 ) ) return false ; if ( ! flag_pic && CONSTANT_ADDRESS_P ( xfoo0 ) && REG_P ( xfoo1 ) ) return false ; if ( ! flag_pic && CONSTANT_ADDRESS_P ( xfoo1 ) && REG_P ( xfoo0 ) ) return false ; return true ;


<s> for ( int i = ( <NUM_LIT> - <NUM_LIT> ) * <NUM_LIT> ; i >= <NUM_LIT> ; i -= <NUM_LIT> ) Ostream << static_cast < char > ( ( Value >> i ) & <NUM_LIT> ) ;


<s> void printARI16Mem ( const MCInst * MI , int opNum , raw_ostream & O ) {


<s> unsigned <ISA_LIT>AsmParser :: checkTargetMatchPredicate ( MCInst & Inst ) { unsigned Opc = Inst . getOpcode ( ) ; const MCInstrDesc & MCID = MII . get ( Opc ) ; if ( ForcedVEXEncoding == VEXEncoding_EVEX && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) return Match_Unsupported ; if ( ( ForcedVEXEncoding == VEXEncoding_VEX || ForcedVEXEncoding == VEXEncoding_VEX2 || ForcedVEXEncoding == VEXEncoding_VEX3 ) && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) return Match_Unsupported ; if ( MCID . TSFlags & <STR_LIT> && ( ForcedVEXEncoding != VEXEncoding_VEX && ForcedVEXEncoding != VEXEncoding_VEX2 && ForcedVEXEncoding != VEXEncoding_VEX3 ) ) return Match_Unsupported ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { switch ( getLexer ( ) . getKind ( ) ) { case AsmToken :: Identifier : { StringRef Tok = Parser . getTok ( ) . getString ( ) ; if ( Tok == Name ) { if ( Tok == <STR_LIT> && isGFX9 ( ) ) Error ( S , <STR_LIT> ) ; if ( Tok == <STR_LIT> && ! isGFX9 ( ) && ! isGFX10 ( ) ) Error ( S , <STR_LIT> ) ; Bit = <NUM_LIT> ; Parser . Lex ( ) ; } else if ( Tok . startswith ( <STR_LIT> ) && Tok . endswith ( Name ) ) { Bit = <NUM_LIT> ; Parser . Lex ( ) ; } else { return MatchOperand_NoMatch ; } break ; } default : return MatchOperand_NoMatch ;


<s> return Error ( NameLoc , <STR_LIT> ) ; } SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( MCConstantExpr :: Create ( Cc , getContext ( ) ) , NameLoc , E ) ) ; } else { return parseMathOperation ( Name , NameLoc , Operands ) ; } Format = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( <STR_LIT> ( Format , NameLoc ) ) ; } setFpFormat ( Format ) ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . EatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ;


<s> return ( uint16x8_t ) __builtin_neon_vdup_lanev8hi ( ( int16x4_t ) __a , __b ) ;


<s> static void printExpr ( const MCExpr * Expr , raw_ostream & OS ) { int Offset = <NUM_LIT> ; const MCSymbolRefExpr * SRE ; if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { SRE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else { SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ;


<s> void Note ( SMLoc L , const Twine & Msg , ArrayRef < SMRange > Ranges = None ) { return Parser . Note ( L , Msg , Ranges ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const {

OS << '$' << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ;


<s> __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv8qi ( ( const __builtin_aarch64_simd_qi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ;


<s> static uint64_t getNearPower2 ( uint64_t x ) { if ( ! x ) return <NUM_LIT> ;

unsigned at = CountLeadingZeros_64 ( x ) ;


<s> Value * <ISA_LIT>IREmitter :: visitCOPY_STRUCT_BYVAL ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const auto * RegInfo = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ;

return MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MFI -> hasStackMap ( ) || MFI -> hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ;


<s> if ( ( ( Subtarget -> hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ;

return OptimizeConditionalInDecrement ( N , DAG ) ;


<s> unsigned getVGPRAllocGranule ( ) const { return <STR_LIT> :: getVGPRAllocGranule ( MCSubtargetInfo :: getFeatureBits ( ) ) ;


<s> SDValue Addr = N -> getOperand ( <NUM_LIT> ) ; if ( Addr -> getOpcode ( ) != <STR_LIT> ) return <NUM_LIT> ; unsigned IntNo = cast < ConstantSDNode > ( Addr -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IntNo != <STR_LIT> ) return <NUM_LIT> ; SDValue nextAddr = Addr -> getOperand ( <NUM_LIT> ) ; SDValue CheckEventChainOut ( Addr . getNode ( ) , <NUM_LIT> ) ; if ( ! CheckEventChainOut . use_empty ( ) ) { SDValue CheckEventChainIn = Addr -> getOperand ( <NUM_LIT> ) ; SDValue NewChain = replaceInChain ( CurDAG , Chain , CheckEventChainOut , CheckEventChainIn ) ; if ( ! NewChain . getNode ( ) ) return <NUM_LIT> ; Chain = NewChain ; } SDValue constOne = getI32Imm ( <NUM_LIT> ) ; SDValue Glue = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , constOne , Chain ) , <NUM_LIT> ) ; Glue = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , constOne , Glue ) , <NUM_LIT> ) ; if ( nextAddr -> getOpcode ( ) == <STR_LIT> && nextAddr -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> ) { return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , nextAddr -> getOperand ( <NUM_LIT> ) , Glue ) ;


<s> } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Imm . Value ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Imm . Value ) ) if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ;


<s> static tree nvptx_get_worker_red_addr ( tree type , tree offset ) { machine_mode mode = TYPE_MODE ( type ) ; tree fndecl = nvptx_builtin_decl ( NVPTX_BUILTIN_WORKER_ADDR , true ) ; tree size = build_int_cst ( unsigned_type_node , GET_MODE_SIZE ( mode ) ) ; tree align = build_int_cst ( unsigned_type_node , GET_MODE_ALIGNMENT ( mode ) / BITS_PER_UNIT ) ;

tree call = build_call_expr ( fndecl , <NUM_LIT> , offset , size , align ) ;


<s> return ( ( imm <= <ISA_LIT>GNULDBackend :: MAX_ADRP_IMM ) && ( imm >= <ISA_LIT>GNULDBackend :: MIN_ADRP_IMM ) ) ;


<s> if ( hasSameVTYPE ( Require ) ) return true ;

if ( Require . MaskRegOp && hasSameVLMAX ( Require ) && TailAgnostic == Require . TailAgnostic && MaskAgnostic == Require . MaskAgnostic ) return true ;


<s> auto TypeKind = StringSwitch < RuntimeMD :: KernelArg :: TypeKind > ( BaseTypeName ) . Case ( <STR_LIT> , RuntimeMD :: KernelArg :: Sampler ) . Case ( <STR_LIT> , RuntimeMD :: KernelArg :: Queue ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , RuntimeMD :: KernelArg :: Image ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , RuntimeMD :: KernelArg :: Image ) . Cases ( <STR_LIT> , <STR_LIT> , RuntimeMD :: KernelArg :: Image ) . Default ( isa < PointerType > ( T ) ? RuntimeMD :: KernelArg :: Pointer : RuntimeMD :: KernelArg :: Value ) ; emitRuntimeMDIntValue ( * OutStreamer , RuntimeMD :: KeyArgTypeKind , TypeKind , <NUM_LIT> ) ; emitRuntimeMDIntValue ( * OutStreamer , RuntimeMD :: KeyArgValueType , getRuntimeMDValueType ( T , BaseTypeName ) , <NUM_LIT> ) ; auto AccQual = cast < MDString > ( F . getMetadata ( <STR_LIT> ) -> getOperand ( I ) ) -> getString ( ) ; auto AQ = StringSwitch < RuntimeMD :: KernelArg :: AccessQualifer > ( AccQual ) . Case ( <STR_LIT> , RuntimeMD :: KernelArg :: ReadOnly ) . Case ( <STR_LIT> , RuntimeMD :: KernelArg :: WriteOnly ) . Case ( <STR_LIT> , RuntimeMD :: KernelArg :: ReadWrite ) . Default ( RuntimeMD :: KernelArg :: None ) ; emitRuntimeMDIntValue ( * OutStreamer , RuntimeMD :: KeyArgAccQual , AQ , <NUM_LIT> ) ; if ( auto * PT = dyn_cast < PointerType > ( T ) ) { emitRuntimeMDIntValue ( * OutStreamer , RuntimeMD :: KeyArgAddrQual , PT -> getAddressSpace ( ) , <NUM_LIT> ) ; } OutStreamer -> EmitIntValue ( RuntimeMD :: KeyArgEnd , <NUM_LIT> ) ; }

if ( auto RWGS = F . getMetadata ( <STR_LIT> ) ) {


<s> for ( reg = * regp ; reg <= lim ; ++ reg ) {

if ( reg -> where == UNW_WHERE_SPILL_HOME ) {


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = ~ CE -> getValue ( ) ; return ( Value >= <NUM_LIT> && Value < <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> && ( Value & <NUM_LIT> ) == <NUM_LIT> ) || ( Value >= <NUM_LIT> && Value <= <NUM_LIT> && ( Value & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> } else if ( sOp . isReg ( ) ) { instb -> addOperand ( MCOperand :: createReg ( sOp . getReg ( ) ) ) ; } else if ( sOp . isMBB ( ) ) { MCOperand MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( sOp . getMBB ( ) -> getSymbol ( ) , this -> OutContext ) ) ; instb -> addOperand ( MCOp ) ; } else if ( sOp . isBlockAddress ( ) ) { MCSymbol * Sym = GetBlockAddressSymbol ( sOp . getBlockAddress ( ) ) ; MCOperand MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( Sym , this -> OutContext ) ) ; instb -> addOperand ( MCOp ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } } MCB . addOperand ( MCOperand :: createInst ( instb ) ) ; } } OutStreamer -> EmitInstruction ( MCB , getSubtargetInfo ( ) ) ; return ; } MCInst inst ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : return ; default : inst . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { MachineOperand sOp = MI -> getOperand ( i ) ; if ( sOp . isImm ( ) ) { inst . addOperand ( MCOperand :: createImm ( sOp . getImm ( ) ) ) ; } else if ( sOp . isFPImm ( ) ) { APFloat Val = sOp . getFPImm ( ) -> getValueAPF ( ) ; inst . addOperand ( MCOperand :: createImm ( Val . bitcastToAPInt ( ) . getZExtValue ( ) ) ) ; } else if ( sOp . isReg ( ) ) { inst . addOperand ( MCOperand :: createReg ( sOp . getReg ( ) ) ) ; } else if ( sOp . isMBB ( ) ) { MCOperand MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( sOp . getMBB ( ) -> getSymbol ( ) , this -> OutContext ) ) ; inst . addOperand ( MCOp ) ; } else if ( sOp . isBlockAddress ( ) ) { MCSymbol * Sym = GetBlockAddressSymbol ( sOp . getBlockAddress ( ) ) ; MCOperand MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( Sym , this -> OutContext ) ) ; inst . addOperand ( MCOp ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; if ( ! Subtarget . is64Bit ( ) ) { getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 } , { p0 } ) . maxScalar ( <NUM_LIT> , s32 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( { G_SHL , G_LSHR , G_ASHR , G_SDIV } ) . legalFor ( { s8 , s16 , s32 } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) ; } setAction ( { G_BRCOND , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 } ) { setAction ( { G_ZEXT , Ty } , Legal ) ; setAction ( { G_SEXT , Ty } , Legal ) ; setAction ( { G_ANYEXT , Ty } , Legal ) ; } setAction ( { G_ANYEXT , s128 } , Legal ) ; setAction ( { G_ICMP , s1 } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { G_ICMP , <NUM_LIT> , Ty } , Legal ) ; for ( const auto & Ty : { s16 , s32 , s64 } ) { setAction ( { G_MERGE_VALUES , Ty } , Legal ) ; setAction ( { G_UNMERGE_VALUES , <NUM_LIT> , Ty } , Legal ) ; } for ( const auto & Ty : { s8 , s16 , s32 } ) { setAction ( { G_MERGE_VALUES , <NUM_LIT> , Ty } , Legal ) ; setAction ( { G_UNMERGE_VALUES , Ty } , Legal ) ; }


<s> SDValue FI = DAG . getFrameIndex ( VarArgsFrameIndex , getPointerTy ( ) ) ;

const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> std :: swap ( LHS , RHS ) ; case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; case <STR_LIT> : TCC = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } <ISA_LIT>CC = DAG . getConstant ( TCC , <STR_LIT> ) ;

if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ;


<s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const {


<s> static const std :: pair < unsigned , std :: pair < unsigned , unsigned >> VFMKMap [ ] = { { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , } ; unsigned Opcode = MI . getOpcode ( ) ; const auto * Found = llvm :: find_if ( VFMKMap , [ & ] ( auto P ) { return P . first == Opcode ; } ) ;

if ( Found == std :: end ( VFMKMap ) ) report_fatal_error ( <STR_LIT> ) ;


<s> getReservedRegs ( const MachineFunction & MF ) const { const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> m -> fs . cfa_offset = m -> fs . sp_offset ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , m -> fs . sp_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } ix86_add_cfa_restore_note ( insn , hard_frame_pointer_rtx , m -> fs . fp_offset ) ;


<s> const Align ABITypeAlign = DL . getABITypeAlign ( ArgTy ) ; if ( ! ArgTy -> isVectorTy ( ) ) return ABITypeAlign ;

return std :: min ( ABITypeAlign , DL . getStackAlignment ( ) ) ;


<s> return create<ISA_LIT>ObjectWriter ( OSABI ) ;


<s> static SDValue PerformUMLALCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { if ( ! Subtarget -> hasV6Ops ( ) || ! Subtarget -> hasDSP ( ) ) return SDValue ( ) ; SDNode * AddcNode = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDNode * AddeNode = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ( AddcNode -> getOpcode ( ) == <STR_LIT> ) && ( AddeNode -> getOpcode ( ) == <STR_LIT> ) && isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) && isNullConstant ( AddeNode -> getOperand ( <NUM_LIT> ) ) && ( AddeNode -> getOperand ( <NUM_LIT> ) . getNode ( ) == AddcNode ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , AddcNode -> getOperand ( <NUM_LIT> ) , AddcNode -> getOperand ( <NUM_LIT> ) } ) ;


<s> void th_mempair_save_restore_regs ( rtx operands [ <NUM_LIT> ] , bool load_p , machine_mode mode ) {

gcc_assert ( th_mempair_operands_p ( operands , load_p , mode ) ) ;


<s> static inline void setMask ( const MachineRegisterInfo & MRI , const <ISA_LIT>RegisterInfo * SRI , unsigned Reg , LaneBitmask & PrevMask , LaneBitmask NewMask , unsigned & SGPRs , unsigned & VGPRs ) { int NewRegs = countPopulation ( NewMask . getAsInteger ( ) ) - countPopulation ( PrevMask . getAsInteger ( ) ) ; if ( SRI -> isSGPRReg ( MRI , Reg ) ) SGPRs += NewRegs ; if ( SRI -> isVGPR ( MRI , Reg ) ) VGPRs += NewRegs ; assert ( ( int ) SGPRs >= <NUM_LIT> && ( int ) VGPRs >= <NUM_LIT> ) ; PrevMask = NewMask ;


<s> EVT MemEltVT = Load -> getMemoryVT ( ) . getVectorElementType ( ) ; EVT EltVT = Op . getValueType ( ) . getVectorElementType ( ) ; EVT PtrVT = Load -> getBasePtr ( ) . getValueType ( ) ; unsigned NumElts = Load -> getMemoryVT ( ) . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Loads ; SDLoc SL ( Op ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Load -> getBasePtr ( ) , DAG . getConstant ( i * ( MemEltVT . getSizeInBits ( ) / <NUM_LIT> ) , PtrVT ) ) ;

Loads . push_back ( DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , EltVT , Load -> getChain ( ) , Ptr , MachinePointerInfo ( Load -> getMemOperand ( ) -> getValue ( ) ) , MemEltVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> getAlignment ( ) ) ) ;


<s> const MCExpr * getShiftedImmVal ( ) const { assert ( Kind == k_ShiftedImm && <STR_LIT> ) ; return ShiftedImm . Val ;


<s> int OffsetA = <NUM_LIT> , OffsetB = <NUM_LIT> ; unsigned SizeA = <NUM_LIT> , SizeB = <NUM_LIT> ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) || MIa -> hasOrderedMemoryRef ( ) || MIa -> hasOrderedMemoryRef ( ) ) return false ; if ( MIa -> mayLoad ( ) && ! isMemOp ( MIa ) && MIb -> mayLoad ( ) && ! isMemOp ( MIb ) ) return true ; unsigned BaseRegA = getBaseAndOffset ( MIa , OffsetA , SizeA ) ;

if ( ! BaseRegA || ! SizeA ) return false ;


<s> SDNode * Result = DAG . getNode ( CFNode , DL , DAG . getVTList ( Res ) , Ops ) . getNode ( ) ; if ( ! HaveChain ) { SDValue Ops [ ] = { SDValue ( Result , <NUM_LIT> ) , BRCOND . getOperand ( <NUM_LIT> ) } ; Result = DAG . getMergeValues ( Ops , DL ) . getNode ( ) ; } if ( BR ) { SDValue Ops [ ] = { BR -> getOperand ( <NUM_LIT> ) , BRCOND . getOperand ( <NUM_LIT> ) } ; SDValue NewBR = DAG . getNode ( <STR_LIT> , DL , BR -> getVTList ( ) , Ops ) ; DAG . ReplaceAllUsesWith ( BR , NewBR . getNode ( ) ) ; } SDValue Chain = SDValue ( Result , Result -> getNumValues ( ) - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Intr -> getNumValues ( ) - <NUM_LIT> ; i != e ; ++ i ) {

SDNode * CopyToReg = findUser ( SDValue ( Intr , i ) , <STR_LIT> ) ;


<s> Args . push_back ( { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , HLTy , <NUM_LIT> } ) ; Args . push_back ( { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , HLAmtTy , <NUM_LIT> } ) ;

if ( ! createLibcall ( Helper . MIRBuilder , Libcall , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , HLTy , <NUM_LIT> } , Args ) ) return false ;


<s> ++ It ; unsigned dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned scratch = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( incr ) . addReg ( dest ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( dest ) . addReg ( incr ) . addImm ( <NUM_LIT> ) ; } unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ;

BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) . addReg ( scratch ) . addReg ( ptr ) ;


<s> return new <ISA_LIT>AddressTypePromotion ( ) ;


return LLT :: scalarOrVector ( ElementCount :: getFixed ( Size / <NUM_LIT> ) , <NUM_LIT> ) ;


<s> if ( Off . getOpcode ( ) != <STR_LIT> ) continue ; SDValue T0 = Off . getOperand ( <NUM_LIT> ) ; if ( T0 . getOpcode ( ) != <STR_LIT> ) continue ; SDValue T1 = T0 . getOperand ( <NUM_LIT> ) ; SDValue T2 = T0 . getOperand ( <NUM_LIT> ) ; if ( T1 . getOpcode ( ) != <STR_LIT> ) continue ; SDValue C = T1 . getOperand ( <NUM_LIT> ) ; ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ; if ( CN == nullptr ) continue ; unsigned CV = CN -> getZExtValue ( ) ; if ( CV > <NUM_LIT> ) continue ; ConstantSDNode * EN = dyn_cast < ConstantSDNode > ( T2 . getNode ( ) ) ; if ( EN == nullptr ) continue ; unsigned EV = EN -> getZExtValue ( ) ; if ( EV % ( <NUM_LIT> << CV ) != <NUM_LIT> ) continue ;

unsigned DV = EV / ( <NUM_LIT> << CV ) ;


<s> Res = DAG . getVectorShuffle ( <STR_LIT> , DL , Res , Res , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; if ( DstVT . is256BitVector ( ) ) return DAG . getBitcast ( DstVT , Res ) ; EVT PackedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PackedSVT , NumElems ) ; Res = DAG . getBitcast ( PackedVT , Res ) ; return truncateVectorCompareWithPACKSS ( DstVT , Res , DL , DAG , Subtarget ) ; } assert ( SrcVT . getSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; EVT PackedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PackedSVT , NumElems / <NUM_LIT> ) ; Lo = truncateVectorCompareWithPACKSS ( PackedVT , Lo , DL , DAG , Subtarget ) ; Hi = truncateVectorCompareWithPACKSS ( PackedVT , Hi , DL , DAG , Subtarget ) ;


<s> Register ThunkReg = ThunkIt -> Reg ; bool isThumb = ThunkIt -> isThumb ; const TargetInstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineBasicBlock * Entry = & MF . front ( ) ; Entry -> clear ( ) ; Entry -> addLiveIn ( ThunkReg ) ;

if ( isThumb ) BuildMI ( Entry , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( ThunkReg ) . add ( predOps ( <STR_LIT> ) ) ;


<s> if ( CS -> arg_size ( ) != CallerFn -> arg_size ( ) ) return false ; ImmutableCallSite :: arg_iterator CalleeArgIter = CS -> arg_begin ( ) ; ImmutableCallSite :: arg_iterator CalleeArgEnd = CS -> arg_end ( ) ; Function :: const_arg_iterator CallerArgIter = CallerFn -> arg_begin ( ) ; for ( ; CalleeArgIter != CalleeArgEnd ; ++ CalleeArgIter , ++ CallerArgIter ) {

const Value * CalleeArg = * CalleeArgIter ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) && getLexer ( ) . isNot ( AsmToken :: String ) ) return Error ( L , <STR_LIT> ) ; StringRef CPU = Parser . getTok ( ) . getIdentifier ( ) ; Parser . Lex ( ) ; if ( CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ) return Error ( L , <STR_LIT> ) ;

if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( L , <STR_LIT> ) ;


<s> const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; bool is<ISA_LIT> = ! AFI -> isThumbFunction ( ) ; unsigned ArgRegsSaveSize = AFI -> getArgRegsSaveSize ( ) ; int NumBytes = ( int ) MFI . getStackSize ( ) ; Register FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) return ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes - ArgRegsSaveSize != <NUM_LIT> ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes - ArgRegsSaveSize ) ; } else { const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( MBBI != MBB . begin ( ) ) { do { -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( * MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( * MBBI , TII , CSRegs ) ) ++ MBBI ; }

NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ;


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != <NUM_LIT> ) O << <STR_LIT> ;

if ( MI -> getOperand ( i ) . isReg ( ) ) printRegName ( O , MI -> getOperand ( i ) . getReg ( ) ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; case ELF :: R_MIPS_HI16 : case ELF :: R_MIPS16_HI16 : case ELF :: R_MICROMIPS_HI16 : case ELF :: R_MIPS_LO16 : case ELF :: R_MIPS16_LO16 :


<s> if ( Subtarget . hasVSX ( ) ) { if ( Subtarget . pairedVectorMemops ( ) ) return CSR_64_AllRegs_VSRP_RegMask ; if ( Subtarget . isAIXABI ( ) && ! TM . getAIXExtendedAltivecABI ( ) ) return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask ; return CSR_64_AllRegs_VSX_RegMask ; } if ( Subtarget . hasAltivec ( ) ) { if ( Subtarget . isAIXABI ( ) && ! TM . getAIXExtendedAltivecABI ( ) ) return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask ; return CSR_64_AllRegs_Altivec_RegMask ; } return CSR_64_AllRegs_RegMask ; } if ( Subtarget . isAIXABI ( ) ) { return TM . is<ISA_LIT>64 ( ) ? ( ( Subtarget . hasAltivec ( ) && TM . getAIXExtendedAltivecABI ( ) ) ? CSR_<ISA_LIT>64_Altivec_RegMask : CSR_<ISA_LIT>64_RegMask ) : ( ( Subtarget . hasAltivec ( ) && TM . getAIXExtendedAltivecABI ( ) ) ? CSR_AIX32_Altivec_RegMask : CSR_AIX32_RegMask ) ;


<s> return new <ISA_LIT>MCELFStreamer ( Context , MAB , OS , CE ) ;


<s> void <ISA_LIT>InstPrinter :: printNeonUImm64MaskOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MOUImm8 = MI -> getOperand ( OpNum ) ; assert ( MOUImm8 . isImm ( ) && <STR_LIT> ) ; uint32_t UImm8 = MOUImm8 . getImm ( ) ; uint64_t Mask = <NUM_LIT> ; for ( unsigned ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( UImm8 >> ByteNum ) & <NUM_LIT> ) Mask |= ( uint64_t ) <NUM_LIT> << ( <NUM_LIT> * ByteNum ) ; }


<s> bool willForceRelocations ( ) const {

return ForceRelocs || STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ! Subtarget . hasAnyFMA ( ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( <NUM_LIT> ) ; SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; auto invertIfNegative = [ & DAG , & TLI , & DCI ] ( SDValue & V ) { bool CodeSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; bool LegalOperations = ! DCI . isBeforeLegalizeOps ( ) ; if ( TLI . isNegatibleForFree ( V , DAG , LegalOperations , CodeSize ) == <NUM_LIT> ) { V = TLI . getNegatedExpression ( V , DAG , LegalOperations , CodeSize ) ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) ) { SDValue Vec = V . getOperand ( <NUM_LIT> ) ; if ( TLI . isNegatibleForFree ( Vec , DAG , LegalOperations , CodeSize ) == <NUM_LIT> ) { SDValue NegVal = TLI . getNegatedExpression ( Vec , DAG , LegalOperations , CodeSize ) ; V = DAG . getNode ( <STR_LIT> , SDLoc ( V ) , V . getValueType ( ) , NegVal , V . getOperand ( <NUM_LIT> ) ) ; return true ; } } return false ; } ; bool NegA = invertIfNegative ( A ) ; bool NegB = invertIfNegative ( B ) ; bool NegC = invertIfNegative ( C ) ; if ( ! NegA && ! NegB && ! NegC ) return SDValue ( ) ; unsigned NewOpcode = negateFMAOpcode ( N -> getOpcode ( ) , NegA != NegB , NegC , false ) ;

if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT , A , B , C , N -> getOperand ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>TargetStreamer :: closeLastSection ( ) { if ( HasSections ) getStreamer ( ) . EmitRawText ( <STR_LIT> ) ;


<s> return N -> getOpcode ( ) == <STR_LIT> ;


<s> if ( SrcVT == <STR_LIT> && TLI . isTypeLegal ( SrcVT ) ) return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ) ; MVT IntegerVT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , IntegerVT , Src ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget . is64Bit ( ) ) { return Op ; } SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ;

SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ) ;


<s> switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : FMov . setOpcode ( <STR_LIT> ) ; FMov . addOperand ( MCOperand :: createReg ( DestReg ) ) ; FMov . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <STR_LIT> : FMov . setOpcode ( <STR_LIT> ) ; FMov . addOperand ( MCOperand :: createReg ( DestReg ) ) ; FMov . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ;


<s> switch ( cast < Operator > ( V ) . getOpcode ( ) ) { case Instruction :: PHI : case Instruction :: BitCast : case Instruction :: AddrSpaceCast : case Instruction :: GetElementPtr :


<s> const TargetMachine & TM = MF . getTarget ( ) ; TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( TM . getInstrInfo ( ) ) ; TRI = TM . getRegisterInfo ( ) ; STI = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false ;

for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ;


<s> if ( isLegalAddressingMode ( DL , AM , Ty , AS ) ) return AM . Scale != <NUM_LIT> ; return - <NUM_LIT> ;


<s> if ( C1 -> getOpcode ( ) == <STR_LIT> ) { SDValue VSel = DCI . DAG . getNode ( <STR_LIT> , dl , ty ( Op ) , C0 , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; return VSel ;


<s> } ; switch ( Kind ) { case KindTy :: Immediate : OS << * getImm ( ) ; break ; case KindTy :: Register : OS << <STR_LIT> << RegName ( getReg ( ) ) << <STR_LIT> ; break ; case KindTy :: Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case KindTy :: SystemRegister : OS << <STR_LIT> << getSysReg ( ) << '>' ;


<s> static void GetSpillList ( SmallVectorImpl < StackSlotInfo > & SpillList , MachineFrameInfo * MFI , <ISA_LIT>FunctionInfo * XFI , bool fetchLR , bool fetchFP ) { if ( fetchLR ) { int Offset = MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) ; SpillList . push_back ( StackSlotInfo ( XFI -> getLRSpillSlot ( ) , Offset , <STR_LIT> ) ) ;


<s> rtx last_set = NULL ; for ( df_ref d = DF_REG_DEF_CHAIN ( REGNO ( x ) ) ; d != NULL ; d = DF_REF_NEXT_REG ( d ) ) { rtx set = const_cast < rtx > ( set_of ( x , DF_REF_INSN ( d ) ) ) ; if ( last_set == NULL || rtx_equal_p ( last_set , set ) ) { last_i = DF_REF_INSN ( d ) ; last_set = set ; } else { last_i = NULL ; last_set = NULL ; break ; } } if ( last_set != NULL && last_i != NULL ) return sh_find_base_reg_disp ( last_i , XEXP ( last_set , <NUM_LIT> ) , disp , XEXP ( last_set , <NUM_LIT> ) ) ; return base_reg_disp ( x , disp ) ; } else if ( GET_CODE ( x ) == PLUS ) { base_reg_disp left_val = sh_find_base_reg_disp ( insn , XEXP ( x , <NUM_LIT> ) ) ; base_reg_disp right_val = sh_find_base_reg_disp ( insn , XEXP ( x , <NUM_LIT> ) ) ; if ( left_val . is_reg ( ) && right_val . is_disp ( ) ) return base_reg_disp ( left_val . reg ( ) , left_val . disp ( ) + right_val . disp ( ) + disp ) ; else if ( right_val . is_reg ( ) && left_val . is_disp ( ) ) return base_reg_disp ( right_val . reg ( ) , right_val . disp ( ) + left_val . disp ( ) + disp ) ; else return base_reg_disp ( base_reg , disp ) ; } else if ( CONST_INT_P ( x ) ) return base_reg_disp ( NULL , disp + INTVAL ( x ) ) ; return base_reg_disp ( base_reg , disp ) ;


<s> int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; Out . EmitBundleLock ( false ) ; EmitBICMask ( Out , Reg , Pred , <NUM_LIT> ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ; Out . EmitBundleUnlock ( ) ;


<s> int64_t val = ( ( const MCConstantExpr * ) Imm . Val ) -> getValue ( ) ; return isInt < <NUM_LIT> > ( val ) ; }


<s> if ( ACCG_P ( regno ) ) return GET_MODE_SIZE ( mode ) ;

else return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;


<s> virtual const TargetData * getTargetData ( ) const { return & DataLayout ;


<s> if ( getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return <NUM_LIT> ;

if ( getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) return <NUM_LIT> ;


<s> } } if ( LogicOp And = interpretAndImmediate ( Opcode ) ) { uint64_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) << And . ImmLSB ; Imm |= allOnes ( And . RegSize ) & ~ ( allOnes ( And . ImmSize ) << And . ImmLSB ) ; unsigned Start , End ; if ( isRxSBGMask ( Imm , And . RegSize , Start , End ) ) { unsigned NewOpcode ; if ( And . RegSize == <NUM_LIT> ) { NewOpcode = <STR_LIT> ; if ( STI . hasMiscellaneousExtensions ( ) ) NewOpcode = <STR_LIT> ; } else { NewOpcode = <STR_LIT> ; Start &= <NUM_LIT> ; End &= <NUM_LIT> ; } MachineOperand & Dest = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ;

MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( NewOpcode ) ) . addOperand ( Dest ) . addReg ( <NUM_LIT> ) . addReg ( Src . getReg ( ) , getKillRegState ( Src . isKill ( ) ) , Src . getSubReg ( ) ) . addImm ( Start ) . addImm ( End + <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) && ! MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ;


if ( ! Triple ( TT ) . isOSNaCl ( ) ) S = createELFStreamer ( Context , MAB , OS , Emitter , RelaxAll , NoExecStack ) ;


<s> return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> if ( auto LI = dyn_cast < LoadInst > ( & I ) ) { if ( Value * NoOpBitcast = maybeGenerateBitcast ( Builder , PointerTypes , I , LI -> getPointerOperand ( ) , LI -> getType ( ) ) ) { LI -> replaceAllUsesWith ( Builder . CreateLoad ( LI -> getType ( ) , NoOpBitcast ) ) ; LI -> eraseFromParent ( ) ; } continue ; } if ( auto SI = dyn_cast < StoreInst > ( & I ) ) { if ( Value * NoOpBitcast = maybeGenerateBitcast ( Builder , PointerTypes , I , SI -> getPointerOperand ( ) , SI -> getValueOperand ( ) -> getType ( ) ) ) { SI -> replaceAllUsesWith ( Builder . CreateStore ( SI -> getValueOperand ( ) , NoOpBitcast ) ) ; SI -> eraseFromParent ( ) ; }


<s> if ( GET_CODE ( x ) == HIGH ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == SYMBOL_REF && read_only_operand ( x , VOIDmode ) ) output_addr_const ( file , x ) ; else if ( GET_CODE ( x ) == SYMBOL_REF && ! flag_pic ) { output_addr_const ( file , x ) ; fputs ( <STR_LIT> , file ) ; } else if ( GET_CODE ( x ) == CONST ) { const char * sep = <STR_LIT> ; int offset = <NUM_LIT> ; rtx base = NULL_RTX ; switch ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) { case LABEL_REF : case SYMBOL_REF : base = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; output_addr_const ( file , base ) ; break ; case CONST_INT : offset = INTVAL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ; break ; default : gcc_unreachable ( ) ; } switch ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) { case LABEL_REF : case SYMBOL_REF : base = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ;


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const { return & InstrInfo . getRegisterInfo ( ) ;


<s> Comparison ( SDValue Op0In , SDValue Op1In , SDValue ChainIn ) : Op0 ( Op0In ) , Op1 ( Op1In ) , Chain ( ChainIn ) , Opcode ( <NUM_LIT> ) , ICmpType ( <NUM_LIT> ) , CCValid ( <NUM_LIT> ) , CCMask ( <NUM_LIT> ) {


<s> SDValue <ISA_LIT>TargetLowering :: performSHLPtrCombine ( SDNode * N , unsigned AddrSpace , DAGCombinerInfo & DCI ) const { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; const ConstantSDNode * CN1 = dyn_cast < ConstantSDNode > ( N1 ) ; if ( ! CN1 ) return SDValue ( ) ; const ConstantSDNode * CAdd = dyn_cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) ; if ( ! CAdd ) return SDValue ( ) ; APInt Offset = CAdd -> getAPIntValue ( ) << CN1 -> getAPIntValue ( ) ;

if ( ! canFoldOffset ( Offset . getZExtValue ( ) , AddrSpace , * Subtarget ) ) return SDValue ( ) ;


<s> if ( ! isMem ( ) || Memory . Alignment != <NUM_LIT> ) return false ; if ( Memory . ShiftType != <STR_LIT> ) return false ;

if ( Memory . OffsetRegNum ) return true ;