<s> return ; } if ( <STR_LIT> ( InstDesc , OpNum ) ) { if ( Literal . getLoBits ( <NUM_LIT> ) != <NUM_LIT> ) { const_cast < <ISA_LIT>AsmParser * > ( AsmParser ) -> Warning ( Inst . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; } Inst . addOperand ( MCOperand :: createImm ( Literal . lshr ( <NUM_LIT> ) . getZExtValue ( ) ) ) ; return ; } llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool lost ; APFloat FPLiteral ( APFloat :: IEEEdouble ( ) , Literal ) ; FPLiteral . convert ( * getOpFltSemantics ( OpTy ) , APFloat :: rmNearestTiesToEven , & lost ) ; uint64_t ImmVal = FPLiteral . bitcastToAPInt ( ) . getZExtValue ( ) ; Inst . addOperand ( MCOperand :: createImm ( ImmVal ) ) ; return ; } default : llvm_unreachable ( <STR_LIT> ) ; } return ; } switch ( OpTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isSafeTruncation ( Val , <NUM_LIT> ) && <STR_LIT> ( static_cast < int32_t > ( Val ) , AsmParser -> hasInv2PiInlineImm ( ) ) ) { Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return ; } Inst . addOperand ( MCOperand :: createImm ( Val & <NUM_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( <STR_LIT> ( Val , AsmParser -> hasInv2PiInlineImm ( ) ) ) { Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return ; } Inst . addOperand ( MCOperand :: createImm ( Lo_32 ( Val ) ) ) ; return ;


<s> <ISA_LIT>TargetObjectFile :: <ISA_LIT>TargetObjectFile ( ) { TextSection = nullptr ; DataSection = nullptr ; BSSSection = nullptr ; ReadOnlySection = nullptr ; StaticCtorSection = nullptr ; StaticDtorSection = nullptr ; LSDASection = nullptr ; EHFrameSection = nullptr ; DwarfAbbrevSection = nullptr ; DwarfInfoSection = nullptr ; DwarfLineSection = nullptr ; DwarfFrameSection = nullptr ; DwarfPubTypesSection = nullptr ; DwarfDebugInlineSection = nullptr ; DwarfStrSection = nullptr ; DwarfLocSection = nullptr ; DwarfARangesSection = nullptr ;


<s> addPass ( createBreakFalseDeps ( ) ) ; } addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createThumb2SizeReductionPass ( [ this ] ( const Function & F ) { return this -> TM -> getSubtarget < <ISA_LIT>Subtarget > ( F ) . restrictIT ( ) ; } ) ) ; addPass ( createIfConverter ( [ ] ( const MachineFunction & MF ) { return ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb1Only ( ) ; } ) ) ; } addPass ( createMVEVPTBlockPass ( ) ) ;

addPass ( createThumb2ITBlockPass ( ) ) ;


<s> static __inline qword si_ceqi ( qword a , signed int b ) { return ( ( qword ) ( vec_cmpeq ( ( vec_int4 ) ( a ) , vec_splat ( ( vec_int4 ) ( si_from_int ( b ) ) , <NUM_LIT> ) ) ) ) ;


return promote_mode ( type , mode , & dummy ) ;


<s> void NPEngineTargetMachine :: addAnalysisPasses ( PassManagerBase & PM ) {


<s> static bool mips_canonicalize_comparison ( enum rtx_code * code , rtx * cmp1 , enum machine_mode mode ) { HOST_WIDE_INT original , plus_one ; if ( GET_CODE ( * cmp1 ) != CONST_INT ) return false ; original = INTVAL ( * cmp1 ) ; plus_one = trunc_int_for_mode ( ( unsigned HOST_WIDE_INT ) original + <NUM_LIT> , mode ) ; switch ( * code ) {


<s> emit_insn ( gen_mov_ldl ( temp , src , left ) ) ; emit_insn ( gen_mov_ldr ( dest , copy_rtx ( src ) , right , temp ) ) ; } else { emit_insn ( gen_mov_lwl ( temp , src , left ) ) ; emit_insn ( gen_mov_lwr ( dest , copy_rtx ( src ) , right , temp ) ) ; }


<s> continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } } if ( MayLoad && Reg == getLdStRegOp ( MI ) . getReg ( ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( & MI ) ; continue ; } if ( ! ModifiedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] && ! ( MI . mayLoad ( ) && UsedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] ) && ! mayAlias ( MI , MemInsns , TII ) ) { Flags . setMergeForward ( false ) ; return MBBI ; } if ( ! ModifiedRegs [ getLdStRegOp ( FirstMI ) . getReg ( ) ] && ! ( MayLoad && UsedRegs [ getLdStRegOp ( FirstMI ) . getReg ( ) ] ) && ! mayAlias ( FirstMI , MemInsns , TII ) ) { Flags . setMergeForward ( true ) ; return MBBI ; } } } if ( MI . isCall ( ) ) return E ; trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( ModifiedRegs [ BaseReg ] ) return E ; if ( MI . mayLoadOrStore ( ) ) MemInsns . push_back ( & MI ) ; } return E ;


<s> if ( Code == <STR_LIT> ) { Error ( S , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return true ; } SMLoc DotL = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + CondCodePos ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , DotL ) ) ; SMLoc E = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + CondCodePos + <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( Code , S , E ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Mnemonic ) ) { Parser . eatToEndOfStatement ( ) ; return true ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Mnemonic ) ) { Parser . eatToEndOfStatement ( ) ; return true ; } if ( Parser . getTok ( ) . is ( AsmToken :: RBrac ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , Loc ) ) ; Parser . Lex ( ) ; } if ( Parser . getTok ( ) . is ( AsmToken :: Exclaim ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , Loc ) ) ; Parser . Lex ( ) ;


<s> if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; auto & I = SubtargetMap [ CPU + FS ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , computeFSAdditions ( FS , getOptLevel ( ) , getTargetTriple ( ) ) , * this ) ; } return I . get ( ) ;


<s> inline vector unsigned int vec_vsraw ( vector unsigned int a1 , vector unsigned int a2 ) { return ( vector unsigned int ) __builtin_altivec_vsraw ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> return ( uint64x2_t ) __builtin_neon_vreinterpretv2div16qi ( __a ) ;


<s> const EVT LaneT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; const size_t Lanes = Op . getNumOperands ( ) ; auto IsConstant = [ ] ( const SDValue & V ) { return V . getOpcode ( ) == <STR_LIT> || V . getOpcode ( ) == <STR_LIT> ; } ; using Entry = std :: pair < SDValue , size_t > ; SmallVector < Entry , <NUM_LIT> > ValueCounts ; size_t NumConst = <NUM_LIT> , NumDynamic = <NUM_LIT> ; for ( const SDValue & Lane : Op -> op_values ( ) ) { if ( Lane . isUndef ( ) ) { continue ; } else if ( IsConstant ( Lane ) ) { NumConst ++ ; } else { NumDynamic ++ ; } auto CountIt = std :: find_if ( ValueCounts . begin ( ) , ValueCounts . end ( ) , [ & Lane ] ( Entry A ) { return A . first == Lane ; } ) ; if ( CountIt == ValueCounts . end ( ) ) { ValueCounts . emplace_back ( Lane , <NUM_LIT> ) ; } else { CountIt -> second ++ ; } }

auto CommonIt = std :: max_element ( ValueCounts . begin ( ) , ValueCounts . end ( ) , [ ] ( Entry A , Entry B ) { return A . second < B . second ; } ) ;


<s> copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( copy1MBB ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI . eraseFromParent ( ) ;


<s> rtx tmp = can_create_pseudo_p ( ) ? gen_reg_rtx_and_attrs ( dest ) : dest ; rs6000_emit_le_vsx_permute ( tmp , source , mode ) ; rs6000_emit_le_vsx_permute ( dest , tmp , mode ) ;


<s> for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i ] = InVec [ i ] ; return ; } for ( unsigned j = <NUM_LIT> ; j < VecElems / <NUM_LIT> ; j ++ ) for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) Vec [ i + j * <NUM_LIT> ] = Builder . CreateShuffleVector ( InVec [ j * <NUM_LIT> + i ] , InVec [ j * <NUM_LIT> + i + <NUM_LIT> ] , makeArrayRef ( Concat , <NUM_LIT> ) ) ;


<s> void <ISA_LIT>LinuxAsmPrinter :: EmitFunctionEntryLabel ( ) { if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; const MCSection * Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ;

MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ;


<s> printOperand ( MI , opNum , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , O ) ;


<s> Streamer . visitUsedExpr ( * getSubExpr ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printBankMask ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {


<s> const MachineOperand & MO = MI . getOperand ( OpNum ) ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) && hasUndefRegUpdate ( MI . getOpcode ( ) , OpNum ) ) return UndefRegClearance ; return <NUM_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( CoprocOption . Val ) ) ;


<s> static inline unsigned getSOImmValRotate ( unsigned Imm ) { if ( ( Imm & ~ <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; unsigned TZ = CountTrailingZeros_32 ( Imm ) ; unsigned RotAmt = TZ & ~ <NUM_LIT> ; if ( ( rotr32 ( Imm , RotAmt ) & ~ <NUM_LIT> ) == <NUM_LIT> ) return ( <NUM_LIT> - RotAmt ) & <NUM_LIT> ; if ( Imm & <NUM_LIT> ) { unsigned TZ2 = CountTrailingZeros_32 ( Imm & ~ <NUM_LIT> ) ; unsigned RotAmt2 = TZ2 & ~ <NUM_LIT> ; if ( ( rotr32 ( Imm , RotAmt2 ) & ~ <NUM_LIT> ) == <NUM_LIT> ) return ( <NUM_LIT> - RotAmt2 ) & <NUM_LIT> ; } return ( <NUM_LIT> - RotAmt ) & <NUM_LIT> ;


<s> if ( static_cast < unsigned > ( Offset ) >= SubRegs . size ( ) ) return std :: make_pair ( IdxReg , SubRegs [ <NUM_LIT> ] ) ;

return std :: make_pair ( IdxBaseReg , SubRegs [ Offset ] ) ;


<s> case CallingConv :: <ISA_LIT>_PS : case CallingConv :: <ISA_LIT>_CS : return F -> getAttributes ( ) . hasParamAttribute ( A -> getArgNo ( ) , Attribute :: InReg ) || F -> getAttributes ( ) . hasParamAttribute ( A -> getArgNo ( ) , Attribute :: ByVal ) ; default : return false ; }


<s> const char * abi = <STR_LIT> ; return build_string_literal ( strlen ( abi ) + <NUM_LIT> , abi ) ;


<s> for ( MachineBasicBlock :: livein_iterator i = MBB -> livein_begin ( ) , e = MBB -> livein_end ( ) ; i != e ; ++ i ) { int rx = RegIndex ( * i ) ; if ( rx < <NUM_LIT> ) continue ; for ( MachineBasicBlock :: const_pred_iterator pi = MBB -> pred_begin ( ) , pe = MBB -> pred_end ( ) ; pi != pe ; ++ pi ) {

LiveOutMap :: const_iterator fi = LiveOuts . find ( * pi ) ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) {


<s> if ( K . isWriteable ( ) ) Flags |= ELF :: SHF_WRITE ; if ( K . isMergeableCString ( ) || K . isMergeableConst4 ( ) || K . isMergeableConst8 ( ) || K . isMergeableConst16 ( ) ) Flags |= ELF :: SHF_MERGE ; if ( K . isMergeableCString ( ) ) Flags |= ELF :: SHF_STRINGS ; return Flags ;


<s> void BTFTypeDeclTag :: completeType ( BTFDebug & BDebug ) { if ( IsCompleted ) return ; IsCompleted = true ;

BTFType . NameOff = BDebug . addString ( Tag ) ;


<s> if ( selectAddrFrameIndex ( Addr , Base , Offset ) ) return true ;

if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> , <NUM_LIT> ) ) return true ;


<s> <ISA_LIT>BaseTargetMachine :: <ISA_LIT>BaseTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , Options ) , JITInfo ( ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( Options . FloatABIType == FloatABI :: Default ) this -> Options . FloatABIType = Subtarget . isTargetHardFloat ( ) ? FloatABI :: Hard : FloatABI :: Soft ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ++ UOps ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : UOps += <NUM_LIT> ; break ; } return UOps ;


<s> LiveInterval & LI = LIS . getInterval ( Reg ) ; ShrinkToUses ( LI , LIS ) ; IsDead = ! LI . liveAt ( LIS . getInstructionIndex ( Def ) . getDeadSlot ( ) ) ; } if ( IsDead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SlotIndex Idx = LIS . getInstructionIndex ( Def ) . getRegSlot ( ) ; LIS . removePhysRegDefAt ( <STR_LIT> , Idx ) ; LIS . removeInterval ( Reg ) ; LIS . RemoveMachineInstrFromMaps ( Def ) ; Def . eraseFromParent ( ) ; MoveDebugValues ( Reg , & * Insert , MBB , MRI ) ; UpdateDebugValuesReg ( Reg , NewReg , MBB , MRI ) ; } else { CloneDebugValues ( Reg , & * Insert , NewReg , MBB , MRI , TII ) ; }


<s> bool aarch64_float_const_zero_rtx_p ( rtx x ) {

if ( GET_MODE ( x ) == VOIDmode ) return false ;


<s> bool Changed = false ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) { MachineLoop * L = * I ; if ( ! L -> getParentLoop ( ) ) Changed |= convertToHardwareLoop ( L ) ; }


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> const Constant * C = Stack . pop_back_val ( ) ; if ( const auto * CE = dyn_cast < ConstantExpr > ( C ) ) { if ( visitConstantExpr ( CE ) ) return true ; } for ( const Use & U : C -> operands ( ) ) { const auto * OpC = dyn_cast < Constant > ( U ) ; if ( ! OpC ) continue ; if ( ! ConstantExprVisited . insert ( OpC ) . second ) continue ; Stack . push_back ( OpC ) ;


<s> return static_cast < MCObjectStreamer & > ( Streamer ) ;


<s> SMLoc Start = Lex ( ) . getLoc ( ) ; ID = getTok ( ) . getString ( ) ; if ( ! isParsingMSInlineAsm ( ) ) {

if ( ( getTok ( ) . isNot ( AsmToken :: Identifier ) && getTok ( ) . isNot ( AsmToken :: String ) ) || getParser ( ) . parsePrimaryExpr ( Val , End , nullptr ) ) return Error ( Start , <STR_LIT> ) ;


<s> vector_insn_info ( ) : vl_vtype_info ( ) , m_state ( UNINITIALIZED ) , m_demands { false } , m_insn ( nullptr ) {


<s> const GlobalValue & FName = MBB . getParent ( ) -> getFunction ( ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , GP ) . addGlobalAddress ( & FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , GP ) . addReg ( GP ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , GP ) . addReg ( GP ) . addGlobalAddress ( & FName , <NUM_LIT> , <STR_LIT> ) ;


<s> if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NegVal , N -> getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NegVal ) ;


<s> if ( ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; SDValue A = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue B = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDValue C = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; SDNodeFlags Flags = N -> getFlags ( ) ; if ( ! IsStrict && Flags . hasAllowReassociation ( ) && TLI . isOperationExpand ( <STR_LIT> , VT ) ) { SDValue Fmul = DAG . getNode ( <STR_LIT> , dl , VT , A , B , Flags ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Fmul , C , Flags ) ; } EVT ScalarVT = VT . getScalarType ( ) ; if ( ( ScalarVT != <STR_LIT> && ScalarVT != <STR_LIT> ) || ! Subtarget . hasAnyFMA ( ) ) return SDValue ( ) ; auto invertIfNegative = [ & DAG , & TLI , & DCI ] ( SDValue & V ) { bool CodeSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; bool LegalOperations = ! DCI . isBeforeLegalizeOps ( ) ; if ( SDValue NegV = TLI . getCheaperNegatedExpression ( V , DAG , LegalOperations , CodeSize ) ) { V = NegV ; return true ; } if ( V . getOpcode ( ) == <STR_LIT> && isNullConstant ( V . getOperand ( <NUM_LIT> ) ) ) { SDValue Vec = V . getOperand ( <NUM_LIT> ) ; if ( SDValue NegV = TLI . getCheaperNegatedExpression ( Vec , DAG , LegalOperations , CodeSize ) ) { V = DAG . getNode ( <STR_LIT> , SDLoc ( V ) , V . getValueType ( ) , NegV , V . getOperand ( <NUM_LIT> ) ) ; return true ; } } return false ; } ; bool NegA = invertIfNegative ( A ) ; bool NegB = invertIfNegative ( B ) ; bool NegC = invertIfNegative ( C ) ;

if ( ! NegA && ! NegB && ! NegC ) return SDValue ( ) ;


<s> return STI . getFeatureBits ( ) & <STR_LIT> ;


<s> int Src0Idx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; if ( Src0 . isReg ( ) ) { Register Reg = Src0 . getReg ( ) ; if ( Reg . isVirtual ( ) && MRI . hasOneUse ( Reg ) ) { MachineInstr * Def = MRI . getUniqueVRegDef ( Reg ) ; if ( Def && Def -> isMoveImmediate ( ) ) { MachineOperand & MovSrc = Def -> getOperand ( <NUM_LIT> ) ; bool ConstantFolded = false ; if ( MovSrc . isImm ( ) && ( isInt < <NUM_LIT> > ( MovSrc . getImm ( ) ) || isUInt < <NUM_LIT> > ( MovSrc . getImm ( ) ) ) ) { Src0 . ChangeToImmediate ( MovSrc . getImm ( ) ) ; ConstantFolded = true ; } else if ( MovSrc . isFI ( ) ) { Src0 . ChangeToFrameIndex ( MovSrc . getIndex ( ) ) ; ConstantFolded = true ; } else if ( MovSrc . isGlobal ( ) ) { Src0 . ChangeToGA ( MovSrc . getGlobal ( ) , MovSrc . getOffset ( ) , MovSrc . getTargetFlags ( ) ) ; ConstantFolded = true ; } if ( ConstantFolded ) { assert ( MRI . use_empty ( Reg ) ) ; Def -> eraseFromParent ( ) ; ++ NumLiteralConstantsFolded ; return true ; } } } }

if ( TryToCommute && MI . isCommutable ( ) ) {


<s> for ( MachineInstr & MI : MBB ) { if ( MI . isDebugInstr ( ) || MI . isPseudo ( ) || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) continue ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isFI ( ) ) continue ; int Offset = <NUM_LIT> ;

if ( is<ISA_LIT>FrameOffsetLegal ( MI , Offset , nullptr , nullptr , nullptr ) == <ISA_LIT>FrameOffsetCannotUpdate ) return <NUM_LIT> ;


<s> void clearFeatureBits ( unsigned Feature , StringRef FeatureString ) { if ( STI . getFeatureBits ( ) & Feature ) {

setAvailableFeatures ( ComputeAvailableFeatures ( STI . ToggleFeature ( FeatureString ) ) ) ;


<s> addPass ( create<ISA_LIT>GenScalarMASSEntriesPass ( ) ) ; } if ( EnablePrefetch . getNumOccurrences ( ) > <NUM_LIT> ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) >= CodeGenOpt :: Default && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; unsigned OpcodeSelect = <STR_LIT> ; SDLoc dl ( Op ) ; if ( isAllOnesConstant ( Mask ) ) return Op ; SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

return DAG . getNode ( <STR_LIT> , dl , VT , Op , VMask ) ;


<s> bool IsDead = RegOp . isDead ( ) ; bool IsUndef = RegOp . isUndef ( ) ; bool IsDebug = RegOp . isDebug ( ) ; if ( NonRegOp . isImm ( ) ) RegOp . ChangeToImmediate ( NonRegOp . getImm ( ) ) ; else if ( NonRegOp . isFI ( ) ) RegOp . ChangeToFrameIndex ( NonRegOp . getIndex ( ) ) ; else if ( NonRegOp . isGlobal ( ) ) { RegOp . ChangeToGA ( NonRegOp . getGlobal ( ) , NonRegOp . getOffset ( ) , NonRegOp . getTargetFlags ( ) ) ; } else return nullptr ; RegOp . setTargetFlags ( NonRegOp . getTargetFlags ( ) ) ; NonRegOp . ChangeToRegister ( Reg , false , false , IsKill , IsDead , IsUndef , IsDebug ) ; NonRegOp . setSubReg ( SubReg ) ; return & MI ;


<s> else emit_move_insn ( r13 , stack_pointer_rtx ) ; emit_move_insn ( r14 , GEN_INT ( PROBE_INTERVAL ) ) ; if ( rounded_size == <NUM_LIT> ) emit_move_insn ( r12 , r13 ) ; else { emit_move_insn ( r12 , GEN_INT ( rounded_size ) ) ; emit_insn ( gen_rtx_SET ( r12 , gen_rtx_MINUS ( Pmode , r13 , r12 ) ) ) ; emit_insn ( gen_probe_stack_range ( Pmode , r13 , r13 , r12 , r14 ) ) ; } if ( size != rounded_size ) { if ( TARGET_64BIT ) emit_stack_probe ( plus_constant ( Pmode , r12 , rounded_size - size ) ) ; else { HOST_WIDE_INT i ; for ( i = <NUM_LIT> ; i < ( size - rounded_size ) ; i += <NUM_LIT> ) { emit_stack_probe ( plus_constant ( Pmode , r12 , - i ) ) ; emit_insn ( gen_rtx_SET ( r12 , plus_constant ( Pmode , r12 , - <NUM_LIT> ) ) ) ; } rtx r1 = plus_constant ( Pmode , r12 , - ( size - rounded_size - i + <NUM_LIT> ) ) ;


<s> return <ISA_LIT>_LOW_OVERHEAD_LOOPS_NAME ;


<s> assert ( ! ST . isAmdHsaOrMesa ( Fn ) ) ; const MCInstrDesc & SMovB32 = TII -> get ( <STR_LIT> ) ; Register Rsrc2 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; Register Rsrc3 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; uint64_t Rsrc23 = TII -> getScratchRsrcWords23 ( ) ; if ( MFI -> hasImplicitBufferPtr ( ) ) { Register Rsrc01 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; if ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) { const MCInstrDesc & Mov64 = TII -> get ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , Mov64 , Rsrc01 ) . addReg ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; } else { const MCInstrDesc & LoadDwordX2 = TII -> get ( <STR_LIT> ) ; PointerType * PtrTy = PointerType :: get ( Type :: getInt64Ty ( MF . getFunction ( ) . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; auto MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , I , DL , LoadDwordX2 , Rsrc01 ) . addReg ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; MF . getRegInfo ( ) . addLiveIn ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) ; MBB . addLiveIn ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) ; } } else { Register Rsrc0 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; Register Rsrc1 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , SMovB32 , Rsrc0 ) . addExternalSymbol ( <STR_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; BuildMI ( MBB , I , DL , SMovB32 , Rsrc1 ) . addExternalSymbol ( <STR_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; }

BuildMI ( MBB , I , DL , SMovB32 , Rsrc2 ) . addImm ( Rsrc23 & <NUM_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ;


<s> assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; for ( MCRegAliasIterator AI ( Reg , & TRI , false ) ; AI . isValid ( ) ; ++ AI ) AS . insert ( RegisterRef ( * AI ) ) ;


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; addOperands ( MIB , MOs , PtrOffset ) ; } else { MIB . addOperand ( MO ) ; } } MachineBasicBlock * MBB = InsertPt -> getParent ( ) ; MBB -> insert ( InsertPt , NewMI ) ;


<s> int min ; fcomi_cost = ix86_fp_comparison_fcomi_cost ( code ) ; sahf_cost = ix86_fp_comparison_sahf_cost ( code ) ;

min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost ( code ) ;


<s> builder . quick_push ( build_all_ones_cst ( bool_type ) ) ; for ( unsigned int i = <NUM_LIT> ; i < element_bytes ; ++ i ) builder . quick_push ( build_zero_cst ( bool_type ) ) ;

return gimple_build_assign ( lhs , builder . build ( ) ) ;


<s> void i386_pe_record_external_function ( tree decl , const char * name ) {


<s> FrameReg = TRI -> getStackRegister ( ) ; return MFI . getObjectOffset ( FI ) - getOffsetOfLocalArea ( ) + Adjustment ;


<s> return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ;


<s> virtual ~ <ISA_LIT>Disassembler ( ) {


<s> return create<ISA_LIT>AsmBackend ( T , STI , MRI , Options , <STR_LIT> ) ;


<s> MachineOperand & pop ( ) { RangeTy & Range = Worklist . back ( ) ; MachineOperand & Op = * Range . begin ( ) ; Range = drop_begin ( Range , <NUM_LIT> ) ; if ( Range . begin ( ) == Range . end ( ) ) Worklist . pop_back ( ) ; assert ( ( Worklist . empty ( ) || Worklist . back ( ) . begin ( ) != Worklist . back ( ) . end ( ) ) && <STR_LIT> ) ; return Op ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( TLI . getVarArgsFrameOffset ( ) , <STR_LIT> ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , Offset , Op . getOperand ( <NUM_LIT> ) , SV , <NUM_LIT> ) ;


<s> static unsigned int ix86_hard_regno_nregs ( unsigned int regno , machine_mode mode ) { if ( GENERAL_REGNO_P ( regno ) ) {

if ( mode == XFmode ) return TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ;


<s> switch ( I -> Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( BitSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addImm ( I -> Op2 ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ;

MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && LastItem ) ) . addImm ( I -> Op1 ) . addImm ( I -> Op2 ) ) ;


<s> assert ( Op . isImm ( ) && <STR_LIT> ) ;

O << <ISA_LIT>BRCondCodeToString ( ( <STR_LIT> ) Op . getImm ( ) ) ;


<s> if ( ! IsNext ( Kind ) ) return Error ( std :: string ( <STR_LIT> ) + KindName + <STR_LIT> , Lexer . getTok ( ) ) ; return false ;


<s> rtx op0 = operands [ <NUM_LIT> ] ; if ( final_sequence && ! INSN_ANNULLED_BRANCH_P ( final_sequence -> insn ( <NUM_LIT> ) ) && get_attr_length ( final_sequence -> insn ( <NUM_LIT> ) ) ) { asm_fprintf ( asm_out_file , <STR_LIT> , logic ? <STR_LIT> : <STR_LIT> , ASSEMBLER_DIALECT ? <STR_LIT> : <STR_LIT> , label ) ; print_slot ( final_sequence ) ; } else asm_fprintf ( asm_out_file , <STR_LIT> , logic ? <STR_LIT> : <STR_LIT> , label ) ; output_asm_insn ( <STR_LIT> , & op0 ) ; fprintf ( asm_out_file , <STR_LIT> ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , label ) ; return <STR_LIT> ; } case <NUM_LIT> : return logic ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( ! TARGET_RELAX ) { int label = lf ++ ;

gcc_assert ( ! final_sequence || ! ( INSN_ANNULLED_BRANCH_P ( XVECEXP ( final_sequence , <NUM_LIT> , <NUM_LIT> ) ) ) ) ;


<s> MCExpr const * <ISA_LIT>MCExpr :: getExpr ( ) const {


<s> if ( II -> getOpcode ( ) == TargetOpcode :: KILL ) return false ; if ( II -> isImplicitDef ( ) ) return false ; if ( QII -> isSolo ( * II ) ) return false ; if ( QII -> isFloat ( * II ) ) return false ; bool HadDef = false ; for ( const MachineOperand & Op : II -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; if ( HadDef ) return false ; HadDef = true ; if ( ! <STR_LIT> . contains ( Op . getReg ( ) ) ) return false ; } assert ( HadDef ) ; for ( unsigned i = <NUM_LIT> ; i < II -> getNumOperands ( ) ; ++ i ) { if ( II -> getOperand ( i ) . isReg ( ) && ( II -> getOperand ( i ) . isUse ( ) || II -> getOperand ( i ) . isDef ( ) ) ) { MachineBasicBlock :: iterator localII = II ; ++ localII ; Register Reg = II -> getOperand ( i ) . getReg ( ) ; for ( MachineBasicBlock :: iterator localBegin = localII ; localBegin != end ; ++ localBegin ) { if ( localBegin == skip ) continue ; if ( localBegin -> modifiesRegister ( Reg , TRI ) || localBegin -> readsRegister ( Reg , TRI ) ) return false ;


<s> const Function * F = MF -> getFunction ( ) ; if ( TFI -> hasFP ( * MF ) ) return ( F -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_INTR ? CSR_FP_INTR_SaveList : CSR_FP_SaveList ) ;

else return ( F -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_INTR ? CSR_NoFP_INTR_SaveList : CSR_NoFP_SaveList ) ;


<s> ShuffleVectorSDNode * SVN = cast < ShuffleVectorSDNode > ( Op . getNode ( ) ) ; ArrayRef < int > ShuffleMask = SVN -> getMask ( ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; if ( SVN -> isSplat ( ) ) { int Lane = SVN -> getSplatIndex ( ) ; if ( Lane == - <NUM_LIT> ) Lane = <NUM_LIT> ; if ( Lane == <NUM_LIT> && V1 . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 . getOperand ( <NUM_LIT> ) ) ; if ( V1 . getOpcode ( ) == <STR_LIT> && ! isa < ConstantSDNode > ( V1 . getOperand ( Lane ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 . getOperand ( Lane ) ) ; unsigned Opcode = getDUPLANEOp ( V1 . getValueType ( ) . getVectorElementType ( ) ) ; return constructDup ( V1 , Lane , dl , VT , Opcode , DAG ) ; } for ( unsigned LaneSize : { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) { unsigned Lane = <NUM_LIT> ; if ( isWideDUPMask ( ShuffleMask , VT , LaneSize , Lane ) ) { unsigned Opcode = LaneSize == <NUM_LIT> ? <STR_LIT> : LaneSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MVT NewEltTy = <STR_LIT> ( LaneSize ) ; unsigned NewEltCount = VT . getSizeInBits ( ) / LaneSize ; MVT NewVecTy = <STR_LIT> ( NewEltTy , NewEltCount ) ; V1 = DAG . getBitcast ( NewVecTy , V1 ) ; V1 = constructDup ( V1 , Lane , dl , NewVecTy , Opcode , DAG ) ; return DAG . getBitcast ( VT , V1 ) ; } } if ( isREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 ) ; if ( isREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 ) ; if ( isREVMask ( ShuffleMask , VT , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 ) ; bool ReverseEXT = false ; unsigned Imm ; if ( isEXTMask ( ShuffleMask , VT , ReverseEXT , Imm ) ) { if ( ReverseEXT ) std :: swap ( V1 , V2 ) ; Imm *= getExtFactor ( V1 ) ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V2 , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ; } else if ( V2 -> isUndef ( ) && isSingletonEXTMask ( ShuffleMask , VT , Imm ) ) { Imm *= getExtFactor ( V1 ) ;

return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , V1 , DAG . getConstant ( Imm , dl , <STR_LIT> ) ) ;


<s> if ( TRC -> hasSuperClassEq ( MRI -> getRegClass ( FullReg ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << printReg ( FullReg ) << <STR_LIT> ) ; eraseInstrWithNoUses ( MI ) ; return FullReg ; } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } } } return optimizeAllLanesPattern ( MI , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( MI -> isRegSequence ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) { unsigned NumImplicit = <NUM_LIT> , NumTotal = <NUM_LIT> ; unsigned NonImplicitReg = ~ <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < MI -> getNumExplicitOperands ( ) ; ++ I ) { if ( ! MI -> getOperand ( I ) . isReg ( ) ) continue ; ++ NumTotal ; unsigned OpReg = MI -> getOperand ( I ) . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( OpReg ) ) break ;

MachineInstr * Def = MRI -> getVRegDef ( OpReg ) ;


<s> explicit Tile64FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {


<s> static DecodeStatus Decode2RSrcDstInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned Op1 , Op2 ; DecodeStatus S = Decode2OpInstruction ( Insn , Op1 , Op2 ) ; if ( S != MCDisassembler :: Success ) return Decode2OpInstructionFail ( Inst , Insn , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op2 , Address , Decoder ) ; return S ;


<s> output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( TARGET_16_BIT ) return <STR_LIT> ; else return <STR_LIT> ;


<s> return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> :


Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> if ( Inid == <STR_LIT> ) { int srcTensorId = GetTensorId ( Intrins -> getOperand ( <NUM_LIT> ) ) ; if ( TensorId != srcTensorId ) CopyIndSpace . insert ( std :: make_pair ( TensorId , srcTensorId ) ) ; } if ( Inid != <STR_LIT> && Inid != <STR_LIT> && Inid != <STR_LIT> ) continue ; int IndexShl = - <NUM_LIT> ; std :: string Formula = <STR_LIT> ; if ( Inid == <STR_LIT> ) { continue ; } else if ( Inid == <STR_LIT> ) { if ( dyn_cast < llvm :: ConstantInt > ( Intrins -> getOperand ( <NUM_LIT> ) ) ) { if ( dyn_cast < Instruction > ( Intrins -> getOperand ( <NUM_LIT> ) ) ) { if ( ! dyn_cast < ICmpInst > ( Intrins -> getOperand ( <NUM_LIT> ) ) ) FallBackVec . insert ( TensorId ) ; else { if ( auto * Icmp = dyn_cast < ICmpInst > ( Intrins -> getOperand ( <NUM_LIT> ) ) ) if ( ! dyn_cast < ConstantInt > ( Icmp -> getOperand ( <NUM_LIT> ) ) ) FallBackVec . insert ( TensorId ) ; } } IndexShl = dyn_cast < llvm :: ConstantInt > ( Intrins -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; CurrLoop = compareStepValuesForAddMask ( PHI , CurrLoop ) ; int64_t AddMaskStep = getAddMaskStepVar ( Intrins ) ; bool CheckIfNodeProcessed = iterateProcessedNodes ( TensorId , CurrLoop ) ; if ( AddMaskStep != INVALID_STRIDE ) { bool CopyPHI = false ; if ( iterateProcessedPHI ( PHI ) ) { if ( CheckIfNodeProcessed ) continue ; else CopyPHI = true ; } unsigned UnrollCount = <NUM_LIT> ; if ( getScevInfo ( CurrLoop ) ) { UnrollCount = getScevInfo ( CurrLoop ) -> getLoopUnrollCount ( CurrLoop ) ; } if ( UnrollCount ) AddMaskStep = AddMaskStep * UnrollCount ; unsigned Index = fetchIndexFromOperand ( IndexShl ) ; UpdateDiffCoords ( TensorId , Index , AddMaskStep , <STR_LIT> , CurrLoop , PHI ) ; prepareLoopIvCoordMap ( TensorId , nullptr , Index ) ; processNestedInstructions ( Intrins , CurrLoop , PHI , TensorId , CopyPHI , F ) ; continue ;


<s> if ( ! TM . isPositionIndependent ( ) || ! TM . getABI ( ) . IsO32 ( ) ) UseFastISel = false ;

return UseFastISel ? <STR_LIT> ( funcInfo , libInfo ) : nullptr ;


<s> for ( auto I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ) { MachineInstr & MI = * I ++ ; assert ( ! <STR_LIT> ( MI ) ) ; if ( MI . isDebugInstr ( ) || MI . isLabel ( ) ) continue ; Changed |= processInstruction ( MI , CurrentStack ) ; } bbInfo . setCalculatedEnd ( CurrentStack ) ; }


<s> unsigned Addr = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( ( <STR_LIT> == Addr ) && <STR_LIT> ) ; Out . EmitBundleLock ( false ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] , STI ) ;

EmitBICMask ( STI , Out , Addr , Pred , <NUM_LIT> ) ;


<s> bool <ISA_LIT>FrameLowering :: updateExitPaths ( MachineBasicBlock & MBB , MachineBasicBlock & RestoreB , BitVector & DoneT , BitVector & DoneF , BitVector & Path ) const { assert ( MBB . getNumber ( ) >= <NUM_LIT> ) ; unsigned BN = MBB . getNumber ( ) ; if ( Path [ BN ] || DoneF [ BN ] ) return false ; if ( DoneT [ BN ] ) return true ; auto & CSI = MBB . getParent ( ) -> getFrameInfo ( ) . getCalleeSavedInfo ( ) ; Path [ BN ] = true ; bool ReachedExit = false ; for ( auto & SB : MBB . successors ( ) ) ReachedExit |= updateExitPaths ( * SB , RestoreB , DoneT , DoneF , Path ) ; if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MachineInstr & RetI = MBB . back ( ) ; if ( ! isRestoreCall ( RetI . getOpcode ( ) ) ) for ( auto & R : CSI ) RetI . addOperand ( MachineOperand :: CreateReg ( R . getReg ( ) , false , true ) ) ;


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) , false ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ; if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ;

addPass ( create<ISA_LIT>Packetizer ( ) , false ) ;


<s> TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; LLVM_DEBUG ( MF . dump ( ) ) ; for ( const auto & MBB : MF ) { Chains . clear ( ) ; for ( const auto & MI : MBB ) { for ( auto r : Chains ) { SmallVector < unsigned , <NUM_LIT> > toDel ; if ( regJustKilledBefore ( LIs , r , MI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( r , TRI ) << <STR_LIT> ; MI . print ( dbgs ( ) ) ; ) ; toDel . push_back ( r ) ; } while ( ! toDel . empty ( ) ) { Chains . remove ( toDel . back ( ) ) ; toDel . pop_back ( ) ; } } switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( addIntraChainConstraint ( G , Rd , Ra ) ) addInterChainConstraint ( G , Rd , Ra ) ; break ; } case <STR_LIT> : case <STR_LIT> : { unsigned Rd = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; addInterChainConstraint ( G , Rd , Rd ) ;


<s> Value = ( Value & <NUM_LIT> ) >> <NUM_LIT> ; ldi :: fixup ( Size , Fixup , Value , Ctx ) ;


<s> if ( FPOffsetFits && PreferFP ) UseFP = true ; } } } assert ( ( ( isFixed || isCSR ) || ! RegInfo -> needsStackRealignment ( MF ) || ! UseFP ) && <STR_LIT> <STR_LIT> ) ; if ( isSVE ) { int64_t OffsetFromSPToSVEArea = MFI . getStackSize ( ) - AFI -> getCalleeSavedStackSize ( ) ; int64_t OffsetFromFPToSVEArea = - AFI -> getCalleeSaveBaseToFrameRecordOffset ( ) ; StackOffset FPOffset = StackOffset ( OffsetFromFPToSVEArea , <STR_LIT> ) + StackOffset ( ObjectOffset , <STR_LIT> ) ; StackOffset SPOffset = SVEStackSize + StackOffset ( ObjectOffset , <STR_LIT> ) + StackOffset ( OffsetFromSPToSVEArea , <STR_LIT> ) ; if ( hasFP ( MF ) && ( SPOffset . getBytes ( ) || FPOffset . getScalableBytes ( ) < SPOffset . getScalableBytes ( ) || RegInfo -> needsStackRealignment ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } FrameReg = RegInfo -> hasBasePointer ( MF ) ? RegInfo -> getBaseRegister ( ) : ( unsigned ) <STR_LIT> ; return SPOffset ; } StackOffset ScalableOffset = { } ; if ( UseFP && ! ( isFixed || isCSR ) ) ScalableOffset = - SVEStackSize ;

if ( ! UseFP && ( isFixed || isCSR ) ) ScalableOffset = SVEStackSize ;


<s> pat = PATTERN ( insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( pat ) != SET ) return false ; subrtx_iterator :: array_type array ;

FOR_EACH_SUBRTX ( iter , array , SET_SRC ( pat ) , NONCONST ) {


<s> case UDIV : case UMOD : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case SIGN_EXTEND : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case ZERO_EXTEND : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case CONST_INT : * total = <NUM_LIT> ; break ; case LABEL_REF : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; break ; case CONST : { rtx offset = const0_rtx ; rtx symref = eliminate_constant_term ( XEXP ( x , <NUM_LIT> ) , & offset ) ; if ( GET_CODE ( symref ) == LABEL_REF ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( GET_CODE ( symref ) != SYMBOL_REF ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( INTVAL ( offset ) < - <NUM_LIT> || INTVAL ( offset ) > <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( SYMBOL_REF_FLAG ( symref ) ? <NUM_LIT> : <NUM_LIT> ) ; break ; } case SYMBOL_REF : * total = COSTS_N_INSNS ( SYMBOL_REF_FLAG ( x ) ? <NUM_LIT> : <NUM_LIT> ) ; break ; case CONST_DOUBLE : { rtx high , low ; split_double ( x , & high , & low ) ; * total = COSTS_N_INSNS ( ( high == CONST0_RTX ( GET_MODE ( high ) ) || low == CONST0_RTX ( GET_MODE ( low ) ) ) ? <NUM_LIT> : <NUM_LIT> ) ; break ; } default : return false ; }


<s> if ( J -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & ReturnMBB ) { MIB = BuildMI ( * * PI , J , J -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( J -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( J -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MIB . copyImplicitOps ( I ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> getOpcode ( ) == <STR_LIT> || J -> getOpcode ( ) == <STR_LIT> ) { if ( J -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & ReturnMBB ) { MIB = BuildMI ( * * PI , J , J -> getDebugLoc ( ) , TII -> get ( J -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addReg ( J -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MIB . copyImplicitOps ( I ) ; MachineBasicBlock :: iterator K = J -- ; K -> eraseFromParent ( ) ; BlockChanged = true ; ++ NumBCLR ; continue ; } } else if ( J -> isBranch ( ) ) { if ( J -> isIndirectBranch ( ) ) { if ( ReturnMBB . hasAddressTaken ( ) ) OtherReference = true ; } else for ( unsigned i = <NUM_LIT> ; i < J -> getNumOperands ( ) ; ++ i ) if ( J -> getOperand ( i ) . isMBB ( ) && J -> getOperand ( i ) . getMBB ( ) == & ReturnMBB ) OtherReference = true ; } else if ( ! J -> isTerminator ( ) && ! J -> isDebugValue ( ) ) break ; if ( J == ( * PI ) -> begin ( ) ) break ; -- J ; } if ( ( * PI ) -> canFallThrough ( ) && ( * PI ) -> isLayoutSuccessor ( & ReturnMBB ) ) OtherReference = true ; if ( ! OtherReference && BlockChanged ) { PredToRemove . push_back ( * PI ) ; } if ( BlockChanged ) Changed = true ; } for ( unsigned i = <NUM_LIT> , ie = PredToRemove . size ( ) ; i != ie ; ++ i ) PredToRemove [ i ] -> removeSuccessor ( & ReturnMBB ) ; if ( Changed && ! ReturnMBB . hasAddressTaken ( ) ) { if ( ReturnMBB . pred_size ( ) == <NUM_LIT> ) { MachineBasicBlock & PrevMBB = * * ReturnMBB . pred_begin ( ) ; if ( PrevMBB . isLayoutSuccessor ( & ReturnMBB ) && PrevMBB . canFallThrough ( ) ) { PrevMBB . splice ( PrevMBB . end ( ) , & ReturnMBB , I ) ; PrevMBB . removeSuccessor ( & ReturnMBB ) ; }


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned GPR3 = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned Opc1 , Opc2 ; const unsigned OrigRegs [ ] = { OutReg , InReg , GPR3 } ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; case <STR_LIT> : Opc1 = <STR_LIT> ; Opc2 = <STR_LIT> ; break ; } BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ;

MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 ) , GPR3 ) . addReg ( GPR3 ) ) ;


<s> if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , Inst ) . mayStore ( ) ) { unsigned Units = ISJ . Core . getUnits ( ) ; if ( Units & Slot1Mask ) { AppliedRestriction = true ; AppliedRestrictions . push_back ( std :: make_pair ( Inst . getLoc ( ) , <STR_LIT> ) ) ; ISJ . Core . setUnits ( Units & ~ Slot1Mask ) ; } } } if ( AppliedRestriction ) AppliedRestrictions . push_back ( std :: make_pair ( * Summary . NoSlot1StoreLoc , <STR_LIT> ) ) ;


<s> <STR_LIT> CC2 = cast < CondCodeSDNode > ( Op2 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue * K1 = isa < ConstantSDNode > ( LHS1 ) ? & LHS1 : isa < ConstantSDNode > ( RHS1 ) ? & RHS1 : NULL ; SDValue * K2 = isa < ConstantSDNode > ( LHS2 ) ? & LHS2 : isa < ConstantSDNode > ( RHS2 ) ? & RHS2 : NULL ; SDValue K2Tmp = isa < ConstantSDNode > ( TrueVal2 ) ? TrueVal2 : FalseVal2 ; SDValue V1Tmp = ( K1 && * K1 == LHS1 ) ? RHS1 : LHS1 ; SDValue V2Tmp = ( K2 && * K2 == LHS2 ) ? RHS2 : LHS2 ; SDValue V2 = ( K2Tmp == TrueVal2 ) ? FalseVal2 : TrueVal2 ; SDValue V2TmpReg = V2Tmp ; if ( V2Tmp -> getOpcode ( ) == <STR_LIT> ) V2TmpReg = V2Tmp -> getOperand ( <NUM_LIT> ) ; if ( ! K1 || ! K2 || * K1 == Op2 || * K2 != K2Tmp || V1Tmp != V2Tmp || V2TmpReg != V2 ) return false ; const SDValue * LowerCheckOp = isLowerSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isLowerSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : NULL ; const SDValue * UpperCheckOp = isUpperSaturate ( LHS1 , RHS1 , TrueVal1 , FalseVal1 , CC1 , * K1 ) ? & Op : isUpperSaturate ( LHS2 , RHS2 , TrueVal2 , FalseVal2 , CC2 , * K2 ) ? & Op2 : NULL ; if ( ! UpperCheckOp || ! LowerCheckOp || LowerCheckOp == UpperCheckOp ) return false ; int64_t Val1 = cast < ConstantSDNode > ( * K1 ) -> getSExtValue ( ) ; int64_t Val2 = cast < ConstantSDNode > ( * K2 ) -> getSExtValue ( ) ; int64_t PosVal = std :: max ( Val1 , Val2 ) ; if ( ( ( Val1 > Val2 && UpperCheckOp == & Op ) || ( Val1 < Val2 && UpperCheckOp == & Op2 ) ) && Val1 == ~ Val2 && isPowerOf2_64 ( PosVal + <NUM_LIT> ) ) { V = V2 ; K = ( uint64_t ) PosVal ; return true ; } return false ;


<s> for ( auto Curr : Blocks ) delete Curr ; for ( auto Curr : Shapes ) delete Curr ;


<s> case <STR_LIT> : return lowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return lowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return lowerSETCC ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVAARG ( Op , DAG ) ; case <STR_LIT> : return lowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE ( Op , DAG ) ;

case <STR_LIT> : return lowerADD ( Op , DAG ) ;


<s> <STR_LIT> ( ID , <ISA_LIT>Features ) ; <STR_LIT> ( <STR_LIT> ( <STR_LIT> , ID ) , <ISA_LIT>Features ) ; MCSubtargetInfo & STI = copySTI ( ) ; std :: vector < std :: string > ArchFeatures ( <ISA_LIT>Features . begin ( ) , <ISA_LIT>Features . end ( ) ) ; STI . setDefaultFeatures ( <STR_LIT> , join ( ArchFeatures . begin ( ) , ArchFeatures . end ( ) , <STR_LIT> ) ) ; SmallVector < StringRef , <NUM_LIT> > RequestedExtensions ; if ( ! ExtensionString . empty ( ) ) ExtensionString . split ( RequestedExtensions , '+' ) ; ExpandCryptoAEK ( ID , RequestedExtensions ) ; FeatureBitset Features = STI . getFeatureBits ( ) ; for ( auto Name : RequestedExtensions ) { bool EnableFeature = true ; if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ;


<s> Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = <NUM_LIT> ; unsigned index = <NUM_LIT> ; unsigned inc = <NUM_LIT> ; switch ( size ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

} else Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;


<s> if ( isUInt < <NUM_LIT> > ( FrameSize ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( FrameSize ) ; else { int Base = <NUM_LIT> ; int64_t Remainder = FrameSize - Base ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addImm ( Base ) ; if ( isInt < <NUM_LIT> > ( - Remainder ) ) BuildAddiuSpImm ( MBB , I , - Remainder ) ; else adjustStackPtrBig ( SP , - Remainder , MBB , I , <STR_LIT> , <STR_LIT> ) ; } } else { MachineInstrBuilder MIB1 = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ;


<s> continue ; } if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) { break ; } if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ;


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , uint8_t _OSABI ) : <ISA_LIT>AsmBackend ( T , TT ) , OSABI ( _OSABI ) {


assert ( ( ( unsigned long ) __P & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> return ( float32x4_t ) __builtin_neon_vdup_lanev4sf ( __a , __b ) ;


<s> static const <ISA_LIT>MCExpr * CreateHi ( const MCExpr * Expr , MCContext & Ctx ) {

return Create ( VK_<ISA_LIT>_HI , Expr , Ctx ) ;


<s> void collectReachableCallees ( Module & M , DenseMap < Function * , SmallPtrSet < Function * , <NUM_LIT> >> & KernelToCallees ) {


<s> unsigned ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned scratch = ( ! BinOpcode ) ? incr : MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( incr ) . addReg ( dest ) . addImm ( <NUM_LIT> ) ; else BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch ) . addReg ( dest ) . addReg ( incr ) . addImm ( <NUM_LIT> ) ; } unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ;

BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) . addReg ( scratch ) . addReg ( ptr ) ;


<s> else { i960_maxbitalignment = <NUM_LIT> ; i960_last_maxbitalignment = <NUM_LIT> ; }


<s> bool MatchInstruction ( SMLoc IDLoc , const SmallVectorImpl < MCParsedAsmOperand * > & Operands , MCInst & Inst ) {

if ( ! MatchInstructionImpl ( Operands , Inst ) ) return false ;


<s> if ( align < <NUM_LIT> ) { rtx scratch1 = gen_reg_rtx ( Pmode ) ; emit_move_insn ( scratch1 , out ) ; if ( align != <NUM_LIT> ) { align_3_label = gen_label_rtx ( ) ; align_2_label = gen_label_rtx ( ) ; align_rtx = expand_binop ( Pmode , and_optab , scratch1 , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( align_rtx , const0_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_4_label ) ; emit_cmp_and_jump_insns ( align_rtx , const2_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_2_label ) ; emit_cmp_and_jump_insns ( align_rtx , const2_rtx , GTU , NULL , Pmode , <NUM_LIT> , align_3_label ) ; } else { align_rtx = expand_binop ( Pmode , and_optab , scratch1 , const2_rtx , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; emit_cmp_and_jump_insns ( align_rtx , const0_rtx , EQ , NULL , Pmode , <NUM_LIT> , align_4_label ) ; } mem = change_address ( src , QImode , out ) ; emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( ix86_gen_add3 ( out , out , const1_rtx ) ) ; if ( align != <NUM_LIT> ) { emit_label ( align_2_label ) ; emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( ix86_gen_add3 ( out , out , const1_rtx ) ) ; emit_label ( align_3_label ) ; } emit_cmp_and_jump_insns ( mem , const0_rtx , EQ , NULL , QImode , <NUM_LIT> , end_0_label ) ; emit_insn ( ix86_gen_add3 ( out , out , const1_rtx ) ) ; }


<s> MachineInstr & Clone = TII -> duplicate ( MBB , Insert , * MI ) ; for ( unsigned i = <NUM_LIT> , e = Clone . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = Clone . getOperand ( i ) ; if ( MO . isReg ( ) && MO . getReg ( ) == Reg ) MO . setReg ( TargetReg ) ;


<s> case TargetOpcode :: INLINEASM : { const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const char * AsmStr = MI -> getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; }


<s> uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> emitXCOFFLocalCommonSymbol ( OutContext . getOrCreateSymbol ( GVSym -> getUnqualifiedName ( ) ) , Size , GVSym , Alignment . value ( ) ) ; else OutStreamer -> emitCommonSymbol ( GVSym , Size , Alignment . value ( ) ) ; return ; } MCSymbol * EmittedInitSym = GVSym ; emitLinkage ( GV , EmittedInitSym ) ; emitAlignment ( getGVAlignment ( GV , DL ) , GV ) ; OutStreamer -> emitLabel ( EmittedInitSym ) ; llvm :: for_each ( GOAliasMap [ GV ] , [ this ] ( const GlobalAlias * Alias ) { OutStreamer -> emitLabel ( getSymbol ( Alias ) ) ; } ) ;

emitGlobalConstant ( GV -> getParent ( ) -> getDataLayout ( ) , GV -> getInitializer ( ) ) ;


<s> case <STR_LIT> : unsigned Hi4 = ( Value & <NUM_LIT> ) >> <NUM_LIT> ; unsigned Lo12 = Value & <NUM_LIT> ; Value = ( Hi4 << <NUM_LIT> ) | ( Lo12 ) ;


<s> if ( IsConstVectorInRange ( Operands [ <NUM_LIT> ] , <NUM_LIT> , ScalarVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) && Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> && Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) { SDValue VecOnes = DAG . getConstant ( <NUM_LIT> , DL , InVT ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , InVT , Operands [ <NUM_LIT> ] , VecOnes ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] ) ; return SplitBinaryOpsAndApply ( DAG , Subtarget , DL , VT , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT> ] , AVGBuilder ) ; } if ( Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; else if ( Operands [ <NUM_LIT> ] . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! IsConstVectorInRange ( Operands [ i ] , <NUM_LIT> , <NUM_LIT> ) ) continue ;

std :: swap ( Operands [ i ] , Operands [ <NUM_LIT> ] ) ;


std :: sort ( children . begin ( ) , children . end ( ) , CostLeafCMP ( ) ) ;


<s> case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addImm ( <NUM_LIT> ) ; SpillsKnownBit = true ; break ; case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addImm ( - <NUM_LIT> ) ; SpillsKnownBit = true ; break ; default : if ( Subtarget . isISA3_1 ( ) ) { BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( SrcReg , RegState :: Undef ) ; break ; } if ( Subtarget . isISA3_0 ( ) ) { if ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) { BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) , RegState :: Undef ) ; break ; } } BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) , RegState :: Undef ) . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; Register Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ;

BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> if ( Ord == AtomicOrdering :: SequentiallyConsistent ) return callIntrinsic ( Builder , <STR_LIT> ) ;

if ( isReleaseOrStronger ( Ord ) ) return callIntrinsic ( Builder , <STR_LIT> ) ;


<s> rtx tmp_reg = dest ; machine_mode mode = GET_MODE ( dest ) ; gcc_assert ( mode == Pmode || mode == ptr_mode ) ; if ( can_create_pseudo_p ( ) ) tmp_reg = gen_reg_rtx ( mode ) ; emit_move_insn ( tmp_reg , gen_rtx_HIGH ( mode , imm ) ) ; emit_insn ( gen_add_losym ( dest , tmp_reg , imm ) ) ; return ; } case SYMBOL_TINY_ABSOLUTE : emit_insn ( gen_rtx_SET ( Pmode , dest , imm ) ) ; return ; case SYMBOL_SMALL_GOT : { rtx tmp_reg = dest ; machine_mode mode = GET_MODE ( dest ) ; if ( can_create_pseudo_p ( ) ) tmp_reg = gen_reg_rtx ( mode ) ; emit_move_insn ( tmp_reg , gen_rtx_HIGH ( mode , imm ) ) ; if ( mode == ptr_mode ) { if ( mode == DImode ) emit_insn ( gen_ldr_got_small_di ( dest , tmp_reg , imm ) ) ; else emit_insn ( gen_ldr_got_small_si ( dest , tmp_reg , imm ) ) ; } else { gcc_assert ( mode == Pmode ) ; emit_insn ( gen_ldr_got_small_sidi ( dest , tmp_reg , imm ) ) ; } return ; } case SYMBOL_SMALL_TLSGD : { rtx_insn * insns ; rtx result = gen_rtx_REG ( Pmode , R0_REGNUM ) ; start_sequence ( ) ; aarch64_emit_call_insn ( gen_tlsgd_small ( result , imm ) ) ; insns = get_insns ( ) ; end_sequence ( ) ; RTL_CONST_CALL_P ( insns ) = <NUM_LIT> ; emit_libcall_block ( insns , dest , result , imm ) ;


<s> if ( CPUString . empty ( ) ) CPUString = <STR_LIT> ; ParseSubtargetFeatures ( CPUString , FS ) ;


<s> if ( Offset > <NUM_LIT> ) Offset -= OffsetStride ; if ( ! inBoundsForPair ( IsUnscaled , Offset , OffsetStride ) ) return false ; LdStPairFlags Flags ; MachineBasicBlock :: iterator Paired = findMatchingInsn ( MBBI , Flags , LdStLimit , false ) ; if ( Paired != E ) { ++ NumPairCreated ; if ( TII -> hasUnscaledLdStOffset ( MI ) ) ++ NumUnscaledPairCreated ; auto Prev = std :: prev ( MBBI ) ; MBBI = mergePairedInsns ( MBBI , Paired , Flags ) ; for ( auto I = std :: next ( Prev ) ; I != MBBI ; I ++ ) updateDefinedRegisters ( * I , DefinedInBB , TRI ) ; return true ;


<s> newd . target = d -> target ? gen_lowpart ( new_mode , d -> target ) : NULL ; newd . op0 = d -> op0 ? gen_lowpart ( new_mode , d -> op0 ) : NULL ; newd . op1 = d -> op1 ? gen_lowpart ( new_mode , d -> op1 ) : NULL ; newd . testing_p = d -> testing_p ; newd . one_vector_p = d -> one_vector_p ; newd . perm . new_vector ( newpermconst , newd . one_vector_p ? <NUM_LIT> : <NUM_LIT> , nelt / <NUM_LIT> ) ;

return aarch64_expand_vec_perm_const_1 ( & newd ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> return Sec . find ( <STR_LIT> ) != StringRef :: npos || Sec . find ( <STR_LIT> ) != StringRef :: npos || Sec . find ( <STR_LIT> ) != StringRef :: npos ;


<s> unsigned ResultReg ; if ( WantResult ) ResultReg = createResultReg ( RC ) ; else ResultReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & II = TII . get ( Opc ) ; LHSReg = constrainOperandRegClass ( II , LHSReg , II . getNumDefs ( ) ) ; RHSReg = constrainOperandRegClass ( II , RHSReg , II . getNumDefs ( ) + <NUM_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( LHSReg , getKillRegState ( LHSIsKill ) ) . addReg ( RHSReg , getKillRegState ( RHSIsKill ) ) ;


<s> const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; bool SeenFI = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isFI ( ) ) { if ( SeenFI ) llvm_unreachable ( <STR_LIT> ) ; SeenFI = true ; } } MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ; assert ( FIOp && FIOp -> isFI ( ) && <STR_LIT> ) ; assert ( TII -> isMUBUF ( MI ) ) ;

MachineOperand * OffsetOp = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ;


<s> if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ;


<s> AddInstr ( SeqLs , Inst ( ADDiu , Imm & <NUM_LIT> ) ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; SDValue Chain = OrigChain . getOperand ( <NUM_LIT> ) ; if ( Chain . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else { assert ( Chain . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Chain . getNumOperands ( ) ; i != e ; ++ i ) if ( Chain . getOperand ( i ) . getNode ( ) == Load . getNode ( ) ) Ops . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; else Ops . push_back ( Chain . getOperand ( i ) ) ; SDValue NewChain = CurDAG -> getNode ( <STR_LIT> , SDLoc ( Load ) , <STR_LIT> , Ops ) ; Ops . clear ( ) ;


<s> if ( DCI . Level != BeforeLegalizeTypes ) return SDValue ( ) ; unsigned Opcode = N -> getOpcode ( ) ; EVT OutVT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OutScalarBits = OutVT . getScalarSizeInBits ( ) ; unsigned InScalarBits = Op -> getValueType ( <NUM_LIT> ) . getScalarSizeInBits ( ) ; if ( OutVT . isVector ( ) && OutScalarBits > InScalarBits ) { MVT ExtVT = <STR_LIT> ( <STR_LIT> ( OutVT . getScalarSizeInBits ( ) ) , OutVT . getVectorNumElements ( ) ) ; unsigned ExtOpcode = ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue ExtOp = DAG . getNode ( ExtOpcode , SDLoc ( N ) , ExtVT , Op ) ;

return DAG . getNode ( Opcode , SDLoc ( N ) , OutVT , ExtOp ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return false ;


<s> static DecodeStatus DecodeADRFRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { bool VPUEncoding = Inst . getFlags ( ) != FlagSPU ; unsigned Register ; if ( VPUEncoding ) { if ( RegNo > <NUM_LIT> || RegNo < <NUM_LIT> ) return MCDisassembler :: Fail ; Register = RegisterTableVPU [ RegNo ] ; } else { if ( RegNo >= <NUM_LIT> || RegNo < <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ; RTLIB :: Libcall LC ;


<s> extern __inline __m256h __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_load_ph ( void const * __P ) { return * ( const __m256h * ) __P ;


<s> return decodeRegisterClass ( Inst , RegNo , VFRegs ) ;


<s> if ( getSTI ( ) . getTargetTriple ( ) . getOS ( ) != Triple :: AMDPAL ) { return Error ( getParser ( ) . getTok ( ) . getLoc ( ) , ( Twine ( PALMD :: AssemblerDirective ) + Twine ( <STR_LIT> <STR_LIT> ) ) . str ( ) ) ; } PALMD :: Metadata PALMetadata ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail || getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return ResTy ; ResTy = parseRegOrImm ( Operands ) ; if ( ResTy == MatchOperand_Success ) return ResTy ; if ( getLexer ( ) . getKind ( ) == AsmToken :: Identifier ) { const auto & Tok = Parser . getTok ( ) ; SMLoc S = Tok . getLoc ( ) ; const MCExpr * Expr = nullptr ;

if ( ! Parser . parseExpression ( Expr ) ) {


<s> const MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( auto FI = dyn_cast < FrameIndexSDNode > ( N ) ) {

SDValue TFI = CurDAG -> getTargetFrameIndex ( FI -> getIndex ( ) , FI -> getValueType ( <NUM_LIT> ) ) ;


<s> RegInterval Interval = getRegInterval ( MI , TII , MRI , TRI , OpNo , false ) ; LLVM_DEBUG ( { const MachineOperand & Opnd = MI -> getOperand ( OpNo ) ;

assert ( TRI -> isVGPR ( * MRI , Opnd . getReg ( ) ) ) ;


<s> unsigned Reg = DFPRegDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ;


<s> } unsigned NumLiterals = ! TII . isInlineConstant ( APInt ( <NUM_LIT> , ConstOffset & <NUM_LIT> ) ) + ! TII . isInlineConstant ( APInt ( <NUM_LIT> , ConstOffset >> <NUM_LIT> ) ) ; if ( STI . getConstantBusLimit ( <STR_LIT> ) > NumLiterals ) return None ; } } } auto AddrDef = getDefSrcRegIgnoringCopies ( Addr , * MRI ) ; if ( ! AddrDef ) return None ; if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { Register SAddr = getSrcRegIgnoringCopies ( AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( SAddr && isSGPR ( SAddr ) ) { Register PtrBaseOffset = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register VOffset = matchZeroExtendFromS32 ( * MRI , PtrBaseOffset ) ) { return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( SAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( VOffset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } } ; } } } if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> || AddrDef -> MI -> getOpcode ( ) == <STR_LIT> || ! isSGPR ( AddrDef -> Reg ) ) return None ; MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; Register VOffset = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , VOffset ) . addImm ( <NUM_LIT> ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( AddrDef -> Reg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( VOffset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; }


<s> return rs6000_builtin_info [ ( int ) fncode ] . name ;


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ;


<s> LastEMS = LastMappingSymbols . lookup ( Section ) ;

MCELFStreamer :: ChangeSection ( Section , Subsection ) ;


<s> if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CCode , DL , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( Op0 . getValueType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isOneConstant ( Op1 ) ) { <STR_LIT> NewCC = <STR_LIT> :: getSetCCInverse ( CC , true ) ; return DAG . getSetCC ( DL , VT , Op0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , NewCC ) ;


<s> } if ( Mld -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT VT = Mld -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT LdVT = Mld -> getMemoryVT ( ) ; SDLoc dl ( Mld ) ; assert ( LdVT != VT && <STR_LIT> ) ; unsigned ToSz = VT . getScalarSizeInBits ( ) ; unsigned FromSz = LdVT . getScalarSizeInBits ( ) ; assert ( isPowerOf2_32 ( NumElems * FromSz * ToSz ) && <STR_LIT> ) ; unsigned SizeRatio = ToSz / FromSz ; assert ( SizeRatio * NumElems * FromSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LdVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDValue WideSrc0 = DAG . getBitcast ( WideVecVT , Mld -> getSrc0 ( ) ) ; if ( ! Mld -> getSrc0 ( ) . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WideVecVT ) && <STR_LIT> ) ; WideSrc0 = DAG . getVectorShuffle ( WideVecVT , dl , WideSrc0 , DAG . getUNDEF ( WideVecVT ) , ShuffleVec ) ; } SDValue NewMask ; SDValue Mask = Mld -> getMask ( ) ; if ( Mask . getValueType ( ) == VT ) { NewMask = DAG . getBitcast ( WideVecVT , Mask ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i ] = i * SizeRatio ; for ( unsigned i = NumElems ; i != NumElems * SizeRatio ; ++ i ) ShuffleVec [ i ] = NumElems * SizeRatio ; NewMask = DAG . getVectorShuffle ( WideVecVT , dl , NewMask , DAG . getConstant ( <NUM_LIT> , dl , WideVecVT ) , ShuffleVec ) ; } else { assert ( Mask . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) ; unsigned WidenNumElts = NumElems * SizeRatio ; unsigned MaskNumElts = VT . getVectorNumElements ( ) ; EVT NewMaskVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , WidenNumElts ) ; unsigned NumConcat = WidenNumElts / MaskNumElts ;

SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat ) ;


<s> MachineInstr * First = Add ; MachineInstr * Last = Ldst ; if ( MDT -> dominates ( Ldst , Add ) ) std :: swap ( First , Last ) ; else if ( ! MDT -> dominates ( Add , Ldst ) ) return nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * First << * Last ) ; unsigned BasePos , OffPos ; if ( ! AII -> getBaseAndOffsetPosition ( * Ldst , BasePos , OffPos ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } Register BaseReg = Ldst -> getOperand ( BasePos ) . getReg ( ) ; if ( Ldst -> mayStore ( ) && Ldst -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { Register StReg = Ldst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Add -> getOperand ( <NUM_LIT> ) . getReg ( ) == StReg || BaseReg == StReg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } } SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterLdst ; SmallVector < MachineInstr * , <NUM_LIT> > UsesAfterAdd ; for ( MachineInstr & MI : MRI -> use_nodbg_instructions ( BaseReg ) ) { if ( & MI == Ldst || & MI == Add ) continue ; if ( & MI != Add && MDT -> dominates ( Ldst , & MI ) ) UsesAfterLdst . push_back ( & MI ) ; else if ( ! MDT -> dominates ( & MI , Ldst ) ) return nullptr ; if ( MDT -> dominates ( Add , & MI ) ) UsesAfterAdd . push_back ( & MI ) ; } MachineInstr * Result = nullptr ; if ( First == Add ) {

if ( noUseOfAddBeforeLoadOrStore ( First , Last ) ) {


<s> const char * rs6000_indirect_call_template ( rtx * operands , unsigned int funop ) {

return rs6000_indirect_call_template_1 ( operands , funop , false ) ;


<s> SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue Tmp4 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue A64cc ; SDValue CmpOp = getSelectableIntSetCC ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , A64cc , DAG , dl ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , CmpOp , DAG . getConstant ( <NUM_LIT> , Tmp4 . getValueType ( ) ) , Tmp4 , A64cc ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , VT , CmpOp , Tmp3 , FalseVal , A64cc ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ;

return DAG . getMergeValues ( Ops , <NUM_LIT> , dl ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result ;


<s> if ( MI . mayLoad ( ) && ! MI . isInvariantLoad ( & AA ) ) Read = true ; if ( MI . mayStore ( ) ) { Write = true ; for ( auto MMO : MI . memoperands ( ) ) { const MachinePointerInfo & MPI = MMO -> getPointerInfo ( ) ; if ( MPI . V . is < const PseudoSourceValue * > ( ) ) { auto PSV = MPI . V . get < const PseudoSourceValue * > ( ) ; if ( const ExternalSymbolPseudoSourceValue * EPSV = dyn_cast < ExternalSymbolPseudoSourceValue > ( PSV ) ) if ( StringRef ( EPSV -> getSymbol ( ) ) == <STR_LIT> ) StackPointer = true ; } } } else if ( MI . hasOrderedMemoryRef ( ) ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ;


<s> FunctionPass * llvm :: create<ISA_LIT>FlagsCopyLoweringPass ( ) {

return new <ISA_LIT>FlagsCopyLoweringPass ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> } if ( off != <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , off ) ; return true ; } HOST_WIDE_INT val ; switch ( GET_CODE ( x ) ) { case CONST_INT : val = INTVAL ( x ) ; break ; case CONST_DOUBLE : gcc_unreachable ( ) ; break ; default : gcc_unreachable ( ) ; } nvptx_assemble_value ( val , size ) ; return true ;


<s> void tilepro_expand_smulsi3_highpart ( rtx op0 , rtx op1 , rtx op2 ) {


<s> break ; case COND_INC_INSN : if ( cond ) c_insn = gen_incscc ( dst , dst ) ; else c_insn = gen_incscc_false ( dst , dst ) ; break ; case COND_DEC_INSN : if ( cond ) c_insn = gen_decscc ( dst , dst ) ; else c_insn = gen_decscc_false ( dst , dst ) ; break ; case COND_BRANCH_INSN : if ( cond ) c_insn = gen_branch_true ( dst ) ; else c_insn = gen_branch_false ( dst ) ; break ; default : return NULL ; }

if ( rtx_length [ GET_CODE ( c_insn ) ] >= <NUM_LIT> && rtx_length [ GET_CODE ( insn ) ] >= <NUM_LIT> ) {


<s> DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> << TargetMBB . getNumber ( ) << <STR_LIT> ) ; for ( auto & Def : MI . defs ( ) ) { for ( auto & Use : MRI -> use_instructions ( Def . getReg ( ) ) ) { if ( Use . isPHI ( ) && Use . getParent ( ) == & TargetMBB ) {


<s> if ( auto * BV = dyn_cast < BuildVectorSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) { if ( ! BV -> isConstant ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT IntVT = BV -> getValueType ( <NUM_LIT> ) ; SDValue SourceConst ; if ( IsStrict ) SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , { VT , <STR_LIT> } , { N -> getOperand ( <NUM_LIT> ) , SDValue ( BV , <NUM_LIT> ) } ) ; else SourceConst = DAG . getNode ( N -> getOpcode ( ) , DL , VT , SDValue ( BV , <NUM_LIT> ) ) ; SDValue MaskConst = DAG . getBitcast ( IntVT , SourceConst ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , IntVT , Op0 -> getOperand ( <NUM_LIT> ) , MaskConst ) ;

SDValue Res = DAG . getBitcast ( VT , NewAnd ) ;


<s> Entry . isSExt = true ; Args . push_back ( Entry ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; return CallResult . second ;


<s> static bool isValidClauseInst ( const MachineInstr & MI , bool IsVMEMClause ) { if ( MI . isDebugValue ( ) || MI . isBundled ( ) ) return false ;

if ( ! MI . mayLoad ( ) || MI . mayStore ( ) ) return false ;


<s> bool bisReversable = true ; if ( isStoreInst ( MCB . getOperand ( j ) . getInst ( ) -> getOpcode ( ) ) && isStoreInst ( MCB . getOperand ( k ) . getInst ( ) -> getOpcode ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << k << <STR_LIT> << j << <STR_LIT> ) ; bisReversable = false ; } if ( <ISA_LIT>MCInstrInfo :: isMemReorderDisabled ( MCB ) ) bisReversable = false ; if ( isOrderedDuplexPair ( MCII , * MCB . getOperand ( k ) . getInst ( ) , <ISA_LIT>MCInstrInfo :: hasExtenderForIndex ( MCB , k - <NUM_LIT> ) , * MCB . getOperand ( j ) . getInst ( ) , <ISA_LIT>MCInstrInfo :: hasExtenderForIndex ( MCB , j - <NUM_LIT> ) , bisReversable , STI ) ) { unsigned iClass = iClassOfDuplexPair ( getDuplexCandidateGroup ( * MCB . getOperand ( k ) . getInst ( ) ) , getDuplexCandidateGroup ( * MCB . getOperand ( j ) . getInst ( ) ) ) ; duplexToTry . push_back ( DuplexCandidate ( j , k , iClass ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << j << <STR_LIT> << k << <STR_LIT> << MCB . getOperand ( j ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> << MCB . getOperand ( k ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> ) ; continue ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << j << <STR_LIT> << k << <STR_LIT> << MCB . getOperand ( j ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> << MCB . getOperand ( k ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>VectorPrint ( ) { return new <ISA_LIT>VectorPrint ( ) ;


<s> bool <ISA_LIT>PacketizerList :: CanPromoteToNewValue ( MachineInstr * MI , SUnit * PacketSU , unsigned DepReg , std :: map < MachineInstr * , SUnit * > MIToSUnit , MachineBasicBlock :: iterator & MII ) { const <ISA_LIT>RegisterInfo * QRI = ( const <ISA_LIT>RegisterInfo * ) TM . getRegisterInfo ( ) ; if ( ! QRI -> Subtarget . hasV4TOps ( ) || ! IsNewifyStore ( MI ) ) return false ; MachineInstr * PacketMI = PacketSU -> getInstr ( ) ; if ( CanPromoteToNewValueStore ( MI , PacketMI , DepReg , MIToSUnit ) ) return true ;


<s> } } } } else if ( DefMI -> isCopyLike ( ) ) { Reg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Register :: isVirtualRegister ( Reg ) ) { DefMI = MRI -> getVRegDef ( Reg ) ; continue ; } } else if ( DefMI -> isInsertSubreg ( ) ) { Reg = DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> return m16_check_op ( op , ( - <NUM_LIT> ) << <NUM_LIT> , <NUM_LIT> << <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( ValMapping . NumBreakDowns >= <NUM_LIT> || ValMapping . BreakDown [ <NUM_LIT> ] . Length >= <NUM_LIT> ) return <NUM_LIT> ;

assert ( ValMapping . NumBreakDowns == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . Length == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . StartIdx == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . Length == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . StartIdx == <NUM_LIT> && ValMapping . BreakDown [ <NUM_LIT> ] . RegBank == ValMapping . BreakDown [ <NUM_LIT> ] . RegBank ) ;


<s> case Instruction :: ExtractElement : case Instruction :: InsertElement : { unsigned EltSize = DL . getTypeSizeInBits ( cast < VectorType > ( ValTy ) -> getElementType ( ) ) ;


return ( __m64 ) ( ( __vector long long ) __r ) [ <NUM_LIT> ] ;


<s> ReturnInst :: Create ( F . getContext ( ) , PN , NewRetBlock ) ; } for ( BasicBlock * BB : ReturningBlocks ) { if ( PN ) PN -> addIncoming ( BB -> getTerminator ( ) -> getOperand ( <NUM_LIT> ) , BB ) ; BB -> getInstList ( ) . pop_back ( ) ; BranchInst :: Create ( NewRetBlock , BB ) ; } for ( BasicBlock * BB : ReturningBlocks ) { SimplifyCFG ( BB , TTI , nullptr , { <NUM_LIT> } ) ; } return NewRetBlock ;


<s> TargetLoweringBase :: LegalizeTypeAction getPreferredVectorAction ( EVT VT ) const override {

if ( VT . getScalarSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> ) return TypeWidenVector ;


<s> bool <ISA_LIT>TTIImpl :: isLegalToVectorizeMemChain ( unsigned ChainSizeInBytes , unsigned Alignment , unsigned AddrSpace ) const {

if ( AddrSpace == ST -> get<ISA_LIT>AS ( ) . PRIVATE_ADDRESS ) {


<s> inline bool isLookupC ( const MCInstrDesc & MCInstD ) { if ( ! isLoadInst ( MCInstD ) ) return false ;

unsigned opc = <ISA_LIT>II :: getSlotOpCode ( MCInstD ) ;


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetSymbolFromOperand ( const MachineOperand & MO ) const { const DataLayout * DL = TM . getDataLayout ( ) ; assert ( ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isMBB ( ) ) && <STR_LIT> ) ; SmallString < <NUM_LIT> > Name ; StringRef Suffix ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : Name += <STR_LIT> ; break ; case <STR_LIT> : Suffix = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Suffix = <STR_LIT> ; break ; } if ( ! Suffix . empty ( ) ) Name += DL -> getPrivateGlobalPrefix ( ) ; unsigned PrefixLen = Name . size ( ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; AsmPrinter . getNameWithPrefix ( Name , GV ) ; } else if ( MO . isSymbol ( ) ) { getMang ( ) -> getNameWithPrefix ( Name , MO . getSymbolName ( ) ) ; } else if ( MO . isMBB ( ) ) { Name += MO . getMBB ( ) -> getSymbol ( ) -> getName ( ) ; } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; switch ( MO . getTargetFlags ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } break ; } case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getHiddenGVStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; }


<s> void <ISA_LIT>Z80RegisterInfo :: splitReg ( unsigned Reg , unsigned & LoReg , unsigned & HiReg ) const { assert ( <STR_LIT> . contains ( Reg ) && <STR_LIT> ) ; LoReg = getSubReg ( Reg , <STR_LIT> ) ; HiReg = getSubReg ( Reg , <STR_LIT> ) ;


<s> for ( const MachineInstr & It : * MBB ) NewMBB -> push_back ( Func -> CloneMachineInstr ( & It ) ) ; return NewMBB ;


<s> std :: vector < GlobalAlias * > AliasesToRemove ; SmallPtrSet < Function * , <NUM_LIT> > FuncsToAlwaysInline ; SmallPtrSet < Function * , <NUM_LIT> > FuncsToNoInline ; for ( GlobalAlias & A : M . aliases ( ) ) { if ( Function * F = dyn_cast < Function > ( A . getAliasee ( ) ) ) { A . replaceAllUsesWith ( F ) ; AliasesToRemove . push_back ( & A ) ; } } if ( GlobalOpt ) { for ( GlobalAlias * A : AliasesToRemove ) { A -> eraseFromParent ( ) ; } } for ( GlobalVariable & GV : M . globals ( ) ) { unsigned AS = GV . getAddressSpace ( ) ;

if ( ( AS == <ISA_LIT>AS :: REGION_ADDRESS ) || ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS && ( ! <ISA_LIT>TargetMachine :: EnableLowerModuleLDS || ! GV . hasInitializer ( ) ) ) ) recursivelyVisitUsers ( GV , FuncsToAlwaysInline ) ;


<s> static SDValue prepareTS1AM ( SDValue Op , SelectionDAG & DAG , SDValue & Flag , SDValue & Bits ) { SDLoc DL ( Op ) ; AtomicSDNode * N = cast < AtomicSDNode > ( Op ) ; SDValue Ptr = N -> getOperand ( <NUM_LIT> ) ; SDValue Val = N -> getOperand ( <NUM_LIT> ) ;


<s> } else { BaseAICalls [ Parent ] = ParentInfo ; } } else if ( auto * GI = dyn_cast < GetElementPtrInst > ( Inst ) ) { if ( GI -> hasAllZeroIndices ( ) ) traceGEP ( GI , Parent , ParentInfo ) ; else BaseAICalls [ Parent ] = ParentInfo ; } else { BaseAICalls [ Parent ] = ParentInfo ;


<s> DecodeStatus S = MCDisassembler :: Success ; if ( ! ( imm & <NUM_LIT> ) && cmode == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; return DecodeNEONModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( create<ISA_LIT>CompressJumpTablesPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ;

addPass ( createUnpackMachineBundles ( nullptr ) ) ;


<s> for ( auto SI = MBB -> succ_begin ( ) , SE = MBB -> succ_end ( ) ; SI != SE ; ++ SI ) if ( ( * SI ) -> isLiveIn ( <STR_LIT> ) ) return false ; } return true ;


<s> int neon_vector_mem_operand ( rtx op , int type , bool strict ) { rtx ind ; if ( ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return ! strict ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , <NUM_LIT> ) ; if ( reload_completed && ( GET_CODE ( ind ) == LABEL_REF || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , <NUM_LIT> ) ; if ( ( type != <NUM_LIT> && GET_CODE ( ind ) == POST_INC ) || ( type == <NUM_LIT> && GET_CODE ( ind ) == PRE_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ; if ( type == <NUM_LIT> && GET_CODE ( ind ) == POST_MODIFY && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) ) return true ; if ( type == <NUM_LIT> && GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , <NUM_LIT> ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , <NUM_LIT> ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , <NUM_LIT> ) ) && INTVAL ( XEXP ( ind , <NUM_LIT> ) ) > - <NUM_LIT> && ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) < ( VALID_NEON_QREG_MODE ( GET_MODE ( op ) ) ? <NUM_LIT> : <NUM_LIT> ) ) && ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return TRUE ;


<s> if ( ( index = get_content_index ( to ) ) == NOT_KNOWN ) return ; gcc_assert ( saved_update_index == NOT_KNOWN ) ; saved_update_index = index ; saved_update_value = get_content_index ( value ) ; saved_update_mode = GET_MODE ( to ) ;


return isImm ( - <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( output_memory_autoinc_first ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( addr , <NUM_LIT> ) ) ] ) ; else fprintf ( file , <STR_LIT> , GET_CODE ( addr ) == POST_DEC ? - offset : offset ) ; } else if ( GET_CODE ( addr ) == POST_MODIFY ) { gcc_assert ( output_memory_reference_mode != VOIDmode ) ; gcc_assert ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == PLUS ) ; if ( output_memory_autoinc_first ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( addr , <NUM_LIT> ) ) ] ) ; else fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ) ;


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= <NUM_LIT> && Constraint [ <NUM_LIT> ] == '{' && * ( Constraint . end ( ) - <NUM_LIT> ) == '}' ) { StringRef name ( Constraint . data ( ) + <NUM_LIT> , Constraint . size ( ) - <NUM_LIT> ) ; uint64_t intVal = <NUM_LIT> ; if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal <= <NUM_LIT> ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / <NUM_LIT> ] ;

char regIdx = '0' + ( intVal % <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isFMAFasterThanFMulAndFAdd ( EVT VT ) const { return isOperationLegalOrCustom ( <STR_LIT> , VT ) ;


<s> return ( ( ( TARGET_ALTIVEC ) ? RS6000_BTM_ALTIVEC : <NUM_LIT> ) | ( ( TARGET_CMPB ) ? RS6000_BTM_CMPB : <NUM_LIT> ) | ( ( TARGET_VSX ) ? RS6000_BTM_VSX : <NUM_LIT> ) | ( ( TARGET_FRE ) ? RS6000_BTM_FRE : <NUM_LIT> ) | ( ( TARGET_FRES ) ? RS6000_BTM_FRES : <NUM_LIT> ) | ( ( TARGET_FRSQRTE ) ? RS6000_BTM_FRSQRTE : <NUM_LIT> ) | ( ( TARGET_FRSQRTES ) ? RS6000_BTM_FRSQRTES : <NUM_LIT> ) | ( ( TARGET_POPCNTD ) ? RS6000_BTM_POPCNTD : <NUM_LIT> ) | ( ( rs6000_cpu == PROCESSOR_CELL ) ? RS6000_BTM_CELL : <NUM_LIT> ) | ( ( TARGET_P8_VECTOR ) ? RS6000_BTM_P8_VECTOR : <NUM_LIT> ) | ( ( TARGET_P9_VECTOR ) ? RS6000_BTM_P9_VECTOR : <NUM_LIT> ) | ( ( TARGET_P9_MISC ) ? RS6000_BTM_P9_MISC : <NUM_LIT> ) | ( ( TARGET_MODULO ) ? RS6000_BTM_MODULO : <NUM_LIT> ) | ( ( TARGET_64BIT ) ? RS6000_BTM_64BIT : <NUM_LIT> ) | ( ( TARGET_POWERPC64 ) ? RS6000_BTM_POWERPC64 : <NUM_LIT> ) | ( ( TARGET_CRYPTO ) ? RS6000_BTM_CRYPTO : <NUM_LIT> ) | ( ( TARGET_HTM ) ? RS6000_BTM_HTM : <NUM_LIT> ) | ( ( TARGET_DFP ) ? RS6000_BTM_DFP : <NUM_LIT> ) | ( ( TARGET_HARD_FLOAT ) ? RS6000_BTM_HARD_FLOAT : <NUM_LIT> ) | ( ( TARGET_LONG_DOUBLE_128 && TARGET_HARD_FLOAT && ! TARGET_IEEEQUAD ) ? RS6000_BTM_LDBL128 : <NUM_LIT> ) | ( ( TARGET_FLOAT128_TYPE ) ? RS6000_BTM_FLOAT128 : <NUM_LIT> ) | ( ( TARGET_FLOAT128_HW ) ? RS6000_BTM_FLOAT128_HW : <NUM_LIT> ) | ( ( TARGET_MMA ) ? RS6000_BTM_MMA : <NUM_LIT> ) | ( ( TARGET_POWER10 ) ? RS6000_BTM_P10 : <NUM_LIT> ) ) ;


<s> LLT ValTy = MRI . getType ( Dst ) ; uint64_t ValSize = ValTy . getSizeInBits ( ) / <NUM_LIT> ; MIRBuilder . buildLoad ( Dst , DstPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , ValTy , std :: max ( Alignment , PtrAlign ) ) ) ; auto Size = MIRBuilder . buildConstant ( IntPtrTy , alignTo ( ValSize , PtrAlign ) ) ; auto NewList = MIRBuilder . buildPtrAdd ( PtrTy , DstPtr , Size . getReg ( <NUM_LIT> ) ) ; MIRBuilder . buildStore ( NewList , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , PtrTy , PtrAlign ) ) ;


<s> static bool classof ( const MCExpr * E ) {

return E -> getKind ( ) == MCExpr :: Target ;


<s> O << getRegisterName ( MO . getReg ( ) ) << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT> ) ;


<s> SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , FudgePtr , MachinePointerInfo :: getConstantPool ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Fild , Fudge ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , Add , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ;


<s> disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ;


<s> explicit Tile64AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) {


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ; auto & PR = * PassRegistry :: getPassRegistry ( ) ;

initialize<ISA_LIT>ExpandPseudoPass ( PR ) ;


<s> case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return Operand == <NUM_LIT> ; case Instruction :: Call : if ( auto * II = dyn_cast < IntrinsicInst > ( I ) ) { switch ( II -> getIntrinsicID ( ) ) { case <STR_LIT> : return Operand == <NUM_LIT> || Operand == <NUM_LIT> ; default : return false ; } } return false ; default : return false ; } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ;

if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ;


<s> return get_attr_type ( rinsn ) == TYPE_VIMOVXV || get_attr_type ( rinsn ) == TYPE_VFMOVFV ;