<s> SDLoc DL ( N ) ; if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) ) if ( auto * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) if ( C -> getAPIntValue ( ) . isOne ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src . getOperand ( <NUM_LIT> ) ) ;

if ( VT == <STR_LIT> && Src . getOpcode ( ) == <STR_LIT> && Src . hasOneUse ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) . isVector ( ) && Src . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) if ( auto * C = dyn_cast < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) if ( C -> isZero ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Src . getOperand ( <NUM_LIT> ) , Src . getOperand ( <NUM_LIT> ) ) ;


<s> return ( __m512i ) __builtin_ia32_pbroadcastb512_mask ( ( __v16qi ) __A , ( __v64qi ) _mm512_undefined_epi32 ( ) , ( __mmask64 ) - <NUM_LIT> ) ;


if ( getEffectiveCallingConv ( CallConv , isVarArg ) != CallingConv :: <ISA_LIT>_AAPCS_VFP ) return false ;


<s> uint64_t Size = DL . getTypeAllocSize ( CV -> getType ( ) ) ; if ( isa < ConstantAggregateZero > ( CV ) || isa < UndefValue > ( CV ) ) return true ; if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( CV ) ) { uint64_t val = CI -> getZExtValue ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Offset << <STR_LIT> << val << '\n' ) ; if ( Size > <NUM_LIT> || ( Size & ( Size - <NUM_LIT> ) ) ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Size ; ++ i ) { Vals [ Offset + i ] = DL . isLittleEndian ( ) ? ( ( val >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) : ( ( val >> ( ( Size - i - <NUM_LIT> ) * <NUM_LIT> ) ) & <NUM_LIT> ) ; } return true ; }

if ( const ConstantDataArray * CDA = dyn_cast < ConstantDataArray > ( CV ) ) return fillConstantDataArray ( DL , CDA , Vals , Offset ) ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override {


<s> if ( ST . hasSGPRInitBug ( ) ) return ScratchWaveOffsetReg ; unsigned NumPreloaded = MFI -> getNumPreloadedSGPRs ( ) ; ArrayRef < MCPhysReg > AllSGPRs = getAllSGPRs ( ST , MF ) ; if ( NumPreloaded > AllSGPRs . size ( ) ) return ScratchWaveOffsetReg ; AllSGPRs = AllSGPRs . slice ( NumPreloaded ) ; unsigned ReservedRegCount = <NUM_LIT> ; if ( AllSGPRs . size ( ) < ReservedRegCount ) return ScratchWaveOffsetReg ; bool HandledScratchWaveOffsetReg = ScratchWaveOffsetReg != TRI -> reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; for ( MCPhysReg Reg : AllSGPRs . drop_back ( ReservedRegCount ) ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) ) { if ( ! HandledScratchWaveOffsetReg ) { HandledScratchWaveOffsetReg = true ; MRI . replaceRegWith ( ScratchWaveOffsetReg , Reg ) ; if ( MFI -> getScratchWaveOffsetReg ( ) == MFI -> getStackPtrOffsetReg ( ) ) { assert ( ! hasFP ( MF ) ) ; MFI -> setStackPtrOffsetReg ( Reg ) ; } MFI -> setScratchWaveOffsetReg ( Reg ) ; MFI -> setFrameOffsetReg ( Reg ) ; ScratchWaveOffsetReg = Reg ; break ; }


<s> N = glueCopyToM0 ( N , Ptr ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( ) , <STR_LIT> ) ; } SDValue Ops [ ] = { Offset , CurDAG -> getTargetConstant ( IsGDS , SDLoc ( ) , <STR_LIT> ) , Chain , N -> getOperand ( N -> getNumOperands ( ) - <NUM_LIT> ) } ; SDNode * Selected = CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , Ops ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Selected ) , { MMO } ) ;


<s> for ( const BasicBlock * BB : L -> getBlocks ( ) ) { for ( const Instruction & I : * BB ) { const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( & I ) ; if ( ! GEP || GEP -> getAddressSpace ( ) != <STR_LIT> ) continue ; const Value * Ptr = GEP -> getPointerOperand ( ) ;

const AllocaInst * Alloca = dyn_cast < AllocaInst > ( GetUnderlyingObject ( Ptr ) ) ;


<s> static bool allocateFloat ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { switch ( LocVT . SimpleTy ) { case <STR_LIT> : { State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ;

unsigned Offset = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ;


<s> SmallVector < Constant * , <NUM_LIT> > CV1 ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; CV1 . push_back ( ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ) ) ; Constant * C1 = ConstantVector :: get ( CV1 ) ; SDValue CPIdx1 = DAG . getConstantPool ( C1 , PtrVT , <NUM_LIT> ) ; SDValue XR1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ;

SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ;


<s> { aarch64_simd_switcher simd ; aarch64_init_simd_builtins ( ) ; } aarch64_init_crc32_builtins ( ) ; aarch64_init_builtin_rsqrt ( ) ; aarch64_init_rng_builtins ( ) ; aarch64_init_data_intrinsics ( ) ; tree ftype_jcvt = build_function_type_list ( intSI_type_node , double_type_node , NULL ) ;


<s> return lookup_attribute ( func_attr , DECL_ATTRIBUTES ( decl ) ) != NULL_TREE ;


<s> MCPhysReg FreeReg = * CallerSavedRegs ; if ( MRI . isPhysRegUsed ( FreeReg ) ) continue ; bool IsCurrentRegUsed = false ; for ( MCRegAliasIterator AI ( FreeReg , & HRI , false ) ; AI . isValid ( ) ; ++ AI ) if ( MRI . isPhysRegUsed ( * AI ) ) { IsCurrentRegUsed = true ; break ; } if ( IsCurrentRegUsed ) continue ; return false ; }


<s> Op -> VectorIndex . Val = Idx ; Op -> StartLoc = S ;


<s> return ( __m256i ) __builtin_ia32_extracti32x8_mask ( ( __v16si ) __A , __imm , ( __v8si ) _mm256_setzero_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> void <ISA_LIT>TargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const { SDValue Res ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> :


<s> assert ( ( IsT1PushPop || ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( NumBytes % ( IsVFPPushPop ? <NUM_LIT> : <NUM_LIT> ) != <NUM_LIT> ) return false ; int RegListIdx = IsT1PushPop ? <NUM_LIT> : <NUM_LIT> ; unsigned RegsNeeded ; const TargetRegisterClass * RegClass ; if ( IsVFPPushPop ) { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } else { RegsNeeded = NumBytes / <NUM_LIT> ; RegClass = & <STR_LIT> ; } SmallVector < MachineOperand , <NUM_LIT> > RegList ; unsigned FirstRegEnc = - <NUM_LIT> ; const TargetRegisterInfo * TRI = MF . getRegInfo ( ) . getTargetRegisterInfo ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= RegListIdx ; -- i ) { MachineOperand & MO = MI -> getOperand ( i ) ; RegList . push_back ( MO ) ; if ( MO . isReg ( ) && ! MO . isImplicit ( ) && TRI -> getEncodingValue ( MO . getReg ( ) ) < FirstRegEnc ) FirstRegEnc = TRI -> getEncodingValue ( MO . getReg ( ) ) ;


<s> if ( isMemNoOffset ( false , <NUM_LIT> ) ) return true ;

return isMemNoOffset ( false , <NUM_LIT> ) ;


<s> Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>CodeEmitter :: getSimm18Lsl3Encoding ( const MachineInstr & MI , unsigned OpNo ) const {


<s> if ( TARGET_NOP_FUN_DLLIMPORT && TREE_CODE ( decl ) == FUNCTION_DECL ) return false ; return true ;


<s> bool <ISA_LIT>PassConfig :: addPreISel ( ) { return false ;


<s> SDLoc DL ( Op ) ; SDValue FpToUInt32 = DAG . getNode ( Op . getOpcode ( ) , DL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FpToUInt32 ) ; }

if ( Op . getValueType ( ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> ) return LowerFP64_TO_INT ( Op , DAG , false ) ;


<s> Tile64PassConfig ( Tile64TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> static SDValue joinDwords ( SelectionDAG & DAG , SDLoc DL , SDValue Op0 , SDValue Op1 ) { if ( Op0 . isUndef ( ) && Op1 . isUndef ( ) ) return DAG . getUNDEF ( <STR_LIT> ) ; if ( Op0 . isUndef ( ) ) Op0 = Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op1 ) ; else if ( Op1 . isUndef ( ) ) Op0 = Op1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; else { Op0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ;


<s> switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ExtraOp = true ; break ; } if ( ! ExtraOp ) return DAG . getNode ( Opc , Op -> getDebugLoc ( ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( Opc , Op -> getDebugLoc ( ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> regno = reg_renumber [ regno ] ; } if ( regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM ) return true ;

if ( TARGET_MIPS16 && regno == STACK_POINTER_REGNUM ) return GET_MODE_SIZE ( mode ) == <NUM_LIT> || GET_MODE_SIZE ( mode ) == <NUM_LIT> ;


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy , CostKind ) ; if ( ! ValTy -> isVectorTy ( ) ) { switch ( Opcode ) { case Instruction :: ICmp : { unsigned ScalarBits = ValTy -> getScalarSizeInBits ( ) ; if ( I != nullptr && ScalarBits >= <NUM_LIT> ) if ( LoadInst * Ld = dyn_cast < LoadInst > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( const ConstantInt * C = dyn_cast < ConstantInt > ( I -> getOperand ( <NUM_LIT> ) ) ) if ( ! Ld -> hasOneUse ( ) && Ld -> getParent ( ) == I -> getParent ( ) && C -> getZExtValue ( ) == <NUM_LIT> ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; if ( ValTy -> isIntegerTy ( ) && ValTy -> getScalarSizeInBits ( ) <= <NUM_LIT> ) Cost += ( I != nullptr ? getOperandsExtensionCost ( I ) : <NUM_LIT> ) ; return Cost ; } case Instruction :: Select : if ( ValTy -> isFloatingPointTy ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } } else if ( ST -> hasVector ( ) ) { unsigned VF = cast < FixedVectorType > ( ValTy ) -> getNumElements ( ) ; if ( Opcode == Instruction :: ICmp || Opcode == Instruction :: FCmp ) { unsigned PredicateExtraCost = <NUM_LIT> ; if ( I != nullptr ) { switch ( cast < CmpInst > ( I ) -> getPredicate ( ) ) { case CmpInst :: Predicate :: ICMP_NE : case CmpInst :: Predicate :: ICMP_UGE : case CmpInst :: Predicate :: ICMP_ULE : case CmpInst :: Predicate :: ICMP_SGE : case CmpInst :: Predicate :: ICMP_SLE : PredicateExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: FCMP_ONE :


<s> if ( TARGET_ELF || TARGET_MACHO ) { bool large_toc_ok ; if ( DEFAULT_ABI == ABI_V4 && flag_pic ) return false ; large_toc_ok = ( lra_in_progress && TARGET_CMODEL != CMODEL_SMALL && small_toc_ref ( x , VOIDmode ) ) ; if ( TARGET_TOC && ! large_toc_ok ) return false ; if ( GET_MODE_NUNITS ( mode ) != <NUM_LIT> ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) return false ; return CONSTANT_P ( x ) || large_toc_ok ;


<s> rtx patt = PATTERN ( last ) ; if ( GET_CODE ( patt ) == SET ) {


<s> void <ISA_LIT>MCAsmStreamer :: EmitValueWithAlignment ( const MCExpr * Value , unsigned Size , SMLoc Loc ) { const char * Directive = nullptr ; switch ( Size ) { default : break ; case <NUM_LIT> : Directive = MAI -> getData8bitsDirective ( ) ; break ;

case <NUM_LIT> : Directive = MAI -> getData16bitsDirective ( ) ; break ;


<s> explicit MDIndex ( unsigned F ) : F ( F ) {


<s> if ( MIInSlot . isInlineAsm ( ) ) return false ; return ! llvm :: any_of ( LoadMI . defs ( ) , [ & ] ( const MachineOperand & Op ) { return Op . isReg ( ) && MIInSlot . readsRegister ( Op . getReg ( ) ) ; } ) ;


<s> unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) ) { assert ( I . isCopy ( ) && <STR_LIT> ) ; return true ; } const RegisterBank & RegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const unsigned DstSize = MRI . getType ( DstReg ) . getSizeInBits ( ) ; unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ; assert ( ( ! TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) || I . isCopy ( ) ) && <STR_LIT> ) ;

assert ( ( DstSize == SrcSize || ( TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) && DstSize <= RBI . getSizeInBits ( SrcReg , MRI , TRI ) ) ) && <STR_LIT> ) ;


<s> static bool isValidCopy ( const MachineInstr & I , const RegisterBank & DstBank , const MachineRegisterInfo & MRI , const TargetRegisterInfo & TRI , const RegisterBankInfo & RBI ) { const unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned DstSize = RBI . getSizeInBits ( DstReg , MRI , TRI ) ;

const unsigned SrcSize = RBI . getSizeInBits ( SrcReg , MRI , TRI ) ;


<s> Signatures . push_back ( std :: move ( Sig ) ) ;


<s> int64_t Imm = Src . second ; std :: vector < MachineOperand * > :: iterator It = std :: find_if ( Lits . begin ( ) , Lits . end ( ) , [ & ] ( MachineOperand * val ) { return val -> isImm ( ) && ( val -> getImm ( ) == Imm ) ; } ) ;

MachineOperand & Operand = MI . getOperand ( TII -> getOperandIdx ( MI . getOpcode ( ) , <STR_LIT> :: literal ) ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: AnalyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) return false ; MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ;

if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) {


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; default :


<s> void <ISA_LIT>InstPrinter :: printCRxOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & CRx = MI -> getOperand ( OpNum ) ; O << 'c' << CRx . getImm ( ) ;


<s> switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> MachineInstr * Inst = MRI -> getVRegDef ( SrcReg ) ; if ( BB1 && Inst -> getOpcode ( ) == <STR_LIT> && Inst -> getParent ( ) == BB2 ) { NextReg = getIncomingRegForBlock ( Inst , BB1 ) ;


<s> IsZvlsseg = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( IsScalableVector ) { MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MemoryLocation :: UnknownSize , MFI . getObjectAlign ( FI ) ) ; MFI . setStackID ( FI , TargetStackID :: ScalableVector ) ; auto MIB = BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addMemOperand ( MMO ) ; if ( IsZvlsseg ) { MIB . addReg ( <STR_LIT> ) ; } } else { MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; BuildMI ( MBB , I , DL , get ( Opcode ) , DstReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; }


<s> } else { MI = BuildMI ( MBB , Before , DebugLoc ( ) , TII -> get ( ST -> isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) , Exec ) . addReg ( Exec ) ; }

LIS -> InsertMachineInstrInMaps ( * MI ) ;


<s> return MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> if ( usesHardware ( <STR_LIT> ) ) { return MAX_LDS_<ISA_LIT>ZE_800 ; } else {


<s> int m32c_eh_return_data_regno ( int n ) { switch ( n ) { case <NUM_LIT> : return A0_REGNO ; case <NUM_LIT> : return A1_REGNO ;


<s> void initializeTargetID ( const MCSubtargetInfo & STI , StringRef FeatureString ) {


<s> SectionKind Kind = CPE . getSectionKind ( TM . getSubtargetImpl ( ) -> getDataLayout ( ) ) ; const Constant * C = CPE . Val . ConstVal ; if ( const MCSectionCOFF * S = dyn_cast < MCSectionCOFF > ( getObjFileLowering ( ) . getSectionForConstant ( Kind , C ) ) ) { if ( MCSymbol * Sym = S -> getCOMDATSymbol ( ) ) { if ( Sym -> isUndefined ( ) ) OutStreamer . EmitSymbolAttribute ( Sym , MCSA_Global ) ; return Sym ; } } }


<s> bool aarch64_mov128_immediate ( rtx imm ) { if ( GET_CODE ( imm ) == CONST_INT ) return true ; gcc_assert ( CONST_WIDE_INT_NUNITS ( imm ) == <NUM_LIT> ) ;

rtx lo = GEN_INT ( CONST_WIDE_INT_ELT ( imm , <NUM_LIT> ) ) ;


<s> for ( auto & Op : I . operands ( ) ) Args . push_back ( Op ) ; Args . push_back ( IRB -> getInt32 ( I . getSyncScopeID ( ) ) ) ; Args . push_back ( IRB -> getInt32 ( getMemSemantics ( I . getSuccessOrdering ( ) ) ) ) ;

Args . push_back ( IRB -> getInt32 ( getMemSemantics ( I . getFailureOrdering ( ) ) ) ) ;


<s> if ( ! after_np_branch ) np_reg = - <NUM_LIT> ; return ( ( np_reg == - <NUM_LIT> || ! harmless_null_pointer_p ( mem , np_reg ) ) && may_trap_p ( mem ) ) ;


<s> static bool expandNOVLXStore ( MachineInstrBuilder & MIB , const TargetRegisterInfo * TRI , const MCInstrDesc & StoreDesc , const MCInstrDesc & ExtractDesc , unsigned SubIdx ) { Register SrcReg = MIB -> getOperand ( <STR_LIT> ) . getReg ( ) ; if ( TRI -> getEncodingValue ( SrcReg ) < <NUM_LIT> ) { MIB -> setDesc ( StoreDesc ) ; } else { MIB -> setDesc ( ExtractDesc ) ; SrcReg = TRI -> getMatchingSuperReg ( SrcReg , SubIdx , & <STR_LIT> ) ; MIB -> getOperand ( <STR_LIT> ) . setReg ( SrcReg ) ;


<s> if ( lFromVEX2of2 ( insn -> vexPrefix [ <NUM_LIT> ] ) ) attrMask |= ATTR_VEXL ; } else { return - <NUM_LIT> ; } } else { if ( insn -> rexPrefix & <NUM_LIT> ) attrMask |= ATTR_REXW ; if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_OPSIZE ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XS ; else if ( isPrefixAtLocation ( insn , <NUM_LIT> , insn -> necessaryPrefixLocation ) ) attrMask |= ATTR_XD ; } if ( getIDWithAttrMask ( & instructionID , insn , attrMask ) ) return - <NUM_LIT> ; if ( ( attrMask & ATTR_XD ) && ( attrMask & ATTR_REXW ) ) { const struct InstructionSpecifier * spec ; uint16_t instructionIDWithREXw ; const struct InstructionSpecifier * specWithREXw ; spec = specifierForUID ( instructionID ) ; if ( getIDWithAttrMask ( & instructionIDWithREXw , insn , attrMask & ( ~ ATTR_XD ) ) ) { insn -> instructionID = instructionID ; insn -> spec = spec ; return <NUM_LIT> ; } specWithREXw = specifierForUID ( instructionIDWithREXw ) ; if ( is64BitEquivalent ( spec -> name , specWithREXw -> name ) ) { insn -> instructionID = instructionIDWithREXw ; insn -> spec = specWithREXw ; } else { insn -> instructionID = instructionID ; insn -> spec = spec ; } return <NUM_LIT> ; } if ( insn -> prefixPresent [ <NUM_LIT> ] && ! ( attrMask & ATTR_OPSIZE ) ) { const struct InstructionSpecifier * spec ; uint16_t instructionIDWithOpsize ; const struct InstructionSpecifier * specWithOpsize ; spec = specifierForUID ( instructionID ) ; if ( getIDWithAttrMask ( & instructionIDWithOpsize , insn , attrMask | ATTR_OPSIZE ) ) { insn -> instructionID = instructionID ;


<s> for ( size_t i = <NUM_LIT> ; i < Contents . size ( ) ; ++ i ) if ( Contents [ i ] . Tag == Attribute ) return & Contents [ i ] ; return nullptr ;


<s> for ( i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { is_kill = true ; reg = CSI [ i ] . getReg ( ) ; MachineRegisterInfo :: livein_iterator li = MRI . livein_begin ( ) ; for ( ; li != MRI . livein_end ( ) ; li ++ ) {


<s> const MachineFrameInfo * FFI = MF . getFrameInfo ( ) ; unsigned CFSize = FFI -> getMaxCallFrameSize ( ) ; if ( CFSize >= ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> / <NUM_LIT> ) return false ;

return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> O << <STR_LIT> ( Mode , isFLDM ) ; } else O << <STR_LIT> ( Mode ) ; return ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { O << TM . getRegisterInfo ( ) -> get ( MO1 . getReg ( ) ) . AsmName ; if ( <STR_LIT> ( MO2 . getImm ( ) ) ) O << <STR_LIT> ; return ; } O << <STR_LIT> << TM . getRegisterInfo ( ) -> get ( MO1 . getReg ( ) ) . AsmName ; if ( unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ) { O << <STR_LIT> << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << ImmOffs * <NUM_LIT> ; } O << <STR_LIT> ;


<s> rtx labelno = GEN_INT ( pic_labelno ++ ) ; rtx label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; rtx sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_DESCSEQ ) , gen_rtx_CONST ( VOIDmode , label ) , GEN_INT ( ! TARGET_ARM ) ) , UNSPEC_TLS ) ; rtx reg0 = load_tls_operand ( sum , gen_rtx_REG ( SImode , R0_REGNUM ) ) ; emit_insn ( gen_tlscall ( x , labelno ) ) ; if ( ! reg ) reg = gen_reg_rtx ( SImode ) ; else gcc_assert ( REGNO ( reg ) != R0_REGNUM ) ;


<s> } if ( Imm1 & ~ <NUM_LIT> ) { Error ( Sx1 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc Sx2 , Ex2 ; Sx2 = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . is ( AsmToken :: Hash ) || Parser . getTok ( ) . is ( AsmToken :: Dollar ) ) Parser . Lex ( ) ; const MCExpr * Imm2Exp ; if ( getParser ( ) . parseExpression ( Imm2Exp , Ex2 ) ) { Error ( Sx2 , <STR_LIT> ) ; return MatchOperand_ParseFail ; } CE = dyn_cast < MCConstantExpr > ( Imm2Exp ) ; if ( CE ) { Imm2 = CE -> getValue ( ) ; if ( ! ( Imm2 & ~ <NUM_LIT> ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateModImm ( Imm1 , Imm2 , S , Ex2 ) ) ; return MatchOperand_Success ; } Error ( Sx2 , <STR_LIT> ) ;


<s> CONSTEXPR fixed_insn_function ( insn_code code ) : m_code ( code ) {


<s> } case Instruction :: PtrToInt : { if ( TLI . getValueType ( U -> getType ( ) ) == TLI . getPointerTy ( ) ) return <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ; break ; } case Instruction :: GetElementPtr : { Address SavedAddr = Addr ; int TmpOffset = Addr . Offset ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = TD . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = TD . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( isa < AddOperator > ( Op ) && ( ! isa < Instruction > ( Op ) || FuncInfo . MBBMap [ cast < Instruction > ( Op ) -> getParent ( ) ] == FuncInfo . MBB ) && isa < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . Offset = TmpOffset ; if ( <ISA_LIT>ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : {

const AllocaInst * AI = cast < AllocaInst > ( Obj ) ;


for ( MachineBasicBlock :: instr_iterator i ( MBB -> instr_begin ( ) ) , ie ( MBB -> instr_end ( ) ) ; i != ie ; i ++ ) {


<s> if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ;


<s> const InstrItineraryData * II = & static_cast < const <ISA_LIT>Subtarget * > ( STI ) -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG , <STR_LIT> ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( STI , DAG ) ;


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { Expr -> print ( OS , MAI ) ;


<s> } bool emitFrameMoves = needsFrameMoves ( MF ) ; if ( FrameSize ) { bool saveLR = XFI -> getUsesLR ( ) ; bool LRSavedOnEntry = false ; int Opcode ; if ( saveLR && ( MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) == <NUM_LIT> ) ) { Opcode = ( isU6 ) ? <STR_LIT> : <STR_LIT> ; MBB . addLiveIn ( <STR_LIT> ) ; saveLR = false ; LRSavedOnEntry = true ; } else { Opcode = ( isU6 ) ? <STR_LIT> : <STR_LIT> ; } BuildMI ( MBB , MBBI , dl , TII . get ( Opcode ) ) . addImm ( FrameSize ) ; if ( emitFrameMoves ) { std :: vector < MachineMove > & Moves = MMI -> getFrameMoves ( ) ; MCSymbol * FrameLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( FrameLabel ) ; MachineLocation SPDst ( MachineLocation :: VirtualFP ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP , - FrameSize * <NUM_LIT> ) ; Moves . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ; if ( LRSavedOnEntry ) { MachineLocation CSDst ( MachineLocation :: VirtualFP , <NUM_LIT> ) ; MachineLocation CSSrc ( <STR_LIT> ) ; Moves . push_back ( MachineMove ( FrameLabel , CSDst , CSSrc ) ) ; } } if ( saveLR ) { int LRSpillOffset = MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) ; storeToStack ( MBB , MBBI , <STR_LIT> , LRSpillOffset + FrameSize * <NUM_LIT> , dl ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * SaveLRLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( SaveLRLabel ) ; MachineLocation CSDst ( MachineLocation :: VirtualFP , LRSpillOffset ) ; MachineLocation CSSrc ( <STR_LIT> ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( SaveLRLabel , CSDst , CSSrc ) ) ; } } } if ( FP ) { int FPSpillOffset = MFI -> getObjectOffset ( XFI -> getFPSpillSlot ( ) ) ; storeToStack ( MBB , MBBI , <STR_LIT> , FPSpillOffset + FrameSize * <NUM_LIT> , dl ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * SaveR10Label = MMI -> getContext ( ) . CreateTempSymbol ( ) ;

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( SaveR10Label ) ;


<s> if ( cast < VectorType > ( Src ) -> getElementCount ( ) == ElementCount :: getScalable ( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ; return LT . first * <NUM_LIT> ;


<s> require_stack_frame = true ; if ( check_stack_slot ) { subrtx_iterator :: array_type array ; FOR_EACH_SUBRTX ( iter , array , PATTERN ( insn ) , ALL ) if ( MEM_P ( * iter ) && ( reg_mentioned_p ( stack_pointer_rtx , * iter ) || reg_mentioned_p ( frame_pointer_rtx , * iter ) ) ) { unsigned int alignment = MEM_ALIGN ( * iter ) ; if ( alignment > stack_alignment ) stack_alignment = alignment ; } } }


<s> case UNSPEC_TPOFF : x = XVECEXP ( inner , <NUM_LIT> , <NUM_LIT> ) ; return ( GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) == TLS_MODEL_LOCAL_EXEC ) ; case UNSPEC_MACHOPIC_OFFSET : return legitimate_pic_address_disp_p ( x ) ; default : return false ; }


<s> ReplaceNode ( Node , New . getNode ( ) ) ; return ; } } if ( Opcode == <STR_LIT> ) { SDLoc DL ( Node ) ; SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; }


<s> if ( ! CI -> isTailCall ( ) ) return false ;


<s> ZeroDirective = AsciiDirective = AscizDirective = nullptr ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data24bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = nullptr ; AssignmentDirective = <STR_LIT> ; GlobalDirective = <STR_LIT> ; HasFunctionAlignment = false ; HasDotTypeDotSizeDirective = false ; WeakDirective = nullptr ; UseIntegratedAssembler = false ; WeakDirective = nullptr ; UseLogicalShr = false ;


<s> return false ; } AM . BaseType = <ISA_LIT>ISelAddressMode :: Base :: RegBase ; AM . BaseReg = N ; return true ;


<s> int32_t I ; float F ; } Imm ; if ( const ConstantSDNode * Node = dyn_cast < ConstantSDNode > ( N ) ) { if ( Node -> getZExtValue ( ) >> <NUM_LIT> ) { return - <NUM_LIT> ; } Imm . I = Node -> getSExtValue ( ) ; } else if ( const ConstantFPSDNode * Node = dyn_cast < ConstantFPSDNode > ( N ) ) { if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return - <NUM_LIT> ; Imm . F = Node -> getValueAPF ( ) . convertToFloat ( ) ; } else return - <NUM_LIT> ; if ( ( Imm . I >= - <NUM_LIT> && Imm . I <= <NUM_LIT> ) || Imm . F == <NUM_LIT> || Imm . F == - <NUM_LIT> || Imm . F == <NUM_LIT> || Imm . F == - <NUM_LIT> || Imm . F == <NUM_LIT> || Imm . F == - <NUM_LIT> || Imm . F == <NUM_LIT> || Imm . F == - <NUM_LIT> ) return <NUM_LIT> ; return Imm . I ;


<s> if ( ! nds32_check_constant_argument ( icode , op1_num , op1 , name ) ) return NULL_RTX ; op0 = nds32_legitimize_argument ( icode , op0_num , op0 ) ; op1 = nds32_legitimize_argument ( icode , op1_num , op1 ) ; if ( return_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 ) ; else pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; return target ;


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : <ISA_LIT>TargetStreamer ( S ) {


<s> const_rtx operand2 = XEXP ( expr , <NUM_LIT> ) ; return ( REG_P ( operand1 ) && REG_P ( operand2 ) ) ; }


<s> bool Changed = false ; for ( MachineFunction :: iterator I = MF -> begin ( ) ; I != MF -> end ( ) ; ++ I ) { MachineBasicBlock & MBB = * I ; MachineBasicBlock :: iterator J = MBB . getFirstTerminator ( ) ; if ( J == MBB . end ( ) ) continue ; MachineInstr & MI = * J ; if ( MI . isConditionalBranch ( ) && ! isBlockInRange ( MI , * getDestBlock ( MI ) ) ) { fixupConditionalBranch ( MI ) ; ++ NumRelaxed ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;


<s> MachineOperand & MO = MI . getOperand ( i + <NUM_LIT> ) ; MIB . add ( MO ) ; } for ( unsigned i = NumOps + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; MIB . add ( MO ) ; }

updateOperandRegConstraints ( MF , * NewMI , TII ) ;


<s> int sparc_split_regreg_legitimate ( rtx reg1 , rtx reg2 ) { int regno1 , regno2 ; if ( GET_CODE ( reg1 ) == SUBREG ) reg1 = SUBREG_REG ( reg1 ) ; if ( GET_CODE ( reg1 ) != REG ) return <NUM_LIT> ; regno1 = REGNO ( reg1 ) ; if ( GET_CODE ( reg2 ) == SUBREG ) reg2 = SUBREG_REG ( reg2 ) ; if ( GET_CODE ( reg2 ) != REG ) return <NUM_LIT> ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitDirectiveSetFp ( <STR_LIT> Value ) { StringRef ModuleValue ;


<s> SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getNOT ( SDLoc ( Op1 ) , Op1 . getOperand ( <NUM_LIT> ) , VT ) ) ; SDValue NewAdd = DAG . getNode ( <STR_LIT> , DL , VT , Op0 , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NewXor , NewAdd ) ;


<s> bool isMEMrri ( ) const { return Kind == k_MemoryRegRegImm ;


<s> emit_move_insn ( mem , gen_const_mem ( HImode , fnaddr ) ) ; mem = adjust_address ( m_tramp , SImode , <NUM_LIT> ) ; emit_move_insn ( mem , cxt ) ;


<s> RegNo = <STR_LIT> + intVal ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ <NUM_LIT> + intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ <NUM_LIT> + intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ <NUM_LIT> + intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> , <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = FloatRegs [ intVal ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> , <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal >= <NUM_LIT> && intVal <= <NUM_LIT> && ( intVal % <NUM_LIT> == <NUM_LIT> ) ) { RegNo = DoubleRegs [ intVal / <NUM_LIT> ] ; RegKind = <STR_LIT> ; return true ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals_lower ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> , <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal < <NUM_LIT> ) { RegNo = IntRegs [ intVal ] ; RegKind = <STR_LIT> ; return true ; } }


<s> static bool isMOVHLPS_v_undef_Mask ( ArrayRef < int > Mask , EVT VT ) { unsigned NumElems = VT . getVectorNumElements ( ) ;

if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return false ;


<s> return AllOnes ? isAllOnesConstant ( N ) : isNullConstant ( N ) ;


<s> if ( ! Subtarget -> hasFPARMv8 ( ) ) return <STR_LIT> ; if ( ConstraintVT . isFloatingPoint ( ) ) return <STR_LIT> ;

if ( ConstraintVT . isVector ( ) && ( ConstraintVT . getSizeInBits ( ) == <NUM_LIT> || ConstraintVT . getSizeInBits ( ) == <NUM_LIT> ) ) return <STR_LIT> ;


<s> TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) -> setReg ( NewBase ) ; TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) -> setImm ( NewOffset ) ;


<s> return <STR_LIT> ; case ALPHA_FPRM_DYN : return <STR_LIT> ; default : gcc_unreachable ( ) ; } break ; case ROUND_SUFFIX_C : return <STR_LIT> ; default : gcc_unreachable ( ) ;


<s> switch ( RegName [ <NUM_LIT> ] ) { case 'r' : case 'f' : case 'v' :

if ( RegName [ <NUM_LIT> ] == 's' ) return RegName + <NUM_LIT> ;


<s> return ( isGlobalInSmallSectionImpl ( GV , TM ) && ( Kind . isData ( ) || Kind . isBSS ( ) || Kind . isCommon ( ) ) ) ;


<s> return getSubRegFromChannel ( IndirectIndex ) ;


<s> <ISA_LIT>WinCOFFObjectWriter ( ) : MCWinCOFFObjectTargetWriter ( COFF :: IMAGE_FILE_MACHINE_ARM64 ) {


<s> fprintf ( stream , <STR_LIT> , name2 , size ) ; fprintf ( stream , <STR_LIT> , name2 , size ) ; return ; } if ( ! global ) { fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , name ) ; fprintf ( stream , <STR_LIT> ) ; } fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , name ) ;

fprintf ( stream , <STR_LIT> , size , align / BITS_PER_UNIT ) ;


<s> __attribute__ ( ( __always_inline__ ) ) vmulxs_f32 ( float32_t a , float32_t b ) { float32_t result ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> Op -> Mem . BaseReg = <NUM_LIT> ; Op -> Mem . AluOp = LPAC :: ADD ; Op -> Mem . OffsetReg = <NUM_LIT> ; Op -> Mem . Offset = Imm ;


<s> static void addAndInterleaveWithUnsupported ( LegalizerInfo :: SizeAndActionsVec & result , const LegalizerInfo :: SizeAndActionsVec & v ) { for ( unsigned i = <NUM_LIT> ; i < v . size ( ) ; ++ i ) { result . push_back ( v [ i ] ) ; if ( i + <NUM_LIT> < v [ i ] . first && i + <NUM_LIT> < v . size ( ) && v [ i + <NUM_LIT> ] . first != v [ i ] . first + <NUM_LIT> ) result . push_back ( { v [ i ] . first + <NUM_LIT> , LegalizerInfo :: Unsupported } ) ;


<s> SDValue CCR = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue Flags = combineSetCCCCR ( CCR , CC , DAG , Subtarget ) ) {

SDValue Cond = DAG . getConstant ( CC , DL , <STR_LIT> ) ;


<s> bool HasAnyUndefs ; if ( ! Node -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget . isLittle ( ) ) ) return false ; Imm = SplatValue ;


<s> I . addOperand ( MCOperand :: CreateReg ( Reg1 ) ) ; I . addOperand ( MCOperand :: CreateReg ( Reg2 ) ) ; OutStreamer . EmitInstruction ( I , getSubtargetInfo ( ) ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetAt ( ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM , OL ) , DataLayout ( is64Bit ? DataLayout64 : DataLayout32 ) , Subtarget ( TT , CPU , FS , is64Bit ) , FrameLowering ( Subtarget ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo ( * this ) {


<s> Val = <STR_LIT> ( AddSub , Val , <STR_LIT> ) ; } else { Val = <STR_LIT> ( Memory . isNegative ? <STR_LIT> : <STR_LIT> , Memory . ShiftImm , Memory . ShiftType ) ; } Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( Memory . OffsetRegNum ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ;


<s> name += skip ; } if ( verbatim ) fputs ( name , stream ) ;

else asm_fprintf ( stream , <STR_LIT> , name ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) || ! isUInt < <NUM_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumImmRangeRejs ; return nullptr ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isDeadDef ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return I ; DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumLiveDstRejs ; return nullptr ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return I ; } MIOperands :: PhysRegInfo PRI = MIOperands ( * I ) . analyzePhysReg ( <STR_LIT> , TRI ) ; if ( PRI . Read ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I ) ; ++ NumMultNZCVUses ; return nullptr ;


<s> SmallVector < SDNode * , <NUM_LIT> > ToReplace ; for ( SDNode * User : N -> uses ( ) ) { assert ( ( User -> getMachineOpcode ( ) == <STR_LIT> || User -> getMachineOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; ToReplace . push_back ( User ) ; } for ( SDNode * User : ToReplace ) { SDNode * ResNode = CurDAG -> getMachineNode ( User -> getMachineOpcode ( ) , SDLoc ( User ) , User -> getValueType ( <NUM_LIT> ) , User -> getOperand ( <NUM_LIT> ) , User -> getOperand ( <NUM_LIT> ) , User -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( User -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ResNode -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> return ( __m64 ) __builtin_ia32_pslldi ( ( __v2si ) __m , __count ) ;


<s> bool nds32_e8_load_to_ex_p ( rtx_insn * producer , rtx_insn * consumer ) { rtx def_reg = SET_DEST ( PATTERN ( producer ) ) ; return e8_consumed_by_ex_p ( consumer , def_reg ) ;


if ( get<ISA_LIT>Subtarget ( ) . isCheri ( ) ) addPass ( createCheriInvalidatePass ( ) ) ;


<s> void <ISA_LIT>ATTAsmPrinter :: printMachineInstruction ( const MachineInstr * MI ) {


<s> case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> rtx size ; int i ; top_label = gen_label_rtx ( ) ; out_label = gen_label_rtx ( ) ; iter = gen_reg_rtx ( iter_mode ) ; size = expand_simple_binop ( iter_mode , AND , count , piece_size_mask , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; if ( piece_size == const1_rtx ) { emit_cmp_and_jump_insns ( size , const0_rtx , EQ , NULL_RTX , iter_mode , true , out_label ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; } emit_move_insn ( iter , const0_rtx ) ; emit_label ( top_label ) ; tmp = convert_modes ( Pmode , iter_mode , iter , true ) ; gcc_assert ( ( piece_size_n & ( piece_size_n - <NUM_LIT> ) ) == <NUM_LIT> ) ; destmem = offset_address ( destmem , tmp , piece_size_n ) ; destmem = adjust_address ( destmem , mode , <NUM_LIT> ) ; if ( ! issetmem ) { srcmem = offset_address ( srcmem , copy_rtx ( tmp ) , piece_size_n ) ; srcmem = adjust_address ( srcmem , mode , <NUM_LIT> ) ; if ( ! TARGET_64BIT && <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) { destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; srcmem = adjust_address ( copy_rtx ( srcmem ) , mode , GET_MODE_SIZE ( mode ) ) ; } emit_move_insn ( destmem , srcmem ) ; } } else { rtx tmpreg [ <NUM_LIT> ] ; gcc_assert ( unroll <= <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { tmpreg [ i ] = gen_reg_rtx ( mode ) ; if ( i ) { srcmem = adjust_address ( copy_rtx ( srcmem ) , mode , GET_MODE_SIZE ( mode ) ) ; } emit_move_insn ( tmpreg [ i ] , srcmem ) ; } for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) { destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; } emit_move_insn ( destmem , tmpreg [ i ] ) ; } }


<s> virtual void emitARM64WinCFISaveLRPair ( unsigned Reg , int Offset ) {


<s> SmallVectorImpl < CCValAssign > & PendingHAMembers = State . getPendingLocs ( ) ; assert ( PendingHAMembers . size ( ) < <NUM_LIT> ) ; if ( PendingHAMembers . size ( ) > <NUM_LIT> ) assert ( PendingHAMembers [ <NUM_LIT> ] . getLocVT ( ) == LocVT ) ; PendingHAMembers . push_back ( CCValAssign :: getPending ( ValNo , ValVT , LocVT , LocInfo ) ) ; if ( ArgFlags . isInConsecutiveRegsLast ( ) ) { assert ( PendingHAMembers . size ( ) > <NUM_LIT> && PendingHAMembers . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; ArrayRef < uint16_t > RegList ; switch ( LocVT . SimpleTy ) { case <STR_LIT> : RegList = SRegList ; break ; case <STR_LIT> : RegList = DRegList ; break ; case <STR_LIT> : RegList = QRegList ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } unsigned RegResult = State . AllocateRegBlock ( RegList , PendingHAMembers . size ( ) ) ; if ( RegResult ) { for ( SmallVectorImpl < CCValAssign > :: iterator It = PendingHAMembers . begin ( ) ; It != PendingHAMembers . end ( ) ; ++ It ) { It -> convertToReg ( RegResult ) ; State . addLoc ( * It ) ; ++ RegResult ; } PendingHAMembers . clear ( ) ; return true ; } for ( unsigned regNo = <NUM_LIT> ; regNo < <NUM_LIT> ; ++ regNo ) State . AllocateReg ( SRegList [ regNo ] ) ; unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; unsigned Align = std :: min ( Size , <NUM_LIT> ) ; for ( auto It : PendingHAMembers ) { It . convertToMem ( State . AllocateStack ( Size , Align ) ) ;


<s> TmpInst . setOpcode ( opCode ) ; TmpInst . addOperand ( Rdd ) ; TmpInst . addOperand ( MO1 ) ;


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , EVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' :

switch ( VT . getSimpleVT ( ) . SimpleTy ) {


<s> return new <ISA_LIT>Disassembler ( STI , T . createMCRegInfo ( <STR_LIT> ) , true ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const {

if ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfhmin ( ) ) return <NUM_LIT> ;


<s> bool Modified = false ; for ( const auto & Use : SamplerArg . uses ( ) ) { auto Inst = dyn_cast < CallInst > ( Use . getUser ( ) ) ; if ( ! Inst ) { continue ; } Function * F = Inst -> getCalledFunction ( ) ; if ( ! F ) continue ; Value * Replacement = nullptr ; StringRef Name = F -> getName ( ) ; if ( Name == GetSamplerResourceIDFunc ) { Replacement = ConstantInt :: get ( Int32Type , ResourceID ) ; } else { continue ; } Inst -> replaceAllUsesWith ( Replacement ) ; InstsToErase . push_back ( Inst ) ; Modified = true ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options ) , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , * this ) , TLOF ( make_unique < TargetLoweringObjectFileELF > ( ) ) {


<s> for ( Argument & Arg : F . args ( ) ) { if ( Arg . getType ( ) -> isPointerTy ( ) ) { if ( Arg . hasByValAttr ( ) ) handleByValParam ( & Arg ) ; else if ( TM && TM -> getDrvInterface ( ) == <STR_LIT> ) markPointerAsGlobal ( & Arg ) ; } }


<s> <ISA_LIT>_64GOTPLT :: ~ <ISA_LIT>_64GOTPLT ( ) {


<s> bool <ISA_LIT>ExpandPseudo :: ExpandMBB ( MachineBasicBlock & MBB ) { bool Modified = false ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= ExpandMI ( MBB , MBBI ) ; MBBI = NMBBI ; } return Modified ;


<s> if ( ! NoOpt ) addPass ( create<ISA_LIT>OptimizeSZextends ( ) ) ; addPass ( create<ISA_LIT>ISelDag ( TM , getOptLevel ( ) ) ) ; if ( ! NoOpt ) { if ( EnableGenPred ) addPass ( create<ISA_LIT>GenPredicate ( ) ) ; if ( EnableLoopResched ) addPass ( create<ISA_LIT>LoopRescheduling ( ) ) ; if ( ! DisableHSDR ) addPass ( create<ISA_LIT>SplitDoubleRegs ( ) ) ;

if ( EnableBitSimplify ) addPass ( create<ISA_LIT>BitSimplify ( ) ) ;


<s> const <ISA_LIT>TargetLowering & TLI = * Subtarget -> getTargetLowering ( ) ; computeLegalValueVTs ( TLI , GV -> getParent ( ) -> getContext ( ) , GV -> getParent ( ) -> getDataLayout ( ) , GlobalVT , VTs ) ; } <STR_LIT> ( Sym , GlobalVT , VTs ) ; } emitVisibility ( Sym , GV -> getVisibility ( ) , ! GV -> isDeclaration ( ) ) ;


<s> bool simple_loop = false ; FOR_EACH_EDGE ( e , ei , bb -> preds ) if ( e -> src == bb ) { simple_loop = true ; break ; } if ( simple_loop ) distance = distance_non_agu_define_in_bb ( regno1 , regno2 , insn , distance , BB_END ( bb ) , & found ) ; else { int shortest_dist = - <NUM_LIT> ; bool found_in_bb = false ; FOR_EACH_EDGE ( e , ei , bb -> preds ) { int bb_dist = distance_non_agu_define_in_bb ( regno1 , regno2 , insn , distance , BB_END ( e -> src ) , & found_in_bb ) ; if ( found_in_bb ) { if ( shortest_dist < <NUM_LIT> ) shortest_dist = bb_dist ; else if ( bb_dist > <NUM_LIT> ) shortest_dist = MIN ( bb_dist , shortest_dist ) ; found = true ; } } distance = shortest_dist ; } }


<s> prepareVolatileOrAtomicLoad ( SDValue Chain , SDLoc DL , SelectionDAG & DAG ) const { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ;


<s> if ( ! <STR_LIT> ( F . getCallingConv ( ) ) ) return false ;


<s> Register Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ;

MaxStoresPerMemset = MaxStoresPerMemsetOptSize = <NUM_LIT> ;


<s> if ( SUnit * SU = Top . pickOnlyChoice ( ) ) { IsTopNode = true ; return SU ; } SchedCandidate BotCand ; CandResult BotResult = pickNodeFromQueue ( Bot . Available , DAG -> getBotRPTracker ( ) , BotCand ) ; assert ( BotResult != NoCand && <STR_LIT> ) ; if ( BotResult == SingleExcess || BotResult == SingleCritical ) { IsTopNode = false ; return BotCand . SU ; } SchedCandidate TopCand ;

CandResult TopResult = pickNodeFromQueue ( Top . Available , DAG -> getTopRPTracker ( ) , TopCand ) ;


<s> void <ISA_LIT>InstPrinter :: printV4U64 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { O << '(' ; printU64 ( MI , OpNo + <NUM_LIT> , O ) ; O << <STR_LIT> ; printU64 ( MI , OpNo + <NUM_LIT> , O ) ;


<s> bool SelectAddrImmX4 ( SDValue N , SDValue & Disp , SDValue & Base ) {

return <ISA_LIT>Lowering -> SelectAddressRegImm ( N , Disp , Base , * CurDAG , <NUM_LIT> ) ;


<s> if ( OptLevel == <NUM_LIT> ) return false ;

if ( MF . getTarget ( ) . Options . AllowFPOpFusion == FPOpFusion :: Fast ) return true ;


<s> TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; return ; } unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( * Tail , PredReg ) ; MachineBasicBlock :: iterator MBBI = Tail ; if ( CC != <STR_LIT> ) -- MBBI ; TargetInstrInfo :: ReplaceTailWithBranchTo ( Tail , NewDest ) ; if ( CC != <STR_LIT> ) { MachineBasicBlock :: iterator E = MBB -> begin ( ) ; unsigned Count = <NUM_LIT> ; while ( Count && MBBI != E ) { if ( MBBI -> isDebugValue ( ) ) { -- MBBI ; continue ; } if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { unsigned Mask = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;

if ( Count == <NUM_LIT> ) MBBI -> eraseFromParent ( ) ;


<s> if ( ! MRI . isLiveIn ( Reg ) ) { VReg = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( Reg , VReg ) ; } else { VReg = MRI . getLiveInVirtReg ( Reg ) ;


<s> static void nvptx_globalize_label ( FILE * , const char * ) {


<s> if ( t1 == cris_got_symbol || t1 == cris_got_symbol ) return cris_got_symbol_needing_fixup ; return t1 != cris_no_symbol ? t1 : t2 ; } case CONST_INT : case CONST_DOUBLE : return cris_no_symbol ; case UNSPEC : return cris_invalid_pic_symbol ; default : fatal_insn ( <STR_LIT> , x ) ; }


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> inline bool mips_lo_sum_offset_hasher :: equal ( const value_type * entry , const compare_type * value ) {

return rtx_equal_p ( entry -> base , value ) ;


<s> WasmSym -> setGlobalType ( <STR_LIT> { uint8_t ( Subtarget . hasAddr64 ( ) ? <STR_LIT> : <STR_LIT> ) , Mutable } ) ; return WasmSym ; } SmallVector < <STR_LIT> , <NUM_LIT> > Returns ; SmallVector < <STR_LIT> , <NUM_LIT> > Params ; if ( strcmp ( Name , <STR_LIT> ) == <NUM_LIT> ) { WasmSym -> setType ( <STR_LIT> ) ; WasmSym -> setEventType ( { <STR_LIT> , <NUM_LIT> } ) ; WasmSym -> setWeak ( true ) ; WasmSym -> setExternal ( true ) ; Params . push_back ( Subtarget . hasAddr64 ( ) ? <STR_LIT> :: I64 : <STR_LIT> :: I32 ) ; } else { WasmSym -> setType ( <STR_LIT> ) ;

getLibcallSignature ( Subtarget , Name , Returns , Params ) ;


<s> if ( ! <STR_LIT> ( DppCtrl -> getImm ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } } auto * RowMaskOpnd = TII -> getNamedOperand ( MovMI , <STR_LIT> :: row_mask ) ; assert ( RowMaskOpnd && RowMaskOpnd -> isImm ( ) ) ; auto * BankMaskOpnd = TII -> getNamedOperand ( MovMI , <STR_LIT> :: bank_mask ) ; assert ( BankMaskOpnd && BankMaskOpnd -> isImm ( ) ) ; const bool MaskAllLanes = RowMaskOpnd -> getImm ( ) == <NUM_LIT> && BankMaskOpnd -> getImm ( ) == <NUM_LIT> ; auto * BCZOpnd = TII -> getNamedOperand ( MovMI , <STR_LIT> :: bound_ctrl ) ; assert ( BCZOpnd && BCZOpnd -> isImm ( ) ) ; bool BoundCtrlZero = BCZOpnd -> getImm ( ) ; auto * OldOpnd = TII -> getNamedOperand ( MovMI , <STR_LIT> :: old ) ; auto * SrcOpnd = TII -> getNamedOperand ( MovMI , <STR_LIT> :: src0 ) ; assert ( OldOpnd && OldOpnd -> isReg ( ) ) ; assert ( SrcOpnd && SrcOpnd -> isReg ( ) ) ; if ( OldOpnd -> getReg ( ) . isPhysical ( ) || SrcOpnd -> getReg ( ) . isPhysical ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto * const OldOpndValue = getOldOpndValue ( * OldOpnd ) ; assert ( ! OldOpndValue || OldOpndValue -> isImm ( ) || OldOpndValue == OldOpnd ) ; bool CombBCZ = false ; if ( MaskAllLanes && BoundCtrlZero ) { CombBCZ = true ; } else { if ( ! OldOpndValue || ! OldOpndValue -> isImm ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( OldOpndValue -> getImm ( ) == <NUM_LIT> ) { if ( MaskAllLanes ) { assert ( ! BoundCtrlZero ) ; CombBCZ = true ; } } else if ( BoundCtrlZero ) { assert ( ! MaskAllLanes ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; if ( ! OldOpndValue ) dbgs ( ) << <STR_LIT> ; else dbgs ( ) << * OldOpndValue ; dbgs ( ) << <STR_LIT> << CombBCZ << '\n' ) ; SmallVector < MachineInstr * , <NUM_LIT> > OrigMIs , DPPMIs ; DenseMap < MachineInstr * , SmallVector < unsigned , <NUM_LIT> >> RegSeqWithOpNos ; auto CombOldVGPR = getRegSubRegPair ( * OldOpnd ) ; if ( CombBCZ && OldOpndValue ) { const TargetRegisterClass * RC = MRI -> getRegClass ( DPPMovReg ) ; CombOldVGPR = RegSubRegPair ( MRI -> createVirtualRegister ( RC ) ) ;

auto UndefInst = BuildMI ( * MovMI . getParent ( ) , MovMI , MovMI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , CombOldVGPR . Reg ) ;


<s> void <ISA_LIT>InstPrinter :: printAdrLabelOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; if ( MO . isExpr ( ) ) { MO . getExpr ( ) -> print ( O , & MAI ) ; return ; } int32_t OffImm = ( int32_t ) MO . getImm ( ) << scale ; O << markup ( <STR_LIT> ) ; if ( OffImm == INT32_MIN ) O << <STR_LIT> ; else if ( OffImm < <NUM_LIT> ) O << <STR_LIT> << - OffImm ; else O << <STR_LIT> << OffImm ; O << markup ( <STR_LIT> ) ;


<s> bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; bool HasMemOp4 = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; if ( HasMemOp4 ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return - <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool HasVEX_4V = ( TSFlags >> <STR_LIT> ) & <STR_LIT> ; unsigned FirstMemOp = <NUM_LIT> ; if ( HasVEX_4V ) ++ FirstMemOp ; return FirstMemOp ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> virtual bool isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , const BranchProbability & Probability ) const { return true ;


<s> OutStreamer -> AddComment ( <STR_LIT> + Twine ( MFI -> getWARegStackId ( MFI -> getWAReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ) ) ; OutStreamer -> AddBlankLine ( ) ; } break ; } case <STR_LIT> : if ( isVerbose ( ) ) { OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> AddBlankLine ( ) ; } break ; default : { <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * this ) ; MCInst TmpInst ;

MCInstLowering . Lower ( MI , TmpInst ) ;


<s> return DAG . getConstant ( ( Subtarget -> is64Bit ( ) ? PnaclTargetArchitecture<ISA_LIT>_64 : PnaclTargetArchitecture<ISA_LIT>_32 ) , Op . getValueType ( ) . getSimpleVT ( ) ) ;


<s> if ( <ISA_LIT>InstrInfo :: isDPP ( * MI ) ) WaitStates = std :: max ( WaitStates , checkDPPHazards ( MI ) ) ; if ( isDivFMas ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkDivFMasHazards ( MI ) ) ; if ( isRWLane ( MI -> getOpcode ( ) ) ) WaitStates = std :: max ( WaitStates , checkRWLaneHazards ( MI ) ) ; if ( ( <ISA_LIT>InstrInfo :: isVALU ( * MI ) || <ISA_LIT>InstrInfo :: isVMEM ( * MI ) || <ISA_LIT>InstrInfo :: isFLAT ( * MI ) || <ISA_LIT>InstrInfo :: isDS ( * MI ) || <ISA_LIT>InstrInfo :: isEXP ( * MI ) ) && checkMAIVALUHazards ( MI ) > <NUM_LIT> ) WaitStates = std :: max ( WaitStates , checkMAIVALUHazards ( MI ) ) ; if ( MI -> isInlineAsm ( ) ) return std :: max ( WaitStates , checkInlineAsmHazards ( MI ) ) ; if ( isSGetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkGetRegHazards ( MI ) ) ; if ( isSSetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkSetRegHazards ( MI ) ) ; if ( isRFE ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkRFEHazards ( MI ) ) ; if ( ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) ) || ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) ) || ( ST . hasReadM0LdsDmaHazard ( ) && isLdsDma ( * MI ) ) || ( ST . hasReadM0LdsDirectHazard ( ) && MI -> readsRegister ( <STR_LIT> ) ) ) return std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; if ( <ISA_LIT>InstrInfo :: isMAI ( * MI ) ) return std :: max ( WaitStates , checkMAIHazards ( MI ) ) ;

if ( <ISA_LIT>InstrInfo :: isVMEM ( * MI ) || <ISA_LIT>InstrInfo :: isFLAT ( * MI ) || <ISA_LIT>InstrInfo :: isDS ( * MI ) ) return std :: max ( WaitStates , checkMAILdStHazards ( MI ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , dl , <STR_LIT> ) ; } break ; } } } else if ( ( <STR_LIT> ( LHS . getOpcode ( ) ) != <STR_LIT> ) && ( <STR_LIT> ( RHS . getOpcode ( ) ) == <STR_LIT> ) ) { CC = <STR_LIT> ( CC ) ; std :: swap ( LHS , RHS ) ; } <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; <STR_LIT> CompareType ; switch ( CondCode ) { default : CompareType = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CompareType = <STR_LIT> ; break ;


<s> MachineBasicBlock * TB = nullptr , * FB = nullptr ; bool NotAnalyzed = TII -> analyzeBranch ( * ExitingBlock , TB , FB , Cond , false ) ; if ( NotAnalyzed ) return false ; unsigned PredR , PredPos , PredRegFlags ; if ( ! TII -> getPredReg ( Cond , PredR , PredPos , PredRegFlags ) ) return false ; MachineInstr * PredI = MRI -> getVRegDef ( PredR ) ; if ( ! PredI -> isCompare ( ) ) return false ; unsigned CmpReg1 = <NUM_LIT> , CmpReg2 = <NUM_LIT> ; int CmpImm = <NUM_LIT> , CmpMask = <NUM_LIT> ; bool CmpAnalyzed = TII -> analyzeCompare ( * PredI , CmpReg1 , CmpReg2 , CmpMask , CmpImm ) ; if ( ! CmpAnalyzed ) return false ; InductionMap :: iterator IndMapEnd = IndMap . end ( ) ; InductionMap :: iterator F = IndMapEnd ; if ( CmpReg1 != <NUM_LIT> ) { InductionMap :: iterator F1 = IndMap . find ( CmpReg1 ) ; if ( F1 != IndMapEnd ) F = F1 ; } if ( CmpReg2 != <NUM_LIT> ) { InductionMap :: iterator F2 = IndMap . find ( CmpReg2 ) ; if ( F2 != IndMapEnd ) { if ( F != IndMapEnd ) return false ;


<s> aarch64_def_or_undef ( TARGET_LSE , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_AES , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SHA2 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SHA3 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_SM4 , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_F16FML , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_FRINT , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_TME , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_RNG , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_MEMTAG , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( aarch64_bti_enabled ( ) , <STR_LIT> , pfile ) ; cpp_undef ( pfile , <STR_LIT> ) ; if ( aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE ) { int v = <NUM_LIT> ; if ( aarch64_ra_sign_key == AARCH64_KEY_A ) v |= <NUM_LIT> ; if ( aarch64_ra_sign_key == AARCH64_KEY_B ) v |= <NUM_LIT> ; if ( aarch64_ra_sign_scope == AARCH64_FUNCTION_ALL ) v |= <NUM_LIT> ; builtin_define_with_int_value ( <STR_LIT> , v ) ; } aarch64_def_or_undef ( TARGET_I8MM , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_BF16_SIMD , <STR_LIT> , pfile ) ; aarch64_def_or_undef ( TARGET_BF16_FP , <STR_LIT> , pfile ) ;

aarch64_def_or_undef ( TARGET_LS64 , <STR_LIT> , pfile ) ;


<s> OutStreamer -> SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; }

OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ;


<s> return decodeBDLAddr12Len8Operand ( Inst , Field , <STR_LIT> ) ;


<s> if ( TREE_CODE ( * node ) != FUNCTION_DECL ) {

warning ( OPT_Wattributes , <STR_LIT> , name ) ;


<s> bool <ISA_LIT>TTIImpl :: areTypesABICompatible ( const Function * Caller , const Function * Callee , const ArrayRef < Type * > & Types ) const { if ( ! BaseT :: areTypesABICompatible ( Caller , Callee , Types ) ) return false ; const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( * Caller ) . useAVX512Regs ( ) == TM . getSubtarget < <ISA_LIT>Subtarget > ( * Callee ) . useAVX512Regs ( ) ) return true ;

return llvm :: none_of ( Types , [ ] ( Type * T ) { return T -> isVectorTy ( ) || T -> isAggregateType ( ) ; } ) ;


<s> const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO1 . getReg ( ) ) ) ; O << <STR_LIT> << TM . getRegisterInfo ( ) -> get ( MO1 . getReg ( ) ) . AsmName ; if ( MO2 . getReg ( ) ) { O << <STR_LIT> << ( char ) <STR_LIT> ( MO3 . getImm ( ) ) << TM . getRegisterInfo ( ) -> get ( MO2 . getReg ( ) ) . AsmName << <STR_LIT> ;


<s> void <ISA_LIT>InstrInfo :: swapOperands ( MachineBasicBlock :: iterator Inst ) const { assert ( Inst -> getNumExplicitOperands ( ) == <NUM_LIT> ) ; MachineOperand Op1 = Inst -> getOperand ( <NUM_LIT> ) ; Inst -> RemoveOperand ( <NUM_LIT> ) ; Inst -> addOperand ( Op1 ) ;


<s> if ( Amount == <NUM_LIT> ) return MBB . erase ( I ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const DebugLoc & DL = I -> getDebugLoc ( ) ; unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII -> getCallFrameDestroyOpcode ( ) ; uint64_t CalleePopAmount = IsDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; if ( ! hasReservedCallFrame ( MF ) ) { Amount = alignTo ( Amount , getStackAlign ( ) ) ;

assert ( isUInt < <NUM_LIT> > ( Amount ) && <STR_LIT> ) ;


<s> Tile64MachineFunctionInfo * FI = MF -> getInfo < Tile64MachineFunctionInfo > ( ) ; unsigned GlobalBaseReg = FI -> getGlobalBaseReg ( ) ; if ( GlobalBaseReg != <NUM_LIT> ) return GlobalBaseReg ; MachineBasicBlock & FirstMBB = MF -> front ( ) ; MachineBasicBlock :: iterator MBBI = FirstMBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ;

return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasOpaqueSPAdjustment ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) || MMI . hasEHFunclets ( ) || MMI . callsEHReturn ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || MFI . hasCopyImplyingStackAdjustment ( ) ) ;


<s> switch ( T ) { case RT64_NONE : return RT32_NONE ; case RT64_64 : llvm_unreachable ( <STR_LIT> ) ; case RT64_32 : case RT64_32S :


<s> if ( T . getOS ( ) == llvm :: Triple :: FreeBSD || ( T . getOS ( ) == llvm :: Triple :: NetBSD && ! is64Bit ) || ( T . getOS ( ) == llvm :: Triple :: OpenBSD && ! is64Bit ) ) UseIntegratedAssembler = true ;


<s> else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; print<ISA_LIT>MEMriOperand ( MI , <NUM_LIT> , O ) ; O << <STR_LIT> ; int addend = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( addend < <NUM_LIT> ) O << <STR_LIT> << <STR_LIT> << - addend << '\n' ; else O << <STR_LIT> << <STR_LIT> << addend << '\n' ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { O << <STR_LIT> ; printRegister ( MI -> getOperand ( <NUM_LIT> ) , false , O ) ; O << <STR_LIT> ;


<s> assert ( RegMap [ Stack [ i ] ] == i && <STR_LIT> ) ; }


<s> return new avr_pass_casesi ( ctxt , <STR_LIT> ) ;


<s> SDValue Low , High ; if ( Subtarget . hasSSE41 ( ) ) { MVT VecI16VT = Is128 ? <STR_LIT> : <STR_LIT> ; SDValue VecCstLowBitcast = DAG . getBitcast ( VecI16VT , VecCstLow ) ; SDValue VecBitcast = DAG . getBitcast ( VecI16VT , V ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecBitcast , VecCstLowBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue VecCstHighBitcast = DAG . getBitcast ( VecI16VT , VecCstHigh ) ; SDValue VecShiftBitcast = DAG . getBitcast ( VecI16VT , HighShift ) ; High = DAG . getNode ( <STR_LIT> , DL , VecI16VT , VecShiftBitcast , VecCstHighBitcast , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } else { SDValue VecCstMask = DAG . getConstant ( <NUM_LIT> , DL , VecIntVT ) ; SDValue LowAnd = DAG . getNode ( <STR_LIT> , DL , VecIntVT , V , VecCstMask ) ; Low = DAG . getNode ( <STR_LIT> , DL , VecIntVT , LowAnd , VecCstLow ) ; High = DAG . getNode ( <STR_LIT> , DL , VecIntVT , HighShift , VecCstHigh ) ; } SDValue VecCstFAdd = DAG . getConstantFP ( APFloat ( APFloat :: IEEEsingle ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) , DL , VecFloatVT ) ;

SDValue HighBitcast = DAG . getBitcast ( VecFloatVT , High ) ;


<s> int tmp ; if ( ! len ) len = & tmp ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) { int val = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( ( val & <NUM_LIT> ) == <NUM_LIT> ) { * len = <NUM_LIT> ; return ( AS2 ( mov , % A0 , __zero_reg__ ) CR_TAB AS2 ( ldi , % <NUM_LIT> , hi8 ( % <NUM_LIT> ) ) CR_TAB AS2 ( mov , % B0 , % <NUM_LIT> ) ) ; } else if ( ( val & <NUM_LIT> ) == <NUM_LIT> ) { * len = <NUM_LIT> ; return ( AS2 ( ldi , % <NUM_LIT> , lo8 ( % <NUM_LIT> ) ) CR_TAB AS2 ( mov , % A0 , % <NUM_LIT> ) CR_TAB AS2 ( mov , % B0 , __zero_reg__ ) ) ; } else if ( ( val & <NUM_LIT> ) == ( ( val & <NUM_LIT> ) >> <NUM_LIT> ) ) { * len = <NUM_LIT> ; return ( AS2 ( ldi , % <NUM_LIT> , lo8 ( % <NUM_LIT> ) ) CR_TAB AS2 ( mov , % A0 , % <NUM_LIT> ) CR_TAB AS2 ( mov , % B0 , % <NUM_LIT> ) ) ; } } * len = <NUM_LIT> ; return ( AS2 ( ldi , % <NUM_LIT> , lo8 ( % <NUM_LIT> ) ) CR_TAB AS2 ( mov , % A0 , % <NUM_LIT> ) CR_TAB AS2 ( ldi , % <NUM_LIT> , hi8 ( % <NUM_LIT> ) ) CR_TAB AS2 ( mov , % B0 , % <NUM_LIT> ) ) ;


MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> for ( i = <NUM_LIT> ; i < ( TARGET_V9 ? <NUM_LIT> : <NUM_LIT> ) ; i += <NUM_LIT> ) if ( save_global_or_fp_reg_p ( i , <NUM_LIT> ) || save_global_or_fp_reg_p ( i + <NUM_LIT> , <NUM_LIT> ) ) n_global_fp_regs += <NUM_LIT> ; if ( size == <NUM_LIT> && n_global_fp_regs == <NUM_LIT> && args_size == <NUM_LIT> && ! save_local_in_regs_p ) frame_size = apparent_frame_size = <NUM_LIT> ; else { apparent_frame_size = ROUND_UP ( size , <NUM_LIT> ) + n_global_fp_regs * <NUM_LIT> ; frame_size = apparent_frame_size + ROUND_UP ( args_size , <NUM_LIT> ) ; frame_size += FIRST_PARM_OFFSET ( cfun -> decl ) ; frame_size = SPARC_STACK_ALIGN ( frame_size ) ; }


<s> LR [ <NUM_LIT> ] . first = <STR_LIT> ; LR [ <NUM_LIT> ] . second = <NUM_LIT> ;


<s> inline vector unsigned int vec_vminuw ( vector unsigned int a1 , vector unsigned int a2 ) { return ( vector unsigned int ) __builtin_altivec_vminuw ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> for ( size_t i = <NUM_LIT> ; i < NumKernelArgMDNodes ; ++ i ) { MDNode * ArgNode = dyn_cast_or_null < MDNode > ( Node -> getOperand ( i + <NUM_LIT> ) ) ; if ( ArgNode -> getNumOperands ( ) != ExpectNumArgNodeOps ) return nullptr ; if ( ! ArgNode -> getOperand ( <NUM_LIT> ) ) return nullptr ; MDString * StringNode = dyn_cast < MDString > ( ArgNode -> getOperand ( <NUM_LIT> ) ) ;

if ( ! StringNode || StringNode -> getString ( ) != KernelArgMDNodeNames [ i ] ) return nullptr ;


<s> void <ISA_LIT>InstPrinter :: printBrTargetOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ;


<s> if ( is<ISA_LIT>64 ( ) ) return <NUM_LIT> ;

return isAIXABI ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> t1 = gen_reg_rtx ( mode ) ; elt = convert_modes ( SImode , inner_mode , elt , true ) ; emit_move_insn ( gen_lowpart ( SImode , t1 ) , elt ) ; switch ( mode ) { case V2SImode : final_insn = gen_bshufflev2si_vis ( target , t1 , t1 ) ; bmask = <NUM_LIT> ; break ; case V4HImode : final_insn = gen_bshufflev4hi_vis ( target , t1 , t1 ) ;


<s> explicit MCGNode ( Type * t ) : MF ( NULL ) , T ( t ) , IsDead ( true ) , IsInSCC ( false ) {


<s> if ( Imm >= - <NUM_LIT> && Imm <= - <NUM_LIT> ) return <NUM_LIT> + std :: abs ( Imm ) ;


<s> static void setup_incoming_varargs ( CUMULATIVE_ARGS * cum , enum machine_mode mode ATTRIBUTE_UNUSED , tree type ATTRIBUTE_UNUSED , int * pretend_size , int no_rtl ) { rtx mem ; int i ; if ( no_rtl ) return ; for ( i = cum -> words + <NUM_LIT> ; i < max_arg_registers ; i ++ ) { mem = gen_rtx_MEM ( Pmode , plus_constant ( arg_pointer_rtx , ( i * UNITS_PER_WORD ) ) ) ; emit_move_insn ( mem , gen_rtx_REG ( Pmode , i ) ) ; }


<s> void <ISA_LIT>FrameLowering :: BuildStackAlignAND ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL , unsigned Reg , uint64_t MaxAlign ) const { uint64_t Val = - MaxAlign ; unsigned AndOp = getANDriOpcode ( Uses64BitFramePtr , Val ) ;

MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( AndOp ) , Reg ) . addReg ( Reg ) . addImm ( Val ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> BICInst . addOperand ( MCOperand :: CreateImm ( Pred ) ) ; BICInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ;

BICInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;


<s> MRI = & MF . getRegInfo ( ) ; ST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = ST -> getInstrInfo ( ) ; TRI = & TII -> getRegisterInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool IsIEEEMode = ST -> enableIEEEBit ( MF ) || ! MFI -> hasNoSignedZerosFPMath ( ) ; for ( MachineBasicBlock * MBB : depth_first ( & MF ) ) { MachineBasicBlock :: iterator I , Next ; for ( I = MBB -> begin ( ) ; I != MBB -> end ( ) ; I = Next ) { Next = std :: next ( I ) ;


<s> static MCOperand GetSymbolRef ( const MachineOperand & MO , const MCSymbol * Symbol , AsmPrinter & Printer , bool isDarwin ) { MCContext & Ctx = Printer . OutContext ; MCSymbolRefExpr :: VariantKind RefKind = MCSymbolRefExpr :: VK_None ; unsigned access = MO . getTargetFlags ( ) & <STR_LIT> ; switch ( access ) { case <STR_LIT> : RefKind = isDarwin ? MCSymbolRefExpr :: VK_<ISA_LIT>_DARWIN_HA16 : MCSymbolRefExpr :: VK_<ISA_LIT>_GAS_HA16 ; break ; case <STR_LIT> : RefKind = isDarwin ? MCSymbolRefExpr :: VK_<ISA_LIT>_DARWIN_LO16 : MCSymbolRefExpr :: VK_<ISA_LIT>_GAS_LO16 ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL16_HA ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_<ISA_LIT>_TPREL16_LO ;


<s> if ( NEED_INDICATE_EXEC_STACK ) file_end_indicate_exec_stack ( ) ;


<s> unsigned FixedNum = <NUM_LIT> , SplitNum = <NUM_LIT> , LoopPhiNum = <NUM_LIT> ; int32_t TotalP = <NUM_LIT> ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; int32_t P = profit ( DefI ) ; if ( P == std :: numeric_limits < int > :: min ( ) ) return false ; TotalP += P ; if ( isInduction ( DR , IRM ) ) TotalP -= <NUM_LIT> ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ;


<s> loongarch_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; if ( info . num_fprs ) return false ;


<s> if ( RVVVectorBitsMax == <NUM_LIT> ) return <NUM_LIT> ; if ( RVVVectorBitsMax < ( int ) ZvlLen ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; assert ( RVVVectorBitsMax >= <NUM_LIT> && RVVVectorBitsMax <= <NUM_LIT> && isPowerOf2_32 ( RVVVectorBitsMax ) && <STR_LIT> <STR_LIT> ) ;

assert ( RVVVectorBitsMax >= RVVVectorBitsMin && <STR_LIT> <STR_LIT> ) ;


<s> void <ISA_LIT>Z80InstPrinter :: printUImm8 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { assert ( MI -> getOperand ( OpNo ) . isImm ( ) && <STR_LIT> ) ; O << format ( <STR_LIT> , ( uint8_t ) ( uint64_t ) MI -> getOperand ( OpNo ) . getImm ( ) ) ;


<s> std :: vector < std :: string > mov_dvm_to ( Ab b ) { return D ( <STR_LIT> , <STR_LIT> , R ( b ) ) ;


<s> MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; if ( isInt < <NUM_LIT> > ( - StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( - StackSize ) ; else expandLargeImm ( SP , - StackSize , STI . isABI_N64 ( ) , TII , MBB , MBBI , dl ) ; MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP , - StackSize ) ; Moves . push_back ( MachineMove ( AdjustSPLabel , DstML , SrcML ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; if ( <STR_LIT> -> contains ( Reg ) ) { const uint16_t * SubRegs = RegInfo -> getSubRegisters ( Reg ) ; MachineLocation DstML0 ( MachineLocation :: VirtualFP , Offset ) ;

MachineLocation DstML1 ( MachineLocation :: VirtualFP , Offset + <NUM_LIT> ) ;


<s> void setDecorationStyle ( NameDecorationStyle style ) {


<s> assert ( FrameRegUpdate ) ; assert ( Size - LoopSize == <NUM_LIT> ) ; BuildMI ( * MBB , InsertI , DL , TII -> get ( ZeroData ? <STR_LIT> : <STR_LIT> ) ) . addDef ( BaseReg ) . addReg ( BaseReg ) . addReg ( BaseReg ) . addImm ( <NUM_LIT> + ExtraBaseRegUpdate / <NUM_LIT> ) . setMemRefs ( CombinedMemRefs ) . setMIFlags ( FrameRegUpdateFlags ) ; } else if ( ExtraBaseRegUpdate ) { BuildMI ( * MBB , InsertI , DL , TII -> get ( ExtraBaseRegUpdate > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addDef ( BaseReg ) . addReg ( BaseReg ) . addImm ( std :: abs ( ExtraBaseRegUpdate ) ) . addImm ( <NUM_LIT> ) . setMIFlags ( FrameRegUpdateFlags ) ;


<s> unsigned getMinVectorRegisterBitWidth ( ) const {


<s> if ( MI . getDesc ( ) . isCall ( ) ) break ; PotentialBlockers . push_back ( & MI ) ; } if ( BlockLimit < LIMIT ) { MachineBasicBlock * MBB = LoadInst -> getParent ( ) ; int LimitLeft = LIMIT - BlockLimit ; for ( MachineBasicBlock :: pred_iterator PB = MBB -> pred_begin ( ) , PE = MBB -> pred_end ( ) ; PB != PE ; ++ PB ) {


<s> static NodeRef getEntryNode ( const MCallSubGraph & G ) { return G . getEntryNode ( ) ? G . getEntryNode ( ) : G . Nodes . front ( ) ;


<s> else if ( ( from ) == ARG_POINTER_REGNUM && ( to ) == FRAME_POINTER_REGNUM ) { ret = cfun -> machine -> local_vars_size ; } else { abort ( ) ;


<s> bool SelectAddrIdxOnly ( SDValue N , SDValue & Base , SDValue & Index ) {

return <ISA_LIT>Lowering -> SelectAddressRegRegOnly ( N , Base , Index , * CurDAG ) ;


<s> void setVarArgsFrameIndex ( int Index ) {


<s> n = - n ; } n_rtx = GEN_INT ( n ) ; gcc_assert ( satisfies_constraint_P27 ( n_rtx ) ) ; switch ( type ) { case ASHIFTRT : emit_insn ( gen_ashrsi3_k ( reg , reg , n_rtx ) ) ; break ; case LSHIFTRT : if ( n == <NUM_LIT> ) emit_insn ( gen_shlr ( reg , reg ) ) ; else emit_insn ( gen_lshrsi3_k ( reg , reg , n_rtx ) ) ; break ; case ASHIFT :

emit_insn ( gen_ashlsi3_k ( reg , reg , n_rtx ) ) ;


<s> MCSection * getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const override { llvm_unreachable ( <STR_LIT> ) ;


<s> loc = opint [ <NUM_LIT> ] & <NUM_LIT> ; bytemask <<= loc ; if ( is_high ) bytemask >>= <NUM_LIT> ; opint [ <NUM_LIT> ] = bytemask ^ <NUM_LIT> ;


<s> case IS_DISPATCH_ON : return true ; case IS_CMP : return is_cmp ( insn ) ; case DISPATCH_VIOLATION : return dispatch_violation ( ) ; case FITS_DISPATCH_WINDOW : return fits_dispatch_window ( insn ) ;


<s> if ( NoFloat ) return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> else if ( TARGET_40_PLUS ) return false ; else { lb = gen_label_rtx ( ) ; r = gen_reg_rtx ( HImode ) ; emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_move_insn ( r , operands [ <NUM_LIT> ] ) ; if ( ! CONST_INT_P ( operands [ <NUM_LIT> ] ) ) { test = gen_rtx_LE ( HImode , r , const0_rtx ) ; emit_jump_insn ( gen_cbranchhi4 ( test , r , const0_rtx , lb ) ) ; } emit_insn ( ( * shift_base ) ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , r ) ) ; if ( ! CONST_INT_P ( operands [ <NUM_LIT> ] ) ) { emit_label ( lb ) ;


<s> Step = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Step , Flags ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Step , Flags ) ; } if ( ! Reciprocal ) Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Estimate , Flags ) ; ExtraSteps = <NUM_LIT> ;


<s> return ( STRICT_ALIGNMENT || ( ! TARGET_EFFICIENT_UNALIGNED_VSX && ( ( SCALAR_FLOAT_MODE_NOT_VECTOR_P ( mode ) && align < <NUM_LIT> ) || ( ( VECTOR_MODE_P ( mode ) || FLOAT128_VECTOR_P ( mode ) ) && ( int ) align < VECTOR_ALIGN ( mode ) ) ) ) ) ;


<s> int reloc = <NUM_LIT> ; switch ( TREE_CODE ( exp ) ) { case ADDR_EXPR : return <NUM_LIT> ; case POINTER_PLUS_EXPR : case PLUS_EXPR : case MINUS_EXPR : reloc = pa_reloc_needed ( TREE_OPERAND ( exp , <NUM_LIT> ) ) ; reloc |= pa_reloc_needed ( TREE_OPERAND ( exp , <NUM_LIT> ) ) ; break ; CASE_CONVERT : case NON_LVALUE_EXPR : reloc = pa_reloc_needed ( TREE_OPERAND ( exp , <NUM_LIT> ) ) ; break ;


<s> int bits ; val = aarch64_replicate_bitmask_imm ( val_in , mode ) ; tmp = val + ( val & - val ) ; if ( tmp == ( tmp & - tmp ) ) return ( val + <NUM_LIT> ) > <NUM_LIT> ;

if ( mode == SImode ) val = ( val << <NUM_LIT> ) | ( val & <NUM_LIT> ) ;


<s> } if ( LastValue . getNode ( ) ) BitGroups . push_back ( BitGroup ( LastValue , LastRLAmt , LastGroupStartIdx , Bits . size ( ) - <NUM_LIT> ) ) ; if ( BitGroups . empty ( ) ) return ; if ( BitGroups . size ( ) > <NUM_LIT> ) {

if ( BitGroups [ <NUM_LIT> ] . StartIdx == <NUM_LIT> && BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . EndIdx == Bits . size ( ) - <NUM_LIT> && BitGroups [ <NUM_LIT> ] . V == BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . V && BitGroups [ <NUM_LIT> ] . RLAmt == BitGroups [ BitGroups . size ( ) - <NUM_LIT> ] . RLAmt ) {


<s> if ( CPV -> getNumOperands ( ) ) for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( const ConstantDataSequential * CDS = dyn_cast < ConstantDataSequential > ( CPV ) ) { if ( CDS -> getNumElements ( ) ) for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) bufferLEByte ( cast < Constant > ( CDS -> getElementAsConstant ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( isa < ConstantStruct > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) { StructType * ST = cast < StructType > ( CPV -> getType ( ) ) ; for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == ( e - <NUM_LIT> ) ) Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( <NUM_LIT> ) + TD -> getTypeAllocSize ( ST ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; else Bytes = TD -> getStructLayout ( ST ) -> getElementOffset ( i + <NUM_LIT> ) - TD -> getStructLayout ( ST ) -> getElementOffset ( i ) ; bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , Bytes , aggBuffer ) ; } } return ;


<s> MachineFunction * MF = C . getMF ( ) ; const TargetRegisterInfo & TRI = * MF -> getSubtarget ( ) . getRegisterInfo ( ) ; const <ISA_LIT>RegisterInfo * ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( & TRI ) ; for ( unsigned Reg : <STR_LIT> ) {

if ( ! ARI -> isReservedReg ( * MF , Reg ) && Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> && C . isAvailableAcrossAndOutOfSeq ( Reg , TRI ) && C . isAvailableInsideSeq ( Reg , TRI ) ) return Reg ;


if ( Opnd2 . isValid ( ) ) Inst . addOperand ( Opnd2 ) ;


<s> bool isMemoryIndexed64SImm7 ( ) const { if ( ! isMem ( ) || Mem . Mode != ImmediateOffset ) return false ; if ( ! Mem . OffsetImm ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Mem . OffsetImm ) ; assert ( CE && <STR_LIT> ) ; int64_t Value = CE -> getValue ( ) ;

return ( ( Value % <NUM_LIT> ) == <NUM_LIT> ) && Value >= - <NUM_LIT> && Value <= <NUM_LIT> ;


<s> if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; int Half = NumElems / <NUM_LIT> ;

for ( int i = <NUM_LIT> ; i < Half ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , NumElems ) ) return false ;


<s> LLVM_DEBUG ( HazardRec -> dumpState ( ) ; ) ; for ( MachineBasicBlock :: iterator I = SinglePredMBB -> getFirstTerminator ( ) ; I != SinglePredMBB -> end ( ) ; I ++ ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ; ) ; bool TakenBranch = ( I -> isBranch ( ) && ( TII -> getBranchInfo ( * I ) . isIndirect ( ) || TII -> getBranchInfo ( * I ) . getMBBTarget ( ) == MBB ) ) ; HazardRec -> emitInstruction ( & * I , TakenBranch ) ; if ( TakenBranch ) break ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ; return MCDisassembler :: Success ;


<s> static MachineInstr * getLoopBreakInstr ( MachineBasicBlock * blk ) { for ( MachineBasicBlock :: iterator iter = blk -> begin ( ) ; ( iter != blk -> end ( ) ) ; ++ iter ) { MachineInstr * instr = & ( * iter ) ; if ( instr -> getOpcode ( ) == AMDGPU :: PREDICATED_BREAK ) { return instr ; } }


<s> StringRef OptStr = Tok . getString ( ) ; if ( OptStr . equals_insensitive ( <STR_LIT> ) ) Opt = <STR_LIT> ; else return MatchOperand_NoMatch ; Parser . Lex ( ) ; } else if ( Tok . is ( AsmToken :: Hash ) || Tok . is ( AsmToken :: Dollar ) || Tok . is ( AsmToken :: Integer ) ) { if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) Parser . Lex ( ) ; SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; const MCExpr * ISBarrierID ; if ( getParser ( ) . parseExpression ( ISBarrierID ) ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ISBarrierID ) ; if ( ! CE ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = CE -> getValue ( ) ; if ( Val & ~ <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Opt = <STR_LIT> + Val ; } else return MatchOperand_ParseFail ; Operands . push_back ( <ISA_LIT>Operand :: CreateInstSyncBarrierOpt ( ( <STR_LIT> ) Opt , S ) ) ;


<s> if ( RVVVectorBitsMax != <NUM_LIT> ) Min = std :: min ( RVVVectorBitsMin , RVVVectorBitsMax ) ;

return PowerOf2Floor ( Min < <NUM_LIT> ? <NUM_LIT> : Min ) ;


<s> Builder . SetInsertPoint ( Trunc ) ; IntegerType * SrcTy = cast < IntegerType > ( Trunc -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; IntegerType * DestTy = cast < IntegerType > ( TruncTysMap [ Trunc ] [ <NUM_LIT> ] ) ; unsigned NumBits = DestTy -> getScalarSizeInBits ( ) ;

ConstantInt * Mask = ConstantInt :: get ( SrcTy , APInt :: getMaxValue ( NumBits ) . getZExtValue ( ) ) ;


<s> const LLT v8s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ;

const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> EVT VecVT = Vec . getValueType ( ) ; unsigned NumElts = VecVT . getVectorNumElements ( ) ; assert ( VecVT . getScalarSizeInBits ( ) == <NUM_LIT> && ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) ) ; DAGCombinerInfo DCI ( DAG , AfterLegalizeVectorOps , true , nullptr ) ; if ( SDValue Combined = performExtractVectorEltCombine ( Op . getNode ( ) , DCI ) ) return Combined ; EVT IntVT = NumElts == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Four = DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) ; SDValue ScaledIdx = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Idx , Four ) ; SDValue BC = DAG . getNode ( <STR_LIT> , SL , IntVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , SL , IntVT , BC , ScaledIdx ) ; if ( ResultVT == <STR_LIT> ) { SDValue Result = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Elt ) ; return DAG . getNode ( <STR_LIT> , SL , ResultVT , Result ) ;


<s> result = gen_rtx_CONST ( Pmode , result ) ; result = ( TARGET_PIC_DATA_TEXT_REL && isFunc ) ? gen_rtx_PLUS ( Pmode , gen_raw_REG ( Pmode , get_base_reg ( op ) ) , result ) : gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , result ) ;

result = ( ! TARGET_PIC_DATA_TEXT_REL ) ? gen_const_mem ( Pmode , result ) : result ;


<s> std :: string sep = <STR_LIT> ; if ( e == static_cast < uint32_t > ( MemoryOperand :: None ) ) return <STR_LIT> ; if ( e == static_cast < uint32_t > ( MemoryOperand :: Volatile ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( MemoryOperand :: Volatile ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( MemoryOperand :: Aligned ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( MemoryOperand :: Aligned ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( MemoryOperand :: Nontemporal ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( MemoryOperand :: Nontemporal ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( MemoryOperand :: MakePointerAvailableKHR ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( MemoryOperand :: MakePointerAvailableKHR ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( MemoryOperand :: MakePointerVisibleKHR ) ) return <STR_LIT> ;

if ( e & static_cast < uint32_t > ( MemoryOperand :: MakePointerVisibleKHR ) ) {


<s> AU . addRequired < TargetLibraryInfo > ( ) ;

FunctionPass :: getAnalysisUsage ( AU ) ;


<s> int64_t Val = Int . getIntVal ( ) ; if ( IsNegative ) Val = - Val ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Int . getLoc ( ) , Int . getEndLoc ( ) , <STR_LIT> { Val } ) ) ;


<s> MCAsmParserExtension :: Initialize ( Parser ) ; MCStreamer & S = getParser ( ) . getStreamer ( ) ; if ( S . getTargetStreamer ( ) == nullptr ) new <ISA_LIT>TargetStreamer ( S ) ;

setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> if ( ! ConstExpr ) return false ; uint64_t Value = ConstExpr -> getValue ( ) ;


<s> return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


return ( getGeneration ( ) >= SOUTHERN_ISLANDS || hasCaymanISA ( ) ) ;


<s> if ( ArgFlags . isSecArgPass ( ) ) { if ( ArgFlags . isHva ( ) ) return CC_<ISA_LIT>_VectorCallAssignRegister ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State ) ; return true ; } if ( ! ( ValVT . isFloatingPoint ( ) || ( ValVT . isVector ( ) && ValVT . getSizeInBits ( ) >= <NUM_LIT> ) ) ) { if ( State . isAllocated ( <STR_LIT> ) ) { ( void ) State . AllocateReg ( CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ) ; } return false ; } if ( ! ArgFlags . isHva ( ) || ArgFlags . isHvaStart ( ) ) { ( void ) State . AllocateReg ( CC_<ISA_LIT>_64_VectorCallGetGPRs ( ) ) ; if ( unsigned Reg = State . AllocateReg ( CC_<ISA_LIT>_VectorCallGetSSEs ( ValVT ) ) ) {

if ( Reg == <STR_LIT> || Reg == <STR_LIT> ) State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ;


<s> SavedVGPRs . clearBitsNotInMask ( TRI -> getAllVGPRRegMask ( ) ) ; const bool WillHaveFP = FrameInfo . hasCalls ( ) && ( SavedVGPRs . any ( ) || ! allStackObjectsAreDead ( FrameInfo ) ) ; for ( auto SSpill : MFI -> getSGPRSpillVGPRs ( ) ) SavedVGPRs . reset ( SSpill . VGPR ) ; const bool HasFP = WillHaveFP || hasFP ( MF ) ; if ( ! HasFP ) return ; if ( MFI -> haveFreeLanesForSGPRSpill ( MF , <NUM_LIT> ) ) { int NewFI = MF . getFrameInfo ( ) . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , true , nullptr , TargetStackID :: SGPRSpill ) ; if ( ! MFI -> allocateSGPRSpillToVGPR ( MF , NewFI ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> raw_string_ostream TempStream ( Name ) ; Symbol -> print ( TempStream , MAI ) ; } LabelToEmit . append ( <STR_LIT> ) ;


<s> return DecodeMem ( Inst , insn , Address , Decoder , false , DecodeI32RegisterClass ) ;


return ( __m512i ) __builtin_ia32_pabsb512_mask ( ( __v64qi ) __A , ( __v64qi ) _mm512_setzero_qi ( ) , ( __mmask64 ) - <NUM_LIT> ) ;


<s> break ; case POST_INC : case PRE_DEC : ok = avr_reg_ok_for_addr_p ( XEXP ( x , <NUM_LIT> ) , ADDR_SPACE_GENERIC , GET_CODE ( x ) , strict ) ; break ; case PLUS : { rtx reg = XEXP ( x , <NUM_LIT> ) ; rtx op1 = XEXP ( x , <NUM_LIT> ) ; if ( REG_P ( reg ) && CONST_INT_P ( op1 ) && INTVAL ( op1 ) >= <NUM_LIT> ) { bool fit = IN_RANGE ( INTVAL ( op1 ) , <NUM_LIT> , MAX_LD_OFFSET ( mode ) ) ; if ( fit ) { ok = ( ! strict || avr_reg_ok_for_addr_p ( reg , ADDR_SPACE_GENERIC , PLUS , strict ) ) ; if ( reg == frame_pointer_rtx || reg == arg_pointer_rtx ) { ok = true ; } } else if ( frame_pointer_needed && reg == frame_pointer_rtx ) { ok = true ; } } } break ; default : break ; } if ( AVR_TINY && CONSTANT_ADDRESS_P ( x ) ) { ok = ( CONST_INT_P ( x ) && IN_RANGE ( INTVAL ( x ) , <NUM_LIT> , <NUM_LIT> - GET_MODE_SIZE ( mode ) ) ) ;


<s> uint32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;

return IsConstantImm && isInt < <NUM_LIT> > ( Imm - <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;