<s> if ( REAL_VALUE_ISINF ( r ) || REAL_VALUE_ISNAN ( r ) || REAL_VALUE_MINUS_ZERO ( r ) ) return - <NUM_LIT> ; sign = REAL_VALUE_NEGATIVE ( r ) ? <NUM_LIT> : <NUM_LIT> ; r = real_value_abs ( & r ) ; exponent = REAL_EXP ( & r ) ; real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * <NUM_LIT> ) ; mantissa = w . elt ( <NUM_LIT> ) ; mant_hi = w . elt ( <NUM_LIT> ) ; if ( mantissa != <NUM_LIT> ) return - <NUM_LIT> ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ;

mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( point_pos - <NUM_LIT> ) ) - <NUM_LIT> ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> if ( Ty == LLT :: scalar ( <NUM_LIT> ) && ! MFI -> getMode ( ) . FP32Denormals ) return true ; if ( Ty == LLT :: scalar ( <NUM_LIT> ) && ! MFI -> getMode ( ) . FP64FP16Denormals ) return true ; MachineIRBuilder HelperBuilder ( MI ) ; GISelObserverWrapper DummyObserver ; LegalizerHelper Helper ( MF , DummyObserver , HelperBuilder ) ; HelperBuilder . setMBB ( * MI . getParent ( ) ) ;

return Helper . lowerFMad ( MI ) == LegalizerHelper :: Legalized ;


<s> MVT Ty = ty ( Val ) ; bool DoCast = ( Ty == <STR_LIT> || Ty == <STR_LIT> || Ty == <STR_LIT> ) ; if ( DoCast ) { SDValue TC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ; SDValue NS = DAG . getStore ( SN -> getChain ( ) , dl , TC , SN -> getBasePtr ( ) , SN -> getMemOperand ( ) ) ; if ( SN -> isIndexed ( ) ) { NS = DAG . getIndexedStore ( NS , dl , SN -> getBasePtr ( ) , SN -> getOffset ( ) , SN -> getAddressingMode ( ) ) ; } SN = cast < StoreSDNode > ( NS . getNode ( ) ) ; } unsigned ClaimAlign = SN -> getAlignment ( ) ; SDValue Ptr = SN -> getBasePtr ( ) ; validateConstPtrAlignment ( Ptr , dl , ClaimAlign ) ; MVT StoreTy = SN -> getMemoryVT ( ) . getSimpleVT ( ) ;

unsigned NeedAlign = Subtarget . getTypeAlignment ( StoreTy ) ;


<s> return new CheriLoopPointerDecanonicalize ( ) ;


<s> DebugLoc DL = Op . getDebugLoc ( ) ; unsigned Reg = <NUM_LIT> ; unsigned size = <NUM_LIT> ; switch ( T . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;

MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ;


<s> MachineBasicBlock * OrigBB = MI -> getParent ( ) ; MachineFunction & MF = * OrigBB -> getParent ( ) ; MachineBasicBlock * NewBB = MF . CreateMachineBasicBlock ( OrigBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = OrigBB ; ++ MBBI ; MF . insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; unsigned Opc = isThumb ? ( isThumb2 ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; BuildMI ( OrigBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( Opc ) ) . addMBB ( NewBB ) ; NumSplit ++ ; while ( ! OrigBB -> succ_empty ( ) ) { MachineBasicBlock * Succ = * OrigBB -> succ_begin ( ) ; OrigBB -> removeSuccessor ( Succ ) ; NewBB -> addSuccessor ( Succ ) ; assert ( ( Succ -> empty ( ) || Succ -> begin ( ) -> getOpcode ( ) != TargetInstrInfo :: PHI ) && <STR_LIT> ) ; } OrigBB -> addSuccessor ( NewBB ) ; MF . RenumberBlocks ( NewBB ) ; BBSizes . insert ( BBSizes . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; BBOffsets . insert ( BBOffsets . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; std :: vector < MachineBasicBlock * > :: iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( next ( IP ) , NewBB ) ; else WaterList . insert ( IP , OrigBB ) ; unsigned NewBBSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = NewBB -> begin ( ) , E = NewBB -> end ( ) ; I != E ; ++ I ) NewBBSize += TII -> GetInstSizeInBytes ( I ) ; unsigned OrigBBI = OrigBB -> getNumber ( ) ; unsigned NewBBI = NewBB -> getNumber ( ) ; BBSizes [ NewBBI ] = NewBBSize ; int delta = isThumb1 ? <NUM_LIT> : <NUM_LIT> ;

BBSizes [ OrigBBI ] -= NewBBSize - delta ;


<s> DefCycle = RegNo ; bool isSLoad = false ; switch ( DefMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isSLoad = true ; break ; } if ( ( isSLoad && ( RegNo % <NUM_LIT> ) ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; } else { DefCycle = RegNo + <NUM_LIT> ;


<s> if ( RetVT != <STR_LIT> ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , RetCC_<ISA_LIT> ) ; if ( RVLocs . size ( ) != <NUM_LIT> ) return false ; MVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ;

if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ;


<s> assert ( Kind == Register && <STR_LIT> ) ;


<s> static bool ix86_ms_bitfield_layout_p ( tree record_type ) { return ( TARGET_MS_BITFIELD_LAYOUT && ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( record_type ) ) ) || lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( record_type ) ) ;


<s> return Error ( Loc , <STR_LIT> ) ; case Match_LogicalSecondSource : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm32Shift : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMovImm64Shift : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift32 : return Error ( Loc , <STR_LIT> ) ; case Match_AddSubRegShift64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidFPImm : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexedSImm9 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16SImm7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryWExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryXExtend128 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed2 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed4 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidMemoryIndexed16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 :


<s> SDValue Op0 , Op1 ; switch ( ConstraintID ) { default : return true ; case InlineAsm :: Constraint_o : case InlineAsm :: Constraint_m : if ( ! SelectADDRrr ( Op , Op0 , Op1 ) ) SelectADDRri ( Op , Op0 , Op1 ) ; break ;


<s> if ( ( INTVAL ( opval ) & ~ ACC_MASK ) != <NUM_LIT> ) { error ( <STR_LIT> ) ; return NULL_RTX ; } reg = gen_rtx_REG ( insn_data [ icode ] . operand [ opnum ] . mode , ACC_FIRST + INTVAL ( opval ) ) ; if ( ! ( * insn_data [ icode ] . operand [ opnum ] . predicate ) ( reg , VOIDmode ) ) SET_REGNO ( reg , ACCG_FIRST + INTVAL ( opval ) ) ; if ( ! ( * insn_data [ icode ] . operand [ opnum ] . predicate ) ( reg , VOIDmode ) ) {

error ( <STR_LIT> , insn_data [ icode ] . name ) ;


<s> int _U_Qfge ( long double a , long double b ) { return ( _U_Qfcmp ( a , b , <NUM_LIT> ) != <NUM_LIT> ) ;


<s> unsigned SubReg ; std :: tie ( SubReg , Offset ) = computeIndirectRegAndOffset ( TRI , VecRC , SrcReg , Offset ) ; bool UseGPRIdxMode = ST . useVGPRIndexMode ( EnableVGPRIndexMode ) ; if ( setM0ToIndexFromSGPR ( TII , MRI , MI , Offset , UseGPRIdxMode , true ) ) { MachineBasicBlock :: iterator I ( & MI ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( UseGPRIdxMode ) { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) ; BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) ; } else { BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( SrcReg , RegState :: Undef , SubReg ) . addReg ( SrcReg , RegState :: Implicit ) ; } MI . eraseFromParent ( ) ; return & MBB ; } const DebugLoc & DL = MI . getDebugLoc ( ) ; MachineBasicBlock :: iterator I ( & MI ) ; Register PhiReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register InitReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: IMPLICIT_DEF ) , InitReg ) ; auto InsPt = loadM0FromVGPR ( TII , MBB , MI , InitReg , PhiReg , Offset , UseGPRIdxMode , true ) ; MachineBasicBlock * LoopBB = InsPt -> getParent ( ) ;


<s> static SDValue PerformZExtCombine ( SDNode * N , SelectionDAG & DAG ) { DebugLoc dl = N -> getDebugLoc ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ;

if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) {


<s> if ( EraseSet . find ( MI ) == EraseSet . end ( ) ) EraseSet . insert ( MI ) ;


<s> Op -> MMask . Val = MMask ; Op -> StartLoc = S ; Op -> EndLoc = S ;


<s> static void rs6000_do_expand_vec_perm ( rtx target , rtx op0 , rtx op1 , machine_mode vmode , const vec_perm_builder & perm ) { rtx x = expand_vec_perm_const ( vmode , op0 , op1 , perm , BLKmode , target ) ;

if ( x != target ) emit_move_insn ( target , x ) ;


<s> if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( IsKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << MF . getName ( ) << '\n' ) ; const auto & MLI = getAnalysis < MachineLoopInfo > ( ) ; auto & MDT = getAnalysis < MachineDominatorTree > ( ) ; const auto & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MF . getRegInfo ( ) . invalidateLiveness ( ) ;

EliminateMultipleEntryLoops ( MF , MLI ) ;


<s> Type * I8 = Type :: getInt8Ty ( Ctx ) ; FunctionType * FnType = FunctionType :: get ( Type :: getVoidTy ( Ctx ) , { Type :: getInt8PtrTy ( Ctx ) , I8 , Arg . getType ( ) } , false ) ; Constant * Fn = F . getParent ( ) -> getOrInsertFunction ( GetArgumentSymbolName ( Arg ) , FnType ) ; Value * ArgName = CreateStringPtr ( BB , Arg . getName ( ) ) ; Value * Args [ ] = { ArgName , ConstantInt :: get ( I8 , Arg . getArgNo ( ) ) , & Arg } ; CallInst :: Create ( Fn , Args , <STR_LIT> , & BB ) ;


<s> ( * I ) -> NodeQueueId &= ~ QSrc -> getID ( ) ; AluKind AK = getAluKind ( * I ) ;


<s> MI . addOperand ( MCOperand :: createImm ( imm ) ) ; return MCDisassembler :: Success ;


<s> } else if ( ! TARGET_64BIT && smode == DImode ) { if ( TARGET_SSE4_1 ) { emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_sse4_1_pinsrd ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ) ; } else { rtx tmp = gen_reg_rtx ( DImode ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_vec_interleave_lowv4si ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) ) ) ; } } else emit_insn ( gen_rtx_SET ( gen_rtx_SUBREG ( vmode , vreg , <NUM_LIT> ) , gen_gpr_to_xmm_move_src ( vmode , reg ) ) ) ;


<s> static unsigned char csky_class_max_nregs ( reg_class_t rclass , machine_mode mode ) { if ( rclass == V_REGS ) return <NUM_LIT> ;


<s> bool IsModified = false ; do { IsModified = false ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ++ I ) { SDNode * Node = I ; MachineSDNode * MachineNode = dyn_cast < MachineSDNode > ( I ) ; if ( ! MachineNode ) continue ; SDNode * ResNode = Lowering . PostISelFolding ( MachineNode , * CurDAG ) ;


<s> emit_label ( label ) ; label = gen_rtx_LABEL_REF ( VOIDmode , label ) ; if ( before == NULL_RTX ) before = gen_reg_rtx ( mode ) ; if ( after == NULL_RTX ) after = gen_reg_rtx ( mode ) ; emit_insn ( gen_arc_load_exclusivesi ( before , mem ) ) ; switch ( code ) { case NOT : x = gen_rtx_AND ( mode , before , val ) ; emit_insn ( gen_rtx_SET ( after , x ) ) ; x = gen_rtx_NOT ( mode , after ) ; emit_insn ( gen_rtx_SET ( after , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( val ) ) { val = GEN_INT ( - INTVAL ( val ) ) ; code = PLUS ; } default : x = gen_rtx_fmt_ee ( code , mode , before , val ) ; emit_insn ( gen_rtx_SET ( after , x ) ) ; break ; } emit_insn ( gen_arc_store_exclusivesi ( mem , after ) ) ; cond = gen_rtx_REG ( CC_Zmode , CC_REG ) ; x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , label , pc_rtx ) ; emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ;


<s> bool <ISA_LIT>TypeRewriter :: runOnFunction ( Function & F ) { if ( <STR_LIT> ( F ) == ShaderType :: COMPUTE ) return false ; visit ( F ) ; visit ( F ) ;


<s> if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ;

return IntWidth == <NUM_LIT> || IntWidth == <NUM_LIT> ;


<s> static bool isNarrowLoad ( MachineInstr & MI ) {

return isNarrowLoad ( MI . getOpcode ( ) ) ;


<s> if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= <NUM_LIT> * BITS_PER_WORD ) return true ;

return default_scalar_mode_supported_p ( mode ) ;


<s> MachineBasicBlock * <ISA_LIT>MachineCFGStructurizer :: getLoopLandInfo ( MachineLoop * LoopRep ) const {

LoopLandInfoMap :: const_iterator It = LLInfoMap . find ( LoopRep ) ;


<s> const MCInstrDesc & MCID = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) ; unsigned PredReg = <STR_LIT> ; bool isTrue = false ; for ( unsigned i = MCID . getNumDefs ( ) ; i < MCID . getNumOperands ( ) ; ++ i ) if ( MCI . getOperand ( i ) . isReg ( ) ) initReg ( MCI , MCI . getOperand ( i ) . getReg ( ) , PredReg , isTrue ) ; for ( unsigned i = <NUM_LIT> ; i < MCID . getNumImplicitUses ( ) ; ++ i ) initReg ( MCI , MCID . getImplicitUses ( ) [ i ] , PredReg , isTrue ) ; if ( const MCPhysReg * ImpDef = MCID . getImplicitDefs ( ) ) for ( ; * ImpDef ; ++ ImpDef ) { unsigned R = * ImpDef ; if ( <STR_LIT> != R && MCID . isCall ( ) ) continue ; if ( <STR_LIT> == R ) continue ; if ( <STR_LIT> == R ) SoftDefs . insert ( R ) ; else if ( isPredicateRegister ( R ) && <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) ) LatePreds . insert ( R ) ; else Defs [ R ] . insert ( PredSense ( PredReg , isTrue ) ) ; } for ( unsigned i = <NUM_LIT> ; i < MCID . getNumDefs ( ) ; ++ i ) { unsigned R = MCI . getOperand ( i ) . getReg ( ) , S = <STR_LIT> ; if ( R == <STR_LIT> ) R = <STR_LIT> ; for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ; SRI . isValid ( ) ; ++ SRI ) { if ( MCSubRegIterator ( * SRI , & RI ) . isValid ( ) ) continue ; if ( R == * SRI ) { if ( S == R ) continue ; else S = R ; } if ( <STR_LIT> != R && <STR_LIT> == * SRI ) SoftDefs . insert ( * SRI ) ; else if ( <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) && isPredicateRegister ( * SRI ) ) LatePreds . insert ( * SRI ) ; else if ( i == <NUM_LIT> && <ISA_LIT>MCInstrInfo :: getType ( MCII , MCI ) == <STR_LIT> ) TmpDefs . insert ( * SRI ) ; else if ( i <= <NUM_LIT> && <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , MCI ) ) Uses . insert ( * SRI ) ; else Defs [ * SRI ] . insert ( PredSense ( PredReg , isTrue ) ) ; } }

if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) for ( unsigned i = MCID . getNumDefs ( ) ; i < MCID . getNumOperands ( ) ; ++ i ) if ( MCI . getOperand ( i ) . isReg ( ) ) {


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & subtarget , const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , Subtarget ( subtarget ) , TII ( tii ) {


<s> case AtomicRMWInst :: Add : case AtomicRMWInst :: Sub : case AtomicRMWInst :: And : case AtomicRMWInst :: Or : case AtomicRMWInst :: Xor : case AtomicRMWInst :: Max : case AtomicRMWInst :: Min : case AtomicRMWInst :: UMax : case AtomicRMWInst :: UMin : break ; } const unsigned PtrIdx = <NUM_LIT> ; const unsigned ValIdx = <NUM_LIT> ; if ( DA -> isDivergentUse ( & I . getOperandUse ( PtrIdx ) ) ) { return ; } const bool ValDivergent = DA -> isDivergentUse ( & I . getOperandUse ( ValIdx ) ) ; if ( ValDivergent && ( ! HasDPP || ( DL -> getTypeSizeInBits ( I . getType ( ) ) != <NUM_LIT> ) ) ) { return ;


<s> if ( inline_secondary_memory_needed ( mode , class1 , class2 , false ) ) { int cost = <NUM_LIT> ; cost += inline_memory_move_cost ( mode , class1 , <NUM_LIT> ) ; cost += inline_memory_move_cost ( mode , class2 , <NUM_LIT> ) ; if ( GET_MODE_BITSIZE ( mode ) > BITS_PER_WORD && TARGET_MEMORY_MISMATCH_STALL && targetm . class_max_nregs ( class1 , mode ) > targetm . class_max_nregs ( class2 , mode ) ) cost += <NUM_LIT> ; if ( ( MMX_CLASS_P ( class1 ) && MAYBE_FLOAT_CLASS_P ( class2 ) ) || ( MMX_CLASS_P ( class2 ) && MAYBE_FLOAT_CLASS_P ( class1 ) ) ) cost += <NUM_LIT> ; return cost ; } if ( MMX_CLASS_P ( class1 ) != MMX_CLASS_P ( class2 ) || SSE_CLASS_P ( class1 ) != SSE_CLASS_P ( class2 ) ) return MAX ( <NUM_LIT> , MMX_CLASS_P ( class1 ) || MMX_CLASS_P ( class2 ) ? ix86_cost -> mmxsse_to_integer : ix86_cost -> ssemmx_to_integer ) ; if ( MAYBE_FLOAT_CLASS_P ( class1 ) ) return ix86_cost -> fp_move ;


<s> while ( ! Queue . empty ( ) ) { SDNode * ChainNext = Queue . pop_back_val ( ) ; if ( ! Visited . insert ( ChainNext ) . second ) continue ; if ( MemSDNode * ChainLD = dyn_cast < MemSDNode > ( ChainNext ) ) { if ( isConsecutiveLS ( ChainLD , LD , VT . getStoreSize ( ) , <NUM_LIT> , DAG ) ) return true ; if ( ! Visited . count ( ChainLD -> getChain ( ) . getNode ( ) ) ) Queue . push_back ( ChainLD -> getChain ( ) . getNode ( ) ) ; } else if ( ChainNext -> getOpcode ( ) == <STR_LIT> ) { for ( const SDUse & O : ChainNext -> ops ( ) ) if ( ! Visited . count ( O . getNode ( ) ) ) Queue . push_back ( O . getNode ( ) ) ;

} else LoadRoots . insert ( ChainNext ) ;


<s> else gcc_unreachable ( ) ; fuse_ops [ <NUM_LIT> ] = XVECEXP ( offset , <NUM_LIT> , <NUM_LIT> ) ; output_asm_insn ( insn_template , fuse_ops ) ; } else if ( GET_CODE ( offset ) == PLUS && GET_CODE ( XEXP ( offset , <NUM_LIT> ) ) == UNSPEC && XINT ( XEXP ( offset , <NUM_LIT> ) , <NUM_LIT> ) == UNSPEC_TOCREL && CONST_INT_P ( XEXP ( offset , <NUM_LIT> ) ) ) { rtx tocrel_unspec = XEXP ( offset , <NUM_LIT> ) ; if ( TARGET_ELF ) sprintf ( insn_template , <STR_LIT> , insn_str ) ; else if ( TARGET_XCOFF ) sprintf ( insn_template , <STR_LIT> , insn_str ) ; else gcc_unreachable ( ) ; fuse_ops [ <NUM_LIT> ] = XVECEXP ( tocrel_unspec , <NUM_LIT> , <NUM_LIT> ) ; fuse_ops [ <NUM_LIT> ] = XEXP ( offset , <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const {


<s> return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> const AsmToken & lexDefinite ( ) { return getLexer ( ) -> Lex ( ) ;


<s> if ( PrevNode ) { changeExit ( PrevNode , Node -> getEntry ( ) , true ) ; } PrevNode = Node ; } else { BasicBlock * Flow = needPrefix ( false ) ; BasicBlock * Entry = Node -> getEntry ( ) ; BasicBlock * Next = needPostfix ( Flow , ExitUseAllowed ) ; Conditions . push_back ( BranchInst :: Create ( Entry , Next , BoolUndef , Flow ) ) ; addPhiValues ( Flow , Entry ) ; DT -> changeImmediateDominator ( Entry , Flow ) ; PrevNode = Node ;

while ( ! Order . empty ( ) && ! Visited . count ( LoopEnd ) && dominatesPredicates ( Entry , Order . back ( ) ) ) {


<s> ( defined ( __ppc__ ) || defined ( __powerpc__ ) ) if ( CPUName == <STR_LIT> ) CPUName = sys :: getHostCPUName ( ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; std :: string FullFS = FS ; if ( Is<ISA_LIT>64 ) { Has64BitSupport = true ; Use64BitRegs = true ; if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; } if ( OptLevel >= CodeGenOpt :: Default ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ; else FullFS = <STR_LIT> ; }

ParseSubtargetFeatures ( CPUName , FullFS ) ;


<s> else return false ; if ( Register Reg = State . AllocateReg ( RegList ) ) State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; else return false ;


<s> SDLoc dl ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; SDValue MLAOp1 ; SDValue MLAOp2 ; int LaneIdx = - <NUM_LIT> ; if ( Op1 . getOpcode ( ) != <STR_LIT> || ! checkV64LaneV128 ( Op1 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) , MLAOp1 , MLAOp2 , LaneIdx ) ) { std :: swap ( Op0 , Op1 ) ; if ( Op1 . getOpcode ( ) != <STR_LIT> || ! checkV64LaneV128 ( Op1 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) , MLAOp1 , MLAOp2 , LaneIdx ) ) return nullptr ; } SDValue LaneIdxVal = CurDAG -> getTargetConstant ( LaneIdx , dl , <STR_LIT> ) ; SDValue Ops [ ] = { Op0 , MLAOp1 , MLAOp2 , LaneIdxVal } ; unsigned MLAOpc = ~ <NUM_LIT> ; switch ( N -> getSimpleValueType ( <NUM_LIT> ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : MLAOpc = <STR_LIT> ; break ; case <STR_LIT> : MLAOpc = <STR_LIT> ; break ;


<s> if ( unsigned Reg = MI . getOperand ( SegOperand ) . getReg ( ) ) emitByte ( <STR_LIT> ( Reg ) , CurByte , OS ) ;


<s> return ( struct bpf_sock * ) __builtin_bpf_helper_sk_lookup_udp ( ctx , ( void * ) tuple , size , netns_id , flags ) ;


<s> if ( <ISA_LIT>ArchVersion == <ISA_LIT>Default ) <ISA_LIT>ArchVersion = <ISA_LIT>32 ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>1 ) report_fatal_error ( <STR_LIT> , false ) ; if ( <ISA_LIT>ArchVersion == <ISA_LIT>5 ) report_fatal_error ( <STR_LIT> , false ) ; assert ( ( ( ! isGP64bit ( ) && isABI_O32 ( ) ) || ( isGP64bit ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ; if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>64r6 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( UseIndirectJumpsHazard ) { if ( InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> ) ; if ( ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> ) ; } if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } if ( hasMSA ( ) && ! MSAWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r5 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; MSAWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r5 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; MSAWarningPrinted = true ; } } CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ;

Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this ) ) ;


<s> void <ISA_LIT>FrameLowering :: findShrunkPrologEpilog ( MachineFunction & MF , MachineBasicBlock * & PrologB , MachineBasicBlock * & EpilogB ) const { static unsigned ShrinkCounter = <NUM_LIT> ; if ( ShrinkLimit . getPosition ( ) ) { if ( ShrinkCounter >= ShrinkLimit ) return ; ShrinkCounter ++ ; } auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MachineDominatorTree MDT ; MDT . runOnMachineFunction ( MF ) ; MachinePostDominatorTree MPT ; MPT . runOnMachineFunction ( MF ) ; using UnsignedMap = DenseMap < unsigned , unsigned > ; using RPOTType = ReversePostOrderTraversal < const MachineFunction * > ; UnsignedMap RPO ; RPOTType RPOT ( & MF ) ; unsigned RPON = <NUM_LIT> ; for ( RPOTType :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) RPO [ ( * I ) -> getNumber ( ) ] = RPON ++ ; for ( auto & I : MF ) {

unsigned BN = RPO [ I . getNumber ( ) ] ;


<s> return _mm_set_epi16 ( * ( short * ) __P , ( short ) <NUM_LIT> , ( short ) <NUM_LIT> , ( short ) <NUM_LIT> , ( short ) <NUM_LIT> , ( short ) <NUM_LIT> , ( short ) <NUM_LIT> , ( short ) <NUM_LIT> ) ;


<s> StringRef getPassName ( ) const override {


<s> const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ; unsigned Opc ; const TargetRegisterClass * RC ; switch ( MI -> getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = BB ; ++ I ; MachineBasicBlock * LoopBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * RemBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , LoopBB ) ; F -> insert ( I , RemBB ) ; RemBB -> splice ( RemBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ;


<s> if ( count <= <NUM_LIT> ) { error ( <STR_LIT> , count ) ; return NULL ; } gcc_assert ( GET_CODE ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) == SET ) ; gcc_assert ( GET_CODE ( SET_SRC ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) ) == PLUS ) ; gcc_assert ( GET_CODE ( XEXP ( SET_SRC ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) , <NUM_LIT> ) ) == REG ) ; gcc_assert ( GET_CODE ( XEXP ( SET_SRC ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) , <NUM_LIT> ) ) == CONST_INT ) ; stack_bytes = INTVAL ( XEXP ( SET_SRC ( XVECEXP ( op , <NUM_LIT> , <NUM_LIT> ) ) , <NUM_LIT> ) ) ; stack_bytes += ( count - ( TARGET_LONG_CALLS ? <NUM_LIT> : <NUM_LIT> ) ) * <NUM_LIT> ; if ( stack_bytes != <NUM_LIT> && stack_bytes != - <NUM_LIT> ) { error ( <STR_LIT> , stack_bytes ) ; return NULL ; } mask = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < count - ( TARGET_LONG_CALLS ? <NUM_LIT> : <NUM_LIT> ) ; i ++ ) { rtx vector_element = XVECEXP ( op , <NUM_LIT> , i ) ; gcc_assert ( GET_CODE ( vector_element ) == SET ) ; gcc_assert ( GET_CODE ( SET_SRC ( vector_element ) ) == REG ) ; gcc_assert ( register_is_ok_for_epilogue ( SET_SRC ( vector_element ) , SImode ) ) ; mask |= <NUM_LIT> << REGNO ( SET_SRC ( vector_element ) ) ; } for ( first = <NUM_LIT> ; first < <NUM_LIT> ; first ++ ) { if ( mask & ( <NUM_LIT> << first ) ) break ; } gcc_assert ( first < <NUM_LIT> ) ; if ( mask & ( <NUM_LIT> << LINK_POINTER_REGNUM ) ) { gcc_assert ( stack_bytes == - <NUM_LIT> ) ; last = LINK_POINTER_REGNUM ; } else { gcc_assert ( ! stack_bytes ) ;

gcc_assert ( mask & ( <NUM_LIT> << <NUM_LIT> ) ) ;


<s> ++ NumDefCFAOffsets ; break ; } case MCCFIInstruction :: OpOffset : { if ( SavedRegIdx == CU_NUM_SAVED_REGS ) return CU :: UNWIND_MODE_DWARF ; unsigned Reg = MRI . getLLVMRegNum ( Inst . getRegister ( ) , true ) ; SavedRegs [ SavedRegIdx ++ ] = Reg ; StackAdjust += OffsetSize ; InstrOffset += PushInstrSize ( Reg ) ; break ; } } } StackAdjust /= StackDivide ; if ( HasFP ) { if ( ( StackAdjust & <NUM_LIT> ) != StackAdjust ) return CU :: UNWIND_MODE_DWARF ; uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame ( ) ; if ( RegEnc == ~ <NUM_LIT> ) return CU :: UNWIND_MODE_DWARF ; CompactUnwindEncoding |= CU :: UNWIND_MODE_BP_FRAME ; CompactUnwindEncoding |= ( StackAdjust & <NUM_LIT> ) << <NUM_LIT> ; CompactUnwindEncoding |= RegEnc & CU :: UNWIND_BP_FRAME_REGISTERS ; } else { SubtractInstrIdx += InstrOffset ; ++ StackAdjust ; if ( ( StackSize & <NUM_LIT> ) == StackSize ) { CompactUnwindEncoding |= CU :: UNWIND_MODE_STACK_IMMD ; CompactUnwindEncoding |= ( StackSize & <NUM_LIT> ) << <NUM_LIT> ; } else { if ( ( StackAdjust & <NUM_LIT> ) != StackAdjust ) return CU :: UNWIND_MODE_DWARF ; CompactUnwindEncoding |= CU :: UNWIND_MODE_STACK_IND ; CompactUnwindEncoding |= ( SubtractInstrIdx & <NUM_LIT> ) << <NUM_LIT> ; CompactUnwindEncoding |= ( StackAdjust & <NUM_LIT> ) << <NUM_LIT> ;


<s> for ( auto & MO : I . operands ( ) ) { if ( CheckDef && MO . isRegMask ( ) && MO . clobbersPhysReg ( DepReg ) ) return true ; if ( ! MO . isReg ( ) || MO . getReg ( ) != DepReg || ! MO . isImplicit ( ) ) continue ; if ( CheckDef == MO . isDef ( ) ) return true ; }


<s> if ( I . getFlag ( MachineInstr :: MIFlag :: FmArcp ) ) flags |= FPFastMathMode :: AllowRecip ; if ( I . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) ) flags |= FPFastMathMode :: Fast ;


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) {


<s> Subtarget = const_cast < <ISA_LIT>Subtarget * > ( getSubtargetImpl ( * MF -> getFunction ( ) ) ) ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __blsic_u64 ( unsigned long long __X ) {


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override {

return & InstrInfo . getRegisterInfo ( ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const { return <ISA_LIT>CSR_RegMask ;


<s> if ( x ) { int pred_val = XINT ( x , <NUM_LIT> ) ; return pred_val >= REG_BR_PROB_BASE / <NUM_LIT> ;


<s> if ( VT . isVector ( ) ) return false ; return Subtarget . hasStdExtZbb ( ) && ! isa < ConstantSDNode > ( Y ) ;


<s> return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> return lowerV8F64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16F32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I64Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I32Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV32I16Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV64I8Shuffle ( DL , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ; default :


<s> if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) return <NUM_LIT> ; if ( ARITHMETIC_P ( XEXP ( x , <NUM_LIT> ) ) || ARITHMETIC_P ( XEXP ( x , <NUM_LIT> ) ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> } else { SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ImmOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; VOffset = Offset ; } return true ;


<s> static bool get<ISA_LIT>LoadDeprecationInfo ( MCInst & MI , MCSubtargetInfo & STI , std :: string & Info ) { assert ( ! STI . getFeatureBits ( ) [ llvm :: <STR_LIT> ] && <STR_LIT> ) ; assert ( MI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; bool ListContainsPC = false , ListContainsLR = false ; for ( unsigned OI = <NUM_LIT> , OE = MI . getNumOperands ( ) ; OI < OE ; ++ OI ) {

assert ( MI . getOperand ( OI ) . isReg ( ) && <STR_LIT> ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( CE && <STR_LIT> ) ; int32_t Val = CE -> getValue ( ) ; <STR_LIT> AddSub = Val < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; if ( Val == std :: numeric_limits < int32_t > :: min ( ) ) Val = <NUM_LIT> ; if ( Val < <NUM_LIT> ) Val = - Val ; Val = <STR_LIT> ( AddSub , Val , <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ;


<s> else x = gen_pop_h8300hs_normal ( reg ) ; x = emit_insn ( x ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR16List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; }


<s> if ( GET_CODE ( op ) != MEM ) return <NUM_LIT> ; op = XEXP ( op , <NUM_LIT> ) ; switch ( GET_CODE ( op ) ) { case REG : return <NUM_LIT> ; case PLUS : { rtx op0 = XEXP ( op , <NUM_LIT> ) ; rtx op1 = XEXP ( op , <NUM_LIT> ) ; if ( ! REG_P ( op0 ) ) return <NUM_LIT> ; if ( REG_P ( op1 ) ) return <NUM_LIT> ; if ( GET_CODE ( op1 ) != CONST_INT ) return <NUM_LIT> ;

if ( mode == HImode || mode == HFmode ) return IS_DISP8_OFF_CONST ( INTVAL ( op1 ) ) ;


emit_insn ( gen_subhi3 ( xval , virtual_stack_vars_rtx , gen_int_mode ( STARTING_FRAME_OFFSET , Pmode ) ) ) ;


<s> if ( Op == <STR_LIT> && ImmVal == <NUM_LIT> ) return true ; return false ;


<s> if ( ! isTailCall && Subtarget . isSVR4ABI ( ) && Subtarget . is<ISA_LIT>64 ( ) ) { if ( CallOpc == <STR_LIT> ) { needsTOCRestore = true ; } else if ( ( CallOpc == <STR_LIT> ) && ( ! isLocalCall ( Callee ) || DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ) { CallOpc = <STR_LIT> ; } else if ( CallOpc == <STR_LIT> ) CallOpc = <STR_LIT> ; } Chain = DAG . getNode ( CallOpc , dl , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; if ( needsTOCRestore ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = <ISA_LIT>FrameLowering :: getTOCSaveOffset ( isELFv2ABI ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , TOCOff ) ; Chain = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , AddTOC , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> unsigned getWavesPerWorkGroup ( unsigned FlatWorkGroupSize ) const {

return alignTo ( FlatWorkGroupSize , getWavefrontSize ( ) ) / getWavefrontSize ( ) ;


<s> rtx loc , a0 ; rtx_insn * insn ; rtx tmp = gen_reg_rtx ( Pmode ) ; a0 = gen_rtx_REG ( Pmode , GP_ARG_FIRST ) ; if ( ! loongarch_tls_symbol ) loongarch_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; loc = loongarch_unspec_address ( sym , type ) ; start_sequence ( ) ; if ( TARGET_EXPLICIT_RELOCS ) { rtx high = gen_rtx_HIGH ( Pmode , copy_rtx ( loc ) ) ; high = loongarch_force_temporary ( tmp , high ) ; if ( TARGET_CMODEL_EXTREME ) { gcc_assert ( TARGET_EXPLICIT_RELOCS ) ; rtx tmp1 = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_tls_low ( Pmode , tmp1 , gen_rtx_REG ( Pmode , <NUM_LIT> ) , loc ) ) ; emit_insn ( gen_lui_h_lo20 ( tmp1 , tmp1 , loc ) ) ; emit_insn ( gen_lui_h_hi12 ( tmp1 , tmp1 , loc ) ) ; emit_move_insn ( a0 , gen_rtx_PLUS ( Pmode , high , tmp1 ) ) ; } else emit_insn ( gen_tls_low ( Pmode , a0 , high , loc ) ) ; } else { if ( type == SYMBOL_TLSLDM ) emit_insn ( loongarch_got_load_tls_ld ( a0 , loc ) ) ; else if ( type == SYMBOL_TLSGD ) emit_insn ( loongarch_got_load_tls_gd ( a0 , loc ) ) ; else gcc_unreachable ( ) ; } if ( flag_plt ) { switch ( la_opt_cmodel ) { case CMODEL_NORMAL : insn = emit_call_insn ( gen_call_value_internal ( v0 , loongarch_tls_symbol , const0_rtx ) ) ; break ; case CMODEL_MEDIUM : { rtx reg = gen_reg_rtx ( Pmode ) ; if ( TARGET_EXPLICIT_RELOCS ) { emit_insn ( gen_pcalau12i ( Pmode , reg , loongarch_tls_symbol ) ) ; rtx call = gen_call_value_internal_1 ( Pmode , v0 , reg , loongarch_tls_symbol , const0_rtx ) ; insn = emit_call_insn ( call ) ; } else { emit_move_insn ( reg , loongarch_tls_symbol ) ; insn = emit_call_insn ( gen_call_value_internal ( v0 , reg , const0_rtx ) ) ; } break ; } case CMODEL_EXTREME : case CMODEL_LARGE : case CMODEL_TINY : case CMODEL_TINY_STATIC : default : gcc_unreachable ( ) ; } } else { rtx dest = gen_reg_rtx ( Pmode ) ; switch ( la_opt_cmodel ) { case CMODEL_NORMAL : case CMODEL_MEDIUM : { if ( TARGET_EXPLICIT_RELOCS ) { rtx high = gen_reg_rtx ( Pmode ) ; loongarch_emit_move ( high , gen_rtx_HIGH ( Pmode , loongarch_tls_symbol ) ) ; emit_insn ( gen_ld_from_got ( Pmode , dest , high , loongarch_tls_symbol ) ) ; } else loongarch_emit_move ( dest , loongarch_tls_symbol ) ; break ; } case CMODEL_EXTREME : { gcc_assert ( TARGET_EXPLICIT_RELOCS ) ; rtx tmp1 = gen_reg_rtx ( Pmode ) ; rtx high = gen_reg_rtx ( Pmode ) ; loongarch_emit_move ( high , gen_rtx_HIGH ( Pmode , loongarch_tls_symbol ) ) ;

loongarch_emit_move ( tmp1 , gen_rtx_LO_SUM ( Pmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) , loongarch_tls_symbol ) ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {


return ( uint8x8_t ) __builtin_neon_vreinterpretv8qiv2si ( __a ) ;


<s> vec_int4 c , d ; vec_int4 sign1 , sign2 , sign3 ; vec_int4 carry , sum_l , sum_h , sat , sat_val ; sign1 = spu_rlmaska ( a , - <NUM_LIT> ) ; sign2 = spu_rlmaska ( b , - <NUM_LIT> ) ; c = spu_rlqwbyte ( a , - <NUM_LIT> ) ; sign3 = spu_rlqwbyte ( sign1 , - <NUM_LIT> ) ; carry = spu_genc ( a , b ) ; sum_l = spu_add ( a , b ) ; sum_h = spu_addx ( sign1 , sign2 , carry ) ; carry = spu_genc ( sum_l , c ) ; sum_l = spu_add ( sum_l , c ) ; sum_h = spu_addx ( sum_h , sign3 , carry ) ; sign1 = spu_rlmaska ( sum_l , - <NUM_LIT> ) ; sign2 = spu_rlmaska ( sum_h , - <NUM_LIT> ) ; sat_val = spu_xor ( sign2 , spu_splats ( ( signed int ) <NUM_LIT> ) ) ; sat = spu_orc ( spu_xor ( sign1 , sign2 ) , ( vec_int4 ) spu_cmpeq ( sum_h , sign2 ) ) ;

d = spu_and ( spu_sel ( sum_l , sat_val , ( vec_uint4 ) ( sat ) ) , ( vec_int4 ) { <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> } ) ;


<s> switch ( LEAOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ;


<s> if ( packet_group -> num_insns > <NUM_LIT> ) qsort ( packet_group -> sorted , packet_group -> num_insns , sizeof ( rtx ) , frv_compare_insns ) ; if ( group == GROUP_B || group == GROUP_C ) return ; dfa_size = state_size ( ) ; state = alloca ( dfa_size ) ; test_state = alloca ( dfa_size ) ; state_reset ( test_state ) ; for ( first = <NUM_LIT> ; first < packet_group -> num_insns ; first ++ ) { memcpy ( state , test_state , dfa_size ) ; if ( state_transition ( test_state , packet_group -> sorted [ first ] ) >= <NUM_LIT> || ! cpu_unit_reservation_p ( test_state , NTH_UNIT ( group , first ) ) ) break ; } if ( first == packet_group -> num_insns ) return ; for ( nop = <NUM_LIT> ; nop < frv_num_nops ; nop ++ ) { max_unit = frv_insn_unit ( frv_nops [ nop ] ) ; if ( frv_unit_groups [ max_unit ] == group ) { packet_group -> nop = frv_nops [ nop ] ; num_slots = UNIT_NUMBER ( max_unit ) + <NUM_LIT> ; for ( i = packet_group -> num_insns ; i < num_slots ; i ++ ) packet_group -> sorted [ i ] = frv_nops [ nop ] ; if ( frv_sort_insn_group_1 ( group , first , num_slots , ( <NUM_LIT> << first ) - <NUM_LIT> , num_slots , state ) ) return ;


<s> for ( unsigned i = <NUM_LIT> ; i < II -> getNumOperands ( ) ; ++ i ) { if ( II -> getOperand ( i ) . isReg ( ) && ( II -> getOperand ( i ) . isUse ( ) || II -> getOperand ( i ) . isDef ( ) ) ) { MachineBasicBlock :: iterator localII = II ; ++ localII ; unsigned Reg = II -> getOperand ( i ) . getReg ( ) ; for ( MachineBasicBlock :: iterator localBegin = localII ; localBegin != end ; ++ localBegin ) { if ( localBegin == skip ) continue ; if ( localBegin -> modifiesRegister ( Reg , TRI ) || localBegin -> readsRegister ( Reg , TRI ) ) return false ; } }


<s> bool Changed = false ; for ( auto & MBB : F ) Changed |= processBlock ( MBB ) ; return Changed ;


<s> if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ;

auto Ptr = AI -> getPointerOperand ( ) ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } } return <NUM_LIT> ;


<s> return ( poly64x2_t ) __builtin_neon_vdup_nv2di ( ( __builtin_neon_di ) __a ) ;


<s> } if ( global_options_set . x_rs6000_tune_index ) { fprintf ( file , <STR_LIT> , start , processor_target_table [ rs6000_tune_index ] . name ) ; start = <STR_LIT> ; } if ( PPC405_ERRATUM77 ) { fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; } switch ( rs6000_sdata ) { case SDATA_NONE : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_DATA : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_SYSV : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; case SDATA_EABI : fprintf ( file , <STR_LIT> , start ) ; start = <STR_LIT> ; break ; } if ( rs6000_sdata && g_switch_value ) { fprintf ( file , <STR_LIT> , start , g_switch_value ) ; start = <STR_LIT> ; } if ( * start == '\0' ) putc ( '\n' , file ) ; } if ( ! ( rs6000_default_cpu && rs6000_default_cpu [ <NUM_LIT> ] ) && ! global_options_set . x_rs6000_cpu_index ) { fputs ( <STR_LIT> , asm_out_file ) ; if ( ( rs6000_isa_flags & OPTION_MASK_MODULO ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_POPCNTD ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ; else if ( ( rs6000_isa_flags & OPTION_MASK_CMPB ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ;

else if ( ( rs6000_isa_flags & OPTION_MASK_POPCNTB ) != <NUM_LIT> ) fputs ( <STR_LIT> , asm_out_file ) ;


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O << <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } return false ;


<s> if ( ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) && Subtarget -> hasAtomicFaddInsts ( ) ) { if ( RMW -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) != <STR_LIT> ) return AtomicExpansionKind :: CmpXChg ; if ( Subtarget -> hasGFX90AInsts ( ) ) { if ( Ty -> isFloatTy ( ) && AS == <ISA_LIT>AS :: FLAT_ADDRESS ) return AtomicExpansionKind :: CmpXChg ; auto S<ISA_LIT>D = RMW -> getSyncScopeID ( ) ; if ( S<ISA_LIT>D == SyncScope :: System || S<ISA_LIT>D == RMW -> getContext ( ) . getOrInsertSyncScopeID ( <STR_LIT> ) ) return AtomicExpansionKind :: CmpXChg ; return ReportUnsafeHWInst ( AtomicExpansionKind :: None ) ; } if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS ) return AtomicExpansionKind :: CmpXChg ; return RMW -> use_empty ( ) ? ReportUnsafeHWInst ( AtomicExpansionKind :: None ) : AtomicExpansionKind :: CmpXChg ; } if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS && Subtarget -> hasLDSFPAtomicAdd ( ) ) { if ( ! Ty -> isDoubleTy ( ) ) return AtomicExpansionKind :: None ; if ( fpModeMatchesGlobalFPAtomicMode ( RMW ) ) return AtomicExpansionKind :: None ; return RMW -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ? ReportUnsafeHWInst ( AtomicExpansionKind :: None ) : AtomicExpansionKind :: CmpXChg ; } return AtomicExpansionKind :: CmpXChg ;


<s> <STR_LIT> ) ; } else { if ( STI . hasFP<ISA_LIT>v8 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( STI . hasVFP4 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( STI . hasVFP3 ( ) ) ATS . emitFPU ( STI . hasD16 ( ) ? <STR_LIT> : <STR_LIT> ) ; else if ( STI . hasVFP2 ( ) ) ATS . emitFPU ( <STR_LIT> ) ; } if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( ! TM . Options . UnsafeFPMath ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( TM . Options . HonorSignDependentRoundingFPMathOption ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else { if ( ! STI . hasVFP2 ( ) ) { if ( STI . hasV7Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( STI . hasVFP3 ( ) ) { ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; } } if ( TM . Options . NoInfsFPMath && TM . Options . NoNaNsFPMath ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . allowsUnalignedMem ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; else ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <NUM_LIT> ) ; if ( STI . isFPOnlySP ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . isAAPCS_ABI ( ) && TM . Options . FloatABIType == FloatABI :: Hard ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasFP16 ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasMPExtension ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( STI . hasDivideIn<ISA_LIT>Mode ( ) && ! STI . hasV8Ops ( ) ) ATS . emitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( MMI ) { if ( const Module * SourceModule = MMI -> getModule ( ) ) {

if ( auto WCharWidthValue = mdconst :: extract_or_null < ConstantInt > ( SourceModule -> getModuleFlag ( <STR_LIT> ) ) ) {


<s> unsigned SubRegs = VRC -> getSize ( ) / <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , SGPR ) . addReg ( SrcReg , <NUM_LIT> , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI . getParent ( ) , UseMI , UseMI . getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) ;


<s> { const unsigned SUBOpc = getSUBriOpcode ( Uses64BitFramePtr , Offset ) ; BuildMI ( MBB , MBBI , DL , TII . get ( SUBOpc ) , FinalStackProbed ) . addReg ( FinalStackProbed ) . addImm ( Offset / StackProbeSize * StackProbeSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } { const unsigned SUBOpc = getSUBriOpcode ( Uses64BitFramePtr , StackProbeSize ) ; BuildMI ( testMBB , DL , TII . get ( SUBOpc ) , StackPtr ) . addReg ( StackPtr ) . addImm ( StackProbeSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } addRegOffset ( BuildMI ( testMBB , DL , TII . get ( MovMIOpc ) ) . setMIFlag ( MachineInstr :: FrameSetup ) , StackPtr , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( testMBB , DL , TII . get ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( StackPtr ) . addReg ( FinalStackProbed ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( testMBB , DL , TII . get ( <STR_LIT> ) ) . addMBB ( testMBB ) . addImm ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; testMBB -> addSuccessor ( testMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; tailMBB -> splice ( tailMBB -> end ( ) , & MBB , MBBI , MBB . end ( ) ) ; tailMBB -> transferSuccessorsAndUpdatePHIs ( & MBB ) ; MBB . addSuccessor ( testMBB ) ;

unsigned TailOffset = Offset % StackProbeSize ;


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; note_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - total_size ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note_rtx ) ; offset = total_size - UNITS_PER_WORD ; } } for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; ++ regno ) { if ( xtensa_call_save_reg ( regno ) ) { rtx x = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ; rtx mem = gen_frame_mem ( SImode , x ) ; rtx reg = gen_rtx_REG ( SImode , regno ) ; offset -= UNITS_PER_WORD ; insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( mem , reg ) ) ; } } if ( total_size > <NUM_LIT> ) { rtx tmp_reg = gen_rtx_REG ( Pmode , A9_REG ) ; emit_move_insn ( tmp_reg , GEN_INT ( total_size - callee_save_size ) ) ; insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp_reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; note_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , callee_save_size - total_size ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note_rtx ) ; } } if ( frame_pointer_needed ) { if ( cfun -> machine -> set_frame_ptr_insn ) { rtx_insn * first ; push_topmost_sequence ( ) ; first = get_insns ( ) ; pop_topmost_sequence ( ) ; for ( insn = first ; insn != cfun -> machine -> set_frame_ptr_insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { PATTERN ( insn ) = replace_rtx ( copy_rtx ( PATTERN ( insn ) ) , hard_frame_pointer_rtx , stack_pointer_rtx ) ; df_insn_rescan ( insn ) ; } } } else { insn = emit_insn ( gen_movsi ( hard_frame_pointer_rtx , stack_pointer_rtx ) ) ; if ( ! TARGET_WINDOWED_ABI ) { note_rtx = gen_rtx_SET ( hard_frame_pointer_rtx , stack_pointer_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note_rtx ) ; } } } if ( TARGET_WINDOWED_ABI ) { note_rtx = gen_rtx_SET ( ( frame_pointer_needed ? hard_frame_pointer_rtx : stack_pointer_rtx ) , plus_constant ( Pmode , stack_pointer_rtx , - total_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note_rtx ) ; }


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_IL32PC64_L64PC128_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32F_LP64F_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_IL32PC64F_L64PC128F_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32D_LP64D_RegMask ; case <STR_LIT> :


<s> else aarch64_emit_move ( temp1 , gen_rtx_SIGN_EXTEND ( Pmode , gen_rtx_MEM ( ptr_mode , addr ) ) ) ; emit_insn ( gen_add2_insn ( this_rtx , temp1 ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; insn = get_insns ( ) ; shorten_branches ( insn ) ; final_start_function ( insn , file , <NUM_LIT> ) ; final ( insn , file , <NUM_LIT> ) ; final_end_function ( ) ; reload_completed = <NUM_LIT> ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> void setSRetReturnReg ( unsigned Reg ) {


<s> if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) return createR600MachineScheduler ( C ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> firstRegToSaveIndex = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; lastRegToSaveIndex = <NUM_LIT> ; } unsigned ArgRegsSize , ArgRegsSaveSize ; computeRegArea ( CCInfo , MF , InRegsParamRecordIdx , ArgSize , ArgRegsSize , ArgRegsSaveSize ) ; if ( ArgRegsSaveSize ) { unsigned Padding = ArgRegsSaveSize - ArgRegsSize ; if ( Padding ) { assert ( AFI -> getStoredByValParamsPadding ( ) == <NUM_LIT> && <STR_LIT> ) ; AFI -> setStoredByValParamsPadding ( Padding ) ; } int FrameIndex = MFI -> CreateFixedObject ( ArgRegsSaveSize , Padding + ArgOffset , false ) ; SDValue FIN = DAG . getFrameIndex ( FrameIndex , getPointerTy ( ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; for ( unsigned i = <NUM_LIT> ; firstRegToSaveIndex < lastRegToSaveIndex ; ++ firstRegToSaveIndex , ++ i ) {


<s> * no_add_attrs = true ; } else if ( strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) && strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) && ! TARGET_V2 ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } else if ( TARGET_V2 && strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ;


<s> return __builtin_aarch64_crypto_pmulldi_ppp ( a , b ) ;


<s> static bool isSigned ( Kind Cmp ) { return ( Cmp & ( L | G ) && ! ( Cmp & U ) ) ;


<s> rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode1 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( icode == CODE_FOR_altivec_vcfux || icode == CODE_FOR_altivec_vcfsx || icode == CODE_FOR_altivec_vctsxs || icode == CODE_FOR_altivec_vctuxs || icode == CODE_FOR_altivec_vspltb || icode == CODE_FOR_altivec_vsplth || icode == CODE_FOR_altivec_vspltw || icode == CODE_FOR_spe_evaddiw || icode == CODE_FOR_spe_evldd || icode == CODE_FOR_spe_evldh || icode == CODE_FOR_spe_evldw || icode == CODE_FOR_spe_evlhhesplat || icode == CODE_FOR_spe_evlhhossplat || icode == CODE_FOR_spe_evlhhousplat || icode == CODE_FOR_spe_evlwhe || icode == CODE_FOR_spe_evlwhos || icode == CODE_FOR_spe_evlwhou || icode == CODE_FOR_spe_evlwhsplat || icode == CODE_FOR_spe_evlwwsplat || icode == CODE_FOR_spe_evrlwi || icode == CODE_FOR_spe_evslwi || icode == CODE_FOR_spe_evsrwis || icode == CODE_FOR_spe_evsubifw || icode == CODE_FOR_spe_evsrwiu ) { STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg1 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_dfptstsfi_eq_dd || icode == CODE_FOR_dfptstsfi_lt_dd || icode == CODE_FOR_dfptstsfi_gt_dd || icode == CODE_FOR_dfptstsfi_unordered_dd || icode == CODE_FOR_dfptstsfi_eq_td || icode == CODE_FOR_dfptstsfi_lt_td || icode == CODE_FOR_dfptstsfi_gt_td || icode == CODE_FOR_dfptstsfi_unordered_td ) { STRIP_NOPS ( arg0 ) ; if ( TREE_CODE ( arg0 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg0 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_xststdcdp || icode == CODE_FOR_xststdcsp || icode == CODE_FOR_xvtstdcdp || icode == CODE_FOR_xvtstdcsp ) { STRIP_NOPS ( arg1 ) ; if ( TREE_CODE ( arg1 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg1 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ;


<s> MachineBasicBlock :: iterator I ( & MI ) ; const MachineOperand * Idx = TII -> getNamedOperand ( MI , <STR_LIT> :: idx ) ; assert ( Idx -> getReg ( ) != <STR_LIT> ) ; if ( Offset == <NUM_LIT> ) {

BuildMI ( * MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . add ( * Idx ) ;


<s> Stack . pop_back ( ) ; EHPadStack . pop_back ( ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : EHPadStack . push_back ( & MBB ) ; break ; case <STR_LIT> : assert ( Stack . back ( ) == & MBB && <STR_LIT> ) ; Stack . pop_back ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Stack . push_back ( & MBB ) ; break ; case <STR_LIT> : Stack . push_back ( EndToBegin [ & MI ] -> getParent ( ) ) ; break ; case <STR_LIT> : { unsigned EHPadDepth = GetDepth ( EHPadStack , MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; MI . RemoveOperand ( <NUM_LIT> ) ; MI . addOperand ( MF , MachineOperand :: CreateImm ( EHPadDepth ) ) ; break ; } case <STR_LIT> : { MachineInstr * Rethrow = BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addImm ( Stack . size ( ) ) ; MI . eraseFromParent ( ) ; I = MachineBasicBlock :: reverse_iterator ( Rethrow ) ;


<s> unsigned <ISA_LIT>Z80MCCodeEmitter :: getExprOpValue ( const MCExpr * Expr , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } if ( Kind == MCExpr :: Target ) { <ISA_LIT>Z80MCExpr const * <ISA_LIT>Z80Expr = cast < <ISA_LIT>Z80MCExpr > ( Expr ) ; int64_t Result ;

if ( <ISA_LIT>Z80Expr -> evaluateAsConstant ( Result ) ) {


<s> bool isValue ( ) const { return Kind == <STR_LIT> ;


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return LowerMEMBARRIER ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINLINEASM ( Op , DAG ) ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_<ISA_LIT> , false ) {


<s> for ( ref = DF_INSN_UID_DEFS ( insn_uid ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( ! HARD_REGISTER_P ( DF_REF_REG ( ref ) ) ) analyze_register_chain ( candidates , ref ) ; for ( ref = DF_INSN_UID_USES ( insn_uid ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( ! DF_REF_REG_MEM_P ( ref ) ) analyze_register_chain ( candidates , ref ) ;


<s> } const auto & CSI = getNonLibcallCSI ( MFI . getCalleeSavedInfo ( ) ) ; auto LastFrameDestroy = MBBI ; if ( ! CSI . empty ( ) ) LastFrameDestroy = std :: prev ( MBBI , CSI . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t RealStackSize = StackSize + RVFI -> getLibCallStackSize ( ) ; uint64_t FPOffset = RealStackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount ( MF ) ; if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , SPReg , SecondSPAdjustAmount , MachineInstr :: FrameDestroy ) ;


<s> Op -> Mem . OffsetReg = <STR_LIT> ; Op -> Mem . Off = nullptr ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> static inline uint8_t encodeAdvSIMDModImmType9 ( uint64_t Imm ) {


<s> SDValue Ptr = lowerKernArgParameterPtr ( DAG , SL , Chain , Offset ) ; SDValue Load = DAG . getLoad ( MemVT , SL , Chain , Ptr , PtrInfo , Align , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; SDValue Val = convertArgType ( DAG , VT , MemVT , SL , Load , Signed , Arg ) ; return DAG . getMergeValues ( { Val , Load . getValue ( <NUM_LIT> ) } , SL ) ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ;

if ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return <STR_LIT> ( <STR_LIT> , VT . getVectorElementCount ( ) ) ;


<s> if ( nregs == <NUM_LIT> && GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) { if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return mode ; else return SImode ; }

else return choose_hard_reg_mode ( regno , nregs , false ) ;


<s> if ( curLoc . isUnknown ( ) ) return ; const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const LLVMContext & ctx = MF -> getFunction ( ) -> getContext ( ) ; DIScope Scope ( curLoc . getScope ( ctx ) ) ; assert ( ( ! Scope || Scope . isScope ( ) ) && <STR_LIT> ) ; if ( ! Scope ) return ; StringRef fileName ( Scope . getFilename ( ) ) ; StringRef dirName ( Scope . getDirectory ( ) ) ; SmallString < <NUM_LIT> > FullPathName = dirName ; if ( ! dirName . empty ( ) && ! sys :: path :: is_absolute ( fileName ) ) {

sys :: path :: append ( FullPathName , fileName ) ;


<s> for ( MachineInstr * MI : Instrs ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) || ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; Register R = MO . getReg ( ) ; if ( ! R . isVirtual ( ) || ! MRI -> use_nodbg_empty ( R ) ) { AllDead = false ; break ; }


<s> <ISA_LIT>BETargetMachine :: <ISA_LIT>BETargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> static void expand_block_move_2 ( rtx dst , rtx dst_reg , rtx src , rtx src_reg , rtx bytes_rtx ) { const rtx sym = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; unsigned HOST_WIDE_INT bytes = UINTVAL ( bytes_rtx ) ; unsigned int rem = bytes % <NUM_LIT> ; emit_library_call ( sym , LCT_NORMAL , VOIDmode , <NUM_LIT> , dst_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , GEN_INT ( bytes >> <NUM_LIT> ) , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ;


<s> assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) ) && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasAVX2 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; unsigned NumLaneElts = NumElts / NumLanes ; for ( unsigned l = <NUM_LIT> ; l != NumLanes ; ++ l ) { for ( unsigned i = l * NumLaneElts , j = ( l * NumLaneElts ) + NumLaneElts / <NUM_LIT> ; i != ( l + <NUM_LIT> ) * NumLaneElts ; i += <NUM_LIT> , ++ j ) { int BitI = Mask [ i ] ;


<s> Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ;

const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) : nullptr ;


<s> if ( MayFoldVectorLoad ( V1 ) && MayFoldIntoStore ( Op ) ) CanFoldLoad = true ; if ( MayFoldVectorLoad ( V1 ) && MayFoldVectorLoad ( V2 ) ) CanFoldLoad = false ; if ( CanFoldLoad ) { if ( HasSSE2 && NumElems == <NUM_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; if ( NumElems == <NUM_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; } ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; if ( ( HasSSE2 && NumElems == <NUM_LIT> ) || ! <STR_LIT> ( SVOp ) ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; else if ( HasSSE2 ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; assert ( VT != <STR_LIT> && <STR_LIT> ) ;

return getTargetShuffleNode ( <STR_LIT> , dl , VT , V2 , V1 , <STR_LIT> ( SVOp ) , DAG ) ;


<s> if ( rs6000_default_long_calls && ( TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE ) ) TYPE_ATTRIBUTES ( type ) = tree_cons ( get_identifier ( <STR_LIT> ) , NULL_TREE , TYPE_ATTRIBUTES ( type ) ) ; darwin_set_default_type_attributes ( type ) ;


<s> for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ) { MachineInstr * MI = & * MBBI ++ ; if ( ! MI -> isCopy ( ) ) continue ; DebugLoc DL = MI -> getDebugLoc ( ) ; Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DstReg . isVirtual ( ) && ( SrcReg == <STR_LIT> || <STR_LIT> . contains ( SrcReg ) ) ) { Register Tmp = MRI -> createVirtualRegister ( & <STR_LIT> ) ; if ( SrcReg == <STR_LIT> ) BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) ; else BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , Tmp ) . addReg ( SrcReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Tmp ) ; Modified = true ; } else if ( SrcReg . isVirtual ( ) && <STR_LIT> . contains ( DstReg ) ) { Register Tmp = MRI -> createVirtualRegister ( & <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( Tmp ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( Tmp ) ; Modified = true ; } }


<s> ~ <ISA_LIT>AsmBackend ( ) override {


<s> MachineBasicBlock :: iterator instrAfterFirstTerminator ; for ( instrAfterFirstTerminator = MBB -> begin ( ) ; & ( * instrAfterFirstTerminator ) != firstTerminator ; ++ instrAfterFirstTerminator ) ; instrAfterFirstTerminator ++ ; MachineBasicBlock * newBB = splitBlockAfterInstr ( instrAfterFirstTerminator , MF ) ; MachineBasicBlock * succ_branch = NULL ; if ( firstTerminator -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) succ_branch = firstTerminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; for ( MachineBasicBlock :: succ_iterator SI = MBB -> succ_begin ( ) , SE = MBB -> succ_end ( ) ; SI != SE ; ++ SI ) { if ( ( * SI ) != succ_branch && ( * SI ) != newBB ) { newBB -> addSuccessor ( * SI ) ; } } for ( MachineBasicBlock :: succ_iterator SI = newBB -> succ_begin ( ) , SE = newBB -> succ_end ( ) ; SI != SE ; ++ SI ) { MBB -> removeSuccessor ( * SI ) ; }


<s> if ( ! isPowerOf2_64 ( Val ) ) return false ; unsigned TestedBit = Log2_64 ( Val ) ; if ( TestedBit >= RegWidth ) return false ;

FixedPos = CurDAG -> getTargetConstant ( TestedBit , <STR_LIT> ) ;


<s> case MachO :: <ISA_LIT>_THUMB_RELOC_BR22 : Value -= <NUM_LIT> ; Range = <NUM_LIT> ; } const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Value += Writer -> getSectionAddress ( & SymSD ) ; Value -= Writer -> getSectionAddress ( Fragment . getParent ( ) ) ; if ( Value > Range || Value < - ( Range + <NUM_LIT> ) ) return true ; return false ;


<s> if ( Outs . empty ( ) ) return NotStructReturn ; const <STR_LIT> & Flags = Outs [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ;

if ( Flags . isInReg ( ) || IsMCU ) return RegStructReturn ;


<s> const <ISA_LIT>ABIInfo & ABI = TM . getABI ( ) ; MachineInstrBuilder CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; const bool IsCalleeGlobalPIC = Info . Callee . isGlobal ( ) && TM . isPositionIndependent ( ) ; MachineInstrBuilder MIB = MIRBuilder . buildInstrNoInsert ( Info . Callee . isReg ( ) || IsCalleeGlobalPIC ? <STR_LIT> : <STR_LIT> ) ; MIB . addDef ( <STR_LIT> , RegState :: Implicit ) ; if ( IsCalleeGlobalPIC ) { Register CalleeReg = MF . getRegInfo ( ) . createGenericVirtualRegister ( LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) ; MachineInstr * CalleeGlobalValue = MIRBuilder . buildGlobalValue ( CalleeReg , Info . Callee . getGlobal ( ) ) ; if ( ! Info . Callee . getGlobal ( ) -> hasLocalLinkage ( ) ) CalleeGlobalValue -> getOperand ( <NUM_LIT> ) . setTargetFlags ( <STR_LIT> ) ; MIB . addUse ( CalleeReg ) ; } else MIB . add ( Info . Callee ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; TargetLowering :: ArgListTy FuncOrigArgs ; FuncOrigArgs . reserve ( Info . OrigArgs . size ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto & Arg : Info . OrigArgs ) splitToValueTypes ( Arg , ArgInfos , DL , Info . CallConv ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; bool IsCalleeVarArg = false ; if ( Info . Callee . isGlobal ( ) ) { const Function * CF = static_cast < const Function * > ( Info . Callee . getGlobal ( ) ) ; IsCalleeVarArg = CF -> isVarArg ( ) ; } <ISA_LIT>CCState CCInfo ( Info . CallConv , IsCalleeVarArg , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( Info . CallConv ) , Align ( <NUM_LIT> ) ) ; const char * Call = Info . Callee . isSymbol ( ) ? Info . Callee . getSymbolName ( ) : nullptr ; <ISA_LIT>OutgoingValueAssigner Assigner ( TLI . CCAssignFnForCall ( ) , Call , false ) ; if ( ! determineAssignments ( Assigner , ArgInfos , CCInfo ) ) return false ; <ISA_LIT>OutgoingValueHandler ArgHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! handleAssignments ( ArgHandler , ArgInfos , CCInfo , ArgLocs , MIRBuilder ) ) return false ; unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ;

unsigned StackAlignment = F . getParent ( ) -> getOverrideStackAlignment ( ) ;


<s> assert ( VT . isFloatingPoint ( ) ) ; return VT == <STR_LIT> || VT == <STR_LIT> ;


<s> assert ( C . LRUWasSet && <STR_LIT> ) ; MachineFunction * MF = C . getMF ( ) ; const <ISA_LIT>BaseRegisterInfo * ARI = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF -> getSubtarget ( ) . getRegisterInfo ( ) ) ; BitVector regsReserved = ARI -> getReservedRegs ( * MF ) ; for ( unsigned Reg : <STR_LIT> ) { if ( ! ( Reg < regsReserved . size ( ) && regsReserved . test ( Reg ) ) && Reg != <STR_LIT> && Reg != <STR_LIT> && C . LRU . available ( Reg ) && C . UsedInSequence . available ( Reg ) ) return Reg ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : VarArgsFrameIndex ( <NUM_LIT> ) {


<s> BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * StackSlotsUsedByFunclet ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( store_funclet_name [ Last - <STR_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; AlreadyAdjusted += <NUM_LIT> * ( StackSlotsUsedByFunclet + <NUM_LIT> ) ; SavedBlink = true ; } if ( MFI . hasCalls ( ) && ! SavedBlink ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) ; AlreadyAdjusted += <NUM_LIT> ; } if ( AFI -> MaxCallStackReq > <NUM_LIT> ) MFI . setStackSize ( MFI . getStackSize ( ) + AFI -> MaxCallStackReq ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( MFI . getStackSize ( ) - AlreadyAdjusted ) << <STR_LIT> ) ; generateStackAdjustment ( MBB , MBBI , * ST . getInstrInfo ( ) , dl , - ( MFI . getStackSize ( ) - AlreadyAdjusted ) , <STR_LIT> ) ; if ( hasFP ( MF ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( isUInt < <NUM_LIT> > ( MFI . getStackSize ( ) ) ? <STR_LIT> : <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( MFI . getStackSize ( ) ) ; } unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int CurOffset = - <NUM_LIT> ; if ( hasFP ( MF ) ) { CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( <STR_LIT> , true ) , CurOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; CurOffset -= <NUM_LIT> ; } if ( MFI . hasCalls ( ) ) { CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( <STR_LIT> , true ) , CurOffset ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlags ( MachineInstr :: FrameSetup ) ; } for ( const auto & Entry : CSI ) { unsigned Reg = Entry . getReg ( ) ;


<s> bytes = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( bytes <= <NUM_LIT> ) return <NUM_LIT> ; value = ( int8_t ) INTVAL ( operands [ <NUM_LIT> ] ) ; align = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( align > MOVE_MAX ) align = MOVE_MAX ; if ( bytes % align != <NUM_LIT> ) return <NUM_LIT> ; count = bytes / align ; if ( ! ( TARGET_LOOPS && optimize ) ) { if ( align == <NUM_LIT> && ! ( bytes <= <NUM_LIT> || xtensa_simm8x256 ( bytes ) ) ) return <NUM_LIT> ; if ( align != <NUM_LIT> && count > ( ( optimize > <NUM_LIT> && ! optimize_size ) ? <NUM_LIT> : <NUM_LIT> ) ) return <NUM_LIT> ; } if ( align == <NUM_LIT> ) expand_len = xtensa_sizeof_MOVI ( value ) ; else if ( value == <NUM_LIT> || value == - <NUM_LIT> ) expand_len = TARGET_DENSITY ? <NUM_LIT> : <NUM_LIT> ; else expand_len = <NUM_LIT> + <NUM_LIT> ; if ( TARGET_LOOPS && optimize ) { expand_len += xtensa_simm12b ( count ) ? xtensa_sizeof_MOVI ( count ) : <NUM_LIT> + <NUM_LIT> ; expand_len += <NUM_LIT> ; expand_len += ( TARGET_DENSITY && align == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) + ( TARGET_DENSITY ? <NUM_LIT> : <NUM_LIT> ) ; }


<s> assert ( Ty -> isIntegerTy ( ) ) ; return true ;


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator JumpI = MI ; if ( ! isFrameSetup && isEFLAGSlive ) { MachineBasicBlock :: iterator LAHF = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; MachineBasicBlock :: iterator SAHF = BuildMI ( * MBB , std :: next ( MI ) , DL , TII -> get ( <STR_LIT> ) ) ; JumpI = SAHF ; if ( isRAXlive ) { insertDoubleXchange ( LAHF ) ; JumpI = insertDoubleXchange ( SAHF ) ; } } MachineInstr * CmpI = BuildMI ( * MBB , MI , DL , TII -> get ( NativeOpc ) ) ; unsigned StartIndex = isFrameSetup ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = StartIndex ; i < MI -> getNumOperands ( ) ; i ++ ) { CmpI -> addOperand ( MI -> getOperand ( i ) ) ; } MachineInstr * JumpMI = BuildMI ( * MBB , JumpI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( MF -> getExitBlock ( ) ) ; JumpMI -> getOperand ( <NUM_LIT> ) . setIsKill ( true ) ; JumpMI -> setFlag ( MachineInstr :: ExitJump ) ; MF -> getExitBlock ( ) -> addPredecessor ( MBB ) ; MI -> eraseFromParent ( ) ;


<s> return ~ __X | ( __X + <NUM_LIT> ) ;


<s> SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getBitcast ( ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + NumElts / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts * <NUM_LIT> / <NUM_LIT> ; } SDValue ResHi = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResHi = DAG . getBitcast ( ResVT , ResHi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , ResLo , ResHi ) ; } unsigned ReducedSizeInBits = ReducedVT . getSizeInBits ( ) ; if ( ( RegSize % ReducedSizeInBits ) != <NUM_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( RegSize / ReducedSizeInBits , DAG . getUNDEF ( ReducedVT ) ) ; Ops [ <NUM_LIT> ] = NewN0 ; NewN0 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; Ops [ <NUM_LIT> ] = NewN1 ; NewN1 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; if ( Mode == MULU8 || Mode == MULS8 ) { SDValue Mul = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue Res = DAG . getNode ( Mode == MULU8 ? <STR_LIT> : <STR_LIT> , DL , ResVT , Mul ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ;

SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ;


<s> int result ; if ( debug_m6811 ) { printf ( <STR_LIT> ) ; fflush ( stdout ) ; debug_rtx ( operand ) ; } result = go_if_legitimate_address_internal ( operand , mode , strict ) ;


<s> static DecodeStatus DecodeGPR64RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) {

if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> return isSignOrZeroExtended ( MI , true , depth ) ;


<s> popType ( ErrorLoc , RVT ) ; } if ( ! Stack . empty ( ) ) {

typeError ( ErrorLoc , std :: to_string ( Stack . size ( ) ) + <STR_LIT> ) ;


<s> Op -> Mem . Off = Off ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> void processFixupValue ( const MCAssembler & Asm , const MCAsmLayout & Layout , const MCFixup & Fixup , const MCFragment * DF , MCValue & Target , uint64_t & Value , bool & IsResolved ) { switch ( ( <STR_LIT> ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> :

if ( Target . getSymA ( ) -> getSymbol ( ) . isTemporary ( ) ) return ;


<s> if ( MBBI -> mayLoadOrStore ( ) && ( ! memAccessesCanBeReordered ( * CI . I , * MBBI , AA ) || ! canMoveInstsAcrossMemOp ( * MBBI , InstsToMove , AA ) ) ) { InstsToMove . push_back ( & * MBBI ) ; addDefsUsesToList ( * MBBI , RegDefsToMove , PhysRegUsesToMove ) ; continue ; } addToListsIfDependent ( * MBBI , RegDefsToMove , PhysRegUsesToMove , InstsToMove ) ; continue ; } if ( addToListsIfDependent ( * MBBI , RegDefsToMove , PhysRegUsesToMove , InstsToMove ) ) continue ; if ( & * MBBI == & * Paired . I ) { if ( canMoveInstsAcrossMemOp ( * MBBI , InstsToMove , AA ) ) { if ( CI . InstClass != MIMG ) offsetsCanBeCombined ( CI , * STM , Paired , true ) ; return true ;


<s> PHINode * PN = nullptr ; if ( F . getReturnType ( ) -> isVoidTy ( ) ) { ReturnInst :: Create ( F . getContext ( ) , nullptr , NewRetBlock ) ; } else { PN = PHINode :: Create ( F . getReturnType ( ) , ReturningBlocks . size ( ) , <STR_LIT> ) ; NewRetBlock -> getInstList ( ) . push_back ( PN ) ; ReturnInst :: Create ( F . getContext ( ) , PN , NewRetBlock ) ; } for ( BasicBlock * BB : ReturningBlocks ) {

if ( PN ) PN -> addIncoming ( BB -> getTerminator ( ) -> getOperand ( <NUM_LIT> ) , BB ) ;


<s> BranchWithZeroOperand = ZeroOperandPosition != - <NUM_LIT> ; } if ( BranchWithZeroOperand ) { switch ( NewOpc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) MIB -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . add ( I -> getOperand ( J ) ) ;


<s> EVT NewVTArg = ContainerVT . changeVectorElementType ( VTArg ) ; Operands . push_back ( DAG . getValueType ( NewVTArg ) ) ; continue ; } assert ( isTypeLegal ( V . getValueType ( ) ) && <STR_LIT> ) ; Operands . push_back ( convertToScalableVector ( DAG , ContainerVT , V ) ) ; } if ( isMergePassthruOpcode ( NewOp ) ) Operands . push_back ( DAG . getUNDEF ( ContainerVT ) ) ; auto ScalableRes = DAG . getNode ( NewOp , DL , ContainerVT , Operands ) ; return convertFromScalableVector ( DAG , VT , ScalableRes ) ; } assert ( VT . isScalableVector ( ) && <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Operands = { Pg } ; for ( const SDValue & V : Op -> op_values ( ) ) {

assert ( ( ! V . getValueType ( ) . isVector ( ) || V . getValueType ( ) . isScalableVector ( ) ) && <STR_LIT> ) ;


<s> else return ( GET_MODE_SIZE ( mode ) + <NUM_LIT> - <NUM_LIT> ) / <NUM_LIT> ; case ACCESS_REGS : return ( GET_MODE_SIZE ( mode ) + <NUM_LIT> - <NUM_LIT> ) / <NUM_LIT> ; default : break ; } return ( GET_MODE_SIZE ( mode ) + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ;


<s> const __v4su shmax = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4su result ; lshift = vec_splat ( ( __v4su ) __B , <NUM_LIT> ) ;


<s> if ( isUInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return <STR_LIT> ; }


<s> sprintf ( buf , <STR_LIT> , arm_data_section_count ++ ) ;


<s> <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , Subtarget ( sti ) {


<s> <ISA_LIT>RelaxMem ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>RelaxMemPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> enum attr_type type ; if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; type = get_attr_type ( insn ) ;

if ( type == TYPE_MUL || type == TYPE_DIV || type == TYPE_SDIV || type == TYPE_DDIV || type == TYPE_SSQRT || type == TYPE_DSQRT || type == TYPE_MFCR || type == TYPE_MFCRF || type == TYPE_MFJMPR ) {


<s> assert ( Subtarget . isFP64bit ( ) ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; MachineRegisterInfo & RegInfo = BB -> getParent ( ) -> getRegInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Wd = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wd_in = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Lane = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Fs = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addImm ( <NUM_LIT> ) . addReg ( Fs ) . addImm ( <STR_LIT> ) ;

BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Wd_in ) . addImm ( Lane ) . addReg ( Wt ) . addImm ( <NUM_LIT> ) ;


<s> AFI -> setStackSizeSVE ( alignTo ( SVEStackSize , <NUM_LIT> ) ) ; AFI -> setMinMaxSVECSFrameIndex ( MinCSFrameIndex , MaxCSFrameIndex ) ; if ( ! MF . hasEHFunclets ( ) ) return ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; int UnwindHelpFI = MFI . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; DebugLoc DL ; RS -> enterBasicBlockEnd ( MBB ) ; RS -> backward ( std :: prev ( MBBI ) ) ;

unsigned DstReg = RS -> FindUnusedReg ( & <STR_LIT> ) ;


<s> static bool rl78_valid_pointer_mode ( machine_mode m ) { return ( m == HImode || m == SImode ) ;


<s> return ( __m64 ) __builtin_arm_wcmpgtsb ( ( __v8qi ) __m1 , ( __v8qi ) __m2 ) ;


return __builtin_neon_vrsqrtev8hf ( __a ) ;


<s> if ( * code == LEU && CONST_INT_P ( * op1 ) ) {

* op1 = gen_int_mode ( INTVAL ( * op1 ) + <NUM_LIT> , SImode ) ;


<s> return getImm34Encoding ( MI , OpNo , Fixups , STI , ( MCFixupKind ) <STR_LIT> ) ;


<s> if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) || isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> } ) ) if ( SDValue V1S = getScalarValueForVectorElement ( V1 , Mask [ <NUM_LIT> ] , DAG ) ) return DAG . getNode ( isShuffleFoldableLoad ( V1S ) ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , V2 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1S ) ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ;

unsigned SHUFPDMask = ( Mask [ <NUM_LIT> ] == <NUM_LIT> ) | ( ( ( Mask [ <NUM_LIT> ] - <NUM_LIT> ) == <NUM_LIT> ) << <NUM_LIT> ) ;


<s> if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != <STR_LIT> ) return CS ; } }


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool NoExecStack , bool IsThumb ) { <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , TAB , OS , Emitter , IsThumb ) ; new <ISA_LIT>TargetELFStreamer ( * S ) ;

S -> getAssembler ( ) . setELFHeaderEFlags ( ELF :: EF_<ISA_LIT>_EABI_VER5 ) ;


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned SPReg = MFI -> getStackPtrOffsetReg ( ) ; unsigned Op = IsDestroy ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , TII -> get ( Op ) , SPReg ) . addReg ( SPReg ) . addImm ( Amount * ST . getWavefrontSize ( ) ) ; } else if ( CalleePopAmount != <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; }


<s> bool isVOP1 ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> <STR_LIT> ) : ( Subtarget . isABI_N64 ( ) ? <STR_LIT> <STR_LIT> : <STR_LIT> ) ) , InstrInfo ( <ISA_LIT>InstrInfo :: create ( * this ) ) , FrameLowering ( <ISA_LIT>FrameLowering :: create ( * this , Subtarget ) ) , TLInfo ( <ISA_LIT>TargetLowering :: create ( * this ) ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) , JITInfo ( ) {


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT , SelectionDAG & DAG ) const { if ( Subtarget . isGP64bit ( ) ) { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; } else { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; } report_fatal_error ( <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> case <STR_LIT> : case <STR_LIT> : Info . ReadMem = false ; Info . WriteMem = true ; Info . PtrVal = Inst -> getArgOperand ( Inst -> getNumArgOperands ( ) - <NUM_LIT> ) ; break ; } switch ( Inst -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : Info . MatchingId = VECTOR_LDST_TWO_ELEMENTS ; break ; case <STR_LIT> :


<s> SDValue OP0 ; SDValue OP1 ; if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext0 = MulOp0 . getOperand ( <NUM_LIT> ) ; if ( Sext0 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { SelectCode ( N ) ; } OP0 = Sext0 ; } else if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp0 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) { SelectCode ( N ) ; } SDValue Chain = LD -> getChain ( ) ; SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; OP0 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LD -> getBasePtr ( ) , TargetConst0 , Chain ) , <NUM_LIT> ) ; } else { return SelectCode ( N ) ; } if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext1 = MulOp1 . getOperand ( <NUM_LIT> ) ; if ( Sext1 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } OP1 = Sext1 ; } else if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp1 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDValue Chain = LD -> getChain ( ) ;


<s> <ISA_LIT>MCTargetExpr ( const MCSymbol * S , VariantKind K ) : Sym ( S ) , Kind ( K ) {


<s> Value * <ISA_LIT>IREmitter :: visitSELECT ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> return ( uint32x4_t ) __builtin_neon_vcgev4si ( __b , __a ) ;


<s> if ( ( getForcedEncodingSize ( ) == <NUM_LIT> && ( TSFlags & <STR_LIT> ) ) || ( getForcedEncodingSize ( ) == <NUM_LIT> && ! ( TSFlags & <STR_LIT> ) ) || ( isForcedDPP ( ) && ! ( TSFlags & <STR_LIT> ) ) || ( isForcedSDWA ( ) && ! ( TSFlags & <STR_LIT> ) ) ) return Match_InvalidOperand ; if ( ( TSFlags & <STR_LIT> ) && ( TSFlags & <STR_LIT> ) && getForcedEncodingSize ( ) != <NUM_LIT> ) return Match_PreferE32 ; return Match_Success ;


<s> const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ;

Entry . Node = Size ; Args . push_back ( Entry ) ;


<s> MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , KernArgSize ( <NUM_LIT> ) , MaxKernArgAlign ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , ABIArgOffset ( <NUM_LIT> ) , IsKernel ( MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_KERNEL || MF . getFunction ( ) -> getCallingConv ( ) == CallingConv :: SPIR_KERNEL ) {


<s> return create<ISA_LIT>ELFObjectWriter ( OS , OSABI , IsLittle ) ;


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext & ctx ) : MCII ( mcii ) , STI ( sti ) , Ctx ( ctx ) {


<s> SDValue <ISA_LIT>DAGToDAGISel :: getHi16Elt ( SDValue In ) const { if ( In . isUndef ( ) ) return CurDAG -> getUNDEF ( <STR_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( In ) ) { SDLoc SL ( In ) ; return CurDAG -> getConstant ( C -> getZExtValue ( ) << <NUM_LIT> , SL , <STR_LIT> ) ; } if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( In ) ) { SDLoc SL ( In ) ;

return CurDAG -> getConstant ( C -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) << <NUM_LIT> , SL , <STR_LIT> ) ;


<s> if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ;

return ( ( Value & <NUM_LIT> ) == <NUM_LIT> && Value <= <NUM_LIT> && Value >= - <NUM_LIT> ) ;


<s> if ( TARGET_X32 ) d_add_builtin_version ( <STR_LIT> ) ; } else d_add_builtin_version ( <STR_LIT> ) ; if ( TARGET_80387 ) d_add_builtin_version ( <STR_LIT> ) ;


<s> void addu16_3ImmOperands ( MCInst & Inst , unsigned N ) const {


<s> reader = new LineReader ( filename ) ; } if ( reader -> fileName ( ) != filename ) { delete reader ; reader = new LineReader ( filename ) ; } return reader ;


<s> static bool rs6000_debug_secondary_memory_needed ( machine_mode mode , reg_class_t from_class , reg_class_t to_class ) { bool ret = rs6000_secondary_memory_needed ( mode , from_class , to_class ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , reg_class_names [ from_class ] , reg_class_names [ to_class ] , GET_MODE_NAME ( mode ) ) ; return ret ;


<s> MachineInstr * BranchMI = getLoopendBlockBranchInstr ( LoopLatch ) ; if ( ! BranchMI || ! isUncondBranch ( BranchMI ) ) return nullptr ; MachineBasicBlock * DummyExitBlk = FuncRep -> CreateMachineBasicBlock ( ) ;


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) clobbered_regs [ i ] = clobbered_regs [ i ] && ! global_regs [ i ] ; cfun_frame_layout . fpr_bitmap = <NUM_LIT> ; cfun_frame_layout . high_fprs = <NUM_LIT> ; for ( i = FPR0_REGNUM ; i <= FPR15_REGNUM ; i ++ ) if ( clobbered_regs [ i ] && ! call_used_regs [ i ] ) { cfun_set_fpr_save ( i ) ; if ( i >= FPR8_REGNUM ) cfun_frame_layout . high_fprs ++ ; } clobbered_regs [ <NUM_LIT> ] |= ( ( flag_pic && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) || ( flag_split_stack && cfun -> stdarg && ( crtl -> is_leaf || TARGET_TPF_PROFILING || has_hard_reg_initial_val ( Pmode , RETURN_REGNUM ) ) ) ) ; clobbered_regs [ BASE_REGNUM ] |= ( cfun -> machine -> base_reg && REGNO ( cfun -> machine -> base_reg ) == BASE_REGNUM ) ; clobbered_regs [ HARD_FRAME_POINTER_REGNUM ] |= ! ! frame_pointer_needed ; clobbered_regs [ RETURN_REGNUM ] |= ( ! crtl -> is_leaf || TARGET_TPF_PROFILING || cfun_frame_layout . save_return_addr_p || crtl -> calls_eh_return ) ; clobbered_regs [ STACK_POINTER_REGNUM ] |= ( ! crtl -> is_leaf || TARGET_TPF_PROFILING || cfun_save_high_fprs_p || get_frame_size ( ) > <NUM_LIT> || ( reload_completed && cfun_frame_layout . frame_size > <NUM_LIT> ) || cfun -> calls_alloca ) ; memset ( cfun_frame_layout . gpr_save_slots , SAVE_SLOT_NONE , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( clobbered_regs [ i ] && ! call_used_regs [ i ] ) cfun_gpr_save_slot ( i ) = SAVE_SLOT_STACK ; s390_register_info_arg_fpr ( ) ;


<s> int NonInlineUseOpNo = - <NUM_LIT> ; MachineRegisterInfo :: use_iterator NextUse , NextInstUse ; for ( MachineRegisterInfo :: use_iterator Use = MRI -> use_begin ( Dst . getReg ( ) ) , E = MRI -> use_end ( ) ; Use != E ; Use = NextUse ) { NextUse = std :: next ( Use ) ; MachineInstr * UseMI = Use -> getParent ( ) ; unsigned OpNo = Use . getOperandNo ( ) ; if ( OpToFold . isImm ( ) && tryConstantFoldOp ( * MRI , TII , UseMI , & OpToFold ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * UseMI << '\n' ) ; NextUse = MRI -> use_begin ( Dst . getReg ( ) ) ; continue ; } if ( isInlineConstantIfFolded ( TII , * UseMI , OpNo , OpToFold ) ) { foldOperand ( OpToFold , UseMI , OpNo , FoldList , CopiesToReplace ) ; } else { if ( ++ NumLiteralUses == <NUM_LIT> ) { NonInlineUse = & * Use ; NonInlineUseOpNo = OpNo ; } } } if ( NumLiteralUses == <NUM_LIT> ) { MachineInstr * UseMI = NonInlineUse -> getParent ( ) ; foldOperand ( OpToFold , UseMI , NonInlineUseOpNo , FoldList , CopiesToReplace ) ; } } else { for ( MachineRegisterInfo :: use_iterator Use = MRI -> use_begin ( Dst . getReg ( ) ) , E = MRI -> use_end ( ) ; Use != E ; ++ Use ) { MachineInstr * UseMI = Use -> getParent ( ) ; foldOperand ( OpToFold , UseMI , Use . getOperandNo ( ) , FoldList , CopiesToReplace ) ; } }

MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ;


<s> unsigned Binary = ( <STR_LIT> ( ( unsigned ) SoImmVal ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= <STR_LIT> ( ( unsigned ) SoImmVal ) ; return Binary ;


<s> case CCValAssign :: ZExt : Opi = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Opi ) ; break ; case CCValAssign :: AExt : Opi = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Opi ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Opi , SDValue ( ) ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ; } else { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;


<s> const LegalizerInfo * <ISA_LIT>Subtarget :: getLegalizerInfo ( ) const { return Legalizer . get ( ) ;


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> OTy = GetRootType ( OTy ) ; gep_type_iterator IdxTyItr = gep_type_begin ( GI ) ; assert ( OTy == IdxTyItr . getIndexedType ( ) && <STR_LIT> ) ;

return getTyIndexInFlattenedType_core ( Func , ConstantInt :: get ( Int32Ty , APInt ( <NUM_LIT> , <NUM_LIT> ) ) , GI , AccessMemFormFlatStruct ) ;


<s> return ( uint64x2_t ) __builtin_neon_vreinterpretv2div16qi ( ( int8x16_t ) __a ) ;


<s> if ( VT . getVectorElementType ( ) . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;


<s> initialize<ISA_LIT>IndexGenPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> return ( ( qword ) ( vec_splat ( ( vec_uint4 ) ( si_from_uint ( imm ) ) , <NUM_LIT> ) ) ) ;


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ;


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , true , false ) ;