<s> code = NE ; break ; case LEU : code = EQ ; break ; case GEU : code = EQ ; op1 = <STR_LIT> ; break ; case LTU : code = NE ; op1 = <STR_LIT> ; break ; default : break ; } } need_z_p = ( ! float_p && code != EQ && code != NE ) ; if ( need_z_p ) op2 = <STR_LIT> ; buffer [ <NUM_LIT> ] = '\0' ; switch ( length ) { case <NUM_LIT> : case <NUM_LIT> : if ( float_p ) sprintf ( buffer , <STR_LIT> , inverted_p ? inverted_comp : comp ) ; else sprintf ( buffer , <STR_LIT> , inverted_p ? inverted_comp : comp , need_z_p ? <STR_LIT> : <STR_LIT> , op1 , op2 ) ; return buffer ; case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : { rtx orig_target ; rtx target = gen_label_rtx ( ) ; orig_target = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = target ; if ( float_p ) sprintf ( buffer , <STR_LIT> , inverted_p ? comp : inverted_comp ) ; else sprintf ( buffer , <STR_LIT> , inverted_p ? comp : inverted_comp , need_z_p ? <STR_LIT> : <STR_LIT> , op1 , op2 ) ; output_asm_insn ( buffer , operands ) ; if ( length != <NUM_LIT> && length != <NUM_LIT> && ! mips_branch_likely ) { rtx insn = final_sequence ; final_scan_insn ( XVECEXP ( insn , <NUM_LIT> , <NUM_LIT> ) , asm_out_file , optimize , <NUM_LIT> , NULL ) ; INSN_DELETED_P ( XVECEXP ( insn , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; if ( length <= <NUM_LIT> ) output_asm_insn ( <STR_LIT> , & orig_target ) ; else { output_asm_insn ( mips_output_load_label ( ) , & orig_target ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } if ( length != <NUM_LIT> && length != <NUM_LIT> && mips_branch_likely ) { rtx insn = final_sequence ; final_scan_insn ( XVECEXP ( insn , <NUM_LIT> , <NUM_LIT> ) , asm_out_file , optimize , <NUM_LIT> , NULL ) ; INSN_DELETED_P ( XVECEXP ( insn , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ; } else output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; ( * targetm . asm_out . internal_label ) ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( target ) ) ; return <STR_LIT> ;


<s> void <ISA_LIT>16InstrInfo :: storeRegToStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI , int64_t Offset ) const { DebugLoc DL ;

if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;


<s> case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } }

return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ;


<s> while ( ! WUsers . empty ( ) ) if ( WeakVH WU = WUsers . pop_back_val ( ) ) { ConstantExpr * CE = dyn_cast < ConstantExpr > ( WU ) ; if ( ! CE || ! replaceConstantExprOp ( CE , P ) ) return false ;


<s> ++ i , ++ realRVLocIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ realRVLocIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( Outs [ i ] . ArgVT == <STR_LIT> ) { Arg = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; } break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : case CCValAssign :: ZExt : Arg = DAG . getZExtOrTrunc ( Arg , DL , VA . getLocVT ( ) ) ; break ; case CCValAssign :: AExtUpper : assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Arg = DAG . getZExtOrTrunc ( Arg , DL , VA . getLocVT ( ) ) ; Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , VA . getLocVT ( ) ) ) ; break ; } if ( RegsUsed . count ( VA . getLocReg ( ) ) ) { SDValue & Bits = llvm :: find_if ( RetVals , [ = ] ( const std :: pair < unsigned , SDValue > & Elt ) { return Elt . first == VA . getLocReg ( ) ;


<s> FunctionPass * llvm :: createCheriInvalidatePass ( ) {


<s> if ( ! MFI -> allocateSGPRSpillToVGPR ( MF , NewFI ) ) llvm_unreachable ( <STR_LIT> ) ; FrameIndex = NewFI ; LLVM_DEBUG ( auto Spill = MFI -> getSGPRToVGPRSpills ( NewFI ) . front ( ) ; dbgs ( ) << <STR_LIT> << ( IsFP ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << printReg ( Spill . VGPR , TRI ) << ':' << Spill . Lane << '\n' ) ; return ; } TempSGPR = findScratchNonCalleeSaveRegister ( MF . getRegInfo ( ) , LiveRegs , <STR_LIT> , true ) ; if ( ! TempSGPR ) { int NewFI = FrameInfo . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , true , nullptr , TargetStackID :: SGPRSpill ) ; if ( TRI -> spillSGPRToVGPR ( ) && MFI -> allocateSGPRSpillToVGPR ( MF , NewFI ) ) { FrameIndex = NewFI ; LLVM_DEBUG ( auto Spill = MFI -> getSGPRToVGPRSpills ( NewFI ) . front ( ) ; dbgs ( ) << ( IsFP ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << printReg ( Spill . VGPR , TRI ) << ':' << Spill . Lane << '\n' ; ) ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseAsmParamRegClass ( OperandVector & Operands ) { unsigned RegNo = <NUM_LIT> ; SMLoc S = getLexer ( ) . getLoc ( ) ; SMLoc E = getLexer ( ) . getTok ( ) . getEndLoc ( ) ; if ( tryParseRegister ( RegNo , S , E ) == MatchOperand_Success ) { auto AsmParamReg = <STR_LIT> ( RegNo , S , E ) ;

if ( validateOperandClass ( * AsmParamReg , MCK_<ISA_LIT>AsmParamRegClass ) == MCTargetAsmParser :: Match_Success ) return MatchOperand_NoMatch ;


<s> } case MachineOperand :: MO_MachineBasicBlock : printBasicBlockLabel ( MO . getMBB ( ) ) ; return ; case MachineOperand :: MO_GlobalAddress : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; GlobalValue * GV = MO . getGlobal ( ) ; O << Mang -> getMangledName ( GV ) ; printOffset ( MO . getOffset ( ) ) ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ExternalSymbol : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; std :: string Name = Mang -> makeNameProper ( MO . getSymbolName ( ) ) ; O << Name ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; break ;


<s> initialize<ISA_LIT>ElfSpecSetPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> RegisterRef getRefForUnit ( uint32_t U ) const {

return RegisterRef ( UnitInfos [ U ] . Reg , UnitInfos [ U ] . Mask ) ;


<s> return & InstrInfo . getRegisterInfo ( ) ;


<s> LoadSDNode * Load = cast < LoadSDNode > ( Op ) ; <STR_LIT> ExtType = Load -> getExtensionType ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; assert ( Load -> getAlignment ( ) >= MemVT . getStoreSize ( ) ) ; SDValue BasePtr = Load -> getBasePtr ( ) ; SDValue Chain = Load -> getChain ( ) ; SDValue Offset = Load -> getOffset ( ) ; SDValue LoadPtr = BasePtr ; if ( ! Offset . isUndef ( ) ) { LoadPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , Offset ) ; } SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; SDValue Read = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , PtrInfo ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoadPtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;

SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> if ( opts -> x_flag_align_labels && ! opts -> x_str_align_labels ) opts -> x_str_align_labels = processor_cost_table [ ix86_tune ] -> align_label ;

if ( opts -> x_flag_align_functions && ! opts -> x_str_align_functions ) opts -> x_str_align_functions = processor_cost_table [ ix86_tune ] -> align_func ;


<s> Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - <NUM_LIT> ) ;

if ( Type != - <NUM_LIT> ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ;


<s> assert ( VT . getSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( VT . is256BitVector ( ) && NumElts != <NUM_LIT> && NumElts != <NUM_LIT> && ( ! HasInt256 || ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) ) ) return false ; assert ( ( ! VT . is512BitVector ( ) || VT . getScalarType ( ) . getSizeInBits ( ) >= <NUM_LIT> ) && <STR_LIT> ) ;

unsigned NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ;


<s> Darwin<ISA_LIT>_64AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef CPU , bool SupportsCU , MachO :: CPUSubType<ISA_LIT> st ) : Darwin<ISA_LIT>AsmBackend ( T , MRI , CPU , true ) , SupportsCU ( SupportsCU ) , Subtype ( st ) {


<s> bool isLegalSMRDImmOffset ( const MCSubtargetInfo & ST , int64_t ByteOffset ) { int64_t EncodedOffset = getSMRDEncodedOffset ( ST , ByteOffset ) ;

return is<ISA_LIT> ( ST ) || isCI ( ST ) ? isUInt < <NUM_LIT> > ( EncodedOffset ) :


<s> static inline bool mips_constant_elt_p ( rtx x ) { return CONST_INT_P ( x ) || GET_CODE ( x ) == CONST_DOUBLE ;


<s> llvm_unreachable ( <STR_LIT> ) ; break ; } } else if ( ! Constraint . empty ( ) && Constraint . size ( ) <= <NUM_LIT> && Constraint [ <NUM_LIT> ] == '{' && * ( Constraint . end ( ) - <NUM_LIT> ) == '}' ) { StringRef name ( Constraint . data ( ) + <NUM_LIT> , Constraint . size ( ) - <NUM_LIT> ) ; uint64_t intVal = <NUM_LIT> ; if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal <= <NUM_LIT> ) { const char regTypes [ ] = { 'g' , 'o' , 'l' , 'i' } ; char regType = regTypes [ intVal / <NUM_LIT> ] ; char regIdx = '0' + ( intVal % <NUM_LIT> ) ; char tmp [ ] = { '{' , regType , regIdx , '}' , <NUM_LIT> } ; std :: string newConstraint = std :: string ( tmp ) ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , newConstraint , VT ) ; } if ( name . substr ( <NUM_LIT> , <NUM_LIT> ) . equals ( <STR_LIT> ) && ! name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , intVal ) && intVal <= <NUM_LIT> ) { std :: string newConstraint ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) {

newConstraint = <STR_LIT> + utostr ( intVal ) + <STR_LIT> ;


<s> if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; RegisterRef RU ( MO ) ; dbgs ( ) << <STR_LIT> << printReg ( RU . Reg , & ME . TRI , RU . Sub ) << <STR_LIT> << ME . getCell ( RU , Map ) << <STR_LIT> ; } dbgs ( ) << <STR_LIT> ; for ( const std :: pair < unsigned , RegisterCell > & P : ResMap ) { RegisterRef RD ( P . first ) ; dbgs ( ) << <STR_LIT> << printReg ( P . first , & ME . TRI ) << <STR_LIT> << ME . getCell ( RD , ResMap ) << <STR_LIT> ; } } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ;

if ( ! TargetRegisterInfo :: isVirtualRegister ( RD . Reg ) ) continue ;


<s> return CallConv == CallingConv :: C || CallConv == CallingConv :: Fast || CallConv == CallingConv :: Cold || CallConv == CallingConv :: PreserveMost || CallConv == CallingConv :: PreserveAll || CallConv == CallingConv :: CXX_FAST_TLS ;


<s> AU . addPreserved < LiveIntervals > ( ) ; AU . addPreservedID ( LiveVariablesID ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( Input . getOperand ( <NUM_LIT> ) ) ; SDValue OrigVector = Input . getOperand ( <NUM_LIT> ) ; if ( Idx && VT == OrigVector . getValueType ( ) ) { unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( NumElts > <NUM_LIT> && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > NewMask ( NumElts , - <NUM_LIT> ) ; unsigned ResultInElt = NumElts / <NUM_LIT> ; ResultInElt -= Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; NewMask [ ResultInElt ] = Idx -> getZExtValue ( ) ;

return DAG . getVectorShuffle ( VT , dl , OrigVector , OrigVector , NewMask ) ;


<s> if ( do_begin_end ) fprintf ( stream , <STR_LIT> ) ;

if ( ( value < ( int64_t ) <NUM_LIT> && value > ( int64_t ) - <NUM_LIT> ) || ( value >= ( int64_t ) <NUM_LIT> && value <= ( int64_t ) <NUM_LIT> ) ) fprintf ( stream , <STR_LIT> , ( int ) value ) ;


<s> if ( ! RASI ) { int LROffset = <ISA_LIT>FrameLowering :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; RASI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , LROffset , true ) ; FI -> setReturnAddrSaveIndex ( RASI ) ; } return DAG . getFrameIndex ( RASI , PtrVT ) ;


<s> MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; } } else llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineInstrBuilder MIB = AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) ) . addMemOperand ( MMO ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; MIB = AddDReg ( MIB , DestReg , <STR_LIT> , RegState :: DefineNoRead , TRI ) ; if ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) ) MIB . addReg ( DestReg , RegState :: ImplicitDefine ) ; } else llvm_unreachable ( <STR_LIT> ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> const MCOperand & Op = MI . getOperand ( i ) ; if ( & Op == & MO ) return i ; } llvm_unreachable ( <STR_LIT> ) ;


<s> return ( poly8x16_t ) __builtin_neon_vdup_lanev16qi ( ( int8x8_t ) __a , __b ) ;


<s> SmallVector < uint32_t , <NUM_LIT> > VPShuf ; SmallVector < uint32_t , <NUM_LIT> > VPAlign [ <NUM_LIT> ] ; SmallVector < uint32_t , <NUM_LIT> > VPAlign2 ; SmallVector < uint32_t , <NUM_LIT> > VPAlign3 ; SmallVector < uint32_t , <NUM_LIT> > GroupSize ; Value * Vec [ <NUM_LIT> ] , * TempVector [ <NUM_LIT> ] ; MVT VT = <STR_LIT> ( Shuffles [ <NUM_LIT> ] -> getType ( ) ) ; createShuffleStride ( VT , <NUM_LIT> , VPShuf ) ; setGroupSize ( VT , GroupSize ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> - i ] , VPAlign [ i ] , false ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] + GroupSize [ <NUM_LIT> ] , VPAlign2 , true , true ) ; DecodePALIGNRMask ( VT , GroupSize [ <NUM_LIT> ] , VPAlign3 , true , true ) ;

concatSubVector ( Vec , InVec , VecElems , Builder ) ;


<s> return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> bool FoundMatch = true ; for ( unsigned k = <NUM_LIT> ; k < VT . getVectorNumElements ( ) ; ++ k ) { ConstantSDNode * CN0 = dyn_cast < ConstantSDNode > ( BVN0 -> getOperand ( k ) ) ; ConstantSDNode * CN1 = dyn_cast < ConstantSDNode > ( BVN1 -> getOperand ( k ) ) ; if ( ! CN0 || ! CN1 || CN0 -> getZExtValue ( ) != ( BitMask & ~ CN1 -> getZExtValue ( ) ) ) { FoundMatch = false ; break ; } } if ( FoundMatch ) return DAG . getNode ( <STR_LIT> , DL , VT , SDValue ( BVN0 , <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> - i ) , N1 -> getOperand ( <NUM_LIT> - j ) ) ; }


<s>
static
BasicBlock
*
nearest_common_dominator
(
DominatorTree
*
DT
,
T
&
Blocks
)
{
DEBUG
(
{
dbgs
(
)
<<
<STR_LIT>
;
for
(
typename
T
::
iterator
I
=
Blocks
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begin
(
)
,
E
=
Blocks
.
end
(
)
;
I
!=
E
;
++
I
)
{
if
(
!
*
I
)
continue
;
BasicBlock
*
B
=
cast
<
BasicBlock
>
(
*
I
)
;
dbgs
(
)
<<
' '
<<
B
->
getName
(
)
;
}
dbgs
(
)
<<
<STR_LIT>
;


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const {

if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ;


<s> assert ( L ) ; BeginToBottom [ Begin ] = <STR_LIT> ( L ) ; } else if ( Begin -> getOpcode ( ) == <STR_LIT> ) { <ISA_LIT>Exception * WE = WEI . getExceptionFor ( TryToEHPad [ Begin ] ) ; assert ( WE ) ; BeginToBottom [ Begin ] = <STR_LIT> ( WE ) ;


<s> fastEmitBranch ( MSucc , Br -> getDebugLoc ( ) ) ; return true ; } MachineBasicBlock * TBB = FuncInfo . MBBMap [ Br -> getSuccessor ( <NUM_LIT> ) ] ; MachineBasicBlock * FBB = FuncInfo . MBBMap [ Br -> getSuccessor ( <NUM_LIT> ) ] ; bool Not ;

unsigned CondReg = getRegForI1Value ( Br -> getCondition ( ) , Not ) ;


<s> OS . EmitIntValue ( std :: get < <NUM_LIT> > ( V ) , <NUM_LIT> ) ; Asm -> EmitLabelReference ( std :: get < <NUM_LIT> > ( V ) , <NUM_LIT> ) ; OS . EmitIntValue ( std :: get < <NUM_LIT> > ( V ) , <NUM_LIT> ) ; }


<s> const MCExpr * <ISA_LIT>TargetStreamer :: addConstantPoolEntry ( const MCExpr * Expr , unsigned Size ) { return ConstantPools -> addEntry ( Streamer , Expr , Size ) ;


<s> val = INTVAL ( operand ) ; switch ( code ) { case IOR : if ( ( val & mask ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ( val & mask ) == mask ) * result = constm1_rtx ; break ; case AND : if ( ( val & mask ) == <NUM_LIT> ) * result = const0_rtx ; if ( ( val & mask ) == mask ) return <NUM_LIT> ; break ; case XOR : if ( ( val & mask ) == <NUM_LIT> ) return <NUM_LIT> ;


<s> const <ISA_LIT>FrameLowering * <ISA_LIT>FrameLowering :: create ( <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & ST ) { if ( TM . getSubtargetImpl ( ) -> in<ISA_LIT>16Mode ( ) ) return llvm :: create<ISA_LIT>16FrameLowering ( ST ) ;

return llvm :: create<ISA_LIT>SEFrameLowering ( ST ) ;


<s> for ( const auto & Def : MRI . def_instructions ( Reg ) ) if ( <STR_LIT> ( Def ) ) return true ; return false ;


<s> return true ; } if ( inClass ( <STR_LIT> , SrcReg , SrcRC ) && inClass ( <STR_LIT> , DestReg , DestRC ) ) { if ( inClass ( <STR_LIT> , SrcReg , SrcRC ) ) { BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } return true ; } if ( inClass ( <STR_LIT> , DestReg , DestRC ) && inClass ( <STR_LIT> , SrcReg , SrcRC ) ) { if ( inClass ( <STR_LIT> , DestReg , DestRC ) ) BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ;

else BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ;


<s> if ( MergeInit ) AU . addRequired < AAResultsWrapperPass > ( ) ;


<s> return true ; } return false ; } ; auto isEligibleForMoveCmp = [ ] ( MachineBasicBlock & BB ) { return BB . succ_size ( ) == <NUM_LIT> ; } ; if ( ! isEligibleBB ( MBB ) ) return false ; unsigned NumPredBBs = MBB . pred_size ( ) ; if ( NumPredBBs == <NUM_LIT> ) { MachineBasicBlock * TmpMBB = * MBB . pred_begin ( ) ; if ( isEligibleBB ( * TmpMBB ) ) { PredMBB = TmpMBB ; MBBtoMoveCmp = nullptr ; return true ; } } else if ( NumPredBBs == <NUM_LIT> ) { MachineBasicBlock :: pred_iterator PI = MBB . pred_begin ( ) ; MachineBasicBlock * Pred1MBB = * PI ; MachineBasicBlock * Pred2MBB = * ( PI + <NUM_LIT> ) ; if ( isEligibleBB ( * Pred1MBB ) && isEligibleForMoveCmp ( * Pred2MBB ) ) { } else if ( isEligibleBB ( * Pred2MBB ) && isEligibleForMoveCmp ( * Pred1MBB ) ) { std :: swap ( Pred1MBB , Pred2MBB ) ; } else return false ; MachineInstr * BI = & * MBB . getFirstInstrTerminator ( ) ; MachineInstr * CMPI = MRI -> getVRegDef ( BI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; for ( int I = <NUM_LIT> ; I <= <NUM_LIT> ; I ++ ) if ( CMPI -> getOperand ( I ) . isReg ( ) ) { MachineInstr * Inst = MRI -> getVRegDef ( CMPI -> getOperand ( I ) . getReg ( ) ) ; if ( Inst -> getParent ( ) == & MBB && Inst -> getOpcode ( ) != <STR_LIT> ) return false ; } PredMBB = Pred1MBB ; MBBtoMoveCmp = Pred2MBB ; return true ;


<s> return std :: make_pair ( TypeIdx , LLT :: scalarOrVector ( ElementCount :: getFixed ( Size / <NUM_LIT> ) , <NUM_LIT> ) ) ;


<s> void addComplexRotationEvenOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ;

Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue ( ) / <NUM_LIT> ) ) ;


<s> DEBUG_TRACE ( { dbgs ( ) << <STR_LIT> ; for ( CD_map_t :: iterator I = CD . begin ( ) , E = CD . end ( ) ; I != E ; ++ I ) { dbgs ( ) . indent ( <NUM_LIT> ) << <STR_LIT> << I -> first -> getMBB ( ) -> getNumber ( ) << <STR_LIT> ; for ( CD_map_entry_t :: iterator EI = I -> second . begin ( ) , EE = I -> second . end ( ) ; EI != EE ; ++ EI ) { Node * n = EI -> first ; Edge e = EI -> second ; fcfg . printNode ( * n ) << <STR_LIT> << ( ( e . first ) ? e . first -> getMBB ( ) -> getNumber ( ) : - <NUM_LIT> ) << <STR_LIT> << e . second -> getMBB ( ) -> getNumber ( ) << <STR_LIT> ; } dbgs ( ) << <STR_LIT> ; }


<s> SuperDestReg = get<ISA_LIT>SubSuperRegister ( OrigDestReg , <NUM_LIT> ) ; const auto SubRegIdx = TRI -> getSubRegIndex ( SuperDestReg , OrigDestReg ) ; if ( SubRegIdx == <STR_LIT> ) return false ; if ( ! LiveRegs . contains ( SuperDestReg ) ) { if ( SubRegIdx != <STR_LIT> ) return true ; if ( ! LiveRegs . contains ( get<ISA_LIT>SubSuperRegister ( OrigDestReg , <NUM_LIT> ) ) && ! LiveRegs . contains ( get<ISA_LIT>SubSuperRegister ( SuperDestReg , <NUM_LIT> , true ) ) ) return true ; } unsigned Opc = OrigMI -> getOpcode ( ) ; ( void ) Opc ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; bool IsDefined = false ; for ( auto & MO : OrigMI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; assert ( ( MO . isDef ( ) || MO . isUse ( ) ) && <STR_LIT> ) ; if ( MO . isDef ( ) && TRI -> isSuperRegisterEq ( OrigDestReg , MO . getReg ( ) ) ) IsDefined = true ;

if ( MO . isUse ( ) && ! TRI -> isSubRegisterEq ( OrigDestReg , MO . getReg ( ) ) && TRI -> regsOverlap ( SuperDestReg , MO . getReg ( ) ) ) return false ;


<s> if ( N -> getMemoryVT ( ) == <STR_LIT> ) { if ( N -> getAlignment ( ) < <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return DAG . getExtLoad ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , N -> getChain ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , <STR_LIT> , N -> isVolatile ( ) , N -> isNonTemporal ( ) , N -> isInvariant ( ) , N -> getAlignment ( ) , N -> getAAInfo ( ) ) ; } if ( N -> getMemoryVT ( ) == <STR_LIT> ) return DAG . getExtLoad ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , N -> getChain ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , <STR_LIT> , N -> isVolatile ( ) , N -> isNonTemporal ( ) , N -> isInvariant ( ) , N -> getAlignment ( ) , N -> getAAInfo ( ) ) ; return SDValue ( ) ;


<s> const MCExpr * <ISA_LIT>64_MachoTargetObjectFile :: getExprForDwarfGlobalReference ( const GlobalValue * GV , Mangler * Mang , MachineModuleInfo * MMI , unsigned Encoding , MCStreamer & Streamer ) const { if ( Encoding & ( DW_EH_PE_indirect | DW_EH_PE_pcrel ) ) { SmallString < <NUM_LIT> > Name ; Mang -> getNameWithPrefix ( Name , GV , false ) ; const MCSymbol * Sym ;

if ( GV -> hasPrivateLinkage ( ) ) Sym = getContext ( ) . GetOrCreateTemporarySymbol ( Name ) ;


<s> if ( ! class_can_hold_mode ( from , mode ) || ! class_can_hold_mode ( to , mode ) ) cost = COSTS_N_INSNS ( <NUM_LIT> ) ; if ( reg_classes_intersect_p ( from , CR_REGS ) ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ; if ( reg_classes_intersect_p ( to , CR_REGS ) ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ; if ( from == MEM_REGS || to == MEM_REGS ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ;

else if ( reg_classes_intersect_p ( from , MEM_REGS ) || reg_classes_intersect_p ( to , MEM_REGS ) ) cost += COSTS_N_INSNS ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: getIndexedAddressParts ( SDNode * Op , SDValue & Base , SDValue & Offset , SelectionDAG & DAG ) const {

if ( Op -> getOpcode ( ) != <STR_LIT> ) return false ;


return __builtin_aarch64_frintnv4sf ( __a ) ;


<s> len = <NUM_LIT> ; for ( m = <NUM_LIT> ; m < NUM_MACHINE_MODES ; ++ m ) if ( rs6000_hard_regno_mode_ok_p [ m ] [ r ] && rs6000_hard_regno_nregs [ m ] [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } if ( rs6000_hard_regno_nregs [ m ] [ r ] > <NUM_LIT> ) len += fprintf ( stderr , <STR_LIT> , comma , GET_MODE_NAME ( m ) , rs6000_hard_regno_nregs [ m ] [ r ] ) ; else len += fprintf ( stderr , <STR_LIT> , comma , GET_MODE_NAME ( m ) ) ; comma = <STR_LIT> ; } if ( call_used_regs [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } len += fprintf ( stderr , <STR_LIT> , comma , <STR_LIT> ) ; comma = <STR_LIT> ; } if ( fixed_regs [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } len += fprintf ( stderr , <STR_LIT> , comma , <STR_LIT> ) ; comma = <STR_LIT> ; } if ( len > <NUM_LIT> ) {


<s> return getRegBitWidth ( MRI -> getRegClass ( RCID ) ) / <NUM_LIT> ;


<s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg ( unsigned PhysReg ) const {

return PhysReg == <STR_LIT> || PhysReg == <STR_LIT> ;


<s> Idx [ <NUM_LIT> ] = Builder . getInt32 ( getTranslator ( ) . getRegSetDesc ( ) . RegOffsetsInSet [ getTranslator ( ) . getRegSetDesc ( ) . RegLargestSupers [ <STR_LIT> ] ] ) ; return Builder . CreateTrunc ( Builder . CreateLoad ( Builder . CreateInBoundsGEP ( RegSet , Idx ) ) , Builder . getInt32Ty ( ) ) ;


<s> const MCInstrDesc & OpDesc = get ( getSGPRSpillRestoreOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; } return ; } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ;


<s> case <STR_LIT> : Changed |= shortenOn001 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : { Changed |= shortenOn001AddCC ( MI , <STR_LIT> , CCLive ) ; break ; } case <STR_LIT> : Changed |= shortenOn01 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= shortenOn0 ( MI , <STR_LIT> ) ; break ; } unsigned UsedLow = <NUM_LIT> ; unsigned UsedHigh = <NUM_LIT> ; for ( auto MOI = MI . operands_begin ( ) , MOE = MI . operands_end ( ) ; MOI != MOE ; ++ MOI ) { MachineOperand & MO = * MOI ; if ( MO . isReg ( ) ) { if ( unsigned Reg = MO . getReg ( ) ) { assert ( Reg < <STR_LIT> && <STR_LIT> ) ; if ( MO . isDef ( ) ) { LiveLow &= ~ LowGPRs [ Reg ] ; LiveHigh &= ~ HighGPRs [ Reg ] ;


<s> unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( SrcReg ) ) ; return MoveReg ;


<s> extern __inline __m256i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_mask_i32gather_epi32 ( __m256i src , int const * base , __m256i index , __m256i mask , const int scale ) {

return ( __m256i ) __builtin_ia32_gathersiv8si ( ( __v8si ) src , base , ( __v8si ) index , ( __v8si ) mask , scale ) ;


<s> SDLoc dl ( Op ) ; MVT ResVT = Op . getSimpleValueType ( ) ; unsigned NumOfOperands = Op . getNumOperands ( ) ; assert ( isPowerOf2_32 ( NumOfOperands ) && <STR_LIT> ) ; if ( NumOfOperands > <NUM_LIT> ) { MVT HalfVT = <STR_LIT> ( ResVT . getScalarType ( ) , ResVT . getVectorNumElements ( ) / <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumOfOperands / <NUM_LIT> ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; Ops . clear ( ) ; for ( unsigned i = NumOfOperands / <NUM_LIT> ; i < NumOfOperands ; i ++ ) Ops . push_back ( Op . getOperand ( i ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , HalfVT , Ops ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Lo , Hi ) ; } SDValue V1 = Op . getOperand ( <NUM_LIT> ) ;

SDValue V2 = Op . getOperand ( <NUM_LIT> ) ;


<s> extern __inline __m256 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_loadu_ps ( float const * __P ) { return * ( __m256_u * ) __P ;


<s> LiveInAttrs . push_back ( std :: make_pair ( VReg , Flags ) ) ;


<s> case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) if ( isHReg ( Reg ) || <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { assert ( ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; else return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; } case <NUM_LIT> : assert ( ( <STR_LIT> . hasSubClassEq ( RC ) || <STR_LIT> . hasSubClassEq ( RC ) ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? <STR_LIT> : <STR_LIT> ; else return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> :


<s> bool hasComplxNum ( ) const { return HasComplxNum ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {

const GlobalValue * GV = GA -> getGlobal ( ) ;


<s> if ( F . hasFnAttribute ( Attribute :: AttrKind :: AlwaysInline ) ) { FuncControl |= static_cast < uint32_t > ( <STR_LIT> :: Inline ) ; } if ( F . hasFnAttribute ( Attribute :: AttrKind :: ReadNone ) ) { FuncControl |= static_cast < uint32_t > ( <STR_LIT> :: Pure ) ; } if ( F . hasFnAttribute ( Attribute :: AttrKind :: ReadOnly ) ) { FuncControl |= static_cast < uint32_t > ( <STR_LIT> :: Const ) ; } if ( F . hasFnAttribute ( Attribute :: AttrKind :: NoInline ) ) { FuncControl |= static_cast < uint32_t > ( <STR_LIT> :: DontInline ) ; }


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> static bool r10k_simplified_address_p ( rtx x ) { if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) x = XEXP ( x , <NUM_LIT> ) ;

return x == virtual_incoming_args_rtx || CONSTANT_P ( x ) ;


<s> <ISA_LIT>MachObjectWriter ( bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) : MCMachObjectTargetWriter ( Is64Bit , CPUType , CPUSubtype , Is64Bit ) {


<s> case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned CmpLHSReg = getRegForValue ( CmpLHS ) ; bool CmpLHSIsKill = hasTrivialKill ( CmpLHS ) ; unsigned CmpRHSReg = getRegForValue ( CmpRHS ) ; bool CmpRHSIsKill = hasTrivialKill ( CmpRHS ) ; if ( ! LHSReg || ! RHSReg || ! CmpLHS || ! CmpRHS ) return false ; const TargetRegisterClass * RC = TLI . getRegClassFor ( RetVT ) ; unsigned ResultReg ; if ( Subtarget -> hasAVX ( ) ) { unsigned CmpOpcode = ( RetVT . SimpleTy == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned BlendOpcode = ( RetVT . SimpleTy == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CmpReg = fastEmitInst_rri ( CmpOpcode , RC , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; ResultReg = fastEmitInst_rrr ( BlendOpcode , RC , RHSReg , RHSIsKill , LHSReg , LHSIsKill , CmpReg , true ) ; } else { unsigned CmpReg = fastEmitInst_rri ( Opc [ <NUM_LIT> ] , RC , CmpLHSReg , CmpLHSIsKill , CmpRHSReg , CmpRHSIsKill , CC ) ; unsigned AndReg = fastEmitInst_rr ( Opc [ <NUM_LIT> ] , RC , CmpReg , false , LHSReg , LHSIsKill ) ; unsigned AndNReg = fastEmitInst_rr ( Opc [ <NUM_LIT> ] , RC , CmpReg , true , RHSReg , RHSIsKill ) ; ResultReg = fastEmitInst_rr ( Opc [ <NUM_LIT> ] , RC , AndNReg , true , AndReg , true ) ; } updateValueMap ( I , ResultReg ) ; return true ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerTRUNCATEVector ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) . isVector ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; unsigned SrcSize = N1 . getValueType ( ) . getSizeInBits ( ) ; assert ( SrcSize <= <NUM_LIT> && <STR_LIT> ) ; SDValue WideSrc = SrcSize == <NUM_LIT> ? N1 : widenVec ( DAG , N1 , DL ) ; EVT TrgVT = Op . getValueType ( ) ; unsigned TrgNumElts = TrgVT . getVectorNumElements ( ) ; EVT EltVT = TrgVT . getVectorElementType ( ) ; unsigned WideNumElts = <NUM_LIT> / EltVT . getSizeInBits ( ) ; EVT WideVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , WideNumElts ) ; unsigned SizeMult = SrcSize / TrgVT . getSizeInBits ( ) ;

SmallVector < int , <NUM_LIT> > ShuffV ;


<s> const <ISA_LIT>RegisterInfo * <ISA_LIT>RI = Subtarget -> getRegisterInfo ( ) ; TargetLowering :: AsmOperandInfoVector TargetConstraints = ParseConstraints ( MF . getDataLayout ( ) , Subtarget -> getRegisterInfo ( ) , * CI ) ; for ( auto & TC : TargetConstraints ) { if ( TC . Type == InlineAsm :: isOutput ) { ComputeConstraintToUse ( TC , SDValue ( ) ) ; unsigned AssignedReg ; const TargetRegisterClass * RC ; std :: tie ( AssignedReg , RC ) = getRegForInlineAsmConstraint ( <ISA_LIT>RI , TC . ConstraintCode , TC . ConstraintVT ) ; if ( RC ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( AssignedReg != <NUM_LIT> && <ISA_LIT>RI -> isSGPRReg ( MRI , AssignedReg ) ) return true ;

else if ( <ISA_LIT>RI -> isSGPRClass ( RC ) ) return true ;


<s> IsLittleEndian = false ; StackGrowsUp = false ; SupportsDebugInformation = true ; AlignmentIsInBytes = false ; PrivateGlobalPrefix = <STR_LIT> ;


<s> TPLo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPLo ) ; SDValue TPHiShifted = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHi , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , TPHiShifted , TPLo ) ;


<s> static bool sh_cannot_modify_jumps_p ( void ) { return ( TARGET_SHMEDIA && ( reload_in_progress || reload_completed ) ) ;


<s> if ( const MCUnaryExpr * UnExpr = dyn_cast < MCUnaryExpr > ( Expr ) ) { if ( UnExpr -> getOpcode ( ) == MCUnaryExpr :: Minus ) { Inst . addOperand ( MCOperand :: createExpr ( UnExpr -> getSubExpr ( ) ) ) ; return ; } } else if ( const MCBinaryExpr * BinExpr = dyn_cast < MCBinaryExpr > ( Expr ) ) { if ( BinExpr -> getOpcode ( ) == MCBinaryExpr :: Sub ) { const MCExpr * NE = MCBinaryExpr :: createSub ( BinExpr -> getRHS ( ) , BinExpr -> getLHS ( ) , Ctx ) ; Inst . addOperand ( MCOperand :: createExpr ( NE ) ) ;


<s> bool <ISA_LIT>16FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { return true ;


<s> const auto * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getSubtarget ( ) . getRegisterInfo ( ) ) ; const auto * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const auto & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; int FPOffset = getFPOffset ( MF , ObjectOffset ) . getBytes ( ) ; int Offset = getStackOffset ( MF , ObjectOffset ) . getBytes ( ) ; bool isCSR = ! isFixed && ObjectOffset >= - ( ( int ) AFI -> getCalleeSavedStackSize ( ) ) ; const StackOffset & SVEStackSize = getSVEStackSize ( MF ) ; bool UseFP = false ; if ( AFI -> hasStackFrame ( ) && ! isSVE ) { PreferFP &= ! SVEStackSize ; if ( isFixed ) { UseFP = hasFP ( MF ) ; } else if ( isCSR && RegInfo -> needsStackRealignment ( MF ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; UseFP = true ; } else if ( hasFP ( MF ) && ! RegInfo -> needsStackRealignment ( MF ) ) { bool FPOffsetFits = ! ForSimm || FPOffset >= - <NUM_LIT> ; PreferFP |= Offset > - FPOffset ; if ( MFI . hasVarSizedObjects ( ) ) { bool CanUseBP = RegInfo -> hasBasePointer ( MF ) ; if ( FPOffsetFits && CanUseBP ) UseFP = PreferFP ; else if ( ! CanUseBP ) { assert ( ! SVEStackSize && <STR_LIT> ) ; UseFP = true ; } } else if ( FPOffset >= <NUM_LIT> ) { UseFP = true ; } else if ( MF . hasEHFunclets ( ) && ! RegInfo -> hasBasePointer ( MF ) ) { ( void ) Subtarget ; assert ( Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) && <STR_LIT> ) ; UseFP = true ; } else { if ( FPOffsetFits && PreferFP ) UseFP = true ; } }


<s> case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Half = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue HalfGPRs = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Half ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , HalfGPRs . getValue ( <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Arg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } SDValue fmrrd = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , & Arg , <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; VA = RVLocs [ ++ i ] ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , fmrrd . getValue ( <NUM_LIT> ) , Flag ) ; } else Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Arg , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; }


<s> if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Chain , TGA } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; } SDValue Flag = Chain . getValue ( <NUM_LIT> ) ; return DAG . getCopyFromReg ( Chain , dl , ReturnReg , PtrVT , Flag ) ;


<s> TheModule = & M ; FrameEscape = <STR_LIT> ( TheModule , <STR_LIT> ) ; FrameRecover = <STR_LIT> ( TheModule , <STR_LIT> ) ;

FrameAddress = <STR_LIT> ( TheModule , <STR_LIT> ) ;


<s> if ( VT == <STR_LIT> ) Mask = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , Mask ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; else Tmp0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp0 ) ; if ( SrcVT == <STR_LIT> ) { Tmp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp1 ) ; if ( VT == <STR_LIT> ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else if ( VT == <STR_LIT> ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp1 ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Tmp0 = DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp0 ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 ) ; SDValue AllOnes = DAG . getTargetConstant ( <STR_LIT> ( <NUM_LIT> , <NUM_LIT> ) , <STR_LIT> ) ; AllOnes = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AllOnes ) ; SDValue MaskNot = DAG . getNode ( <STR_LIT> , dl , OpVT , Mask , DAG . getNode ( <STR_LIT> , dl , OpVT , AllOnes ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp1 , Mask ) , DAG . getNode ( <STR_LIT> , dl , OpVT , Tmp0 , MaskNot ) ) ; if ( VT == <STR_LIT> ) { Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res ) ; }


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < MachineLoopInfo > ( ) ;

AU . addPreserved < MachineLoopInfo > ( ) ;


<s> static inline bool pdp11_saved_regno ( unsigned regno ) { return ! call_used_regs [ regno ] && df_regs_ever_live_p ( regno ) ;


<s> Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> std :: string BTFTypeStruct :: getName ( ) { return std :: string ( STy -> getName ( ) ) ;


<s> vec_uchar16 hihi_promote = ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; vec_uint4 biteq ; vec_uint4 aabs ; vec_uint4 babs ; vec_uint4 a_gt ; vec_uint4 ahi_inf ; vec_uint4 anan ; vec_uint4 iszero ; vec_uint4 result ; union { vec_uchar16 v ; int i [ <NUM_LIT> ] ; } x ; x . i [ <NUM_LIT> ] = <NUM_LIT> << <NUM_LIT> ; biteq = ( vec_uint4 ) vec_cmpeq ( ( vec_uint4 ) a , ( vec_uint4 ) b ) ; biteq = vec_and ( biteq , ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) biteq , x . v ) ) ; aabs = vec_and ( ( vec_uint4 ) a , sign_mask ) ; babs = vec_and ( ( vec_uint4 ) b , sign_mask ) ; a_gt = ( vec_uint4 ) vec_cmpgt ( aabs , nan_mask ) ; ahi_inf = ( vec_uint4 ) vec_cmpeq ( aabs , nan_mask ) ; anan = ( vec_uint4 ) vec_or ( a_gt , vec_and ( ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) a_gt , x . v ) , ahi_inf ) ) ; iszero = ( vec_uint4 ) vec_cmpeq ( ( vec_uint4 ) vec_or ( aabs , babs ) , ( vec_uint4 ) vec_splat_u32 ( <NUM_LIT> ) ) ; iszero = vec_and ( iszero , ( vec_uint4 ) vec_slo ( ( vec_uchar16 ) iszero , x . v ) ) ; result = vec_or ( biteq , iszero ) ;


<s> return K == <NUM_LIT> ? LaneBitmask :: getAll ( ) : get ( K ) ;


<s> GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; if ( RelocM == Reloc :: PIC_ ) { bool UseGOTOFF = GV -> hasLocalLinkage ( ) || GV -> hasHiddenVisibility ( ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <STR_LIT> , UseGOTOFF ? <STR_LIT> : <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , NULL , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , NULL , <NUM_LIT> ) ; return Result ; } else { SDValue CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , NULL , <NUM_LIT> ) ; }


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , getDataLayoutString ( TT ) , TT , CPU , computeFSAdditions ( FS , OL , TT ) , Options , getEffectiveRelocModel ( TT , RM ) , getEffective<ISA_LIT>CodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , TargetABI ( computeTargetABI ( TT , Options ) ) , Endianness ( isLittleEndianTriple ( TT ) ? Endian :: LITTLE : Endian :: BIG ) { initAsmInfo ( ) ;


<s> int __gthr_win32_setspecific ( __gthread_key_t key , const void * ptr ) { return ( TlsSetValue ( key , ( void * ) ptr ) != <NUM_LIT> ) ? <NUM_LIT> : ( int ) GetLastError ( ) ;


<s> machine_mode mode ; int unsigned_p ; while ( POINTER_TYPE_P ( type ) || TREE_CODE ( type ) == FUNCTION_TYPE || TREE_CODE ( type ) == METHOD_TYPE || TREE_CODE ( type ) == ARRAY_TYPE ) type = TREE_TYPE ( type ) ; mode = TYPE_MODE ( type ) ; unsigned_p = TYPE_UNSIGNED ( type ) ; switch ( mode ) { case E_DImode : result = ( unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node ) ; break ; case E_SImode : result = ( unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node ) ; break ; case E_HImode : result = ( unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node ) ; break ; case E_QImode : result = ( unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node ) ; break ; case E_SFmode : result = V4SF_type_node ; break ; case E_DFmode : result = V2DF_type_node ; break ; default : break ; } if ( result && result != type && TYPE_QUALS ( type ) ) result = build_qualified_type ( result , TYPE_QUALS ( type ) ) ; * no_add_attrs = true ;

if ( ! result ) warning ( <NUM_LIT> , <STR_LIT> , name ) ;


<s> unsigned Count = CSI . size ( ) ; ( void ) CC ; assert ( ( ! produceCompactUnwindFrame ( MF ) || CC == CallingConv :: PreserveMost || ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; int ByteOffset = AFI -> getCalleeSavedStackSize ( ) ; int ScalableByteOffset = AFI -> getSVECalleeSavedStackSize ( ) ; bool FixupDone = false ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { RegPairInfo RPI ; RPI . Reg1 = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: GPR ; else if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: FPR64 ; else if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: FPR128 ; else if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: ZPR ; else if ( <STR_LIT> . contains ( RPI . Reg1 ) ) RPI . Type = RegPairInfo :: PPR ; else llvm_unreachable ( <STR_LIT> ) ; if ( i + <NUM_LIT> < Count ) { unsigned NextReg = CSI [ i + <NUM_LIT> ] . getReg ( ) ; switch ( RPI . Type ) { case RegPairInfo :: GPR : if ( <STR_LIT> . contains ( NextReg ) && ! invalidateRegisterPairing ( RPI . Reg1 , NextReg , IsWindows , NeedsWinCFI , NeedsFrameRecord ) ) RPI . Reg2 = NextReg ; break ; case RegPairInfo :: FPR64 : if ( <STR_LIT> . contains ( NextReg ) && ! invalidateWindowsRegisterPairing ( RPI . Reg1 , NextReg , NeedsWinCFI ) ) RPI . Reg2 = NextReg ; break ; case RegPairInfo :: FPR128 : if ( <STR_LIT> . contains ( NextReg ) ) RPI . Reg2 = NextReg ; break ; case RegPairInfo :: PPR : case RegPairInfo :: ZPR : break ; } } if ( ( RPI . Reg1 == <STR_LIT> || RPI . Reg2 == <STR_LIT> ) && MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ) { if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( <NUM_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; NeedShadowCallStackProlog = true ;


<s> bool isXchg ( unsigned i ) const { return ! p [ i ] ; } bool isPush ( unsigned i ) const { return p [ i ] ; } unsigned countXchgs ( ) const { return llvm :: count ( p , false ) ; } unsigned countPushes ( ) const { return llvm :: count ( p , true ) ; } unsigned code ( ) const { return ( ( p [ <NUM_LIT> ] ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( p [ <NUM_LIT> ] ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( p [ <NUM_LIT> ] ? <NUM_LIT> : <NUM_LIT> ) ; } std :: string codeName ( ) const { std :: ostringstream Oss ; for ( bool IsPush : p ) Oss << ( IsPush ? <STR_LIT> : <STR_LIT> ) ; return Oss . str ( ) ; } bool p [ <NUM_LIT> ] ; unsigned args [ <NUM_LIT> ] ; } ; struct xchg3 : tripleChange { xchg3 ( unsigned i , unsigned j , unsigned k ) : tripleChange ( false , false , false , i , j , k ) {


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( & IfConverterID ) ; if ( ! DisableQPXLoadSplat ) addPass ( create<ISA_LIT>QPXLoadSplatPass ( ) ) ; }


<s> } } break ; } case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { case <STR_LIT> : { MachineSDNode * TLSBase = CurDAG -> getMachineNode ( GlobalGetIns , DL , PtrVT , <STR_LIT> , CurDAG -> getTargetExternalSymbol ( <STR_LIT> , PtrVT ) , Node -> getOperand ( <NUM_LIT> ) ) ; ReplaceNode ( Node , TLSBase ) ; return ; } } break ; } case <STR_LIT> : case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( size_t i = <NUM_LIT> ; i < Node -> getNumOperands ( ) ; ++ i ) { SDValue Op = Node -> getOperand ( i ) ; if ( i == <NUM_LIT> && Op -> getOpcode ( ) == <STR_LIT> ) Op = Op -> getOperand ( <NUM_LIT> ) ; Ops . push_back ( Op ) ; } Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; MachineSDNode * CallParams = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ; unsigned Results = Node -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Link ( CallParams , <NUM_LIT> ) ; MachineSDNode * CallResults = CurDAG -> getMachineNode ( Results , DL , Node -> getVTList ( ) , Link ) ; ReplaceNode ( Node , CallResults ) ; return ;


<s> void <ISA_LIT>AsmBackend :: relaxForImmediate ( MCInst & Inst , const MCSubtargetInfo & STI ) { while ( visitRelaxableOperand ( Inst , STI , [ & Inst ] ( const MCOperand & Operand , unsigned RelaxTo , bool BankRelax ) { int64_t Imm ; if ( ! Operand . evaluateAsConstantImm ( Imm ) || ( Imm >= <NUM_LIT> && Imm <= ( BankRelax ? UINT16_MAX : UCHAR_MAX ) ) ) {


<s> void <ISA_LIT>InstPrinter :: printBDVAddrOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { printAddress ( MI -> getOperand ( OpNum ) . getReg ( ) , MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) , MI -> getOperand ( OpNum + <NUM_LIT> ) . getReg ( ) , O ) ;


<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> :


<s> TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; }


<s> GPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinGPR ) { MinGPR = Reg ; } } else if ( RC == <STR_LIT> ) { HasG8SaveArea = true ; G8Regs . push_back ( CSI [ i ] ) ; if ( Reg < MinG8R ) { MinG8R = Reg ; } } else if ( RC == <STR_LIT> ) { HasFPSaveArea = true ; FPRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinFPR ) { MinFPR = Reg ; } } else if ( RC == <STR_LIT> || RC == <STR_LIT> ) { } else if ( RC == <STR_LIT> ) { HasVRSAVESaveArea = true ; } else if ( RC == <STR_LIT> ) { HasVRSaveArea = true ; VRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( PerformTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound = TCSPDelta ; } if ( HasFPSaveArea ) { for ( unsigned i = <NUM_LIT> , e = FPRegs . size ( ) ; i != e ; ++ i ) { int FI = FPRegs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } LowerBound -= ( <NUM_LIT> - getRegisterNumbering ( MinFPR ) + <NUM_LIT> ) * <NUM_LIT> ; } if ( needsFP ( MF ) ) { HasGPSaveArea = true ; int FI = PFI -> getFramePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ;


<s> void <ISA_LIT>InstPrinter :: printPCDMem ( const MCInst * MI , uint64_t Address , unsigned opNum , raw_ostream & O ) { O << '(' ; printDisp ( MI , opNum + <STR_LIT> , O ) ; O << <STR_LIT> ;


<s> Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ;


<s> case TargetStackID :: ScalableVector : return true ; case TargetStackID :: NoAlloc : case TargetStackID :: SGPRSpill : return false ; }


<s> Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; Inst . addOperand ( MCOperand :: createImm ( Hint ) ) ;


<s> if ( Occupancy >= MFI -> getMinAllowedOccupancy ( ) && MaxPressure . getVGPRNum ( ) <= MaxVGPRs && MaxPressure . getSGPRNum ( ) <= MaxSGPRs ) {


<s> if ( ( IsTex && ! TII -> usesTextureCache ( I ) ) || ( ! IsTex && ! TII -> usesVertexCache ( I ) ) ) break ; if ( ! isCompatibleWithClause ( I , DstRegs ) ) break ; AluInstCount ++ ; ClauseContent . push_back ( I ) ; } MachineInstr * MIb = BuildMI ( MBB , ClauseHead , MBB . findDebugLoc ( ClauseHead ) , getHWInstrDesc ( IsTex ? CF_TC : CF_VC ) ) . addImm ( <NUM_LIT> ) . addImm ( AluInstCount - <NUM_LIT> ) ; return ClauseFile ( MIb , std :: move ( ClauseContent ) ) ;


<s> unsigned NopSize ; unsigned Opc , BaseReg , ScaleVal , IndexReg , Displacement , SegmentReg ; Opc = IndexReg = Displacement = SegmentReg = <NUM_LIT> ; BaseReg = <STR_LIT> ; ScaleVal = <NUM_LIT> ; switch ( NumBytes ) { case <NUM_LIT> : llvm_unreachable ( <STR_LIT> ) ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; case <NUM_LIT> : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; break ; default : NopSize = <NUM_LIT> ; Opc = <STR_LIT> ; Displacement = <NUM_LIT> ; IndexReg = <STR_LIT> ; SegmentReg = <STR_LIT> ; break ; } unsigned NumPrefixes = std :: min ( NumBytes - NopSize , <NUM_LIT> ) ; NopSize += NumPrefixes ; for ( unsigned i = <NUM_LIT> ; i != NumPrefixes ; ++ i ) OS . EmitBytes ( <STR_LIT> ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> :

OS . EmitInstruction ( MCInstBuilder ( Opc ) , STI ) ;


<s> * __carry_out = ( __builtin_arm_get_fpscr_nzcvqc ( ) >> <NUM_LIT> ) & <NUM_LIT> ;


<s> void addRegOrImmOperands ( MCInst & Inst , unsigned N ) const {

if ( isReg ( ) ) addRegOperands ( Inst , N ) ;


<s> MCAsmLexer & getLexer ( ) const { return Parser . getLexer ( ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _addcarry_u64 ( unsigned char __CF , unsigned long long __X , unsigned long long __Y , unsigned long long * __P ) {


<s> bool AMDGPUAsmParser :: ParseDirective ( AsmToken DirectiveID ) {


<s> p [ i ] = ( unsigned char ) vp ; vp >>= <NUM_LIT> ; }


<s> LLT Ty = MRI . getType ( Reg ) ; MachineIRBuilder B ( MI ) ; if ( Bank != & <STR_LIT> ) { Reg = B . buildCopy ( Ty , Reg ) . getReg ( <NUM_LIT> ) ; MRI . setRegBank ( Reg , <STR_LIT> ) ; } Register SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( SGPR ) . addReg ( Reg ) ; MRI . setType ( SGPR , Ty ) ;

const TargetRegisterClass * Constrained = constrainGenericRegister ( Reg , <STR_LIT> , MRI ) ;


<s> static SDValue LowerPredicateLoad ( SDValue Op , SelectionDAG & DAG ) { LoadSDNode * LD = cast < LoadSDNode > ( Op . getNode ( ) ) ; EVT MemVT = LD -> getMemoryVT ( ) ; assert ( ( MemVT == <STR_LIT> || MemVT == <STR_LIT> || MemVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( MemVT == Op . getValueType ( ) ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( LD -> isUnindexed ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Load = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , LD -> getChain ( ) , LD -> getBasePtr ( ) , EVT :: getIntegerVT ( * DAG . getContext ( ) , MemVT . getSizeInBits ( ) ) , LD -> getMemOperand ( ) ) ; SDValue Pred = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) ; if ( MemVT != <STR_LIT> ) Pred = DAG . getNode ( <STR_LIT> , dl , MemVT , Pred , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;

return DAG . getMergeValues ( { Pred , Load . getValue ( <NUM_LIT> ) } , dl ) ;


<s> SDValue In = Op . getOperand ( <NUM_LIT> ) ; MVT InVT = In . getSimpleValueType ( ) ; if ( VT == <STR_LIT> ) { assert ( ( InVT . isInteger ( ) && ( InVT . getSizeInBits ( ) <= <NUM_LIT> ) ) && <STR_LIT> ) ; if ( InVT . getSizeInBits ( ) >= <NUM_LIT> ) return SDValue ( ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; } assert ( VT . getVectorNumElements ( ) == InVT . getVectorNumElements ( ) && <STR_LIT> ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return LowerTruncateVecI1 ( Op , DAG , Subtarget ) ; if ( Subtarget . hasAVX512 ( ) ) { if ( InVT == <STR_LIT> && ! Subtarget . hasBWI ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , getExtendInVec ( <STR_LIT> , DL , <STR_LIT> , In , DAG ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In ) ; } if ( InVT . getScalarSizeInBits ( ) == DAG . ComputeNumSignBits ( In ) ) if ( SDValue V = truncateVectorCompareWithPACKSS ( VT , In , DL , DAG , Subtarget ) ) return V ; if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget . hasInt256 ( ) ) { static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getBitcast ( <STR_LIT> , In ) ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask ) ; return DAG . getNode ( <STR_LIT> , DL , VT , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , DL , OpLo , OpHi , ShufMask ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget . hasInt256 ( ) ) {


<s> virtual const <ISA_LIT>BaseInstrInfo * getInstrInfo ( ) const {


<s> void addUImm2Operands ( MCInst & Inst , unsigned N ) const {


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; useGOT = <NUM_LIT> ; TLSOffset = nullptr ;


<s> if ( Modifier && strncmp ( Modifier , <STR_LIT> , strlen ( <STR_LIT> ) ) == <NUM_LIT> ) { unsigned Size = ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <NUM_LIT> : ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <NUM_LIT> : ( strcmp ( Modifier + <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;

Reg = get<ISA_LIT>SubSuperRegister ( Reg , Size ) ;


<s> void <ISA_LIT>Shuffler :: restrictPreferSlot3 ( <ISA_LIT>PacketSummary const & Summary ) { const bool HasOnlySlot3 = llvm :: any_of ( insts ( ) , [ & ] ( <ISA_LIT>Instr const & I ) { return ( I . Core . getUnits ( ) == Slot3Mask ) ; } ) ; const bool NeedsPrefSlot3Shuffle = ( Summary . branchInsts . size ( ) <= <NUM_LIT> && ! HasOnlySlot3 && Summary . pSlot3Cnt == <NUM_LIT> && Summary . PrefSlot3Inst ) ; if ( ! NeedsPrefSlot3Shuffle ) return ; <ISA_LIT>Instr * PrefSlot3Inst = * Summary . PrefSlot3Inst ; const unsigned saveUnits = PrefSlot3Inst -> Core . getUnits ( ) ; PrefSlot3Inst -> Core . setUnits ( saveUnits & Slot3Mask ) ; const bool HasShuffledPacket = tryAuction ( Summary ) . hasValue ( ) ;


<s> assert ( ( N == <NUM_LIT> ) && <STR_LIT> ) ; if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getMemDisp ( ) ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ;

else Inst . addOperand ( MCOperand :: CreateExpr ( getMemDisp ( ) ) ) ;


<s> if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ? ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) : ( is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ;

BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> Inst . setOpcode ( <STR_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( imm ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( imm ) ) ) ;


<s> return ( uint16x8_t ) __builtin_neon_vreinterpretv8hiv8hi ( __a ) ;


<s> switch ( IntrData -> Type ) { case LOADA : case LOADU : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( I . getType ( ) ) ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = ( IntrData -> Type == LOADA ? Info . memVT . getSizeInBits ( ) / <NUM_LIT> : <NUM_LIT> ) ;


return ( STI . getFeatureBits ( ) & <STR_LIT> ) ;


<s> if ( Acc < <NUM_LIT> ) { unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc && <STR_LIT> ) ; int Val = ( TotalSize == <NUM_LIT> ) ? int16_t ( Acc ) : int ( Acc ) ; const MCInstrDesc & StD = TII -> get ( WOpc ) ; MachineOperand & MR = FirstSt -> getOperand ( <NUM_LIT> ) ; int64_t Off = FirstSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * StI = BuildMI ( * MF , DL , StD ) . addReg ( MR . getReg ( ) , getKillRegState ( MR . isKill ( ) ) , MR . getSubReg ( ) ) . addImm ( Off ) . addImm ( Val ) ; StI -> addMemOperand ( * MF , NewM ) ; NG . push_back ( StI ) ; } else { const MCInstrDesc & TfrD = TII -> get ( <STR_LIT> ) ; const TargetRegisterClass * RC = TII -> getRegClass ( TfrD , <NUM_LIT> , TRI , * MF ) ; unsigned VReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * TfrI = BuildMI ( * MF , DL , TfrD , VReg ) . addImm ( int ( Acc ) ) ; NG . push_back ( TfrI ) ; unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ;


<s> if ( isCPEntryInRange ( UserMI , UserOffset , CPE . CPEMI , U . getMaxDisp ( ) , U . NegOk ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPE . CPI << <STR_LIT> ) ; U . CPEMI = CPE . CPEMI ; for ( MachineOperand & MO : UserMI -> operands ( ) ) if ( MO . isCPI ( ) ) { MO . setIndex ( CPE . CPI ) ; break ; }


<s> if ( SecName . startswith ( <STR_LIT> ) ) visitMapDefType ( DIGlobal -> getType ( ) , GVTypeId ) ; else visitTypeEntry ( DIGlobal -> getType ( ) , GVTypeId , false , false ) ; break ; } auto Linkage = Global . getLinkage ( ) ; if ( Linkage != GlobalValue :: InternalLinkage && Linkage != GlobalValue :: ExternalLinkage && Linkage != GlobalValue :: WeakAnyLinkage && Linkage != GlobalValue :: WeakODRLinkage && Linkage != GlobalValue :: ExternalWeakLinkage ) continue ; uint32_t GVarInfo ; if ( Linkage == GlobalValue :: InternalLinkage ) { GVarInfo = <STR_LIT> ; } else if ( Global . hasInitializer ( ) ) { GVarInfo = <STR_LIT> ; } else { GVarInfo = <STR_LIT> ; } auto VarEntry = std :: make_unique < BTFKindVar > ( Global . getName ( ) , GVTypeId , GVarInfo ) ; uint32_t VarId = addType ( std :: move ( VarEntry ) ) ; processDeclAnnotations ( DIGlobal -> getAnnotations ( ) , VarId , - <NUM_LIT> ) ; if ( SecName . empty ( ) ) continue ;

if ( DataSecEntries . find ( std :: string ( SecName ) ) == DataSecEntries . end ( ) ) {


<s> if ( ! Disp . isImm ( ) ) return false ; if ( Scale . getImm ( ) != <NUM_LIT> ) return false ; if ( ! ( Index . isReg ( ) && Index . getReg ( ) == <STR_LIT> ) ) return false ; if ( ! ( Segment . isReg ( ) && Segment . getReg ( ) == <STR_LIT> ) ) return false ; return true ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_EXTEND ( SDValue Op , SelectionDAG & DAG ) const { if ( Op . getValueType ( ) . isScalableVector ( ) ) return LowerToPredicatedOp ( Op , DAG , <STR_LIT> ) ; assert ( Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; RTLIB :: Libcall LC ; LC = RTLIB :: getFPEXT ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;

return LowerF128Call ( Op , DAG , LC ) ;


<s> for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ;


<s> rtx_insn * insn , * insns [ <NUM_LIT> ] ; FOR_BB_INSNS ( bb , insn ) { if ( avr_is_casesi_sequence ( bb , insn , insns ) ) { avr_optimize_casesi ( insns , recog_data . operand ) ; } }


<s> MCOperand <ISA_LIT>Disassembler :: decodeMandatoryLiteralConstant ( unsigned Val ) const { if ( HasLiteral ) {

if ( Literal != Val ) return errOperand ( Val , <STR_LIT> ) ;


<s> <ISA_LIT>BlockPlacement ( ) : MachineFunctionPass ( ID ) {


<s> static inline unsigned GetCondBranchFromCond ( <STR_LIT> CC ) { switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> Op2 = constrainOperandRegClass ( II , Op2 , II . getNumDefs ( ) + <NUM_LIT> ) ; Op3 = constrainOperandRegClass ( II , Op3 , II . getNumDefs ( ) + <NUM_LIT> ) ; if ( II . getNumDefs ( ) >= <NUM_LIT> ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , ResultReg ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) . addReg ( Op1 , getKillRegState ( Op1IsKill ) ) . addReg ( Op2 , getKillRegState ( Op2IsKill ) ) . addReg ( Op3 , getKillRegState ( Op3IsKill ) ) ; else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) . addReg ( Op1 , getKillRegState ( Op1IsKill ) ) . addReg ( Op2 , getKillRegState ( Op2IsKill ) ) . addReg ( Op3 , getKillRegState ( Op3IsKill ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ; } return ResultReg ;


<s> if ( isPowerOf2_64 ( MulAmt2 ) && ! ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ; if ( isPowerOf2_64 ( MulAmt1 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( MulAmt1 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MulAmt1 , DL , VT ) ) ; if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( MulAmt2 , DL , VT ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewMul ) ; } else if ( ! Subtarget . slowLEA ( ) ) NewMul = combineMulSpecial ( C -> getZExtValue ( ) , N , DAG , VT , DL ) ; if ( ! NewMul ) { assert ( C -> getZExtValue ( ) != <NUM_LIT> && C -> getZExtValue ( ) != ( VT == <STR_LIT> ? UINT64_MAX : UINT32_MAX ) && <STR_LIT> <STR_LIT> ) ; if ( isPowerOf2_64 ( AbsMulAmt - <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewMul ) ; } else if ( isPowerOf2_64 ( AbsMulAmt + <NUM_LIT> ) ) { NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( AbsMulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) ;

if ( SignMulAmt < <NUM_LIT> ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , NewMul ) ;


<s> const Function * F = MF . getFunction ( ) ; std :: string FuncName = F -> getName ( ) ; ResetTmpOffsetMap ( ) ; InitReservedFrameCount ( F ) ; const char * tmpName = createESName ( PAN :: getArgsLabel ( FuncName ) ) ; SDValue ES = DAG . getTargetExternalSymbol ( tmpName , <STR_LIT> ) ;

SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;


<s> } if ( Info . hasKernargSegmentPtr ( ) ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; Register InputPtrReg = Info . addKernargSegmentPtr ( TRI ) ; const LLT P4 = LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ; Register VReg = MRI . createGenericVirtualRegister ( P4 ) ; MRI . addLiveIn ( InputPtrReg , VReg ) ; B . getMBB ( ) . addLiveIn ( InputPtrReg ) ; B . buildCopy ( VReg , InputPtrReg ) ; CCInfo . AllocateReg ( InputPtrReg ) ; } if ( Info . hasDispatchID ( ) ) {

Register DispatchIDReg = Info . addDispatchID ( TRI ) ;


<s> static bool canDemoteGlobalVar ( const GlobalVariable * gv , Function const * & f ) { if ( gv -> hasInternalLinkage ( ) == false ) return false ; const PointerType * Pty = gv -> getType ( ) ; if ( Pty -> getAddressSpace ( ) != llvm :: ADDRESS_SPACE_SHARED ) return false ; const Function * oneFunc = nullptr ;

bool flag = usedInOneFunc ( gv , oneFunc ) ;


<s> const double sin ( double x ) { double value ;

__asm ( <STR_LIT> : <STR_LIT> ( value ) : <STR_LIT> ( x ) ) ;


<s> void <ISA_LIT>Operand :: addMoveMaskOperands ( MCInst & Inst , unsigned N ) const { assert ( isMoveMask ( ) && <STR_LIT> ) ; assert ( ( N == <NUM_LIT> ) && <STR_LIT> ) ; uint16_t MoveMask = MemOp . RegMask ;

if ( MemOp . Op == <STR_LIT> :: Reg ) MoveMask = <NUM_LIT> << getRegisterIndex ( MemOp . OuterReg ) ;


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const {


<s> <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , TargetTriple ( TT ) , Gen ( SOUTHERN_ISLANDS ) , IsaVersion ( ISAVersion0_0_0 ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , VIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasR128A16 ( false ) , HasDLInsts ( false ) , D16PreservesUnusedBits ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ; RegBankInfo . reset ( new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ) ; InstSelector . reset ( new <ISA_LIT>InstructionSelector ( * this , * static_cast < <ISA_LIT>RegisterBankInfo * > ( RegBankInfo . get ( ) ) , TM ) ) ;


<s> static DecodeStatus decodeU8ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler * Decoder ) {

return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm ) ;


<s> unsigned NewVReg = MRI -> createVirtualRegister ( DstRC ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( NewVReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; auto InsertPoint = ++ MachineBasicBlock :: iterator ( MI ) ; if ( DstRC == & <STR_LIT> ) { unsigned VSRCTmp1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; unsigned VSRCTmp2 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , InsertPoint , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , VSRCTmp1 ) . addReg ( NewVReg ) ; DEBUG ( std :: prev ( InsertPoint ) -> dump ( ) ) ; insertSwap ( MI , InsertPoint , VSRCTmp2 , VSRCTmp1 ) ; DEBUG ( std :: prev ( InsertPoint ) -> dump ( ) ) ; BuildMI ( * MI -> getParent ( ) , InsertPoint , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( VSRCTmp2 ) ; DEBUG ( std :: prev ( InsertPoint ) -> dump ( ) ) ;


<s> error ( <STR_LIT> ) ; return has_target_p ? gen_reg_rtx ( ops [ <NUM_LIT> ] . mode ) : const0_rtx ; }

return has_target_p ? ops [ <NUM_LIT> ] . value : const0_rtx ;


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Reg = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; unsigned Imm8 = MO1 . getImm ( ) ; return ( Reg << <NUM_LIT> ) | Imm8 ;


<s> if ( ! CONST_INT_P ( cpl ) ) { error_at ( EXPR_LOCATION ( exp ) , <STR_LIT> ) ; return const0_rtx ; } pred = gen_reg_rtx ( BImode ) ; if ( ! REG_P ( redop ) ) redop = copy_to_mode_reg ( SImode , redop ) ; emit_insn ( gen_rtx_SET ( pred , gen_rtx_NE ( BImode , redop , GEN_INT ( <NUM_LIT> ) ) ) ) ; redop = pred ; rtx pat ; switch ( code ) { case NVPTX_BUILTIN_BAR_RED_AND : dst = gen_reg_rtx ( BImode ) ; pat = gen_nvptx_barred_and ( dst , bar , nthr , cpl , redop ) ; break ; case NVPTX_BUILTIN_BAR_RED_OR : dst = gen_reg_rtx ( BImode ) ; pat = gen_nvptx_barred_or ( dst , bar , nthr , cpl , redop ) ; break ; case NVPTX_BUILTIN_BAR_RED_POPC : dst = gen_reg_rtx ( SImode ) ; pat = gen_nvptx_barred_popc ( dst , bar , nthr , cpl , redop ) ; break ; default : gcc_unreachable ( ) ; } emit_insn ( pat ) ; if ( GET_MODE ( dst ) == BImode ) { rtx tmp = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( tmp , gen_rtx_NE ( mode , dst , GEN_INT ( <NUM_LIT> ) ) ) ) ;


<s> unsigned <ISA_LIT>TTIImpl :: getCacheLineSize ( ) const {


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return <STR_LIT> ; return VT . changeVectorElementTypeToInteger ( ) ;


<s> if ( NumVecs == <NUM_LIT> ) RegSeq = SDValue ( createDRegPairNode ( <STR_LIT> , V0 , V1 ) , <NUM_LIT> ) ; else { SDValue V2 = N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( FirstTblReg + <NUM_LIT> ) ; RegSeq = SDValue ( createQuadDRegsNode ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; }

SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> const MachineOperand * M0Reg = TII -> getNamedOperand ( * I , AMDGPU :: OpName :: m0 ) ; unsigned DestReg0 = TII -> getNamedOperand ( * I , AMDGPU :: OpName :: vdst ) -> getReg ( ) ; unsigned DestReg1 = TII -> getNamedOperand ( * Paired , AMDGPU :: OpName :: vdst ) -> getReg ( ) ; unsigned Offset0 = TII -> getNamedOperand ( * I , AMDGPU :: OpName :: offset ) -> getImm ( ) & <NUM_LIT> ; unsigned Offset1 = TII -> getNamedOperand ( * Paired , AMDGPU :: OpName :: offset ) -> getImm ( ) & <NUM_LIT> ; unsigned NewOffset0 = Offset0 / EltSize ; unsigned NewOffset1 = Offset1 / EltSize ; unsigned Opc = ( EltSize == <NUM_LIT> ) ? AMDGPU :: DS_READ2_B32 : AMDGPU :: DS_READ2_B64 ; bool UseST64 = ( NewOffset0 % <NUM_LIT> == <NUM_LIT> ) && ( NewOffset1 % <NUM_LIT> == <NUM_LIT> ) ; if ( UseST64 ) { NewOffset0 /= <NUM_LIT> ; NewOffset1 /= <NUM_LIT> ; Opc = ( EltSize == <NUM_LIT> ) ? AMDGPU :: DS_READ2ST64_B32 : AMDGPU :: DS_READ2ST64_B64 ; } assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Read2Desc = TII -> get ( Opc ) ; const TargetRegisterClass * SuperRC = ( EltSize == <NUM_LIT> ) ? & AMDGPU :: VReg_64RegClass : & AMDGPU :: VReg_128RegClass ; unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; DebugLoc DL = I -> getDebugLoc ( ) ; MachineInstrBuilder Read2 = BuildMI ( * MBB , I , DL , Read2Desc , DestReg ) . addOperand ( * AddrReg ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addImm ( <NUM_LIT> ) . addOperand ( * M0Reg ) . addMemOperand ( * I -> memoperands_begin ( ) ) . addMemOperand ( * Paired -> memoperands_begin ( ) ) ; LIS -> InsertMachineInstrInMaps ( Read2 ) ; unsigned SubRegIdx0 = ( EltSize == <NUM_LIT> ) ? AMDGPU :: sub0 : AMDGPU :: sub0_sub1 ; unsigned SubRegIdx1 = ( EltSize == <NUM_LIT> ) ? AMDGPU :: sub1 : AMDGPU :: sub2_sub3 ; updateRegDefsUses ( DestReg0 , DestReg , SubRegIdx0 ) ; updateRegDefsUses ( DestReg1 , DestReg , SubRegIdx1 ) ; LIS -> RemoveMachineInstrFromMaps ( I ) ; LIS -> RemoveMachineInstrFromMaps ( Paired ) ;


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

if ( CC == CallingConv :: GHC ) return CSR_NoRegs_RegMask ;


<s> void printf64mem ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {


<s> DecodeVectorRegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeVectorRegisterClass ( Inst , Rd , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( ( cmode & <NUM_LIT> ) << <NUM_LIT> ) ) ;


<s> int i ; if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF ) return <NUM_LIT> ;

if ( GET_CODE ( x ) == UNSPEC && ( XINT ( x , <NUM_LIT> ) == UNSPEC_PIC || XINT ( x , <NUM_LIT> ) == UNSPEC_GOT || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTOFF || XINT ( x , <NUM_LIT> ) == UNSPEC_PLT || XINT ( x , <NUM_LIT> ) == UNSPEC_GOTSYM_OFF ) ) return <NUM_LIT> ;


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( isWave32 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned MaxNumAGPRs = MaxNumVGPRs ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ; if ( ST . hasGFX90AInsts ( ) ) { if ( MFI -> usesAGPRs ( MF ) ) { MaxNumVGPRs /= <NUM_LIT> ; MaxNumAGPRs = MaxNumVGPRs ; } else { if ( MaxNumVGPRs > TotalNumVGPRs ) { MaxNumAGPRs = MaxNumVGPRs - TotalNumVGPRs ; MaxNumVGPRs = TotalNumVGPRs ; } else MaxNumAGPRs = <NUM_LIT> ; } } for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } for ( unsigned i = MaxNumAGPRs ; i < TotalNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } for ( auto Reg : <STR_LIT> ) { Reserved . set ( getSubReg ( Reg , <STR_LIT> ) ) ; Register Low = getSubReg ( Reg , <STR_LIT> ) ; if ( ! <STR_LIT> . contains ( Low ) ) Reserved . set ( Low ) ; } for ( auto Reg : <STR_LIT> ) { Reserved . set ( getSubReg ( Reg , <STR_LIT> ) ) ; } if ( ! ST . hasMAIInsts ( ) ) { for ( unsigned i = <NUM_LIT> ; i < MaxNumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ;


<s> if ( fcode == AARCH64_BUILTIN_RNG_RNDR ) icode = CODE_FOR_aarch64_rndr ; else if ( fcode == AARCH64_BUILTIN_RNG_RNDRRS ) icode = CODE_FOR_aarch64_rndrrs ; else gcc_unreachable ( ) ; rtx rand = gen_reg_rtx ( DImode ) ; pat = GEN_FCN ( icode ) ( rand ) ; if ( ! pat ) return NULL_RTX ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx res_addr = expand_normal ( arg0 ) ; res_addr = convert_memory_address ( Pmode , res_addr ) ; rtx res_mem = gen_rtx_MEM ( DImode , res_addr ) ; emit_insn ( pat ) ;


<s> <ISA_LIT>64GNULDBackend :: <ISA_LIT>64GNULDBackend ( const LinkerConfig & pConfig , <ISA_LIT>GNUInfo * pInfo ) : <ISA_LIT>GNULDBackend ( pConfig , pInfo ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ; break ; } if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ;

Inst . addOperand ( MCOperand :: createImm ( shift ) ) ;


<s> static inline struct bpf_sock * bpf_sk_lookup_udp ( void * ctx , struct bpf_sock_tuple * tuple , int size , unsigned long long netns_id , unsigned long long flags ) {

return ( struct bpf_sock * ) __builtin_bpf_helper_sk_lookup_udp ( ctx , ( void * ) tuple , size , netns_id , flags ) ;


<s> std :: string cloneVarName = Var ; std :: string cloneFnName = getCloneFnName ( Fn ) ; cloneVarName . replace ( cloneVarName . find ( Fn ) , Fn . length ( ) , cloneFnName ) ;


__builtin_ia32_pmovswb128mem_mask ( ( unsigned long long * ) __P , ( __v8hi ) __A , __M ) ;


<s> src = simplify_gen_subreg ( move_mode , operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; dst = simplify_gen_subreg ( move_mode , operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; if ( ! rtx_equal_p ( dst , src ) ) { emit_move_insn ( dst , gen_rtx_XOR ( QImode , dst , src ) ) ; emit_move_insn ( src , gen_rtx_XOR ( QImode , src , dst ) ) ; emit_move_insn ( dst , gen_rtx_XOR ( QImode , dst , src ) ) ; } } else { struct { rtx src , dst ; int links ; } move [ MAX_SIZE + <NUM_LIT> ] ; int blocked , moves ; gcc_assert ( size <= MAX_SIZE ) ; for ( i = <NUM_LIT> ; i < size ; i ++ ) { int from = i ; int to = ( from + offset ) % size ; move [ i ] . src = simplify_gen_subreg ( move_mode , operands [ <NUM_LIT> ] , mode , from * move_size ) ; move [ i ] . dst = simplify_gen_subreg ( move_mode , operands [ <NUM_LIT> ] , mode , to * move_size ) ; move [ i ] . links = - <NUM_LIT> ; } if ( overlapped ) for ( i = <NUM_LIT> ; i < size ; i ++ ) if ( reg_overlap_mentioned_p ( move [ i ] . dst , operands [ <NUM_LIT> ] ) ) for ( j = <NUM_LIT> ; j < size ; j ++ ) if ( j != i && rtx_equal_p ( move [ j ] . src , move [ i ] . dst ) ) { move [ i ] . links = j ; break ; } blocked = - <NUM_LIT> ;


<s> if ( getRelaxedOpcodeBranch ( Inst , false ) != Inst . getOpcode ( ) ) return true ; if ( getRelaxedOpcodeArith ( Inst ) == Inst . getOpcode ( ) ) return false ; unsigned RelaxableOp = Inst . getNumOperands ( ) - <NUM_LIT> ; if ( Inst . getOperand ( RelaxableOp ) . isExpr ( ) ) return true ;


<s> return VectorIndex . Val < <NUM_LIT> ;


<s> void emitBasicBlockEnd ( const MachineBasicBlock & MBB ) override {


<s> if ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && ! Subtarget -> isX18Reserved ( ) ) Reg = <NUM_LIT> ; if ( Reg ) return Reg ;

report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ;


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const {


<s> static auto InitializeRegisterBankOnce = [ this ] ( ) { assert ( & getRegBank ( <STR_LIT> ) == & <STR_LIT> && & getRegBank ( <STR_LIT> ) == & <STR_LIT> && & getRegBank ( <STR_LIT> ) == & <STR_LIT> ) ;


<s> if ( Ins [ i ] . Flags . isByVal ( ) ) { EVT PtrTy = getPointerTy ( ) ; int Size = Ins [ i ] . Flags . getByValSize ( ) ; unsigned NumRegs = ( Size + <NUM_LIT> ) / <NUM_LIT> ; unsigned FrameIdx = MFI -> CreateFixedObject ( <NUM_LIT> * NumRegs , VA . getLocMemOffset ( ) , false ) ; SDValue FrameIdxN = DAG . getFrameIndex ( FrameIdx , PtrTy ) ; InVals . push_back ( FrameIdxN ) ; continue ; } if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; SDValue ArgValue ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> || RegVT . is64BitVector ( ) ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> || RegVT . is128BitVector ( ) ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: AExt : case CCValAssign :: SExt : case CCValAssign :: ZExt : assert ( RegVT == Ins [ i ] . VT && <STR_LIT> ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ArgOffset = VA . getLocMemOffset ( ) ; unsigned ArgSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ;


<s> static void extractValues ( IRBuilder < > & Builder , SmallVectorImpl < Value * > & Values , Value * V ) {

VectorType * VT = dyn_cast < VectorType > ( V -> getType ( ) ) ;


<s> do { computeInsertionPoint ( U -> User , U -> Op , InsertPts ) ; } while ( ++ U != E && U -> C == C ) ; auto & Promotion = PromotionCache [ C ] ; ensurePromotedGV ( F , * C , Promotion ) ; insertDefinitions ( F , * Promotion . GV , InsertPts ) ;


<s> TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int64_t TailCallReturnAddrDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MFI . CreateFixedObject ( - TailCallReturnAddrDelta , TailCallReturnAddrDelta - SlotSize , true ) ; } if ( TRI -> hasBasePointer ( MF ) ) { SavedRegs . set ( TRI -> getBaseRegister ( ) ) ; if ( MF . hasEHFunclets ( ) ) { int FI = MFI . CreateSpillStackObject ( SlotSize , SlotSize ) ; <ISA_LIT>FI -> setHasSEHFramePtrSave ( true ) ; <ISA_LIT>FI -> setSEHFramePtrSaveIndex ( FI ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: LowerEXTRACT_SUBVECTOR ( SDValue Op , SelectionDAG & DAG ) const { SmallVector < SDValue , <NUM_LIT> > Args ; unsigned Start = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getValueType ( ) ; DAG . ExtractVectorElements ( Op . getOperand ( <NUM_LIT> ) , Args , Start , VT . getVectorNumElements ( ) ) ; return DAG . getBuildVector ( Op . getValueType ( ) , SDLoc ( Op ) , Args ) ;


<s> static bool aarch64_use_by_pieces_infrastructure_p ( unsigned HOST_WIDE_INT size , unsigned int align , enum by_pieces_operation op , bool speed_p ) {

if ( op == STORE_BY_PIECES ) return false ;


<s> int getSEHRegNum ( unsigned i ) const {


<s> const std :: string & ConstraintsStr = IA -> getConstraintString ( ) ; SplitString ( StringRef ( ConstraintsStr ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; std :: sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } break ; case <NUM_LIT> : if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> && matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) { AsmPieces . clear ( ) ; const std :: string & ConstraintsStr = IA -> getConstraintString ( ) ; SplitString ( StringRef ( ConstraintsStr ) . substr ( <NUM_LIT> ) , AsmPieces , <STR_LIT> ) ; std :: sort ( AsmPieces . begin ( ) , AsmPieces . end ( ) ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } if ( CI -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) { InlineAsm :: ConstraintInfoVector Constraints = IA -> ParseConstraints ( ) ; if ( Constraints . size ( ) >= <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> && Constraints [ <NUM_LIT> ] . Codes . size ( ) == <NUM_LIT> && Constraints [ <NUM_LIT> ] . Codes [ <NUM_LIT> ] == <STR_LIT> ) { if ( matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> ) && matchAsm ( AsmPieces [ <NUM_LIT> ] , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ; } } break ;


<s> return build_pointer_type ( integer_type_node ) ;


<s> for ( unsigned oper = <NUM_LIT> ; oper < MI . getNumOperands ( ) ; ++ oper ) { MachineOperand MO = MI . getOperand ( oper ) ; if ( MO . isReg ( ) ) { if ( ! MO . isDef ( ) ) continue ; const TargetRegisterClass * RC = HRI . getMinimalPhysRegClass ( MO . getReg ( ) ) ; if ( RC == & <STR_LIT> ) { Pred . push_back ( MO ) ; return true ; } continue ; } else if ( MO . isRegMask ( ) ) { for ( unsigned PR : <STR_LIT> ) { if ( ! MI . modifiesRegister ( PR , & HRI ) ) continue ; Pred . push_back ( MO ) ;


<s> } else if ( ( word & <NUM_LIT> ) == <NUM_LIT> ) { lo = le_int ( region , address + <NUM_LIT> ) | uint64_t ( word ) << <NUM_LIT> ; } else if ( ( word & <NUM_LIT> ) == <NUM_LIT> ) { lo = le_short ( region , address + <NUM_LIT> ) << <NUM_LIT> | le_short ( region , address + <NUM_LIT> ) | uint64_t ( word ) << <NUM_LIT> ; } else if ( ( word & <NUM_LIT> ) == <NUM_LIT> ) { lo = le_short ( region , address + <NUM_LIT> ) << <NUM_LIT> | le_short ( region , address + <NUM_LIT> ) << <NUM_LIT> | le_short ( region , address + <NUM_LIT> ) << <NUM_LIT> | le_short ( region , address + <NUM_LIT> ) ; hi = word ;


<s> const LLT v4s32 = LLT :: fixed_vector ( <NUM_LIT> , <NUM_LIT> ) ;

auto & LegacyInfo = getLegacyLegalizerInfo ( ) ;


<s> return ( int32x4_t ) __builtin_neon_vreinterpretv4siti ( ( __builtin_neon_ti ) __a ) ;


<s> const MCInstrDesc & FMCID = std :: prev ( FMBB . end ( ) ) -> getDesc ( ) ; if ( FMCID . isReturn ( ) || FMCID . isCall ( ) ) return false ; if ( ( NumTCycles + NumFCycles ) > <NUM_LIT> ) return false ;

return ! mayStall ( TMBB ) && ! mayStall ( FMBB ) ;


<s> SDNode * emitBuildVector ( SDNode * bvNode ) { EVT vecVT = bvNode -> getValueType ( <NUM_LIT> ) ; EVT eltVT = vecVT . getVectorElementType ( ) ; DebugLoc dl = bvNode -> getDebugLoc ( ) ; if ( ( ( vecVT == <STR_LIT> ) && ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) ) || ( ( vecVT == <STR_LIT> ) && ( ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG ) . getNode ( ) != <NUM_LIT> ) ) ) || ( ( vecVT == <STR_LIT> ) && ( ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) ) ) ) { HandleSDNode Dummy ( SDValue ( bvNode , <NUM_LIT> ) ) ; if ( SDNode * N = Select ( bvNode ) ) return N ; return Dummy . getValue ( ) . getNode ( ) ; } std :: vector < Constant * > CV ; for ( size_t i = <NUM_LIT> ; i < bvNode -> getNumOperands ( ) ; ++ i ) { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( bvNode -> getOperand ( i ) ) ; CV . push_back ( const_cast < ConstantInt * > ( V -> getConstantIntValue ( ) ) ) ; }

Constant * CP = ConstantVector :: get ( CV ) ;


<s> bool hasCapabilitySetAddress ( ) const override {


<s> unsigned int byte = ( high_p != BYTES_BIG_ENDIAN ) ? UNITS_PER_WORD : <NUM_LIT> ; machine_mode mode = GET_MODE ( op ) ; if ( mode == VOIDmode ) mode = TARGET_64BIT ? TImode : DImode ; if ( MEM_P ( op ) ) return adjust_address ( op , word_mode , byte ) ;

if ( REG_P ( op ) ) gcc_assert ( ! FP_REG_RTX_P ( op ) ) ;


<s> tailReplicator . duplicateTail ( * pred , * tail ) ; assert ( tail -> pred_size ( ) == <NUM_LIT> && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << tail -> getName ( ) << '\n' ) ; ++ NumDuplicatedBlocks ;


<s> if ( Kind == VK_<ISA_LIT>_PCREL_HI || Kind == VK_<ISA_LIT>_PCREL_LO || Kind == VK_<ISA_LIT>_GOT_HI || Kind == VK_<ISA_LIT>_TPREL_HI || Kind == VK_<ISA_LIT>_TPREL_LO || Kind == VK_<ISA_LIT>_TPREL_ADD || Kind == VK_<ISA_LIT>_TLS_GOT_HI || Kind == VK_<ISA_LIT>_TLS_GD_HI || Kind == VK_<ISA_LIT>_CALL || Kind == VK_<ISA_LIT>_CALL_PLT ) return false ; if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) return false ; if ( ! Value . isAbsolute ( ) ) return false ;

Res = evaluateAsInt64 ( Value . getConstant ( ) ) ;


<s> if ( optimize_size ) return <NUM_LIT> ; insn = next_active_insn ( label ) ; if ( insn == <NUM_LIT> ) return <NUM_LIT> ; else if ( ( get_attr_length ( insn ) % <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ;


<s> tree t ; basic_block bb ; gimple_stmt_iterator gsi ; gcc_assert ( cfun -> machine -> sdmode_stack_slot == NULL_RTX ) ; if ( ira_use_lra_p ) return ; if ( TARGET_NO_SDMODE_STACK ) return ; FOR_EACH_BB_FN ( bb , cfun ) for ( gsi = gsi_start_bb ( bb ) ; ! gsi_end_p ( gsi ) ; gsi_next ( & gsi ) ) { tree ret = walk_gimple_op ( gsi_stmt ( gsi ) , rs6000_check_sdmode , NULL ) ; if ( ret ) { rtx stack = assign_stack_local ( DDmode , GET_MODE_SIZE ( DDmode ) , <NUM_LIT> ) ; cfun -> machine -> sdmode_stack_slot = adjust_address_nv ( stack , SDmode , <NUM_LIT> ) ; return ; }


<s> Register ( const MachineOperand & Op ) : Reg ( Op . getReg ( ) ) , Sub ( Op . getSubReg ( ) ) {


<s> Function * Func = Arg -> getParent ( ) ; Instruction * FirstInst = & ( Func -> getEntryBlock ( ) . front ( ) ) ; PointerType * PType = dyn_cast < PointerType > ( Arg -> getType ( ) ) ; assert ( PType && <STR_LIT> ) ; Type * StructType = PType -> getElementType ( ) ; const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ; unsigned AS = DL . getAllocaAddrSpace ( ) ; AllocaInst * AllocA = new AllocaInst ( StructType , AS , Arg -> getName ( ) , FirstInst ) ;

AllocA -> setAlignment ( Func -> getParamAlign ( Arg -> getArgNo ( ) ) . getValueOr ( DL . getPrefTypeAlign ( StructType ) ) ) ;


<s> unsigned VLMUL = ( VType & <NUM_LIT> ) | ( ( VType & <NUM_LIT> ) >> <NUM_LIT> ) ;

return static_cast < <ISA_LIT>VLMUL > ( VLMUL ) ;