<s> static SDValue LowerBITCAST ( SDValue Op , SelectionDAG & DAG ) { if ( Op . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDLoc DL ( Op ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; Op = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ; return SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , Op , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> Op = DAG . getNode ( <STR_LIT> , dl , NewVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue CtlzNode = DAG . getNode ( <STR_LIT> , dl , NewVT , Op ) ; SDValue TruncNode = DAG . getNode ( <STR_LIT> , dl , VT , CtlzNode ) ; SDValue Delta = DAG . getConstant ( <NUM_LIT> - EltVT . getSizeInBits ( ) , dl , VT ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , TruncNode , Delta ) ;


<s> void <ISA_LIT>DbgInfo :: EndModule ( Module & M ) { if ( ! EmitDebugDirectives ) return ; EmitVarDebugInfo ( M ) ; if ( CurFile != <STR_LIT> ) O << <STR_LIT> ;


<s> if ( ! isInt < <NUM_LIT> > ( Imm ) ) { Shift = countTrailingZeros < uint64_t > ( Imm ) ; int64_t ImmSh = static_cast < uint64_t > ( Imm ) >> Shift ; if ( isInt < <NUM_LIT> > ( ImmSh ) ) { Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; }


<s> void ConvergingVLIWScheduler :: initialize ( ScheduleDAGMI * dag ) { DAG = static_cast < VLIWMachineScheduler * > ( dag ) ; SchedModel = DAG -> getSchedModel ( ) ; TRI = DAG -> TRI ; Top . init ( DAG , SchedModel ) ; Bot . init ( DAG , SchedModel ) ;

const InstrItineraryData * Itin = DAG -> getSchedModel ( ) -> getInstrItineraries ( ) ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( ( Imm == <NUM_LIT> ? <NUM_LIT> : Imm ) ) ) ;


<s> <ISA_LIT>MCInstLower ( MCContext & Ctx , AsmPrinter & Printer ) : Ctx ( Ctx ) , Printer ( Printer ) {


<s> initialize ( MF ) ; return simplifyCode ( ) ;


<s> static SDValue getUnpackl ( SelectionDAG & DAG , const SDLoc & dl , MVT VT , SDValue V1 , SDValue V2 ) { SmallVector < int , <NUM_LIT> > Mask ; createUnpackShuffleMask ( VT , Mask , true , false ) ; return DAG . getVectorShuffle ( VT , dl , V1 , V2 , Mask ) ;


__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> APInt Mask17 = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( DAG . MaskedValueIsZero ( Op , Mask17 ) ) return Op ; if ( <STR_LIT> ( Op . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op , DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ) ; if ( Op . getOpcode ( ) == <STR_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getScalarValueSizeInBits ( ) == <NUM_LIT> && VT . getSizeInBits ( ) <= <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; if ( Src . getScalarValueSizeInBits ( ) < <NUM_LIT> && ! Subtarget . hasSSE41 ( ) ) { EVT ExtVT = VT . changeVectorElementType ( <STR_LIT> ) ; Src = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , ExtVT , Src ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; } } if ( Op . getOpcode ( ) == <STR_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getScalarValueSizeInBits ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Src ) ; } if ( Op . getOpcode ( ) == <STR_LIT> && Op . getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> && N -> isOnlyUserOf ( Op . getNode ( ) ) ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } return SDValue ( ) ; } ; SDValue ZeroN0 = GetZeroableOp ( N0 ) ; SDValue ZeroN1 = GetZeroableOp ( N1 ) ;

if ( ! ZeroN0 && ! ZeroN1 ) return SDValue ( ) ;


<s> if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ; if ( STI . hasFeature ( <STR_LIT> ) ) Arch += <STR_LIT> ;

emitTextAttribute ( <STR_LIT> , Arch ) ;


<s> explicit <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> , Align ( <NUM_LIT> ) , true ) {


<s> unsigned <ISA_LIT>Z80DAGToDAGISel :: selectIndexedProgMemLoad ( const LoadSDNode * LD , MVT VT ) { <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( LD -> getExtensionType ( ) != <STR_LIT> || AM != <STR_LIT> ) { return <NUM_LIT> ; } unsigned Opcode = <NUM_LIT> ; int Offs = cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getSExtValue ( ) ; switch ( VT . SimpleTy ) { case <STR_LIT> : { if ( Offs != <NUM_LIT> ) { return <NUM_LIT> ; } Opcode = <STR_LIT> ; break ; } case <STR_LIT> : { if ( Offs != <NUM_LIT> ) { return <NUM_LIT> ; } Opcode = <STR_LIT> ; break ; } default :


<s> if ( InfoAndKind . Is<ISA_LIT> ) { CCVal = DAG . getConstant ( <STR_LIT> ( InfoAndKind . Info . <ISA_LIT> . CC ) , dl , <STR_LIT> ) ; Cmp = * InfoAndKind . Info . <ISA_LIT> . Cmp ; } else Cmp = get<ISA_LIT>Cmp ( * InfoAndKind . Info . Generic . Opnd0 , * InfoAndKind . Info . Generic . Opnd1 , <STR_LIT> ( InfoAndKind . Info . Generic . CC , CmpVT ) , CCVal , DAG , dl ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ;

LHS = DAG . getNode ( <STR_LIT> , dl , VT , RHS , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectFI ( SDValue N , SDValue & Reg , SDValue & Off ) {

if ( ! SelectOff ( N , Reg , Off ) ) return false ;


<s> return ( __m128i ) __builtin_ia32_vphadddq ( ( __v4si ) __A ) ;


<s> unsigned EltBits = VT . getVectorElementType ( ) . getSizeInBits ( ) ; EVT EltVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , EltBits * <NUM_LIT> ) ; auto HalfEC = VT . getVectorElementCount ( ) / <NUM_LIT> ;

return EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , HalfEC ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align :: None ( ) , - <NUM_LIT> ) {


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_<ISA_LIT> , false ) {


<s> if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) return <STR_LIT> ;


<s> static void arm_emit_multi_reg_pop ( unsigned long saved_regs_mask ) { int num_regs = <NUM_LIT> ; int i , j ; rtx par ; rtx dwarf = NULL_RTX ; rtx tmp , reg ; bool return_in_pc = saved_regs_mask & ( <NUM_LIT> << PC_REGNUM ) ; int offset_adj ; int emit_update ; offset_adj = return_in_pc ? <NUM_LIT> : <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= <NUM_LIT> ) ; emit_update = ( saved_regs_mask & ( <NUM_LIT> << SP_REGNUM ) ) ? <NUM_LIT> : <NUM_LIT> ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + emit_update + offset_adj ) ) ;

if ( return_in_pc ) XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = ret_rtx ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned ArgOffset = <ISA_LIT>FrameLowering :: minStackSize ( ) ; unsigned ArgRegIdx = <NUM_LIT> ; unsigned StackSlotSize = <ISA_LIT>FrameLowering :: stackSlotSize ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CCC_<ISA_LIT> ) ; for ( unsigned ArgNo = <NUM_LIT> , e = Ins . size ( ) ; ArgNo != e ; ++ ArgNo ) { EVT ObjectVT = Ins [ ArgNo ] . VT ; unsigned ObjSize = ObjectVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ArgVal ; CCValAssign & VA = ArgLocs [ ArgNo ] ; if ( VA . isRegLoc ( ) ) { const TargetRegisterClass * ArgRegClass ; switch ( ObjectVT . getSimpleVT ( ) . SimpleTy ) { default : report_fatal_error ( <STR_LIT> + Twine ( ObjectVT . getEVTString ( ) ) ) ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } InVals . push_back ( ArgVal ) ; Chain = ArgVal . getOperand ( <NUM_LIT> ) ;


<s> short <ISA_LIT>OptAddrMode :: getBaseWithLongOffset ( const MachineInstr & MI ) const { if ( HII -> getAddrMode ( MI ) == <STR_LIT> ) { short TempOpCode = HII -> getBaseWithRegOffset ( MI ) ; return HII -> getBaseWithLongOffset ( TempOpCode ) ;

} else return HII -> getBaseWithLongOffset ( MI ) ;


<s> while ( depth -- ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , dl ) ) ; FrameAddr = DAG . getLoad ( VT , dl , Chain , Ptr , MachinePointerInfo ( ) ) ; } if ( Subtarget -> is64Bit ( ) ) FrameAddr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( stackBias , dl ) ) ; return FrameAddr ;


<s> void RelaxInstruction ( const MCInst & Inst , MCInst & Res ) const {


<s> if ( ( * leaf ) -> getType ( ) == nodeType :: LOOP ) return status :: LOOPSTATUS ; if ( * leaf != globalPath -> getEnd ( ) ) { <ISA_LIT>_DEBUG ( <STR_LIT> + to_string ( ( * leaf ) -> getMachinBB ( ) -> getNumber ( ) ) + <STR_LIT> ) ;

if ( computeAllPath ( globalPath , * leaf , list , ( * leaf ) -> getCycle ( ) + costCollect ) == status :: LOOPSTATUS ) return status :: LOOPSTATUS ;


<s> if ( abi_break & warn_psabi ) inform ( input_location , <STR_LIT> <STR_LIT> , type ) ; return MIN ( MAX ( alignment , PARM_BOUNDARY ) , STACK_BOUNDARY ) ;


<s> char * * values ; unsigned num = <NUM_LIT> , i ; curval = strchr ( str , ':' ) ; while ( curval ) { num ++ ; curval = strchr ( curval + <NUM_LIT> , ':' ) ; } values = ( char * * ) xmalloc ( num * sizeof ( char * ) ) ; curval = str ; nextval = strchr ( curval , ':' ) ; if ( nextval == NULL ) nextval = strchr ( curval , '\0' ) ; for ( i = <NUM_LIT> ; i < num ; i ++ ) {


<s> const ValueList & getValues ( ) const { return Values ;


error ( <STR_LIT> , decl , src_arg_index + <NUM_LIT> ) ;


<s> if ( VT . isVector ( ) ) return VT . changeVectorElementTypeToInteger ( ) ;

return EVT :: getIntegerVT ( C , <NUM_LIT> ) ;


<s> return ( __m256 ) __builtin_ia32_loadups256_mask ( ( __v8sf * ) __P , ( __v8sf ) _mm256_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> static bool alwaysInlineImpl ( Module & M , bool GlobalOpt ) { std :: vector < GlobalAlias * > AliasesToRemove ; SmallPtrSet < Function * , <NUM_LIT> > FuncsToAlwaysInline ; SmallPtrSet < Function * , <NUM_LIT> > FuncsToNoInline ; for ( GlobalAlias & A : M . aliases ( ) ) { if ( Function * F = dyn_cast < Function > ( A . getAliasee ( ) ) ) { A . replaceAllUsesWith ( F ) ; AliasesToRemove . push_back ( & A ) ; } } if ( GlobalOpt ) { for ( GlobalAlias * A : AliasesToRemove ) { A -> eraseFromParent ( ) ; } } for ( GlobalVariable & GV : M . globals ( ) ) { unsigned AS = GV . getAddressSpace ( ) ; if ( ( AS == <ISA_LIT>AS :: REGION_ADDRESS ) || ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS && ! <ISA_LIT>TargetMachine :: EnableLowerModuleLDS ) ) recursivelyVisitUsers ( GV , FuncsToAlwaysInline ) ; } if ( ! <ISA_LIT>TargetMachine :: EnableFunctionCalls || StressCalls ) { auto IncompatAttr = StressCalls ? Attribute :: AlwaysInline : Attribute :: NoInline ;


<s> auto Ty = MRI . getType ( CompareReg ) ; unsigned Width = Ty . getSizeInBits ( ) ; assert ( ! Ty . isVector ( ) && <STR_LIT> ) ; assert ( Width <= <NUM_LIT> && <STR_LIT> ) ;

static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ;


<s> <STR_LIT> ABI = Subtarget . getTargetABI ( ) ;

if ( ( ABI == <STR_LIT> || ABI == <STR_LIT> ) && ( Type == <STR_LIT> ) ) return false ;


<s> case ELF :: ELFABIVER<ISA_LIT>ON_AMDGPU_HSA_V2 : case ELF :: ELFABIVER<ISA_LIT>ON_AMDGPU_HSA_V3 : return getEFlagsV3 ( ) ; case ELF :: ELFABIVER<ISA_LIT>ON_AMDGPU_HSA_V4 : case ELF :: ELFABIVER<ISA_LIT>ON_AMDGPU_HSA_V5 : return getEFlagsV4 ( ) ;


<s> bool isMesaKernel ( const Function & F ) const {

return isMesa3DOS ( ) && ! <STR_LIT> ( F . getCallingConv ( ) ) ;


<s> if ( Reg == <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < ValLocs . size ( ) ; ++ i ) { CCValAssign & VA = ValLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetRegs . push_back ( VA . getLocReg ( ) ) ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT RVEVT = TLI . getValueType ( RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ; MVT RVVT = RVEVT . getSimpleVT ( ) ; MVT DestVT = VA . getLocVT ( ) ; if ( RVVT != DestVT && RVVT != <STR_LIT> && RVVT != <STR_LIT> && RVVT != <STR_LIT> ) return false ; if ( RVVT != DestVT ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: AExt : case CCValAssign :: ZExt : { const TargetRegisterClass * RC = ( DestVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned TmpReg = createResultReg ( RC ) ; if ( ! <ISA_LIT>EmitIntExt ( RVVT , SrcReg , DestVT , TmpReg , true ) ) return false ; SrcReg = TmpReg ; break ;


<s> SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ;

SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ;


<s> MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( STI . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( STI . getRegisterInfo ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; <ISA_LIT>ABIInfo ABI = STI . getABI ( ) ; unsigned SP = <STR_LIT> ; uint64_t StackSize = MFI -> getStackSize ( ) ; if ( ! StackSize ) return ;

TII . adjustStackPtr ( SP , StackSize , MBB , MBBI ) ;


<s> static bool moxie_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CC_REG ; * p2 = INVALID_REGNUM ;


<s> DIVariable V ( const_cast < MDNode * > ( MI -> getOperand ( NOps - <NUM_LIT> ) . getMetadata ( ) ) ) ; OS << V . getName ( ) ; OS << <STR_LIT> ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) ; OS << '[' << <ISA_LIT>InstPrinter :: getRegisterName ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;

OS << '+' << MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> extract_base_offset_in_addr ( mem_1 , & base , & offset ) ; gcc_assert ( base != NULL_RTX && offset != NULL_RTX ) ; msize = GET_MODE_SIZE ( mode ) ; stp_off_limit = msize * <NUM_LIT> ; off_val = INTVAL ( offset ) ; abs_off = ( off_val < <NUM_LIT> ) ? - off_val : off_val ; new_off = abs_off % stp_off_limit ; adj_off = abs_off - new_off ; if ( ( new_off + msize * <NUM_LIT> ) >= stp_off_limit ) { adj_off += stp_off_limit ; new_off -= stp_off_limit ; } if ( adj_off >= <NUM_LIT> ) return false ; if ( off_val < <NUM_LIT> ) { adj_off = - adj_off ; new_off = - new_off ; } mem_1 = change_address ( mem_1 , VOIDmode , plus_constant ( DImode , operands [ <NUM_LIT> ] , new_off ) ) ; if ( ! aarch64_mem_pair_operand ( mem_1 , mode ) ) return false ; msize = GET_MODE_SIZE ( mode ) ; mem_2 = change_address ( mem_2 , VOIDmode , plus_constant ( DImode , operands [ <NUM_LIT> ] , new_off + msize ) ) ; mem_3 = change_address ( mem_3 , VOIDmode , plus_constant ( DImode , operands [ <NUM_LIT> ] , new_off + msize * <NUM_LIT> ) ) ; mem_4 = change_address ( mem_4 , VOIDmode , plus_constant ( DImode , operands [ <NUM_LIT> ] , new_off + msize * <NUM_LIT> ) ) ; if ( code == ZERO_EXTEND ) { mem_1 = gen_rtx_ZERO_EXTEND ( DImode , mem_1 ) ; mem_2 = gen_rtx_ZERO_EXTEND ( DImode , mem_2 ) ; mem_3 = gen_rtx_ZERO_EXTEND ( DImode , mem_3 ) ; mem_4 = gen_rtx_ZERO_EXTEND ( DImode , mem_4 ) ; } else if ( code == SIGN_EXTEND ) { mem_1 = gen_rtx_SIGN_EXTEND ( DImode , mem_1 ) ; mem_2 = gen_rtx_SIGN_EXTEND ( DImode , mem_2 ) ; mem_3 = gen_rtx_SIGN_EXTEND ( DImode , mem_3 ) ; mem_4 = gen_rtx_SIGN_EXTEND ( DImode , mem_4 ) ; } if ( load ) { operands [ <NUM_LIT> ] = mem_1 ; operands [ <NUM_LIT> ] = mem_2 ; operands [ <NUM_LIT> ] = mem_3 ; operands [ <NUM_LIT> ] = mem_4 ; } else { operands [ <NUM_LIT> ] = mem_1 ; operands [ <NUM_LIT> ] = mem_2 ; operands [ <NUM_LIT> ] = mem_3 ; operands [ <NUM_LIT> ] = mem_4 ; } emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , plus_constant ( DImode , base , adj_off ) ) ) ; t1 = gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; t2 = gen_rtx_SET ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , t1 , t2 ) ) ) ;


<s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue Elt = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { MVT ExtVecVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MVT ExtEltVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue ExtOp = DAG . getNode ( <STR_LIT> , dl , ExtVecVT , DAG . getNode ( <STR_LIT> , dl , ExtVecVT , Vec ) , DAG . getNode ( <STR_LIT> , dl , ExtEltVT , Elt ) , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , VecVT , ExtOp ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; SDValue EltInVec = DAG . getNode ( <STR_LIT> , dl , VecVT , Elt ) ; unsigned NumElems = VecVT . getVectorNumElements ( ) ; if ( Vec . isUndef ( ) ) { if ( IdxVal ) EltInVec = DAG . getNode ( <STR_LIT> , dl , VecVT , EltInVec , DAG . getConstant ( IdxVal , dl , <STR_LIT> ) ) ; return EltInVec ; } if ( IdxVal == <NUM_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> SDValue CP = LowerConstantPool ( DAG . getConstantPool ( CV , ByteTy , Alignment ) , DAG ) ; SDValue Bytes = DAG . getLoad ( ByteTy , dl , DAG . getEntryNode ( ) , CP , MachinePointerInfo :: getConstantPool ( MF ) , Alignment ) ; SDValue Sel = DAG . getSelect ( dl , VecTy , VecQ , DAG . getBitcast ( VecTy , Bytes ) , getZero ( dl , VecTy , DAG ) ) ; SDValue All1 = DAG . getSplatBuildVector ( <STR_LIT> , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Vrmpy = getInstr ( <STR_LIT> , dl , ByteTy , { Sel , All1 } , DAG ) ; SDValue Rot = getInstr ( <STR_LIT> , dl , ByteTy , { Vrmpy , Vrmpy , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) } , DAG ) ; SDValue Vor = DAG . getNode ( <STR_LIT> , dl , ByteTy , { Vrmpy , Rot } ) ;


<s> rtx mem = adjust_address_nv ( base_mem , SImode , offset ) ; return gen_rtx_SET ( load_p ? reg : mem , load_p ? mem : reg ) ;


<s> Alignment = getDataLayout ( ) -> getABITypeAlignment ( GVPtrTy -> getElementType ( ) ) ; } else { Alignment = <NUM_LIT> ; } } unsigned char HiFixup , LoFixup ; bool UseGOT = Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ; if ( UseGOT ) { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; Alignment = <NUM_LIT> ; } else { HiFixup = <STR_LIT> ; LoFixup = <STR_LIT> ; } SDValue GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , HiFixup ) , DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , LoFixup ) , DAG . getConstant ( Alignment , <STR_LIT> ) ) ; if ( UseGOT ) {

GlobalRef = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getEntryNode ( ) , GlobalRef ) ;


<s> case <STR_LIT> : Count = <NUM_LIT> ; break ; } SmallVector < unsigned , <NUM_LIT> > ResultRegs ; for ( unsigned i = <NUM_LIT> ; i < Count ; ++ i ) { unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & NewMI = * BuildMI ( MBB , MII , DL , get ( NewOpcode ) , ResultReg ) . addReg ( Offset . getReg ( ) ) . addReg ( Rsrc . getReg ( ) ) . addImm ( <NUM_LIT> ) . addImm ( i << <NUM_LIT> ) . addImm ( Glc . getImm ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( * Inst . memoperands_begin ( ) ) ; auto & NewDestOp = NewMI . getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) ResultRegs . push_back ( buildExtractSubReg ( MII , MRI , NewDestOp , & <STR_LIT> , RI . getSubRegFromChannel ( i ) , & <STR_LIT> ) ) ;


<s> return ( uint32x2_t ) __builtin_neon_vcgtv2sf ( __a , __b ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> if ( ! needToReserveScavengingSpillSlots ( MF , HRI , RC ) ) continue ; unsigned Num = RC == & <STR_LIT> ? NumberScavengerSlots : <NUM_LIT> ; unsigned S = HRI . getSpillSize ( * RC ) , A = HRI . getSpillAlignment ( * RC ) ; for ( unsigned i = <NUM_LIT> ; i < Num ; i ++ ) { int NewFI = MFI . CreateSpillStackObject ( S , A ) ; RS -> addScavengingFrameIndex ( NewFI ) ; } } }

TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( const MemOp & Op , const AttributeList & FuncAttributes ) const { if ( Subtarget . has<ISA_LIT>64 ( ) ) return <STR_LIT> ;


<s> addPass ( create<ISA_LIT>StackTaggingPass ( TM -> getOptLevel ( ) == CodeGenOpt :: None ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ;


<s> char * lo0 = lo ; for ( ; * up ; up ++ , lo ++ ) * lo = TOLOWER ( * up ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ;


<s> } if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { unsigned char OpFlags = <NUM_LIT> ; if ( DAG . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static && ( <ISA_LIT>SubTarget . getTargetTriple ( ) . isMacOSX ( ) && <ISA_LIT>SubTarget . getTargetTriple ( ) . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ) { OpFlags = <STR_LIT> ; } Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , Callee . getValueType ( ) , OpFlags ) ; needIndirectCall = false ; } if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 ) { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue LoadFuncPtr = DAG . getNode ( <STR_LIT> , dl , VTs , MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ; Chain = LoadFuncPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadFuncPtr . getValue ( <NUM_LIT> ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , AddPtr , InFlag ) ; Chain = LoadEnvPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadEnvPtr . getValue ( <NUM_LIT> ) ; SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LoadTOCPtr = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Callee , InFlag ) ; Chain = LoadTOCPtr . getValue ( <NUM_LIT> ) ; InFlag = LoadTOCPtr . getValue ( <NUM_LIT> ) ; MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ] = LoadFuncPtr ; MTCTROps [ <NUM_LIT> ] = InFlag ; }

Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , MTCTROps , <NUM_LIT> + ( InFlag . getNode ( ) != <NUM_LIT> ) ) ;


<s> unsigned getPCAdjustment ( ) const { return PCAdjust ;


<s> if ( ! MO . isReg ( ) ) continue ; unsigned R = MO . getReg ( ) - <STR_LIT> ; if ( R < <NUM_LIT> ) { if ( MF -> getFunction ( ) . getCallingConv ( ) != CallingConv :: <ISA_LIT>_RegCall ) { assert ( MO . isDef ( ) && MO . isImplicit ( ) ) ; } STReturns |= <NUM_LIT> << R ; } } unsigned N = countTrailingOnes ( STReturns ) ; assert ( STReturns == <NUM_LIT> || ( isMask_32 ( STReturns ) && N <= <NUM_LIT> ) ) ; while ( StackTop > <NUM_LIT> ) popReg ( ) ;

for ( unsigned I = <NUM_LIT> ; I < N ; ++ I ) pushReg ( N - I - <NUM_LIT> ) ;


<s> if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { InstrInfo . reset ( new <ISA_LIT>InstrInfo ( * this ) ) ; TLInfo . reset ( new <ISA_LIT>TargetLowering ( TM , * this ) ) ; FrameLowering . reset ( new <ISA_LIT>FrameLowering ( TargetFrameLowering :: StackGrowsUp , MaxStackAlign , <NUM_LIT> ) ) ; } else { InstrInfo . reset ( new <ISA_LIT>InstrInfo ( * this ) ) ; TLInfo . reset ( new <ISA_LIT>TargetLowering ( TM , * this ) ) ; FrameLowering . reset ( new <ISA_LIT>FrameLowering ( TargetFrameLowering :: StackGrowsUp , MaxStackAlign , <NUM_LIT> ) ) ;


<s> RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; } else RTVEC_ELT ( p , offset ++ ) = gen_rtx_USE ( VOIDmode , gen_rtx_REG ( Pmode , use_reg ) ) ; for ( i = <NUM_LIT> ; i < end_reg - start_reg ; i ++ ) RTVEC_ELT ( p , i + offset ) = gen_frame_set ( gen_rtx_REG ( reg_mode , start_reg + i ) , frame_reg_rtx , save_area_offset + reg_size * i , ( sel & SAVRES_SAVE ) != <NUM_LIT> ) ; if ( ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) RTVEC_ELT ( p , i + offset ) = gen_frame_store ( gen_rtx_REG ( Pmode , <NUM_LIT> ) , frame_reg_rtx , lr_offset ) ; par = gen_rtx_PARALLEL ( VOIDmode , p ) ; if ( ! ( sel & SAVRES_SAVE ) && ( sel & SAVRES_LR ) ) { insn = emit_jump_insn ( par ) ; JUMP_LABEL ( insn ) = ret_rtx ;


<s> machine_mode mode = GET_MODE ( ops [ <NUM_LIT> ] ) ; enum immediate_class c = classify_immediate ( ops [ <NUM_LIT> ] , mode ) ; switch ( c ) { case IC_IL2 : { unsigned char arrhi [ <NUM_LIT> ] ; unsigned char arrlo [ <NUM_LIT> ] ; rtx to , temp , hi , lo ; int i ; machine_mode imode = mode ; imode = int_mode_for_mode ( mode ) ; constant_to_array ( mode , ops [ <NUM_LIT> ] , arrhi ) ; if ( imode != mode ) to = simplify_gen_subreg ( imode , ops [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; else to = ops [ <NUM_LIT> ] ; temp = ! can_create_pseudo_p ( ) ? to : gen_reg_rtx ( imode ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) { arrlo [ i + <NUM_LIT> ] = arrhi [ i + <NUM_LIT> ] ; arrlo [ i + <NUM_LIT> ] = arrhi [ i + <NUM_LIT> ] ; arrlo [ i + <NUM_LIT> ] = arrlo [ i + <NUM_LIT> ] = <NUM_LIT> ; arrhi [ i + <NUM_LIT> ] = arrhi [ i + <NUM_LIT> ] = <NUM_LIT> ; } hi = array_to_constant ( imode , arrhi ) ; lo = array_to_constant ( imode , arrlo ) ; emit_move_insn ( temp , hi ) ; emit_insn ( gen_rtx_SET ( VOIDmode , to , gen_rtx_IOR ( imode , temp , lo ) ) ) ; return <NUM_LIT> ; } case IC_FSMBI2 : { unsigned char arr_fsmbi [ <NUM_LIT> ] ; unsigned char arr_andbi [ <NUM_LIT> ] ; rtx to , reg_fsmbi , reg_and ; int i ; machine_mode imode = mode ; imode = int_mode_for_mode ( mode ) ; constant_to_array ( mode , ops [ <NUM_LIT> ] , arr_fsmbi ) ; if ( imode != mode ) to = simplify_gen_subreg ( imode , ops [ <NUM_LIT> ] , GET_MODE ( ops [ <NUM_LIT> ] ) , <NUM_LIT> ) ; else to = ops [ <NUM_LIT> ] ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( arr_fsmbi [ i ] != <NUM_LIT> ) { arr_andbi [ <NUM_LIT> ] = arr_fsmbi [ i ] ; arr_fsmbi [ i ] = <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) arr_andbi [ i ] = arr_andbi [ <NUM_LIT> ] ; reg_fsmbi = array_to_constant ( imode , arr_fsmbi ) ;

reg_and = array_to_constant ( imode , arr_andbi ) ;


<s> if ( regno >= FIRST_PSEUDO_REGISTER ) { if ( ! strict ) return true ; if ( ! reg_renumber ) return false ; regno = reg_renumber [ regno ] ;

if ( regno == INVALID_REGNUM ) return false ;


<s> O << <STR_LIT> << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << MO . getIndex ( ) ; printOffset ( MO . getOffset ( ) ) ; O << <STR_LIT> ; return ; } case MachineOperand :: MO_GlobalAddress : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; bool isMemOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; GlobalValue * GV = MO . getGlobal ( ) ; std :: string Name = Mang -> getValueName ( GV ) ; decorateName ( Name , GV ) ; if ( ! isMemOp && ! isCallOp ) O << <STR_LIT> ; if ( GV -> hasDLLImportLinkage ( ) ) { O << <STR_LIT> ; } O << Name ; printOffset ( MO . getOffset ( ) ) ; return ; } case MachineOperand :: MO_ExternalSymbol : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; if ( ! isCallOp ) O << <STR_LIT> ; O << TAI -> getGlobalPrefix ( ) << MO . getSymbolName ( ) ; return ; }


<s> StringRef <ISA_LIT>InstPrinter :: getOpcodeName ( unsigned Opcode ) const {


<s> static bool isFlatGlobalAddrSpace ( unsigned AS , <ISA_LIT>AS AMDGPUA<ISA_LIT> ) {

return AS == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS || AS == AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ;


<s> std :: vector < std :: string > mov_x1 ( Abl a ) { return D ( <STR_LIT> , R ( a ) , <STR_LIT> ) ;


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; if ( CM == CodeModel :: Default ) CM = CodeModel :: Small ;

X -> InitMCCodeGenInfo ( RM , CM , L ) ;


<s> NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } else { NopInst . setOpcode ( <STR_LIT> ) ;

NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;


<s> Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( DecodeRegListOperand ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; LLVM_FALLTHROUGH ; default :


<s> if ( mode == DImode && ne == <NUM_LIT> ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LSHIFTRT && INTVAL ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - INTVAL ( operands [ <NUM_LIT> ] ) ) ; operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - nb ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( mode == DImode && nb == <NUM_LIT> ) { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - ne ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( mode == DImode && GET_CODE ( operands [ <NUM_LIT> ] ) != LSHIFTRT && CONST_INT_P ( operands [ <NUM_LIT> ] ) && ne == INTVAL ( operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - nb ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( nb < <NUM_LIT> && ne < <NUM_LIT> ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LSHIFTRT && INTVAL ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - INTVAL ( operands [ <NUM_LIT> ] ) ) ; operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - nb ) ;


<s> static unsigned int nds32_relax_opt ( void ) { if ( TARGET_RELAX_HINT ) nds32_relax_group ( ) ; return <NUM_LIT> ;


<s> static inline bool isImmLL ( uint64_t Val ) { return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;


<s> NaCl<ISA_LIT>AsmBackend ( const Target & T , bool _is64Bit ) : <ISA_LIT>AsmBackend ( T , Triple :: NaCl , true , _is64Bit ) { State . SaveCount = <NUM_LIT> ; State . I = <NUM_LIT> ;


<s> Register SrcLoReg , SrcHiReg , DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( SrcReg , SrcLoReg , SrcHiReg ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; auto MIBLO = buildMI ( MBB , MBBI , Op ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcLoReg , getKillRegState ( SrcIsKill ) ) ; MIBLO -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MIBHI = buildMI ( MBB , MBBI , Op ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcHiReg , getKillRegState ( SrcIsKill ) ) ; if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'O' : if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'e' : { if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , <STR_LIT> ) ; break ; } } return ; } case 'Z' : { if ( auto * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; } case 'i' : { if ( auto * CST = dyn_cast < ConstantSDNode > ( Op ) ) { bool IsBool = CST -> getConstantIntValue ( ) -> getBitWidth ( ) == <NUM_LIT> ; BooleanContent BCont = getBooleanContents ( <STR_LIT> ) ; <STR_LIT> ExtOpc = IsBool ? getExtendForContent ( BCont ) : <STR_LIT> ; int64_t ExtVal = ExtOpc == <STR_LIT> ? CST -> getZExtValue ( ) : CST -> getSExtValue ( ) ; Result = DAG . getTargetConstant ( ExtVal , SDLoc ( Op ) , <STR_LIT> ) ; break ; } if ( ( Subtarget . isPICStyleGOT ( ) || Subtarget . isPICStyleStubPIC ( ) ) && ! isa < BlockAddressSDNode > ( Op ) ) return ; if ( auto * GA = dyn_cast < GlobalAddressSDNode > ( Op ) ) if ( isGlobalStubReference ( Subtarget . classifyGlobalReference ( GA -> getGlobal ( ) ) ) ) return ;


<s> return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> void <ISA_LIT>HazardRecognizer :: clearProcResCounters ( ) { ProcResourceCounters . assign ( SchedModel -> getNumProcResourceKinds ( ) , <NUM_LIT> ) ; CriticalResourceIdx = UINT_MAX ;


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; HasE1 = false ;


<s> StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Res , S , E ) ) ; return false ;


<s> if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> if ( ! WaterList . empty ( ) ) { for ( std :: vector < MachineBasicBlock * > :: iterator IP = prior ( WaterList . end ( ) ) , B = WaterList . begin ( ) ; ; -- IP ) { MachineBasicBlock * WaterBB = * IP ; if ( WaterIsInRange ( UserOffset , WaterBB , U ) ) { unsigned WBBId = WaterBB -> getNumber ( ) ; if ( isThumb && ( BBOffsets [ WBBId ] + BBSizes [ WBBId ] ) % <NUM_LIT> != <NUM_LIT> ) { if ( ! WaterBBThatWouldPad ) { WaterBBThatWouldPad = WaterBB ; IPThatWouldPad = IP ; } } else { * NewMBB = AcceptWater ( WaterBB , IP ) ; return true ; } } if ( IP == B ) break ; } } if ( isThumb && WaterBBThatWouldPad ) { * NewMBB = AcceptWater ( WaterBBThatWouldPad , IPThatWouldPad ) ; return true ; } return false ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>beAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TheTriple , StringRef CPU ) {

assert ( TheTriple . isOSBinFormatELF ( ) && <STR_LIT> ) ;


<s> static SDValue LowerMGATHER ( SDValue Op , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { assert ( Subtarget -> hasAVX512 ( ) && <STR_LIT> ) ; MaskedGatherSDNode * N = cast < MaskedGatherSDNode > ( Op . getNode ( ) ) ; EVT VT = Op . getValueType ( ) ; assert ( VT . getScalarSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Index = N -> getIndex ( ) ; if ( ! Subtarget -> hasVLX ( ) && ! VT . is512BitVector ( ) && ! Index . getValueType ( ) . is512BitVector ( ) ) { Index = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index ) ;

SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Index } ;


<s> return __builtin_aarch64_rbitv16qi ( __a ) ;


<s> FormalArgHandler ( MachineIRBuilder & B , MachineRegisterInfo & MRI , CCAssignFn * AssignFn ) : IncomingArgHandler ( B , MRI , AssignFn ) {


<s> if ( DAG -> top ( ) == DAG -> bottom ( ) ) { assert ( Top . Available . empty ( ) && Top . Pending . empty ( ) && Bot . Available . empty ( ) && Bot . Pending . empty ( ) && <STR_LIT> ) ; return nullptr ; } SUnit * SU ; if ( llvm :: ForceTopDown ) { SU = Top . pickOnlyChoice ( ) ; if ( ! SU ) { SchedCandidate TopCand ; CandResult TopResult = pickNodeFromQueue ( Top . Available , DAG -> getTopRPTracker ( ) , TopCand ) ; assert ( TopResult != NoCand && <STR_LIT> ) ; ( void ) TopResult ; SU = TopCand . SU ; } IsTopNode = true ; } else if ( llvm :: ForceBottomUp ) { SU = Bot . pickOnlyChoice ( ) ; if ( ! SU ) { SchedCandidate BotCand ; CandResult BotResult = pickNodeFromQueue ( Bot . Available , DAG -> getBotRPTracker ( ) , BotCand ) ; assert ( BotResult != NoCand && <STR_LIT> ) ; ( void ) BotResult ; SU = BotCand . SU ; } IsTopNode = false ; } else { SU = pickNodeBidrectional ( IsTopNode ) ; } if ( SU -> isTopReady ( ) ) Top . removeReady ( SU ) ; if ( SU -> isBottomReady ( ) ) Bot . removeReady ( SU ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << ( IsTopNode ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( IsTopNode ? Top . CurrCycle : Bot . CurrCycle ) << '\n' ;


<s> return __builtin_mve_vcmulq_rot270v4sf ( __a , __b ) ;


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { return true ;


<s> scalar_int_mode int_mode ; if ( ! is_a < scalar_int_mode > ( mode , & int_mode ) ) return false ; if ( aarch64_bitmask_imm ( val_in , int_mode ) ) return false ; if ( aarch64_move_imm ( val_in , int_mode ) ) return false ; unsigned HOST_WIDE_INT imm2 = aarch64_and_split_imm2 ( val_in ) ;


<s> CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getLocVT ( ) ; Chain = DAG . getCopyFromReg ( Chain , DL , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue Val = Chain . getValue ( <NUM_LIT> ) ; if ( VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Val ) ; }


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> if ( MO . isFPImm ( ) ) return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; assert ( MO . isExpr ( ) ) ;

return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ;


<s> } int ShiftEltBits = VT . getScalarSizeInBits ( ) * Scale ; bool ByteShift = ShiftEltBits > <NUM_LIT> ; unsigned OpCode = Left ? ( ByteShift ? <STR_LIT> : <STR_LIT> ) : ( ByteShift ? <STR_LIT> : <STR_LIT> ) ; int ShiftAmt = Shift * VT . getScalarSizeInBits ( ) / ( ByteShift ? <NUM_LIT> : <NUM_LIT> ) ; Scale = ByteShift ? Scale / <NUM_LIT> : Scale ; MVT ShiftSVT = <STR_LIT> ( VT . getScalarSizeInBits ( ) * Scale ) ; MVT ShiftVT = <STR_LIT> ( ShiftSVT , Size / Scale ) ; assert ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( ShiftVT ) && <STR_LIT> ) ; V = DAG . getBitcast ( ShiftVT , V ) ; V = DAG . getNode ( OpCode , DL , ShiftVT , V , DAG . getConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; return DAG . getBitcast ( VT , V ) ; } ; for ( int Scale = <NUM_LIT> ; Scale * VT . getScalarSizeInBits ( ) <= <NUM_LIT> ; Scale *= <NUM_LIT> ) for ( int Shift = <NUM_LIT> ; Shift != Scale ; ++ Shift ) for ( bool Left : { true , false } ) if ( CheckZeros ( Shift , Scale , Left ) ) for ( SDValue V : { V1 , V2 } ) if ( SDValue Match = MatchShift ( Shift , Scale , Left , V ) ) return Match ; return SDValue ( ) ;


<s> while ( Ox < NP ) { MachineOperand & MO = MI . getOperand ( Ox ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) MB . add ( MO ) ; Ox ++ ; } MachineFunction & MF = * B . getParent ( ) ; MachineInstr :: mmo_iterator I = MI . memoperands_begin ( ) ; unsigned NR = std :: distance ( I , MI . memoperands_end ( ) ) ; MachineInstr :: mmo_iterator MemRefs = MF . allocateMemRefsArray ( NR ) ; for ( unsigned i = <NUM_LIT> ; i < NR ; ++ i ) MemRefs [ i ] = * I ++ ; MB . setMemRefs ( MemRefs , MemRefs + NR ) ; MachineInstr * NewI = MB ; NewI -> clearKillInfo ( ) ; LIS -> InsertMachineInstrInMaps ( * NewI ) ; for ( auto & Op : NewI -> operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ;


<s> unsigned RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( RegLst == <NUM_LIT> ) return MCDisassembler :: Fail ; RegNum = RegLst & <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < RegNum - <NUM_LIT> ; i ++ ) Inst . addOperand ( MCOperand :: CreateReg ( Regs [ i ] ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; return MCDisassembler :: Success ;


<s> MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = lowerSymbolOperand ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = lowerSymbolOperand ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ;


<s> return :: isUNPCKLMask ( N -> getMask ( ) , N -> getValueType ( <NUM_LIT> ) , HasAVX2 , V2IsSplat ) ;


<s> return TargetIRAnalysis ( [ this ] ( Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ; } ) ;


<s> return __builtin_aarch64_frint64xsf ( __a ) ;


<s> Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> ) ) , ELFWriterInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) {

if ( ! Subtarget . has<ISA_LIT>Ops ( ) ) report_fatal_error ( <STR_LIT> + Subtarget . getCPUString ( ) + <STR_LIT> <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel , bool Verbose , raw_ostream & Out ) { PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , OptLevel , Verbose ) ) ; return false ;


<s> if ( ! ExportMap [ Slot ] ) { SDValue Vector = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Scalar , DAG . getConstant ( Channel , <STR_LIT> ) ) ; unsigned Mask = <NUM_LIT> << Channel ; const SDValue Ops [ ] = { Chain , Vector , DAG . getConstant ( Inst , <STR_LIT> ) , DAG . getConstant ( Type , <STR_LIT> ) , DAG . getConstant ( Slot , <STR_LIT> ) , DAG . getConstant ( Mask , <STR_LIT> ) } ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops , <NUM_LIT> ) ; ExportMap [ Slot ] = Res . getNode ( ) ; return Res ;


<s> const MCSymbolRefExpr * HiSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI , MCA . getContext ( ) ) ; TmpInst . addOperand ( MCOperand :: CreateExpr ( HiSym ) ) ; getStreamer ( ) . EmitInstruction ( TmpInst , STI ) ; TmpInst . clear ( ) ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ;

const MCSymbolRefExpr * LoSym = MCSymbolRefExpr :: Create ( <STR_LIT> , MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO , MCA . getContext ( ) ) ;


<s> return true ; } return false ; } if ( MaskNode . getOpcode ( ) != <STR_LIT> ) return false ; if ( ( VT . getScalarSizeInBits ( ) % MaskEltSizeInBits ) != <NUM_LIT> ) return false ; unsigned ElementSplit = VT . getScalarSizeInBits ( ) / MaskEltSizeInBits ; for ( int i = <NUM_LIT> , e = MaskNode . getNumOperands ( ) ; i < e ; ++ i ) { SDValue Op = MaskNode . getOperand ( i ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) { RawMask . push_back ( ( uint64_t ) SM_SentinelUndef ) ; continue ; } APInt MaskElement ; if ( auto * CN = dyn_cast < ConstantSDNode > ( Op . getNode ( ) ) ) MaskElement = CN -> getAPIntValue ( ) ; else if ( auto * CFN = dyn_cast < ConstantFPSDNode > ( Op . getNode ( ) ) ) MaskElement = CFN -> getValueAPF ( ) . bitcastToAPInt ( ) ; else return false ; for ( unsigned j = <NUM_LIT> ; j < ElementSplit ; ++ j ) { APInt RawElt = MaskElement . getLoBits ( MaskEltSizeInBits ) ; RawMask . push_back ( RawElt . getZExtValue ( ) ) ; MaskElement = MaskElement . lshr ( MaskEltSizeInBits ) ; } } return true ;


<s> switch ( insn . sibBase ) { default : debug ( <STR_LIT> ) ; return true ; case SIB_BASE_ ## x : \ baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; ALL_SIB_BASES } } else { baseReg = MCOperand :: CreateReg ( <NUM_LIT> ) ; } if ( insn . sibIndex != SIB_INDEX_NONE ) { switch ( insn . sibIndex ) { default : debug ( <STR_LIT> ) ; return true ; case SIB_INDEX_ ## x : \ indexReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; EA_BASES_32BIT EA_BASES_64BIT } } else { indexReg = MCOperand :: CreateReg ( <NUM_LIT> ) ; } scaleAmount = MCOperand :: CreateImm ( insn . sibScale ) ; } else { switch ( insn . eaBase ) { case EA_BASE_NONE : if ( insn . eaDisplacement == EA_DISP_NONE ) { debug ( <STR_LIT> ) ; return true ; } if ( insn . mode == MODE_64BIT ) baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; else baseReg = MCOperand :: CreateReg ( <NUM_LIT> ) ; indexReg = MCOperand :: CreateReg ( <NUM_LIT> ) ; break ; case EA_BASE_BX_SI : baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; indexReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; case EA_BASE_BX_DI : baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; indexReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; case EA_BASE_BP_SI : baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; indexReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; case EA_BASE_BP_DI : baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; indexReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; default : indexReg = MCOperand :: CreateReg ( <NUM_LIT> ) ; switch ( insn . eaBase ) { default : debug ( <STR_LIT> ) ; return true ; case EA_BASE_ ## x : \ baseReg = MCOperand :: CreateReg ( <STR_LIT> ) ; break ; ALL_EA_BASES ALL_REGS debug ( <STR_LIT> <STR_LIT> ) ; return true ; } } scaleAmount = MCOperand :: CreateImm ( <NUM_LIT> ) ;


<s> } bool Done = false ; if ( ! AFI -> isThumbFunction ( ) ) Done = rewrite<ISA_LIT>FrameIndex ( MI , i , BaseReg , Off , TII ) ; else { assert ( AFI -> isThumb2Function ( ) ) ; Done = rewriteT2FrameIndex ( MI , i , BaseReg , Off , TII ) ; } assert ( Done && <STR_LIT> ) ;


<s> if ( SrcTy -> isFPOrFPVectorTy ( ) || DstTy -> isFPOrFPVectorTy ( ) ) { unsigned SrcN = SrcTy -> isFPOrFPVectorTy ( ) ? getTypeNumElements ( SrcTy ) : <NUM_LIT> ; unsigned DstN = DstTy -> isFPOrFPVectorTy ( ) ? getTypeNumElements ( DstTy ) : <NUM_LIT> ; std :: pair < InstructionCost , MVT > SrcLT = TLI . getTypeLegalizationCost ( DL , SrcTy ) ;

std :: pair < InstructionCost , MVT > DstLT = TLI . getTypeLegalizationCost ( DL , DstTy ) ;


<s> const auto & MLI = getAnalysis < MachineLoopInfo > ( ) ; const auto & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineLoop * Loop = MLI . getLoopFor ( & MBB ) ; if ( ! Loop || Loop -> getHeader ( ) != & MBB ) return ; MachineBasicBlock * Bottom = <STR_LIT> ( Loop ) ; auto Iter = std :: next ( MachineFunction :: iterator ( Bottom ) ) ; if ( Iter == MF . end ( ) ) { MachineBasicBlock * Label = MF . CreateMachineBasicBlock ( ) ; Label -> addSuccessor ( Label ) ; MF . push_back ( Label ) ; Iter = std :: next ( MachineFunction :: iterator ( Bottom ) ) ; } MachineBasicBlock * AfterLoop = & * Iter ;

SmallPtrSet < const MachineInstr * , <NUM_LIT> > BeforeSet ;


<s> User * V = U . getUser ( ) ; while ( V ) { if ( isAMXCast ( dyn_cast < Instruction > ( V ) ) ) { if ( V -> use_empty ( ) ) break ; Use & U = * ( V -> use_begin ( ) ) ; OpNo = U . getOperandNo ( ) ; V = U . getUser ( ) ; } else if ( isAMXInstrinsic ( V ) ) { return getShape ( cast < IntrinsicInst > ( V ) , OpNo ) ; } else if ( isa < PHINode > ( V ) ) { if ( V -> use_empty ( ) ) break ;


<s> if ( MI . isDebugValue ( ) ) continue ; assert ( MI . isEHLabel ( ) && <STR_LIT> ) ; Sym = MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; break ; } if ( ! MMI -> hasCallSiteLandingPad ( Sym ) ) continue ; for ( unsigned CSI : MMI -> getCallSiteLandingPad ( Sym ) ) { CallSiteNumToLPad [ CSI ] . push_back ( & MBB ) ; MaxCSNum = std :: max ( MaxCSNum , CSI ) ; } } std :: vector < MachineBasicBlock * > LPadList ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > InvokeBBs ; LPadList . reserve ( CallSiteNumToLPad . size ( ) ) ; for ( unsigned CSI = <NUM_LIT> ; CSI <= MaxCSNum ; ++ CSI ) { for ( auto & LP : CallSiteNumToLPad [ CSI ] ) { LPadList . push_back ( LP ) ; InvokeBBs . insert ( LP -> pred_begin ( ) , LP -> pred_end ( ) ) ; } } assert ( ! LPadList . empty ( ) && <STR_LIT> ) ; MachineBasicBlock * DispatchBB = MF -> CreateMachineBasicBlock ( ) ; DispatchBB -> setIsEHPad ( true ) ; MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) ; DispatchBB -> addSuccessor ( TrapBB ) ; MachineBasicBlock * DispContBB = MF -> CreateMachineBasicBlock ( ) ; DispatchBB -> addSuccessor ( DispContBB ) ; MF -> push_back ( DispatchBB ) ; MF -> push_back ( DispContBB ) ; MF -> push_back ( TrapBB ) ; SetupEntryBlockForSjLj ( MI , BB , DispatchBB , FI ) ; MachineJumpTableInfo * JTI = MF -> getOrCreateJumpTableInfo ( getJumpTableEncoding ( ) ) ; unsigned MJTI = JTI -> createJumpTableIndex ( LPadList ) ; const <ISA_LIT>InstrInfo * XII = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) ; const <ISA_LIT>RegisterInfo & RI = XII -> getRegisterInfo ( ) ; if ( RI . hasBasePointer ( * MF ) ) { const bool FPIs64Bit = Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> setRestoreBasePointer ( MF ) ; unsigned FP = RI . getFrameRegister ( * MF ) ; unsigned BP = RI . getBaseRegister ( ) ; unsigned Op = FPIs64Bit ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( DispatchBB , DL , TII -> get ( Op ) , BP ) , FP , true , MFI -> getRestoreBasePointerOffset ( ) ) . addRegMask ( RI . getNoPreservedMask ( ) ) ; } else { BuildMI ( DispatchBB , DL , TII -> get ( <STR_LIT> ) ) . addRegMask ( RI . getNoPreservedMask ( ) ) ; }

unsigned IReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ;


<s> default : return true ; case 'b' : case 'h' : case 'w' : case 'k' : return printAsmMRegister ( MI -> getOperand ( OpNo ) , ExtraCode [ <NUM_LIT> ] ) ; }


<s> case <STR_LIT> :: tc_b4407292 : case <STR_LIT> :: tc_fc3999b4 : return true ; default : return false ; }


return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SP , DAG . getIntPtrConstant ( TFL -> getBackchainOffset ( MF ) , DL ) ) ;


<s> static void combineAwayG_UNMERGE_VALUES ( LegalizationArtifactCombiner & ArtCombiner , MachineInstr & MI , GISelObserverWrapper & Observer ) { SmallVector < Register , <NUM_LIT> > UpdatedDefs ; SmallVector < MachineInstr * , <NUM_LIT> > DeadInstrs ; ArtCombiner . tryCombineUnmergeValues ( MI , DeadInstrs , UpdatedDefs , Observer ) ; for ( MachineInstr * DeadMI : DeadInstrs ) DeadMI -> eraseFromParent ( ) ;


<s> if ( ! CI -> isTailCall ( ) ) return false ; const Function * ParentFn = CI -> getParent ( ) -> getParent ( ) ; if ( <STR_LIT> ( ParentFn -> getCallingConv ( ) ) ) return false ;


<s> static inline uint64_t __ev_convert_u64 ( __ev64_opaque__ a ) { return ( uint64_t ) a ;


<s> assert ( Kind == RegisterList && <STR_LIT> ) ;


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ; return true ;


<s> SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { const unsigned Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ;

FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ;


<s> bool Changed = false ; for ( MachineBasicBlock & MBB : F ) Changed |= runOnMachineBasicBlock ( MBB ) ; if ( Changed ) F . getRegInfo ( ) . invalidateLiveness ( ) ; return Changed ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ;

if ( ! hasThumb ( ) ) return Error ( L , <STR_LIT> ) ;


return S . schedule ( TopRoots , DAG ) ;


<s> unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; if ( ! Subtarget -> hasNEON ( ) || ( SubVecSize != <NUM_LIT> && SubVecSize % <NUM_LIT> != <NUM_LIT> ) ) return false ; unsigned NumStores = getNumInterleavedAccesses ( SubVecTy , DL ) ; Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( SI ) ; if ( EltTy -> isPointerTy ( ) ) { Type * IntTy = DL . getIntPtrType ( EltTy ) ; unsigned NumOpElts = dyn_cast < VectorType > ( Op0 -> getType ( ) ) -> getVectorNumElements ( ) ; Type * IntVecTy = VectorType :: get ( IntTy , NumOpElts ) ; Op0 = Builder . CreatePtrToInt ( Op0 , IntVecTy ) ; Op1 = Builder . CreatePtrToInt ( Op1 , IntVecTy ) ; SubVecTy = VectorType :: get ( IntTy , LaneLen ) ; } Value * BaseAddr = SI -> getPointerOperand ( ) ; if ( NumStores > <NUM_LIT> ) { LaneLen /= NumStores ; SubVecTy = VectorType :: get ( SubVecTy -> getVectorElementType ( ) , LaneLen ) ; BaseAddr = Builder . CreateBitCast ( BaseAddr , SubVecTy -> getVectorElementType ( ) -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ) ; } auto Mask = SVI -> getShuffleMask ( ) ; Type * PtrTy = SubVecTy -> getPointerTo ( SI -> getPointerAddressSpace ( ) ) ; Type * Tys [ <NUM_LIT> ] = { SubVecTy , PtrTy } ; static const <STR_LIT> StoreInts [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> } ; Function * StNFunc = <STR_LIT> ( SI -> getModule ( ) , StoreInts [ Factor - <NUM_LIT> ] , Tys ) ; for ( unsigned StoreCount = <NUM_LIT> ; StoreCount < NumStores ; ++ StoreCount ) { SmallVector < Value * , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < Factor ; i ++ ) { unsigned IdxI = StoreCount * LaneLen * Factor + i ; if ( Mask [ IdxI ] >= <NUM_LIT> ) { Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Builder , Mask [ IdxI ] , LaneLen , <NUM_LIT> ) ) ) ; } else { unsigned StartMask = <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < LaneLen ; j ++ ) { unsigned IdxJ = StoreCount * LaneLen * Factor + j ; if ( Mask [ IdxJ * Factor + IdxI ] >= <NUM_LIT> ) { StartMask = Mask [ IdxJ * Factor + IdxI ] - IdxJ ; break ; } } Ops . push_back ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Builder , StartMask , LaneLen , <NUM_LIT> ) ) ) ;


<s> void h8300_swap_into_er6 ( rtx addr ) { rtx insn = push ( HARD_FRAME_POINTER_REGNUM , false ) ; if ( frame_pointer_needed ) add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , gen_rtx_MEM ( Pmode , stack_pointer_rtx ) , <NUM_LIT> * UNITS_PER_WORD ) ) ; else add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> ) ) ) ; emit_move_insn ( hard_frame_pointer_rtx , addr ) ; if ( REGNO ( addr ) == SP_REG ) emit_move_insn ( hard_frame_pointer_rtx , plus_constant ( Pmode , hard_frame_pointer_rtx , GET_MODE_SIZE ( word_mode ) ) ) ;


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( <ISA_LIT>ABI == UnknownABI ) <ISA_LIT>ABI = has<ISA_LIT>64 ( ) ? N64 : O32 ; assert ( ( ( ! has<ISA_LIT>64 ( ) && ( isABI_O32 ( ) || isABI_EABI ( ) ) ) || ( has<ISA_LIT>64 ( ) && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) ) && <STR_LIT> ) ;

if ( TT . find ( <STR_LIT> ) == std :: string :: npos ) IsLinux = false ;


<s> <STR_LIT> AMDGPU<ISA_LIT>Device ( ) {


<s> if ( <STR_LIT> ( GO ) && ! GO -> hasSection ( ) && Kind . isReadOnly ( ) ) return ProgmemDataSection ;

return Base :: SelectSectionForGlobal ( GO , Kind , TM ) ;


<s> case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; const unsigned DstSz = VT . getScalarSizeInBits ( ) ; const unsigned SrcSz = VecVT . getVectorElementType ( ) . getSizeInBits ( ) ; ( void ) SrcSz ; assert ( SrcSz == Known . getBitWidth ( ) ) ; assert ( DstSz > SrcSz ) ;

if ( Op . getOpcode ( ) == <STR_LIT> ) Known = Known . sext ( DstSz ) ;


<s> return DAG . getNode ( Opc , DL , VT , Opnd0 , Opnd1 , Opnd2 ) ; } if ( IsSubAdd ) return SDValue ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Opnd0 , Opnd1 ) ;


<s> } std :: unique_ptr < <ISA_LIT>Operand > Offset ; OperandMatchResultTy ResTy = parse<ISA_LIT>AsmOperand ( Offset ) ; if ( ResTy != MatchOperand_Success || ! Offset ) return MatchOperand_NoMatch ;

Operands . push_back ( Offset -> isImm ( ) ? <STR_LIT> ( BaseReg , std :: move ( Offset ) ) : <STR_LIT> ( BaseReg , std :: move ( Offset ) ) ) ;


<s> static int cris_memory_move_cost ( machine_mode mode , reg_class_t rclass ATTRIBUTE_UNUSED , bool in ATTRIBUTE_UNUSED ) { if ( mode == QImode || mode == HImode ) return <NUM_LIT> ; else return <NUM_LIT> ;


<s> const LLT ValTy = MRI . getType ( ValReg ) ; if ( ! ValTy . isVector ( ) || ! ValTy . getElementType ( ) . isPointer ( ) || ValTy . getElementType ( ) . getAddressSpace ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MIRBuilder . setInstrAndDebugLoc ( MI ) ; unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getNumElements ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ;

if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE ) {


<s> static unsigned getRB ( uint32_t insn ) {

if ( ! get<ISA_LIT>RegisterFromNumbering ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) ) return UNSUPPORTED ;


<s> <STR_LIT> ( ) ; for ( size_t i = <NUM_LIT> ; i < ARRAY_SIZE ( riscv_builtins ) ; i ++ ) {

const struct riscv_builtin_description * d = & riscv_builtins [ i ] ;


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ;


<s> SmallVector < EVT , <NUM_LIT> > VTs ; ComputeValueVTs ( TLI , GV -> getParent ( ) -> getDataLayout ( ) , GV -> getValueType ( ) , VTs ) ; if ( VTs . size ( ) != <NUM_LIT> || TLI . getNumRegisters ( GV -> getParent ( ) -> getContext ( ) , VTs [ <NUM_LIT> ] ) != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; MVT VT = TLI . getRegisterType ( GV -> getParent ( ) -> getContext ( ) , VTs [ <NUM_LIT> ] ) ; bool Mutable = true ; <STR_LIT> Type = <STR_LIT> ( VT ) ; Sym -> setType ( <STR_LIT> ) ; Sym -> setGlobalType ( <STR_LIT> { uint8_t ( Type ) , Mutable } ) ; } emitVisibility ( Sym , GV -> getVisibility ( ) , ! GV -> isDeclaration ( ) ) ; if ( GV -> hasInitializer ( ) ) { assert ( getSymbolPreferLocal ( * GV ) == Sym ) ; emitLinkage ( GV , Sym ) ; getTargetStreamer ( ) -> emitGlobalType ( Sym ) ; OutStreamer -> emitLabel ( Sym ) ;


<s> if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; return <NUM_LIT> ; } if ( TREE_CODE ( type ) == VECTOR_TYPE && int_size_in_bytes ( type ) > ( TARGET_ALTIVEC_ABI ? <NUM_LIT> : <NUM_LIT> ) ) { static bool warned_for_pass_big_vectors = false ; if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; if ( ! warned_for_pass_big_vectors ) { warning ( OPT_Wpsabi , <STR_LIT> <STR_LIT> ) ; warned_for_pass_big_vectors = true ;


<s> for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; unsigned Reg ;

if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ;


<s> Register AndMaskSrc = LiveIn ; if ( Shift != <NUM_LIT> ) { auto ShiftAmt = B . buildConstant ( S32 , Shift ) ; AndMaskSrc = B . buildLShr ( S32 , LiveIn , ShiftAmt ) . getReg ( <NUM_LIT> ) ; } B . buildAnd ( DstReg , AndMaskSrc , B . buildConstant ( S32 , Mask >> Shift ) ) ; } else { B . buildCopy ( DstReg , LiveIn ) ; }


<s> return MCDisassembler :: Fail ; } Insn = <STR_LIT> :: read32be ( Bytes . data ( ) ) ; Result = decodeInstruction ( DecoderTable32 , MI , Insn , Address , this , STI ) ; Size = <NUM_LIT> ;


<s> __inline__ static unsigned long long sh_media_MSHLRD_W ( unsigned long long mm , unsigned int mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res ;


<s> static bool isNaturalMemoryOperand ( SDValue Op , unsigned ICmpType ) { LoadSDNode * Load = dyn_cast < LoadSDNode > ( Op . getNode ( ) ) ; if ( Load ) { if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return false ; switch ( Load -> getExtensionType ( ) ) { case <STR_LIT> : return true ; case <STR_LIT> : return ICmpType != <STR_LIT> ; case <STR_LIT> : return ICmpType != <STR_LIT> ;


<s> if ( reg_base == REG_X ) { gcc_assert ( ! reg_overlap_mentioned_p ( XEXP ( base , <NUM_LIT> ) , src ) ) ; avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; if ( ! reg_unused_after ( insn , XEXP ( base , <NUM_LIT> ) ) ) avr_asm_len ( <STR_LIT> , op , plen , <NUM_LIT> ) ; return <STR_LIT> ; } return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } else if ( GET_CODE ( base ) == PRE_DEC ) return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ;


<s> if ( ! plt1_entry ) fatal ( diag :: fail_allocate_memory_plt ) ;


return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false , false ) ;


if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return new Darwin<ISA_LIT>_64AsmBackend ( T , CPU ) ;


<s> if ( TREE_CODE ( exp ) == VAR_DECL && ! is_global_var ( exp ) ) return false ; if ( TREE_CODE ( exp ) == VAR_DECL && DECL_SECTION_NAME ( exp ) ) { const char * section = DECL_SECTION_NAME ( exp ) ; if ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> ) return true ;


<s> unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; } unsigned FPReg = TRI -> getFrameRegister ( MF ) ; unsigned Opc = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ;


<s> SDLoc dl ( Op ) ; unsigned Opc ; SDValue CompareFlag ; if ( LHS . getValueType ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) . getValue ( <NUM_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } return DAG . getNode ( Opc , dl , TrueVal . getValueType ( ) , TrueVal , FalseVal , CompareFlag ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) { MachineOperand & MO = MBBI -> getOperand ( I ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , this , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != <STR_LIT> && CS != <STR_LIT> && CS != <STR_LIT> ) return CS ; }


<s> void Initialize ( MCContext & ctx , const TargetMachine & TM ) override { TargetLoweringObjectFile :: Initialize ( ctx , TM ) ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( RegOrOffset ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( RegOrOffset ) ) ; } getStreamer ( ) . EmitInstruction ( Inst , STI ) ; Inst . clear ( ) ; const MCSymbolRefExpr * HiExpr = MCSymbolRefExpr :: Create ( Sym . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_HI , MCA . getContext ( ) ) ; const MCSymbolRefExpr * LoExpr = MCSymbolRefExpr :: Create ( Sym . getName ( ) , MCSymbolRefExpr :: VK_<ISA_LIT>_GPOFF_LO , MCA . getContext ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ;


<s> auto SC = static_cast < StorageClass :: StorageClass > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( ST -> getTarget<ISA_LIT>Version ( ) >= <NUM_LIT> || SC == StorageClass :: Input || SC == StorageClass :: Output ) { MachineFunction * MF = MI -> getMF ( ) ; Register Reg = MAI -> getRegisterAlias ( MF , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; InterfaceIDs . insert ( Reg ) ; } } for ( MachineInstr * MI : MAI -> getMSInstrs ( <STR_LIT> ) ) { <ISA_LIT>MCInstLower MCInstLowering ; MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst , MF , MAI ) ; for ( Register Reg : InterfaceIDs ) { assert ( Reg . isValid ( ) ) ;

TmpInst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> if ( DEFAULT_ABI == ABI_DARWIN && crtl -> calls_eh_return && ! TARGET_ALTIVEC ) return FIRST_ALTIVEC_REGNO + <NUM_LIT> ; for ( i = FIRST_ALTIVEC_REGNO + <NUM_LIT> ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( save_reg_p ( i ) ) break ;


<s> case R8 : case R9 : case R10 : case R11 : case R12 : return SplitFramePushPop ;


<s> if ( IsFunc ) report_fatal_error ( <STR_LIT> ) ; Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; }

return MCOperand :: createExpr ( Expr ) ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) { return new <ISA_LIT>MCAsmInfo ( TT ) ;


<s> if ( ! MO . isReg ( ) || MO . getReg ( ) != DepReg || ! MO . isImplicit ( ) ) continue ;

if ( CheckDef == MO . isDef ( ) ) return true ;


<s> if ( DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && FLOAT128_IEEE_P ( TYPE_MODE ( type ) ) ) { if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; return <NUM_LIT> ; } if ( DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P ( type ) ) { if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; return <NUM_LIT> ; } if ( int_size_in_bytes ( type ) < <NUM_LIT> ) { if ( TARGET_DEBUG_ARG ) fprintf ( stderr , <STR_LIT> ) ; return <NUM_LIT> ;


<s> for ( int i = <NUM_LIT> ; i <= Counter ; ++ i ) { unsigned v_reg = MRI -> createVirtualRegister ( PrologBlock -> getParent ( ) -> getSubtarget ( ) . getTargetLowering ( ) -> getRegClassFor ( <STR_LIT> ) ) ; if ( LoopInst -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned LoopCounter = LoopInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * MI = BuildMI ( * PrologBlock , EpilogInserter , DebugLoc ( ) , TII -> get ( Opcode ) , v_reg ) . addReg ( PrevReg ) . addReg ( LoopCounter ) . addImm ( <ISA_LIT>II :: OpType :: INT32 ) . addImm ( <NUM_LIT> ) . addReg ( LoopCounter , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; LLVM_DEBUG ( ExecThreads [ i ] . Epilog . push_back ( MI ) ) ; EpilogInserter = ++ MachineBasicBlock :: iterator ( MI ) ; PrevReg = v_reg ; } else { int Decrement = Inclusive ? i - <NUM_LIT> : i ; MachineInstr * MI = BuildMI ( * PrologBlock , EpilogInserter , DebugLoc ( ) , TII -> get ( Opcode ) , v_reg ) . addReg ( BoundaryReg ) . addImm ( LoopInst -> getOperand ( <NUM_LIT> ) . getImm ( ) * Decrement ) . addImm ( <ISA_LIT>II :: OpType :: INT32 ) . addImm ( <NUM_LIT> ) . addReg ( LoopCounter , RegState :: Undef ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;

LLVM_DEBUG ( ExecThreads [ Counter - i ] . Epilog . push_back ( MI ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getMaxAlusPerClause ( ) const { return <NUM_LIT> ;


<s> std :: tie ( Mask , VL ) = getDefaultVLOps ( VecVT , ContainerVT , DL , DAG , Subtarget ) ; SDValue NeutralElem = DAG . getNeutralElement ( BaseOpc , DL , VecEltVT , SDNodeFlags ( ) ) ; SDValue IdentitySplat = lowerScalarSplat ( NeutralElem , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) , M1VT , DL , DAG , Subtarget ) ; SDValue Reduction = DAG . getNode ( RVVOpcode , DL , M1VT , DAG . getUNDEF ( M1VT ) , Vec , IdentitySplat , Mask , VL ) ; SDValue Elt0 = DAG . getNode ( <STR_LIT> , DL , VecEltVT , Reduction , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; return DAG . getSExtOrTrunc ( Elt0 , DL , Op . getValueType ( ) ) ;


emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) , LCT_NORMAL , VOIDmode , <NUM_LIT> ) ;


<s> if ( IsFunclet && Terminator -> getOpcode ( ) == <STR_LIT> ) emitCatchRetReturnValue ( MBB , FirstCSPop , & * Terminator ) ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI . hasVarSizedObjects ( ) ) NumBytes += mergeSPUpdates ( MBB , MBBI , true ) ; if ( ( TRI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) && ! IsFunclet ) { if ( TRI -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; unsigned SEHFrameOffset = calculateSetFPREG ( SEHStackAllocAmt ) ; uint64_t LEAAmount = IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : - CSSize ; if ( LEAAmount != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( Uses64BitFramePtr ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , LEAAmount ) ; -- MBBI ; } else { unsigned Opc = ( Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; -- MBBI ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , DL , NumBytes , true ) ; if ( ! hasFP ( MF ) && NeedsDwarfCFI ) { BuildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createDefCfaOffset ( nullptr , - CSSize - SlotSize ) ) ; } -- MBBI ; } if ( NeedsWin64CFI && MF . hasWinCFI ( ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) ; if ( ! hasFP ( MF ) && NeedsDwarfCFI ) { MBBI = FirstCSPop ; int64_t Offset = - CSSize - SlotSize ;


<s> static bool classof ( const MCExpr * E ) {

return E -> getKind ( ) == MCExpr :: Target ;


<s> Pub ( * pub ) , MaxRegs ( availRegs ) , NumLocs ( <NUM_LIT> ) , ChildrenMaxCumLocs ( <NUM_LIT> ) , FirstUsableReg ( <NUM_LIT> ) , FirstUsableStackSlot ( <NUM_LIT> ) , NeedsScopeSpill ( true ) { createLiveRanges ( ) ; assignLocations ( ) ;


<s> assert ( LSCEV && <STR_LIT> ) ; bool FoundBucket = false ; for ( auto & B : Buckets ) { if ( cast < SCEVAddRecExpr > ( B . BaseSCEV ) -> getStepRecurrence ( * SE ) != cast < SCEVAddRecExpr > ( LSCEV ) -> getStepRecurrence ( * SE ) ) continue ; const SCEV * Diff = SE -> getMinusSCEV ( LSCEV , B . BaseSCEV ) ; if ( isValidDiff ( Diff ) ) { B . Elements . push_back ( BucketElement ( Diff , MemI ) ) ; FoundBucket = true ; break ; } } if ( ! FoundBucket ) { if ( Buckets . size ( ) == MaxCandidateNum ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MaxCandidateNum << <STR_LIT> ) ; return ;


<s> SMLoc S , E ; OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( ResTy == MatchOperand_Success ) return false ; if ( ResTy == MatchOperand_ParseFail ) return true ; switch ( getLexer ( ) . getKind ( ) ) { default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Identifier : { if ( ! tryParseRegisterWithWriteBack ( Operands ) ) return false ; int Res = tryParseShiftRegister ( Operands ) ; if ( Res == <NUM_LIT> ) return false ; else if ( Res == - <NUM_LIT> ) return true ; if ( Mnemonic == <STR_LIT> && Parser . getTok ( ) . getString ( ) . equals_lower ( <STR_LIT> ) ) { S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , S ) ) ; return false ; } } case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: String : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ;


<s> if ( INTEGRAL_TYPE_P ( t ) && INTEGRAL_TYPE_P ( builtin_type ) ) return true ; else return lang_hooks . types_compatible_p ( t , builtin_type ) ;


<s> const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ;


<s> void setCalleeSavedFrameSize ( unsigned Bytes ) {


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = TRI -> getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ;


<s> addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . useConstIslands ( ) ) addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isTargetNaCl ( ) ) {

addPass ( create<ISA_LIT>NaClRewritePass ( ) ) ;


<s> void <ISA_LIT>AnalyzeImmediate :: ReplaceADDiuSLLWithLUi ( InstSeq & Seq ) { if ( ( Seq . size ( ) < <NUM_LIT> ) || ( Seq [ <NUM_LIT> ] . Opc != ADDiu ) || ( Seq [ <NUM_LIT> ] . Opc != SLL ) || ( Seq [ <NUM_LIT> ] . ImmOpnd < <NUM_LIT> ) ) return ;

int64_t Imm = ( ( ( int64_t ) Seq [ <NUM_LIT> ] . ImmOpnd ) << <NUM_LIT> ) >> <NUM_LIT> ;


<s> DollarIsPC = true ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ; AllowAdditionalComments = false ; AllowQuestionAtStartOfIdentifier = true ; AllowDollarAtStartOfIdentifier = true ;


<s> mips_set_compression_mode ( mips_get_compress_mode ( fndecl ) ) ;


<s> case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; case <STR_LIT> : { if ( OpNum == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RI . isPhysicalRegister ( SrcReg ) && ! RI . isLowRegister ( SrcReg ) ) return false ; } else {

unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> emit_insn ( gen_th_fmv_x_w ( low_dest , src ) ) ; emit_insn ( gen_th_fmv_x_hw ( high_dest , src ) ) ; return ; } } rtx low_dest = riscv_subword ( dest , false ) ; if ( REG_P ( low_dest ) && reg_overlap_mentioned_p ( low_dest , src ) ) { riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ; riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; } else { riscv_emit_move ( low_dest , riscv_subword ( src , false ) ) ; riscv_emit_move ( riscv_subword ( dest , true ) , riscv_subword ( src , true ) ) ; }


<s> if ( ! VT . isFixedLengthVector ( ) ) return false ; switch ( VT . getVectorElementType ( ) . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: iterator RegIter ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPURegs ) ; ++ I ) Reserved . set ( ReservedCPURegs [ I ] ) ; return Reserved ;


<s> void <ISA_LIT>BrCCMCExpr :: fixELFSymbolsInTLSFixups ( MCAssembler & assembler ) const {


if ( r <= <NUM_LIT> ) return reg_class_tab [ r ] ;


<s> Optional < DestSourcePair > <ISA_LIT>16InstrInfo :: isCopyInstrImpl ( const MachineInstr & MI ) const { if ( MI . isMoveReg ( ) ) return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ;


<s> llvm_unreachable ( <STR_LIT> ) ; } return Res ; } if ( const MCSymbolRefExpr * MSRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ) { StringRef Symbol = MSRE -> getSymbol ( ) . getName ( ) ; MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; Res = MCSymbolRefExpr :: Create ( Symbol , VK , getContext ( ) ) ; return Res ; } if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { MCSymbolRefExpr :: VariantKind VK = getVariantKind ( RelocStr ) ; if ( isa < MCSymbolRefExpr > ( BE -> getLHS ( ) ) && isa < MCSymbolRefExpr > ( BE -> getRHS ( ) ) && ( VK == MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI || VK == MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO ) ) { if ( VK == MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI ) return <ISA_LIT>MCExpr :: CreateHi ( Expr , getContext ( ) ) ; return <ISA_LIT>MCExpr :: CreateLo ( Expr , getContext ( ) ) ; } const MCExpr * LExp = evaluateRelocExpr ( BE -> getLHS ( ) , RelocStr ) ; const MCExpr * RExp = evaluateRelocExpr ( BE -> getRHS ( ) , RelocStr ) ; Res = MCBinaryExpr :: Create ( BE -> getOpcode ( ) , LExp , RExp , getContext ( ) ) ; return Res ; } if ( const MCUnaryExpr * UN = dyn_cast < MCUnaryExpr > ( Expr ) ) { const MCExpr * UnExp = evaluateRelocExpr ( UN -> getSubExpr ( ) , RelocStr ) ; Res = MCUnaryExpr :: Create ( UN -> getOpcode ( ) , UnExp , getContext ( ) ) ;


<s> Instruction * <ISA_LIT>TargetLowering :: emitLeadingFence ( IRBuilder < > & Builder , AtomicOrdering Ord , bool IsStore , bool IsLoad ) const { switch ( Ord ) { case AtomicOrdering :: NotAtomic : case AtomicOrdering :: Unordered : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : case AtomicOrdering :: Acquire : return nullptr ; case AtomicOrdering :: SequentiallyConsistent :


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = <NUM_LIT> ; i < XVECLEN ( pat , <NUM_LIT> ) ; i ++ ) { rtx sub = XVECEXP ( pat , <NUM_LIT> , i ) ; if ( GET_CODE ( sub ) == USE ) {


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; return splitAndLowerVectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ;


<s> FunctionType * AsmFTy = FunctionType :: get ( Type :: getVoidTy ( C ) , AsmArgTypes , false ) ;

InlineAsm * IA = InlineAsm :: get ( AsmFTy , AsmText , <STR_LIT> , true , false , InlineAsm :: AD_ATT ) ;


<s> case 'c' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'l' : case 'N' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'f' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'd' :


<s> uint32_t size = pSD . getSection ( ) . size ( ) ; llvm :: StringRef region = pInput . memArea ( ) -> request ( offset , size ) ; if ( region . size ( ) == <NUM_LIT> ) { frag = new FillFragment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; } else { frag = new RegionFragment ( region ) ; } ObjectBuilder :: AppendFragment ( * frag , pSD ) ;


<s> void addSImm5Plus1Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; int64_t Imm = <NUM_LIT> ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstant = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; assert ( IsConstant && <STR_LIT> ) ; ( void ) IsConstant ;

Inst . addOperand ( MCOperand :: createImm ( Imm - <NUM_LIT> ) ) ;


<s> if ( TII -> isPredicated ( BI ) ) continue ; if ( TII -> isTransOnly ( BI ) ) continue ; int OperandIdx = TII -> getOperandIdx ( BI -> getOpcode ( ) , <STR_LIT> ) ; if ( OperandIdx < <NUM_LIT> ) continue ; if ( BI -> getOperand ( OperandIdx ) . getImm ( ) == <NUM_LIT> ) continue ; unsigned Dst = BI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BI -> getOpcode ( ) == AMDGPU :: DOT4_r600_real ) { Result [ Dst ] = AMDGPU :: PV_X ; continue ; } unsigned PVReg = <NUM_LIT> ; switch ( TRI . getHWRegChan ( Dst ) ) { case <NUM_LIT> : PVReg = AMDGPU :: PV_X ; break ; case <NUM_LIT> : PVReg = AMDGPU :: PV_Y ; break ; case <NUM_LIT> : PVReg = AMDGPU :: PV_Z ; break ; case <NUM_LIT> : PVReg = AMDGPU :: PV_W ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Result [ Dst ] = PVReg ;

} while ( ( ++ BI ) -> isBundledWithPred ( ) ) ;


<s> static __inline qword si_fnms ( qword a , qword b , qword c ) { return ( ( qword ) ( vec_nmsub ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b ) , ( vec_float4 ) ( c ) ) ) ) ;


<s> BasicBlock :: iterator I = std :: prev ( B -> end ( ) ) , NextI , Begin = B -> begin ( ) ; while ( true ) { if ( HasCutoff && ( ExtractCount >= Cutoff ) ) return Changed ; bool Last = ( I == Begin ) ; if ( ! Last ) NextI = std :: prev ( I ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , STI ( STI ) {


<s> std :: unique_ptr < MCObjectWriter > llvm :: create<ISA_LIT>MachObjectWriter ( raw_pwrite_stream & OS , bool Is64Bit , uint32_t CPUType , uint32_t CPUSubtype ) {

return createMachObjectWriter ( llvm :: make_unique < <ISA_LIT>MachObjectWriter > ( Is64Bit , CPUType , CPUSubtype ) , OS , false ) ;


<s> if ( NumNonZero > <NUM_LIT> && ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; return LowerBuildVectorAsInsert ( Op , NonZeros , NumNonZero , NumZero , DAG , Subtarget ) ;


<s> if ( isVGPRClass ( RC ) ) return getAlignedVGPRClassForBitWidth ( Size ) ; if ( isAGPRClass ( RC ) ) return getAlignedAGPRClassForBitWidth ( Size ) ; if ( isVectorSuperClass ( RC ) ) return getAlignedVectorSuperClassForBitWidth ( Size ) ; return RC ;


<s>
OS
<<
'('
<<
OpcodeName
(
TII
,
MI
)
;
for
(
const
MachineOperand
&
MO
:
MI
->
uses
(
)
)
switch
(
MO
.
getType
(
)
)
{
default
:
llvm_unreachable
(
<STR_LIT>
)
;
case
MachineOperand
::
MO_Register
:
{
if
(
MO
.
isImplicit
(
)
)
continue
;
unsigned
Reg
=
MO
.
getReg
(
)
;
OS
<<
<STR_LIT>
<<
TargetRegisterInfo
::
virtReg2Index
(
Reg
)
;
}
break
;
case
MachineOperand
::
MO_Immediate
:
{
OS
<<
' '
<<
MO
.
getImm
(
)
;
}
break
;
case
MachineOperand
::
MO_FPImmediate
:
{

OS
<<
' '
<<
toString
(
MO
.
getFPImm
(
)
->
getValueAPF
(
)
)
;


<s> ApplyFunctionEntry ( ApplyFunctionType pFunc , const char * pName , size_t pSize = <NUM_LIT> ) : func ( pFunc ) , name ( pName ) , size ( pSize ) {


<s> const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; SavedVGPRs . clearBitsNotInMask ( TRI -> getAllVGPRRegMask ( ) ) ; const bool WillHaveFP = FrameInfo . hasCalls ( ) && ( SavedVGPRs . any ( ) || ! allStackObjectsAreDead ( FrameInfo ) ) ; for ( auto SSpill : MFI -> getSGPRSpillVGPRs ( ) ) SavedVGPRs . reset ( SSpill . VGPR ) ; const bool HasFP = WillHaveFP || hasFP ( MF ) ; if ( ! HasFP ) return ; if ( MFI -> haveFreeLanesForSGPRSpill ( MF , <NUM_LIT> ) ) { int NewFI = MF . getFrameInfo ( ) . CreateStackObject ( <NUM_LIT> , <NUM_LIT> , true , nullptr , TargetStackID :: SGPRSpill ) ; if ( ! MFI -> allocateSGPRSpillToVGPR ( MF , NewFI ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {

return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> static const char * getSpillLibCallName ( const MachineFunction & MF , const std :: vector < CalleeSavedInfo > & CSI ) { static const char * const SpillLibCalls [ ] = {


<s> unsigned CommuteIdx1 = TargetInstrInfo :: CommuteAnyOperandIndex ; bool CanCommute = TII -> findCommutedOpIndices ( * MI , CommuteIdx0 , CommuteIdx1 ) ; if ( CanCommute ) { if ( CommuteIdx0 == OpNo ) CommuteOpNo = CommuteIdx1 ; else if ( CommuteIdx1 == OpNo ) CommuteOpNo = CommuteIdx0 ; } if ( CanCommute && ( ! MI -> getOperand ( CommuteIdx0 ) . isReg ( ) || ! MI -> getOperand ( CommuteIdx1 ) . isReg ( ) ) ) return false ; if ( ! CanCommute || ! TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ) return false ; if ( ! TII -> isOperandLegal ( * MI , CommuteOpNo , OpToFold ) ) { if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && ( OpToFold -> isImm ( ) || OpToFold -> isFI ( ) ) ) { MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; unsigned OtherIdx = CommuteOpNo == CommuteIdx0 ? CommuteIdx1 : CommuteIdx0 ; MachineOperand & OtherOp = MI -> getOperand ( OtherIdx ) ; if ( ! OtherOp . isReg ( ) || ! TII -> getRegisterInfo ( ) . isVGPR ( MRI , OtherOp . getReg ( ) ) ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isDef ( ) ) ; unsigned MaybeCommutedOpc = MI -> getOpcode ( ) ; int Op32 = <STR_LIT> ( MaybeCommutedOpc ) ; FoldList . push_back ( FoldCandidate ( MI , CommuteOpNo , OpToFold , true , Op32 ) ) ;


<s> MCTargetOptions MCOpts = Options . MCOptions ; if ( MCOpts . getABIName ( ) . empty ( ) ) { _ABI = Call0_ABI ; } else { if ( MCOpts . getABIName ( ) == <STR_LIT> ) _ABI = Window_ABI ; else if ( MCOpts . getABIName ( ) == <STR_LIT> ) _ABI = Call0_ABI ; else { _ABI = Call0_ABI ;

errs ( ) << <STR_LIT> << MCOpts . getABIName ( ) << <STR_LIT> ;


<s> static nodes_iterator nodes_begin ( const GraphType & G ) {


<s> Value * Z = Builder . CreateFPToUI ( ScaledY , I32Ty ) ; Value * NegY = Builder . CreateSub ( Zero , Y ) ; Value * NegYZ = Builder . CreateMul ( NegY , Z ) ; Z = Builder . CreateAdd ( Z , getMulHu ( Builder , Z , NegYZ ) ) ; Value * Q = getMulHu ( Builder , X , Z ) ; Value * R = Builder . CreateSub ( X , Builder . CreateMul ( Q , Y ) ) ; Value * Cond = Builder . CreateICmpUGE ( R , Y ) ; if ( IsDiv ) Q = Builder . CreateSelect ( Cond , Builder . CreateAdd ( Q , One ) , Q ) ; R = Builder . CreateSelect ( Cond , Builder . CreateSub ( R , Y ) , R ) ; Cond = Builder . CreateICmpUGE ( R , Y ) ; Value * Res ; if ( IsDiv ) Res = Builder . CreateSelect ( Cond , Builder . CreateAdd ( Q , One ) , Q ) ; else Res = Builder . CreateSelect ( Cond , Builder . CreateSub ( R , Y ) , R ) ; if ( IsSigned ) { Res = Builder . CreateXor ( Res , Sign ) ; Res = Builder . CreateSub ( Res , Sign ) ; } Res = Builder . CreateTrunc ( Res , Ty ) ; return Res ;


<s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerATOMIC_SWAP ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG , * this , Subtarget ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG , * this , Subtarget ) ; case <STR_LIT> : return lowerBUILD_<ISA_LIT>CTOR ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE ( Op , DAG ) ; case <STR_LIT> :


<s> assert ( ! BytesRemoved && <STR_LIT> ) ; MachineBasicBlock :: reverse_iterator I = MBB . rbegin ( ) , REnd = MBB . rend ( ) ; unsigned removed = <NUM_LIT> ; while ( I != REnd && removed < <NUM_LIT> ) { if ( I -> isDebugInstr ( ) ) {


<s> bool SelectMOVWAddressRef ( SDValue N , SDValue & Imm , SDValue & Shift ) { Imm = N ; Shift = CurDAG -> getTargetConstant ( LogShift , <STR_LIT> ) ;


<s> MCInst Inst ; unsigned MatchResult ; MatchResult = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ; switch ( MatchResult ) { default : break ; case Match_Success : Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst ) ; return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ; ++ I ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ;


<s> Register coord = OrigArgs [ <NUM_LIT> ] ; auto MIB = MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( resVReg ) . addUse ( GR -> get<ISA_LIT>TypeID ( retType ) ) . addUse ( image ) . addUse ( coord ) . addImm ( ImageOperand :: Sample ) . addUse ( OrigArgs [ <NUM_LIT> ] ) ;


<s> uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result ;


<s> if ( P == std :: numeric_limits < int > :: min ( ) ) return false ; TotalP += P ; if ( isInduction ( DR , IRM ) ) TotalP -= <NUM_LIT> ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) { MachineInstr * UseI = U -> getParent ( ) ; if ( isFixedInstr ( UseI ) ) { FixedNum ++ ; for ( auto & Op : UseI -> operands ( ) ) { if ( Op . isReg ( ) && Part . count ( Op . getReg ( ) ) ) if ( Op . getSubReg ( ) ) TotalP -= <NUM_LIT> ; } continue ; } if ( UseI -> isPHI ( ) ) { const MachineBasicBlock * PB = UseI -> getParent ( ) ; const MachineLoop * L = MLI -> getLoopFor ( PB ) ; if ( L && L -> getHeader ( ) == PB ) LoopPhiNum ++ ; } int32_t P = profit ( UseI ) ; if ( P == std :: numeric_limits < int > :: min ( ) ) return false ; TotalP += P ; }


<s> SDValue In1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2L = Node -> getOperand ( <NUM_LIT> ) ; SDValue In2H = Node -> getOperand ( <NUM_LIT> ) ; SDValue Tmp0 , Tmp1 , Tmp2 , Tmp3 ;

if ( ! SelectAddr ( In1 , In1 , Tmp0 , Tmp1 , Tmp2 , Tmp3 ) ) return NULL ;


<s> case <STR_LIT> : case <STR_LIT> : return VTBits ; case <STR_LIT> : { unsigned Tmp0 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; if ( Tmp0 == <NUM_LIT> ) return <NUM_LIT> ; unsigned Tmp1 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , DemandedElts , Depth + <NUM_LIT> ) ; return std :: min ( Tmp0 , Tmp1 ) ; } case <STR_LIT> : { unsigned Tmp0 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Tmp0 == <NUM_LIT> ) return <NUM_LIT> ; unsigned Tmp1 = DAG . ComputeNumSignBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; return std :: min ( Tmp0 , Tmp1 ) ; } } if ( isTargetShuffle ( Opcode ) ) { SmallVector < int , <NUM_LIT> > Mask ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( getTargetShuffleMask ( Op . getNode ( ) , VT . getSimpleVT ( ) , true , Ops , Mask ) ) { unsigned NumOps = Ops . size ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( Mask . size ( ) == NumElts ) { SmallVector < APInt , <NUM_LIT> > DemandedOps ( NumOps , APInt ( NumElts , <NUM_LIT> ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { if ( ! DemandedElts [ i ] ) continue ; int M = Mask [ i ] ; if ( M == SM_SentinelUndef ) { return <NUM_LIT> ; } else if ( M == SM_SentinelZero ) { continue ; } assert ( <NUM_LIT> <= M && ( unsigned ) M < ( NumOps * NumElts ) && <STR_LIT> ) ; unsigned OpIdx = ( unsigned ) M / NumElts ; unsigned EltIdx = ( unsigned ) M % NumElts ; if ( Ops [ OpIdx ] . getValueType ( ) != VT ) { return <NUM_LIT> ; } DemandedOps [ OpIdx ] . setBit ( EltIdx ) ; }


IEEE ( true ) , DX10Clamp ( true ) , FP32Denormals ( true ) , FP64FP16Denormals ( true ) {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; <STR_LIT> ET = getShiftExtendType ( ) ;

bool IsSigned = ET == <STR_LIT> || ET == <STR_LIT> ;


<s> unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getIntPtrConstant ( NormalizedIdxVal ) ; return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec , VecIdx ) ;


<s> ExpandPseudo :: ExpandPseudo ( MachineFunction & MF_ ) : MF ( MF_ ) , MRI ( MF . getRegInfo ( ) ) , Subtarget ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , TII ( * static_cast < const <ISA_LIT>SEInstrInfo * > ( Subtarget . getInstrInfo ( ) ) ) , RegInfo ( * Subtarget . getRegisterInfo ( ) ) {


<s> dst_base_reg = copy_to_mode_reg ( SImode , XEXP ( dstmem , <NUM_LIT> ) ) ; src_base_reg = copy_to_mode_reg ( SImode , XEXP ( srcmem , <NUM_LIT> ) ) ; out_words = in_words = INTVAL ( total_bytes ) / UNITS_PER_WORD ; emit_insn ( nds32_expand_load_multiple ( <NUM_LIT> , in_words , src_base_reg , srcmem ) ) ; emit_insn ( nds32_expand_store_multiple ( <NUM_LIT> , out_words , dst_base_reg , dstmem ) ) ; return <NUM_LIT> ;


<s> ++ Count ; } if ( Count ) return ( Count - <NUM_LIT> ) ;


<s> } bool Changed = false ; NumHWLoopsInternal = <NUM_LIT> ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; const <ISA_LIT>Subtarget & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = HST . getInstrInfo ( ) ; TRI = HST . getRegisterInfo ( ) ; for ( auto & L : * MLI ) if ( ! L -> getParentLoop ( ) ) { bool L0Used = false ; bool L1Used = false ; KnownHardwareLoops . clear ( ) ; Changed |= convertToHardwareLoop ( L , L0Used , L1Used ) ; }


<s> if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } } Parser . Lex ( ) ;


<s> initialize<ISA_LIT>LongBranchPass ( PR ) ; initialize<ISA_LIT>LDCleanupPass ( PR ) ; initialize<ISA_LIT>ShortenInstPass ( PR ) ;

initialize<ISA_LIT>PostRewritePass ( PR ) ;