<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ;


<s> if ( ! TT . empty ( ) ) return <NUM_LIT> ; if ( M . getEndianness ( ) == Module :: LittleEndian && M . getPointerSize ( ) == Module :: Pointer32 ) return <NUM_LIT> ; else if ( M . getEndianness ( ) != Module :: AnyEndianness || M . getPointerSize ( ) != Module :: AnyPointerSize ) return <NUM_LIT> ; return getJITMatchQuality ( ) / <NUM_LIT> ;


<s> <ISA_LIT>ISelAddressMode ( ) : BaseType ( RegBase ) , Disp ( <NUM_LIT> ) , GV ( nullptr ) , CP ( nullptr ) , BlockAddr ( nullptr ) , ES ( nullptr ) , JT ( - <NUM_LIT> ) , Align ( <NUM_LIT> ) {


<s> unsigned <ISA_LIT>LoopIdiomRecognize :: getStoreSizeInBytes ( StoreInst * SI ) { uint64_t SizeInBits = DL -> getTypeSizeInBits ( SI -> getValueOperand ( ) -> getType ( ) ) ; assert ( ( ( SizeInBits & <NUM_LIT> ) || ( SizeInBits >> <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; return ( unsigned ) SizeInBits >> <NUM_LIT> ;


<s> if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; if ( RelocM == Reloc :: Static ) return Result ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , PtrVT , Result , PICLabel ) ;


<s> Type * SingleMemOpTy = VectorType :: get ( VecTy -> getVectorElementType ( ) , LegalVT . getVectorNumElements ( ) ) ; unsigned MemOpCost = getMemoryOpCost ( Opcode , SingleMemOpTy , MaybeAlign ( Alignment ) , AddressSpace ) ; VectorType * VT = VectorType :: get ( ScalarTy , VF ) ; EVT ETy = TLI -> getValueType ( DL , VT ) ; if ( ! ETy . isSimple ( ) ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; static const CostTblEntry AVX2InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , {


return isExtImm < <NUM_LIT> > ( true , <NUM_LIT> ) ;


<s> if ( has_scale ) return true ; if ( split_cost < <NUM_LIT> ) return false ; if ( regno0 == regno1 || regno0 == regno2 ) return false ; return true ; } dist_define = distance_non_agu_define ( regno1 , regno2 , insn ) ;

dist_use = distance_agu_use ( regno0 , insn ) ;


* __carry = ( __builtin_arm_get_fpscr_nzcvqc ( ) >> <NUM_LIT> ) & <NUM_LIT> ;


<s> bool AMDGPUInstrInfo :: hasLoadFromStackSlot ( const MachineInstr * MI , const MachineMemOperand * & MMO , int & FrameIndex ) const { return false ;


<s> static MCCodeEmitter * createCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & , MCContext & Ctx ) { return create<ISA_LIT>MCCodeEmitter ( MCII ) ;


<s> void <ISA_LIT>InstPrinter :: printU2ImmOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= <NUM_LIT> && <STR_LIT> ) ;


<s> case X86_DIRFLAG : return ix86_dirflag_mode_entry ( ) ; case AVX_U128 : return ix86_avx_u128_mode_entry ( ) ; case I387_TRUNC :


<s> SDValue Pg = getPredicateForVector ( DAG , DL , RoundVT ) ; Val = convertToScalableVector ( DAG , ContainerSrcVT , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , RoundVT , Pg , Val , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( RoundVT ) ) ; Val = getSVESafeBitCast ( ContainerSrcVT . changeTypeToInteger ( ) , Val , DAG ) ; Val = convertFromScalableVector ( DAG , SrcVT . changeTypeToInteger ( ) , Val ) ; Val = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , Val ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , Val ) ;


<s> if ( ! ( mode == SFmode || mode == DFmode ) ) return false ;

return aarch64_float_const_representable_p ( x ) ;


<s> if ( ! Subtarget -> is64Bit ( ) || ( ( M == CodeModel :: Small || M == CodeModel :: Kernel ) && TM . getRelocationModel ( ) == Reloc :: Static ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else { JumpTableSDNode * J = cast < JumpTableSDNode > ( N0 ) ; AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } return false ;


<s> if ( Kind != SK_Reverse ) return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index , SubTp ) ; static const CostTblEntry < <STR_LIT> > NEONShuffleTbl [ ] = {


<s> void <ISA_LIT>ELFStreamer :: EmitValueImpl ( const MCExpr * Value , unsigned Size , SMLoc Loc ) { MCELFStreamer :: EmitValueImpl ( Value , Size , Loc ) ; Labels . clear ( ) ;


<s> if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ;


<s> CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>32 ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; } return Chain ;


<s> static void ix86_expand_divmod_libfunc ( rtx libfunc , machine_mode mode , rtx op0 , rtx op1 , rtx * quot_p , rtx * rem_p ) { rtx rem = assign_386_stack_local ( mode , SLOT_TEMP ) ; rtx quot = emit_library_call_value ( libfunc , NULL_RTX , LCT_NORMAL , mode , <NUM_LIT> , op0 , GET_MODE ( op0 ) , op1 , GET_MODE ( op1 ) , XEXP ( rem , <NUM_LIT> ) , Pmode ) ; * quot_p = quot ; * rem_p = rem ;


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const {

return getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ;


if ( regno == LR_REGNUM ) return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : { Value * Ptr = II -> getArgOperand ( <NUM_LIT> ) ; AccessTy = II -> getType ( ) ; Ops . push_back ( Ptr ) ; return true ; }


<s> TargetLoweringObjectFileELF ( ) , AttributesSection ( NULL ) {


<s> if ( MO . isImm ( ) ) < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) && MO . getExpr ( ) -> getKind ( ) == MCExpr :: SymbolRef ) ; <STR_LIT> FixupKind = <STR_LIT> ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : FixupKind = <STR_LIT> ; break ;


<s> void <ISA_LIT>ATTAsmPrinter :: printGVStub ( const char * GV , const char * Prefix ) { printSuffixedName ( GV , <STR_LIT> , Prefix ) ; O << <STR_LIT> ; if ( Prefix ) O << Prefix ; O << GV << <STR_LIT> ;


<s> return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerGET_DYNAMIC_AREA_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerEH_DWARF_CFA ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> :


<s> if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; }


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ;


<s> MCSymbol * Sym = getSymbol ( GV ) ; std :: string OriginalName ; raw_string_ostream OriginalNameStream ( OriginalName ) ; Sym -> print ( OriginalNameStream ) ; OriginalNameStream . flush ( ) ; std :: string CleanName ; raw_string_ostream CleanNameStream ( CleanName ) ; for ( unsigned I = <NUM_LIT> , E = OriginalName . size ( ) ; I != E ; ++ I ) { char C = OriginalName [ I ] ; if ( C == '.' ) { CleanNameStream << <STR_LIT> ;


<s> void <ISA_LIT>CodeEmitter :: emitMachineBasicBlock ( MachineBasicBlock * BB , unsigned Reloc , intptr_t JTBase ) { MCE . addRelocation ( MachineRelocation :: getBB ( MCE . getCurrentPCOffset ( ) , Reloc , BB , JTBase ) ) ;


<s> Value * Hi = Builder . CreateTrunc ( Builder . CreateLShr ( Val , <NUM_LIT> ) , Int32Ty , <STR_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Addr = Builder . CreateBitCast ( Addr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ; return Builder . CreateCall ( Strex , { Lo , Hi , Addr } ) ; } <STR_LIT> Int = IsRelease ? <STR_LIT> : <STR_LIT> ; Type * Tys [ ] = { Addr -> getType ( ) } ;

Function * Strex = <STR_LIT> ( M , Int , Tys ) ;


<s> } if ( TREE_CODE ( b_arg_type ) == INTEGER_TYPE && TREE_CODE ( in_type ) == INTEGER_TYPE ) { match_type ++ ; continue ; } if ( POINTER_TYPE_P ( b_arg_type ) && POINTER_TYPE_P ( in_type ) && ! ( TYPE_QUALS ( TREE_TYPE ( in_type ) ) & ~ TYPE_QUALS ( TREE_TYPE ( b_arg_type ) ) ) && ( TYPE_QUALS ( TREE_TYPE ( b_arg_type ) ) & ~ TYPE_QUALS ( TREE_TYPE ( in_type ) ) ) ) { tree qual_in_type = build_qualified_type ( TREE_TYPE ( in_type ) , TYPE_QUALS ( TREE_TYPE ( b_arg_type ) ) ) ; if ( lang_hooks . types_compatible_p ( qual_in_type , TREE_TYPE ( b_arg_type ) ) ) { match_type ++ ; continue ;


<s> const MCExpr * ME = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; if ( ! MO . isJTI ( ) && ! MO . isMBB ( ) && MO . getOffset ( ) ) ME = MCBinaryExpr :: createAdd ( ME , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: createExpr ( ME ) ;


<s> if ( TARGET_SVE2 ) current_tune . extra_tuning_flags &= ~ AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS ;


<s> fnname = targetm . strip_name_encoding ( XSTR ( fn , <NUM_LIT> ) ) ; for ( l = mips16_stubs ; l != NULL ; l = l -> next ) if ( strcmp ( l -> name , fnname ) == <NUM_LIT> ) break ; if ( l == NULL ) { const char * separator ; char * secname , * stubname ; tree stubid , stubdecl ; unsigned int f ; secname = ACONCAT ( ( <STR_LIT> , fp_ret_p ? <STR_LIT> : <STR_LIT> , fnname , NULL ) ) ; stubname = ACONCAT ( ( <STR_LIT> , fp_ret_p ? <STR_LIT> : <STR_LIT> , fnname , NULL ) ) ; stubid = get_identifier ( stubname ) ; stubdecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , stubid , build_function_type_list ( void_type_node , NULL_TREE ) ) ; set_decl_section_name ( stubdecl , secname ) ; DECL_RESULT ( stubdecl ) = build_decl ( BUILTINS_LOCATION , RESULT_DECL , NULL_TREE , void_type_node ) ; fprintf ( asm_out_file , <STR_LIT> , ( fp_ret_p ? ( GET_MODE ( retval ) == SFmode ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) , fnname ) ; separator = <STR_LIT> ; for ( f = ( unsigned int ) fp_code ; f != <NUM_LIT> ; f >>= <NUM_LIT> ) { fprintf ( asm_out_file , <STR_LIT> , separator , ( f & <NUM_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; separator = <STR_LIT> ; } fprintf ( asm_out_file , <STR_LIT> ) ; assemble_start_function ( stubdecl , stubname ) ; mips_start_function_definition ( stubname , false ) ; if ( fp_ret_p ) { fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> ) ; fprintf ( asm_out_file , <STR_LIT> , reg_names [ GP_REG_FIRST + <NUM_LIT> ] , reg_names [ RETURN_ADDR_REGNUM ] ) ; } else { if ( TARGET_EXPLICIT_RELOCS ) { output_asm_insn ( <STR_LIT> , & fn ) ; output_asm_insn ( <STR_LIT> , & fn ) ; } else output_asm_insn ( <STR_LIT> , & fn ) ; } mips_output_args_xfer ( fp_code , 't' ) ; if ( fp_ret_p ) { output_asm_insn ( mips_output_jump ( & fn , <NUM_LIT> , - <NUM_LIT> , true ) , & fn ) ; fprintf ( asm_out_file , <STR_LIT> ) ; switch ( GET_MODE ( retval ) ) { case E_SCmode : mips_output_32bit_xfer ( 'f' , GP_RETURN + TARGET_BIG_ENDIAN , TARGET_BIG_ENDIAN ? FP_REG_FIRST + <NUM_LIT> : FP_REG_FIRST ) ; mips_output_32bit_xfer ( 'f' , GP_RETURN + TARGET_LITTLE_ENDIAN , TARGET_LITTLE_ENDIAN ? FP_REG_FIRST + <NUM_LIT> : FP_REG_FIRST ) ;

if ( GET_MODE ( retval ) == SCmode && TARGET_64BIT ) {


<s> vec_double2 v ; double d [ <NUM_LIT> ] ; } aa , bb , dd ; aa . v = ( vec_double2 ) ( a ) ; bb . v = ( vec_double2 ) ( b ) ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] - bb . d [ <NUM_LIT> ] ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] - bb . d [ <NUM_LIT> ] ;


<s> break ; case 'R' : switch ( GET_CODE ( x ) ) { case REG : fprintf ( file , reg_names [ REGNO ( x ) + <NUM_LIT> ] ) ; break ; case MEM : { machine_mode mode = GET_MODE ( x ) ; x = XEXP ( adjust_address ( x , SImode , <NUM_LIT> ) , <NUM_LIT> ) ; v850_print_operand_address ( file , mode , x ) ; if ( GET_CODE ( x ) == CONST_INT ) fprintf ( file , <STR_LIT> ) ; } break ; case CONST_INT : { unsigned HOST_WIDE_INT v = INTVAL ( x ) ; v = v >> <NUM_LIT> ; v = v >> <NUM_LIT> ; fprintf ( file , HOST_WIDE_INT_PRINT_HEX , v ) ; break ; } case CONST_DOUBLE : fprintf ( file , HOST_WIDE_INT_PRINT_HEX , CONST_DOUBLE_HIGH ( x ) ) ; break ; default : debug_rtx ( x ) ; gcc_unreachable ( ) ; } break ; case 'S' : { if ( GET_CODE ( x ) == MEM && ep_memory_operand ( x , GET_MODE ( x ) , FALSE ) ) fputs ( <STR_LIT> , file ) ; break ; } case 'T' : { if ( GET_CODE ( x ) == MEM && ep_memory_operand ( x , GET_MODE ( x ) , TRUE ) ) fputs ( <STR_LIT> , file ) ; break ; } case 'W' : switch ( GET_MODE ( x ) ) { default : gcc_unreachable ( ) ; case E_QImode : fputs ( <STR_LIT> , file ) ; break ; case E_HImode : fputs ( <STR_LIT> , file ) ; break ; case E_SImode : fputs ( <STR_LIT> , file ) ; break ; case E_SFmode : fputs ( <STR_LIT> , file ) ; break ; } break ; case '.' : fputs ( reg_names [ <NUM_LIT> ] , file ) ; break ; case 'z' : if ( REG_P ( x ) ) fputs ( reg_names [ REGNO ( x ) ] , file ) ;

else if ( ( GET_MODE ( x ) == SImode || GET_MODE ( x ) == DFmode || GET_MODE ( x ) == SFmode ) && x == CONST0_RTX ( GET_MODE ( x ) ) ) fputs ( reg_names [ <NUM_LIT> ] , file ) ;


<s> if ( ! SrcBlkInfo ) SrcBlkInfo = new BlockInformation ( ) ; SrcBlkInfo -> IsRetired = true ; assert ( MBB -> succ_empty ( ) && MBB -> pred_empty ( ) && <STR_LIT> ) ;


<s> if ( ! DisableFunctionSplitterRewrite ) rewriteCode ( ) ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( Imm & <NUM_LIT> ) ) ; return Success ;


<s> Inst . addOperand ( MCOperand :: createReg ( VSRpRegs [ RegNo >> <NUM_LIT> ] ) ) ;


<s> I != E ; ++ I ) { Size += ( * I ) -> getSize ( ) ; } return Size / <NUM_LIT> ;


<s> <ISA_LIT>AbstractMemberAccess ( <ISA_LIT>TargetMachine * TM = nullptr ) : ModulePass ( ID ) , TM ( TM ) {


<s> SDValue R600TargetLowering :: LowerSTORE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; StoreSDNode * StoreNode = cast < StoreSDNode > ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; SDValue Ptr = Op . getOperand ( <NUM_LIT> ) ; SDValue Result = AMDGPUTargetLowering :: LowerSTORE ( Op , DAG ) ; if ( Result . getNode ( ) ) { return Result ; } if ( StoreNode -> getAddressSpace ( ) == <STR_LIT> ) { if ( StoreNode -> isTruncatingStore ( ) ) { EVT VT = Value . getValueType ( ) ; assert ( VT . bitsLE ( <STR_LIT> ) ) ; EVT MemVT = StoreNode -> getMemoryVT ( ) ; SDValue MaskConstant ; if ( MemVT == <STR_LIT> ) { MaskConstant = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; } else { assert ( MemVT == <STR_LIT> ) ; MaskConstant = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; } SDValue DWordAddr = DAG . getNode ( <STR_LIT> , DL , VT , Ptr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ByteIndex = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> , VT ) ) ; SDValue TruncValue = DAG . getNode ( <STR_LIT> , DL , VT , Value , MaskConstant ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , DL , VT , ByteIndex , DAG . getConstant ( <NUM_LIT> , VT ) ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , VT , TruncValue , Shift ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskConstant , Shift ) ; SDValue Src [ <NUM_LIT> ] = { ShiftedValue , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Mask } ; SDValue Input = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , <NUM_LIT> ) ; SDValue Args [ <NUM_LIT> ] = { Chain , Input , DWordAddr } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Op -> getVTList ( ) , Args , <NUM_LIT> , MemVT , StoreNode -> getMemOperand ( ) ) ; } else if ( Ptr -> getOpcode ( ) != <STR_LIT> && Value . getValueType ( ) . bitsGE ( <STR_LIT> ) ) { Ptr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; if ( StoreNode -> isTruncatingStore ( ) || StoreNode -> isIndexed ( ) ) {


<s> static SDValue LowerI8Math ( SDValue Op , SelectionDAG & DAG , unsigned Opc , const TargetLowering & TLI ) { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT ShiftVT = TLI . getShiftAmountTy ( N0 . getValueType ( ) ) ; assert ( Op . getValueType ( ) == <STR_LIT> ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; N1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N1 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , N0 , N1 ) ) ; } case <STR_LIT> : case <STR_LIT> : { SDValue N1 = Op . getOperand ( <NUM_LIT> ) ; EVT N1VT = N1 . getValueType ( ) ; N0 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ; if ( ! N1VT . bitsEq ( ShiftVT ) ) { unsigned N1Opc = N1 . getValueType ( ) . bitsLT ( ShiftVT ) ? <STR_LIT> : <STR_LIT> ; N1 = DAG . getNode ( N1Opc , dl , ShiftVT , N1 ) ; } SDValue ExpandArg = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( Opc , dl , <STR_LIT> , ExpandArg , N1 ) ) ; } case <STR_LIT> :


<s> return ( int ) __builtin_ia32_vcvttsh2si32_round ( __A , _MM_FROUND_CUR_DIRECTION ) ;


<s> unsigned Size = <NUM_LIT> ; for ( const MachineInstr & MI : MBB ) Size += TII -> GetInstSizeInBytes ( MI ) ;

BlockInfo [ MBB . getNumber ( ) ] . Size = Size ;


<s> const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI , Paired ) ; Register DestReg = MRI -> createVirtualRegister ( SuperRC ) ; unsigned MergedOffset = std :: min ( CI . Offset , Paired . Offset ) ; auto MIB = BuildMI ( * MBB , Paired . I , DL , TII -> get ( Opcode ) , DestReg ) ; const unsigned Regs = getRegs ( Opcode , * TII ) ; if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; assert ( CI . I -> hasOneMemOperand ( ) && Paired . I -> hasOneMemOperand ( ) ) ; const MachineMemOperand * MMOa = * CI . I -> memoperands_begin ( ) ; const MachineMemOperand * MMOb = * Paired . I -> memoperands_begin ( ) ; MachineInstr * New = MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( MergedOffset ) . addImm ( CI . GLC ) . addImm ( CI . SLC ) . addImm ( <NUM_LIT> ) . addImm ( CI . DLC ) . addImm ( <NUM_LIT> ) . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI , Paired ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Dest1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ;

MachineInstr * Copy1 = BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ;


<s> return __builtin_neon_vpmaxfv4hf ( __a , __b ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCInstLowering ( * this ) , Mang ( new Mangler ( ) ) {


<s> const char * RegName = getRegisterName ( RegNo ) ; if ( MAI -> getAssemblerDialect ( ) == AD_HLASM ) {

assert ( isalpha ( RegName [ <NUM_LIT> ] ) && isdigit ( RegName [ <NUM_LIT> ] ) ) ;


<s> <ISA_LIT>_64TargetMachine :: <ISA_LIT>_64TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>TargetMachine ( T , TT , FS , true ) {


<s> bool <ISA_LIT>TargetLowering :: mayBeEmittedAsTailCall ( CallInst * CI ) const {

if ( ! Enable<ISA_LIT>TailCalls ) return false ;


<s> if ( Op . getSubReg ( ) ) { LaneBitmask LM = TRI -> getSubRegIndexLaneMask ( Op . getSubReg ( ) ) ; if ( TRI -> hasVGPRs ( RC ) ) { if ( TRI -> getNumCoveredRegs ( LM ) >= NUM_VGPR_BANKS ) continue ; } else { if ( TRI -> getNumCoveredRegs ( LM ) / <NUM_LIT> >= NUM_SGPR_BANKS ) continue ; } } unsigned ShiftedBank = Bank ; if ( Bank != - <NUM_LIT> && R == Reg && ( Op . getSubReg ( ) || SubReg ) ) { unsigned RegOffset = TRI -> getChannelFromSubReg ( SubReg ? SubReg : ( unsigned ) <STR_LIT> ) ; unsigned Offset = TRI -> getChannelFromSubReg ( Op . getSubReg ( ) ? Op . getSubReg ( ) : ( unsigned ) <STR_LIT> ) ; if ( Bank < NUM_VGPR_BANKS ) {

unsigned Shift = ( ( NUM_VGPR_BANKS + Offset ) - RegOffset ) ;


<s> void <ISA_LIT>InstrPostProcess :: postProcessInstruction ( std :: unique_ptr < Instruction > & Inst , const MCInst & MCI ) {


<s> bool isAdd = true ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ;

MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ;


<s> if ( isLegalCmpImmediate ( C - <NUM_LIT> , isThumb ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C > <NUM_LIT> && isLegalCmpImmediate ( C - <NUM_LIT> , isThumb ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( isLegalCmpImmediate ( C + <NUM_LIT> , isThumb ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C < <NUM_LIT> && isLegalCmpImmediate ( C + <NUM_LIT> , isThumb ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , <STR_LIT> ) ; } break ; } } } <STR_LIT> CondCode = IntCCTo<ISA_LIT>CC ( CC ) ; <STR_LIT> CompareType ; switch ( CondCode ) { default : CompareType = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CompareType = <STR_LIT> ; break ; }

<ISA_LIT>CC = DAG . getConstant ( CondCode , <STR_LIT> ) ;


<s> static LegalityPredicate isSmallOddVector ( unsigned TypeIdx ) { return [ = ] ( const LegalityQuery & Query ) { const LLT Ty = Query . Types [ TypeIdx ] ; return Ty . isVector ( ) && Ty . getNumElements ( ) % <NUM_LIT> != <NUM_LIT> && Ty . getElementType ( ) . getSizeInBits ( ) < <NUM_LIT> && Ty . getSizeInBits ( ) % <NUM_LIT> != <NUM_LIT> ;


<s> if ( out_words_to_go != in_words_to_go && ( ( in_words_to_go - <NUM_LIT> ) & <NUM_LIT> ) != <NUM_LIT> ) part_bytes_reg = gen_rtx_REG ( SImode , ( in_words_to_go - <NUM_LIT> ) & <NUM_LIT> ) ; for ( i = <NUM_LIT> ; in_words_to_go >= <NUM_LIT> ; i += <NUM_LIT> ) { if ( in_words_to_go > <NUM_LIT> ) emit_insn ( arm_gen_load_multiple ( <NUM_LIT> , <NUM_LIT> , src , TRUE , TRUE , srcbase , & srcoffset ) ) ; else emit_insn ( arm_gen_load_multiple ( <NUM_LIT> , in_words_to_go , src , TRUE , FALSE , srcbase , & srcoffset ) ) ; if ( out_words_to_go ) { if ( out_words_to_go > <NUM_LIT> ) emit_insn ( arm_gen_store_multiple ( <NUM_LIT> , <NUM_LIT> , dst , TRUE , TRUE , dstbase , & dstoffset ) ) ; else if ( out_words_to_go != <NUM_LIT> ) emit_insn ( arm_gen_store_multiple ( <NUM_LIT> , out_words_to_go , dst , TRUE , ( last_bytes == <NUM_LIT> ? FALSE : TRUE ) , dstbase , & dstoffset ) ) ; else { mem = adjust_automodify_address ( dstbase , SImode , dst , dstoffset ) ; emit_move_insn ( mem , gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; if ( last_bytes != <NUM_LIT> ) { emit_insn ( gen_addsi3 ( dst , dst , GEN_INT ( <NUM_LIT> ) ) ) ; dstoffset += <NUM_LIT> ; } } } in_words_to_go -= in_words_to_go < <NUM_LIT> ? in_words_to_go : <NUM_LIT> ; out_words_to_go -= out_words_to_go < <NUM_LIT> ? out_words_to_go : <NUM_LIT> ; } if ( out_words_to_go ) { rtx sreg ; mem = adjust_automodify_address ( srcbase , SImode , src , srcoffset ) ; sreg = copy_to_reg ( mem ) ; mem = adjust_automodify_address ( dstbase , SImode , dst , dstoffset ) ; emit_move_insn ( mem , sreg ) ; in_words_to_go -- ; gcc_assert ( ! in_words_to_go ) ; } if ( in_words_to_go ) { gcc_assert ( in_words_to_go > <NUM_LIT> ) ; mem = adjust_automodify_address ( srcbase , SImode , src , srcoffset ) ; part_bytes_reg = copy_to_mode_reg ( SImode , mem ) ; } gcc_assert ( ! last_bytes || part_bytes_reg ) ; if ( BYTES_BIG_ENDIAN && last_bytes ) { rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp , part_bytes_reg , GEN_INT ( <NUM_LIT> * ( <NUM_LIT> - last_bytes ) ) ) ) ; part_bytes_reg = tmp ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateNumericReg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { DEBUG ( dbgs ( ) << <STR_LIT> << Index << <STR_LIT> ) ;

return CreateReg ( Index , RegKind_Numeric , RegInfo , S , E , Parser ) ;


<s> for ( MCRegUnitIterator RUI ( Reg , & TRI ) ; RUI . isValid ( ) ; ++ RUI ) BV . set ( * RUI ) ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( bool Is64Bit , uint8_t OSABI ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , Is64Bit ? ELF :: EM_<ISA_LIT>64 : ELF :: EM_<ISA_LIT> , true ) {


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * ThisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * Copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , Copy0MBB ) ; F -> insert ( I , Copy1MBB ) ; Copy1MBB -> splice ( Copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( Copy0MBB ) ; BB -> addSuccessor ( Copy1MBB ) ; unsigned LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int CC = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int NewCC ; switch ( CC ) { case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectOp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> :


<s> const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( VT . getVectorElementType ( ) ) ) return SDValue ( ) ; if ( Subtarget -> hasAVX ( ) && VT . getSizeInBits ( ) == <NUM_LIT> && N -> getOpcode ( ) == <STR_LIT> ) return PerformShuffleCombine256 ( N , DAG , DCI , Subtarget -> hasAVX2 ( ) ) ;

if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ;


<s> EVT SrcVecVT = ExtElt . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned VecWidth = SrcVecVT . getSizeInBits ( ) ; unsigned NumElts = VecWidth / DestWidth ; EVT BitcastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , TruncVT , NumElts ) ; SDValue BitcastVec = DAG . getBitcast ( BitcastVT , ExtElt . getOperand ( <NUM_LIT> ) ) ; SDLoc DL ( N ) ; SDValue NewExtElt = DAG . getNode ( <STR_LIT> , DL , TruncVT , BitcastVec , ExtElt . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( N -> getOpcode ( ) , DL , N -> getValueType ( <NUM_LIT> ) , NewExtElt ) ;


<s> if ( isSelectPseudo ( MI ) ) while ( NextMIIt != MBB -> end ( ) && isSelectPseudo ( * NextMIIt ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CCValid && ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CCMask || NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) ) { LastMI = & * NextMIIt ; ++ NextMIIt ; } MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; if ( ! LastMI -> killsRegister ( <STR_LIT> ) && ! checkCCKill ( * LastMI , JoinMBB ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; MBB -> addSuccessor ( JoinMBB ) ; MBB = JoinMBB ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastMI ) ) ; createPHIsForSelects ( MIItBegin , MIItEnd , StartMBB , FalseMBB , MBB ) ;

StartMBB -> erase ( MIItBegin , MIItEnd ) ;


<s> static SDValue combineVectorInsert ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { assert ( ( ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) || ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op ( N , <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > NonceMask ;


<s>
auto
BB
=
Begin
->
getParent
(
)
;
OS
<<
BB
->
getParent
(
)
->
getName
(
)
<<
<STR_LIT>
<<
printMBBReference
(
*
BB
)
<<
' '
<<
BB
->
getName
(
)
<<
<STR_LIT>
;
auto
I
=
Begin
;
MaxInstNum
=
std
::
max
(
MaxInstNum
,
<NUM_LIT>
)
;
for
(
;
I
!=
End
&&
MaxInstNum
;
++
I
,
MaxInstNum
)
{
if
(
!
I
->
isDebugInstr
(
)
&&
LIS
)
OS
<<
LIS
->
getInstructionIndex
(
*
I
)
;
OS
<<
'\t'
<<
*
I
;


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ;


<s> MCAsmParserExtension :: Initialize ( _Parser ) ; if ( Parser . getStreamer ( ) . getTargetStreamer ( ) == nullptr ) new <ISA_LIT>TargetStreamer ( Parser . getStreamer ( ) ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( value & <NUM_LIT> ) { fprintf ( stream , <STR_LIT> , ( int ) ( value & <NUM_LIT> ) ) ; return ;


<s> int Val = <STR_LIT> ( APInt ( <NUM_LIT> , CE -> getValue ( ) ) ) ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ;


<s> if ( ! GV -> hasInitializer ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return ; } static const char * Ignored [ ] = { <STR_LIT> , <STR_LIT> } ; for ( const char * I : Ignored ) if ( Name == I ) return ; static const char * Unhandled [ ] = { <STR_LIT> , <STR_LIT> } ; for ( const char * U : Unhandled ) if ( Name == U ) report_fatal_error ( <STR_LIT> ) ; if ( Name . startswith ( <STR_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; if ( GV -> isThreadLocal ( ) ) report_fatal_error ( <STR_LIT> ) ; const DataLayout & DL = getDataLayout ( ) ;

const Constant * Init = GV -> getInitializer ( ) ;


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override {


<s> L = getLoc ( ) ; if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ; if ( check ( ( ( Reg - <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) , L , <STR_LIT> ) ) return true ; getTargetStreamer ( ) . emitARM64WinCFISaveLRPair ( Reg , Offset ) ; return false ;


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( B && C ) { uint32_t BVal = B -> getZExtValue ( ) ; uint32_t CVal = C -> getZExtValue ( ) ; if ( <NUM_LIT> < BVal && BVal <= CVal && CVal < <NUM_LIT> ) { bool Signed = N -> getOpcode ( ) == <STR_LIT> ;

unsigned Opcode = Signed ? <STR_LIT> : <STR_LIT> ;


<s> static unsigned getLastSymbolicHwreg ( const MCSubtargetInfo & STI ) { if ( is<ISA_LIT> ( STI ) || isCI ( STI ) || isVI ( STI ) ) return ID_SYMBOLIC_FIRST_GFX9_ ; else if ( isGFX9 ( STI ) ) return ID_SYMBOLIC_FIRST_GFX10_ ;

else if ( isGFX10 ( STI ) && ! isGFX10_BEncoding ( STI ) ) return ID_SYMBOLIC_FIRST_GFX1030_ ;


<s> } if ( Sym && Sym -> isELF ( ) ) { unsigned Type = cast < MCSymbolELF > ( Sym ) -> getType ( ) ; if ( ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC ) ) { if ( Asm . isThumbFunc ( Sym ) && ( FixupKind == <STR_LIT> ) ) return true ; if ( ! Asm . isThumbFunc ( Sym ) && ( FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> ) ) return true ; } } if ( A && ( FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> ) ) return true ; return false ;


<s> MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ; ++ PI2 ; if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ;

MachineBasicBlock :: const_iterator I = Pred -> end ( ) ;


<s> unsigned long count = <NUM_LIT> ; while ( value ) {


<s> ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ;


<s> if ( ElemTy == <STR_LIT> ) { for ( MVT T : Tys ) { assert ( T != <STR_LIT> ) ; auto A = getPreferredHvxVectorAction ( <STR_LIT> ( T , VecLen ) ) ; if ( A != ~ <NUM_LIT> ) return A ; } return ~ <NUM_LIT> ; }

if ( llvm :: is_contained ( Tys , ElemTy ) ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerUMUL_LOHI ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getValueType ( ) == <STR_LIT> && Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , LHS , RHS , Zero , Zero ) ; SDValue Lo ( Hi . getNode ( ) , <NUM_LIT> ) ; SDValue Ops [ ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl ) ;


<s> if ( TREE_CODE ( value ) != STRING_CST ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; }

else if ( strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) && strcmp ( TREE_STRING_POINTER ( value ) , <STR_LIT> ) && ! TARGET_V2 ) {


<s> fixed_regs [ i ] = <NUM_LIT> ; call_used_regs [ i ] = <NUM_LIT> ; } if ( TARGET_M6812 && flag_omit_frame_pointer && optimize ) { fixed_regs [ HARD_Z_REGNUM ] = <NUM_LIT> ; }


<s> unsigned Reg1 = Ctx . getRegisterInfo ( ) -> getEncodingValue ( RegOp1 ) ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { assert ( Reg0 != Reg1 && <STR_LIT> ) ; if ( Reg0 < Reg1 ) return ; } else if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { if ( Reg0 >= Reg1 ) return ; } else if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { if ( Reg1 >= Reg0 ) return ; } else llvm_unreachable ( <STR_LIT> ) ;

Inst . getOperand ( <NUM_LIT> ) . setReg ( RegOp1 ) ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> unsigned Reg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCOperand & Op1 = Inst . getOperand ( <NUM_LIT> ) ; if ( Op1 . isExpr ( ) ) { emitToStreamer ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( Reg ) . addReg ( <STR_LIT> ) . addExpr ( Op1 . getExpr ( ) ) ) ; return false ; } int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isRV64 ( ) ) Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; emitLoadImm ( Reg , Imm , Out ) ; return false ; } case <STR_LIT> : emitLoadLocalAddress ( Inst , IDLoc , Out ) ; return false ; case <STR_LIT> :

emitLoadAddress ( Inst , IDLoc , Out ) ;


<s> static bool riscv_size_ok_for_small_data_p ( int size ) { return g_switch_value && IN_RANGE ( size , <NUM_LIT> , g_switch_value ) ;


<s> } if ( MO . isReg ( ) ) { O << '(' ; printOperand ( MI , OpNo ) ; O << ')' ; return false ; } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO ) ; else printOperand ( MI , OpNo ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo ) ; return false ; } return true ; case 'b' :


<s> bool hasFPUv3HalfFloat ( ) const { return HasFPUv3HalfFloat ;


<s> void <ISA_LIT>AsmParser :: emitCapLoadLocalCap ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out ) { MCOperand DestReg = Inst . getOperand ( <NUM_LIT> ) ; const MCExpr * Symbol = Inst . getOperand ( <NUM_LIT> ) . getExpr ( ) ; emitAuipccInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI , <STR_LIT> , IDLoc , Out ) ;


<s> void DecodeSHUFPSMask ( unsigned NElts , unsigned Imm , SmallVectorImpl < unsigned > & ShuffleMask ) { for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) { ShuffleMask . push_back ( Imm % NElts ) ; Imm /= NElts ; } for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) {

ShuffleMask . push_back ( Imm % NElts + NElts ) ;


<s> MI . getOperand ( Op ) . setImm ( BS . back ( ) ) ; if ( ! CurrentPacketMIs . empty ( ) ) setIsLastBit ( CurrentPacketMIs . back ( ) , <NUM_LIT> ) ; substitutePV ( MI , PV ) ; MachineBasicBlock :: iterator It = VLIWPacketizerList :: addToPacket ( MI ) ; if ( isTransSlot ) { endPacket ( std :: next ( It ) -> getParent ( ) , std :: next ( It ) ) ; } return It ; } endPacket ( MI . getParent ( ) , MI ) ;

if ( TII -> isTransOnly ( MI ) ) return MI ;


<s> return __gnu_unwind_pr_common ( state , ucbp , context , <NUM_LIT> ) ;


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp ; switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = LowerSymbolOperand ( MO , GetJumpTableSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = LowerSymbolOperand ( MO , GetConstantPoolIndexSymbol ( MO ) ) ; break ; case MachineOperand :: MO_BlockAddress :

MCOp = LowerSymbolOperand ( MO , GetBlockAddressSymbol ( MO ) ) ;


<s> return __builtin_mve_vldrhq_z_uv8hi ( ( __builtin_neon_hi * ) __base , __p ) ;


<s> if ( Opcode != <STR_LIT> ) return ; SDValue Chain = Results [ <NUM_LIT> ] ; SDValue ecx = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Glue ) ;


<s> bool isScalarVecReg ( unsigned Reg ) { return ( isRegInClass ( Reg , & <STR_LIT> ) || isRegInClass ( Reg , & <STR_LIT> ) ) ;


<s> return new <ISA_LIT>TextureIntrinsicsReplacer ( ) ;


<s> static int getOrCreateFixedStackObject ( MachineFrameInfo & MFI , unsigned Size , int64_t Offset ) { for ( int I = MFI . getObjectIndexBegin ( ) ; I < <NUM_LIT> ; ++ I ) { if ( MFI . getObjectOffset ( I ) == Offset ) { assert ( MFI . getObjectSize ( I ) == Size ) ; return I ; } } return MFI . CreateFixedObject ( Size , Offset , true ) ;


<s> unsigned int incoming_stack_boundary ; if ( ix86_user_incoming_stack_boundary ) incoming_stack_boundary = ix86_user_incoming_stack_boundary ; else if ( ! sibcall && ! TARGET_64BIT && ix86_force_align_arg_pointer && crtl -> stack_alignment_estimated == <NUM_LIT> ) incoming_stack_boundary = MIN_STACK_BOUNDARY ;


<s> unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned addr = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned W = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned U = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned P = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; bool writeback = ( W == <NUM_LIT> ) | ( P == <NUM_LIT> ) ; addr |= ( U << <NUM_LIT> ) | ( Rn << <NUM_LIT> ) ; if ( writeback && ( Rn == Rt || Rn == Rt2 ) ) Check ( S , MCDisassembler :: SoftFail ) ;

if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> bool isMRSSystemRegister ( ) const { if ( ! isSysReg ( ) ) return false ; bool IsKnownRegister ; <STR_LIT> ( ) . fromString ( getSysReg ( ) , IsKnownRegister ) ;


<s> OwningPtr < const TargetMachine > targetMachine ( T . createTargetMachine ( tripleString , featureString ) ) ; InitRegisterMap ( targetMachine -> getRegisterInfo ( ) ) ;


<s> const bool Is64Bit = getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_AMD64 ; unsigned FixupKind = Fixup . getKind ( ) ; if ( IsCrossSection ) { if ( FixupKind == FK_Data_4 || FixupKind == llvm :: <STR_LIT> || ( FixupKind == FK_Data_8 && Is64Bit ) ) { FixupKind = FK_PCRel_4 ; } else { Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; } } MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; if ( Is64Bit ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_AMD64_REL32 ; case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_AMD64_ADDR32NB ; if ( Modifier == MCSymbolRefExpr :: VK_SECREL ) return COFF :: IMAGE_REL_AMD64_SECREL ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; case FK_Data_8 : return COFF :: IMAGE_REL_AMD64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_AMD64_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_AMD64_SECREL ; default : Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; } } else if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_I386 ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_I386_REL32 ; case FK_Data_4 :


<s> SDLoc dl ( N ) ; MVT DstVT = InVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue P = DAG . getNode ( <STR_LIT> , dl , DstVT , Op0 ) ; return DAG . getNode ( <STR_LIT> , dl , N -> getValueType ( <NUM_LIT> ) , P ) ; } if ( Op0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * Ld = cast < LoadSDNode > ( Op0 . getNode ( ) ) ; EVT VT = Ld -> getValueType ( <NUM_LIT> ) ; if ( ! Ld -> isVolatile ( ) && ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ( Op0 . getNode ( ) ) && Op0 . hasOneUse ( ) && ! XTLI -> getSubtarget ( ) -> is64Bit ( ) && VT == <STR_LIT> ) { SDValue FILDChain = XTLI -> BuildFILD ( SDValue ( N , <NUM_LIT> ) , Ld -> getValueType ( <NUM_LIT> ) , Ld -> getChain ( ) , Op0 , DAG ) ; DAG . ReplaceAllUsesOfValueWith ( Op0 . getValue ( <NUM_LIT> ) , FILDChain . getValue ( <NUM_LIT> ) ) ; return FILDChain ; }


<s> void <ISA_LIT>InstructionSelector :: renderFImm32 ( MachineInstrBuilder & MIB , const MachineInstr & I , int OpIdx ) const { assert ( I . getOpcode ( ) == TargetOpcode :: G_FCONSTANT && OpIdx == - <NUM_LIT> && <STR_LIT> ) ; const ConstantFP * FPImm = I . getOperand ( <NUM_LIT> ) . getFPImm ( ) ; addNumImm ( FPImm -> getValueAPF ( ) . bitcastToAPInt ( ) , MIB ) ;


<s> else if ( ! TARGET_MEMPARM && ! type ) { if ( mode == QFmode || mode == HFmode ) reg = c4x_fp_reglist [ cum -> floats ] ; else if ( mode == QImode || mode == Pmode ) reg = c4x_int_reglist [ <NUM_LIT> ] [ cum -> ints ] ; } if ( TARGET_DEBUG ) { fprintf ( stderr , <STR_LIT> , GET_MODE_NAME ( mode ) , named ) ; if ( reg ) fprintf ( stderr , <STR_LIT> , reg_names [ reg ] ) ; else fprintf ( stderr , <STR_LIT> ) ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { llvm_unreachable ( <STR_LIT> ) ;


<s> static inline void aarch64_add_sp ( int scratchreg , HOST_WIDE_INT delta , bool emit_move_imm ) {

aarch64_add_constant_internal ( Pmode , SP_REGNUM , scratchreg , delta , true , emit_move_imm ) ;


<s> if ( ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return false ; x = XEXP ( x , <NUM_LIT> ) ; } if ( GET_CODE ( x ) == UNSPEC ) { switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLT : case UNSPEC_TLSGD : case UNSPEC_TLSLD : case UNSPEC_TLSIE : case UNSPEC_TLSLE : case UNSPEC_ICT : return false ; default : return true ; } } break ; case SYMBOL_REF : if ( SYMBOL_REF_TLS_MODEL ( x ) ) return false ; break ;


<s> SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; }

if ( isSingleInputShuffleMask ( Mask ) ) {


<s> return isa < Function > ( GV ) ? false : TargetLowering :: isOffsetFoldingLegal ( GA ) ;


<s> assert ( <STR_LIT> ( ShiftOpnd ) == <STR_LIT> && <STR_LIT> ) ; unsigned ShiftVal = <STR_LIT> ( ShiftOpnd ) ; assert ( ( ShiftVal == <NUM_LIT> || ShiftVal == <NUM_LIT> ) && <STR_LIT> ) ;

auto Immediate = MI . getOperand ( OpIdx ) . getImm ( ) ;


<s> Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return nullptr ; auto Builder = IRBuilder < > ( AI ) ; Module * M = Builder . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ; auto SynchScope = AI -> getSynchScope ( ) ; auto Order = AtomicCmpXchgInst :: getStrongestFailureOrdering ( AI -> getOrdering ( ) ) ; auto Ptr = AI -> getPointerOperand ( ) ; if ( SynchScope == SingleThread ) return nullptr ; if ( ! hasMFENCE ( Subtarget ) ) return nullptr ; Function * MFence = llvm :: <STR_LIT> ( M , <STR_LIT> ) ; Builder . CreateCall ( MFence , { } ) ; LoadInst * Loaded = Builder . CreateAlignedLoad ( Ptr , AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ) ;

Loaded -> setAtomic ( Order , SynchScope ) ;


<s> if ( frame_pointer_needed ) return false ; if ( df_regs_ever_live_p ( <NUM_LIT> ) ) return false ; if ( crtl -> profile ) return false ; return pa_compute_frame_size ( get_frame_size ( ) , <NUM_LIT> ) == <NUM_LIT> ;


<s> if ( ExpandPseudo ( MF ) . expand ( ) ) { const TargetRegisterClass & RC = STI . isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ; } uint64_t MaxSPOffset = estimateStackSize ( MF ) ; if ( isIntN ( STI . hasMSA ( ) ? <NUM_LIT> : <NUM_LIT> , MaxSPOffset ) && ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ) return ; const TargetRegisterClass & RC = ABI . ArePtrs64bit ( ) ? <STR_LIT> : <STR_LIT> ; int FI = MF . getFrameInfo ( ) . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlignment ( RC ) , false ) ; RS -> addScavengingFrameIndex ( FI ) ;


<s> void clearModuleFeatureBits ( uint64_t Feature , StringRef FeatureString ) { clearFeatureBits ( Feature , FeatureString ) ;

AssemblerOptions . front ( ) -> setFeatures ( STI . getFeatureBits ( ) ) ;


<s> SDValue GprIndex = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , InChain , VAListPtr , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; InChain = GprIndex . getValue ( <NUM_LIT> ) ; if ( VT == <STR_LIT> ) { SDValue GprAnd = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GprIndex , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CC64 = DAG . getSetCC ( dl , <STR_LIT> , GprAnd , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue GprIndexPlusOne = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GprIndex , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; GprIndex = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CC64 , GprIndexPlusOne , GprIndex ) ; } SDValue FprPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue FprIndex = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , InChain , FprPtr , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; InChain = FprIndex . getValue ( <NUM_LIT> ) ; SDValue RegSaveAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue OverflowAreaPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , VAListPtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;

SDValue OverflowArea = DAG . getLoad ( <STR_LIT> , dl , InChain , OverflowAreaPtr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> return gen_storewb_pairdf_di ( base , base , reg , reg2 , GEN_INT ( - adjustment ) , GEN_INT ( UNITS_PER_WORD - adjustment ) ) ;


<s> MCGSite * MCallGraph :: makeMCGSite ( MCGNode * Caller , MachineInstr * MI , MCGNode * Callee ) { bool is_site_in_SCC = isInSCC ( MI ) ; MCGSite * newSite = new MCGSite ( Caller , MI , Callee , is_site_in_SCC ) ; Sites . push_back ( newSite ) ;

Caller -> Sites . push_back ( newSite ) ;


<s> MOP . setReg ( GetMatchingSubReg ( MOP . getReg ( ) ) ) ; SeenDef = true ; } } } else { for ( auto & MOP : MI . operands ( ) ) { if ( MOP . isReg ( ) && ! MOP . isDebug ( ) && MOP . getReg ( ) && TRI -> regsOverlap ( MOP . getReg ( ) , RegToRename ) ) { assert ( ( MOP . isImplicit ( ) || ( MOP . isRenamable ( ) && ! MOP . isEarlyClobber ( ) ) ) && <STR_LIT> ) ; MOP . setReg ( GetMatchingSubReg ( MOP . getReg ( ) ) ) ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; return true ; } ; forAllMIsUntilDef ( * I , RegToRename , TRI , LdStLimit , UpdateMIs ) ; for ( auto & MI : iterator_range < MachineInstrBundleIterator < llvm :: MachineInstr >> ( std :: next ( I ) , std :: next ( Paired ) ) ) assert ( all_of ( MI . operands ( ) , [ this , & RenameReg ] ( const MachineOperand & MOP ) { return ! MOP . isReg ( ) || MOP . isDebug ( ) || ! MOP . getReg ( ) || ! TRI -> regsOverlap ( MOP . getReg ( ) , * RenameReg ) ; } ) && <STR_LIT> <STR_LIT> ) ; } MachineBasicBlock :: iterator InsertionPoint = MergeForward ? Paired : I ; const MachineOperand & BaseRegOp = MergeForward ? getLdStBaseOp ( * Paired ) : getLdStBaseOp ( * I ) ; int Offset = getLdStOffsetOp ( * I ) . getImm ( ) ; int PairedOffset = getLdStOffsetOp ( * Paired ) . getImm ( ) ; bool PairedIsUnscaled = TII -> hasUnscaledLdStOffset ( Paired -> getOpcode ( ) ) ; if ( IsUnscaled != PairedIsUnscaled ) { int MemSize = TII -> getMemScale ( * Paired ) ; if ( PairedIsUnscaled ) { assert ( ! ( PairedOffset % TII -> getMemScale ( * Paired ) ) && <STR_LIT> ) ; PairedOffset /= MemSize ; } else { PairedOffset *= MemSize ; } } MachineInstr * RtMI , * Rt2MI ; if ( Offset == PairedOffset + OffsetStride && ! <ISA_LIT>InstrInfo :: isPreLdSt ( * I ) ) { RtMI = & * Paired ; Rt2MI = & * I ; if ( SExtIdx != - <NUM_LIT> ) SExtIdx = ( SExtIdx + <NUM_LIT> ) % <NUM_LIT> ; } else {


<s> explicit <ISA_LIT>ImagePseudoSourceValue ( const TargetInstrInfo & TII ) : <ISA_LIT>PseudoSourceValue ( PSVImage , TII ) {


<s> if ( F . hasFnAttribute ( <STR_LIT> ) ) { if ( ! F . hasOneUse ( ) || ! F . user_begin ( ) -> hasOneUse ( ) || ! isa < ConstantExpr > ( * F . user_begin ( ) ) || ! isa < ConstantExpr > ( * F . user_begin ( ) -> user_begin ( ) ) ) { continue ; } auto * BitCast = cast < ConstantExpr > ( * F . user_begin ( ) ) ; auto * AddrCast = cast < ConstantExpr > ( * BitCast -> user_begin ( ) ) ; auto RuntimeHandle = ( F . getName ( ) + <STR_LIT> ) . str ( ) ; auto * GV = new GlobalVariable ( M , Type :: getInt8Ty ( C ) -> getPointerTo ( <ISA_LIT>AS :: GLOBAL_ADDRESS ) , true , GlobalValue :: ExternalLinkage , nullptr , RuntimeHandle , nullptr , GlobalValue :: NotThreadLocal , <ISA_LIT>AS :: GLOBAL_ADDRESS , true ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << * GV << '\n' ) ;


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; }


<s> return ( __m128i ) __builtin_ia32_prolvq128_mask ( ( __v2di ) __A , ( __v2di ) __B , ( __v2di ) _mm_setzero_di ( ) , ( __mmask8 ) __U ) ;


<s> return __builtin_mve_vmovltq_sv16qi ( __a ) ;


<s> int lane = INTVAL ( operands [ <NUM_LIT> ] ) ; machine_mode constmode = SImode ; machine_mode mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; int regno = REGNO ( operands [ <NUM_LIT> ] ) ; regno = ( ( regno - FIRST_VFP_REGNUM ) >> <NUM_LIT> ) ; if ( lane > <NUM_LIT> && lane >= GET_MODE_NUNITS ( mode ) / <NUM_LIT> ) { operands [ <NUM_LIT> ] = gen_int_mode ( regno + <NUM_LIT> , constmode ) ; operands [ <NUM_LIT> ] = gen_int_mode ( lane - GET_MODE_NUNITS ( mode ) / <NUM_LIT> , constmode ) ; } else { operands [ <NUM_LIT> ] = gen_int_mode ( regno , constmode ) ; operands [ <NUM_LIT> ] = gen_int_mode ( lane , constmode ) ;


<s> return TargetTransformInfo :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ;


<s> } if ( SLC ) { * SLC = ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Value &= ~ ( uint64_t ) <NUM_LIT> ; } if ( DLC ) { * DLC = ( Value & <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Value &= ~ ( uint64_t ) <NUM_LIT> ; } return Value == <NUM_LIT> ;


<s> if ( ! GEP ) return ConstantInt :: getNullValue ( Type :: getInt32Ty ( Ptr -> getContext ( ) ) ) ; auto I = GEPIdx . find ( GEP ) ;

assert ( I != GEPIdx . end ( ) && <STR_LIT> ) ;


<s> return ( __m128i ) __builtin_ia32_pmovsqw256_mask ( ( __v4di ) __A , ( __v8hi ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getByValTypeAlignment ( Type * Ty ) const {


<s> return ( __m128i ) __builtin_ia32_vpopcountb_v16qi ( ( __v16qi ) __A ) ;


<s> DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; TTI = & getAnalysis < TargetTransformInfoWrapperPass > ( ) . getTTI ( F ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; TLI = TLIP ? & TLIP -> getTLI ( * L -> getHeader ( ) -> getParent ( ) ) : nullptr ; DL = & L -> getHeader ( ) -> getModule ( ) -> getDataLayout ( ) ; this -> L = L ; ActiveLaneMask = nullptr ; if ( ! ST -> hasMVEIntegerOps ( ) || ! ST -> hasV8_1MMainlineOps ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } BasicBlock * Preheader = L -> getLoopPreheader ( ) ; if ( ! Preheader ) return false ; auto FindLoopIterations = [ ] ( BasicBlock * BB ) -> IntrinsicInst * { for ( auto & I : * BB ) { auto * Call = dyn_cast < IntrinsicInst > ( & I ) ; if ( ! Call ) continue ; <STR_LIT> ID = Call -> getIntrinsicID ( ) ; if ( ID == <STR_LIT> || ID == <STR_LIT> ) return cast < IntrinsicInst > ( & I ) ; } return nullptr ; } ; IntrinsicInst * Setup = FindLoopIterations ( Preheader ) ; if ( ! Setup ) { if ( ! Preheader -> getSinglePredecessor ( ) ) return false ;

Setup = FindLoopIterations ( Preheader -> getSinglePredecessor ( ) ) ;


<s> } else if ( Ty -> isIntegerTy ( ) ) { const auto * CI = cast < ConstantInt > ( C ) ; AI = CI -> getValue ( ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } return APIntToHexString ( AI ) ;


<s> size_t Last = <ISA_LIT>MCInstrInfo :: bundleSize ( HMB ) - <NUM_LIT> ; for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( HMB ) ) { MCInst & HMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; verifyInstructionPredicates ( HMI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; EncodeSingleInstruction ( HMI , OS , Fixups , STI , parseBits ( Last , HMB , HMI ) ) ; * Extended = <ISA_LIT>MCInstrInfo :: isImmext ( HMI ) ; * Addend += HEXAGON_INSTR_SIZE ; ++ * CurrentIndex ;


const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ;


<s> const MCInstrDesc & IDesc = I . getDesc ( ) ; const MCOperandInfo & IInfo = IDesc . OpInfo [ <ISA_LIT>II :: getImmFieldOpNum ( IDesc ) ] ; bool isSigned = <ISA_LIT>MCInstrInfo :: isInstTypeSigned ( IDesc , I ) ; return <ISA_LIT>MCInstrInfo :: useImmSlotForImm ( IInfo , Val , isSigned ) ;


<s> static const MachineOperand & getLdStBaseOp ( const MachineInstr & MI ) {

unsigned Idx = isPairedLdSt ( MI ) || <ISA_LIT>InstrInfo :: isPreLdSt ( MI ) ? <NUM_LIT> : <NUM_LIT> ;


<s> std :: string <STR_LIT> ( ) const { return std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ) ;


<s> static SDValue lowerToAddSubOrFMAddSub ( const BuildVectorSDNode * BV , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDValue Opnd0 , Opnd1 ;

if ( ! isAddSub ( BV , Subtarget , DAG , Opnd0 , Opnd1 ) ) return SDValue ( ) ;


<s> for ( const Use & U : I . operands ( ) ) { const auto * OpC = dyn_cast < Constant > ( U ) ; if ( ! OpC ) continue ; if ( visitConstantExprsRecursively ( OpC , ConstantExprVisited ) ) return true ;


<s> Parent = Succ ; } else { return std :: make_pair ( Position , true ) ; } } while ( Parent -> empty ( ) ) ; } Iter Instr = getNextMachineInstrInBB ( Position ) ; if ( Instr == Parent -> end ( ) ) { return getNextMachineInstr ( Instr , Parent ) ; } return std :: make_pair ( Instr , false ) ;


<s> SDNode * <ISA_LIT>TargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const {

const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ;


<s> } if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) continue ; if ( ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) continue ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t ImmVal = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * DefInst = MRI -> getUniqueVRegDef ( SrcReg ) ; if ( ! DefInst ) continue ; bool IsCandidate = false ; if ( DefInst -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & MO = DefInst -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar ) { if ( GVar -> hasAttribute ( <STR_LIT> ) ) { assert ( ImmVal == <NUM_LIT> ) ; IsCandidate = true ; } else if ( ! GVar -> hasInitializer ( ) && GVar -> hasExternalLinkage ( ) && GVar -> getSection ( ) == <STR_LIT> ) { if ( ImmVal == <NUM_LIT> ) IsCandidate = true ; else errs ( ) << <STR_LIT> << GVar -> getName ( ) << <STR_LIT> << ImmVal << <STR_LIT> ; } } } } if ( ! IsCandidate ) continue ; auto Begin = MRI -> use_begin ( DstReg ) , End = MRI -> use_end ( ) ;


<s> bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } else { bool LaneUsed [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneUsed [ ( Mask [ i ] / LaneSize ) ] = true ; if ( ! LaneUsed [ <NUM_LIT> ] || ! LaneUsed [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; } assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > FlippedBlendMask ( Size ) ;

for ( int i = <NUM_LIT> ; i < Size ; ++ i ) FlippedBlendMask [ i ] = Mask [ i ] < <NUM_LIT> ? - <NUM_LIT> : ( ( ( Mask [ i ] % Size ) / LaneSize == i / LaneSize ) ? Mask [ i ] : Mask [ i ] % LaneSize + ( i / LaneSize ) * LaneSize + Size ) ;


<s> unsigned SubVecSize = DL . getTypeSizeInBits ( SubVecTy ) ; if ( NumElts % Factor == <NUM_LIT> && ( SubVecSize == <NUM_LIT> || SubVecSize % <NUM_LIT> == <NUM_LIT> ) && ! VecTy -> getScalarType ( ) -> isHalfTy ( ) ) return Factor * ( ( SubVecSize + <NUM_LIT> ) / <NUM_LIT> ) ; } return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ;


<s> const auto SavedBytes = Bytes ; if ( decodeInstruction ( Table , TmpInst , Inst , Address , this , STI ) ) { MI = TmpInst ; return MCDisassembler :: Success ; } Bytes = SavedBytes ;


<s> <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & st ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , ST ( st ) {


<s> static <ISA_LIT>Operand * CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E , MCContext & Ctx ) {

<ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Immediate , Ctx ) ;


<s> static bool canTreatAsByteVector ( EVT VT ) {

return VT . isVector ( ) && VT . getVectorElementType ( ) . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumOps ; i += <NUM_LIT> ) { MIB . addUse ( I . getOperand ( i + <NUM_LIT> ) . getReg ( ) ) ; MIB . addMBB ( I . getOperand ( i + <NUM_LIT> ) . getMBB ( ) ) ; } return MIB . constrainAllUses ( TII , TRI , RBI ) ;


<s> dbgs ( ) << <STR_LIT> << maxH << <STR_LIT> ; ) ; DEBUG ( unsigned maxD = <NUM_LIT> ; for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) if ( SUnits [ su ] . getDepth ( ) > maxD ) maxD = SUnits [ su ] . getDepth ( ) ; dbgs ( ) << <STR_LIT> << maxD << <STR_LIT> ; ) ; DEBUG ( for ( unsigned su = <NUM_LIT> , e = SUnits . size ( ) ; su != e ; ++ su ) SUnits [ su ] . dumpAll ( this ) ) ; initQueues ( TopRoots , BotRoots ) ;


<s> AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; TII = static_cast < const Thumb2InstrInfo * > ( STI . getInstrInfo ( ) ) ; TRI = STI . getRegisterInfo ( ) ; restrictIT = STI . restrictIT ( ) ; if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( auto & MBB : Fn ) Modified |= InsertITInstructions ( MBB ) ;

if ( Modified ) AFI -> setHasITBlocks ( true ) ;


<s> bool isGPR64sp0 ( ) const { return Kind == k_Register && ! Reg . isVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectVOP3NoMods ( SDValue In , SDValue & Src ) const { if ( In . getOpcode ( ) == <STR_LIT> || In . getOpcode ( ) == <STR_LIT> ) return false ;


<s> EVT PTy = getPointerTy ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; <ISA_LIT>FunctionInfo * AFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDValue UId = DAG . getConstant ( AFI -> createJumpTableUId ( ) , PTy ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PTy ) ; Table = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI , UId ) ; Index = DAG . getNode ( <STR_LIT> , dl , PTy , Index , DAG . getConstant ( <NUM_LIT> , PTy ) ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Index , Table ) ; if ( Subtarget -> isThumb2 ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , Op . getOperand ( <NUM_LIT> ) , JTI , UId ) ; } if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { Addr = DAG . getLoad ( ( EVT ) <STR_LIT> , dl , Chain , Addr , PseudoSourceValue :: getJumpTable ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; Addr = DAG . getNode ( <STR_LIT> , dl , PTy , Addr , Table ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI , UId ) ; } else { Addr = DAG . getLoad ( PTy , dl , Chain , Addr , PseudoSourceValue :: getJumpTable ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Addr . getValue ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Addr , JTI , UId ) ;


<s> SMLoc getStartLoc ( ) const override { return StartLoc ;


<s> p = NULL ; fprintf ( stderr , <STR_LIT> , prefix , q ) ; prefix = <STR_LIT> ; } } else if ( TREE_CODE ( args ) == TREE_LIST ) { do { tree value = TREE_VALUE ( args ) ; if ( value ) { rs6000_debug_target_options ( value , prefix ) ; prefix = <STR_LIT> ;


<s> MCSection * getExplicitSectionGlobal ( const GlobalObject * GO , SectionKind Kind , const TargetMachine & TM ) const override {


<s> int Bytes ; if ( isa < ConstantArray > ( CPV ) || isa < ConstantVector > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) for ( unsigned i = <NUM_LIT> , e = CPV -> getNumOperands ( ) ; i != e ; ++ i ) bufferLEByte ( cast < Constant > ( CPV -> getOperand ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( const ConstantDataSequential * CDS = dyn_cast < ConstantDataSequential > ( CPV ) ) { if ( CDS -> getNumElements ( ) ) for ( unsigned i = <NUM_LIT> ; i < CDS -> getNumElements ( ) ; ++ i ) bufferLEByte ( cast < Constant > ( CDS -> getElementAsConstant ( i ) ) , <NUM_LIT> , aggBuffer ) ; return ; } if ( isa < ConstantStruct > ( CPV ) ) { if ( CPV -> getNumOperands ( ) ) {

StructType * ST = cast < StructType > ( CPV -> getType ( ) ) ;


<s> return ! any_of ( M , [ & ] ( const Function & F ) {

return F . getFnAttribute ( Attr ) . getValueAsString ( ) != Value ;


<s> void <ISA_LIT>InstPrinter :: printShiftedRegister ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) ; printShifter ( MI , OpNum + <NUM_LIT> , STI , O ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitJal ( const MCSubtargetInfo & STI , MCSymbol * Symbol ) { MCInst I ; I . setOpcode ( <STR_LIT> ) ; I . addOperand ( MCOperand :: createExpr ( MCSymbolRefExpr :: create ( Symbol , OutContext ) ) ) ; OutStreamer -> EmitInstruction ( I , STI ) ;


<s> PreservedAnalyses <ISA_LIT>IRPeepholePass :: run ( Function & F , FunctionAnalysisManager & AM ) {

return <ISA_LIT>IRPeepholeImpl ( F ) ? PreservedAnalyses :: none ( ) : PreservedAnalyses :: all ( ) ;


<s> const int64_t C0 = C0Node -> getSExtValue ( ) ; APInt CA = C0Node -> getAPIntValue ( ) * C1Node -> getAPIntValue ( ) ; if ( ! isLegalAddImmediate ( C0 ) || isLegalAddImmediate ( CA . getSExtValue ( ) ) ) return true ; if ( ConstantMaterializationCost ( ( unsigned ) CA . getZExtValue ( ) , Subtarget ) > <NUM_LIT> ) return false ;


<s> if ( ! LiveRegs . contains ( get<ISA_LIT>SubSuperRegister ( OrigDestReg , <NUM_LIT> ) ) && ! LiveRegs . contains ( get<ISA_LIT>SubSuperRegister ( SuperDestReg , <NUM_LIT> , true ) ) ) return true ; } unsigned Opc = OrigMI -> getOpcode ( ) ; ( void ) Opc ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; bool IsDefined = false ; for ( auto & MO : OrigMI -> implicit_operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; assert ( ( MO . isDef ( ) || MO . isUse ( ) ) && <STR_LIT> ) ; if ( MO . isDef ( ) && TRI -> isSuperRegisterEq ( OrigDestReg , MO . getReg ( ) ) ) IsDefined = true ; if ( MO . isUse ( ) && ! TRI -> isSubRegisterEq ( OrigDestReg , MO . getReg ( ) ) && TRI -> regsOverlap ( SuperDestReg , MO . getReg ( ) ) ) return false ;


<s> auto * Int257Ty = Type :: getIntNTy ( Ctx , <NUM_LIT> ) ; if ( Ty == Int257Ty ) return ConstantInt :: get ( Int257Ty , <NUM_LIT> ) ; if ( Ty == Type :: get<ISA_LIT>CellTy ( Ctx ) ) { IRBuilder < > Builder ( & I ) ; CallInst * Pushnull = Builder . CreateIntrinsic ( <STR_LIT> ) ; auto * Fn = <STR_LIT> ( I . getModule ( ) , <STR_LIT> ) ; return Builder . CreateCall ( Fn , ArrayRef < Value * > { Pushnull } ) ; } if ( Ty == Type :: get<ISA_LIT>SliceTy ( Ctx ) ) { IRBuilder < > Builder ( & I ) ; CallInst * Pushnull = Builder . CreateIntrinsic ( <STR_LIT> ) ; auto * Fn = <STR_LIT> ( I . getModule ( ) , <STR_LIT> ) ; return Builder . CreateCall ( Fn , ArrayRef < Value * > { Pushnull } ) ; }

if ( Ty == Type :: get<ISA_LIT>BuilderTy ( Ctx ) ) {


<s> static int64_t get_ldah16 ( int64_t x ) { int64_t y = x / IMM_MULT ; if ( x % IMM_MULT > IMM_HIGH ) ++ y ;


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & getInstrInfo ( ) -> getRegisterInfo ( ) ;


<s> if ( EltVT == <STR_LIT> ) { Constant * C = ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } else { Constant * C = ConstantFP :: get ( APFloat ( APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; CV . push_back ( C ) ; } Constant * C = ConstantVector :: get ( CV ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , <NUM_LIT> ) ;


<s> bool isLegalToVectorizeReduction ( const RecurrenceDescriptor & RdxDesc , ElementCount VF ) const { if ( ! VF . isScalable ( ) ) return true ; Type * Ty = RdxDesc . getRecurrenceType ( ) ; if ( ! TLI -> isLegalElementTypeForRVV ( Ty ) ) return false ; switch ( RdxDesc . getRecurrenceKind ( ) ) { case RecurKind :: Add : case RecurKind :: FAdd : case RecurKind :: And : case RecurKind :: Or : case RecurKind :: Xor : case RecurKind :: SMin : case RecurKind :: SMax : case RecurKind :: UMin : case RecurKind :: UMax : case RecurKind :: FMin : case RecurKind :: FMax : return true ; default :


<s> MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } FrameReg = RI -> getFrameRegister ( MF ) ; if ( ( FI >= MinCSFI && FI <= MaxCSFI ) || ! hasFP ( MF ) ) {


<s> static void DecodeSymbolicOperandOff ( MCInst & Inst , uint64_t Address , uint64_t Offset , const void * Decoder ) {

uint64_t NextAddress = Address + Offset ;


<s> EVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) ; unsigned XorOp = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MachineSDNode * Node = DAG . getMachineNode ( XorOp , DL , PtrTy , Val ) ; return SDValue ( Node , <NUM_LIT> ) ;


<s> unsigned long save_reg_mask = <NUM_LIT> ; unsigned int reg ; if ( IS_INTERRUPT ( func_type ) ) { unsigned int max_reg ; if ( ARM_FUNC_TYPE ( func_type ) == ARM_FT_FIQ ) max_reg = <NUM_LIT> ; else max_reg = <NUM_LIT> ; for ( reg = <NUM_LIT> ; reg <= max_reg ; reg ++ ) if ( reg_needs_saving_p ( reg ) ) save_reg_mask |= ( <NUM_LIT> << reg ) ; if ( PIC_REGISTER_MAY_NEED_SAVING && crtl -> uses_pic_offset_table ) save_reg_mask |= <NUM_LIT> << PIC_OFFSET_TABLE_REGNUM ; } else if ( IS_VOLATILE ( func_type ) ) { if ( frame_pointer_needed ) save_reg_mask |= <NUM_LIT> << HARD_FRAME_POINTER_REGNUM ; if ( df_regs_ever_live_p ( ARM_HARD_FRAME_POINTER_REGNUM ) ) save_reg_mask |= <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ; if ( df_regs_ever_live_p ( THUMB_HARD_FRAME_POINTER_REGNUM ) ) save_reg_mask |= <NUM_LIT> << THUMB_HARD_FRAME_POINTER_REGNUM ; } else { for ( reg = <NUM_LIT> ; reg <= <NUM_LIT> ; reg ++ ) if ( df_regs_ever_live_p ( reg ) && callee_saved_reg_p ( reg ) ) save_reg_mask |= ( <NUM_LIT> << reg ) ; if ( frame_pointer_needed ) save_reg_mask |= <NUM_LIT> << HARD_FRAME_POINTER_REGNUM ; if ( PIC_REGISTER_MAY_NEED_SAVING && ( df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) || crtl -> uses_pic_offset_table ) ) save_reg_mask |= <NUM_LIT> << PIC_OFFSET_TABLE_REGNUM ; if ( IS_STACKALIGN ( func_type ) ) save_reg_mask |= <NUM_LIT> ; } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = <NUM_LIT> ; ; i ++ ) { reg = EH_RETURN_DATA_REGNO ( i ) ; if ( reg == INVALID_REGNUM ) break ; save_reg_mask |= <NUM_LIT> << reg ;


<s> EVT VT = Data . getValueType ( ) ; bool Byte = cast < AtomicSDNode > ( Op ) -> getMemoryVT ( ) == <STR_LIT> ; SDValue NewData = DAG . getNode ( <STR_LIT> , DL , VT , Data , Bits ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , { NewData , DAG . getConstant ( Byte ? <NUM_LIT> : <NUM_LIT> , DL , VT ) } ) ;


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override { auto MMO = MIRBuilder . getMF ( ) . getMachineMemOperand ( MPO , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant , Size , <NUM_LIT> ) ; MIRBuilder . buildLoad ( ValVReg , Addr , * MMO ) ;


<s> decltype ( MaxPressure ) moveMaxPressure ( ) { auto Res = MaxPressure ; MaxPressure . clear ( ) ; return Res ;


<s> if ( loongarch_rtx_constant_in_small_data_p ( mode ) ) return get_named_section ( NULL , <STR_LIT> , <NUM_LIT> ) ;

return default_elf_select_rtx_section ( mode , x , align ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T ) : MCAsmBackend ( ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DataLayout ( is64Bit ? DataLayout64 : DataLayout32 ) , Subtarget ( TT , CPU , FS , is64Bit ) , FrameLowering ( Subtarget ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo ( * this ) {


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ; switch ( Desc . getOpcode ( ) ) { default : return <NUM_LIT> ; case TargetOpcode :: DBG_VALUE :


<s> Op -> Mem . IndexReg = Index ; Op -> Mem . Index = nullptr ; Op -> Mem . Offset = Imm ;


<s> static void ix86_add_new_builtins ( HOST_WIDE_INT isa , HOST_WIDE_INT isa2 ) { if ( ( isa & deferred_isa_values ) == <NUM_LIT> && ( isa2 & deferred_isa_values2 ) == <NUM_LIT> ) return ; deferred_isa_values &= ~ isa ; deferred_isa_values2 &= ~ isa2 ; int i ; tree saved_current_target_pragma = current_target_pragma ; current_target_pragma = NULL_TREE ; for ( i = <NUM_LIT> ; i < ( int ) IX86_BUILTIN_MAX ; i ++ ) { if ( ( ( ix86_builtins_isa [ i ] . isa & isa ) != <NUM_LIT> || ( ix86_builtins_isa [ i ] . isa2 & isa2 ) != <NUM_LIT> ) && ix86_builtins_isa [ i ] . set_and_not_built_p ) { tree decl , type ; ix86_builtins_isa [ i ] . set_and_not_built_p = false ; type = ix86_get_builtin_func_type ( ix86_builtins_isa [ i ] . tcode ) ; decl = add_builtin_function_ext_scope ( ix86_builtins_isa [ i ] . name , type , i , BUILT_IN_MD , NULL , NULL_TREE ) ; ix86_builtins [ i ] = decl ; if ( ix86_builtins_isa [ i ] . const_p ) TREE_READONLY ( decl ) = <NUM_LIT> ; if ( ix86_builtins_isa [ i ] . leaf_p ) DECL_ATTRIBUTES ( decl ) = build_tree_list ( get_identifier ( <STR_LIT> ) , NULL_TREE ) ;

if ( ix86_builtins_isa [ i ] . nothrow_p ) TREE_NOTHROW ( decl ) = <NUM_LIT> ;


<s> assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( IsStore ( MI ) ) { if ( Offset >= - <NUM_LIT> && Offset <= <NUM_LIT> ) { MI . getOperand ( i ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; } else { MI . getOperand ( i ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } } else { MI . getOperand ( i ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo InfosLE [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ;

const static MCFixupKindInfo InfosBE [ <STR_LIT> ] = {


<s> SDValue ConstantVector ( MVT VT , int ElemVal ) { assert ( VT . isVector ( ) && <STR_LIT> ) ; SDValue Elem = Constant ( ElemVal , VT . getVectorElementType ( ) ) ; SmallVector < SDValue , <NUM_LIT> > Pool ;

for ( unsigned i = <NUM_LIT> ; i < VT . getVectorNumElements ( ) ; ++ i ) Pool . push_back ( Elem ) ;


<s> * __P = ( unsigned int ) ( __res >> <NUM_LIT> ) ; return ( unsigned int ) __res ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( <ISA_LIT>AsmPrinter & asmprinter ) : AsmPrinter ( asmprinter ) {


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;

assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ;


<s> GlueToNewValueJump = false ; GlueAllocframeStore = false ; FoundSequentialDependence = false ;


<s> void <ISA_LIT>SEFrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; if ( MF . getFrameInfo ( ) . hasCalls ( ) ) setAliasRegs ( MF , SavedRegs , <STR_LIT> ) ;


<s> unsigned char <ISA_LIT>Subtarget :: ClassifyGlobalReference ( const GlobalValue * GV , const TargetMachine & TM ) const { bool isDecl = GV -> isDeclarationForLinker ( ) ; if ( TM . getCodeModel ( ) == CodeModel :: Large && isTargetMachO ( ) ) return <STR_LIT> ;

if ( TM . getCodeModel ( ) == CodeModel :: Small && GV -> isWeakForLinker ( ) && isDecl ) {


<s> default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; Predicate = CmpInst :: ICMP_NE ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; Predicate = CmpInst :: ICMP_NE ; break ; } bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; if ( SETFOpc ) { unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; auto const & II = TII . get ( SETFOpc [ <NUM_LIT> ] ) ; if ( II . getNumDefs ( ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } } NeedTest = false ; } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , I , Cond ) ) {

unsigned TmpReg = getRegForValue ( Cond ) ;


<s> if ( GET_CODE ( reg1 ) != REG || GET_CODE ( reg2 ) != REG ) return <NUM_LIT> ; if ( REGNO ( reg1 ) % <NUM_LIT> != <NUM_LIT> ) return <NUM_LIT> ;

if ( TARGET_V9 && SPARC_INT_REG_P ( REGNO ( reg1 ) ) ) return <NUM_LIT> ;


<s> bool has<ISA_LIT>64r3 ( ) const { return ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) ;


<s> if ( INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != <NUM_LIT> ) return false ; break ; case <NUM_LIT> : if ( ! TARGET_LL64 ) return false ; case <NUM_LIT> : if ( INTVAL ( XEXP ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) != <NUM_LIT> ) return false ; default : return false ; } if ( RTX_OK_FOR_BASE_P ( XEXP ( op , <NUM_LIT> ) , ( strict ) ) ) return true ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ;

Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> static void output_reg_adjust ( rtx reg , int n ) { const char * s ; gcc_assert ( GET_MODE ( reg ) == SImode && n >= - <NUM_LIT> && n != <NUM_LIT> && n <= <NUM_LIT> ) ; switch ( n ) { case <NUM_LIT> : s = <STR_LIT> ; break ;


return __builtin_aarch64_reduc_smax_scal_v2si ( __a ) ;


<s> <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_ARM , false ) {


<s> if ( TARGET_POST_INC && ( GET_CODE ( x ) == POST_DEC || GET_CODE ( x ) == POST_INC ) && RTX_OK_FOR_BASE_P ( XEXP ( ( x ) , <NUM_LIT> ) ) ) return true ; if ( ( TARGET_POST_MODIFY || reload_completed ) && GET_CODE ( x ) == POST_MODIFY && GET_CODE ( XEXP ( ( x ) , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( ( x ) , <NUM_LIT> ) , XEXP ( XEXP ( ( x ) , <NUM_LIT> ) , <NUM_LIT> ) ) && LEGITIMATE_OFFSET_ADDRESS_P ( mode , XEXP ( ( x ) , <NUM_LIT> ) ) ) return true ; if ( mode == BLKmode ) return epiphany_legitimate_address_p ( SImode , x , strict ) ; return false ;


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;

if ( hasFP ( MF ) ) MRI . setPhysRegUsed ( <STR_LIT> ) ;


<s> const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool isDirect = ! Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( STI , isDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool isThumb = STI . isThumb ( ) ; if ( isThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Callee ) ; if ( ! isDirect ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = isThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) return false ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , Arg . Reg ) ; } auto ArgAssignFn = TLI . CCAssignFnForCall ( CallConv , false ) ; OutgoingValueHandler ArgHandler ( MIRBuilder , MRI , MIB , ArgAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , ArgHandler ) ) return false ; MIRBuilder . insertInstr ( MIB ) ; if ( ! OrigRet . Ty -> isVoidTy ( ) ) { if ( ! isSupportedType ( DL , TLI , OrigRet . Ty ) ) return false ; ArgInfos . clear ( ) ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , ArgInfos , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { SplitRegs . push_back ( Reg ) ; } ) ; auto RetAssignFn = TLI . CCAssignFnForReturn ( CallConv , false ) ; CallReturnHandler RetHandler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , ArgInfos , RetHandler ) ) return false ;


<s> if ( ! reload_in_progress ) operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ; } if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) && tilegx_tls_referenced_p ( operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = tilegx_legitimize_tls_address ( operands [ <NUM_LIT> ] ) ; return false ; } if ( flag_pic && CONSTANT_P ( operands [ <NUM_LIT> ] ) ) { if ( tilegx_pic_address_needs_scratch ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = tilegx_legitimize_pic_address ( operands [ <NUM_LIT> ] , mode , <NUM_LIT> ) ; if ( symbolic_operand ( operands [ <NUM_LIT> ] , mode ) ) { operands [ <NUM_LIT> ] = tilegx_legitimize_pic_address ( operands [ <NUM_LIT> ] , mode , ( reload_in_progress ? operands [ <NUM_LIT> ] : NULL_RTX ) ) ; return false ; } }

if ( ! CONSTANT_P ( operands [ <NUM_LIT> ] ) || move_operand ( operands [ <NUM_LIT> ] , mode ) ) return false ;


printU4ImmOperand ( MI , OpNo , STI , O ) ;


<s> MCTargetStreamer * llvm :: create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) {

return new <ISA_LIT>TargetAsmStreamer ( S , OS ) ;


<s> Register PromotedReg2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg0 ) . addReg ( Reg ) ; BuildMI ( BB , DL , TII . get ( <STR_LIT> ) , PromotedReg1 ) . addReg ( PromotedReg0 ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII . get ( RShiftOp ) , PromotedReg2 ) . addReg ( PromotedReg1 ) . addImm ( <NUM_LIT> ) ; return PromotedReg2 ;


<s> const auto * RVFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( CSI . empty ( ) || ! RVFI -> useSaveRestoreLibCalls ( MF ) ) return - <NUM_LIT> ; Register MaxReg = <STR_LIT> ; for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) < <NUM_LIT> ) MaxReg = std :: max ( MaxReg . id ( ) , CS . getReg ( ) ) ; if ( MaxReg == <STR_LIT> ) return - <NUM_LIT> ; switch ( MaxReg ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , bool is64Bit ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , StackAlignment ( <NUM_LIT> ) , DarwinDirective ( <STR_LIT> ) , IsGigaProcessor ( false ) , Has64BitSupport ( false ) , Use64BitRegs ( false ) , Is<ISA_LIT>64 ( is64Bit ) , HasAltivec ( false ) , HasFSQRT ( false ) , HasSTFIWX ( false ) , HasLazyResolverStubs ( false ) , IsJITCodeModel ( false ) , TargetTriple ( TT ) { std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; if ( CPUName == <STR_LIT> ) CPUName = GetCurrentPowerPCCPU ( ) ; ParseSubtargetFeatures ( CPUName , FS ) ;

InstrItins = getInstrItineraryForCPU ( CPUName ) ;


<s> if ( alignment < PARM_BOUNDARY ) alignment = PARM_BOUNDARY ; if ( alignment > STACK_BOUNDARY ) alignment = STACK_BOUNDARY ;


<s> Chain ( MachineInstr * MI , unsigned Idx , Color C ) : StartInst ( MI ) , LastInst ( MI ) , KillInst ( nullptr ) , StartInstIdx ( Idx ) , LastInstIdx ( Idx ) , KillInstIdx ( <NUM_LIT> ) , LastColor ( C ) {


<s> { <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; const uint64_t OptimalCount = ( Count < <NUM_LIT> ) ? Count : <NUM_LIT> ; const uint64_t Prefixes = OptimalCount <= <NUM_LIT> ? <NUM_LIT> : OptimalCount - <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> , e = Prefixes ; i != e ; i ++ ) OW -> Write8 ( <NUM_LIT> ) ; const uint64_t Rest = OptimalCount - Prefixes ; for ( uint64_t i = <NUM_LIT> , e = Rest ; i != e ; i ++ ) OW -> Write8 ( Nops [ Rest - <NUM_LIT> ] [ i ] ) ; for ( uint64_t i = OptimalCount , e = Count ; i != e ; ++ i ) OW -> Write8 ( <NUM_LIT> ) ; return true ;


<s> Val = getToken ( ) . getStringContents ( ) ; lex ( ) ; return true ; } else { Error ( getLoc ( ) , ErrMsg ) ; return false ;


<s> static inline unsigned getThumbImmValShift ( unsigned Imm ) { if ( ( Imm & ~ <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> Optional < std :: string > getOutliningStyle ( ) const { return OutliningStyle ;


<s> bool iss11_3Ext ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true , true , true ) ;


<s> bool loongarch_eh_uses ( unsigned int regno ATTRIBUTE_UNUSED ) {


<s> } return V ; } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool ThisIsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( ThisIsNonZero && First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } if ( ( i & <NUM_LIT> ) != <NUM_LIT> ) { SDValue ThisElt , LastElt ; bool LastIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ; if ( LastIsNonZero ) { LastElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i - <NUM_LIT> ) ) ; } if ( ThisIsNonZero ) { ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ; ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; if ( LastIsNonZero ) ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , LastElt ) ; } else ThisElt = LastElt ; if ( ThisElt . getNode ( ) ) V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , ThisElt , DAG . getIntPtrConstant ( i / <NUM_LIT> ) ) ; }


<s> static bool isZeroImm ( const MachineOperand & Op ) { return Op . isImm ( ) && Op . getImm ( ) == <NUM_LIT> ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> <ISA_LIT>_64TargetMachine :: <ISA_LIT>_64TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>TargetMachine ( T , TT , FS , true ) {


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool IsThumb ) {

<ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Context , TAB , OS , Emitter , IsThumb ) ;


<s> LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; DA = & getAnalysis < DivergenceAnalysis > ( ) ; for ( df_iterator < BasicBlock * > I = df_begin ( & F . getEntryBlock ( ) ) , E = df_end ( & F . getEntryBlock ( ) ) ; I != E ; ++ I ) { BasicBlock * BB = * I ; BranchInst * Term = dyn_cast < BranchInst > ( BB -> getTerminator ( ) ) ; if ( ! Term || Term -> isUnconditional ( ) ) { if ( isTopOfStack ( BB ) ) closeControlFlow ( BB ) ;


<s> tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tree arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = Pmode ; machine_mode mode1 = Pmode ; rtx op0 = expand_normal ( arg0 ) ; rtx op1 = expand_normal ( arg1 ) ; if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ; if ( arg0 == error_mark_node || arg1 == error_mark_node ) return const0_rtx ; if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( op0 == const0_rtx ) { addr = gen_rtx_MEM ( tmode , op1 ) ; } else { op0 = copy_to_mode_reg ( mode0 , op0 ) ; addr = gen_rtx_MEM ( tmode , gen_rtx_PLUS ( Pmode , op0 , op1 ) ) ; } pat = GEN_FCN ( icode ) ( target , addr ) ; if ( ! pat ) return <NUM_LIT> ;


<s> reportParseError ( <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( true , isABI_O32 ( ) ) ; clearFeatureBits ( <STR_LIT> , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { if ( ! isABI_O32 ( ) ) { Error ( L , <STR_LIT> ) ; return false ; } getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( false , isABI_O32 ( ) ) ; setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) {