<s> for ( i = nregs - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) emit_insn ( gen_rtx_SET ( VOIDmode , simplify_gen_subreg ( reg_mode , dst , mode , i * reg_mode_size ) , simplify_gen_subreg ( reg_mode , src , mode , i * reg_mode_size ) ) ) ; } else { int i ; int j = - <NUM_LIT> ; bool used_update = false ; if ( MEM_P ( src ) && INT_REGNO_P ( reg ) ) { rtx breg ; if ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == PRE_INC || GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == PRE_DEC ) { rtx delta_rtx ; breg = XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ; delta_rtx = ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == PRE_INC ? GEN_INT ( GET_MODE_SIZE ( GET_MODE ( src ) ) ) : GEN_INT ( - GET_MODE_SIZE ( GET_MODE ( src ) ) ) ) ; emit_insn ( TARGET_32BIT ? gen_addsi3 ( breg , breg , delta_rtx ) : gen_adddi3 ( breg , breg , delta_rtx ) ) ; src = replace_equiv_address ( src , breg ) ; } else if ( ! offsettable_memref_p ( src ) ) { rtx basereg ; basereg = gen_rtx_REG ( Pmode , reg ) ; emit_insn ( gen_rtx_SET ( VOIDmode , basereg , XEXP ( src , <NUM_LIT> ) ) ) ; src = replace_equiv_address ( src , basereg ) ; } breg = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( breg ) == PLUS || GET_CODE ( breg ) == LO_SUM ) breg = XEXP ( breg , <NUM_LIT> ) ; if ( REG_P ( breg ) && REGNO ( breg ) >= REGNO ( dst ) && REGNO ( breg ) < REGNO ( dst ) + nregs ) j = REGNO ( breg ) - REGNO ( dst ) ; } if ( GET_CODE ( dst ) == MEM && INT_REGNO_P ( reg ) ) { rtx breg ;

if ( GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PRE_INC || GET_CODE ( XEXP ( dst , <NUM_LIT> ) ) == PRE_DEC ) {


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result ;


<s> assert ( Ex . S == <NUM_LIT> && <STR_LIT> ) ; assert ( ! Ex . Neg && <STR_LIT> ) ; InitI = BuildMI ( MBB , At , dl , HII -> get ( <STR_LIT> ) , DefR ) . add ( MachineOperand ( Ex . Rs ) ) . add ( ExtOp ) ; } else { assert ( ( Ex . Rs . Reg == <NUM_LIT> || Ex . Rs . isVReg ( ) ) && <STR_LIT> ) ; if ( Ex . trivial ( ) ) { InitI = BuildMI ( MBB , At , dl , HII -> get ( <STR_LIT> ) , DefR ) . add ( ExtOp ) ; } else if ( Ex . S == <NUM_LIT> ) { if ( Ex . Neg ) { InitI = BuildMI ( MBB , At , dl , HII -> get ( <STR_LIT> ) , DefR ) . add ( ExtOp ) . add ( MachineOperand ( Ex . Rs ) ) ; } else { InitI = BuildMI ( MBB , At , dl , HII -> get ( <STR_LIT> ) , DefR ) . add ( MachineOperand ( Ex . Rs ) ) . add ( ExtOp ) ; } } else { unsigned NewOpc = Ex . Neg ? <STR_LIT> : <STR_LIT> ; InitI = BuildMI ( MBB , At , dl , HII -> get ( NewOpc ) , DefR ) . add ( ExtOp ) . add ( MachineOperand ( Ex . Rs ) ) . addImm ( Ex . S ) ; } } assert ( InitI ) ; ( void ) InitI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> << PrintInit ( ExtI , * HRI ) << <STR_LIT> << * InitI ) ; return { DefR , <NUM_LIT> } ;


<s> cvtT2LdrdPre ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;

( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemImm8s4OffsetOperands ( Inst , <NUM_LIT> ) ;


<s> } for ( unsigned i = <NUM_LIT> , e = Shuffles . size ( ) ; i < e ; ++ i ) Shuffles [ i ] -> replaceAllUsesWith ( TransposedVectors [ Indices [ i ] ] ) ; return true ; } Type * ShuffleEltTy = ShuffleTy -> getVectorElementType ( ) ; unsigned NumSubVecElems = ShuffleTy -> getVectorNumElements ( ) / Factor ; decompose ( Shuffles [ <NUM_LIT> ] , Factor , VectorType :: get ( ShuffleEltTy , NumSubVecElems ) , DecomposedVectors ) ; switch ( NumSubVecElems ) { case <NUM_LIT> : transpose_4x4 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> : interleave8bitStride4VF8 ( DecomposedVectors , TransposedVectors ) ; break ; case <NUM_LIT> :


<s> RegisterTarget < Triple :: kudeyar > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> static void LowerMemOpCallTo ( SelectionDAG & DAG , MachineFunction & MF , SDValue Chain , SDValue Arg , SDValue PtrOff , int SPDiff , unsigned ArgOffset , bool is<ISA_LIT>64 , bool isTailCall , bool isVector , SmallVector < SDValue , <NUM_LIT> > & MemOpChains , SmallVector < TailCallArgumentInfo , <NUM_LIT> > & TailCallArguments , SDLoc dl ) { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; if ( ! isTailCall ) { if ( isVector ) { SDValue StackPtr ; if ( is<ISA_LIT>64 ) StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; else StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;

PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , DAG . getConstant ( ArgOffset , PtrVT ) ) ;


<s> if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; DebugLoc dl = InputVector . getDebugLoc ( ) ; SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; for ( SmallVectorImpl < SDNode * > :: iterator UI = Uses . begin ( ) , UE = Uses . end ( ) ; UI != UE ; ++ UI ) { SDNode * Extract = * UI ; SDValue Idx = Extract -> getOperand ( <NUM_LIT> ) ; unsigned EltSize = InputVector . getValueType ( ) . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; uint64_t Offset = EltSize * cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ;

SDValue OffsetVal = DAG . getConstant ( Offset , TLI . getPointerTy ( ) ) ;


<s> void ReplaceTXF ( CallInst & I ) { Value * Coord = I . getArgOperand ( <NUM_LIT> ) ; Value * ResourceId = I . getArgOperand ( <NUM_LIT> ) ; Value * SamplerId = I . getArgOperand ( <NUM_LIT> ) ;

unsigned TextureType = cast < ConstantInt > ( I . getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ; default : return false ; }


<s> LineReader * <ISA_LIT>AsmPrinter :: getReader ( std :: string filename ) { if ( reader == NULL ) { reader = new LineReader ( filename ) ; }

if ( reader -> fileName ( ) != filename ) {


<s> unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getSExtValue ( ) ) ; return ImmReg ; } int64_t Imm = CI -> getZExtValue ( ) ; if ( VT == <STR_LIT> ) return <ISA_LIT>Materialize64BitInt ( Imm , RC ) ; else if ( VT == <STR_LIT> ) return <ISA_LIT>Materialize32BitInt ( Imm , RC ) ;


<s> Builder . addExtension ( PassManagerBuilder :: EP_ModuleOptimizerEarly , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) {

PM . add ( create<ISA_LIT>UnifyMetadataPass ( ) ) ;


<s> CCInfo . AnalyzeFormalArguments ( * Ins , ArgCC_<ISA_LIT>_Vararg ) ; } return ; } SmallVector < unsigned , <NUM_LIT> > Args ; if ( IsCall ) { parseExternFuncCallArgs ( * Outs , Args ) ; } else { assert ( F != nullptr && <STR_LIT> ) ; parseFunctionArgs ( F , TD , Args ) ; } unsigned RegsLeft = array_lengthof ( RegList8 ) , ValNo = <NUM_LIT> ; bool UsesStack = false ; for ( unsigned i = <NUM_LIT> , pos = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i ) { unsigned Size = Args [ i ] ; if ( Size == <NUM_LIT> ) continue ; MVT LocVT = ( IsCall ) ? ( * Outs ) [ pos ] . VT : ( * Ins ) [ pos ] . VT ; if ( ! UsesStack && ( Size <= RegsLeft ) ) { const MCPhysReg * RegList = ( LocVT == <STR_LIT> ) ? RegList16 : RegList8 ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) { unsigned Reg = CCInfo . AllocateReg ( ArrayRef < MCPhysReg > ( RegList , array_lengthof ( RegList8 ) ) ) ; CCInfo . addLoc ( CCValAssign :: getReg ( ValNo ++ , LocVT , Reg , LocVT , CCValAssign :: Full ) ) ; -- RegsLeft ; } std :: reverse ( ArgLocs . begin ( ) + pos , ArgLocs . begin ( ) + pos + Size ) ; } else { UsesStack = true ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ( ( Subtarget -> hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , true ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , LHS , RHS ) ; return SDValue ( ) ;


<s> <STR_LIT> getTargetABI ( ) const { return TargetABI ;


<s> if ( parseImmediate ( Operands ) == MatchOperand_Success ) { if ( getLexer ( ) . is ( AsmToken :: LParen ) ) return parseMemOpBaseReg ( Operands ) != MatchOperand_Success ; return false ; } Error ( getLoc ( ) , <STR_LIT> ) ; return true ;


<s> if ( op != MOVE_BY_PIECES || ( speed_p && ( size > ( MOVE_MAX_PIECES ) ) ) ) return default_use_by_pieces_infrastructure_p ( size , align , op , speed_p ) ; return size <= ( MOVE_MAX_PIECES ) ;


<s> bool hasAutoWaitcntBeforeBarrier ( ) const {


<s> while ( I != MBB . instr_begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ;


<s> if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , * I2 , MI , DoInsertAtI1 , OptForSize ) ;


<s> if ( a < <NUM_LIT> ) return - local_fixunsdfdi ( - a ) ;


<s> switch ( this -> Subtarget . getDarwinDirective ( ) ) { default : return false ; case <STR_LIT> : return true ; case <STR_LIT> : return IsAddOne && IsNeg ? VT . isVector ( ) : true ; } } ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; const APInt & MulAmt = ConstOpOrElement -> getAPIntValue ( ) ; bool IsNeg = MulAmt . isNegative ( ) ; APInt MulAmtAbs = MulAmt . abs ( ) ; if ( ( MulAmtAbs - <NUM_LIT> ) . isPowerOf2 ( ) ) { if ( ! IsProfitable ( IsNeg , true , VT ) ) return SDValue ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( MulAmtAbs - <NUM_LIT> ) . logBase2 ( ) , DL , VT ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , Op0 , Op1 ) ; if ( ! IsNeg ) return Res ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Res ) ; } else if ( ( MulAmtAbs + <NUM_LIT> ) . isPowerOf2 ( ) ) {

if ( ! IsProfitable ( IsNeg , false , VT ) ) return SDValue ( ) ;


<s> MVT getPairVT ( MVT ElemTy ) const { unsigned NumElems = ( <NUM_LIT> * HwLen ) / ( ElemTy . getSizeInBits ( ) / <NUM_LIT> ) ; return <STR_LIT> ( ElemTy , NumElems ) ;


<s> static <ISA_LIT>Operand * CreateRotImm ( unsigned Imm , SMLoc S , SMLoc E ) {

<ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_RotateImmediate ) ;


<s> const RegisterBank & <ISA_LIT>RegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC , LLT ) const { using namespace <ISA_LIT> ; switch ( RC . getID ( ) ) { case GPRRegClassID : case GPRwithAPSRRegClassID : case GPRnoipRegClassID : case GPRnopcRegClassID : case GPRnoip_and_GPRnopcRegClassID : case rGPRRegClassID : case GPRspRegClassID : case GPRnoip_and_tcGPRRegClassID : case tcGPRRegClassID :


<s> bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ;


<s> LoopInfo * LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; for ( auto & L : LI -> getLoopsInPreorder ( ) ) { assert ( L -> isLCSSAForm ( DT ) ) ; } Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ;

return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> SDValue AlignedAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( - <NUM_LIT> , PtrVT ) ) ; SDValue BitShift = DAG . getNode ( <STR_LIT> , DL , PtrVT , Addr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; BitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift ) ; SDValue NegBitShift = DAG . getNode ( <STR_LIT> , DL , WideVT , DAG . getConstant ( <NUM_LIT> , WideVT ) , BitShift ) ; if ( Opcode != <STR_LIT> ) Src2 = DAG . getNode ( <STR_LIT> , DL , WideVT , Src2 , DAG . getConstant ( <NUM_LIT> - BitSize , WideVT ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Src2 = DAG . getNode ( <STR_LIT> , DL , WideVT , Src2 , DAG . getConstant ( uint32_t ( - <NUM_LIT> ) >> BitSize , WideVT ) ) ; SDVTList VTList = DAG . getVTList ( WideVT , <STR_LIT> ) ; SDValue Ops [ ] = { ChainIn , AlignedAddr , Src2 , BitShift , NegBitShift , DAG . getConstant ( BitSize , WideVT ) } ; SDValue AtomicOp = DAG . getMemIntrinsicNode ( Opcode , DL , VTList , Ops , NarrowVT , MMO ) ; SDValue ResultShift = DAG . getNode ( <STR_LIT> , DL , WideVT , BitShift , DAG . getConstant ( BitSize , WideVT ) ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , WideVT , AtomicOp , ResultShift ) ; SDValue RetOps [ <NUM_LIT> ] = { Result , AtomicOp . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( RetOps , DL ) ;


return Kind == k_VectorIndex && VectorIndex . Val < <NUM_LIT> ;


<s> Parser . addAliasForDirective ( <STR_LIT> , is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ;

if ( is64Bit ( ) ) Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ;


<s> Instruction * Inst = CS . getInstruction ( ) ; Value * Arg = CS . getArgOperand ( I ) ; if ( isa < Constant > ( Arg ) ) continue ; Arg -> replaceUsesWithIf ( Inst , [ & ] ( Use & U ) { return DT -> dominates ( Inst , U ) ; } ) ; }


<s> EVT OrigVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( OrigVT . getSizeInBits ( ) <= OptSize ) { S = Signed ; return true ; } } else if ( Op . getOpcode ( ) == <STR_LIT> ) {


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . hasStdExtV ( ) ) return false ;


<s> case llvm :: ADDRESS_SPACE_LOCAL : return <STR_LIT> :: LOCAL ; case llvm :: ADDRESS_SPACE_GLOBAL : return <STR_LIT> :: GLOBAL ; case llvm :: ADDRESS_SPACE_SHARED : return <STR_LIT> :: SHARED ; case llvm :: ADDRESS_SPACE_GENERIC : return <STR_LIT> :: GENERIC ; case llvm :: ADDRESS_SPACE_PARAM : return <STR_LIT> :: PARAM ; case llvm :: ADDRESS_SPACE_CONST : return <STR_LIT> :: CONSTANT ; default : break ; }


<s> if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand & OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand & OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> return llvm :: make_unique < <ISA_LIT>WasmObjectWriter > ( Is64Bit ) ;


<s> const <ISA_LIT>MachineFunction * MFI = MF -> getInfo < <ISA_LIT>MachineFunction > ( ) ; if ( ! MFI -> isEntryFunction ( ) ) return ; const <ISA_LIT>Subtarget & STM = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; amd_kernel_code_t KernelCode ; if ( STM . isAmdCodeObjectV2 ( * MF ) ) { getAmdKernelCode ( KernelCode , CurrentProgramInfo , * MF ) ;

getTargetStreamer ( ) -> EmitAMDKernelCodeT ( KernelCode ) ;


<s> HiSmall = DAG . getNode ( <STR_LIT> , DL , VT , HiSmall , Overflow ) ; SDValue LoSmall = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shift ) ; SDValue HiBig = DAG . getNode ( <STR_LIT> , DL , VT , Lo , BigShift ) ; SDValue LoBig = Zero ; Hi = DAG . getSelectCC ( DL , Shift , Width , HiSmall , HiBig , <STR_LIT> ) ; Lo = DAG . getSelectCC ( DL , Shift , Width , LoSmall , LoBig , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , VT ) , Lo , Hi ) ;


<s> DCI . CombineTo ( OrigOp . getNode ( ) , DAG . getNode ( Opcode , DL , VT , Op0 , Op1 , Op2 ) ) ; return true ; } ; unsigned Opcode = Op . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : { if ( EltVT . getSizeInBits ( ) != <NUM_LIT> && EltVT . getSizeInBits ( ) != <NUM_LIT> ) return false ; if ( VT . isInteger ( ) != Op . getSimpleValueType ( ) . isInteger ( ) ) return false ; return BitcastAndCombineShuffle ( Opcode , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; }


<s> tmp = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = tmp ; } output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; break ; case <NUM_LIT> : if ( REGNO ( operands [ <NUM_LIT> ] ) > REGNO ( operands [ <NUM_LIT> ] ) ) { tmp = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = tmp ; } if ( REGNO ( operands [ <NUM_LIT> ] ) > REGNO ( operands [ <NUM_LIT> ] ) ) { tmp = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = tmp ; } if ( REGNO ( operands [ <NUM_LIT> ] ) > REGNO ( operands [ <NUM_LIT> ] ) ) { tmp = operands [ <NUM_LIT> ] ;


__builtin_ia32_pmovsdb128mem_mask ( ( unsigned int * ) __P , ( __v4si ) __A , __M ) ;


<s> if ( ! VCTPs . empty ( ) ) { dbgs ( ) << <STR_LIT> ; for ( auto * MI : VCTPs ) dbgs ( ) << <STR_LIT> << * MI ; } if ( ! FoundAllComponents ( ) ) dbgs ( ) << <STR_LIT> ;

else if ( ! ( Start && Dec && End ) ) dbgs ( ) << <STR_LIT> ;


<s> unsigned & CondReg = CondRegs [ Cond ] ; if ( ! CondReg ) CondReg = promoteCondToReg ( TestMBB , TestPos , TestLoc , Cond ) ; if ( ! SetCCI . mayStore ( ) ) { assert ( SetCCI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; MRI -> replaceRegWith ( SetCCI . getOperand ( <NUM_LIT> ) . getReg ( ) , CondReg ) ; SetCCI . eraseFromParent ( ) ; return ; } auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ;

for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( SetCCI . getOperand ( i ) ) ;


<s> return parseSetReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoReorderDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetMacroDirective ( ) ; } else if ( Tok . getString ( ) == <STR_LIT> ) { return parseSetNoMacroDirective ( ) ;


<s> bool <ISA_LIT>AsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { unsigned Kind = Fixup . getKind ( ) ;

if ( Kind >= FirstLiteralRelocationKind ) return true ;


<s> if ( strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) emitVirtualRegister ( MO . getReg ( ) , true , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } return ; case MachineOperand :: MO_Immediate : if ( ! Modifier ) O << MO . getImm ( ) ; else if ( strstr ( Modifier , <STR_LIT> ) == Modifier ) printVecModifiedImmediate ( MO , Modifier , O ) ; else llvm_unreachable ( <STR_LIT> ) ; return ; case MachineOperand :: MO_FPImmediate : printFPConstant ( MO . getFPImm ( ) , O ) ; break ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ;

case MachineOperand :: MO_ExternalSymbol : {


<s> return ( vector signed char ) __builtin_altivec_vcmpequb ( ( vector signed char ) a1 , ( vector signed char ) a2 ) ;


<s> return true ; case DX_REG : return ( ! TARGET_64BIT || ix86_cfun_abi ( ) != MS_ABI ) ; case DI_REG : case SI_REG : return TARGET_64BIT && ix86_cfun_abi ( ) != MS_ABI ;


<s> if ( LdSt . getNumExplicitOperands ( ) != <NUM_LIT> ) return false ; if ( ! LdSt . getOperand ( <NUM_LIT> ) . isImm ( ) || ! LdSt . getOperand ( <NUM_LIT> ) . isReg ( ) ) return false ; if ( ! LdSt . hasOneMemOperand ( ) ) return false ; Width = ( * LdSt . memoperands_begin ( ) ) -> getSize ( ) ; Offset = LdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; BaseReg = & LdSt . getOperand ( <NUM_LIT> ) ;


<s> return ( GET_CODE ( base ) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( base ) && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( get_pool_constant ( base ) , Pmode ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , Options . MCOptions , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , getEffectiveCodeModel ( TT , CM , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ;


<s> tree type = NULL_TREE ; if ( ( qualifiers & qualifier_pointer ) && VECTOR_MODE_P ( mode ) ) mode = GET_MODE_INNER ( mode ) ; if ( ( qualifiers & qualifier_poly ) || VECTOR_MODE_P ( mode ) ) type = aarch64_lookup_simd_type_in_table ( mode , qualifiers ) ; else type = aarch64_int_or_fp_type ( mode , qualifiers ) ; gcc_assert ( type != NULL_TREE ) ;

if ( qualifiers & qualifier_const ) type = build_qualified_type ( type , TYPE_QUAL_CONST ) ;


<s> EVT PtrVT = getPointerTy ( ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; if ( model == TLSModel :: GeneralDynamic || model == TLSModel :: LocalDynamic ) { unsigned HiTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI22 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_HI22 ) ; unsigned LoTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_LO10 : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_LO10 ) ; unsigned addTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_ADD : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_ADD ) ; unsigned callTF = ( ( model == TLSModel :: GeneralDynamic ) ? <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_CALL : <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDM_CALL ) ; SDValue HiLo = makeHiLoPair ( Op , HiTF , LoTF , DAG ) ; SDValue Base = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; SDValue Argument = DAG . getNode ( <STR_LIT> , DL , PtrVT , Base , HiLo , withTargetFlags ( Op , addTF , DAG ) ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue InFlag ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Argument , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Callee = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT ) ; SDValue Symbol = withTargetFlags ( Op , callTF , DAG ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; Ops . push_back ( Symbol ) ; Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , InFlag , DL ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDValue Ret = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , PtrVT , InFlag ) ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_HIX22 , DAG ) ) ;

SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , withTargetFlags ( Op , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_LDO_LOX10 , DAG ) ) ;


<s> case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; break ; } case MCExpr :: Unary : fixELFSymbolsInTLSFixupsImpl ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ;


<s> virtual void getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < <ISA_LIT>SPReduce > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> struct scratch_reg sr ; get_scratch_register_on_entry ( & sr ) ; rounded_size = ROUND_DOWN ( size , get_probe_interval ( ) ) ; emit_move_insn ( sr . reg , GEN_INT ( - first ) ) ; last = first + rounded_size ; emit_insn ( ix86_gen_probe_stack_range ( sr . reg , sr . reg , GEN_INT ( - last ) ) ) ; if ( size != rounded_size ) emit_stack_probe ( plus_constant ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , sr . reg ) , rounded_size - size ) ) ; release_scratch_register_on_entry ( & sr , size , true ) ;


<s> if ( ! def_link || ! def_link -> ref || DF_REF_IS_ARTIFICIAL ( def_link -> ref ) || def_link -> next ) return false ; rtx def_insn = DF_REF_INSN ( def_link -> ref ) ; unsigned uid2 = INSN_UID ( def_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || insn_entry [ uid2 ] . is_load || insn_entry [ uid2 ] . is_store ) return false ; break ; } rtx set = single_set ( insn ) ; if ( set ) { rtx dest = SET_DEST ( set ) ; if ( MEM_P ( dest ) ) return ( MEM_ALIGN ( dest ) >= <NUM_LIT> ) ; }


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , ST ( ST ) , AMDGPUA<ISA_LIT> ( ST . get<ISA_LIT>AS ( ) ) {


<s> int getOperandLatency ( const InstrItineraryData * ItinData , SDNode * DefNode , unsigned DefIdx , SDNode * UseNode , unsigned UseIdx ) const override {

return <ISA_LIT>GenInstrInfo :: getOperandLatency ( ItinData , DefNode , DefIdx , UseNode , UseIdx ) ;


<s> if ( SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return ZExt ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DL , DAG ) ) ;

if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ;


<s> for ( auto & MO : make_range ( MI . operands_begin ( ) + <NUM_LIT> , MI . operands_end ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) MCI . addOperand ( MaybeOperand . getValue ( ) ) ; SmallString < <NUM_LIT> > Code ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; raw_svector_ostream VecOS ( Code ) ; CodeEmitter -> encodeInstruction ( MCI , VecOS , Fixups , getSubtargetInfo ( ) ) ; if ( Code . size ( ) < MinSize ) { if ( MinSize == <NUM_LIT> && Opcode == <STR_LIT> ) { MCI . setOpcode ( <STR_LIT> ) ; } else { unsigned NopSize = EmitNop ( * OutStreamer , MinSize , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; assert ( NopSize == MinSize && <STR_LIT> ) ;


<s> merge_hi_p = false ; break ; } if ( ! merge_hi_p ) { for ( int telt = <NUM_LIT> ; telt < d . nelt ; telt ++ ) if ( d . perm [ telt ] != ( telt + d . nelt ) / <NUM_LIT> + ( telt % <NUM_LIT> ) * d . nelt ) { merge_lo_p = false ; break ; }


<s> auto & TRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; bool Changed = false ; assert ( ! mustPreserveAnalysisID ( LiveIntervalsID ) && <STR_LIT> ) ; for ( unsigned PReg = <STR_LIT> + <NUM_LIT> ; PReg < <STR_LIT> ; ++ PReg ) { if ( PReg == <STR_LIT> || PReg == <STR_LIT> ) continue ; const TargetRegisterClass * RC = TRI . getMinimalPhysRegClass ( PReg ) ; unsigned VReg = <STR_LIT> ; for ( MachineOperand & MO : llvm :: make_early_inc_range ( MRI . reg_operands ( PReg ) ) ) { if ( ! MO . isImplicit ( ) ) { if ( VReg == <STR_LIT> ) {

VReg = MRI . createVirtualRegister ( RC ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerNaClTargetArch ( SDValue Op , SelectionDAG & DAG ) const {

return DAG . getConstant ( PnaclTargetArchitecture<ISA_LIT>_32 , Op . getValueType ( ) . getSimpleVT ( ) ) ;


<s> const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = getSplitDestVTs ( VT , DAG ) ; std :: tie ( LoMemVT , HiMemVT ) = getSplitDestVTs ( MemVT , DAG ) ; std :: tie ( Lo , Hi ) = splitVector ( Op , SL , LoVT , HiVT , DAG ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , Size ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , HiAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ;

auto IdxTy = getVectorIdxTy ( DAG . getDataLayout ( ) ) ;


<s> } } else { i = from . position ( StackVreg ( * Preserved ) ) ; } if ( numPops ) -- numPops ; if ( i != j ) { if ( i == <NUM_LIT> ) { rv ( curStack += rv ( xchgTop ( j ) ) ) ; } else if ( j == <NUM_LIT> ) { rv ( curStack += rv ( xchgTop ( i ) ) ) ; } else if ( i <= XchgLimit && j <= XchgLimit ) { rv ( curStack += rv ( xchg ( i , j ) ) ) ; } else { rv ( curStack += rv ( xchgTop ( i ) ) ) ; rv ( curStack += rv ( xchgTop ( j ) ) ) ; rv ( curStack += rv ( xchgTop ( i ) ) ) ; } }


<s> static void nvptx_init_axis_predicate ( FILE * file , int regno , const char * name ) { fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , name ) ; fprintf ( file , <STR_LIT> , name , name ) ; fprintf ( file , <STR_LIT> , regno , name ) ; fprintf ( file , <STR_LIT> ) ;


<s> int bs = HOST_BITS_PER_WIDE_INT ; bool b ; gcc_assert ( ! ! start == ! ! end ) ; if ( ( in & ( ( ~ HOST_WIDE_INT_0U ) >> ( bs - size ) ) ) == <NUM_LIT> ) return false ; b = s390_contiguous_bitmask_nowrap_p ( in , size , start , end ) ; if ( b ) return true ; if ( ! wrap_p ) return false ; b = s390_contiguous_bitmask_nowrap_p ( ~ in , size , start , end ) ; if ( b && start ) { int s = * start ; int e = * end ; gcc_assert ( s >= <NUM_LIT> ) ; * start = ( ( e + <NUM_LIT> ) & ( bs - <NUM_LIT> ) ) ; * end = ( ( s - <NUM_LIT> + bs ) & ( bs - <NUM_LIT> ) ) ; } return b ;


<s> <ISA_LIT>InstPrinter :: <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) , ControlFlowCounter ( <NUM_LIT> ) {


<s> if ( isa < ConstantSDNode > ( Lo ) && isa < ConstantSDNode > ( Hi ) ) { int32_t LoC = cast < ConstantSDNode > ( Lo ) -> getSExtValue ( ) ; int32_t HiC = cast < ConstantSDNode > ( Hi ) -> getSExtValue ( ) ;

if ( ( LoC >> <NUM_LIT> ) == HiC ) return DAG . getNode ( <STR_LIT> , DL , VT , Passthru , Lo , VL ) ;


<s> unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MI -> setDesc ( Desc ) ; MachineInstrBuilder ( MI ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ;

assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Reg && <STR_LIT> ) ;


<s> static inline int getT2SOImmValSplatVal ( unsigned V ) { unsigned u , Vs , Imm ; if ( ( V & <NUM_LIT> ) == <NUM_LIT> ) return V ;

Vs = ( ( V & <NUM_LIT> ) == <NUM_LIT> ) ? V >> <NUM_LIT> : V ;


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) , Lowering ( * TM . getTargetLowering ( ) ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; } } } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && isa < ConstantSDNode > ( RHS ) ) { if ( ( cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) >> <NUM_LIT> == <NUM_LIT> ) && isa < LoadSDNode > ( LHS ) ) { if ( cast < LoadSDNode > ( LHS ) -> getExtensionType ( ) == <STR_LIT> && cast < LoadSDNode > ( LHS ) -> getMemoryVT ( ) == <STR_LIT> && LHS . getNode ( ) -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) { int16_t ValueofRHS = cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ; if ( ValueofRHS < <NUM_LIT> && isLegalArithImmed ( - ValueofRHS ) ) { SDValue SExt = DAG . getNode ( <STR_LIT> , dl , LHS . getValueType ( ) , LHS , DAG . getValueType ( <STR_LIT> ) ) ; Cmp = emitComparison ( SExt , DAG . getConstant ( ValueofRHS , RHS . getValueType ( ) ) , CC , dl , DAG ) ; <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ; <ISA_LIT>cc = DAG . getConstant ( <ISA_LIT>CC , <STR_LIT> ) ; return Cmp ; } } } } Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <ISA_LIT>CC = changeIntCCTo<ISA_LIT>CC ( CC ) ;


<s> bool AMDGPUDAGToDAGISel :: isLocalStore ( const StoreSDNode * N ) {

return checkType ( N -> getSrcValue ( ) , <STR_LIT> ) ;


<s> if ( E ) EVal = <ISA_LIT>MCExpr :: Create ( Variant , E , false , getParser ( ) . getContext ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isADDIInstrEligibleForFolding ( MachineInstr & ADDIMI , int64_t & Imm ) const { unsigned Opc = ADDIMI . getOpcode ( ) ;

if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ;


<s> bool ProfitableArch = Subtarget -> isCortexA57 ( ) || Subtarget -> isKryo ( ) ;

return ProfitableArch && ! Subtarget -> requiresStrictAlign ( ) ;


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>64LETarget , create<ISA_LIT>LEDisassembler ) ;


<s> rtx xplus0 = XEXP ( xinsn , <NUM_LIT> ) ; rtx xplus1 = XEXP ( xinsn , <NUM_LIT> ) ; enum rtx_code code0 = GET_CODE ( xplus0 ) ; enum rtx_code code1 = GET_CODE ( xplus1 ) ; if ( code0 != REG && code1 == REG ) { xplus0 = XEXP ( xinsn , <NUM_LIT> ) ; xplus1 = XEXP ( xinsn , <NUM_LIT> ) ; code0 = GET_CODE ( xplus0 ) ;


<s> addRegisterClass ( VT , <STR_LIT> ) ;

addTypeForNEON ( VT , <STR_LIT> , <STR_LIT> ) ;


<s> if ( ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ) || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ;

unsigned BasePtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregoiv2di ( __o , <NUM_LIT> ) ; return ret ;


<s> if ( ! I -> isBranch ( ) ) break ; if ( ! getBranchInfo ( * I ) . Target -> isMBB ( ) ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; }


<s> void <ISA_LIT>AsmParser :: errorExpTgt ( ) {

Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ;


<s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ;


<s> else ca -> call_cookie |= CALL_COOKIE_STACKSEQ ( numregs ) ; } } if ( GET_SH_ARG_CLASS ( mode2 ) == SH_ARG_FLOAT && ( named || ! ca -> prototype_p ) ) { if ( mode2 == SFmode && ca -> free_single_fp_reg ) ca -> free_single_fp_reg = <NUM_LIT> ; else if ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) { int numfpregs = MIN ( ( GET_MODE_SIZE ( mode2 ) + <NUM_LIT> ) / <NUM_LIT> * <NUM_LIT> , NPARM_REGS ( SFmode ) - ca -> arg_count [ ( int ) SH_ARG_FLOAT ] ) ; ca -> arg_count [ ( int ) SH_ARG_FLOAT ] += numfpregs ; if ( TARGET_SHCOMPACT && ! ca -> prototype_p ) { if ( ca -> outgoing && numregs > <NUM_LIT> ) do { ca -> call_cookie |= ( CALL_COOKIE_INT_REG ( ca -> arg_count [ ( int ) SH_ARG_INT ] - numregs + ( ( numfpregs - <NUM_LIT> ) / <NUM_LIT> ) , <NUM_LIT> + ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] - numfpregs ) / <NUM_LIT> ) ) ; } while ( numfpregs -= <NUM_LIT> ) ; } else if ( mode2 == SFmode && ( named ) && ( ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) ) ca -> free_single_fp_reg = FIRST_FP_PARM_REG - numfpregs + ca -> arg_count [ ( int ) SH_ARG_FLOAT ] + <NUM_LIT> ; } } return ; } if ( ( TARGET_HITACHI || ca -> renesas_abi ) && TARGET_FPU_DOUBLE ) { if ( mode == SFmode && ca -> free_single_fp_reg ) { ca -> free_single_fp_reg = <NUM_LIT> ;


<s> if ( <STR_LIT> . contains ( Reg ) ) Index = Reg - <STR_LIT> ; else if ( <STR_LIT> . contains ( Reg ) ) Index = Reg - <STR_LIT> ; else if ( <STR_LIT> . contains ( Reg ) ) Index = Reg - <STR_LIT> ; else return true ; switch ( Mode ) { default : return true ; case 'x' : Reg = <STR_LIT> + Index ; break ; case 't' : Reg = <STR_LIT> + Index ; break ; case 'g' : Reg = <STR_LIT> + Index ; break ; } if ( EmitPercent ) O << '%' ; O << <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ;


<s> if ( ( MEM_P ( src1 ) || bcst_mem_operand ( src1 , mode ) ) && ( MEM_P ( src2 ) || bcst_mem_operand ( src2 , mode ) ) ) return false ; if ( ix86_swap_binary_operands_p ( code , mode , operands ) ) std :: swap ( src1 , src2 ) ;

if ( MEM_P ( dst ) && ! rtx_equal_p ( dst , src1 ) ) return false ;


<s> auto * F = dyn_cast < Function > ( GV ) ; if ( UseNonLazyBind && F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) return <STR_LIT> ;


<s> case Instruction :: Mul : return selectMul ( I ) ; case Instruction :: SDiv : return selectSDiv ( I ) ; case Instruction :: SRem : if ( ! selectBinaryOp ( I , <STR_LIT> ) ) return selectRem ( I , <STR_LIT> ) ; return true ; case Instruction :: URem : if ( ! selectBinaryOp ( I , <STR_LIT> ) ) return selectRem ( I , <STR_LIT> ) ; return true ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : return selectShift ( I ) ; case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : return selectLogicalOp ( I ) ; case Instruction :: Br : return selectBranch ( I ) ; case Instruction :: IndirectBr : return selectIndirectBr ( I ) ; case Instruction :: BitCast : if ( ! FastISel :: selectBitCast ( I ) ) return selectBitCast ( I ) ; return true ; case Instruction :: FPToSI : if ( ! selectCast ( I , <STR_LIT> ) ) return selectFPToInt ( I , true ) ; return true ; case Instruction :: FPToUI : return selectFPToInt ( I , false ) ; case Instruction :: ZExt : case Instruction :: SExt : return selectIntExt ( I ) ; case Instruction :: Trunc : if ( ! selectCast ( I , <STR_LIT> ) ) return selectTrunc ( I ) ; return true ; case Instruction :: FPExt : return selectFPExt ( I ) ; case Instruction :: FPTrunc : return selectFPTrunc ( I ) ; case Instruction :: SIToFP : if ( ! selectCast ( I , <STR_LIT> ) ) return selectIntToFP ( I , true ) ; return true ; case Instruction :: UIToFP : return selectIntToFP ( I , false ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: FCmp : case Instruction :: ICmp : return selectCmp ( I ) ; case Instruction :: Select : return selectSelect ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: FRem : return selectFRem ( I ) ; case Instruction :: GetElementPtr :


<s> return ( __m128 ) __builtin_ia32_loadss ( __P ) ;


<s> if ( ! Subtarget -> hasSVE ( ) || DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT OpVT = N0 . getValueType ( ) ; if ( ! OpVT . isScalableVector ( ) || OpVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; if ( Idx . getOpcode ( ) != <STR_LIT> || ! isAllOnesConstant ( Idx . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue VS = Idx . getOperand ( <NUM_LIT> ) ; if ( VS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned NumEls = OpVT . getVectorElementCount ( ) . getKnownMinValue ( ) ; if ( VS . getConstantOperandVal ( <NUM_LIT> ) != NumEls ) return SDValue ( ) ;


<s> return ; } bool Was16 = isCode16 ( StartInfo . getTargetTriple ( ) ) ;

if ( ! EndInfo || Was16 != isCode16 ( EndInfo -> getTargetTriple ( ) ) ) {


<s> ResourcesModel -> clearResources ( ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS , TT . isArch64Bit ( ) ) ) , InstrInfo ( ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {


<s> int result = findInRangeCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; unsigned ID = AFI -> createPICLabelUId ( ) ; MachineBasicBlock * NewIsland = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . count ( WaterBB ) ) { NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } NewMBB = llvm :: next ( MachineFunction :: iterator ( WaterBB ) ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = prior ( MachineFunction :: iterator ( NewMBB ) ) ;

IP = std :: find ( WaterList . begin ( ) , WaterList . end ( ) , WaterBB ) ;


<s> rtx next = DEP_CON ( dep ) ; if ( next == next_insn && rs6000_is_costly_dependence ( dep , dep_cost ( dep ) , <NUM_LIT> ) ) return true ;


<s> bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ;


<s> unsigned getNumFixupKinds ( ) const override {


<s> break ; case MachineOperand :: MO_GlobalAddress : Symbol = Printer . getSymbol ( MO . getGlobal ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const unsigned Option = MO . getTargetFlags ( ) & <STR_LIT> ; MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; switch ( Option ) { default : break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_HI ;


<s> if ( J -> readsRegister ( CopyFromExec , TRI ) ) { SaveExecInst = & * J ; DEBUG ( dbgs ( ) << <STR_LIT> << * SaveExecInst << '\n' ) ; continue ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << * J << '\n' ) ; break ; } } if ( SaveExecInst && J -> readsRegister ( CopyToExec , TRI ) ) { assert ( SaveExecInst != & * J ) ; OtherUseInsts . push_back ( & * J ) ; } } if ( ! SaveExecInst ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * SaveExecInst << '\n' ) ; MachineOperand & Src0 = SaveExecInst -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = SaveExecInst -> getOperand ( <NUM_LIT> ) ; MachineOperand * OtherOp = nullptr ; if ( Src0 . isReg ( ) && Src0 . getReg ( ) == CopyFromExec ) { OtherOp = & Src1 ; } else if ( Src1 . isReg ( ) && Src1 . getReg ( ) == CopyFromExec ) { if ( ! SaveExecInst -> isCommutable ( ) ) break ; OtherOp = & Src0 ; } else llvm_unreachable ( <STR_LIT> ) ; CopyFromExecInst -> eraseFromParent ( ) ; auto InsPt = SaveExecInst -> getIterator ( ) ; const DebugLoc & DL = SaveExecInst -> getDebugLoc ( ) ; BuildMI ( MBB , InsPt , DL , TII -> get ( getSaveExecOp ( SaveExecInst -> getOpcode ( ) ) ) , CopyFromExec ) . addReg ( OtherOp -> getReg ( ) ) ;


<s> static rtx pa_trampoline_adjust_address ( rtx addr ) { if ( ! TARGET_64BIT ) addr = memory_address ( Pmode , plus_constant ( Pmode , addr , <NUM_LIT> ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLVP ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_TLVP , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_SECREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSGD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLD ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TLSLDM ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_INDNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_TPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_DTPOFF ; break ;

case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_NTPOFF ; break ;


<s> BasicBlock * Parent = Phi -> getParent ( ) ; PHINode * NewPhi = PHINode :: Create ( Int64 , <NUM_LIT> , <STR_LIT> , & Parent -> front ( ) ) ; Value * Ret = NewPhi ; for ( unsigned i = <NUM_LIT> , e = Phi -> getNumIncomingValues ( ) ; i != e ; ++ i ) { Value * Incoming = Phi -> getIncomingValue ( i ) ; BasicBlock * From = Phi -> getIncomingBlock ( i ) ; if ( isa < ConstantInt > ( Incoming ) ) { NewPhi -> addIncoming ( Broken , From ) ; continue ; } Phi -> setIncomingValue ( i , BoolFalse ) ; Value * PhiArg = handleLoopCondition ( Incoming , Broken , L , Term ) ; NewPhi -> addIncoming ( PhiArg , From ) ; } BasicBlock * IDom = DT -> getNode ( Parent ) -> getIDom ( ) -> getBlock ( ) ; for ( unsigned i = <NUM_LIT> , e = Phi -> getNumIncomingValues ( ) ; i != e ; ++ i ) { Value * Incoming = Phi -> getIncomingValue ( i ) ; if ( Incoming != BoolTrue ) continue ; BasicBlock * From = Phi -> getIncomingBlock ( i ) ; if ( From == IDom ) { CallInst * OldEnd = dyn_cast < CallInst > ( Parent -> getFirstInsertionPt ( ) ) ; while ( OldEnd && OldEnd -> getCalledFunction ( ) != EndCf ) OldEnd = dyn_cast < CallInst > ( OldEnd -> getNextNode ( ) ) ; if ( OldEnd && OldEnd -> getCalledFunction ( ) == EndCf ) { Value * Args [ ] = { OldEnd -> getArgOperand ( <NUM_LIT> ) , NewPhi } ; Ret = CallInst :: Create ( ElseBreak , Args , <STR_LIT> , OldEnd ) ; continue ; } } TerminatorInst * Insert = From -> getTerminator ( ) ; Value * PhiArg = CallInst :: Create ( Break , Broken , <STR_LIT> , Insert ) ;

NewPhi -> setIncomingValue ( i , PhiArg ) ;


<s> sub = gen_rtx_SET ( VOIDmode , w_dest , gen_rtx_MINUS ( HImode , sub_1 , w_src1 ) ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , carry ) ; branch = gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( HImode , sub_1 , w_src1 ) , pc_rtx , pc_rtx ) ) ; insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , branch , sub , clobber ) ) ; } else if ( firstloop && code != COMPARE && GET_CODE ( w_src1 ) == CONST_INT && INTVAL ( w_src1 ) == <NUM_LIT> ) continue ; else if ( firstloop ) insn = gen_subchi4 ( w_dest , w_src0 , w_src1 , carry ) ; else insn = gen_subchi5 ( w_dest , w_src0 , w_src1 , carry , carry ) ; break ; case IOR : case XOR :


<s> bool useScalarIncVL ( ) const { return UseScalarIncVL ;


<s> void <ISA_LIT>BankConflictHazardRecognizer :: Reset ( ) { Accesses . clear ( ) ;


<s> if ( ! GEP ) { if ( ! canVectorizeInst ( cast < Instruction > ( AllocaUser ) , Alloca ) ) return false ; WorkList . push_back ( AllocaUser ) ; continue ; } Value * Index = GEPToVectorIndex ( GEP ) ; if ( ! Index ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * GEP << '\n' ) ; return false ; } GEPVectorIdx [ GEP ] = Index ; for ( User * GEPUser : AllocaUser -> users ( ) ) { if ( ! canVectorizeInst ( cast < Instruction > ( GEPUser ) , AllocaUser ) ) return false ; WorkList . push_back ( GEPUser ) ; } } VectorType * VectorTy = arrayTypeToVecType ( AllocaTy ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * AllocaTy << <STR_LIT> << * VectorTy << '\n' ) ; for ( Value * V : WorkList ) { Instruction * Inst = cast < Instruction > ( V ) ; IRBuilder < > Builder ( Inst ) ; switch ( Inst -> getOpcode ( ) ) { case Instruction :: Load : { Type * VecPtrTy = VectorTy -> getPointerTo ( <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; Value * Ptr = cast < LoadInst > ( Inst ) -> getPointerOperand ( ) ; Value * Index = calculateVectorIndex ( Ptr , GEPVectorIdx ) ; Value * BitCast = Builder . CreateBitCast ( Alloca , VecPtrTy ) ; Value * VecValue = Builder . CreateLoad ( BitCast ) ; Value * ExtractElement = Builder . CreateExtractElement ( VecValue , Index ) ; Inst -> replaceAllUsesWith ( ExtractElement ) ; Inst -> eraseFromParent ( ) ; break ; } case Instruction :: Store : { Type * VecPtrTy = VectorTy -> getPointerTo ( <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; StoreInst * <ISA_LIT> = cast < StoreInst > ( Inst ) ; Value * Ptr = <ISA_LIT> -> getPointerOperand ( ) ; Value * Index = calculateVectorIndex ( Ptr , GEPVectorIdx ) ; Value * BitCast = Builder . CreateBitCast ( Alloca , VecPtrTy ) ; Value * VecValue = Builder . CreateLoad ( BitCast ) ; Value * NewVecValue = Builder . CreateInsertElement ( VecValue , <ISA_LIT> -> getValueOperand ( ) , Index ) ; Builder . CreateStore ( NewVecValue , BitCast ) ; Inst -> eraseFromParent ( ) ; break ; } case Instruction :: BitCast : case Instruction :: AddrSpaceCast : break ; default :


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InGlue , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , SDLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { assert ( ! isVarArg && <STR_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ;

CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ;


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveFRegPX ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSetFP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHAddFP ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHNop ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHSaveNext ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHEpilogStart ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHEpilogEnd ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHTrapFrame ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHMachineFrame ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHContext ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSEHClearUnwoundToCall ( Loc ) ; else return true ; } else return true ;


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ; return new <ISA_LIT>MCAsmBackend ( OSABI ) ;


<s> const Value * Callee = CLI . Callee ; MCSymbol * Symbol = CLI . Symbol ; if ( CC == CallingConv :: Fast ) return false ; if ( IsTailCall ) return false ; if ( IsVarArg ) return false ; MVT RetVT ; if ( CLI . RetTy -> isVoidTy ( ) ) RetVT = <STR_LIT> ; else if ( ! isTypeSupported ( CLI . RetTy , RetVT ) ) return false ; for ( auto Flag : CLI . OutFlags ) if ( Flag . isInReg ( ) || Flag . isSRet ( ) || Flag . isNest ( ) || Flag . isByVal ( ) ) return false ; SmallVector < MVT , <NUM_LIT> > OutVTs ; OutVTs . reserve ( CLI . OutVals . size ( ) ) ; for ( auto * Val : CLI . OutVals ) { MVT VT ; if ( ! isTypeLegal ( Val -> getType ( ) , VT ) && ! ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return false ; if ( VT . isVector ( ) || VT . getSizeInBits ( ) > <NUM_LIT> ) return false ; OutVTs . push_back ( VT ) ; } Address Addr ; if ( ! computeCallAddress ( Callee , Addr ) ) return false ; unsigned NumBytes ; if ( ! processCallArgs ( CLI , OutVTs , NumBytes ) ) return false ; if ( ! Addr . getGlobalValue ( ) ) return false ; unsigned DestAddress ; if ( Symbol ) DestAddress = materializeExternalCallSym ( Symbol ) ; else DestAddress = materializeGV ( Addr . getGlobalValue ( ) , <STR_LIT> ) ; emitInst ( TargetOpcode :: COPY , <STR_LIT> ) . addReg ( DestAddress ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; for ( auto Reg : CLI . OutRegs ) MIB . addReg ( Reg , RegState :: Implicit ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( * FuncInfo . MF , CC ) ) ; CLI . Call = MIB ;

return finishCall ( CLI , RetVT , NumBytes ) ;


<s> vrev64q_s32 ( int32x4_t a ) { return __builtin_shuffle ( a , ( uint32x4_t ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ;


<s> if ( Thumb2PreloadOpcodeNoPCI ( Opcode ) && slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) Opcode = T2Morph2Preload2PCI ( Opcode ) ; <ISA_LIT>Format Format = <ISA_LIT>Formats [ Opcode ] ; Size = IsThumb2 ? <NUM_LIT> : <NUM_LIT> ; DEBUG ( { errs ( ) << <STR_LIT> << Opcode << <STR_LIT> << <STR_LIT> ( Opcode ) << <STR_LIT> << stringFor<ISA_LIT>Format ( Format ) << '(' << ( int ) Format << <STR_LIT> ; showBitVector ( errs ( ) , insn ) ; } ) ; <ISA_LIT>BasicMCBuilder * Builder = CreateMCBuilder ( Opcode , Format ) ; Builder -> SetSession ( const_cast < Session * > ( & SO ) ) ; if ( ! Builder ) return false ;

if ( ! Builder -> Build ( MI , insn ) ) return false ;


<s> SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , MemVT , NewLD ) , NewLD . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; } if ( ! MemVT . isVector ( ) ) return SDValue ( ) ; assert ( Op . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned AS = Load -> getAddressSpace ( ) ; if ( ! allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , MemVT , AS , Load -> getAlignment ( ) ) ) { SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = expandUnalignedLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , DL ) ; } unsigned NumElements = MemVT . getVectorNumElements ( ) ; switch ( AS ) { case <ISA_LIT>AS :: CONSTANT_ADDRESS : if ( isMemOpUniform ( Load ) ) return SDValue ( ) ; case <ISA_LIT>AS :: GLOBAL_ADDRESS : case <ISA_LIT>AS :: FLAT_ADDRESS : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; case <ISA_LIT>AS :: PRIVATE_ADDRESS : { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorLoad ( Load , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorLoad ( Op , DAG ) ; return SDValue ( ) ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> const struct mips_builtin_description * d ; unsigned int i ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( mips_builtins ) ; i ++ ) {


<s> unsigned OpIdx = <NUM_LIT> ; if ( TableEntry -> isUpdating ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) MIB . addOperand ( MI . getOperand ( OpIdx ++ ) ) ; bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ;

if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ;


<s> using namespace PatternMatch ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; auto * Ty = cast < FixedVectorType > ( I -> getType ( ) ) ; Value * Ptr = I -> getArgOperand ( <NUM_LIT> ) ; unsigned Alignment = cast < ConstantInt > ( I -> getArgOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; Value * PassThru = I -> getArgOperand ( <NUM_LIT> ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Instruction * Root = I ; Value * Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = Builder . CreateSelect ( Mask , Load , PassThru ) ; }


<s> assert ( Op . getValueType ( ) == <STR_LIT> ) ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op ) ;


<s> return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> unsigned CmpOp = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MRI . constrainRegClass ( dest , TRCsp ) ; BuildMI ( BB , dl , TII -> get ( CmpOp ) ) . addReg ( dest ) . addReg ( oldval ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( exitMBB ) ; BB -> addSuccessor ( loop2MBB ) ; BB -> addSuccessor ( exitMBB ) ; BB = loop2MBB ; unsigned stxr_status = MRI . createVirtualRegister ( & <STR_LIT> ) ; MRI . constrainRegClass ( stxr_status , & <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( strOpc ) , stxr_status ) . addReg ( newval ) . addReg ( ptr ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( stxr_status ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( loop1MBB ) ;


<s> static <ISA_LIT>Operand * createToken ( StringRef Str , SMLoc Loc ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( KindToken , Loc , Loc ) ;


<s> return new <ISA_LIT>XCOFFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) ;


<s> unsigned char VEX_B = <NUM_LIT> ; unsigned char VEX_W = <NUM_LIT> ; unsigned char XOP = <NUM_LIT> ; unsigned char VEX_5M = <NUM_LIT> ; unsigned char VEX_4V = <NUM_LIT> ; unsigned char VEX_L = <NUM_LIT> ; unsigned char VEX_PP = <NUM_LIT> ; if ( TSFlags & <STR_LIT> ) VEX_PP = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) VEX_W = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) XOP = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) VEX_L = <NUM_LIT> ; switch ( TSFlags & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <NUM_LIT> : break ; } unsigned NumOps = Desc . getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) { assert ( Desc . getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ; CurOp += <NUM_LIT> ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : { if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ;


<s> unsigned Flags1 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) ; ) ; if ( Cond [ <NUM_LIT> ] . isReg ( ) ) { unsigned Flags2 = getUndefRegState ( Cond [ <NUM_LIT> ] . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags2 ) . addMBB ( TBB ) ; } else if ( Cond [ <NUM_LIT> ] . isImm ( ) ) { BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) , Flags1 ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ; } else llvm_unreachable ( <STR_LIT> ) ; } else { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; const MachineOperand & RO = Cond [ <NUM_LIT> ] ; unsigned Flags = getUndefRegState ( RO . isUndef ( ) ) ; BuildMI ( & MBB , DL , get ( BccOpc ) ) . addReg ( RO . getReg ( ) , Flags ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } assert ( ( ! Cond . empty ( ) ) && <STR_LIT> ) ; assert ( ( ! isNewValueJump ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) && <STR_LIT> ) ; if ( isEndLoopN ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) { int EndLoopOp = Cond [ <NUM_LIT> ] . getImm ( ) ; assert ( Cond [ <NUM_LIT> ] . isMBB ( ) ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > VisitedBBs ; MachineInstr * Loop = findLoopInstr ( TBB , EndLoopOp , VisitedBBs ) ; assert ( Loop != <NUM_LIT> && <STR_LIT> ) ;

Loop -> getOperand ( <NUM_LIT> ) . setMBB ( TBB ) ;


<s> SDValue ResNode ; SDValue HiPart ; SDLoc dl ( Op ) ; EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ;

SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <NUM_LIT> ) ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . getOperand ( <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_X ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_Y ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_Z ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MI . getOperand ( getOperandIdx ( MI , <STR_LIT> :: pred_sel_W ) ) . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; return true ; } if ( PIdx != - <NUM_LIT> ) { MachineOperand & PMO = MI . getOperand ( PIdx ) ; PMO . setReg ( Pred [ <NUM_LIT> ] . getReg ( ) ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ;


<s> ) ; const TargetRegisterClass * I32RC = TRI -> getCFGStructurizerRegClass ( <STR_LIT> ) ; if ( ! MigrateTrue || ! MigrateFalse ) { return <NUM_LIT> ; } int NumNewBlk = <NUM_LIT> ; bool LandBlkHasOtherPred = ( LandBlk -> pred_size ( ) > <NUM_LIT> ) ; MachineBasicBlock :: iterator I = insertInstrBefore ( LandBlk , <STR_LIT> ) ; if ( LandBlkHasOtherPred ) { llvm_unreachable ( <STR_LIT> ) ; unsigned CmpResReg = HeadMBB -> getParent ( ) -> getRegInfo ( ) . createVirtualRegister ( I32RC ) ; llvm_unreachable ( <STR_LIT> ) ; insertCondBranchBefore ( LandBlk , I , <STR_LIT> , CmpResReg , DebugLoc ( ) ) ; } unsigned InitReg = HeadMBB -> getParent ( ) -> getRegInfo ( ) . createVirtualRegister ( I32RC ) ; insertCondBranchBefore ( LandBlk , I , <STR_LIT> , InitReg , DebugLoc ( ) ) ; if ( MigrateTrue ) { migrateInstruction ( TrueMBB , LandBlk , I ) ; llvm_unreachable ( <STR_LIT> ) ; } insertInstrBefore ( I , <STR_LIT> ) ; if ( MigrateFalse ) { migrateInstruction ( FalseMBB , LandBlk , I ) ; llvm_unreachable ( <STR_LIT> ) ; } if ( LandBlkHasOtherPred ) { insertInstrBefore ( I , <STR_LIT> ) ;

for ( MachineBasicBlock :: pred_iterator PI = LandBlk -> pred_begin ( ) , PE = LandBlk -> pred_end ( ) ; PI != PE ; ++ PI ) {


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; auto SPReg = MIRBuilder . buildCopy ( p0 , Register ( <STR_LIT> ) ) ; unsigned Offset = VA . getLocMemOffset ( ) ; auto OffsetReg = MIRBuilder . buildConstant ( s32 , Offset ) ; auto AddrReg = MIRBuilder . buildPtrAdd ( p0 , SPReg , OffsetReg ) ; MachinePointerInfo MPO = MachinePointerInfo :: getStack ( MIRBuilder . getMF ( ) , Offset ) ;

unsigned Size = alignTo ( VA . getValVT ( ) . getSizeInBits ( ) , <NUM_LIT> ) / <NUM_LIT> ;


<s> return new <ISA_LIT>AsmBackend ( T , CPU ) ;


<s> if ( ! RASI ) { int LROffset = <ISA_LIT>FrameLowering :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; RASI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , LROffset , true ) ; FI -> setReturnAddrSaveIndex ( RASI ) ;


<s> SmallVector < <ISA_LIT>SamplerHandle * , <NUM_LIT> > getSamplerHandles ( ) { return <ISA_LIT>Samplers ;


<s> if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; if ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return false ; Reg = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ;


<s> MachineInstr * MI = getLoopendBlockBranchInstr ( ContingMBB ) ; if ( MI ) { assert ( isCondBranch ( MI ) ) ; MachineBasicBlock :: iterator I = MI ; MachineBasicBlock * TrueBranch = getTrueBranch ( MI ) ; int OldOpcode = MI -> getOpcode ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; bool UseContinueLogical = ( ( & * ContingMBB -> rbegin ( ) ) == MI ) ; if ( ! UseContinueLogical ) { int BranchOpcode = TrueBranch == ContMBB ? getBranchNzeroOpcode ( OldOpcode ) : getBranchZeroOpcode ( OldOpcode ) ; insertCondBranchBefore ( I , BranchOpcode , DL ) ; insertInstrEnd ( ContingMBB , AMDGPU :: CONTINUE , DL ) ; insertInstrEnd ( ContingMBB , AMDGPU :: ENDIF , DL ) ;


<s> int addVal = <NUM_LIT> ; switch ( offset ) { case <NUM_LIT> : addVal = <NUM_LIT> ; break ; case <NUM_LIT> : addVal = <NUM_LIT> ; break ; case <NUM_LIT> : addVal = <NUM_LIT> ;


<s> SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi , Lo ; SDValue CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops0 [ <NUM_LIT> ] = { Tmp2 , Tmp3 , CC , Cond } ; SDValue Ops1 [ <NUM_LIT> ] = { Tmp3 , Tmp1 , CC , Cond } ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Hi = DAG . getNode ( <STR_LIT> , dl , VT , Ops0 , <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , VT , Ops1 , <NUM_LIT> ) ; } else { Lo = DAG . getNode ( <STR_LIT> , dl , VT , Ops0 , <NUM_LIT> ) ;

Hi = DAG . getNode ( <STR_LIT> , dl , VT , Ops1 , <NUM_LIT> ) ;


<s> unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ;

if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> if ( ! Subtarget . hasVLX ( ) && ! VT . is512BitVector ( ) && ! Index . getSimpleValueType ( ) . is512BitVector ( ) ) { unsigned Factor = std :: min ( <NUM_LIT> / VT . getSizeInBits ( ) , <NUM_LIT> / IndexVT . getSizeInBits ( ) ) ; unsigned NumElts = VT . getVectorNumElements ( ) * Factor ; VT = <STR_LIT> ( VT . getVectorElementType ( ) , NumElts ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , NumElts ) ; MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; Src = ExtendToType ( Src , VT , DAG ) ; Index = ExtendToType ( Index , IndexVT , DAG ) ; Mask = ExtendToType ( Mask , MaskVT , DAG , true ) ; } SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Src , Mask , BasePtr , Index , Scale } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , Ops , N -> getMemoryVT ( ) , N -> getMemOperand ( ) ) ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Ws = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Rt = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const MachineMemOperand & MMO = * * MI . memoperands_begin ( ) ; unsigned Imm = MMO . getOffset ( ) ;

const TargetRegisterClass * RC = MI . getOperand ( <NUM_LIT> ) . isReg ( ) ? RegInfo . getRegClass ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) : ( Subtarget . isABI_O32 ( ) ? & <STR_LIT> : & <STR_LIT> ) ;


<s> if ( ! SRASrc1 || SRASrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ; SDValue Op0 = SignExt . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { SDValue SHL = Op0 ; ConstantSDNode * SHLSrc1 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! SHLSrc1 || SHLSrc1 -> getZExtValue ( ) != <NUM_LIT> ) return false ;

* Opc = Accumulate ? <STR_LIT> : <STR_LIT> ;


<s> case 'x' : case 'w' : return C_RegisterClass ; case 'Q' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'Y' : case 'Z' : return C_Immediate ; case 'z' : case 'S' : return C_Other ; }


<s> SDValue Tmp5 = DAG . getNode ( <STR_LIT> , dl , AmtVT , Amt , DAG . getConstant ( - BitWidth , AmtVT ) ) ; SDValue Tmp6 = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Tmp5 ) ; SDValue OutHi = DAG . getNode ( <STR_LIT> , dl , VT , Tmp4 , Tmp6 ) ; SDValue OutLo = DAG . getNode ( <STR_LIT> , dl , VT , Lo , Amt ) ; SDValue OutOps [ ] = { OutLo , OutHi } ;

return DAG . getMergeValues ( OutOps , <NUM_LIT> , dl ) ;


<s> __vis_alignaddr ( void * __A , long __B ) { return __builtin_vis_alignaddr ( __A , __B ) ;


<s> return Reg != <NUM_LIT> && ! Reg . isStack ( ) && Reg . isVirtual ( ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( nullptr ) , InConstantPool ( false ) , MCInstLowering ( * this ) {

Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> addPass ( create<ISA_LIT>ModeRegisterPass ( ) ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & <ISA_LIT>InsertHardClausesID ) ; addPass ( & <ISA_LIT>LateBranchLoweringPassID ) ;

if ( isPassEnabled ( EnableSetWavePriority , CodeGenOpt :: Less ) ) addPass ( create<ISA_LIT>SetWavePriorityPass ( ) ) ;


<s> bool isNegated ( ) const { return Negated ;


<s> addPass ( create<ISA_LIT>OptimizeLiveIntervals ( ) ) ; addPass ( create<ISA_LIT>MemIntrinsicResults ( ) ) ; addPass ( create<ISA_LIT>RegStackify ( ) ) ; addPass ( create<ISA_LIT>RegColoring ( ) ) ; } addPass ( create<ISA_LIT>ExplicitLocals ( ) ) ; addPass ( create<ISA_LIT>CFGSort ( ) ) ; addPass ( create<ISA_LIT>CFGStackify ( ) ) ; addPass ( create<ISA_LIT>LowerBrUnless ( ) ) ;

if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>Peephole ( ) ) ;


<s> uint8_t Cost = <NUM_LIT> ; switch ( VT . SimpleTy ) { default : return TargetLowering :: findRepresentativeClass ( VT ) ; case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ; break ; } return std :: make_pair ( RRC , Cost ) ;


<s> Value * <ISA_LIT>IREmitter :: visitSMUL ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> ExceptionsType = ExceptionHandling :: None ; UseParensForSymbolVariant = true ; UseIntegratedAssembler = false ; DwarfRegNumForCFI = true ;


<s> int SoImmVal = <STR_LIT> ( SoImm ) ; assert ( SoImmVal != - <NUM_LIT> && <STR_LIT> ) ; unsigned Binary = ( <STR_LIT> ( ( unsigned ) SoImmVal ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= <STR_LIT> ( ( unsigned ) SoImmVal ) ;


<s> BB -> addSuccessor ( SinkMBB ) ; BB = SinkMBB ; BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( ThisMBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Copy0MBB ) ; MI . eraseFromParent ( ) ; return BB ;


<s> if ( X . getValueType ( ) == VT ) return X ; } if ( Op0 . getValueType ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { SDValue BV = Op0 . getOperand ( <NUM_LIT> ) ; unsigned Offset = N -> getConstantOperandVal ( <NUM_LIT> ) ; SDValue MOV = BV . getOperand ( Offset < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( MOV . getOpcode ( ) == <STR_LIT> ) return MOV . getOperand ( ST -> isLittle ( ) ? Offset % <NUM_LIT> : <NUM_LIT> - Offset % <NUM_LIT> ) ; } if ( SDValue R = PerformExtractEltToVMOVRRD ( N , DCI ) ) return R ;


<s> if ( MI . isImplicitDef ( ) ) return false ; const MCInstrDesc & TID = MI . getDesc ( ) ; auto * IS = ResourceTracker -> getInstrItins ( ) -> beginStage ( TID . getSchedClass ( ) ) ; unsigned FuncUnits = IS -> getUnits ( ) ; return ! FuncUnits ;


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const { Streamer . visitUsedExpr ( * getSubExpr ( ) ) ;


<s> return b . IFH1 ( b . HiMask ( <NUM_LIT> , <NUM_LIT> ) , b . XOR ( Tmp , b . SHL < <NUM_LIT> > ( b . AND ( A1 , A2 ) ) ) , Tmp ) ; } llvm_unreachable ( <STR_LIT> ) ;


<s> if ( isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ; int C1Cost = <STR_LIT> ( C1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; int ShiftedC1Cost = <STR_LIT> ( ShiftedC1Int , Ty . getSizeInBits ( ) , Subtarget . is64Bit ( ) ) ; if ( C1Cost < ShiftedC1Cost ) return false ; } }


<s> void <ISA_LIT>TargetMachine :: addAnalysisPasses ( PassManagerBase & PM ) {


<s> for ( unsigned Reg : OutRegs ) { if ( ! Register :: isVirtualRegister ( Reg ) ) continue ; PSetIterator PSetI = DAG -> getMRI ( ) -> getPressureSets ( Reg ) ; for ( ; PSetI . isValid ( ) ; ++ PSetI ) { DiffSetPressure [ * PSetI ] += PSetI . getWeight ( ) ; }


<s> uint64_t Rsrc23 = getDefaultRsrcDataFormat ( ) | <STR_LIT> | <NUM_LIT> ; if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { uint64_t EltSizeValue = Log2_32 ( ST . getMaxPrivateElementSize ( ) ) - <NUM_LIT> ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT . isInteger ( ) && N -> getOpcode ( ) == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 . getOperand ( <NUM_LIT> ) ) if ( ConstantSDNode * Y1C = dyn_cast < ConstantSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) ) if ( Y1C -> getAPIntValue ( ) == VT . getSizeInBits ( ) - <NUM_LIT> ) {

SDValue Neg = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , VT ) , N0 . getOperand ( <NUM_LIT> ) ) ;


<s> isAdd = false ; haveEaten = true ; } SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; int Reg = tryParseRegister ( ) ; if ( Reg == - <NUM_LIT> ) { if ( ! haveEaten ) return MatchOperand_NoMatch ; Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } <STR_LIT> ShiftTy = <STR_LIT> ; unsigned ShiftImm = <NUM_LIT> ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseMemRegOffsetShift ( ShiftTy , ShiftImm ) ) return MatchOperand_ParseFail ; E = Parser . getTok ( ) . getLoc ( ) ; }

Operands . push_back ( <ISA_LIT>Operand :: CreatePostIdxReg ( Reg , isAdd , ShiftTy , ShiftImm , S , E ) ) ;


<s> Reserved . set ( <STR_LIT> ) ; if ( hasFP ( MF ) ) Reserved . set ( <STR_LIT> ) ;


<s> for ( unsigned i = NumElts / <NUM_LIT> ; i != NumElts ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , NumElts / <NUM_LIT> ) ) return false ; return true ;


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < N > ( Value ) && <STR_LIT> ) ;


<s> bool <ISA_LIT>SEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) {

Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ;


<s> void <ISA_LIT>AsmBackend :: relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const {


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {

return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> size_t OpIdx = <NUM_LIT> ; Ops [ OpIdx ++ ] = Op . getOperand ( <NUM_LIT> ) ; Ops [ OpIdx ++ ] = Op . getOperand ( <NUM_LIT> ) ; for ( size_t I = <NUM_LIT> , Lanes = Mask . size ( ) ; I < Lanes ; ++ I ) { for ( size_t J = <NUM_LIT> ; J < LaneBytes ; ++ J ) {

Ops [ OpIdx ++ ] = DAG . getConstant ( ( uint64_t ) Mask [ I ] * LaneBytes + J , DL , <STR_LIT> ) ;


<s> RawPrinter -> printRegName ( O , RegNo ) ;


<s> if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ; } else if ( VT == <STR_LIT> ) { if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return Op ; }


<s> Rd |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rm |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned size = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> void Initialize ( MCContext & ctx , const TargetMachine & TM ) override {

TargetLoweringObjectFile :: Initialize ( ctx , TM ) ;


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetGlobalAddressSymbol ( const MachineOperand & MO ) const { assert ( ! MO . getTargetFlags ( ) && <STR_LIT> ) ; return AsmPrinter . getSymbol ( MO . getGlobal ( ) ) ;


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned SP = STI . getABI ( ) . GetStackPtr ( ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ( I -> getOpcode ( ) == <STR_LIT> ) || ( I -> getOpcode ( ) == <STR_LIT> ) ) Amount = - Amount ; STI . getInstrInfo ( ) -> adjustStackPtr ( SP , Amount , MBB , I ) ;


<s> default : return ( val >= <NUM_LIT> && ( val + GET_MODE_SIZE ( mode ) ) <= <NUM_LIT> && ( val & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> return new <ISA_LIT>PrepareForLiveIntervals ( ) ;


<s> int Opc = MI . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertShift ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : return insertMul ( MI , MBB ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; const <ISA_LIT>InstrInfo & TII = ( const <ISA_LIT>InstrInfo & ) * MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock * FallThrough = MBB -> getFallThrough ( ) ; if ( FallThrough != nullptr ) { BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( FallThrough ) ; } MachineBasicBlock * trueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * falseMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator I ; for ( I = MF -> begin ( ) ; I != MF -> end ( ) && & ( * I ) != MBB ; ++ I ) ; if ( I != MF -> end ( ) ) ++ I ; MF -> insert ( I , trueMBB ) ; MF -> insert ( I , falseMBB ) ; trueMBB -> splice ( trueMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; trueMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; <STR_LIT> CC = ( <STR_LIT> ) MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( MBB , dl , TII . getBrCond ( CC ) ) . addMBB ( trueMBB ) ; BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( falseMBB ) ; MBB -> addSuccessor ( falseMBB ) ; MBB -> addSuccessor ( trueMBB ) ; BuildMI ( falseMBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( trueMBB ) ; falseMBB -> addSuccessor ( trueMBB ) ; BuildMI ( * trueMBB , trueMBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( falseMBB ) ; MI . eraseFromParent ( ) ;


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_Data_4 : return <NUM_LIT> ;


<s> void <ISA_LIT>JITInfo :: replaceMachineCodeForFunction ( void * Old , void * New ) { llvm_unreachable ( <NUM_LIT> ) ;


<s> static bool getTargetShuffleInputs ( SDValue Op , SmallVectorImpl < SDValue > & Inputs , SmallVectorImpl < int > & Mask , const SelectionDAG & DAG , unsigned Depth = <NUM_LIT> , bool ResolveKnownElts = true ) {


<s> StringRef getPassName ( ) const override {


<s> getThumbAddrModeRegRegOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & , const MCSubtargetInfo & STI ) const { const MCOperand & MO1 = MI . getOperand ( OpIdx ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO1 . getReg ( ) ) ;

unsigned Rm = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO2 . getReg ( ) ) ;


<s> uint32_t <ISA_LIT>Relocator :: getDebugStringOffset ( Relocation & pReloc ) const { if ( pReloc . type ( ) != llvm :: ELF :: R_<ISA_LIT>_ABS32 ) error ( diag :: unsupport_reloc_for_debug_string ) << getName ( pReloc . type ( ) ) << <STR_LIT> ;

if ( pReloc . symInfo ( ) -> type ( ) == ResolveInfo :: Section ) return pReloc . target ( ) + pReloc . addend ( ) ;


<s> } if ( isUseMIInFoldList ( FoldList , MI ) ) return false ; unsigned CommuteOpNo = OpNo ; unsigned CommuteIdx0 = TargetInstrInfo :: CommuteAnyOperandIndex ; unsigned CommuteIdx1 = TargetInstrInfo :: CommuteAnyOperandIndex ; bool CanCommute = TII -> findCommutedOpIndices ( * MI , CommuteIdx0 , CommuteIdx1 ) ; if ( CanCommute ) { if ( CommuteIdx0 == OpNo ) CommuteOpNo = CommuteIdx1 ; else if ( CommuteIdx1 == OpNo ) CommuteOpNo = CommuteIdx0 ; } if ( CanCommute && ( ! MI -> getOperand ( CommuteIdx0 ) . isReg ( ) || ! MI -> getOperand ( CommuteIdx1 ) . isReg ( ) ) ) return false ; if ( ! CanCommute || ! TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ) return false ; if ( ! TII -> isOperandLegal ( * MI , CommuteOpNo , OpToFold ) ) { if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && OpToFold -> isImm ( ) ) { MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; unsigned OtherIdx = CommuteOpNo == CommuteIdx0 ? CommuteIdx1 : CommuteIdx0 ; MachineOperand & OtherOp = MI -> getOperand ( OtherIdx ) ; if ( ! OtherOp . isReg ( ) || ! TII -> getRegisterInfo ( ) . isVGPR ( MRI , OtherOp . getReg ( ) ) ) return false ; assert ( MI -> getOperand ( <NUM_LIT> ) . isDef ( ) ) ; unsigned MaybeCommutedOpc = MI -> getOpcode ( ) ; int Op32 = <STR_LIT> ( MaybeCommutedOpc ) ; FoldList . push_back ( FoldCandidate ( MI , CommuteOpNo , OpToFold , true , Op32 ) ) ; return true ; } TII -> commuteInstruction ( * MI , false , CommuteIdx0 , CommuteIdx1 ) ; return false ; } FoldList . push_back ( FoldCandidate ( MI , CommuteOpNo , OpToFold , true ) ) ; return true ; } FoldList . push_back ( FoldCandidate ( MI , OpNo , OpToFold ) ) ;


<s> for ( ; link ; link = link -> next ) { if ( ! ALTIVEC_OR_VSX_VECTOR_MODE ( GET_MODE ( DF_REF_REG ( link -> ref ) ) ) ) continue ; if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx reached_insn = DF_REF_INSN ( link -> ref ) ; unsigned uid = INSN_UID ( reached_insn ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( reached_insn ) ; if ( ! insn_entry [ uid ] . is_swap || insn_entry [ uid ] . is_load || insn_entry [ uid ] . is_store ) return false ; if ( purpose == FOR_LOADS ) { df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * swap_link = DF_REF_CHAIN ( use ) ; while ( swap_link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) return false ; rtx swap_def_insn = DF_REF_INSN ( swap_link -> ref ) ; unsigned uid2 = INSN_UID ( swap_def_insn ) ; if ( ! insn_entry [ uid2 ] . is_swap || ! insn_entry [ uid2 ] . is_load ) return false ; swap_link = swap_link -> next ; } } } else if ( purpose == FOR_STORES ) {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isMovDGAll ( ) && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( MovDGAll . Val ) ) ;


<s> MachineInstr & MI = * I ; if ( <STR_LIT> ( MI ) ) return I ; } return MBB . end ( ) ;


<s> void <ISA_LIT>LoopIdiomRecognize :: collectStores ( Loop * CurLoop , BasicBlock * BB , SmallVectorImpl < StoreInst * > & Stores ) { Stores . clear ( ) ; for ( Instruction & I : * BB ) if ( StoreInst * SI = dyn_cast < StoreInst > ( & I ) ) if ( isLegalStore ( CurLoop , SI ) ) Stores . push_back ( SI ) ;


<s> if ( Kind != k_Immediate && Kind != k_PostIndexRegister ) return false ;

if ( Kind == k_PostIndexRegister ) return PostIdxReg . ShiftTy == <STR_LIT> ;


<s> const <ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFInfo = FuncInfo . MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! FuncInfo . CanLowerReturn ) return false ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( CC != CallingConv :: C && CC != CallingConv :: Fast && CC != CallingConv :: <ISA_LIT>_FastCall && CC != CallingConv :: <ISA_LIT>_64_SysV ) return false ; if ( Subtarget -> isCallingConvWin64 ( CC ) ) return false ; if ( <ISA_LIT>MFInfo -> getBytesToPopOnReturn ( ) != <NUM_LIT> ) return false ; if ( CC == CallingConv :: Fast && TM . Options . GuaranteedTailCallOpt ) return false ; if ( F . isVarArg ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ; if ( SrcVT != DstVT ) { if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( ! Outs [ <NUM_LIT> ] . Flags . isZExt ( ) && ! Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; assert ( DstVT == <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { if ( Outs [ <NUM_LIT> ] . Flags . isSExt ( ) ) return false ; SrcReg = fastEmitZExtFromI1 ( <STR_LIT> , SrcReg , false ) ;


<s> return ( __m128 ) __builtin_ia32_rcp14ps128_mask ( ( __v4sf ) __A , ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) , Subtarget ( ST ) {


<s> return __builtin_arm_qasx ( __a , __b ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: toy , false > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> __arm_mcr2 ( const unsigned int __coproc , const unsigned int __opc1 , uint32_t __value , const unsigned int __CRn , const unsigned int __CRm , const unsigned int __opc2 ) { return __builtin_arm_mcr2 ( __coproc , __opc1 , __value , __CRn , __CRm , __opc2 ) ;


<s> if ( TIED_TO ) { R2 = Rn ; Imm = decodeImm8 ( insn ) ; } else { R2 = decodeRm ( insn ) ; Imm = slice ( insn , <NUM_LIT> , <NUM_LIT> ) ; } } else { if ( Imm12 ) Imm = getImm12 ( insn ) ; else Imm = decodeImm8 ( insn ) ; } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R0 ) ) ) ; ++ OpIdx ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R1 ) ) ) ; ++ OpIdx ; if ( ThreeReg ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , R2 ) ) ) ; ++ OpIdx ; } assert ( OpInfo [ OpIdx ] . RegClass == <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateImm ( Imm ) ) ;


<s> if ( ! BaseOp || ! BaseOp -> isReg ( ) ) return false ; BaseOps . push_back ( BaseOp ) ;


<s> if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; operands [ <NUM_LIT> ] = GEN_INT ( sp_adjust ) ; } else { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> ) ; } } snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; } else { int pop_en4_only_p = <NUM_LIT> ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , rb_callee_saved ) ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_callee_saved ) ; if ( ! cfun -> machine -> fp_size && ! cfun -> machine -> gp_size && ! cfun -> machine -> lp_size && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM ) { return <STR_LIT> ; } else { if ( REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM ) pop_en4_only_p = <NUM_LIT> ; snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , pop_en4_only_p ? <STR_LIT> : <STR_LIT> , cfun -> machine -> fp_size ? <STR_LIT> : <STR_LIT> , cfun -> machine -> gp_size ? <STR_LIT> : <STR_LIT> , cfun -> machine -> lp_size ? <STR_LIT> : <STR_LIT> ) ; }


<s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC = TLI . getRegClassFor ( LocVT . getSimpleVT ( ) ) ; Register VReg = RegInfo . createVirtualRegister ( RC ) ;

RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ;


<s> bool <ISA_LIT>SchedStrategy :: regBelongsToClass ( Register Reg , const TargetRegisterClass * RC ) const { if ( ! Reg . isVirtual ( ) ) { return RC -> contains ( Reg ) ;


<s> return CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ;


<s> static bool ix86_expand_sse_fp_minmax ( rtx dest , enum rtx_code code , rtx cmp_op0 , rtx cmp_op1 , rtx if_true , rtx if_false ) { machine_mode mode ; bool is_min ; rtx tmp ; if ( code == LT ) ; else if ( code == UNGE ) std :: swap ( if_true , if_false ) ; else return false ; if ( rtx_equal_p ( cmp_op0 , if_true ) && rtx_equal_p ( cmp_op1 , if_false ) ) is_min = true ; else if ( rtx_equal_p ( cmp_op1 , if_true ) && rtx_equal_p ( cmp_op0 , if_false ) ) is_min = false ; else return false ; mode = GET_MODE ( dest ) ; if ( ! flag_finite_math_only || flag_signed_zeros ) { int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX ;


<s> rtx mem = XEXP ( set , opn ) ; rtx addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( mem ) != MEM ) return <NUM_LIT> ; if ( register_operand ( addr , Pmode ) ) return <NUM_LIT> ; if ( GET_CODE ( addr ) == POST_INC ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> default : return false ; case Triple :: IOS : case Triple :: TvOS : return Major < <NUM_LIT> ; case Triple :: WatchOS : return Major < <NUM_LIT> ; case Triple :: MacOSX : case Triple :: Darwin : return Major < <NUM_LIT> ;


<s> if ( ! K0 ) return SDValue ( ) ; APFloat :: cmpResult Cmp = K0 -> getValueAPF ( ) . compare ( K1 -> getValueAPF ( ) ) ; if ( Cmp == APFloat :: cmpGreaterThan ) return SDValue ( ) ; EVT VT = Op0 . getValueType ( ) ; if ( Subtarget -> enableDX10Clamp ( ) ) { if ( K1 -> isExactlyValue ( <NUM_LIT> ) && K0 -> isExactlyValue ( <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , SL , VT , Op0 . getOperand ( <NUM_LIT> ) ) ; } if ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasMed3_16 ( ) ) ) { SDValue Var = Op0 . getOperand ( <NUM_LIT> ) ; if ( ! DAG . isKnownNeverSNaN ( Var ) ) return SDValue ( ) ; const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; if ( ( ! K0 -> hasOneUse ( ) || TII -> isInlineConstant ( K0 -> getValueAPF ( ) . bitcastToAPInt ( ) ) ) && ( ! K1 -> hasOneUse ( ) || TII -> isInlineConstant ( K1 -> getValueAPF ( ) . bitcastToAPInt ( ) ) ) ) {

return DAG . getNode ( <STR_LIT> , SL , K0 -> getValueType ( <NUM_LIT> ) , Var , SDValue ( K0 , <NUM_LIT> ) , SDValue ( K1 , <NUM_LIT> ) ) ;


<s> if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) {

EVT PtrVT = getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ;


<s> void adds8Imm64Operands ( MCInst & Inst , unsigned N ) const {


<s> BuildVectorSDNode * BVN = cast < BuildVectorSDNode > ( Op . getNode ( ) ) ; DebugLoc dl = Op . getDebugLoc ( ) ; EVT VT = Op . getValueType ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) {

SDValue Val = isVMOVSplat ( SplatBits . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG ) ;


<s> BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; unsigned TempReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( TempReg , RegState :: Define ) . addReg ( GlobalBaseReg ) ; MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setUsesPICBase ( true ) ; } } else { GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , dl , TII . get ( <STR_LIT> ) , GlobalBaseReg ) ; } } else { MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> setShrinkWrapDisabled ( true ) ; GlobalBaseReg = RegInfo -> createVirtualRegister ( & <STR_LIT> ) ;


<s> Key += CPU ; Key += FS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) Key += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; FS = Key . substr ( CPU . size ( ) ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride ) ; GISelAccessor * GISel = new GISelAccessor ( ) ; <ISA_LIT>GISelActualAccessor * GISel = new <ISA_LIT>GISelActualAccessor ( ) ;

GISel -> CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * I -> getTargetLowering ( ) ) ) ;


<s> if ( POINTER_TYPE_P ( type ) && FUNC_OR_METHOD_TYPE_P ( TREE_TYPE ( type ) ) ) res = true ; else if ( RECORD_OR_UNION_TYPE_P ( type ) ) { tree field ;

for ( field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( TREE_CODE ( field ) == FIELD_DECL ) res = res || chkp_type_has_function_pointer ( TREE_TYPE ( field ) ) ;


<s> default : return ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; case <NUM_LIT> : RC = & <STR_LIT> ; break ; } unsigned NewOpcode = TII -> getMaskedMIMGOp ( MI -> getOpcode ( ) , BitsSet ) ; MI -> setDesc ( TII -> get ( NewOpcode ) ) ; MRI . setRegClass ( VReg , RC ) ; return ; } int NoRetAtomicOp = <STR_LIT> ( MI -> getOpcode ( ) ) ; if ( NoRetAtomicOp != - <NUM_LIT> ) { if ( ! Node -> hasAnyUseOfValue ( <NUM_LIT> ) ) { MI -> setDesc ( TII -> get ( NoRetAtomicOp ) ) ;