<s> SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Chain , Size ) ; MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> setHasWinAlloca ( true ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned SPReg = RegInfo -> getStackRegister ( ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , SPTy ) ; Chain = SP . getValue ( <NUM_LIT> ) ; if ( Align ) { SP = DAG . getNode ( <STR_LIT> , dl , VT , SP . getValue ( <NUM_LIT> ) , DAG . getConstant ( - ( uint64_t ) Align , dl , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , SP ) ; } Result = SP ; } Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , SDValue ( ) , dl ) ; SDValue Ops [ <NUM_LIT> ] = { Result , Chain } ; return DAG . getMergeValues ( Ops , dl ) ;


<s> { MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_SBREL , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } , { MO_SECREL , <STR_LIT> } , { MO_NONLAZY , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ;


<s> if ( InstrInfo . MaskRegOp && hasSameVLMAX ( InstrInfo ) && TailAgnostic == InstrInfo . TailAgnostic && MaskAgnostic == InstrInfo . MaskAgnostic ) return true ;


<s> if ( ! MO . isReg ( ) ) return false ; unsigned Reg = MO . getReg ( ) ; const TargetRegisterClass * RC = TargetRegisterInfo :: isVirtualRegister ( Reg ) ? MRI . getRegClass ( Reg ) :


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> if ( ! cum ) return false ; if ( TARGET_SHCOMPACT ) { cum -> byref = shcompact_byref ( cum , mode , type , named ) ;


<s> return __builtin_aarch64_sqrshlv2si ( __a , __b ) ;


<s> if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ <NUM_LIT> ] ; switch ( d -> vmode ) { case E_V16QImode : gen = gen_neon_vextv16qi ; break ; case E_V8QImode : gen = gen_neon_vextv8qi ; break ; case E_V4HImode : gen = gen_neon_vextv4hi ; break ; case E_V8HImode : gen = gen_neon_vextv8hi ; break ; case E_V2SImode : gen = gen_neon_vextv2si ; break ; case E_V4SImode : gen = gen_neon_vextv4si ; break ; case E_V4HFmode : gen = gen_neon_vextv4hf ; break ; case E_V8HFmode : gen = gen_neon_vextv8hf ; break ; case E_V2SFmode : gen = gen_neon_vextv2sf ; break ; case E_V4SFmode : gen = gen_neon_vextv4sf ; break ; case E_V2DImode : gen = gen_neon_vextv2di ; break ; default : return false ; } if ( d -> testing_p ) return true ; offset = GEN_INT ( location ) ;

emit_insn ( gen ( d -> target , d -> op0 , d -> op1 , offset ) ) ;


<s> if ( NewOpcode == <STR_LIT> ) { legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst -> setDesc ( NewDesc ) ; for ( unsigned i = Inst -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) Inst -> RemoveOperand ( i ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Inst -> addImplicitDefUseOperands ( * Inst -> getParent ( ) -> getParent ( ) ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & OffsetWidthOp = Inst -> getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst -> RemoveOperand ( <NUM_LIT> ) ;

Inst -> addOperand ( MachineOperand :: CreateImm ( Offset ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> ) ) return true ; return false ;


<s> SDValue TGA = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; GlobalAddressSDNode * GSDN = dyn_cast < GlobalAddressSDNode > ( TGA ) ; if ( GSDN -> getAddressSpace ( ) == <STR_LIT> ) return true ;


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { return <STR_LIT> ;


<s> void <ISA_LIT>ELFStreamer :: emitHandlerData ( ) {


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; assert ( ( ( Val && VReg ) || ( ! Val && ! VReg ) ) && <STR_LIT> ) ; bool Success = true ; if ( VReg ) { const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { MIRBuilder . buildExtract ( Reg , VReg , Offset ) ; } ) ; OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFn , AssignFn ) ;

Success = handleAssignments ( MIRBuilder , SplitArgs , Handler ) ;


<s> else if ( basereg == SP_REGNO && offset >= <NUM_LIT> && offset < <NUM_LIT> && ( offset & <NUM_LIT> ) == <NUM_LIT> ) return true ; return false ;


<s> if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return new Darwin<ISA_LIT>_64AsmBackend ( T , MRI , CPU , TheTriple . isMacOSX ( ) && ! TheTriple . isMacOSXVersionLT ( <NUM_LIT> , <NUM_LIT> ) ) ; if ( TheTriple . isOSWindows ( ) && TheTriple . getEnvironment ( ) != Triple :: ELF ) return new Windows<ISA_LIT>AsmBackend ( T , true , CPU ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TheTriple . getOS ( ) ) ;

return new ELF<ISA_LIT>_64AsmBackend ( T , OSABI , CPU ) ;


<s> return __builtin_altivec_abs_v4sf ( a1 ) ;


<s> FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( ! hasAddr64 ( ) && ! FS . contains ( <STR_LIT> ) ) { FlatForGlobal = true ; } if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { FP16Denormals = false ; FP32Denormals = false ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>Family ( UltraScale ) , TM ( TM ) , TargetTriple ( TT ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * CP = cast < ConstantPoolSDNode > ( Op ) ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Large ) {


<s> return insertSubVector ( Result , Vec , IdxVal , DAG , dl , <NUM_LIT> ) ;


<s> return VectorList . Count == <NUM_LIT> ;


<s> case NE : check_unordered = true ; mode = CCZmode ; const_val = const1_rtx ; break ; default : gcc_unreachable ( ) ; } target = gen_reg_rtx ( SImode ) ; emit_move_insn ( target , const_val ) ; target = gen_rtx_SUBREG ( QImode , target , <NUM_LIT> ) ; if ( ( optimize && ! register_operand ( op0 , mode0 ) ) || ! insn_p -> operand [ <NUM_LIT> ] . predicate ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ( optimize && ! register_operand ( op1 , mode1 ) ) || ! insn_p -> operand [ <NUM_LIT> ] . predicate ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( icode ) ( op0 , op1 ) ; if ( ! pat ) return <NUM_LIT> ; set_dst = SET_DEST ( pat ) ; emit_insn ( pat ) ; return ix86_ssecom_setcc ( comparison , check_unordered , mode , set_dst , target ) ;


<s> OS << <ISA_LIT>CondCodeToString ( getCondCode ( ) ) ; break ; case CCOut : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case Immediate : getImm ( ) -> print ( OS ) ; break ; case Memory : OS << <STR_LIT> ; break ; case Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ;


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; EVT VT = Op . getValueType ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; if ( MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { int FrameAddrIndex = FuncInfo -> getFAIndex ( ) ; if ( ! FrameAddrIndex ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; FrameAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , <NUM_LIT> , false ) ; FuncInfo -> setFAIndex ( FrameAddrIndex ) ;


<s> Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ;


<s> } for ( const Argument & Arg : F -> args ( ) ) { if ( Arg . getArgNo ( ) >= <NUM_LIT> ) return false ; if ( Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: ByVal ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const MCPhysReg GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const TargetRegisterClass * RC = & <STR_LIT> ; for ( const Argument & Arg : F -> args ( ) ) { unsigned ArgNo = Arg . getArgNo ( ) ; unsigned SrcReg = GPRArgRegs [ ArgNo ] ;

unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ;


<s> init_machine_status = c6x_init_machine_status ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( c6x_unit_names ) ; i ++ ) c6x_unit_codes [ i ] = get_cpu_unit_code ( c6x_unit_names [ i ] ) ; if ( flag_pic && ! TARGET_DSBT ) { error ( <STR_LIT> <STR_LIT> ) ;


<s> if ( ! isUIntN ( Width , Value ) ) { std :: string Diagnostic = <STR_LIT> + Description ; int64_t Max = maxUIntN ( Width ) ; Diagnostic += <STR_LIT> + std :: to_string ( Max ) + <STR_LIT> ;


<s> static SDValue LowerBUILD_VECTOR ( SDValue Op , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; EVT EltVT = VT . getVectorElementType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; BuildVectorSDNode * BCN = dyn_cast < BuildVectorSDNode > ( Op . getNode ( ) ) ; assert ( BCN != <NUM_LIT> && <STR_LIT> ) ; unsigned minSplatBits = EltVT . getSizeInBits ( ) ; if ( minSplatBits < <NUM_LIT> ) minSplatBits = <NUM_LIT> ; APInt APSplatBits , APSplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( ! BCN -> isConstantSplat ( APSplatBits , APSplatUndef , SplatBitSize , HasAnyUndefs , minSplatBits ) || minSplatBits < SplatBitSize ) return SDValue ( ) ; uint64_t SplatBits = APSplatBits . getZExtValue ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : report_fatal_error ( <STR_LIT> + Twine ( VT . getEVTString ( ) ) ) ; case <STR_LIT> : { uint32_t Value32 = uint32_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( Value32 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T , T , T ) ) ; break ; } case <STR_LIT> : { uint64_t f64val = uint64_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( f64val , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ) ; break ; } case <STR_LIT> : { unsigned short Value16 = SplatBits ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . assign ( <NUM_LIT> , DAG . getConstant ( Value16 , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ) ; }


<s> Target & llvm :: getThe<ISA_LIT>elTarget ( ) { static Target The<ISA_LIT>elTarget ; return The<ISA_LIT>elTarget ;


<s> RegisterTarget < Triple :: m680x0 , true > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> void <ISA_LIT>CFGStackify :: fixEndsAtEndOfFunction ( MachineFunction & MF ) { const auto & MFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( MFI . getResults ( ) . empty ( ) ) return ; <STR_LIT> RetType = MFI . getResults ( ) . size ( ) > <NUM_LIT> ? <STR_LIT> :: Multivalue : <STR_LIT> ( <STR_LIT> ( MFI . getResults ( ) . front ( ) ) ) ; SmallVector < MachineBasicBlock :: reverse_iterator , <NUM_LIT> > Worklist ; Worklist . push_back ( MF . rbegin ( ) -> rbegin ( ) ) ; auto Process = [ & ] ( MachineBasicBlock :: reverse_iterator It ) { auto * MBB = It -> getParent ( ) ; while ( It != MBB -> rend ( ) ) { MachineInstr & MI = * It ++ ; if ( MI . isPosition ( ) || MI . isDebugInstr ( ) ) continue ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { auto * EHPad = TryToEHPad . lookup ( EndToBegin [ & MI ] ) ; assert ( EHPad ) ; auto NextIt = std :: next ( <STR_LIT> ( EHPad ) -> getReverseIterator ( ) ) ;

if ( NextIt != EHPad -> rend ( ) ) Worklist . push_back ( NextIt ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) Mask . push_back ( i ) ;

return DAG . getVectorShuffle ( VT , dl , V1 , V2 , & Mask [ <NUM_LIT> ] ) ;


<s> if ( Alignment >= Size ) return true ; } if ( CurDAG -> isBaseWithConstantOffset ( N ) ) { if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int64_t RHSC = ( int64_t ) RHS -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( RHSC & ( Size - <NUM_LIT> ) ) == <NUM_LIT> && RHSC >= <NUM_LIT> && RHSC < ( <NUM_LIT> << Scale ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC >> Scale , <STR_LIT> ) ; return true ; } } } if ( SelectAddrModeUnscaled ( N , Size , Base , OffImm ) ) return false ; Base = N ;

OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ;


if ( ST -> getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return <NUM_LIT> ;


<s> rtx bsel ; emit_move_insn ( mask , cmp_res ) ; if ( register_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx xop1 = operands [ <NUM_LIT> ] ; if ( mode != vimode ) { xop1 = gen_reg_rtx ( vimode ) ; emit_move_insn ( xop1 , gen_lowpart ( vimode , operands [ <NUM_LIT> ] ) ) ; } emit_move_insn ( src1 , xop1 ) ; } else { gcc_assert ( operands [ <NUM_LIT> ] == CONSTM1_RTX ( vimode ) ) ; emit_move_insn ( src1 , mask ) ; } if ( register_operand ( operands [ <NUM_LIT> ] , mode ) ) { rtx xop2 = operands [ <NUM_LIT> ] ; if ( mode != vimode ) { xop2 = gen_reg_rtx ( vimode ) ; emit_move_insn ( xop2 , gen_lowpart ( vimode , operands [ <NUM_LIT> ] ) ) ; } emit_move_insn ( src2 , xop2 ) ; } else { gcc_assert ( operands [ <NUM_LIT> ] == CONST0_RTX ( mode ) ) ; emit_move_insn ( src2 , mask ) ;


<s> if ( TLI . isPositionIndependent ( ) ) return <NUM_LIT> ; if ( GV -> isThreadLocal ( ) ) return <NUM_LIT> ;

unsigned ResultReg = createResultReg ( Subtarget -> hasAddr64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ;


<s> if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { int FI = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addFrameIndex ( FI ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( ImmOffset ) ; } } } ; } Register SAddr = AddrDef -> Reg ; if ( AddrDef -> MI -> getOpcode ( ) == <STR_LIT> ) { Register LHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto LHSDef = getDefSrcRegIgnoringCopies ( LHS , * MRI ) ; auto RHSDef = getDefSrcRegIgnoringCopies ( RHS , * MRI ) ; if ( LHSDef && RHSDef && LHSDef -> MI -> getOpcode ( ) == <STR_LIT> && isSGPR ( RHSDef -> Reg ) ) { int FI = LHSDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; MachineInstr & I = * Root . getParent ( ) ; MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; SAddr = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , SAddr ) . addFrameIndex ( FI ) . addReg ( RHSDef -> Reg ) ; } } if ( ! isSGPR ( SAddr ) ) return None ;


<s> FunctionPass * createSNITCHFrepLoopsPass ( ) {


<s> continue ; } customEmitInstruction ( & * I ) ; } while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ;


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ;


<s> APInt SignificantBitsToBeInserted = BitsToBeInserted . zextOrTrunc ( BitWidth ) ; return ( SignificantDstMask & SignificantBitsToBeInserted ) == <NUM_LIT> && ( SignificantDstMask | SignificantBitsToBeInserted ) . isAllOnesValue ( ) ;


<s> tree r , u ; r = size_int ( NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD ) ; u = build2 ( MODIFY_EXPR , TREE_TYPE ( count_tmp ) , count_tmp , r ) ; t = fold_convert ( TREE_TYPE ( count ) , r ) ; t = build2 ( GE_EXPR , boolean_type_node , count_tmp , t ) ; t = build3 ( COND_EXPR , void_type_node , t , NULL_TREE , u ) ; gimplify_and_add ( t , pre_p ) ; } t = size_int ( NUM_ARGUMENT_REGISTERS * UNITS_PER_WORD + INCOMING_FRAME_SP_OFFSET ) ; t = fold_convert ( TREE_TYPE ( count ) , t ) ; t = build2 ( MINUS_EXPR , TREE_TYPE ( count ) , count_tmp , t ) ; t = build2 ( PLUS_EXPR , TREE_TYPE ( count ) , t , fold_convert ( TREE_TYPE ( count ) , size_tree ) ) ; t = fold_convert ( TREE_TYPE ( t ) , fold ( t ) ) ; t = fold_build1 ( NEGATE_EXPR , TREE_TYPE ( t ) , t ) ; t = fold_build_pointer_plus ( base , t ) ; gimplify_assign ( addr , t , pre_p ) ; t = build1 ( LABEL_EXPR , void_type_node , lab_gotaddr ) ; gimplify_and_add ( t , pre_p ) ; t = fold_convert ( TREE_TYPE ( count ) , size_tree ) ; t = build2 ( PLUS_EXPR , TREE_TYPE ( count ) , count_tmp , t ) ; gimplify_assign ( count , t , pre_p ) ;

addr = fold_convert ( build_pointer_type ( type ) , addr ) ;


<s> if ( MO . isImm ( ) && isInlineConstant ( MO , OpInfo ) ) return RI . opCanUseInlineConstant ( OpInfo . OperandType ) ; if ( ! RI . opCanUseLiteralConstant ( OpInfo . OperandType ) ) return false ; if ( ! isVOP3 ( MI ) || ! <STR_LIT> ( InstDesc , OpNo ) ) return true ;

const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_MemoryReg ) ; Op -> Mem . Base = Base ; Op -> Mem . OffsetReg = <STR_LIT> ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> if ( ! isLowringToMASSSafe ( Op ) ) return SDValue ( ) ; if ( ! isLowringToMASSFiniteSafe ( Op ) ) return lowerLibCallBasedOnType ( LibCallFloatName , LibCallDoubleName , Op , DAG ) ; return lowerLibCallBasedOnType ( LibCallFloatNameFinite , LibCallDoubleNameFinite , Op , DAG ) ;


<s> Sch . scheduleRegion ( Rgn , Sch . SUnits , SaveMaxRP ) ;


<s> unsigned int getSlaveReg1 ( unsigned int regNUM ) { std :: unordered_map < unsigned int , unsigned int > :: const_iterator got = GPRregistersMap1 . find ( regNUM ) ;

if ( got == GPRregistersMap1 . end ( ) ) {


<s> static __inline qword si_andbi ( qword a , signed char b ) { return ( ( qword ) ( vec_and ( ( vec_char16 ) ( a ) , vec_splat ( ( vec_char16 ) ( si_from_char ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> virtual unsigned getRelocationInfo ( ) const {


<s> bool <ISA_LIT>InstrInfo :: shouldOutlineFromFunctionByDefault ( MachineFunction & MF ) const { return MF . getFunction ( ) . hasMinSize ( ) ;


<s> void <ISA_LIT>PassConfig :: addPreLegalizeMachineIR ( ) {

addPass ( create<ISA_LIT>PreLegalizerPass ( ) ) ;


<s> if ( ! isExport ( * PredSU ) && ! Pred . isWeak ( ) ) DAG -> addEdge ( ChainHead , SDep ( PredSU , SDep :: Artificial ) ) ; } DAG -> addEdge ( SUb , SDep ( SUa , SDep :: Barrier ) ) ;

DAG -> addEdge ( SUb , SDep ( SUa , SDep :: Cluster ) ) ;


<s> if ( MO . isDef ( ) ) { if ( Reg != <STR_LIT> && Reg != <STR_LIT> ) for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) ModifiedRegs . set ( * AI ) ; } else { assert ( MO . isUse ( ) && <STR_LIT> ) ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) UsedRegs . set ( * AI ) ;


<s> static void free_label_state ( struct unw_labeled_state * ls ) { labeled_state_alloced -- ; if ( PTR_IN ( emergency_labeled_state , ls ) ) atomic_free ( & emergency_labeled_state_free , emergency_labeled_state - ls ) ;


<s> LLVM_DEBUG ( printLivenessInfo ( dbgs ( ) , RegionBegin , RegionEnd , LIS ) ; if ( ! Regions . empty ( ) && Regions . back ( ) -> Begin == RegionBegin ) {


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { const <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; FrameReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Offset = { MFI . getObjectOffset ( FrameIndex ) + AFI -> getTaggedBasePointerOffset ( ) , <STR_LIT> } ; } else if ( Tagged ) { StackOffset SPOffset = { MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) , <STR_LIT> } ; if ( MFI . hasVarSizedObjects ( ) || is<ISA_LIT>FrameOffsetLegal ( MI , SPOffset , nullptr , nullptr , nullptr ) != ( <ISA_LIT>FrameOffsetCanUpdate | <ISA_LIT>FrameOffsetIsLegal ) ) { Offset = TFI -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg , false , true ) ; Register ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; emitFrameOffset ( MBB , II , MI . getDebugLoc ( ) , ScratchReg , FrameReg , Offset , TII ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( ScratchReg , false , false , true ) ; return ; } FrameReg = <STR_LIT> ; Offset = { MFI . getObjectOffset ( FrameIndex ) + ( int64_t ) MFI . getStackSize ( ) , <STR_LIT> } ;


return ( __m128i ) __builtin_ia32_pmovdw128_mask ( ( __v4si ) __A , ( __v8hi ) _mm_setzero_si128 ( ) , __M ) ;


} else if ( Model == TLSModel :: InitialExec ) {


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override { return & Subtarget ;


<s> if ( UniquedVals [ i ] . getNode ( ) == <NUM_LIT> ) continue ; LeadingZero &= cast < ConstantSDNode > ( UniquedVals [ i ] ) -> isNullValue ( ) ; LeadingOnes &= cast < ConstantSDNode > ( UniquedVals [ i ] ) -> isAllOnesValue ( ) ; } if ( LeadingZero ) { if ( UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) == <NUM_LIT> ) return DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getZExtValue ( ) ; if ( Val < <NUM_LIT> ) return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } if ( LeadingOnes ) { if ( UniquedVals [ Multiple - <NUM_LIT> ] . getNode ( ) == <NUM_LIT> ) return DAG . getTargetConstant ( ~ <NUM_LIT> , <STR_LIT> ) ; int Val = cast < ConstantSDNode > ( UniquedVals [ Multiple - <NUM_LIT> ] ) -> getSExtValue ( ) ; if ( Val >= - <NUM_LIT> ) return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } return SDValue ( ) ; } for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { if ( N -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> ) continue ; if ( OpVal . getNode ( ) == <NUM_LIT> ) OpVal = N -> getOperand ( i ) ; else if ( OpVal != N -> getOperand ( i ) ) return SDValue ( ) ; } if ( OpVal . getNode ( ) == <NUM_LIT> ) return SDValue ( ) ; unsigned ValSizeInBytes = EltSize ; uint64_t Value = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( OpVal ) ) { Value = CN -> getZExtValue ( ) ; } else if ( ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( OpVal ) ) { assert ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; Value = FloatToBits ( CN -> getValueAPF ( ) . convertToFloat ( ) ) ; } if ( ValSizeInBytes < ByteSize ) return SDValue ( ) ; while ( ValSizeInBytes > ByteSize ) { ValSizeInBytes >>= <NUM_LIT> ; if ( ( ( Value >> ( ValSizeInBytes * <NUM_LIT> ) ) & ( ( <NUM_LIT> << ( <NUM_LIT> * ValSizeInBytes ) ) - <NUM_LIT> ) ) != ( Value & ( ( <NUM_LIT> << ( <NUM_LIT> * ValSizeInBytes ) ) - <NUM_LIT> ) ) ) return SDValue ( ) ; } int MaskVal = SignExtend32 ( Value , ByteSize * <NUM_LIT> ) ;

if ( MaskVal == <NUM_LIT> ) return SDValue ( ) ;


<s> else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetWindows ( ) && ! Subtarget -> isTargetCygMing ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( SymbolName ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( Subtarget -> isTargetCOFF ( ) && ! Subtarget -> isTargetEnvMacho ( ) ) { <ISA_LIT>COFFMachineModuleInfo & COFFMMI = MMI -> getObjFileInfo < <ISA_LIT>COFFMachineModuleInfo > ( ) ; typedef <ISA_LIT>COFFMachineModuleInfo :: externals_iterator externals_iterator ; for ( externals_iterator I = COFFMMI . externals_begin ( ) , E = COFFMMI . externals_end ( ) ; I != E ; ++ I ) { OutStreamer . BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer . EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ; OutStreamer . EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ; OutStreamer . EndCOFFSymbolDef ( ) ; } std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; for ( Module :: const_iterator I = M . begin ( ) , E = M . end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedFns . push_back ( Mang -> getSymbol ( I ) ) ; for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ; I != E ; ++ I ) if ( I -> hasDLLExportLinkage ( ) ) DLLExportedGlobals . push_back ( Mang -> getSymbol ( I ) ) ; if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; SmallString < <NUM_LIT> > name ;

for ( unsigned i = <NUM_LIT> , e = DLLExportedGlobals . size ( ) ; i != e ; ++ i ) {


<s> for ( i = reg ; i < reg + count ; i ++ ) { if ( i > reg ) fputs ( <STR_LIT> , stream ) ; asm_fprintf ( stream , <STR_LIT> , i ) ;


<s> case Match_InvalidImm0_1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_7 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_15 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_31 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_63 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_127 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_255 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm0_65535 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_8 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_16 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_32 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidImm1_64 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndex1 : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexB : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexH : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexS : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidIndexD : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidLabel : return Error ( Loc , <STR_LIT> ) ; case Match_MRS : return Error ( Loc , <STR_LIT> ) ; case Match_MSR : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidComplexRotationEven : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidComplexRotationOdd : return Error ( Loc , <STR_LIT> ) ; case Match_MnemonicFail : { std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , ComputeAvailableFeatures ( STI -> getFeatureBits ( ) ) ) ; return Error ( Loc , <STR_LIT> + Suggestion ) ; } case Match_InvalidSVEPattern : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidSVEPredicateAnyReg : case Match_InvalidSVEPredicateBReg : case Match_InvalidSVEPredicateHReg : case Match_InvalidSVEPredicateSReg : case Match_InvalidSVEPredicateDReg : return Error ( Loc , <STR_LIT> ) ; case Match_InvalidSVEPredicate3bAnyReg : case Match_InvalidSVEPredicate3bBReg :


initialize<ISA_LIT>OptimizeLEAPassPass ( PR ) ;


<s> if ( RegVT . is256BitVector ( ) && ! DCI . isBeforeLegalizeOps ( ) && Ext == <STR_LIT> && TLI . allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , RegVT , AddressSpace , Alignment , & Fast ) && ! Fast ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue ( ) ; SDValue Ptr = Ld -> getBasePtr ( ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Alignment ) ; Ptr = DAG . getMemBasePlusOffset ( Ptr , <NUM_LIT> , dl ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , std :: min ( <NUM_LIT> , Alignment ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getUNDEF ( RegVT ) ; NewVec = Insert128BitVector ( NewVec , Load1 , <NUM_LIT> , DAG , dl ) ; NewVec = Insert128BitVector ( NewVec , Load2 , NumElems / <NUM_LIT> , DAG , dl ) ; return DCI . CombineTo ( N , NewVec , TF , true ) ;


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( SDValue Res = tryCombineToEXTR ( N , DCI ) ) return Res ; if ( SDValue Res = tryCombineToBSL ( N , DCI ) ) return Res ; if ( SDValue Res = tryCombineVecOrNot ( N , DCI ) ) return Res ;


<s> if ( Opt . getNumOccurrences ( ) ) return Opt ;

if ( TM -> getOptLevel ( ) < Level ) return false ;


<s> static rtx visium_legitimize_address ( rtx x , rtx oldx ATTRIBUTE_UNUSED , machine_mode mode ) { if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && mode != BLKmode ) {

int offset = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ;


<s> const MCExpr * <ISA_LIT>TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { if ( ! Subtarget . is<ISA_LIT>64 ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; default :

return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ;


<s> bool isVectorRegister ( const MachineRegisterInfo & MRI , Register Reg ) const { return isVGPR ( MRI , Reg ) || isAGPR ( MRI , Reg ) ;


<s> PrintIFR ( const IFRecord & R , const TargetRegisterInfo * RI ) : IFR ( R ) , TRI ( RI ) {


<s> vst2_u8 ( uint8_t * __a , uint8x8x2_t val ) { __builtin_aarch64_simd_oi __o ; uint8x16x2_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> DAG . computeKnownBits ( N . getOperand ( <NUM_LIT> ) , LHSKnownZero , LHSKnownOne ) ; if ( ( LHSKnownZero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Disp = DAG . getTargetConstant ( imm , N . getValueType ( ) ) ; return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { short Imm ; if ( isIntS16Immediate ( CN , Imm ) && ( ! Aligned || ( Imm & <NUM_LIT> ) == <NUM_LIT> ) ) { Disp = DAG . getTargetConstant ( Imm , CN -> getValueType ( <NUM_LIT> ) ) ; Base = DAG . getRegister ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> || ( int64_t ) CN -> getZExtValue ( ) == ( int ) CN -> getZExtValue ( ) ) && ( ! Aligned || ( CN -> getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) ) { int Addr = ( int ) CN -> getZExtValue ( ) ; Disp = DAG . getTargetConstant ( ( short ) Addr , <STR_LIT> ) ; Base = DAG . getTargetConstant ( ( Addr - ( signed short ) Addr ) >> <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Base = SDValue ( DAG . getMachineNode ( Opc , dl , CN -> getValueType ( <NUM_LIT> ) , Base ) , <NUM_LIT> ) ; return true ; }


<s> static void ia64_hpux_add_pragma_builtin ( tree func ) { size_t i ; if ( ! flag_isoc94 && flag_iso ) { for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( c89_mathlib_name_list ) ; i ++ ) { if ( ! strcmp ( c89_mathlib_name_list [ i ] . realname , IDENTIFIER_POINTER ( func ) ) ) { add_to_renaming_pragma_list ( func , get_identifier ( c89_mathlib_name_list [ i ] . c89name ) ) ; } } }


<s> void <ISA_LIT>TargetStreamer :: emitFnStart ( ) {


<s> void <ISA_LIT>AsmPrinter :: printPICLabel ( const MachineInstr * MI , unsigned Op , raw_ostream & O ) { O << * MF -> getPICBaseSymbol ( ) << '\n' ; O << * MF -> getPICBaseSymbol ( ) << ':' ;


__o = __builtin_aarch64_set_qregxiv2di_ssps ( __o , ( poly64x2_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; V = DAG . getBitcast ( <STR_LIT> , V ) ; continue ; } } V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , Op . getOperand ( i ) , DAG . getIntPtrConstant ( i , dl ) ) ; } } return V ; } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool ThisIsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( ThisIsNonZero && First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } if ( ( i & <NUM_LIT> ) != <NUM_LIT> ) { SDValue ThisElt , LastElt ; bool LastIsNonZero = ( NonZeros & ( <NUM_LIT> << ( i - <NUM_LIT> ) ) ) != <NUM_LIT> ; if ( LastIsNonZero ) { LastElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i - <NUM_LIT> ) ) ; } if ( ThisIsNonZero ) { ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ; ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( LastIsNonZero ) ThisElt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ThisElt , LastElt ) ; } else ThisElt = LastElt ; if ( ThisElt ) { if ( <NUM_LIT> == i ) { V = NumZero ? DAG . getZExtOrTrunc ( ThisElt , dl , <STR_LIT> ) : DAG . getAnyExtOrTrunc ( ThisElt , dl , <STR_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; V = DAG . getBitcast ( <STR_LIT> , V ) ; } else { V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , ThisElt , DAG . getIntPtrConstant ( i / <NUM_LIT> , dl ) ) ; } } }


<s> tree t ; t = rs6000_builtin_types [ id < <NUM_LIT> ? ~ id : id ] ;

return id < <NUM_LIT> ? build_pointer_type ( t ) : t ;


<s> if ( code == PRE_MODIFY || code == POST_MODIFY ) * offset = addr . offset ; else { unsigned int_offset = GET_MODE_SIZE ( mode ) . to_constant ( ) ; if ( load_pair && ( code == POST_INC || code == POST_DEC ) ) int_offset *= <NUM_LIT> ; * offset = GEN_INT ( int_offset ) ; } return true ; } else if ( addr . type == ADDRESS_REG_IMM || addr . type == ADDRESS_REG_REG ) { if ( ! iv_p ( insn , addr . base , loop ) ) return false ; * base = addr . base ;


<s> bool hasBSS ( ) const { return HasBSS ;


<s> if ( ! I . isAssignedRegDep ( ) || I . getSUnit ( ) != Dst ) continue ; unsigned DepR = I . getReg ( ) ; int DefIdx = - <NUM_LIT> ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < SrcI -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = SrcI -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == DepR ) DefIdx = OpNum ; } assert ( DefIdx >= <NUM_LIT> && <STR_LIT> ) ; MachineInstr * DstI = Dst -> getInstr ( ) ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DstI -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DstI -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DepR ) { int Latency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcI , DefIdx , * DstI , OpNum ) ) ; if ( Latency <= <NUM_LIT> ) Latency = <NUM_LIT> ; I . setLatency ( Latency ) ; updateLatency ( * SrcI , * DstI , I ) ; } } for ( auto & J : Dst -> Preds ) {

if ( J . getSUnit ( ) != Src ) continue ;


<s> return ( __m512i ) __builtin_ia32_punpckhqdq512_mask ( ( __v8di ) __A , ( __v8di ) __B , ( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( HasBaseReg ) { PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; NeedPlus = true ; } if ( IndexReg . getReg ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; if ( ScaleVal != <NUM_LIT> ) O << ScaleVal << '*' ; PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; NeedPlus = true ; } if ( ! DispSpec . isImm ( ) ) { if ( NeedPlus ) O << <STR_LIT> ; PrintOperand ( MI , OpNo + <STR_LIT> , O ) ; } else { int64_t DispVal = DispSpec . getImm ( ) ; if ( DispVal || ( ! IndexReg . getReg ( ) && ! HasBaseReg ) ) { if ( NeedPlus ) { if ( DispVal > <NUM_LIT> ) O << <STR_LIT> ; else {


<s> SDValue <ISA_LIT>SETargetLowering :: lowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; SDValue Op0 = Op -> getOperand ( <NUM_LIT> ) ;

EVT VecTy = Op0 -> getValueType ( <NUM_LIT> ) ;


<s> static MVT getSimpleVTForType ( Type * Ty ) { return EVT :: getEVT ( Ty ) . getSimpleVT ( ) ;


<s> static bool bfin_function_ok_for_sibcall ( tree decl ATTRIBUTE_UNUSED , tree exp ATTRIBUTE_UNUSED ) { cgraph_node * this_func , * called_func ; e_funkind fkind = funkind ( TREE_TYPE ( current_function_decl ) ) ; if ( fkind != SUBROUTINE ) return false ; if ( ! TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA ) return true ;


<s> unsigned Opc = getStoreRegOpcode ( SrcReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) ) , FrameIdx ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> static rtx aarch64_move_pointer ( rtx pointer , poly_int64 amount ) {

rtx next = plus_constant ( Pmode , XEXP ( pointer , <NUM_LIT> ) , amount ) ;


<s> AttributeItemType item = Contents [ i ] ; Streamer . EmitULEB128IntValue ( item . Tag , <NUM_LIT> ) ; switch ( item . Type ) { case AttributeItemType :: NumericAttribute : Streamer . EmitULEB128IntValue ( item . IntValue , <NUM_LIT> ) ; break ; case AttributeItemType :: TextAttribute : Streamer . EmitBytes ( item . StringValue . upper ( ) , <NUM_LIT> ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ;


addPass ( create<ISA_LIT>WholeQuadModePass ( ) ) ;


<s> if ( code == PLUS ) { rtx xop0 = XEXP ( addr , <NUM_LIT> ) ; rtx xop1 = XEXP ( addr , <NUM_LIT> ) ; return ( ( is_csky_address_register_rtx_p ( xop0 , strict_p ) && csky_legitimate_index_p ( mode , xop1 , strict_p ) ) || ( is_csky_address_register_rtx_p ( xop1 , strict_p ) && csky_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; }


<s> else if ( mode == TImode || ( TARGET_NEON && VALID_NEON_STRUCT_MODE ( mode ) ) ) return <NUM_LIT> ; else if ( code == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; return ( ( arm_address_register_rtx_p ( xop0 , strict_p ) && ( thumb2_legitimate_index_p ( mode , xop1 , strict_p ) || ( ! strict_p && will_be_in_index_register ( xop1 ) ) ) ) || ( arm_address_register_rtx_p ( xop1 , strict_p ) && thumb2_legitimate_index_p ( mode , xop0 , strict_p ) ) ) ; } else if ( can_avoid_literal_pool_for_label_p ( x ) ) return <NUM_LIT> ;

else if ( GET_MODE_CLASS ( mode ) != MODE_FLOAT && code == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P ( x ) && ! ( flag_pic && symbol_mentioned_p ( get_pool_constant ( x ) ) && ! pcrel_constant_p ( get_pool_constant ( x ) ) ) ) return <NUM_LIT> ;


<s> static ScheduleDAGInstrs * create<ISA_LIT>PostMachineScheduler ( MachineSchedContext * C ) {

ScheduleDAGMI * DAG = new ScheduleDAGMI ( C , llvm :: make_unique < <ISA_LIT>PostRASchedStrategy > ( C ) , true ) ;


<s> return true ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { unsigned RegTarget ; if ( Is64Bit ) { RegTarget = ( HideSandboxBase ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , RegTarget ) ; if ( Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; } BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( RegTarget ) . addReg ( FlagUseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; } else { RegTarget = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , RegTarget ) ; if ( Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; } BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( RegTarget ) ; } MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( Is64Bit && ! FlagUseZeroBasedSandbox ? <STR_LIT> : <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ;


<s> void <ISA_LIT>ExpandPseudo :: ExpandExtractElementF64 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned N = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const MCInstrDesc & Mfc1Tdd = TII -> get ( <STR_LIT> ) ; DebugLoc dl = I -> getDebugLoc ( ) ;

const unsigned * SubReg = TM . getRegisterInfo ( ) -> getSubRegisters ( SrcReg ) ;


<s> if ( ! I . isAssignedRegDep ( ) || I . getSUnit ( ) != Dst ) continue ; SDep T = I ; I . setLatency ( Lat ) ; T . setSUnit ( Src ) ; auto F = find ( Dst -> Preds , T ) ; assert ( F != Dst -> Preds . end ( ) ) ; F -> setLatency ( Lat ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

MFI -> setFrameAddressIsTaken ( true ) ;


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> bool <ISA_LIT>FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const { if ( STI . hasV8_1MMainlineOps ( ) && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> isCmseNSEntryFunction ( ) ) {


<s> assert ( ( ( ! Subtarget -> hasAVX512 ( ) && VT == <STR_LIT> ) || ( VT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerToBT ( Op0 , CC , dl , DAG ) ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( CCode , dl , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( ( Op0 . getValueType ( ) == <STR_LIT> ) && isOneConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { <STR_LIT> NewCC = <STR_LIT> ( CC , true ) ; return DAG . getSetCC ( dl , VT , Op0 , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , NewCC ) ; } bool isFP = Op1 . getSimpleValueType ( ) . isFloatingPoint ( ) ; unsigned <ISA_LIT>CC = Translate<ISA_LIT>CC ( CC , dl , isFP , Op0 , Op1 , DAG ) ;

if ( <ISA_LIT>CC == <STR_LIT> ) return SDValue ( ) ;


<s> void extendOutArgFIRange ( int FirstFI , int LastFI ) { if ( ! OutArgFIRange . second ) OutArgFIRange . first = FirstFI ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBUILD_VECTORvXi1 ( SDValue Op , SelectionDAG & DAG ) const { MVT VT = Op . getSimpleValueType ( ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) return DAG . getTargetConstant ( <NUM_LIT> , dl , VT ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) return DAG . getTargetConstant ( <NUM_LIT> , dl , VT ) ; if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue Imm = ConvertI1VectorToInteger ( Op , DAG ) ; if ( Imm . getValueSizeInBits ( ) == VT . getSizeInBits ( ) ) return DAG . getBitcast ( VT , Imm ) ; SDValue ExtVec = DAG . getBitcast ( <STR_LIT> , Imm ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } uint64_t Immediate = <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > NonConstIdx ; bool IsSplat = true ; bool HasConstElts = false ; int SplatIdx = - <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ;


<s> RegisterTarget < Triple :: wasm64 > Y ( getThe<ISA_LIT>Target64 ( ) , <STR_LIT> , <STR_LIT> ) ;


<s> assert ( Kind == OpKind :: Reg && <STR_LIT> ) ; return Reg . Num ;


<s> STI -> hasAGPRs ( RC ) ? ( STI -> getRegSizeInBits ( * RC ) == <NUM_LIT> ? AGPR32 : AGPR_TUPLE ) :

( STI -> getRegSizeInBits ( * RC ) == <NUM_LIT> ? VGPR32 : VGPR_TUPLE ) ;


<s> if ( <ISA_LIT>MCInstrInfo :: getExtendableOp ( MII , * MI ) == OpNo && ( HasExtender || <ISA_LIT>MCInstrInfo :: isConstExtended ( MII , * MI ) ) ) O << <STR_LIT> ; MCOperand const & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { O << getRegisterName ( MO . getReg ( ) ) ; } else if ( MO . isExpr ( ) ) {


<s> AllNative = useNativeFunc ( <STR_LIT> ) || ( UseNative . getNumOccurrences ( ) && UseNative . size ( ) == <NUM_LIT> && UseNative . begin ( ) -> empty ( ) ) ;


<s> <STR_LIT> AM = LdSt -> getAddressingMode ( ) ; if ( AM != <STR_LIT> ) return false ; Offset = N ; if ( ConstantSDNode * NC = dyn_cast < ConstantSDNode > ( N ) ) {

if ( NC -> getZExtValue ( ) * <NUM_LIT> == LdSt -> getMemoryVT ( ) . getSizeInBits ( ) ) Offset = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ;


<s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;

return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> if ( rs6000_abi_string == <NUM_LIT> ) return ; else if ( ! strcmp ( rs6000_abi_string , <STR_LIT> ) ) rs6000_altivec_abi = <NUM_LIT> ; else if ( ! strcmp ( rs6000_abi_string , <STR_LIT> ) ) rs6000_altivec_abi = <NUM_LIT> ;

else error ( <STR_LIT> , rs6000_abi_string ) ;


<s> for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , rs6000_get_some_local_dynamic_name_1 , <NUM_LIT> ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable ( ) ;


<s> MachineBasicBlock * lastCheck = NULL ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = ( MBB -> end ( ) ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) { for ( unsigned int opcount = <NUM_LIT> ; opcount < <NUM_LIT> ; opcount ++ ) if ( I -> getOperand ( opcount ) . isReg ( ) ) { lastCheck = insertVotingTZDC ( MF , I , I -> getOperand ( opcount ) . getReg ( ) , lastCheck ) ; } }


<s> Next = std :: next ( I ) ; MachineInstr & MI = * I ; if ( TII -> isDS ( MI . getOpcode ( ) ) ) { NeedM0 = true ; NeedWQM = true ; } switch ( MI . getOpcode ( ) ) { default : break ; case AMDGPU :: <ISA_LIT>_IF : ++ Depth ; If ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_ELSE : Else ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_BREAK : Break ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_IF_BREAK : IfBreak ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_ELSE_BREAK : ElseBreak ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_LOOP : ++ Depth ; Loop ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_END_CF : if ( -- Depth == <NUM_LIT> && HaveKill ) { SkipIfDead ( MI ) ; HaveKill = false ; } EndCf ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_KILL : if ( Depth == <NUM_LIT> ) SkipIfDead ( MI ) ;


<s> LLVM_DEBUG ( errs ( ) << format ( <STR_LIT> , Bead ) ) ; unsigned NumToRead ; switch ( Op ) { case <STR_LIT> : NumToRead = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : NumToRead = <NUM_LIT> ; break ; case <STR_LIT> : NumToRead = <NUM_LIT> ; break ; case <STR_LIT> : NumToRead = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectDS64Bit4ByteAligned ( SDValue Addr , SDValue & Base , SDValue & Offset0 , SDValue & Offset1 ) const { return SelectDSReadWrite2 ( Addr , Base , Offset0 , Offset1 , false ) ;


<s> assert ( AlignConst && <STR_LIT> ) ; unsigned A = AlignConst -> getSExtValue ( ) ; auto & HFI = * Subtarget . getFrameLowering ( ) ; if ( A == <NUM_LIT> ) A = HFI . getStackAlignment ( ) ; DEBUG ( { dbgs ( ) << __func__ << <STR_LIT> << A << <STR_LIT> ; Size . getNode ( ) -> dump ( & DAG ) ; dbgs ( ) << <STR_LIT> ; } ) ; SDValue AC = DAG . getConstant ( A , dl , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue AA = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Size , AC ) ; DAG . ReplaceAllUsesOfValueWith ( Op , AA ) ; return AA ;


<s> if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return false ;

uint64_t Index = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) -> getZExtValue ( ) ;


<s> static void mn10300_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) {

CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ;


<s> void <ISA_LIT>BasicBlockUtils :: computeBlockSize ( MachineBasicBlock * MBB ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << <STR_LIT> ) ; BasicBlockInfo & BBI = BBInfo [ MBB -> getNumber ( ) ] ; BBI . Size = <NUM_LIT> ; BBI . Unalign = <NUM_LIT> ; BBI . PostAlign = <NUM_LIT> ; for ( MachineInstr & I : * MBB ) { BBI . Size += TII -> getInstSizeInBytes ( I ) ; if ( I . isInlineAsm ( ) ) BBI . Unalign = isThumb ? <NUM_LIT> : <NUM_LIT> ; else if ( isThumb && mayOptimizeThumb2Instruction ( & I ) ) BBI . Unalign = <NUM_LIT> ;


<s> int pa_is_function_label_plus_const ( rtx op ) { if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , <NUM_LIT> ) ;

return ( GET_CODE ( op ) == PLUS && function_label_operand ( XEXP ( op , <NUM_LIT> ) , VOIDmode ) && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) ;


<s> MCSymbolRefExpr :: VK_GOT , Ctx ) ; break ; case <ISA_LIT>_64_RELOC_SUBTRACTOR : { Rel . moveNext ( ) ; any_relocation_info RENext = Obj -> getRelocation ( Rel . getRawDataRefImpl ( ) ) ; unsigned RType = Obj -> getAnyRelocationType ( RENext ) ; if ( RType != <ISA_LIT>_64_RELOC_UNSIGNED ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; const MCExpr * LHS = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; symbol_iterator RSymI = Rel . getSymbol ( ) ; uint64_t RSymAddr ; RSymI -> getAddress ( RSymAddr ) ; StringRef RSymName ; RSymI -> getName ( RSymName ) ; MCSymbol * RSym = Ctx . GetOrCreateSymbol ( RSymName ) ; if ( ! RSym -> isVariable ( ) ) RSym -> setVariableValue ( MCConstantExpr :: Create ( RSymAddr , Ctx ) ) ; const MCExpr * RHS = MCSymbolRefExpr :: Create ( RSym , Ctx ) ;

Expr = MCBinaryExpr :: CreateSub ( LHS , RHS , Ctx ) ;


<s> SDNode * OpNode = Op . getNode ( ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , Op . getDebugLoc ( ) , OpNode -> getValueType ( <NUM_LIT> ) , Cond , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> unsigned Opcode = U . MI -> getOpcode ( ) ; unsigned NewOpc = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; unsigned Bits = <NUM_LIT> ; switch ( Opcode ) { default : break ; case <STR_LIT> : if ( is<ISA_LIT>LowRegister ( U . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; } break ; case <STR_LIT> : if ( is<ISA_LIT>LowRegister ( U . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; }


<s> if ( isKernelFunction ( * F ) ) { if ( isSampler ( * I ) || isImage ( * I ) ) { if ( isImage ( * I ) ) { std :: string sname = I -> getName ( ) ; if ( isImageWriteOnly ( * I ) || isImageReadWrite ( * I ) ) { if ( nvptxSubtarget . hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << * CurrentFnSym << <STR_LIT> << paramIndex ; } else { if ( nvptxSubtarget . hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << * CurrentFnSym << <STR_LIT> << paramIndex ; } } else { if ( nvptxSubtarget . hasImageHandles ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << * CurrentFnSym << <STR_LIT> << paramIndex ; } continue ; } } if ( PAL . hasAttribute ( paramIndex + <NUM_LIT> , Attribute :: ByVal ) == false ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = TD -> getABITypeAlignment ( Ty ) ; unsigned sz = TD -> getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; O << <STR_LIT> << sz << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; if ( isKernelFunc ) { if ( PTy ) { O << <STR_LIT> << thePointerTy . getSizeInBits ( ) << <STR_LIT> ; if ( nvptxSubtarget . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( TD , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ;


<s> } <STR_LIT> CC ; SDValue LHS , RHS ; if ( CCVal . getOpcode ( ) == <STR_LIT> ) { LHS = CCVal . getOperand ( <NUM_LIT> ) ; RHS = CCVal . getOperand ( <NUM_LIT> ) ; CC = cast < CondCodeSDNode > ( CCVal -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; } else { LHS = CCVal ; RHS = DAG . getConstant ( <NUM_LIT> , DL , CCVal . getValueType ( ) ) ;


<s> MCPhysReg <ISA_LIT>MachineFunctionInfo :: getNextSystemSGPR ( ) const {

return <STR_LIT> + NumUserSGPRs + NumSystemSGPRs ;


<s> } ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineDominatorTree & MDT = getAnalysis < MachineDominatorTree > ( ) ; const <ISA_LIT>TargetLowering & TLI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetLowering ( ) ; auto & LibInfo = getAnalysis < TargetLibraryInfoWrapperPass > ( ) . getTLI ( ) ; bool Changed = false ; assert ( MRI . isSSA ( ) && <STR_LIT> ) ; for ( auto & MBB : MF ) { DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << '\n' ) ; for ( auto & MI : MBB ) switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ToReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned FromReg = MI . getOperand ( <STR_LIT> ) . getReg ( ) ; Changed |= ReplaceDominatedUses ( MBB , MI , FromReg , ToReg , MRI , MDT ) ; break ; } case <STR_LIT> : case <STR_LIT> : {

MachineOperand & Op1 = MI . getOperand ( <NUM_LIT> ) ;


<s> Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Integer ) ) { SMLoc IntS = getLoc ( ) ; int64_t Val = Tok . getIntVal ( ) ; if ( Val == <NUM_LIT> ) { Parser . Lex ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: RBrac ) { SMLoc RBracS = getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , LBracS , getContext ( ) ) ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , IntS , getContext ( ) ) ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , RBracS , getContext ( ) ) ) ;


<s> else FullFS = <STR_LIT> ; } ParseSubtargetFeatures ( CPUName , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; InstrItins = getInstrItineraryForCPU ( CPUName ) ; if ( In64BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In32BitMode ) ToggleFeature ( <STR_LIT> ) ; else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ; else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || isTargetKFreeBSD ( ) || In64BitMode ) stackAlignment = <NUM_LIT> ; if ( hasAVX512 ( ) || ( hasAVX2 ( ) && hasFastGather ( ) ) ) GatherOverhead = <NUM_LIT> ;

if ( hasAVX512 ( ) ) ScatterOverhead = <NUM_LIT> ;


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; printSOImm ( O , MO . getImm ( ) , TAI ) ;


<s> return ( from == GENERAL_REGS && from == to ) ? <NUM_LIT> : <NUM_LIT> ;


<s> return getComputePGMRSrc1 ( ) ; } uint64_t Reg = S_00B848_VGPRS ( VGPRBlocks ) | S_00B848_SGPRS ( SGPRBlocks ) | S_00B848_PRIORITY ( Priority ) | S_00B848_FLOAT_MODE ( FloatMode ) | S_00B848_PRIV ( Priv ) | S_00B848_DX10_CLAMP ( DX10Clamp ) | S_00B848_DEBUG_MODE ( DebugMode ) | S_00B848_IEEE_MODE ( IEEEMode ) ; switch ( CC ) { case CallingConv :: <ISA_LIT>_PS : Reg |= S_00B028_MEM_ORDERED ( MemOrdered ) ; break ; case CallingConv :: <ISA_LIT>_VS : Reg |= S_00B128_MEM_ORDERED ( MemOrdered ) ; break ; case CallingConv :: <ISA_LIT>_GS : Reg |= S_00B228_WGP_MODE ( WgpMode ) | S_00B228_MEM_ORDERED ( MemOrdered ) ; break ; case CallingConv :: <ISA_LIT>_HS : Reg |= S_00B428_WGP_MODE ( WgpMode ) | S_00B428_MEM_ORDERED ( MemOrdered ) ; break ; default : break ; }


<s> if ( ! MemOpChains2 . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains2 [ <NUM_LIT> ] , MemOpChains2 . size ( ) ) ; Chain = EmitTailCallStoreFPAndRetAddr ( DAG , MF , Chain , LROp , FPOp , SPDiff , is<ISA_LIT>64 , isDarwinABI , dl ) ;

Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , InFlag , dl ) ;


<s> size = atoi ( value ) ; if ( size > small_memory [ type ] . physical_max ) error ( <STR_LIT> , small_memory [ type ] . name ) ; else small_memory [ type ] . max = size ; return true ;


<s> int64_t ImmValue = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned FirstShift = <STR_LIT> ; unsigned SecondShift = <STR_LIT> ; if ( has<ISA_LIT>32r2 ( ) ) { if ( Inst . getOpcode ( ) == <STR_LIT> ) { uint64_t MaxShift = <NUM_LIT> ; uint64_t ShiftValue = ImmValue ; if ( ImmValue != <NUM_LIT> ) ShiftValue = MaxShift - ImmValue ; TOut . emitRRI ( <STR_LIT> , DReg , SReg , ShiftValue , Inst . getLoc ( ) , STI ) ; return false ; } if ( Inst . getOpcode ( ) == <STR_LIT> ) { TOut . emitRRI ( <STR_LIT> , DReg , SReg , ImmValue , Inst . getLoc ( ) , STI ) ; return false ; } return true ; } if ( has<ISA_LIT>32 ( ) ) { if ( ImmValue == <NUM_LIT> ) { TOut . emitRRI ( <STR_LIT> , DReg , SReg , <NUM_LIT> , Inst . getLoc ( ) , STI ) ; return false ; } switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : FirstShift = <STR_LIT> ; SecondShift = <STR_LIT> ; break ;


<s> RegisterSet ( const RegisterSet & RS ) : BitVector ( RS ) {


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


<s> } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , SDLoc ( Addr ) , ValTy ) ; return true ; } }


<s> write_omp_entry ( file , name , buf ) ; name = buf ; } std :: stringstream s ; write_fn_proto ( s , true , name , decl ) ; s << <STR_LIT> ; bool return_in_mem = write_return_type ( s , false , result_type ) ; if ( return_in_mem ) argno = write_arg_type ( s , <NUM_LIT> , argno , ptr_type_node , true ) ; tree args = TYPE_ARG_TYPES ( fntype ) ; bool prototyped = true ; if ( ! args ) { args = DECL_ARGUMENTS ( decl ) ; prototyped = false ; } for ( ; args != NULL_TREE ; args = TREE_CHAIN ( args ) ) { tree type = prototyped ? TREE_VALUE ( args ) : TREE_TYPE ( args ) ; argno = write_arg_type ( s , <NUM_LIT> , argno , type , prototyped ) ; } if ( stdarg_p ( fntype ) ) argno = write_arg_type ( s , ARG_POINTER_REGNUM , argno , ptr_type_node , true ) ; if ( DECL_STATIC_CHAIN ( decl ) || cfun -> machine -> has_chain ) write_arg_type ( s , STATIC_CHAIN_REGNUM , DECL_STATIC_CHAIN ( decl ) ? argno : - <NUM_LIT> , ptr_type_node , true ) ; fprintf ( file , <STR_LIT> , s . str ( ) . c_str ( ) ) ; if ( ! crtl -> is_leaf ) crtl -> is_leaf = leaf_function_p ( ) ; HOST_WIDE_INT sz = get_frame_size ( ) ; bool need_frameptr = sz || cfun -> machine -> has_chain ; int alignment = crtl -> stack_alignment_needed / BITS_PER_UNIT ; if ( ! TARGET_SOFT_STACK ) { if ( cfun -> machine -> has_varadic ) init_frame ( file , STACK_POINTER_REGNUM , UNITS_PER_WORD , crtl -> outgoing_args_size ) ; if ( need_frameptr ) init_frame ( file , FRAME_POINTER_REGNUM , alignment , ROUND_UP ( sz , GET_MODE_SIZE ( DImode ) ) ) ; } else if ( need_frameptr || cfun -> machine -> has_varadic || cfun -> calls_alloca || ( cfun -> machine -> has_simtreg && ! crtl -> is_leaf ) ) init_softstack_frame ( file , alignment , sz ) ; if ( cfun -> machine -> has_simtreg ) { unsigned HOST_WIDE_INT & simtsz = cfun -> machine -> simt_stack_size ; unsigned HOST_WIDE_INT & align = cfun -> machine -> simt_stack_align ; align = MAX ( align , GET_MODE_SIZE ( DImode ) ) ; if ( ! crtl -> is_leaf || cfun -> calls_alloca ) simtsz = HOST_WIDE_INT_M1U ; if ( simtsz == HOST_WIDE_INT_M1U ) simtsz = nvptx_softstack_size ; if ( cfun -> machine -> has_softstack ) simtsz += POINTER_SIZE / <NUM_LIT> ; simtsz = ROUND_UP ( simtsz , GET_MODE_SIZE ( DImode ) ) ; if ( align > GET_MODE_SIZE ( DImode ) ) simtsz += align - GET_MODE_SIZE ( DImode ) ; if ( simtsz ) fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , simtsz ) ;


<s> F -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; int br_code ; switch ( Opc ) { case <STR_LIT> : br_code = <STR_LIT> ; break ; case <STR_LIT> : br_code = <STR_LIT> ; break ; default : br_code = <NUM_LIT> ; }

BuildMI ( BB , dl , TII . get ( br_code ) ) . addMBB ( copy1MBB ) ;


<s> if ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) RecipOp = <STR_LIT> ; else if ( ( VT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( VT == <STR_LIT> && Subtarget . hasAVX ( ) ) ) RecipOp = <STR_LIT> ; else return SDValue ( ) ; TargetRecip Recips = DCI . DAG . getTarget ( ) . Options . Reciprocals ; if ( ! Recips . isEnabled ( RecipOp ) ) return SDValue ( ) ; RefinementSteps = Recips . getRefinementSteps ( RecipOp ) ; return DCI . DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , Op ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) {


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const { return & Subtarget ;


<s> MachineFunction * MF = MBB -> getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; unsigned IndexOperand = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; bool WaveRelease = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; bool WaveDone = MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ; if ( WaveDone && ! WaveRelease ) report_fatal_error ( <STR_LIT> ) ; unsigned OrderedCountIndex = IndexOperand & <NUM_LIT> ; IndexOperand &= ~ <NUM_LIT> ; unsigned CountDw = <NUM_LIT> ; if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) { CountDw = ( IndexOperand >> <NUM_LIT> ) & <NUM_LIT> ; IndexOperand &= ~ ( <NUM_LIT> << <NUM_LIT> ) ; if ( CountDw < <NUM_LIT> || CountDw > <NUM_LIT> ) { report_fatal_error ( <STR_LIT> ) ; } } if ( IndexOperand ) report_fatal_error ( <STR_LIT> ) ; unsigned Instruction = IntrID == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned ShaderType = getDSShaderTypeValue ( * MF ) ; unsigned Offset0 = OrderedCountIndex << <NUM_LIT> ; unsigned Offset1 = WaveRelease | ( WaveDone << <NUM_LIT> ) | ( ShaderType << <NUM_LIT> ) | ( Instruction << <NUM_LIT> ) ; if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) Offset1 |= ( CountDw - <NUM_LIT> ) << <NUM_LIT> ; unsigned Offset = Offset0 | ( Offset1 << <NUM_LIT> ) ; Register M0Val = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Val ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder DS = BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( ValReg ) . addImm ( Offset ) . cloneMemRefs ( MI ) ; if ( ! RBI . constrainGenericRegister ( M0Val , <STR_LIT> , * MRI ) ) return false ;

bool Ret = constrainSelectedInstRegOperands ( * DS , TII , TRI , RBI ) ;


<s> FM . serializeToFaultMapSection ( ) ; OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isKnownWindowsMSVCEnvironment ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream FlagsOS ( Flags ) ; for ( const auto & Function : M ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Function , * Mang ) ; for ( const auto & Global : M . globals ( ) ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Global , * Mang ) ; for ( const auto & Alias : M . aliases ( ) ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Alias , * Mang ) ; FlagsOS . flush ( ) ; if ( ! Flags . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ;


<s> unsigned StackAlign = TFI . getStackAlignment ( ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ;

return DAG . getMergeValues ( Ops1 , dl ) ;


<s> if ( startswith ( s -> named . name , <STR_LIT> ) ) { char * name = ( char * ) alloca ( strlen ( s -> named . name ) + <NUM_LIT> ) ; sprintf ( name , <STR_LIT> , s -> named . name + <NUM_LIT> ) ; return get_section ( name , s -> named . common . flags , NULL ) ; } if ( s == data_section ) return sdata_section ;


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ;

printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ;


<s> return <ISA_LIT>_PREALLOC_LOAD_STORE_OPT_NAME ;


<s> bool isVecListDPairSpaced ( ) const { if ( Kind != k_VectorList ) return false ; if ( isSingleSpacedVectorList ( ) ) return false ;

return ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( VectorList . RegNum ) ) ;


<s> bool llvm :: execMayBeModifiedBeforeAnyUse ( const MachineRegisterInfo & MRI , Register VReg , const MachineInstr & DefMI ) { assert ( MRI . isSSA ( ) && <STR_LIT> ) ; auto * TRI = MRI . getTargetRegisterInfo ( ) ; auto * DefBB = DefMI . getParent ( ) ; const int MaxUseInstScan = <NUM_LIT> ; int NumUseInst = <NUM_LIT> ; for ( auto & UseInst : MRI . use_nodbg_instructions ( VReg ) ) {

if ( UseInst . getParent ( ) != DefBB ) return true ;


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectAddrFI ( SDValue Addr , SDValue & Base ) const { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) {


<s> static rtx nios2_legitimize_constant_address ( rtx addr ) { rtx base , offset ; split_const ( addr , & base , & offset ) ; if ( nios2_tls_symbol_p ( base ) ) base = nios2_legitimize_tls_address ( base ) ; else if ( flag_pic ) base = nios2_load_pic_address ( base , UNSPEC_PIC_SYM , NULL_RTX ) ; else if ( ! nios2_large_constant_allowed ( ) && nios2_symbolic_constant_p ( addr ) ) return nios2_split_large_constant ( addr , gen_reg_rtx ( Pmode ) ) ; else if ( CONST_INT_P ( addr ) ) { HOST_WIDE_INT val = INTVAL ( addr ) ; if ( SMALL_INT ( val ) ) return addr ; else if ( ! nios2_large_constant_allowed ( ) ) return nios2_split_large_constant ( addr , gen_reg_rtx ( Pmode ) ) ;


<s> for ( auto I : predecessors ( Root ) ) if ( Set . insert ( I ) ) DFS ( I , Set ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvttsd_si64 ( __m128d __A ) { long long result = ( ( __v2df ) __A ) [ <NUM_LIT> ] ; return result ;


<s> Scale = <NUM_LIT> ; } break ; case <STR_LIT> : if ( is<ISA_LIT>LowRegister ( U . MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { NewOpc = <STR_LIT> ; Bits = <NUM_LIT> ; Scale = <NUM_LIT> ; } break ; } if ( ! NewOpc ) continue ; unsigned UserOffset = getUserOffset ( U ) ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; if ( ! U . KnownAlignment ) MaxOffs -= <NUM_LIT> ;

if ( isCPEntryInRange ( U . MI , UserOffset , U . CPEMI , MaxOffs , false , true ) ) {


<s> llvm_unreachable ( <STR_LIT> ) ; return false ;


<s> IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Instruction * Root = I ; Value * Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ;

Load = Builder . CreateSelect ( Mask , Load , PassThru ) ;


<s> bool Odd = Const [ <NUM_LIT> ] ; Const . lshrInPlace ( <NUM_LIT> ) ; SDValue Half = DAG . getNode ( <STR_LIT> , DL , VT , N0 , DAG . getConstant ( Const , DL , VT ) ) ; SDValue Double = DAG . getNode ( <STR_LIT> , DL , VT , Half , Half ) ; if ( Odd ) {

Double = DAG . getNode ( <STR_LIT> , DL , VT , Double , N0 ) ;


<s> GetInstSeqLs ( Imm >> Shamt , RemSize - Shamt , SeqLs ) ; AddInstr ( SeqLs , Inst ( SLL , Shamt ) ) ;


<s> LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; EVT RegVT = Ld -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Ld -> getMemoryVT ( ) ; SDLoc dl ( Ld ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; <STR_LIT> Ext = Ld -> getExtensionType ( ) ; bool Fast ; if ( RegVT . is256BitVector ( ) && ! DCI . isBeforeLegalizeOps ( ) && Ext == <STR_LIT> && ( ( Ld -> isNonTemporal ( ) && ! Subtarget . hasInt256 ( ) && Ld -> getAlignment ( ) >= <NUM_LIT> ) || ( TLI . allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , RegVT , * Ld -> getMemOperand ( ) , & Fast ) && ! Fast ) ) ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue ( ) ; unsigned HalfOffset = <NUM_LIT> ; SDValue Ptr1 = Ld -> getBasePtr ( ) ;

SDValue Ptr2 = DAG . getMemBasePlusOffset ( Ptr1 , HalfOffset , dl ) ;


<s> Triple T ( TT ) ; if ( T . isOSDarwin ( ) ) RM = Reloc :: DynamicNoPIC ; else RM = Reloc :: Static ; } if ( CM == CodeModel :: Default ) { Triple T ( TT ) ; if ( ! T . isOSDarwin ( ) && T . getArch ( ) == Triple :: ppc64 ) CM = CodeModel :: Medium ; } X -> InitMCCodeGenInfo ( RM , CM , OL ) ; return X ;


<s> AU . addRequired < <ISA_LIT>StackCacheAnalysisInfo > ( ) ;


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> SDValue <ISA_LIT>DAGToDAGISel :: getUNDEF ( const SDLoc & DL , EVT VT ) const { SDNode * N = CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , VT ) ; return SDValue ( N , <NUM_LIT> ) ;


<s> rtx op0 = XEXP ( op , <NUM_LIT> ) ; rtx op1 = XEXP ( op , <NUM_LIT> ) ; machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; rtx compare_rtx ; rtx cmove_rtx ; rtx clobber_rtx ; if ( ! can_create_pseudo_p ( ) ) return <NUM_LIT> ; if ( ! ( compare_mode == result_mode || ( compare_mode == SFmode && result_mode == DFmode ) || ( compare_mode == DFmode && result_mode == SFmode ) ) ) return false ; switch ( code ) { case EQ : case GE : case GT :


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64Bit ) , DataLayout ( Subtarget . getTargetDataString ( ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , JITInfo ( * this , is64Bit ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ;


<s> unsigned NewOpcode ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; } if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NegVal , N -> getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NegVal ) ;


<s> MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; MCPhysReg Reg = MFI -> getVGPRToAGPRSpill ( Index , Lane ) ; if ( Reg == <STR_LIT> ) return MachineInstrBuilder ( ) ; bool IsStore = MI -> mayStore ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; auto * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; unsigned Dst = IsStore ? Reg : ValueReg ; unsigned Src = IsStore ? ValueReg : Reg ;

unsigned Opc = ( IsStore ^ TRI -> isVGPR ( MRI , Reg ) ) ? <STR_LIT> : <STR_LIT> ;


<s> const auto & Op2 = MI . getOperand ( <NUM_LIT> ) ; switch ( Op2 . getType ( ) ) { case MachineOperand :: MO_Register : { unsigned FromReg = Op2 . getReg ( ) ; unsigned ToReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI . getRegClass ( FromReg ) != MRI . getRegClass ( ToReg ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; return ReplaceDominatedUses ( MBB , MI , FromReg , ToReg , MRI , MDT ) ; } case MachineOperand :: MO_FrameIndex : return false ; default :


<s> if ( C && isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) VL = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>InstructionSelector :: select ( MachineInstr & I , CodeGenCoverage & CoverageInfo ) const { if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCOPY ( I ) ; return true ; } switch ( I . getOpcode ( ) ) { default : return selectImpl ( I , CoverageInfo ) ; case TargetOpcode :: G_ADD : return selectG_ADD ( I ) ; case TargetOpcode :: G_INTTOPTR : case TargetOpcode :: G_BITCAST : return selectCOPY ( I ) ; case TargetOpcode :: G_CONSTANT : case TargetOpcode :: G_FCONSTANT : return selectG_CONSTANT ( I ) ; case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_IMPLICIT_DEF : return selectG_IMPLICIT_DEF ( I ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C : return selectG_INTRIN<ISA_LIT>C ( I , CoverageInfo ) ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Subtarget ( nullptr ) {


<s> unsigned getGDSSize ( ) const { return GDSSize ;


<s> bool shouldFormOverflowOp ( unsigned Opcode , EVT VT , bool MathUsed ) const override {

return TargetLowering :: shouldFormOverflowOp ( Opcode , VT , true ) ;


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const <ISA_LIT>TargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) {


<s> MCSymbol * TlsGetAddr = OutContext . getOrCreateSymbol ( Name ) ; MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; const Module * M = MF -> getFunction ( ) . getParent ( ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( Subtarget -> is32BitELFABI ( ) && isPositionIndependent ( ) ) Kind = MCSymbolRefExpr :: VK_PLT ; const MCExpr * TlsRef = MCSymbolRefExpr :: create ( TlsGetAddr , Kind , OutContext ) ;

if ( Kind == MCSymbolRefExpr :: VK_PLT && Subtarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC ) TlsRef = MCBinaryExpr :: createAdd ( TlsRef , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ;


<s> static DecodeStatus decodeU4ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler * Decoder ) { return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm ) ;


<s> mem = adjust_address ( m_tramp , ptr_mode , TRAMPOLINE_SIZE - ptr_mode_size ) ; emit_move_insn ( mem , chaddr ) ; begin_addr = force_reg ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) ) ;

end_addr = force_reg ( Pmode , plus_constant ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) , TRAMPOLINE_SIZE ) ) ;


<s> bool isPCRelLabel19 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> while ( * a && * b ) { if ( letter ( * a ) && digit ( * b ) ) return - <NUM_LIT> ; if ( digit ( * a ) && letter ( * b ) ) return <NUM_LIT> ; if ( * a != * b ) return * a - * b ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) && ! MI . getOperand ( <NUM_LIT> ) . getImm ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) {

FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> return ( uint16x4_t ) __builtin_neon_vdup_nv4hi ( ( __builtin_neon_hi ) __a ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; <ISA_LIT>ISelAddressMode AM ( <ISA_LIT>ISelAddressMode :: PCI ) ; if ( ! matchAddress ( N , AM ) ) return false ; if ( ! AM . isPCRelative ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; }


<s> * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case LABEL_REF : case SYMBOL_REF : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case CONST_DOUBLE : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case FLOAT_EXTEND : case FLOAT_TRUNCATE : case FLOAT : case UNSIGNED_FLOAT : case FIX : case UNSIGNED_FIX : * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case PLUS : if ( mode == TImode ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } break ; case MULT : cost = GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG ? COSTS_N_INSNS ( <NUM_LIT> ) : COSTS_N_INSNS ( <NUM_LIT> ) ; if ( mode == SImode && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG ) { if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; cost = COSTS_N_INSNS ( <NUM_LIT> ) ; if ( ( val & <NUM_LIT> ) == <NUM_LIT> ) cost = COSTS_N_INSNS ( <NUM_LIT> ) ;

else if ( val > <NUM_LIT> && val < <NUM_LIT> ) cost = COSTS_N_INSNS ( <NUM_LIT> ) ;


<s> EVT SrcVT , DestVT ; SrcVT = TLI . getValueType ( DL , Op -> getType ( ) , true ) ; DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ;

if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ;


<s> void <ISA_LIT>BaseInstrInfo :: getUnconditionalBranch ( MCInst & Branch , const MCSymbolRefExpr * BranchTarget ) const { if ( Subtarget . isThumb ( ) ) Branch . setOpcode ( <STR_LIT> ) ; else if ( Subtarget . isThumb2 ( ) ) Branch . setOpcode ( <STR_LIT> ) ; else Branch . setOpcode ( <STR_LIT> ) ; Branch . addOperand ( MCOperand :: CreateExpr ( BranchTarget ) ) ; Branch . addOperand ( MCOperand :: CreateImm ( <STR_LIT> ) ) ;

Branch . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;


<s> unsigned VF = cast < FixedVectorType > ( ValTy ) -> getNumElements ( ) ; if ( Opcode == Instruction :: ICmp || Opcode == Instruction :: FCmp ) { unsigned PredicateExtraCost = <NUM_LIT> ; if ( I != nullptr ) { switch ( cast < CmpInst > ( I ) -> getPredicate ( ) ) { case CmpInst :: Predicate :: ICMP_NE : case CmpInst :: Predicate :: ICMP_UGE : case CmpInst :: Predicate :: ICMP_ULE : case CmpInst :: Predicate :: ICMP_SGE : case CmpInst :: Predicate :: ICMP_SLE : PredicateExtraCost = <NUM_LIT> ; break ; case CmpInst :: Predicate :: FCMP_ONE : case CmpInst :: Predicate :: FCMP_ORD : case CmpInst :: Predicate :: FCMP_UEQ : case CmpInst :: Predicate :: FCMP_UNO : PredicateExtraCost = <NUM_LIT> ; break ; default : break ; } } unsigned CmpCostPerVector = ( ValTy -> getScalarType ( ) -> isFloatTy ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumVecs_cmp = getNumVectorRegs ( ValTy ) ;

unsigned Cost = ( NumVecs_cmp * ( CmpCostPerVector + PredicateExtraCost ) ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , TargetJT , Index ) ; } assert ( ( NumEntries >> <NUM_LIT> ) == <NUM_LIT> ) ; SDValue ScaledIndex = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Index , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , TargetJT , ScaledIndex ) ;


<s> return data_ref_p ( XEXP ( op , <NUM_LIT> ) ) ;


<s> if ( GET_CODE ( x ) == PLUS && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && ( REG_P ( XEXP ( x , <NUM_LIT> ) ) || GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == SUBREG ) ) { if ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> ) cost = <NUM_LIT> ; } else if ( CONSTANT_ADDRESS_P ( x ) ) {

if ( optimize > <NUM_LIT> && io_address_operand ( x , QImode ) ) cost = <NUM_LIT> ;


<s> void addACC64DSPAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateReg ( getACC64DSPReg ( ) ) ) ;


<s> SDLoc DL ( GSD ) ; const GlobalValue * GV = GSD -> getGlobal ( ) ; EVT PtrVT = Op . getValueType ( ) ; if ( shouldEmitFixup ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT ) ;

else if ( shouldEmitPCReloc ( GV ) ) return buildPCRelGlobalAddress ( DAG , GV , DL , GSD -> getOffset ( ) , PtrVT , <ISA_LIT>InstrInfo :: MO_REL32 ) ;


<s> return Base . Reg != <NUM_LIT> ; } else { return Base . FI != <NUM_LIT> ;


<s> Register RHS = CCMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto Pred = static_cast < CmpInst :: Predicate > ( CCMI -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; if ( CCMIOpc == TargetOpcode :: G_FCMP ) { emitFPCompare ( LHS , RHS , MIB ) ; <STR_LIT> CC1 , CC2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CC1 , CC2 ) ; MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( CC1 ) . addMBB ( DestMBB ) ; if ( CC2 != <STR_LIT> ) MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( CC2 ) . addMBB ( DestMBB ) ; I . eraseFromParent ( ) ; return true ; } auto VRegAndVal = getConstantVRegValWithLookThrough ( RHS , MRI ) ; MachineInstr * LHSMI = getDefIgnoringCopies ( LHS , MRI ) ; if ( VRegAndVal && LHSMI -> getOpcode ( ) != TargetOpcode :: G_AND ) { int64_t C = VRegAndVal -> Value ; if ( C == - <NUM_LIT> && Pred == CmpInst :: ICMP_SGT ) { uint64_t Bit = MRI . getType ( LHS ) . getSizeInBits ( ) - <NUM_LIT> ; emitTestBit ( LHS , Bit , false , DestMBB , MIB ) ; I . eraseFromParent ( ) ; return true ; } if ( C == <NUM_LIT> && Pred == CmpInst :: ICMP_SLT ) { uint64_t Bit = MRI . getType ( LHS ) . getSizeInBits ( ) - <NUM_LIT> ; emitTestBit ( LHS , Bit , true , DestMBB , MIB ) ; I . eraseFromParent ( ) ; return true ; } } if ( ! VRegAndVal ) { std :: swap ( RHS , LHS ) ; VRegAndVal = getConstantVRegValWithLookThrough ( RHS , MRI ) ; LHSMI = getDefIgnoringCopies ( LHS , MRI ) ; } if ( ! VRegAndVal || VRegAndVal -> Value != <NUM_LIT> ) { auto Pred = static_cast < CmpInst :: Predicate > ( CCMI -> getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; emitIntegerCompare ( CCMI -> getOperand ( <NUM_LIT> ) , CCMI -> getOperand ( <NUM_LIT> ) , CCMI -> getOperand ( <NUM_LIT> ) , MIB ) ; const <STR_LIT> CC = changeICMPPredTo<ISA_LIT>CC ( Pred ) ; MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( CC ) . addMBB ( DestMBB ) ; I . eraseFromParent ( ) ; return true ; } if ( tryOptAndIntoCompareBranch ( LHSMI , VRegAndVal -> Value , Pred , DestMBB , MIB ) ) { I . eraseFromParent ( ) ; return true ; } const RegisterBank & RB = * RBI . getRegBank ( LHS , MRI , TRI ) ; if ( RB . getID ( ) != <STR_LIT> ) return false ; if ( Pred != CmpInst :: ICMP_NE && Pred != CmpInst :: ICMP_EQ ) return false ;

const unsigned CmpWidth = MRI . getType ( LHS ) . getSizeInBits ( ) ;


<s> switch ( DECL_MD_FUNCTION_CODE ( fndecl ) ) { case RS6000_BIF_XVSQRTDP : if ( ! RS6000_RECIP_AUTO_RSQRTE_P ( V2DFmode ) ) return NULL_TREE ;

return rs6000_builtin_decls [ RS6000_BIF_RSQRT_2DF ] ;


<s> SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Base , Offset ; unsigned Opc ; std :: tie ( Opc , Base , Offset ) = findAddrModeSVELoadStore ( N , Opc_rr , Opc_ri , N -> getOperand ( IsIntr ? <NUM_LIT> : <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Scale ) ; SDValue Ops [ ] = { N -> getOperand ( IsIntr ? <NUM_LIT> : <NUM_LIT> ) , Base , Offset , Chain } ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Load = CurDAG -> getMachineNode ( Opc , DL , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Load , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( <STR_LIT> + i , DL , VT , SuperReg ) ) ; unsigned ChainIdx = NumVecs ;

ReplaceUses ( SDValue ( N , ChainIdx ) , SDValue ( Load , <NUM_LIT> ) ) ;


<s> return D ( <STR_LIT> , <STR_LIT> , R ( b ) ) ;


<s> HARD_REG_SET cc ; int i ; reg_class_t best = NO_REGS ; unsigned int best_size = <NUM_LIT> ; if ( original_class == limiting_class ) return original_class ; cc = reg_class_contents [ original_class ] & reg_class_contents [ limiting_class ] ; for ( i = <NUM_LIT> ; i < LIM_REG_CLASSES ; i ++ ) { if ( hard_reg_set_subset_p ( reg_class_contents [ i ] , cc ) ) if ( best_size < reg_class_size [ i ] ) { best = ( reg_class_t ) i ; best_size = reg_class_size [ i ] ; } }

if ( best == NO_REGS ) return returned_if_empty ;


<s> for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= undoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; AFI -> recordCPEClone ( i , CPE . CPI ) ; } } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ; CPEntries . clear ( ) ;


<s> struct machine_function GTY ( ( ) ) { int ra_needs_full_frame ; struct rtx_def * eh_stack_adjust ; int interrupt_handler ;


<s> break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ;

AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( Op1 ) . addReg ( Op2 ) ) ;


<s> case TYPE_FDIVD : case TYPE_FSQRTS : case TYPE_FSQRTD : case TYPE_NEON_FP_SQRT_S : case TYPE_NEON_FP_SQRT_D : case TYPE_NEON_FP_SQRT_S_Q : case TYPE_NEON_FP_SQRT_D_Q : case TYPE_NEON_FP_DIV_S : case TYPE_NEON_FP_DIV_D : case TYPE_NEON_FP_DIV_S_Q : case TYPE_NEON_FP_DIV_D_Q :


<s> MachineBasicBlock :: reverse_iterator E = MBB -> rend ( ) ; if ( E == B ) return false ; ++ B ; for ( MachineBasicBlock :: reverse_iterator I = B ; I != E ; ++ I ) { if ( I -> definesRegister ( reg ) ) { return true ; } if ( I -> readsRegister ( reg ) && ( <STR_LIT> ( & * I ) || I -> mayStore ( ) ) ) { canBeSpilled = true ; return true ;


<s> int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; } } if ( Writer -> doesSymbolRequireExternRelocation ( SD ) ) { IsExtern = <NUM_LIT> ; Index = SD -> getIndex ( ) ; if ( ! SD -> getSymbol ( ) . isUndefined ( ) ) FixedValue -= Layout . getSymbolOffset ( SD ) ; } else { const MCSectionData & SymSD = Asm . getSectionData ( SD -> getSymbol ( ) . getSection ( ) ) ; Index = SymSD . getOrdinal ( ) + <NUM_LIT> ;

FixedValue += Writer -> getSectionAddress ( & SymSD ) ;


<s> inline SDValue getImm ( const SDNode * Node , uint64_t Imm ) {

return CurDAG -> getTargetConstant ( Imm , Node -> getValueType ( <NUM_LIT> ) ) ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; unsigned V0 = IsN64 ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( V0 , getPointerTy ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ;

if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ;


<s> if ( SLT == <STR_LIT> ) return LT . first * NElts * get64BitInstrCost ( ) ; if ( ST -> has16BitInsts ( ) && SLT == <STR_LIT> ) NElts = ( NElts + <NUM_LIT> ) / <NUM_LIT> ; unsigned InstRate = getQuarterRateInstrCost ( ) ; if ( ID == <STR_LIT> ) { InstRate = ST -> hasFastFMAF32 ( ) ? getHalfRateInstrCost ( ) : getQuarterRateInstrCost ( ) ; } return LT . first * NElts * InstRate ;


<s> for ( MVT Ty : Types ) Returns . push_back ( MVT2WasmType ( Ty ) ) ;

cast < MCSymbolWasm > ( Symbol ) -> setReturns ( std :: move ( Returns ) ) ;


<s> doubleword_aligned_p = tilepro_function_arg_boundary ( arg . mode , arg . type ) > BITS_PER_WORD ; if ( doubleword_aligned_p ) cum += cum & <NUM_LIT> ; if ( ( cum + ( byte_size + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) > TILEPRO_NUM_ARG_REGS ) return NULL_RTX ;

return gen_rtx_REG ( arg . mode , cum ) ;