<s> BBGen = make_unique < const MachineInstr * [ ] > ( NbReg ) ; std :: fill ( BBGen . get ( ) , BBGen . get ( ) + NbReg , nullptr ) ; BitVector & BBKillSet = Kill [ & MBB ] ; BBKillSet . resize ( NbReg ) ; for ( const MachineInstr & MI : MBB ) { bool IsADRP = MI . getOpcode ( ) == <STR_LIT> ; if ( IsADRP || ! ADRPMode ) for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ( ! ADRPMode && ! MO . isUse ( ) ) || ( ADRPMode && ( ! IsADRP || ! MO . isDef ( ) ) ) ) continue ; unsigned CurReg = MO . getReg ( ) ; MapRegToId :: const_iterator ItCurRegId = RegToId . find ( CurReg ) ; if ( ItCurRegId == RegToId . end ( ) ) continue ; CurReg = ItCurRegId -> second ; if ( ! BBGen [ CurReg ] && ! BBKillSet . test ( CurReg ) ) getSet ( ReachableUses , MBB , CurReg , NbReg ) . insert ( & MI ) ; if ( BBGen [ CurReg ] ) getUses ( ColorOpToReachedUses , CurReg , * BBGen [ CurReg ] ) . insert ( & MI ) ; } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isRegMask ( ) ) continue ; const uint32_t * PreservedRegs = MO . getRegMask ( ) ; for ( const auto Entry : RegToId ) { unsigned Reg = Entry . second ; if ( MachineOperand :: clobbersPhysReg ( PreservedRegs , Entry . first ) ) {

BBGen [ Reg ] = ADRPMode ? & MI : nullptr ;


<s> return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ;


<s> unsigned char <ISA_LIT>Subtarget :: classifyBlockAddressReference ( ) const {


<s> MCAsmParser & Parser = getParser ( ) ; const MCExpr * Value ;

if ( getParser ( ) . parseExpression ( Value ) ) return true ;


<s> Type = ELF :: R_MIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_LDM ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_LO16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_PC16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_DISP ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHER ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHEST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_26_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_PC16_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_CALL16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_DISP ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_LDM ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_DTPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_DTPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_TPREL_LO16 ;


<s> emit_insn ( gen_addsi3 ( reg , reg , tmp ) ) ; * valuep = emit_library_call_value ( get_tls_get_addr ( ) , NULL_RTX , LCT_PURE , Pmode , reg , Pmode ) ; insns = get_insns ( ) ; end_sequence ( ) ; return insns ;


<s> else if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) regno = FIRST_SSE_REG ; else if ( X87_FLOAT_MODE_P ( mode ) && TARGET_FLOAT_RETURNS_IN_80387 ) regno = FIRST_FLOAT_REG ; else regno = AX_REG ; if ( ( fn || fntype ) && ( mode == SFmode || mode == DFmode ) ) { int sse_level = ix86_function_sseregparm ( fntype , fn , false ) ; if ( ( sse_level >= <NUM_LIT> && mode == SFmode ) || ( sse_level == <NUM_LIT> && mode == DFmode ) ) regno = FIRST_SSE_REG ; } gcc_assert ( mode != OImode ) ;

return gen_rtx_REG ( orig_mode , regno ) ;


<s> unsigned int shift_cnt = <NUM_LIT> ; FOR_EACH_VEC_ELT ( LOOP_VINFO_LENS ( loop_vinfo ) , num_vectors_m1 , rgc ) if ( rgc -> type ) shift_cnt += num_vectors_m1 + <NUM_LIT> ;


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> SDValue Res = [ & ] { if ( CP -> isMachineConstantPoolEntry ( ) ) return DAG . getTargetConstantPool ( CP -> getMachineCPVal ( ) , PtrVT , CP -> getAlignment ( ) ) ;

else return DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlignment ( ) ) ;


<s> MCContext & Ctx ; Mangler & Mang ; AsmPrinter & Printer ; public : <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler & mang , AsmPrinter & printer ) : Ctx ( ctx ) , Mang ( mang ) , Printer ( printer ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ;

MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ;


<s> static bool mips_lra_p ( void ) { return mips_lra_flag ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> Function * UpdateDPP = <STR_LIT> ( M , <STR_LIT> , Ty ) ; Function * PermLaneX16 = <STR_LIT> ( M , <STR_LIT> , { } ) ; Function * ReadLane = <STR_LIT> ( M , <STR_LIT> , { } ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; Idx ++ ) { V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , V , B . getInt32 ( DPP :: ROW_SHR0 | <NUM_LIT> << Idx ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; } if ( ST -> hasDPPBroadcasts ( ) ) { V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , V , B . getInt32 ( DPP :: BCAST15 ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , V , B . getInt32 ( DPP :: BCAST31 ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; } else { Value * const PermX = B . CreateCall ( PermLaneX16 , { V , V , B . getInt32 ( - <NUM_LIT> ) , B . getInt32 ( - <NUM_LIT> ) , B . getFalse ( ) , B . getFalse ( ) } ) ; V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , PermX , B . getInt32 ( DPP :: QUAD_PERM_ID ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ;


<s> Register ResVReg = createTypeVReg ( MIRBuilder ) ; auto MIB = MIRBuilder . buildInstr ( <STR_LIT> ) . addDef ( ResVReg ) . addUse ( get<ISA_LIT>TypeID ( SampledType ) ) . addImm ( Dim ) . addImm ( Depth ) . addImm ( Arrayed ) . addImm ( Multisampled ) . addImm ( Sampled ) . addImm ( ImageFormat ) . addImm ( AccessQual ) ; DT . add ( TD , & MIRBuilder . getMF ( ) , ResVReg ) ;


<s> enum rtx_code code = GET_CODE ( operands [ <NUM_LIT> ] ) ; rtx op0 = operands [ <NUM_LIT> ] ; rtx op1 = operands [ <NUM_LIT> ] ;


<s> Or = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Or , Bias ) ; EVT DestVT = Op . getValueType ( ) ; if ( DestVT . bitsLT ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; if ( DestVT . bitsGT ( <STR_LIT> ) ) return DAG . getNode ( <STR_LIT> , dl , DestVT , Sub ) ;


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ;


<s> return IsConstantImm && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Imm ) && ( Imm != <NUM_LIT> ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> if ( lra_in_progress && mode == SDmode ) return DDmode ;


<s> auto * HRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; HII . loadRegFromStackSlot ( B , It , TmpR1 , FI , RC , HRI ) ; expandLoadVec ( B , std :: prev ( It ) , MRI , HII , NewRegs ) ; BuildMI ( B , It , DL , HII . get ( <STR_LIT> ) , DstR ) . addReg ( TmpR1 , RegState :: Kill ) . addReg ( TmpR0 , RegState :: Kill ) ;


<s> } EVT VT = Node -> getValueType ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && VT == XLenVT ) { auto * ConstNode = cast < ConstantSDNode > ( Node ) ; if ( ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } } if ( Opcode == <STR_LIT> ) { SDLoc DL ( Node ) ; SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Qm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; int imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { if ( imm == <NUM_LIT> ) imm = INT32_MIN ; else imm *= - <NUM_LIT> ; }

if ( imm != INT32_MIN ) imm *= ( <NUM_LIT> << shift ) ;


<s> const DataLayout * getDataLayout ( ) const override { return & DL ;


<s> SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue LO , HI ; SDValue Chain = DAG . getCopyToReg ( N -> getOperand ( <NUM_LIT> ) , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDNode * N1 = DAG . getMachineNode ( <STR_LIT> , DL , Tys , Chain ) ; Chain = SDValue ( N1 , <NUM_LIT> ) ; if ( Subtarget . is64Bit ( ) ) { LO = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , SDValue ( N1 , <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ; } else { LO = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , SDValue ( N1 , <NUM_LIT> ) ) ; HI = DAG . getCopyFromReg ( LO . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , LO . getValue ( <NUM_LIT> ) ) ;


<s> SmallVector < MachineBasicBlock * , <NUM_LIT> > Blocks ; for ( auto & MBB : MF ) Blocks . push_back ( & MBB ) ; if ( collectCmovCandidates ( Blocks , AllCmovGroups , true ) ) { for ( auto & Group : AllCmovGroups ) { if ( ForceMemOperand && ! ForceAll && llvm :: none_of ( Group , [ & ] ( MachineInstr * I ) { return I -> mayLoad ( ) ; } ) ) continue ; Changed = true ; convertCmovInstsToBranches ( Group ) ; } } if ( ForceAll ) return Changed ; } SmallVector < MachineLoop * , <NUM_LIT> > Loops ( MLI -> begin ( ) , MLI -> end ( ) ) ;

for ( int i = <NUM_LIT> ; i < ( int ) Loops . size ( ) ; ++ i ) for ( MachineLoop * Child : Loops [ i ] -> getSubLoops ( ) ) Loops . push_back ( Child ) ;


<s> initialize<ISA_LIT>InsertVSETVLIPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } unsigned Opc = ( CallConv == CallingConv :: <ISA_LIT>_INTR ? <STR_LIT> : <STR_LIT> ) ; if ( Flag . getNode ( ) ) return DAG . getNode ( Opc , dl , <STR_LIT> , Chain , Flag ) ;

return DAG . getNode ( Opc , dl , <STR_LIT> , Chain ) ;


<s> ModeIEEERndNear = false ; UseBSBScheduling = false ;


<s> return make_unique < <ISA_LIT>Operand > ( RegNum , Val , S , E ) ;


<s> static bool canLowerToLDG ( MemSDNode * N , const <ISA_LIT>Subtarget & Subtarget , unsigned CodeAddrSpace , MachineFunction * F ) { if ( ! Subtarget . hasLDG ( ) || CodeAddrSpace != <STR_LIT> :: GLOBAL ) return false ; if ( N -> isInvariant ( ) ) return true ; bool IsKernelFn = isKernelFunction ( F -> getFunction ( ) ) ; SmallVector < const Value * , <NUM_LIT> > Objs ;

getUnderlyingObjects ( N -> getMemOperand ( ) -> getValue ( ) , Objs ) ;


<s> AddrRegs [ I ] = MI . getOperand ( DimIdx + I ) . getReg ( ) ; assert ( B . getMRI ( ) -> getType ( AddrRegs [ I ] ) == LLT :: scalar ( <NUM_LIT> ) ) ; }

auto VAddr = B . buildBuildVector ( LLT :: vector ( NumVAddrs , <NUM_LIT> ) , AddrRegs ) ;


<s> void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm8 ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperandEA ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier = nullptr ) ; void printRegisterList ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void EmitStartOfAsmFile ( Module & M ) override ; void EmitEndOfAsmFile ( Module & M ) override ;

void PrintDebugValueComment ( const MachineInstr * MI , raw_ostream & OS ) ;


<s> if ( ! flags ) { fprintf ( stderr , DEBUG_FMT_S , string , <STR_LIT> ) ; return ; } start_column += fprintf ( stderr , DEBUG_FMT_WX , string , flags ) ; cur_column = start_column ; for ( i = <NUM_LIT> ; i < num_elements ; i ++ ) { bool invert = opts [ i ] . invert ; const char * name = opts [ i ] . name ; const char * no_str = <STR_LIT> ; HOST_WIDE_INT mask = opts [ i ] . mask ; size_t len = comma_len + prefix_len + strlen ( name ) ; if ( ! invert ) { if ( ( flags & mask ) == <NUM_LIT> ) { no_str = <STR_LIT> ; len += strlen ( <STR_LIT> ) ; } flags &= ~ mask ; } else { if ( ( flags & mask ) != <NUM_LIT> ) { no_str = <STR_LIT> ; len += strlen ( <STR_LIT> ) ; } flags |= mask ; } cur_column += len ; if ( cur_column > max_column ) { fprintf ( stderr , <STR_LIT> , ( int ) start_column , <STR_LIT> ) ; cur_column = start_column + len ; comma = <STR_LIT> ; } fprintf ( file , <STR_LIT> , comma , prefix , no_str , name ) ; comma = <STR_LIT> ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { switch ( CC ) { case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Cold :


<s> SDValue Table = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; MVT PTy = getPointerTy ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Table ) ; <ISA_LIT>FunctionInfo * AFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDValue UId = DAG . getConstant ( AFI -> createJumpTableUId ( ) , PTy ) ;

SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PTy ) ;


<s> fprintf ( asm_out_file , <STR_LIT> , symbol_name , symbol_name ) ;


<s> auto MovI = MIB . buildInstr ( <STR_LIT> ) . addDef ( DstReg ) . addUse ( SrcReg ) ; if ( auto * GV = dyn_cast < GlobalValue > ( V ) ) { MovI -> addOperand ( MF , MachineOperand :: CreateGA ( GV , MovZ -> getOperand ( <NUM_LIT> ) . getOffset ( ) , Flags ) ) ; } else { MovI -> addOperand ( MF , MachineOperand :: CreateBA ( cast < BlockAddress > ( V ) , MovZ -> getOperand ( <NUM_LIT> ) . getOffset ( ) , Flags ) ) ; } MovI -> addOperand ( MF , MachineOperand :: CreateImm ( Offset ) ) ;

constrainSelectedInstRegOperands ( * MovI , TII , TRI , RBI ) ;


<s> if ( rfn . overloaded_p ) return function_resolver ( location , rfn . instance , rfn . decl , * arglist ) . resolve ( ) ; return NULL_TREE ;


<s> } unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ; } const MCFixupKindInfo & getFixupKindInfo ( MCFixupKind Kind ) const override ; void applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const override ; bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ; } bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * Fragment , const MCAsmLayout & Layout ) const override { return false ; } bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override ; std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>ObjectWriter ( OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned BitSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned Size = ( BitSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -= <NUM_LIT> ; }


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB . getInstr ( ) << <STR_LIT> ) ; unsigned Dst = MIB -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SubDst = RI . getSubReg ( Dst , MVTSrc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; assert ( SubDst && <STR_LIT> ) ; MIB -> setDesc ( Desc ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( SubDst ) ; MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; I ++ ; MachineBasicBlock & MBB = * MIB -> getParent ( ) ; DebugLoc DL = MIB -> getDebugLoc ( ) ; if ( isSigned ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << '\n' ) ; AddSExt ( MBB , I , DL , Dst , MVTSrc , MVTDst ) ;


<s> static SDValue PerformSHLCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , CodeGenOpt :: Level OptLevel ) { if ( OptLevel > <NUM_LIT> ) { if ( SDValue Ret = TryMULWIDECombine ( N , DCI ) ) return Ret ; } return SDValue ( ) ;


<s> emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ; if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ; else old_out = new_out ; value = simplify_gen_subreg ( wmode , value , mode , <NUM_LIT> ) ; if ( is_sync ) aarch64_emit_load_exclusive ( mode , old_out , mem , GEN_INT ( MEMMODEL_RELAXED ) ) ; else aarch64_emit_load_exclusive ( mode , old_out , mem , model_rtx ) ; switch ( code ) { case SET : new_out = value ; break ; case NOT : x = gen_rtx_AND ( wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( new_out , x ) ) ; break ; } aarch64_emit_store_exclusive ( mode , cond , mem , gen_lowpart ( mode , new_out ) , model_rtx ) ; if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , cond , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , cond , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label ) , pc_rtx ) ;

aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ;


<s> assert ( V -> getType ( ) -> isPointerTy ( ) && V -> getType ( ) -> getPointerAddressSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) ; const auto * Ptr = LD -> getPointerOperand ( ) ;

if ( Ptr -> getType ( ) -> getPointerAddressSpace ( ) != <ISA_LIT>AS :: CONSTANT_ADDRESS ) return <ISA_LIT>AS :: UNKNOWN_ADDRESS_SPACE ;


<s> unsigned getLongFormOpcode ( ) const {


<s> const char * StackProbeSymbol = Subtarget -> isTargetWindows ( ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( StackProbeSymbol ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; MI -> eraseFromParent ( ) ; return BB ;


<s> const MIMGInfo * NewInfo = getMIMGOpcodeHelper ( OrigInfo -> BaseOpcode , OrigInfo -> MIMGEncoding , NewChannels , OrigInfo -> VAddrDwords ) ;

return NewInfo ? NewInfo -> Opcode : - <NUM_LIT> ;


<s> <ISA_LIT>ResourceModel ( const TargetSubtargetInfo & STI , const TargetSchedModel * SM ) : SchedModel ( SM ) , TotalPackets ( <NUM_LIT> ) {

ResourcesModel = STI . getInstrInfo ( ) -> CreateTargetScheduleState ( STI ) ;


<s> assert ( <STR_LIT> == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;

return <STR_LIT> == MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> allocateFixedSGPRInputImpl ( CCInfo , & <STR_LIT> , Arg . getRegister ( ) ) ;

} else Arg = allocateSGPR32InputImpl ( CCInfo , & <STR_LIT> , <NUM_LIT> ) ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __blsr_u64 ( unsigned long long __X ) {


<s> return __builtin_aarch64_floorv4sf ( __a ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { emitByte ( Val & <NUM_LIT> , OS ) ; Val >>= <NUM_LIT> ; }


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , Subtarget ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) , TOCLabelID ( <NUM_LIT> ) , SM ( * this ) {


<s> if ( STI . isTargetNaCl ( ) ) { unsigned AddrIdx ; if ( ( isBasePlusOffsetMemoryAccess ( CurrI -> getOpcode ( ) , & AddrIdx ) && baseRegNeedsLoadStoreMask ( CurrI -> getOperand ( AddrIdx ) . getReg ( ) ) ) || CurrI -> modifiesRegister ( <STR_LIT> , STI . getRegisterInfo ( ) ) ) continue ; } bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; unsigned Opcode = ( * Slot ) . getOpcode ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * CurrI ) == <NUM_LIT> && ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ) continue ; Filler = CurrI ;


<s> const SMLoc S = getLoc ( ) ; StringRef Kind ; unsigned RegNum ; auto Res = tryParseVectorRegister ( RegNum , Kind , RegKind :: SVEPredicateVector ) ; if ( Res != MatchOperand_Success ) return Res ; const auto & KindRes = parseVectorKind ( Kind , RegKind :: SVEPredicateVector ) ; if ( ! KindRes ) return MatchOperand_NoMatch ; unsigned ElementWidth = KindRes -> second ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( RegNum , RegKind :: SVEPredicateVector , ElementWidth , S , getLoc ( ) , getContext ( ) ) ) ; if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { if ( parseOperand ( Operands , false , false ) ) return MatchOperand_NoMatch ; } if ( getTok ( ) . isNot ( AsmToken :: Slash ) ) return MatchOperand_Success ; if ( ! Kind . empty ( ) ) { Error ( S , <STR_LIT> ) ;


<s> SDLoc DL ( Op ) ; SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; unsigned ShiftRightOp = IsSRA ? <STR_LIT> : <STR_LIT> ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , XLenMinus1 , Shamt ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue ShiftLeftHi1 = DAG . getNode ( <STR_LIT> , DL , VT , Hi , One ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi1 , XLenMinus1Shamt ) ; SDValue LoTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRightLo , ShiftLeftHi ) ; SDValue HiTrue = DAG . getNode ( ShiftRightOp , DL , VT , Hi , Shamt ) ; SDValue LoFalse = DAG . getNode ( ShiftRightOp , DL , VT , Hi , ShamtMinusXLen ) ; SDValue HiFalse = IsSRA ? DAG . getNode ( <STR_LIT> , DL , VT , Hi , XLenMinus1 ) : Zero ; SDValue CC = DAG . getSetCC ( DL , VT , ShamtMinusXLen , Zero , <STR_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , CC , LoTrue , LoFalse ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , CC , HiTrue , HiFalse ) ; SDValue Parts [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Parts , DL ) ;


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ;

Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) - <NUM_LIT> ) ) ;


<s> unsigned ScratchRsrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRsrcReg == <STR_LIT> || ! MRI . isPhysRegUsed ( ScratchRsrcReg ) ) return <STR_LIT> ; if ( ST . hasSGPRInitBug ( ) || ScratchRsrcReg != TRI -> reservedPrivateSegmentBufferReg ( MF ) ) return ScratchRsrcReg ; unsigned NumPreloaded = ( MFI -> getNumPreloadedSGPRs ( ) + <NUM_LIT> ) / <NUM_LIT> ; ArrayRef < MCPhysReg > AllSGPR128s = getAllSGPR128 ( ST , MF ) ; AllSGPR128s = AllSGPR128s . slice ( std :: min ( static_cast < unsigned > ( AllSGPR128s . size ( ) ) , NumPreloaded ) ) ; for ( MCPhysReg Reg : AllSGPR128s ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) ) { MRI . replaceRegWith ( ScratchRsrcReg , Reg ) ; MFI -> setScratchRSrcReg ( Reg ) ; return Reg ; } }


<s> if ( N -> getOpcode ( ) != <STR_LIT> ) return TM . getCodeModel ( ) == CodeModel :: Small ; Optional < ConstantRange > CR = cast < GlobalAddressSDNode > ( N ) -> getGlobal ( ) -> getAbsoluteSymbolRange ( ) ;

if ( ! CR ) return TM . getCodeModel ( ) == CodeModel :: Small ;


<s> if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ( Reg == <NUM_LIT> ) || MRI . isReserved ( Reg ) ) continue ; bool kill = false ; if ( ! killedRegs . test ( Reg ) ) { kill = true ; for ( MCSubRegIterator SubRegs ( Reg , TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) { if ( LiveRegs . test ( * SubRegs ) ) { kill = false ; break ; } } if ( kill ) kill = ! LiveRegs . test ( Reg ) ; } if ( MO . isKill ( ) != kill ) { DEBUG ( dbgs ( ) << <STR_LIT> << MO << <STR_LIT> ) ; toggleKillFlag ( MI , MO ) ; DEBUG ( MI -> dump ( ) ) ; } killedRegs . set ( Reg ) ; } for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {

MachineOperand & MO = MI -> getOperand ( i ) ;


<s> Register getExceptionPointerRegister ( const Constant * PersonalityFn ) const override {


<s> buildDAGWithRegPressure ( ) ; DEBUG ( for ( SUnit & SU : SUnits ) SU . dumpAll ( this ) ) ; topologicalSort ( ) ; findRootsAndBiasEdges ( TopRoots , BotRoots ) ; SchedImpl -> initialize ( this ) ; initQueues ( TopRoots , BotRoots ) ; SUnitsLinksBackup = SUnits ; IsLowLatencySU . clear ( ) ; LowLatencyOffset . clear ( ) ; IsHighLatencySU . clear ( ) ; IsLowLatencySU . resize ( SUnits . size ( ) , <NUM_LIT> ) ; LowLatencyOffset . resize ( SUnits . size ( ) , <NUM_LIT> ) ; IsHighLatencySU . resize ( SUnits . size ( ) , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ( unsigned ) SUnits . size ( ) ; i != e ; ++ i ) { SUnit * SU = & SUnits [ i ] ; unsigned BaseLatReg ; int64_t OffLatReg ; if ( <ISA_LIT>TII -> isLowLatencyInstruction ( SU -> getInstr ( ) ) ) { IsLowLatencySU [ i ] = <NUM_LIT> ; if ( <ISA_LIT>TII -> getMemOpBaseRegImmOfs ( SU -> getInstr ( ) , BaseLatReg , OffLatReg , TRI ) ) LowLatencyOffset [ i ] = OffLatReg ; } else if ( <ISA_LIT>TII -> isHighLatencyInstruction ( SU -> getInstr ( ) ) ) IsHighLatencySU [ i ] = <NUM_LIT> ; } <ISA_LIT>Scheduler Scheduler ( this ) ; Best = Scheduler . scheduleVariant ( <STR_LIT> , <STR_LIT> ) ; if ( Best . MaxVGPRUsage > <NUM_LIT> ) { std :: vector < std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant >> Variants = { { LatenciesAlone , BlockRegUsageLatency } , { LatenciesGrouped , BlockLatencyRegUsage } , { LatenciesAlonePlusConsecutive , BlockLatencyRegUsage } , } ; for ( std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > v : Variants ) { Temp = Scheduler . scheduleVariant ( v . first , v . second ) ; if ( Temp . MaxVGPRUsage < Best . MaxVGPRUsage ) Best = Temp ; } } if ( Best . MaxVGPRUsage > <NUM_LIT> ) { std :: vector < std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant >> Variants = { { LatenciesAlone , BlockRegUsage } , { LatenciesGrouped , BlockRegUsageLatency } , { LatenciesGrouped , BlockRegUsage } , { LatenciesAlonePlusConsecutive , BlockRegUsageLatency } , { LatenciesAlonePlusConsecutive , BlockRegUsage } } ; for ( std :: pair < <ISA_LIT>SchedulerBlockCreatorVariant , <ISA_LIT>SchedulerBlockSchedulerVariant > v : Variants ) { Temp = Scheduler . scheduleVariant ( v . first , v . second ) ; if ( Temp . MaxVGPRUsage < Best . MaxVGPRUsage ) Best = Temp ; } }


<s> if ( code == SMAX || code == SMIN ) c = GE ; else c = GEU ; if ( code == SMAX || code == UMAX ) target = emit_conditional_move ( dest , c , op0 , op1 , mode , op0 , op1 , mode , <NUM_LIT> ) ; else target = emit_conditional_move ( dest , c , op0 , op1 , mode , op1 , op0 , mode , <NUM_LIT> ) ;


<s> case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } default :


<s> } if ( ST -> is<ISA_LIT>64 ( ) ) return <NUM_LIT> ; return <NUM_LIT> ;


OutStreamer . emitRawComment ( <STR_LIT> + Twine ( header . hsail_version_minor ) , false ) ;


<s> DollarIsPC = true ; SeparatorString = <STR_LIT> ; CommentString = <STR_LIT> ;


<s> if ( C . front ( ) != '{' || C . back ( ) != '}' ) return std :: make_pair ( false , false ) ; StringRef :: const_iterator I , B = C . begin ( ) + <NUM_LIT> , E = C . end ( ) - <NUM_LIT> ; I = std :: find_if ( B , E , isdigit ) ; Prefix = StringRef ( B , I - B ) ;

if ( I == E ) return std :: make_pair ( true , false ) ;


<s> void onLabelParsed ( MCSymbol * Symbol ) override { AC -> onLabelEmited ( Symbol ) ; FreeLabels . insert ( Symbol -> getName ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Symbol -> getName ( ) << <STR_LIT> ) ;


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_Float4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SpillToVSR ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) { DebugLoc dl = Op . getDebugLoc ( ) ; if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) > <NUM_LIT> ) return SDValue ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ;

bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ;


<s> const char * <ISA_LIT>InstPrinter :: getRegisterName ( unsigned RegNo ) { return getRegisterName ( RegNo , ArchRegNames ? <STR_LIT> : <STR_LIT> ) ;


<s> for ( int i = opNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i != opNum ) O << <STR_LIT> ; printOperand ( MI , i , O ) ;


<s> bool iss11_1Imm ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true , true , true ) ;


if ( asm_switch -> nesting_level == <NUM_LIT> ) fprintf ( asm_out_file , <STR_LIT> , prefix , asm_switch -> name , suffix ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool UseFP ; if ( FuncInfo -> isLeafProc ( ) ) { UseFP = false ; } else if ( isFixed ) { UseFP = true ; } else if ( RegInfo -> needsStackRealignment ( MF ) ) { UseFP = false ; } else { UseFP = true ; } int64_t FrameOffset = MF . getFrameInfo ( ) . getObjectOffset ( FI ) + Subtarget . getStackPointerBias ( ) ; if ( UseFP ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return StackOffset :: getFixed ( FrameOffset ) ;


<s> unsigned NumBytes = <NUM_LIT> ; uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + i ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - Info . TargetSize ) ) ; Value <<= Info . TargetOffset ; Mask <<= Info . TargetOffset ;


<s> void <ISA_LIT>InstructionSelector :: beginFunction ( const MachineFunction & MF ) { ForCodeSize = MF . getFunction ( ) -> optForSize ( ) ; AvailableFeatures = computeAvailableFeatures ( & MF , & STI ) ;


<s> if ( Subtarget . hasSSSE3 ( ) ) { assert ( ( ! VT . is512BitVector ( ) || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , ByteVT , Lo , Hi , DAG . getConstant ( ByteRotation , DL , <STR_LIT> ) ) ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( ByteVT == <STR_LIT> && <STR_LIT> ) ; int LoByteShift = <NUM_LIT> - ByteRotation ; int HiByteShift = ByteRotation ; SDValue LoShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getConstant ( LoByteShift , DL , <STR_LIT> ) ) ; SDValue HiShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( HiByteShift , DL , <STR_LIT> ) ) ;

return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoShift , HiShift ) ) ;


<s> void Thumb2InstrInfo :: getNoopForMachoTarget ( MCInst & NopInst ) const {


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _fxsave ( void * __P ) {


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> bool isTargetKnownWindowsMSVC ( ) const { return TargetTriple . isKnownWindowsMSVCEnvironment ( ) ;


<s> bool Ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ; return Ret ;


<s> unsigned getRegisterType ( unsigned Reg ) const { if ( RegInfo . count ( Reg ) ) return RegInfo . lookup ( Reg ) . Type ; else llvm_unreachable ( <STR_LIT> ) ;


<s> Register StoreSrcReg = StoreMI . getValueReg ( ) ; LLT StoreSrcTy = MRI . getType ( StoreSrcReg ) ; if ( ! DefDstTy . isValid ( ) ) return false ; if ( DefDstTy . getSizeInBits ( ) != StoreSrcTy . getSizeInBits ( ) ) return false ;

if ( StoreSrcTy . getSizeInBits ( ) != StoreMI . getMemSizeInBits ( ) ) return false ;


<s> r = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_zero_extendsidi2 ( r , exp ) ) ; return r ;


<s> case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerINTRINSIC_W_CHAIN ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAME_TO_ARGS_OFFSET ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_SETUP_DISPATCH ( Op , DAG ) ; case <STR_LIT> : return LowerINIT_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerADJUST_TRAMPOLINE ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTLZ ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerCTTZ ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerMULH ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerRotate ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op , Subtarget , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , Subtarget , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerADDSUBCARRY ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerAddSub ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDSAT_SUBSAT ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerMINMAX ( Op , DAG ) ;

case <STR_LIT> : return LowerABS ( Op , Subtarget , DAG ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ExpandPseudoPass ( ) { return new <ISA_LIT>ExpandPseudo ( ) ;


<s> bool isValidForTie ( const <ISA_LIT>Operand & Other ) const { if ( Kind != Other . Kind ) return false ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; return false ; case Register : return Reg . RegNum == Other . Reg . RegNum ;


<s> else aarch64_emit_load_exclusive ( mode , rval , mem , model_rtx ) ; if ( strong_zero_p ) x = gen_rtx_NE ( VOIDmode , rval , const0_rtx ) ; else { rtx cc_reg = aarch64_gen_compare_reg_maybe_ze ( NE , rval , oldval , mode ) ; x = gen_rtx_NE ( VOIDmode , cc_reg , const0_rtx ) ; } x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label2 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ; aarch64_emit_store_exclusive ( mode , scratch , mem , newval , model_rtx ) ; if ( ! is_weak ) { if ( aarch64_track_speculation ) { rtx cc_reg = aarch64_gen_compare_reg ( NE , scratch , const0_rtx ) ; x = gen_rtx_NE ( GET_MODE ( cc_reg ) , cc_reg , const0_rtx ) ; } else x = gen_rtx_NE ( VOIDmode , scratch , const0_rtx ) ; x = gen_rtx_IF_THEN_ELSE ( VOIDmode , x , gen_rtx_LABEL_REF ( Pmode , label1 ) , pc_rtx ) ; aarch64_emit_unlikely_jump ( gen_rtx_SET ( pc_rtx , x ) ) ;


<s> break ; } unsigned ArgNo = Arg -> getArgNo ( ) ; if ( F -> getAttributes ( ) . hasAttribute ( ArgNo + <NUM_LIT> , Attribute :: NoAlias ) && ( F -> getAttributes ( ) . hasAttribute ( ArgNo + <NUM_LIT> , Attribute :: ReadNone ) || F -> getAttributes ( ) . hasAttribute ( ArgNo + <NUM_LIT> , Attribute :: ReadOnly ) ) ) { return true ; } }

return AAResultBase :: pointsToConstantMemory ( Loc , OrLocal ) ;


<s> if ( Count % <NUM_LIT> != <NUM_LIT> ) return false ; uint64_t NumNops = Count / <NUM_LIT> ;

for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ;


<s> if ( ! CheckOk ) return false ; if ( ! <ISA_LIT>DisableCompound ) <ISA_LIT>MCInstrInfo :: tryCompound ( MCII , STI , Context , MCB ) ; <ISA_LIT>MCShuffle ( false , MCII , STI , MCB ) ; MCInst InstBundlePreDuplex = MCInst ( MCB ) ; if ( ! <ISA_LIT>DisableDuplex ) { SmallVector < DuplexCandidate , <NUM_LIT> > possibleDuplexes ; possibleDuplexes = <ISA_LIT>MCInstrInfo :: getDuplexPossibilties ( MCII , STI , MCB ) ; <ISA_LIT>MCShuffle ( MCII , STI , Context , MCB , possibleDuplexes ) ; } <ISA_LIT>MCInstrInfo :: padEndloop ( MCB , Context ) ; if ( <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) > HEXAGON_PACKET_SIZE ) return false ;

CheckOk = Check ? Check -> check ( true ) : true ;


<s> unsigned ImmOffs = <STR_LIT> ( MO2 . getImm ( ) ) ; assert ( ImmOffs && <STR_LIT> ) ;

O << <STR_LIT> << ( char ) <STR_LIT> ( MO2 . getImm ( ) ) << ImmOffs ;


<s> Out . EmitBundleLock ( true ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ;


<s> bool isGPR64as32 ( ) const { return Kind == k_Register && Reg . Kind == RegKind :: Scalar && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> dsecond . one_operand_p = true ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) if ( d -> perm [ i ] >= nelt ) { dsecond . perm [ i / <NUM_LIT> + ( i >= lane ? lane / <NUM_LIT> : <NUM_LIT> ) ] = d -> perm [ i ] - nelt ; if ( d -> perm [ i ] - nelt != i / <NUM_LIT> + ( i >= lane ? lane / <NUM_LIT> : <NUM_LIT> ) ) ident2 = false ; dsecond . perm [ i / <NUM_LIT> + ( i >= lane ? lane : lane / <NUM_LIT> ) ] = d -> perm [ i ] - nelt ; } else { dfirst . perm [ i / <NUM_LIT> + ( i >= lane ? lane / <NUM_LIT> : <NUM_LIT> ) ] = d -> perm [ i ] ; if ( d -> perm [ i ] != i / <NUM_LIT> + ( i >= lane ? lane / <NUM_LIT> : <NUM_LIT> ) ) ident1 = false ; dfirst . perm [ i / <NUM_LIT> + ( i >= lane ? lane : lane / <NUM_LIT> ) ] = d -> perm [ i ] ; } if ( two_insn && ! ident1 && ! ident2 ) return false ; if ( ! d -> testing_p ) { if ( ! ident1 ) dfinal . op0 = dfirst . target = gen_reg_rtx ( d -> vmode ) ; if ( ! ident2 ) dfinal . op1 = dsecond . target = gen_reg_rtx ( d -> vmode ) ; if ( d -> perm [ <NUM_LIT> ] >= nelt ) std :: swap ( dfinal . op0 , dfinal . op1 ) ; } bool ok ; rtx_insn * seq1 = NULL , * seq2 = NULL ; if ( ! ident1 ) { start_sequence ( ) ; ok = expand_vec_perm_1 ( & dfirst ) ; seq1 = get_insns ( ) ; end_sequence ( ) ; if ( ! ok ) return false ; } if ( ! ident2 ) { start_sequence ( ) ; ok = expand_vec_perm_1 ( & dsecond ) ; seq2 = get_insns ( ) ; end_sequence ( ) ; if ( ! ok ) return false ; } if ( d -> testing_p ) return true ; for ( i = <NUM_LIT> ; i < nelt ; i ++ ) {


<s> unsigned Align = DAG . getDataLayout ( ) . getPreferredAlignment ( GVar ) ; unsigned RequiredPadding = <NUM_LIT> - ( Size % <NUM_LIT> ) ; bool PaddingPossible = RequiredPadding == <NUM_LIT> || ( CDAInit && CDAInit -> isString ( ) ) ; if ( ! PaddingPossible || Align > <NUM_LIT> || Size > ConstpoolPromotionMaxSize || Size == <NUM_LIT> ) return SDValue ( ) ; unsigned PaddedSize = Size + ( ( RequiredPadding == <NUM_LIT> ) ? <NUM_LIT> : RequiredPadding ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) && Size > <NUM_LIT> ) if ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> >= ConstpoolPromotionMaxTotal ) return SDValue ( ) ; if ( ! allUsersAreInFunction ( GVar , & F ) ) return SDValue ( ) ; if ( RequiredPadding != <NUM_LIT> ) { StringRef S = CDAInit -> getAsString ( ) ; SmallVector < uint8_t , <NUM_LIT> > V ( S . size ( ) ) ; std :: copy ( S . bytes_begin ( ) , S . bytes_end ( ) , V . begin ( ) ) ; while ( RequiredPadding -- ) V . push_back ( <NUM_LIT> ) ;

Init = ConstantDataArray :: get ( * DAG . getContext ( ) , V ) ;


<s> EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getEVTString ( ) << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > <NUM_LIT> ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ;

InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ;


<s> CCAssignFn * <ISA_LIT>TargetLowering :: getRetCCAssignFn ( CallingConv :: ID CallConv ) const { switch ( CallConv ) {

default : llvm_unreachable ( <STR_LIT> ) ;


<s> static int v850_arg_partial_bytes ( cumulative_args_t cum_v , const function_arg_info & arg ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int size , align ; if ( ! arg . named ) return <NUM_LIT> ; size = arg . promoted_size_in_bytes ( ) ; if ( size < <NUM_LIT> ) size = <NUM_LIT> ; if ( ! TARGET_GCC_ABI ) align = UNITS_PER_WORD ;

else if ( arg . type ) align = TYPE_ALIGN ( arg . type ) / BITS_PER_UNIT ;


<s> unsigned NumElems = InVT . getVectorNumElements ( ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; SmallVector < int , <NUM_LIT> > ShufMask1 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask1 [ i ] = i ; SDValue OpLo = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask1 [ <NUM_LIT> ] ) ; SmallVector < int , <NUM_LIT> > ShufMask2 ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) ShufMask2 [ i ] = i + NumElems / <NUM_LIT> ;

SDValue OpHi = DAG . getVectorShuffle ( InVT , dl , In , Undef , & ShufMask2 [ <NUM_LIT> ] ) ;


<s> vmovl_high_u16 ( uint16x8_t a ) { uint32x4_t result ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> if ( getMemOpBaseRegImmOfsWidth ( MIa , BaseRegA , OffsetA , WidthA , TRI ) && getMemOpBaseRegImmOfsWidth ( MIb , BaseRegB , OffsetB , WidthB , TRI ) ) { if ( BaseRegA == BaseRegB ) { int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB ; int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ; if ( LowOffset + LowWidth <= HighOffset ) return true ; } }


<s> SDValue getMergeValues ( ArrayRef < SDValue > Values ) const { return DAG . getMergeValues ( Values , DL ) ;


<s> assert ( Emitted && <STR_LIT> ) ; ( void ) Emitted ; ArgVT = VA . getLocVT ( ) ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT> ) return false ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; if ( ! ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) ) ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , VA . getLocReg ( ) ) . addReg ( NextVA . getLocReg ( ) , RegState :: Define ) . addReg ( Arg ) ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; RegArgs . push_back ( NextVA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; Address Addr ; Addr . BaseType = Address :: RegBase ; Addr . Base . Reg = <STR_LIT> ;

Addr . Offset = VA . getLocMemOffset ( ) ;


<s> MCInstrDesc MCID = MI -> getDesc ( ) ; unsigned E = MI -> isCall ( ) || MI -> isReturn ( ) ? MCID . getNumOperands ( ) : MI -> getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I != E ; ++ I ) {

const MachineOperand & MO = MI -> getOperand ( I ) ;


<s> return <ISA_LIT>_EXPAND_PSEUDO_NAME ;


<s> unsigned <ISA_LIT>TTIImpl :: getHardwareNumberOfRegisters ( bool Vec ) const { if ( ST -> getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return <NUM_LIT> ; return <NUM_LIT> * <NUM_LIT> ;


<s> if ( isUnalignedLoadStore ( Opc ) ) { MCInst Directive ; Directive . setOpcode ( <STR_LIT> ) ; OutStreamer . EmitInstruction ( Directive ) ; OutStreamer . EmitInstruction ( TmpInst0 ) ; Directive . setOpcode ( <STR_LIT> ) ; OutStreamer . EmitInstruction ( Directive ) ;


<s> return ; } if ( BitCastInst * Op = dyn_cast < BitCastInst > ( I . getOperand ( <NUM_LIT> ) ) ) { if ( Op -> getSrcTy ( ) == i128 ) {

I . replaceAllUsesWith ( Op -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( isJmpInstr ( * Inst , DestMBB ) && MBB . getNumber ( ) == DestMBB -> getNumber ( ) ) IsDestination = true ; } } if ( ! <ISA_LIT>CompressJumps ) { prevMI = nullptr ; } for ( MachineBasicBlock :: iterator I = BegBB , E = EndBB ; I != E ; ) { MachineInstr & MI = * I ; ++ I ; if ( MI . isDebugInstr ( ) ) continue ; bool isLoopEndN = false ; if ( I != E ) { int num = <NUM_LIT> ; for ( MachineBasicBlock :: iterator X = I ; X != E ; ++ X ) { if ( X != E ) { if ( ( * X ) . getOpcode ( ) == <STR_LIT> ) { isLoopEndN = true ; break ; } if ( ! ( * X ) . isDebugInstr ( ) ) { num ++ ;


<s> if ( ( ( bisa & ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) == ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) && ( isa & ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ) != <NUM_LIT> ) isa |= ( OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 ) ; if ( ( ( bisa & ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) == ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) && ( isa & ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ) != <NUM_LIT> ) isa |= ( OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_FMA4 ) ; if ( ( ( ( bisa & ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) || ( bisa2 & OPTION_MASK_ISA2_AVXVNNI ) != <NUM_LIT> ) && ( ( ( isa & ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) == ( OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ) ) || ( isa2 & OPTION_MASK_ISA2_AVXVNNI ) != <NUM_LIT> ) ) { isa |= OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VL ; isa2 |= OPTION_MASK_ISA2_AVXVNNI ; } if ( ( bisa & OPTION_MASK_ISA_MMX ) && ! TARGET_MMX && TARGET_MMX_WITH_SSE && fcode != IX86_BUILTIN_MASKMOVQ ) { bisa &= ~ OPTION_MASK_ISA_MMX ; bisa |= OPTION_MASK_ISA_SSE2 ; } if ( pbisa ) * pbisa = bisa ;


<s> std :: vector < MachineInstr * > NewMIs ; if ( isPre ) { if ( isLoad ) MemMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( MemOpc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( WBReg ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; else MemMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( MemOpc ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( WBReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; NewMIs . push_back ( MemMI ) ; NewMIs . push_back ( UpdateMI ) ; } else { if ( isLoad ) MemMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( MemOpc ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( BaseReg ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; else MemMI = BuildMI ( MF , MI . getDebugLoc ( ) , get ( MemOpc ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( BaseReg ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Pred ) ; if ( WB . isDead ( ) ) UpdateMI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; NewMIs . push_back ( UpdateMI ) ; NewMIs . push_back ( MemMI ) ; } if ( LV ) { for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) { unsigned Reg = MO . getReg ( ) ; LiveVariables :: VarInfo & VI = LV -> getVarInfo ( Reg ) ; if ( MO . isDef ( ) ) { MachineInstr * NewMI = ( Reg == WBReg ) ? UpdateMI : MemMI ; if ( MO . isDead ( ) ) LV -> addVirtualRegisterDead ( Reg , * NewMI ) ; } if ( MO . isUse ( ) && MO . isKill ( ) ) { for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { MachineInstr * NewMI = NewMIs [ j ] ; if ( ! NewMI -> readsRegister ( Reg ) ) continue ; LV -> addVirtualRegisterKilled ( Reg , * NewMI ) ; if ( VI . removeKill ( MI ) ) VI . Kills . push_back ( NewMI ) ; break ; }


<s> <ISA_LIT>Scheduler ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) {


<s> BTFTypeTag :: BTFTypeTag ( uint32_t BaseTypeId , int ComponentIdx , StringRef Tag ) : Tag ( Tag ) { Kind = <STR_LIT> ; BTFType . Info = Kind << <NUM_LIT> ; BTFType . Type = BaseTypeId ;


<s> return true ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; Opc = <STR_LIT> ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { return true ; } assert ( Opc != <STR_LIT> && <STR_LIT> ) ; if ( Opc == <STR_LIT> ) { unsigned BaseReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Scale = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned IndexReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( DestReg == <STR_LIT> ) ; assert ( Scale == <NUM_LIT> ) ; assert ( BaseReg == <STR_LIT> ) ; assert ( IndexReg == <NUM_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; Opc = <STR_LIT> ; } else { auto NextMBBI = MBBI ; ++ NextMBBI ; BuildMI ( MBB , NextMBBI , MBBI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; MIBundleBuilder ( MBB , MBBI , NextMBBI ) ; finalizeBundle ( MBB , MBBI . getInstrIterator ( ) ) ; return true ; } }

if ( Opc == <STR_LIT> && MatchesSPAdj ( MI ) ) {


<s> static <ISA_LIT>Operand * CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Immediate ) ; Op -> Imm . Val = Val ; Op -> StartLoc = S ;


<s> SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SExtValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) ) ; SDValue MaskedValue = DAG . getZeroExtendInReg ( SExtValue , DL , MemVT ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( Mask , DL , <STR_LIT> ) , ShiftAmt ) ; DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DstMask , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , DstMask ) ; SDValue Value = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , ShiftedValue ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Value , Ptr , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> , true ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <STR_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinaryPartword ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwapPartword ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return emitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> :


<s> static DecodeStatus DecodeIntRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;

unsigned Reg = IntRegDecoderTable [ RegNo ] ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetMC ( ) { TargetRegistry :: RegisterMCAsmInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstrInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCAsmBackend ) ; TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ;

TargetRegistry :: RegisterAsmTargetStreamer ( getThe<ISA_LIT>Target ( ) , createAsmTargetStreamer ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { emitFrameDirective ( ) ;


<s> } unsigned SrcReg1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; SrcReg1 = constrainOperandRegClass ( TII . get ( Opc ) , SrcReg1 , <NUM_LIT> ) ; SrcReg2 = constrainOperandRegClass ( TII . get ( Opc ) , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ;


<s> unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

unsigned Opcode = getOpcodeForOffset ( isHighReg ( Reg ) ? HighOpcode : LowOpcode , MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> void <ISA_LIT>GenInsert :: dump_map ( ) const { using iterator = IFMapType :: const_iterator ; for ( iterator I = IFMap . begin ( ) , E = IFMap . end ( ) ; I != E ; ++ I ) { dbgs ( ) << <STR_LIT> << printReg ( I -> first , HRI ) << <STR_LIT> ;


<s> unsigned FrameReg = getFrameRegister ( MF ) ; int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; unsigned reg = MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , ++ II , dl , TII . get ( <STR_LIT> ) , reg ) . addReg ( reg ) . addImm ( Offset ) ; return ; } int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { llvm_unreachable ( <STR_LIT> ) ; } MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> case <STR_LIT> : return PerformADDCCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformADDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformSUBCombine ( N , DCI ) ; case <STR_LIT> : return PerformMULCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformXORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return PerformBFICombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVRRDCombine ( N , DCI ) ; case <STR_LIT> : return PerformVMOVDRRCombine ( N , DCI . DAG ) ; case <STR_LIT> : return PerformSTORECombine ( N , DCI ) ; case <STR_LIT> : return PerformBUILD_VECTORCombine ( N , DCI ) ; case <STR_LIT> : return PerformInsertEltCombine ( N , DCI ) ;

case <STR_LIT> : return PerformVECTOR_SHUFFLECombine ( N , DCI . DAG ) ;


<s> case FB_REGNO : return FB_REGS ; case SP_REGNO : return SP_REGS ; case FLG_REGNO : return FLG_REGS ; default : if ( IS_MEM_REGNO ( regno ) ) return MEM_REGS ;


<s> void <ISA_LIT>ElfTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { bool isAAPCS_ABI = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . TargetABI == <ISA_LIT>TargetMachine :: <STR_LIT> ; TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ;


return create<ISA_LIT>ELFStreamer ( Ctx , MAB , _OS , _Emitter , RelaxAll , NoExecStack ) ;


<s> assert ( Register :: isPhysicalRegister ( Reg ) ) ; assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg ) ) { const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; Reg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; } O << <ISA_LIT>InstPrinter :: getRegisterName ( Reg ) ; break ; } case MachineOperand :: MO_Immediate : { O << '#' ; unsigned TF = MO . getTargetFlags ( ) ; if ( TF == <STR_LIT> ) O << <STR_LIT> ; else if ( TF == <STR_LIT> ) O << <STR_LIT> ; O << MO . getImm ( ) ; break ; } case MachineOperand :: MO_MachineBasicBlock : MO . getMBB ( ) -> getSymbol ( ) -> print ( O , MAI ) ; return ; case MachineOperand :: MO_GlobalAddress : { PrintSymbolOperand ( MO , O ) ; break ; } case MachineOperand :: MO_ConstantPoolIndex : if ( Subtarget -> genExecuteOnly ( ) ) llvm_unreachable ( <STR_LIT> ) ; GetCPISymbol ( MO . getIndex ( ) ) -> print ( O , MAI ) ; break ;


<s> void <ISA_LIT>InstructionSelector :: composePtr ( MachineIRBuilder & Builder , Register Dst , Register Lo , Register Hi ) { auto RegSeq = Builder . buildInstr ( <STR_LIT> ) . addDef ( Dst ) . addUse ( Lo ) . addImm ( <STR_LIT> ) . addUse ( Hi ) . addImm ( <STR_LIT> ) ;


<s> LEONMachineFunctionPass ( tm , ID ) {


<s> static void printMasking ( raw_ostream & OS , const MCInst * MI , const MCInstrInfo & MCII ) { const MCInstrDesc & Desc = MCII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; if ( ! ( TSFlags & <STR_LIT> ) ) return ; bool MaskWithZero = ( TSFlags & <STR_LIT> ) ; unsigned MaskOp = Desc . getNumDefs ( ) ; if ( Desc . getOperandConstraint ( MaskOp , MCOI :: TIED_TO ) != - <NUM_LIT> ) ++ MaskOp ; const char * MaskRegName = getRegName ( MI -> getOperand ( MaskOp ) . getReg ( ) ) ; OS << <STR_LIT> << MaskRegName << <STR_LIT> ; if ( MaskWithZero ) OS << <STR_LIT> ;


<s> BB -> moveAfter ( JTBB ) ; OldPrior -> updateTerminator ( ) ; BB -> updateTerminator ( ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return nullptr ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ JTBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; if ( isThumb2 ) BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ;

else BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( Subtarget -> hasSIMD128 ( ) ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; } computeRegisterProperties ( Subtarget -> getRegisterInfo ( ) ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto T : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , T , Legal ) ; for ( auto CC : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setCondCodeAction ( CC , T , Expand ) ; for ( auto Op : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Op , T , Expand ) ; for ( auto Op : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Op , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Expand ) ; setOperationAction ( <STR_LIT> , T , Expand ) ; setLoadExtAction ( <STR_LIT> , T , <STR_LIT> , Expand ) ; setTruncStoreAction ( T , <STR_LIT> , Expand ) ; } for ( auto T : { <STR_LIT> , <STR_LIT> } ) { for ( auto Op : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) {


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;

int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , <NUM_LIT> , CCInfo . getInRegsParamsCount ( ) , <NUM_LIT> , ArgOffset , <NUM_LIT> , ForceMutable , <NUM_LIT> , TotalArgRegsSaveSize ) ;


<s> bool <ISA_LIT>ExpandAtomicPseudo :: runOnMachineFunction ( MachineFunction & MF ) { TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; bool Modified = false ;

for ( auto & MBB : MF ) Modified |= expandMBB ( MBB ) ;


<s> bool <ISA_LIT>CallLowering :: LowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function :: ArgumentListType & Args , const SmallVectorImpl < unsigned > & VRegs ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = * MF . getFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; unsigned NumArgs = Args . size ( ) ; Function :: const_arg_iterator CurOrigArg = Args . begin ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i , ++ CurOrigArg ) { MVT ValVT = <STR_LIT> ( CurOrigArg -> getType ( ) ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; bool Res = AssignFn ( i , ValVT , ValVT , CCValAssign :: Full , <STR_LIT> ( ) , CCInfo ) ; assert ( ! Res && <STR_LIT> ) ; ( void ) Res ; } assert ( ArgLocs . size ( ) == Args . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; MIRBuilder . getMBB ( ) . addLiveIn ( VA . getLocReg ( ) ) ; MIRBuilder . buildInstr ( TargetOpcode :: COPY , VRegs [ i ] , VA . getLocReg ( ) ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : break ; case CCValAssign :: AExt :


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> void <ISA_LIT>DAGToDAGISel :: PreprocessISelDAG ( ) { auto getNodes = [ this ] ( ) -> std :: vector < SDNode * > { std :: vector < SDNode * > T ; T . reserve ( CurDAG -> allnodes_size ( ) ) ; for ( SDNode & N : CurDAG -> allnodes ( ) ) T . push_back ( & N ) ; return T ; } ; ppSimplifyOrSelect0 ( getNodes ( ) ) ; ppAddrReorderAddShl ( getNodes ( ) ) ; ppAddrRewriteAndSrl ( getNodes ( ) ) ; ppHoistZextI1 ( getNodes ( ) ) ; DEBUG_WITH_TYPE ( <STR_LIT> , {


<s> MaskUnpackCost = getScalarizationOverhead ( MaskTy , DemandedElts , false , true ) ; int ScalarCompareCost = getCmpSelInstrCost ( Instruction :: ICmp , Type :: getInt1Ty ( SrcVTy -> getContext ( ) ) , nullptr , CmpInst :: BAD_ICMP_PREDICATE , CostKind ) ; int BranchCost = getCFInstrCost ( Instruction :: Br , CostKind ) ; MaskUnpackCost += VF * ( BranchCost + ScalarCompareCost ) ; } int MemoryOpCost = VF * getMemoryOpCost ( Opcode , SrcVTy -> getScalarType ( ) , MaybeAlign ( Alignment ) , AddressSpace , CostKind ) ; int InsertExtractCost = <NUM_LIT> ; if ( Opcode == Instruction :: Load ) for ( unsigned i = <NUM_LIT> ; i < VF ; ++ i ) InsertExtractCost += getVectorInstrCost ( Instruction :: InsertElement , SrcVTy , i ) ;

else for ( unsigned i = <NUM_LIT> ; i < VF ; ++ i ) InsertExtractCost += getVectorInstrCost ( Instruction :: ExtractElement , SrcVTy , i ) ;


<s> sp = stack_pointer_rtx ; i = <NUM_LIT> ; if ( return_p ) { RTVEC_ELT ( vec , i ) = ret_rtx ; i ++ ; } for ( j = <NUM_LIT> ; j < nregs ; j ++ ) { rtx lhs , rhs ; if ( pop_p ) { lhs = gen_rtx_REG ( SImode , regno + j ) ; rhs = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp , ( nregs - j - <NUM_LIT> ) * <NUM_LIT> ) ) ; } else { lhs = gen_rtx_MEM ( SImode , plus_constant ( Pmode , sp , ( j + <NUM_LIT> ) * - <NUM_LIT> ) ) ; rhs = gen_rtx_REG ( SImode , regno + j ) ; } RTVEC_ELT ( vec , i + j ) = gen_rtx_SET ( VOIDmode , lhs , rhs ) ; } offset = GEN_INT ( ( pop_p ? nregs : - nregs ) * <NUM_LIT> ) ; RTVEC_ELT ( vec , i + j ) = gen_rtx_SET ( VOIDmode , sp , gen_rtx_PLUS ( Pmode , sp , offset ) ) ; x = gen_rtx_PARALLEL ( VOIDmode , vec ) ; if ( ! pop_p ) x = Fpa ( x ) ; if ( return_p ) emit_jump_insn ( x ) ; else emit_insn ( x ) ;


<s> MBBVector ExitBlks ; LoopRep -> getExitBlocks ( ExitBlks ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > ExitBlkSet ; for ( unsigned i = <NUM_LIT> , e = ExitBlks . size ( ) ; i < e ; ++ i ) ExitBlkSet . insert ( ExitBlks [ i ] ) ; assert ( ExitBlkSet . size ( ) == <NUM_LIT> ) ; MachineBasicBlock * ExitBlk = * ExitBlks . begin ( ) ; assert ( ExitBlk && <STR_LIT> ) ; MBBVector LatchBlks ; typedef GraphTraits < Inverse < MachineBasicBlock * >> InvMBBTraits ; InvMBBTraits :: ChildIteratorType PI = InvMBBTraits :: child_begin ( LoopHeader ) , PE = InvMBBTraits :: child_end ( LoopHeader ) ; for ( ; PI != PE ; PI ++ ) { if ( LoopRep -> contains ( * PI ) ) LatchBlks . push_back ( * PI ) ; } for ( unsigned i = <NUM_LIT> , e = ExitingMBBs . size ( ) ; i < e ; ++ i ) mergeLoopbreakBlock ( ExitingMBBs [ i ] , ExitBlk ) ; for ( unsigned i = <NUM_LIT> , e = LatchBlks . size ( ) ; i < e ; ++ i ) settleLoopcontBlock ( LatchBlks [ i ] , LoopHeader ) ; int Match = <NUM_LIT> ; do { Match = <NUM_LIT> ; Match += serialPatternMatch ( LoopHeader ) ; Match += ifPatternMatch ( LoopHeader ) ; } while ( Match > <NUM_LIT> ) ; mergeLooplandBlock ( LoopHeader , ExitBlk ) ; MachineLoop * ParentLoop = LoopRep -> getParentLoop ( ) ; if ( ParentLoop ) MLI -> changeLoopFor ( LoopHeader , ParentLoop ) ; else MLI -> removeBlock ( LoopHeader ) ;


<s> return StringRef ( Tok . Data , Tok . Length ) ;


if ( ! isSingleSpacedVectorList ( ) ) return false ;


<s> memset ( info , <NUM_LIT> , sizeof ( * info ) ) ; info -> gpr_offset = cum -> num_gprs ; info -> fpr_offset = cum -> num_fprs ; if ( named ) { riscv_aggregate_field fields [ <NUM_LIT> ] ; unsigned fregno = fpr_base + info -> fpr_offset ; unsigned gregno = gpr_base + info -> gpr_offset ; if ( ( info -> num_fprs = riscv_pass_aggregate_in_fpr_pair_p ( type , fields ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( info -> num_fprs ) { case <NUM_LIT> : return riscv_pass_fpr_single ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) ) ; case <NUM_LIT> : return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , fregno + <NUM_LIT> , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; default : gcc_unreachable ( ) ; } if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : return gen_rtx_REG ( mode , fregno ) ;


<s> rtx predec = gen_rtx_MEM ( SImode , predec1 ) ; rtx insn ; tree attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ; bool all = lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE ; tree kspisusp = lookup_attribute ( <STR_LIT> , attrs ) ; if ( kspisusp ) { insn = emit_move_insn ( spreg , gen_rtx_REG ( Pmode , REG_USP ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( fkind == EXCPT_HANDLER ) { insn = emit_insn ( gen_addsi3 ( spreg , spreg , GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } insn = emit_move_insn ( predec , gen_rtx_REG ( SImode , REG_ASTAT ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( ! current_function_is_leaf ) all = true ; expand_prologue_reg_save ( spreg , all , true ) ; for ( i = REG_P7 + <NUM_LIT> ; i < REG_CC ; i ++ ) if ( all || regs_ever_live [ i ] || ( ! leaf_function_p ( ) && call_used_regs [ i ] ) ) { if ( i == REG_A0 || i == REG_A1 ) insn = emit_move_insn ( gen_rtx_MEM ( PDImode , predec1 ) , gen_rtx_REG ( PDImode , i ) ) ; else insn = emit_move_insn ( predec , gen_rtx_REG ( SImode , i ) ) ;


<s> if ( CachedEStackSize == - <NUM_LIT> ) { CachedEStackSize = MF . getFrameInfo ( ) . estimateStackSize ( MF ) ; } return CachedEStackSize > <NUM_LIT> ;


<s> return ( int8x16_t ) __builtin_aarch64_shaddv16qi ( __a , __b ) ;


<s> if ( UI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( UI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( cast < RegisterSDNode > ( UI -> getOperand ( <NUM_LIT> ) ) -> getReg ( ) != <STR_LIT> ) return false ; for ( SDNode :: use_iterator FlagUI = UI -> use_begin ( ) , FlagUE = UI -> use_end ( ) ; FlagUI != FlagUE ; ++ FlagUI ) { if ( FlagUI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( ! FlagUI -> isMachineOpcode ( ) ) return false ; switch ( FlagUI -> getMachineOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; getParser ( ) . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } getParser ( ) . Lex ( ) ; return false ;


<s> printImplicitDef ( const MachineInstr * MI , raw_ostream & O ) const { O << <STR_LIT> ;


<s> getAssembler ( ) . setIsThumbFunc ( Symbol ) ;


<s> return false ; case V4DImode : if ( ! TARGET_64BIT ) return false ; case V4DFmode : case V8SFmode : case V8SImode : case V16HImode : case V32QImode : case V4SFmode : case V4SImode : case V8HImode : case V4HImode : break ; case V16QImode : if ( TARGET_SSE4_1 ) break ; wmode = V8HImode ; goto widen ; case V8QImode : wmode = V4HImode ; goto widen ; widen : x = XVECEXP ( vals , <NUM_LIT> , one_var ^ <NUM_LIT> ) ; if ( one_var & <NUM_LIT> ) { var = convert_modes ( HImode , QImode , var , true ) ; var = expand_simple_binop ( HImode , ASHIFT , var , GEN_INT ( <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; x = GEN_INT ( INTVAL ( x ) & <NUM_LIT> ) ; } else { var = convert_modes ( HImode , QImode , var , true ) ; x = gen_int_mode ( INTVAL ( x ) << <NUM_LIT> , HImode ) ; }

if ( x != const0_rtx ) var = expand_simple_binop ( HImode , IOR , var , x , var , <NUM_LIT> , OPTAB_LIB_WIDEN ) ;


<s> XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ; } for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ;

MachineMemOperand * MMO = F -> getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( RegSaveFrameIndex ) , MachineMemOperand :: MOStore , Offset , <NUM_LIT> , <NUM_LIT> ) ;


<s> for ( MachineInstr * MI : NewInsts ) applyBank ( * MI ) ;


<s> addPass ( & BranchRelaxationPassID ) ; addPass ( create<ISA_LIT>MakeCompressibleOptPass ( ) ) ;


<s> ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; if ( isZeroShuffle ( SVOp ) ) return getZeroVector ( VT , Subtarget , DAG , dl ) ; if ( SVOp -> isSplat ( ) ) { SDValue Broadcast = LowerVectorBroadcast ( Op , Subtarget , DAG ) ; if ( Broadcast . getNode ( ) ) return Broadcast ; } SDValue NewOp = LowerVectorIntExtend ( Op , Subtarget , DAG ) ; if ( NewOp . getNode ( ) ) return NewOp ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , NewOp ) ; } else if ( ( VT == <STR_LIT> || ( VT == <STR_LIT> && Subtarget -> hasSSE2 ( ) ) ) ) { if ( <STR_LIT> ( V2 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) { MVT NewVT = NewOp . getSimpleValueType ( ) ; if ( isCommutedMOVLMask ( cast < ShuffleVectorSDNode > ( NewOp ) -> getMask ( ) , NewVT , true , false ) ) return getVZextMovL ( VT , NewVT , NewOp . getOperand ( <NUM_LIT> ) , DAG , Subtarget , dl ) ; } } else if ( <STR_LIT> ( V1 . getNode ( ) ) ) { SDValue NewOp = RewriteAsNarrowerShuffle ( SVOp , DAG ) ; if ( NewOp . getNode ( ) ) {


<s> void * _Unwind_GetLanguageSpecificData ( struct _Unwind_Context * context ) {


<s> if ( CALL_P ( insn ) ) return <STR_LIT> ;

if ( JUMP_P ( insn ) && ( GET_CODE ( PATTERN ( insn ) ) == ADDR_DIFF_VEC || GET_CODE ( PATTERN ( insn ) ) == ADDR_VEC ) ) return <STR_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const {


<s> amount = offsets -> outgoing_args - offsets -> saved_regs ; if ( frame_pointer_needed ) { emit_insn ( gen_movsi ( stack_pointer_rtx , hard_frame_pointer_rtx ) ) ; amount = offsets -> locals_base - offsets -> saved_regs ; } amount -= <NUM_LIT> * thumb1_extra_regs_pushed ( offsets , false ) ; gcc_assert ( amount >= <NUM_LIT> ) ; if ( amount ) { emit_insn ( gen_blockage ( ) ) ; if ( amount < <NUM_LIT> ) emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ) ;


<s> const TargetSubtargetInfo & STI = MF . getSubtarget ( ) ; const MCRegisterInfo * MRI = STI . getRegisterInfo ( ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , - <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Et = MBB . insert ( Et , LDRXpost ) ; } const Function & CF = OF . Candidates . front ( ) . getMF ( ) -> getFunction ( ) ; bool ShouldSignReturnAddr = false ; if ( CF . hasFnAttribute ( <STR_LIT> ) ) { StringRef Scope = CF . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( Scope . equals ( <STR_LIT> ) ) ShouldSignReturnAddr = true ; else if ( Scope . equals ( <STR_LIT> ) && ! IsLeafFunction ) ShouldSignReturnAddr = true ; } bool ShouldSignReturnAddrWithAKey = true ; if ( CF . hasFnAttribute ( <STR_LIT> ) ) { const StringRef Key = CF . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ;

assert ( ( Key . equals_lower ( <STR_LIT> ) || Key . equals_lower ( <STR_LIT> ) ) && <STR_LIT> ) ;


<s> } if ( ! AM . IndexReg . getNode ( ) ) AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; getAddressOperands ( AM , Base , Scale , Index , Disp ) ;


<s> O << <STR_LIT> ; printMemReference ( MI , OpNo ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {


<s> case Unordered : llvm_unreachable ( <STR_LIT> ) ; case Monotonic : case Release : return nullptr ; case Acquire : case AcquireRelease : case SequentiallyConsistent : return makeDMB ( Builder , <STR_LIT> ) ;


<s> void setLRIsSpilledForFarJump ( bool s ) {


<s> static rtx rs6000_expand_unop_builtin ( enum insn_code icode , tree exp , rtx target ) { rtx pat ; tree arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; rtx op0 = expand_normal ( arg0 ) ; machine_mode tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; machine_mode mode0 = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ;

if ( icode == CODE_FOR_nothing ) return <NUM_LIT> ;


<s> MCStreamer :: EmitWinEHHandlerData ( Loc ) ; EHStreamer . EmitUnwindInfo ( * this , getCurrentWinFrameInfo ( ) ) ;


<s> bool <ISA_LIT>ExpandCondsets :: isIntraBlocks ( LiveInterval & LI ) { for ( LiveRange :: Segment & LR : LI ) { if ( ! LR . start . isRegister ( ) ) return false ; if ( ! LR . end . isRegister ( ) && ! LR . end . isDead ( ) ) return false ;


<s> const char * <ISA_LIT>DAGToDAGISel :: getPassName ( ) const {


<s> } } if ( ContainsZeros ) return false ; assert ( llvm :: all_of ( Mask , [ & ] ( int M ) { return SM_SentinelUndef <= M && M < ( int ) NumMaskElts ; } ) && <STR_LIT> ) ; unsigned InputSizeInBits = MaskVT . getSizeInBits ( ) ; unsigned MaskScalarSizeInBits = InputSizeInBits / Mask . size ( ) ; MVT MaskEltVT = <STR_LIT> ( MaskScalarSizeInBits ) ; if ( MaskScalarSizeInBits == <NUM_LIT> ) { SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( MaskEltVT , Mask , RepeatedMask ) ) { ArrayRef < int > LoMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; ArrayRef < int > HiMask ( Mask . data ( ) + <NUM_LIT> , <NUM_LIT> ) ; if ( isUndefOrInRange ( LoMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( HiMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( LoMask ) ; return true ; } if ( isUndefOrInRange ( HiMask , <NUM_LIT> , <NUM_LIT> ) && isSequentialOrUndefInRange ( LoMask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) { int OffsetHiMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) OffsetHiMask [ i ] = ( HiMask [ i ] < <NUM_LIT> ? HiMask [ i ] : HiMask [ i ] - <NUM_LIT> ) ; Shuffle = <STR_LIT> ; ShuffleVT = <STR_LIT> ( <STR_LIT> , InputSizeInBits / <NUM_LIT> ) ; PermuteImm = getV4<ISA_LIT>ShuffleImm ( OffsetHiMask ) ; return true ; } return false ; } return false ; } if ( MaskScalarSizeInBits != <NUM_LIT> && MaskScalarSizeInBits != <NUM_LIT> ) return false ; if ( FloatDomain && ! Subtarget . hasAVX ( ) ) return false ; if ( MaskVT . is256BitVector ( ) && ! Subtarget . hasAVX2 ( ) ) FloatDomain = true ; if ( is128BitLaneCrossingShuffleMask ( MaskEltVT , Mask ) ) {

if ( Subtarget . hasAVX2 ( ) && MaskVT . is256BitVector ( ) && Mask . size ( ) == <NUM_LIT> ) {


<s> inline SDValue getImm ( const SDNode * Node , unsigned Imm ) {

return CurDAG -> getTargetConstant ( Imm , SDLoc ( Node ) , Node -> getValueType ( <NUM_LIT> ) ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> DEBUG ( LRMI . dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( isEarly ? <STR_LIT> : <STR_LIT> ) ) ; DEBUG ( ESMI . dump ( ) ) ; if ( isLate && isEarly ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> SmallVector < MachineBasicBlock * , <NUM_LIT> > Stack ; Stack . push_back ( A ) ; do { MachineBasicBlock * MBB = Stack . back ( ) ; Stack . pop_back ( ) ; for ( MachineBasicBlock * Succ : MBB -> successors ( ) ) { if ( Succ == A ) return false ; if ( Succ != B && Reachable . insert ( Succ ) . second ) Stack . push_back ( Succ ) ; }


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSMEMOffsetEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { auto Offset = MI . getOperand ( OpNo ) . getImm ( ) ; assert ( ! <STR_LIT> ( STI ) || isUInt < <NUM_LIT> > ( Offset ) ) ;


initialize<ISA_LIT>UseNativeCallsPass ( * PR ) ;


<s> case REG : operands [ i + <NUM_LIT> ] = gen_rtx_REG ( HImode , REGNO ( operands [ i ] ) ) ; break ; case CONST_INT : operands [ i + <NUM_LIT> ] = GEN_INT ( ( INTVAL ( operands [ i ] ) & <NUM_LIT> ) + ( ( char ) INTVAL ( operands [ i + <NUM_LIT> ] ) ) * <NUM_LIT> ) ; break ; case MEM : operands [ i + <NUM_LIT> ] = adjust_address ( operands [ i ] , HImode , <NUM_LIT> ) ; break ;


<s> bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; if ( ! Subtarget . hasFastHorizontalOps ( ) && ! OptForSize ) return SDValue ( ) ; unsigned HorizOpcode = Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( ( ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) ) || ( ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) && Subtarget . hasSSE3 ( ) ) ) { unsigned NumElts = VecVT . getVectorNumElements ( ) ; SDValue Hi = extract128BitVector ( Rdx , NumElts / <NUM_LIT> , DAG , DL ) ; SDValue Lo = extract128BitVector ( Rdx , <NUM_LIT> , DAG , DL ) ; Rdx = DAG . getNode ( HorizOpcode , DL , Lo . getValueType ( ) , Hi , Lo ) ; VecVT = Rdx . getValueType ( ) ; } if ( ! ( ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) && Subtarget . hasSSSE3 ( ) ) && ! ( ( VecVT == <STR_LIT> || VecVT == <STR_LIT> ) && Subtarget . hasSSE3 ( ) ) ) return SDValue ( ) ; unsigned ReductionSteps = Log2_32 ( VecVT . getVectorNumElements ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != ReductionSteps ; ++ i ) Rdx = DAG . getNode ( HorizOpcode , DL , VecVT , Rdx , Rdx ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , Rdx , Index ) ;


<s> DebugLoc dl = MI . getDebugLoc ( ) ; unsigned OffsetOperandNo = getOffsetONFromFION ( MI , FIOperandNum ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; <ISA_LIT>FunctionInfo * FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; unsigned OpC = MI . getOpcode ( ) ; if ( ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAreaOffset ( II ) ; return ; } if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerDynamicAlloc ( II ) ; return ; } if ( FPSI && FrameIndex == FPSI && ( OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> || OpC == <STR_LIT> ) ) { lowerPrepareProbedAlloca ( II ) ; return ; } if ( OpC == <STR_LIT> ) { lowerCRSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRRestore ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitSpilling ( II , FrameIndex ) ; return ; } else if ( OpC == <STR_LIT> ) { lowerCRBitRestore ( II , FrameIndex ) ; return ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI . getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI . getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; bool OffsetFitsMnemonic = ( OpC == <STR_LIT> || OpC == <STR_LIT> ) ? isUInt < <NUM_LIT> > ( Offset ) : isInt < <NUM_LIT> > ( Offset ) ; if ( ! noImmForm && ( ( OffsetFitsMnemonic && ( ( Offset % offsetMinAlign ( MI ) ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) {

MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ;


<s> bool <ISA_LIT>AvoidSFBPass :: runOnMachineFunction ( MachineFunction & MF ) { bool Changed = false ; if ( Disable<ISA_LIT>AvoidStoreForwardBlocks || skipFunction ( MF . getFunction ( ) ) || ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return false ; MRI = & MF . getRegInfo ( ) ; assert ( MRI -> isSSA ( ) && <STR_LIT> ) ; TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; findPotentiallylBlockedCopies ( MF ) ; for ( auto LoadStoreInstPair : BlockedLoadsStoresPairs ) { MachineInstr * LoadInst = LoadStoreInstPair . first ; int64_t LdDispImm = getDispOperand ( LoadInst ) . getImm ( ) ; DisplacementSizeMap BlockingStoresDispSizeMap ; SmallVector < MachineInstr * , <NUM_LIT> > PotentialBlockers = findPotentialBlockers ( LoadInst ) ; for ( auto PBInst : PotentialBlockers ) { if ( ! isPotentialBlockingStoreInst ( PBInst -> getOpcode ( ) , LoadInst -> getOpcode ( ) ) || ! isRelevantAddressingMode ( PBInst ) ) continue ; int64_t PBstDispImm = getDispOperand ( PBInst ) . getImm ( ) ; assert ( PBInst -> hasOneMemOperand ( ) && <STR_LIT> ) ; unsigned PBstSize = ( * PBInst -> memoperands_begin ( ) ) -> getSize ( ) ; if ( hasSameBaseOpValue ( LoadInst , PBInst ) && isBlockingStore ( LdDispImm , getRegSizeInBytes ( LoadInst ) , PBstDispImm , PBstSize ) ) updateBlockingStoresDispSizeMap ( BlockingStoresDispSizeMap , PBstDispImm , PBstSize ) ; } if ( BlockingStoresDispSizeMap . empty ( ) ) continue ; MachineInstr * StoreInst = LoadStoreInstPair . second ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( LoadInst -> dump ( ) ) ; LLVM_DEBUG ( StoreInst -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; removeRedundantBlockingStores ( BlockingStoresDispSizeMap ) ; breakBlockedCopies ( LoadInst , StoreInst , BlockingStoresDispSizeMap ) ; updateKillStatus ( LoadInst , StoreInst ) ; ForRemoval . push_back ( LoadInst ) ; ForRemoval . push_back ( StoreInst ) ;


<s> B . setInstrAndDebugLoc ( MI ) ; auto Lane = B . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , MatchInfo . second ) ; B . buildInstr ( MatchInfo . first , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Lane } ) ;


<s> SDValue Dest = N -> getOperand ( <NUM_LIT> ) ; SDValue EFLAGS = N -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; SDValue Flags ; Flags = checkBoolTestSetCCCombine ( EFLAGS , CC ) ; if ( Flags . getNode ( ) ) { SDValue Cond = DAG . getConstant ( CC , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , Chain , Dest , Cond , Flags ) ; }


<s> SMLoc getEndLoc ( ) const override {


<s> case <STR_LIT> : break ; } } const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 && ( ! Src1 -> isReg ( ) || ! RI . isVGPR ( MRI , Src1 -> getReg ( ) ) || hasModifiersSet ( MI , <STR_LIT> :: src1_modifiers ) ) ) return false ; if ( hasModifiersSet ( MI , <STR_LIT> :: src0_modifiers ) ) return false ; return ! hasModifiersSet ( MI , <STR_LIT> :: omod ) && ! hasModifiersSet ( MI , <STR_LIT> :: clamp ) ;


<s> if ( RegNo > <NUM_LIT> || ( hasD16 && RegNo > <NUM_LIT> ) ) return MCDisassembler :: Fail ; unsigned Register = DPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> rtx pattern = PATTERN ( insn ) ; rtx unspec ; rtx addr ; rtx opnds [ <NUM_LIT> ] ; rtx_insn * new_insns ; rtx got_rtx = tilegx_got_rtx ( ) ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; opnds [ <NUM_LIT> ] = SET_DEST ( pattern ) ; unspec = SET_SRC ( pattern ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; gcc_assert ( XINT ( unspec , <NUM_LIT> ) == UNSPEC_INSN_ADDR_SHL16INSLI ) ; opnds [ <NUM_LIT> ] = XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) ; addr = XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( addr ) == CONST ) ; unspec = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; gcc_assert ( XINT ( unspec , <NUM_LIT> ) == UNSPEC_HW0_PCREL ) ; opnds [ <NUM_LIT> ] = XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( opnds [ <NUM_LIT> ] ) != SYMBOL_REF ) return ; start_sequence ( ) ; if ( flag_pic == <NUM_LIT> ) { if ( TARGET_32BIT ) emit_insn ( gen_add_got16_32bit ( opnds [ <NUM_LIT> ] , got_rtx , opnds [ <NUM_LIT> ] ) ) ; else emit_insn ( gen_add_got16 ( opnds [ <NUM_LIT> ] , got_rtx , opnds [ <NUM_LIT> ] ) ) ; } else {

if ( TARGET_32BIT ) emit_insn ( gen_mov_got32_step2_32bit ( opnds [ <NUM_LIT> ] , opnds [ <NUM_LIT> ] , opnds [ <NUM_LIT> ] ) ) ;


<s> static DecodeStatus DecodeAS ( MCInst & MI , uint64_t insn , uint64_t Address , const MCDisassembler * Decoder ) { unsigned sz = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; bool cz = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; uint64_t simm32 = SignExtend64 < <NUM_LIT> > ( fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ) ; DecodeStatus status ; if ( cz ) { status = DecodeI64RegisterClass ( MI , sz , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } else {

MI . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;


<s> RC = & <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT LocVT = VA . getLocVT ( ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DL ) ) ; InVals . push_back ( DAG . getLoad ( LocVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) , <NUM_LIT> ) ) ; } }