<s> MVT eltVT = vecVT . getVectorElementType ( ) ; SDNode * bvNode = build_vec . getNode ( ) ; DebugLoc dl = bvNode -> getDebugLoc ( ) ; if ( ( ( vecVT == <STR_LIT> ) && ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) ) || ( ( vecVT == <STR_LIT> ) && ( ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG ) . getNode ( ) != <NUM_LIT> ) ) ) || ( ( vecVT == <STR_LIT> ) && ( ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) || ( <STR_LIT> ( bvNode , * CurDAG , <STR_LIT> ) . getNode ( ) != <NUM_LIT> ) ) ) ) return Select ( build_vec ) ; std :: vector < Constant * > CV ; for ( size_t i = <NUM_LIT> ; i < build_vec . getNumOperands ( ) ; ++ i ) { ConstantSDNode * V = dyn_cast < ConstantSDNode > ( build_vec . getOperand ( i ) ) ; CV . push_back ( const_cast < ConstantInt * > ( V -> getConstantIntValue ( ) ) ) ; } Constant * CP = ConstantVector :: get ( CV ) ;

SDValue CPIdx = CurDAG -> getConstantPool ( CP , <ISA_LIT>tli . getPointerTy ( ) ) ;


<s> OutStreamer . EmitInstruction ( Directive ) ; } else { MCInstLowering . LowerUnalignedLoadStore ( MI , MCInsts ) ; for ( SmallVector < MCInst , <NUM_LIT> > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; } return ; } if ( ! OutStreamer . hasRawTextSupport ( ) ) { if ( Opc == <STR_LIT> ) MCInstLowering . LowerCPLOAD ( MI , MCInsts ) ; else if ( Opc == <STR_LIT> ) MCInstLowering . LowerCPRESTORE ( MI , MCInsts ) ; if ( ! MCInsts . empty ( ) ) { for ( SmallVector < MCInst , <NUM_LIT> > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; return ; } } if ( Opc == <STR_LIT> ) { MCInstLowering . LowerSETGP01 ( MI , MCInsts ) ; for ( SmallVector < MCInst , <NUM_LIT> > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; return ; } OutStreamer . EmitInstruction ( TmpInst0 ) ;


<s> return parseRegister ( Operands , VR128Reg ) ;


<s> bool isAligned = ( Subtarget . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , Subtarget ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ;


<s> static bool CC_<ISA_LIT>_APCS_Custom_f64 ( unsigned & ValNo , MVT & ValVT , MVT & LocVT , CCValAssign :: LocInfo & LocInfo , <STR_LIT> & ArgFlags , CCState & State ) { static const unsigned HiRegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned LoRegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned Reg = State . AllocateReg ( HiRegList , LoRegList , <NUM_LIT> ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned i ;

for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( HiRegList [ i ] == Reg ) break ;


<s> static void aarch64_emit_mult ( rtx dst , rtx ptrue , rtx src1 , rtx src2 ) { if ( ptrue ) emit_insn ( gen_aarch64_pred ( UNSPEC_COND_FMUL , GET_MODE ( dst ) , dst , ptrue , src1 , src2 , gen_int_mode ( SVE_RELAXED_GP , SImode ) ) ) ;

else emit_set_insn ( dst , gen_rtx_MULT ( GET_MODE ( dst ) , src1 , src2 ) ) ;


<s> return ( int8x16_t ) __builtin_neon_vnegv16qi ( __a ) ;


<s> RegisterMCAsmInfo < MandarinELFMCAsmInfo > X ( TheMandarinTarget ) ; TargetRegistry :: RegisterMCCodeGenInfo ( TheMandarinTarget , createMandarinMCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( TheMandarinTarget , createMandarinMCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( TheMandarinTarget , createMandarinMCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( TheMandarinTarget , createMandarinMCSubtargetInfo ) ;


<s> void <ISA_LIT>SEInstrInfo :: expandPseudoMFHiLo ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned NewOpc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( NewOpc ) , I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> std :: string DsmReg ( RegName a ) { switch ( a ) { case RegName :: a0 : return <STR_LIT> ; case RegName :: a0l : return <STR_LIT> ; case RegName :: a0h : return <STR_LIT> ; case RegName :: a0e : return <STR_LIT> ; case RegName :: a1 : return <STR_LIT> ; case RegName :: a1l : return <STR_LIT> ; case RegName :: a1h : return <STR_LIT> ; case RegName :: a1e : return <STR_LIT> ; case RegName :: b0 : return <STR_LIT> ; case RegName :: b0l : return <STR_LIT> ; case RegName :: b0h : return <STR_LIT> ; case RegName :: b0e : return <STR_LIT> ; case RegName :: b1 : return <STR_LIT> ; case RegName :: b1l : return <STR_LIT> ; case RegName :: b1h : return <STR_LIT> ; case RegName :: b1e : return <STR_LIT> ; case RegName :: r0 : return <STR_LIT> ; case RegName :: r1 : return <STR_LIT> ; case RegName :: r2 : return <STR_LIT> ; case RegName :: r3 : return <STR_LIT> ; case RegName :: r4 : return <STR_LIT> ; case RegName :: r5 : return <STR_LIT> ; case RegName :: r6 : return <STR_LIT> ; case RegName :: r7 : return <STR_LIT> ; case RegName :: ar0 : return <STR_LIT> ; case RegName :: ar1 : return <STR_LIT> ; case RegName :: arp0 : return <STR_LIT> ; case RegName :: arp1 : return <STR_LIT> ; case RegName :: arp2 : return <STR_LIT> ; case RegName :: arp3 : return <STR_LIT> ;


value4byte = simplify_gen_subreg ( QImode , value4doubleword , DImode , subreg_lowpart_offset ( QImode , DImode ) ) ;


<s> unsigned DefAdj = <NUM_LIT> ; if ( DefMI -> isBundle ( ) ) { DefMI = getBundledDefMI ( & getRegisterInfo ( ) , DefMI , Reg , DefIdx , DefAdj ) ; DefMCID = & DefMI -> getDesc ( ) ; } if ( DefMI -> isCopyLike ( ) || DefMI -> isInsertSubreg ( ) || DefMI -> isRegSequence ( ) || DefMI -> isImplicitDef ( ) ) { return <NUM_LIT> ; } unsigned UseAdj = <NUM_LIT> ; if ( UseMI -> isBundle ( ) ) { unsigned NewUseIdx ; const MachineInstr * NewUseMI = getBundledUseMI ( & getRegisterInfo ( ) , UseMI , Reg , NewUseIdx , UseAdj ) ; if ( ! NewUseMI ) return - <NUM_LIT> ; UseMI = NewUseMI ; UseIdx = NewUseIdx ; UseMCID = & UseMI -> getDesc ( ) ; } if ( Reg == <STR_LIT> ) { if ( DefMI -> getOpcode ( ) == <STR_LIT> ) { return Subtarget . isLikeA9 ( ) ? <NUM_LIT> : <NUM_LIT> ; } if ( UseMI -> isBranch ( ) ) return <NUM_LIT> ; unsigned Latency = getInstrLatency ( ItinData , DefMI ) ; if ( Latency > <NUM_LIT> && Subtarget . isThumb2 ( ) ) { const MachineFunction * MF = DefMI -> getParent ( ) -> getParent ( ) ; if ( MF -> getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: OptimizeForSize ) ) -- Latency ; } return Latency ;


<s> default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg1 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg2 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ; updateValueMap ( I , ResultReg ) ; return true ; } <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = <STR_LIT> ( Predicate ) ; assert ( CC <= <STR_LIT> && <STR_LIT> ) ;

if ( SwapArgs ) std :: swap ( LHS , RHS ) ;


<s> if ( GET_CODE ( x ) == IF_THEN_ELSE && ( XEXP ( x , <NUM_LIT> ) == const0_rtx || XEXP ( x , <NUM_LIT> ) == const1_rtx ) && COMPARISON_P ( XEXP ( x , <NUM_LIT> ) ) && COMPARISON_P ( XEXP ( x , <NUM_LIT> ) ) ) return arm_select_dominance_cc_mode ( XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) , INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ; if ( GET_CODE ( x ) == AND && COMPARISON_P ( XEXP ( x , <NUM_LIT> ) ) && COMPARISON_P ( XEXP ( x , <NUM_LIT> ) ) ) return arm_select_dominance_cc_mode ( XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) , DOM_CC_X_AND_Y ) ; if ( GET_CODE ( x ) == IOR && COMPARISON_P ( XEXP ( x , <NUM_LIT> ) ) && COMPARISON_P ( XEXP ( x , <NUM_LIT> ) ) ) return arm_select_dominance_cc_mode ( XEXP ( x , <NUM_LIT> ) , XEXP ( x , <NUM_LIT> ) , DOM_CC_X_OR_Y ) ; if ( TARGET_THUMB && GET_MODE ( x ) == SImode && ( op == EQ || op == NE ) && ( GET_CODE ( x ) == ZERO_EXTRACT ) ) return CC_Nmode ; if ( GET_MODE ( x ) == SImode && y == const0_rtx && ( op == EQ || op == NE || op == LT || op == GE ) && ( GET_CODE ( x ) == PLUS || GET_CODE ( x ) == MINUS || GET_CODE ( x ) == AND || GET_CODE ( x ) == IOR || GET_CODE ( x ) == XOR || GET_CODE ( x ) == MULT || GET_CODE ( x ) == NOT || GET_CODE ( x ) == NEG || GET_CODE ( x ) == LSHIFTRT || GET_CODE ( x ) == ASHIFT || GET_CODE ( x ) == ASHIFTRT || GET_CODE ( x ) == ROTATERT || ( TARGET_ARM && GET_CODE ( x ) == ZERO_EXTRACT ) ) ) return CC_NOOVmode ; if ( GET_MODE ( x ) == QImode && ( op == EQ || op == NE ) ) return CC_Zmode ; if ( GET_MODE ( x ) == SImode && ( op == LTU || op == GEU ) && GET_CODE ( x ) == PLUS && ( rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , y ) || rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , y ) ) ) return CC_Cmode ; return CCmode ;


<s> } else { const MCInstrDesc & LoadDwordX2 = TII -> get ( <STR_LIT> ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; auto MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( MBB , I , DL , LoadDwordX2 , Rsrc01 ) . addReg ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; MF . getRegInfo ( ) . addLiveIn ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) ; MBB . addLiveIn ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) ; } } else { Register Rsrc0 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; Register Rsrc1 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , SMovB32 , Rsrc0 ) . addExternalSymbol ( <STR_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; BuildMI ( MBB , I , DL , SMovB32 , Rsrc1 ) . addExternalSymbol ( <STR_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; } BuildMI ( MBB , I , DL , SMovB32 , Rsrc2 ) . addImm ( Rsrc23 & <NUM_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; BuildMI ( MBB , I , DL , SMovB32 , Rsrc3 ) . addImm ( Rsrc23 >> <NUM_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; } else if ( ST . isAmdHsaOrMesa ( Fn ) ) { assert ( PreloadedScratchRsrcReg ) ; if ( ScratchRsrcReg != PreloadedScratchRsrcReg ) {

BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , ScratchRsrcReg ) . addReg ( PreloadedScratchRsrcReg , RegState :: Kill ) ;


<s> for ( MCSubRegIterator SubRegIt ( Reg , MCRegInfo , true ) ; SubRegIt . isValid ( ) ; ++ SubRegIt ) { unsigned CurrentSubReg = * SubRegIt ; unsigned EncVal = MCRegInfo -> getEncodingValue ( CurrentSubReg ) ; Value |= <NUM_LIT> << EncVal ; if ( GPR32RegClass -> contains ( CurrentSubReg ) || GPR64RegClass -> contains ( CurrentSubReg ) ) ri_gprmask |= Value ;

else if ( COP0RegClass -> contains ( CurrentSubReg ) ) ri_cprmask [ <NUM_LIT> ] |= Value ;


<s> int Sum = <NUM_LIT> ; for ( int Idx : Mask ) { if ( Idx == - <NUM_LIT> ) return false ; Sum += Idx ; } int N = Mask . size ( ) ;

return <NUM_LIT> * Sum == N * ( N - <NUM_LIT> ) ;


<s> if ( ! Subtarget -> hasVFP2 ( ) ) return false ; Value * V = I -> getOperand ( <NUM_LIT> ) ; if ( ! ( I -> getType ( ) -> isFloatTy ( ) && V -> getType ( ) -> isDoubleTy ( ) ) ) return false ; unsigned Op = getRegForValue ( V ) ; if ( Op == <NUM_LIT> ) return false ; unsigned Result = createResultReg ( & <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , Result ) . addReg ( Op ) ) ;


<s> void DecodeZeroMoveLowMask ( unsigned NumElts , SmallVectorImpl < int > & ShuffleMask ) { ShuffleMask . push_back ( <NUM_LIT> ) ;

for ( unsigned i = <NUM_LIT> ; i < NumElts ; i ++ ) ShuffleMask . push_back ( SM_SentinelZero ) ;


<s> SDLoc DL ( N ) ; int TagOffset = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDNode * N1 = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ) ;

SDNode * N2 = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { SDValue ( N1 , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ) ;


<s> if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { CInfo . Kind = <ISA_LIT>PreserveArrayAI ; CInfo . Metadata = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; if ( ! CInfo . Metadata ) report_fatal_error ( <STR_LIT> ) ; CInfo . AccessIndex = getConstant ( Call -> getArgOperand ( <NUM_LIT> ) ) ; CInfo . Base = Call -> getArgOperand ( <NUM_LIT> ) ; CInfo . RecordAlignment = DL -> getABITypeAlign ( CInfo . Base -> getType ( ) -> getPointerElementType ( ) ) ; return true ; } if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { CInfo . Kind = <ISA_LIT>PreserveUnionAI ; CInfo . Metadata = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; if ( ! CInfo . Metadata ) report_fatal_error ( <STR_LIT> ) ; CInfo . AccessIndex = getConstant ( Call -> getArgOperand ( <NUM_LIT> ) ) ; CInfo . Base = Call -> getArgOperand ( <NUM_LIT> ) ; CInfo . RecordAlignment = DL -> getABITypeAlign ( CInfo . Base -> getType ( ) -> getPointerElementType ( ) ) ; return true ; } if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { CInfo . Kind = <ISA_LIT>PreserveStructAI ; CInfo . Metadata = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; if ( ! CInfo . Metadata ) report_fatal_error ( <STR_LIT> ) ; CInfo . AccessIndex = getConstant ( Call -> getArgOperand ( <NUM_LIT> ) ) ; CInfo . Base = Call -> getArgOperand ( <NUM_LIT> ) ; CInfo . RecordAlignment = DL -> getABITypeAlign ( CInfo . Base -> getType ( ) -> getPointerElementType ( ) ) ; return true ; } if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { CInfo . Kind = <ISA_LIT>PreserveFieldInfoAI ; CInfo . Metadata = nullptr ; uint64_t InfoKind = getConstant ( Call -> getArgOperand ( <NUM_LIT> ) ) ;

if ( InfoKind >= <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ;


<s> unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; std :: pair < unsigned , unsigned > Opcodes = getMFHiLoOpc ( Src ) ; if ( ! Opcodes . first ) return false ;

return expandCopyACC ( MBB , I , Opcodes . first , Opcodes . second ) ;


<s> AU . addPreserved < MachineFunctionAnalysis > ( ) ;

FunctionPass :: getAnalysisUsage ( AU ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( bool IsForTls ) {

Register GlobalBaseReg = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseReg ( * MF , IsForTls ) ;


<s> AU . addPreserved < MachineLoopInfo > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> return genConstMult ( N -> getOperand ( <NUM_LIT> ) , C -> getAPIntValue ( ) , SDLoc ( N ) , VT , TL -> getScalarShiftAmountTy ( DAG . getDataLayout ( ) , VT ) , DAG ) ; } return SDValue ( N , <NUM_LIT> ) ;


<s> if ( regno >= LOC_REG ( <NUM_LIT> ) && regno < LOC_REG ( <NUM_LIT> - frame_pointer_needed ) && current_frame_info . n_local_regs < regno - LOC_REG ( <NUM_LIT> ) + <NUM_LIT> ) current_frame_info . n_local_regs = regno - LOC_REG ( <NUM_LIT> ) + <NUM_LIT> ; else if ( crtl -> is_leaf && regno >= GR_REG ( <NUM_LIT> ) && regno <= GR_REG ( <NUM_LIT> ) ) current_frame_info . gr_used_mask |= <NUM_LIT> << regno ;


<s> getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {

if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;


<s> switch ( Opcode ) { case <STR_LIT> : \ return <STR_LIT> ; case <STR_LIT> : \ case <STR_LIT> : \ return <STR_LIT> ; }


<s> LastCMOV = & * NextMIIt ; ++ NextMIIt ; } } if ( LastCMOV == & MI && NextMIIt != ThisMBB -> end ( ) && NextMIIt -> getOpcode ( ) == MI . getOpcode ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && NextMIIt -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { return EmitLoweredCascadedSelect ( MI , * NextMIIt , ThisMBB ) ; } const BasicBlock * LLVM_BB = ThisMBB -> getBasicBlock ( ) ; MachineFunction * F = ThisMBB -> getParent ( ) ; MachineBasicBlock * FalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ThisMBB -> getIterator ( ) ; F -> insert ( It , FalseMBB ) ; F -> insert ( It , SinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; if ( ! LastCMOV -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( LastCMOV , ThisMBB , TRI ) ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( FalseMBB ) ; ThisMBB -> addSuccessor ( SinkMBB ) ; FalseMBB -> addSuccessor ( SinkMBB ) ;


<s> if ( BV . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Op0 = BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; int Offset = BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> || ( Offset != <NUM_LIT> && Offset != <NUM_LIT> ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { auto Check = [ ] ( SDValue Trunc , SDValue Op , unsigned Idx ) { return Trunc . getOpcode ( ) == <STR_LIT> && Trunc . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Trunc . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) == Op && Trunc . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) == Idx ; } ; if ( ! Check ( BV . getOperand ( i ) , Op0 , <NUM_LIT> * i + Offset ) ) return SDValue ( ) ; } return DAG . getNode ( <STR_LIT> , dl , VT , Op0 , DAG . getConstant ( Offset , dl , <STR_LIT> ) ) ;


<s> TM = & F . getTarget ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : F ) Changed |= runOnMachineBasicBlock ( MBB ) ; if ( Changed ) F . getRegInfo ( ) . invalidateLiveness ( ) ; return Changed ;


<s> if ( VA . getLocVT ( ) . isInteger ( ) && VA . getValVT ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ;

else if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Val ) ;


<s> void Emitter < CodeEmitter > :: emitMiscInstruction ( const MachineInstr & MI ) { unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const {


<s> output_asm_insn ( <STR_LIT> , xoperands ) ; if ( TARGET_GAS ) { output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; } else { xoperands [ <NUM_LIT> ] = GEN_INT ( val_14 ? <NUM_LIT> : <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; } if ( val_14 ) { output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } else { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } } else if ( TARGET_PORTABLE_RUNTIME ) { output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( ! val_14 ) output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( val_14 ) { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } else { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } } else if ( TARGET_SOM && flag_pic && TREE_PUBLIC ( function ) ) { ASM_GENERATE_INTERNAL_LABEL ( label , <STR_LIT> , current_thunk_number ) ; xoperands [ <NUM_LIT> ] = gen_rtx_SYMBOL_REF ( Pmode , label ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; output_asm_insn ( <STR_LIT> , xoperands ) ; if ( ! val_14 ) { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } if ( TARGET_PA_20 ) { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; } else if ( TARGET_NO_SPACE_REGS ) { output_asm_insn ( <STR_LIT> , xoperands ) ; nbytes += <NUM_LIT> ; }


<s> static bool isGPRShadowAligned ( MCPhysReg Reg , Align RequiredAlign ) { assert ( RequiredAlign . value ( ) <= <NUM_LIT> && <STR_LIT> ) ; switch ( Reg ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> Function * EmAsmConstIntSyncMainF = M . getFunction ( <STR_LIT> ) ; Function * EmAsmConstDoubleSyncMainF = M . getFunction ( <STR_LIT> ) ;

Function * EmAsmConstAsyncMainF = M . getFunction ( <STR_LIT> ) ;


<s> WorkItem ( MachineInstr * MI ) : MI ( MI ) {


<s> <ISA_LIT>PromoteAlloca ( const TargetMachine * TM_ = nullptr ) :

FunctionPass ( ID ) , TM ( TM_ ) , Mod ( nullptr ) , LocalMemAvailable ( <NUM_LIT> ) {


<s> return __builtin_neon_vcvtphusi ( __a ) ;


<s> Base = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) ? CurDAG -> getTargetFrameIndex ( AM . Base . FrameIndex , TLI . getPointerTy ( ) ) : AM . Base . Reg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , <STR_LIT> , AM . Disp , <NUM_LIT> ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , <NUM_LIT> ) ; else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , <NUM_LIT> ) ;

else if ( AM . JT != - <NUM_LIT> ) Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , <NUM_LIT> ) ;


<s> virtual void emitIndirectFunctionType ( StringRef name , SmallVectorImpl < MVT > & Params , SmallVectorImpl < MVT > & Results ) { llvm_unreachable ( <STR_LIT> ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ;

TargetRegistry :: RegisterELFStreamer ( * T , create<ISA_LIT>MCStreamer ) ;


<s> PM . add ( create<ISA_LIT>ISelDag ( * this , getOptLevel ( ) ) ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> unsigned RegHi = RI . getSubReg ( Reg , AMDGPU :: sub1 ) ; BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_GETPC_B64 ) , Reg ) ;

BuildMI ( MBB , MI , DL , get ( AMDGPU :: S_ADD_U32 ) , RegLo ) . addReg ( RegLo ) . addTargetIndex ( AMDGPU :: TI_CONSTDATA_START ) . addReg ( AMDGPU :: SCC , RegState :: Define | RegState :: Implicit ) ;


<s> bool hasHipeCC = ( F ? F -> getCallingConv ( ) == CallingConv :: HiPE : false ) ; if ( hasHipeCC ) return & <STR_LIT> ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;


<s> * code = EQ ; case ORDERED : tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = const0_rtx ; break ; case UNEQ : case LTGT : * code = fp_code == LTGT ? GTU : EQ ; tmp0 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op0 ) ; tmp1 = riscv_force_binary ( word_mode , EQ , cmp_op1 , cmp_op1 ) ; * op0 = riscv_force_binary ( word_mode , AND , tmp0 , tmp1 ) ; * op1 = riscv_force_binary ( word_mode , EQ , cmp_op0 , cmp_op1 ) ; break ; case CODE : \ * code = EQ ; \ * op0 = gen_reg_rtx ( word_mode ) ; \ if ( GET_MODE ( cmp_op0 ) == SFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietsfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == SFmode ) \ emit_insn ( gen_f ## CMP ## _quietsfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode && TARGET_64BIT ) \ emit_insn ( gen_f ## CMP ## _quietdfdi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else if ( GET_MODE ( cmp_op0 ) == DFmode ) \ emit_insn ( gen_f ## CMP ## _quietdfsi4 ( * op0 , cmp_op0 , cmp_op1 ) ) ; \ else \ gcc_unreachable ( ) ; \ * op1 = const0_rtx ; \ break ; case UNLT : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGT , le ) case UNLE : std :: swap ( cmp_op0 , cmp_op1 ) ; gcc_fallthrough ( ) ; UNORDERED_COMPARISON ( UNGE , lt ) case NE : fp_code = EQ ; * code = EQ ; case EQ : case LE : case LT : case GE : case GT : * op0 = riscv_force_binary ( word_mode , fp_code , cmp_op0 , cmp_op1 ) ; * op1 = const0_rtx ; break ; default :


<s> unsigned int size ; if ( GET_CODE ( op ) != MEM ) return false ; addr = XEXP ( op , <NUM_LIT> ) ;

size = GET_MODE_SIZE ( GET_MODE ( op ) ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForNode ( CallConv , false , isVarArg ) ) ; SmallVector < SDValue , <NUM_LIT> > ArgValues ; int lastInsIndex = - <NUM_LIT> ; SDValue ArgValue ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue ArgValue1 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; VA = ArgLocs [ ++ i ] ; SDValue ArgValue2 ; if ( VA . isMemLoc ( ) ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , <NUM_LIT> ) ; } else { ArgValue2 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else ArgValue = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } else { TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = ( AFI -> isThumb1OnlyFunction ( ) ? <STR_LIT> : <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ;

ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ;


<s> const MDNode * elem = NMD -> getOperand ( i ) ; Value * entity = elem -> getOperand ( <NUM_LIT> ) ; if ( ! entity ) continue ; if ( entity != gv ) continue ; cacheAnnotationFromMD ( elem , tmp ) ; } if ( tmp . empty ( ) ) return ; if ( ( * annotationCache ) . find ( m ) != ( * annotationCache ) . end ( ) ) ( * annotationCache ) [ m ] [ gv ] = tmp ; else { global_val_annot_t tmp1 ; tmp1 [ gv ] = tmp ; ( * annotationCache ) [ m ] = tmp1 ;


<s> return MI -> getDesc ( ) . isBranch ( ) ;


<s> while ( ! PtrUsers . empty ( ) ) { Instruction * U = dyn_cast < Instruction > ( PtrUsers . pop_back_val ( ) ) ; if ( ! U ) continue ; switch ( U -> getOpcode ( ) ) { default : break ; case Instruction :: Load : { LoadInst * LD = cast < LoadInst > ( U ) ; PointerType * PT = dyn_cast < PointerType > ( LD -> getType ( ) ) ; if ( ! PT || ( PT -> getAddressSpace ( ) != <ISA_LIT>AS :: FLAT_ADDRESS && PT -> getAddressSpace ( ) != <ISA_LIT>AS :: GLOBAL_ADDRESS && PT -> getAddressSpace ( ) != <ISA_LIT>AS :: CONSTANT_ADDRESS ) || LD -> getPointerOperand ( ) -> stripInBoundsOffsets ( ) != Ptr ) break ; const MemoryAccess * MA = MSSA -> getWalker ( ) -> getClobberingMemoryAccess ( LD ) ; if ( MSSA -> isLiveOnEntryDef ( MA ) ) Ptrs . push_back ( LD ) ; break ; } case Instruction :: GetElementPtr : case Instruction :: AddrSpaceCast : case Instruction :: BitCast : if ( U -> getOperand ( <NUM_LIT> ) -> stripInBoundsOffsets ( ) == Ptr ) PtrUsers . append ( U -> user_begin ( ) , U -> user_end ( ) ) ;


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineFunction :: iterator It = BB ; ++ It ; unsigned dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned incr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned oldval = dest ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * TRC , * TRCsp ; if ( Size == <NUM_LIT> ) { TRC = & <STR_LIT> ; TRCsp = & <STR_LIT> ; } else { TRC = & <STR_LIT> ; TRCsp = & <STR_LIT> ; } unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , ldrOpc , strOpc ) ; MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ;

unsigned scratch = MRI . createVirtualRegister ( TRC ) ;


<s> MCContext & Ctx = getContext ( ) ; MCStreamer & Out = getStreamer ( ) ; const MCExpr * Expr ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Expr ) ) return MatchOperand_NoMatch ; if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ; if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal ) { Error ( StartLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } MCSymbol * Sym = Ctx . CreateTempSymbol ( ) ; Out . EmitLabel ( Sym ) ; const MCExpr * Base = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , Ctx ) ; Expr = Value == <NUM_LIT> ? Base : MCBinaryExpr :: CreateAdd ( Base , Expr , Ctx ) ; } SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;

Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , StartLoc , EndLoc ) ) ;


<s> SmallString < <NUM_LIT> > NewName ( <STR_LIT> ) ; NewName += Name ; NewName += <STR_LIT> ;

FBody -> setName ( NewName . str ( ) ) ;


<s> if ( std :: distance ( RepeatedSequenceLocs . begin ( ) , NoPAC ) > std :: distance ( NoPAC , RepeatedSequenceLocs . end ( ) ) ) RepeatedSequenceLocs . erase ( NoPAC , RepeatedSequenceLocs . end ( ) ) ; else RepeatedSequenceLocs . erase ( RepeatedSequenceLocs . begin ( ) , NoPAC ) ; if ( RepeatedSequenceLocs . size ( ) < <NUM_LIT> ) return outliner :: OutlinedFunction ( ) ; unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; OutlinerCosts Costs ( Subtarget ) ; const auto & SomeMFI = * RepeatedSequenceLocs . front ( ) . getMF ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( SomeMFI . branchTargetEnforcement ( ) ) { Costs . FrameDefault += <NUM_LIT> ; Costs . FrameNoLRSave += <NUM_LIT> ; Costs . FrameRegSave += <NUM_LIT> ; Costs . FrameTailCall += <NUM_LIT> ; Costs . FrameThunk += <NUM_LIT> ; } if ( SomeMFI . shouldSignReturnAddress ( true ) ) { Costs . CallDefault += <NUM_LIT> ; Costs . SaveRestoreLROnStack += <NUM_LIT> ; } unsigned FrameID = MachineOutlinerDefault ; unsigned NumBytesToCreateFrame = Costs . FrameDefault ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = Costs . FrameTailCall ; SetCandidateCallInfo ( MachineOutlinerTailCall , Costs . CallTailCall ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = Costs . FrameThunk ; SetCandidateCallInfo ( MachineOutlinerThunk , Costs . CallThunk ) ; } else { unsigned NumBytesNoStackCalls = <NUM_LIT> ; std :: vector < outliner :: Candidate > CandidatesWithoutStackFixups ; for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { C . initLRU ( TRI ) ; const auto Last = C . getMBB ( ) -> rbegin ( ) ; const bool LRIsAvailable = C . getMBB ( ) -> isReturnBlock ( ) && ! Last -> isCall ( ) ? isLRAvailable ( TRI , Last , ( MachineBasicBlock :: reverse_iterator ) C . front ( ) ) : C . LRU . available ( <STR_LIT> ) ; if ( LRIsAvailable ) { FrameID = MachineOutlinerNoLRSave ; NumBytesNoStackCalls += Costs . CallNoLRSave ; C . setCallInfo ( MachineOutlinerNoLRSave , Costs . CallNoLRSave ) ; CandidatesWithoutStackFixups . push_back ( C ) ;


<s> uint64_t SMPos , SMSize ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Mask ) ) || ! isShiftedMask ( CN -> getZExtValue ( ) , SMPos , SMSize ) ) return SDValue ( ) ; EVT ValTy = N -> getValueType ( <NUM_LIT> ) ; if ( SMPos != <NUM_LIT> || Pos + SMSize > ValTy . getSizeInBits ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ;

return DAG . getNode ( <STR_LIT> , DL , ValTy , ShiftRight . getOperand ( <NUM_LIT> ) , DAG . getConstant ( Pos , DL , <STR_LIT> ) , DAG . getConstant ( SMSize , DL , <STR_LIT> ) ) ;


<s> SmallVector < MachineInstr * , <NUM_LIT> > DeadInstrs ; ArtCombiner . tryCombineMerges ( MI , DeadInstrs , UpdatedDefs ) ; for ( MachineInstr * DeadMI : DeadInstrs ) DeadMI -> eraseFromParent ( ) ;


<s> for ( auto RegNo : getRegList ( ) ) Inst . addOperand ( MCOperand :: createReg ( RegNo ) ) ;


<s> for ( ; AI != AE && PI != PE ; ++ AI , ++ PI ) { Type * ArgType = AI -> getType ( ) ; Type * ParamType = * PI ; if ( ArgType == ParamType ) { Args . push_back ( & * AI ) ; } else { if ( CastInst :: isBitOrNoopPointerCastable ( ArgType , ParamType , DL ) ) { Instruction * PtrCast = CastInst :: CreateBitOrPointerCast ( AI , ParamType , <STR_LIT> ) ; BB -> getInstList ( ) . push_back ( PtrCast ) ; Args . push_back ( PtrCast ) ; } else if ( ArgType -> isStructTy ( ) || ParamType -> isStructTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; WrapperNeeded = false ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Args . size ( ) << <STR_LIT> << * ParamType << <STR_LIT> << * ArgType << <STR_LIT> ) ; TypeMismatch = true ; break ; } } } if ( WrapperNeeded && ! TypeMismatch ) { for ( ; PI != PE ; ++ PI ) Args . push_back ( UndefValue :: get ( * PI ) ) ; if ( F -> isVarArg ( ) ) for ( ; AI != AE ; ++ AI ) Args . push_back ( & * AI ) ;

CallInst * Call = CallInst :: Create ( F , Args , <STR_LIT> , BB ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , TM ( tm ) , RI ( * TM . getSubtargetImpl ( ) , * this ) {


<s> return __aarch64_vdup_laneq_p16 ( __a , __b ) ;


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const {


<s> assert ( Result >= <NUM_LIT> && <STR_LIT> ) ;


<s> if ( MI . readsRegister ( <STR_LIT> , TRI ) ) SingleUseCondition = false ; } if ( ! ConditionDef ) return true ; if ( SingleUseCondition ) { for ( auto * Succ : MBB . successors ( ) ) if ( Succ -> isLiveIn ( <STR_LIT> ) ) SingleUseCondition = false ; } MBP . ConditionDef = ConditionDef ; MBP . SingleUseCondition = SingleUseCondition ; const unsigned TestOpcode = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ConditionDef -> getOpcode ( ) == TestOpcode && ConditionDef -> getNumOperands ( ) == <NUM_LIT> && ConditionDef -> getOperand ( <NUM_LIT> ) . isIdenticalTo ( ConditionDef -> getOperand ( <NUM_LIT> ) ) && ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) ) { MBP . LHS = ConditionDef -> getOperand ( <NUM_LIT> ) ; MBP . RHS = MachineOperand :: CreateImm ( <NUM_LIT> ) ; MBP . Predicate = Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ? MachineBranchPredicate :: PRED_NE : MachineBranchPredicate :: PRED_EQ ; return false ; } return true ;


<s> FinalAction < F > finally ( F && f ) noexcept { return FinalAction < F > ( std :: forward < F > ( f ) ) ;


return lowerVectorShuffleAsSplitOrBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ;


<s> else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;


<s> Table = DecoderTable32 ; } else { Size = <NUM_LIT> ; Table = DecoderTable48 ; } if ( Bytes . size ( ) < Size ) return MCDisassembler :: Fail ; uint64_t Inst = <NUM_LIT> ; for ( uint64_t I = <NUM_LIT> ; I < Size ; ++ I ) Inst = ( Inst << <NUM_LIT> ) | Bytes [ I ] ;

return decodeInstruction ( Table , MI , Inst , Address , this , STI ) ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( getLexer ( ) . getTok ( ) . getString ( ) != <STR_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return MatchOperand_ParseFail ; Parser . Lex ( ) ; std :: string Token ; if ( getLexer ( ) . is ( AsmToken :: Integer ) ) { SMLoc Loc = getLexer ( ) . getTok ( ) . getEndLoc ( ) ; Token = std :: string ( getLexer ( ) . getTok ( ) . getString ( ) ) ; Parser . Lex ( ) ;

if ( getLexer ( ) . getTok ( ) . getLoc ( ) != Loc ) return MatchOperand_ParseFail ;


<s> bool <ISA_LIT>AsmParser :: ParseDirectiveAMDKernelCodeT ( ) { amd_kernel_code_t Header ; <STR_LIT> ( Header , & getSTI ( ) ) ; while ( true ) { while ( trySkipToken ( AsmToken :: EndOfStatement ) ) ; StringRef ID ; if ( ! parseId ( ID , <STR_LIT> ) ) return true ; if ( ID == <STR_LIT> ) break ;

if ( ParseAMDKernelCodeTValue ( ID , Header ) ) return true ;


<s> initializeNVVMIntrRangePass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> return t == cris_unspec || t == cris_got_symbol || t == cris_rel_symbol ;


<s> Value * <ISA_LIT>IREmitter :: visitVQSHLsu ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> Relocation :: Type type = pRelocation . type ( ) ; if ( type > <NUM_LIT> ) {


<s> SDValue PassThru = DAG . getConstant ( <NUM_LIT> , DL , LoadVT ) ; SDValue L = DAG . getMaskedLoad ( LoadVT , DL , MINode -> getChain ( ) , MINode -> getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( PtrTy ) , MINode -> getOperand ( <NUM_LIT> ) , PassThru , MINode -> getMemoryVT ( ) , MINode -> getMemOperand ( ) , <STR_LIT> , <STR_LIT> , false ) ; if ( VT . isFloatingPoint ( ) ) { SDValue Ops [ ] = { DAG . getNode ( <STR_LIT> , DL , VT , L ) , L . getValue ( <NUM_LIT> ) } ; return DAG . getMergeValues ( Ops , DL ) ; }


return DecodeRegisterClass ( Inst , RegNo , IntRegDecoderTable ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) break ; case <STR_LIT> : KnownZero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; break ; case <STR_LIT> : { unsigned IntId = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned NumLoBits = <NUM_LIT> ; switch ( IntId ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { switch ( IntId ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NumLoBits = <NUM_LIT> ; break ; case <STR_LIT> : NumLoBits = <NUM_LIT> ; break ; case <STR_LIT> : NumLoBits = <NUM_LIT> ; break ; case <STR_LIT> : NumLoBits = <NUM_LIT> ; break ; case <STR_LIT> : NumLoBits = <NUM_LIT> ; break ;


<s> static bool elementPairIsContiguous ( ArrayRef < int > Mask , int Elt ) {

assert ( Elt % <NUM_LIT> == <NUM_LIT> ) ;


<s> static DecodeStatus DecodeGPRCRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {

if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;


AU . addRequired < DominatorTreeWrapperPass > ( ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getNumRegistersForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) && VT . getVectorElementType ( ) == <STR_LIT> && Subtarget . hasAVX512 ( ) ) {

unsigned NumElts = VT . getVectorNumElements ( ) ;


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override {


<s> return DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; return MIRBuilder . buildFrameIndex ( LLT :: pointer ( <NUM_LIT> , DL . getPointerSizeInBits ( <NUM_LIT> ) ) , FI ) . getReg ( <NUM_LIT> ) ;


<s> BUILTIN_VDQIF ( UNOP , reduc_smax_scal_ , <NUM_LIT> ) BUILTIN_VDQ_BHSI ( UNOPU , reduc_umax_scal_ , <NUM_LIT> ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_MAX_EXPR , args [ <NUM_LIT> ] ) ; break ; BUILTIN_VDQIF ( UNOP , reduc_smin_scal_ , <NUM_LIT> ) BUILTIN_VDQ_BHSI ( UNOPU , reduc_umin_scal_ , <NUM_LIT> ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_MIN_EXPR , args [ <NUM_LIT> ] ) ; break ; default :


<s> return ; } MCSymbolData * SD = <NUM_LIT> ; if ( Target . getSymA ( ) ) SD = & Asm . getSymbolData ( Target . getSymA ( ) -> getSymbol ( ) ) ; const uint32_t FixupOffset = getFixupOffset ( Layout , Fragment , Fixup ) ; unsigned Index = <NUM_LIT> ; unsigned IsExtern = <NUM_LIT> ; unsigned Type = RelocType ; if ( Target . isAbsolute ( ) ) { report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } else { if ( SD -> getSymbol ( ) . isVariable ( ) ) { int64_t Res ; if ( SD -> getSymbol ( ) . getVariableValue ( ) -> EvaluateAsAbsolute ( Res , Layout , Writer -> getSectionAddressMap ( ) ) ) { FixedValue = Res ; return ; }


<s> case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> TypeSize = OrigTy -> getPrimitiveSizeInBits ( ) ; if ( TypeSize > <NUM_LIT> || TypeSize < <NUM_LIT> ) return false ; if ( ! isSupportedValue ( V ) || ! shouldPromote ( V ) || ! isLegalToPromote ( V ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> << TypeSize << <STR_LIT> ) ; SetVector < Value * > WorkList ; SmallPtrSet < Value * , <NUM_LIT> > Sources ; SmallPtrSet < Instruction * , <NUM_LIT> > Sinks ; WorkList . insert ( V ) ; SmallPtrSet < Value * , <NUM_LIT> > CurrentVisited ; CurrentVisited . clear ( ) ; auto AddLegalInst = [ & ] ( Value * V ) { if ( CurrentVisited . count ( V ) ) return true ; if ( isa < GetElementPtrInst > ( V ) ) return true ; if ( ! isSupportedValue ( V ) || ( shouldPromote ( V ) && ! isLegalToPromote ( V ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; return false ; } WorkList . insert ( V ) ; return true ; } ; while ( ! WorkList . empty ( ) ) { Value * V = WorkList . back ( ) ; WorkList . pop_back ( ) ; if ( CurrentVisited . count ( V ) ) continue ; if ( ! isa < Instruction > ( V ) && ! isSource ( V ) ) continue ; if ( AllVisited . count ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; return false ; } CurrentVisited . insert ( V ) ; AllVisited . insert ( V ) ; if ( isSink ( V ) ) Sinks . insert ( cast < Instruction > ( V ) ) ; if ( isSource ( V ) ) Sources . insert ( V ) ; else if ( auto * I = dyn_cast < Instruction > ( V ) ) { for ( auto & U : I -> operands ( ) ) { if ( ! AddLegalInst ( U ) ) return false ; } } if ( isSource ( V ) || shouldPromote ( V ) ) { for ( Use & U : V -> uses ( ) ) { if ( ! AddLegalInst ( U . getUser ( ) ) ) return false ; } } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto * I : CurrentVisited ) I -> dump ( ) ; ) ; unsigned ToPromote = <NUM_LIT> ; for ( auto * V : CurrentVisited ) { if ( Sources . count ( V ) ) continue ; if ( Sinks . count ( cast < Instruction > ( V ) ) ) continue ; ++ ToPromote ; }

if ( ToPromote < <NUM_LIT> ) return false ;


<s> StructTypeId = StructType -> getId ( ) ; break ; } } if ( StructTypeId == <NUM_LIT> ) { auto FwdTypeEntry = std :: make_unique < BTFTypeFwd > ( TypeName , IsUnion ) ; StructTypeId = addType ( std :: move ( FwdTypeEntry ) ) ; }

for ( auto & DType : Fixup . second . second ) {


<s> if ( Reg == <STR_LIT> ) Reg = MatchRegisterName ( RegName ) ; if ( Reg == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ; BitVector ReservedRegs = Subtarget . getRegisterInfo ( ) -> getReservedRegs ( MF ) ; if ( ! ReservedRegs . test ( Reg ) && ! Subtarget . isRegisterReservedByUser ( Reg ) ) report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ;


<s> gcc_assert ( GET_CODE ( addr ) != AND ) ; if ( ! address_needs_split ( ops [ <NUM_LIT> ] ) ) { reg = gen_reg_rtx ( TImode ) ; emit_insn ( gen_spu_convert ( reg , ops [ <NUM_LIT> ] ) ) ; ops [ <NUM_LIT> ] = change_address ( ops [ <NUM_LIT> ] , TImode , addr ) ; emit_move_insn ( ops [ <NUM_LIT> ] , reg ) ; return <NUM_LIT> ; } if ( GET_CODE ( addr ) == PLUS ) { aform = <NUM_LIT> ; p0 = XEXP ( addr , <NUM_LIT> ) ; p1 = p1_lo = XEXP ( addr , <NUM_LIT> ) ; if ( REG_P ( p0 ) && GET_CODE ( p1 ) == CONST_INT ) { p1_lo = GEN_INT ( INTVAL ( p1 ) & <NUM_LIT> ) ; if ( reg_aligned_for_addr ( p0 ) ) { p1 = GEN_INT ( INTVAL ( p1 ) & - <NUM_LIT> ) ; if ( p1 == const0_rtx ) addr = p0 ; else addr = gen_rtx_PLUS ( SImode , p0 , p1 ) ; } else { rtx x = gen_reg_rtx ( SImode ) ; emit_move_insn ( x , p1 ) ; addr = gen_rtx_PLUS ( SImode , p0 , x ) ; } } } else if ( REG_P ( addr ) ) { aform = <NUM_LIT> ; p0 = addr ; p1 = p1_lo = const0_rtx ; } else {


<s> SmallVector < StringRef , <NUM_LIT> > AsmPieces ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; switch ( AsmPieces . size ( ) ) { default : return false ; case <NUM_LIT> : AsmStr = std :: string ( AsmPieces [ <NUM_LIT> ] ) ; AsmPieces . clear ( ) ; SplitString ( AsmStr , AsmPieces , <STR_LIT> ) ; if ( AsmPieces . size ( ) == <NUM_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && AsmPieces [ <NUM_LIT> ] == <STR_LIT> && IA -> getConstraintString ( ) . compare ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) == <NUM_LIT> ) { IntegerType * Ty = dyn_cast < IntegerType > ( CI -> getType ( ) ) ; if ( Ty && Ty -> getBitWidth ( ) == <NUM_LIT> ) return IntrinsicLowering :: LowerToByteSwap ( CI ) ;


<s> unsigned Binary = <NUM_LIT> ; bool isSPVFP = false ; RegM = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RegM , & isSPVFP ) ; if ( ! isSPVFP ) Binary |= RegM ; else { Binary |= ( ( RegM & <NUM_LIT> ) >> <NUM_LIT> ) ; Binary |= ( RegM & <NUM_LIT> ) << <STR_LIT> ;


<s> static DecodeStatus DecodeDPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = DPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ;


<s> fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_MODE_NAME ( from ) , GET_MODE_NAME ( to ) , reg_class_names [ rclass ] ) ; return ret ;


<s> EVT Op0VT = Op0 . getValueType ( ) ; if ( ( OpVT == <STR_LIT> && Op0VT == <STR_LIT> ) || OpVT == <STR_LIT> ) { RTLIB :: Libcall LC = ( Op . getOpcode ( ) == <STR_LIT> ) ? RTLIB :: getFPTOSINT ( Op0VT , OpVT ) : RTLIB :: getFPTOUINT ( Op0VT , OpVT ) ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; SDValue Dummy ; return ExpandLibCall ( LC , Op , DAG , false , Dummy , TLI ) ; } return Op ;


<s> static rtx or1k_function_arg ( cumulative_args_t cum_v , const function_arg_info & arg ) { if ( arg . end_marker_p ( ) ) return NULL_RTX ;

CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ;


<s> SeenFI = true ; } } MachineOperand * FIOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vaddr ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; assert ( FIOp && FIOp -> isFI ( ) && <STR_LIT> ) ; assert ( TII -> isMUBUF ( MI ) ) ; assert ( TII -> getNamedOperand ( MI , <STR_LIT> :: soffset ) -> getReg ( ) == MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getStackPtrOffsetReg ( ) && <STR_LIT> ) ;

MachineOperand * OffsetOp = TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ;


<s> FILE * f ; int i ; if ( argc < <NUM_LIT> ) return NULL ; if ( strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) && strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) ) return NULL ; kc = kstat_open ( ) ; if ( kc != NULL ) { ksp = kstat_lookup ( kc , CONST_CAST2 ( char * , const char * , <STR_LIT> ) , - <NUM_LIT> , NULL ) ; if ( ksp != NULL && kstat_read ( kc , ksp , NULL ) != - <NUM_LIT> && ksp -> ks_type == KSTAT_TYPE_NAMED ) brand = ( kstat_named_t * ) kstat_data_lookup ( ksp , CONST_CAST2 ( char * , const char * , <STR_LIT> ) ) ; if ( brand == NULL ) brand = ( kstat_named_t * ) kstat_data_lookup ( ksp , CONST_CAST2 ( char * , const char * , <STR_LIT> ) ) ; if ( brand != NULL && brand -> data_type == KSTAT_DATA_STRING ) buf = KSTAT_NAMED_STR_PTR ( brand ) ; if ( brand != NULL && brand -> data_type == KSTAT_DATA_CHAR ) buf = brand -> value . c ; } kstat_close ( kc ) ; for ( i = <NUM_LIT> ; cpu_names [ i ] . name != NULL ; i ++ ) if ( strcmp ( buf , cpu_names [ i ] . name ) == <NUM_LIT> ) cpu = cpu_names [ i ] . cpu ; f = fopen ( <STR_LIT> , <STR_LIT> ) ; if ( f == NULL ) return NULL ; while ( fgets ( buf , sizeof ( buf ) , f ) != NULL ) if ( strncmp ( buf , <STR_LIT> , sizeof ( <STR_LIT> ) - <NUM_LIT> ) == <NUM_LIT> ) { for ( i = <NUM_LIT> ; cpu_names [ i ] . name ; i ++ ) if ( strstr ( buf , cpu_names [ i ] . name ) != NULL ) { cpu = cpu_names [ i ] . cpu ; break ; } break ; }


<s> MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( MBBI -> modifiesRegister ( SrcReg , TRI ) || ( SrcReg2 && MBBI -> modifiesRegister ( SrcReg2 , TRI ) ) ) return false ; MachineOperand CCMask ( MBBI -> getOperand ( <NUM_LIT> ) ) ; assert ( ( CCMask . getImm ( ) & ~ <STR_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand Target ( MBBI -> getOperand ( Type == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) ) ; const uint32_t * RegMask ; if ( Type == <STR_LIT> ) RegMask = MBBI -> getOperand ( <NUM_LIT> ) . getRegMask ( ) ; int CCUse = MBBI -> findRegisterUseOperandIdx ( <STR_LIT> , false , TRI ) ; assert ( CCUse >= <NUM_LIT> && <STR_LIT> ) ; Branch -> RemoveOperand ( CCUse ) ; if ( Type == <STR_LIT> || Type == <STR_LIT> ) Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> RemoveOperand ( <NUM_LIT> ) ; Branch -> setDesc ( TII -> get ( FusedOpcode ) ) ; MachineInstrBuilder MIB ( * Branch -> getParent ( ) -> getParent ( ) , Branch ) ;

MIB . addOperand ( Compare -> getOperand ( <NUM_LIT> ) ) . addOperand ( Compare -> getOperand ( <NUM_LIT> ) ) . addOperand ( CCMask ) ;


<s> <ISA_LIT>SplitTFRCondSets ( <ISA_LIT>TargetMachine & TM ) : MachineFunctionPass ( ID ) , QTM ( TM ) , QST ( * TM . getSubtargetImpl ( ) ) {


<s> Default . second = <STR_LIT> ( F , <STR_LIT> , Default . second ) ; Default . first = std :: min ( Default . first , Default . second ) ; std :: pair < unsigned , unsigned > Requested = <STR_LIT> ( F , <STR_LIT> , Default ) ;

if ( Requested . first > Requested . second ) return Default ;


<s> void setNegated ( bool negated = true ) {


<s> MCSymbolRefExpr :: VariantKind Modifier = Target . isAbsolute ( ) ? MCSymbolRefExpr :: VK_None : Target . getSymA ( ) -> getKind ( ) ; unsigned Type = <NUM_LIT> ; if ( IsPCRel ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case FK_Data_4 : switch ( Modifier ) { default : llvm_unreachable ( <STR_LIT> ) ; case MCSymbolRefExpr :: VK_None : Type = ELF :: R_<ISA_LIT>_REL32 ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_TLSGD : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTTPOFF : Type = ELF :: R_<ISA_LIT>_TLS_IE32 ; break ; } break ; case <STR_LIT> : switch ( Modifier ) { case MCSymbolRefExpr :: VK_<ISA_LIT>_PLT : Type = ELF :: R_<ISA_LIT>_PLT32 ; break ; default : Type = ELF :: R_<ISA_LIT>_CALL ; break ; } break ; case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_JUMP24 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVT_PREL ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVT_PREL ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_MOVW_PREL_NC ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_<ISA_LIT>_THM_CALL ; break ; } } else { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> void addRegGPRCNoR0Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( RRegsNoR0 [ getReg ( ) ] ) ) ;


<s> } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isSplatShuffle ( II -> getOperand ( <NUM_LIT> ) ) ) Ops . push_back ( & II -> getOperandUse ( <NUM_LIT> ) ) ; if ( isSplatShuffle ( II -> getOperand ( <NUM_LIT> ) ) ) Ops . push_back ( & II -> getOperandUse ( <NUM_LIT> ) ) ; return ! Ops . empty ( ) ; case <STR_LIT> : if ( ! areOperandsOfVmullHighP64 ( II -> getArgOperand ( <NUM_LIT> ) , II -> getArgOperand ( <NUM_LIT> ) ) ) return false ; Ops . push_back ( & II -> getArgOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & II -> getArgOperandUse ( <NUM_LIT> ) ) ; return true ; default : return false ; } } switch ( I -> getOpcode ( ) ) { case Instruction :: Sub : case Instruction :: Add : { if ( ! areExtractExts ( I -> getOperand ( <NUM_LIT> ) , I -> getOperand ( <NUM_LIT> ) ) ) return false ; auto Ext1 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; auto Ext2 = cast < Instruction > ( I -> getOperand ( <NUM_LIT> ) ) ; if ( areExtractShuffleVectors ( Ext1 -> getOperand ( <NUM_LIT> ) , Ext2 -> getOperand ( <NUM_LIT> ) ) ) { Ops . push_back ( & Ext1 -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Ext2 -> getOperandUse ( <NUM_LIT> ) ) ; } Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & I -> getOperandUse ( <NUM_LIT> ) ) ; return true ; } case Instruction :: Mul : { bool IsProfitable = false ; for ( auto & Op : I -> operands ( ) ) { if ( any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; ShuffleVectorInst * Shuffle = dyn_cast < ShuffleVectorInst > ( Op ) ; if ( ! Shuffle || ! Shuffle -> isZeroEltSplat ( ) ) continue ; Value * ShuffleOperand = Shuffle -> getOperand ( <NUM_LIT> ) ; InsertElementInst * Insert = dyn_cast < InsertElementInst > ( ShuffleOperand ) ; if ( ! Insert ) continue ; Instruction * OperandInstr = dyn_cast < Instruction > ( Insert -> getOperand ( <NUM_LIT> ) ) ; if ( ! OperandInstr ) continue ; ConstantInt * ElementConstant = dyn_cast < ConstantInt > ( Insert -> getOperand ( <NUM_LIT> ) ) ; if ( ! ElementConstant || ElementConstant -> getZExtValue ( ) != <NUM_LIT> ) continue ; unsigned Opcode = OperandInstr -> getOpcode ( ) ; if ( Opcode != Instruction :: SExt && Opcode != Instruction :: ZExt ) continue ; Ops . push_back ( & Shuffle -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & Op ) ;


<s> if ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Med3 = performIntMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 , false ) ) return Med3 ; } if ( ( ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) || ( Opc == <STR_LIT> && Op0 . getOpcode ( ) == <STR_LIT> ) ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Op0 . hasOneUse ( ) ) { if ( SDValue Res = performFPMed3ImmCombine ( DAG , SDLoc ( N ) , Op0 , Op1 ) ) return Res ; }


<s> unsigned Size = LI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; return Size == <NUM_LIT> ;


<s> default : case OPW32 : case OPW16 : case OPWV216 : return TTMP_32RegClassID ; case OPW64 : return TTMP_64RegClassID ;

case OPW128 : return TTMP_128RegClassID ;


<s> inline disp_t base_reg_disp :: disp ( void ) const {


<s> return ( __m512 ) __builtin_ia32_broadcastf32x2_512_mask ( ( __v4sf ) __A , ( __v16sf ) _mm512_undefined_ps ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ;

O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) << <STR_LIT> ;


<s> expand_set_cint64 ( op0 , op1 ) ; } else { rtx temp = create_temp_reg_if_possible ( Pmode , op0 ) ; if ( TARGET_32BIT ) { emit_insn ( gen_mov_address_32bit_step1 ( temp , op1 ) ) ;

emit_insn ( gen_mov_address_32bit_step2 ( op0 , temp , op1 ) ) ;


<s> void <ISA_LIT>AsmPrinter :: emitEndOfAsmFile ( Module & M ) {


<s> bool <ISA_LIT>DiscriminateMemOps :: runOnMachineFunction ( MachineFunction & MF ) { if ( ! EnableDiscriminateMemops ) return false ; DISubprogram * FDI = MF . getFunction ( ) . getSubprogram ( ) ; if ( ! FDI || ! FDI -> getUnit ( ) -> getDebugInfoForProfiling ( ) ) return false ; const DILocation * ReferenceDI = DILocation :: get ( FDI -> getContext ( ) , FDI -> getLine ( ) , <NUM_LIT> , FDI ) ; assert ( ReferenceDI && <STR_LIT> ) ; DenseMap < Location , unsigned > MemOpDiscriminators ; MemOpDiscriminators [ diToLocation ( ReferenceDI ) ] = <NUM_LIT> ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { const auto & DI = MI . getDebugLoc ( ) ; if ( ! DI ) continue ; if ( BypassPrefetchInstructions && IsPrefetchOpcode ( MI . getDesc ( ) . Opcode ) ) continue ; Location Loc = diToLocation ( DI ) ; MemOpDiscriminators [ Loc ] = std :: max ( MemOpDiscriminators [ Loc ] , DI -> getBaseDiscriminator ( ) ) ; } } DenseMap < Location , DenseSet < unsigned >> Seen ; bool Changed = false ; for ( auto & MBB : MF ) { for ( auto & MI : MBB ) { if ( <STR_LIT> ( MI . getDesc ( ) . TSFlags ) < <NUM_LIT> ) continue ; if ( BypassPrefetchInstructions && IsPrefetchOpcode ( MI . getDesc ( ) . Opcode ) ) continue ; const DILocation * DI = MI . getDebugLoc ( ) ; bool HasDebug = DI ; if ( ! HasDebug ) { DI = ReferenceDI ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * VFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDValue FI = DAG . getFrameIndex ( VFI -> getVarArgsFrameIndex ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ;

const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> return <NUM_LIT> ; case ARII : case PCI : return <NUM_LIT> ; case ARID : case PCD : return <NUM_LIT> ; case AL : return <NUM_LIT> ;


<s> if ( auto SyExp = dyn_cast < MCSymbolRefExpr > ( Expr ) ) { if ( SyExp -> getSymbol ( ) . isInSection ( ) ) return & SyExp -> getSymbol ( ) . getSection ( ) ; return nullptr ; } if ( auto BinOp = dyn_cast < MCBinaryExpr > ( Expr ) ) { auto SectionLHS = getTargetSection ( BinOp -> getLHS ( ) ) ;

auto SectionRHS = getTargetSection ( BinOp -> getRHS ( ) ) ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getIntrinsicInstrCost ( const IntrinsicCostAttributes & ICA , TTI :: TargetCostKind CostKind ) { auto * RetTy = ICA . getReturnType ( ) ; switch ( ICA . getID ( ) ) { case <STR_LIT> : case <STR_LIT> : { auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( LT . second == <STR_LIT> ) return LT . first * <NUM_LIT> ; LLVM_FALLTHROUGH ; } case <STR_LIT> : case <STR_LIT> : { static const auto ValidMinMaxTys = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto LT = TLI -> getTypeLegalizationCost ( DL , RetTy ) ; if ( any_of ( ValidMinMaxTys , [ & LT ] ( MVT M ) { return M == LT . second ; } ) ) return LT . first ; break ;


<s> static struct machine_function * loongarch_init_machine_status ( void ) {

return ggc_cleared_alloc < machine_function > ( ) ;


<s> comp1 = SET_SRC ( comp1 ) ; ifelse1 = SET_SRC ( xcond1 ) ; ifelse2 = SET_SRC ( xcond2 ) ; if ( EQ != GET_CODE ( XEXP ( ifelse1 , <NUM_LIT> ) ) || ! REG_P ( XEXP ( comp1 , <NUM_LIT> ) ) || ! CONST_INT_P ( XEXP ( comp1 , <NUM_LIT> ) ) || XEXP ( ifelse1 , <NUM_LIT> ) != pc_rtx || XEXP ( ifelse2 , <NUM_LIT> ) != pc_rtx || LABEL_REF != GET_CODE ( XEXP ( ifelse1 , <NUM_LIT> ) ) || LABEL_REF != GET_CODE ( XEXP ( ifelse2 , <NUM_LIT> ) ) || ! COMPARISON_P ( XEXP ( ifelse2 , <NUM_LIT> ) ) || REG_CC != REGNO ( XEXP ( XEXP ( ifelse1 , <NUM_LIT> ) , <NUM_LIT> ) ) || REG_CC != REGNO ( XEXP ( XEXP ( ifelse2 , <NUM_LIT> ) , <NUM_LIT> ) ) || const0_rtx != XEXP ( XEXP ( ifelse1 , <NUM_LIT> ) , <NUM_LIT> ) || const0_rtx != XEXP ( XEXP ( ifelse2 , <NUM_LIT> ) , <NUM_LIT> ) ) { return false ; } code = GET_CODE ( XEXP ( ifelse2 , <NUM_LIT> ) ) ; switch ( code ) { case EQ : case LT : case LTU : case GE : case GEU : break ; case LE : case LEU : case GT : case GTU : code = avr_normalize_condition ( code ) ; break ; default : return false ; } target = XEXP ( XEXP ( ifelse1 , <NUM_LIT> ) , <NUM_LIT> ) ; cond = XEXP ( ifelse1 , <NUM_LIT> ) ;

jump = emit_jump_insn_after ( gen_branch_unspec ( target , cond ) , insn1 ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>LEAsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) {

return create<ISA_LIT>AsmBackend ( T , STI , MRI , Options , true ) ;


<s> int <ISA_LIT>RegisterInfo :: getRegisterOrder ( unsigned Reg , const TargetRegisterClass & TRC ) const { for ( unsigned i = <NUM_LIT> ; i < TRC . getNumRegs ( ) ; ++ i ) { if ( regsOverlap ( Reg , TRC . getRegister ( i ) ) ) { return i ; } }


<s> bool isImmXLen ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;

bool IsInRange = isRV64 ( ) ? true : isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ;


<s> int i ; fprintf ( stderr , <STR_LIT> , mode_name [ mode ] , mep_section_tag ( operands [ <NUM_LIT> ] ) , mep_section_tag ( operands [ <NUM_LIT> ] ) ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == HIGH ) return false ; if ( mep_section_tag ( operands [ <NUM_LIT> ] ) == 'f' || mep_section_tag ( operands [ <NUM_LIT> ] ) == 'f' ) { fprintf ( stderr , <STR_LIT> ) ; return false ; } i = mep_section_tag ( operands [ <NUM_LIT> ] ) ; if ( ( i == 'b' || i == 't' ) && ! reload_completed && ! reload_in_progress ) { fprintf ( stderr , <STR_LIT> ) ; return false ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { rtx x = operands [ i ] ; if ( GET_CODE ( x ) == SUBREG ) x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == REG && ! MEP_CONTROL_REG ( x ) ) { fprintf ( stderr , <STR_LIT> ) ; return true ; }


<s> void <ISA_LIT>TargetStreamer :: emitUnwindRaw ( int64_t StackOffset , const SmallVectorImpl < uint8_t > & Opcodes ) {


<s> const TFL * getFrameLowering ( ) const { return static_cast < const TFL * > ( getFrameLowering ( ) ) ;


<s> <ISA_LIT>PassConfig :: <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> SDValue Lo , Hi ; expandShiftParts ( Op . getNode ( ) , Lo , Hi , DAG ) ; return DAG . getMergeValues ( { Lo , Hi } , SDLoc ( Op ) ) ;


<s> if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; isNonExt = LD -> getExtensionType ( ) == <STR_LIT> ; } else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; Alignment = ST -> getAlign ( ) ; isNonExt = ! ST -> isTruncatingStore ( ) ; } else if ( MaskedLoadSDNode * LD = dyn_cast < MaskedLoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Ptr = LD -> getBasePtr ( ) ; Alignment = LD -> getAlign ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ; isNonExt = LD -> getExtensionType ( ) == <STR_LIT> ; IsMasked = true ; } else if ( MaskedStoreSDNode * ST = dyn_cast < MaskedStoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Ptr = ST -> getBasePtr ( ) ; Alignment = ST -> getAlign ( ) ; isNonExt = ! ST -> isTruncatingStore ( ) ; IsMasked = true ; } else return false ; if ( Subtarget -> isThumb1Only ( ) ) { assert ( Op -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; if ( Op -> getOpcode ( ) != <STR_LIT> || ! isNonExt ) return false ; auto * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS || RHS -> getZExtValue ( ) != <NUM_LIT> ) return false ; if ( Alignment < Align ( <NUM_LIT> ) ) return false ; Offset = Op -> getOperand ( <NUM_LIT> ) ; Base = Op -> getOperand ( <NUM_LIT> ) ; AM = <STR_LIT> ; return true ; } bool isInc ; bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Op , VT , Alignment , isSEXTLoad , IsMasked , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Op , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; } if ( ! isLegal ) return false ; if ( Ptr != Base ) { if ( Ptr == Offset && Op -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> isThumb2 ( ) ) std :: swap ( Base , Offset ) ; if ( Ptr != Base ) return false ; } AM = isInc ? <STR_LIT> : <STR_LIT> ; return true ;


<s> } SDValue RetVal = OutVals [ i ] ; if ( ExtendIntegerRetVal ) { RetVal = DAG . getNode ( Outs [ i ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } else if ( RetVal . getValueSizeInBits ( ) < <NUM_LIT> ) { RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } StoreOperands . push_back ( RetVal ) ; if ( VectorInfo [ i ] & PVF_LAST ) { <STR_LIT> Op ; unsigned NumElts = StoreOperands . size ( ) - <NUM_LIT> ; switch ( NumElts ) { case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> : Op = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } EVT TheStoreType = ExtendIntegerRetVal ? <STR_LIT> : VTs [ i ] ; Chain = DAG . getMemIntrinsicNode ( Op , dl , DAG . getVTList ( <STR_LIT> ) , StoreOperands , TheStoreType , MachinePointerInfo ( ) , Align ( <NUM_LIT> ) , MachineMemOperand :: MOStore ) ; StoreOperands . clear ( ) ; } } return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;


<s> bool <ISA_LIT>Operand :: isInlineValue ( ) const { return isRegKind ( ) && :: isInlineValue ( getReg ( ) ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) { return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ;


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> int64_t Shift = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Shift <= <NUM_LIT> ) return ; Shift -= <NUM_LIT> ; Inst . getOperand ( <NUM_LIT> ) . setImm ( Shift ) ; switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> : Inst . setOpcode ( <STR_LIT> ) ; return ; case <STR_LIT> :


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N ) { SmallVector < int , <NUM_LIT> > M ; N -> getMask ( M ) ;

return :: isUNPCKL_v_undef_Mask ( M , N -> getValueType ( <NUM_LIT> ) ) ;


<s> O << formatHex ( MI -> getOperand ( OpNo ) . getImm ( ) & <NUM_LIT> ) ;


<s> DAG . MorphNodeTo ( BR , <STR_LIT> , BR -> getVTList ( ) , Ops , <NUM_LIT> ) ; } SDValue Chain = SDValue ( Result , Result -> getNumValues ( ) - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Intr -> getNumValues ( ) - <NUM_LIT> ; i != e ; ++ i ) { SDNode * CopyToReg = findUser ( SDValue ( Intr , i ) , <STR_LIT> ) ; if ( ! CopyToReg ) continue ; Chain = DAG . getCopyToReg ( Chain , DL , CopyToReg -> getOperand ( <NUM_LIT> ) , SDValue ( Result , i - <NUM_LIT> ) , SDValue ( ) ) ; DAG . ReplaceAllUsesWith ( SDValue ( CopyToReg , <NUM_LIT> ) , CopyToReg -> getOperand ( <NUM_LIT> ) ) ; } DAG . ReplaceAllUsesOfValueWith ( SDValue ( Intr , Intr -> getNumValues ( ) - <NUM_LIT> ) , Intr -> getOperand ( <NUM_LIT> ) ) ;


<s> const MCOperandInfo * OpInfo = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . OpInfo ; MCInst :: iterator I = MI . begin ( ) ; unsigned short NumOps = <ISA_LIT>Insts [ MI . getOpcode ( ) ] . NumOperands ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i , ++ I ) { if ( OpInfo [ i ] . isPredicate ( ) ) { if ( CC != <STR_LIT> && ! <ISA_LIT>Insts [ MI . getOpcode ( ) ] . isPredicable ( ) ) Check ( S , SoftFail ) ; I -> setImm ( CC ) ; ++ I ; if ( CC == <STR_LIT> ) I -> setReg ( <NUM_LIT> ) ; else I -> setReg ( <STR_LIT> ) ;


<s> if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( createInterleavedLoadCombinePass ( ) ) ; addPass ( createInterleavedAccessPass ( ) ) ; } if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ;


<s> bool hasBase ( ) const { return BaseType == FrameIndexBase || BaseReg . getNode ( ) != nullptr ;


<s> void <ISA_LIT>MCCodeEmitter :: EmitOpcodePrefix ( uint64_t TSFlags , unsigned & CurByte , int MemOperand , const MCInst & MI , const MCInstrDesc & Desc , const MCSubtargetInfo & STI , raw_ostream & OS ) const { unsigned char OpSize = ( TSFlags & <STR_LIT> ) >> <STR_LIT> ; if ( OpSize == ( is16BitMode ( STI ) ? <STR_LIT> : <STR_LIT> ) ) EmitByte ( <NUM_LIT> , CurByte , OS ) ; switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } if ( is64BitMode ( STI ) ) { if ( unsigned REX = DetermineREXPrefix ( MI , TSFlags , Desc ) ) EmitByte ( <NUM_LIT> | REX , CurByte , OS ) ; } switch ( TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> break ; case k_MemoryZeroRegImm : assert ( getMemOffset ( ) != nullptr ) ; OS << <STR_LIT> << getMemIndexReg ( ) << <STR_LIT> << * getMemOffset ( ) << <STR_LIT> ; break ; case k_MemoryZeroImmImm : assert ( getMemIndex ( ) != nullptr && getMemOffset ( ) != nullptr ) ; OS << <STR_LIT> << * getMemIndex ( ) << <STR_LIT> << * getMemOffset ( ) << <STR_LIT> ; break ; }


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> static bool isSubRegOf ( const <ISA_LIT>RegisterInfo & TRI , const MachineOperand & SuperVec , const MachineOperand & SubReg ) { if ( SubReg . getReg ( ) . isPhysical ( ) ) return TRI . isSubRegister ( SuperVec . getReg ( ) , SubReg . getReg ( ) ) ; return SubReg . getSubReg ( ) != <STR_LIT> && SubReg . getReg ( ) == SuperVec . getReg ( ) ;


<s> assert ( AM . Scale == <NUM_LIT> || AM . Scale == <NUM_LIT> || AM . Scale == <NUM_LIT> || AM . Scale == <NUM_LIT> ) ; if ( AM . BaseType == <STR_LIT> ) MIB . addReg ( AM . Base . Reg ) ; else if ( AM . BaseType == <STR_LIT> ) MIB . addFrameIndex ( AM . Base . FrameIndex ) ; else assert ( <NUM_LIT> ) ;

MIB . addImm ( AM . Scale ) . addReg ( AM . IndexReg ) ;


<s> EHStreamer . EmitUnwindInfo ( * this , getCurrentWinFrameInfo ( ) ) ;


<s> bool <ISA_LIT>FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( ! Subtarget . isSVR4ABI ( ) ) return false ; MachineFunction * MF = MBB . getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * Subtarget . getInstrInfo ( ) ; <ISA_LIT>FunctionInfo * FI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool MustSaveTOC = FI -> mustSaveTOC ( ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == <STR_LIT> && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = <STR_LIT> <= Reg && Reg <= <STR_LIT> ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; bool IsLiveIn = MRI . isLiveIn ( Reg ) ; if ( ! IsLiveIn ) MBB . addLiveIn ( Reg ) ;


if ( ! ( Subtarget . hasAVX2 ( ) && ( isShuffleMaskInputInPlace ( <NUM_LIT> , Mask ) || isShuffleMaskInputInPlace ( <NUM_LIT> , Mask ) ) ) ) if ( SDValue Result = lowerVectorShuffleByMerging128BitLanes ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Result ;


<s> return StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( name ) . Case ( <STR_LIT> , VK_<ISA_LIT>_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_GOT_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_LO ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_ADD ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GOT_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_CAPTAB_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TPREL_CINCOFFSET ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI ) . Case ( <STR_LIT> , VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI ) . Default ( VK_<ISA_LIT>_Invalid ) ;


<s> bool NeedCFI = MF . getMMI ( ) . hasDebugInfo ( ) || MF . getFunction ( ) -> needsUnwindTableEntry ( ) ;


<s> const char * getPassName ( ) const override {


<s> rtx x ; gcc_assert ( SYMBOL_REF_DECL ( symbol ) ) ; imp_decl = get_dllimport_decl ( SYMBOL_REF_DECL ( symbol ) , true ) ; x = DECL_RTL ( imp_decl ) ;

if ( want_reg ) x = force_reg ( Pmode , x ) ;


<s> if ( rclass == CCREGS ) return mode == BImode ; if ( mode == PDImode || mode == V2PDImode ) return regno == REG_A0 || regno == REG_A1 ;

if ( mode == DImode ) return regno < REG_M3 ;


<s> Instruction * <ISA_LIT>TargetLowering :: emitTrailingFence ( IRBuilder < > & Builder , Instruction * Inst , AtomicOrdering Ord ) const {

if ( isa < LoadInst > ( Inst ) && isAcquireOrStronger ( Ord ) ) return Builder . CreateFence ( AtomicOrdering :: Acquire ) ;


<s> assert ( ( Indices . size ( ) % <NUM_LIT> ) == <NUM_LIT> ) ; int SplatIndex = - <NUM_LIT> ; for ( const auto & V : Indices ) { if ( V != - <NUM_LIT> ) { SplatIndex = V ; break ; } } return fitsRegularPattern < int > ( Indices . begin ( ) , <NUM_LIT> , Indices . end ( ) , SplatIndex , <NUM_LIT> ) ;


<s> void <ISA_LIT>TargetLowering :: InitReservedFrameCount ( const Function * F ) { unsigned NumArgs = F -> arg_size ( ) ; bool isVoidFunc = ( F -> getReturnType ( ) -> getTypeID ( ) == Type :: VoidTyID ) ; if ( isVoidFunc ) ReservedFrameCount = NumArgs ; else ReservedFrameCount = NumArgs + <NUM_LIT> ;


<s> if ( <STR_LIT> ( ShiftTypeAndValue ) == <STR_LIT> ) { uint64_t ShiftAmt = <STR_LIT> ( ShiftTypeAndValue ) ; Mask <<= ShiftAmt ; getUsefulBits ( Op , Mask , Depth + <NUM_LIT> ) ; Mask . lshrInPlace ( ShiftAmt ) ; } else if ( <STR_LIT> ( ShiftTypeAndValue ) == <STR_LIT> ) { uint64_t ShiftAmt = <STR_LIT> ( ShiftTypeAndValue ) ;


<s> unsigned RetReg = <STR_LIT> ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue RetAddr ; if ( depth == <NUM_LIT> ) RetAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , RetReg , VT ) ; else { SDValue Chain = getFLUSHW ( Op , DAG ) ; RetAddr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , VT ) ; for ( uint64_t i = <NUM_LIT> ; i != depth ; ++ i ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetAddr , DAG . getIntPtrConstant ( ( i == depth - <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ) ; RetAddr = DAG . getLoad ( <STR_LIT> , dl , Chain , Ptr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } } return RetAddr ;


<s> EVT HalfVT = VT . getHalfNumVectorElementsVT ( Ctx ) ; Type * HalfTy = HalfVT . getTypeForEVT ( Ctx ) ; LoadInst * Lo , * Hi ; std :: tie ( Lo , Hi ) = LoadMap [ ST -> getValueOperand ( ) ] ; Value * Ptr = ST -> getPointerOperand ( ) ;

PointerType * HalfPtrTy = HalfTy -> getPointerTo ( ST -> getPointerAddressSpace ( ) ) ;


<s> if ( V0 . getNode ( ) == <NUM_LIT> ) { V0 = Elt . getOperand ( <NUM_LIT> ) ; V0NumElts = V0 . getValueType ( ) . getVectorNumElements ( ) ; } if ( Elt . getOperand ( <NUM_LIT> ) == V0 ) { Mask [ i ] = ( cast < ConstantSDNode > ( Elt -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; continue ; } else if ( V1 . getNode ( ) == <NUM_LIT> ) { V1 = Elt . getOperand ( <NUM_LIT> ) ; } if ( Elt . getOperand ( <NUM_LIT> ) == V1 ) { unsigned Lane = cast < ConstantSDNode > ( Elt -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Mask [ i ] = ( Lane + V0NumElts ) ; continue ; } else {


<s> return SrcRC != & <STR_LIT> && TRI . isSGPRClass ( DstRC ) && TRI . hasVGPRs ( SrcRC ) ;


<s> bool hasLoadArgs ( ) const { return HasLoadArgs ;


<s> static __inline qword si_frsqest ( qword a ) { return ( ( qword ) ( vec_rsqrte ( ( vec_float4 ) ( a ) ) ) ) ;


<s> for ( auto * MI : C . instructions ( ) ) Cost += Converters . find ( { DstDomain , MI -> getOpcode ( ) } ) -> second -> getExtraCost ( MI , MRI ) ;


<s> value * merge_cells ( value * cl1 , value * cl2 ) const { auto b1 = std :: get < cell > ( * cl1 ) . b ;

auto b2 = std :: get < cell > ( * cl2 ) . b ;


<s> size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ;


<s> std :: tie ( LoV1 , HiV1 ) = SplitVector ( V1 ) ; std :: tie ( LoV2 , HiV2 ) = SplitVector ( V2 ) ; auto HalfBlend = [ & ] ( ArrayRef < int > HalfMask ) { bool UseLoV1 = false , UseHiV1 = false , UseLoV2 = false , UseHiV2 = false ; SmallVector < int , <NUM_LIT> > V1BlendMask , V2BlendMask , BlendMask ; for ( int i = <NUM_LIT> ; i < SplitNumElements ; ++ i ) { int M = HalfMask [ i ] ; if ( M >= NumElements ) { if ( M >= NumElements + SplitNumElements ) UseHiV2 = true ; else UseLoV2 = true ; V2BlendMask . push_back ( M - NumElements ) ; V1BlendMask . push_back ( - <NUM_LIT> ) ; BlendMask . push_back ( SplitNumElements + i ) ; } else if ( M >= <NUM_LIT> ) { if ( M >= SplitNumElements ) UseHiV1 = true ; else UseLoV1 = true ; V2BlendMask . push_back ( - <NUM_LIT> ) ; V1BlendMask . push_back ( M ) ; BlendMask . push_back ( i ) ; } else { V2BlendMask . push_back ( - <NUM_LIT> ) ; V1BlendMask . push_back ( - <NUM_LIT> ) ; BlendMask . push_back ( - <NUM_LIT> ) ; } } if ( ! UseLoV1 && ! UseHiV1 && ! UseLoV2 && ! UseHiV2 ) return DAG . getUNDEF ( SplitVT ) ; if ( ! UseLoV2 && ! UseHiV2 ) return DAG . getVectorShuffle ( SplitVT , DL , LoV1 , HiV1 , V1BlendMask ) ; if ( ! UseLoV1 && ! UseHiV1 ) return DAG . getVectorShuffle ( SplitVT , DL , LoV2 , HiV2 , V2BlendMask ) ; SDValue V1Blend , V2Blend ; if ( UseLoV1 && UseHiV1 ) { V1Blend = DAG . getVectorShuffle ( SplitVT , DL , LoV1 , HiV1 , V1BlendMask ) ; } else { V1Blend = UseLoV1 ? LoV1 : HiV1 ; for ( int i = <NUM_LIT> ; i < SplitNumElements ; ++ i ) if ( BlendMask [ i ] >= <NUM_LIT> && BlendMask [ i ] < SplitNumElements ) BlendMask [ i ] = V1BlendMask [ i ] - ( UseLoV1 ? <NUM_LIT> : SplitNumElements ) ; } if ( UseLoV2 && UseHiV2 ) { V2Blend = DAG . getVectorShuffle ( SplitVT , DL , LoV2 , HiV2 , V2BlendMask ) ; } else { V2Blend = UseLoV2 ? LoV2 : HiV2 ; for ( int i = <NUM_LIT> ; i < SplitNumElements ; ++ i ) if ( BlendMask [ i ] >= SplitNumElements ) BlendMask [ i ] = V2BlendMask [ i ] + ( UseLoV2 ? SplitNumElements : <NUM_LIT> ) ; }

return DAG . getVectorShuffle ( SplitVT , DL , V1Blend , V2Blend , BlendMask ) ;


<s> addPass ( createInterleavedAccessPass ( ) ) ; addPass ( create<ISA_LIT>PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ;


<s> regno = ( BASE_ARG_REG ( mode ) + sh_round_reg ( * ca , mode ) ) ^ ( mode == SFmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN && ! TARGET_HITACHI && ! ca -> renesas_abi ) ; return gen_rtx_REG ( mode , regno ) ; } if ( TARGET_SH5 ) { if ( mode == VOIDmode && TARGET_SHCOMPACT ) return GEN_INT ( ca -> call_cookie ) ; if ( mode == SFmode && ca -> free_single_fp_reg ) return SH5_PROTOTYPED_FLOAT_ARG ( * ca , mode , ca -> free_single_fp_reg ) ; if ( ( GET_SH_ARG_CLASS ( mode ) == SH_ARG_FLOAT ) && ( named || ! ca -> prototype_p ) && ca -> arg_count [ ( int ) SH_ARG_FLOAT ] < NPARM_REGS ( SFmode ) ) { if ( ! ca -> prototype_p && TARGET_SHMEDIA ) return SH5_PROTOTYPELESS_FLOAT_ARG ( * ca , mode ) ; return SH5_PROTOTYPED_FLOAT_ARG ( * ca , mode , FIRST_FP_PARM_REG + ca -> arg_count [ ( int ) SH_ARG_FLOAT ] ) ; } if ( ca -> arg_count [ ( int ) SH_ARG_INT ] < NPARM_REGS ( SImode ) && ( ! TARGET_SHCOMPACT || ( ! SHCOMPACT_FORCE_ON_STACK ( mode , type ) && ! SH5_WOULD_BE_PARTIAL_NREGS ( * ca , mode , type , named ) ) ) ) { return gen_rtx_REG ( mode , ( FIRST_PARM_REG + ca -> arg_count [ ( int ) SH_ARG_INT ] ) ) ; } return NULL_RTX ; } return NULL_RTX ;


<s> MachineInstr & MI = * I ; ++ I ; unsigned Opc = MI . getOpcode ( ) ; if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmValue = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addImm ( ImmValue ) ; B . erase ( & MI ) ; } else if ( Opc == <STR_LIT> ) {


<s> unsigned RegToPrint = RC -> getRegister ( RI -> getEncodingValue ( Reg ) ) ; assert ( RI -> regsOverlap ( RegToPrint , Reg ) ) ; O << <ISA_LIT>InstPrinter :: getRegisterName ( RegToPrint , isVector ? <STR_LIT> : <STR_LIT> ) ;


<s> void printT2AddrModeImm8s4OffsetOperand ( const MCInst * MI , unsigned OpNum ) {


if ( ( TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ! TREE_SIDE_EFFECTS ( decl ) && DECL_INITIAL ( decl ) && ( DECL_INITIAL ( decl ) == error_mark_node || TREE_CONSTANT ( DECL_INITIAL ( decl ) ) ) ) || TREE_CODE ( decl ) != VAR_DECL ) readonly_data_section ( ) ;


<s> bool IsSelfLoop = MBB . isSuccessor ( & MBB ) ; MachineBasicBlock :: instr_iterator MII = MBB . instr_begin ( ) , E = MBB . instr_end ( ) ; MachineBasicBlock :: instr_iterator NextMII ; for ( ; MII != E ; MII = NextMII ) { NextMII = llvm :: next ( MII ) ; MachineInstr * MI = & * MII ; if ( MI -> isBundle ( ) ) { BundleMI = MI ; continue ; } LiveCPSR = UpdateCPSRUse ( * MI , LiveCPSR ) ; unsigned Opcode = MI -> getOpcode ( ) ; DenseMap < unsigned , unsigned > :: iterator OPI = ReduceOpcodeMap . find ( Opcode ) ; if ( OPI != ReduceOpcodeMap . end ( ) ) { const ReduceEntry & Entry = ReduceTable [ OPI -> second ] ; if ( Entry . Special ) { if ( ReduceSpecial ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: instr_iterator I = prior ( NextMII ) ; MI = & * I ; } goto ProcessNext ; } if ( Entry . NarrowOpc2 && ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: instr_iterator I = prior ( NextMII ) ; MI = & * I ; goto ProcessNext ; } if ( Entry . NarrowOpc1 && ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , CPSRDef , IsSelfLoop ) ) { Modified = true ; MachineBasicBlock :: instr_iterator I = prior ( NextMII ) ;


<s> Type * SrcTy = Src -> getType ( ) ; if ( ! isTypeLegal ( SrcTy , SrcVT ) ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; unsigned DestReg = createResultReg ( & <STR_LIT> ) ; unsigned TempReg = createResultReg ( & <STR_LIT> ) ; unsigned Opc = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; emitInst ( Opc , TempReg ) . addReg ( SrcReg ) ; emitInst ( <STR_LIT> , DestReg ) . addReg ( TempReg ) ; updateValueMap ( I , DestReg ) ;


<s> V0 = RegInfo . createVirtualRegister ( RC ) ; V1 = RegInfo . createVirtualRegister ( RC ) ; V2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ;

BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ;


<s> Register Reg ; if ( DT . find ( LLVMTy , CurMF , Reg ) ) { return get<ISA_LIT>TypeForVReg ( Reg ) ; } MachineBasicBlock & BB = * I . getParent ( ) ; auto MIB = BuildMI ( BB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( createTypeVReg ( CurMF -> getRegInfo ( ) ) ) . addUse ( get<ISA_LIT>TypeID ( BaseType ) ) . addImm ( NumElements ) ;

return restOfCreate<ISA_LIT>Type ( LLVMTy , MIB ) ;


<s> return MFI -> getShaderType ( ) == ShaderType :: COMPUTE && TM . getOptLevel ( ) == CodeGenOpt :: None ;


<s> bool <ISA_LIT>AsmParser :: parseSetNoReorderDirective ( ) { Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ;


<s> unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; } if ( Opc == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { int32_t Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return false ; } if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isInlineAsm ( ) ) return false ; unsigned W = RC . width ( ) ; while ( W > <NUM_LIT> && RC [ W - <NUM_LIT> ] . is ( <NUM_LIT> ) ) W -- ; if ( W == <NUM_LIT> || W == RC . width ( ) ) return false ; unsigned NewOpc = ( W == <NUM_LIT> ) ? <STR_LIT> : ( W == <NUM_LIT> ) ? <STR_LIT> : ( W < <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( auto & Op : MI -> uses ( ) ) { if ( ! Op . isReg ( ) ) continue ; BitTracker :: RegisterRef RS = Op ; if ( ! BT . has ( RS . Reg ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; unsigned BN , BW ; if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; if ( BW < W || ! HBS :: isEqual ( RC , <NUM_LIT> , SC , BN , W ) ) continue ; if ( ! validateReg ( RS , NewOpc , <NUM_LIT> ) ) continue ;

unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ;


<s> Value = ( Value & <NUM_LIT> ) >> <NUM_LIT> ; ldi :: fixup ( Size , Fixup , Value , Ctx ) ;


<s> return ( strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strncmp ( section , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> || strcmp ( section , <STR_LIT> ) == <NUM_LIT> || strncmp ( section , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) ;


<s> return ( float64x1_t ) { __builtin_aarch64_fmulxdf ( __a [ <NUM_LIT> ] , __b [ <NUM_LIT> ] ) } ;


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const { if ( TRI -> hasBasePointer ( MF ) ) FrameReg = TRI -> getBaseRegister ( ) ;

else if ( TRI -> needsStackRealignment ( MF ) ) FrameReg = TRI -> getStackRegister ( ) ;


<s> if ( isTargetShuffle ( Opcode ) ) { MVT ShufVT = VT . getSimpleVT ( ) ; MVT ShufSVT = ShufVT . getVectorElementType ( ) ; int NumElems = ( int ) ShufVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; SmallVector < SDValue , <NUM_LIT> > ShuffleOps ; bool IsUnary ; if ( ! getTargetShuffleMask ( Op . getNode ( ) , ShufVT , true , ShuffleOps , ShuffleMask , IsUnary ) ) return SDValue ( ) ; int Elt = ShuffleMask [ Index ] ; if ( Elt == SM_SentinelZero ) return ShufSVT . isInteger ( ) ? DAG . getConstant ( <NUM_LIT> , SDLoc ( Op ) , ShufSVT ) : DAG . getConstantFP ( + <NUM_LIT> , SDLoc ( Op ) , ShufSVT ) ; if ( Elt == SM_SentinelUndef ) return DAG . getUNDEF ( ShufSVT ) ; assert ( <NUM_LIT> <= Elt && Elt < ( <NUM_LIT> * NumElems ) && <STR_LIT> ) ; SDValue Src = ( Elt < NumElems ) ? ShuffleOps [ <NUM_LIT> ] : ShuffleOps [ <NUM_LIT> ] ; return getShuffleScalarElt ( Src , Elt % NumElems , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue Sub = Op . getOperand ( <NUM_LIT> ) ; uint64_t SubIdx = Op . getConstantOperandVal ( <NUM_LIT> ) ; unsigned NumSubElts = Sub . getValueType ( ) . getVectorNumElements ( ) ; if ( SubIdx <= Index && Index < ( SubIdx + NumSubElts ) ) return getShuffleScalarElt ( Sub , Index - SubIdx , DAG , Depth + <NUM_LIT> ) ; return getShuffleScalarElt ( Vec , Index , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { EVT SubVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned NumSubElts = SubVT . getVectorNumElements ( ) ; uint64_t SubIdx = Index / NumSubElts ; uint64_t SubElt = Index % NumSubElts ; return getShuffleScalarElt ( Op . getOperand ( SubIdx ) , SubElt , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; uint64_t SrcIdx = Op . getConstantOperandVal ( <NUM_LIT> ) ; return getShuffleScalarElt ( Src , Index + SrcIdx , DAG , Depth + <NUM_LIT> ) ; } if ( Opcode == <STR_LIT> ) { SDValue Src = Op . getOperand ( <NUM_LIT> ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> unsigned int NumElts = VT . getVectorNumElements ( ) ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return SDValue ( ) ; if ( VT . is512BitVector ( ) && InVT . getVectorElementType ( ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; assert ( InVT . getVectorElementType ( ) == <STR_LIT> && <STR_LIT> ) ; MVT ExtVT = ( NumElts == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; Constant * C = ConstantInt :: get ( * DAG . getContext ( ) , APInt :: getAllOnesValue ( ExtVT . getScalarType ( ) . getSizeInBits ( ) ) ) ; SDValue CP = DAG . getConstantPool ( C , TLI . getPointerTy ( ) ) ;

unsigned Alignment = cast < ConstantPoolSDNode > ( CP ) -> getAlignment ( ) ;


<s> for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] != - <NUM_LIT> && Mask [ i ] != i && Mask [ i ] != i + Size ) return SDValue ( ) ; MaskOps . push_back ( Mask [ i ] < Size ? AllOnes : Zero ) ; } SDValue V1Mask = DAG . getBuildVector ( VT , DL , MaskOps ) ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V1Mask ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getSizeInBits ( ) / <NUM_LIT> ) ; V2 = DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , MaskVT , DAG . getBitcast ( MaskVT , V1Mask ) , DAG . getBitcast ( MaskVT , V2 ) ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ;


<s> case CRYPTO_BUILTIN_VPMSUMD : case CRYPTO_BUILTIN_VPMSUM : case MISC_BUILTIN_ADDG6S : case MISC_BUILTIN_DIVWEU : case MISC_BUILTIN_DIVDEU : case VSX_BUILTIN_UDIV_V2DI : case ALTIVEC_BUILTIN_VMAXUB : case ALTIVEC_BUILTIN_VMINUB : case ALTIVEC_BUILTIN_VMAXUH : case ALTIVEC_BUILTIN_VMINUH : case ALTIVEC_BUILTIN_VMAXUW : case ALTIVEC_BUILTIN_VMINUW : case P8V_BUILTIN_VMAXUD : case P8V_BUILTIN_VMINUD : case ALTIVEC_BUILTIN_VAND_V16QI_UNS : case ALTIVEC_BUILTIN_VAND_V8HI_UNS : case ALTIVEC_BUILTIN_VAND_V4SI_UNS : case ALTIVEC_BUILTIN_VAND_V2DI_UNS : case ALTIVEC_BUILTIN_VANDC_V16QI_UNS : case ALTIVEC_BUILTIN_VANDC_V8HI_UNS : case ALTIVEC_BUILTIN_VANDC_V4SI_UNS : case ALTIVEC_BUILTIN_VANDC_V2DI_UNS : case ALTIVEC_BUILTIN_VNOR_V16QI_UNS : case ALTIVEC_BUILTIN_VNOR_V8HI_UNS : case ALTIVEC_BUILTIN_VNOR_V4SI_UNS : case ALTIVEC_BUILTIN_VNOR_V2DI_UNS : case ALTIVEC_BUILTIN_VOR_V16QI_UNS : case ALTIVEC_BUILTIN_VOR_V8HI_UNS : case ALTIVEC_BUILTIN_VOR_V4SI_UNS : case ALTIVEC_BUILTIN_VOR_V2DI_UNS : case ALTIVEC_BUILTIN_VXOR_V16QI_UNS : case ALTIVEC_BUILTIN_VXOR_V8HI_UNS : case ALTIVEC_BUILTIN_VXOR_V4SI_UNS : case ALTIVEC_BUILTIN_VXOR_V2DI_UNS : case P8V_BUILTIN_EQV_V16QI_UNS : case P8V_BUILTIN_EQV_V8HI_UNS : case P8V_BUILTIN_EQV_V4SI_UNS : case P8V_BUILTIN_EQV_V2DI_UNS : case P8V_BUILTIN_EQV_V1TI_UNS : case P8V_BUILTIN_NAND_V16QI_UNS : case P8V_BUILTIN_NAND_V8HI_UNS : case P8V_BUILTIN_NAND_V4SI_UNS : case P8V_BUILTIN_NAND_V2DI_UNS : case P8V_BUILTIN_NAND_V1TI_UNS : case P8V_BUILTIN_ORC_V16QI_UNS : case P8V_BUILTIN_ORC_V8HI_UNS : case P8V_BUILTIN_ORC_V4SI_UNS : case P8V_BUILTIN_ORC_V2DI_UNS : case P8V_BUILTIN_ORC_V1TI_UNS : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VPERM_16QI_UNS : case ALTIVEC_BUILTIN_VPERM_8HI_UNS : case ALTIVEC_BUILTIN_VPERM_4SI_UNS : case ALTIVEC_BUILTIN_VPERM_2DI_UNS : case ALTIVEC_BUILTIN_VSEL_16QI_UNS : case ALTIVEC_BUILTIN_VSEL_8HI_UNS : case ALTIVEC_BUILTIN_VSEL_4SI_UNS : case ALTIVEC_BUILTIN_VSEL_2DI_UNS : case VSX_BUILTIN_VPERM_16QI_UNS : case VSX_BUILTIN_VPERM_8HI_UNS : case VSX_BUILTIN_VPERM_4SI_UNS : case VSX_BUILTIN_VPERM_2DI_UNS : case VSX_BUILTIN_XXSEL_16QI_UNS : case VSX_BUILTIN_XXSEL_8HI_UNS : case VSX_BUILTIN_XXSEL_4SI_UNS : case VSX_BUILTIN_XXSEL_2DI_UNS : case CRYPTO_BUILTIN_VPERMXOR : case CRYPTO_BUILTIN_VPERMXOR_V2DI : case CRYPTO_BUILTIN_VPERMXOR_V4SI : case CRYPTO_BUILTIN_VPERMXOR_V8HI : case CRYPTO_BUILTIN_VPERMXOR_V16QI : case CRYPTO_BUILTIN_VSHASIGMAW : case CRYPTO_BUILTIN_VSHASIGMAD : case CRYPTO_BUILTIN_VSHASIGMA : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VPERM_16QI : case ALTIVEC_BUILTIN_VPERM_8HI : case ALTIVEC_BUILTIN_VPERM_4SI : case ALTIVEC_BUILTIN_VPERM_4SF : case ALTIVEC_BUILTIN_VPERM_2DI : case ALTIVEC_BUILTIN_VPERM_2DF : case VSX_BUILTIN_VPERM_16QI : case VSX_BUILTIN_VPERM_8HI : case VSX_BUILTIN_VPERM_4SI : case VSX_BUILTIN_VPERM_4SF : case VSX_BUILTIN_VPERM_2DI : case VSX_BUILTIN_VPERM_2DF : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case VSX_BUILTIN_XVCVUXDSP : case VSX_BUILTIN_XVCVUXDDP_UNS : case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case VSX_BUILTIN_XVCVDPUXDS_UNS : case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI : case MISC_BUILTIN_UNPACK_TD : case MISC_BUILTIN_UNPACK_V1TI : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case ALTIVEC_BUILTIN_VCMPEQUB : case ALTIVEC_BUILTIN_VCMPEQUH : case ALTIVEC_BUILTIN_VCMPEQUW : case P8V_BUILTIN_VCMPEQUD : case VSX_BUILTIN_CMPGE_U16QI : case VSX_BUILTIN_CMPGE_U8HI : case VSX_BUILTIN_CMPGE_U4SI : case VSX_BUILTIN_CMPGE_U2DI : case ALTIVEC_BUILTIN_VCMPGTUB : case ALTIVEC_BUILTIN_VCMPGTUH : case ALTIVEC_BUILTIN_VCMPGTUW : case P8V_BUILTIN_VCMPGTUD : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ; case MISC_BUILTIN_PACK_TD : case MISC_BUILTIN_PACK_V1TI : h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; h . uns_p [ <NUM_LIT> ] = <NUM_LIT> ; break ;


<s> unsigned <ISA_LIT>Subtarget :: getImplicitArgNumBytes ( const Function & F ) const { assert ( <STR_LIT> ( F . getCallingConv ( ) ) ) ;

if ( F . hasFnAttribute ( <STR_LIT> ) ) return <NUM_LIT> ;


<s> } return Result ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) . isFloatingPoint ( ) ) return SDValue ( ) ; unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Op . getValueType ( ) . isFloatingPoint ( ) ) { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;