<s> if ( ! Unsafe && VT == <STR_LIT> && Subtarget -> hasFP32Denormals ( ) ) return SDValue ( ) ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( Unsafe || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } if ( CLHS -> isExactlyValue ( - <NUM_LIT> ) ) { SDValue FNegRHS = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , SL , VT , FNegRHS ) ; } } } const SDNodeFlags * Flags = Op -> getFlags ( ) ; if ( Unsafe || Flags -> hasAllowReciprocal ( ) ) {


<s> return BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Opcode ) ) . addDef ( ResVReg ) . addUse ( GR . get<ISA_LIT>TypeID ( ResType ) ) . addUse ( SrcReg ) . constrainAllUses ( TII , TRI , RBI ) ;


<s> <ISA_LIT>JITInfo :: <ISA_LIT>JITInfo ( <ISA_LIT>Subtarget & STI ) : Subtarget ( STI ) , is64Bit ( STI . is<ISA_LIT>64 ( ) ) {


<s> <STR_LIT> Cond = <STR_LIT> ( MI ) ; if ( Cond != <STR_LIT> && ! MI . mayStore ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && Register :: isVirtualRegister ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { assert ( MI . getOperand ( <NUM_LIT> ) . isDef ( ) && <STR_LIT> ) ; CondRegs [ Cond ] = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( MI . findRegisterDefOperand ( <STR_LIT> ) ) break ;


<s> OperandMatchResultTy parseGR128 ( OperandVector & Operands ) {

return parseRegister ( Operands , RegGR , <STR_LIT> , GR128Reg ) ;


<s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {


<s> clearProcResCounters ( ) ; GrpCount = <NUM_LIT> ; LastFPdOpCycleIdx = UINT_MAX ; LastEmittedMI = nullptr ;

LLVM_DEBUG ( CurGroupDbg = <STR_LIT> ; ) ;


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , <NUM_LIT> , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == <STR_LIT> ) RC = <STR_LIT> ; if ( RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; } else if ( RC == <STR_LIT> || RC == <STR_LIT> || RC == <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> if ( arc_compute_function_type ( current_function_decl ) != ARC_FUNCTION_NORMAL ) return <NUM_LIT> ; if ( ! current_frame_info . initialized ) ( void ) arc_compute_frame_size ( get_frame_size ( ) ) ;


<s> ModulePass * llvm :: create<ISA_LIT>CallGraphBuilder ( ) { return new <ISA_LIT>CallGraphBuilder ( ) ;


<s> case IES_INTEGER : case IES_REGISTER : case IES_RPAREN : State = IES_RBRAC ; if ( CurrState == IES_REGISTER && PrevState != IES_MULTIPLY ) { if ( ! BaseReg ) { BaseReg = TmpReg ; } else { assert ( ! IndexReg && <STR_LIT> ) ; IndexReg = TmpReg ; Scale = <NUM_LIT> ; }


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { return true ; } printSrcMemOperand ( MI , OpNo , O ) ; return false ;


<s> for ( MachineOperand & IMO : DefMI -> uses ( ) ) { if ( IMO . isIdenticalTo ( HeadPhiUse ) ) continue ; if ( IMO . isReg ( ) && IMO . getReg ( ) == Phi -> getOperand ( <NUM_LIT> ) . getReg ( ) ) continue ; OperandStack . push_back ( & IMO ) ; } auto Pos = std :: find ( Path . begin ( ) , Path . end ( ) , DefMI ) ;


<s> if ( SymA -> getSymbol ( ) . getName ( ) == <STR_LIT> || SymA -> getSymbol ( ) . getName ( ) == <STR_LIT> ) return ELF :: R_<ISA_LIT>_ABS32_LO ; } switch ( Target . getAccessVariant ( ) ) { default : break ; case MCSymbolRefExpr :: VK_GOTPCREL : return ELF :: R_<ISA_LIT>_GOTPCREL ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_LO : return ELF :: R_<ISA_LIT>_GOTPCREL32_LO ; case MCSymbolRefExpr :: VK_<ISA_LIT>_GOTPCREL32_HI : return ELF :: R_<ISA_LIT>_GOTPCREL32_HI ; case MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_LO : return ELF :: R_<ISA_LIT>_REL32_LO ; case MCSymbolRefExpr :: VK_<ISA_LIT>_REL32_HI :


<s> assert ( State . PrefixPass == false ) ; MCInst PrefixInst ; PrefixInst . setOpcode ( Opc ) ; State . PrefixPass = true ; Out . EmitInstruction ( PrefixInst ) ; assert ( State . PrefixSaved == <NUM_LIT> ) ;


<s> unsigned SuperReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SubRegLo = MRI . createVirtualRegister ( & AMDGPU :: SGPR_64RegClass ) ; unsigned SubRegHi = MRI . createVirtualRegister ( & AMDGPU :: SGPR_64RegClass ) ; unsigned SubRegHiHi = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; unsigned SubRegHiLo = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B64 ) , SubRegLo ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , SubRegHiLo ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: S_MOV_B32 ) , SubRegHiHi ) . addImm ( AMDGPU :: RSRC_DATA_FORMAT >> <NUM_LIT> ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: REG_SEQUENCE ) , SubRegHi ) . addReg ( SubRegHiLo ) . addImm ( AMDGPU :: sub0 ) . addReg ( SubRegHiHi ) . addImm ( AMDGPU :: sub1 ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: REG_SEQUENCE ) , SuperReg ) . addReg ( SubRegLo ) . addImm ( AMDGPU :: sub0_sub1 ) . addReg ( SubRegHi ) . addImm ( AMDGPU :: sub2_sub3 ) ; MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: V_SUB_F64 : { const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( getTargetMachine ( ) . getInstrInfo ( ) ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: V_ADD_F64 ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: <ISA_LIT>_RegisterStorePseudo : { MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( getTargetMachine ( ) . getInstrInfo ( ) ) ; unsigned Reg = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; MachineInstrBuilder MIB = BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: <ISA_LIT>_RegisterStore ) , Reg ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ;


<s> if ( STI . isDarwinABI ( ) ) return STI . is<ISA_LIT>64 ( ) ? - <NUM_LIT> : - <NUM_LIT> ;


<s> MRI . setPhysRegUnused ( <STR_LIT> ) ; MRI . setPhysRegUnused ( <STR_LIT> ) ; MRI . setPhysRegUnused ( <STR_LIT> ) ; MRI . setPhysRegUnused ( <STR_LIT> ) ;


<ISA_LIT>TargetStreamer :: emitDirectiveSet<ISA_LIT>32R5 ( ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetAt ( ) {


<s> gcc_assert ( sparc_compare_emitted == NULL_RTX ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ;


<s> uint64_t <ISA_LIT>GOTPLT :: emit ( MemoryRegion & pRegion ) { uint32_t * buffer = reinterpret_cast < uint32_t * > ( pRegion . begin ( ) ) ; uint64_t result = <NUM_LIT> ; for ( iterator it = begin ( ) , ie = end ( ) ; it != ie ; ++ it , ++ buffer ) { GOTPLTEntry * got = & ( llvm :: cast < GOTPLTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ;


<s> } else if ( Reg == TRI -> getStackRegister ( ) || Reg == TRI -> getBaseRegister ( ) || Reg == TRI -> getFrameRegister ( * MBB . getParent ( ) ) ) { State . setBegin ( MI ) ; State . setBase ( Reg ) ; State . update ( Offset , Mask ) ;

IsStore ? State . setStore ( ) : State . setLoad ( ) ;


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override {


<s> const GlobalValue * GV = GA -> getGlobal ( ) ; SDLoc dl ( GA ) ; SDValue Offset ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( model == TLSModel :: InitialExec ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ;

SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ;


<s> <ISA_LIT>GatherScatterLowering ( ) : FunctionPass ( ID ) {


<s> uint64_t Control = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; static const unsigned GPRControlBit [ <NUM_LIT> ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Control |= GPRControlBit [ <NUM_LIT> ] ; if ( TFI -> hasFP ( MF ) ) Control |= GPRControlBit [ <NUM_LIT> ] ; MI . getOperand ( <NUM_LIT> ) . setImm ( Control ) ; for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; I ++ ) { if ( ( Control & GPRControlBit [ I ] ) == <NUM_LIT> ) { unsigned Reg = <STR_LIT> [ I ] ;

MI . addOperand ( MachineOperand :: CreateReg ( Reg , true , true ) ) ;


<s> static bool nds32_can_eliminate ( const int from_reg , const int to_reg ) { if ( from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM ) return true ;

if ( from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM ) return true ;


<s> return aarch64_classify_address ( & addr , x , mode , outer_code , strict_p ) ;


<s> void GCNPassConfig :: addPreSched2 ( ) {


<s> addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; addPass ( create<ISA_LIT>FixupLEAs ( ) ) ; }

if ( Triple ( TM -> getTargetTriple ( ) ) . isOSNaCl ( ) ) {


<s> if ( L && ! L -> isLoopInvariant ( MI ) ) return false ; MachineInstr * MovMI = MRI -> getUniqueVRegDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineInstr * SubregToRegMI = nullptr ; if ( MovMI -> getOpcode ( ) == TargetOpcode :: SUBREG_TO_REG ) { SubregToRegMI = MovMI ; MovMI = MRI -> getUniqueVRegDef ( MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( MovMI -> getOpcode ( ) != <STR_LIT> && MovMI -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ! MRI -> hasOneUse ( MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( SubregToRegMI && ! MRI -> hasOneUse ( SubregToRegMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; T UImm = static_cast < T > ( MovMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( SubregToRegMI ) UImm &= <NUM_LIT> ; T Imm1Enc ; T Imm2Enc ; if ( ! splitBitmaskImm ( UImm , RegSize , Imm1Enc , Imm2Enc ) ) return false ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetRegisterClass * ANDImmRC = ( RegSize == <NUM_LIT> ) ? & <STR_LIT> : & <STR_LIT> ;

Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


TARGET_NODE_CASE ( Lo ) TARGET_NODE_CASE ( Hi ) TARGET_NODE_CASE ( GETFUNPLT ) TARGET_NODE_CASE ( GETSTACKTOP ) TARGET_NODE_CASE ( GETTLSADDR ) TARGET_NODE_CASE ( MEMBARRIER ) TARGET_NODE_CASE ( CALL ) TARGET_NODE_CASE ( RET_FLAG ) TARGET_NODE_CASE ( GLOBAL_BASE_REG ) }


<s> if ( IsCompleted ) return ; IsCompleted = true ; BTFType . NameOff = BDebug . addString ( ETy -> getName ( ) ) ;

DINodeArray Elements = ETy -> getElements ( ) ;


<s> while ( ! Phase2List . empty ( ) ) { processBlockPhase2 ( * Phase2List . front ( ) , TII ) ; Phase2List . pop ( ) ; } for ( MachineBasicBlock & BB : MF ) processBlockPhase3 ( BB , TII ) ; BlockInfo . clear ( ) ;


<s> ParseSubtargetFeatures ( GPU , FS ) ; return * this ;


<s> Register Dummy ; return findCatch ( EHPad , Dummy ) ;


<s> bool <ISA_LIT>ELFObjectWriter :: needsRelocateWithSymbol ( const MCSymbolData & SD , unsigned Type ) const { switch ( Type ) {


<s> int64_t Value = ( - Op2 -> getAPIntValue ( ) ) . getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Value ) || Subtarget . hasInterlockedAccess1 ( ) ) NegSrc2 = DAG . getConstant ( Value , MemVT ) ; } else if ( Subtarget . hasInterlockedAccess1 ( ) ) NegSrc2 = DAG . getNode ( <STR_LIT> , DL , MemVT , DAG . getConstant ( <NUM_LIT> , MemVT ) , Src2 ) ; if ( NegSrc2 . getNode ( ) ) return DAG . getAtomic ( <STR_LIT> , DL , MemVT , Node -> getChain ( ) , Node -> getBasePtr ( ) , NegSrc2 , Node -> getMemOperand ( ) , Node -> getOrdering ( ) , Node -> getSynchScope ( ) ) ; return Op ; } return lowerATOMIC_LOAD_OP ( Op , DAG , <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> const IntrinsicData * IntrData = getIntrinsicWithChain ( Intrinsic ) ; if ( ! IntrData ) return false ; Info . opc = <STR_LIT> ; Info . flags = MachineMemOperand :: MONone ; Info . offset = <NUM_LIT> ; switch ( IntrData -> Type ) { case EXPAND_FROM_MEM : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( I . getType ( ) ) ; Info . align = <NUM_LIT> ; Info . flags |= MachineMemOperand :: MOLoad ; break ; } case COMPRESS_TO_MEM : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . align = <NUM_LIT> ; Info . flags |= MachineMemOperand :: MOStore ; break ; } case TRUNCATE_TO_MEM_VI8 : case TRUNCATE_TO_MEM_VI16 : case TRUNCATE_TO_MEM_VI32 : { Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; MVT VT = <STR_LIT> ( I . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT ScalarVT = <STR_LIT> ;

if ( IntrData -> Type == TRUNCATE_TO_MEM_VI8 ) ScalarVT = <STR_LIT> ;


<s> unsigned RangeEnd = Last ; if ( Base == <STR_LIT> ) { if ( Last == <STR_LIT> ) { RangeEnd = <STR_LIT> ; if ( Reg == <STR_LIT> ) { Out = <NUM_LIT> ; return false ; } } if ( Last == <STR_LIT> ) { RangeEnd = <STR_LIT> ; if ( Reg == <STR_LIT> ) { Out = <NUM_LIT> ; return false ; } else if ( Reg == <STR_LIT> ) { Out = <NUM_LIT> ;


<s> <ISA_LIT>AsmBackend ( const Target & T , StringRef TT , bool IsLittle ) : MCAsmBackend ( ) , STI ( <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ( TT , <STR_LIT> , <STR_LIT> ) ) , isThumbMode ( TT . startswith ( <STR_LIT> ) ) , IsLittleEndian ( IsLittle ) {


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & Ctx , const <ISA_LIT>Subtarget & ST , const AsmPrinter & AP ) : <ISA_LIT>MCInstLower ( Ctx , ST , AP ) {


<s> void <ISA_LIT>InstPrinter :: printBranchOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return printOperand ( MI , OpNo , O ) ; O << <STR_LIT> ; printAbsBranchOperand ( MI , OpNo , O ) ;


<s> rtx result = gen_reg_rtx ( TImode ) ; if ( TARGET_SSE2 ) { rtx temp = force_reg ( V2DImode , gen_lowpart ( V2DImode , x ) ) ; rtx lo = gen_lowpart ( DImode , result ) ; emit_insn ( gen_vec_extractv2didi ( lo , temp , const0_rtx ) ) ; rtx hi = gen_highpart ( DImode , result ) ; emit_insn ( gen_vec_extractv2didi ( hi , temp , const1_rtx ) ) ; }

else emit_move_insn ( result , gen_lowpart ( TImode , x ) ) ;


<s> bool GCNTTIImpl :: collectFlatAddressOperands ( SmallVectorImpl < int > & OpIndexes , <STR_LIT> IID ) const { switch ( IID ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OpIndexes . push_back ( <NUM_LIT> ) ; return true ;


<s> if ( DefSymbol . startswith ( <STR_LIT> ) ) { OperandMatchResultTy ResTy = MatchAnyRegisterNameWithoutDollar ( Operands , DefSymbol . substr ( <NUM_LIT> ) , S ) ; if ( ResTy == MatchOperand_Success ) { Parser . Lex ( ) ; return true ; } else if ( ResTy == MatchOperand_ParseFail ) llvm_unreachable ( <STR_LIT> ) ; return false ; } } else if ( Expr -> getKind ( ) == MCExpr :: Constant ) {


<s> if ( ! MRI -> hasOneUse ( Reg ) ) return false ; MachineInstr & OffsetTail = * MRI -> getVRegDef ( Reg ) ; if ( OffsetTail . getOpcode ( ) == <STR_LIT> ) { MachineOperand & AddiImmOp = OffsetTail . getOperand ( <NUM_LIT> ) ; if ( AddiImmOp . getTargetFlags ( ) != <STR_LIT> ) return false ; int64_t OffLo = AddiImmOp . getImm ( ) ; MachineInstr & OffsetLui = * MRI -> getVRegDef ( OffsetTail . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MachineOperand & LuiImmOp = OffsetLui . getOperand ( <NUM_LIT> ) ; if ( OffsetLui . getOpcode ( ) != <STR_LIT> || LuiImmOp . getTargetFlags ( ) != <STR_LIT> || ! MRI -> hasOneUse ( OffsetLui . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; Offset = SignExtend64 < <NUM_LIT> > ( LuiImmOp . getImm ( ) << <NUM_LIT> ) ; Offset += OffLo ; if ( ! ST -> is64Bit ( ) ) Offset = SignExtend64 < <NUM_LIT> > ( Offset ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << OffsetTail << <STR_LIT> << OffsetLui ) ; DeadInstrs . insert ( & OffsetTail ) ; DeadInstrs . insert ( & OffsetLui ) ; return true ; } else if ( OffsetTail . getOpcode ( ) == <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << OffsetTail ) ; Offset = SignExtend64 < <NUM_LIT> > ( OffsetTail . getOperand ( <NUM_LIT> ) . getImm ( ) << <NUM_LIT> ) ;


<s> static DecodeStatus DecodeNegImmOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) {

Inst . addOperand ( MCOperand :: createImm ( - ( int64_t ) Val ) ) ;


<s> for ( auto & MO : J . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) || ! MO . isDead ( ) ) continue ; Register R = MO . getReg ( ) ; if ( R != <STR_LIT> && DeadDefs [ R ] ) return true ;


<s> __inline__ static unsigned long long sh_media_MSHARD_W ( unsigned long long mm , unsigned int mn ) { unsigned long long res ;

__asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ;


<s> ParseSubtargetFeatures ( CPU , FS ) ; return * this ;


<s> } if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { ++ MBBI ; break ; } if ( TII -> isLdStPairSuppressed ( MI ) ) { ++ MBBI ; break ; } bool MergeForward = false ; int SExtIdx = - <NUM_LIT> ; MachineBasicBlock :: iterator Paired = findMatchingInsn ( MBBI , MergeForward , SExtIdx , ScanLimit ) ; if ( Paired != E ) { MBBI = mergePairedInsns ( MBBI , Paired , MergeForward , SExtIdx ) ; Modified = true ; ++ NumPairCreated ; if ( isUnscaledLdst ( MI -> getOpcode ( ) ) ) ++ NumUnscaledPairCreated ; break ; } ++ MBBI ; break ; } } } for ( MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MBBI != E ; ) { MachineInstr * MI = MBBI ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : ++ MBBI ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { ++ MBBI ; break ; } MachineBasicBlock :: iterator Update = findMatchingUpdateInsnForward ( MBBI , ScanLimit , <NUM_LIT> ) ; if ( Update != E ) { MBBI = mergePostIdxUpdateInsn ( MBBI , Update ) ; Modified = true ; ++ NumPostFolded ; break ; } if ( isUnscaledLdst ( Opc ) ) { ++ MBBI ; break ; } Update = findMatchingUpdateInsnBackward ( MBBI , ScanLimit ) ; if ( Update != E ) { MBBI = mergePreIdxUpdateInsn ( MBBI , Update ) ; Modified = true ; ++ NumPreFolded ; break ; }

int Value = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * TII -> getRegClass ( MI -> getDesc ( ) , <NUM_LIT> , TRI , * ( MBB . getParent ( ) ) ) -> getSize ( ) ;


<s> bool aarch64_use_pseudo_pic_reg ( void ) {


<s> PTLI = static_cast < <ISA_LIT>TargetLowering * > ( TM . getTargetLowering ( ) ) ; PMAI = static_cast < const <ISA_LIT>MCAsmInfo * > ( TM . getMCAsmInfo ( ) ) ; PTOF = ( <ISA_LIT>TargetObjectFile * ) & PTLI -> getObjFileLowering ( ) ;


<s> return STI -> getFeatureBits ( ) . test ( FeatureWavefrontSize32 ) ? <NUM_LIT> : <NUM_LIT> ;


<s> if ( <STR_LIT> != R && <STR_LIT> == * SRI ) SoftDefs . insert ( * SRI ) ; else if ( <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) && <ISA_LIT>MCInstrInfo :: isPredReg ( RI , * SRI ) ) LatePreds . insert ( * SRI ) ; else if ( i == <NUM_LIT> && <ISA_LIT>MCInstrInfo :: getType ( MCII , MCI ) == <STR_LIT> ) TmpDefs . insert ( * SRI ) ; else if ( i <= <NUM_LIT> && <ISA_LIT>MCInstrInfo :: hasNewValue2 ( MCII , MCI ) ) Uses . insert ( * SRI ) ; else if ( ! IgnoreTmpDst ) Defs [ * SRI ] . insert ( PredSense ( PredReg , isTrue ) ) ; } } if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) for ( unsigned i = MCID . getNumDefs ( ) ; i < MCID . getNumOperands ( ) ; ++ i ) if ( MCI . getOperand ( i ) . isReg ( ) ) { unsigned P = MCI . getOperand ( i ) . getReg ( ) ; if ( <ISA_LIT>MCInstrInfo :: isPredReg ( RI , P ) ) NewPreds . insert ( P ) ;


<s> rtx limit = force_reg ( DImode , gen_int_mode ( vl , DImode ) ) ;

target = aarch64_target_reg ( target , mode ) ;


<s> EVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue NewRetAddrFrIdx = DAG . getFrameIndex ( NewRetAddr , VT ) ; Chain = DAG . getStore ( Chain , dl , OldRetAddr , NewRetAddrFrIdx , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , NewRetAddr ) , false , false , <NUM_LIT> ) ; if ( isDarwinABI ) { int NewFPLoc = SPDiff + FL -> getFramePointerSaveOffset ( ) ; int NewFPIdx = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , NewFPLoc , true ) ; SDValue NewFramePtrIdx = DAG . getFrameIndex ( NewFPIdx , VT ) ; Chain = DAG . getStore ( Chain , dl , OldFP , NewFramePtrIdx , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , NewFPIdx ) , false , false , <NUM_LIT> ) ;


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , ReciprocalDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * FunctionCallDivCost } , } ; if ( const auto * Entry = CostTableLookup ( CostTbl , ISDOpcode , LT . second ) ) return LT . first * Entry -> Cost ; int Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( LT . second == <STR_LIT> && Op2Info == TargetTransformInfo :: OK_UniformConstantValue ) Cost += <NUM_LIT> ; return Cost ; }


<s> int direct_return ( void ) { return ( reload_completed && xstormy16_compute_stack_layout ( ) . frame_size == <NUM_LIT> ) ;


<s> int64_t Value = ConstExpr -> getValue ( ) ; return ( Value % <NUM_LIT> == <NUM_LIT> ) && ( Value >= <NUM_LIT> ) && ( Value <= <NUM_LIT> ) ; } if ( const <ISA_LIT>MCExpr * SymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( Op . getImm ( ) ) ) return SymbolRefExpr -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( Op . getImm ( ) ) ) {

const <ISA_LIT>MCExpr * LHSSymbolRefExpr = dyn_cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) ;


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> if ( VT == <STR_LIT> && Subtarget -> getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) { return CombineIMinMax ( DL , VT , LHS , RHS , True , False , CC , DAG ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal ) ; } if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } if ( BitsFrom . hasOneUse ( ) ) { APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLO . ShrinkDemandedConstant ( BitsFrom , Demanded ) || TLI . SimplifyDemandedBits ( BitsFrom , Demanded , KnownZero , KnownOne , TLO ) ) { DCI . CommitTargetLoweringOpt ( TLO ) ; } } break ; }


<s> MVT ResTy = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; MVT OpTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSimpleVT ( ) ; ( void ) OpTy ;

assert ( HST -> getVectorLength ( ) * <NUM_LIT> == OpTy . getSizeInBits ( ) ) ;


<s> static inline MCFixupKind getFixupForSize ( unsigned Size , bool isPCRel ) { switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> :

return isPCRel ? FK_PCRel_1 : FK_Data_1 ;


<s> sri -> icode = CODE_FOR_reload_indi_r1 ; break ; default : gcc_unreachable ( ) ; } return NO_REGS ; } } if ( regno >= FIRST_PSEUDO_REGISTER || GET_CODE ( x ) == SUBREG ) regno = true_regnum ( x ) ; if ( ( regno >= FIRST_PSEUDO_REGISTER || regno == - <NUM_LIT> ) && FP_REG_CLASS_P ( rclass ) ) { if ( MEM_P ( x ) ) { x = XEXP ( x , <NUM_LIT> ) ; if ( IS_INDEX_ADDR_P ( x ) ) return NO_REGS ; } sri -> icode = ( in_p ? direct_optab_handler ( reload_in_optab , mode ) : direct_optab_handler ( reload_out_optab , mode ) ) ; return NO_REGS ; } if ( rclass == SHIFT_REGS ) { if ( regno >= FIRST_PSEUDO_REGISTER || regno < <NUM_LIT> ) { sri -> icode = ( in_p ? direct_optab_handler ( reload_in_optab , mode ) : direct_optab_handler ( reload_out_optab , mode ) ) ; return NO_REGS ; } if ( FP_REG_CLASS_P ( REGNO_REG_CLASS ( regno ) ) ) return GENERAL_REGS ;


<s> bool isSRA = Op . getOpcode ( ) == <STR_LIT> ; SDValue ShOpLo = Op . getOperand ( <NUM_LIT> ) ; SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue Tmp1 = isSRA ? DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , DAG . getConstant ( VTBits - <NUM_LIT> , <STR_LIT> ) ) : DAG . getConstant ( <NUM_LIT> , VT ) ; SDValue Tmp2 , Tmp3 ; if ( Op . getOpcode ( ) == <STR_LIT> ) { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShOpLo , ShAmt ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; } else { Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; Tmp3 = DAG . getNode ( isSRA ? <STR_LIT> : <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ; } SDValue AndNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AndNode , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi , Lo ; SDValue CC = DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops0 [ <NUM_LIT> ] = { Tmp2 , Tmp3 , CC , Cond } ; SDValue Ops1 [ <NUM_LIT> ] = { Tmp3 , Tmp1 , CC , Cond } ; if ( Op . getOpcode ( ) == <STR_LIT> ) {

Hi = DAG . getNode ( <STR_LIT> , dl , VT , Ops0 , <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! ML ) break ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; uint64_t LoopSize = <NUM_LIT> ; for ( auto I = ML -> block_begin ( ) , IE = ML -> block_end ( ) ; I != IE ; ++ I ) for ( auto J = ( * I ) -> begin ( ) , JE = ( * I ) -> end ( ) ; J != JE ; ++ J ) { LoopSize += TII -> GetInstSizeInBytes ( J ) ; if ( LoopSize > <NUM_LIT> ) break ; } if ( LoopSize > <NUM_LIT> && LoopSize <= <NUM_LIT> ) return <NUM_LIT> ; break ; } } return TargetLowering :: getPrefLoopAlignment ( ML ) ;


<s> emitLeadingFence ( Builder , CI , Ord ) ; Value * LoHi = Builder . CreateCall ( IntCmpXchg , { Addr , CmpLo , CmpHi , NewLo , NewHi } ) ; emitTrailingFence ( Builder , CI , Ord ) ; Value * Lo = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Value * Hi = Builder . CreateExtractValue ( LoHi , <NUM_LIT> , <STR_LIT> ) ; Lo = Builder . CreateZExt ( Lo , ValTy , <STR_LIT> ) ; Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ;

return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { return expandExtendStackPseudo ( MI ) ; } case <STR_LIT> : { MI . eraseFromParent ( ) ; return true ; } } return false ;


<s> } unsigned Start , End ; if ( TII -> isRxSBGMask ( Value , BitsPerElement , Start , End ) ) { Start -= <NUM_LIT> - BitsPerElement ; End -= <NUM_LIT> - BitsPerElement ; MVT VecVT = <STR_LIT> ( <STR_LIT> ( BitsPerElement ) , <STR_LIT> / BitsPerElement ) ; SDValue Op = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getConstant ( Start , DL , <STR_LIT> , false , true ) , DAG . getConstant ( End , DL , <STR_LIT> , false , true ) ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , Op ) ;


<s> if ( evt == <STR_LIT> || ! evt . isSimple ( ) ) return false ; VT = evt . getSimpleVT ( ) ; if ( VT == <STR_LIT> ) return false ;


return ( __m128i ) __builtin_ia32_pternlogq128_mask ( ( __v2di ) __A , ( __v2di ) __B , ( __v2di ) __C , ( unsigned char ) __imm , ( __mmask8 ) __U ) ;


<s> return ( int32x2_t ) __builtin_neon_vrshlsv2si ( __a , __b ) ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . isCortexA9 ( ) ) addPass ( createMLxExpansionPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . isCortexA15 ( ) && get<ISA_LIT>Subtarget ( ) . hasNEON ( ) && ! DisableA15SDOptimization ) { addPass ( createA15SDOptimizerPass ( ) ) ;


<s> int HalfSize = Mask . size ( ) / <NUM_LIT> ; return HalfNo == <NUM_LIT> ? Mask . drop_back ( HalfSize ) : Mask . drop_front ( HalfSize ) ;


<s> <ISA_LIT>CallLowering :: <ISA_LIT>CallLowering ( const <ISA_LIT>TargetLowering & TLI ) : CallLowering ( & TLI ) {


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMV_OFFSET_MIN_128B ) && ( Offset <= <ISA_LIT>_MEMV_OFFSET_MAX_128B ) ; case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( Offset ) ; } if ( Extend ) return true ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMW_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMW_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMD_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMD_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMH_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMH_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( Offset >= <ISA_LIT>_MEMB_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_MEMB_OFFSET_MAX ) ; case <STR_LIT> : return ( Offset >= <ISA_LIT>_ADDI_OFFSET_MIN ) && ( Offset <= <ISA_LIT>_ADDI_OFFSET_MAX ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : case <STR_LIT> :


<s> if ( i2 == NULL ) return <NUM_LIT> ; i3 = next_nonnote_insn ( i2 ) ; if ( i3 == NULL ) return <NUM_LIT> ;

return ( INSN_P ( i3 ) && rtx_equal_p ( PATTERN ( i1 ) , PATTERN ( i3 ) ) && any_condjump_p ( i2 ) && onlyjump_p ( i2 ) ) ;


<s> PtrArg = getUnderlyingObject ( PtrArg ) ; if ( const AllocaInst * AI = dyn_cast < AllocaInst > ( PtrArg ) ) { if ( ! AI -> isStaticAlloca ( ) || ! AIVisited . insert ( AI ) . second ) continue ; AllocaSize += DL . getTypeAllocSize ( AI -> getAllocatedType ( ) ) ; if ( AllocaSize > ArgAllocaCutoff ) {


<s> static DecodeStatus DecodeIntRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;

RegNo = get<ISA_LIT>RegisterFromNumbering ( RegNo ) ;


<s> if ( ! no_rtl ) { rtx regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( <NUM_LIT> ) ) ) ; move_block_from_reg ( first_reg_offset , regblock , MAX_ARC_PARM_REGS - first_reg_offset ) ; } * pretend_size = ( ( MAX_ARC_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ; }


<s> return Optional < <STR_LIT> > ( ) ; case CmpInst :: FCMP_OEQ : case CmpInst :: ICMP_EQ : return <STR_LIT> ; case CmpInst :: FCMP_OGT : case CmpInst :: ICMP_UGT : case CmpInst :: ICMP_SGT : return <STR_LIT> ; case CmpInst :: FCMP_OGE : case CmpInst :: ICMP_UGE : case CmpInst :: ICMP_SGE : return <STR_LIT> ;


<s> RegisterTargetMachine < <ISA_LIT>ebTargetMachine > X ( The<ISA_LIT>Target ) ;

RegisterTargetMachine < <ISA_LIT>elTargetMachine > Y ( The<ISA_LIT>elTarget ) ;


<s> gcc_assert ( dest != src ) ; insn = emit_move_insn ( dest , src ) ; } else if ( ok_for_max_constant ( INTVAL ( val ) ) ) insn = emit_insn ( gen_addsi3 ( dest , src , val ) ) ; else { val = gen_rtx_CONST ( SImode , gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , val ) , UNSPEC_CONST ) ) ; insn = emit_insn ( gen_addsi3 ( dest , src , val ) ) ;

if ( is_frame_related ) add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( dest , gen_rtx_PLUS ( SImode , src , val ) ) ) ;


<s> auto * WS = getContext ( ) . getWasmSection ( SecName , SectionKind :: getText ( ) , Group , MCContext :: GenericSectionID , nullptr ) ; getStreamer ( ) . SwitchSection ( WS ) ;

if ( getContext ( ) . getGenDwarfForAssembly ( ) ) getContext ( ) . addGenDwarfSection ( WS ) ;


<s> const Function * F = FuncInfo . Fn ; if ( F -> isVarArg ( ) ) return false ; CallingConv :: ID CC = F -> getCallingConv ( ) ; if ( CC != CallingConv :: C ) return false ; if ( Subtarget -> isCallingConvWin64 ( CC ) ) return false ; if ( ! Subtarget -> is64Bit ( ) ) return false ; if ( Subtarget -> useSoftFloat ( ) ) return false ; unsigned GPRCnt = <NUM_LIT> ; unsigned FPRCnt = <NUM_LIT> ; for ( auto const & Arg : F -> args ( ) ) { if ( Arg . hasAttribute ( Attribute :: ByVal ) || Arg . hasAttribute ( Attribute :: InReg ) || Arg . hasAttribute ( Attribute :: StructRet ) || Arg . hasAttribute ( Attribute :: SwiftSelf ) || Arg . hasAttribute ( Attribute :: SwiftAsync ) || Arg . hasAttribute ( Attribute :: SwiftError ) || Arg . hasAttribute ( Attribute :: Nest ) ) return false ; Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> :


<s> Value &= ~ ( <NUM_LIT> << PBitShift ) ; if ( ! LPAC :: isPostOp ( AluCode ) && ( ( Op2 . isImm ( ) && Op2 . getImm ( ) != <NUM_LIT> ) || ( Op2 . isReg ( ) && Op2 . getReg ( ) != <STR_LIT> ) || ( Op2 . isExpr ( ) ) ) ) Value |= ( <NUM_LIT> << PBitShift ) ;

assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ;


<s> void printDFormAddr ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) { assert ( MI -> getOperand ( OpNo ) . isImm ( ) && <STR_LIT> ) ; int64_t value = int64_t ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; int16_t value16 = int16_t ( value ) ;

assert ( ( value16 >= - ( <NUM_LIT> << ( <NUM_LIT> + <NUM_LIT> ) ) && value16 <= ( <NUM_LIT> << ( <NUM_LIT> + <NUM_LIT> ) ) - <NUM_LIT> ) && <STR_LIT> ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } auto VRegAndVal = getIConstantVRegValWithLookThrough ( LaneIdxOp . getReg ( ) , MRI ) ; if ( ! VRegAndVal ) return false ; unsigned LaneIdx = VRegAndVal -> Value . getSExtValue ( ) ; const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ;

MachineInstr * Extract = emitExtractVectorElt ( DstReg , DstRB , NarrowTy , SrcReg , LaneIdx , MIB ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumPairs ; ++ i ) { if ( Pairs [ i ] . Value == Value ) { Valid = true ; return Pairs [ i ] . Name ; } }


<s> assert ( ! ABI . IsCheriPureCap ( ) ) ; assert ( ! Ty . isFatPointer ( ) ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) , DAG . getNode ( <STR_LIT> , DL , Ty , Lo ) ) ;


<s> break ; default : break ; } if ( uses_spr ) { machine_mode mode = ( TARGET_POWERPC64 ) ? DImode : SImode ; op [ nopnds ++ ] = gen_rtx_CONST_INT ( mode , htm_spr_num ( fcode ) ) ; op [ nopnds ++ ] = gen_rtx_REG ( mode , htm_spr_regno ( fcode ) ) ; } else if ( attr & RS6000_BTC_CR ) { cr = gen_reg_rtx ( CCmode ) ; op [ nopnds ++ ] = cr ; } if ( flag_checking ) { int expected_nopnds = <NUM_LIT> ; if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_UNARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_BINARY ) expected_nopnds = <NUM_LIT> ; else if ( ( attr & RS6000_BTC_TYPE_MASK ) == RS6000_BTC_TERNARY ) expected_nopnds = <NUM_LIT> ; if ( ! ( attr & RS6000_BTC_VOID ) ) expected_nopnds += <NUM_LIT> ; if ( uses_spr ) expected_nopnds += <NUM_LIT> ; gcc_assert ( nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS ) ; } switch ( nopnds ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; default : gcc_unreachable ( ) ; } if ( ! pat ) return NULL_RTX ; emit_insn ( pat ) ; if ( attr & RS6000_BTC_CR ) { if ( fcode == HTM_BUILTIN_TBEGIN ) { rtx scratch = gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( scratch , gen_rtx_EQ ( SImode , cr , const0_rtx ) ) ) ; emit_insn ( gen_rtx_SET ( target , gen_rtx_XOR ( SImode , scratch , GEN_INT ( <NUM_LIT> ) ) ) ) ; } else { rtx scratch1 = gen_reg_rtx ( SImode ) ; rtx scratch2 = gen_reg_rtx ( SImode ) ; rtx subreg = simplify_gen_subreg ( CCmode , scratch1 , SImode , <NUM_LIT> ) ;

emit_insn ( gen_movcc ( subreg , cr ) ) ;


<s> else { LL = IsN64 ? <STR_LIT> : <STR_LIT> ; SC = IsN64 ? <STR_LIT> : <STR_LIT> ; ZERO = <STR_LIT> ; BNE = <STR_LIT> ; BEQ = <STR_LIT> ; } unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned OldVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewVal = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Success = RegInfo . createVirtualRegister ( RC ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = BB ; ++ It ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; loop1MBB -> addSuccessor ( exitMBB ) ; loop1MBB -> addSuccessor ( loop2MBB ) ; loop2MBB -> addSuccessor ( loop1MBB ) ; loop2MBB -> addSuccessor ( exitMBB ) ; BB = loop1MBB ;

BuildMI ( BB , dl , TII -> get ( LL ) , Dest ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ;


<s> } unsigned Size = Desc . getSize ( ) ; switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { uint16_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write < uint16_t > ( OS , Bits , <STR_LIT> ) ; break ; } case <NUM_LIT> : { uint32_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; <STR_LIT> :: write ( OS , Bits , <STR_LIT> ) ; break ;


return ( __m256i ) __builtin_ia32_vpconflictdi_256_mask ( ( __v4di ) __A , ( __v4di ) _mm256_setzero_si256 ( ) , ( __mmask8 ) __U ) ;


<s> ScheduleHazardRecognizer * Thumb2InstrInfo :: CreateTargetPostRAHazardRecognizer ( const InstrItineraryData & II ) const { return ( ScheduleHazardRecognizer * ) new Thumb2HazardRecognizer ( II ) ;


<s> bool invalidate ( Function & , const PreservedAnalyses & ) {


<s> unsigned Offset = GetInitialOffset ( Fn ) ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock * MBB = & * MFI ; if ( MBB -> getNumber ( ) > <NUM_LIT> ) { auto & BS = BlockSizes [ MBB -> getNumber ( ) - <NUM_LIT> ] ;


<s> RegisterContext RegCtx ( <STR_LIT> , <STR_LIT> , IsSmallMemAccess ( AccessSize ) ? <STR_LIT> : <STR_LIT> ) ; RegCtx . AddBusyReg ( DstReg ) ; RegCtx . AddBusyReg ( SrcReg ) ; RegCtx . AddBusyReg ( CntReg ) ; InstrumentMemOperandPrologue ( RegCtx , Ctx , Out ) ; { const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , SrcReg , <NUM_LIT> , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ; InstrumentMemOperand ( * Op , AccessSize , false , RegCtx , Ctx , Out ) ; } { const MCExpr * Disp = MCConstantExpr :: Create ( - <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( <NUM_LIT> , Disp , SrcReg , CntReg , AccessSize , SMLoc ( ) , SMLoc ( ) ) ) ;


<s> if ( ! isUndefHI && ! V1 -> isUndef ( ) ) HI = DAG . getNode ( <ISA_LIT>Opcode , DL , NewVT , V1_LO , V1_HI ) ; } else { if ( ! isUndefLO && ( ! V0_LO -> isUndef ( ) || ! V1_LO -> isUndef ( ) ) ) LO = DAG . getNode ( <ISA_LIT>Opcode , DL , NewVT , V0_LO , V1_LO ) ;

if ( ! isUndefHI && ( ! V0_HI -> isUndef ( ) || ! V1_HI -> isUndef ( ) ) ) HI = DAG . getNode ( <ISA_LIT>Opcode , DL , NewVT , V0_HI , V1_HI ) ;


<s> b = ix86_function_value ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) , cfun -> decl , false ) ; if ( STACK_REG_P ( a ) || STACK_REG_P ( b ) ) { if ( ! rtx_equal_p ( a , b ) ) return false ; } else if ( VOID_TYPE_P ( TREE_TYPE ( DECL_RESULT ( cfun -> decl ) ) ) ) ; else if ( ! rtx_equal_p ( a , b ) ) return false ;


<s> EVT VT = Op . getValueType ( ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; EVT ValVT = Val . getValueType ( ) ; assert ( ( ( VT == <STR_LIT> && ValVT == <STR_LIT> ) ) && <STR_LIT> ) ;

return DAG . getTargetInsertSubreg ( ValVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , VT , DAG . getUNDEF ( VT ) , Val ) ;


<s> void MCLDInitialize<ISA_LIT>Emulation ( ) {

mcld :: TargetRegistry :: RegisterEmulation ( mcld :: The<ISA_LIT>_32Target , mcld :: emulate<ISA_LIT>LD ) ;


<s> else if ( Inst . mayLoad ( ) && <STR_LIT> ( Inst . getOpcode ( ) ) == - <NUM_LIT> ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_READ_ACCESS , Inst ) ; else ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_WRITE_ACCESS , Inst ) ; } if ( TII -> usesLGKM_CNT ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , LDS_ACCESS , Inst ) ; if ( mayAccessLDSThroughFlat ( Inst ) ) ScoreBrackets -> setPendingFlat ( ) ; } } else if ( <ISA_LIT>InstrInfo :: isVMEM ( Inst ) && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> ) { if ( ! ST -> hasVscnt ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; else if ( ( Inst . mayLoad ( ) && <STR_LIT> ( Inst . getOpcode ( ) ) == - <NUM_LIT> ) || ( TII -> isMIMG ( Inst ) && ! Inst . mayLoad ( ) && ! Inst . mayStore ( ) ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_READ_ACCESS , Inst ) ; else if ( Inst . mayStore ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_WRITE_ACCESS , Inst ) ; if ( ST -> vmemWriteNeedsExpWaitcnt ( ) && ( Inst . mayStore ( ) || <STR_LIT> ( Inst . getOpcode ( ) ) != - <NUM_LIT> ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMW_GPR_LOCK , Inst ) ; } } else if ( TII -> isSMRD ( Inst ) ) {

ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SMEM_ACCESS , Inst ) ;


<s> MVT VT = CEVT . getSimpleVT ( ) ; if ( const auto * CI = dyn_cast < ConstantInt > ( C ) ) return <ISA_LIT>MaterializeInt ( CI , VT ) ; else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ;

else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ;


<s> else if ( size <= <NUM_LIT> ) { emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size - <NUM_LIT> ) ) ) ; } else { rtx reg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( reg , GEN_INT ( size ) ) ; emit_insn ( gen_stack_pointer_inc ( reg ) ) ; }


<s> if ( <STR_LIT> ( Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return <NUM_LIT> ; if ( Subtarget -> hasV6T2Ops ( ) && Val <= <NUM_LIT> ) return <NUM_LIT> ; if ( <STR_LIT> ( Val ) ) return <NUM_LIT> ; }

if ( Subtarget -> useMovt ( ) ) return <NUM_LIT> ;


<s> for ( unsigned i = <NUM_LIT> ; i < MCID . getNumImplicitUses ( ) ; ++ i ) initReg ( MCI , MCID . getImplicitUses ( ) [ i ] , PredReg , isTrue ) ; const bool IgnoreTmpDst = ( <ISA_LIT>MCInstrInfo :: hasTmpDst ( MCII , MCI ) || <ISA_LIT>MCInstrInfo :: hasHvxTmp ( MCII , MCI ) ) && STI . getFeatureBits ( ) [ <STR_LIT> ] ; if ( const MCPhysReg * ImpDef = MCID . getImplicitDefs ( ) ) for ( ; * ImpDef ; ++ ImpDef ) { unsigned R = * ImpDef ; if ( <STR_LIT> != R && MCID . isCall ( ) ) continue ; if ( <STR_LIT> == R ) continue ; if ( <STR_LIT> == R ) SoftDefs . insert ( R ) ; else if ( isPredicateRegister ( R ) && <ISA_LIT>MCInstrInfo :: isPredicateLate ( MCII , MCI ) ) LatePreds . insert ( R ) ; else if ( ! IgnoreTmpDst ) Defs [ R ] . insert ( PredSense ( PredReg , isTrue ) ) ; } for ( unsigned i = <NUM_LIT> ; i < MCID . getNumDefs ( ) ; ++ i ) { unsigned R = MCI . getOperand ( i ) . getReg ( ) , S = <STR_LIT> ; if ( R == <STR_LIT> ) R = <STR_LIT> ; if ( <ISA_LIT>MCInstrInfo :: IsReverseVecRegPair ( R ) ) ReversePairs . insert ( R ) ; for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ; SRI . isValid ( ) ; ++ SRI ) { if ( MCSubRegIterator ( * SRI , & RI ) . isValid ( ) ) continue ; if ( R == * SRI ) { if ( S == R ) continue ; else S = R ; }

if ( <STR_LIT> != R && <STR_LIT> == * SRI ) SoftDefs . insert ( * SRI ) ;


<s> return BA . Addr -> getType ( ) == NodeAttrs :: Ref && BA . Addr -> getKind ( ) == NodeAttrs :: Def ;


<s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , } ;

if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;


<s> if ( isNullConstant ( Idx ) ) return Op ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT EltVT = Op . getValueType ( ) ; EVT VecVT = Vec . getValueType ( ) ;

SDValue Slidedown = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , Vec , Idx ) ;


<s> MCSymbol * Name = AP . Mang -> getSymbol ( GVar ) ; O << * Name ; } else if ( ConstantExpr * Cexpr = dyn_cast < ConstantExpr > ( v ) ) { O << * <STR_LIT> ( Cexpr , AP ) ; } else llvm_unreachable ( <STR_LIT> ) ; nSym ++ ; if ( nSym >= numSymbols ) nextSymbolPos = size + <NUM_LIT> ; else nextSymbolPos = symbolPosInBuffer [ nSym ] ; } else if ( nBytes == <NUM_LIT> ) O << * ( unsigned int * ) ( buffer + pos ) ;

else O << * ( unsigned long long * ) ( buffer + pos ) ;


<s> DA = & getAnalysis < DivergenceAnalysis > ( ) ; MDR = & getAnalysis < MemoryDependenceWrapperPass > ( ) . getMemDep ( ) ; LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; isKernelFunc = F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_KERNEL ;


<s> void MachineConstPropagator :: removeCFGEdge ( MachineBasicBlock * From , MachineBasicBlock * To ) { From -> removeSuccessor ( To ) ; for ( auto I = To -> begin ( ) , E = To -> getFirstNonPHI ( ) ; I != E ; ++ I ) { MachineInstr * PN = & * I ; int N = PN -> getNumOperands ( ) - <NUM_LIT> ; while ( N > <NUM_LIT> ) { if ( PN -> getOperand ( N + <NUM_LIT> ) . getMBB ( ) == From ) { PN -> RemoveOperand ( N + <NUM_LIT> ) ; PN -> RemoveOperand ( N ) ; } N -= <NUM_LIT> ;


<s> Header = ScopeTop ; break ; } } } for ( MachineLoop * Loop = MLI . getLoopFor ( LayoutPred ) ; Loop && Loop -> contains ( LayoutPred ) ; Loop = Loop -> getParentLoop ( ) ) if ( Loop && LoopBottom ( Loop ) == LayoutPred && Loop -> contains ( Header ) ) return ; MachineBasicBlock :: iterator InsertPos ; MachineLoop * HeaderLoop = MLI . getLoopFor ( Header ) ; if ( HeaderLoop && MBB . getNumber ( ) > LoopBottom ( HeaderLoop ) -> getNumber ( ) ) { InsertPos = Header -> begin ( ) ; } else { InsertPos = Header -> getFirstTerminator ( ) ; while ( InsertPos != Header -> begin ( ) && prev ( InsertPos ) -> definesRegister ( <STR_LIT> ) && prev ( InsertPos ) -> getOpcode ( ) != <STR_LIT> && prev ( InsertPos ) -> getOpcode ( ) != <STR_LIT> && prev ( InsertPos ) -> getOpcode ( ) != <STR_LIT> ) -- InsertPos ; } BuildMI ( * Header , InsertPos , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; InsertPos = MBB . begin ( ) ; while ( InsertPos != MBB . end ( ) && InsertPos -> getOpcode ( ) == <STR_LIT> ) ++ InsertPos ; BuildMI ( MBB , InsertPos , DebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; int Number = MBB . getNumber ( ) ; if ( ! ScopeTops [ Number ] || ScopeTops [ Number ] -> getNumber ( ) > Header -> getNumber ( ) ) ScopeTops [ Number ] = Header ;


<s> explicit MachineModulePass ( char & ID ) : ModulePass ( ID ) {


<s> Inst . addOperand ( MCOperand :: createImm ( Val ) ) ;


<s> static bool ge_sew_lmul_unavailable_p ( const vector_insn_info & info1 , const vector_insn_info & info2 ) { if ( ! info2 . demand_p ( DEMAND_RATIO ) && info2 . demand_p ( DEMAND_GE_SEW ) ) return info1 . get_sew ( ) < info2 . get_sew ( ) ; return true ;


<s> bool useSoftFloat ( ) const { if ( isAIXABI ( ) && ! HasHardFloat ) report_fatal_error ( <STR_LIT> ) ;


<s> if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; for ( MCSubRegIterator I ( getBaseRegister ( ) , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> if ( hasAVLReg ( ) ) return getAVLReg ( ) == <STR_LIT> ;


<s> AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II , ResultReg ) . addImm ( Imm ) ) ; } else { AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , II ) . addImm ( Imm ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( II . ImplicitDefs [ <NUM_LIT> ] ) ) ; }


<s> n = ARRAY_SIZE ( vax_cvt_ops ) ; } for ( i = <NUM_LIT> ; i < n ; ++ i , ++ ops ) if ( ops -> code == code ) { rtx func = ops -> libcall ; if ( ! func ) { func = init_one_libfunc ( TARGET_ABI_OPEN_VMS ? ops -> vms_func : ops -> osf_func ) ; ops -> libcall = func ;


<s> return MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ;


<s> } else { NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: TryFoldLoad ( SDValue P , SDValue N , SDValue & Base , SDValue & Disp , SDValue & Index ) { if ( <STR_LIT> ( N . getNode ( ) ) && N . hasOneUse ( ) && IsLegalAndProfitableToFold ( N . getNode ( ) , P . getNode ( ) , P . getNode ( ) ) ) return SelectAddrRRI20 ( P , N . getOperand ( <NUM_LIT> ) , Base , Disp , Index ) ;


<s> if ( needsStackRealignment ( MF ) && ! TFI -> hasReservedCallFrame ( MF ) ) return true ; if ( AFI -> isThumbFunction ( ) && MFI . hasVarSizedObjects ( ) ) { if ( AFI -> isThumb2Function ( ) && MFI . getLocalFrameSize ( ) < <NUM_LIT> ) return false ; return true ;


<s> bool UseGOT_PREL = ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ; LLVMContext * Context = & MF -> getFunction ( ) -> getContext ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , UseGOT_PREL ? <STR_LIT> : <STR_LIT> , UseGOT_PREL ) ; unsigned ConstAlign = MF -> getDataLayout ( ) . getPrefTypeAlignment ( Type :: getInt32PtrTy ( * Context ) ) ; unsigned Idx = MF -> getConstantPool ( ) -> getConstantPoolIndex ( CPV , ConstAlign ) ; unsigned TempReg = MF -> getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ;

MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , TempReg ) . addConstantPoolIndex ( Idx ) ;


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; unsigned Flags = MCA . getELFHeaderEFlags ( ) ; Flags |= ELF :: EF_MIPS_ARCH_ASE_M16 ; MCA . setELFHeaderEFlags ( Flags ) ;


<s> if ( REG_P ( operands [ <NUM_LIT> ] ) || ( SImode_address_operand ( operands [ <NUM_LIT> ] , VOIDmode ) && REG_P ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ) ) return false ; if ( ! ix86_ok_to_clobber_flags ( insn ) ) return false ; ok = ix86_decompose_address ( operands [ <NUM_LIT> ] , & parts ) ; gcc_assert ( ok ) ; if ( ( parts . base != NULL_RTX ) + ( parts . index != NULL_RTX ) + ( parts . disp != NULL_RTX ) + ( parts . scale > <NUM_LIT> ) < <NUM_LIT> ) return false ; if ( parts . disp && flag_pic && ! LEGITIMATE_PIC_OPERAND_P ( parts . disp ) ) return false ;

regno0 = true_regnum ( operands [ <NUM_LIT> ] ) ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT> ) ;


<s> if ( BaseRegNo != N86 :: EBP ) { if ( Disp . isImm ( ) && Disp . getImm ( ) == <NUM_LIT> && AllowNoDisp ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; return ; } if ( Disp . isExpr ( ) ) { auto * Sym = dyn_cast < MCSymbolRefExpr > ( Disp . getExpr ( ) ) ; if ( Sym && Sym -> getKind ( ) == MCSymbolRefExpr :: VK_TLSCALL ) { Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Sym , FK_NONE , MI . getLoc ( ) ) ) ; emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; return ; } } } if ( Disp . isImm ( ) && AllowDisp8 ) { int ImmOffset = <NUM_LIT> ; if ( isDispOrCDisp8 ( TSFlags , Disp . getImm ( ) , ImmOffset ) ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , FK_Data_1 , StartByte , OS , Fixups , ImmOffset ) ; return ; } } emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) , OS ) ; unsigned Opcode = MI . getOpcode ( ) ; unsigned FixupKind = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; emitImmediate ( Disp , MI . getLoc ( ) , <NUM_LIT> , MCFixupKind ( FixupKind ) , StartByte , OS , Fixups ) ; return ; } assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; int ImmOffset = <NUM_LIT> ; if ( BaseReg == <NUM_LIT> ) { BaseRegNo = <NUM_LIT> ; emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; ForceDisp32 = true ; } else if ( Disp . isImm ( ) && Disp . getImm ( ) == <NUM_LIT> && AllowNoDisp && BaseRegNo != N86 :: EBP ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; } else if ( Disp . isImm ( ) && AllowDisp8 && isDispOrCDisp8 ( TSFlags , Disp . getImm ( ) , ImmOffset ) ) { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; ForceDisp8 = true ; } else { emitByte ( modRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) , OS ) ; ForceDisp32 = true ; } static const unsigned SSTable [ ] = { ~ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> } ; unsigned SS = SSTable [ Scale . getImm ( ) ] ;

unsigned IndexRegNo = IndexReg . getReg ( ) ? get<ISA_LIT>RegNum ( IndexReg ) : <NUM_LIT> ;


<s> const struct xtensa_config_v1 * xtensa_get_config_v1 ( void ) { static const struct xtensa_config_v1 * config ; if ( ! config ) config = ( const struct xtensa_config_v1 * ) xtensa_load_config ( <STR_LIT> , & xtensa_config_v1 , NULL ) ; return config ;


<s> if ( RB . getID ( ) == <STR_LIT> ) { if ( Ty . getSizeInBits ( ) <= <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; return nullptr ; } if ( RB . getID ( ) == <STR_LIT> ) { switch ( Ty . getSizeInBits ( ) ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ;


<s> unsigned OpNum = Ops [ <NUM_LIT> ] ; unsigned Opc = MI -> getOpcode ( ) ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; bool isTwoAddr = NumOps > <NUM_LIT> && MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , TOI :: TIED_TO ) != - <NUM_LIT> ; const DenseMap < unsigned * , std :: pair < unsigned , unsigned > > * OpcodeTablePtr = NULL ; if ( isTwoAddr && NumOps >= <NUM_LIT> && OpNum < <NUM_LIT> ) { OpcodeTablePtr = & RegOp2MemOpTable2Addr ; } else if ( OpNum == <NUM_LIT> ) { switch ( Opc ) { case <STR_LIT> : case <STR_LIT> :


<s> TargetLowering :: ConstraintWeight <ISA_LIT>TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( CallOperandVal == NULL ) return CW_Default ; Type * type = CallOperandVal -> getType ( ) ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'y' : if ( type -> isIntegerTy ( ) ) weight = CW_Register ; break ; case 'f' : if ( type -> isFloatTy ( ) ) weight = CW_Register ; break ; } return weight ;


<s> unsigned NumElems = VT . getVectorNumElements ( ) ; EVT ScalarVT = VT . getVectorElementType ( ) ; if ( ! ( ( ScalarVT == <STR_LIT> || ScalarVT == <STR_LIT> ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ; EVT InScalarVT = InVT . getVectorElementType ( ) ; if ( InScalarVT . getSizeInBits ( ) <= ScalarVT . getSizeInBits ( ) ) return SDValue ( ) ; if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; if ( In . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto IsConstVectorInRange = [ ] ( SDValue V , unsigned Min , unsigned Max ) { return <STR_LIT> ( V , [ Min , Max ] ( ConstantSDNode * C ) { return ! ( C -> getAPIntValue ( ) . ult ( Min ) || C -> getAPIntValue ( ) . ugt ( Max ) ) ; } ) ; } ; auto LHS = In . getOperand ( <NUM_LIT> ) ; auto RHS = In . getOperand ( <NUM_LIT> ) ; if ( ! IsConstVectorInRange ( RHS , <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Operands [ <NUM_LIT> ] ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; auto AVGBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; auto AVGSplitter = [ & ] ( SDValue Op0 , SDValue Op1 ) { unsigned NumElemsPow2 = PowerOf2Ceil ( NumElems ) ; EVT Pow2VT = EVT :: getVectorVT ( * DAG . getContext ( ) , ScalarVT , NumElemsPow2 ) ; if ( NumElemsPow2 != NumElems ) { SmallVector < SDValue , <NUM_LIT> > Ops0 ( NumElemsPow2 , DAG . getUNDEF ( ScalarVT ) ) ; SmallVector < SDValue , <NUM_LIT> > Ops1 ( NumElemsPow2 , DAG . getUNDEF ( ScalarVT ) ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Idx = DAG . getIntPtrConstant ( i , DL ) ; Ops0 [ i ] = DAG . getNode ( <STR_LIT> , DL , ScalarVT , Op0 , Idx ) ; Ops1 [ i ] = DAG . getNode ( <STR_LIT> , DL , ScalarVT , Op1 , Idx ) ;


<s> const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ImmOp . isImm ( ) && <STR_LIT> ) ; const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ;

if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , false , IDLoc , Instructions ) ) return true ;


<s> int i ; if ( ! TARGET_ALTIVEC_ABI ) return LAST_ALTIVEC_REGNO + <NUM_LIT> ; if ( DEFAULT_ABI == ABI_DARWIN && crtl -> calls_eh_return && ! TARGET_ALTIVEC ) return FIRST_ALTIVEC_REGNO + <NUM_LIT> ;

for ( i = FIRST_ALTIVEC_REGNO + <NUM_LIT> ; i <= LAST_ALTIVEC_REGNO ; ++ i ) if ( save_reg_p ( i ) ) break ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> ~ <ISA_LIT>AsmBackend ( ) override {


<s> UserStack . push_back ( U ) ; while ( ! UserStack . empty ( ) ) { auto * UU = UserStack . pop_back_val ( ) ; if ( ! VisitedUsers . insert ( UU ) . second ) continue ; if ( isa < GlobalValue > ( UU ) ) continue ; if ( isa < Constant > ( UU ) ) { append_range ( UserStack , UU -> users ( ) ) ; continue ; } auto * I = cast < Instruction > ( UU ) ; Function * F = I -> getFunction ( ) ; if ( CollectKernelInsts ) { if ( ! llvm :: <STR_LIT> ( F ) ) { continue ; } } else { if ( llvm :: <STR_LIT> ( F ) ) { continue ; } }

FunctionToInsts . insert ( std :: make_pair ( F , SmallPtrSet < Instruction * , <NUM_LIT> > ( ) ) ) ;


<s> CPUser ( MachineInstr * mi , MachineInstr * cpemi , unsigned maxdisp , bool neg , bool soimm ) : MI ( mi ) , CPEMI ( cpemi ) , MaxDisp ( maxdisp ) , NegOk ( neg ) , IsSoImm ( soimm ) , KnownAlignment ( false ) { HighWaterMark = CPEMI -> getParent ( ) ;


<s> unsigned <ISA_LIT>AsmParser :: ParseRegList ( RegisterKind & RegKind , unsigned & RegNum , unsigned & RegWidth , SmallVectorImpl < AsmToken > & Tokens ) { unsigned Reg = <STR_LIT> ; auto ListLoc = getLoc ( ) ; if ( ! skipToken ( AsmToken :: LBrac , <STR_LIT> ) ) { return <STR_LIT> ; } auto Loc = getLoc ( ) ; if ( ! Parse<ISA_LIT>Register ( RegKind , Reg , RegNum , RegWidth ) ) return <STR_LIT> ; if ( RegWidth != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return <STR_LIT> ; } for ( ; trySkipToken ( AsmToken :: Comma ) ; ) { RegisterKind NextRegKind ; unsigned NextReg , NextRegNum , NextRegWidth ; Loc = getLoc ( ) ; if ( ! Parse<ISA_LIT>Register ( NextRegKind , NextReg , NextRegNum , NextRegWidth , Tokens ) ) { return <STR_LIT> ; } if ( NextRegWidth != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return <STR_LIT> ; } if ( NextRegKind != RegKind ) { Error ( Loc , <STR_LIT> ) ; return <STR_LIT> ; } if ( ! AddNextRegisterToList ( Reg , RegWidth , RegKind , NextReg , Loc ) ) return <STR_LIT> ;


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; unsigned Qn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Qn |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; unsigned Qm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Qm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;

Inst . addOperand ( MCOperand :: createImm ( Qd ) ) ;


<s> return ( __m128i ) __builtin_ia32_vpcomltq ( ( __v2di ) __A , ( __v2di ) __B ) ;


<s> MVT ExtVT = VT ; if ( ! VT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) ExtVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> / NumElts ) , NumElts ) ; SDValue V ; if ( Subtarget . hasDQI ( ) ) { V = getExtendInVec ( <STR_LIT> , dl , ExtVT , In , DAG ) ; assert ( ! VT . is512BitVector ( ) && <STR_LIT> ) ; } else { SDValue NegOne = getOnesVector ( ExtVT , DAG , dl ) ; SDValue Zero = getZeroVector ( ExtVT , Subtarget , DAG , dl ) ; V = DAG . getNode ( <STR_LIT> , dl , ExtVT , In , NegOne , Zero ) ; if ( ExtVT == VT ) return V ; }

return DAG . getNode ( <STR_LIT> , dl , VT , V ) ;


<s> std :: vector < CallInst * > PreserveArrayIndexCalls ; std :: vector < CallInst * > PreserveUnionIndexCalls ; std :: vector < CallInst * > PreserveStructIndexCalls ; bool Found = false ; for ( auto & BB : F ) for ( auto & I : BB ) { auto * Call = dyn_cast < CallInst > ( & I ) ; CallInfo CInfo ; if ( ! IsPreserveDIAccessIndexCall ( Call , CInfo ) ) continue ;


<s> DAG = static_cast < ScheduleDAGMI * > ( DAGInstrs ) ; const TargetSchedModel * TSchedModel = DAGInstrs -> getSchedModel ( ) ; if ( ! TSchedModel || DAG -> SUnits . empty ( ) ) return ; auto LastSALU = DAG -> SUnits . begin ( ) ; auto E = DAG -> SUnits . end ( ) ; SmallPtrSet < SUnit * , <NUM_LIT> > Visited ; for ( SUnit & SU : DAG -> SUnits ) { MachineInstr & MAI = * SU . getInstr ( ) ; if ( ! TII -> isMAI ( MAI ) || MAI . getOpcode ( ) == <STR_LIT> || MAI . getOpcode ( ) == <STR_LIT> ) continue ; unsigned Lat = TSchedModel -> computeInstrLatency ( & MAI ) - <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; DAG -> dumpNode ( SU ) ;

dbgs ( ) << <STR_LIT> << Lat << <STR_LIT> ) ;


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) const {

return <STR_LIT> ( funcInfo , libInfo ) ;


<s> const unsigned NumArgRegs = array_lengthof ( ArgRegs ) ; unsigned RegNum = State . getFirstUnallocated ( ArgRegs , NumArgRegs ) ; if ( RegNum != NumArgRegs && ArgRegs [ RegNum ] == <STR_LIT> ) { State . AllocateReg ( ArgRegs [ RegNum ] ) ;


<s> while ( InsertPos != MBB . end ( ) && InsertPos -> isEHLabel ( ) ) InsertPos ++ ; if ( InsertPos == MBB . end ( ) || ! <STR_LIT> ( InsertPos -> getOpcode ( ) ) ) { Changed = true ; BuildMI ( MBB , InsertPos , InsertPos -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; } } return Changed ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {

return getFrameLowering ( MF ) -> hasFP ( MF ) ? ( Is24Bit ? <STR_LIT> : <STR_LIT> ) : ( Is24Bit ? <STR_LIT> : <STR_LIT> ) ;


<s> return ( __m128d ) __builtin_ia32_cmpnltpd ( ( __v2df ) __A , ( __v2df ) __B ) ;


<s> break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2Base ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ;

MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ;


<s> return ( Imm & <NUM_LIT> ) != <NUM_LIT> ;


<s> if ( ElemVT == <STR_LIT> ) { SDValue SplatVal = Op . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SplatVal ) ; } return SDValue ( ) ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Unsigned = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( Opc ) return DAG . getNode ( Opc , dl , VT , Op0 , Op1 ) ; Opc = Unsigned ? <STR_LIT> : <STR_LIT> ;

return DAG . getNode ( Opc , dl , VT , Op0 , Op1 , DAG . getConstant ( SSECC , dl , <STR_LIT> ) ) ;


<s> SpilledReg ( Register R , int L ) : VGPR ( R ) , Lane ( L ) {


<s> virtual bool gate ( function * ) { return sparc_fix_at697f != <NUM_LIT> || sparc_fix_ut699 != <NUM_LIT> ;


<s> if ( ! GlobalBaseReg ) { getGlobalBaseReg ( ) ; initGlobalBaseReg ( ) ; } return GlobalBaseReg ;


<s> unsigned regCode = MRI . getEncodingValue ( MI . getOperand ( OpNo ) . getReg ( ) ) ; return ( regCode & <NUM_LIT> ) >> shift ;


<s> if ( V . getOpcode ( ) == <STR_LIT> ) if ( ConstantSDNode * MaskCst = dyn_cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { uint64_t Mask = MaskCst -> getZExtValue ( ) ; return ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ; } return false ; } ; if ( ! Op . hasOneUse ( ) ) return <NUM_LIT> ; if ( isSupportedExtend ( Op ) ) return <NUM_LIT> ; unsigned Opc = Op . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) if ( ConstantSDNode * ShiftCst = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { uint64_t Shift = ShiftCst -> getZExtValue ( ) ; if ( isSupportedExtend ( Op . getOperand ( <NUM_LIT> ) ) ) return ( Shift <= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;


<s> const TargetInstrDesc desc = MI -> getDesc ( ) ; std :: set < const TargetRegisterClass * > result ; for ( MachineInstr :: const_mop_iterator MOI = MI -> operands_begin ( ) , MOE = MI -> operands_end ( ) ; MOI != MOE ; ++ MOI ) { const MachineOperand & op = * MOI ; if ( op . isReg ( ) && op . isUse ( ) ) { unsigned reg = op . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( reg ) ) { const TargetRegisterClass * RC = MRI . getRegClass ( reg ) ; result . insert ( resolveSide ( RC ) ) ; } else { result . insert ( <STR_LIT> . contains ( reg ) ? BRegsRegisterClass :


<s> static nodes_iterator nodes_end ( const MCallSubGraph & G ) {


<s> if ( ( tmp & <NUM_LIT> ) == <NUM_LIT> ) { NSize = <NUM_LIT> ; RegDecoder = DecodeMSA128BRegisterClass ; } else if ( ( tmp & <NUM_LIT> ) == <NUM_LIT> ) { NSize = <NUM_LIT> ; RegDecoder = DecodeMSA128HRegisterClass ; } else if ( ( tmp & <NUM_LIT> ) == <NUM_LIT> ) { NSize = <NUM_LIT> ; RegDecoder = DecodeMSA128WRegisterClass ; } else if ( ( tmp & <NUM_LIT> ) == <NUM_LIT> ) { NSize = <NUM_LIT> ; RegDecoder = DecodeMSA128DRegisterClass ; } else llvm_unreachable ( <STR_LIT> ) ; assert ( NSize != <NUM_LIT> && RegDecoder != nullptr ) ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( RegDecoder ( MI , tmp , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( RegDecoder ( MI , tmp , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , NSize ) ; MI . addOperand ( MCOperand :: CreateImm ( tmp ) ) ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> } if ( crtl -> calls_eh_return ) { unsigned int i ; for ( i = <NUM_LIT> ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( INVALID_REGNUM == regno ) break ; current_frame_info . save_regs [ regno ] = <NUM_LIT> ; } } for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( current_frame_info . save_regs [ regno ] == <NUM_LIT> ) { current_frame_info . last_reg_to_save = regno ; if ( regno >= CR16_FIRST_DWORD_REGISTER ) current_frame_info . reg_size += CR16_UNITS_PER_DWORD ;


<s> for ( i = <NUM_LIT> ; i < ( TARGET_V9 ? <NUM_LIT> : <NUM_LIT> ) ; i += <NUM_LIT> ) if ( ( regs_ever_live [ i ] && ! call_used_regs [ i ] ) || ( regs_ever_live [ i + <NUM_LIT> ] && ! call_used_regs [ i + <NUM_LIT> ] ) ) n_regs += <NUM_LIT> ; num_gfregs = n_regs ; if ( leaf_function_p && n_regs == <NUM_LIT> && size == <NUM_LIT> && current_function_outgoing_args_size == <NUM_LIT> ) actual_fsize = apparent_fsize = <NUM_LIT> ; else { apparent_fsize = ( size - STARTING_FRAME_OFFSET + <NUM_LIT> ) & - <NUM_LIT> ; apparent_fsize += n_regs * <NUM_LIT> ; actual_fsize = apparent_fsize + ( ( outgoing_args_size + <NUM_LIT> ) & - <NUM_LIT> ) ; } if ( ! leaf_function_p || size > <NUM_LIT> ) actual_fsize += FIRST_PARM_OFFSET ( current_function_decl ) ; return SPARC_STACK_ALIGN ( actual_fsize ) ;


<s> vmlaq_f32 ( float32x4_t a , float32x4_t b , float32x4_t c ) { return a + b * c ;


<s> void mips_output_aligned_decl_common ( FILE * stream , tree decl , const char * name , unsigned HOST_WIDE_INT size , unsigned int align ) { if ( TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA && TREE_CODE ( decl ) == VAR_DECL && TREE_READONLY ( decl ) && ( DECL_INITIAL ( decl ) == <NUM_LIT> || DECL_INITIAL ( decl ) == error_mark_node ) ) { if ( TREE_PUBLIC ( decl ) && DECL_NAME ( decl ) ) targetm . asm_out . globalize_label ( stream , name ) ;


<s> bool <ISA_LIT>ConstantIslands :: runOnMachineFunction ( MachineFunction & F ) { return false ;


<s> EmitBundleLock ( false ) ; emitMask ( AddrReg , IndirectBranchMaskReg , STI ) ; MCELFStreamer :: EmitInstruction ( MI , STI ) ;


<s> bool <ISA_LIT>AsmPrinter :: isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const { if ( MBB -> isEHPad ( ) || MBB -> pred_empty ( ) || MBB -> hasAddressTaken ( ) ) return false ;

MachineBasicBlock :: const_pred_iterator PI = MBB -> pred_begin ( ) , PI2 = PI ;


<s> if ( TargetTriple . getArch ( ) == Triple :: nios2 ) { if ( CPU != <STR_LIT> ) { CPU = <STR_LIT> ; <ISA_LIT>ArchVersion = <ISA_LIT>r1 ; } else { <ISA_LIT>ArchVersion = <ISA_LIT>r2 ; } } else { errs ( ) << <STR_LIT> << TargetTriple . getArch ( ) << <STR_LIT> << CPU << <STR_LIT> ; exit ( <NUM_LIT> ) ; } ParseSubtargetFeatures ( CPU , FS ) ;


<s> unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>cc , DAG , dl ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>cc , CCR , Cmp ) ;

SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ;


return ( vec_sel ( __A , __c , __mask ) ) ;


<s> int64_t Tmp = - <NUM_LIT> ; if ( ! isToken ( AsmToken :: Integer ) && ! isToken ( AsmToken :: Identifier ) ) { return true ; } if ( getParser ( ) . parseAbsoluteExpression ( Tmp ) ) { return true ;


<s> if ( MI -> isCFIInstruction ( ) ) return false ; if ( MI -> isInlineAsm ( ) ) return false ; if ( MI -> isImplicitDef ( ) ) return false ; const MCInstrDesc & TID = MI -> getDesc ( ) ; auto * IS = ResourceTracker -> getInstrItins ( ) -> beginStage ( TID . getSchedClass ( ) ) ;

unsigned FuncUnits = IS -> getUnits ( ) ;


<s> SmallVector < int , <NUM_LIT> > MaskVals ( SVOp -> getMask ( ) . begin ( ) , SVOp -> getMask ( ) . end ( ) ) ; bool V2IsUndef = V2 . getOpcode ( ) == <STR_LIT> ; bool V1IsAllZero = <STR_LIT> ( V1 . getNode ( ) ) ; bool V2IsAllZero = <STR_LIT> ( V2 . getNode ( ) ) ; if ( VT != <STR_LIT> || ! Subtarget -> hasAVX2 ( ) || ( ! V2IsUndef && ! V2IsAllZero && ! V1IsAllZero ) ) return SDValue ( ) ; if ( V1IsAllZero && ! V2IsAllZero ) { CommuteVectorShuffleMask ( MaskVals , <NUM_LIT> ) ; V1 = V2 ; } SmallVector < SDValue , <NUM_LIT> > pshufbMask ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; i ++ ) { int EltIdx = MaskVals [ i ] ;

if ( EltIdx < <NUM_LIT> || EltIdx >= <NUM_LIT> ) EltIdx = <NUM_LIT> ;


<s> unsigned Idx = dyn_cast < ConstantSDNode > ( NewBldVec [ i ] . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( i == Idx ) isUnmovable [ Idx ] = true ; } } for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) {


<s> x = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; x = gen_frame_mem ( Pmode , x ) ; emit_move_insn ( x , gen_rtx_REG ( Pmode , regno ) ) ; } for ( regno = AC0_REGNUM ; regno <= AC3_REGNUM ; regno ++ ) if ( pdp11_saved_regno ( regno ) ) { x = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ; x = gen_frame_mem ( DFmode , x ) ; via_ac = gen_rtx_REG ( DFmode , regno ) ; emit_move_insn ( x , via_ac ) ; } for ( regno = AC4_REGNUM ; regno <= AC5_REGNUM ; regno ++ ) if ( pdp11_saved_regno ( regno ) ) { gcc_assert ( via_ac != NULL ) ; emit_move_insn ( via_ac , gen_rtx_REG ( DFmode , regno ) ) ; x = gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ;


<s> SMLoc StartLoc = getLoc ( ) ; unsigned RegNum ; OperandMatchResultTy Res = tryParseScalarRegister ( RegNum ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ! ParseShiftExtend || getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , StartLoc , getLoc ( ) , getContext ( ) ) ) ; return MatchOperand_Success ; } getParser ( ) . Lex ( ) ; SmallVector < std :: unique_ptr < MCParsedAsmOperand > , <NUM_LIT> > ExtOpnd ; Res = tryParseOptionalShiftExtend ( ExtOpnd ) ; if ( Res != MatchOperand_Success ) return Res ; auto Ext = static_cast < <ISA_LIT>Operand * > ( ExtOpnd . back ( ) . get ( ) ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , StartLoc , Ext -> getEndLoc ( ) , getContext ( ) , Ext -> getShiftExtendType ( ) , Ext -> getShiftExtendAmount ( ) , Ext -> hasShiftExtendAmount ( ) ) ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitInstrReg ( unsigned Opcode , unsigned Reg ) { MCInst I ; I . setOpcode ( Opcode ) ;

I . addOperand ( MCOperand :: CreateReg ( Reg ) ) ;


<s> explicit BlockInfo ( MachineBasicBlock * MBB ) : MBB ( MBB ) {


<s> EVT NewVT = getExtensionTo64Bits ( OrigTy ) ;

return DAG . getNode ( ExtOpcode , SDLoc ( N ) , NewVT , N ) ;


<s> if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( IMod != ~ <NUM_LIT> ) {


<s> IFMapType :: iterator F = IFMap . find ( VR ) ; assert ( F != IFMap . end ( ) ) ; IFListType & LL = F -> second ; auto IsCopy = [ ] ( const IFRecordWithRegSet & IR ) -> bool {

return IR . first . Wdh == <NUM_LIT> && ( IR . first . Off == <NUM_LIT> || IR . first . Off == <NUM_LIT> ) ;


<s> assert ( RestoreMI -> getOpcode ( ) == <STR_LIT> ) ; RestoreMI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( reg - <STR_LIT> + <STR_LIT> ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( imm ) ;


<s> unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes ) ) return false ; MachineInstrBuilder MIB ; unsigned CallOpc = <ISA_LIT>SelectCallOp ( NULL ) ; if ( isThumb2 ) MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; else MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ) ; for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RegArgs [ i ] ) ; MIB . addRegMask ( TRI . getCallPreservedMask ( CC ) ) ; SmallVector < unsigned , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes ) ) return false ; static_cast < MachineInstr * > ( MIB ) -> setPhysRegsDeadExcept ( UsedRegs , TRI ) ;


<s> void printlea64_32mem ( const MachineInstr * MI , unsigned OpNo ) {

printMemReference ( MI , OpNo , <STR_LIT> ) ;


<s> lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = <NUM_LIT> ; while ( ( lsb >>= <NUM_LIT> ) != <NUM_LIT> ) shift ++ ; m1 <<= <NUM_LIT> - shift ; m1 = ~ m1 ; m2 = ~ c ; } else { lsb = c & - c ; m2 = - lsb ; c = ~ c ; c &= - lsb ; lsb = c & - c ; c = ~ c ; c &= - lsb ; shift = <NUM_LIT> ; while ( ( lsb >>= <NUM_LIT> ) != <NUM_LIT> ) shift ++ ; m1 = ~ c ; m1 >>= shift ; m1 = ~ m1 ; } out [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - shift ) ; out [ <NUM_LIT> ] = GEN_INT ( m1 ) ; out [ <NUM_LIT> ] = GEN_INT ( shift ) ; out [ <NUM_LIT> ] = GEN_INT ( m2 ) ; ( void ) in ;


<s> machine_mode mode ; int unsigned_p ; mode = TYPE_MODE ( valtype ) ;

mode = promote_function_mode ( valtype , mode , & unsigned_p , func , <NUM_LIT> ) ;


<s> bool <ISA_LIT>LoopPreIncPrep :: runOnFunction ( Function & F ) { LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; bool MadeChange = false ; for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> dbgs ( ) << '{' ; for ( int x = Regs . find_first ( ) ; x >= <NUM_LIT> ; x = Regs . find_next ( x ) ) { unsigned R = x ;

dbgs
(
)
<<
' '
<<
printReg
(
R
,
&
TRI
)
;


<s> return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr , IsDarwin ) ;


<s> void encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const override { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; unsigned Size = Desc . getSize ( ) ; switch ( Size ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( IsLittleEndian ) { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } else { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } break ; case <NUM_LIT> : if ( IsLittleEndian ) { uint64_t Swapped = ( Bits << <NUM_LIT> ) | ( Bits >> <NUM_LIT> ) ; <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint64_t > ( Swapped ) ; } else { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint64_t > ( Bits ) ; } break ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> Wait . ExpCnt = std :: min ( Wait . ExpCnt , Count ) ; break ; case LGKM_CNT : Wait . LgkmCnt = std :: min ( Wait . LgkmCnt , Count ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> default_stack = <NUM_LIT> ; } save_all = NULL_RTX ; if ( TARGET_PROLOG_FUNCTION && num_save > <NUM_LIT> && actual_fsize >= default_stack ) { int alloc_stack = ( <NUM_LIT> * num_save ) + default_stack ; int unalloc_stack = actual_fsize - alloc_stack ; int save_func_len = <NUM_LIT> ; int save_normal_len ; if ( unalloc_stack ) save_func_len += CONST_OK_FOR_J ( unalloc_stack ) ? <NUM_LIT> : <NUM_LIT> ; if ( TARGET_EP && num_save > <NUM_LIT> && ( unsigned ) actual_fsize < <NUM_LIT> ) save_normal_len = ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * num_save ) ; else save_normal_len = <NUM_LIT> * num_save ; save_normal_len += CONST_OK_FOR_J ( actual_fsize ) ? <NUM_LIT> : <NUM_LIT> ; if ( save_func_len < save_normal_len ) { save_all = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_save + <NUM_LIT> + ( TARGET_V850 ? ( TARGET_LONG_CALLS ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ) ) ) ; XVECEXP ( save_all , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( stack_pointer_rtx , - alloc_stack ) ) ; offset = - default_stack ; for ( i = <NUM_LIT> ; i < num_save ; i ++ ) { XVECEXP ( save_all , <NUM_LIT> , i + <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( Pmode , plus_constant ( stack_pointer_rtx , offset ) ) , save_regs [ i ] ) ; offset -= <NUM_LIT> ; } if ( TARGET_V850 ) { XVECEXP ( save_all , <NUM_LIT> , num_save + <NUM_LIT> ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; if ( TARGET_LONG_CALLS ) XVECEXP ( save_all , <NUM_LIT> , num_save + <NUM_LIT> ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; } code = recog ( save_all , NULL_RTX , NULL ) ; if ( code >= <NUM_LIT> ) { rtx insn = emit_insn ( save_all ) ; INSN_CODE ( insn ) = code ; actual_fsize -= alloc_stack ; if ( TARGET_DEBUG ) fprintf ( stderr , <STR_LIT> , save_normal_len - save_func_len , save_normal_len , save_func_len , IDENTIFIER_POINTER ( DECL_NAME ( current_function_decl ) ) ) ; } else save_all = NULL_RTX ; } } if ( ! save_all ) { if ( interrupt_handler && ( ( <NUM_LIT> << LINK_POINTER_REGNUM ) & reg_saved ) != <NUM_LIT> ) { if ( TARGET_V850E && ! TARGET_DISABLE_CALLT ) emit_insn ( gen_callt_save_all_interrupt ( ) ) ; else emit_insn ( gen_save_all_interrupt ( ) ) ; } else { if ( actual_fsize && ! CONST_OK_FOR_K ( - actual_fsize ) ) init_stack_alloc = compute_register_save_size ( NULL ) ; else init_stack_alloc = actual_fsize ;


<s> void <ISA_LIT>16TargetLowering :: getOpndList ( SmallVectorImpl < SDValue > & Ops , std :: deque < std :: pair < unsigned , SDValue > > & RegsToPass , bool IsPICCall , bool GlobalOrExternal , bool InternalLinkage , bool IsCallReloc , CallLoweringInfo & CLI , SDValue Callee , SDValue Chain ) const { SelectionDAG & DAG = CLI . DAG ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const char * <ISA_LIT>16HelperFunction = nullptr ; bool Need<ISA_LIT>16Helper = false ; if ( Subtarget . in<ISA_LIT>16HardFloat ( ) ) { bool LookupHelper = true ; if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( CLI . Callee ) ) { <ISA_LIT>16Libcall Find = { RTLIB :: UNKNOWN_LIBCALL , S -> getSymbol ( ) } ; if ( std :: binary_search ( std :: begin ( HardFloatLibCalls ) , std :: end ( HardFloatLibCalls ) , Find ) ) LookupHelper = false ;


<s> MaxWorkGroupSizeRange = MDB . createRange ( APInt ( <NUM_LIT> , <NUM_LIT> ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; IsAMDGCN = TT . getArch ( ) == Triple :: amdgcn ;

IsAMDHSA = TT . getOS ( ) == Triple :: AMDHSA ;


<s> aarch64_ra_sign_scope = AARCH64_FUNCTION_NONE ; aarch64_enable_bti = <NUM_LIT> ; if ( rest ) { error ( <STR_LIT> , rest , str ) ; return AARCH64_PARSE_INVALID_FEATURE ;


<s> static bool isVRegCompatibleReg ( const <ISA_LIT>RegisterInfo & TRI , const MachineRegisterInfo & MRI , Register Reg ) {

unsigned Size = TRI . getRegSizeInBits ( Reg , MRI ) ;


<s> inline bool isPCREL ( unsigned Opcode ) {

return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool isMem = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; MachineOperand & StackAdjust = MBBI -> getOperand ( isMem ? <NUM_LIT> : <NUM_LIT> ) ; assert ( StackAdjust . isImm ( ) && <STR_LIT> ) ; int StackAdj = StackAdjust . getImm ( ) ; if ( StackAdj ) { StackAdj += <ISA_LIT>FL -> mergeSPUpdates ( MBB , MBBI , true ) ; <ISA_LIT>FL -> emitSPUpdate ( MBB , MBBI , StackAdj , true ) ; } bool IsWin64 = STI -> isTargetWin64 ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Op = ( Opcode == <STR_LIT> ) ? <STR_LIT> : ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( Op ) ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) MIB . addOperand ( MBBI -> getOperand ( i ) ) ; } else if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( IsWin64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ;


<s> if ( ! RS6000_WEAK || ! DECL_WEAK ( n -> decl ) ) { if ( dollar_inside ) { if ( data -> function_descriptor ) fprintf ( data -> file , <STR_LIT> , buffer , name ) ; fprintf ( data -> file , <STR_LIT> , buffer , name ) ; } if ( data -> function_descriptor ) { fputs ( <STR_LIT> , data -> file ) ; RS6000_OUTPUT_BASENAME ( data -> file , buffer ) ; putc ( '\n' , data -> file ) ; } fputs ( <STR_LIT> , data -> file ) ; RS6000_OUTPUT_BASENAME ( data -> file , buffer ) ; putc ( '\n' , data -> file ) ; } else if ( DECL_WEAK ( n -> decl ) && ! data -> function_descriptor ) ASM_WEAKEN_DECL ( data -> file , n -> decl , name , NULL ) ;


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const {

return resolveFrameIndexReference ( MF , FI , FrameReg , MF . getFunction ( ) . hasFnAttribute ( Attribute :: SanitizeHWAddress ) , false ) ;


<s> for ( auto DefMI : List ) { int64_t AddrDispShiftTemp = getAddrDispShift ( MI , MemOpNo , * DefMI , <NUM_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( AddrDispShiftTemp ) ) continue ; if ( TII -> getRegClass ( Desc , MemOpNo + <STR_LIT> , TRI , * MF ) != MRI -> getRegClass ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) continue ; int DistTemp = calcInstrDist ( * DefMI , MI ) ; assert ( DistTemp != <NUM_LIT> && <STR_LIT> ) ; if ( DistTemp > <NUM_LIT> || BestLEA == nullptr ) { if ( BestLEA != nullptr && ! isInt < <NUM_LIT> > ( AddrDispShiftTemp ) && isInt < <NUM_LIT> > ( AddrDispShift ) ) continue ; BestLEA = DefMI ; AddrDispShift = AddrDispShiftTemp ; Dist = DistTemp ; } if ( DistTemp < <NUM_LIT> ) break ; }


<s> return ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getSubtargetImpl ( ) -> useSmallSection ( ) && LocalSData && IsInSmallSection ( DL . getTypeAllocSize ( CN -> getType ( ) ) ) ) ;


<s> SMLoc <ISA_LIT>AsmParser :: getSMEMOffsetLoc ( const OperandVector & Operands ) const { for ( unsigned i = <NUM_LIT> , e = Operands . size ( ) ; i != e ; ++ i ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ i ] ) ; if ( Op . isSMEMOffset ( ) ) return Op . getStartLoc ( ) ; } return getLoc ( ) ;


<s> bool AMDGPUDAGToDAGISel :: isPrivateLoad ( const LoadSDNode * N ) const { if ( checkType ( N -> getSrcValue ( ) , <STR_LIT> ) ) { if ( isCPLoad ( N ) || isConstantLoad ( N , - <NUM_LIT> ) ) { return false ; } } if ( ! checkType ( N -> getSrcValue ( ) , <STR_LIT> ) && ! checkType ( N -> getSrcValue ( ) , <STR_LIT> ) && ! checkType ( N -> getSrcValue ( ) , <STR_LIT> ) && ! checkType ( N -> getSrcValue ( ) , <STR_LIT> ) && ! checkType ( N -> getSrcValue ( ) , <STR_LIT> ) && ! checkType ( N -> getSrcValue ( ) , <STR_LIT> ) ) {


<s> static bool isStartChunk ( uint64_t Chunk ) { if ( Chunk == <NUM_LIT> || Chunk == UINT64_MAX ) return false ;

return ( CountLeadingOnes_64 ( Chunk ) + countTrailingZeros ( Chunk ) ) == <NUM_LIT> ;


<s> assert ( MRI . getType ( Reg ) . getSizeInBits ( ) == NewTy . getSizeInBits ( ) ) ;


<s> return isMemDisp12 ( BDVMem , ADDR64Reg ) ;