<s> DEBUG ( dbgs ( ) << <STR_LIT> ; L -> dump ( ) ) ; DebugLoc DL ; if ( InsertPos != Preheader -> end ( ) ) DL = InsertPos -> getDebugLoc ( ) ; if ( TripCount -> isReg ( ) ) { unsigned CountReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * Preheader , InsertPos , DL , TII -> get ( TargetOpcode :: COPY ) , CountReg ) . addReg ( TripCount -> getReg ( ) , <NUM_LIT> , TripCount -> getSubReg ( ) ) ; BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_r ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ; } else { assert ( TripCount -> isImm ( ) && <STR_LIT> ) ; int64_t CountImm = TripCount -> getImm ( ) ; if ( ! TII -> isValidOffset ( LOOP_i , CountImm , TRI ) ) { unsigned CountReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * Preheader , InsertPos , DL , TII -> get ( <STR_LIT> ) , CountReg ) . addImm ( CountImm ) ; BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_r ) ) . addMBB ( LoopStart ) . addReg ( CountReg ) ; } else BuildMI ( * Preheader , InsertPos , DL , TII -> get ( LOOP_i ) ) . addMBB ( LoopStart ) . addImm ( CountImm ) ; } LoopStart -> setHasAddressTaken ( ) ; BlockAddress :: get ( const_cast < BasicBlock * > ( LoopStart -> getBasicBlock ( ) ) ) ; DebugLoc LastIDL = LastI -> getDebugLoc ( ) ; BuildMI ( * LastMBB , LastI , LastIDL , TII -> get ( ENDLOOP ) ) . addMBB ( LoopStart ) ; if ( LastI -> getOpcode ( ) == <STR_LIT> || LastI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * BranchTarget = LastI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; LastI = LastMBB -> erase ( LastI ) ; if ( ! L -> contains ( BranchTarget ) ) { if ( LastI != LastMBB -> end ( ) ) LastI = LastMBB -> erase ( LastI ) ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; TII -> insertBranch ( * LastMBB , BranchTarget , nullptr , Cond , LastIDL ) ; } } else { LastMBB -> erase ( LastI ) ; } delete TripCount ; for ( unsigned i = <NUM_LIT> ; i < OldInsts . size ( ) ; ++ i ) removeIfDead ( OldInsts [ i ] ) ; ++ NumHWLoops ; if ( L0Used ) RecL1used = true ; else RecL0used = true ; return true ;


<s> else if ( DEFAULT_ABI == ABI_DARWIN ) { const char * mcount_name = RS6000_MCOUNT ; int caller_addr_regno = LR_REGNO ; crtl -> uses_pic_offset_table = <NUM_LIT> ; if ( MACHOPIC_INDIRECT && crtl -> uses_pic_offset_table ) caller_addr_regno = <NUM_LIT> ;

emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , mcount_name ) , LCT_NORMAL , VOIDmode , <NUM_LIT> , gen_rtx_REG ( Pmode , caller_addr_regno ) , Pmode ) ;


<s> SmallString < <NUM_LIT> > Tmp ; raw_svector_ostream OS ( Tmp ) ; Inst . dump_pretty ( OS ) ; OS << <STR_LIT> ; report_fatal_error ( <STR_LIT> + OS . str ( ) ) ; }


<s> void <ISA_LIT>MCAsmStreamer :: EmitLocalCommonSymbol ( MCSymbol * Symbol , uint64_t Size , unsigned ByteAlignment ) {


<s> return Kind == MachineOperand :: MO_GlobalAddress ;


<s> case <STR_LIT> : return combineMaskedLoad ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineMaskedStore ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : return combineVZextMovl ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineVZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> Shift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { Shift , Const5 } ) ; PackedElt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { PackedElt , Shift } ) ; SDValue Mask = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; PackedElt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , { PackedElt , Mask } ) ; SDValue SubI32 = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; Result = SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , PackedElt , SubI32 ) , <NUM_LIT> ) ; if ( Op . getSimpleValueType ( ) == <STR_LIT> ) { Result = DAG . getBitcast ( <STR_LIT> , Result ) ; } else { assert ( Op . getSimpleValueType ( ) == <STR_LIT> ) ;


<s> return __builtin_mve_vcmulq_rot90v4sf ( __a , __b ) ;


<s> } else if ( ashiftrt_insns [ INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ] > <NUM_LIT> + SH_DYNAMIC_SHIFT_COST ) { rtx count = force_reg ( SImode , GEN_INT ( - ( INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) ) ) ; emit_insn ( gen_ashrsi3_d ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , count ) ) ; return <NUM_LIT> ; } } if ( GET_CODE ( operands [ <NUM_LIT> ] ) != CONST_INT ) return <NUM_LIT> ; value = INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ; if ( value == <NUM_LIT> ) { if ( currently_expanding_to_rtl ) { emit_insn ( gen_cmpgtsi_t ( force_reg ( SImode , CONST0_RTX ( SImode ) ) , operands [ <NUM_LIT> ] ) ) ; emit_insn ( gen_mov_neg_si_t ( operands [ <NUM_LIT> ] ) ) ; return <NUM_LIT> ; } emit_insn ( gen_ashrsi2_31 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; return <NUM_LIT> ; } else if ( value >= <NUM_LIT> && value <= <NUM_LIT> ) {


<s> if ( FrameObjects . empty ( ) ) { TopVectorFrame = getVectorDataSize ( ) ; TopScalarFrame = getScalarDataSize ( ) ; } FrameObject * Obj = nullptr ; if ( static_cast < unsigned > ( FrameIndex ) < FrameObjects . size ( ) ) { Obj = & FrameObjects [ FrameIndex ] ; if ( ! Obj -> isEmpty ( ) ) { assert ( Obj -> Size >= Sz ) ; return Obj -> Offset ; } } else { FrameObjects . resize ( FrameIndex + <NUM_LIT> ) ; Obj = & FrameObjects . back ( ) ; } unsigned & TopFrame = UsesVLM ? TopVectorFrame : TopScalarFrame ; unsigned MemLimit = UsesVLM ? MaxVectorMemory : MaxScalarMemory ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; Obj -> Size = MFI . getObjectSize ( FrameIndex ) ; Obj -> Offset = TopFrame ; TopFrame += Obj -> Size ; if ( UsesVLM ) { unsigned VectorSpillSize = TopFrame - getVectorDataSize ( ) ; if ( getSpillVectorDataSize ( ) < VectorSpillSize ) setSpillVectorDataSize ( VectorSpillSize ) ; } else { unsigned ScalarSpillSize = TopFrame - getScalarDataSize ( ) ; if ( getSpillScalarDataSize ( ) < ScalarSpillSize ) setSpillScalarDataSize ( ScalarSpillSize ) ; } if ( TopFrame > MemLimit ) { StringRef Msg = UsesVLM ? <STR_LIT> : <STR_LIT> ; if ( ! IgnoreMemOverflow ) { report_fatal_error ( Msg . str ( ) , false ) ; } else { errs ( ) << <STR_LIT> << Msg . str ( ) ; } }


<s> const <ISA_LIT>TargetLowering * llvm :: create<ISA_LIT>16TargetLowering ( <ISA_LIT>TargetMachine & TM ) {

return new <ISA_LIT>16TargetLowering ( TM ) ;


<s> if ( ! isUInt < <NUM_LIT> > ( Offset ) ) return false ; if ( STI . hasUsableDSOffset ( ) || STI . unsafeDSOffsetFoldingEnabled ( ) ) return true ;

return KnownBits -> signBitIsZero ( Base ) ;


<s> } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( VAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( SOffset ) MIB . addReg ( SOffset ) ; else MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( <STR_LIT> :: GLC ) ;


<s> if ( ( NewOp = tryAdvSIMDModImm64 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm321s ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm8 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImmFP ( <STR_LIT> , Op , DAG , DefBits ) ) ) return NewOp ; DefBits = ~ DefBits ; if ( ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm321s ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , Op , DAG , DefBits ) ) ) return NewOp ; DefBits = UndefBits ; if ( ( NewOp = tryAdvSIMDModImm64 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm321s ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm8 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImmFP ( <STR_LIT> , Op , DAG , DefBits ) ) ) return NewOp ; DefBits = ~ UndefBits ; if ( ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm321s ( <STR_LIT> , Op , DAG , DefBits ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , Op , DAG , DefBits ) ) ) return NewOp ; }


<s> poly_uint64 nelt = d -> perm . length ( ) ; rtx out , in0 , in1 , x ; machine_mode vmode = d -> vmode ; if ( GET_MODE_UNIT_SIZE ( vmode ) > <NUM_LIT> ) return false ; poly_uint64 first = d -> perm [ <NUM_LIT> ] ; if ( ( maybe_ne ( first , <NUM_LIT> ) && maybe_ne ( first * <NUM_LIT> , nelt ) ) || ! d -> perm . series_p ( <NUM_LIT> , <NUM_LIT> , first , <NUM_LIT> ) || ! d -> perm . series_p ( <NUM_LIT> , <NUM_LIT> , first + nelt , <NUM_LIT> ) ) return false ; high = maybe_ne ( first , <NUM_LIT> ) ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; in1 = d -> op1 ; if ( BYTES_BIG_ENDIAN && d -> vec_flags == VEC_ADVSIMD ) { x = in0 , in0 = in1 , in1 = x ;


<s> const GCNSubtarget & ST = TM . getSubtarget < GCNSubtarget > ( F ) ;


<s> static DecodeStatus DecodeBranchTarget26MM ( MCInst & Inst , unsigned Offset , uint64_t Address , const MCDisassembler * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset << <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler :: Success ;


<s> return MCDisassembler :: Fail ; } uint32_t insn32 = ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; MI . clear ( ) ; result = decodeInstruction ( DecoderTableThumb32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; bool InITBlock = ITBlock . instrInITBlock ( ) ; Check ( result , AddThumbPredicate ( MI ) ) ; AddThumb1SBit ( MI , InITBlock ) ; return result ; } MI . clear ( ) ; result = decodeInstruction ( DecoderTableThumb232 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; result = decodeInstruction ( DecoderTableVFP32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; UpdateThumbVFPPredicate ( MI ) ; return result ; } } MI . clear ( ) ; result = decodeInstruction ( DecoderTableVFPV832 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return result ; } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; result = decodeInstruction ( DecoderTableNEONDup32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; uint32_t NEONLdStInsn = insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address , this , STI ) ;


<s> unsigned NumSubRegs = std :: max ( ( int ) ( * I ) -> getSize ( ) / <NUM_LIT> , <NUM_LIT> ) ; unsigned Limit ; if ( isSGPRClass ( * I ) ) { Limit = SGPRLimit / NumSubRegs ; } else { Limit = VGPRLimit / NumSubRegs ; } const int * Sets = getRegClassPressureSets ( * I ) ; assert ( Sets ) ; for ( unsigned i = <NUM_LIT> ; Sets [ i ] != - <NUM_LIT> ; ++ i ) { if ( Sets [ i ] == ( int ) Idx ) return Limit ; } } return <NUM_LIT> ;


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MRI = & MF . getRegInfo ( ) ; MFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; return AsmPrinter :: runOnMachineFunction ( MF ) ;


<s> SuccSU -> setDepthToAtLeast ( SU -> getDepth ( ) + SuccEdge -> getLatency ( ) ) ;

if ( SuccSU -> NumPredsLeft == <NUM_LIT> && SuccSU != & ExitSU ) PendingQueue . push_back ( SuccSU ) ;


initialize<ISA_LIT>LowerAllocaPass ( PR ) ;


<s> switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI20 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO12 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI20 ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO12 ; break ;


<s> assert ( Op0 . isReg ( ) ) ; unsigned DestReg = Op0 . getReg ( ) ; if ( ! Op1 . isImm ( ) && Op1 . getTargetFlags ( ) != <STR_LIT> ) return false ; bool NotExt = Op1 . isImm ( ) && isInt < <NUM_LIT> > ( Op1 . getImm ( ) ) ; return <STR_LIT> . contains ( DestReg ) && ( ShouldCombineAggressively || NotExt ) ; } case <STR_LIT> : case <STR_LIT> : return true ; default :


<s> HST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = HST -> getInstrInfo ( ) ; const auto & HRI = * HST -> getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; Register AR = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getStackAlignBaseVReg ( ) ; std :: map < unsigned , SmallVector < MachineInstr * , <NUM_LIT> >> VExtractMap ; MaybeAlign MaxAlign ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { unsigned Opc = MI . getOpcode ( ) ; if ( Opc != <STR_LIT> ) continue ; Register VecR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; VExtractMap [ VecR ] . push_back ( & MI ) ; } } auto EmitAddr = [ & ] ( MachineBasicBlock & BB , MachineBasicBlock :: iterator At , DebugLoc dl , int FI , unsigned Offset ) { Register AddrR = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned FiOpc = AR != <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; auto MIB = BuildMI ( BB , At , dl , HII -> get ( FiOpc ) , AddrR ) ; if ( AR ) MIB . addReg ( AR ) ; MIB . addFrameIndex ( FI ) . addImm ( Offset ) ; return AddrR ; } ; for ( auto & P : VExtractMap ) { unsigned VecR = P . first ; if ( P . second . size ( ) <= VExtractThreshold ) continue ; const auto & VecRC = * MRI . getRegClass ( VecR ) ; Align Alignment = HRI . getSpillAlign ( VecRC ) ; MaxAlign = max ( MaxAlign , Alignment ) ; int FI = MFI . CreateStackObject ( HRI . getSpillSize ( VecRC ) , Alignment , false ) ; MachineInstr * DefI = MRI . getVRegDef ( VecR ) ; MachineBasicBlock :: iterator At = std :: next ( DefI -> getIterator ( ) ) ; MachineBasicBlock & DefB = * DefI -> getParent ( ) ; unsigned StoreOpc = VecRC . getID ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Register AddrR = EmitAddr ( DefB , At , DefI -> getDebugLoc ( ) , FI , <NUM_LIT> ) ; BuildMI ( DefB , At , DefI -> getDebugLoc ( ) , HII -> get ( StoreOpc ) ) . addReg ( AddrR ) . addImm ( <NUM_LIT> ) . addReg ( VecR ) ; unsigned VecSize = HRI . getRegSizeInBits ( VecRC ) / <NUM_LIT> ; for ( MachineInstr * ExtI : P . second ) { assert ( ExtI -> getOpcode ( ) == <STR_LIT> ) ; unsigned SR = ExtI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; assert ( ExtI -> getOperand ( <NUM_LIT> ) . getReg ( ) == VecR ) ;

MachineBasicBlock & ExtB = * ExtI -> getParent ( ) ;


<s> llvm :: Loop * L = LI -> getLoopFor ( BB ) ; if ( L && L -> getHeader ( ) == BB ) { SmallVector < BasicBlock * , <NUM_LIT> > Latches ; L -> getLoopLatches ( Latches ) ; std :: vector < BasicBlock * > Preds ; for ( pred_iterator PI = pred_begin ( BB ) , PE = pred_end ( BB ) ; PI != PE ; ++ PI ) { if ( std :: find ( Latches . begin ( ) , Latches . end ( ) , * PI ) == Latches . end ( ) ) Preds . push_back ( * PI ) ; } BB = llvm :: SplitBlockPredecessors ( BB , Preds , <STR_LIT> , this ) ; }

CallInst :: Create ( EndCf , popSaved ( ) , <STR_LIT> , BB -> getFirstInsertionPt ( ) ) ;


<s> rtx cfa_relative_addr = gen_rtx_PLUS ( Pmode , cfa , GEN_INT ( cfa_offset ) ) ; rtx cfa_relative_mem = gen_frame_mem ( DImode , cfa_relative_addr ) ; rtx real = gen_rtx_SET ( cfa_relative_mem , reg_note ) ; add_reg_note ( mov , REG_CFA_OFFSET , real ) ;


<s> unsigned Reg ; bool RV = <ISA_LIT>FastEmitLoad ( VT , SrcAM , nullptr , Reg ) ; RV &= <ISA_LIT>FastEmitStore ( VT , Reg , DestAM ) ; assert ( RV && <STR_LIT> ) ; unsigned Size = VT . getSizeInBits ( ) / <NUM_LIT> ; Len -= Size ;


<s> PrintIFR ( const IFRecord & R , const TargetRegisterInfo * RI ) : IFR ( R ) , TRI ( RI ) {


<s> createUnpackShuffleMask ( HalfVT , MaskHighTemp , false , false ) ; scaleShuffleMask ( <NUM_LIT> , MaskLowTemp , LowHighMask [ <NUM_LIT> ] ) ; scaleShuffleMask ( <NUM_LIT> , MaskHighTemp , LowHighMask [ <NUM_LIT> ] ) ; Value * IntrVec [ <NUM_LIT> ] ; IntrVec [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , MaskLow ) ; IntrVec [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , MaskHigh ) ; IntrVec [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , MaskLow ) ; IntrVec [ <NUM_LIT> ] = Builder . CreateShuffleVector ( Matrix [ <NUM_LIT> ] , Matrix [ <NUM_LIT> ] , MaskHigh ) ; Value * VecOut [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) VecOut [ i ] = Builder . CreateShuffleVector ( IntrVec [ i / <NUM_LIT> ] , IntrVec [ i / <NUM_LIT> + <NUM_LIT> ] , LowHighMask [ i % <NUM_LIT> ] ) ; if ( VT == <STR_LIT> ) { std :: copy ( VecOut , VecOut + <NUM_LIT> , TransposedMatrix . begin ( ) ) ; return ; } reorderSubVector ( VT , TransposedMatrix , VecOut , makeArrayRef ( Concat , <NUM_LIT> ) , NumOfElm , <NUM_LIT> , Builder ) ;


<s> int flags = opts -> x_target_flags ; const struct arm_fpu_desc * fpu_desc = & all_fpus [ opts -> x_arm_fpu_index ] ; if ( TARGET_IWMMXT && TARGET_VFP && ARM_FPU_FSET_HAS ( fpu_desc -> features , FPU_FL_NEON ) ) error ( <STR_LIT> ) ; if ( TARGET_ARM_P ( flags ) && ! ARM_FSET_HAS_CPU1 ( insn_flags , FL_NOTM ) ) error ( <STR_LIT> ) ; if ( ( TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME ) && TARGET_ARM_P ( flags ) ) warning ( <NUM_LIT> , <STR_LIT> ) ; if ( TARGET_ARM_P ( flags ) && TARGET_CALLEE_INTERWORKING ) warning ( <NUM_LIT> , <STR_LIT> ) ; if ( TARGET_ARM_P ( flags ) && write_symbols != NO_DEBUG && ! TARGET_APCS_FRAME && ( TARGET_DEFAULT & MASK_APCS_FRAME ) ) warning ( <NUM_LIT> , <STR_LIT> ) ;

if ( TARGET_THUMB_P ( flags ) && TARGET_IWMMXT ) error ( <STR_LIT> ) ;


<s> } SmallVector < int , <NUM_LIT> > ShuffV ( Mask . begin ( ) , Mask . end ( ) ) ; SDValue SToVLHS = isScalarToVec ( LHS ) ; SDValue SToVRHS = isScalarToVec ( RHS ) ; if ( SToVLHS || SToVRHS ) { int NumEltsIn = SToVLHS ? SToVLHS . getValueType ( ) . getVectorNumElements ( ) : SToVRHS . getValueType ( ) . getVectorNumElements ( ) ; int NumEltsOut = ShuffV . size ( ) ; int LHSMaxIdx = - <NUM_LIT> ; int RHSMinIdx = - <NUM_LIT> ; int RHSMaxIdx = - <NUM_LIT> ; int HalfVec = LHS . getValueType ( ) . getVectorNumElements ( ) / <NUM_LIT> ; if ( SToVLHS ) { LHSMaxIdx = NumEltsOut / NumEltsIn ; SToVLHS = getSToVPermuted ( SToVLHS , DAG ) ; if ( SToVLHS . getValueType ( ) != LHS . getValueType ( ) ) SToVLHS = DAG . getBitcast ( LHS . getValueType ( ) , SToVLHS ) ; LHS = SToVLHS ; } if ( SToVRHS ) { RHSMinIdx = NumEltsOut ; RHSMaxIdx = NumEltsOut / NumEltsIn + RHSMinIdx ; SToVRHS = getSToVPermuted ( SToVRHS , DAG ) ; if ( SToVRHS . getValueType ( ) != RHS . getValueType ( ) ) SToVRHS = DAG . getBitcast ( RHS . getValueType ( ) , SToVRHS ) ; RHS = SToVRHS ; }

fixupShuffleMaskForPermutedSToV ( ShuffV , LHSMaxIdx , RHSMinIdx , RHSMaxIdx , HalfVec ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> bool useEL3ForTP ( ) const { return UseEL3ForTP ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> const char * getPassName ( ) const override {


<s> Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else if ( isa < MCBinaryExpr > ( getImm ( ) ) ) { const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm ( ) ) ;

assert ( isa < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) && cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_HI ) ;


<s> return MatchOperand_ParseFail ; } getLexer ( ) . Lex ( ) ; if ( parseRegister ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } auto Rz = Operands . back ( ) -> getReg ( ) ;


<s> Type * I32Ty = getI32Ty ( Builder , I . getType ( ) ) ; Value * ExtOp0 = nullptr ; Value * ExtOp1 = nullptr ; Value * ExtRes = nullptr ; Value * TruncRes = nullptr ; if ( isSigned ( I ) ) { ExtOp0 = Builder . CreateSExt ( I . getOperand ( <NUM_LIT> ) , I32Ty ) ;

ExtOp1 = Builder . CreateSExt ( I . getOperand ( <NUM_LIT> ) , I32Ty ) ;


<s> if ( Extract ) { if ( ! Insert && Ty -> getScalarSizeInBits ( ) == <NUM_LIT> && ! ST -> hasAVX512 ( ) ) { unsigned NumElts = cast < FixedVectorType > ( Ty ) -> getNumElements ( ) ; unsigned MaxElts = ST -> hasAVX2 ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned MOVMSKCost = ( NumElts + MaxElts - <NUM_LIT> ) / MaxElts ; return MOVMSKCost ; } if ( LT . second . isVector ( ) ) { int CostValue = * LT . first . getValue ( ) ; assert ( CostValue >= <NUM_LIT> && <STR_LIT> ) ; unsigned NumElts = LT . second . getVectorNumElements ( ) * CostValue ; assert ( NumElts >= DemandedElts . getBitWidth ( ) && <STR_LIT> ) ; if ( SizeInBits > <NUM_LIT> ) { assert ( ( SizeInBits % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; unsigned NumLegal128Lanes = SizeInBits / <NUM_LIT> ; unsigned Num128Lanes = NumLegal128Lanes * CostValue ; APInt WidenedDemandedElts = DemandedElts . zext ( NumElts ) ; unsigned Scale = NumElts / Num128Lanes ; APInt DemandedUpper128Lanes = APIntOps :: ScaleBitMask ( WidenedDemandedElts , Num128Lanes ) ; auto * Ty128 = FixedVectorType :: get ( Ty -> getElementType ( ) , Scale ) ; for ( unsigned I = <NUM_LIT> ; I != Num128Lanes ; ++ I ) if ( DemandedUpper128Lanes [ I ] ) Cost += getShuffleCost ( TTI :: SK_ExtractSubvector , Ty , None , I * Scale , Ty128 ) ; for ( unsigned I = <NUM_LIT> ; I != NumElts ; ++ I ) if ( WidenedDemandedElts [ I ] ) { unsigned Idx = I % Scale ; Cost += getVectorInstrCost ( Instruction :: ExtractElement , Ty , Idx ) ; } return Cost ; }


<s> switch ( Op . getOpcode ( ) ) { default : return AMDGPUTargetLowering :: LowerOperation ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>GN_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( MFI , Op , DAG ) ; case <STR_LIT> : { unsigned IntrinsicID = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned NumUserSGPRs = <NUM_LIT> ; switch ( IntrinsicID ) { default : return AMDGPUTargetLowering :: LowerOperation ( Op , DAG ) ; case <STR_LIT> : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , <NUM_LIT> ) ; case <STR_LIT> : return LowerParameter ( DAG , VT , DL , DAG . getEntryNode ( ) , <NUM_LIT> ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: SReg_32RegClass , AMDGPU :: SReg_32RegClass . getRegister ( NumUserSGPRs + <NUM_LIT> ) , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: SReg_32RegClass , AMDGPU :: SReg_32RegClass . getRegister ( NumUserSGPRs + <NUM_LIT> ) , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: SReg_32RegClass , AMDGPU :: SReg_32RegClass . getRegister ( NumUserSGPRs + <NUM_LIT> ) , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR0 , VT ) ; case <STR_LIT> : return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR1 , VT ) ; case <STR_LIT> :

return CreateLiveInRegister ( DAG , & AMDGPU :: VReg_32RegClass , AMDGPU :: VGPR2 , VT ) ;


<s> return GISel -> getInstructionSelector ( ) ;


<s> static void EmitBICMask ( const MCSubtargetInfo & STI , MCStreamer & Out , unsigned Addr , int64_t Pred , unsigned Mask ) { MCInst BICInst ; const int32_t EncodedMask = <STR_LIT> ( Mask ) ; assert ( EncodedMask != - <NUM_LIT> ) ; BICInst . setOpcode ( <STR_LIT> ) ; BICInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; BICInst . addOperand ( MCOperand :: CreateReg ( Addr ) ) ; BICInst . addOperand ( MCOperand :: CreateImm ( EncodedMask ) ) ;

BICInst . addOperand ( MCOperand :: CreateImm ( Pred ) ) ;


<s> if ( cfun -> machine -> use_rts == <NUM_LIT> ) F ( emit_insn ( m32c_all_frame_related ( TARGET_A16 ? gen_prologue_enter_16 ( GEN_INT ( frame_size + <NUM_LIT> ) ) : gen_prologue_enter_24 ( GEN_INT ( frame_size + <NUM_LIT> ) ) ) ) ) ; if ( extra_frame_size ) { complex_prologue = <NUM_LIT> ; if ( TARGET_A16 ) F ( emit_insn ( gen_addhi3 ( gen_rtx_REG ( HImode , SP_REGNO ) , gen_rtx_REG ( HImode , SP_REGNO ) , GEN_INT ( - extra_frame_size ) ) ) ) ; else F ( emit_insn ( gen_addpsi3 ( gen_rtx_REG ( PSImode , SP_REGNO ) , gen_rtx_REG ( PSImode , SP_REGNO ) , GEN_INT ( - extra_frame_size ) ) ) ) ; }


<s> ByValArgs . push_back ( FIPtr ) ; } Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , dl , PtrVT , true ) , dl ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; SDValue StackPtr ; for ( unsigned i = <NUM_LIT> , j = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( Flags . isByVal ( ) ) Arg = ByValArgs [ j ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , PtrVT ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , dl ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MemOpChains ) ; SDValue InFlag ; if ( IsPIC ) { unsigned GPReg = <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , GPReg , getGlobalReg ( DAG , PtrVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } uint8_t OpFlag = IsPIC ? <STR_LIT> : <STR_LIT> ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ) ; } if ( DstVT == <STR_LIT> && TLI . isTypeLegal ( SrcVT ) ) { SDValue Cvt ; if ( DAG . getDataLayout ( ) . isBigEndian ( ) && SrcVT . isVector ( ) && SrcVT . getVectorNumElements ( ) > <NUM_LIT> ) Cvt = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Op ) ) ; else Cvt = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Op ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cvt , Cvt . getValue ( <NUM_LIT> ) ) ; } return SDValue ( ) ;


<s> virtual void EmitARM64WinCFISaveFPLR ( int Offset ) {


<s> bool iss7_0Ext ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true , true , true ) ;


<s> } if ( CONSTANT_P ( src ) && ! move_operand ( src , mode ) ) { loongarch_legitimize_const_move ( mode , dest , src ) ; set_unique_reg_note ( get_last_insn ( ) , REG_EQUAL , copy_rtx ( src ) ) ; return true ;


<s> for ( unsigned i = <NUM_LIT> ; i < PackCount ; i ++ ) { Value * Shift = ConstantInt :: get ( Ret -> getType ( ) , DL . getTypeSizeInBits ( Val -> getType ( ) ) * i ) ; Value * ShiftVal = IRB . CreateShl ( Ret , Shift ) ; Ret = IRB . CreateOr ( Ret , ShiftVal ) ;


<s> if ( ! LastFunctionLabel ) return ; auto TempSym = getContext ( ) . createLinkerPrivateTempSymbol ( ) ; getStreamer ( ) . EmitLabel ( TempSym ) ; auto Start = MCSymbolRefExpr :: create ( LastFunctionLabel , getContext ( ) ) ; auto End = MCSymbolRefExpr :: create ( TempSym , getContext ( ) ) ; auto Expr = MCBinaryExpr :: create ( MCBinaryExpr :: Sub , End , Start , getContext ( ) ) ; getStreamer ( ) . emitELFSize ( LastFunctionLabel , Expr ) ;


<s> SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ;


<s> inline static CondCode getInvertedCondCode ( CondCode Code ) { switch ( Code ) { default : llvm_unreachable ( <STR_LIT> ) ; case EQ : return NE ; case NE : return EQ ; case HS : return LO ; case LO : return HS ; case MI : return PL ; case PL : return MI ; case VS : return VC ; case VC : return VS ;


<s> case <STR_LIT> : case <STR_LIT> : { EVT VT = cast < MemIntrinsicSDNode > ( Op ) -> getMemoryVT ( ) ; unsigned MemBits = VT . getScalarSizeInBits ( ) ; Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - MemBits ) ; return ; } } } case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; ConstantSDNode * CI = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; const APInt & Mask = CI -> getAPIntValue ( ) ; Known . Zero &= Mask ; Known . One &= Mask ; return ; } case <STR_LIT> : case <STR_LIT> : { const SDValue & SrcSV = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = SrcSV . getValueType ( ) ; assert ( VecVT . isVector ( ) && <STR_LIT> ) ; const unsigned NumSrcElts = VecVT . getVectorNumElements ( ) ; ConstantSDNode * Pos = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; assert ( Pos -> getAPIntValue ( ) . ult ( NumSrcElts ) && <STR_LIT> ) ; unsigned Idx = Pos -> getZExtValue ( ) ; APInt DemandedElt = APInt :: getOneBitSet ( NumSrcElts , Idx ) ; Known = DAG . computeKnownBits ( SrcSV , DemandedElt , Depth + <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; const unsigned DstSz = VT . getScalarSizeInBits ( ) ; const unsigned SrcSz = VecVT . getVectorElementType ( ) . getSizeInBits ( ) ; ( void ) SrcSz ; assert ( SrcSz == Known . getBitWidth ( ) ) ; assert ( DstSz > SrcSz ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) Known = Known . sext ( DstSz ) ; else { Known = Known . zext ( DstSz , true ) ; }

assert ( DstSz == Known . getBitWidth ( ) ) ;


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ;

auto IsHazardFn = [ IsHazardDef , TRI , Reg ] ( const MachineInstr & MI ) {


<s> case <STR_LIT> : { const char * Prefix = <STR_LIT> ; Name . insert ( Name . begin ( ) , Prefix , Prefix + strlen ( Prefix ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MCSymbol * & StubSym = getMachOMMI ( ) . getGVStubEntry ( Sym ) ; if ( StubSym == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = AsmPrinter . GetGlobalValueSymbol ( MO . getGlobal ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MCSymbol * & StubSym = getMachOMMI ( ) . getHiddenGVStubEntry ( Sym ) ; if ( StubSym == <NUM_LIT> ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = AsmPrinter . GetGlobalValueSymbol ( MO . getGlobal ( ) ) ; } return Sym ; } case <STR_LIT> : { Name += <STR_LIT> ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name . str ( ) ) ; MCSymbol * & StubSym = getMachOMMI ( ) . getFnStubEntry ( Sym ) ; if ( StubSym ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = AsmPrinter . GetGlobalValueSymbol ( MO . getGlobal ( ) ) ; } else {

Name . erase ( Name . end ( ) - <NUM_LIT> , Name . end ( ) ) ;


<s> if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDX = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDY = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) WorkItemIDZ = true ; } const MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; bool MaySpill = ST . isVGPRSpillingEnabled ( F ) ; bool HasStackObjects = FrameInfo . hasStackObjects ( ) ; if ( isEntryFunction ( ) ) { if ( WorkItemIDZ ) WorkItemIDY = true ; if ( HasStackObjects || MaySpill ) { PrivateSegmentWaveByteOffset = true ; if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX9 && ( CC == CallingConv :: <ISA_LIT>_HS || CC == CallingConv :: <ISA_LIT>_GS ) ) ArgInfo . PrivateSegmentWaveByteOffset = ArgDescriptor :: createRegister ( <STR_LIT> ) ; } } bool isAmdHsaOrMesa = ST . isAmdHsaOrMesa ( F ) ; if ( isAmdHsaOrMesa ) { if ( HasStackObjects || MaySpill ) PrivateSegmentBuffer = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) DispatchPtr = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) QueuePtr = true ; if ( F . hasFnAttribute ( <STR_LIT> ) ) DispatchID = true ; } else if ( ST . isMesaGfxShader ( F ) ) { if ( HasStackObjects || MaySpill ) ImplicitBufferPtr = true ; } if ( F . hasFnAttribute ( <STR_LIT> ) ) KernargSegmentPtr = true ; if ( ST . hasFlatAddressSpace ( ) && isEntryFunction ( ) && isAmdHsaOrMesa ) { if ( HasStackObjects || F . hasFnAttribute ( <STR_LIT> ) ) FlatScratchInit = true ;


<s> <ISA_LIT>CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCAssignFn * RetCC = RetCC_<ISA_LIT> ; CCInfo . AnalyzeReturn ( Outs , RetCC ) ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; if ( ( VA . getLocInfo ( ) != CCValAssign :: Full ) && ( VA . getLocInfo ( ) != CCValAssign :: BCvt ) ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; unsigned DestReg = VA . getLocReg ( ) ; if ( ! MRI . getRegClass ( SrcReg ) -> contains ( DestReg ) ) return false ; EVT RVEVT = TLI . getValueType ( DL , RV -> getType ( ) ) ; if ( ! RVEVT . isSimple ( ) ) return false ;

if ( RVEVT . isVector ( ) ) return false ;


<s> if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( V2 . isUndef ( ) ) { if ( SDValue Rotate = lowerShuffleAsBitRotate ( DL , <STR_LIT> , V1 , Mask , Subtarget , DAG ) ) return Rotate ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { return lowerV8I16GeneralSingleInputShuffle ( DL , <STR_LIT> , V1 , RepeatedMask , Subtarget , DAG ) ; } } if ( SDValue Blend = lowerShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue PSHUFB = lowerShuffleWithPSHUFB ( DL , <STR_LIT> , Mask , V1 , V2 , Zeroable , Subtarget , DAG ) ) return PSHUFB ;

return lowerShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


EndLoc = Parser . getTok ( ) . getLoc ( ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCallerSavedRegs ( const MachineFunction * MF ) const { static const MCPhysReg CallerSavedRegsV4 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; switch ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . get<ISA_LIT>ArchVersion ( ) ) { case <ISA_LIT>Subtarget :: V4 : case <ISA_LIT>Subtarget :: V5 : case <ISA_LIT>Subtarget :: V55 :


<s> if ( ! matchVectorAddressRecursively ( N . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && ! matchVectorAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) return false ; AM = Backup ; if ( ! matchVectorAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && ! matchVectorAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) return false ; AM = Backup ;


<s> if ( IID == <STR_LIT> ) { HaveCall = true ; copyFeaturesToFunction ( F , * Callee , NeedQueuePtr ) ; Changed = true ; } else { bool NonKernelOnly = false ; if ( ! IsFunc && IID == <STR_LIT> ) { F . addFnAttr ( <STR_LIT> ) ; } else { StringRef AttrName = intrinsicToAttrName ( IID , NonKernelOnly , NeedQueuePtr ) ; if ( ! AttrName . empty ( ) && ( IsFunc || ! NonKernelOnly ) ) { F . addFnAttr ( AttrName ) ; Changed = true ; } } } } if ( NeedQueuePtr || ( ! IsFunc && HasApertureRegs ) ) continue ; if ( const AddrSpaceCastInst * ASC = dyn_cast < AddrSpaceCastInst > ( & I ) ) { if ( ! HasApertureRegs && castRequiresQueuePtr ( ASC ) ) { NeedQueuePtr = true ; continue ; } } for ( const Use & U : I . operands ( ) ) { const auto * OpC = dyn_cast < Constant > ( U ) ; if ( ! OpC ) continue ; if ( visitConstantExprsRecursively ( OpC , ConstantExprVisited , IsFunc , HasApertureRegs ) ) { NeedQueuePtr = true ; break ;


<s> tree decl = build_decl ( input_location , TYPE_DECL , id , vectype ) ; decl = lang_hooks . decls . pushdecl ( decl ) ;

if ( decl && TREE_CODE ( decl ) == TYPE_DECL && TYPE_MAIN_VARIANT ( TREE_TYPE ( decl ) ) == vectype ) vectype = TREE_TYPE ( decl ) ;


<s> if ( ! detectLuiAddiGlobal ( HiLUI , LoADDI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * LoADDI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) << <STR_LIT> ) ; detectAndFoldOffset ( HiLUI , * LoADDI ) ; } }

for ( auto * MI : DeadInstrs ) MI -> eraseFromParent ( ) ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; AFI -> setStackSizeSVE ( alignTo ( SVEStackSize , <NUM_LIT> ) ) ; AFI -> setMinMaxSVECSFrameIndex ( MinCSFrameIndex , MaxCSFrameIndex ) ; if ( ! MF . hasEHFunclets ( ) ) return ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ; while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ; int64_t FixedObject = getFixedObjectSize ( MF , AFI , true , false ) ; int UnwindHelpFI = MFI . CreateFixedObject ( <NUM_LIT> , - FixedObject , false ) ; EHInfo . UnwindHelpFrameIdx = UnwindHelpFI ; DebugLoc DL ; RS -> enterBasicBlockEnd ( MBB ) ; RS -> backward ( std :: prev ( MBBI ) ) ; unsigned DstReg = RS -> FindUnusedReg ( & <STR_LIT> ) ; assert ( DstReg && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( - <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( DstReg , getKillRegState ( true ) ) . addFrameIndex ( UnwindHelpFI ) . addImm ( <NUM_LIT> ) ;


<s> static DecodeStatus DecodeI64RegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = IntRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm << <NUM_LIT> ) ) ) ; return MCDisassembler :: Success ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitCCBottomFunction ( StringRef Name ) { OS << <STR_LIT> ;


<s> } else if ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> ) { i0 = CONST_DOUBLE_LOW ( x ) ; i1 = - ( i0 < <NUM_LIT> ) ; } else { i0 = CONST_DOUBLE_LOW ( x ) ; i1 = CONST_DOUBLE_HIGH ( x ) ; }


<s> uint64_t flags ( ) const { return <NUM_LIT> ;


<s> void FPS :: handleCall ( MachineBasicBlock :: iterator & I ) { MachineInstr & MI = * I ; unsigned STReturns = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isImplicit ( ) && <STR_LIT> ) ; if ( Op . isDef ( ) ) STReturns |= <NUM_LIT> << getFPReg ( Op ) ; MI . RemoveOperand ( i ) ; -- i ; -- e ; } unsigned N = countTrailingOnes ( STReturns ) ;

assert ( STReturns == <NUM_LIT> || ( isMask_32 ( STReturns ) && N <= <NUM_LIT> ) ) ;


<s> else if ( COP0RegClass -> contains ( SubReg ) ) ri_cprmask [ <NUM_LIT> ] |= Value ; else if ( FGR32RegClass -> contains ( SubReg ) || FGR64RegClass -> contains ( SubReg ) || AFGR64RegClass -> contains ( SubReg ) || MSA128BRegClass -> contains ( SubReg ) ) ri_cprmask [ <NUM_LIT> ] |= Value ; else if ( COP2RegClass -> contains ( SubReg ) ) ri_cprmask [ <NUM_LIT> ] |= Value ;

else if ( COP3RegClass -> contains ( SubReg ) ) ri_cprmask [ <NUM_LIT> ] |= Value ;


<s> static bool compareMbbNumbers ( const MachineBasicBlock * LHS , const MachineBasicBlock * RHS ) {

return LHS -> getNumber ( ) < RHS -> getNumber ( ) ;


<s> void <ISA_LIT>RegisterInfo :: lowerCRSpilling ( MachineBasicBlock :: iterator II , unsigned FrameIndex ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; bool LP64 = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ;

unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ;


<s> Value * Cond = Term -> getCondition ( ) ; IRBuilder < > Builder ( Term ) ; Cond = Builder . CreateNot ( Cond ) ;


<s> continue ; } if ( Op1 . isReg ( ) && Op2 . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( Op1 . getReg ( ) ) && TargetRegisterInfo :: isVirtualRegister ( Op2 . getReg ( ) ) ) { MachineInstr * Op1Def = MRI -> getVRegDef ( Op1 . getReg ( ) ) ; MachineInstr * Op2Def = MRI -> getVRegDef ( Op2 . getReg ( ) ) ; if ( TII -> produceSameValue ( * Op1Def , * Op2Def , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Op1Def << <STR_LIT> << * Op2Def << <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } return true ;


<s> assert ( Ty -> isIntegerTy ( ) ) ; unsigned Bits = Ty -> getPrimitiveSizeInBits ( ) ; if ( Bits == <NUM_LIT> || Bits > <NUM_LIT> ) return <NUM_LIT> ; int64_t SImmVal = Imm . getSExtValue ( ) ; uint64_t ZImmVal = Imm . getZExtValue ( ) ; if ( ! ST -> isThumb ( ) ) { if ( ( SImmVal >= <NUM_LIT> && SImmVal < <NUM_LIT> ) || ( <STR_LIT> ( ZImmVal ) != - <NUM_LIT> ) || ( <STR_LIT> ( ~ ZImmVal ) != - <NUM_LIT> ) ) return <NUM_LIT> ;

return ST -> hasV6T2Ops ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> APInt Op1Zero , Op1One ; DAG . ComputeMaskedBits ( Op0 , Op0Zero , Op0One , Depth ) ; DAG . ComputeMaskedBits ( Op1 , Op1Zero , Op1One , Depth ) ; KnownZero = Op0Zero & Op1Zero ; KnownOne = Op0One & Op1One ;


<s> } NewMBB = llvm :: next ( MachineFunction :: iterator ( WaterBB ) ) ; } else { DEBUG ( errs ( ) << <STR_LIT> ) ; CreateNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = prior ( MachineFunction :: iterator ( NewMBB ) ) ; IP = std :: find ( WaterList . begin ( ) , WaterList . end ( ) , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF . insert ( NewMBB , NewIsland ) ; UpdateForInsertedWaterBlock ( NewIsland ) ; DecrementOldEntry ( CPI , CPEMI ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ;

CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ;


<s> MachineBasicBlock * MBB = * WL . begin ( ) ; WL . erase ( WL . begin ( ) ) ; propagateDeadArea ( WL , INs , * i , MBB ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF -> getFunction ( ) -> getName ( ) << <STR_LIT> ; ) ; for ( MBBUInt :: const_iterator j ( INs . begin ( ) ) , je ( INs . end ( ) ) ; j != je ; j ++ ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << j -> first -> getName ( ) << <STR_LIT> << j -> first -> getNumber ( ) << <STR_LIT> << <STR_LIT> << j -> second << <STR_LIT> ; ) ; TotalBlocks ++ ; if ( j -> second == getBytesReserved ( * i ) ) TotallyDeadBlocks ++ ; else if ( ( j -> second != <NUM_LIT> ) && ( j -> second != std :: numeric_limits < unsigned int > :: max ( ) ) ) { PartiallyDeadBlocks ++ ; } } } }


<s> return createELFObjectWriter ( MOTW , OS , false ) ;


<s> XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned CountReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget -> isTargetWin64 ( ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) ; MBB -> addSuccessor ( EndMBB ) ;


<s> int InstrOffs = MI . getOperand ( ImmIdx ) . getImm ( ) ; unsigned NumBits = ( FrameReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; Offset += InstrOffs * Scale ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; MachineOperand & ImmOp = MI . getOperand ( ImmIdx ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; unsigned NewOpc = convertToNonSPOpcode ( Opcode ) ; if ( NewOpc != Opcode && FrameReg != <STR_LIT> ) MI . setDesc ( TII . get ( NewOpc ) ) ; return true ; } NumBits = <NUM_LIT> ; Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { ImmOp . ChangeToImmediate ( <NUM_LIT> ) ; } else { ImmedOffset = ImmedOffset & Mask ; ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset &= ~ ( Mask * Scale ) ;


<s> bool isImm1_8 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> LLVMContext & C = LongjmpF -> getParent ( ) -> getContext ( ) ; IRBuilder < > IRB ( C ) ; for ( User * U : LongjmpF -> users ( ) ) { auto * CI = dyn_cast < CallInst > ( U ) ; if ( CI && CI -> getCalledFunction ( ) == LongjmpF ) { IRB . SetInsertPoint ( CI ) ; Value * Jmpbuf = IRB . CreatePtrToInt ( CI -> getArgOperand ( <NUM_LIT> ) , IRB . getInt32Ty ( ) , <STR_LIT> ) ; IRB . CreateCall ( EmLongjmpF , { Jmpbuf , CI -> getArgOperand ( <NUM_LIT> ) } ) ; ToErase . push_back ( CI ) ;


<s> Type * VecWidth = VecInst -> getType ( ) ; ( void ) VecWidth ; assert ( VecWidth -> isVectorTy ( ) && DL . getTypeSizeInBits ( VecWidth ) >= DL . getTypeSizeInBits ( SubVecTy ) * NumSubVectors && <STR_LIT> ) ; if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( VecInst ) ) { Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Indices [ i ] , SubVecTy -> getNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ;

unsigned VecLength = DL . getTypeSizeInBits ( VecWidth ) ;


<s> case FLAGS_VALID_YES : case FLAGS_VALID_NOOV : flags_operand1 = dest ; flags_operand2 = NULL_RTX ; break ; case FLAGS_VALID_MOVE : if ( dest != NULL_RTX && ! FP_REG_P ( dest ) && ( FP_REG_P ( src ) || GET_CODE ( src ) == FIX || FLOAT_MODE_P ( GET_MODE ( dest ) ) ) ) flags_operand1 = flags_operand2 = NULL_RTX ; else { flags_operand1 = dest ; if ( GET_MODE ( src ) != VOIDmode && ! side_effects_p ( src ) && ! modified_in_p ( src , insn ) ) flags_operand2 = src ; else flags_operand2 = NULL_RTX ; } break ; default : gcc_unreachable ( ) ;


<s> static bool ia64_vectorize_vec_perm_const ( machine_mode vmode , rtx target , rtx op0 , rtx op1 , const vec_perm_indices & sel ) { struct expand_vec_perm_d d ; unsigned char perm [ MAX_VECT_LEN ] ; unsigned int i , nelt , which ; d . target = target ; if ( op0 ) { rtx nop0 = force_reg ( vmode , op0 ) ; if ( op0 == op1 ) op1 = nop0 ; op0 = nop0 ; } if ( op1 ) op1 = force_reg ( vmode , op1 ) ; d . op0 = op0 ; d . op1 = op1 ; d . vmode = vmode ; gcc_assert ( VECTOR_MODE_P ( d . vmode ) ) ; d . nelt = nelt = GET_MODE_NUNITS ( d . vmode ) ; d . testing_p = ! target ; gcc_assert ( sel . length ( ) == nelt ) ; gcc_checking_assert ( sizeof ( d . perm ) == sizeof ( perm ) ) ; for ( i = which = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned int ei = sel [ i ] & ( <NUM_LIT> * nelt - <NUM_LIT> ) ; which |= ( ei < nelt ? <NUM_LIT> : <NUM_LIT> ) ; d . perm [ i ] = ei ; perm [ i ] = ei ; } switch ( which ) { default : gcc_unreachable ( ) ; case <NUM_LIT> : if ( d . testing_p || ! rtx_equal_p ( d . op0 , d . op1 ) ) { d . one_operand_p = false ; break ; } for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d . perm [ i ] >= nelt ) d . perm [ i ] -= nelt ;


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; auto Flags = MachineMemOperand :: MONone ; if ( MCID . mayLoad ( ) ) Flags |= MachineMemOperand :: MOLoad ; if ( MCID . mayStore ( ) ) Flags |= MachineMemOperand :: MOStore ; int64_t Offset = <NUM_LIT> ;

MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , Flags , MFFrame . getObjectSize ( FI ) , MFFrame . getObjectAlign ( FI ) ) ;


<s> const MCInstrDesc & MCID = MII . get ( Opc ) ; if ( ForcedVEXEncoding == VEXEncoding_EVEX && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) return Match_Unsupported ; if ( ( ForcedVEXEncoding == VEXEncoding_VEX || ForcedVEXEncoding == VEXEncoding_VEX2 || ForcedVEXEncoding == VEXEncoding_VEX3 ) && ( MCID . TSFlags & <STR_LIT> ) != <STR_LIT> ) return Match_Unsupported ; if ( MCID . TSFlags & <STR_LIT> && ( ForcedVEXEncoding != VEXEncoding_VEX && ForcedVEXEncoding != VEXEncoding_VEX2 && ForcedVEXEncoding != VEXEncoding_VEX3 ) ) return Match_Unsupported ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ForcedVEXEncoding != VEXEncoding_EVEX ) return Match_Unsupported ; break ;


<s> Register LHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = AddrDef -> MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto LHSDef = getDefSrcRegIgnoringCopies ( LHS , * MRI ) ; auto RHSDef = getDefSrcRegIgnoringCopies ( RHS , * MRI ) ; if ( LHSDef && RHSDef && LHSDef -> MI -> getOpcode ( ) == <STR_LIT> && isSGPR ( RHSDef -> Reg ) ) { int FI = LHSDef -> MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; MachineInstr & I = * Root . getParent ( ) ; MachineBasicBlock * BB = I . getParent ( ) ; const DebugLoc & DL = I . getDebugLoc ( ) ; SAddr = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , SAddr ) . addFrameIndex ( FI ) . addReg ( RHSDef -> Reg ) ; } } if ( ! isSGPR ( SAddr ) ) return None ;


<s> unsigned DestSub0 = MRI . createVirtualRegister ( DestRC ) ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub0 ) . addOperand ( SrcReg0Sub0 ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , AMDGPU :: sub1 , Src0SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( DestSubRC ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( DestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( AMDGPU :: sub0 ) . addReg ( DestSub1 ) . addImm ( AMDGPU :: sub1 ) ;

MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ;


<s> typedef std :: vector < unsigned > SortableVectorType ; SortableVectorType VRs ; for ( RegisterOrdering :: iterator I = RB . begin ( ) , E = RB . end ( ) ; I != E ; ++ I ) VRs . push_back ( I -> first ) ;

std :: sort ( VRs . begin ( ) , VRs . end ( ) , LexCmp ) ;


<s> const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . getGeneration ( ) <= AMDGPUSubtarget :: NORTHERN_ISLANDS ) { addPass ( createAMDGPUCFGStructurizerPass ( ) , false ) ; addPass ( createR600ExpandSpecialInstrsPass ( * TM ) , false ) ; addPass ( & FinalizeMachineBundlesID , false ) ;

addPass ( createR600Packetizer ( * TM ) , false ) ;


<s> virtual bool isProfitableToDupForIfCvt ( MachineBasicBlock & MBB , unsigned NumInstrs ) const { return NumInstrs && NumInstrs == <NUM_LIT> ;


<s> return ggc_alloc_cleared ( sizeof ( struct machine_function ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOLoad ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ;

BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ;


<s> auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg && TheReg -> isInRequiredFeatures ( { <STR_LIT> } ) ) { O << TheReg -> Name ; return ; } } SYSm &= <NUM_LIT> ; if ( Opcode == <STR_LIT> && FeatureBits [ <STR_LIT> ] ) { auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg ) { O << TheReg -> Name ; return ; } } auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg ) { O << TheReg -> Name ; return ; } O << SYSm ; return ; } unsigned SpecRegRBit = Op . getImm ( ) >> <NUM_LIT> ; unsigned Mask = Op . getImm ( ) & <NUM_LIT> ; if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default :


<s> break ; case MachineOperand :: MO_Register : if ( Subtarget -> useIndirectThunkCalls ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; CallTargetMCOp = MCOperand :: createReg ( CallTarget . getReg ( ) ) ; CallOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } MCInst CallInst ; CallInst . setOpcode ( CallOpcode ) ; CallInst . addOperand ( CallTargetMCOp ) ; OutStreamer -> emitInstruction ( CallInst , getSubtargetInfo ( ) ) ; }

auto & Ctx = OutStreamer -> getContext ( ) ;


<s> int LoSrc , HiSrc ; return ( isElementRotate ( LoSrc , HiSrc , M ) > <NUM_LIT> ) || isInterleaveShuffle ( M , SVT , SwapSources , Subtarget ) ;


<s> case 'M' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( C -> getZExtValue ( ) <= <NUM_LIT> ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; case 'e' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getSExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getSExtValue ( ) , SDLoc ( Op ) , <STR_LIT> ) ; break ; } } return ; } case 'Z' : { if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { if ( ConstantInt :: isValueValidForType ( Type :: getInt32Ty ( * DAG . getContext ( ) ) , C -> getZExtValue ( ) ) ) { Result = DAG . getTargetConstant ( C -> getZExtValue ( ) , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } } return ; } case 'i' : { if ( ConstantSDNode * CST = dyn_cast < ConstantSDNode > ( Op ) ) { Result = DAG . getTargetConstant ( CST -> getSExtValue ( ) , SDLoc ( Op ) , <STR_LIT> ) ; break ; } if ( Subtarget . isPICStyleGOT ( ) || Subtarget . isPICStyleStubPIC ( ) ) return ;


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> if ( Op -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) ) return false ; Base = Op -> getOperand ( <NUM_LIT> ) ; Offset = DAG . getConstant ( RHSC , VT ) ; AM = <STR_LIT> ; return true ; }


<s> if ( TII -> isVector ( * MI ) ) return true ;

if ( ! TII -> isALUInstr ( MI -> getOpcode ( ) ) ) return true ;


<s> for ( unsigned BTI = <NUM_LIT> , BTE = BI -> NumTerminators ; BTI != BTE ; ++ BTI ) { assert ( Position . Address <= TI -> Address && <STR_LIT> ) ; if ( mustRelaxBranch ( * TI , Position . Address ) ) relaxBranch ( * TI ) ; skipTerminator ( Position , * TI , false ) ; ++ TI ; } }


<s> } ) ; } ; auto CanBeUsedForAllClasses = [ & RequiredClasses , TRI ] ( MCPhysReg PR ) { return all_of ( RequiredClasses , [ PR , TRI ] ( const TargetRegisterClass * C ) { return any_of ( TRI -> sub_and_superregs_inclusive ( PR ) , [ C , TRI ] ( MCPhysReg SubOrSuper ) { return C == TRI -> getMinimalPhysRegClass ( SubOrSuper ) ; } ) ; } ) ; } ; auto * RegClass = TRI -> getMinimalPhysRegClass ( Reg ) ; for ( const MCPhysReg & PR : * RegClass ) { if ( DefinedInBB . available ( PR ) && UsedInBetween . available ( PR ) && ! RegInfo . isReserved ( PR ) && ! AnySubOrSuperRegCalleePreserved ( PR ) && CanBeUsedForAllClasses ( PR ) ) { DefinedInBB . addReg ( PR ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( PR , TRI ) << <STR_LIT> ) ;


<s> FnProperties adjustToCaller ( const FnProperties & CallerProps ) const {

FnProperties New ( ( Features & ~ TargetFeatures ) | CallerProps . Features ) ;


<s> if ( isSingleInputShuffleMask ( Mask ) ) { V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DAG ) ) ) ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Blend ; V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ;

V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 ) ;


<s> StringRef getName ( ) const { return StringRef ( reinterpret_cast < const char * > ( this ) + sizeof ( * this ) , namesz ) ;


<s> std :: fill ( LiveRegs , LiveRegs + NumRegs , ( DomainValue * ) <NUM_LIT> ) ; } if ( LiveRegs [ rx ] == dv ) return ; if ( LiveRegs [ rx ] ) {

assert ( LiveRegs [ rx ] -> Refs && <STR_LIT> ) ;


<s> } int LastOpcode = LastInst -> getOpcode ( ) ; int SecLastOpcode = SecondLastInst ? SecondLastInst -> getOpcode ( ) : <NUM_LIT> ; if ( LastOpcode == <STR_LIT> && ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( SecLastOpcode == <STR_LIT> && ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNVJump = isNewValueJump ( * LastInst ) ; if ( LastOpcodeHasJMP_c && ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isEndLoopN ( LastOpcode ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasNVJump && ( LastInst -> getNumExplicitOperands ( ) == <NUM_LIT> ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getNumber ( ) << <STR_LIT> ; ) ; return true ; } bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNVJump = isNewValueJump ( * SecondLastInst ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { if ( ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( SecondLastInst -> getOpcode ( ) ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ;


<s> bool <ISA_LIT>AsmParser :: generateImmOutOfRangeError ( OperandVector & Operands , uint64_t ErrorInfo , int64_t Lower , int64_t Upper , Twine Msg = <STR_LIT> ) {

SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ;


<s> case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : return Is64Bit ? COFF :: IMAGE_REL_AMD64_REL32 : COFF :: IMAGE_REL_I386_REL32 ; case FK_Data_4 : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return Is64Bit ? COFF :: IMAGE_REL_AMD64_ADDR32NB : COFF :: IMAGE_REL_I386_DIR32NB ; return Is64Bit ? COFF :: IMAGE_REL_AMD64_ADDR32 : COFF :: IMAGE_REL_I386_DIR32 ; case FK_Data_8 : if ( Is64Bit ) return COFF :: IMAGE_REL_AMD64_ADDR64 ; llvm_unreachable ( <STR_LIT> ) ; case FK_SecRel_4 : return Is64Bit ? COFF :: IMAGE_REL_AMD64_SECREL : COFF :: IMAGE_REL_I386_SECREL ; default :


<s> load_got_register ( ) ; return global_offset_table_rtx ; }


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const { return ;


<s> return MO . isImm ( ) && ! isInlineConstant ( MI , OpIdx ) ;


<s> Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; break ; default : return false ; } uint64_t Size ; uint64_t Bits ; if ( VT == <STR_LIT> ) { Bits = <NUM_LIT> ; Size = <NUM_LIT> ; } else if ( VT == <STR_LIT> ) { Bits = <NUM_LIT> ; Size = <NUM_LIT> ; } else return false ; SDValue ShiftAmt = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue NewShiftAmt ; if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> || ShiftAmt -> getOpcode ( ) == <STR_LIT> ) ShiftAmt = ShiftAmt -> getOperand ( <NUM_LIT> ) ; if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> || ShiftAmt -> getOpcode ( ) == <STR_LIT> ) { SDValue Add0 = ShiftAmt -> getOperand ( <NUM_LIT> ) ; SDValue Add1 = ShiftAmt -> getOperand ( <NUM_LIT> ) ; uint64_t Add0Imm ; uint64_t Add1Imm ; if ( isIntImmediate ( Add1 , Add1Imm ) && ( Add1Imm % Size == <NUM_LIT> ) ) NewShiftAmt = Add0 ; else if ( ShiftAmt -> getOpcode ( ) == <STR_LIT> && isIntImmediate ( Add0 , Add0Imm ) && Add0Imm != <NUM_LIT> && ( Add0Imm % Size == <NUM_LIT> ) ) { unsigned NegOpc ; unsigned ZeroReg ; EVT SubVT = ShiftAmt -> getValueType ( <NUM_LIT> ) ; if ( SubVT == <STR_LIT> ) { NegOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } else { assert ( SubVT == <STR_LIT> ) ; NegOpc = <STR_LIT> ; ZeroReg = <STR_LIT> ; } SDValue Zero = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DL , ZeroReg , SubVT ) ; MachineSDNode * Neg = CurDAG -> getMachineNode ( NegOpc , DL , SubVT , Zero , Add1 ) ; NewShiftAmt = SDValue ( Neg , <NUM_LIT> ) ; } else return false ; } else { uint64_t MaskImm ; if ( ! isOpcWithIntImmediate ( ShiftAmt . getNode ( ) , <STR_LIT> , MaskImm ) && ! isOpcWithIntImmediate ( ShiftAmt . getNode ( ) , <STR_LIT> , MaskImm ) ) return false ; if ( countTrailingOnes ( MaskImm ) < Bits ) return false ; NewShiftAmt = ShiftAmt -> getOperand ( <NUM_LIT> ) ; } if ( VT == <STR_LIT> ) NewShiftAmt = narrowIfNeeded ( CurDAG , NewShiftAmt ) ; else if ( VT == <STR_LIT> && NewShiftAmt -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; MachineSDNode * Ext = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , NewShiftAmt , SubReg ) ; NewShiftAmt = SDValue ( Ext , <NUM_LIT> ) ;


<s> return ( __m256 ) __builtin_ia32_broadcastf32x4_256_mask ( ( __v4sf ) __A , ( __v8sf ) _mm256_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ; ++ OpNo ; break ; } }


<s> enum rtx_code test = GET_CODE ( operands [ <NUM_LIT> ] ) ; rtx cc_reg = frv_emit_comparison ( test , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; machine_mode cc_mode = GET_MODE ( cc_reg ) ; label_ref = gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) ; test_rtx = gen_rtx_fmt_ee ( test , cc_mode , cc_reg , const0_rtx ) ;


<s> FunctionCallee <ISA_LIT>LibCalls :: getFunction ( Module * M , const FuncInfo & fInfo ) { return EnablePreLink ? <ISA_LIT>LibFunc :: getOrInsertFunction ( M , fInfo ) : <ISA_LIT>LibFunc :: getFunction ( M , fInfo ) ;


<s> static tree aarch64_simd_builtin_std_type ( machine_mode mode , enum aarch64_type_qualifiers q ) { ( ( q == qualifier_none ) ? int ## M ## _type_node : unsigned_int ## M ## _type_node ) ; switch ( mode ) { case E_QImode : return QUAL_TYPE ( QI ) ; case E_HImode : return QUAL_TYPE ( HI ) ; case E_SImode : return QUAL_TYPE ( SI ) ; case E_DImode : return QUAL_TYPE ( DI ) ;


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue N2 = N -> getOperand ( <NUM_LIT> ) ; SDValue Addr ; SDValue Offset , Base ; unsigned Opcode ; <STR_LIT> SourceVT = N1 . getNode ( ) -> getSimpleValueType ( <NUM_LIT> ) . SimpleTy ; if ( SelectDirectAddr ( N2 , Addr ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } SDValue Ops [ ] = { N1 , getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( toType ) , getI32Imm ( toTypeWidth ) , Addr , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; } else if ( Subtarget . is64Bit ( ) ? SelectADDRsi64 ( N2 . getNode ( ) , N2 , Base , Offset ) : SelectADDRsi ( N2 . getNode ( ) , N2 , Base , Offset ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } SDValue Ops [ ] = { N1 , getI32Imm ( isVolatile ) , getI32Imm ( codeAddrSpace ) , getI32Imm ( vecType ) , getI32Imm ( toType ) , getI32Imm ( toTypeWidth ) , Base , Offset , Chain } ; <ISA_LIT>ST = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , Ops ) ; } else if ( Subtarget . is64Bit ( ) ? SelectADDRri64 ( N2 . getNode ( ) , N2 , Base , Offset ) : SelectADDRri ( N2 . getNode ( ) , N2 , Base , Offset ) ) { if ( Subtarget . is64Bit ( ) ) { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; default : return nullptr ; } } else { switch ( SourceVT ) { case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ;


<s> bool isSrcIdx8 ( ) const { return isMem8 ( ) && isSrcIdx ( ) ;


<s> static RegImmPair getRegImmPairPreventingCompression ( const MachineInstr & MI ) { const unsigned Opcode = MI . getOpcode ( ) ; if ( isCompressibleLoad ( MI ) || isCompressibleStore ( MI ) ) { const MachineOperand & MOImm = MI . getOperand ( <NUM_LIT> ) ; if ( ! MOImm . isImm ( ) ) return RegImmPair ( <STR_LIT> , <NUM_LIT> ) ; int64_t Offset = MOImm . getImm ( ) ; int64_t NewBaseAdjust = getBaseAdjustForCompression ( Offset , Opcode ) ; Register Base = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( <STR_LIT> . contains ( Base ) ) { if ( ! compressibleSPOffset ( Offset , Opcode ) && NewBaseAdjust ) return RegImmPair ( Base , NewBaseAdjust ) ; } else { Register SrcDest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool SrcDestCompressed = isCompressedReg ( SrcDest ) ; bool BaseCompressed = isCompressedReg ( Base ) ; if ( ( ! BaseCompressed || NewBaseAdjust ) && SrcDestCompressed ) return RegImmPair ( Base , NewBaseAdjust ) ;


<s> void <ISA_LIT>AsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved ) const {

Value = adjustFixupValue ( Fixup , Value , & Asm . getContext ( ) ) ;


<s> if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) ) return RegStructReturn ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target & T , StringRef TT , StringRef CPU ) { if ( Triple ( TT ) . isOSNaCl ( ) ) return new NaCl<ISA_LIT>AsmBackend ( T , false ) ;

return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( ) , true , false ) ;


<s> if ( memOpAlign ( SrcAlign , DstAlign , AlignCheck ) ) return true ; bool Fast ; return allowsMisalignedMemoryAccesses ( VT , <NUM_LIT> , <NUM_LIT> , & Fast ) && Fast ; } ; if ( CanUseNEON && IsMemset && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) ) return <STR_LIT> ; if ( CanUseFP && ! IsSmallMemset && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) ) return <STR_LIT> ; if ( Size >= <NUM_LIT> && AlignmentIsAcceptable ( <STR_LIT> , <NUM_LIT> ) ) return <STR_LIT> ;


<s> return _mm_adds_pu8 ( __m1 , __m2 ) ;


<s> uint64_t THMTo<ISA_LIT>Stub :: initSymValue ( ) const {


<s> unsigned DestReg = IsStoreXReg ? Register ( TRI -> getMatchingSuperReg ( LdRt , <STR_LIT> , & <STR_LIT> ) ) : LdRt ; assert ( ( UnscaledLdOffset >= UnscaledStOffset && ( UnscaledLdOffset + LoadSize ) <= UnscaledStOffset + StoreSize ) && <STR_LIT> ) ; int Immr = <NUM_LIT> * ( UnscaledLdOffset - UnscaledStOffset ) ; int Imms = Immr + Width - <NUM_LIT> ; if ( UnscaledLdOffset == UnscaledStOffset ) { uint32_t AndMaskEncoded = ( ( IsStoreXReg ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ) | ( ( Immr ) << <NUM_LIT> ) | ( ( Imms ) << <NUM_LIT> ) ; BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( AndMaskEncoded ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } else { BitExtMI = BuildMI ( * LoadI -> getParent ( ) , LoadI , LoadI -> getDebugLoc ( ) , TII -> get ( IsStoreXReg ? <STR_LIT> : <STR_LIT> ) , DestReg ) . add ( StMO ) . addImm ( Immr ) . addImm ( Imms ) . setMIFlags ( LoadI -> getFlags ( ) ) ; } } for ( MachineInstr & MI : make_range ( StoreI -> getIterator ( ) , BitExtMI -> getIterator ( ) ) ) if ( MI . killsRegister ( StRt , TRI ) ) { MI . clearRegisterKills ( StRt , TRI ) ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( LoadI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( StoreI -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ( BitExtMI ) -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LoadI -> eraseFromParent ( ) ; return NextI ;


<s> Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; HasLEB128 = true ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; HasLCOMMDirective = true ; DwarfRequiresFrameSection = false ;


<s> return ( cond == GE || cond == LT ) ;


<s> void AnalyzeCallOperands ( const SmallVectorImpl < <STR_LIT> > & Outs , CCAssignFn Fn , std :: vector < TargetLowering :: ArgListEntry > & FuncArgs , const SDNode * CallNode ) { PreAnalyzeCallOperands ( Outs , FuncArgs , CallNode ) ;

CCState :: AnalyzeCallOperands ( Outs , Fn ) ;


return ( poly8x8_t ) ~ ( ( int8x8_t ) __a ) ;


<s> SDValue TlsReadTp ; if ( NaClReadTp == NULL ) TlsReadTp = DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) ; else TlsReadTp = DAG . getGlobalAddress ( NaClReadTp , DL , PtrVT ) ; ArgListTy Args ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , PtrTy , TlsReadTp , std :: move ( Args ) , <NUM_LIT> ) ;

std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ;


<s> EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( ! Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . is128BitVector ( ) ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) {

if ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return Op ;


for ( group = <NUM_LIT> ; group < NUM_GROUPS ; group ++ ) frv_packet . groups [ group ] . num_insns = <NUM_LIT> ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode ) { return true ; }

const MachineOperand & MO = MI -> getOperand ( OpNum ) ;


<s> BuildMI ( MBB , I , DL , get ( TargetOpcode :: COPY ) , FReg ) . addReg ( FalseReg ) ; TrueReg = TReg ; FalseReg = FReg ; } } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( STI . hasMiscellaneousExtensions3 ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ;

BuildMI ( MBB , I , DL , get ( Opc ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) . addImm ( CCValid ) . addImm ( CCMask ) ;


<s> if ( VT . getSimpleVT ( ) . getScalarType ( ) == <STR_LIT> ) return false ; if ( VT . getSimpleVT ( ) . getSizeInBits ( ) == <NUM_LIT> ) return false ;

return isTypeLegal ( VT . getSimpleVT ( ) ) ;


<s> return ! SPARC_SIMM13_P ( i ) && SPARC_SETHI_P ( i ) ; } return <NUM_LIT> ;


<s> void msp430_start_function ( FILE * file , const char * name , tree decl ) { tree int_attr ; int_attr = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( decl ) ) ; if ( int_attr != NULL_TREE ) { tree intr_vector = TREE_VALUE ( int_attr ) ; if ( intr_vector != NULL_TREE ) { char buf [ <NUM_LIT> ] ; intr_vector = TREE_VALUE ( intr_vector ) ; if ( TREE_CODE ( intr_vector ) == STRING_CST ) sprintf ( buf , <STR_LIT> , TREE_STRING_POINTER ( intr_vector ) ) ; else sprintf ( buf , <STR_LIT> , ( unsigned int ) TREE_INT_CST_LOW ( intr_vector ) ) ; switch_to_section ( get_section ( buf , SECTION_CODE , decl ) ) ;


<s> ScaledMask . assign ( static_cast < size_t > ( NumElts * Scale ) , - <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) { for ( int s = <NUM_LIT> ; s != Scale ; ++ s ) ScaledMask [ ( Scale * i ) + s ] = M ; continue ; }

for ( int s = <NUM_LIT> ; s != Scale ; ++ s ) ScaledMask [ ( Scale * i ) + s ] = ( Scale * M ) + s ;


<s> base = x ; break ; case PLUS : base = XEXP ( x , <NUM_LIT> ) ; addend = XEXP ( x , <NUM_LIT> ) ; if ( ! REG_P ( base ) ) return false ; if ( ! strict_p && virtual_frame_reg_operand ( base , VOIDmode ) ) return CONST_INT_P ( addend ) ; if ( ! satisfies_constraint_I ( addend ) ) return false ; break ; case LO_SUM : base = XEXP ( x , <NUM_LIT> ) ; if ( ! REG_P ( base ) ) return false ; x = XEXP ( x , <NUM_LIT> ) ; switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : case LABEL_REF :


<s> assert ( MF && <STR_LIT> ) ; if ( MF -> getFunction ( ) . getCallingConv ( ) == CallingConv :: CXX_FAST_TLS && MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> isSplitCSR ( ) ) return CSR_iOS_CXX_TLS_ViaCopy_SaveList ;


<s> static bool hasDimMask ( const MCInst * MI , const MCInstrDesc & MCID , const MCRegisterInfo & MRI ) { for ( const MCOperandInfo & Info : MCID . operands ( ) ) { if ( Info . OperandType == <STR_LIT> ) return true ; } if ( MI -> getNumOperands ( ) && MCID . getNumDefs ( ) ) { const MCOperand & Op = MI -> getOperand ( <NUM_LIT> ) ; if ( Op . isReg ( ) && MRI . getRegClass ( <STR_LIT> ) . contains ( Op . getReg ( ) ) ) return true ;


<s> const MachineOperand * Src0 = & MI . getOperand ( Src0Idx ) ; if ( ! Src0 -> isReg ( ) && ! Src0 -> isImm ( ) ) return nullptr ; if ( Src0 -> isImm ( ) && ! isInlineConstant ( MI , Src0Idx , * Src0 ) ) return nullptr ; break ; } } const MachineOperand * Dst = getNamedOperand ( MI , <STR_LIT> :: vdst ) ; const MachineOperand * Src0 = getNamedOperand ( MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src0Mods = getNamedOperand ( MI , <STR_LIT> :: src0_modifiers ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; const MachineOperand * Src1Mods = getNamedOperand ( MI , <STR_LIT> :: src1_modifiers ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; const MachineOperand * Clamp = getNamedOperand ( MI , <STR_LIT> :: clamp ) ; const MachineOperand * Omod = getNamedOperand ( MI , <STR_LIT> :: omod ) ; if ( ! IsFMA && ! Src0Mods && ! Src1Mods && ! Clamp && ! Omod && ( ! Src0 -> isReg ( ) || ! RI . isSGPRReg ( MBB -> getParent ( ) -> getRegInfo ( ) , Src0 -> getReg ( ) ) ) ) { if ( auto Imm = getFoldableImm ( Src2 ) ) { return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? <STR_LIT> : <STR_LIT> ) ) . add ( * Dst ) . add ( * Src0 ) . add ( * Src1 ) . addImm ( Imm ) ; } if ( auto Imm = getFoldableImm ( Src1 ) ) { return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? <STR_LIT> : <STR_LIT> ) ) . add ( * Dst ) . add ( * Src0 ) . addImm ( Imm ) . add ( * Src2 ) ; } if ( auto Imm = getFoldableImm ( Src0 ) ) { if ( isOperandLegal ( MI , <STR_LIT> ( <STR_LIT> , <STR_LIT> :: src0 ) , Src1 ) ) return BuildMI ( * MBB , MI , MI . getDebugLoc ( ) , get ( IsF16 ? <STR_LIT> : <STR_LIT> ) ) . add ( * Dst ) . add ( * Src1 ) . addImm ( Imm ) . add ( * Src2 ) ;


<s> case InlineAsm :: Constraint_X : case InlineAsm :: Constraint_p : if ( ! selectAddr ( nullptr , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ;


<s> bool trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const override {


<s> unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned pred = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Rn == <NUM_LIT> || Rn == Rt ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeSORegMemOperand ( Inst , imm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> Op -> Mem . OffsetRegShifted = OffsetRegShifted ; Op -> Mem . ShiftType = ShiftType ; Op -> Mem . ShiftAmount = ShiftAmount ; Op -> Mem . Preindexed = Preindexed ; Op -> Mem . Postindexed = Postindexed ; Op -> Mem . Negative = Negative ; Op -> Mem . Writeback = Writeback ; Op -> StartLoc = S ;


addPass ( create<ISA_LIT>RegNumbering ( ) ) ;


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;

Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> + RegNo ) ) ;


<s> const MCInstrDesc & InstDesc = get ( MI -> getOpcode ( ) ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - <NUM_LIT> ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI -> getOperand ( OpIdx ) ; if ( isVALU ( InstDesc . Opcode ) && usesConstantBus ( MRI , * MO , DefinedRC -> getSize ( ) ) ) { unsigned SGPRUsed = MO -> isReg ( ) ? MO -> getReg ( ) : ( unsigned ) AMDGPU :: NoRegister ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) != SGPRUsed && usesConstantBus ( MRI , Op , getOpSize ( * MI , i ) ) ) { return false ;


<s> } InlineAsmIdentifierInfo Info ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return <NUM_LIT> ; return CreateMemForInlineAsm ( <NUM_LIT> , Val , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size , Identifier , Info ) ;


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return EmitShiftInstr ( MI , BB ) ; const TargetInstrInfo & TII = * getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = BB ; ++ I ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , copy0MBB ) ; F -> insert ( I , copy1MBB ) ;

copy1MBB -> splice ( copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ;


<s> struct df_link * link = DF_REF_CHAIN ( use ) ; if ( ! link ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = <NUM_LIT> ; while ( link ) { if ( DF_REF_IS_ARTIFICIAL ( link -> ref ) ) insn_entry [ INSN_UID ( insn ) ] . is_live_in = <NUM_LIT> ;

if ( DF_REF_INSN_INFO ( link -> ref ) ) {


<s> return vldrwq_z_u32 ( __base , __p ) ;


<s> SDValue InLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;

SDValue InHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> SDValue Value , Overflow ; std :: tie ( Value , Overflow ) = get<ISA_LIT>XALUOOp ( CC , Sel . getValue ( <NUM_LIT> ) , DAG ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , TVal , FVal , CCVal , Overflow ) ; } if ( Sel . getOpcode ( ) != <STR_LIT> ) std :: swap ( Sel , Other ) ; if ( Sel . getOpcode ( ) != <STR_LIT> ) return Op ; <STR_LIT> CC = cast < CondCodeSDNode > ( Sel . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue RHS = Sel . getOperand ( <NUM_LIT> ) ; SDValue TVal = Sel . getOperand ( <NUM_LIT> ) ; SDValue FVal = Sel . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return Op ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TVal ) ; if ( ! CFVal || ! CTVal ) return Op ; if ( CTVal -> isAllOnesValue ( ) && CFVal -> isNullValue ( ) ) { std :: swap ( TVal , FVal ) ; std :: swap ( CTVal , CFVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; } if ( CTVal -> isNullValue ( ) && CFVal -> isAllOnesValue ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , CCVal , DAG , dl ) ; FVal = Other ; TVal = DAG . getNode ( <STR_LIT> , dl , Other . getValueType ( ) , Other , DAG . getConstant ( - <NUM_LIT> , dl , Other . getValueType ( ) ) ) ; return DAG . getNode ( <STR_LIT> , dl , Sel . getValueType ( ) , FVal , TVal , CCVal , Cmp ) ;


<s> if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , getTargetLowering ( ) -> getPointerTy ( ) ) ; } else { Base = Addr . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ; } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ; }


<s> DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i ) ; if ( CPChange && ++ NoCPIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ; MadeChange = true ; } if ( isThumb2 && ! STI -> prefers32BitThumb ( ) ) MadeChange |= optimizeThumb2Instructions ( ) ; verify ( ) ; if ( isThumb && ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) ) MadeChange |= undoLRSpillRestore ( ) ; for ( unsigned i = <NUM_LIT> , e = CPEntries . size ( ) ; i != e ; ++ i ) { for ( unsigned j = <NUM_LIT> , je = CPEntries [ i ] . size ( ) ; j != je ; ++ j ) { const CPEntry & CPE = CPEntries [ i ] [ j ] ; AFI -> recordCPEClone ( i , CPE . CPI ) ; } } DEBUG ( dbgs ( ) << '\n' ; dumpBBs ( ) ) ; BBInfo . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ;


<s> if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ; } else { return false ; } } if ( VT == <STR_LIT> ) return false ; if ( Fast ) * Fast = true ;


<s> t = build3 ( COND_EXPR , void_type_node , t , u , NULL_TREE ) ; gimplify_and_add ( t , pre_p ) ; t = sav ; if ( sav_ofs ) t = build2 ( PLUS_EXPR , ptr_type_node , sav , size_int ( sav_ofs ) ) ; u = build2 ( POSTINCREMENT_EXPR , TREE_TYPE ( reg ) , reg , size_int ( n_reg ) ) ; u = build1 ( CONVERT_EXPR , integer_type_node , u ) ; u = build2 ( MULT_EXPR , integer_type_node , u , size_int ( sav_scale ) ) ; t = build2 ( PLUS_EXPR , ptr_type_node , t , u ) ; t = build2 ( MODIFY_EXPR , void_type_node , addr , t ) ; gimplify_and_add ( t , pre_p ) ; t = build1 ( GOTO_EXPR , void_type_node , lab_over ) ; gimplify_and_add ( t , pre_p ) ; t = build1 ( LABEL_EXPR , void_type_node , lab_false ) ; append_to_statement_list ( t , pre_p ) ; if ( n_reg > <NUM_LIT> ) { t = build ( MODIFY_EXPR , TREE_TYPE ( reg ) , reg , size_int ( <NUM_LIT> ) ) ; gimplify_and_add ( t , pre_p ) ; } } t = ovf ; if ( align != <NUM_LIT> ) { t = build2 ( PLUS_EXPR , TREE_TYPE ( t ) , t , size_int ( align - <NUM_LIT> ) ) ; t = build2 ( BIT_AND_EXPR , TREE_TYPE ( t ) , t , build_int_cst ( NULL_TREE , - align ) ) ; } gimplify_expr ( & t , pre_p , NULL , is_gimple_val , fb_rvalue ) ; u = build2 ( MODIFY_EXPR , void_type_node , addr , t ) ; gimplify_and_add ( u , pre_p ) ; t = build2 ( PLUS_EXPR , TREE_TYPE ( t ) , t , size_int ( size ) ) ; t = build2 ( MODIFY_EXPR , TREE_TYPE ( ovf ) , ovf , t ) ; gimplify_and_add ( t , pre_p ) ; if ( lab_over ) {


<s> int min_preserve_fpr = INT_MAX , max_preserve_fpr = - <NUM_LIT> ; int min_fpr , max_fpr ; if ( cfun -> stdarg && TARGET_HARD_FLOAT && cfun -> va_list_fpr_size && crtl -> args . info . fprs < FP_ARG_NUM_REG ) { min_stdarg_fpr = crtl -> args . info . fprs ; max_stdarg_fpr = min_stdarg_fpr + cfun -> va_list_fpr_size - <NUM_LIT> ; if ( max_stdarg_fpr >= FP_ARG_NUM_REG ) max_stdarg_fpr = FP_ARG_NUM_REG - <NUM_LIT> ; min_stdarg_fpr += FPR0_REGNUM ; max_stdarg_fpr += FPR0_REGNUM ; } if ( s390_preserve_args_p && crtl -> args . info . fprs ) { min_preserve_fpr = FPR0_REGNUM ; max_preserve_fpr = MIN ( FPR0_REGNUM + FP_ARG_NUM_REG - <NUM_LIT> , FPR0_REGNUM + crtl -> args . info . fprs - <NUM_LIT> ) ; } min_fpr = MIN ( min_stdarg_fpr , min_preserve_fpr ) ; max_fpr = MAX ( max_stdarg_fpr , max_preserve_fpr ) ;


<s> static SDValue Expand64BitShift ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ShOpc = N -> getOpcode ( ) ; if ( ST -> hasMVEIntegerOps ( ) ) { SDValue ShAmt = N -> getOperand ( <NUM_LIT> ) ; unsigned ShPartsOpc = <STR_LIT> ; ConstantSDNode * Con = dyn_cast < ConstantSDNode > ( ShAmt ) ; if ( Con && Con -> getZExtValue ( ) > <NUM_LIT> ) return SDValue ( ) ; if ( ShAmt -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; if ( ShOpc == <STR_LIT> ) { if ( ! Con ) ShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , ShAmt ) ; else ShPartsOpc = <STR_LIT> ; } else if ( ShOpc == <STR_LIT> ) ShPartsOpc = <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Lo = DAG . getNode ( ShPartsOpc , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Lo , Hi , ShAmt ) ; Hi = SDValue ( Lo . getNode ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; }

if ( ! isOneConstant ( N -> getOperand ( <NUM_LIT> ) ) || N -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ;

if ( ( ( Subtarget -> hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasFp256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , false ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , LHS , RHS ) ;


<s> std :: vector < std :: string > alb ( Alb op , Imm16 a , SttMod b ) {


<s> vmovl_high_u32 ( uint32x4_t a ) { uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> void <ISA_LIT>TargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) {