<s> static unsigned getMaxCalleeSavedReg ( ArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo & TRI ) { static_assert ( <STR_LIT> > <NUM_LIT> , <STR_LIT> ) ; if ( CSI . empty ( ) ) return <NUM_LIT> ; unsigned Max = getMax32BitSubRegister ( CSI [ <NUM_LIT> ] . getReg ( ) , TRI ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I < E ; ++ I ) {

unsigned Reg = getMax32BitSubRegister ( CSI [ I ] . getReg ( ) , TRI ) ;


<s> if ( ! STI . getFeatureBits ( ) . test ( FeatureSupportsSRAMECC ) ) SramEccSetting = TargetIDSetting :: Unsupported ;


<s> mac_op0 = XEXP ( XEXP ( XEXP ( mac , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ; mac_op1 = XEXP ( XEXP ( XEXP ( mac , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ; mac_acc = XEXP ( XEXP ( mac , <NUM_LIT> ) , <NUM_LIT> ) ;


<s> static unsigned findDeadCallerSavedReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const TargetRegisterInfo * TRI , bool Is64Bit ) { const MachineFunction * MF = MBB . getParent ( ) ; const Function * F = MF -> getFunction ( ) ; if ( ! F || MF -> getMMI ( ) . callsEHReturn ( ) ) return <NUM_LIT> ; static const uint16_t CallerSavedRegs32Bit [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const uint16_t CallerSavedRegs64Bit [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; unsigned Opc = MBBI -> getOpcode ( ) ; switch ( Opc ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; }


<s> static SDValue getGeneralPermuteNode ( SelectionDAG & DAG , SDLoc DL , SDValue * Ops , const SmallVectorImpl < int > & Bytes ) { for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) Ops [ I ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ I ] ) ; unsigned StartIndex , OpNo0 , OpNo1 ; if ( isShlDoublePermute ( Bytes , StartIndex , OpNo0 , OpNo1 ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ OpNo0 ] , Ops [ OpNo1 ] , DAG . getConstant ( StartIndex , DL , <STR_LIT> ) ) ; SDValue IndexNodes [ <STR_LIT> ] ;

for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; ++ I ) if ( Bytes [ I ] >= <NUM_LIT> ) IndexNodes [ I ] = DAG . getConstant ( Bytes [ I ] , DL , <STR_LIT> ) ;


<s> isICmp = false ; if ( isEquality ) CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; else CmpOpc = UseImm ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : needsExt = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( isThumb2 ) { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } else { if ( ! UseImm ) CmpOpc = <STR_LIT> ; else CmpOpc = isNegativeImm ? <STR_LIT> : <STR_LIT> ; } break ; } unsigned SrcReg1 = getRegForValue ( Src1Value ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = <NUM_LIT> ; if ( ! UseImm ) { SrcReg2 = getRegForValue ( Src2Value ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } if ( needsExt ) { SrcReg1 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg1 , <STR_LIT> , isZExt ) ; if ( SrcReg1 == <NUM_LIT> ) return false ; if ( ! UseImm ) { SrcReg2 = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg2 , <STR_LIT> , isZExt ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; } } const MCInstrDesc & II = TII . get ( CmpOpc ) ; SrcReg1 = constrainOperandRegClass ( II , SrcReg1 , <NUM_LIT> ) ; if ( ! UseImm ) { SrcReg2 = constrainOperandRegClass ( II , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; } else { MachineInstrBuilder MIB ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( SrcReg1 ) ; if ( isICmp ) MIB . addImm ( Imm ) ;


<s> if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Shuf128 ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ;

return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> uint16x4x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( Opc , dl , VT , V1 , V2 ) ; } return SDValue ( ) ;


<s> void EmitConstantPool ( ) override {


<s> return Ty . getSizeInBits ( ) % <NUM_LIT> == <NUM_LIT> ; } ;


<s> const RegisterAggr & getLiveIns ( ) const { return LiveIns ;


<s> machine_mode mode = GET_MODE ( target ) ; machine_mode inner_mode = GET_MODE_INNER ( mode ) ; int n_elts = GET_MODE_NUNITS ( mode ) ; bool all_same = true , all_regs = true , all_const_int = true ; rtx x ; int i ; for ( i = <NUM_LIT> ; i < n_elts ; ++ i ) { x = XVECEXP ( vals , <NUM_LIT> , i ) ; if ( ! CONST_INT_P ( x ) ) all_const_int = false ; if ( i > <NUM_LIT> && ! rtx_equal_p ( x , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) all_same = false ; if ( ! REG_P ( x ) ) all_regs = false ;


<s> static inline bool isImmHH ( uint64_t Val ) { return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;


<s> const char * getPassName ( ) const { return <STR_LIT> ;


<s> Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler :: Success ;


<s> MIRBuilder . getMRI ( ) -> addLiveIn ( PhysReg ) ; MIRBuilder . getMBB ( ) . addLiveIn ( PhysReg ) ;

IncomingValueHandler :: assignValueToReg ( ValVReg , PhysReg , VA ) ;


<s> op2 = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( op1 ) == REG && CONST_INT_P ( op2 ) && INTVAL ( op2 ) >= - <NUM_LIT> && INTVAL ( op2 ) < <NUM_LIT> && reg_ok_for_base_p ( op1 , strict ) ) goto yes ; if ( GET_CODE ( op1 ) == SYMBOL_REF && CONST_INT_P ( op2 ) ) goto yes ; } if ( REG_P ( x ) && reg_ok_for_base_p ( x , strict ) ) goto yes ; if ( GET_CODE ( x ) == SYMBOL_REF || GET_CODE ( x ) == LABEL_REF || CONST_INT_P ( x ) ) goto yes ; } else { if ( REG_P ( x ) && reg_ok_for_base_p ( x , strict ) ) goto yes ; } return <NUM_LIT> ; yes :


<s> if ( ! CONST_INT_P ( elt ) ) return false ; HOST_WIDE_INT val = INTVAL ( elt ) ; if ( negate_p ) val = - val ;

val &= GET_MODE_MASK ( GET_MODE_INNER ( mode ) ) ;


<s> unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool isPICBase = false ; for ( MachineRegisterInfo :: def_iterator I = MRI . def_begin ( BaseReg ) , E = MRI . def_end ( ) ; I != E ; ++ I ) { MachineInstr * DefMI = I . getOperand ( ) . getParent ( ) ; if ( DefMI -> getOpcode ( ) != <STR_LIT> ) return false ; assert ( ! isPICBase && <STR_LIT> ) ; isPICBase = true ; } return isPICBase ; } return false ; } case <STR_LIT> : case <STR_LIT> : {

if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <NUM_LIT> && ! MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) {


<s> if ( strcmp ( m32r_model_string , <STR_LIT> ) == <NUM_LIT> ) m32r_model = M32R_MODEL_SMALL ; else if ( strcmp ( m32r_model_string , <STR_LIT> ) == <NUM_LIT> ) m32r_model = M32R_MODEL_MEDIUM ; else if ( strcmp ( m32r_model_string , <STR_LIT> ) == <NUM_LIT> ) m32r_model = M32R_MODEL_LARGE ; else error ( <STR_LIT> , m32r_model_string ) ; if ( strcmp ( m32r_sdata_string , <STR_LIT> ) == <NUM_LIT> ) m32r_sdata = M32R_SDATA_NONE ; else if ( strcmp ( m32r_sdata_string , <STR_LIT> ) == <NUM_LIT> ) m32r_sdata = M32R_SDATA_SDATA ; else if ( strcmp ( m32r_sdata_string , <STR_LIT> ) == <NUM_LIT> ) m32r_sdata = M32R_SDATA_USE ; else error ( <STR_LIT> , m32r_sdata_string ) ;


<s> if ( type && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST ) size = int_size_in_bytes ( type ) ; } else size = GET_MODE_SIZE ( mode ) ; if ( size == <NUM_LIT> || size == <NUM_LIT> || size == <NUM_LIT> ) return PAD_DOWNWARD ; } return PAD_UPWARD ;


<s> else { q = a - z ; zz = q + c + ( a - ( q + z ) ) + aa + cc ; if ( zz == <NUM_LIT> ) return z ; xh = z + zz ; if ( nonfinite ( xh ) ) return xh ; x . dval [ <NUM_LIT> ] = xh ;


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return CS_Encoding ; case <STR_LIT> : return DS_Encoding ; case <STR_LIT> : return ES_Encoding ; case <STR_LIT> : return FS_Encoding ; case <STR_LIT> : return GS_Encoding ;


<s> bool mayAlias ( const MachineFrameInfo * ) const override { return false ;


<s> if ( RegNum > getContext ( ) . getRegisterInfo ( ) -> getRegClass ( RegClass ) . getNumRegs ( ) ) return - <NUM_LIT> ; return getReg ( RegClass , RegNum ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: isPredicable ( MachineInstr * MI ) const { if ( ! MI -> isPredicable ( ) ) return false ; <ISA_LIT>FunctionInfo * AFI = MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( MI ) ; } else { if ( ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ;


<s> if ( CannotReserveFrame ) return true ; Align StackAlign = TFL -> getStackAlign ( ) ; int64_t Advantage = <NUM_LIT> ; for ( auto CC : CallSeqVector ) { if ( CC . NoStackParams ) continue ; if ( ! CC . UsePush ) { Advantage -= <NUM_LIT> ; } else { Advantage -= <NUM_LIT> ; if ( ! isAligned ( StackAlign , CC . ExpectedDist ) ) Advantage -= <NUM_LIT> ; Advantage += ( CC . ExpectedDist >> Log2SlotSize ) * <NUM_LIT> ; } } return Advantage >= <NUM_LIT> ;


<s> explicit blkdrop ( unsigned sz ) : sz ( sz ) { assert ( sz >= <NUM_LIT> && <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isNarrowingProfitable ( MVT VT1 , MVT VT2 ) const {

return ! ( VT1 == <STR_LIT> && VT2 == <STR_LIT> ) ;


<s> <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNo ) . getImm ( ) ;


<s> const BranchInst * BI = cast < BranchInst > ( I ) ; MachineBasicBlock * BrBB = FuncInfo . MBB ; MachineBasicBlock * TBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; MachineBasicBlock * FBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; if ( const CmpInst * CI = dyn_cast < CmpInst > ( BI -> getCondition ( ) ) ) { Optional < <STR_LIT> > Opt<ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( ! Opt<ISA_LIT>Pred ) return false ; <STR_LIT> <ISA_LIT>Pred = Opt<ISA_LIT>Pred . getValue ( ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; <ISA_LIT>Pred = <STR_LIT> ( <ISA_LIT>Pred ) ; } unsigned CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; FastEmitBranch ( FBB , DL ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; FastEmitBranch ( Target , DL ) ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> return parseRegister ( Operands , FP32Reg ) ;


<s> uint8_t <ISA_LIT>TargetLowering :: getRepRegClassCostFor ( MVT VT ) const {


<s> uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ;

<STR_LIT> :: write < uint64_t > ( OS , Bits , <STR_LIT> ) ;


<s> hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ;


<s> if ( ! getMemOperandsWithOffsetWidth ( MIa , BaseOps0 , Offset0 , Offset0IsScalable , Dummy0 , & RI ) || ! getMemOperandsWithOffsetWidth ( MIb , BaseOps1 , Offset1 , Offset1IsScalable , Dummy1 , & RI ) ) return false ;

if ( ! memOpsHaveSameBaseOperands ( BaseOps0 , BaseOps1 ) ) return false ;


<s> if ( Modifier == MCSymbolRefExpr :: VK_None && ! IsPCRel ) return RT64_32S ; return RT64_32 ; case <STR_LIT> : Modifier = MCSymbolRefExpr :: VK_GOT ; IsPCRel = true ; return RT64_32 ; case FK_Data_4 : case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return RT64_32 ; case FK_PCRel_2 :


if ( isSequentialOrUndefInRange ( Mask , <NUM_LIT> , NumElements / <NUM_LIT> , NumElements ) ) return V2 ;


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;


<s> status CostTree :: computeAllPath ( allPath * globalPath , CostLeaf * current , vector < CostLeaf * > list , int costCollect ) { if ( ! globalPath ) return status :: LOOPSTATUS ; list . push_back ( current ) ; for ( auto leaf = current -> getChildren ( ) -> begin ( ) , end = current -> getChildren ( ) -> end ( ) ; leaf != end ; leaf ++ ) { if ( ( * leaf ) -> getType ( ) == nodeType :: LOOP ) return status :: LOOPSTATUS ; if ( * leaf != globalPath -> getEnd ( ) ) { <ISA_LIT>_DEBUG ( <STR_LIT> + to_string ( ( * leaf ) -> getMachinBB ( ) -> getNumber ( ) ) + <STR_LIT> ) ; if ( computeAllPath ( globalPath , * leaf , list , ( * leaf ) -> getCycle ( ) + costCollect ) == status :: LOOPSTATUS ) return status :: LOOPSTATUS ; } else { globalPath -> pushToAllPath ( list , costCollect ) ;


<s> SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , DAG , DCI , Subtarget ) ) { DCI . CombineTo ( N , Res ) ; return SDValue ( ) ;


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_popcnt_u32 ( unsigned int __X ) {


<s> auto Mad = B . buildFMAD ( S32 , CvtHi , B . buildFConstant ( S32 , BitsToFloat ( <NUM_LIT> ) ) , CvtLo ) ; auto Rcp = B . buildInstr ( <STR_LIT> , { S32 } , { Mad } ) ; auto Mul1 = B . buildFMul ( S32 , Rcp , B . buildFConstant ( S32 , BitsToFloat ( <NUM_LIT> ) ) ) ; auto Mul2 = B . buildFMul ( S32 , Mul1 , B . buildFConstant ( S32 , BitsToFloat ( <NUM_LIT> ) ) ) ; auto Trunc = B . buildIntrinsicTrunc ( S32 , Mul2 ) ; auto Mad2 = B . buildFMAD ( S32 , Trunc , B . buildFConstant ( S32 , BitsToFloat ( <NUM_LIT> ) ) , Mul1 ) ;

auto ResultLo = B . buildFPTOUI ( S32 , Mad2 ) ;


<s> rtx * base_ptr ; if ( GET_CODE ( ref ) != MEM ) return ;

if ( ! MEM_VOLATILE_P ( ref ) && ! MEM_IN_STRUCT_P ( ref ) && ! MEM_SCALAR_P ( ref ) && ! MEM_NOTRAP_P ( ref ) && ! MEM_READONLY_P ( ref ) ) return ;


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return false ; const MachineInstr * MI = MRI . getUniqueVRegDef ( Reg ) ;


<s> case k_FPImm : OS << <STR_LIT> << getFPImm ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( ! getFPImmIsExact ( ) ) OS << <STR_LIT> ; OS << <STR_LIT> ; break ; case k_Barrier : { StringRef Name = getBarrierName ( ) ; if ( ! Name . empty ( ) ) OS << <STR_LIT> << Name << <STR_LIT> ; else OS << <STR_LIT> << getBarrier ( ) << <STR_LIT> ; break ; } case k_Immediate : OS << * getImm ( ) ; break ; case k_ShiftedImm : { unsigned Shift = getShiftedImmShift ( ) ; OS << <STR_LIT> ; OS << * getShiftedImmVal ( ) ; OS << <STR_LIT> << <STR_LIT> ( Shift ) << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printLoopControl ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( OpNo < MI -> getNumOperands ( ) ) { unsigned e = static_cast < unsigned > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; O << <STR_LIT> ( e ) ;


<s> int <ISA_LIT>FunctionInfo :: createFPSpillSlot ( MachineFunction & MF ) { if ( FPSpillSlotSet ) { return FPSpillSlot ; } const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; FPSpillSlot = MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , true ) ; FPSpillSlotSet = true ; return FPSpillSlot ;


<s> bool isSOP2 ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( ) ;

return VT . changeVectorElementTypeToInteger ( ) ;


<s> RegNum = matchACRegisterName ( RegName ) ; break ; default : break ; } if ( RegNum < <NUM_LIT> ) return MatchOperand_NoMatch ; int RegVal = getReg ( regKindToRegClass ( Kind ) , RegNum ) ; if ( RegVal == - <NUM_LIT> ) return MatchOperand_NoMatch ; <ISA_LIT>Operand * Op = <STR_LIT> ( RegVal , S , Parser . getTok ( ) . getLoc ( ) ) ; Op -> setRegKind ( Kind ) ; Operands . push_back ( Op ) ; hasConsumedDollar = false ; Parser . Lex ( ) ; return MatchOperand_Success ; } else if ( getLexer ( ) . getKind ( ) == AsmToken :: Integer ) { unsigned RegNum = Parser . getTok ( ) . getIntVal ( ) ; if ( Kind == <STR_LIT> ) { if ( RegNum != <NUM_LIT> ) return MatchOperand_NoMatch ; RegNum = <NUM_LIT> ; } int Reg = matchRegisterByNumber ( RegNum , regKindToRegClass ( Kind ) ) ; if ( Reg == - <NUM_LIT> ) return MatchOperand_NoMatch ;

<ISA_LIT>Operand * Op = <STR_LIT> ( Reg , S , Parser . getTok ( ) . getLoc ( ) ) ;


<s> unsigned int old = * mask , ret , new ; while ( <NUM_LIT> ) { if ( old == <NUM_LIT> ) return - <NUM_LIT> ; ret = old & - old ; new = old & ~ ret ; new = __sync_val_compare_and_swap ( mask , old , new ) ;


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & , MachineBasicBlock & MBB ) const {


<s> MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Stubs [ i ] . second . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; } Stubs . clear ( ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const { static const unsigned Regs [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ;

return Regs [ TFI -> hasFP ( MF ) ] [ TT . isArch64Bit ( ) ] ;


<s> Value * <ISA_LIT>IREmitter :: visitEH_SJLJ_SETJMP ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> assert ( Fixup . getOffset ( ) + Size <= DataSize && <STR_LIT> ) ; char * data = Data + Fixup . getOffset ( ) ; switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : case <NUM_LIT> : llvm_unreachable ( <STR_LIT> ) ; }


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseCCRRegs ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseRegs ( Operands , ( int ) <STR_LIT> ) ;


<s> return LowerVACOPY ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerSTACKRESTORE ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG , <ISA_LIT>SubTarget ) ; case <STR_LIT> : return lowerEH_SJLJ_SETJMP ( Op , DAG ) ; case <STR_LIT> : return lowerEH_SJLJ_LONGJMP ( Op , DAG ) ; case <STR_LIT> : return LowerLOAD ( Op , DAG ) ; case <STR_LIT> : return LowerSTORE ( Op , DAG ) ; case <STR_LIT> : return LowerTRUNCATE ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ;

case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ;


<s> void <ISA_LIT>TargetMachine :: adjustPassManager ( PassManagerBuilder & Builder ) { Builder . addExtension ( PassManagerBuilder :: EP_EarlyAsPossible , [ & ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) {

PM . add ( createNVVMReflectPass ( Subtarget . getSmVersion ( ) ) ) ;


<s> MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; int FPOffset = <ISA_LIT>FI -> getFPStackOffset ( ) ; int RAOffset = <ISA_LIT>FI -> getRAStackOffset ( ) ; if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( FPOffset ) . addReg ( <STR_LIT> ) ; } if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( RAOffset ) . addReg ( <STR_LIT> ) ; }


<s> unsigned ConvOpc = IsSingle ? ( IsSigned ? <STR_LIT> : <STR_LIT> ) : ( IsSigned ? <STR_LIT> : <STR_LIT> ) ; EVT ConvTy = IsSingle ? <STR_LIT> : <STR_LIT> ;

return DAG . getNode ( ConvOpc , dl , ConvTy , Src ) ;


<s> LLT S32 = LLT :: scalar ( <NUM_LIT> ) ; LLT S1 = LLT :: scalar ( <NUM_LIT> ) ; auto Abs = B . buildFAbs ( S32 , RHS , Flags ) ; const APFloat C0Val ( <NUM_LIT> ) ; auto C0 = B . buildConstant ( S32 , <NUM_LIT> ) ; auto C1 = B . buildConstant ( S32 , <NUM_LIT> ) ; auto C2 = B . buildConstant ( S32 , FloatToBits ( <NUM_LIT> ) ) ; auto CmpRes = B . buildFCmp ( CmpInst :: FCMP_OGT , S1 , Abs , C0 , Flags ) ; auto Sel = B . buildSelect ( S32 , CmpRes , C1 , C2 , Flags ) ;

auto Mul0 = B . buildFMul ( S32 , RHS , Sel , Flags ) ;


<s> return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } MCFixupKind FixupKind = static_cast < MCFixupKind > ( Fixup ) ;

Fixups . push_back ( MCFixup :: create ( Offset , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ;


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override {


<s> void <ISA_LIT>AsmParser :: convertToMapAndConstraints ( unsigned Kind , const OperandVector & Operands ) {

dbgs ( ) << <STR_LIT> << Kind << <STR_LIT> ;


<s> void Initialize ( MCAsmParser & Parser ) override {

MCAsmParserExtension :: Initialize ( Parser ) ;


<s> case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ;

case MachineOperand :: MO_ExternalSymbol :


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ;

SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ;


<s> case 'R' : case 'S' : case 'T' : case 'm' : return C_Memory ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' :


<s> for ( unsigned int i = <NUM_LIT> ; i < <ISA_LIT>GOT0Num ; ++ i ) new <ISA_LIT>GOTEntry ( <NUM_LIT> , m_SectionData ) ;


<s> void LLVMInitialize<ISA_LIT>65816AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>65816AsmPrinter > X ( The<ISA_LIT>65816Target ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> if ( Subtarget . hasZeroCycleZeroingFP ( ) ) { if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; } if ( Subtarget . hasZeroCycleZeroingGP ( ) ) { if ( Opcode == TargetOpcode :: COPY && ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return true ; } if ( Subtarget . hasExynosCheapAsMoveHandling ( ) ) { if ( isExynosResetFast ( MI ) || isExynosShiftLeftFast ( MI ) ) return true ; else return MI . isAsCheapAsAMove ( ) ; } switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ;


<s> MCI . addOperand ( MCOperand :: CreateInst ( nullptr ) ) ;


<s> int memory_reload_operand ( rtx operand , enum machine_mode mode ATTRIBUTE_UNUSED ) {

return GET_CODE ( operand ) == MEM && GET_CODE ( XEXP ( operand , <NUM_LIT> ) ) == PLUS && ( ( GET_CODE ( XEXP ( XEXP ( operand , <NUM_LIT> ) , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( XEXP ( operand , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) || ( GET_CODE ( XEXP ( XEXP ( operand , <NUM_LIT> ) , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( XEXP ( operand , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ) ;


<s> tree field ; for ( field = TYPE_FIELDS ( type ) ; field ; field = TREE_CHAIN ( field ) ) { if ( TREE_CODE ( field ) == FIELD_DECL ) { if ( TREE_CODE ( TREE_TYPE ( field ) ) == RECORD_TYPE ) scan_record_type ( TREE_TYPE ( field ) , intregs_p , fpregs_p , <NUM_LIT> ) ; else if ( ( FLOAT_TYPE_P ( TREE_TYPE ( field ) ) || TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) && TARGET_FPU ) * fpregs_p = <NUM_LIT> ; else * intregs_p = <NUM_LIT> ; if ( packed_p && DECL_PACKED ( field ) ) * packed_p = <NUM_LIT> ;


<s> LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( LN -> isSimple ( ) ) { SDLoc dl ( N ) ; unsigned NumBits = InVT . getScalarSizeInBits ( ) * VT . getVectorNumElements ( ) ; MVT MemVT = <STR_LIT> ( NumBits ) ; MVT LoadVT = <STR_LIT> ( MemVT , <NUM_LIT> / NumBits ) ; SDVTList Tys = DAG . getVTList ( LoadVT , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , LN -> getBasePtr ( ) } ;

SDValue VZLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , MemVT , LN -> getPointerInfo ( ) , LN -> getOriginalAlign ( ) , LN -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> void EmitConstant ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { unsigned Shift = i * <NUM_LIT> ; EmitByte ( ( Val >> Shift ) & <NUM_LIT> , OS ) ; }


return ( getGeneration ( ) >= EVERGREEN ) ;


<s> void arm_split_atomic_op ( enum rtx_code code , rtx old_out , rtx new_out , rtx mem , rtx value , rtx model_rtx , rtx cond ) { enum memmodel model = memmodel_from_int ( INTVAL ( model_rtx ) ) ; machine_mode mode = GET_MODE ( mem ) ; machine_mode wmode = ( mode == DImode ? DImode : SImode ) ; rtx_code_label * label ; bool all_low_regs , bind_old_new ; rtx x ; bool is_armv8_sync = arm_arch8 && is_mm_sync ( model ) ; bool use_acquire = TARGET_HAVE_LDACQ && aarch_mm_needs_acquire ( model_rtx ) ; bool use_release = TARGET_HAVE_LDACQ && aarch_mm_needs_release ( model_rtx ) ; if ( is_armv8_sync ) use_acquire = false ; if ( ! ( use_acquire || use_release ) ) arm_pre_atomic_barrier ( model ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; if ( new_out ) new_out = gen_lowpart ( wmode , new_out ) ;

if ( old_out ) old_out = gen_lowpart ( wmode , old_out ) ;


<s> SDValue Value = Store -> getValue ( ) ; EVT VT = Value . getValueType ( ) ; EVT ElemVT = VT . getVectorElementType ( ) ; SDValue Ptr = Store -> getBasePtr ( ) ; EVT MemEltVT = MemVT . getVectorElementType ( ) ; unsigned MemEltBits = MemEltVT . getSizeInBits ( ) ; unsigned MemNumElements = MemVT . getVectorNumElements ( ) ; unsigned PackedSize = MemVT . getStoreSizeInBits ( ) ; SDValue Mask = DAG . getConstant ( ( <NUM_LIT> << MemEltBits ) - <NUM_LIT> , DL , <STR_LIT> ) ; assert ( Value . getValueType ( ) . getScalarSizeInBits ( ) >= <NUM_LIT> ) ; SDValue PackedValue ; for ( unsigned i = <NUM_LIT> ; i < MemNumElements ; ++ i ) { SDValue Elt = DAG . getNode ( <STR_LIT> , DL , ElemVT , Value , DAG . getConstant ( i , DL , <STR_LIT> ) ) ; Elt = DAG . getZExtOrTrunc ( Elt , DL , <STR_LIT> ) ; Elt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Elt , Mask ) ; SDValue Shift = DAG . getConstant ( MemEltBits * i , DL , <STR_LIT> ) ; Elt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Elt , Shift ) ; if ( i == <NUM_LIT> ) { PackedValue = Elt ; } else {

PackedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PackedValue , Elt ) ;


if ( cum -> regs_used < NUM_ARG_REGS ) return_rtx = gen_rtx_REG ( arg . mode , FIRST_ARG_REGNO + cum -> regs_used ) ;


<s> continue ; } } else if ( const GEPOperator * GEP = dyn_cast < GEPOperator > ( V ) ) { V = GEP -> getPointerOperand ( ) -> stripPointerCasts ( ) ; continue ; } else if ( const PHINode * PN = dyn_cast < PHINode > ( V ) ) { if ( V != V2 && processed . find ( V ) != processed . end ( ) ) return NULL ; processed . insert ( PN ) ; const Value * common = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != PN -> getNumIncomingValues ( ) ; ++ i ) { const Value * pv = PN -> getIncomingValue ( i ) ; const Value * base = skipPointerTransfer ( pv , processed ) ; if ( base ) { if ( common == <NUM_LIT> ) common = base ; else if ( common != base ) return PN ; } } if ( common == <NUM_LIT> ) return PN ; V = common ; } break ; } return V ;


<s> SDValue C = CurDAG -> getTargetConstant ( - <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * R = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , C ) ; SDNode * T = CurDAG -> getMachineNode ( <STR_LIT> , dl , ResTy , N -> getOperand ( <NUM_LIT> ) , SDValue ( R , <NUM_LIT> ) ) ; ReplaceNode ( N , T ) ;


<s> MinReservedArea = EnsureStackAlignment ( Subtarget . getFrameLowering ( ) , MinReservedArea ) ; FuncInfo -> setMinReservedArea ( MinReservedArea ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; if ( isVarArg ) { static const MCPhysReg GPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const unsigned NumGPArgRegs = array_lengthof ( GPArgRegs ) ; static const MCPhysReg FPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned NumFPArgRegs = array_lengthof ( FPArgRegs ) ; if ( useSoftFloat ( ) || hasSPE ( ) ) NumFPArgRegs = <NUM_LIT> ; FuncInfo -> setVarArgsNumGPR ( CCInfo . getFirstUnallocated ( GPArgRegs ) ) ; FuncInfo -> setVarArgsNumFPR ( CCInfo . getFirstUnallocated ( FPArgRegs ) ) ; int Depth = NumGPArgRegs * PtrVT . getSizeInBits ( ) / <NUM_LIT> + NumFPArgRegs * MVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> ; FuncInfo -> setVarArgsStackOffset ( MFI . CreateFixedObject ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ) ; FuncInfo -> setVarArgsFrameIndex ( MFI . CreateStackObject ( Depth , <NUM_LIT> , false ) ) ; SDValue FIN = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; for ( unsigned GPRIndex = <NUM_LIT> ; GPRIndex != NumGPArgRegs ; ++ GPRIndex ) { unsigned VReg = MF . getRegInfo ( ) . getLiveInVirtReg ( GPArgRegs [ GPRIndex ] ) ; if ( ! VReg ) VReg = MF . addLiveIn ( GPArgRegs [ GPRIndex ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , PtrVT ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) ) ; MemOps . push_back ( Store ) ; SDValue PtrOff = DAG . getConstant ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , dl , PtrVT ) ; FIN = DAG . getNode ( <STR_LIT> , dl , PtrOff . getValueType ( ) , FIN , PtrOff ) ; } for ( unsigned FPRIndex = <NUM_LIT> ; FPRIndex != NumFPArgRegs ; ++ FPRIndex ) { unsigned VReg = MF . getRegInfo ( ) . getLiveInVirtReg ( FPArgRegs [ FPRIndex ] ) ; if ( ! VReg ) VReg = MF . addLiveIn ( FPArgRegs [ FPRIndex ] , & <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Val . getValue ( <NUM_LIT> ) , dl , Val , FIN , MachinePointerInfo ( ) ) ; MemOps . push_back ( Store ) ; SDValue PtrOff = DAG . getConstant ( MVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> , dl , PtrVT ) ;


<s> return IDAlu ; } switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return IDAlu ; default : return IDOther ; }


<s> if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ;


<s> const TargetInstrDesc & TID = MI . getDesc ( ) ; if ( TID . Opcode == <STR_LIT> ) abort ( ) ; unsigned Binary = getBinaryCodeForInstr ( MI ) ;

Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ;


<s> unsigned Reg = Op . getReg ( ) ; printRegName ( O , Reg ) ; } else if ( Op . isImm ( ) ) { O << markup ( <STR_LIT> ) << formatImm ( Op . getImm ( ) ) << markup ( <STR_LIT> ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ;

Op . getExpr ( ) -> print ( O , & MAI ) ;


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * N ) { DEBUG ( errs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ;


<s> if ( fndecl == NULL_TREE ) { if ( old_tree != target_option_current_node ) ix86_reset_previous_fndecl ( ) ; return ; } ix86_set_func_type ( fndecl ) ; ix86_set_indirect_branch_type ( fndecl ) ; tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; if ( old_tree != new_tree ) { cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; } ix86_previous_fndecl = fndecl ; static bool prev_no_caller_saved_registers ; if ( TARGET_64BIT && ( call_used_regs [ SI_REG ] == ( cfun -> machine -> call_abi == MS_ABI ) ) ) reinit_regs ( ) ; else if ( prev_no_caller_saved_registers != cfun -> machine -> no_caller_saved_registers ) reinit_regs ( ) ; if ( cfun -> machine -> func_type != TYPE_NORMAL || cfun -> machine -> no_caller_saved_registers ) { const char * isa ; if ( TARGET_SSE ) isa = <STR_LIT> ; else if ( TARGET_MMX ) isa = <STR_LIT> ; else if ( TARGET_80387 ) isa = <STR_LIT> ; else isa = NULL ; if ( isa != NULL ) {

if ( cfun -> machine -> func_type != TYPE_NORMAL ) sorry ( cfun -> machine -> func_type == TYPE_EXCEPTION ? G_ ( <STR_LIT> <STR_LIT> ) : G_ ( <STR_LIT> <STR_LIT> ) , isa ) ;


<s> unsigned SplatBits = APSplatBits . getZExtValue ( ) ; int32_t SextVal = ( ( int32_t ) ( SplatBits << ( <NUM_LIT> - SplatBitSize ) ) >> ( <NUM_LIT> - SplatBitSize ) ) ; return createSplat ( DAG , dl , VT , DAG . getConstant ( SextVal , dl , <STR_LIT> ) ) ; } if ( VT . getSimpleVT ( ) == <STR_LIT> ) { SDValue V0 = BVN -> getOperand ( <NUM_LIT> ) ; SDValue V1 = BVN -> getOperand ( <NUM_LIT> ) ; if ( V0 . getOpcode ( ) == <STR_LIT> ) V0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; if ( V1 . getOpcode ( ) == <STR_LIT> ) V1 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; ConstantSDNode * C0 = dyn_cast < ConstantSDNode > ( V0 ) ; ConstantSDNode * C1 = dyn_cast < ConstantSDNode > ( V1 ) ; if ( ! C0 || ! C1 ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V0 ) ; if ( isInt < <NUM_LIT> > ( C0 -> getSExtValue ( ) ) || isInt < <NUM_LIT> > ( C1 -> getSExtValue ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V0 ) ; } if ( VT . getSimpleVT ( ) == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> , e = NElts ; i != e ; ++ i ) { if ( BVN -> getOperand ( i ) . getOpcode ( ) == <STR_LIT> ) continue ; ConstantSDNode * Cst = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( i ) ) ; if ( ! Cst ) { SDValue pack = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BVN -> getOperand ( <NUM_LIT> ) , BVN -> getOperand ( <NUM_LIT> ) ) ; return DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , pack ) ; } } } uint64_t Res = <NUM_LIT> ; unsigned EltSize = Size / NElts ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> for ( i = FIRST_PARM_REG ; i < FIRST_PARM_REG + NPARM_REGS ( SImode ) ; i ++ ) CLEAR_HARD_REG_BIT ( temps , i ) ; if ( cfun -> static_chain_decl != NULL ) CLEAR_HARD_REG_BIT ( temps , STATIC_CHAIN_REGNUM ) ; } temp = scavenge_reg ( & temps ) ; } if ( temp < <NUM_LIT> && live_regs_mask ) temp = scavenge_reg ( live_regs_mask ) ; if ( temp < <NUM_LIT> ) { rtx adj_reg , tmp_reg , mem ; gcc_assert ( ! TARGET_SHMEDIA && epilogue_p ) ; gcc_assert ( ! fixed_regs [ <NUM_LIT> ] && ! fixed_regs [ <NUM_LIT> ] && ! global_regs [ <NUM_LIT> ] && ! global_regs [ <NUM_LIT> ] ) ; adj_reg = gen_rtx_REG ( GET_MODE ( reg ) , <NUM_LIT> ) ; tmp_reg = gen_rtx_REG ( GET_MODE ( reg ) , <NUM_LIT> ) ; emit_move_insn ( gen_tmp_stack_mem ( Pmode , reg ) , adj_reg ) ; emit_insn ( GEN_MOV ( adj_reg , GEN_INT ( size ) ) ) ; emit_insn ( GEN_ADD3 ( adj_reg , adj_reg , reg ) ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , adj_reg ) ) ; emit_move_insn ( mem , tmp_reg ) ; emit_move_insn ( tmp_reg , gen_tmp_stack_mem ( Pmode , reg ) ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , adj_reg ) ) ; emit_move_insn ( mem , tmp_reg ) ; emit_move_insn ( reg , adj_reg ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_POST_INC ( Pmode , reg ) ) ; emit_move_insn ( adj_reg , mem ) ; mem = gen_tmp_stack_mem ( Pmode , gen_rtx_POST_INC ( Pmode , reg ) ) ; emit_move_insn ( tmp_reg , mem ) ; return ; } const_reg = gen_rtx_REG ( GET_MODE ( reg ) , temp ) ; if ( size < <NUM_LIT> ) { emit_insn ( GEN_MOV ( const_reg , GEN_INT ( - size ) ) ) ; insn = emit_fn ( GEN_SUB3 ( reg , reg , const_reg ) ) ; } else { emit_insn ( GEN_MOV ( const_reg , GEN_INT ( size ) ) ) ; insn = emit_fn ( GEN_ADD3 ( reg , reg , const_reg ) ) ; } if ( ! epilogue_p ) REG_NOTES ( insn ) = ( gen_rtx_EXPR_LIST ( REG_FRAME_RELATED_EXPR , gen_rtx_SET ( VOIDmode , reg , gen_rtx_PLUS ( SImode , reg , GEN_INT ( size ) ) ) , REG_NOTES ( insn ) ) ) ;


<s> hi = XEXP ( hi , <NUM_LIT> ) ; if ( GET_CODE ( lo ) == POST_INC ) return rtx_equal_p ( lo , hi ) ; switch ( GET_CODE ( lo ) ) { case REG : case SYMBOL_REF : lo_offset = <NUM_LIT> ; break ; case CONST : lo = XEXP ( lo , <NUM_LIT> ) ; case PLUS : if ( ! CONST_INT_P ( XEXP ( lo , <NUM_LIT> ) ) ) return false ; lo_offset = INTVAL ( XEXP ( lo , <NUM_LIT> ) ) ; lo = XEXP ( lo , <NUM_LIT> ) ; break ; default : return false ; } switch ( GET_CODE ( hi ) ) { case REG : case SYMBOL_REF : hi_offset = <NUM_LIT> ; break ; case CONST : hi = XEXP ( hi , <NUM_LIT> ) ; case PLUS : if ( ! CONST_INT_P ( XEXP ( hi , <NUM_LIT> ) ) ) return false ; hi_offset = INTVAL ( XEXP ( hi , <NUM_LIT> ) ) ; hi = XEXP ( hi , <NUM_LIT> ) ; break ; default : return false ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RLocs ; SDValue Flag ; CCState CCInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RLocs . size ( ) ; ++ i ) if ( RLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RLocs [ i ] . getLocReg ( ) ) ; } for ( unsigned i = <NUM_LIT> ; i != RLocs . size ( ) ; ++ i ) { CCValAssign & VA = RLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


<s> assert ( Is32BitInt && <STR_LIT> ) ; Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; UseOffset = ( ( Addr . Offset & <NUM_LIT> ) == <NUM_LIT> ) ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } unsigned IndexReg = <NUM_LIT> ; <ISA_LIT>SimplifyAddress ( Addr , VT , UseOffset , IndexReg ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) ) . addReg ( SrcReg ) . addReg ( Addr . Base . Reg ) . addReg ( IndexReg ) ;


<s> SmallString < <NUM_LIT> > str ; raw_svector_ostream OS ( str ) ; OS << <STR_LIT> ; OS << ST . getABIOptionString ( ) << <STR_LIT> ; OS << <STR_LIT> ; OS << <STR_LIT> ;


<s> return TLI -> isOperationLegal ( IsSigned ? <STR_LIT> : <STR_LIT> , VT ) ;


<s> MachineFunction * MF = MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; const DebugLoc & DL = MBB . findDebugLoc ( MI ) ; unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , Size , Align ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ;

FrameInfo . setStackID ( FrameIndex , <STR_LIT> ) ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectHvxVAlign ( SDNode * N ) {

HvxSelector ( * this , * CurDAG ) . selectVAlign ( N ) ;


<s> else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> ContBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( TrapBB ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( TrapBB ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TrapBB ) ; AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( ContBB ) ) ; MBB -> addSuccessor ( ContBB ) ; MI -> eraseFromParent ( ) ; return ContBB ;


<s> unsigned Mask2 = C -> getZExtValue ( ) ; if ( <STR_LIT> ( Mask ) && <STR_LIT> ( ~ Mask2 ) && ( CountPopulation_32 ( Mask ) == CountPopulation_32 ( ~ Mask2 ) ) ) { if ( Subtarget -> hasT2ExtractPack ( ) && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) return SDValue ( ) ; unsigned lsb = CountTrailingZeros_32 ( Mask2 ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( lsb , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , Res , DAG . getConstant ( Mask , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; } else if ( <STR_LIT> ( ~ Mask ) && <STR_LIT> ( Mask2 ) && ( CountPopulation_32 ( ~ Mask ) == CountPopulation_32 ( Mask2 ) ) ) { if ( Subtarget -> hasT2ExtractPack ( ) && ( Mask2 == <NUM_LIT> || Mask2 == <NUM_LIT> ) ) return SDValue ( ) ; unsigned lsb = CountTrailingZeros_32 ( Mask ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( lsb , <STR_LIT> ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , Res , DAG . getConstant ( Mask2 , <STR_LIT> ) ) ; DCI . CombineTo ( N , Res , false ) ; } } return SDValue ( ) ;


<s> Changed = true ; unsigned NewReg = MRI . createVirtualRegister ( MRI . getRegClass ( OldReg ) ) ; MO . setReg ( NewReg ) ; MO . setIsDead ( ) ; MFI . stackifyVReg ( NewReg ) ;


<s> void <ISA_LIT>InstPrinter :: printCallOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const {


<s> Inst . addOperand ( MCOperand :: CreateImm ( ~ CE -> getValue ( ) ) ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) ) ;


<s> MCWinCOFFStreamer :: finishImpl ( ) ;


<s> std :: string CPU = <STR_LIT> ; ParseSubtargetFeatures ( FS , CPU ) ;


<s> Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getBitcast ( VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) { if ( Zeroable [ i ] ) continue ; SDValue Current = Op -> getOperand ( i ) ; SDValue SrcVector = Current -> getOperand ( <NUM_LIT> ) ; if ( ! V1 . getNode ( ) ) V1 = SrcVector ; CanFold = SrcVector == V1 && cast < ConstantSDNode > ( Current . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) == i ; } if ( ! CanFold ) return SDValue ( ) ; assert ( V1 . getNode ( ) && <STR_LIT> ) ; if ( V1 . getSimpleValueType ( ) != <STR_LIT> ) V1 = DAG . getBitcast ( <STR_LIT> , V1 ) ; if ( V2 . getSimpleValueType ( ) != <STR_LIT> ) V2 = DAG . getBitcast ( <STR_LIT> , V2 ) ; unsigned ZMask = Zeroable . to_ulong ( ) ; unsigned InsertPSMask = EltMaskIdx << <NUM_LIT> | EltIdx << <NUM_LIT> | ZMask ; assert ( ( InsertPSMask & ~ <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ;


<s> return ( ValVT == <STR_LIT> || ValVT == <STR_LIT> ) ? ValVT . getStoreSize ( ) : VA . getLocVT ( ) . getStoreSize ( ) ;


<s> Opc = <STR_LIT> ; } else if ( <STR_LIT> ( CC ) ) { if ( isInt32Immediate ( RHS , Imm ) && isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } else { short SImm ; if ( isIntS16Immediate ( RHS , SImm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( ( int ) SImm & <NUM_LIT> ) ) , <NUM_LIT> ) ; Opc = <STR_LIT> ; } } else if ( LHS . getValueType ( ) == <STR_LIT> ) { uint64_t Imm ; if ( CC == <STR_LIT> || CC == <STR_LIT> ) { if ( isInt64Immediate ( RHS . getNode ( ) , Imm ) ) { if ( isUInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isInt < <NUM_LIT> > ( Imm ) ) return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI32Imm ( Imm & <NUM_LIT> ) ) , <NUM_LIT> ) ; if ( isUInt < <NUM_LIT> > ( Imm ) ) {

SDValue Xor ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , LHS , getI64Imm ( Imm >> <NUM_LIT> ) ) , <NUM_LIT> ) ;


<s> bool missingFeature ( llvm :: SMLoc const & Loc , uint64_t const & ) {


<s> void <ISA_LIT>TargetStreamer :: emit<ISA_LIT>WinCFISaveLR ( unsigned Offset ) {


<s> if ( STUses && ! isMask_32 ( STUses ) ) MI . emitError ( <STR_LIT> ) ; unsigned NumSTUses = countTrailingOnes ( STUses ) ; if ( STDefs && ! isMask_32 ( STDefs ) ) { MI . emitError ( <STR_LIT> ) ; STDefs = NextPowerOf2 ( STDefs ) - <NUM_LIT> ; } unsigned NumSTDefs = countTrailingOnes ( STDefs ) ; if ( STClobbers && ! isMask_32 ( STDefs | STClobbers ) ) MI . emitError ( <STR_LIT> ) ; unsigned STPopped = STUses & ( STDefs | STClobbers ) ; if ( STPopped && ! isMask_32 ( STPopped ) ) MI . emitError ( <STR_LIT> ) ; unsigned NumSTPopped = countTrailingOnes ( STPopped ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NumSTUses << <STR_LIT> << NumSTPopped << <STR_LIT> << NumSTDefs << <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> , E = MI . getNumOperands ( ) ; I < E ; ++ I ) if ( FRegIdx . count ( I ) ) { assert ( ( <NUM_LIT> << getFPReg ( MI . getOperand ( I ) ) & STDefs ) == <NUM_LIT> && <STR_LIT> ) ; } unsigned FPKills = ( ( <NUM_LIT> << NumFPRegs ) - <NUM_LIT> ) & ~ <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; unsigned FPReg = getFPReg ( Op ) ; if ( Op . isUse ( ) && Op . isKill ( ) ) FPKills |= <NUM_LIT> << FPReg ; } FPKills &= ~ ( STDefs | STClobbers ) ; unsigned char STUsesArray [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumSTUses ; ++ I ) STUsesArray [ I ] = I ; shuffleStackTop ( STUsesArray , NumSTUses , Inst ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; dumpStack ( ) ; } ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI . getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; unsigned FPReg = getFPReg ( Op ) ;

if ( FRegIdx . count ( i ) ) Op . setReg ( getSTReg ( FPReg ) ) ;


<s> if ( GET_MODE_UNIT_SIZE ( d -> vmode ) >= <NUM_LIT> ) return false ; if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else if ( d -> perm [ <NUM_LIT> ] == <NUM_LIT> ) odd = <NUM_LIT> ; else return false ; mask = ( d -> one_vector_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; i += <NUM_LIT> ) { if ( d -> perm [ i ] != i + odd ) return false ; if ( d -> perm [ i + <NUM_LIT> ] != ( ( i + nelt + odd ) & mask ) ) return false ; } if ( d -> testing_p ) return true ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vtrnv16qi_internal ; break ; case V8QImode : gen = gen_neon_vtrnv8qi_internal ; break ; case V8HImode : gen = gen_neon_vtrnv8hi_internal ; break ; case V4HImode : gen = gen_neon_vtrnv4hi_internal ; break ; case V4SImode : gen = gen_neon_vtrnv4si_internal ; break ;

case V2SImode : gen = gen_neon_vtrnv2si_internal ; break ;


<s> auto I = LoopEnterers . find ( LoopEntry ) ; assert ( I != LoopEnterers . end ( ) ) ; return I -> second ;


<s> std :: pair < int , MVT > SrcLT = TLI . getTypeLegalizationCost ( DL , SrcTy ) ; std :: pair < int , MVT > DstLT = TLI . getTypeLegalizationCost ( DL , DstTy ) ;

return std :: max ( SrcLT . first , DstLT . first ) + FloatFactor * ( SrcN + DstN ) ;


<s> return ( VersionMajor >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;


<s> if ( isSSetReg ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkSetRegHazards ( MI ) ) ; if ( isRFE ( MI -> getOpcode ( ) ) ) return std :: max ( WaitStates , checkRFEHazards ( MI ) ) ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) ) return std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) ) return std :: max ( WaitStates , checkReadM0Hazards ( MI ) ) ; if ( <ISA_LIT>InstrInfo :: isMAI ( * MI ) ) return std :: max ( WaitStates , checkMAIHazards ( MI ) ) ;

if ( MI -> mayLoadOrStore ( ) ) return std :: max ( WaitStates , checkMAILdStHazards ( MI ) ) ;


<s> LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return Op ; case <STR_LIT> : case <STR_LIT> : return Op ;

case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ;


<s> Operands . push_back ( std :: move ( Dst ) ) ; Operands . push_back ( std :: move ( Src ) ) ; } else { Operands . push_back ( std :: move ( Src ) ) ; Operands . push_back ( std :: move ( Dst ) ) ; }


<s> return __builtin_ia32_subsh_mask ( __B , __C , _mm_setzero_ph ( ) , __A ) ;


<s> avr_pass_pre_proep ( gcc :: context * ctxt , const char * name ) : rtl_opt_pass ( avr_pass_data_pre_proep , ctxt ) {


<s> void <ISA_LIT>InstPrinter :: printCPSIMod ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {

const MCOperand & Op = MI -> getOperand ( OpNum ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned imm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Q = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Q ) { if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ;


<s> const TargetRegisterClass * TRC = isThumb2 ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned storesuccess = MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; if ( isThumb2 ) { AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( destlo , RegState :: Define ) . addReg ( desthi , RegState :: Define ) . addReg ( ptr ) ) ; } else { unsigned GPRPair0 = MRI . createVirtualRegister ( & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( GPRPair0 , RegState :: Define ) . addReg ( ptr ) ) ; BuildMI ( BB , dl , TII -> get ( TargetOpcode :: COPY ) , destlo ) . addReg ( GPRPair0 , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( BB , dl , TII -> get ( TargetOpcode :: COPY ) , desthi ) . addReg ( GPRPair0 , <NUM_LIT> , <STR_LIT> ) ; } unsigned StoreLo , StoreHi ; if ( IsCmpxchg ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( i == <NUM_LIT> ? destlo : desthi ) . addReg ( i == <NUM_LIT> ? vallo : valhi ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addMBB ( exitMBB ) . addImm ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BB -> addSuccessor ( exitMBB ) ; BB -> addSuccessor ( i == <NUM_LIT> ? contBB : cont2BB ) ; BB = ( i == <NUM_LIT> ? contBB : cont2BB ) ; } StoreLo = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; StoreHi = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( Op1 ) { unsigned tmpRegLo = MRI . createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( Op1 ) , tmpRegLo ) . addReg ( destlo ) . addReg ( vallo ) ) . addReg ( NeedsCarry ? <STR_LIT> : <NUM_LIT> , getDefRegState ( NeedsCarry ) ) ; unsigned tmpRegHi = MRI . createVirtualRegister ( TRC ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( Op2 ) , tmpRegHi ) . addReg ( desthi ) . addReg ( valhi ) ) . addReg ( IsMinMax ? <STR_LIT> : <NUM_LIT> , getDefRegState ( IsMinMax ) ) ;


<s> SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Opc , <ISA_LIT>CC = ~ <NUM_LIT> ; LookThroughSetCC ( LHS , RHS , CC , <ISA_LIT>CC ) ; SDValue CompareFlag ; if ( LHS . getValueType ( ) == <STR_LIT> ) { std :: vector < EVT > VTs ; VTs . push_back ( LHS . getValueType ( ) ) ; VTs . push_back ( <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { LHS , RHS } ; CompareFlag = DAG . getNode ( <STR_LIT> , dl , VTs , Ops , <NUM_LIT> ) . getValue ( <NUM_LIT> ) ; Opc = <STR_LIT> ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = IntCondCCodeToICC ( CC ) ; } else { CompareFlag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ; Opc = <STR_LIT> ; if ( <ISA_LIT>CC == ~ <NUM_LIT> ) <ISA_LIT>CC = FPCondCCodeToFCC ( CC ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) {

return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ;


<s> bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { InstOffset = BlockToInstOffset [ & MBB ] ; MachineBasicBlock :: iterator MII = MBB . begin ( ) ; MachineBasicBlock :: iterator MIE = MBB . end ( ) ; while ( MII != MIE ) { InstOffset += HII -> getSize ( & * MII ) ; if ( MII -> isDebugValue ( ) ) { ++ MII ; continue ; } if ( isHardwareLoop ( MII ) ) { assert ( MII -> getOperand ( <NUM_LIT> ) . isMBB ( ) && <STR_LIT> ) ; int diff = InstOffset - BlockToInstOffset [ MII -> getOperand ( <NUM_LIT> ) . getMBB ( ) ] ; if ( ( unsigned ) abs ( diff ) > MaxLoopRange ) { useExtLoopInstr ( MF , MII ) ; MII = MBB . erase ( MII ) ; Changed = true ;


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; if ( RegNo % <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; const MCRegisterInfo * RI = Dis -> getContext ( ) . getRegisterInfo ( ) ; MCRegister Reg = RI -> getMatchingSuperReg ( <STR_LIT> + RegNo , <STR_LIT> , & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ) ;

Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> void <ISA_LIT>LowerControlFlowPass :: Skip ( MachineInstr & From , MachineOperand & To ) { if ( ! shouldSkip ( * From . getParent ( ) -> succ_begin ( ) , To . getMBB ( ) ) ) return ;


<s> return ( ( int ) ( spu_extract ( spu_gather ( spu_cmpgt ( a , b ) ) , <NUM_LIT> ) == <NUM_LIT> ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: performMulLoHi24Combine ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; if ( simplifyI24 ( N , <NUM_LIT> , DCI ) || simplifyI24 ( N , <NUM_LIT> , DCI ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; bool Signed = ( N -> getOpcode ( ) == <STR_LIT> ) ; unsigned MulLoOpc = Signed ? <STR_LIT> : <STR_LIT> ; unsigned MulHiOpc = Signed ? <STR_LIT> : <STR_LIT> ;


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( Subtarget . is<ISA_LIT>64 ( ) ) { return <STR_LIT> ; } else { return <STR_LIT> ; }


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) ;


<s> explicit <ISA_LIT>DagToDagISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level optLevel ) : SelectionDAGISel ( tm , optLevel ) , Subtarget ( * tm . getSubtargetImpl ( ) ) {


<s> void visitCallInst ( CallInst & I ) { if ( ! I . getCalledFunction ( ) ) return ; StringRef Name = I . getCalledFunction ( ) -> getName ( ) ; if ( Name == <STR_LIT> ) { ReplaceTexIntrinsic ( I , false , TexSign , <STR_LIT> , <STR_LIT> ) ; return ; } if ( Name == <STR_LIT> ) { ReplaceTexIntrinsic ( I , true , TexSign , <STR_LIT> , <STR_LIT> ) ; return ; } if ( Name == <STR_LIT> ) { ReplaceTexIntrinsic ( I , true , TexSign , <STR_LIT> , <STR_LIT> ) ; return ; } if ( Name == <STR_LIT> ) { ReplaceTXF ( I ) ; return ; } if ( Name == <STR_LIT> ) { ReplaceTexIntrinsic ( I , false , TexQSign , <STR_LIT> , <STR_LIT> ) ; return ; } if ( Name == <STR_LIT> ) { ReplaceTexIntrinsic ( I , false , TexSign , <STR_LIT> , <STR_LIT> ) ; return ; } if ( Name == <STR_LIT> ) { ReplaceTexIntrinsic ( I , false , TexSign , <STR_LIT> , <STR_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isPredicable ( const MachineInstr & MI ) const { if ( ! MI . getDesc ( ) . isPredicable ( ) ) return false ; if ( MI . isCall ( ) || isTailCall ( MI ) ) { if ( ! Subtarget . usePredicatedCalls ( ) ) return false ; } if ( ! Subtarget . hasV62TOps ( ) ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineDominatorTree > ( ) ;


<s> MCA . registerSection ( * Sec ) ; Sec -> setAlignment ( Align ( <NUM_LIT> ) ) ; OS . SwitchSection ( Sec ) ; OS << ABIFlagsSection ;


<s> else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O << formatHex ( ( uint64_t ) Address ) ; } else { O << * Op . getExpr ( ) ; }


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> ( a ) ) ; return ( int ) d ;


<s> MCSymbol * Sym = getSymbol ( & F ) ; getTargetStreamer ( ) -> emitIndirectFunctionType ( Sym , Params , Results ) ; if ( TM . getTargetTriple ( ) . isOSBinFormatWasm ( ) && F . hasFnAttribute ( <STR_LIT> ) ) { MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Sym ) ; StringRef Name = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; getTargetStreamer ( ) -> emitImportModule ( WasmSym , Name ) ; } } } for ( const auto & G : M . globals ( ) ) { if ( ! G . hasInitializer ( ) && G . hasExternalLinkage ( ) ) { if ( G . getValueType ( ) -> isSized ( ) ) { uint16_t Size = M . getDataLayout ( ) . getTypeAllocSize ( G . getValueType ( ) ) ; OutStreamer -> emitELFSize ( getSymbol ( & G ) , MCConstantExpr :: create ( Size , OutContext ) ) ; } } } if ( const NamedMDNode * Named = M . getNamedMetadata ( <STR_LIT> ) ) { for ( const Metadata * MD : Named -> operands ( ) ) { const MDTuple * Tuple = dyn_cast < MDTuple > ( MD ) ; if ( ! Tuple || Tuple -> getNumOperands ( ) != <NUM_LIT> ) continue ;

const MDString * Name = dyn_cast < MDString > ( Tuple -> getOperand ( <NUM_LIT> ) ) ;


<s> bool hasExtXfexpauxvecalthalf ( ) const { return HasExtXfexpauxvecalthalf ;


<s> Src0 = ScalarToVector -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } unsigned Opcode ; if ( DstSize == <NUM_LIT> && VecTy . getScalarSizeInBits ( ) == <NUM_LIT> ) Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstSize == <NUM_LIT> && VecTy . getScalarSizeInBits ( ) == <NUM_LIT> ) Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstSize == <NUM_LIT> && VecTy . getScalarSizeInBits ( ) == <NUM_LIT> ) Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstSize == <NUM_LIT> && VecTy . getScalarSizeInBits ( ) == <NUM_LIT> ) Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstSize == <NUM_LIT> && VecTy . getScalarSizeInBits ( ) == <NUM_LIT> ) Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; MachineInstr * ExtI = nullptr ; if ( DstSize == <NUM_LIT> && ! IsSigned ) { Register NewReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . buildInstr ( Opcode , { NewReg } , { Src0 } ) . addImm ( Lane ) ; ExtI = MIB . buildInstr ( <STR_LIT> , { DefReg } , { } ) . addImm ( <NUM_LIT> ) . addUse ( NewReg ) . addImm ( <STR_LIT> ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else ExtI = MIB . buildInstr ( Opcode , { DefReg } , { Src0 } ) . addImm ( Lane ) ; constrainSelectedInstRegOperands ( * ExtI , TII , TRI , RBI ) ; MI . eraseFromParent ( ) ; return true ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . End -> eraseFromParent ( ) ; LoLoop . Dec -> eraseFromParent ( ) ; return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec , true ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else {

LoLoop . Start = ExpandLoopStart ( LoLoop ) ;


<s> assert ( Cond . empty ( ) && ! FBB && TBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ;


<s> static hashval_t hash ( const char * str ) { return htab_hash_string ( str ) ;


<s> MachineOperand & Row = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & Col = MI . getOperand ( <NUM_LIT> ) ; unsigned TMMIdx = MI . getOperand ( <NUM_LIT> ) . getReg ( ) - <STR_LIT> ; ShapeInfos . push_back ( { TMMIdx , ShapeT ( & Row , & Col ) } ) ; } else { int SS = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; for ( auto & ShapeInfo : ShapeInfos ) { DebugLoc DL ; unsigned TMMIdx = ShapeInfo . first ; Register RowReg = ShapeInfo . second . getRow ( ) -> getReg ( ) ; Register ColReg = ShapeInfo . second . getCol ( ) -> getReg ( ) ; int RowOffset = <NUM_LIT> + TMMIdx ; int ColOffset = <NUM_LIT> + TMMIdx * <NUM_LIT> ; Register SubRowReg = TRI -> getSubReg ( RowReg , <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , SubRowReg ) ; MachineInstrBuilder StoreRow = BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addFrameReference ( StoreRow , SS , RowOffset ) . addReg ( SubRowReg ) ; MachineInstrBuilder StoreCol = BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addFrameReference ( StoreCol , SS , ColOffset ) . addReg ( ColReg ) ; }


<s> void <ISA_LIT>SchedStrategy :: initialize ( ScheduleDAGMI * dag ) { assert ( dag -> hasVRegLiveness ( ) && <STR_LIT> ) ; DAG = static_cast < ScheduleDAGMILive * > ( dag ) ; const <ISA_LIT>Subtarget & ST = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( DAG -> TII ) ; TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG -> TRI ) ; VLIW5 = ! ST . hasCaymanISA ( ) ; MRI = & DAG -> MRI ; CurInstKind = IDOther ; CurEmitted = <NUM_LIT> ; OccupedSlotsMask = <NUM_LIT> ;

InstKindLimit [ IDAlu ] = TII -> getMaxAlusPerClause ( ) ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; if ( NumBytes >= ALLOCFRAME_MAX ) { BuildMI ( MBB , InsertPt , dl , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , InsertPt , dl , TII . get ( <STR_LIT> ) , HEXAGON_RESERVED_REG_1 ) . addImm ( NumBytes ) ; BuildMI ( MBB , InsertPt , dl , TII . get ( <STR_LIT> ) , QRI -> getStackRegister ( ) ) . addReg ( QRI -> getStackRegister ( ) ) . addReg ( HEXAGON_RESERVED_REG_1 ) ; } else {

BuildMI ( MBB , InsertPt , dl , TII . get ( <STR_LIT> ) ) . addImm ( NumBytes ) ;


<s> static tree ix86_vector_shift_count ( tree arg1 ) { if ( tree_fits_uhwi_p ( arg1 ) ) return arg1 ; else if ( TREE_CODE ( arg1 ) == VECTOR_CST && CHAR_BIT == <NUM_LIT> ) {


<s> void addConstpoolOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> if ( OldMI -> registerDefIsDead ( <STR_LIT> ) ) {

MachineOperand * CCDef = NewMI -> findRegisterDefOperand ( <STR_LIT> ) ;


<s> MFI . RemoveStackObject ( R . first ) ; SGPRToVGPRSpills . erase ( R . first ) ; } } bool HaveSGPRToMemory = false ; if ( ResetSGPRSpillStackIDs ) { for ( int i = MFI . getObjectIndexBegin ( ) , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( i != FramePointerSaveIndex && i != BasePointerSaveIndex ) { if ( MFI . getStackID ( i ) == TargetStackID :: SGPRSpill ) { MFI . setStackID ( i , TargetStackID :: Default ) ; HaveSGPRToMemory = true ; } } } } for ( auto & R : VGPRToAGPRSpills ) { if ( R . second . IsDead ) MFI . RemoveStackObject ( R . first ) ; } return HaveSGPRToMemory ;


<s> SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ; if ( UseGOT_PREL ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return Result ; } else if ( Subtarget -> isROPI ( ) && IsRO ) { SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; return Result ; } else if ( Subtarget -> isRWPI ( ) && ! IsRO ) { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue G = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; SDValue SB = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ;

SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , SB , G ) ;


<s> const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL , getContext ( ) ) ;

return MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , getContext ( ) ) ;


<s> case FusionFeature :: FK_LoadCmp1 : case FusionFeature :: FK_LoadCmp2 : { const MachineOperand & BT = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! BT . isReg ( ) || ( ! Register :: isVirtualRegister ( BT . getReg ( ) ) && BT . getReg ( ) != <STR_LIT> ) ) return false ; if ( SecondMI . getOpcode ( ) == <STR_LIT> && matchingImmOps ( SecondMI , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> ) ) return true ; return matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) ; } case FusionFeature :: FK_LoadCmp3 : { const MachineOperand & BT = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! BT . isReg ( ) || ( ! Register :: isVirtualRegister ( BT . getReg ( ) ) && BT . getReg ( ) != <STR_LIT> ) ) return false ; return matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> ) ; } case FusionFeature :: FK_ZeroMoveCTR : return ( FirstMI . getOpcode ( ) != <STR_LIT> && FirstMI . getOpcode ( ) != <STR_LIT> ) || matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_ZeroMoveLR : return ( FirstMI . getOpcode ( ) != <STR_LIT> && FirstMI . getOpcode ( ) != <STR_LIT> ) || matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_AddisAddi : { const MachineOperand & RA = FirstMI . getOperand ( <NUM_LIT> ) ; const MachineOperand & SI = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! SI . isImm ( ) || ! RA . isReg ( ) ) return false ; if ( RA . getReg ( ) == <STR_LIT> || RA . getReg ( ) == <STR_LIT> ) return false ; return SignExtend64 ( SI . getImm ( ) , <NUM_LIT> ) >= <NUM_LIT> ; }


<s> const auto & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const auto Occ = Regions . front ( ) -> MaxPressure . getOccupancy ( ST ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TargetOcc << <STR_LIT> << Occ << '\n' ) ; auto NewOcc = TargetOcc ; for ( auto R : Regions ) { if ( R -> MaxPressure . getOccupancy ( ST ) >= NewOcc ) break ; LLVM_DEBUG ( printRegion ( dbgs ( ) , R -> Begin , R -> End , LIS , <NUM_LIT> ) ; printLivenessInfo ( dbgs ( ) , R -> Begin , R -> End , LIS ) ) ; BuildDAG DAG ( * R , * this ) ; const auto MinSchedule = makeMinRegSchedule ( DAG . getTopRoots ( ) , * this ) ; const auto MaxRP = getSchedulePressure ( * R , MinSchedule ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; printSchedRP ( dbgs ( ) , R -> MaxPressure , MaxRP ) ) ; NewOcc = std :: min ( NewOcc , MaxRP . getOccupancy ( ST ) ) ; if ( NewOcc <= Occ ) break ; setBestSchedule ( * R , MinSchedule , MaxRP ) ; }

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NewOcc << <STR_LIT> << Occ << '\n' ) ;


<s> if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Subtarget -> hasFullFP16 ( ) ) ) && DstVT == SatVT && ( DstVT == <STR_LIT> || DstVT == <STR_LIT> ) ) return DAG . getNode ( Op . getOpcode ( ) , DL , DstVT , SrcVal , DAG . getValueType ( DstVT ) ) ; if ( DstWidth < SatWidth ) return SDValue ( ) ; SDValue NativeCvt = DAG . getNode ( Op . getOpcode ( ) , DL , DstVT , SrcVal , DAG . getValueType ( DstVT ) ) ; SDValue Sat ; if ( Op . getOpcode ( ) == <STR_LIT> ) { SDValue MinC = DAG . getConstant ( APInt :: getSignedMaxValue ( SatWidth ) . sext ( DstWidth ) , DL , DstVT ) ; SDValue Min = DAG . getNode ( <STR_LIT> , DL , DstVT , NativeCvt , MinC ) ; SDValue MaxC = DAG . getConstant ( APInt :: getSignedMinValue ( SatWidth ) . sext ( DstWidth ) , DL , DstVT ) ; Sat = DAG . getNode ( <STR_LIT> , DL , DstVT , Min , MaxC ) ; } else { SDValue MinC = DAG . getConstant ( APInt :: getAllOnesValue ( SatWidth ) . zext ( DstWidth ) , DL , DstVT ) ;

Sat = DAG . getNode ( <STR_LIT> , DL , DstVT , NativeCvt , MinC ) ;


<s> const unsigned DoShift = ro_Wextend -> getZExtValue ( ) & <NUM_LIT> ; assert ( ! ( ro_Wextend -> getZExtValue ( ) & ~ <NUM_LIT> ) ) ; if ( DoShift != <NUM_LIT> ) return nullptr ; if ( Signed ) Offset = Builder . CreateSExt ( Offset , Base -> getType ( ) ) ; else Offset = Builder . CreateZExt ( Offset , Base -> getType ( ) ) ; return Builder . CreateAdd ( Base , Offset ) ; } case <STR_LIT> :: AddrModeIndexed8 : case <STR_LIT> :: AddrModeIndexed16 : case <STR_LIT> :: AddrModeIndexed32 :


<s> } } if ( OtherUsers || KillsAddendSrc ) continue ; unsigned KilledProdOp = <NUM_LIT> , OtherProdOp = <NUM_LIT> ; if ( LIS -> getInterval ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . Query ( FMAIdx ) . isKill ( ) ) { KilledProdOp = <NUM_LIT> ; OtherProdOp = <NUM_LIT> ; } else if ( LIS -> getInterval ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . Query ( FMAIdx ) . isKill ( ) ) { KilledProdOp = <NUM_LIT> ; OtherProdOp = <NUM_LIT> ; } if ( ! KilledProdOp ) continue ; if ( TargetRegisterInfo :: isVirtualRegister ( AddendSrcReg ) && ! LIS -> getInterval ( AddendSrcReg ) . liveAt ( FMAIdx ) ) continue ; unsigned KilledProdReg = MI -> getOperand ( KilledProdOp ) . getReg ( ) ; unsigned OtherProdReg = MI -> getOperand ( OtherProdOp ) . getReg ( ) ; unsigned AddSubReg = AddendMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned KilledProdSubReg = MI -> getOperand ( KilledProdOp ) . getSubReg ( ) ; unsigned OtherProdSubReg = MI -> getOperand ( OtherProdOp ) . getSubReg ( ) ; bool AddRegKill = AddendMI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool KilledProdRegKill = MI -> getOperand ( KilledProdOp ) . isKill ( ) ; bool OtherProdRegKill = MI -> getOperand ( OtherProdOp ) . isKill ( ) ; bool AddRegUndef = AddendMI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool KilledProdRegUndef = MI -> getOperand ( KilledProdOp ) . isUndef ( ) ; bool OtherProdRegUndef = MI -> getOperand ( OtherProdOp ) . isUndef ( ) ; unsigned OldFMAReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( OldFMAReg == KilledProdReg ) continue ; if ( ! MRI . constrainRegClass ( KilledProdReg , MRI . getRegClass ( OldFMAReg ) ) ) continue ; assert ( OldFMAReg == AddendMI -> getOperand ( <NUM_LIT> ) . getReg ( ) && <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ; ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( KilledProdReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( KilledProdReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( AddendSrcReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( OtherProdReg ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( KilledProdSubReg ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( KilledProdSubReg ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( AddSubReg ) ; MI -> getOperand ( <NUM_LIT> ) . setSubReg ( OtherProdSubReg ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( KilledProdRegKill ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( AddRegKill ) ; MI -> getOperand ( <NUM_LIT> ) . setIsKill ( OtherProdRegKill ) ;

MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( KilledProdRegUndef ) ;


<s> if ( WAReg < MFI -> getParams ( ) . size ( ) ) continue ; if ( int ( WAReg ) < <NUM_LIT> ) continue ; LocalTypes . push_back ( getRegType ( VReg ) ) ; AnyWARegs = true ; } auto & PhysRegs = MFI -> getPhysRegs ( ) ; for ( unsigned PReg = <NUM_LIT> ; PReg < PhysRegs . size ( ) ; ++ PReg ) { if ( PhysRegs [ PReg ] == - <NUM_LIT> ) continue ;

LocalTypes . push_back ( getRegType ( PReg ) ) ;


<s> unsigned RelaxedOp = getRelaxedOpcode ( Inst . getOpcode ( ) ) ; if ( RelaxedOp == Inst . getOpcode ( ) ) { SmallString < <NUM_LIT> > Tmp ; raw_svector_ostream OS ( Tmp ) ;


<s> StringRef getPrefetchName ( ) const { assert ( Kind == k_Prefetch && <STR_LIT> ) ; return StringRef ( Prefetch . Data , Prefetch . Length ) ;


<s> return parseRegister ( Operands , RegV , <STR_LIT> , VR64Reg ) ;


<s> void <ISA_LIT>TargetLowering :: LowerHvxOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const {


<s> return ; } printOperand ( MI , OpNo , STI , O ) ; O << <STR_LIT> ;

printOperand ( MI , OpNo + <NUM_LIT> , STI , O ) ;


<s> const MCExpr * Val ; SMLoc End ; if ( ! isParsingInlineAsm ( ) ) { if ( getParser ( ) . parsePrimaryExpr ( Val , End ) ) return ErrorOperand ( Tok . getLoc ( ) , <STR_LIT> ) ; return <STR_LIT> ( Val , Start , End , Size ) ; } InlineAsmIdentifierInfo Info ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return <NUM_LIT> ; return CreateMemForInlineAsm ( <NUM_LIT> , Val , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size , Identifier , Info ) ;


<s> if ( TM . getTargetTriple ( ) . isOSBinFormatWasm ( ) && F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Name = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; Sym -> setImportName ( Name ) ; getTargetStreamer ( ) -> emitImportName ( Sym , Name ) ; } } } for ( const auto & G : M . globals ( ) ) { if ( ! G . hasInitializer ( ) && G . hasExternalLinkage ( ) ) { if ( G . getValueType ( ) -> isSized ( ) ) { uint16_t Size = M . getDataLayout ( ) . getTypeAllocSize ( G . getValueType ( ) ) ; OutStreamer -> emitELFSize ( getSymbol ( & G ) , MCConstantExpr :: create ( Size , OutContext ) ) ; } } } if ( const NamedMDNode * Named = M . getNamedMetadata ( <STR_LIT> ) ) { for ( const Metadata * MD : Named -> operands ( ) ) { const auto * Tuple = dyn_cast < MDTuple > ( MD ) ; if ( ! Tuple || Tuple -> getNumOperands ( ) != <NUM_LIT> ) continue ; const MDString * Name = dyn_cast < MDString > ( Tuple -> getOperand ( <NUM_LIT> ) ) ; const MDString * Contents = dyn_cast < MDString > ( Tuple -> getOperand ( <NUM_LIT> ) ) ; if ( ! Name || ! Contents ) continue ; OutStreamer -> PushSection ( ) ; std :: string SectionName = ( <STR_LIT> + Name -> getString ( ) ) . str ( ) ; MCSectionWasm * MySection = OutContext . getWasmSection ( SectionName , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( MySection ) ; OutStreamer -> EmitBytes ( Contents -> getString ( ) ) ; OutStreamer -> PopSection ( ) ; } }


<s> Register <ISA_LIT>FunctionInfo :: getGlobalBaseReg ( ) { if ( ! GlobalBaseReg ) GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( & getGlobalBaseRegClass ( MF ) ) ;


<s> static bool invalidateWindowsRegisterPairing ( unsigned Reg1 , unsigned Reg2 , bool NeedsWinCFI ) { if ( ! NeedsWinCFI ) return false ; if ( Reg2 == Reg1 + <NUM_LIT> ) return false ; return true ;


<s> if ( ReplaceOutside && ( isLiveOut ( Register ) || this -> getParent ( ) -> isLiveOut ( Register ) ) ) { LinearizedRegion * Current = this ; while ( Current != nullptr && Current -> getEntry ( ) != nullptr ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Current -> print ( dbgs ( ) , MRI -> getTargetRegisterInfo ( ) ) ) ; Current -> replaceLiveOut ( Register , NewRegister ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Current -> print ( dbgs ( ) , MRI -> getTargetRegisterInfo ( ) ) ) ; Current = Current -> getParent ( ) ; } } for ( MachineRegisterInfo :: reg_iterator I = MRI -> reg_begin ( Register ) , E = MRI -> reg_end ( ) ; I != E ; ) { MachineOperand & O = * I ; ++ I ; if ( O . isDef ( ) ) continue ; bool IsInside = contains ( O . getParent ( ) -> getParent ( ) ) ; bool IsLoopPHI = IsInside && ( O . getParent ( ) -> isPHI ( ) && O . getParent ( ) -> getParent ( ) == getEntry ( ) ) ; bool ShouldReplace = ( IsInside && ReplaceInside ) || ( ! IsInside && ReplaceOutside ) || ( IncludeLoopPHI && IsLoopPHI ) ; if ( ShouldReplace ) { if ( TargetRegisterInfo :: isPhysicalRegister ( NewRegister ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( NewRegister , MRI -> getTargetRegisterInfo ( ) ) << <STR_LIT> ) ;


<s> if ( MulImm >= <NUM_LIT> && MulImm <= Max ) { MulImm *= Scale ;

Imm = CurDAG -> getTargetConstant ( MulImm , SDLoc ( N ) , <STR_LIT> ) ;


<s> assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , i ) ) ; ++ NumCPEs ;

DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> << Align << '\n' ) ;


<s> static struct machine_function * riscv_init_machine_status ( void ) {

return ggc_cleared_alloc < machine_function > ( ) ;


<s> Regs . push_back ( RegNo ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; if ( parseAnyRegister ( TmpOperands ) != MatchOperand_Success ) return MatchOperand_ParseFail ; Reg = & static_cast < <ISA_LIT>Operand & > ( * TmpOperands . back ( ) ) ; RegNo = isGP64bit ( ) ? Reg -> getGPR64Reg ( ) : Reg -> getGPR32Reg ( ) ; Regs . push_back ( RegNo ) ;

Operands . push_back ( <STR_LIT> ( Regs , S , E , * this ) ) ;


<s> SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue <ISA_LIT>Z80CC ; SDValue Flag = EmitCMP ( LHS , RHS , <ISA_LIT>Z80CC , CC , dl , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VT , TrueV , FalseV , <ISA_LIT>Z80CC , Flag ) ;


<s> bool contains ( MachineInstr & MI ) {

return Insts . count ( & MI ) > <NUM_LIT> ;


<s> next_pow10 = ( j > ( INTMAX_MAX / <NUM_LIT> ) ) ? <NUM_LIT> : j * <NUM_LIT> ; if ( ( abs_multiplier - prev_pow10 <= <NUM_LIT> ) || ( next_pow10 && ( next_pow10 - abs_multiplier <= <NUM_LIT> ) ) ) return true ; } if ( num_ops <= <NUM_LIT> ) return true ; if ( __builtin_popcountll ( multiplier ) <= <NUM_LIT> || __builtin_popcountll ( multiplier ) >= <NUM_LIT> ) return true ; if ( find_mult_constants_used ( multiplier ) ) return true ;


<s> const unsigned * OpcodesForSpill = getLoadOpcodesForSpillArray ( ) ;

return OpcodesForSpill [ getSpillIndex ( RC ) ] ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ;


<s> LIS -> createAndComputeVirtRegInterval ( Reg ) ;


<s> const SDNode * Node = N . getNode ( ) ; for ( SDNode * UI : Node -> uses ( ) ) { if ( ! isa < MemSDNode > ( * UI ) ) return false ; } if ( isa < ConstantSDNode > ( RHS ) ) { int64_t ImmOff = ( int64_t ) cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ; unsigned Scale = Log2_32 ( Size ) ; if ( ( ImmOff % Size == <NUM_LIT> && ImmOff >= <NUM_LIT> && ImmOff < ( <NUM_LIT> << Scale ) ) || isPreferredADD ( ImmOff ) || isPreferredADD ( - ImmOff ) ) return false ; SDLoc DL ( N . getNode ( ) ) ; SDValue Ops [ ] = { RHS } ; SDNode * MOVI = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ; SDValue MOVIV = SDValue ( MOVI , <NUM_LIT> ) ; N = CurDAG -> getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , MOVIV ) ; }

bool IsExtendedRegisterWorthFolding = isWorthFolding ( N ) ;


<s> FunctionPass * create<ISA_LIT>O0PreLegalizerCombiner ( ) { return new <ISA_LIT>O0PreLegalizerCombiner ( ) ;


<s> bool <ISA_LIT>TTIImpl :: extractAndPopulate ( const <STR_LIT> ID , Type * RetTy , ArrayRef < Value * > Args , <STR_LIT> & Ild ) const { Type :: TypeID Ty = RetTy -> getTypeID ( ) ;

IntrinsicInfo II { ID , { Ty , ( Ty == Type :: VectorTyID ) ? RetTy -> getVectorElementType ( ) -> getTypeID ( ) : Type :: VoidTyID } } ;


<s> void <ISA_LIT>AsmInstrumentation :: InstrumentInstruction ( const MCInst & Inst , OperandVector & Operands , MCContext & Ctx , const MCInstrInfo & MII , MCStreamer & Out ) {


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( PTLI -> GetTmpOffsetForFI ( FI , <NUM_LIT> ) ) . addExternalSymbol ( tmpName ) . addImm ( <NUM_LIT> ) ; } else if ( RC == <STR_LIT> ) { unsigned opcode = ( DestReg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( opcode ) , DestReg ) . addImm ( PTLI -> GetTmpOffsetForFI ( FI , <NUM_LIT> ) ) . addExternalSymbol ( tmpName ) . addImm ( <NUM_LIT> ) ; }

else assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> if ( MI . getOpcode ( ) != TargetOpcode :: LOAD_STACK_GUARD ) return false ; MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MI . memoperands_begin ( ) ) -> getValue ( ) ) ; const TargetMachine & TM = MBB . getParent ( ) -> getTarget ( ) ; unsigned char OpFlags = Subtarget . ClassifyGlobalReference ( GV , TM ) ; const unsigned char MO_NC = <STR_LIT> ; if ( ( OpFlags & <STR_LIT> ) != <NUM_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , OpFlags ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addMemOperand ( * MI . memoperands_begin ( ) ) ;

} else if ( TM . getCodeModel ( ) == CodeModel :: Large ) {


<s> ShuffleMask . push_back ( SM_SentinelUndef ) ; continue ; } uint64_t Element = RawMask [ i ] ; uint64_t Index = Element & <NUM_LIT> ; uint64_t PermuteOp = ( Element >> <NUM_LIT> ) & <NUM_LIT> ; if ( PermuteOp == <NUM_LIT> ) { ShuffleMask . push_back ( SM_SentinelZero ) ; continue ; } if ( PermuteOp != <NUM_LIT> ) { ShuffleMask . clear ( ) ;


<s> addPass ( createR600Packetizer ( * TM ) ) ; addPass ( createR600ControlFlowFinalizer ( * TM ) ) ; } else { addPass ( create<ISA_LIT>LowerControlFlowPass ( * TM ) ) ; } return false ;


<s> EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; case <STR_LIT> : EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ;


<s> if ( isUndef ( Vec32 ) ) return DAG . getUNDEF ( <STR_LIT> ) ; return getInstr ( <STR_LIT> , dl , <STR_LIT> , { Vec32 } , DAG ) ;


<s> seekLEAFixup ( p , I , MFI ) ; } MachineOperand & q = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; if ( q . isReg ( ) && q . getReg ( ) != <STR_LIT> ) { seekLEAFixup ( q , I , MFI ) ;


<s> inline vector signed char vec_xor ( vector signed char a1 , vector signed char a2 ) {

return ( vector signed char ) __builtin_altivec_vxor ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> if ( <ISA_LIT>II :: isSPUInst ( MC ) ) { return opc == <ISA_LIT>II :: spuCONVERT_INT32 || opc == <ISA_LIT>II :: spuCONVERT_UINT32 || opc == <ISA_LIT>II :: spuCONVERT_INT16 || opc == <ISA_LIT>II :: spuCONVERT_UINT16 ;


<s> if ( Subtarget -> hasMVEIntegerOps ( ) ) return <NUM_LIT> ;

return TargetLoweringBase :: getMaxSupportedInterleaveFactor ( ) ;


<s> } if ( clobber_fprs_p ) emit_insn ( gen_tbegin_1 ( gen_rtx_CONST_INT ( VOIDmode , TBEGIN_MASK ) , tdb ) ) ; else emit_insn ( gen_tbegin_nofloat_1 ( gen_rtx_CONST_INT ( VOIDmode , TBEGIN_MASK ) , tdb ) ) ; emit_move_insn ( dest , gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , gen_rtx_REG ( CCRAWmode , CC_REGNUM ) ) , UNSPEC_CC_TO_INT ) ) ; if ( retry != NULL_RTX ) { const int CC0 = <NUM_LIT> << <NUM_LIT> ; const int CC1 = <NUM_LIT> << <NUM_LIT> ; const int CC3 = <NUM_LIT> << <NUM_LIT> ; rtx jump ; rtx count = gen_reg_rtx ( SImode ) ; rtx_code_label * leave_label = gen_label_rtx ( ) ; jump = s390_emit_jump ( leave_label , gen_rtx_EQ ( VOIDmode , gen_rtx_REG ( CCRAWmode , CC_REGNUM ) , gen_rtx_CONST_INT ( VOIDmode , CC0 | CC1 | CC3 ) ) ) ; LABEL_NUSES ( leave_label ) = <NUM_LIT> ;

emit_move_insn ( count , retry_plus_two ) ;


<s> for ( auto J : ToErase ) Substs . erase ( J ) ; if ( & I != G -> getKill ( ) ) { MachineOperand & MO = I . getOperand ( <NUM_LIT> ) ; bool Change = TransformAll || getColor ( MO . getReg ( ) ) != C ; if ( G -> requiresFixup ( ) && & I == G -> getLast ( ) ) Change = false ; if ( Change ) { Substs [ MO . getReg ( ) ] = Reg ; MO . setReg ( Reg ) ; Changed = true ; } } } assert ( Substs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( G -> getKill ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> int FI = MFI -> getFunctionContextIndex ( ) ; DenseMap < unsigned , SmallVector < MachineBasicBlock * , <NUM_LIT> >> CallSiteNumToLPad ; unsigned MaxCSNum = <NUM_LIT> ; for ( auto & MBB : * MF ) { if ( ! MBB . isEHPad ( ) ) continue ; MCSymbol * Sym = nullptr ; for ( const auto & MI : MBB ) { if ( MI . isDebugValue ( ) ) continue ; assert ( MI . isEHLabel ( ) && <STR_LIT> ) ; Sym = MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ; break ; } if ( ! MMI -> hasCallSiteLandingPad ( Sym ) ) continue ; for ( unsigned CSI : MMI -> getCallSiteLandingPad ( Sym ) ) { CallSiteNumToLPad [ CSI ] . push_back ( & MBB ) ; MaxCSNum = std :: max ( MaxCSNum , CSI ) ; } } std :: vector < MachineBasicBlock * > LPadList ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > InvokeBBs ; LPadList . reserve ( CallSiteNumToLPad . size ( ) ) ; for ( unsigned CSI = <NUM_LIT> ; CSI <= MaxCSNum ; ++ CSI ) { for ( auto & LP : CallSiteNumToLPad [ CSI ] ) { LPadList . push_back ( LP ) ; InvokeBBs . insert ( LP -> pred_begin ( ) , LP -> pred_end ( ) ) ; } } assert ( ! LPadList . empty ( ) && <STR_LIT> ) ; MachineBasicBlock * DispatchBB = MF -> CreateMachineBasicBlock ( ) ; DispatchBB -> setIsEHPad ( true ) ; MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) ; DispatchBB -> addSuccessor ( TrapBB ) ; MachineBasicBlock * DispContBB = MF -> CreateMachineBasicBlock ( ) ; DispatchBB -> addSuccessor ( DispContBB ) ; MF -> push_back ( DispatchBB ) ; MF -> push_back ( DispContBB ) ;


<s> <ISA_LIT>leTargetMachine :: <ISA_LIT>leTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> void initPacketizerState ( ) override {


<s> CSOpcode = TII -> getOpcodeForOffset ( CSOpcode , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; unsigned OrigVal = MRI . createVirtualRegister ( RC ) ; unsigned OldVal = MRI . createVirtualRegister ( RC ) ; unsigned NewVal = ( BinOpcode || IsSubWord ? MRI . createVirtualRegister ( RC ) : Src2 . getReg ( ) ) ; unsigned RotatedOldVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : OldVal ) ; unsigned RotatedNewVal = ( IsSubWord ? MRI . createVirtualRegister ( RC ) : NewVal ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigVal ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigVal ) . addMBB ( StartMBB ) . addReg ( Dest ) . addMBB ( LoopMBB ) ; if ( IsSubWord ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedOldVal ) . addReg ( OldVal ) . addReg ( BitShift ) . addImm ( <NUM_LIT> ) ; if ( Invert ) { unsigned Tmp = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( BinOpcode ) , Tmp ) . addReg ( RotatedOldVal ) . addOperand ( Src2 ) ; if ( BitSize <= <NUM_LIT> ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp ) . addImm ( - <NUM_LIT> << ( <NUM_LIT> - BitSize ) ) ; else { unsigned Tmp2 = MRI . createVirtualRegister ( RC ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , Tmp2 ) . addReg ( Tmp ) ;

BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , RotatedNewVal ) . addReg ( Tmp2 ) . addImm ( - <NUM_LIT> ) ;


<s> void setVarArgsSaveSize ( int Size ) { VarArgsSaveSize = Size ;


<s> rtx add_op1 = XEXP ( op1 , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( op1 , <NUM_LIT> ) ) == CONST_INT ) add_op0 = XEXP ( op1 , <NUM_LIT> ) , add_op1 = XEXP ( op1 , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = add_op0 ; operands [ <NUM_LIT> ] = add_op1 ; ret = <STR_LIT> ; } else if ( code1 == HIGH ) { operands [ <NUM_LIT> ] = XEXP ( op1 , <NUM_LIT> ) ; ret = <STR_LIT> ; } } else if ( code0 == MEM ) { if ( TARGET_STATS ) iq2000_count_memory_refs ( op0 , <NUM_LIT> ) ; if ( code1 == REG ) { int regno1 = REGNO ( op1 ) + subreg_offset1 ; if ( GP_REG_P ( regno1 ) ) { switch ( mode ) { case SFmode : ret = <STR_LIT> ; break ; case SImode : ret = <STR_LIT> ; break ; case HImode : ret = <STR_LIT> ; break ; case QImode : ret = <STR_LIT> ; break ; default : break ; } } } else if ( code1 == CONST_INT && INTVAL ( op1 ) == <NUM_LIT> ) { switch ( mode ) { case SFmode : ret = <STR_LIT> ; break ; case SImode : ret = <STR_LIT> ; break ; case HImode : ret = <STR_LIT> ; break ; case QImode : ret = <STR_LIT> ; break ; default : break ; } } else if ( code1 == CONST_DOUBLE && op1 == CONST0_RTX ( mode ) ) { switch ( mode ) { case SFmode : ret = <STR_LIT> ; break ; case SImode : ret = <STR_LIT> ; break ; case HImode : ret = <STR_LIT> ; break ; case QImode : ret = <STR_LIT> ; break ; default : break ; } } }


<s> unsigned getCSRFirstUseCost ( const MachineFunction & MF ) const override {


<s> const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; if ( Desc . isVariadic ( ) ) for ( auto i = Desc . getNumOperands ( ) , e = MI -> getNumOperands ( ) ; i < e ; ++ i ) { if ( i != <NUM_LIT> && ( ( MI -> getOpcode ( ) != <STR_LIT> && MI -> getOpcode ( ) != <STR_LIT> ) || i != Desc . getNumOperands ( ) ) ) OS << <STR_LIT> ; printOperand ( MI , i , OS ) ; } printAnnotation ( OS , Annot ) ; if ( CommentStream ) { switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { printAnnotation ( OS , <STR_LIT> + utostr ( ControlFlowCounter ) + ':' ) ;

ControlFlowStack . push_back ( std :: make_pair ( ControlFlowCounter ++ , true ) ) ;


<s> for ( auto iter = Definitions . begin ( ) , end = Definitions . end ( ) ; iter != end ; iter ++ ) { if ( ( * iter ) . useBlock == oldBlock ) { ( * iter ) . useBlock = newBlock ; } } for ( auto iter = ExitTargets . begin ( ) , end = ExitTargets . end ( ) ; iter != end ; iter ++ ) {


<s> initialize<ISA_LIT>VSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & <ISA_LIT>VSXFMAMutateID ) ;

if ( get<ISA_LIT>TargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) addPass ( create<ISA_LIT>TLSDynamicCallPass ( ) ) ;


<s> const DebugLoc & DL = MI -> getDebugLoc ( ) ; Register Reg = MRI -> createVirtualRegister ( TII -> getRegClass ( TII -> get ( DstOpcode ) , <NUM_LIT> , MRI -> getTargetRegisterInfo ( ) , * MBB -> getParent ( ) ) ) ; MachineInstrBuilder Bld = BuildMI ( * MBB , MI , DL , TII -> get ( DstOpcode ) , Reg ) ; for ( const MachineOperand & MO : llvm :: drop_begin ( MI -> operands ( ) ) ) Bld . add ( MO ) ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addReg ( Reg ) ;