<s> static void nvptx_file_end ( void ) { hash_table < tree_hasher > :: iterator iter ; tree decl ; FOR_EACH_HASH_TABLE_ELEMENT ( * needed_fndecls_htab , decl , tree , iter ) nvptx_record_fndecl ( decl ) ; fputs ( func_decls . str ( ) . c_str ( ) , asm_out_file ) ; if ( worker_bcast_size ) write_worker_buffer ( asm_out_file , worker_bcast_sym , worker_bcast_align , worker_bcast_size ) ; if ( worker_red_size ) write_worker_buffer ( asm_out_file , worker_red_sym , worker_red_align , worker_red_size ) ;


<s> DebugLoc DL = Op . getDebugLoc ( ) ;

SDValue OpNode = DAG . getNode ( VCCNode , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ) ;


<s> if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) return <NUM_LIT> ;


<s> SelectionDAG & DAG = * CurDAG ; for ( SDNode * N : Nodes ) { unsigned Opc = N -> getOpcode ( ) ; if ( Opc != <STR_LIT> ) continue ; SDValue OpI1 = N -> getOperand ( <NUM_LIT> ) ; EVT OpVT = OpI1 . getValueType ( ) ; if ( ! OpVT . isSimple ( ) || OpVT . getSimpleVT ( ) != <STR_LIT> ) continue ; for ( auto I = N -> use_begin ( ) , E = N -> use_end ( ) ; I != E ; ++ I ) { SDNode * U = * I ; if ( U -> getNumValues ( ) != <NUM_LIT> ) continue ; EVT UVT = U -> getValueType ( <NUM_LIT> ) ; if ( ! UVT . isSimple ( ) || ! UVT . isInteger ( ) || UVT . getSimpleVT ( ) == <STR_LIT> ) continue ; if ( UVT . isVector ( ) && UVT . getVectorElementType ( ) == <STR_LIT> ) continue ; if ( isMemOPCandidate ( N , U ) ) continue ; unsigned I1N = I . getOperandNo ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( U -> getNumOperands ( ) ) ; for ( unsigned i = <NUM_LIT> , n = U -> getNumOperands ( ) ; i != n ; ++ i ) Ops [ i ] = U -> getOperand ( i ) ; EVT BVT = Ops [ I1N ] . getValueType ( ) ; const SDLoc & dl ( U ) ; SDValue C0 = DAG . getConstant ( <NUM_LIT> , dl , BVT ) ; SDValue C1 = DAG . getConstant ( <NUM_LIT> , dl , BVT ) ; SDValue If0 , If1 ; if ( isa < MachineSDNode > ( U ) ) { unsigned UseOpc = U -> getMachineOpcode ( ) ; Ops [ I1N ] = C0 ; If0 = SDValue ( DAG . getMachineNode ( UseOpc , dl , UVT , Ops ) , <NUM_LIT> ) ; Ops [ I1N ] = C1 ; If1 = SDValue ( DAG . getMachineNode ( UseOpc , dl , UVT , Ops ) , <NUM_LIT> ) ; } else { unsigned UseOpc = U -> getOpcode ( ) ; Ops [ I1N ] = C0 ; If0 = DAG . getNode ( UseOpc , dl , UVT , Ops ) ; Ops [ I1N ] = C1 ; If1 = DAG . getNode ( UseOpc , dl , UVT , Ops ) ; } unsigned UW = UVT . getSizeInBits ( ) ;

EVT SVT = ( UW == <NUM_LIT> || UW == <NUM_LIT> ) ? <STR_LIT> ( UW ) : UVT ;


<s> int flags_in_68881 ( ) { return cc_status . flags & CC_IN_68881 ;


<s> bool isPIC = MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int BPSI = FI -> getBasePointerSaveIndex ( ) ; if ( ! BPSI && RegInfo -> hasBasePointer ( MF ) ) { int BPOffset = getBasePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI , isPIC ) ; BPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , BPOffset , true ) ; FI -> setBasePointerSaveIndex ( BPSI ) ; }


<s> explicit <ISA_LIT>AdvSIMDScalar ( ) : MachineFunctionPass ( ID ) {

initialize<ISA_LIT>AdvSIMDScalarPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> static inline bool getAM4WBFlag ( unsigned Mode ) {

return ( Mode >> <NUM_LIT> ) & <NUM_LIT> ;


return ( __m128i ) __builtin_ia32_pmovusdw256_mask ( ( __v8si ) __A , ( __v8hi ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> void printNegZeroOperand ( const MachineInstr * MI , int OpNum , raw_ostream & O ) {


<s> switch ( BitsSet ) { default : return ; case <NUM_LIT> : RC = & AMDGPU :: VReg_32RegClass ; break ; case <NUM_LIT> : RC = & AMDGPU :: VReg_64RegClass ; break ; case <NUM_LIT> : RC = & AMDGPU :: VReg_96RegClass ; break ; } MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ;


<s> void emitARM64WinCFISaveFPLR ( int Offset ) override {

OS << <STR_LIT> << Offset << <STR_LIT> ;


<s> static inline unsigned UnknownPadding ( unsigned LogAlign , unsigned KnownBits ) { if ( KnownBits < LogAlign ) return ( <NUM_LIT> << LogAlign ) - ( <NUM_LIT> << KnownBits ) ;


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

AFI = funcInfo . MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ;


<s> if ( CModel == CodeModel :: Small || CModel == CodeModel :: JITDefault ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) . addMemOperand ( MMO ) ; else { unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx , <NUM_LIT> , <STR_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; }


initialize<ISA_LIT>FixupSetCCPassPass ( PR ) ;


<s> _mm_setcsr ( ( _mm_getcsr ( ) & ~ _MM_EXCEPT_MASK ) | __mask ) ;


<s> printOperand ( MI , opNum + <NUM_LIT> ) ;


<s> unsigned CCReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; ++ NumCBrFixed ; if ( BMI != MI ) { if ( llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) == prior ( MBB -> end ( ) ) && BMI -> getOpcode ( ) == Br . UncondBr ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , NewDest , Br . MaxDisp ) ) { DEBUG ( errs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; MI -> getOperand ( <NUM_LIT> ) . setMBB ( NewDest ) ; MI -> getOperand ( <NUM_LIT> ) . setImm ( CC ) ; return true ; } } } if ( NeedSplit ) { SplitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BBSizes [ MBB -> getNumber ( ) ] -= delta ; MachineBasicBlock * SplitBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; AdjustBBOffsetsAfter ( SplitBB , - delta ) ; MBB -> back ( ) . eraseFromParent ( ) ; } MachineBasicBlock * NextBB = llvm :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( errs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ;

BBSizes [ MBB -> getNumber ( ) ] += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ;


<s> SDValue MaskNode = DAG . getConstant ( VEXPANDMask , DL , IntegerType ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; SDValue VMask = getMaskNode ( MaskNode , <STR_LIT> ( <STR_LIT> , NumElts ) , Subtarget , DAG , DL ) ; SDValue ZeroVector = getZeroVector ( VT , Subtarget , DAG , DL ) ; SDValue ExpandedVector = IsLeftZeroSide ? V2 : V1 ;

return DAG . getNode ( <STR_LIT> , DL , VT , VMask , DAG . getNode ( <STR_LIT> , DL , VT , ExpandedVector ) , ZeroVector ) ;


<s> return <STR_LIT> + DsmArRn ( reg ) + DsmArStep ( step ) + <STR_LIT> ;


<s> using namespace <ISA_LIT> ; case PCALL_INDIRECT_VOID : return CALL_INDIRECT_VOID ; case PCALL_INDIRECT_I32 : return CALL_INDIRECT_I32 ; case PCALL_INDIRECT_I64 : return CALL_INDIRECT_I64 ; case PCALL_INDIRECT_F32 : return CALL_INDIRECT_F32 ;


<s> MachineBasicBlock :: iterator I = MBB . begin ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned V0 , V1 , V2 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC = ( const TargetRegisterClass * ) & <STR_LIT> ;

V0 = RegInfo . createVirtualRegister ( RC ) ;


<s> warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } if ( TREE_CODE ( * node ) != FUNCTION_DECL ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ;


<s> OPCODE ( Hi ) ; OPCODE ( Lo ) ; OPCODE ( FENCE ) ; OPCODE ( SELECT_CC ) ; OPCODE ( SMIN ) ; OPCODE ( UMIN ) ; OPCODE ( SMAX ) ; OPCODE ( UMAX ) ; } return NULL ;


<s> tree type = builtin_types [ function_types [ type_idx ] . type_indexes [ base_type ] ] . vector ; return type ? function_types [ type_idx ] . type_indexes [ base_type ] : NUM_VECTOR_TYPES ;


<s> bool a_is_memory = desc . mayLoad ( ) || desc . mayStore ( ) ; const unsigned aend = getLastRealOperand ( a ) ; const unsigned bend = getLastRealOperand ( b ) ; MachineBasicBlock :: iterator m = a ; for ( ++ m ; m != b ; ++ m ) { for ( unsigned aop = <NUM_LIT> ; aop < aend ; ++ aop ) { bool aop_is_reg = a -> getOperand ( aop ) . isReg ( ) ; if ( ! aop_is_reg ) continue ; bool aop_is_def = a -> getOperand ( aop ) . isDef ( ) ; unsigned aop_reg = a -> getOperand ( aop ) . getReg ( ) ; const unsigned mend = getLastRealOperand ( m ) ; for ( unsigned mop = <NUM_LIT> ; mop < mend ; ++ mop ) { bool mop_is_reg = m -> getOperand ( mop ) . isReg ( ) ; if ( ! mop_is_reg ) continue ; bool mop_is_def = m -> getOperand ( mop ) . isDef ( ) ; unsigned mop_reg = m -> getOperand ( mop ) . getReg ( ) ; if ( aop_is_def && ( mop_reg == aop_reg ) ) return true ; else if ( mop_is_def && ( mop_reg == aop_reg ) ) return true ; } } if ( a_is_memory && m -> getDesc ( ) . mayStore ( ) ) return true ;


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( ST -> hasAVX ( ) ) { int Idx = CostTableLookup ( AVXAltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVXAltShuffleTbl [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > SSE41AltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( ST -> hasSSE41 ( ) ) { int Idx = CostTableLookup ( SSE41AltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSE41AltShuffleTbl [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > SSSE3AltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( ST -> hasSSSE3 ( ) ) { int Idx = CostTableLookup ( SSSE3AltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSSE3AltShuffleTbl [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > SSEAltShuffleTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; int Idx = CostTableLookup ( SSEAltShuffleTbl , <STR_LIT> , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSEAltShuffleTbl [ Idx ] . Cost ;

return BaseT :: getShuffleCost ( Kind , Tp , Index , SubTp ) ;


<s> break ; case <NUM_LIT> : Register = <STR_LIT> ; break ; default : return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> switch ( N -> getOpcode ( ) ) { default : return false ; case <STR_LIT> : { CC = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDValue N2 = N -> getOperand ( <NUM_LIT> ) ; if ( isZeroOrAllOnes ( N1 , AllOnes ) ) { Invert = false ; OtherOp = N2 ; return true ; } if ( isZeroOrAllOnes ( N2 , AllOnes ) ) { Invert = true ; OtherOp = N1 ; return true ;


<s> <ISA_LIT>BranchTargets ( ) : MachineFunctionPass ( ID ) {


<s> return __builtin_ia32_vcvtuw2ph256_mask ( ( __v16hi ) __A , _mm256_setzero_ph ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> if ( CondCodePos != StringRef :: npos ) { SMLoc S = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + CondCodePos + <NUM_LIT> ) ; StringRef CondStr = Name . substr ( CondCodePos + <NUM_LIT> , StringRef :: npos ) ; <STR_LIT> Code ; Code = A64StringToCondCode ( CondStr ) ; if ( Code == <STR_LIT> ) { Error ( S , <STR_LIT> ) ; Parser . eatToEndOfStatement ( ) ; return true ; } SMLoc DotL = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + CondCodePos ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , DotL ) ) ; SMLoc E = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + CondCodePos + <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( Code , S , E ) ) ;


<s> assert ( CI . Width >= <NUM_LIT> && CI . Width <= <NUM_LIT> ) ; assert ( Paired . Width >= <NUM_LIT> && Paired . Width <= <NUM_LIT> ) ; if ( Paired < CI ) { Idx1 = Idxs [ <NUM_LIT> ] [ Paired . Width - <NUM_LIT> ] ; Idx0 = Idxs [ Paired . Width ] [ CI . Width - <NUM_LIT> ] ; } else {

Idx0 = Idxs [ <NUM_LIT> ] [ CI . Width - <NUM_LIT> ] ;


<s> OutStreamer . EmitRawText ( Twine ( <STR_LIT> + ST . getTargetString ( ) + ( ST . supportsDouble ( ) ? <STR_LIT> : <STR_LIT> ) ) ) ; if ( ST . supports<ISA_LIT>23 ( ) ) { std :: string addrSize = ST . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; OutStreamer . EmitRawText ( Twine ( <STR_LIT> + addrSize ) ) ; } OutStreamer . AddBlankLine ( ) ; DebugInfoFinder DbgFinder ; DbgFinder . processModule ( M ) ; for ( DebugInfoFinder :: iterator I = DbgFinder . compile_unit_begin ( ) , E = DbgFinder . compile_unit_end ( ) ; I != E ; ++ I ) { DICompileUnit DIUnit ( * I ) ; StringRef FN = DIUnit . getFilename ( ) ; StringRef Dir = DIUnit . getDirectory ( ) ;


<s> opt_pass * clone ( ) final override {


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const {


<s> return false ; } if ( Start -> getOpcode ( ) == <STR_LIT> && ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) || ! BBUtils -> isBBInRange ( Start , Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) , <NUM_LIT> ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } return true ; } ; auto FindStartInsertionPoint = [ ] ( MachineInstr * Start , MachineInstr * Dec , MachineBasicBlock :: iterator & InsertPt , MachineBasicBlock * & InsertBB , ReachingDefAnalysis & RDA , InstSet & ToRemove ) { if ( Start -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } Register CountReg = Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto IsMoveLR = [ & CountReg ] ( MachineInstr * MI ) { return MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == CountReg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ; } ; if ( auto * LRDef = RDA . getUniqueReachingMIDef ( Start , MCRegister :: from ( <STR_LIT> ) ) ) { if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg . asMCReg ( ) ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { Dec } ; if ( ! TryRemove ( LRDef , RDA , ToRemove , Ignore ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } } MachineBasicBlock * MBB = Start -> getParent ( ) ; if ( auto * LRDef = RDA . getLocalLiveOutMIDef ( MBB , MCRegister :: from ( <STR_LIT> ) ) ) { if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { Start , Dec } ; if ( ! TryRemove ( LRDef , RDA , ToRemove , Ignore ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( LRDef ) ; InsertBB = LRDef -> getParent ( ) ; return true ; } } if ( ! RDA . isSafeToDefRegAt ( Start , MCRegister :: from ( <STR_LIT> ) ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( Start ) ;


<s> for ( frag = m_pSectionData -> begin ( ) ; frag != fragEnd ; ++ frag ) { frag -> setOffset ( offset ) ; offset += frag -> size ( ) ; }


<s> StoreOpcode = TII -> getOpcodeForOffset ( StoreOpcode , Disp ) ; if ( ! Invert ) CCMask = CCMask ^ <STR_LIT> ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = splitBlockAfter ( MI , MBB ) ; MachineBasicBlock * FalseMBB = emitBlockAfter ( StartMBB ) ; MBB = StartMBB ; if ( ! convertPrevCompareToBranch ( MBB , MI , CCMask , JoinMBB ) ) BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ; MBB -> addSuccessor ( FalseMBB ) ; MBB = FalseMBB ; BuildMI ( MBB , DL , TII -> get ( StoreOpcode ) ) . addReg ( SrcReg ) . addOperand ( Base ) . addImm ( Disp ) . addReg ( IndexReg ) ;


<s> if ( Kind . isMergeableConst4 ( ) ) return MergeableConst4Section ; if ( Kind . isMergeableConst8 ( ) ) return MergeableConst8Section ; if ( Kind . isMergeableConst16 ( ) ) return MergeableConst16Section ;

assert ( ( Kind . isReadOnly ( ) || Kind . isReadOnlyWithRel ( ) ) && <STR_LIT> ) ;


<s> if ( Op . isReg ( ) ) { bool isPtrReg = ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) ; if ( isPtrReg ) {

O << getRegisterName ( Op . getReg ( ) , <STR_LIT> ) ;


<s> } else { return <NUM_LIT> ; } case CFStack :: FIRST_NON_WQM_PUSH_W_FULL_ENTRY : assert ( ST -> getGeneration ( ) >= <ISA_LIT>Subtarget :: EVERGREEN ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) {

bool ret = SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> assert ( ( Imm & <NUM_LIT> ) == Imm ) ; printSSEAVXCC ( Imm , O ) ;


<s> static SDValue carryFlagToValue ( SDValue Flag , EVT VT , SelectionDAG & DAG , bool Invert ) { assert ( Flag . getResNo ( ) == <NUM_LIT> ) ; SDLoc DL ( Flag ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ;

unsigned Cond = Invert ? <STR_LIT> : <STR_LIT> ;


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & OS , raw_ostream & CS ) const { Size = <NUM_LIT> ; if ( Bytes . size ( ) < <NUM_LIT> ) { Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } uint32_t Inst = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) {

DecodeStatus result = decodeInstruction ( DecoderTableQPX32 , MI , Inst , Address , this , STI ) ;


<s> unsigned Opc = <NUM_LIT> , ZeroReg = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; else if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) { if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> , ZeroReg = <STR_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( SrcReg == <STR_LIT> ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( SrcReg ) ) { if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( DestReg == <STR_LIT> ) Opc = <STR_LIT> , DestReg = <NUM_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) ) Opc = <STR_LIT> ; } assert ( Opc && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ; if ( DestReg ) MIB . addReg ( DestReg , RegState :: Define ) ; if ( ZeroReg ) MIB . addReg ( ZeroReg ) ;

if ( SrcReg ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCtlz ( ) const { return Subtarget -> hasV6T2Ops ( ) ;


<s> unsigned getScalarDataSize ( ) const {


<s> unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return ( <STR_LIT> . contains ( DstReg ) || <STR_LIT> . contains ( DstReg ) ) ; } case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { assert ( MI -> getDesc ( ) . getNumOperands ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ;


<s> for ( auto ul : UseLocs [ MBB ] ) { auto opLoc = f ( ul . second ) ; if ( opLoc . first ) { result [ ul . first ] = unifyRegister ( opLoc . second ) ; } } }


<s> if ( DefTy == LLT :: scalar ( <NUM_LIT> ) ) { if ( ! AllowRiskySelect ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; } const RegClassOrRegBank & RegClassOrBank = MRI -> getRegClassOrRegBank ( DefReg ) ; const TargetRegisterClass * DefRC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; if ( ! DefRC ) { if ( ! DefTy . isValid ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; }

const RegisterBank & RB = * RegClassOrBank . get < const RegisterBank * > ( ) ;


<s> if ( isa < ArrayType > ( Ty ) ) { char IDStr [ <NUM_LIT> ] = { '\0' } ; Type * ElmTy = cast < ArrayType > ( Ty ) -> getElementType ( ) ; unsigned NumElm = cast < ArrayType > ( Ty ) -> getNumElements ( ) ; std :: string ElmTyStr = EmitTypeString ( ElmTy ) ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; sprintf ( IDStr , <STR_LIT> , NumElm ) ; FieldInit += IDStr ; if ( isa < StructType > ( ElmTy ) ) FieldInit += <STR_LIT> ; else FieldInit += <STR_LIT> ; FieldInit += ElmTyStr ; FieldInit += <STR_LIT> ; FieldInit += ClassName ; FieldInit += <STR_LIT> ; IDStr [ <NUM_LIT> ] = '\0' ; sprintf ( IDStr , <STR_LIT> , FieldID ) ; FieldInit += IDStr ; FieldInit += <STR_LIT> ; MFI -> getTypeDescriptor ( Ty , FieldInit ) ; if ( isa < StructType > ( ElmTy ) ) { for ( unsigned i = <NUM_LIT> ; i < NumElm ; i ++ ) { FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += ClassName ; FieldInit += <STR_LIT> ; IDStr [ <NUM_LIT> ] = '\0' ; sprintf ( IDStr , <STR_LIT> , FieldID ) ; FieldInit += IDStr ; FieldInit += <STR_LIT> ; MFI -> getTypeDescriptor ( Ty , FieldInit ) ; if ( i < <NUM_LIT> ) FieldInit += <STR_LIT> ; else FieldInit += <STR_LIT> ; IDStr [ <NUM_LIT> ] = '\0' ; sprintf ( IDStr , <STR_LIT> , i ) ; FieldInit += IDStr ; FieldInit += <STR_LIT> ; FieldInit += ElmTyStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += ElmTyStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; } } } else if ( isa < StructType > ( Ty ) ) { char IDStr [ <NUM_LIT> ] = { '\0' } ; std :: string TypeStr = EmitTypeString ( Ty ) ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += TypeStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += TypeStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += ClassName ;


<s> int arm_max_const_double_inline_cost ( ) { return ( ( optimize_size || arm_ld_sched ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; TRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; for ( auto & MBB : MF ) {


<s> const MCOperand & MO = MI -> getOperand ( opNum ) ; if ( MO . isReg ( ) ) { printRegName ( O , MO . getReg ( ) ) ; return ; } if ( MO . isImm ( ) ) { O << ( int ) MO . getImm ( ) ; return ; } assert ( MO . isExpr ( ) && <STR_LIT> ) ; MO . getExpr ( ) -> print ( O ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {


<s> unsigned <ISA_LIT>Evaluator :: getVirtRegFor ( unsigned PReg ) const { using iterator = MachineRegisterInfo :: livein_iterator ; for ( iterator I = MRI . livein_begin ( ) , E = MRI . livein_end ( ) ; I != E ; ++ I ) { if ( I -> first == PReg ) return I -> second ; } return <NUM_LIT> ;


<s> assert ( RegMask <= <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( RegMask ) ) ;


<s> return create<ISA_LIT>ObjectTargetWriter ( ) ;


<s> bool <ISA_LIT>StackModel :: runOnBasicBlocks ( MachineFunction & MF , const Stack & StartStack ) { bool Changed = false ; auto & FirstBB = MF . front ( ) ; BBInfo [ & FirstBB ] . setFixedBegin ( StartStack ) ; using RPOTType = ReversePostOrderTraversal < MachineFunction * > ; RPOTType RPOT ( & MF ) ; llvm :: dbgs ( ) << <STR_LIT> ; for ( RPOTType :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) { auto MBB = * I ; llvm :: dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) ; } llvm :: dbgs ( ) << <STR_LIT> ; for ( RPOTType :: rpo_iterator I = RPOT . begin ( ) , E = RPOT . end ( ) ; I != E ; ++ I ) { auto MBB = * I ; auto & bbInfo = BBInfo [ MBB ] ;

auto CurrentStack = bbInfo . fixedBegin ( ) ;


<s> if ( any_of ( Ins , [ ] ( const <STR_LIT> & IA ) { return IA . Flags . isByVal ( ) ; } ) ) return false ; if ( any_of ( Outs , [ ] ( const <STR_LIT> & OA ) { return OA . Flags . isByVal ( ) ; } ) ) return false ; if ( ! isFunctionGlobalAddress ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) return false ; if ( ! callsShareTOCBase ( Caller , Callee , getTargetMachine ( ) ) ) return false ; if ( CalleeCC == CallingConv :: Fast && TailCallOpt ) return true ; if ( DisableSCO ) return false ; if ( ! hasSameArgumentList ( Caller , CS ) && needStackSlotPassParameters ( Subtarget , Outs ) ) { return false ; } return true ;


<s> if ( EltTy -> isIntegerTy ( <NUM_LIT> ) || EltTy -> isIntegerTy ( <NUM_LIT> ) ) return HasBW ; return false ; } ; if ( ST -> hasAVX512 ( ) && isSupportedOnAVX512 ( VecTy , ST -> hasBWI ( ) ) ) return getInterleavedMemoryOpCostAVX512 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; if ( ST -> hasAVX2 ( ) ) return getInterleavedMemoryOpCostAVX2 ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ;

return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ;


<s> auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar && GVar -> hasAttribute ( <STR_LIT> ) ) { uint32_t Imm = PatchImms [ GVar -> getName ( ) . str ( ) ] ; OutMI . setOpcode ( <STR_LIT> ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return true ;


<s> uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; if ( FloatBits != <NUM_LIT> && FloatBits != <NUM_LIT> ) return SDValue ( ) ; MVT IntTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; if ( IntBits != <NUM_LIT> && IntBits != <NUM_LIT> && IntBits != <NUM_LIT> ) return SDValue ( ) ; if ( IntBits > FloatBits ) return SDValue ( ) ; BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t Bits = IntBits == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , Bits + <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > Bits ) return SDValue ( ) ; MVT ResTy ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; switch ( NumLanes ) { default : return SDValue ( ) ; case <NUM_LIT> :

ResTy = FloatBits == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) return true ; return TII -> isLD<ISA_LIT>nstr ( MI . getOpcode ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> SUnit * SU = & DAG -> SUnits [ SUNum ] ; unsigned color = CurrentColoring [ SU -> NodeNum ] ; std :: set < unsigned > SUColors ; if ( CurrentColoring [ SU -> NodeNum ] <= ( int ) DAGSize ) continue ; if ( ColorCount [ color ] > <NUM_LIT> ) continue ; for ( SDep & SuccDep : SU -> Succs ) { SUnit * Succ = SuccDep . getSUnit ( ) ; if ( SuccDep . isWeak ( ) || Succ -> NodeNum >= DAGSize ) continue ; SUColors . insert ( CurrentColoring [ Succ -> NodeNum ] ) ;


<s> Cond = Term -> getCondition ( ) ; if ( Idx != Invert ) Cond = invert ( Cond ) ;


<s> else if ( size > <NUM_LIT> ) loongarch_emit_probe_stack_range ( get_stack_check_protect ( ) , size ) ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , loongarch_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; loongarch_for_each_saved_reg ( size , loongarch_save_reg ) ; } if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; loongarch_emit_stack_tie ( ) ; }


<s> AMDGPUAsmParser ( MCSubtargetInfo & _STI , MCAsmParser & _Parser , const MCInstrInfo & _MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( _STI ) , Parser ( _Parser ) {

setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> unsigned int i ; if ( ! reg_overlap_mentioned_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) || REGNO ( operands [ <NUM_LIT> ] ) < REGNO ( operands [ <NUM_LIT> ] ) ) { for ( i = <NUM_LIT> ; i < count ; i ++ ) {

operands [ <NUM_LIT> * i ] = dest [ i ] ;


<s> } if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; return ; } assert ( Op . isExpr ( ) && <STR_LIT> ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> static DecodeStatus DecodeStoreI64 ( MCInst & Inst , uint64_t insn , uint64_t Address , const MCDisassembler * Decoder ) {

return DecodeMem ( Inst , insn , Address , Decoder , false , DecodeI64RegisterClass ) ;


<s> static SDValue tryConvertSVEWideCompare ( SDNode * N , <STR_LIT> CC , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG ) { if ( DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; SDValue Comparator = N -> getOperand ( <NUM_LIT> ) ; if ( Comparator . getOpcode ( ) == <STR_LIT> || Comparator . getOpcode ( ) == <STR_LIT> ) { unsigned IID = getIntrinsicID ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT CmpVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Pred = N -> getOperand ( <NUM_LIT> ) ; SDValue Imm ; SDLoc DL ( N ) ; switch ( IID ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( auto * CN = dyn_cast < ConstantSDNode > ( Comparator . getOperand ( <NUM_LIT> ) ) ) { int64_t ImmVal = CN -> getSExtValue ( ) ;

if ( ImmVal >= - <NUM_LIT> && ImmVal <= <NUM_LIT> ) Imm = DAG . getConstant ( ImmVal , DL , <STR_LIT> ) ;


<s> if ( Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) break ; -- MBBI ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; DL = MBBI -> getDebugLoc ( ) ; if ( NumBytes || MFI -> hasVarSizedObjects ( ) ) mergeSPUpdatesUp ( MBB , MBBI , StackPtr , & NumBytes ) ; if ( RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) ) { if ( RegInfo -> needsStackRealignment ( MF ) ) MBBI = FirstCSPop ; if ( CSSize != <NUM_LIT> ) { unsigned Opc = getLEArOpcode ( IsLP64 ) ; addRegOffset ( BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) , FramePtr , false , - CSSize ) ; } else { unsigned Opc = ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Opc ) , StackPtr ) . addReg ( FramePtr ) ; } } else if ( NumBytes ) { emitSPUpdate ( MBB , MBBI , StackPtr , NumBytes , Is64Bit , IsLP64 , UseLEA , TII , * RegInfo ) ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & DestAddr = MBBI -> getOperand ( <NUM_LIT> ) ; assert ( DestAddr . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( DestAddr . getReg ( ) ) ; } else if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { bool isMem = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; MachineOperand & StackAdjust = MBBI -> getOperand ( isMem ? <NUM_LIT> : <NUM_LIT> ) ; assert ( StackAdjust . isImm ( ) && <STR_LIT> ) ; int StackAdj = StackAdjust . getImm ( ) ; int MaxTCDelta = <ISA_LIT>FI -> getTCReturnAddrDelta ( ) ; int Offset = <NUM_LIT> ; assert ( MaxTCDelta <= <NUM_LIT> && <STR_LIT> ) ; Offset = StackAdj - MaxTCDelta ; assert ( Offset >= <NUM_LIT> && <STR_LIT> ) ; if ( Offset ) { Offset += mergeSPUpdates ( MBB , MBBI , StackPtr , true ) ;

emitSPUpdate ( MBB , MBBI , StackPtr , Offset , Is64Bit , IsLP64 , UseLEA , TII , * RegInfo ) ;


<s> Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <NUM_LIT> ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; ConstantPoolSection = <STR_LIT> ; JumpTableDataSection = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; AscizDirective = <STR_LIT> ; WeakDefDirective = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; SetDirective = <STR_LIT> ; HasLEB128 = true ; AbsoluteDebugSectionOffsets = true ; DwarfAbbrevSection = <STR_LIT> ; DwarfInfoSection = <STR_LIT> ; DwarfLineSection = <STR_LIT> ; DwarfFrameSection = <STR_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFSINCOS ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; SDValue Arg = Op . getOperand ( <NUM_LIT> ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . IsSExt = false ; Entry . IsZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DAG . getDataLayout ( ) ) ) ; StructType * RetTy = StructType :: get ( ArgTy , ArgTy ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: Fast , RetTy , Callee , std :: move ( Args ) ) ;

std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ;


<s> CostLeaf * getLoopHead ( ) { return this -> LoopHead ;


<s> const uint64_t QW = eatBytes < uint64_t > ( Bytes ) ; Res = tryDecodeInst ( DecoderTableDPP64 , MI , QW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTableSDWA64 , MI , QW , Address ) ; if ( Res ) break ; } Bytes = Bytes_ . slice ( <NUM_LIT> , MaxInstBytesNum ) ; if ( Bytes . size ( ) < <NUM_LIT> ) break ; const uint32_t DW = eatBytes < uint32_t > ( Bytes ) ; Res = tryDecodeInst ( DecoderTableVI32 , MI , DW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTable<ISA_LIT>32 , MI , DW , Address ) ; if ( Res ) break ; if ( Bytes . size ( ) < <NUM_LIT> ) break ; const uint64_t QW = ( ( uint64_t ) eatBytes < uint32_t > ( Bytes ) << <NUM_LIT> ) | DW ; Res = tryDecodeInst ( DecoderTableVI64 , MI , QW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTable<ISA_LIT>64 , MI , QW , Address ) ; } while ( false ) ; if ( Res && ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ) {

int Src2ModIdx = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: src2_modifiers ) ;


<s> bool <ISA_LIT>MCInstrInfo :: isCanon ( MCInstrInfo const & MCII , MCInst const & MCI ) {

return ( ! <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isPseudo ( ) && ! <ISA_LIT>MCInstrInfo :: isPrefix ( MCII , MCI ) && <ISA_LIT>MCInstrInfo :: getType ( MCII , MCI ) != <STR_LIT> ) ;


<s> TargetRegisterClass * RC = TLI . getRegClassFor ( VT ) ; unsigned ResultReg = createResultReg ( RC ) ; unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( SI -> second ) . addImm ( <NUM_LIT> ) ) ; return ResultReg ;


<s> <ISA_LIT>AsmPrinter :: <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , AFI ( nullptr ) , MCP ( nullptr ) , InConstantPool ( false ) {


<s> bool FP = hasFP ( MF ) ; if ( FP ) { unsigned FramePtr = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( FramePtr ) ; } int FrameSize = MFI -> getStackSize ( ) ; assert ( FrameSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; FrameSize /= <NUM_LIT> ; bool isU6 = isImmU6 ( FrameSize ) ; if ( ! isU6 && ! isImmU16 ( FrameSize ) ) { report_fatal_error ( <STR_LIT> + Twine ( FrameSize ) ) ; } if ( FP ) { int FPSpillOffset = MFI -> getObjectOffset ( XFI -> getFPSpillSlot ( ) ) ; FPSpillOffset += FrameSize * <NUM_LIT> ; loadFromStack ( MBB , MBBI , <STR_LIT> , FPSpillOffset , dl , TII ) ; }


<s> case <STR_LIT> : if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) break ; if ( <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) break ; if ( getLdStRegOp ( MI ) . getReg ( ) == BaseReg && getLdStBaseOp ( MI ) . getReg ( ) == BaseReg && getLdStOffsetOp ( MI ) . getImm ( ) <= <NUM_LIT> && getLdStOffsetOp ( MI ) . getImm ( ) >= - <NUM_LIT> ) { if ( ! Offset || Offset == MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return true ; } break ; } return false ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ; return ; case <STR_LIT> : ReplaceATOMIC_OP_64 ( N , Results , DAG , <STR_LIT> ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64bit ) , DL ( Subtarget . getDataLayout ( ) ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {


<s> return ( __mmask8 ) __builtin_ia32_cvtq2mask256 ( ( __v4di ) __A ) ;


<s> if ( HII -> isDotNewInst ( MI ) && ! HII -> mayBeNewStore ( MI ) ) return false ; if ( ! isNewifiable ( MI , RC ) ) return false ; const MachineInstr & PI = * PacketSU -> getInstr ( ) ; if ( PI . isInlineAsm ( ) ) return false ; if ( PI . isImplicitDef ( ) ) return false ; if ( isImplicitDependency ( PI , DepReg ) ) return false ; const MCInstrDesc & MCID = PI . getDesc ( ) ; const TargetRegisterClass * VecRC = HII -> getRegClass ( MCID , <NUM_LIT> , HRI , MF ) ; if ( DisableVecDblNVStores && VecRC == & <STR_LIT> ) return false ; if ( RC == & <STR_LIT> ) if ( HII -> isCondInst ( MI ) || MI . isReturn ( ) ) return HII -> predCanBeUsedAsDotNew ( PI , DepReg ) ; if ( RC != & <STR_LIT> && ! HII -> mayBeNewStore ( MI ) ) return false ; int NewOpcode = HII -> getDotNewOp ( MI ) ; const MCInstrDesc & D = HII -> get ( NewOpcode ) ; MachineInstr * NewMI = MF . CreateMachineInstr ( D , DebugLoc ( ) ) ;

bool ResourcesAvailable = ResourceTracker -> canReserveResources ( * NewMI ) ;


<s> virtual const char * getPassName ( ) const {


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectConcatVector ( SDNode * N ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ;

if ( ! VT . is128BitVector ( ) || N -> getNumOperands ( ) != <NUM_LIT> ) llvm_unreachable ( <STR_LIT> ) ;


<s> SDLoc DL ( N ) ; SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) , DAG . getNode ( <STR_LIT> , DL , Ty , Lo ) ) ;


<s> const GlobalValue * GV = GSD -> getGlobal ( ) ; MVT PtrVT = getPointerTy ( GSD -> getAddressSpace ( ) ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> ) ; SDValue PtrLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;

SDValue PtrHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { unsigned ShiftAmt = V . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < ValueBit , <NUM_LIT> > LHSBits ( Bits . size ( ) ) ; getValueBits ( V . getOperand ( <NUM_LIT> ) , LHSBits ) ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) - ShiftAmt ; ++ i ) Bits [ i ] = LHSBits [ i + ShiftAmt ] ; for ( unsigned i = Bits . size ( ) - ShiftAmt ; i < Bits . size ( ) ; ++ i ) Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; return true ; } break ; case <STR_LIT> : if ( isa < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ) { uint64_t Mask = V . getConstantOperandVal ( <NUM_LIT> ) ; SmallVector < ValueBit , <NUM_LIT> > LHSBits ( Bits . size ( ) ) ; bool LHSTrivial = getValueBits ( V . getOperand ( <NUM_LIT> ) , LHSBits ) ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) ; ++ i ) if ( ( ( Mask >> i ) & <NUM_LIT> ) == <NUM_LIT> ) Bits [ i ] = LHSBits [ i ] ; else Bits [ i ] = ValueBit ( ValueBit :: ConstZero ) ; return LHSTrivial ; } break ; case <STR_LIT> : { SmallVector < ValueBit , <NUM_LIT> > LHSBits ( Bits . size ( ) ) , RHSBits ( Bits . size ( ) ) ; getValueBits ( V . getOperand ( <NUM_LIT> ) , LHSBits ) ; getValueBits ( V . getOperand ( <NUM_LIT> ) , RHSBits ) ; bool AllDisjoint = true ; for ( unsigned i = <NUM_LIT> ; i < Bits . size ( ) ; ++ i ) if ( LHSBits [ i ] . isZero ( ) ) Bits [ i ] = RHSBits [ i ] ; else if ( RHSBits [ i ] . isZero ( ) ) Bits [ i ] = LHSBits [ i ] ; else { AllDisjoint = false ; break ; } if ( ! AllDisjoint ) break ; return true ; }


<s> return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: verifyInstruction ( const MachineInstr & MI , StringRef & ErrInfo ) const {

return TargetInstrInfo :: verifyInstruction ( MI , ErrInfo ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT , unsigned , Align , MachineMemOperand :: Flags , bool * Fast ) const {


<s> SDValue In2L = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue In2H = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { Chain , In1 , In2L , In2H } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getMemIntrinsicNode ( NewOp , dl , Tys , Ops , <NUM_LIT> , <STR_LIT> , cast < MemSDNode > ( Node ) -> getMemOperand ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpsF , <NUM_LIT> ) ) ; Results . push_back ( Result . getValue ( <NUM_LIT> ) ) ;


<s> if ( size % UNITS_PER_WORD != <NUM_LIT> ) { size += UNITS_PER_WORD - size % UNITS_PER_WORD ; mode = int_mode_for_size ( size * BITS_PER_UNIT , <NUM_LIT> ) . require ( ) ; } }


<s> void setHasSEHFramePtrSave ( bool V ) { HasSEHFramePtrSave = V ;


<s> const LLT P2 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; setAction ( { G_CONSTANT , S64 } , Legal ) ; setAction ( { G_GEP , P1 } , Legal ) ; setAction ( { G_GEP , P2 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , S64 } , Legal ) ; setAction ( { G_LOAD , P1 } , Legal ) ; setAction ( { G_LOAD , P2 } , Legal ) ; setAction ( { G_LOAD , S32 } , Legal ) ; setAction ( { G_LOAD , <NUM_LIT> , P1 } , Legal ) ; setAction ( { G_LOAD , <NUM_LIT> , P2 } , Legal ) ; setAction ( { G_STORE , S32 } , Legal ) ; setAction ( { G_STORE , <NUM_LIT> , P1 } , Legal ) ;


<s> unsigned SrcSize = getRegSizeInBits ( * SrcRC ) ; unsigned DstSize = getRegSizeInBits ( * DstRC ) ;

unsigned NewSize = getRegSizeInBits ( * NewRC ) ;


<s> for ( int64_t i = WordCount - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { uint16_t Word = Words [ i ] ; OS << ( uint8_t ) ( ( Word & <NUM_LIT> ) >> <NUM_LIT> ) ; OS << ( uint8_t ) ( ( Word & <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> void addITMaskOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , <STR_LIT> , & MI -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , & MI -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , & MI -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( <STR_LIT> , <STR_LIT> , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) , & MI -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> :


<s> MachineBasicBlock :: iterator J = I ; if ( ! MBDisableDelaySlotFiller ) D = findDelayInstr ( MBB , I ) ; ++ FilledSlots ; Changed = true ; if ( D == MBB . end ( ) ) BuildMI ( MBB , ++ J , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; else MBB . splice ( ++ J , & MBB , D ) ; }


<s> bool isCheri256 ( ) const { return IsCheri256 ;


<s> <ISA_LIT>RegBankCombinerInfo ( bool EnableOpt , bool OptSize , bool MinSize , const <ISA_LIT>LegalizerInfo * LI , GISelKnownBits * KB , MachineDominatorTree * MDT ) : CombinerInfo ( false , true , LI , EnableOpt , OptSize , MinSize ) , KB ( KB ) , MDT ( MDT ) { if ( ! Generated . parseCommandLineOption ( ) ) report_fatal_error ( <STR_LIT> ) ;


<s> return static_cast < unsigned > ( ( MCInstD . TSFlags >> LanesStart ) & <ISA_LIT>II :: LanesMask ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( getCheriHWRegsReg ( ) ) ) ;


<s> else if ( GET_CODE ( src ) == ZERO_EXTEND && GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == MEM ) { mem = XEXP ( src , <NUM_LIT> ) ; unsignedp = TRUE ; } else mem = NULL_RTX ; if ( mem && ep_memory_operand ( mem , GET_MODE ( mem ) , unsignedp ) ) use_ep = TRUE ; else if ( ! use_ep && mem && GET_MODE_SIZE ( GET_MODE ( mem ) ) <= UNITS_PER_WORD ) { rtx addr = XEXP ( mem , <NUM_LIT> ) ; int regno = - <NUM_LIT> ; int short_p ; if ( GET_CODE ( addr ) == REG ) { short_p = TRUE ; regno = REGNO ( addr ) ; } else if ( GET_CODE ( addr ) == PLUS && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT && ( ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) ) < ep_memory_offset ( GET_MODE ( mem ) , unsignedp ) ) && ( ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) ) >= <NUM_LIT> ) ) { short_p = TRUE ; regno = REGNO ( XEXP ( addr , <NUM_LIT> ) ) ; } else short_p = FALSE ; if ( short_p ) { regs [ regno ] . uses ++ ; regs [ regno ] . last_insn = insn ; if ( ! regs [ regno ] . first_insn ) regs [ regno ] . first_insn = insn ; } } if ( GET_CODE ( dest ) == REG ) { enum machine_mode mode = GET_MODE ( dest ) ; int regno ; int endregno ; regno = REGNO ( dest ) ; endregno = regno + HARD_REGNO_NREGS ( regno , mode ) ; if ( ! use_ep ) { int max_uses = - <NUM_LIT> ; int max_regno = - <NUM_LIT> ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) { if ( max_uses < regs [ i ] . uses ) { max_uses = regs [ i ] . uses ; max_regno = i ;


<s> bool <ISA_LIT>AsmBackend :: mayNeedRelaxation ( const MCInst & Inst ) const {


<s> SDLoc DL ( CCReg ) ; SDValue IPM = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CCReg ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , IPM , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( TM -> getTargetTriple ( ) . isOSBinFormatELF ( ) && TM -> Options . EnableFastISel ) addPass ( create<ISA_LIT>GlobalBaseRegPass ( ) ) ;


<s> return ( Kind != ScalarCondVectorVal ) ;


<s> return ( __m64 ) __builtin_arm_wmulwsmr ( ( __v2si ) a , ( __v2si ) b ) ;


<s> ret = rs6000_legitimize_address ( x , oldx , mode ) ; insns = get_insns ( ) ; end_sequence ( ) ; if ( ret != x ) {

fprintf ( stderr , <STR_LIT> <STR_LIT> , GET_MODE_NAME ( mode ) , GET_RTX_NAME ( GET_CODE ( x ) ) , GET_RTX_NAME ( GET_CODE ( ret ) ) ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , bool Is64Bit , bool IsLittleEndian , uint8_t OSABI ) {

MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( Is64Bit , OSABI ) ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( isWave32 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ;

unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ;


<s> assert ( RemapSwizzle . empty ( ) ) ; SDValue NewBldVec [ <NUM_LIT> ] = { VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) , VectorEntry . getOperand ( <NUM_LIT> ) } ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( NewBldVec [ i ] . getOpcode ( ) == <STR_LIT> ) RemapSwizzle [ i ] = <NUM_LIT> ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( NewBldVec [ i ] ) ) { if ( C -> isZero ( ) ) { RemapSwizzle [ i ] = <NUM_LIT> ; NewBldVec [ i ] = DAG . getUNDEF ( <STR_LIT> ) ; } else if ( C -> isExactlyValue ( <NUM_LIT> ) ) {


<s> SDValue <ISA_LIT>TargetLowering :: getGlobalAddressWrapper ( SDValue GA , const GlobalValue * GV , SelectionDAG & DAG ) const { SDLoc dl ( GA ) ; const GlobalValue * UnderlyingGV = GV ; if ( const GlobalAlias * GA = dyn_cast < GlobalAlias > ( GV ) ) UnderlyingGV = GA -> getAliasee ( ) ;

if ( const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( UnderlyingGV ) ) {


<s> if ( Subtarget . in<ISA_LIT>16Mode ( ) ) return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ; else return TFI -> hasFP ( MF ) ? ( IsN64 ? <STR_LIT> : <STR_LIT> ) : ( IsN64 ? <STR_LIT> : <STR_LIT> ) ;


<s> for ( auto I = B . instr_begin ( ) , E = B . instr_end ( ) ; I != E ; I = NextI ) { NextI = std :: next ( I ) ; MachineInstr * MI = & * I ; if ( MI -> isBundle ( ) ) BundleIt = I ; if ( ! MI -> isInsideBundle ( ) ) continue ; bool InsertBeforeBundle ; if ( MI -> isInlineAsm ( ) ) InsertBeforeBundle = ! hasWriteToReadDep ( MI , BundleIt , HRI ) ; else if ( MI -> isDebugValue ( ) ) InsertBeforeBundle = true ; else continue ; BundleIt = moveInstrOut ( MI , BundleIt , InsertBeforeBundle ) ; }


<s> name += utostr ( RegRets . size ( ) - <NUM_LIT> ) ;


<s> FeatureBitset Features = coalesceFeatures ( M ) ; std :: string FeatureStr = getFeatureString ( Features ) ; for ( auto & F : M ) replaceFeatures ( F , FeatureStr ) ; bool Stripped = false ; if ( ! Features [ <STR_LIT> ] ) { Stripped |= stripAtomics ( M ) ;


<s> if ( getRelaxedOpcodeArith ( Inst ) == Inst . getOpcode ( ) ) return false ;

unsigned RelaxableOp = Inst . getNumOperands ( ) - <NUM_LIT> ;


<s> case <STR_LIT> : return MCSymbolRefExpr :: VK_TPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_GOTTPOFF ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL ; case <STR_LIT> : return MCSymbolRefExpr :: VK_<ISA_LIT>_GOT_PREL ; case <STR_LIT> : return MCSymbolRefExpr :: VK_SECREL ;


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; if ( CModel == CodeModel :: Large ) { unsigned TmpReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg2 ) . addConstantPoolIndex ( Idx ) . addReg ( TmpReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg2 ) ;

} else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx , <NUM_LIT> , <STR_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc dl ( Op ) ; if ( Subtarget . isDarwinABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) { EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( MF . getDataLayout ( ) ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; } SDValue ArgGPR = DAG . getConstant ( FuncInfo -> getVarArgsNumGPR ( ) , dl , <STR_LIT> ) ; SDValue ArgFPR = DAG . getConstant ( FuncInfo -> getVarArgsNumFPR ( ) , dl , <STR_LIT> ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( MF . getDataLayout ( ) ) ; SDValue StackOffsetFI = DAG . getFrameIndex ( FuncInfo -> getVarArgsStackOffset ( ) , PtrVT ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ; uint64_t FrameOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> ; SDValue ConstFrameOffset = DAG . getConstant ( FrameOffset , dl , PtrVT ) ; uint64_t StackOffset = PtrVT . getSizeInBits ( ) / <NUM_LIT> - <NUM_LIT> ; SDValue ConstStackOffset = DAG . getConstant ( StackOffset , dl , PtrVT ) ; uint64_t FPROffset = <NUM_LIT> ; SDValue ConstFPROffset = DAG . getConstant ( FPROffset , dl , PtrVT ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue firstStore = DAG . getTruncStore ( Op . getOperand ( <NUM_LIT> ) , dl , ArgGPR , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , <STR_LIT> , false , false , <NUM_LIT> ) ; uint64_t nextOffset = FPROffset ; SDValue nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op . getOperand ( <NUM_LIT> ) , ConstFPROffset ) ; SDValue secondStore = DAG . getTruncStore ( firstStore , dl , ArgFPR , nextPtr , MachinePointerInfo ( SV , nextOffset ) , <STR_LIT> , false , false , <NUM_LIT> ) ; nextOffset += StackOffset ; nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , nextPtr , ConstStackOffset ) ; SDValue thirdStore = DAG . getStore ( secondStore , dl , StackOffsetFI , nextPtr , MachinePointerInfo ( SV , nextOffset ) , false , false , <NUM_LIT> ) ; nextOffset += FrameOffset ; nextPtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , nextPtr , ConstFrameOffset ) ;

return DAG . getStore ( thirdStore , dl , FR , nextPtr , MachinePointerInfo ( SV , nextOffset ) , false , false , <NUM_LIT> ) ;


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { const <ISA_LIT>TargetMachine & TM = get<ISA_LIT>TargetMachine ( ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; addPass ( createAtomicExpandPass ( ) ) ; addPass ( create<ISA_LIT>LowerIntrinsicsPass ( ) ) ; addPass ( create<ISA_LIT>AlwaysInlinePass ( ) ) ; addPass ( createAlwaysInlinerLegacyPass ( ) ) ; addPass ( createBarrierNoopPass ( ) ) ; if ( TM . getTargetTriple ( ) . getArch ( ) == Triple :: amdgcn ) {

addPass ( create<ISA_LIT>CodeGenPreparePass ( ) ) ;


<s> if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } bool SrcIsKill = MI . getOperand ( OpIdx ) . isKill ( ) ; bool SrcIsUndef = MI . getOperand ( OpIdx ) . isUndef ( ) ; unsigned SrcReg = MI . getOperand ( OpIdx ++ ) . getReg ( ) ; unsigned D0 , D1 , D2 , D3 ; GetDSubRegs ( SrcReg , RegSpc , TRI , D0 , D1 , D2 , D3 ) ; MIB . addReg ( D0 , getUndefRegState ( SrcIsUndef ) ) ;

if ( NumRegs > <NUM_LIT> && TableEntry -> copyAllListRegs ) MIB . addReg ( D1 , getUndefRegState ( SrcIsUndef ) ) ;


<s> to_add = tmp ; } if ( TARGET_32BIT ) pat = gen_sp_adjust_32bit ( stack_pointer_rtx , stack_pointer_rtx , to_add ) ; else pat = gen_sp_adjust ( stack_pointer_rtx , stack_pointer_rtx , to_add ) ; insn = emit_insn ( pat ) ; REG_NOTES ( insn ) = reg_notes ; if ( frame_related ) { rtx real = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , imm_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;

add_reg_note ( insn , REG_CFA_ADJUST_CFA , real ) ;


<s> auto * L = cast < LoadSDNode > ( C . Op0 . getOperand ( <NUM_LIT> ) ) ; if ( L -> getMemoryVT ( ) . getStoreSizeInBits ( ) . getFixedSize ( ) <= C . Op0 . getValueSizeInBits ( ) . getFixedSize ( ) ) { unsigned Type = L -> getExtensionType ( ) ; if ( ( Type == <STR_LIT> && C . ICmpType != <STR_LIT> ) || ( Type == <STR_LIT> && C . ICmpType != <STR_LIT> ) ) { C . Op0 = C . Op0 . getOperand ( <NUM_LIT> ) ; C . Op1 = DAG . getConstant ( <NUM_LIT> , DL , C . Op0 . getValueType ( ) ) ; } }


<s> return encodeImmN ( MI , Op , Fixups , STI , MCFixupKind ( <STR_LIT> ) ) ;


<s> } return LPCC :: ICC_GT ; case <STR_LIT> : return LPCC :: ICC_UGT ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) return LPCC :: ICC_MI ; return LPCC :: ICC_LT ; case <STR_LIT> : return LPCC :: ICC_ULT ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return LPCC :: ICC_MI ; } return LPCC :: ICC_LE ; case <STR_LIT> : return LPCC :: ICC_ULE ; case <STR_LIT> : if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) if ( RHSC -> getZExtValue ( ) == <NUM_LIT> ) return LPCC :: ICC_PL ; return LPCC :: ICC_GE ; case <STR_LIT> : return LPCC :: ICC_UGE ; case <STR_LIT> : return LPCC :: ICC_NE ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static SDValue lowerShuffleWithSSE4A ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const APInt & Zeroable , SelectionDAG & DAG ) { uint64_t BitLen , BitIdx ; if ( matchShuffleAsEXTRQ ( VT , V1 , V2 , Mask , BitLen , BitIdx , Zeroable ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , DAG . getTargetConstant ( BitLen , DL , <STR_LIT> ) , DAG . getTargetConstant ( BitIdx , DL , <STR_LIT> ) ) ;

if ( matchShuffleAsINSERTQ ( VT , V1 , V2 , Mask , BitLen , BitIdx ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 ? V1 : DAG . getUNDEF ( VT ) , V2 ? V2 : DAG . getUNDEF ( VT ) , DAG . getTargetConstant ( BitLen , DL , <STR_LIT> ) , DAG . getTargetConstant ( BitIdx , DL , <STR_LIT> ) ) ;


<s> recovery -> push_back ( memRestoreInst ) ; unsigned int valReg = strInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned int memReg = strInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * MoveValRegM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( valReg ) . addReg ( getSlaveReg2 ( valReg ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * MoveValRegD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( getSlaveReg1 ( valReg ) ) . addReg ( getSlaveReg2 ( valReg ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * MoveMemRegM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( memReg ) . addReg ( getSlaveReg2 ( memReg ) ) . addImm ( <NUM_LIT> ) ; MachineInstr * MoveMemRegD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( getSlaveReg1 ( memReg ) ) . addReg ( getSlaveReg2 ( memReg ) ) . addImm ( <NUM_LIT> ) ; recovery -> push_back ( MoveValRegM ) ; recovery -> push_back ( MoveValRegD ) ; recovery -> push_back ( MoveMemRegM ) ; recovery -> push_back ( MoveMemRegD ) ; MachineInstr * jumpBack = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addMBB ( sourceMB ) ;


<s> return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } else if ( Opcode == TargetOpcode :: STACKMAP ) { return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else if ( Opcode == TargetOpcode :: PATCHPOINT ) {


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( const MCInst * MI , unsigned OpNum ) { <STR_LIT> CC = ( <STR_LIT> ) MI -> getOperand ( OpNum ) . getImm ( ) ; if ( CC != <STR_LIT> ) O << <ISA_LIT>CondCodeToString ( CC ) ;


<s> setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Custom ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( ! Subtarget . hasStdExtM ( ) ) { setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; } setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ; setOperationAction ( <STR_LIT> , XLenVT , Expand ) ;


<s> LastEMS = LastMappingSymbols . lookup ( Section ) ; MCELFStreamer :: ChangeSection ( Section ) ;


<s> tree expr = MEM_EXPR ( mem ) ; if ( ! expr ) continue ; if ( TREE_CODE ( expr ) == MEM_REF && TREE_CODE ( TREE_OPERAND ( expr , <NUM_LIT> ) ) == SSA_NAME ) { gimple * def_stmt = SSA_NAME_DEF_STMT ( TREE_OPERAND ( expr , <NUM_LIT> ) ) ; if ( def_stmt && is_gimple_assign ( def_stmt ) ) expr = gimple_assign_rhs1 ( def_stmt ) ; } if ( is_attr_preserve_access ( expr ) ) maybe_make_core_relo ( expr , BPF_RELO_FIELD_BYTE_OFFSET ) ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : MF ( MF ) , SRetReturnReg ( <NUM_LIT> ) , GlobalBaseReg ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , InArgFIRange ( std :: make_pair ( - <NUM_LIT> , <NUM_LIT> ) ) , OutArgFIRange ( std :: make_pair ( - <NUM_LIT> , <NUM_LIT> ) ) , GPFI ( <NUM_LIT> ) , DynAllocFI ( <NUM_LIT> ) , MaxCallFrameSize ( <NUM_LIT> ) {


<s> * NewMBB = next ( MachineFunction :: iterator ( UserMBB ) ) ; int UncondBr = isThumb ? ( ( isThumb2 ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; BuildMI ( UserMBB , DebugLoc :: getUnknownLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( * NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; int delta = isThumb1 ? <NUM_LIT> : <NUM_LIT> ; BBSizes [ UserMBB -> getNumber ( ) ] += delta ; AdjustBBOffsetsAfter ( UserMBB , delta ) ; } else { unsigned BaseInsertOffset = UserOffset + U . MaxDisp - <NUM_LIT> ; if ( BaseInsertOffset >= BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] ) BaseInsertOffset = BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] - ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; unsigned EndInsertOffset = BaseInsertOffset + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;

MachineBasicBlock :: iterator MI = UserMI ;


<s> parseOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , StringRef Mnemonic ) { OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail ) return ResTy ; if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) { Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Percent ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; unsigned RegNo , RegKind ; if ( ! matchRegisterName ( Parser . getTok ( ) , RegNo , RegKind ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( RegNo , RegKind , S , E ) ) ; ResTy = MatchOperand_Success ; } else { ResTy = parseMEMOperand ( Operands ) ; } if ( ResTy != MatchOperand_Success ) return ResTy ; if ( ! getLexer ( ) . is ( AsmToken :: RBrac ) ) return MatchOperand_ParseFail ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , Parser . getTok ( ) . getLoc ( ) ) ) ; Parser . Lex ( ) ; return MatchOperand_Success ;


<s> return ; } printOperand ( MI , opNum , O ) ; O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT> ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> static const <ISA_LIT>MCExpr * CreateLo ( const MCExpr * Expr , MCContext & Ctx ) { return Create ( VK_<ISA_LIT>_ABS_LO , Expr , Ctx ) ;


<s> unsigned Align = std :: max ( Out . Flags . getOrigAlign ( ) , Layout . getABITypeAlignment ( Ty ) ) ; unsigned Offset = CCInfo . AllocateStack ( Layout . getTypeAllocSize ( Ty ) , Align ) ; CCInfo . addLoc ( CCValAssign :: getMem ( ArgLocs . size ( ) , VT . getSimpleVT ( ) , Offset , VT . getSimpleVT ( ) , CCValAssign :: Full ) ) ; } } unsigned NumBytes = CCInfo . getAlignedCallFrameSize ( ) ; SDValue FINode ; if ( IsVarArg && NumBytes ) { int FI = MF . getFrameInfo ( ) . CreateStackObject ( NumBytes , Layout . getStackAlignment ( ) , false ) ; unsigned ValNo = <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( SDValue Arg : make_range ( OutVals . begin ( ) + NumFixedArgs , OutVals . end ( ) ) ) { assert ( ArgLocs [ ValNo ] . getValNo ( ) == ValNo && <STR_LIT> ) ; unsigned Offset = ArgLocs [ ValNo ++ ] . getLocMemOffset ( ) ; FINode = DAG . getFrameIndex ( FI , getPointerTy ( Layout ) ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , FINode , DAG . getConstant ( Offset , DL , PtrVT ) ) ; Chains . push_back ( DAG . getStore ( Chain , DL , Arg , Add , MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) , <NUM_LIT> ) ) ; } if ( ! Chains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ; } else if ( IsVarArg ) { FINode = DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ; } if ( Callee -> getOpcode ( ) == <STR_LIT> ) { GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Callee ) ; Callee = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , getPointerTy ( DAG . getDataLayout ( ) ) , GA -> getOffset ( ) ) ; Callee = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Callee ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; Ops . append ( OutVals . begin ( ) , IsVarArg ? OutVals . begin ( ) + NumFixedArgs : OutVals . end ( ) ) ; if ( IsVarArg ) Ops . push_back ( FINode ) ; SmallVector < EVT , <NUM_LIT> > InTys ;


<s> for ( auto iter = df_begin ( rootScope ) , end = df_end ( rootScope ) ; iter != end ; ++ iter ) { auto scope = * iter ; RAInfo & RI = RAInfos . at ( scope ) ; if ( ! scope -> isTopLevel ( ) ) { RI . Priv -> unifyWithParent ( * ( RAInfos . at ( scope -> getParent ( ) ) . Priv ) , spillLocCnt , scope -> isTopLevel ( ) ) ;

if ( ! RI . needsScopeSpill ( ) ) NoSpillScopes ++ ;


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : <ISA_LIT>TargetStreamer ( S ) , OS ( OS ) {


<s> if ( TCI . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ;


<s> static __inline qword si_rot ( qword a , qword b ) { return ( ( qword ) ( vec_rl ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) ( b ) ) ) ) ;


<s> const TargetFrameLowering * TFI = MF -> getTarget ( ) . getFrameLowering ( ) ;

return TFI -> hasFP ( * MF ) ? CSR_FP_SaveList : CSR_SaveList ;


<s> return ( ! flag_trapping_math && flag_unsafe_math_optimizations && ( ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_APPROX_RSQRT ) || flag_mrecip_low_precision_sqrt ) ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ResultTy = Extend -> getType ( ) ; if ( ResultTy -> getPrimitiveSizeInBits ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } } Value * Offsets ; Value * BasePtr = checkGEP ( Offsets , ResultTy , Ptr , Builder ) ; if ( ! BasePtr ) return nullptr ; int Scale = computeScale ( BasePtr -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) , OriginalTy -> getScalarSizeInBits ( ) ) ; if ( Scale == - <NUM_LIT> ) return nullptr ; Root = Extend ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ; if ( ! match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { ResultTy , BasePtr -> getType ( ) , Offsets -> getType ( ) , Mask -> getType ( ) } , { BasePtr , Offsets , Builder . getInt32 ( OriginalTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Builder . getInt32 ( Unsigned ) , Mask } ) ;

else return Builder . CreateIntrinsic ( <STR_LIT> , { ResultTy , BasePtr -> getType ( ) , Offsets -> getType ( ) } , { BasePtr , Offsets , Builder . getInt32 ( OriginalTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Builder . getInt32 ( Unsigned ) } ) ;


<s> return [ = ] ( const LegalityQuery & Query ) { const LLT Ty = Query . Types [ TypeIdx ] ; const LLT EltTy = Ty . getScalarType ( ) ;

return EltTy . getSizeInBits ( ) == <NUM_LIT> && Ty . getNumElements ( ) > <NUM_LIT> ;


<s> MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; auto NumBits = Info . TargetSize + Info . TargetOffset ; auto NumBytes = ( NumBits / <NUM_LIT> ) + ( ( NumBits % <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumBytes ; ++ i ) { uint8_t mask = ( ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ) ; Data [ Offset + i ] |= mask ;


<s> case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTNTPOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTPCREL ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOT ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_GOTOFF ; break ; case <STR_LIT> : RefKind = MCSymbolRefExpr :: VK_PLT ; break ; case <STR_LIT> : case <STR_LIT> : Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( MF . getPICBaseSymbol ( ) , Ctx ) , Ctx ) ; if ( MO . isJTI ( ) ) { assert ( MAI . doesSetDirectiveSuppressesReloc ( ) ) ; MCSymbol * Label = Ctx . createTempSymbol ( ) ; AsmPrinter . OutStreamer -> EmitAssignment ( Label , Expr ) ; Expr = MCSymbolRefExpr :: create ( Label , Ctx ) ; } break ;


<s> pat = GEN_FCN ( icode ) ( target , op0 ) ; if ( ! pat ) return NULL_RTX ;


<s> SDValue Op = Chain . getOperand ( i ) ; if ( Op == Load . getValue ( <NUM_LIT> ) ) { ChainCheck = true ; ChainOps . push_back ( Load . getOperand ( <NUM_LIT> ) ) ; continue ; } int LoadId = LoadNode -> getNodeId ( ) ; for ( SDNode :: use_iterator UI = Op . getNode ( ) -> use_begin ( ) , UE = UI -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI . getUse ( ) . getResNo ( ) != <NUM_LIT> ) continue ; if ( UI -> getNodeId ( ) > LoadId ) return false ; } ChainOps . push_back ( Op ) ;


<s> static unsigned HOST_WIDE_INT rs6000_asan_shadow_offset ( void ) { return ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ;


<s> static DecodeStatus DecodeUImm6Lsl2 ( MCInst & Inst , unsigned Value , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( Value << <NUM_LIT> ) ) ;


<s> auto it = StackModelComments . find ( MI ) ; if ( it != StackModelComments . end ( ) ) return it -> second ; it = StackModelComments . find ( nullptr ) ; assert ( it != StackModelComments . end ( ) ) ; return it -> second ;


<s> uint64_t TSFlags = MII . get ( Inst . getOpcode ( ) ) . TSFlags ;

if ( ( getForcedEncodingSize ( ) == <NUM_LIT> && ( TSFlags & <STR_LIT> ) ) || ( getForcedEncodingSize ( ) == <NUM_LIT> && ! ( TSFlags & <STR_LIT> ) ) ) return Match_InvalidOperand ;


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GPReg , GPRelNode ) ; } return getAddrNonPIC ( Op , DAG ) ; } if ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) return getAddrLocal ( Op , DAG , Has<ISA_LIT>64 ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( Op , DAG , <STR_LIT> , <STR_LIT> ) ;

return getAddrGlobal ( Op , DAG , Has<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressImmediate ( llvm :: GlobalValue * GV ) const {


<s> bool <ISA_LIT>InstrInfo :: mustBeLastInClause ( unsigned Opcode ) const { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> :


<s> MachineFunction & MF = B . getMF ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; B . setInstr ( MI ) ; if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS || AS == <ISA_LIT>AS :: REGION_ADDRESS ) { if ( ! MFI -> isEntryFunction ( ) ) { const Function & Fn = MF . getFunction ( ) ; DiagnosticInfoUnsupported BadLDSDecl ( Fn , <STR_LIT> , MI . getDebugLoc ( ) ) ; Fn . getContext ( ) . diagnose ( BadLDSDecl ) ; } if ( ! <ISA_LIT>TargetLowering :: hasDefinedInitializer ( GV ) ) { const <ISA_LIT>TargetLowering * TLI = ST . getTargetLowering ( ) ; if ( ! TLI -> shouldUseLDSConstAddress ( GV ) ) { MI . getOperand ( <NUM_LIT> ) . setTargetFlags ( <ISA_LIT>InstrInfo :: MO_ABS32_LO ) ; return true ; } B . buildConstant ( DstReg , MFI -> allocateLDSGlobal ( B . getDataLayout ( ) , * GV ) ) ; MI . eraseFromParent ( ) ; return true ; } const Function & Fn = MF . getFunction ( ) ; DiagnosticInfoUnsupported BadInit ( Fn , <STR_LIT> , MI . getDebugLoc ( ) ) ;

Fn . getContext ( ) . diagnose ( BadInit ) ;


<s> static bool isValidIndexedLoad ( const LoadSDNode * LD ) { <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( AM != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> ) return false ; EVT VT = LD -> getMemoryVT ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : if ( cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getZExtValue ( ) != <NUM_LIT> ) return false ; break ; case <STR_LIT> : if ( cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getZExtValue ( ) != <NUM_LIT> ) return false ; break ;


<s> void print<ISA_LIT>Operands ( OperandVector & Operands ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;

for ( size_t i = <NUM_LIT> ; i < Operands . size ( ) ; i ++ ) {


<s> bool <ISA_LIT>MachineFunctionInfo :: haveFreeLanesForSGPRSpill ( const MachineFunction & MF , unsigned NumNeed ) const { const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned WaveSize = ST . getWavefrontSize ( ) ;

return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs . size ( ) ;


<s> if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckh ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckl ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckl ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 ) ; ShuffleVectorSDNode :: commuteMask ( Unpckh ) ; if ( isShuffleEquivalent ( V1 , V2 , Mask , Unpckh ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 ) ; return SDValue ( ) ;


<s> while ( GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; while ( GET_CODE ( y ) == SUBREG ) y = SUBREG_REG ( y ) ;

if ( GET_CODE ( x ) == REG && GET_CODE ( y ) == REG && REGNO ( x ) == REGNO ( y ) ) return <NUM_LIT> ;


<s> if ( CPU == <STR_LIT> ) report_fatal_error ( Twine ( <STR_LIT> ) + ( TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ;

return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ;


<s> SDValue Ops [ <NUM_LIT> ] ; if ( is32Bit ( VT ) ) lowerMUL_LOHI32 ( DAG , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; else if ( Subtarget . hasMiscellaneousExtensions2 ( ) ) lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; else { SDValue C63 = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue LL = Op . getOperand ( <NUM_LIT> ) ; SDValue RL = Op . getOperand ( <NUM_LIT> ) ; SDValue LH = DAG . getNode ( <STR_LIT> , DL , VT , LL , C63 ) ; SDValue RH = DAG . getNode ( <STR_LIT> , DL , VT , RL , C63 ) ; lowerGR128Binary ( DAG , DL , VT , <STR_LIT> , LL , RL , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;

SDValue NegLLTimesRH = DAG . getNode ( <STR_LIT> , DL , VT , LL , RH ) ;


<s> } else if ( MI . getOpcode ( ) == <STR_LIT> ) { } else {


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = FPR32DecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return Success ;


<s> Op -> Mem . Base = Base ; Op -> Mem . OffsetReg = offsetReg ; Op -> Mem . Off = <NUM_LIT> ;


<s> GShlE_match < ADDR_P , CARRYIN_P > m_GShlE ( Register & CarryOut , const ADDR_P & Addr , const CARRYIN_P & CarryIn ) { return { CarryOut , Addr , CarryIn } ;


<s> if ( arity > MAX_ARGS ) return NULL_RTX ; insn_op = & insn_data [ icode ] . operand [ arity + nonvoid ] ; op [ arity ] = expand_expr ( arg , NULL_RTX , insn_op -> mode , EXPAND_NORMAL ) ; if ( ! ( * insn_op -> predicate ) ( op [ arity ] , insn_op -> mode ) ) op [ arity ] = copy_to_mode_reg ( insn_op -> mode , op [ arity ] ) ; arity ++ ;


<s> if ( Reg ) { State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return true ; }


<s> LoadSDNode * LD = cast < LoadSDNode > ( Op . getNode ( ) ) ; EVT MemVT = LD -> getMemoryVT ( ) ; assert ( ( MemVT == <STR_LIT> || MemVT == <STR_LIT> || MemVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( MemVT == Op . getValueType ( ) ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( LD -> isUnindexed ( ) && <STR_LIT> ) ; SDLoc dl ( Op ) ; SDValue Load = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , LD -> getChain ( ) , LD -> getBasePtr ( ) , EVT :: getIntegerVT ( * DAG . getContext ( ) , MemVT . getSizeInBits ( ) ) , LD -> getMemOperand ( ) ) ; SDValue Val = Load ; if ( DAG . getDataLayout ( ) . isBigEndian ( ) ) Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load ) , DAG . getConstant ( <NUM_LIT> - MemVT . getSizeInBits ( ) , dl , <STR_LIT> ) ) ; SDValue Pred = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val ) ;

if ( MemVT != <STR_LIT> ) Pred = DAG . getNode ( <STR_LIT> , dl , MemVT , Pred , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> case <STR_LIT> : { int Idx = Instr . findRegisterUseOperandIdx ( <STR_LIT> ) ; assert ( Idx >= <NUM_LIT> ) ; return static_cast < <STR_LIT> > ( Instr . getOperand ( Idx - <NUM_LIT> ) . getImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { int Idx = Instr . findRegisterUseOperandIdx ( <STR_LIT> ) ; assert ( Idx >= <NUM_LIT> ) ;


<s> printOperand ( MI , Op + <NUM_LIT> ) ; O << ':' ; } printLeaMemReference ( MI , Op ) ;


<s> selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>5 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R3 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R5 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R6 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R3 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R5 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R6 ( ) ; break ; case <STR_LIT> : setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetCRC ( ) ; break ; case <STR_LIT> : setFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSetVirt ( ) ; break ; case <STR_LIT> :


<s> int64_t ObjectOffset = MFI . getObjectOffset ( FI ) ; bool isFixed = MFI . isFixedObjectIndex ( FI ) ; bool isSVE = MFI . getStackID ( FI ) == TargetStackID :: SVEVector ; return resolveFrameOffsetReference ( MF , ObjectOffset , isFixed , isSVE , FrameReg , PreferFP , ForSimm ) ;


<s> unsigned Byte = ( ( Elem * FromBytesPerElement ) % <STR_LIT> + ( FromBytesPerElement - BytesPerElement ) ) ; while ( Op . getNode ( ) ) { if ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; else if ( Op . getOpcode ( ) == <STR_LIT> && Op . hasOneUse ( ) ) { SmallVector < int , <STR_LIT> > OpBytes ; getVPermMask ( cast < ShuffleVectorSDNode > ( Op ) , OpBytes ) ; int NewByte ; if ( ! getShuffleInput ( OpBytes , Byte , BytesPerElement , NewByte ) ) break ; if ( NewByte < <NUM_LIT> ) { addUndef ( ) ; return ; } Op = Op . getOperand ( unsigned ( NewByte ) / <STR_LIT> ) ;

Byte = unsigned ( NewByte ) % <STR_LIT> ;


<s> <ISA_LIT>CallLowering :: <ISA_LIT>CallLowering ( const <ISA_LIT>TargetLowering & TLI , <ISA_LIT>GlobalRegistry * GR ) : CallLowering ( & TLI ) , GR ( GR ) {


<s> uint64_t OffsetVal = Offset -> getZExtValue ( ) ; unsigned ScalarSizeInBytes = MemVT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( OffsetVal % ScalarSizeInBytes || OffsetVal / ScalarSizeInBytes > <NUM_LIT> ) return ;

Opcode = IsGather ? <STR_LIT> : <STR_LIT> ;


<s> if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) return R ; return combineSetCCAtomicArith ( EFLAGS , CC , DAG ) ;


<s> unsigned getArgumentStackToRestore ( ) const {


<s> int64_t <ISA_LIT>RegisterInfo :: getMUBUFInstrOffset ( const MachineInstr * MI ) const { assert ( <ISA_LIT>InstrInfo :: isMUBUF ( * MI ) ) ; int OffIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: offset ) ; return MI -> getOperand ( OffIdx ) . getImm ( ) ;


<s> void <ISA_LIT>GenPredicate :: collectPredicateGPR ( MachineFunction & MF ) { for ( MachineFunction :: iterator A = MF . begin ( ) , Z = MF . end ( ) ; A != Z ; ++ A ) { MachineBasicBlock & B = * A ; for ( MachineBasicBlock :: iterator I = B . begin ( ) , E = B . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case TargetOpcode :: COPY : if ( isPredReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Register RD = MI -> getOperand ( <NUM_LIT> ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RD . R ) ) PredGPRs . insert ( RD ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerINSERT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; if ( useSVEForFixedLengthVectorVT ( Op . getValueType ( ) ) ) return LowerFixedLengthInsertVectorElt ( Op , DAG ) ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CI || CI -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ;

if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ;


<s> unsigned OpReg = getRegForValue ( V ) ; if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ; }


<s> if ( & UserMBB -> back ( ) == UserMI ) assert ( BBHasFallthrough ( UserMBB ) && <STR_LIT> ) ; NewMBB = llvm :: next ( MachineFunction :: iterator ( UserMBB ) ) ; int UncondBr = isThumb ? ( ( isThumb2 ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; int delta = isThumb1 ? <NUM_LIT> : <NUM_LIT> ; BBSizes [ UserMBB -> getNumber ( ) ] += delta ; AdjustBBOffsetsAfter ( UserMBB , delta ) ; } else { unsigned BaseInsertOffset = UserOffset + U . MaxDisp - <NUM_LIT> ; if ( BaseInsertOffset >= BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] ) BaseInsertOffset = BBOffsets [ UserMBB -> getNumber ( ) + <NUM_LIT> ] - ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; unsigned EndInsertOffset = BaseInsertOffset + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = <NUM_LIT> ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = llvm :: next ( MI ) ) { if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! OffsetIsInRange ( Offset , EndInsertOffset , U . MaxDisp , U . NegOk , U . IsSoImm ) ) { BaseInsertOffset -= ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; EndInsertOffset -= ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; } EndInsertOffset += CPUsers [ CPUIndex ] . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) LastIT = MI ;


<s> void addUse ( long pos ) { uses . set ( pos ) ;


<s> if ( StackBumpBytes >= <NUM_LIT> || windowsRequiresStackProbe ( MF , StackBumpBytes ) ) return false ; if ( MFI . hasVarSizedObjects ( ) ) return false ; if ( RegInfo -> needsStackRealignment ( MF ) ) return false ; if ( canUseRedZone ( MF ) ) return false ; return true ;


<s> static DecodeStatus DecodeAdrInstruction ( MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; imm |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; if ( imm & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) imm |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ;

if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm , Addr , Fail , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: createImm ( imm ) ) ;


<s> if ( STI . hasFeature ( <STR_LIT> ) && getLexer ( ) . is ( AsmToken :: LBrac ) ) { eatThatToken ( Operands ) ; if ( ! tryParseExpr ( Operands , <STR_LIT> ) ) { FirstTime = false ; continue ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Lex ( ) ; continue ; } StringRef TokName ; SMLoc TokLoc ; TokName = getLexer ( ) . getTok ( ) . getString ( ) ;

TokLoc = getLexer ( ) . getTok ( ) . getLoc ( ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCInstLowering ( * this ) {


<s> for ( unsigned i = <NUM_LIT> , e = args . size ( ) ; i != e ; ++ i ) { StringRef piece ( * args [ i ] ) ; if ( ! s . startswith ( piece ) ) return false ; s = s . substr ( piece . size ( ) ) ; StringRef :: size_type pos = s . find_first_not_of ( <STR_LIT> ) ; if ( pos == <NUM_LIT> ) return false ; s = s . substr ( pos ) ;


<s> uint64_t Disp = Imm & <NUM_LIT> ; assert ( Base < <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Disp << <NUM_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( RRegsNoR0 [ Base ] ) ) ; return MCDisassembler :: Success ;


<s> <ISA_LIT>RegisterInfo :: ~ <ISA_LIT>RegisterInfo ( ) {


<s> void <ISA_LIT>InstPrinter :: printNegHi ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {

printPackedModifier ( MI , <STR_LIT> , <STR_LIT> , O ) ;


<s> unsigned getInlineAsmMemConstraint ( StringRef ConstraintCode ) const override { if ( ConstraintCode . size ( ) == <NUM_LIT> ) { switch ( ConstraintCode [ <NUM_LIT> ] ) { default : break ;


<s> return const0_rtx ; case IA64_BUILTIN_INFQ : case IA64_BUILTIN_HUGE_VALQ : { machine_mode target_mode = TYPE_MODE ( TREE_TYPE ( exp ) ) ; REAL_VALUE_TYPE inf ; rtx tmp ; real_inf ( & inf ) ; tmp = const_double_from_real_value ( inf , target_mode ) ; tmp = validize_mem ( force_const_mem ( target_mode , tmp ) ) ; if ( target == <NUM_LIT> ) target = gen_reg_rtx ( target_mode ) ; emit_move_insn ( target , tmp ) ; return target ; }


<s> assert ( MI -> getOperand ( OpNo ) . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; printOperand ( MI , OpNo , O ) ; if ( OffsetOp . isImm ( ) ) { int64_t Offset = OffsetOp . getImm ( ) ; if ( Offset >= <NUM_LIT> ) O << '+' ; O << Offset ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , InstrInfo ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) , InstrItins ( & Subtarget . getInstrItineraryData ( ) ) {


<s> bool isFMAFasterThanFMulAndFAdd ( const MachineFunction & MF , EVT ) const override { return true ;


<s> static DecodeStatus DecodeFPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {

if ( RegNo > array_lengthof ( FPR64DecoderTable ) ) return MCDisassembler :: Fail ;


<s> EVT ShVT = <STR_LIT> ; unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG . getConstant ( NumBits , TLI . getShiftAmountTy ( ) ) ) ) ;


<s> break ; } case <STR_LIT> : MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : MIB . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( I . getOperand ( <NUM_LIT> ) . getImm ( ) | ( 'U' << <NUM_LIT> ) ) ; break ; } I . eraseFromParent ( ) ;


<s> bool AMDGPUDAGToDAGISel :: isDSOffsetLegal ( const SDValue & Base , unsigned Offset , unsigned OffsetBits ) const { const AMDGPUSubtarget & ST = TM . getSubtarget < AMDGPUSubtarget > ( ) ; if ( ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) || ( OffsetBits == <NUM_LIT> && ! isUInt < <NUM_LIT> > ( Offset ) ) ) return false ; if ( ST . getGeneration ( ) >= AMDGPUSubtarget :: SEA_ISLANDS ) return true ; return CurDAG -> SignBitIsZero ( Base ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Val = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Val ) ;


<s> assert ( ! ( NeedsWinCFI && ( NumPredicateVectors || NumDataVectors ) ) && <STR_LIT> ) ; if ( NumDataVectors ) { emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , NumDataVectors , <STR_LIT> , TII , Flag , NeedsWinCFI , nullptr , EmitCFAOffset , CFAOffset , FrameReg ) ; CFAOffset += StackOffset :: getScalable ( - NumDataVectors * <NUM_LIT> ) ; SrcReg = DestReg ; } if ( NumPredicateVectors ) { assert ( DestReg != <STR_LIT> && <STR_LIT> ) ; emitFrameOffsetAdj ( MBB , MBBI , DL , DestReg , SrcReg , NumPredicateVectors , <STR_LIT> , TII , Flag , NeedsWinCFI , nullptr , EmitCFAOffset , CFAOffset , FrameReg ) ; }