<s> SDValue <ISA_LIT>TargetLowering :: get<ISA_LIT>Cmp ( SDValue LHS , SDValue RHS , <STR_LIT> CC , SDValue & <ISA_LIT>cc , SelectionDAG & DAG , const SDLoc & dl ) const { if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS . getNode ( ) ) ) { unsigned C = RHSC -> getZExtValue ( ) ; if ( ! isLegalICmpImmediate ( ( int32_t ) C ) ) { switch ( CC ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C - <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C - <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , dl , <STR_LIT> ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( C != <NUM_LIT> && isLegalICmpImmediate ( C + <NUM_LIT> ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; RHS = DAG . getConstant ( C + <NUM_LIT> , dl , <STR_LIT> ) ; } break ; } } } else if ( ( <STR_LIT> ( LHS . getOpcode ( ) ) != <STR_LIT> ) && ( <STR_LIT> ( RHS . getOpcode ( ) ) == <STR_LIT> ) ) {


<s> case AMDGPU :: <ISA_LIT>_SPILL_S64_SAVE : case AMDGPU :: <ISA_LIT>_SPILL_S64_RESTORE : return <NUM_LIT> ; case AMDGPU :: <ISA_LIT>_SPILL_S32_RESTORE : return <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> SDValue Tmp2 = ST -> getBasePtr ( ) ; SDValue Tmp3 = ST -> getValue ( ) ; assert ( Tmp3 . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ;

Tmp3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp3 ) ;


<s> const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; const LLT s1 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s8 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) for ( auto Ty : { s8 , s16 , s32 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned Op : { G_UADDE } ) { setAction ( { Op , s32 } , Legal ) ; setAction ( { Op , <NUM_LIT> , s1 } , Legal ) ; } for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } , Legal ) ; setAction ( { G_GEP , p0 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { G_GEP , <NUM_LIT> , Ty } , WidenScalar ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { TargetOpcode :: G_CONSTANT , Ty } , Legal ) ; setAction ( { TargetOpcode :: G_CONSTANT , s1 } , WidenScalar ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , NarrowScalar ) ; setAction ( { G_ZEXT , s32 } , Legal ) ; setAction ( { G_SEXT , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) {

setAction ( { G_ZEXT , <NUM_LIT> , Ty } , Legal ) ;


<s> <ISA_LIT>_LOG ( <STR_LIT> ) ; return false ;


<s> SDValue Tgt = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( Op , DAG , Flag ) ) ;

return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Tgt , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ;


<s> Op . addRegOperands ( Inst , <NUM_LIT> ) ; if ( IsAtomicReturn && i == FirstOperandIdx ) Op . addRegOperands ( Inst , <NUM_LIT> ) ; continue ; } if ( Op . isImm ( ) && Op . getImmTy ( ) == <ISA_LIT>Operand :: ImmTyNone ) { Op . addImmOperands ( Inst , <NUM_LIT> ) ; continue ; } HasLdsModifier = Op . isLDS ( ) ; if ( Op . isToken ( ) ) { continue ; } assert ( Op . isImm ( ) ) ; OptionalIdx [ Op . getImmTy ( ) ] = i ; } if ( IsLdsOpcode && ! HasLdsModifier ) {

int NoLdsOpcode = <STR_LIT> ( Inst . getOpcode ( ) ) ;


return ( int64x1_t ) { __builtin_aarch64_sqabsdi ( __a [ <NUM_LIT> ] ) } ;


<s> if ( ! isTailCall ) { for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } } if ( isTailCall ) { InFlag = SDValue ( ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } InFlag = SDValue ( ) ; } if ( flag_aligned_memcpy ) { const char * MemcpyName = <STR_LIT> ; Callee = DAG . getTargetExternalSymbol ( MemcpyName , getPointerTy ( ) ) ; flag_aligned_memcpy = false ; } else if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , getPointerTy ( ) ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; } if ( InFlag . getNode ( ) ) { Ops . push_back ( InFlag ) ; } if ( isTailCall ) return DAG . getNode ( <STR_LIT> , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , dl , DAG , InVals , OutVals , Callee ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target ( ) ) ;

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>64Target ( ) ) ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const { assert ( <NUM_LIT> && <STR_LIT> ) ; return false ;


<s> rtx scale ; rtx temp2 ; temp1 = gen_reg_rtx ( SImode ) ; temp2 = gen_reg_rtx ( SImode ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) != CONST_INT ) { scale = gen_reg_rtx ( SImode ) ; emit_insn ( gen_zero_extendpsisi2 ( scale , operands [ <NUM_LIT> ] ) ) ; } else scale = copy_to_mode_reg ( SImode , operands [ <NUM_LIT> ] ) ;

emit_insn ( gen_zero_extendpsisi2 ( temp1 , operands [ <NUM_LIT> ] ) ) ;


<s> distance = increase_distance ( prev , next , distance ) ; if ( insn_uses_reg_mem ( regno , next ) ) { * found = true ; return distance ; } if ( insn_defines_reg ( regno , INVALID_REGNUM , next ) ) { * redefined = true ; return - <NUM_LIT> ; } prev = next ; } if ( next == BB_END ( bb ) ) break ;


<s> if ( ! Register :: isVirtualRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return nullptr ; MachineInstr * Def = MRI -> getVRegDef ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> MachineBasicBlock * SecondInsertedMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ThisMBB -> getIterator ( ) ; F -> insert ( It , FirstInsertedMBB ) ; F -> insert ( It , SecondInsertedMBB ) ; F -> insert ( It , SinkMBB ) ; FirstInsertedMBB -> addLiveIn ( <STR_LIT> ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; if ( ! SecondCascadedCMOV . killsRegister ( <STR_LIT> ) && ! checkAndUpdateEFLAGSKill ( SecondCascadedCMOV , ThisMBB , TRI ) ) { SecondInsertedMBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( FirstCMOV ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( FirstInsertedMBB ) ;


<s> default : assert ( ! <STR_LIT> ) ; return - <NUM_LIT> ; } } if ( TargetFlags & <STR_LIT> ) { OpTableIdx = <NUM_LIT> ; } else if ( TargetFlags & <STR_LIT> ) { OpTableIdx = <NUM_LIT> ; } else { assert ( ( TargetFlags & <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; OpTableIdx = <NUM_LIT> ; }

return <STR_LIT> [ OpTableIdx ] [ Op ] ;


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> void EmitValueImpl ( const MCExpr * Value , unsigned Size , const SMLoc & Loc ) override { if ( const MCSymbolRefExpr * SRE = dyn_cast_or_null < MCSymbolRefExpr > ( Value ) ) if ( SRE -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL && ! ( Size == <NUM_LIT> ) ) getContext ( ) . FatalError ( Loc , <STR_LIT> ) ; EmitDataMappingSymbol ( ) ;

MCELFStreamer :: EmitValueImpl ( Value , Size ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ValReg ) . addReg ( ValReg ) . addReg ( ShamtReg ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex ) const { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {

FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> <ISA_LIT>_MC :: InitLLVM2SEHRegisterMapping ( this ) ; const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Is64Bit = Subtarget -> is64Bit ( ) ; IsWin64 = Subtarget -> isTargetWin64 ( ) ; if ( Is64Bit ) { SlotSize = <NUM_LIT> ; StackPtr = <STR_LIT> ; FramePtr = <STR_LIT> ; } else { SlotSize = <NUM_LIT> ; StackPtr = <STR_LIT> ; FramePtr = <STR_LIT> ;


<s> static DecodeStatus DecodeDPR_VFP2RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) {

if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> continue ; } PHINode * PN = cast < PHINode > ( D -> front ( ) ) ; Instruction * BEInst = D -> back ( ) ; int Iters = D -> iterations ( ) ; BasicBlock * BB = PN -> getParent ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * PN << <STR_LIT> ) ; SmallVector < Instruction * , <NUM_LIT> > PNUsers ; for ( auto UI = PN -> use_begin ( ) , E = PN -> use_end ( ) ; UI != E ; ++ UI ) { Use & U = * UI ; Instruction * User = cast < Instruction > ( U . getUser ( ) ) ; if ( User -> getParent ( ) != BB ) continue ; if ( ReplacedInsts . count ( User ) ) { LLVM_DEBUG ( dbgs ( ) << * User << <STR_LIT> ) ; continue ; } if ( isa < PHINode > ( User ) ) continue ; if ( User -> mayHaveSideEffects ( ) ) continue ; if ( ! canReplace ( User ) ) continue ;


<s> initialize<ISA_LIT>LowerKernelCallsPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> unsigned BaseIdx = <ISA_LIT>Subtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG - <NUM_LIT> - <NUM_LIT> ; unsigned BaseReg ( <STR_LIT> . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , <STR_LIT> , & <STR_LIT> ) ; } if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { return <STR_LIT> ;


<s> if ( PHI -> getNumIncomingValues ( ) != <NUM_LIT> ) return false ; if ( PHI -> getIncomingValue ( <NUM_LIT> ) == I ) { EntryBB = PHI -> getIncomingBlock ( <NUM_LIT> ) ; BackEdgeBB = PHI -> getIncomingBlock ( <NUM_LIT> ) ;


<s> SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . getOpcode ( ) == <STR_LIT> && ! VT . isVector ( ) ) { SDValue Vec = Src . getOperand ( <NUM_LIT> ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) { SDValue Elt0 = Vec . getOperand ( <NUM_LIT> ) ; EVT EltVT = Elt0 . getValueType ( ) ; if ( VT . getFixedSizeInBits ( ) <= EltVT . getFixedSizeInBits ( ) ) { if ( EltVT . isFloatingPoint ( ) ) { Elt0 = DAG . getNode ( <STR_LIT> , SL , EltVT . changeTypeToInteger ( ) , Elt0 ) ; } return DAG . getNode ( <STR_LIT> , SL , VT , Elt0 ) ; } } } if ( Src . getOpcode ( ) == <STR_LIT> && ! VT . isVector ( ) ) { if ( auto K = isConstOrConstSplat ( Src . getOperand ( <NUM_LIT> ) ) ) { if ( <NUM_LIT> * K -> getZExtValue ( ) == Src . getValueType ( ) . getScalarSizeInBits ( ) ) { SDValue BV = stripBitcast ( Src . getOperand ( <NUM_LIT> ) ) ; if ( BV . getOpcode ( ) == <STR_LIT> && BV . getValueType ( ) . getVectorNumElements ( ) == <NUM_LIT> ) { SDValue SrcElt = BV . getOperand ( <NUM_LIT> ) ; EVT SrcEltVT = SrcElt . getValueType ( ) ; if ( SrcEltVT . isFloatingPoint ( ) ) { SrcElt = DAG . getNode ( <STR_LIT> , SL , SrcEltVT . changeTypeToInteger ( ) , SrcElt ) ; } return DAG . getNode ( <STR_LIT> , SL , VT , SrcElt ) ; } } } } if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> ) { EVT SrcVT = Src . getValueType ( ) ; if ( SrcVT . getScalarSizeInBits ( ) > <NUM_LIT> && ( Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> || Src . getOpcode ( ) == <STR_LIT> ) ) {

SDValue Amt = Src . getOperand ( <NUM_LIT> ) ;


<s> static const char * get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return cfun -> machine -> some_ld_name ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , get_some_local_dynamic_name_1 , <NUM_LIT> ) ) return cfun -> machine -> some_ld_name ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & Subtarget ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( Subtarget ) {


<s> StoreSDNode * ST = cast < StoreSDNode > ( N ) ; <STR_LIT> AM = ST -> getAddressingMode ( ) ; if ( AM != <STR_LIT> ) { return SelectIndexedStore ( ST , dl ) ; } return SelectBaseOffsetStore ( ST , dl ) ;


<s> Uses . clear ( ) ; TrackDefUses ( MI , Defs , Uses , TRI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; MachineInstr * LastITMI = MI ; MachineBasicBlock :: iterator InsertPos = MIB . getInstr ( ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; if ( ! restrictIT ) { for ( ; MBBI != E && Pos && ( ! MI -> isBranch ( ) && ! MI -> isReturn ( ) ) ; ++ MBBI ) { if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getITInstrPredicate ( * NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( NCC & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ClearKillFlags ( MI , Uses ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos ; } } Mask |= ( <NUM_LIT> << Pos ) ; Mask |= ( CC & <NUM_LIT> ) << <NUM_LIT> ; MIB . addImm ( Mask ) ; LastITMI -> findRegisterUseOperand ( <STR_LIT> ) -> setIsKill ( ) ; finalizeBundle ( MBB , InsertPos . getInstrIterator ( ) , ++ LastITMI -> getIterator ( ) ) ; Modified = true ;


<s> if ( context -> br_loc [ <NUM_LIT> ] && * context -> br_loc [ <NUM_LIT> ] != context -> rp ) { fs -> curr . reg [ UNW_REG_RP ] . where = UNW_WHERE_BR ; fs -> curr . reg [ UNW_REG_RP ] . when = - <NUM_LIT> ; fs -> curr . reg [ UNW_REG_RP ] . val = <NUM_LIT> ; goto success ; } return _URC_END_OF_STACK ; success : return _URC_NO_REASON ; return _URC_END_OF_STACK ; } context -> region_start = ent -> start_offset + segment_base ; fs -> when_target = ( context -> rp - context -> region_start ) / <NUM_LIT> * <NUM_LIT> ; unw = ( unsigned long * ) ( ent -> info_offset + segment_base ) ; header = * unw ; length = UNW_LENGTH ( header ) ; if ( UNW_FLAG_EHANDLER ( header ) | UNW_FLAG_UHANDLER ( header ) ) { fs -> personality = * ( _Unwind_Personality_Fn * ) ( unw [ length + <NUM_LIT> ] + context -> gp ) ; context -> lsda = unw + length + <NUM_LIT> ; } insn = ( unsigned char * ) ( unw + <NUM_LIT> ) ; insn_end = ( unsigned char * ) ( unw + <NUM_LIT> + length ) ; while ( ! fs -> done && insn < insn_end ) insn = unw_decode ( insn , fs -> in_body , fs ) ; free_label_states ( fs -> labeled_states ) ; free_state_stack ( & fs -> curr ) ; if ( reg_state_alloced || labeled_state_alloced ) abort ( ) ; if ( fs -> when_target > fs -> epilogue_start ) { struct unw_reg_info * r ; fs -> curr . reg [ UNW_REG_PSP ] . where = UNW_WHERE_NONE ; fs -> curr . reg [ UNW_REG_PSP ] . val = <NUM_LIT> ;

for ( r = fs -> curr . reg ; r < fs -> curr . reg + UNW_NUM_REGS ; ++ r ) if ( ( r -> where == UNW_WHERE_PSPREL && r -> val <= <NUM_LIT> ) || r -> where == UNW_WHERE_SPREL ) r -> where = UNW_WHERE_NONE ;


return isMoveWideImm ( <NUM_LIT> , PermittedModifiers , NumModifiers ) ;


<s> It ++ ; It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; It ++ ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> if ( Subtarget . is<ISA_LIT>64 ( ) ) { FuncInfo -> addMustSaveCR ( Reg ) ; } else { CRSpilled = true ; FuncInfo -> setSpillsCR ( ) ; CRMIB = BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Reg , RegState :: ImplicitKill ) ; MBB . insert ( MI , CRMIB ) ; MBB . insert ( MI , addFrameReference ( BuildMI ( * MF , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) , CSI [ i ] . getFrameIdx ( ) ) ) ; } } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) && Size > <NUM_LIT> ) if ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> >= ConstpoolPromotionMaxTotal ) return SDValue ( ) ; if ( ! allUsersAreInFunction ( GVar , & F ) ) return SDValue ( ) ; if ( RequiredPadding != <NUM_LIT> ) { StringRef S = CDAInit -> getAsString ( ) ; SmallVector < uint8_t , <NUM_LIT> > V ( S . size ( ) ) ; std :: copy ( S . bytes_begin ( ) , S . bytes_end ( ) , V . begin ( ) ) ; while ( RequiredPadding -- ) V . push_back ( <NUM_LIT> ) ; Init = ConstantDataArray :: get ( * DAG . getContext ( ) , V ) ; } auto CPVal = <ISA_LIT>ConstantPoolConstant :: Create ( GVar , Init ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPVal , PtrVT , Align ( <NUM_LIT> ) ) ; if ( ! AFI -> getGlobalsPromotedToConstantPool ( ) . count ( GVar ) ) { AFI -> markGlobalAsPromotedToConstantPool ( GVar ) ; AFI -> setPromotedConstpoolIncrease ( AFI -> getPromotedConstpoolIncrease ( ) + PaddedSize - <NUM_LIT> ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) {


<s> if ( isa < ScalableVectorType > ( Ty ) ) return AM . HasBaseReg && ! AM . BaseOffs && ! AM . Scale ; uint64_t NumBytes = <NUM_LIT> ; if ( Ty -> isSized ( ) ) { uint64_t NumBits = DL . getTypeSizeInBits ( Ty ) ; NumBytes = NumBits / <NUM_LIT> ; if ( ! isPowerOf2_64 ( NumBits ) ) NumBytes = <NUM_LIT> ; } if ( ! AM . Scale ) { int64_t Offset = AM . BaseOffs ; if ( isInt < <NUM_LIT> > ( Offset ) ) return true ;


<s> O << format ( <STR_LIT> PRIu8 <STR_LIT> PRIu8 <STR_LIT> PRIu8 <STR_LIT> PRIu8 <STR_LIT> , U . Byte [ <NUM_LIT> ] , U . Byte [ <NUM_LIT> ] , U . Byte [ <NUM_LIT> ] , U . Byte [ <NUM_LIT> ] ) ; return ; } printOperand ( MI , OpNo , O ) ;


<s> vmlsq_s8 ( int8x16_t a , int8x16_t b , int8x16_t c ) { int8x16_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result ;


<s> assert ( ConstraintCode == 'm' && <STR_LIT> ) ; SDValue Base , Offset , Opc ; if ( ! SelectAddrMode2 ( Op , Op , Base , Offset , Opc ) ) return true ; OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; OutOps . push_back ( Opc ) ;


<s> case Instruction :: Or : case Instruction :: Xor : case Instruction :: Mul : return false ; case Instruction :: Add : return ScalarBits * VTy -> getNumElements ( ) >= <NUM_LIT> ; case Instruction :: ICmp : return ( ScalarBits < <NUM_LIT> ) && ( ScalarBits * VTy -> getNumElements ( ) >= <NUM_LIT> ) ; case Instruction :: FCmp : return Flags . NoNaN ; default : llvm_unreachable ( <STR_LIT> ) ; } return false ;


<s> unsigned NumWords = ( Size + <NUM_LIT> ) / <NUM_LIT> ; unsigned NewSize = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumWords ; ++ i ) {

if ( ! State -> AllocateReg ( ArgRegList , <NUM_LIT> ) ) {


<s> case <NUM_LIT> : if ( REGNO ( operands [ <NUM_LIT> ] ) > REGNO ( operands [ <NUM_LIT> ] ) ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; break ; case <NUM_LIT> : if ( REGNO ( operands [ <NUM_LIT> ] ) > REGNO ( operands [ <NUM_LIT> ] ) ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; if ( REGNO ( operands [ <NUM_LIT> ] ) > REGNO ( operands [ <NUM_LIT> ] ) ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; if ( REGNO ( operands [ <NUM_LIT> ] ) > REGNO ( operands [ <NUM_LIT> ] ) ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; break ;


<s> MachineInstr * MI = MBB -> getParent ( ) -> CreateMachineInstr ( TII -> get ( NewOpcode ) , DL ) ;


<s> bool <ISA_LIT>InstrInfo :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { bool AtStart = MI == MBB . begin ( ) ; MachineBasicBlock :: iterator BeforeI = MI ; if ( ! AtStart ) -- BeforeI ; for ( std :: vector < CalleeSavedInfo > :: const_iterator it = CSI . begin ( ) ; it != CSI . end ( ) ; ++ it ) { unsigned Reg = it -> getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; loadRegFromStackSlot ( MBB , MI , it -> getReg ( ) , it -> getFrameIdx ( ) , RC , & RI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; if ( AtStart ) MI = MBB . begin ( ) ; else { MI = BeforeI ; ++ MI ; } }


<s> expandArith ( unsigned OpLo , unsigned OpHi , Block & MBB , BlockIt MBBI ) { MachineInstr & MI = * MBBI ; unsigned SrcLoReg , SrcHiReg , DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( SrcReg , SrcLoReg , SrcHiReg ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , OpLo ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcLoReg , getKillRegState ( SrcIsKill ) ) ; auto MIBHI = buildMI ( MBB , MBBI , OpHi ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcHiReg , getKillRegState ( SrcIsKill ) ) ; if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MIBHI -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ; MI . eraseFromParent ( ) ; return true ;


<s> warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name ) ) ; * no_add_attrs = true ; } return NULL_TREE ;


<s> for ( MachineBasicBlock & B : llvm :: make_early_inc_range ( MF ) ) Changed |= processBlock ( B ) ; return Changed ;


<s> int RegNo = ( int ) ( DefIdx + <NUM_LIT> ) - DefMCID . getNumOperands ( ) + <NUM_LIT> ; if ( RegNo <= <NUM_LIT> ) return ItinData -> getOperandCycle ( DefClass , DefIdx ) ; int DefCycle ; if ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA7 ( ) ) { DefCycle = RegNo / <NUM_LIT> ; if ( DefCycle < <NUM_LIT> ) DefCycle = <NUM_LIT> ; DefCycle += <NUM_LIT> ; } else if ( Subtarget . isLikeA9 ( ) || Subtarget . isSwift ( ) ) { DefCycle = ( RegNo / <NUM_LIT> ) ; if ( ( RegNo % <NUM_LIT> ) || DefAlign < <NUM_LIT> ) ++ DefCycle ; DefCycle += <NUM_LIT> ;


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const {

return create<ISA_LIT>ELFObjectWriter ( OS , OSABI ) ;


<s> getDoubleRegPair ( DestDReg , EvenDestReg , OddDestReg ) ; getDoubleRegPair ( SrcDReg , EvenSrcReg , OddSrcReg ) ; const TargetInstrInfo * TII = TM . getInstrInfo ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; else assert ( <NUM_LIT> && <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( EvenDestReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( EvenSrcReg ) ; DOUT << <STR_LIT> << * MI ; if ( DestDReg != SrcDReg ) {

MI = BuildMI ( MBB , I , dl , TM . getInstrInfo ( ) -> get ( <STR_LIT> ) , OddDestReg ) . addReg ( OddSrcReg ) ;


<s> explicit <ISA_LIT>MCExpr ( const MCExpr * Expr , VariantKind Kind ) : Expr ( Expr ) , Kind ( Kind ) {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; uint32_t Enc = <STR_LIT> ( - CE -> getValue ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( Enc ) ) ;


<s> if ( Log2 ( Block . Alignment ) > Position . KnownBits ) { Position . Address += ( Block . Alignment . value ( ) - ( uint64_t ( <NUM_LIT> ) << Position . KnownBits ) ) ; Position . KnownBits = Log2 ( Block . Alignment ) ; } Position . Address = alignTo ( Position . Address , Block . Alignment ) ; Block . Address = Position . Address ; Position . Address += Block . Size ;


<s> if ( getParser ( ) . ParseExpression ( Val , End ) ) return ErrorOperand ( Start , <STR_LIT> ) ; InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Skip , OffsetOfLoc , <NUM_LIT> ) ) ; unsigned RegNo = is64BitMode ( ) ? <STR_LIT> : <STR_LIT> ;

return <STR_LIT> ( RegNo , Start , End , OffsetOfLoc ) ;


<s> if ( MCSym . getInt ( ) ) OutStreamer . emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . emitValue ( MCSymbolRefExpr :: create ( MCSym . getPointer ( ) , OutStreamer . getContext ( ) ) , <NUM_LIT> ) ;


<s> for ( auto & I : MBB ) AllInsns . push_back ( & I ) ; for ( auto I = AllInsns . begin ( ) , E = AllInsns . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = * I ; if ( ! MI || ! handledStoreType ( MI ) ) continue ;


<s> return ( int16x4_t ) __builtin_aarch64_ashrv4hi ( __a , __b ) ;


<s> dbgs ( ) << __func__ << <STR_LIT> << A << <STR_LIT> ; Size . getNode ( ) -> dump ( & DAG ) ; dbgs ( ) << <STR_LIT> ; } ) ; SDValue AC = DAG . getConstant ( A , dl , <STR_LIT> ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue AA = DAG . getNode ( <STR_LIT> , dl , VTs , Chain , Size , AC ) ;

DAG . ReplaceAllUsesOfValueWith ( Op , AA ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: tl45 > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) { Res = tryDecodeInst ( DecoderTableGFX9_DL64 , MI , QW , Address ) ; if ( Res ) break ; } } Bytes = Bytes_ . slice ( <NUM_LIT> , MaxInstBytesNum ) ; if ( Bytes . size ( ) < <NUM_LIT> ) break ; const uint32_t DW = eatBytes < uint32_t > ( Bytes ) ; Res = tryDecodeInst ( DecoderTableVI32 , MI , DW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTable<ISA_LIT>32 , MI , DW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTableGFX932 , MI , DW , Address ) ; if ( Res ) break ; if ( Bytes . size ( ) < <NUM_LIT> ) break ; const uint64_t QW = ( ( uint64_t ) eatBytes < uint32_t > ( Bytes ) << <NUM_LIT> ) | DW ; Res = tryDecodeInst ( DecoderTableVI64 , MI , QW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTable<ISA_LIT>64 , MI , QW , Address ) ; if ( Res ) break ; Res = tryDecodeInst ( DecoderTableGFX964 , MI , QW , Address ) ; } while ( false ) ; if ( Res && ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) ) { insertNamedMCOperand ( MI , MCOperand :: createImm ( <NUM_LIT> ) , <STR_LIT> :: src2_modifiers ) ; } if ( Res && ( MCII -> get ( MI . getOpcode ( ) ) . TSFlags & <STR_LIT> ) ) { Res = convertMIMGInst ( MI ) ; } if ( Res && IsSDWA ) Res = convertSDWAInst ( MI ) ;

Size = Res ? ( MaxInstBytesNum - Bytes . size ( ) ) : std :: min ( ( size_t ) <NUM_LIT> , Bytes_ . size ( ) ) ;


<s> MVT VT = N -> getValueType ( <NUM_LIT> ) . getSimpleVT ( ) ; unsigned ElSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ;

bool Result = ( Index * ElSize ) % <NUM_LIT> == <NUM_LIT> ;


<s> if ( ! I -> isDeclaration ( ) && ! I -> hasExternalLinkage ( ) ) continue ; MCSymbol * Sym = Mang -> getSymbol ( I ) ; if ( I -> isDeclaration ( ) && PAN :: isMemIntrinsic ( Sym -> getName ( ) ) ) continue ; const char * directive = I -> isDeclaration ( ) ? MAI -> getExternDirective ( ) : MAI -> getGlobalDirective ( ) ; OutStreamer . EmitRawText ( directive + Twine ( Sym -> getName ( ) ) ) ; OutStreamer . EmitRawText ( directive + Twine ( PAN :: getRetvalLabel ( Sym -> getName ( ) ) ) ) ;

OutStreamer . EmitRawText ( directive + Twine ( PAN :: getArgsLabel ( Sym -> getName ( ) ) ) ) ;


<s> MIB . addReg ( D0 ) ; MachineOperand VmSrc ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( VmSrc ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . addReg ( SrcReg , RegState :: Implicit | getKillRegState ( SrcIsKill ) ) ; TransferImpOps ( MI , MIB , MIB ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesAll ( ) ;


<s> if ( OptLevel >= CodeGenOpt :: Aggressive ) return true ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; unsigned Reg = cast < RegisterSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getReg ( ) ; EVT VT = Src . getValueType ( ) ; SDValue Copy ( DAG . getMachineNode ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , VT , Src ) , <NUM_LIT> ) ;

return Op . getNode ( ) -> getNumValues ( ) == <NUM_LIT> ? DAG . getCopyToReg ( Chain , DL , Reg , Copy ) : DAG . getCopyToReg ( Chain , DL , Reg , Copy , Op . getNumOperands ( ) == <NUM_LIT> ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ) ;


<s> if ( ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ; }


<s> for ( MachineInstr & MI : llvm :: reverse ( * B ) ) Instrs . push_back ( & MI ) ; for ( auto MI : Instrs ) { unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == TargetOpcode :: LIFETIME_START || Opc == TargetOpcode :: LIFETIME_END ) continue ; bool Store = false ; if ( MI -> isInlineAsm ( ) ) continue ; if ( ! MI -> isPHI ( ) && ! MI -> isSafeToMove ( nullptr , Store ) ) continue ; bool AllDead = true ; SmallVector < unsigned , <NUM_LIT> > Regs ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) ) continue ; Register R = Op . getReg ( ) ; if ( ! R . isVirtual ( ) || ! isDead ( R ) ) { AllDead = false ; break ;


<s> MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> isThreadLocal ( ) ? MMIMachO . getThreadLocalGVStubEntry ( MCSym ) : MMIMachO . getGVStubEntry ( MCSym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; return MCSym ; } else if ( Subtarget -> isTargetCOFF ( ) ) { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; bool IsIndirect = ( TargetFlags & <STR_LIT> ) ;

if ( ! IsIndirect ) return getSymbol ( GV ) ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {

return new <ISA_LIT>PassConfig ( this , PM ) ;


<s> SDValue Src0 = peekThroughBitcasts ( V . getOperand ( <NUM_LIT> ) ) ; SDValue Src1 = peekThroughBitcasts ( V . getOperand ( <NUM_LIT> ) ) ; unsigned SrcOpc0 = Src0 . getOpcode ( ) ; unsigned SrcOpc1 = Src1 . getOpcode ( ) ; EVT SrcVT0 = Src0 . getValueType ( ) ; EVT SrcVT1 = Src1 . getValueType ( ) ; if ( ! Src1 . isUndef ( ) && ( SrcVT0 != SrcVT1 || SrcOpc0 != SrcOpc1 ) ) return SDValue ( ) ; switch ( SrcOpc0 ) { case <STR_LIT> : { SDValue LHS = DAG . getBitcast ( VT , Src0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getBitcast ( VT , Src1 . isUndef ( ) ? Src1 : Src1 . getOperand ( <NUM_LIT> ) ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , V . getOperand ( <NUM_LIT> ) ) ; Res = DAG . getNode ( SrcOpc0 , DL , SrcVT0 , DAG . getBitcast ( SrcVT0 , Res ) ) ; return DAG . getBitcast ( VT , Res ) ; } case <STR_LIT> : if ( SrcVT0 == <STR_LIT> ) { uint64_t Mask = Src0 . getConstantOperandVal ( <NUM_LIT> ) ; if ( ( Mask & <NUM_LIT> ) != ( ( Mask >> <NUM_LIT> ) & <NUM_LIT> ) ) break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Src1 . isUndef ( ) || Src0 . getOperand ( <NUM_LIT> ) == Src1 . getOperand ( <NUM_LIT> ) ) { SDValue LHS = DAG . getBitcast ( VT , Src0 . getOperand ( <NUM_LIT> ) ) ; SDValue RHS = DAG . getBitcast ( VT , Src1 . isUndef ( ) ? Src1 : Src1 . getOperand ( <NUM_LIT> ) ) ;


<s> bool <STR_LIT> ( const MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; } if ( isCallIndirect ( MI . getOpcode ( ) ) ) return true ; if ( ! MI . isCall ( ) ) return false ; const MachineOperand & MO = MI . getOperand ( getCalleeOpNo ( MI . getOpcode ( ) ) ) ; assert ( MO . isGlobal ( ) ) ; const auto * F = dyn_cast < Function > ( MO . getGlobal ( ) ) ; if ( ! F ) return true ;

if ( F -> doesNotThrow ( ) ) return false ;


<s> changeComponent ( AM , IsBase , Op0 ) ; AM . Disp = TestDisp ; return true ; } return false ;


<s> return ( __m256i ) __builtin_ia32_pmovsxwd256_mask ( ( __v8hi ) __A , ( __v8si ) _mm256_setzero_si256 ( ) , ( __mmask8 ) __U ) ;


<s> } Register TmpReg ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i != e ; ++ i , Offset += EltSize ) { Register SubReg = NumSubRegs == <NUM_LIT> ? Register ( ValueReg ) : getSubReg ( ValueReg , getSubRegFromChannel ( i ) ) ; unsigned SOffsetRegState = <NUM_LIT> ; unsigned SrcDstRegState = getDefRegState ( ! IsStore ) ; if ( i + <NUM_LIT> == e ) { SOffsetRegState |= getKillRegState ( Scavenged ) ; SrcDstRegState |= getKillRegState ( IsKill ) ; } auto MIB = spillVGPRtoAGPR ( ST , MI , Index , i , SubReg , IsKill ) ; if ( ! MIB . getInstr ( ) ) { unsigned FinalReg = SubReg ; if ( hasAGPRs ( RC ) ) { if ( ! TmpReg ) { assert ( RS && <STR_LIT> ) ; TmpReg = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; RS -> setRegUsed ( TmpReg ) ; } if ( IsStore ) BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpReg ) . addReg ( SubReg , getKillRegState ( IsKill ) ) ; SubReg = TmpReg ; } MachinePointerInfo PInfo = BasePtrInfo . getWithOffset ( EltSize * i ) ; MachineMemOperand * NewMMO = MF -> getMachineMemOperand ( PInfo , MMO -> getFlags ( ) , EltSize , commonAlignment ( Alignment , EltSize * i ) ) ; MIB = BuildMI ( * MBB , MI , DL , Desc ) . addReg ( SubReg , getDefRegState ( ! IsStore ) | getKillRegState ( IsKill ) ) . addReg ( ScratchRsrcReg ) ; if ( SOffset == <STR_LIT> ) { MIB . addImm ( <NUM_LIT> ) ; } else {

MIB . addReg ( SOffset , SOffsetRegState ) ;


<s> unsigned RegisterPair = GPRPairDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( RegisterPair ) ) ; return S ;


<s> return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) || ( GuaranteedTailCallOpt && MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> hasFastCall ( ) ) ;


<s> void <ISA_LIT>TargetStreamer :: emitSetFP ( unsigned FpReg , unsigned SpReg , int64_t Offset ) {


<s> return getDelaySlotCycles ( MI ) * <NUM_LIT> ;


<s> const REAL_VALUE_TYPE * rtype = CONST_DOUBLE_REAL_VALUE ( op ) ; long real_words [ VECTOR_128BIT_WORDS ] ; gcc_assert ( num_words <= VECTOR_128BIT_WORDS && ( bitsize % <NUM_LIT> ) == <NUM_LIT> ) ; real_to_target ( real_words , rtype , mode ) ; for ( unsigned num = <NUM_LIT> ; num < num_words ; num ++ ) { unsigned endian_num = ( BYTES_BIG_ENDIAN ? num : num_words - <NUM_LIT> - num ) ; unsigned uvalue = real_words [ endian_num ] ; for ( int shift = <NUM_LIT> - <NUM_LIT> ; shift >= <NUM_LIT> ; shift -= <NUM_LIT> ) info -> bytes [ byte_num ++ ] = ( uvalue >> shift ) & <NUM_LIT> ;


<s> StringRef FS = <STR_LIT> ; if ( CPUName . equals_lower ( <STR_LIT> ) || CPUName . equals_lower ( <STR_LIT> ) ) FS = <STR_LIT> ; return FS ;


return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , false , false ) ;


<s> const MachineOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ;

O << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) << <STR_LIT> ;


<s> static bool equal_keys ( const char * a , const char * b ) {


<s> WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; ++ j ) { if ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != <NUM_LIT> * j + WhichResult ) return false ; } }

if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ;


<s> bool isSVEPredicateRedReg ( ) const { return Kind == k_Register && Reg . Kind == RegKind :: SVEPredicate && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; if ( RHSC * <NUM_LIT> < MFI . getObjectSize ( FI ) ) { if ( ! MFI . isFixedObjectIndex ( FI ) && MFI . getObjectAlignment ( FI ) < <NUM_LIT> ) MFI . setObjectAlignment ( FI , <NUM_LIT> ) ; if ( MFI . getObjectAlignment ( FI ) >= <NUM_LIT> ) {

Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ;


<s> assert ( isInt < <NUM_LIT> > ( Offset ) && ( Offset >= <NUM_LIT> ) && <STR_LIT> ) ; MCOperand SPReg = MCOperand :: CreateReg ( <STR_LIT> ) , BaseReg = SPReg ; MCOperand GPReg = MCOperand :: CreateReg ( <STR_LIT> ) ; MCOperand ZEROReg = MCOperand :: CreateReg ( <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { unsigned Hi = ( ( Offset + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; Offset &= <NUM_LIT> ;

MCOperand ATReg = MCOperand :: CreateReg ( <STR_LIT> ) ;


<s> assert ( ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) && <STR_LIT> ) ; bool Is64Bit = ( RetVT == <STR_LIT> ) ; unsigned RegSize = Is64Bit ? <NUM_LIT> : <NUM_LIT> ; unsigned DstBits = RetVT . getSizeInBits ( ) ; unsigned SrcBits = SrcVT . getSizeInBits ( ) ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( Shift == <NUM_LIT> ) { if ( RetVT == SrcVT ) { Register ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( Op0 ) ; return ResultReg ; } else return emitIntExt ( SrcVT , Op0 , RetVT , IsZExt ) ; } if ( Shift >= DstBits ) return <NUM_LIT> ; if ( Shift >= SrcBits && IsZExt ) return materializeInt ( ConstantInt :: get ( * Context , APInt ( RegSize , <NUM_LIT> ) ) , RetVT ) ;

unsigned ImmR = std :: min < unsigned > ( SrcBits - <NUM_LIT> , Shift ) ;


<s> else return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'r' : return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; break ; }


<s> } if ( INT_REGNO_P ( regno ) ) return INT_REGNO_P ( last_regno ) ; if ( FP_REGNO_P ( regno ) ) { if ( SCALAR_FLOAT_MODE_P ( mode ) && ( mode != TDmode || ( regno % <NUM_LIT> ) == <NUM_LIT> ) && FP_REGNO_P ( last_regno ) ) return <NUM_LIT> ; if ( GET_MODE_CLASS ( mode ) == MODE_INT && GET_MODE_SIZE ( mode ) == UNITS_PER_FP_WORD ) return <NUM_LIT> ; if ( PAIRED_SIMD_REGNO_P ( regno ) && TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( mode ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( CR_REGNO_P ( regno ) ) return GET_MODE_CLASS ( mode ) == MODE_CC ; if ( CA_REGNO_P ( regno ) ) return mode == Pmode || mode == SImode ; if ( ALTIVEC_REGNO_P ( regno ) ) return ( VECTOR_MEM_ALTIVEC_OR_VSX_P ( mode ) || mode == V1TImode ) ; if ( SPE_SIMD_REGNO_P ( regno ) && TARGET_SPE && SPE_VECTOR_MODE ( mode ) ) return <NUM_LIT> ;

return GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ;


<s> if ( ElemTy == <STR_LIT> ) { if ( AllConst ) { int32_t V = ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) | ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) << <NUM_LIT> | ( Consts [ <NUM_LIT> ] -> getZExtValue ( ) & <NUM_LIT> ) << <NUM_LIT> | Consts [ <NUM_LIT> ] -> getZExtValue ( ) << <NUM_LIT> ; return DAG . getBitcast ( <STR_LIT> , DAG . getConstant ( V , dl , <STR_LIT> ) ) ; } bool IsSplat = true ; for ( unsigned i = First + <NUM_LIT> ; i != Num ; ++ i ) { if ( Elem [ i ] == Elem [ First ] || isUndef ( Elem [ i ] ) ) continue ; IsSplat = false ; break ; } if ( IsSplat ) { SDValue Ext = DAG . getZExtOrTrunc ( Elem [ First ] , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , Ext ) ; } assert ( Elem . size ( ) == <NUM_LIT> ) ; SDValue Vs [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { Vs [ i ] = DAG . getZExtOrTrunc ( Elem [ i ] , dl , <STR_LIT> ) ;

Vs [ i ] = DAG . getZeroExtendInReg ( Vs [ i ] , dl , <STR_LIT> ) ;


<s> unsigned OperandsBeginIdx = <NUM_LIT> ; assert ( FK < FaultMaps :: FaultKindMax && <STR_LIT> ) ; FM . recordFaultingOp ( FK , HandlerLabel ) ; MCInst MI ; MI . setOpcode ( Opcode ) ; if ( DefRegister != <STR_LIT> ) MI . addOperand ( MCOperand :: createReg ( DefRegister ) ) ; for ( auto I = FaultingMI . operands_begin ( ) + OperandsBeginIdx , E = FaultingMI . operands_end ( ) ;

I != E ; ++ I ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & FaultingMI , * I ) ) MI . addOperand ( MaybeOperand . getValue ( ) ) ;


<s> static const uint16_t ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const unsigned NumArgRegs = array_lengthof ( ArgRegs ) ; unsigned RegNum = State . getFirstUnallocated ( ArgRegs , NumArgRegs ) ; if ( RegNum != NumArgRegs && RegNum % <NUM_LIT> == <NUM_LIT> ) { State . AllocateReg ( ArgRegs [ RegNum ] ) ;


<s> BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrOut , RegState :: Define ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } else if ( IsThumb1 ) { BuildMI ( * BB , Pos , dl , TII -> get ( LdOpc ) , Data ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) . add ( t1CondCodeOp ( ) ) . addReg ( AddrIn ) . addImm ( LdSize ) . add ( predOps ( <STR_LIT> ) ) ;


<s> bool Thumb2InstrInfo :: BlockHasNoFallThrough ( const MachineBasicBlock & MBB ) const { if ( MBB . empty ( ) ) return false ; switch ( MBB . back ( ) . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; if ( CallConv == CallingConv :: GHC && ! RVLocs . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; assert ( RegLo < <STR_LIT> && <STR_LIT> ) ; Register RegHi = RegLo + <NUM_LIT> ; if ( STI . isRegisterReservedByUser ( RegLo ) || STI . isRegisterReservedByUser ( RegHi ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; if ( STI . isRegisterReservedByUser ( VA . getLocReg ( ) ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } } RetOps [ <NUM_LIT> ] = Chain ;


<s> if ( ! isUIntN ( Width , Value ) ) { std :: string Diagnostic = <STR_LIT> + Description ; int64_t Max = maxUIntN ( Width ) ; Diagnostic += <STR_LIT> + std :: to_string ( Max ) + <STR_LIT> ; if ( Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , Diagnostic ) ; } else { llvm_unreachable ( Diagnostic . c_str ( ) ) ; } }


<s> CodeModel :: Model M = DAG . getTarget ( ) . getCodeModel ( ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) { if ( Subtarget -> isTargetDarwin ( ) || Subtarget -> isTargetELF ( ) ) OpFlag = <STR_LIT> ; WrapperKind = <STR_LIT> ; } else if ( Subtarget -> isPICStyleGOT ( ) ) { OpFlag = <STR_LIT> ; } else if ( Subtarget -> isPICStyleStubPIC ( ) ) { OpFlag = <STR_LIT> ;

} else if ( Subtarget -> isPICStyleStubNoDynamic ( ) ) {


<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) continue ; if ( HII -> isMemOp ( * MJ ) ) continue ; if ( MJ -> mayLoad ( ) ) FoundLoad = true ; if ( MJ -> mayStore ( ) && ! HII -> isNewValueStore ( * MJ ) ) FoundStore = true ; }


<s> bool <ISA_LIT>InstrInfo :: isGenAddr ( const MachineInstr & MI ) const {

const auto Opcode = MI . getOpcode ( ) ;


<s> return new Darwin<ISA_LIT>AsmBackend ( T , TT , object :: mach :: CS<ISA_LIT>_V7 ) ; } if ( TheTriple . isOSWindows ( ) ) assert ( <NUM_LIT> && <STR_LIT> ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ; return new ELF<ISA_LIT>AsmBackend ( T , TT , OSABI ) ;


<s> void <ISA_LIT>FrameLowering :: addCalleeSaveRegistersAsImpOperand ( MachineInstr * MI , const CSIVect & CSI , bool IsDef , bool IsKill ) const { for ( auto & R : CSI ) MI -> addOperand ( MachineOperand :: CreateReg ( R . getReg ( ) , IsDef , true , IsKill ) ) ;


<s> vector < Constant * > Init = createAString ( index_space , Int8Ty ) ; ArrayType * ATy = ArrayType :: get ( Int8Ty , Init . size ( ) ) ; llvm :: GlobalVariable * GV0 = new llvm :: GlobalVariable ( * p_func -> getParent ( ) , ATy , true , GlobalValue :: ExternalLinkage , ConstantArray :: get ( ATy , Init ) , Name ) ;


<s> if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( mode == DImode && GET_CODE ( operands [ <NUM_LIT> ] ) != LSHIFTRT && CONST_INT_P ( operands [ <NUM_LIT> ] ) && ne == INTVAL ( operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - nb ) ; if ( dot ) return <STR_LIT> ; return <STR_LIT> ; } if ( nb < <NUM_LIT> && ne < <NUM_LIT> ) { if ( GET_CODE ( operands [ <NUM_LIT> ] ) == LSHIFTRT && INTVAL ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - INTVAL ( operands [ <NUM_LIT> ] ) ) ; operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - nb ) ;

operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> - ne ) ;


<s> return StringSwitch < <STR_LIT> > ( ID ) . Case ( <STR_LIT> , <STR_LIT> :: I32 ) . Case ( <STR_LIT> , <STR_LIT> :: I64 ) . Case ( <STR_LIT> , <STR_LIT> :: F32 ) . Case ( <STR_LIT> , <STR_LIT> :: F64 ) . Case ( <STR_LIT> , <STR_LIT> :: V128 ) . Case ( <STR_LIT> , <STR_LIT> :: Funcref ) . Case ( <STR_LIT> , <STR_LIT> :: Externref ) . Case ( <STR_LIT> , <STR_LIT> :: Void ) . Default ( <STR_LIT> :: Invalid ) ;


<s> if ( ForSubprog ) TypeId = addType ( std :: move ( TypeEntry ) ) ; else TypeId = addType ( std :: move ( TypeEntry ) , STy ) ; for ( const auto Element : Elements ) { visitTypeEntry ( Element ) ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) , STI ( sti ) {


<s> if ( Pred1 . size ( ) > <NUM_LIT> || Pred2 . size ( ) > <NUM_LIT> ) { return false ; } <STR_LIT> CC1 = ( <STR_LIT> ) Pred1 [ <NUM_LIT> ] . getImm ( ) ; <STR_LIT> CC2 = ( <STR_LIT> ) Pred2 [ <NUM_LIT> ] . getImm ( ) ; if ( CC1 == CC2 ) { return true ; } switch ( CC1 ) { case <STR_LIT> : return true ;


<s> <ISA_LIT>LowerThreadLocal ( ) : ModulePass ( ID ) {

initialize<ISA_LIT>LowerThreadLocalPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> case E_DFmode : return ( gen_aarch64_frecpsdf ) ; case E_V2DFmode : return ( gen_aarch64_frecpsv2df ) ; default : gcc_unreachable ( ) ;


<s> void print<ISA_LIT>NegImmOperand ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O ) {

int value = MI -> getOperand ( OpNo ) . getImm ( ) ;


<s> MachineMemOperand * MMO = getMemOperand ( MBB , FrameIndex , MachineMemOperand :: MOLoad ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ;


<s> void <ISA_LIT>CFGStructurizer :: insertCondBranchEnd ( MachineBasicBlock * MBB , int NewOpcode , int RegNum ) { MachineFunction * MF = MBB -> getParent ( ) ; MachineInstr * NewInstr = MF -> CreateMachineInstr ( TII -> get ( NewOpcode ) , DebugLoc ( ) ) ; MBB -> push_back ( NewInstr ) ;

MachineInstrBuilder ( * MF , NewInstr ) . addReg ( RegNum , false ) ;


<s> bool <ISA_LIT>FunctionInfo :: capGlobalBaseRegSet ( ) const { return CapGlobalBaseReg ;


<s> else if ( isGFX9 ( STI ) ) return ID_SYMBOLIC_FIRST_GFX10_ ; else if ( isGFX10 ( STI ) && ! isGFX10_BEncoding ( STI ) ) return ID_SYMBOLIC_FIRST_GFX1030_ ;


<s> if ( In . isCall ( ) || In . isReturn ( ) || In . isInlineAsm ( ) ) return true ; if ( In . isBranch ( ) ) for ( auto & O : In . operands ( ) ) if ( O . isGlobal ( ) || O . isSymbol ( ) ) return true ; const MCInstrDesc & D = In . getDesc ( ) ; if ( ! D . getImplicitDefs ( ) && ! D . getImplicitUses ( ) ) return false ;

const MachineOperand & Op = In . getOperand ( OpNum ) ;


<s> case SECCAT_SRODATA : sname = <STR_LIT> ; flags = <NUM_LIT> ; break ; case SECCAT_SDATA : sname = <STR_LIT> ; break ; case SECCAT_SBSS : sname = <STR_LIT> ; flags |= SECTION_BSS ; default : break ; } } else { switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_DATA : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL_LOCAL : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL_RO : sname = <STR_LIT> ; break ; case SECCAT_DATA_REL_RO_LOCAL : sname = <STR_LIT> ; break ; case SECCAT_BSS : sname = <STR_LIT> ; flags |= SECTION_BSS ; break ; case SECCAT_RODATA : sname = <STR_LIT> ; flags = <NUM_LIT> ; break ; case SECCAT_SRODATA : case SECCAT_SDATA : case SECCAT_SBSS :


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; uint64_t Val = CE -> getValue ( ) ; Inst . addOperand ( MCOperand :: CreateImm ( Val & ( ( <NUM_LIT> << BitWidth ) - <NUM_LIT> ) ) ) ;


<s> int16_t imm = <NUM_LIT> ; if ( N . getOpcode ( ) == <STR_LIT> && ( ! isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) || ! N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) || ! N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ; return true ; }

Base = DAG . getRegister ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , N . getValueType ( ) ) ;


<s> static bool arm_must_pass_in_stack ( machine_mode mode , const_tree type ) { if ( TARGET_AAPCS_BASED ) return must_pass_in_stack_var_size ( mode , type ) ;

else return must_pass_in_stack_var_size_or_pad ( mode , type ) ;


<s> unsigned <ISA_LIT>ABIInfo :: GetPtrAndOp ( ) const {


<s> gcc_assert ( ( code != GTU && code != LTU && code != GEU && code != LEU ) || mode == CCUNSmode ) ; gcc_assert ( mode == CCFPmode || ( code != ORDERED && code != UNORDERED && code != UNEQ && code != LTGT && code != UNGT && code != UNLT && code != UNGE && code != UNLE ) ) ; gcc_assert ( mode != CCEQmode || code == EQ || code == NE ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: expandSelectCC ( MachineInstr & MI , MachineBasicBlock * BB , unsigned BROpcode ) const { const TargetInstrInfo & TII = * Subtarget -> getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; unsigned CC = ( <STR_LIT> ) MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; MachineBasicBlock * ThisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * IfFalseMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , IfFalseMBB ) ; F -> insert ( It , SinkMBB ) ; SinkMBB -> splice ( SinkMBB -> begin ( ) , ThisMBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , ThisMBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( ThisMBB ) ; ThisMBB -> addSuccessor ( IfFalseMBB ) ; ThisMBB -> addSuccessor ( SinkMBB ) ;

BuildMI ( ThisMBB , dl , TII . get ( BROpcode ) ) . addMBB ( SinkMBB ) . addImm ( CC ) ;


<s> MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; unsigned FirstReg = <NUM_LIT> , SecondReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ; unsigned NewOpc = <NUM_LIT> ; int Offset = <NUM_LIT> ; DebugLoc dl ; if ( NumMove == <NUM_LIT> && CanFormLdStDWord ( Op0 , Op1 , dl , NewOpc , FirstReg , SecondReg , BaseReg , Offset , PredReg , Pred , isT2 ) ) { Ops . pop_back ( ) ; Ops . pop_back ( ) ; const MCInstrDesc & MCID = TII -> get ( NewOpc ) ; const TargetRegisterClass * TRC = TII -> getRegClass ( MCID , <NUM_LIT> , TRI , * MF ) ; MRI -> constrainRegClass ( FirstReg , TRC ) ; MRI -> constrainRegClass ( SecondReg , TRC ) ; if ( isLd ) { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( FirstReg , RegState :: Define ) . addReg ( SecondReg , RegState :: Define ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; MIB . setMemRefs ( Op0 -> mergeMemRefsWith ( * Op1 ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumLDRDFormed ; } else { MachineInstrBuilder MIB = BuildMI ( * MBB , InsertPos , dl , MCID ) . addReg ( FirstReg ) . addReg ( SecondReg ) . addReg ( BaseReg ) ; if ( ! isT2 ) MIB . addReg ( <NUM_LIT> ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; MIB . setMemRefs ( Op0 -> mergeMemRefsWith ( * Op1 ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * MIB << <STR_LIT> ) ; ++ NumSTRDFormed ; } MBB -> erase ( Op0 ) ; MBB -> erase ( Op1 ) ; if ( ! isT2 ) { MRI -> setRegAllocationHint ( FirstReg , <STR_LIT> , SecondReg ) ; MRI -> setRegAllocationHint ( SecondReg , <STR_LIT> , FirstReg ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; assert ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) ;

if ( MI . getOpcode ( ) == <STR_LIT> ) Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , FK_PCRel_4 ) ) ;


<s> reportParseError ( <STR_LIT> ) ; return false ; } StringRef Option ; if ( Parser . parseIdentifier ( Option ) ) { reportParseError ( <STR_LIT> ) ; return false ; } if ( Option == <STR_LIT> ) { clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { if ( ! isABI_O32 ( ) ) { return Error ( L , <STR_LIT> ) ; } setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleOddSPReg ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { return parseDirectiveModuleFP ( ) ; } else if ( Option == <STR_LIT> ) { setModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleSoftFloat ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ; return false ; } return false ; } else if ( Option == <STR_LIT> ) { clearModuleFeatureBits ( <STR_LIT> , <STR_LIT> ) ; getTargetStreamer ( ) . updateABIInfo ( * this ) ; getTargetStreamer ( ) . emitDirectiveModuleHardFloat ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) {


<s> return can_create_pseudo_p ( ) ? gen_reg_rtx ( mode ) : default_reg ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasDistinctOps ( false ) , HasLoadStoreOnCond ( false ) , HasHighWord ( false ) , HasFPExtension ( false ) , HasPopulationCount ( false ) , HasFastSerialization ( false ) , HasInterlockedAccess1 ( false ) , HasMiscellaneousExtensions ( false ) , HasTransactionalExecution ( false ) , HasProcessorAssist ( false ) , HasVector ( false ) , HasLoadStoreOnCond2 ( false ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( ) , FrameLowering ( ) {


<s> if ( is_interrupt_func ( cfun -> decl ) ) { if ( regno < <NUM_LIT> ) return true ; if ( regno > <NUM_LIT> ) return false ; if ( ! crtl -> is_leaf && call_used_or_fixed_reg_p ( regno ) && regno < <NUM_LIT> ) return true ; return df_regs_ever_live_p ( regno ) ;


<s> static inline int vec_any_eq ( vec_float4 a , vec_float4 b ) {

return ( ( int ) ( spu_extract ( spu_orx ( spu_rlmask ( spu_cmpeq ( a , b ) , - <NUM_LIT> ) ) , <NUM_LIT> ) ) ) ;


<s> } case <STR_LIT> : ImmIdx = Idx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs = - InstrOffs ; break ; case <STR_LIT> : ImmIdx = Idx + <NUM_LIT> ; InstrOffs = <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) ; if ( <STR_LIT> ( MI -> getOperand ( ImmIdx ) . getImm ( ) ) == <STR_LIT> ) InstrOffs = - InstrOffs ;


<s> arr [ <NUM_LIT> ] = ( a >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( a >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( a >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( b >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( b >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( b >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( b >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( c >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( c >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( c >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( c >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( d >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( d >> <NUM_LIT> ) & <NUM_LIT> ; arr [ <NUM_LIT> ] = ( d >> <NUM_LIT> ) & <NUM_LIT> ;


<s> } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return false ; } if ( isa < GlobalValue > ( C ) ) { <ISA_LIT>AddressMode AM ; if ( <ISA_LIT>SelectAddress ( C , AM ) ) { if ( AM . BaseType == <STR_LIT> && AM . IndexReg == <NUM_LIT> && AM . Disp == <NUM_LIT> && AM . GV == <NUM_LIT> ) return AM . Base . Reg ; Opc = TLI . getPointerTy ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg ; } return <NUM_LIT> ; } unsigned Align = TD . getPrefTypeAlignment ( C -> getType ( ) ) ;


<s> rtx ra = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx insn ; bool need_barrier_p = known_ne ( get_frame_size ( ) + cfun -> machine -> frame . arg_pointer_offset , <NUM_LIT> ) ; if ( cfun -> machine -> naked_p ) { gcc_assert ( style == NORMAL_RETURN ) ; emit_jump_insn ( gen_return ( ) ) ; return ; } if ( ( style == NORMAL_RETURN ) && riscv_can_use_return_insn ( ) ) { emit_jump_insn ( gen_return ( ) ) ; return ; } epilogue_cfa_sp_offset = <NUM_LIT> ; if ( cfun -> calls_alloca ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; poly_int64 adjust_offset = - frame -> hard_frame_pointer_offset ; rtx adjust = NULL_RTX ; if ( ! adjust_offset . is_constant ( ) ) { rtx tmp1 = RISCV_PROLOGUE_TEMP ( Pmode ) ; rtx tmp2 = RISCV_PROLOGUE_TEMP2 ( Pmode ) ; riscv_legitimize_poly_move ( Pmode , tmp1 , tmp2 , gen_int_mode ( adjust_offset , Pmode ) ) ; adjust = tmp1 ; } else { if ( ! SMALL_OPERAND ( adjust_offset . to_constant ( ) ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( adjust_offset . to_constant ( ) ) ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } else adjust = GEN_INT ( adjust_offset . to_constant ( ) ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , hard_frame_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_value = gen_rtx_PLUS ( Pmode , hard_frame_pointer_rtx , gen_int_mode ( - frame -> hard_frame_pointer_offset , Pmode ) ) ; rtx cfa_adjust_rtx = gen_rtx_SET ( stack_pointer_rtx , cfa_adjust_value ) ; dwarf = alloc_reg_note ( REG_CFA_ADJUST_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { step2 = riscv_first_stack_step ( frame ) ; step1 -= step2 ; } if ( known_gt ( step1 , <NUM_LIT> ) ) { riscv_emit_stack_tie ( ) ; need_barrier_p = false ; if ( ! step1 . is_constant ( ) ) { poly_int64 scalable_frame = step1 ; scalable_frame . coeffs [ <NUM_LIT> ] = step1 . coeffs [ <NUM_LIT> ] ; riscv_v_adjust_scalable_frame ( stack_pointer_rtx , scalable_frame , true ) ; step1 -= scalable_frame ; } if ( step1 . to_constant ( ) != <NUM_LIT> ) { rtx adjust = GEN_INT ( step1 . to_constant ( ) ) ; if ( ! SMALL_OPERAND ( step1 . to_constant ( ) ) ) { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , adjust ) ; adjust = RISCV_PROLOGUE_TEMP ( Pmode ) ; } insn = emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , adjust ) ) ; rtx dwarf = NULL_RTX ; rtx cfa_adjust_rtx = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( step2 ) ) ; dwarf = alloc_reg_note ( REG_CFA_DEF_CFA , cfa_adjust_rtx , dwarf ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;


<s> } else if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , DoesntNeedLRSave ) ) { CallID = MachineOutlinerNoLRSave ; FrameID = MachineOutlinerNoLRSave ; NumInstrsForCall = <NUM_LIT> ; NumInstrsToCreateFrame = <NUM_LIT> ; } if ( std :: any_of ( RepeatedSequenceLocs [ <NUM_LIT> ] . first , RepeatedSequenceLocs [ <NUM_LIT> ] . second , [ ] ( const MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) NumInstrsToCreateFrame += <NUM_LIT> ; else if ( RepeatedSequenceLocs [ <NUM_LIT> ] . second -> isCall ( ) && FrameID != MachineOutlinerTailCall ) NumInstrsToCreateFrame += <NUM_LIT> ;

return MachineOutlinerInfo ( NumInstrsForCall , NumInstrsToCreateFrame , CallID , FrameID ) ;


<s> <STR_LIT> <ISA_LIT>GlobalRegistry :: getPointerStorageClass ( Register VReg ) const { <ISA_LIT>Type * Type = get<ISA_LIT>TypeForVReg ( VReg ) ; assert ( Type && Type -> getOpcode ( ) == <STR_LIT> && Type -> getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; return static_cast < <STR_LIT> > ( Type -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> O << TheReg -> Name ; return ; } } auto TheReg = <STR_LIT> ( SYSm ) ; if ( TheReg ) { O << TheReg -> Name ; return ; } llvm_unreachable ( <STR_LIT> ) ; return ; } unsigned SpecRegRBit = Op . getImm ( ) >> <NUM_LIT> ; unsigned Mask = Op . getImm ( ) & <NUM_LIT> ; if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ;


<s> return CallGraphSCCPass :: doInitialization ( CG ) ;


<s> explicit <ISA_LIT>UnmangledLibFunc ( StringRef FName , FunctionType * FT ) { Name = std :: string ( FName ) ; FuncTy = FT ;


<s> return gen_rtx_REG ( ( INTEGRAL_TYPE_P ( valtype ) && TYPE_PRECISION ( valtype ) < BITS_PER_WORD ) ? SImode : TYPE_MODE ( valtype ) , outgoing ? GP_OUTGOING_RETURN : GP_RETURN_FIRST ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\n' << '\t' << * Info . MI1 << '\n' << '\t' << * Info . MI0 << '\n' ) ; AFI . addLOHDirective ( MCLOH_AdrpAddLdr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumADDToLDR ; break ; case MCLOH_AdrpAddStr : if ( Info . MI1 != nullptr ) { DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\n' << '\t' << * Info . MI1 << '\n' << '\t' << * Info . MI0 << '\n' ) ; AFI . addLOHDirective ( MCLOH_AdrpAddStr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumADDToSTR ; } break ; case MCLOH_AdrpLdrGotLdr : DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\n' << '\t' << * Info . MI1 << '\n' << '\t' << * Info . MI0 << '\n' ) ; AFI . addLOHDirective ( MCLOH_AdrpLdrGotLdr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumLDRToLDR ; break ; case MCLOH_AdrpLdrGotStr : DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\n' << '\t' << * Info . MI1 << '\n' << '\t' << * Info . MI0 << '\n' ) ; AFI . addLOHDirective ( MCLOH_AdrpLdrGotStr , { & MI , Info . MI1 , Info . MI0 } ) ; ++ NumLDRToSTR ; break ; case MCLOH_AdrpLdrGot : DEBUG ( dbgs ( ) << <STR_LIT> << '\t' << MI << '\n' << '\t' << * Info . MI0 << '\n' ) ; AFI . addLOHDirective ( MCLOH_AdrpLdrGot , { & MI , Info . MI0 } ) ; break ; case MCLOH_AdrpAdrp :


<s> if ( ! isITCondCode ( ) ) return false ; <STR_LIT> CC = getCondCode ( ) ;

return CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ;


<s> auto & Src = MI . getOperand ( <NUM_LIT> ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = Src . getReg ( ) ; if ( ! SrcReg . isVirtual ( ) || ! DstReg . isVirtual ( ) ) return false ;

for ( const auto & MO : MRI . reg_nodbg_operands ( DstReg ) ) {


<s> <ISA_LIT>DAGToDAGISel :: <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) , TM ( tm ) {


<s> std :: vector < GlobalAlias * > AliasesToRemove ; SmallPtrSet < Function * , <NUM_LIT> > FuncsToAlwaysInline ; SmallPtrSet < Function * , <NUM_LIT> > FuncsToNoInline ; for ( GlobalAlias & A : M . aliases ( ) ) { if ( Function * F = dyn_cast < Function > ( A . getAliasee ( ) ) ) { A . replaceAllUsesWith ( F ) ; AliasesToRemove . push_back ( & A ) ; } } if ( GlobalOpt ) { for ( GlobalAlias * A : AliasesToRemove ) { A -> eraseFromParent ( ) ; } } for ( GlobalVariable & GV : M . globals ( ) ) { unsigned AS = GV . getAddressSpace ( ) ; if ( AS != <ISA_LIT>AS :: LOCAL_ADDRESS && AS != <ISA_LIT>AS :: REGION_ADDRESS ) continue ; recursivelyVisitUsers ( GV , FuncsToAlwaysInline ) ; } if ( ! <ISA_LIT>TargetMachine :: EnableFunctionCalls || StressCalls ) { auto IncompatAttr = StressCalls ? Attribute :: AlwaysInline : Attribute :: NoInline ; for ( Function & F : M ) { if ( ! F . isDeclaration ( ) && ! F . use_empty ( ) && ! F . hasFnAttribute ( IncompatAttr ) ) { if ( StressCalls ) { if ( ! FuncsToAlwaysInline . count ( & F ) ) FuncsToNoInline . insert ( & F ) ; } else FuncsToAlwaysInline . insert ( & F ) ; } } } for ( Function * F : FuncsToAlwaysInline ) F -> addFnAttr ( Attribute :: AlwaysInline ) ; for ( Function * F : FuncsToNoInline ) F -> addFnAttr ( Attribute :: NoInline ) ;

return ! FuncsToAlwaysInline . empty ( ) || ! FuncsToNoInline . empty ( ) ;


<s> unsigned epiphany_adjust_field_align ( tree field , unsigned computed ) {

if ( computed == <NUM_LIT> && TREE_CODE ( TREE_TYPE ( field ) ) == ARRAY_TYPE ) {


<s> static const TargetRegisterClass * const CalleeSavedRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , <NUM_LIT> } ;


<s> return ; } if ( Op . isImm ( ) ) { if ( getOpcodeName ( MI -> getOpcode ( ) ) == <STR_LIT> || getOpcodeName ( MI -> getOpcode ( ) ) == <STR_LIT> ) O << <STR_LIT> << MCInstPrinter :: formatHex ( Op . getImm ( ) ) ; else O << <STR_LIT> << Op . getImm ( ) ;


<s> if ( Scope . equals ( <STR_LIT> ) ) return false ; if ( Scope . equals ( <STR_LIT> ) ) return true ; assert ( Scope . equals ( <STR_LIT> ) && <STR_LIT> ) ;

for ( const auto & Info : MF . getFrameInfo ( ) . getCalleeSavedInfo ( ) ) if ( Info . getReg ( ) == <STR_LIT> ) return true ;


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ;

return Val > - <NUM_LIT> && Val < <NUM_LIT> ;


<s> const Value * SV = cast < SrcValueSDNode > ( n -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDValue loadptr = DAG . getLoad ( <STR_LIT> , op . getDebugLoc ( ) , chain , valoc , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; SDValue newptr = DAG . getNode ( <STR_LIT> , op . getDebugLoc ( ) , <STR_LIT> , loadptr , DAG . getConstant ( vt . getSizeInBits ( ) / <NUM_LIT> , <STR_LIT> ) ) ;

chain = DAG . getStore ( loadptr . getValue ( <NUM_LIT> ) , op . getDebugLoc ( ) , newptr , valoc , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> void BTFDebug :: processGlobalValue ( const MachineOperand & MO ) { if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( ! GVar ) {

processFuncPrototypes ( dyn_cast < Function > ( GVal ) ) ;


<s> attributes = TYPE_ATTRIBUTES ( TREE_TYPE ( current_function_decl ) ) ;

return lookup_attribute ( <STR_LIT> , attributes ) != NULL_TREE ;


<s> tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; enum rs6000_builtins fcode = ( enum rs6000_builtins ) DECL_MD_FUNCTION_CODE ( fndecl ) ; const struct builtin_description * d = bdesc_mma ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_mma ) ; i ++ , d ++ ) if ( d -> code == fcode ) break ; if ( i >= ARRAY_SIZE ( bdesc_mma ) ) { * expandedp = false ; return NULL_RTX ; } * expandedp = true ; tree arg ; call_expr_arg_iterator iter ; enum insn_code icode = d -> icode ; const struct insn_operand_data * insn_op ; rtx op [ MAX_MMA_OPERANDS ] ; unsigned nopnds = <NUM_LIT> ; unsigned attr = rs6000_builtin_info [ fcode ] . attr ; bool void_func = ( attr & RS6000_BTC_VOID ) ; machine_mode tmode = VOIDmode ; if ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) != void_type_node ) { tmode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; op [ nopnds ++ ] = target ; } else target = const0_rtx ; FOR_EACH_CALL_EXPR_ARG ( arg , iter , exp ) { if ( arg == error_mark_node ) return const0_rtx ; rtx opnd ; insn_op = & insn_data [ icode ] . operand [ nopnds ] ; if ( TREE_CODE ( arg ) == ADDR_EXPR && MEM_P ( DECL_RTL ( TREE_OPERAND ( arg , <NUM_LIT> ) ) ) ) opnd = DECL_RTL ( TREE_OPERAND ( arg , <NUM_LIT> ) ) ; else opnd = expand_normal ( arg ) ; if ( ! ( * insn_op -> predicate ) ( opnd , insn_op -> mode ) ) { if ( ! strcmp ( insn_op -> constraint , <STR_LIT> ) ) { if ( ! CONST_INT_P ( opnd ) ) error ( <STR_LIT> , nopnds ) ; else error ( <STR_LIT> <STR_LIT> , nopnds ) ; return const0_rtx ; } opnd = copy_to_mode_reg ( insn_op -> mode , opnd ) ; } if ( ! void_func && nopnds == <NUM_LIT> && ! strcmp ( insn_op -> constraint , <STR_LIT> ) && insn_op -> mode == tmode && REG_P ( opnd ) && ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( opnd , tmode ) ) target = op [ <NUM_LIT> ] = opnd ; op [ nopnds ++ ] = opnd ; } unsigned attr_args = attr & RS6000_BTC_OPND_MASK ; if ( attr & RS6000_BTC_QUAD || fcode == VSX_BUILTIN_DISASSEMBLE_PAIR_INTERNAL ) attr_args ++ ; gcc_assert ( nopnds == attr_args ) ; rtx pat ; switch ( nopnds ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> :

pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ;


<s> const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; const unsigned ProbeSize = getStackProbeSize ( * MF ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineBasicBlock * testMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * tailMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * blockMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator MBBIter = ++ MBB -> getIterator ( ) ; MF -> insert ( MBBIter , testMBB ) ; MF -> insert ( MBBIter , blockMBB ) ; MF -> insert ( MBBIter , tailMBB ) ; Register sizeVReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register physSPReg = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; Register TmpStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; Register FinalStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * MBB , { MI } , DL , TII -> get ( TargetOpcode :: COPY ) , TmpStackPtr ) . addReg ( physSPReg ) ;


<s> char * curr_feature_string = xstrdup ( opts -> x_ix86_tune_ctrl_string ) ; char * orig = curr_feature_string ; int i ; do { bool clear = false ; next_feature_string = strchr ( curr_feature_string , ',' ) ; if ( next_feature_string ) * next_feature_string ++ = '\0' ; if ( * curr_feature_string == '^' ) { curr_feature_string ++ ; clear = true ; } for ( i = <NUM_LIT> ; i < X86_TUNE_LAST ; i ++ ) {

if ( ! strcmp ( curr_feature_string , ix86_tune_feature_names [ i ] ) ) {


<s> unsigned NumNOPBytes = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; auto & Ctx = OutStreamer -> getContext ( ) ; MCSymbol * MILabel = Ctx . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( MILabel ) ; SM . recordStackMap ( * MILabel , MI ) ; assert ( NumNOPBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; unsigned ShadowBytes = <NUM_LIT> ; const MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineBasicBlock :: const_iterator MII ( MI ) ; ++ MII ; while ( ShadowBytes < NumNOPBytes ) { if ( MII == MBB . end ( ) || MII -> getOpcode ( ) == TargetOpcode :: PATCHPOINT || MII -> getOpcode ( ) == TargetOpcode :: STACKMAP ) break ; ShadowBytes += TII -> getInstSizeInBytes ( * MII ) ; if ( MII -> isCall ( ) ) break ; ++ MII ;


<s> src1 = operands [ <NUM_LIT> ] ; src2 = operands [ <NUM_LIT> ] ; op = gen_rtx_SET ( dst , gen_rtx_fmt_ee ( code , mode , src1 , src2 ) ) ;

if ( reload_completed && code == PLUS && ! rtx_equal_p ( dst , src1 ) ) {


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const Function & F = MF . getFunction ( ) ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = PointerType :: get ( ParamTy , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; LLT PtrType = getLLTForType ( * PtrTy , DL ) ; unsigned DstReg = MRI . createGenericVirtualRegister ( PtrType ) ; unsigned KernArgSegmentPtr = MFI -> getPreloadedReg ( <STR_LIT> ) ; unsigned KernArgSegmentVReg = MRI . getLiveInVirtReg ( KernArgSegmentPtr ) ;

unsigned OffsetReg = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ;


<s> <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ;

S -> EmitBundleAlignMode ( MIPS_NACL_BUNDLE_ALIGN ) ;


<s> bool aarch64_harden_sls_blr_p ( void ) {


<s> void <ISA_LIT>AsmPrinter :: setAndEmitFunctionVirtualRegisters ( const MachineFunction & MF ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream O ( Str ) ; const TargetRegisterInfo * TRI = MF . getTarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; if ( NumBytes ) { O << <STR_LIT> << MFI -> getMaxAlignment ( ) << <STR_LIT> << DEPOTNAME << getFunctionNumber ( ) << <STR_LIT> << NumBytes << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) { O << <STR_LIT> ; O << <STR_LIT> ; } else { O << <STR_LIT> ; O << <STR_LIT> ; } } unsigned int numVRs = MRI -> getNumVirtRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numVRs ; i ++ ) { unsigned int vr = TRI -> index2VirtReg ( i ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( vr ) ;

DenseMap < unsigned , unsigned > & regmap = VRegMapping [ RC ] ;


<s> warning ( <NUM_LIT> , <STR_LIT> , feature ) ; warned_once = true ; }


<s> void <ISA_LIT>InstPrinter :: printZeroOffsetMemOp ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNo ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MO . getReg ( ) ) ; O << <STR_LIT> ;


<s> return __builtin_mve_vcmulq_rot90_m_fv8hf ( __arm_vuninitializedq_f16 ( ) , __a , __b , __p ) ;


<s> unsigned int mips_case_values_threshold ( void ) {

if ( TARGET_MIPS16 && optimize_size ) return <NUM_LIT> ;


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } switch ( Addr . getOpcode ( ) ) { case <STR_LIT> : if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { uint64_t CVal = CN -> getZExtValue ( ) ; if ( ( ( CVal << <NUM_LIT> ) >> <NUM_LIT> ) == CVal ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N0 ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else Base = N0 ;

Disp = CurDAG -> getTargetConstant ( CVal , <STR_LIT> ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> Comparison ( SDValue Op0In , SDValue Op1In , SDValue ChainIn ) : Op0 ( Op0In ) , Op1 ( Op1In ) , Chain ( ChainIn ) , Opcode ( <NUM_LIT> ) , ICmpType ( <NUM_LIT> ) , CCValid ( <NUM_LIT> ) , CCMask ( <NUM_LIT> ) {


<s> addr = memory_address ( SImode , plus_constant ( tramp , jmpofs ) ) ; temp1 = force_reg ( SImode , gen_rtx_MEM ( SImode , addr ) ) ; temp1 = expand_and ( SImode , temp1 , GEN_INT ( <NUM_LIT> ) , NULL_RTX ) ; temp1 = expand_binop ( SImode , ior_optab , temp1 , temp , temp1 , <NUM_LIT> , OPTAB_WIDEN ) ; emit_move_insn ( gen_rtx_MEM ( SImode , addr ) , temp1 ) ; } emit_library_call ( init_one_libfunc ( <STR_LIT> ) , <NUM_LIT> , VOIDmode , <NUM_LIT> , tramp , Pmode ) ; if ( jmpofs >= <NUM_LIT> ) emit_insn ( gen_imb ( ) ) ;


<s> unsigned IsPCRel = <NUM_LIT> ; const MCSymbolData * SD_A = & Asm . getSymbolData ( Target . getSymA ( ) -> getSymbol ( ) ) ; unsigned Index = SD_A -> getIndex ( ) ; if ( Target . getSymB ( ) ) { uint32_t FixupAddress = Writer -> getFragmentAddress ( Fragment , Layout ) + Fixup . getOffset ( ) ; const MCSymbolData * SD_B = & Asm . getSymbolData ( Target . getSymB ( ) -> getSymbol ( ) ) ; IsPCRel = <NUM_LIT> ; FixedValue = ( FixupAddress - Writer -> getSymbolAddress ( SD_B , Layout ) + Target . getConstant ( ) ) ; FixedValue += <NUM_LIT> << Log2Size ; } else {


<s> int64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> return new <ISA_LIT>Z80PostPEI ( ) ;


<s> static unsigned getEFlagsForFeatureSet ( const FeatureBitset & Features ) { unsigned EFlags = <NUM_LIT> ; return EFlags ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Masked ;


<s> SDLoc DL ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , DAG . getConstant ( condCodeToFCC ( CC ) , DL , <STR_LIT> ) ) ;


<s> if ( TLI -> getOperationAction ( ISD , VT ) == TargetLowering :: LibCall ) return true ; if ( auto * Call = dyn_cast < CallInst > ( & I ) ) { if ( isa < IntrinsicInst > ( Call ) ) { if ( const Function * F = Call -> getCalledFunction ( ) ) return isLoweredToCall ( F ) ; } return true ; } switch ( I . getOpcode ( ) ) { default : break ; case Instruction :: FPToSI : case Instruction :: FPToUI : case Instruction :: SIToFP : case Instruction :: UIToFP : case Instruction :: FPTrunc : case Instruction :: FPExt : return ! ST -> hasFP<ISA_LIT>v8Base ( ) ; } if ( VT . isInteger ( ) && VT . getSizeInBits ( ) >= <NUM_LIT> ) { switch ( ISD ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> assert ( VT . getSizeInBits ( ) >= <NUM_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == VT && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == VT && <STR_LIT> ) ; ArrayRef < int > LoMask = Mask . slice ( <NUM_LIT> , Mask . size ( ) / <NUM_LIT> ) ; ArrayRef < int > HiMask = Mask . slice ( Mask . size ( ) / <NUM_LIT> ) ; int NumElements = VT . getVectorNumElements ( ) ; int SplitNumElements = NumElements / <NUM_LIT> ; MVT ScalarVT = VT . getScalarType ( ) ; MVT SplitVT = <STR_LIT> ( ScalarVT , NumElements / <NUM_LIT> ) ; SDValue LoV1 = DAG . getNode ( <STR_LIT> , DL , SplitVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue HiV1 = DAG . getNode ( <STR_LIT> , DL , SplitVT , V1 , DAG . getIntPtrConstant ( SplitNumElements ) ) ; SDValue LoV2 = DAG . getNode ( <STR_LIT> , DL , SplitVT , V2 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue HiV2 = DAG . getNode ( <STR_LIT> , DL , SplitVT , V2 , DAG . getIntPtrConstant ( SplitNumElements ) ) ; auto HalfBlend = [ & ] ( ArrayRef < int > HalfMask ) {

bool UseLoV1 = false , UseHiV1 = false , UseLoV2 = false , UseHiV2 = false ;


<s> return ( int16x8_t ) __builtin_neon_vqsubsv8hi ( __a , __b ) ;


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; MachineFrameInfo * FrameInfo = MF -> getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; int64_t Offset = FrameInfo -> getObjectOffset ( FrameIndex ) ; Offset += SubIdx * <NUM_LIT> ; unsigned LaneVGPRIdx = Offset / ( <NUM_LIT> * <NUM_LIT> ) ; unsigned Lane = ( Offset / <NUM_LIT> ) % <NUM_LIT> ; struct SpilledReg Spill ; Spill . Lane = Lane ; if ( ! LaneVGPRs . count ( LaneVGPRIdx ) ) { unsigned LaneVGPR = TRI -> findUnusedRegister ( MRI , & <STR_LIT> , * MF ) ; if ( LaneVGPR == <STR_LIT> ) return Spill ; LaneVGPRs [ LaneVGPRIdx ] = LaneVGPR ; for ( MachineFunction :: iterator BI = MF -> begin ( ) , BE = MF -> end ( ) ; BI != BE ; ++ BI ) { BI -> addLiveIn ( LaneVGPR ) ;


<s> Type * ArgTys [ <NUM_LIT> ] = { Int8PtrType , Int8PtrType , Int8PtrType , Int8PtrType , Int8PtrType } ; FunctionType * TrampolineTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; FunctionType * TargetFuncTy = FunctionType :: get ( Int32Ty , makeArrayRef ( & ArgTys [ <NUM_LIT> ] , <NUM_LIT> ) , false ) ; Function * Trampoline = Function :: Create ( TrampolineTy , GlobalValue :: InternalLinkage , Twine ( <STR_LIT> ) + GlobalValue :: getRealLinkageName ( ParentFunc -> getName ( ) ) , TheModule ) ; BasicBlock * EntryBB = BasicBlock :: Create ( Context , <STR_LIT> , Trampoline ) ; IRBuilder < > Builder ( EntryBB ) ; Value * LSDA = emitEHLSDA ( Builder , ParentFunc ) ;

Value * CastPersonality = Builder . CreateBitCast ( PersonalityFn , TargetFuncTy -> getPointerTo ( ) ) ;


<s> bool <ISA_LIT>RegisterInfo :: hasBasePointer ( const MachineFunction & MF ) const { return false ;


<s> unsigned Size = MMOa -> getSize ( ) + MMOb -> getSize ( ) ; if ( Paired < CI ) std :: swap ( MMOa , MMOb ) ; MachinePointerInfo PtrInfo ( MMOa -> getPointerInfo ( ) ) ; if ( MMOb -> getAddrSpace ( ) == <ISA_LIT>AS :: FLAT_ADDRESS ) PtrInfo . AddrSpace = <ISA_LIT>AS :: FLAT_ADDRESS ; MachineFunction * MF = CI . I -> getMF ( ) ;

return MF -> getMachineMemOperand ( MMOa , PtrInfo , Size ) ;


<s> Parser . Lex ( ) ; AsmToken Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Equal ) ) { reportParseError ( <STR_LIT> ) ; return false ; } Parser . Lex ( ) ; Tok = Parser . getTok ( ) ; if ( ! parseFpABIValue ( FpAbiVal , <STR_LIT> ) ) return false ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { reportParseError ( <STR_LIT> ) ;


<s> explicit Thumb1FrameLowering ( const <ISA_LIT>Subtarget & sti ) : <ISA_LIT>FrameLowering ( sti ) {


<s> <ISA_LIT>DebugFixup ( ) : MachineFunctionPass ( ID ) {


<s> static int rs6000_psave_function_arg ( machine_mode mode , const_tree type , int align_words , rtx * rvec ) { int k = <NUM_LIT> ; if ( align_words < GP_ARG_NUM_REG ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( align_words + n_words > GP_ARG_NUM_REG || mode == BLKmode || ( TARGET_32BIT && TARGET_POWERPC64 ) ) { machine_mode rmode = TARGET_32BIT ? SImode : DImode ; int i = <NUM_LIT> ; if ( align_words + n_words > GP_ARG_NUM_REG ) { rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } do { rtx r = gen_rtx_REG ( rmode , GP_ARG_MIN_REG + align_words ) ; rtx off = GEN_INT ( i ++ * GET_MODE_SIZE ( rmode ) ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , off ) ; } while ( ++ align_words < GP_ARG_NUM_REG && -- n_words != <NUM_LIT> ) ; } else { rtx r = gen_rtx_REG ( mode , GP_ARG_MIN_REG + align_words ) ; rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , r , const0_rtx ) ; } } else { rvec [ k ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; } return k ;


<s> void <ISA_LIT>_MachoTargetObjectFile :: getNameWithPrefix ( SmallVectorImpl < char > & OutName , const GlobalValue * GV , const TargetMachine & TM ) const {

getMangler ( ) . getNameWithPrefix ( OutName , GV , true ) ;


<s> if ( ! CSKY_ISA_FEATURE ( E2 ) ) { emit_move_insn ( operands [ <NUM_LIT> ] , input ) ; input = operands [ <NUM_LIT> ] ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ( mask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) { emit_insn ( gen_bclri ( operands [ <NUM_LIT> ] , input , GEN_INT ( i ) ) ) ; input = operands [ <NUM_LIT> ] ; } return true ; } for ( i = ( CSKY_ISA_FEATURE ( E2 ) ? <NUM_LIT> : <NUM_LIT> ) ; i < <NUM_LIT> ; i ++ ) { if ( ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << i ) - <NUM_LIT> == mask ) { if ( CSKY_ISA_FEATURE ( <NUM_LIT> ) ) emit_insn ( gen_cskyv2_extzv ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , GEN_INT ( i ) , const0_rtx ) ) ; else { rtx shift = GEN_INT ( <NUM_LIT> - i ) ; rtx reg = ( reload_completed ? operands [ <NUM_LIT> ] : gen_reg_rtx ( SImode ) ) ; emit_insn ( gen_ashlsi3 ( reg , operands [ <NUM_LIT> ] , shift ) ) ; emit_insn ( gen_lshrsi3 ( operands [ <NUM_LIT> ] , reg , shift ) ) ; } return true ; } else if ( ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << i ) - <NUM_LIT> == ~ mask ) { rtx shift = GEN_INT ( i ) ; rtx reg = ( reload_completed ? operands [ <NUM_LIT> ] : gen_reg_rtx ( SImode ) ) ; emit_insn ( gen_lshrsi3 ( reg , operands [ <NUM_LIT> ] , shift ) ) ; emit_insn ( gen_ashlsi3 ( operands [ <NUM_LIT> ] , reg , shift ) ) ; return true ; } } if ( ! reload_completed && INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> ) { rtx reg = copy_to_mode_reg ( SImode , not_value ) ; if ( CSKY_ISA_FEATURE ( E2 ) ) emit_insn ( gen_cskyv2_andnsi3 ( operands [ <NUM_LIT> ] , reg , operands [ <NUM_LIT> ] ) ) ; else { emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; emit_insn ( gen_ck801_andnsi3 ( operands [ <NUM_LIT> ] , reg , operands [ <NUM_LIT> ] ) ) ; } return true ; } if ( reload_completed ) { emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; }

else operands [ <NUM_LIT> ] = copy_to_mode_reg ( SImode , operands [ <NUM_LIT> ] ) ;


<s> SDValue ArgValue2 = DAG . getCopyFromReg ( Chain , DL , Reg2 , RegVT ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( ArgValue , ArgValue2 ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArgValue , ArgValue2 ) ; } InVals . push_back ( ArgValue ) ; } else { MVT LocVT = VA . getLocVT ( ) ; if ( ABI . IsO32 ( ) ) { if ( VA . getValVT ( ) . isFloatingPoint ( ) && ! Subtarget . useSoftFloat ( ) ) LocVT = VA . getValVT ( ) ; } assert ( VA . isMemLoc ( ) ) ; int FI = MFI -> CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue ArgValue = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; OutChains . push_back ( ArgValue . getValue ( <NUM_LIT> ) ) ; ArgValue = UnpackFromArgumentSlot ( ArgValue , VA , Ins [ i ] . ArgVT , DL , DAG ) ; InVals . push_back ( ArgValue ) ; } } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { if ( Ins [ i ] . Flags . isSRet ( ) ) { unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) { Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ) ) ; <ISA_LIT>FI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ i ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; break ; } }

if ( IsVarArg ) writeVarArgRegs ( OutChains , Chain , DL , DAG , CCInfo ) ;


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> } Op = DAG . getNode ( NewOpc , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ) ;

return SDValue ( DAG . getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Op , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> SDValue CLod0 = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , CPIdx0 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue Unpck1 = getUnpackl ( DAG , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , XR1 ) , CLod0 ) ; SDValue CLod1 = DAG . getLoad ( <STR_LIT> , dl , CLod0 . getValue ( <NUM_LIT> ) , CPIdx1 , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <NUM_LIT> ) ; SDValue XR2F = DAG . getBitcast ( <STR_LIT> , Unpck1 ) ; SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , XR2F , CLod1 ) ; SDValue Result ; if ( Subtarget . hasSSE3 ( ) ) {

Result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sub , Sub ) ;


<s> if ( ! FS . empty ( ) ) FullFS = ( Twine ( FullFS ) + <STR_LIT> + FS ) . str ( ) ; ParseSubtargetFeatures ( CPU , TuneCPU , FullFS ) ; if ( hasSSE42 ( ) || hasSSE4A ( ) ) IsUAMem16Slow = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; if ( In64BitMode && ! Has<ISA_LIT>_64 ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ;

if ( StackAlignOverride ) stackAlignment = * StackAlignOverride ;


<s> return TargetTriple . isOSBinFormatELF ( ) ;


<s> bool <ISA_LIT>LowerEmscriptenEHSjLj :: runSjLjOnFunction ( Function & F ) { return false ;


<s> ix86_tls_symbol = gen_rtx_SYMBOL_REF ( Pmode , ( TARGET_GNU_TLS && ! TARGET_64BIT ) ? <STR_LIT> : <STR_LIT> ) ; }


<s> SDLoc SL ( N ) ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ; Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = N -> getOperand ( <NUM_LIT> ) ;

bool UseFMAC = Subtarget -> hasDLInsts ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) && cast < ConstantSDNode > ( Ops [ <NUM_LIT> ] ) -> isZero ( ) ;


<s> if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( N0 . getNode ( ) ) ; if ( ! LD -> isSimple ( ) || ! N0 . hasOneUse ( ) || LD -> isIndexed ( ) || LD -> getExtensionType ( ) != <STR_LIT> ) return SDValue ( ) ; EVT FromVT = LD -> getValueType ( <NUM_LIT> ) ; EVT ToVT = N -> getValueType ( <NUM_LIT> ) ; if ( ! ToVT . isVector ( ) ) return SDValue ( ) ; assert ( FromVT . getVectorNumElements ( ) == ToVT . getVectorNumElements ( ) ) ; EVT ToEltVT = ToVT . getVectorElementType ( ) ; EVT FromEltVT = FromVT . getVectorElementType ( ) ; unsigned NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( ToEltVT == <STR_LIT> && FromEltVT == <STR_LIT> ) NumElements = <NUM_LIT> ; if ( NumElements == <NUM_LIT> || ( FromEltVT != <STR_LIT> && FromVT . getVectorNumElements ( ) == NumElements ) || FromVT . getVectorNumElements ( ) % NumElements != <NUM_LIT> || ! isPowerOf2_32 ( NumElements ) ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( LD ) ;


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == <NUM_LIT> || ! Inst . getOperand ( <NUM_LIT> ) . isImm ( ) || Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType != MCOI :: OPERAND_PCREL ) return false ;

int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> if ( s390_safe_relative_long_p ( insn ) ) return ; find_constant_pool_ref_1 ( PATTERN ( insn ) , ref ) ;


<s> return StringSwitch < unsigned > ( CC . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ;


<s> static bool isPhysicalRegCopy ( MachineInstr * MI ) { if ( MI -> getOpcode ( ) != <STR_LIT> ) return false ; return ! MI -> getOperand ( <NUM_LIT> ) . getReg ( ) . isVirtual ( ) ;


<s> setForcedEncodingSize ( <NUM_LIT> ) ; return Name . substr ( <NUM_LIT> , Name . size ( ) - <NUM_LIT> ) ; } else if ( Name . endswith ( <STR_LIT> ) ) { setForcedEncodingSize ( <NUM_LIT> ) ; return Name . substr ( <NUM_LIT> , Name . size ( ) - <NUM_LIT> ) ; } else if ( Name . endswith ( <STR_LIT> ) ) { setForcedDPP ( true ) ; return Name . substr ( <NUM_LIT> , Name . size ( ) - <NUM_LIT> ) ; } else if ( Name . endswith ( <STR_LIT> ) ) { setForcedSDWA ( true ) ; return Name . substr ( <NUM_LIT> , Name . size ( ) - <NUM_LIT> ) ; }