<s> MI -> getParent ( ) -> erase ( MI ) ; return true ; } if ( ! WidenVMOVS || ! MI -> isCopy ( ) || Subtarget . isCortexA15 ( ) || Subtarget . isFPOnlySP ( ) ) return false ; unsigned DstRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI -> RemoveOperand ( ImpDefIdx ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MIB ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MI -> addRegisterKilled ( SrcRegS , TRI , true ) ; }


<s> AltMappings . emplace_back ( std :: move ( GPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( FPRMapping ) ) ; return AltMappings ; } case TargetOpcode :: G_BITCAST : { unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( Size != <NUM_LIT> && Size != <NUM_LIT> ) break ; if ( MI . getNumOperands ( ) != <NUM_LIT> ) break ; InstructionMappings AltMappings ; InstructionMapping GPRMapping ( <NUM_LIT> , <NUM_LIT> , getCopyMapping ( <STR_LIT> , <STR_LIT> , Size ) , <NUM_LIT> ) ; InstructionMapping FPRMapping ( <NUM_LIT> , <NUM_LIT> , getCopyMapping ( <STR_LIT> , <STR_LIT> , Size ) , <NUM_LIT> ) ; InstructionMapping GPRToFPRMapping ( <NUM_LIT> , copyCost ( <STR_LIT> , <STR_LIT> , Size ) , getCopyMapping ( <STR_LIT> , <STR_LIT> , Size ) , <NUM_LIT> ) ; InstructionMapping FPRToGPRMapping ( <NUM_LIT> , copyCost ( <STR_LIT> , <STR_LIT> , Size ) , getCopyMapping ( <STR_LIT> , <STR_LIT> , Size ) , <NUM_LIT> ) ; AltMappings . emplace_back ( std :: move ( GPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( FPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( GPRToFPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( FPRToGPRMapping ) ) ; return AltMappings ; } case TargetOpcode :: G_LOAD : { unsigned Size = getSizeInBits ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , TRI ) ; if ( Size != <NUM_LIT> ) break ; if ( MI . getNumOperands ( ) != <NUM_LIT> ) break ; InstructionMappings AltMappings ; InstructionMapping GPRMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( { getValueMapping ( PMI_FirstGPR , Size ) , getValueMapping ( PMI_FirstGPR , <NUM_LIT> ) } ) , <NUM_LIT> ) ; InstructionMapping FPRMapping ( <NUM_LIT> , <NUM_LIT> , getOperandsMapping ( { getValueMapping ( PMI_FirstFPR , Size ) , getValueMapping ( PMI_FirstGPR , <NUM_LIT> ) } ) , <NUM_LIT> ) ; AltMappings . emplace_back ( std :: move ( GPRMapping ) ) ; AltMappings . emplace_back ( std :: move ( FPRMapping ) ) ; return AltMappings ; } default :


<s> const MachineInstrBuilder & <ISA_LIT>FastISel :: AddOptionalDefs ( const MachineInstrBuilder & MIB ) { MachineInstr * MI = & * MIB ; if ( TII . isPredicable ( MI ) || is<ISA_LIT>NEONPred ( MI ) ) AddDefaultPred ( MIB ) ; bool CPSR = false ; if ( DefinesOptionalPredicate ( MI , & CPSR ) ) { if ( CPSR ) AddDefaultT1CC ( MIB ) ; else AddDefaultCC ( MIB ) ; }


<s> assert ( PredReg . isReg ( ) && <STR_LIT> ) ; assert ( Polarity . isImm ( ) && <STR_LIT> ) ; assert ( MRI . getRegClass ( <STR_LIT> ) . contains ( PredReg . getReg ( ) ) && <STR_LIT> ) ;

if ( Polarity . getImm ( ) ) O << <STR_LIT> ;


<s> return ArgOffset ; case GRID_OFFSET : return ArgOffset + <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case FK_Data_4 : case <STR_LIT> :


<s> return Kind == Expression || ( Kind == Immediate && isInt < <NUM_LIT> > ( getImm ( ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : if ( CmpMask != MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; if ( SrcReg == MI -> getOperand ( CommonUse ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ) return true ; break ; }


<s> if ( AT == <NUM_LIT> ) reportParseError ( Loc , <STR_LIT> ) ; return AT ;


<s> case CallingConv :: C : case CallingConv :: Fast : case CallingConv :: Swift : case CallingConv :: <ISA_LIT>_FastCall : case CallingConv :: <ISA_LIT>_StdCall : case CallingConv :: <ISA_LIT>_ThisCall : case CallingConv :: <ISA_LIT>_VectorCall : case CallingConv :: Intel_OCL_BI :


<s> I != E ; ) { SDNode * Node = & * I ++ ; unsigned Opcode = Node -> getOpcode ( ) ; if ( Opcode == <STR_LIT> ) PreprocessLoad ( Node , I ) ; else if ( Opcode == <STR_LIT> ) PreprocessTrunc ( Node , I ) ; }


<s> void R600SchedStrategy :: MoveUnits ( std :: vector < SUnit * > & QSrc , std :: vector < SUnit * > & QDst ) { QDst . insert ( QDst . end ( ) , QSrc . begin ( ) , QSrc . end ( ) ) ;


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; }

<ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ;


<s> static bool alpha_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) {

if ( IN_RANGE ( regno , <NUM_LIT> , <NUM_LIT> ) ) return ( mode == SFmode || mode == DFmode || mode == DImode || mode == SCmode || mode == DCmode ) ;


ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregxidi ( __o , <NUM_LIT> ) ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Val ) ) ; return MCDisassembler :: Success ;


<s> void addVectorIndex1Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( getVectorIndex ( ) ) ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned , unsigned , bool * Fast ) const { bool AllowsUnaligned = Subtarget -> allowsUnalignedMem ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> :


<s> BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ;

if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX20Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ;


<s> Op -> RegList . List2From = reglist [ i ] ; Op -> RegList . List2To = reglist [ i + <NUM_LIT> ] ; } else if ( Op -> RegList . List3From == <NUM_LIT> ) { Op -> RegList . List3From = reglist [ i ] ; Op -> RegList . List3To = reglist [ i + <NUM_LIT> ] ; } else if ( Op -> RegList . List4From == <NUM_LIT> ) { Op -> RegList . List4From = reglist [ i ] ; Op -> RegList . List4To = reglist [ i + <NUM_LIT> ] ; } else { assert ( <NUM_LIT> ) ; } }


<s> for ( NodeAddr < BlockNode * > BA : Blocks ) { MachineBasicBlock * MB = BA . Addr -> getCode ( ) ; RefMap & LON = PhiLON [ MB ] ; for ( auto P : BA . Addr -> members_if ( DFG . IsCode < NodeAttrs :: Phi > , DFG ) ) for ( const RefMap :: value_type & S : RealUseMap [ P . Id ] ) LON [ S . first ] . insert ( S . second . begin ( ) , S . second . end ( ) ) ; } if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( auto & I : PhiLON ) dbgs ( ) << <STR_LIT> << I . first -> getNumber ( ) << <STR_LIT> << Print < RefMap > ( I . second , DFG ) << '\n' ; } for ( NodeAddr < BlockNode * > BA : Blocks ) { NodeList Phis = BA . Addr -> members_if ( DFG . IsCode < NodeAttrs :: Phi > , DFG ) ; for ( NodeAddr < PhiNode * > PA : Phis ) { RefMap & RUs = RealUseMap [ PA . Id ] ; if ( RUs . empty ( ) ) continue ; NodeSet SeenUses ; for ( auto U : PA . Addr -> members_if ( DFG . IsRef < NodeAttrs :: Use > , DFG ) ) { if ( ! SeenUses . insert ( U . Id ) . second ) continue ; NodeAddr < PhiUseNode * > PUA = U ; if ( PUA . Addr -> getReachingDef ( ) == <NUM_LIT> ) continue ; auto PrA = DFG . addr < BlockNode * > ( PUA . Addr -> getPredecessor ( ) ) ; RefMap & LOX = PhiLOX [ PrA . Addr -> getCode ( ) ] ; for ( const std :: pair < RegisterId , NodeRefSet > & RS : RUs ) { for ( std :: pair < NodeId , LaneBitmask > P : RS . second ) { RegisterRef S ( RS . first , P . second ) ; NodeList Ds = getAllReachingDefs ( S , PUA , true , false , NoRegs ) ; for ( NodeAddr < DefNode * > D : Ds ) LOX [ S . Reg ] . insert ( { D . Id , S . Mask } ) ;


<s> for ( MachineInstr & MI : llvm :: make_early_inc_range ( llvm :: make_range ( StartMI , MBB . end ( ) ) ) ) { if ( MI . isCall ( ) ) break ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) continue ; assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned STOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( TII . get ( STOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; }


<s> unsigned <ISA_LIT>FrameLowering :: getOpcGlobSet ( const MachineFunction & MF ) {

return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAddr64 ( ) ? <STR_LIT> : <STR_LIT> ;


<s> return static_cast < const <ISA_LIT>Subtarget & > ( STI ) . createDFAPacketizer ( II ) ;


<s> break ; case <STR_LIT> : return instCombineConvertFromSVBool ( IC , II ) ; case <STR_LIT> : return instCombineSVEDup ( IC , II ) ; case <STR_LIT> :


<s> addAssemblyEmitter ( PassManagerBase & PM , bool Fast , raw_ostream & Out ) { PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , Fast ) ) ;


<s> bool microblaze_cannot_force_const_mem ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { return microblaze_tls_referenced_p ( x ) ;


<s> int m32c_modes_tieable_p ( machine_mode m1 , machine_mode m2 ) { if ( GET_MODE_SIZE ( m1 ) == GET_MODE_SIZE ( m2 ) ) return <NUM_LIT> ; if ( m1 == QImode || m2 == QImode ) return <NUM_LIT> ;


<s> OriginalArgWasFloat . clear ( ) ; OriginalArgWasF128 . clear ( ) ;


<s> unsigned Rs2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; DecodeGPRRegisterClass ( Inst , Rd , Address , Decoder ) ;

DecodeGPRRegisterClass ( Inst , Rs2 , Address , Decoder ) ;


<s> unsigned LastInstrOpcode = RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> getOpcode ( ) ; auto SetCandidateCallInfo = [ & RepeatedSequenceLocs ] ( unsigned CallID , unsigned NumBytesForCall ) { for ( outliner :: Candidate & C : RepeatedSequenceLocs ) C . setCallInfo ( CallID , NumBytesForCall ) ; } ; unsigned FrameID = MachineOutlinerDefault ; unsigned NumBytesToCreateFrame = <NUM_LIT> ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) { FrameID = MachineOutlinerTailCall ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerTailCall , <NUM_LIT> ) ; } else if ( LastInstrOpcode == <STR_LIT> || LastInstrOpcode == <STR_LIT> ) { FrameID = MachineOutlinerThunk ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerThunk , <NUM_LIT> ) ; } else if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ ] ( outliner :: Candidate & C ) { return C . LRU . available ( <STR_LIT> ) ; } ) ) { FrameID = MachineOutlinerNoLRSave ; NumBytesToCreateFrame = <NUM_LIT> ; SetCandidateCallInfo ( MachineOutlinerNoLRSave , <NUM_LIT> ) ; } else { if ( std :: all_of ( RepeatedSequenceLocs . begin ( ) , RepeatedSequenceLocs . end ( ) , [ this ] ( outliner :: Candidate & C ) { return findRegisterToSaveLRTo ( C ) ; } ) ) { FrameID = MachineOutlinerRegSave ; NumBytesToCreateFrame = <NUM_LIT> ;

SetCandidateCallInfo ( MachineOutlinerRegSave , <NUM_LIT> ) ;


<s> if ( RI . isSubRegisterEq ( <STR_LIT> , Reg ) ) DE = true ; else if ( RI . isSubRegisterEq ( <STR_LIT> , Reg ) ) HL = true ; }


<s> for ( water_iterator IP = std :: prev ( WaterList . end ( ) ) , B = WaterList . begin ( ) ; ; -- IP ) { MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( isWaterInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) ) && Growth < BestGrowth ) { BestGrowth = Growth ;


<s> EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Op , SL , LoVT , HiVT ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , Load -> getAlignment ( ) ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , PtrVT ) ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> isInvariant ( ) , Load -> getAlignment ( ) ) ; SDValue Ops [ ] = {

DAG . getNode ( <STR_LIT> , SL , VT , LoLoad , HiLoad ) , DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LoLoad . getValue ( <NUM_LIT> ) , HiLoad . getValue ( <NUM_LIT> ) ) } ;


<s> unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; unsigned Size = Desc . getSize ( ) ; TSFlags = Desc . TSFlags ; <STR_LIT> ( TSFlags , getRegPrefix ( MI ) ) ; EmitPrefix ( OS ) ; uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups ) ; switch ( TSFlags & <STR_LIT> ) { default : break ; case <STR_LIT> : case <STR_LIT> : Bits = ByteSwap_16 ( Bits ) ; break ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> GCNSubtarget :: GCNSubtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT , getFeatureBits ( ) ) , TargetTriple ( TT ) , Gen ( SOUTHERN_ISLANDS ) , IsaVersion ( ISAVersion0_0_0 ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP64FP16Denormals ( false ) , DX10Clamp ( false ) , FlatForGlobal ( false ) , AutoWaitcntBeforeBarrier ( false ) , CodeObjectV3 ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , HasApertureRegs ( false ) , EnableXNACK ( false ) , TrapHandler ( false ) , DebuggerInsertNops ( false ) , DebuggerEmitPrologue ( false ) , EnableHugePrivateBuffer ( false ) , EnableVGPRSpilling ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , EnableDS128 ( false ) , DumpCode ( false ) , FP64 ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , VIInsts ( false ) , GFX9Insts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , HasIntClamp ( false ) , HasFmaMixInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasScalarAtomics ( false ) , HasInv2PiInlineImm ( false ) , HasSDWAOmod ( false ) , HasSDWAScalar ( false ) , HasSDWASdst ( false ) , HasSDWAMac ( false ) , HasSDWAOutModsVOPC ( false ) , HasDPP ( false ) , HasDLInsts ( false ) , D16PreservesUnusedBits ( false ) , FlatAddressSpace ( false ) , FlatInstOffsets ( false ) , FlatGlobalInsts ( false ) , FlatScratchInsts ( false ) , AddNoCarryInsts ( false ) , HasUnpackedD16VMem ( false ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrInfo ( initializeSubtargetDependencies ( TT , GPU , FS ) ) , TLInfo ( TM , * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) {


<s> static inline vec_float4 vec_lvlx ( int a , vec_float4 * b ) {

vec_float4 * p = ( vec_float4 * ) ( ( unsigned char * ) ( b ) + a ) ;


<s> case TYPE_CR64 : return translateRMRegister ( mcInst , insn ) ; case TYPE_M : case TYPE_M8 : case TYPE_M16 : case TYPE_M32 : case TYPE_M64 : case TYPE_M128 : case TYPE_M512 : case TYPE_Mv : case TYPE_M32FP : case TYPE_M64FP : case TYPE_M80FP : case TYPE_M16INT : case TYPE_M32INT : case TYPE_M64INT : case TYPE_M1616 : case TYPE_M1632 : case TYPE_M1664 :

return translateRMMemory ( mcInst , insn , true ) ;


<s> RegisterTarget < Triple :: thumb , true > A ( TheThumbLETarget , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: thumbeb , true > B ( TheThumbBETarget , <STR_LIT> , <STR_LIT> ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> static int rs6000_clone_priority ( tree fndecl ) { tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; HOST_WIDE_INT isa_masks ; int ret = CLONE_DEFAULT ; tree attrs = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( fndecl ) ) ; const char * attrs_str = NULL ; attrs = TREE_VALUE ( TREE_VALUE ( attrs ) ) ; attrs_str = TREE_STRING_POINTER ( attrs ) ; if ( strcmp ( attrs_str , <STR_LIT> ) != <NUM_LIT> ) { if ( fn_opts == NULL_TREE ) fn_opts = target_option_default_node ;

if ( ! fn_opts || ! TREE_TARGET_OPTION ( fn_opts ) ) isa_masks = rs6000_isa_flags ;


<s> static DecodeStatus s32_0ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { <ISA_LIT>Disassembler const & Disassembler = disassembler ( Decoder ) ; unsigned Bits = <ISA_LIT>MCInstrInfo :: getExtentBits ( * Disassembler . MCII , MI ) ; tmp = SignExtend64 ( tmp , Bits ) ; signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ; return MCDisassembler :: Success ;


<s> MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg || Reg == <STR_LIT> || Reg == <STR_LIT> ) continue ; if ( MO . isUse ( ) ) LocalUses . push_back ( Reg ) ; else LocalDefs . push_back ( Reg ) ; } for ( unsigned i = <NUM_LIT> , e = LocalUses . size ( ) ; i != e ; ++ i ) { unsigned Reg = LocalUses [ i ] ; Uses . insert ( Reg ) ; for ( const unsigned * Subreg = TRI -> getSubRegisters ( Reg ) ; * Subreg ; ++ Subreg ) Uses . insert ( * Subreg ) ; } for ( unsigned i = <NUM_LIT> , e = LocalDefs . size ( ) ; i != e ; ++ i ) { unsigned Reg = LocalDefs [ i ] ; Defs . insert ( Reg ) ; for ( const unsigned * Subreg = TRI -> getSubRegisters ( Reg ) ; * Subreg ; ++ Subreg ) Defs . insert ( * Subreg ) ; if ( Reg == <STR_LIT> ) continue ; }


<s> if ( Name == <STR_LIT> ) { MappedKind = FK_Data_4 ; return true ; }

return MCAsmBackend :: getFixupKind ( Name , MappedKind ) ;


<s> explicit <ISA_LIT>AsmBackend ( bool Is64Bit ) : MCAsmBackend ( ) , Is64Bit ( Is64Bit ) {


<s> MOp1 = MF . getMachineMemOperand ( MMO , HwLen , HwLen ) ; } unsigned MemOpc = BN -> getOpcode ( ) ; SDValue NewOp ; if ( MemOpc == <STR_LIT> ) { SDValue Load0 = DAG . getLoad ( SingleTy , dl , Chain , Base0 , MOp0 ) ; SDValue Load1 = DAG . getLoad ( SingleTy , dl , Chain , Base1 , MOp1 ) ; NewOp = DAG . getMergeValues ( { DAG . getNode ( <STR_LIT> , dl , MemTy , Load0 , Load1 ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load0 . getValue ( <NUM_LIT> ) , Load1 . getValue ( <NUM_LIT> ) ) } , dl ) ; } else {


<s> if ( MF . getTarget ( ) . Options . UnsafeFPMath ) return true ; const Function & F = MF . getFunction ( ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { Attribute Attr = F . getFnAttribute ( <STR_LIT> ) ; StringRef Val = Attr . getValueAsString ( ) ;


<s> if ( TARGET_NEON ) switch ( mode ) { case E_HFmode : return TARGET_NEON_VECTORIZE_DOUBLE ? V4HFmode : V8HFmode ; case E_SFmode : return TARGET_NEON_VECTORIZE_DOUBLE ? V2SFmode : V4SFmode ; case E_SImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V2SImode : V4SImode ; case E_HImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V4HImode : V8HImode ; case E_QImode : return TARGET_NEON_VECTORIZE_DOUBLE ? V8QImode : V16QImode ; case E_DImode : if ( ! TARGET_NEON_VECTORIZE_DOUBLE ) return V2DImode ; break ; default : ; } if ( TARGET_REALLY_IWMMXT ) switch ( mode ) {


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result ;


<s> if ( early_blink_restore ) { rtx addr = plus_constant ( Pmode , stack_pointer_rtx , offs ) ; reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; rtx insn = frame_move_inc ( reg , gen_frame_mem ( Pmode , addr ) , stack_pointer_rtx , NULL_RTX ) ; add_reg_note ( insn , REG_CFA_RESTORE , reg ) ; restore_blink = false ; } if ( gmask ) for ( i = <NUM_LIT> ; i <= GMASK_LEN ; i ++ ) { machine_mode restore_mode = SImode ; if ( TARGET_LL64 && ( ( i % <NUM_LIT> ) == <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << i ) ) != <NUM_LIT> ) && ( ( gmask & ( <NUM_LIT> << ( i + <NUM_LIT> ) ) ) != <NUM_LIT> ) ) restore_mode = DImode ; else if ( ( gmask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) continue ; reg = gen_rtx_REG ( restore_mode , i ) ; offs = <NUM_LIT> ; switch ( restore_mode ) { case E_DImode : if ( ( GMASK_LEN - __builtin_clzll ( gmask ) ) == ( i + <NUM_LIT> ) && early_blink_restore ) offs = <NUM_LIT> ; break ; case E_SImode : if ( ( GMASK_LEN - __builtin_clzll ( gmask ) ) == i && early_blink_restore ) offs = <NUM_LIT> ; break ;


<s> llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : \ return NAME ; } return nullptr ;


<s> return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || TRI -> needsStackRealignment ( MF ) ) ;


<s> Register Lo = Unmerge . getReg ( <NUM_LIT> ) ; Register Hi = Unmerge . getReg ( <NUM_LIT> ) ; Arg . OrigRegs . assign ( Arg . Regs . begin ( ) , Arg . Regs . end ( ) ) ; Arg . Regs = { Lo , Hi } ; if ( ! STI . isLittle ( ) ) std :: swap ( Lo , Hi ) ; MIRBuilder . buildCopy ( VALo . getLocReg ( ) , Lo ) ; MIRBuilder . buildCopy ( VAHi . getLocReg ( ) , Hi ) ;


<s> if ( getArgType ( FInfo ) != <ISA_LIT>LibFunc :: F32 || FInfo . getPrefix ( ) != <ISA_LIT>LibFunc :: NOPFX || ! HasNative ( FInfo . getId ( ) ) ) return false ; <ISA_LIT>LibFunc nf = FInfo ; nf . setPrefix ( <ISA_LIT>LibFunc :: NATIVE ) ;

if ( Constant * FPExpr = getFunction ( M , nf ) ) {


<s> case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getConstant ( BlendMask , <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> hasAVX2 ( ) && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget -> hasAVX2 ( ) ) { int Scale = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; BlendMask = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= Size ) for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) BlendMask |= <NUM_LIT> << ( i * Scale + j ) ; MVT BlendVT = VT . getSizeInBits ( ) > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; V1 = DAG . getNode ( <STR_LIT> , DL , BlendVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , DL , BlendVT , V2 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , BlendVT , V1 , V2 , DAG . getConstant ( BlendMask , <STR_LIT> ) ) ) ; } case <STR_LIT> : { int Scale = <NUM_LIT> / VT . getVectorNumElements ( ) ; BlendMask = <NUM_LIT> ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= Size ) for ( int j = <NUM_LIT> ; j < Scale ; ++ j ) BlendMask |= <NUM_LIT> << ( i * Scale + j ) ; V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( BlendMask , <STR_LIT> ) ) ) ; } case <STR_LIT> : { assert ( Subtarget -> hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; BlendMask = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) BlendMask |= <NUM_LIT> << i ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( BlendMask , <STR_LIT> ) ) ; } }


<s> CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC ) ;


<s> if ( isSelectPseudo ( * NextMIIt ) ) { assert ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CCValid && <STR_LIT> ) ; if ( NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == CCMask || NextMIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( CCValid ^ CCMask ) ) { Selects . push_back ( & * NextMIIt ) ; continue ; } break ; } if ( NextMIIt -> definesRegister ( <STR_LIT> ) || NextMIIt -> usesCustomInsertionHook ( ) ) break ; bool User = false ; for ( auto SelMI : Selects ) if ( NextMIIt -> readsVirtualRegister ( SelMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { User = true ; break ; } if ( NextMIIt -> isDebugInstr ( ) ) { if ( User ) { assert ( NextMIIt -> isDebugValue ( ) && <STR_LIT> ) ; DbgValues . push_back ( & * NextMIIt ) ; } } else if ( User || ++ Count > <NUM_LIT> ) break ; } MachineInstr * LastMI = Selects . back ( ) ; bool CCKilled = ( LastMI -> killsRegister ( <STR_LIT> ) || checkCCKill ( * LastMI , MBB ) ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * JoinMBB = <STR_LIT> ( LastMI , MBB ) ; MachineBasicBlock * FalseMBB = <STR_LIT> ( StartMBB ) ; if ( ! CCKilled ) { FalseMBB -> addLiveIn ( <STR_LIT> ) ; JoinMBB -> addLiveIn ( <STR_LIT> ) ; } MBB = StartMBB ; BuildMI ( MBB , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( JoinMBB ) ; MBB -> addSuccessor ( JoinMBB ) ;


<s> Type * ScalarTy = DataTy -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ;

if ( ! ScalarTy -> isIntegerTy ( ) ) return false ;


<s> else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_v ;

else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_X ;


<s> emitAuipcInstPair ( DestReg , DestReg , Symbol , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TLS_GD_HI , <STR_LIT> , IDLoc , Out ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitStartOfAsmFile ( Module & M ) {


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Opc = MI . getOpcode ( ) ; bool isSelectRROp = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ; bool isMemcpyOp = Opc == <STR_LIT> ; bool isSelectRIOp = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ; assert ( ( isSelectRROp || isSelectRIOp || isMemcpyOp ) && <STR_LIT> ) ; if ( isMemcpyOp ) return EmitInstrWithCustomInserterMemcpy ( MI , BB ) ; bool is32BitCmp = ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ BB -> getIterator ( ) ; MachineBasicBlock * ThisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * Copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Copy1MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( I , Copy0MBB ) ; F -> insert ( I , Copy1MBB ) ; Copy1MBB -> splice ( Copy1MBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Copy1MBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( Copy0MBB ) ; BB -> addSuccessor ( Copy1MBB ) ; int CC = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int NewCC ; switch ( CC ) { case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : NewCC = isSelectRROp ? <STR_LIT> : <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> + Twine ( CC ) ) ; } unsigned LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

bool isSignedCmp = ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ;


<s> static SDValue PerformSubCombine ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ;


<s> bool <ISA_LIT>InstrInfo :: expandExtendStackPseudo ( MachineInstr & MI ) const { MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBB . findDebugLoc ( MI ) ; MachineBasicBlock * BB = & MBB ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineBasicBlock * syscallMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = MF . CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator It = ++ ( BB -> getIterator ( ) ) ; MF . insert ( It , syscallMBB ) ; MF . insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) ) , BB -> end ( ) ) ;

sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ;


<s> const ExtValue & EV = ExtI . first ; ( void ) EV ; const ExtExpr & Ex = ExtI . second ; ( void ) Ex ; if ( ExtOpc == <STR_LIT> || ExtOpc == <STR_LIT> ) { bool IsAddi = ExtOpc == <STR_LIT> ; const MachineOperand & RegOp = MI . getOperand ( IsAddi ? <NUM_LIT> : <NUM_LIT> ) ; const MachineOperand & ImmOp = MI . getOperand ( IsAddi ? <NUM_LIT> : <NUM_LIT> ) ; assert ( Ex . Rs == RegOp && EV == ImmOp && Ex . Neg != IsAddi && <STR_LIT> ) ; BuildMI ( MBB , At , dl , HII -> get ( TargetOpcode :: COPY ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MachineOperand ( ExtR ) ) ; Diff = <NUM_LIT> ; MBB . erase ( MI ) ; return true ; } if ( ExtOpc == <STR_LIT> || ExtOpc == <STR_LIT> || ExtOpc == <STR_LIT> || ExtOpc == <STR_LIT> ) { bool IsSub = ExtOpc == <STR_LIT> ; Register Rs = MI . getOperand ( IsSub ? <NUM_LIT> : <NUM_LIT> ) ; ExtValue V = MI . getOperand ( IsSub ? <NUM_LIT> : <NUM_LIT> ) ; assert ( EV == V && Rs == Ex . Rs && IsSub == Ex . Neg && <STR_LIT> ) ; unsigned NewOpc = ExtOpc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , At , dl , HII -> get ( NewOpc ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MachineOperand ( ExtR ) ) ; MBB . erase ( MI ) ; return true ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) emitSegmentOverridePrefix ( <NUM_LIT> , MI , OS ) ; CurOp += <NUM_LIT> ; break ; } case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) emitSegmentOverridePrefix ( <NUM_LIT> , MI , OS ) ; CurOp += <NUM_LIT> ; break ; } case <STR_LIT> : { ++ CurOp ; break ; } case <STR_LIT> : { emitSegmentOverridePrefix ( <NUM_LIT> , MI , OS ) ; break ; } } uint64_t Encoding = TSFlags & <STR_LIT> ; bool HasREX = false ; if ( Encoding ) emitVEXOpcodePrefix ( MemoryOperand , MI , OS ) ;

else HasREX = emitOpcodePrefix ( MemoryOperand , MI , STI , OS ) ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TT ) { CodePointerSize = <NUM_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; IsLittleEndian = false ; MaxInstLength = <NUM_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ;


<s> bool <ISA_LIT>LDBackend :: initBRIslandFactory ( ) { if ( m_pBRIslandFactory == NULL ) {

m_pBRIslandFactory = new BranchIslandFactory ( maxFwdBranchOffset ( ) , maxBwdBranchOffset ( ) , <NUM_LIT> ) ;


<s> static void rs6000_emit_stack_tie ( void ) { rtx mem = gen_rtx_MEM ( BLKmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ) ;

set_mem_alias_set ( mem , rs6000_sr_alias_set ) ;


<s> void printf128mem ( const MCInst * MI , unsigned OpNo ) { O << <STR_LIT> ;


<s> MachineInstr * MI = SA . Addr -> getCode ( ) ; if ( ( MI -> getOpcode ( ) != <STR_LIT> || ! MI -> getOperand ( <NUM_LIT> ) . isGlobal ( ) ) && ( MI -> getOpcode ( ) != <STR_LIT> || ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) || HII -> isConstExtended ( * MI ) ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << HII -> getName ( MI -> getOpcode ( ) ) << <STR_LIT> << * MI << <STR_LIT> << Print < NodeAddr < InstrNode * >> ( IA , * DFG ) << '\n' ) ; NodeList UNodeList ; getAllRealUses ( SA , UNodeList ) ; if ( ! allValidCandidates ( SA , UNodeList ) ) continue ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { Changed |= processAddUses ( SA , MI , UNodeList ) ; continue ; } short SizeInc = <NUM_LIT> ; unsigned DefR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; InstrEvalMap InstrEvalResult ; if ( ! analyzeUses ( DefR , UNodeList , InstrEvalResult , SizeInc ) ) continue ; if ( SizeInc > CodeGrowthLimit ) continue ; bool KeepTfr = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << UNodeList . size ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E ; ++ I ) { NodeAddr < UseNode * > UseN = * I ; assert ( ! ( UseN . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) && <STR_LIT> ) ; NodeAddr < StmtNode * > OwnerN = UseN . Addr -> getOwner ( * DFG ) ; MachineInstr * UseMI = OwnerN . Addr -> getCode ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * UseMI -> getParent ( ) ) << <STR_LIT> << * UseMI << <STR_LIT> ) ; int UseMOnum = - <NUM_LIT> ; unsigned NumOperands = UseMI -> getNumOperands ( ) ; for ( unsigned j = <NUM_LIT> ; j < NumOperands - <NUM_LIT> ; ++ j ) { const MachineOperand & op = UseMI -> getOperand ( j ) ; if ( op . isReg ( ) && op . isUse ( ) && DefR == op . getReg ( ) ) UseMOnum = j ; } if ( UseMOnum >= <NUM_LIT> && InstrEvalResult [ UseMI ] ) Changed |= xformUseMI ( MI , UseMI , UseN , UseMOnum ) ; else KeepTfr = true ;


<s> void add<ISA_LIT>SOImmOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( ) ) ;


<s> return llvm :: InlineCost :: getNever ( IsViable . getFailureReason ( ) ) ; } if ( isWrapperOnlyCall ( CB ) ) return llvm :: InlineCost :: getAlways ( <STR_LIT> ) ; InlineParams LocalParams = Params ; LocalParams . DefaultThreshold = ( int ) getInlineThreshold ( CB ) ; bool RemarksEnabled = false ; const auto & BBs = Caller -> getBasicBlockList ( ) ; if ( ! BBs . empty ( ) ) { auto DI = OptimizationRemark ( DEBUG_TYPE , <STR_LIT> , DebugLoc ( ) , & BBs . front ( ) ) ; if ( DI . isEnabled ( ) ) RemarksEnabled = true ; } OptimizationRemarkEmitter ORE ( Caller ) ; auto GetAssumptionCache = [ this ] ( Function & F ) -> AssumptionCache & { return ACT -> getAssumptionCache ( F ) ; } ; auto IC = llvm :: getInlineCost ( CB , Callee , LocalParams , TTI , GetAssumptionCache , GetTLI , nullptr , P<ISA_LIT> , RemarksEnabled ? & ORE : nullptr ) ; if ( IC && ! IC . isAlways ( ) && ! Callee -> hasFnAttribute ( Attribute :: InlineHint ) ) {

size_t Size = Caller -> size ( ) + Callee -> size ( ) - <NUM_LIT> ;


<s> Subtarget = & MF . getSubtarget < GCNSubtarget > ( ) ; InstructionSelector :: setupMF ( MF , KB , CoverageInfo ) ;


<s> return decodeUImmOperand < N > ( Inst , Imm + <NUM_LIT> , Address , Decoder ) ;


<s> for ( unsigned Idx = <NUM_LIT> , IdxE = MRI -> getNumVirtRegs ( ) ; Idx != IdxE ; ++ Idx ) { unsigned VReg = TargetRegisterInfo :: index2VirtReg ( Idx ) ; unsigned WAReg = MFI -> getWAReg ( VReg ) ; if ( WAReg == <ISA_LIT>FunctionInfo :: UnusedReg ) continue ; if ( WAReg < MFI -> getParams ( ) . size ( ) ) continue ; if ( int ( WAReg ) < <NUM_LIT> ) continue ; MFI -> addLocal ( getRegType ( VReg ) ) ; } getTargetStreamer ( ) -> emitLocal ( MFI -> getLocals ( ) ) ; AsmPrinter :: EmitFunctionBodyStart ( ) ;


<s> void <ISA_LIT>RegisterBankInfo :: constrainOpWithReadfirstlane ( MachineInstr & MI , MachineRegisterInfo & MRI , unsigned OpIdx ) const { Register Reg = MI . getOperand ( OpIdx ) . getReg ( ) ; const RegisterBank * Bank = getRegBank ( Reg , MRI , * TRI ) ; if ( Bank != & <STR_LIT> ) return ; MachineIRBuilder B ( MI ) ; Register SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; B . buildInstr ( <STR_LIT> ) . addDef ( SGPR ) . addReg ( Reg ) ;

MRI . setType ( SGPR , MRI . getType ( Reg ) ) ;


<s> end_sequence ( ) ; push_topmost_sequence ( ) ; for ( scan = get_insns ( ) ; scan != NULL_RTX ; scan = NEXT_INSN ( scan ) ) if ( NOTE_P ( scan ) && NOTE_LINE_NUMBER ( scan ) == NOTE_INSN_FUNCTION_BEG ) break ; if ( scan == NULL_RTX ) scan = get_insns ( ) ; insn = emit_insn_after ( insn , scan ) ; pop_topmost_sequence ( ) ; }

return cfun -> machine -> mips16_gp_pseudo_rtx ;


<s> createLShiftOri < ShiftAmount > ( MCOperand :: createImm ( Value ) , RegNo , IDLoc , Instructions ) ;


<s> new_mode = GET_MODE_INNER ( mode ) ; } else if ( type && composite_p ) { unsigned int warn_psabi_flags = <NUM_LIT> ; int ag_count = aapcs_vfp_sub_candidate ( type , & new_mode , & warn_psabi_flags ) ; if ( ag_count > <NUM_LIT> && ag_count <= HA_MAX_NUM_FLDS ) { static unsigned last_reported_type_uid ; unsigned uid = TYPE_UID ( TYPE_MAIN_VARIANT ( type ) ) ; int alt ; if ( ! silent_p && warn_psabi && warn_psabi_flags && uid != last_reported_type_uid && ( ( alt = aapcs_vfp_sub_candidate ( type , & new_mode , NULL ) ) != ag_count ) ) { const char * url = CHANGES_ROOT_URL <STR_LIT> ; gcc_assert ( alt == - <NUM_LIT> ) ; last_reported_type_uid = uid ; if ( warn_psabi_flags & WARN_PSABI_NO_UNIQUE_ADDRESS ) inform ( input_location , <STR_LIT> <STR_LIT> <STR_LIT> , TYPE_MAIN_VARIANT ( type ) , url ) ; else if ( warn_psabi_flags & WARN_PSABI_EMPTY_CXX17_BASE ) inform ( input_location , <STR_LIT> <STR_LIT> <STR_LIT> , TYPE_MAIN_VARIANT ( type ) , url ) ; } if ( is_ha != NULL ) * is_ha = true ; * count = ag_count ; } else return false ; } else return false ; gcc_assert ( ! aarch64_sve_mode_p ( new_mode ) ) ; * base_mode = new_mode ; return true ;


if ( fcode == AARCH64_LS64_BUILTIN_LD64B || fcode == AARCH64_LS64_BUILTIN_ST64B || fcode == AARCH64_LS64_BUILTIN_ST64BV || fcode == AARCH64_LS64_BUILTIN_ST64BV0 ) return aarch64_expand_builtin_ls64 ( fcode , exp , target ) ;


<s> else if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ;

else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV ) ;


<s> rtx elementsize = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( CONST_INT_P ( totalsize ) && CONST_INT_P ( elementsize ) && UINTVAL ( elementsize ) != <NUM_LIT> && UINTVAL ( totalsize ) != <NUM_LIT> ) { rtx lane_idx = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( CONST_INT_P ( lane_idx ) ) aarch64_simd_lane_bounds ( lane_idx , <NUM_LIT> , UINTVAL ( totalsize ) / UINTVAL ( elementsize ) , exp ) ; else error ( <STR_LIT> , exp ) ; } else error ( <STR_LIT> , exp ) ; return const0_rtx ; } aarch64_simd_builtin_datum * d = & aarch64_simd_builtin_data [ fcode - AARCH64_SIMD_PATTERN_START ] ; enum insn_code icode = d -> code ; builtin_simd_arg args [ SIMD_MAX_BUILTIN_ARGS + <NUM_LIT> ] ; int num_args = insn_data [ d -> code ] . n_operands ; int is_void = <NUM_LIT> ; int k ; is_void = ! ! ( d -> qualifiers [ <NUM_LIT> ] & qualifier_void ) ; num_args += is_void ; for ( k = <NUM_LIT> ; k < num_args ; k ++ ) { int qualifiers_k = k ; int operands_k = k - is_void ;


<s> bool convertSelectOfConstantsToMath ( EVT VT ) const override {


assert ( Kind == k_FPImm && <STR_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( unsigned ( getCondCode ( ) ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Src2 -> isReg ( ) || ! RI . isVGPR ( MRI , Src2 -> getReg ( ) ) || hasModifiersSet ( MI , <STR_LIT> :: src2_modifiers ) ) return false ; break ; case <STR_LIT> : break ; } } const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 && ( ! Src1 -> isReg ( ) || ! RI . isVGPR ( MRI , Src1 -> getReg ( ) ) || hasModifiersSet ( MI , <STR_LIT> :: src1_modifiers ) ) ) return false ; if ( hasModifiersSet ( MI , <STR_LIT> :: src0_modifiers ) ) return false ; if ( ! hasVALU32BitEncoding ( MI . getOpcode ( ) ) ) return false ;

return ! hasModifiersSet ( MI , <STR_LIT> :: omod ) && ! hasModifiersSet ( MI , <STR_LIT> :: clamp ) ;


<s> if ( TARGET_FLOAT128 ) { if ( suffix == 'q' || suffix == 'Q' ) return ( FLOAT128_IEEE_P ( TFmode ) ) ? TFmode : KFmode ;


<s> uint64_t bit = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; bit |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; int64_t dst = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ;

if ( dst & ( <NUM_LIT> << ( <NUM_LIT> - <NUM_LIT> ) ) ) dst |= ~ ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> , e = Blocks . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = Blocks [ i ] ; for ( MachineBasicBlock :: iterator MII = MBB -> begin ( ) , E = MBB -> end ( ) ; MII != E ; ++ MII ) { const MachineInstr * MI = & * MII ; if ( isInvalidLoopOperation ( MI ) ) return true ;


<s> MachineBasicBlock * MBB2 = * std :: next ( MBB -> succ_begin ( ) ) ; if ( MBB1 != MBB2 ) return ; MachineInstr * BranchMI = getNormalBlockBranchInstr ( MBB ) ; assert ( BranchMI && isCondBranch ( BranchMI ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; BranchMI -> dump ( ) ; ) ; BranchMI -> eraseFromParent ( ) ;


<s> MachineInstr & MI = * MII ++ ; if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) { if ( PrevVSETVLI && ( MI . isCall ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) ) { PrevVSETVLI = nullptr ; } continue ; } if ( ! PrevVSETVLI || ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) { PrevVSETVLI = & MI ; continue ; } if ( PrevVSETVLI -> getOpcode ( ) != MI . getOpcode ( ) ) { PrevVSETVLI = & MI ; continue ; } Register AVLReg ; bool SameAVL = false ; if ( MI . getOpcode ( ) == <STR_LIT> ) { AVLReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SameAVL = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getReg ( ) == AVLReg ; } else { SameAVL = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getImm ( ) == MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; } int64_t PrevVTYPEImm = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VTYPEImm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! SameAVL || PrevVTYPEImm != VTYPEImm ) { PrevVSETVLI = & MI ; continue ; } if ( ( MI . getOpcode ( ) == <STR_LIT> ) && ( AVLReg == <STR_LIT> ) ) { assert ( ( PrevVSETVLI -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; Register PrevOutVL = PrevVSETVLI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OutVL = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( PrevOutVL == <STR_LIT> && OutVL != <STR_LIT> ) { PrevVSETVLI = & MI ; continue ; }


<s> MachineInstr * NewCmp = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , LoopEnd ) . addReg ( LoopCount ) . addImm ( <NUM_LIT> ) ; unsigned NewLoopCount = createVR ( MF , <STR_LIT> ) ; MachineInstr * NewAdd = BuildMI ( & MBB , DL , get ( <STR_LIT> ) , NewLoopCount ) . addReg ( LoopCount ) . addImm ( - <NUM_LIT> ) ; for ( SmallVectorImpl < MachineInstr * > :: iterator I = PrevInsts . begin ( ) , E = PrevInsts . end ( ) ; I != E ; ++ I ) ( * I ) -> substituteRegister ( LoopCount , NewLoopCount , <NUM_LIT> , getRegisterInfo ( ) ) ; PrevInsts . clear ( ) ; PrevInsts . push_back ( NewCmp ) ; PrevInsts . push_back ( NewAdd ) ; if ( Iter == MaxIter ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( Loop -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addReg ( NewLoopCount ) ; if ( Iter == <NUM_LIT> ) Loop -> eraseFromParent ( ) ;

Cond . push_back ( MachineOperand :: CreateImm ( <STR_LIT> ) ) ;


<s> if ( ! VECTOR_MODE_P ( GET_MODE ( x ) ) ) mode = GET_MODE_INNER ( mode ) ; x = simplify_unary_operation ( NEG , mode , x , mode ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitAtomicBinary ( MachineInstr & MI , MachineBasicBlock * BB , unsigned Opcode , bool InvertResult ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; unsigned Dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned Success = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned NewValue = MRI . createVirtualRegister ( & <STR_LIT> ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction * MF = BB -> getParent ( ) ; MachineFunction :: iterator It = BB -> getIterator ( ) ; ++ It ; MachineBasicBlock * LoopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * ExitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , LoopMBB ) ; MF -> insert ( It , ExitMBB ) ; ExitMBB -> splice ( ExitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; ExitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopMBB ) ; BB = LoopMBB ; if ( Opcode != <NUM_LIT> ) { unsigned OldValue = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , OldValue ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( OldValue ) ; if ( MI . getOperand ( <NUM_LIT> ) . getType ( ) == MachineOperand :: MO_Register ) { BuildMI ( BB , DL , TII -> get ( Opcode ) , NewValue ) . addReg ( OldValue ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } else if ( MI . getOperand ( <NUM_LIT> ) . getType ( ) == MachineOperand :: MO_Immediate ) { BuildMI ( BB , DL , TII -> get ( Opcode ) , NewValue ) . addReg ( OldValue ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( InvertResult ) { unsigned int Inverted = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , Inverted ) . addReg ( NewValue ) . addImm ( - <NUM_LIT> ) ;


<s> mode = TYPE_MODE ( type ) ; mode = promote_function_mode ( type , mode , & unsigned_p , func , <NUM_LIT> ) ; } memset ( & args , <NUM_LIT> , sizeof args ) ;

return riscv_get_arg_info ( & info , & args , mode , type , true , true ) ;


<s> if ( TARGET_DEBUG_ADDR ) { if ( SYMBOL_REF_P ( symbol ) ) fprintf ( stderr , <STR_LIT> , XSTR ( symbol , <NUM_LIT> ) ) ; else { fprintf ( stderr , <STR_LIT> , GET_RTX_NAME ( GET_CODE ( symbol ) ) ) ; debug_rtx ( symbol ) ; } } if ( ! can_create_pseudo_p ( ) ) df_set_regs_ever_live ( TOC_REGISTER , true ) ; tocreg = gen_rtx_REG ( Pmode , TOC_REGISTER ) ; tocrel = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , symbol , tocreg ) , UNSPEC_TOCREL ) ; if ( TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ( ) ) return tocrel ; hi = gen_rtx_HIGH ( Pmode , copy_rtx ( tocrel ) ) ;


<s> setAvailableFeatures ( ComputeAvailableFeatures ( sti . getFeatureBits ( ) ) ) ;

MRI = Parser . getContext ( ) . getRegisterInfo ( ) ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) , N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getNode ( ) -> hasOneUse ( ) ) {

SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI ) ;


<s> if ( VT == <STR_LIT> ) { if ( Subtarget . hasBWI ( ) ) { SDValue ExA = DAG . getNode ( ExAVX , dl , <STR_LIT> , A ) ; SDValue ExB = DAG . getNode ( ExAVX , dl , <STR_LIT> , B ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ExA , ExB ) ; Mul = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mul , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Mul ) ; } SDValue ALo = extract128BitVector ( A , <NUM_LIT> , DAG , dl ) ; SDValue BLo = extract128BitVector ( B , <NUM_LIT> , DAG , dl ) ; SDValue AHi = extract128BitVector ( A , NumElems / <NUM_LIT> , DAG , dl ) ; SDValue BHi = extract128BitVector ( B , NumElems / <NUM_LIT> , DAG , dl ) ; ALo = DAG . getNode ( ExAVX , dl , <STR_LIT> , ALo ) ; BLo = DAG . getNode ( ExAVX , dl , <STR_LIT> , BLo ) ; AHi = DAG . getNode ( ExAVX , dl , <STR_LIT> , AHi ) ; BHi = DAG . getNode ( ExAVX , dl , <STR_LIT> , BHi ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ALo , BLo ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , AHi , BHi ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; const int LoMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; const int HiMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( <STR_LIT> , dl , Lo , Hi , LoMask ) , DAG . getVectorShuffle ( <STR_LIT> , dl , Lo , Hi , HiMask ) ) ; } assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue ExA = DAG . getNode ( ExAVX , dl , <STR_LIT> , A ) ; SDValue ExB = DAG . getNode ( ExAVX , dl , <STR_LIT> , B ) ;


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , CurDAG -> getTargetConstantFP ( APF . convertToFloat ( ) , dl , <STR_LIT> ) ) ) ; return ; }

else if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) {


<s> EFlagsV3 |= getElfMach ( STI . getCPU ( ) ) ; if ( getTargetID ( ) -> isXnackOnOrAny ( ) ) EFlagsV3 |= ELF :: EF_<ISA_LIT>_FEATURE_XNACK_V3 ; if ( getTargetID ( ) -> isSramEccOnOrAny ( ) ) EFlagsV3 |= ELF :: EF_<ISA_LIT>_FEATURE_SRAMECC_V3 ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> } } else { switch ( model ) { case TLSModel :: GeneralDynamic : case TLSModel :: LocalDynamic : return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , false ) ; } } assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; } } else { assert ( ( Offset + FulleSizeInBytes ) <= Data . size ( ) && <STR_LIT> ) ; assert ( NumBytes <= FulleSizeInBytes && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = FulleSizeInBytes - <NUM_LIT> - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; } } <ISA_LIT>MCExpr :: VariantKind RefKind = static_cast < <ISA_LIT>MCExpr :: VariantKind > ( Target . getRefKind ( ) ) ; if ( <ISA_LIT>MCExpr :: getSymbolLoc ( RefKind ) == <ISA_LIT>MCExpr :: VK_SABS || ( ! RefKind && Fixup . getTargetKind ( ) == <STR_LIT> ) ) { if ( SignedValue < <NUM_LIT> ) Data [ Offset + <NUM_LIT> ] &= ~ ( <NUM_LIT> << <NUM_LIT> ) ; else Data [ Offset + <NUM_LIT> ] |= ( <NUM_LIT> << <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: expandPostRAPseudo ( MachineBasicBlock :: iterator MI ) const { return false ;


<s> const size_t Lanes = Op . getNumOperands ( ) ; auto IsConstant = [ ] ( const SDValue & V ) { return V . getOpcode ( ) == <STR_LIT> || V . getOpcode ( ) == <STR_LIT> ; } ; using Entry = std :: pair < SDValue , size_t > ; SmallVector < Entry , <NUM_LIT> > ValueCounts ; size_t NumConst = <NUM_LIT> , NumDynamic = <NUM_LIT> ; for ( const SDValue & Lane : Op -> op_values ( ) ) { if ( Lane . isUndef ( ) ) { continue ; } else if ( IsConstant ( Lane ) ) { NumConst ++ ; } else { NumDynamic ++ ; } auto CountIt = std :: find_if ( ValueCounts . begin ( ) , ValueCounts . end ( ) , [ & Lane ] ( Entry A ) { return A . first == Lane ; } ) ; if ( CountIt == ValueCounts . end ( ) ) { ValueCounts . emplace_back ( Lane , <NUM_LIT> ) ; } else { CountIt -> second ++ ; } } auto CommonIt = std :: max_element ( ValueCounts . begin ( ) , ValueCounts . end ( ) , [ ] ( Entry A , Entry B ) { return A . second < B . second ; } ) ; assert ( CommonIt != ValueCounts . end ( ) && <STR_LIT> ) ; SDValue SplatValue = CommonIt -> first ; size_t NumCommon = CommonIt -> second ; if ( Subtarget -> hasUnimplementedSIMD128 ( ) ) { const size_t ConstBytes = <NUM_LIT> + std :: max ( size_t ( <NUM_LIT> ) , <NUM_LIT> / Lanes ) ; const size_t SplatBytes = <NUM_LIT> ; const size_t SplatConstBytes = SplatBytes + ConstBytes ;


<s> GCNIterativeScheduler :: GCNIterativeScheduler ( MachineSchedContext * C , StrategyKind S ) : BaseClass ( C , std :: make_unique < SchedStrategyStub > ( ) ) , Context ( C ) , Strategy ( S ) , UPTracker ( * LIS ) {


<s> MachineOperand * getPreservedOperand ( ) const {


<s> if ( MI -> getOperand ( OpNo ) . isImm ( ) ) { unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( Value <= ( ( unsigned int ) pow ( <NUM_LIT> , bits ) - <NUM_LIT> ) && <STR_LIT> ) ; O << ( unsigned int ) Value ; } else printOperand ( MI , OpNo , O ) ;


<s> MachineBasicBlock :: iterator FindAllocFrame ( MachineBasicBlock & B ) {

for ( auto & I : B ) if ( IsAllocFrame ( I ) ) return I ;


<s> void setParent ( RegionMRT * Region ) { Parent = Region ;


<s> sel &= <NUM_LIT> ; O << cb << <STR_LIT> << sel << <STR_LIT> ; } else if ( sel >= <NUM_LIT> ) { sel -= <NUM_LIT> ; O << sel ;


<s> N -> setNodeId ( - <NUM_LIT> ) ; return ; } if ( trySelect ( N ) ) return ;


<s> TValIsAllOnes = FValIsAllOnes ; FValIsAllZeros = TValIsAllZeros ; } } if ( DAG . ComputeNumSignBits ( Cond ) != CondVT . getScalarSizeInBits ( ) ) return SDValue ( ) ; if ( TValIsAllOnes && FValIsAllZeros ) return DAG . getBitcast ( VT , Cond ) ; if ( ! DCI . isBeforeLegalize ( ) && ! TLI . isTypeLegal ( CondVT ) ) return SDValue ( ) ; if ( TValIsAllOnes ) { SDValue CastRHS = DAG . getBitcast ( CondVT , RHS ) ; SDValue Or = DAG . getNode ( <STR_LIT> , DL , CondVT , Cond , CastRHS ) ; return DAG . getBitcast ( VT , Or ) ; } if ( FValIsAllZeros ) { SDValue CastLHS = DAG . getBitcast ( CondVT , LHS ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , CondVT , Cond , CastLHS ) ; return DAG . getBitcast ( VT , And ) ; } if ( TValIsAllZeros ) { MVT AndNVT = <STR_LIT> ( <STR_LIT> , CondVT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue CastCond = DAG . getBitcast ( AndNVT , Cond ) ; SDValue CastRHS = DAG . getBitcast ( AndNVT , RHS ) ; SDValue AndN = DAG . getNode ( <STR_LIT> , DL , AndNVT , CastCond , CastRHS ) ; return DAG . getBitcast ( VT , AndN ) ; } return SDValue ( ) ;


<s> OpIdx = <NUM_LIT> ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { assert ( NumOps >= <NUM_LIT> && OpInfo [ OpIdx ] . RegClass == <STR_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; OpIdx = <NUM_LIT> ; return true ; } return false ;


<s> AU . addPreserved < DominatorTreeWrapperPass > ( ) ; AU . addRequired < ScalarEvolution > ( ) ;


<s> auto ShiftOffset = Signed ? B . buildAShr ( S64 , SrcReg , OffsetReg ) : B . buildLShr ( S64 , SrcReg , OffsetReg ) ; auto UnmergeSOffset = B . buildUnmerge ( { S32 , S32 } , ShiftOffset ) ; if ( auto ConstWidth = getIConstantVRegValWithLookThrough ( WidthReg , MRI ) ) { auto Zero = B . buildConstant ( S32 , <NUM_LIT> ) ; auto WidthImm = ConstWidth -> Value . getZExtValue ( ) ; if ( WidthImm <= <NUM_LIT> ) { auto Extract = Signed ? B . buildSbfx ( S32 , UnmergeSOffset . getReg ( <NUM_LIT> ) , Zero , WidthReg ) : B . buildUbfx ( S32 , UnmergeSOffset . getReg ( <NUM_LIT> ) , Zero , WidthReg ) ; auto Extend = Signed ? B . buildAShr ( S32 , Extract , B . buildConstant ( S32 , <NUM_LIT> ) ) : Zero ; B . buildMerge ( DstReg , { Extract , Extend } ) ; } else { auto UpperWidth = B . buildConstant ( S32 , WidthImm - <NUM_LIT> ) ; auto Extract = Signed ? B . buildSbfx ( S32 , UnmergeSOffset . getReg ( <NUM_LIT> ) , Zero , UpperWidth ) : B . buildUbfx ( S32 , UnmergeSOffset . getReg ( <NUM_LIT> ) , Zero , UpperWidth ) ; B . buildMerge ( DstReg , { UnmergeSOffset . getReg ( <NUM_LIT> ) , Extract } ) ; } MI . eraseFromParent ( ) ; return true ; } auto ExtShift = B . buildSub ( S32 , B . buildConstant ( S32 , <NUM_LIT> ) , WidthReg ) ; auto SignBit = B . buildShl ( S64 , ShiftOffset , ExtShift ) ; if ( Signed ) B . buildAShr ( S64 , SignBit , ExtShift ) ; else B . buildLShr ( S64 , SignBit , ExtShift ) ; MI . eraseFromParent ( ) ; return true ;


<s> int64_t StackPosEntry = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( StackPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; int64_t LRPosEntry = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , <NUM_LIT> ) ) ; BuildMI ( MBB , It , DebugLoc ( ) , get ( <STR_LIT> ) ) . addCFIIndex ( LRPosEntry ) . setMIFlags ( MachineInstr :: FrameSetup ) ; MachineInstr * LDRXpost = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; Et = MBB . insert ( Et , LDRXpost ) ; } if ( MInfo . FrameConstructionID == MachineOutlinerTailCall || MInfo . FrameConstructionID == MachineOutlinerThunk ) return ; MachineInstr * ret = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) ; MBB . insert ( MBB . end ( ) , ret ) ;

if ( MInfo . FrameConstructionID == MachineOutlinerNoLRSave ) return ;


<s> Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; } else { assert ( model == TLSModel :: LocalExec ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ;


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const unsigned DefaultSafety = <NUM_LIT> ; switch ( RC -> getID ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - DefaultSafety ; } case <STR_LIT> : case <STR_LIT> :


<s> emit_move_insn ( adjust_address ( tramp_mem , SImode , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; emit_move_insn ( adjust_address ( tramp_mem , SImode , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( gen_ic_invalidate_line ( tramp ) ) ; return ; } tramp_templ = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; fixed_len = TRAMPOLINE_SIZE - <NUM_LIT> * GET_MODE_SIZE ( Pmode ) ; tramp_templ = gen_datalabel_ref ( tramp_templ ) ; dst = tramp_mem ; src = gen_const_mem ( BLKmode , tramp_templ ) ; set_mem_align ( dst , <NUM_LIT> ) ; set_mem_align ( src , <NUM_LIT> ) ; emit_block_move ( dst , src , GEN_INT ( fixed_len ) , BLOCK_OP_NORMAL ) ; emit_move_insn ( adjust_address ( tramp_mem , Pmode , fixed_len ) , fnaddr ) ; emit_move_insn ( adjust_address ( tramp_mem , Pmode , fixed_len + GET_MODE_SIZE ( Pmode ) ) , cxt ) ; emit_insn ( gen_ic_invalidate_line ( tramp ) ) ; return ; } else if ( TARGET_SHMEDIA ) { rtx quad0 = gen_reg_rtx ( DImode ) , cxtload = gen_reg_rtx ( DImode ) ; rtx quad1 = gen_reg_rtx ( DImode ) , quad2 = gen_reg_rtx ( DImode ) ; rtx movishori = force_reg ( V2HImode , ( simplify_gen_subreg ( V2HImode , GEN_INT ( <NUM_LIT> ) , SImode , <NUM_LIT> ) ) ) ; rtx ptabs = force_reg ( DImode , GEN_INT ( <NUM_LIT> ) ) ; rtx blink = force_reg ( DImode , GEN_INT ( <NUM_LIT> ) ) ; tramp = force_reg ( Pmode , tramp ) ; fnaddr = force_reg ( SImode , fnaddr ) ; cxt = force_reg ( SImode , cxt ) ; emit_insn ( gen_mshflo_w_x ( gen_rtx_SUBREG ( V4HImode , quad0 , <NUM_LIT> ) , gen_rtx_SUBREG ( V2HImode , fnaddr , <NUM_LIT> ) , movishori ) ) ; emit_insn ( gen_rotrdi3_mextr ( quad0 , quad0 , GEN_INT ( TARGET_LITTLE_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ) ) ; emit_insn ( gen_ashldi3_media ( quad0 , quad0 , const2_rtx ) ) ; emit_move_insn ( change_address ( tramp_mem , DImode , NULL_RTX ) , quad0 ) ;

emit_insn ( gen_mshflo_w_x ( gen_rtx_SUBREG ( V4HImode , cxtload , <NUM_LIT> ) , gen_rtx_SUBREG ( V2HImode , cxt , <NUM_LIT> ) , movishori ) ) ;


<s> Relocator :: DWord A = helper_extract_movw_movt_addend ( pReloc . target ( ) ) + pReloc . addend ( ) ;


<s> static rtx_insn * visium_md_asm_adjust ( vec < rtx > & , vec < rtx > & , vec < machine_mode > & , vec < const char * > & , vec < rtx > & clobbers , HARD_REG_SET & clobbered_regs , location_t ) { clobbers . safe_push ( gen_rtx_REG ( CCmode , FLAGS_REGNUM ) ) ; SET_HARD_REG_BIT ( clobbered_regs , FLAGS_REGNUM ) ; return NULL ;


<s> unsigned <ISA_LIT>TargetLowering :: getFunctionAlignment ( const Function * F ) const { return F -> hasFnAttr ( Attribute :: OptimizeForSize ) ? <NUM_LIT> : <NUM_LIT> ;


<s> unsigned NativeWidth = Subtarget -> is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; const Type * MemType = AI -> getType ( ) ; if ( MemType -> getPrimitiveSizeInBits ( ) > NativeWidth ) return needsCmpXchgNb ( MemType ) ;

AtomicRMWInst :: BinOp Op = AI -> getOperation ( ) ;


<s> auto * ExtMI = MF . CreateMachineInstr ( HII -> get ( <STR_LIT> ) , DebugLoc ( ) ) ;

bool Avail = ResourceTracker -> canReserveResources ( ExtMI ) ;


<s> JTI = ( ( <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ) . getJITInfo ( ) ; II = ( ( const <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ) . getInstrInfo ( ) ; TD = ( ( const <ISA_LIT>TargetMachine & ) MF . getTarget ( ) ) . getDataLayout ( ) ; Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; MCPEs = & MF . getConstantPool ( ) -> getConstants ( ) ; MJTEs = <NUM_LIT> ; if ( MF . getJumpTableInfo ( ) ) MJTEs = & MF . getJumpTableInfo ( ) -> getJumpTables ( ) ; JTI -> Initialize ( MF , IsPIC ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do { DEBUG ( errs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator MBB = MF . begin ( ) , E = MF . end ( ) ; MBB != E ; ++ MBB ) { MCE . StartMachineBasicBlock ( MBB ) ; for ( MachineBasicBlock :: instr_iterator I = MBB -> instr_begin ( ) , E = MBB -> instr_end ( ) ; I != E ; ++ I ) emitInstruction ( * I ) ; }

} while ( MCE . finishFunction ( MF ) ) ;


<s> continue ; } else if ( TII -> isDisableWQM ( MI ) ) { BBI . Needs |= StateExact ; if ( ! ( BBI . InNeeds & StateExact ) ) { BBI . InNeeds |= StateExact ; Worklist . push_back ( & MBB ) ; } GlobalFlags |= StateExact ; III . Disabled = StateWQM | StateWWM ; continue ; } else { if ( Opcode == <STR_LIT> ) { LiveMaskQueries . push_back ( & MI ) ; } else if ( WQMOutputs ) { for ( const MachineOperand & MO : MI . defs ( ) ) { if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! TRI -> isVirtualRegister ( Reg ) && TRI -> hasVGPRs ( TRI -> getPhysRegClass ( Reg ) ) ) { Flags = StateWQM ; break ; } } } if ( ! Flags ) continue ; } markInstruction ( MI , Flags , Worklist ) ; GlobalFlags |= Flags ; } } if ( GlobalFlags & StateWQM ) { for ( MachineInstr * MI : SetInactiveInstrs ) markInstruction ( * MI , StateWQM , Worklist ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getConstrainedRegClassForOperand ( const MachineOperand & MO , const MachineRegisterInfo & MRI ) const {

if ( const RegisterBank * RB = MRI . getRegBankOrNull ( MO . getReg ( ) ) ) return getRegClassForTypeOnBank ( MRI . getType ( MO . getReg ( ) ) , * RB , MRI ) ;


<s> if ( ! ZeroExt ) return DAG . getNode ( <STR_LIT> , dl , ResTy , VecV ) ; assert ( ty ( VecV ) . getVectorNumElements ( ) == ResTy . getVectorNumElements ( ) ) ; SDValue True = DAG . getNode ( <STR_LIT> , dl , ResTy , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue False = getZero ( dl , ResTy , DAG ) ; return DAG . getSelect ( dl , ResTy , VecV , True , False ) ;


<s> unsigned POTReg = getPOTBaseRegister ( ) ; if ( MF . getFunction ( ) . isPagerando ( ) ) { return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , POTReg , PtrVT ) ; } else { SDValue POTAddress = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; POTAddress = DAG . getNode ( <STR_LIT> , dl , PtrVT , POTAddress ) ; SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , POTReg , POTAddress ) ; SDValue Ops [ <NUM_LIT> ] = { POTAddress , Chain } ;

return DAG . getMergeValues ( Ops , dl ) ;


<s> if ( size <= <NUM_LIT> ) insn = emit_insn ( gen_stack_pointer_inc ( size_int_rtx ) ) ; else if ( size <= <NUM_LIT> ) { insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( - <NUM_LIT> ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; insn = emit_insn ( gen_stack_pointer_inc ( size_rtx ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_stack_pointer_inc ( size_int_rtx ) ) ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else { rtx size_int_rtx = GEN_INT ( - size ) ; if ( size <= <NUM_LIT> ) emit_window_save ( size_int_rtx ) ; else if ( size <= <NUM_LIT> ) { emit_window_save ( GEN_INT ( - <NUM_LIT> ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> - size ) ) ) ; emit_insn ( gen_frame_blockage ( ) ) ; } else { rtx size_rtx = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_move_insn ( size_rtx , size_int_rtx ) ; emit_window_save ( size_rtx ) ; } } if ( sparc_leaf_function_p ) { sparc_frame_base_reg = stack_pointer_rtx ;

sparc_frame_base_offset = size + SPARC_STACK_BIAS ;


<s> const ConstantFP * Cnt = MO . getFPImm ( ) ; const APFloat & Val = Cnt -> getValueAPF ( ) ; switch ( Cnt -> getType ( ) -> getTypeID ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; break ; case Type :: HalfTyID : MCOp = MCOperand :: createExpr ( <ISA_LIT>FloatMCExpr :: createConstantFPHalf ( Val , OutContext ) ) ; break ; case Type :: FloatTyID : MCOp = MCOperand :: createExpr ( <ISA_LIT>FloatMCExpr :: createConstantFPSingle ( Val , OutContext ) ) ;


<s> if ( Opcode == <STR_LIT> ) { if ( ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI . getOperand ( <NUM_LIT> ) ) ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> void setVarArgsFrameIndex ( int Index ) {


<s> insn = NEXT_INSN ( insn ) ; if ( insn == <NUM_LIT> || ( active_insn_p ( insn ) && NONDEBUG_INSN_P ( insn ) && ! NOTE_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != UNSPEC_VOLATILE && GET_CODE ( PATTERN ( insn ) ) != PARALLEL ) ) break ; }


<s> bool <ISA_LIT>BranchRelaxation :: relaxBranchInstructions ( ) { bool Changed = false ; for ( MachineFunction :: iterator I = MF -> begin ( ) ; I != MF -> end ( ) ; ++ I ) { MachineBasicBlock & MBB = * I ; MachineInstr * MI = MBB . getFirstTerminator ( ) ; if ( isConditionalBranch ( MI -> getOpcode ( ) ) && ! isBlockInRange ( MI , getDestBlock ( MI ) , getBranchDisplacementBits ( MI -> getOpcode ( ) ) ) ) { fixupConditionalBranch ( MI ) ; ++ NumRelaxed ; Changed = true ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) { std :: string CPUName = <STR_LIT> ;

ParseSubtargetFeatures ( CPUName , FS ) ;


<s> void frv_split_double_load ( rtx dest , rtx source ) { int regno = REGNO ( dest ) ; rtx dest1 = gen_highpart ( SImode , dest ) ; rtx dest2 = gen_lowpart ( SImode , dest ) ; rtx address = XEXP ( source , <NUM_LIT> ) ;

if ( GET_CODE ( address ) == PRE_MODIFY || ! refers_to_regno_p ( regno , address ) ) {


<s> bool isEXP ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> if ( isCalleeStructRet || isCallerStructRet ) return false ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; const Triple & TT = getTargetMachine ( ) . getTargetTriple ( ) ; if ( GV -> hasExternalWeakLinkage ( ) && ( ! TT . isOSWindows ( ) || TT . isOSBinFormatELF ( ) || TT . isOSBinFormatMachO ( ) ) ) return false ; } LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( getEffectiveCallingConv ( CalleeCC , isVarArg ) , getEffectiveCallingConv ( CallerCC , CallerF . isVarArg ( ) ) , MF , C , Ins , CCAssignFnForReturn ( CalleeCC , isVarArg ) , CCAssignFnForReturn ( CallerCC , CallerF . isVarArg ( ) ) ) ) return false ; const <ISA_LIT>BaseRegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * CallerPreserved = TRI -> getCallPreservedMask ( MF , CallerCC ) ; if ( CalleeCC != CallerCC ) { const uint32_t * CalleePreserved = TRI -> getCallPreservedMask ( MF , CalleeCC ) ; if ( ! TRI -> regmaskSubsetEqual ( CallerPreserved , CalleePreserved ) ) return false ; } const <ISA_LIT>FunctionInfo * AFI_Caller = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI_Caller -> getArgRegsSaveSize ( ) ) return false ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CCAssignFnForCall ( CalleeCC , isVarArg ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ;

const TargetInstrInfo * TII = Subtarget -> getInstrInfo ( ) ;


<s> bool <ISA_LIT>TTIImpl :: forceScalarizeMaskedGather ( VectorType * VTy , Align Alignment ) {

unsigned NumElts = cast < FixedVectorType > ( VTy ) -> getNumElements ( ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> auto * PtrTy = cast < PointerType > ( I -> getOperand ( TypeOp ) -> getType ( ) ) ;

auto * VecTy = cast < FixedVectorType > ( PtrTy -> getElementType ( ) ) ;


<s> bool AMDGPUInstrInfo :: DefinesPredicate ( MachineInstr * MI , std :: vector < MachineOperand > & Pred ) const {


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT VT , unsigned AddrSpace , unsigned Alignment , MachineMemOperand :: Flags Flags , bool * Fast ) const { MVT SVT = VT . getSimpleVT ( ) ;

if ( Subtarget . isHVXVectorType ( SVT , true ) ) return allowsHvxMisalignedMemoryAccesses ( SVT , Alignment , Flags , Fast ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( auto & Loc : RVLocs ) { SDValue RV = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) ; Chain = RV . getValue ( <NUM_LIT> ) ; InGlue = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( RV ) ;


<s> return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ;


<s> switch ( AM . Scale ) { case <NUM_LIT> : break ; case <NUM_LIT> : if ( ! AM . HasBaseReg ) break ; return false ; default : return false ;


<s> unsigned GCNTTIImpl :: getLoadStoreVecRegBitWidth ( unsigned AddrSpace ) const { if ( AddrSpace == <ISA_LIT>AS :: GLOBAL_ADDRESS || AddrSpace == <ISA_LIT>AS :: CONSTANT_ADDRESS || AddrSpace == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) { return <NUM_LIT> ; } if ( AddrSpace == <ISA_LIT>AS :: FLAT_ADDRESS || AddrSpace == <ISA_LIT>AS :: LOCAL_ADDRESS || AddrSpace == <ISA_LIT>AS :: REGION_ADDRESS ) return <NUM_LIT> ; if ( AddrSpace == <ISA_LIT>AS :: PRIVATE_ADDRESS ) return <NUM_LIT> * ST -> getMaxPrivateElementSize ( ) ;


<s> bool s390_hard_regno_rename_ok ( unsigned int old_reg , unsigned int new_reg ) { if ( cfun -> machine -> base_reg ) if ( REGNO ( cfun -> machine -> base_reg ) == old_reg || REGNO ( cfun -> machine -> base_reg ) == new_reg ) return false ; if ( GENERAL_REGNO_P ( new_reg ) && ! call_really_used_regs [ new_reg ] && cfun_gpr_save_slot ( new_reg ) == SAVE_SLOT_NONE ) return false ; return true ;


<s> SDValue GA = DAG . getTargetGlobalAddress ( GV , Op . getDebugLoc ( ) , <STR_LIT> ) ; return getGlobalAddressWrapper ( GA , GV , DAG ) ;


<s> for ( DeferredEraseSetIter I = EraseSet . begin ( ) , E = EraseSet . end ( ) ; I != E ;


<s> return FixupKind == FK_<ISA_LIT>_PCrel ;


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) {


<s> if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { Parser . Lex ( ) ; isParenExpr = true ; } if ( getLexer ( ) . getKind ( ) != AsmToken :: Dollar ) { if ( parseMemOffset ( IdVal , isParenExpr ) ) return MatchOperand_ParseFail ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( Mnemonic . getToken ( ) == <STR_LIT> || Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , <STR_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = parseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) {


<s> if ( al == NULL ) { size_t buf_len ; char * linksym ; tree id ; if ( name [ <NUM_LIT> ] == '*' ) name ++ ; id = maybe_get_identifier ( name ) ; if ( id ) { while ( IDENTIFIER_TRANSPARENT_ALIAS ( id ) ) id = TREE_CHAIN ( id ) ; name = IDENTIFIER_POINTER ( id ) ; } buf_len = strlen ( name ) + <NUM_LIT> + <NUM_LIT> ; linksym = ( char * ) alloca ( buf_len ) ; snprintf ( linksym , buf_len , <STR_LIT> , cfun -> funcdef_no , name ) ;


<s> if ( save_blink ) { reg = gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ; frame_allocated += frame_save_reg ( reg , offset ) ; offset = <NUM_LIT> ; } if ( reg_size || offset ) { frame_stack_add ( offset - reg_size ) ; frame_allocated += nregs * UNITS_PER_WORD - offset ; offset = <NUM_LIT> ; } insn = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nregs + <NUM_LIT> ) ) ; indx = <NUM_LIT> ; XVECEXP ( insn , <NUM_LIT> , nregs ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) ) ; for ( regno = start_reg , indx = <NUM_LIT> , off = <NUM_LIT> ; regno <= end_reg ; regno ++ , indx ++ , off += UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; XVECEXP ( insn , <NUM_LIT> , indx ) = gen_rtx_SET ( mem , reg ) ; RTX_FRAME_RELATED_P ( XVECEXP ( insn , <NUM_LIT> , indx ) ) = <NUM_LIT> ; gmask = gmask & ~ ( <NUM_LIT> << regno ) ; } insn = frame_insn ( insn ) ; for ( regno = start_reg , off = <NUM_LIT> ; regno <= end_reg ; regno ++ , off += UNITS_PER_WORD ) { reg = gen_rtx_REG ( SImode , regno ) ; mem = gen_rtx_MEM ( SImode , plus_constant ( Pmode , stack_pointer_rtx , off ) ) ; add_reg_note ( insn , REG_CFA_OFFSET , gen_rtx_SET ( mem , reg ) ) ; } if ( arc_must_save_return_addr ( cfun ) ) { emit_insn ( gen_rtx_SET ( gen_rtx_REG ( Pmode , RETURN_ADDR_REGNUM ) , gen_rtx_MEM ( Pmode , plus_constant ( Pmode , stack_pointer_rtx , reg_size ) ) ) ) ; } for ( regno = <NUM_LIT> ; regno <= GMASK_LEN ; regno ++ ) {

if ( ( gmask & ( <NUM_LIT> << regno ) ) == <NUM_LIT> ) continue ;


<s> <ISA_LIT>AsmBackend ( uint8_t OSABI ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( OSABI ) {


<s> if ( Subtarget . isPICStyleRIPRel ( ) ) return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ;


ret . val [ <NUM_LIT> ] = ( float16x8_t ) __builtin_aarch64_get_qregoiv8hf ( __o , <NUM_LIT> ) ;


<s> else llvm_unreachable ( <STR_LIT> ) ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int64_t Offset = SPOffsetFromCFA + RegSpillOffsets [ Reg ] ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , true ) , Offset ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } } uint64_t StackSize = getAllocatedStackSize ( MF ) ; if ( StackSize ) { bool StoreBackchain = MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > CFIIndexes ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned IgnoredFrameReg ; int64_t Offset = getFrameIndexReference ( MF , Save . getFrameIdx ( ) , IgnoredFrameReg ) ;

unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DwarfReg , SPOffsetFromCFA + Offset ) ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> DT = & getAnalysis < DominatorTreeWrapperPass > ( ) . getDomTree ( ) ;


<s> MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; MMI -> AnalyzeModule ( M ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( OutContext , * TM . getDataLayout ( ) ) ; emitHeader ( M , OS1 ) ; OutStreamer . EmitRawText ( OS1 . str ( ) ) ; if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) recordAndEmitFilenames ( M ) ; SmallString < <NUM_LIT> > Str2 ; raw_svector_ostream OS2 ( Str2 ) ; emitDeclarations ( M , OS2 ) ; SmallVector < GlobalVariable * , <NUM_LIT> > Globals ; DenseSet < GlobalVariable * > GVVisited ; DenseSet < GlobalVariable * > GVVisiting ;

for ( Module :: global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT ) ; ResultReg = createResultReg ( RC ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOLoad ) ;


<s> void addInstSyncBarrierOptOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( unsigned ( getInstSyncBarrierOpt ( ) ) ) ) ;


return ( to != GENERAL_REGS ? <NUM_LIT> : <NUM_LIT> ) ;


<s> std :: vector < std :: string > ret ( Cond c ) {


<s> LImm = ( Insn >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( LImm ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; return MCDisassembler :: Success ;


<s> if ( ! isImm ( ) ) return false ; int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;

bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ;


<s> assert ( ! I -> getOperand ( <NUM_LIT> ) . getImm ( ) && hasFP ( MF ) && <STR_LIT> ) ; const auto * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; if ( I -> getOpcode ( ) == TII -> getCallFrameDestroyOpcode ( ) && needsSPWriteback ( MF , * MF . getFrameInfo ( ) ) ) {


<s> } } } FOR_EACH_BB_FN ( bb , cfun ) { rtx_insn * end = BB_END ( bb ) ; rtx_insn * call_insn = NULL ; if ( bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) { rtx_insn * label = NULL ; for ( insn = BB_HEAD ( bb ) ; insn != end ; insn = NEXT_INSN ( insn ) ) { if ( LABEL_P ( insn ) ) label = insn ; if ( NOTE_INSN_BASIC_BLOCK_P ( insn ) ) label = insn ; if ( INSN_P ( insn ) ) break ; } gcc_assert ( label ) ; emit_insn_after ( aarch64_speculation_establish_tracker ( ) , label ) ; } for ( insn = BB_HEAD ( bb ) ; ; insn = NEXT_INSN ( insn ) ) { if ( NONDEBUG_INSN_P ( insn ) && recog_memoized ( insn ) >= <NUM_LIT> && ( get_attr_speculation_barrier ( insn ) == SPECULATION_BARRIER_TRUE ) ) { if ( call_insn ) { emit_insn_after ( aarch64_speculation_establish_tracker ( ) , call_insn ) ; call_insn = NULL ; } needs_tracking = true ; } if ( CALL_P ( insn ) ) { bool tailcall = ( SIBLING_CALL_P ( insn ) || find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) ; if ( tailcall && ( need_second_pass || ! needs_tracking ) ) { fixups_pending ++ ; need_second_pass = true ; break ; } needs_tracking = true ; if ( ! call_insn ) emit_insn_before ( aarch64_speculation_clobber_sp ( ) , insn ) ; if ( ! tailcall ) call_insn = insn ; else call_insn = NULL ; } if ( insn == end ) break ; } if ( call_insn ) { rtx_insn * seq = aarch64_speculation_establish_tracker ( ) ; for ( insn = call_insn ; insn != end && DEBUG_INSN_P ( NEXT_INSN ( insn ) ) ; insn = NEXT_INSN ( insn ) ) ; if ( insn == end ) { edge e = find_fallthru_edge ( bb -> succs ) ; if ( e ) { if ( ! INSN_P ( seq ) ) { start_sequence ( ) ; emit_insn ( seq ) ; seq = get_insns ( ) ; end_sequence ( ) ; } for ( rtx_insn * list = seq ; list ; list = NEXT_INSN ( list ) ) INSN_LOCATION ( list ) = INSN_LOCATION ( call_insn ) ; insert_insn_on_edge ( seq , e ) ; } } else emit_insn_after ( seq , call_insn ) ; } } if ( needs_tracking ) { if ( need_second_pass ) { FOR_EACH_BB_FN ( bb , cfun ) { insn = BB_END ( bb ) ; while ( insn != BB_HEAD ( bb ) && NOTE_P ( insn ) ) insn = PREV_INSN ( insn ) ; if ( ( control_flow_insn_p ( insn ) && GET_CODE ( PATTERN ( insn ) ) == RETURN ) || ( CALL_P ( insn ) && ( SIBLING_CALL_P ( insn ) || find_reg_note ( insn , REG_NORETURN , NULL_RTX ) ) ) ) {

rtx_insn * seq = aarch64_speculation_clobber_sp ( ) ;


<s> SDValue Shift = DAG . getNode ( <STR_LIT> , DL , XLenVT , RMValue , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; SDValue Shifted = DAG . getNode ( <STR_LIT> , DL , XLenVT , DAG . getConstant ( Table , DL , XLenVT ) , Shift ) ; RMValue = DAG . getNode ( <STR_LIT> , DL , XLenVT , Shifted , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , SysRegNo , RMValue ) ;


<s> for ( auto * MI : Killed ) BasicBlocks . insert ( MI -> getParent ( ) ) ; std :: map < MachineInstr * , SmallPtrSet < MachineInstr * , <NUM_LIT> >> ITBlocks ; for ( auto * MBB : BasicBlocks ) { for ( auto & MI : * MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; RDA -> getReachingLocalUses ( & MI , <STR_LIT> , ITBlocks [ & MI ] ) ; } } SmallPtrSet < MachineInstr * , <NUM_LIT> > ModifiedITs ; for ( auto * MI : Killed ) { if ( MachineOperand * MO = MI -> findRegisterUseOperand ( <STR_LIT> ) ) { MachineInstr * IT = RDA -> getMIOperand ( MI , * MO ) ; auto & CurrentBlock = ITBlocks [ IT ] ; CurrentBlock . erase ( MI ) ; if ( CurrentBlock . empty ( ) ) ModifiedITs . erase ( IT ) ; else ModifiedITs . insert ( IT ) ; } } if ( ModifiedITs . empty ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; for ( auto * MI : Killed ) dbgs ( ) << <STR_LIT> << * MI ) ;

LoLoop . ToRemove . insert ( Killed . begin ( ) , Killed . end ( ) ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateFPImm ( APFloat Val , bool IsExact , SMLoc S , MCContext & Ctx ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_FPImm , Ctx ) ; Op -> FPImm . Val = Val . bitcastToAPInt ( ) . getSExtValue ( ) ; Op -> FPImm . IsExact = IsExact ; Op -> StartLoc = S ; Op -> EndLoc = S ;


<s> break ; case CCValAssign :: AExtUpper : UseUpperBits = true ; case CCValAssign :: AExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: ZExtUpper : UseUpperBits = true ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; case CCValAssign :: SExtUpper : UseUpperBits = true ; case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val ) ; break ; } if ( UseUpperBits ) { unsigned ValSizeInBits = Outs [ i ] . ArgVT . getSizeInBits ( ) ; unsigned LocSizeInBits = VA . getLocVT ( ) . getSizeInBits ( ) ; Val = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Val , DAG . getConstant ( LocSizeInBits - ValSizeInBits , VA . getLocVT ( ) ) ) ; } Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ;

unsigned V0 = Subtarget . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ;


<s> SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ;

return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( Subtarget -> has64BitPointers ( ) ? <NUM_LIT> : <NUM_LIT> ) , Subtarget -> has64BitPointers ( ) ? <NUM_LIT> : <NUM_LIT> , false , false , false , MachinePointerInfo ( DstSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> unsigned Reg = Op . getReg ( ) ; printRegName ( O , Reg ) ; } else if ( Op . isImm ( ) ) { O << markup ( <STR_LIT> ) << formatImm ( Op . getImm ( ) ) << markup ( <STR_LIT> ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; Op . getExpr ( ) -> print ( O , & MAI ) ; }


<s> for ( MachineBasicBlock :: reverse_iterator I ( slot ) ; I != MBB . rend ( ) ; ++ I ) { if ( I -> isDebugValue ( ) ) continue ; MachineBasicBlock :: iterator FI ( llvm :: next ( I ) . base ( ) ) ; if ( I -> hasUnmodeledSideEffects ( ) || I -> isInlineAsm ( ) || I -> isLabel ( ) || FI == LastFiller || I -> getDesc ( ) . isPseudo ( ) ) break ; if ( delayHasHazard ( FI , sawLoad , sawStore , RegDefs , RegUses ) ) {

insertDefsUses ( FI , RegDefs , RegUses ) ;


<s> auto SetOffset = DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ; auto PCC = DAG . getNode ( <STR_LIT> , DL , CapType , GetPCC ) ;

return DAG . getNode ( <STR_LIT> , DL , CapType , SetOffset , PCC , Offset ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> if ( VT . getSizeInBits ( ) . getKnownMinSize ( ) > <STR_LIT> ) return SDValue ( ) ; EVT ContainerVT = VT ; if ( ContainerVT . isInteger ( ) ) ContainerVT = getSVEContainerType ( ContainerVT ) ; SDVTList VTs = DAG . getVTList ( ContainerVT , <STR_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getValueType ( VT ) } ; SDValue Load = DAG . getNode ( Opc , DL , VTs , Ops ) ; SDValue LoadChain = SDValue ( Load . getNode ( ) , <NUM_LIT> ) ; if ( ContainerVT . isInteger ( ) && ( VT != ContainerVT ) ) Load = DAG . getNode ( <STR_LIT> , DL , VT , Load . getValue ( <NUM_LIT> ) ) ;

return DAG . getMergeValues ( { Load , LoadChain } , DL ) ;


<s> unsigned Reg = Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO1 . getReg ( ) ) ; const MCOperand & MO = MI . getOperand ( <NUM_LIT> ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int64_t Count = MO . getImm ( ) ;

assert ( ( Count >= <NUM_LIT> && Count <= <NUM_LIT> ) && <STR_LIT> ) ;


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: Static ; return * RM ;


<s> OffsetRange & extendBy ( int32_t D ) { assert ( D % Align == <NUM_LIT> ) ; if ( D < <NUM_LIT> ) Min = ( INT_MIN - D < Min ) ? Min + D : INT_MIN ;

else Max = ( INT_MAX - D > Max ) ? Max + D : INT_MAX ;


<s> const MachineOperand & MO1 = MI -> getOperand ( Op ) ; const MachineOperand & MO2 = MI -> getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << getRegisterName ( MO1 . getReg ( ) ) ; O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ; if ( MO2 . getReg ( ) ) { O << getRegisterName ( MO2 . getReg ( ) ) ; assert ( <STR_LIT> ( MO3 . getImm ( ) ) == <NUM_LIT> ) ; } else { O << <STR_LIT> << <STR_LIT> ( MO3 . getImm ( ) ) ; }


<s> <ISA_LIT>CondBrFolding ( const <ISA_LIT>InstrInfo * TII , const MachineBranchProbabilityInfo * MBPI , MachineFunction & MF ) : TII ( TII ) , MBPI ( MBPI ) , MF ( MF ) {


<s> return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; case <STR_LIT> : return <STR_LIT> ( MI . getOpcode ( ) ) ; default : return - <NUM_LIT> ;


<s> SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , Src . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ; if ( Mask . getValueType ( ) != MaskVT ) Mask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ; MemIntrinsicSDNode * MemIntr = cast < MemIntrinsicSDNode > ( Op ) ; SDVTList VTs = DAG . getVTList ( MaskVT , <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Src , Mask , Base , Index , Scale } ;

SDValue Res = DAG . getTargetMemSDNode < <ISA_LIT>MaskedScatterSDNode > ( VTs , Ops , dl , MemIntr -> getMemoryVT ( ) , MemIntr -> getMemOperand ( ) ) ;


<s> O << <STR_LIT> ; printSrcIdx ( MI , OpNo , O ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) {


<s> virtual const char * getPassName ( ) const {


if ( ! isTailCall && CS && CS . isMustTailCall ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ;


<s> unsigned VGPRPressure = Pressure [ SRI -> getVGPRPressureSet ( ) ] ; ReadyQueue & Q = Zone . Available ; for ( SUnit * SU : Q ) { SchedCandidate TryCand ( ZonePolicy ) ; initCandidate ( TryCand , SU , Zone . isTop ( ) , RPTracker , SRI , SGPRPressure , VGPRPressure ) ; SchedBoundary * ZoneArg = Cand . AtTop == TryCand . AtTop ? & Zone : nullptr ;

GenericScheduler :: tryCandidate ( Cand , TryCand , ZoneArg ) ;


<s> index = XEXP ( x , <NUM_LIT> ) ; * size = ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; } else { index = x ; * size = <NUM_LIT> ; } if ( GET_CODE ( index ) == MULT && GET_CODE ( XEXP ( index , <NUM_LIT> ) ) == CONST_INT && ( factor == <NUM_LIT> || factor == INTVAL ( XEXP ( index , <NUM_LIT> ) ) ) ) return XEXP ( index , <NUM_LIT> ) ;


return __builtin_ia32_movmskps256 ( ( __v8sf ) __A ) ;


<s> return Query . Types [ TypeIdx0 ] . getSizeInBits ( ) > Query . Types [ TypeIdx1 ] . getSizeInBits ( ) ;


<s> O << <STR_LIT> << * CurrentFnSym << <STR_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> if ( AM . hasIndexField ( ) && ! AM . Index . getNode ( ) ) { AM . Base = Base ; AM . Index = Index ;


<s> if ( NumArg != <NUM_LIT> && NumArg != <NUM_LIT> ) return false ; auto * PacketSize = CI -> getArgOperand ( NumArg - <NUM_LIT> ) ; auto * PacketAlign = CI -> getArgOperand ( NumArg - <NUM_LIT> ) ; if ( ! isa < ConstantInt > ( PacketSize ) || ! isa < ConstantInt > ( PacketAlign ) ) return false ; unsigned Size = cast < ConstantInt > ( PacketSize ) -> getZExtValue ( ) ; unsigned Align = cast < ConstantInt > ( PacketAlign ) -> getZExtValue ( ) ; if ( Size != Align || ! isPowerOf2_32 ( Size ) ) return false ; Type * PtrElemTy ; if ( Size <= <NUM_LIT> ) PtrElemTy = Type :: getIntNTy ( Ctx , Size * <NUM_LIT> ) ; else PtrElemTy = VectorType :: get ( Type :: getInt64Ty ( Ctx ) , Size / <NUM_LIT> ) ; unsigned PtrArgLoc = CI -> getNumArgOperands ( ) - <NUM_LIT> ; auto PtrArg = CI -> getArgOperand ( PtrArgLoc ) ; unsigned PtrArgAS = PtrArg -> getType ( ) -> getPointerAddressSpace ( ) ; auto * PtrTy = llvm :: PointerType :: get ( PtrElemTy , PtrArgAS ) ; SmallVector < llvm :: Type * , <NUM_LIT> > ArgTys ; for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) ArgTys . push_back ( CI -> getArgOperand ( I ) -> getType ( ) ) ; ArgTys . push_back ( PtrTy ) ; Name = Name + <STR_LIT> + std :: to_string ( Size ) ; auto * FTy = FunctionType :: get ( Callee -> getReturnType ( ) , ArrayRef < Type * > ( ArgTys ) , false ) ; <ISA_LIT>LibFunc NewLibFunc ( Name , FTy ) ; FunctionCallee F = <ISA_LIT>LibFunc :: getOrInsertFunction ( M , NewLibFunc ) ; if ( ! F ) return false ; auto * BCast = B . CreatePointerCast ( PtrArg , PtrTy ) ; SmallVector < Value * , <NUM_LIT> > Args ; for ( unsigned I = <NUM_LIT> ; I != PtrArgLoc ; ++ I ) Args . push_back ( CI -> getArgOperand ( I ) ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseCoprocNumOperand ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; int Num = MatchCoprocessorOperandName ( Tok . getString ( ) , 'p' ) ; if ( Num == - <NUM_LIT> ) return MatchOperand_NoMatch ; if ( ( hasV7Ops ( ) || hasV8Ops ( ) ) && ( Num == <NUM_LIT> || Num == <NUM_LIT> ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreateCoprocNum ( Num , S ) ) ;


<s> if ( VecLen == <NUM_LIT> || VT . isScalableVector ( ) ) return TargetLoweringBase :: TypeScalarizeVector ; if ( Subtarget . useHVXOps ( ) ) { unsigned HwLen = Subtarget . getVectorLength ( ) ; ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: find ( Tys , ElemTy ) != Tys . end ( ) ) { unsigned HwWidth = <NUM_LIT> * HwLen ; unsigned VecWidth = VT . getSizeInBits ( ) ;

if ( VecWidth >= HwWidth / <NUM_LIT> && VecWidth < HwWidth ) return TargetLoweringBase :: TypeWidenVector ;


<s> return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DL , DAG ) ) ) ; } assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] != - <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] < <NUM_LIT> && <STR_LIT> ) ; assert ( Mask [ <NUM_LIT> ] >= <NUM_LIT> && <STR_LIT> ) ; if ( Subtarget . hasAVX2 ( ) ) if ( SDValue Extract = lowerShuffleOfExtractsAsVperm ( DL , V1 , V2 , Mask , DAG ) ) return Extract ; if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] ^ <NUM_LIT> , Mask [ <NUM_LIT> ] ^ <NUM_LIT> } ; if ( SDValue Insertion = lowerShuffleAsElementInsertion ( DL , <STR_LIT> , V2 , V1 , InverseMask , Zeroable , Subtarget , DAG ) ) return Insertion ;

bool IsBlendSupported = Subtarget . hasSSE41 ( ) ;


<s> case TYPE_DPACK : case TYPE_DINSB : case TYPE_DCMP : case TYPE_DCLIP : case TYPE_DALUROUND : use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_ALU_SHIFT : use_rtx = extract_shift_reg ( consumer ) ; break ; case TYPE_PBSADA : return pbsada_insn_ra_rb_dep_reg_p ( consumer , def_reg ) ; case TYPE_MAC : case TYPE_DMAC : use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( divmod_p ( consumer ) ) use_rtx = SET_SRC ( parallel_element ( consumer , <NUM_LIT> ) ) ;

else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ;


<s> operands [ <NUM_LIT> ] = sp ; } emit_insn ( gen_eh_epilogue ( operands [ <NUM_LIT> ] ) ) ;


<s> return __builtin_mve_vshlltq_m_n_uv8hi ( __arm_vuninitializedq_u32 ( ) , __a , __imm , __p ) ;