<s> case <STR_LIT> : return ExpandPUSH_POP ( MIB , get ( <STR_LIT> ) , false ) ; case <STR_LIT> : return ExpandPUSH_POP ( MIB , get ( <STR_LIT> ) , false ) ; case <STR_LIT> : return ExpandPUSH_POP ( MIB , get ( <STR_LIT> ) , false ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; }


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; assert ( MFI -> getShaderType ( ) == ShaderType :: PIXEL || MFI -> getShaderType ( ) == ShaderType :: GEOMETRY ) ; if ( ( Op . isImm ( ) ) ) { if ( Op . getImm ( ) & <NUM_LIT> ) {

BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> rtx select0 = XEXP ( concat , <NUM_LIT> ) ; rtx select1 = XEXP ( concat , <NUM_LIT> ) ; if ( GET_CODE ( select0 ) != VEC_SELECT || GET_CODE ( select1 ) != VEC_SELECT ) return false ; rtx reg0 = XEXP ( select0 , <NUM_LIT> ) ; rtx reg1 = XEXP ( select1 , <NUM_LIT> ) ; if ( ! rtx_equal_p ( reg0 , reg1 ) || ! REG_P ( reg0 ) ) return false ;

rtx parallel0 = XEXP ( select0 , <NUM_LIT> ) ;


<s> SDValue AllOnes = DAG . getConstant ( APInt :: getAllOnesValue ( NumEltBits ) , DL , EltVT ) ; SmallVector < SDValue , <NUM_LIT> > MaskOps ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { if ( Mask [ i ] != - <NUM_LIT> && Mask [ i ] != i && Mask [ i ] != i + Size ) return SDValue ( ) ; MaskOps . push_back ( Mask [ i ] < Size ? AllOnes : Zero ) ; }

SDValue V1Mask = DAG . getNode ( <STR_LIT> , DL , VT , MaskOps ) ;


<s> ScheduleDAGInstrs * createMachineScheduler ( MachineSchedContext * C ) const override { ScheduleDAGMILive * DAG = createGenericSchedLive ( C ) ;

DAG -> addMutation ( createLoadClusterDAGMutation ( DAG -> TII , DAG -> TRI ) ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx ) : MCII ( mcii ) , Ctx ( ctx ) {


<s> <ISA_LIT>_64TargetMachine :: <ISA_LIT>_64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) , DL ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , JITInfo ( * this ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {


<s> if ( MF . getTarget ( ) . Options . UnsafeFPMath ) return true ; const Function & F = MF . getFunction ( ) ;

return F . getFnAttribute ( <STR_LIT> ) . getValueAsBool ( ) ;


<s> if ( I . getOperand ( oi - <NUM_LIT> ) . getMBB ( ) == CmpBB ) { I . removeOperand ( oi - <NUM_LIT> ) ; I . removeOperand ( oi - <NUM_LIT> ) ; } } }


<s> O << TM . getRegisterInfo ( ) -> get ( MO . getReg ( ) ) . AsmName ; } else if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; } else { printOp ( MO ) ;


<s> bool <ISA_LIT>InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ^ Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> return ( uint32x4_t ) __builtin_neon_vreinterpretv4siv8hi ( __a ) ;


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , uint8_t _OSABI ) : <ISA_LIT>AsmBackend ( T , TT ) , OSABI ( _OSABI ) {


<s> NeedBlockSplit = true ; break ; } } unsigned Opcode = OrOpc ; MachineBasicBlock * SplitBB = & MBB ; if ( NeedBlockSplit ) { SplitBB = MBB . splitAt ( MI , true , LIS ) ; if ( MDT && SplitBB != & MBB ) { MachineDomTreeNode * MBBNode = ( * MDT ) [ & MBB ] ; SmallVector < MachineDomTreeNode * > Children ( MBBNode -> begin ( ) , MBBNode -> end ( ) ) ; MachineDomTreeNode * SplitBBNode = MDT -> addNewBlock ( SplitBB , & MBB ) ; for ( MachineDomTreeNode * Child : Children ) MDT -> changeImmediateDominator ( Child , SplitBBNode ) ;


<s> ST = & mf . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = mf . getSubtarget ( ) . getInstrInfo ( ) ; DomTree = & getAnalysis < MachineDominatorTree > ( ) ;

VRM = & getAnalysis < VirtRegMap > ( ) ;


<s> static rtx emit_frame_insn ( rtx x ) { x = emit_insn ( x ) ; RTX_FRAME_RELATED_P ( x ) = <NUM_LIT> ;


<s> index_iterator index_end ( ) const { return V . set_bits_end ( ) ;


<s> MachineBasicBlock :: iterator <ISA_LIT>InstrInfo :: insertOutlinedCall ( Module & M , MachineBasicBlock & MBB , MachineBasicBlock :: iterator & It , MachineFunction & MF , outliner :: Candidate & C ) const { if ( C . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } return It ;


<s> void <ISA_LIT>SPReduce :: getStackLocPair ( int & fi , unsigned & bitpos , const unsigned stloc ) const {

fi = PMFI -> getSinglePathExcessSpillFI ( stloc / <NUM_LIT> ) ;


<s> MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addImm ( ShiftOpc ) ; MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; return constrainSelectedInstRegOperands ( * MIB , TII , TRI , RBI ) ;


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> IsGlobalInSmallSection ( const GlobalValue * GV , const TargetMachine & TM , SectionKind Kind ) const { const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

if ( ! Subtarget . useSmallSection ( ) ) return false ;


<s> SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler * Mang , const TargetMachine & TM ) const {

if ( Kind . isBSS ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallBSSSection ;


<s> } <ISA_LIT>Operand & RegOpnd = static_cast < <ISA_LIT>Operand & > ( * Reg [ <NUM_LIT> ] ) ; if ( ! RegOpnd . isGPRAsmReg ( ) ) { reportParseError ( RegOpnd . getStartLoc ( ) , <STR_LIT> ) ;


<s> <ISA_LIT>Combiner :: <ISA_LIT>Combiner ( ) : MachineFunctionPass ( ID ) {

initialize<ISA_LIT>CombinerPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> static bool canGuaranteeTCO ( CallingConv :: ID CC ) {

return ( CC == CallingConv :: Fast || CC == CallingConv :: GHC || CC == CallingConv :: <ISA_LIT>_RegCall || CC == CallingConv :: HiPE || CC == CallingConv :: HHVM ) ;


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const override {


<s> GepNode ( ) : Flags ( <NUM_LIT> ) , Parent ( nullptr ) , Idx ( nullptr ) , PTy ( nullptr ) {


<s> printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isPredicateLate ( unsigned Opcode ) const { const uint64_t F = get ( Opcode ) . TSFlags ;

return ~ ( F >> <STR_LIT> ) & <STR_LIT> ;


<s> <STR_LIT> <ISA_LIT>RegBankCombinerHelper :: getMode ( ) {

return MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMode ( ) ;


<s> if ( ! isLoadTypeLegal ( I -> getType ( ) , VT ) ) return false ; Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) : nullptr ; Register ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , RC , true , <ISA_LIT>SubTarget -> hasSPE ( ) ? <STR_LIT> : <STR_LIT> ) ) return false ; updateValueMap ( I , ResultReg ) ; return true ;


<s> <ISA_LIT>16FrameLowering :: <ISA_LIT>16FrameLowering ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>FrameLowering ( STI , STI . getStackAlignment ( ) ) {


<s> AtomicSDNode * AN = cast < AtomicSDNode > ( Op . getNode ( ) ) ; RHS = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( - <NUM_LIT> , dl , VT ) , RHS ) ;

return DAG . getAtomic ( <STR_LIT> , dl , AN -> getMemoryVT ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , RHS , AN -> getMemOperand ( ) ) ;


<s> bool IsLargeCodeModel = MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ; unsigned CallOp ; if ( Is64Bit ) CallOp = IsLargeCodeModel ? <STR_LIT> : <STR_LIT> ; else CallOp = <STR_LIT> ; const char * Symbol ; if ( Is64Bit ) { if ( STI . isTargetCygMing ( ) ) { Symbol = <STR_LIT> ; } else { Symbol = <STR_LIT> ; } } else if ( STI . isTargetCygMing ( ) ) Symbol = <STR_LIT> ; else Symbol = <STR_LIT> ; MachineInstrBuilder CI ; MachineBasicBlock :: iterator ExpansionMBBI = std :: prev ( MBBI ) ; if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( Symbol ) ; CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addReg ( <STR_LIT> ) ; } else { CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addExternalSymbol ( Symbol ) ; } CI -> setFlags ( CI -> getFlags ( ) | MachineInstr :: FrameSetup ) ; unsigned AX = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned SP = Is64Bit ? <STR_LIT> : <STR_LIT> ; CI . addReg ( AX , RegState :: Implicit ) . addReg ( SP , RegState :: Implicit ) . addReg ( AX , RegState :: Define | RegState :: Implicit ) . addReg ( SP , RegState :: Define | RegState :: Implicit ) . addReg ( <STR_LIT> , RegState :: Define | RegState :: Implicit ) ; if ( Is64Bit ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } if ( InProlog ) { for ( ++ ExpansionMBBI ; ExpansionMBBI != MBBI ; ++ ExpansionMBBI ) ExpansionMBBI -> setFlag ( MachineInstr :: FrameSetup ) ; }


<s> char buf [ <NUM_LIT> ] ; buf [ <NUM_LIT> ] = uint8_t ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ; buf [ <NUM_LIT> ] = uint8_t ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) ;

buf [ <NUM_LIT> ] = uint8_t ( Value & <NUM_LIT> ) ;


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> && Op -> isOnlyUserOf ( Vec . getNode ( ) ) ) { int DWordIdx = IdxVal / <NUM_LIT> ; if ( DWordIdx == <NUM_LIT> ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( DWordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } int WordIdx = IdxVal / <NUM_LIT> ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( WordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ;

int Mask [ <NUM_LIT> ] = { static_cast < int > ( IdxVal ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ;


<s> enum csky_inline_const_type trick_type ; rtx out_operands [ <NUM_LIT> ] ; char buf [ <NUM_LIT> ] ; char load_op [ <NUM_LIT> ] ; const char * dst_fmt ; HOST_WIDE_INT value = INTVAL ( operands [ <NUM_LIT> ] ) ; int ivalue = ( int ) value ; unsigned int uvalue = ( unsigned int ) value ; trick_type = try_csky_constant_tricks ( value , & x , & y ) ; gcc_assert ( trick_type != IC_UNINLINABLE ) ; out_operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; out_operands [ <NUM_LIT> ] = GEN_INT ( x ) ; if ( trick_type != IC_SINGLE && trick_type != IC_APPEND_NOT ) out_operands [ <NUM_LIT> ] = GEN_INT ( y ) ; if ( mode == DImode && TARGET_BIG_ENDIAN ) dst_fmt = <STR_LIT> ; else dst_fmt = <STR_LIT> ; if ( CSKY_CONST_OK_FOR_I ( x ) ) sprintf ( load_op , <STR_LIT> , dst_fmt ) ; else if ( CSKY_CONST_OK_FOR_Uc ( x ) ) sprintf ( load_op , <STR_LIT> , dst_fmt ) ; else if ( CSKY_CONST_OK_FOR_MOVIH ( x ) ) sprintf ( load_op , <STR_LIT> , dst_fmt ) ; else { sprintf ( load_op , <STR_LIT> , dst_fmt ) ; gcc_unreachable ( ) ; } switch ( trick_type ) { case IC_SINGLE : strcpy ( buf , load_op ) ; break ; case IC_APPEND_NOT : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , dst_fmt , ivalue , uvalue ) ; break ; case IC_APPEND_ADDI : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , dst_fmt , ivalue , uvalue ) ; break ; case IC_APPEND_SUBI : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , dst_fmt , ivalue , uvalue ) ; break ; case IC_BGENI_ADDI : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , dst_fmt , ivalue , uvalue ) ; break ; case IC_BGENI_SUBI : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , dst_fmt , ivalue , uvalue ) ; break ; case IC_APPEND_BSETI : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , dst_fmt , ivalue , uvalue ) ; break ; case IC_APPEND_MOVI : sprintf ( buf , <STR_LIT> , load_op , dst_fmt , ivalue , uvalue ) ;


<s> SDLoc DL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > VTBLMask ; for ( int I : ShuffleMask ) VTBLMask . push_back ( DAG . getConstant ( I , DL , <STR_LIT> ) ) ; if ( V2 . getNode ( ) -> isUndef ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getBuildVector ( <STR_LIT> , DL , VTBLMask ) ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getBuildVector ( <STR_LIT> , DL , VTBLMask ) ) ;


<s> <ISA_LIT>MachineFunctionInfo ( const MachineFunction & MF ) {


<s> sysctlbyname ( <STR_LIT> , & l1_line , & len , NULL , <NUM_LIT> ) ;


<s> unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getConstant ( NormalizedIdxVal , <STR_LIT> ) ;

Result = DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec , VecIdx ) ;


<s> if ( TII -> getNamedOperand ( Inst , <STR_LIT> :: gds ) -> getImm ( ) != <NUM_LIT> ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , GDS_ACCESS , Inst ) ; ScoreBrackets -> updateByEvent ( TII , TRI , MRI , GDS_GPR_LOCK , Inst ) ; } else { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , LDS_ACCESS , Inst ) ; } } else if ( TII -> isFLAT ( Inst ) ) { assert ( Inst . mayLoad ( ) || Inst . mayStore ( ) ) ; ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; ScoreBrackets -> updateByEvent ( TII , TRI , MRI , LDS_ACCESS , Inst ) ; bool FoundLDSMem = false ; for ( const MachineMemOperand * Memop : Inst . memoperands ( ) ) { unsigned AS = Memop -> getAddrSpace ( ) ; if ( AS == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) FoundLDSMem = true ; } if ( FoundLDSMem ) { ScoreBrackets -> setPendingFlat ( ) ; } } else if ( <ISA_LIT>InstrInfo :: isVMEM ( Inst ) && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; if ( ( Inst . mayStore ( ) || <STR_LIT> ( Inst . getOpcode ( ) ) ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMW_GPR_LOCK , Inst ) ; } } else if ( TII -> isSMRD ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SMEM_ACCESS , Inst ) ; } else { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SQ_MESSAGE , Inst ) ; break ; case <STR_LIT> : case <STR_LIT> : { int Imm = TII -> getNamedOperand ( Inst , <STR_LIT> :: tgt ) -> getImm ( ) ; if ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , EXP_PARAM_ACCESS , Inst ) ; else if ( Imm >= <NUM_LIT> && Imm <= <NUM_LIT> ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , EXP_POS_ACCESS , Inst ) ; else ScoreBrackets -> updateByEvent ( TII , TRI , MRI , EXP_GPR_LOCK , Inst ) ; break ; } case <STR_LIT> : case <STR_LIT> : ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SMEM_ACCESS , Inst ) ; break ; default : break ; } }


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( isRegShiftedReg ( ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( RegShiftedReg . SrcReg ) ) ; Inst . addOperand ( MCOperand :: createReg ( RegShiftedReg . ShiftReg ) ) ;

Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ( RegShiftedReg . ShiftTy , RegShiftedReg . ShiftImm ) ) ) ;


<s> SDValue VAListPtr = Node -> getOperand ( <NUM_LIT> ) ; EVT PtrVT = VAListPtr . getValueType ( ) ; const Value * SV = cast < SrcValueSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Node ) ; SDValue VAList = DAG . getLoad ( PtrVT , DL , InChain , VAListPtr , MachinePointerInfo ( SV ) , false , false , false , <NUM_LIT> ) ; SDValue NextPtr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getIntPtrConstant ( VT . getSizeInBits ( ) / <NUM_LIT> , DL ) ) ; InChain = DAG . getStore ( VAList . getValue ( <NUM_LIT> ) , DL , NextPtr , VAListPtr , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ; return DAG . getLoad ( VT , DL , InChain , VAList , MachinePointerInfo ( ) , false , false , false , std :: min ( PtrVT . getSizeInBits ( ) , VT . getSizeInBits ( ) ) / <NUM_LIT> ) ;


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( Subtarget -> isFPOnlySP ( ) && LHS . getValueType ( ) == <STR_LIT> ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) == <STR_LIT> ) { SDValue <ISA_LIT>cc ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , <ISA_LIT>cc , DAG , dl ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; if ( getTargetMachine ( ) . Options . UnsafeFPMath && ( CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue Result = OptimizeVFPBrcond ( Op , DAG ) ) return Result ; } <STR_LIT> CondCode , CondCode2 ; bool InvalidOnQNaN ; FPCCTo<ISA_LIT>CC ( CC , CondCode , CondCode2 , InvalidOnQNaN ) ; SDValue <ISA_LIT>cc = DAG . getConstant ( CondCode , dl , <STR_LIT> ) ; SDValue Cmp = getVFPCmp ( LHS , RHS , DAG , dl , InvalidOnQNaN ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;

SDValue Ops [ ] = { Chain , Dest , <ISA_LIT>cc , CCR , Cmp } ;


<s> InstrInfo16 . swap ( InstrInfo ) ; FrameLowering16 . swap ( FrameLowering ) ; TLInfo16 . swap ( TLInfo ) ; if ( ! InstrInfoSE ) { InstrInfo . reset ( <ISA_LIT>InstrInfo :: create ( * TM ) ) ; FrameLowering . reset ( <ISA_LIT>FrameLowering :: create ( * TM , * this ) ) ; TLInfo . reset ( <ISA_LIT>TargetLowering :: create ( * TM ) ) ; } else { InstrInfoSE . swap ( InstrInfo ) ; FrameLoweringSE . swap ( FrameLowering ) ; TLInfoSE . swap ( TLInfo ) ;


<s> static int mips_fpr_return_fields ( tree valtype , tree * fields ) { tree field ; int i ; if ( ! TARGET_NEWABI ) return <NUM_LIT> ; if ( TREE_CODE ( valtype ) != RECORD_TYPE ) return <NUM_LIT> ; i = <NUM_LIT> ; for ( field = TYPE_FIELDS ( valtype ) ; field != <NUM_LIT> ; field = TREE_CHAIN ( field ) ) {

if ( TREE_CODE ( field ) != FIELD_DECL ) continue ;


<s> assert ( ! WE -> getParentException ( ) && <STR_LIT> ) ;

TopLevelExceptions . push_back ( std :: move ( WE ) ) ;


<s> if ( ( ! State -> isFirstByValRegValid ( ) ) && ( <STR_LIT> <= reg ) && ( reg <= <STR_LIT> ) ) { State -> setFirstByValReg ( reg ) ;

if ( State -> getCallOrPrologue ( ) == Call ) {


<s> if ( to_type == NO_REG_TYPE || from_type == NO_REG_TYPE ) return false ; if ( ( to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE ) || ( to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( from_type ) ) || ( from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE ( to_type ) ) ) return true ;

if ( to_type == from_type && IS_STD_REG_TYPE ( to_type ) ) return true ;


<s> MachineIRBuilder MIRBuilder ( I ) ; switch ( IntrinID ) { default : return false ; case <STR_LIT> : MIRBuilder . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : MIRBuilder . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( <NUM_LIT> ) ; break ; case <STR_LIT> : MIRBuilder . buildInstr ( <STR_LIT> , { } , { } ) . addImm ( I . getOperand ( <NUM_LIT> ) . getImm ( ) | ( 'U' << <NUM_LIT> ) ) ; break ; } I . eraseFromParent ( ) ;


<s> addPass ( create<ISA_LIT>RelaxMemPass ( ) ) ; addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ;


<s> static SDValue performSpliceCombine ( SDNode * N , SelectionDAG & DAG ) { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ;

if ( N -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) return N -> getOperand ( <NUM_LIT> ) ;


<s> int i ; if ( GET_CODE ( dep_rtx ) == SET && addr_generation_dependency_p ( dep_rtx , insn ) ) return <NUM_LIT> ; else if ( GET_CODE ( dep_rtx ) == PARALLEL ) { for ( i = <NUM_LIT> ; i < XVECLEN ( dep_rtx , <NUM_LIT> ) ; i ++ ) { if ( addr_generation_dependency_p ( XVECEXP ( dep_rtx , <NUM_LIT> , i ) , insn ) ) return <NUM_LIT> ; }


<s> decl_op1 = SYMBOL_REF_DECL ( XEXP ( p , <NUM_LIT> ) ) ; if ( decl_op1 && GET_CODE ( XEXP ( p , <NUM_LIT> ) ) == SYMBOL_REF && ( decl_op0 = SYMBOL_REF_DECL ( XEXP ( p , <NUM_LIT> ) ) ) ) { if ( ( TREE_CODE ( decl_op1 ) == VAR_DECL || TREE_CODE ( decl_op1 ) == CONST_DECL ) && ( TREE_CODE ( decl_op0 ) == VAR_DECL || TREE_CODE ( decl_op0 ) == CONST_DECL ) ) return ( get_variable_section ( decl_op1 , false ) != get_variable_section ( decl_op0 , false ) ) ;


<s> initializeGCNRegBankReassignPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> if ( <ISA_LIT>MCInstrInfo :: isInnerLoop ( MCB ) ) { assert ( ! Duplex ) ; assert ( State . Index != Last ) ; return <STR_LIT> ; } } if ( State . Index == <NUM_LIT> ) { if ( <ISA_LIT>MCInstrInfo :: isOuterLoop ( MCB ) ) { assert ( ! Duplex ) ; assert ( State . Index != Last ) ; return <STR_LIT> ; } } if ( Duplex ) { assert ( State . Index == Last ) ; return <STR_LIT> ; } if ( State . Index == Last ) return <STR_LIT> ; return <STR_LIT> ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) { VectorComponents = <NUM_LIT> ; } else if ( ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( DestReg ) ) && ( <STR_LIT> . contains ( SrcReg ) || <STR_LIT> . contains ( SrcReg ) ) ) {


<s> Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; } AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addGlobalAddress ( GV ) ) ; } else { unsigned Align = TD . getPrefTypeAlignment ( GV -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = TD . getTypeAllocSize ( GV -> getType ( ) ) ; } if ( Subtarget -> isTargetELF ( ) && RelocM == Reloc :: PIC_ ) return <ISA_LIT>LowerPICELF ( GV , Align , VT ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned Id = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , Id , <STR_LIT> , PCAdj ) ; unsigned Idx = MCP . getConstantPoolIndex ( CPV , Align ) ; MachineInstrBuilder MIB ; if ( isThumb2 ) { unsigned Opc = ( RelocM != Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx ) ; if ( RelocM == Reloc :: PIC_ ) MIB . addImm ( Id ) ; AddOptionalDefs ( MIB ) ; } else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ; AddOptionalDefs ( MIB ) ; if ( RelocM == Reloc :: PIC_ ) { unsigned Opc = IsIndirect ? <STR_LIT> : <STR_LIT> ; unsigned NewDestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , NewDestReg ) . addReg ( DestReg ) . addImm ( Id ) ;


<s> static bool pa_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_PORTABLE_RUNTIME ) return false ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) PM . add ( createGlobalMergePass ( getTargetLowering ( ) ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != StackTop ; ++ i ) { dbgs ( ) << <STR_LIT> << Stack [ i ] ; assert ( RegMap [ Stack [ i ] ] == i && <STR_LIT> ) ; }

for ( unsigned i = <NUM_LIT> ; i != NumPendingSTs ; ++ i ) dbgs ( ) << <STR_LIT> << i << <STR_LIT> << unsigned ( PendingST [ i ] ) ;


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ;

int StackSize = ( int ) MFI -> getStackSize ( ) ;


<s> if ( GET_CODE ( SET_SRC ( curr_set ) ) == LO_SUM && REG_P ( XEXP ( SET_SRC ( curr_set ) , <NUM_LIT> ) ) && REGNO ( XEXP ( SET_SRC ( curr_set ) , <NUM_LIT> ) ) == REGNO ( SET_DEST ( prev_set ) ) && rtx_equal_p ( XEXP ( SET_SRC ( prev_set ) , <NUM_LIT> ) , XEXP ( SET_SRC ( curr_set ) , <NUM_LIT> ) ) ) return true ; } } if ( simple_sets_p && aarch64_fusion_enabled_p ( AARCH64_FUSE_MOVK_MOVK ) ) { if ( GET_CODE ( SET_DEST ( prev_set ) ) == ZERO_EXTRACT && GET_CODE ( SET_DEST ( curr_set ) ) == ZERO_EXTRACT && REG_P ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) && REG_P ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) && REGNO ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) == REGNO ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) && INTVAL ( XEXP ( SET_DEST ( prev_set ) , <NUM_LIT> ) ) == <NUM_LIT> && INTVAL ( XEXP ( SET_DEST ( curr_set ) , <NUM_LIT> ) ) == <NUM_LIT> && CONST_INT_P ( SET_SRC ( prev_set ) ) && CONST_INT_P ( SET_SRC ( curr_set ) ) ) return true ; }

if ( simple_sets_p && aarch64_fusion_enabled_p ( AARCH64_FUSE_ADRP_LDR ) ) {


<s> bool isImageWriteOnly ( const Value & val ) {

if ( const Argument * arg = dyn_cast < Argument > ( & val ) ) {


<s> int getPICBasePointerSaveIndex ( ) const {


<s> const InstrItineraryData & getInstrItineraryData ( ) const {


<s> OpHi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpHi ) ; int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; OpLo = DAG . getVectorShuffle ( <STR_LIT> , dl , OpLo , DAG . getUNDEF ( <STR_LIT> ) , ShufMask1 ) ; OpHi = DAG . getVectorShuffle ( <STR_LIT> , dl , OpHi , DAG . getUNDEF ( <STR_LIT> ) , ShufMask1 ) ; OpLo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpLo ) ; OpHi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpHi ) ; int ShufMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SDValue res = DAG . getVectorShuffle ( <STR_LIT> , dl , OpLo , OpHi , ShufMask2 ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , res ) ; } return SDValue ( ) ;


<s> bool is31 = ( getTargetMachine ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> getFnAttributes ( ) . hasNakedAttr ( ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> : <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FrameAddr ;


<s> bool <ISA_LIT>PacketizerList :: ignorePseudoInstruction ( const MachineInstr & MI , const MachineBasicBlock * ) { if ( MI . isDebugInstr ( ) ) return true ; if ( MI . isCFIInstruction ( ) ) return false ; if ( MI . isInlineAsm ( ) ) return false ; if ( MI . isImplicitDef ( ) ) return false ; const MCInstrDesc & TID = MI . getDesc ( ) ; auto * IS = ResourceTracker -> getInstrItins ( ) -> beginStage ( TID . getSchedClass ( ) ) ;


<s> bool <ISA_LIT>Operand :: isBLGP ( ) const { return isImm ( ) && getImmTy ( ) == ImmTyBLGP && isUInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> } } else { if ( ConstantInt * ConstInt = dyn_cast < ConstantInt > ( & V ) ) { APInt IntValue ( ConstInt -> getValue ( ) ) ; return IntValue . getActiveBits ( ) <= <NUM_LIT> ; } } Value * CastSrc ; bool IsExt = IsFloat ? match ( & V , m_FPExt ( PatternMatch :: m_Value ( CastSrc ) ) ) : match ( & V , m_ZExt ( PatternMatch :: m_Value ( CastSrc ) ) ) ; if ( IsExt ) {

Type * CastSrcTy = CastSrc -> getType ( ) ;


<s> tree newdecl = bpf_core_newdecl ( TREE_TYPE ( * tp ) ) ; tree newcall = build_call_expr_loc ( loc , newdecl , <NUM_LIT> , * tp ) ; * tp = newcall ; * walk_subtrees = <NUM_LIT> ;


<s> auto <STR_LIT> ( Type * Ty ) const -> bool { if ( ! isByteVecTy ( Ty ) ) return false ; int Size = getSizeOf ( Ty ) ; if ( HST . isTypeForHVX ( Ty ) ) return Size == static_cast < int > ( HST . getVectorLength ( ) ) ; return Size == <NUM_LIT> || Size == <NUM_LIT> ;


<s> if ( __count <= <NUM_LIT> ) { __r = ( __vector signed short ) vec_splats ( __m ) ; __c = ( __vector unsigned short ) vec_splats ( ( unsigned short ) __count ) ; __r = vec_sra ( __r , ( __vector unsigned short ) __c ) ;

return ( __m64 ) ( ( __vector long long ) __r ) [ <NUM_LIT> ] ;


<s> const MCRegisterInfo * MRI = getContext ( ) . getRegisterInfo ( ) ; switch ( Inst . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ForcedVEXEncoding == VEXEncoding_VEX3 || MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) >= <NUM_LIT> || MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) < <NUM_LIT> ) return false ; unsigned NewOpc ; switch ( Inst . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ;


<s> bool <ISA_LIT>RegisterInfo :: canRealignStack ( const MachineFunction & MF ) const { if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; if ( getFrameLowering ( MF ) -> hasReservedCallFrame ( MF ) ) return true ;


<s> return ( nios2_large_constant_p ( addr ) || nios2_plus_large_constant_p ( addr ) ) ;


<s> SMLoc S ; bool isParenExpr = false ; <ISA_LIT>AsmParser :: OperandMatchResultTy Res = MatchOperand_NoMatch ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) { Parser . Lex ( ) ; isParenExpr = true ; } if ( getLexer ( ) . getKind ( ) != AsmToken :: Dollar ) { if ( parseMemOffset ( IdVal , isParenExpr ) ) return MatchOperand_ParseFail ; const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: LParen ) ) { <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; if ( Mnemonic . getToken ( ) == <STR_LIT> ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = parseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( ! IdVal ) IdVal = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ;

std :: unique_ptr < <ISA_LIT>Operand > op ( static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) . release ( ) ) ) ;


<s> unsigned metric = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { unsigned ai = avr_map ( a , i ) ; if ( mode == MAP_FIXED_0_7 ) metric += ai == i ; else if ( mode == MAP_NONFIXED_0_7 ) metric += ai < <NUM_LIT> && ai != i ; else if ( mode == MAP_MASK_FIXED_0_7 ) metric |= ( ( unsigned ) ( ai == i ) ) << i ; else if ( mode == MAP_PREIMAGE_0_7 ) metric += ai < <NUM_LIT> ; else if ( mode == MAP_MASK_PREIMAGE_F ) metric |= ( ( unsigned ) ( ai == <NUM_LIT> ) ) << i ;


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( ) const { assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> return ( mode == SImode || mode == SFmode || mode == HImode || mode == QImode || mode == BImode ) ;


<s> case <STR_LIT> : return Subtarget . hasStdExtZfh ( ) ; case <STR_LIT> : return Subtarget . hasStdExtF ( ) ; case <STR_LIT> : return Subtarget . hasStdExtD ( ) ;


<s> bool <ISA_LIT>PacketizerList :: PromoteToDotNew ( MachineInstr * MI , SDep :: Kind DepType , MachineBasicBlock :: iterator & MII , const TargetRegisterClass * RC ) { assert ( DepType == SDep :: Data ) ; const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ;


<s> unsigned Reg = addLiveIn ( MF , ArgRegs [ I ] , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegTy ) ; FI = MFI -> CreateFixedObject ( RegSize , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( <NUM_LIT> ) ;


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; if ( I != MBB . begin ( ) ) I -- ; else return Changed ;

if ( I -> getOpcode ( ) == <STR_LIT> && I -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & MBBN ) {


<s> if ( OutStreamer -> hasRawTextSupport ( ) ) {

OutStreamer -> EmitRawText ( <STR_LIT> ) ;


<s> unsigned dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ptr = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned oldval = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned newval = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ord = static_cast < AtomicOrdering > ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * TRCsp ; TRCsp = Size == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ; unsigned ldrOpc , strOpc ; getExclusiveOperation ( Size , Ord , ldrOpc , strOpc ) ; MachineFunction * MF = BB -> getParent ( ) ; const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * loop1MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loop1MBB ) ; MF -> insert ( It , loop2MBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loop1MBB ) ; BB = loop1MBB ; BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; unsigned CmpOp = Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MRI . constrainRegClass ( dest , TRCsp ) ; BuildMI ( BB , dl , TII -> get ( CmpOp ) ) . addReg ( dest ) . addReg ( oldval ) . addImm ( <NUM_LIT> ) ;

BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> ) . addMBB ( exitMBB ) ;


<s> bool hasStdExtZbe ( ) const { return HasStdExtZbe ;


<s> fnname = XSTR ( XEXP ( DECL_RTL ( current_function_decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; mips_start_function_definition ( fnname , TARGET_MIPS16 ) ; if ( ! flag_inhibit_size_directive ) { const struct mips_frame_info * frame ; frame = & cfun -> machine -> frame ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , reg_names [ frame_pointer_needed ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ] , ( frame_pointer_needed ? frame -> total_size - frame -> hard_frame_pointer_offset : frame -> total_size ) , reg_names [ RETURN_ADDR_REGNUM ] , frame -> var_size , frame -> num_gp , frame -> num_fp , frame -> args_size , frame -> cprestore_size ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , frame -> mask , frame -> gp_save_offset ) ; fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , frame -> fmask , frame -> fp_save_offset ) ; } if ( mips_must_initialize_gp_p ( ) && mips_current_loadgp_style ( ) == LOADGP_OLDABI ) { if ( TARGET_MIPS16 ) { output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; } else { mips_push_asm_switch ( & mips_noreorder ) ; output_asm_insn ( <STR_LIT> , <NUM_LIT> ) ; if ( ! cfun -> machine -> all_noreorder_p ) mips_pop_asm_switch ( & mips_noreorder ) ; else mips_push_asm_switch ( & mips_nomacro ) ; } } else if ( cfun -> machine -> all_noreorder_p ) { mips_push_asm_switch ( & mips_noreorder ) ;


<s> for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) continue ; Changed = true ;

MBB . erase ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB . end ( ) ) ;


<s> if ( TARGET_NEON && ( MEM_P ( x ) || GET_CODE ( x ) == CONST_VECTOR ) && ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT || VALID_NEON_STRUCT_MODE ( mode ) ) ) return NO_REGS ;

if ( arm_coproc_mem_operand ( x , wb ) || s_register_operand ( x , mode ) ) return NO_REGS ;


<s> printVectorList ( MI , OpNum , O , <STR_LIT> ) ;


<s> pcum -> aapcs_stack_words = <NUM_LIT> ; pcum -> aapcs_stack_size = <NUM_LIT> ; pcum -> silent_p = silent_p ; if ( ! silent_p && ! TARGET_FLOAT && fntype && fntype != error_mark_node ) { const_tree type = TREE_TYPE ( fntype ) ; machine_mode mode ATTRIBUTE_UNUSED ; int nregs ATTRIBUTE_UNUSED ;

if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( type ) , type , & mode , & nregs , NULL , false ) ) aarch64_err_no_fpadvsimd ( TYPE_MODE ( type ) ) ;


<s> static void mapping ( IO & YamlIO , Program :: Metadata & Prog ) {

YamlIO . mapRequired ( KeyName :: MDVersion , Prog . MDVersionSeq ) ;


<s> switch ( IID ) { default : break ; case <STR_LIT> : case <STR_LIT> : return tryCombineFixedPointConvert ( N , DCI , DAG ) ; break ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineLongOpWithDup ( IID , N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return tryCombineShiftImm ( IID , N , DAG ) ; case <STR_LIT> : case <STR_LIT> :

return tryCombineCRC32 ( <NUM_LIT> , N , DAG ) ;


<s> assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ;


<s> FunctionPass * create<ISA_LIT>OffsetAllocator ( ) {

return new <ISA_LIT>OffsetAllocator ( ) ;


<s> pushReg ( AsReg ) ; BuildMI ( * MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addReg ( STReg ) ;


<s> if ( U . isImplicit ( ) ) return false ; const MachineInstr * UseInst = U . getParent ( ) ; if ( UseInst -> isCopy ( ) && UseInst -> getOperand ( <NUM_LIT> ) . getReg ( ) == PhysReg ) return false ; } const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( PhysReg ) ;

if ( TRI -> hasVGPRs ( RC ) ) return true ;


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> if ( ! isTypeLegal ( Ty , VT ) ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( MBB , DL , TII . get ( OpC ) , ResultReg ) . addImm ( CI -> getZExtValue ( ) == <NUM_LIT> ? - <NUM_LIT> : <NUM_LIT> ) ; UpdateValueMap ( & I , ResultReg ) ; return true ; } case <STR_LIT> : { DbgDeclareInst * DI = cast < DbgDeclareInst > ( & I ) ; <ISA_LIT>AddressMode AM ; assert ( DI -> getAddress ( ) && <STR_LIT> ) ; if ( ! <ISA_LIT>SelectAddress ( DI -> getAddress ( ) , AM ) ) return false ; const TargetInstrDesc & II = TII . get ( TargetOpcode :: DBG_VALUE ) ; addFullAddress ( BuildMI ( MBB , DL , II ) , AM ) . addImm ( <NUM_LIT> ) . addMetadata ( DI -> getVariable ( ) ) ; return true ; } case <STR_LIT> : { BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const Function * Callee = I . getCalledFunction ( ) ; const Type * RetTy = cast < StructType > ( Callee -> getReturnType ( ) ) -> getTypeAtIndex ( unsigned ( <NUM_LIT> ) ) ; EVT VT ; if ( ! isTypeLegal ( RetTy , VT ) ) return false ; Value * Op1 = I . getOperand ( <NUM_LIT> ) ; Value * Op2 = I . getOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Op1 ) ; unsigned Reg2 = getRegForValue ( Op2 ) ; if ( Reg1 == <NUM_LIT> || Reg2 == <NUM_LIT> ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( MBB , DL , TII . get ( OpC ) , ResultReg ) . addReg ( Reg1 ) . addReg ( Reg2 ) ; unsigned DestReg1 = UpdateValueMap ( & I , ResultReg ) ; if ( DestReg1 != ResultReg ) ResultReg = DestReg1 + <NUM_LIT> ; else ResultReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; unsigned Opc = <STR_LIT> ;

if ( I . getIntrinsicID ( ) == <STR_LIT> ) Opc = <STR_LIT> ;


Out . wavefront_sgpr_count = CurrentProgramInfo . NumSGPR ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>_BUILTIN ) ; }

unsigned TotalBytes = getTotalArgumentsSizeInBytes ( Outs ) ;


<s> <ISA_LIT>Operand ( unsigned Reg , MCExpr const * Expr , SMLoc const & S , SMLoc const & E ) : Base ( ) , Kind ( k_Mem ) , Mem ( { Reg , Expr ) , Start ( S ) , End ( E ) {


<s> static bool v850_pass_by_reference ( cumulative_args_t cum ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { unsigned HOST_WIDE_INT size ; if ( ! TARGET_GCC_ABI ) return <NUM_LIT> ;

if ( type ) size = int_size_in_bytes ( type ) ;


<s> Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex ++ , <STR_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , NULL , <NUM_LIT> ) ; } else { <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <STR_LIT> , <STR_LIT> ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , NULL , <NUM_LIT> ) ; } return DAG . getNode ( <STR_LIT> , dl , PtrVT , ThreadPointer , Offset ) ;


<s> label = gen_label_rtx ( ) ; emit_label_after ( label , insn ) ; DUMP ( <STR_LIT> , label ) ; } else { DUMP ( <STR_LIT> , label ) ; emit_insn_before ( gen_setlb ( ) , label ) ; } comparison = XEXP ( SET_SRC ( PATTERN ( branch ) ) , <NUM_LIT> ) ; cmp_reg = XEXP ( comparison , <NUM_LIT> ) ; gcc_assert ( REG_P ( cmp_reg ) ) ;

gcc_assert ( REGNO ( cmp_reg ) == CC_REG ) ;


<s> return makeArrayRef ( <STR_LIT> . begin ( ) , ST . getMaxNumSGPRs ( MF ) / <NUM_LIT> ) ;


<s> break ; case PLUS : retval = CRX_SCALED_INDX ; base = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; disp = XEXP ( addr , <NUM_LIT> ) ; if ( ! RTX_SIGNED_INT_FITS_N_BITS ( disp , <NUM_LIT> ) ) return CRX_INVALID ; switch ( GET_CODE ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ) ) { case REG : index = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; scale = <NUM_LIT> ; break ; case MULT : index = XEXP ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ; scale_rtx = XEXP ( XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( ( scale = SCALE_FOR_INDEX_P ( scale_rtx ) ) == - <NUM_LIT> ) return CRX_INVALID ; break ; default : return CRX_INVALID ; } break ; case MULT : retval = CRX_SCALED_INDX ; base = XEXP ( addr , <NUM_LIT> ) ; index = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; scale_rtx = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; if ( ( scale = SCALE_FOR_INDEX_P ( scale_rtx ) ) == - <NUM_LIT> ) return CRX_INVALID ; break ; default : return CRX_INVALID ; } break ; case POST_INC : case POST_DEC : retval = CRX_POST_INC ; base = XEXP ( addr , <NUM_LIT> ) ; side_effect = addr ;


<s> void aarch64_expand_compare_and_swap ( rtx operands [ ] ) { rtx bval , rval , mem , oldval , newval , is_weak , mod_s , mod_f , x ; machine_mode mode , cmp_mode ; typedef rtx ( * gen_cas_fn ) ( rtx , rtx , rtx , rtx , rtx , rtx , rtx ) ; int idx ; gen_cas_fn gen ; const gen_cas_fn split_cas [ ] = { gen_aarch64_compare_and_swapqi , gen_aarch64_compare_and_swaphi , gen_aarch64_compare_and_swapsi , gen_aarch64_compare_and_swapdi } ; const gen_cas_fn atomic_cas [ ] = { gen_aarch64_compare_and_swapqi_lse , gen_aarch64_compare_and_swaphi_lse , gen_aarch64_compare_and_swapsi_lse , gen_aarch64_compare_and_swapdi_lse } ; bval = operands [ <NUM_LIT> ] ; rval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = operands [ <NUM_LIT> ] ; mod_s = operands [ <NUM_LIT> ] ; mod_f = operands [ <NUM_LIT> ] ; mode = GET_MODE ( mem ) ; cmp_mode = mode ; if ( is_mm_acquire ( memmodel_from_int ( INTVAL ( mod_f ) ) ) && is_mm_release ( memmodel_from_int ( INTVAL ( mod_s ) ) ) ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case E_QImode : case E_HImode : cmp_mode = SImode ; rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case E_SImode : case E_DImode : if ( ! aarch64_plus_operand ( oldval , mode ) ) oldval = force_reg ( cmp_mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case E_QImode : idx = <NUM_LIT> ; break ; case E_HImode : idx = <NUM_LIT> ; break ; case E_SImode : idx = <NUM_LIT> ; break ; case E_DImode : idx = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ;


<s> static MCStreamer * createMCStreamer ( const Target & T , StringRef TT , MCContext & Ctx , MCAsmBackend & MAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool RelaxAll , bool NoExecStack ) { if ( Triple ( TT ) . isOSDarwin ( ) ) return createMachOStreamer ( Ctx , MAB , OS , Emitter , RelaxAll ) ; <ISA_LIT>TargetStreamer * S = new <ISA_LIT>TargetELFStreamer ( ) ; return createELFStreamer ( Ctx , S , MAB , OS , Emitter , RelaxAll , NoExecStack ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } CCAssignFn * AssignFnFixed ; CCAssignFn * AssignFnVarArg ; std :: tie ( AssignFnFixed , AssignFnVarArg ) = getAssignFnsForCC ( Info . CallConv , TLI ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; unsigned Opc = getCallOpcode ( MF , Info . Callee . isReg ( ) , false ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . addDef ( TRI -> getReturnAddressReg ( MF ) ) ; if ( ! addCallTargetOperands ( MIB , MIRBuilder , Info ) ) return false ; const uint32_t * Mask = TRI -> getCallPreservedMask ( MF , Info . CallConv ) ; MIB . addRegMask ( Mask ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( Info . CallConv , Info . IsVarArg , MF , ArgLocs , F . getContext ( ) ) ; SmallVector < std :: pair < MCRegister , Register > , <NUM_LIT> > ImplicitArgRegs ; if ( <ISA_LIT>TargetMachine :: EnableFixedFunctionABI ) { if ( ! passSpecialInputs ( MIRBuilder , CCInfo , ImplicitArgRegs , Info ) ) return false ; } SmallVector < Register , <NUM_LIT> > PhysRegs ; <ISA_LIT>OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB , AssignFnFixed , AssignFnVarArg , false ) ; if ( ! handleAssignments ( CCInfo , ArgLocs , MIRBuilder , OutArgs , Handler ) ) return false ; const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! ST . enableFlatScratch ( ) ) { auto ScratchRSrcReg = MIRBuilder . buildCopy ( LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) , MFI -> getScratchRSrcReg ( ) ) ; MIRBuilder . buildCopy ( <STR_LIT> , ScratchRSrcReg ) ; MIB . addReg ( <STR_LIT> , RegState :: Implicit ) ; } for ( std :: pair < MCRegister , Register > ArgReg : ImplicitArgRegs ) { MIRBuilder . buildCopy ( ( Register ) ArgReg . first , ArgReg . second ) ; MIB . addReg ( ArgReg . first , RegState :: Implicit ) ;


<s> MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( Using<ISA_LIT>32 ? <STR_LIT> : <STR_LIT> ) , Rt ) ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i ++ ) MIB . addOperand ( MI . getOperand ( i ) ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wd ) . addReg ( Rt ) ; MI . eraseFromParent ( ) ;


<s> case ARG_POINTER_REGNUM : return pc_size + fp_size ; case RETURN_ADDRESS_POINTER_REGNUM : return fp_size ; case FRAME_POINTER_REGNUM : return - saved_regs_size ; default : gcc_unreachable ( ) ; } break ; case STACK_POINTER_REGNUM : switch ( from ) { case ARG_POINTER_REGNUM : return pc_size + saved_regs_size + frame_size ; case RETURN_ADDRESS_POINTER_REGNUM : return saved_regs_size + frame_size ; case FRAME_POINTER_REGNUM : return frame_size ; default : gcc_unreachable ( ) ; }


<s> ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemImm12OffsetOperands ( Inst , <NUM_LIT> ) ;

( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ;


<s> if ( isa < PHINode > ( V ) || isa < SelectInst > ( V ) || isa < ReturnInst > ( V ) || isa < LoadInst > ( V ) ) return isSupportedType ( V ) ; if ( auto * Cast = dyn_cast < CastInst > ( V ) ) return isSupportedType ( Cast ) || isSupportedType ( Cast -> getOperand ( <NUM_LIT> ) ) ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return isSupportedType ( Call ) && Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; if ( ! isa < BinaryOperator > ( V ) ) return false ; if ( ! isSupportedType ( V ) ) return false ;


<s> static bool isLDSTPIIMM ( InsnType insn ) {

return ( ( ( insn ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; printSOImm ( O , MO . getImm ( ) , CommentStream , & MAI ) ;


<s> return __builtin_aarch64_fix_trunchfhi ( __a ) ;


<s> rtx reg = regno_reg_rtx [ regno ] ; rtx vreg = gen_reg_rtx ( DImode ) ; df_ref ref ; for ( ref = DF_REG_DEF_CHAIN ( regno ) ; ref ; ref = DF_REF_NEXT_REG ( ref ) ) if ( ! bitmap_bit_p ( insns , DF_REF_INSN_UID ( ref ) ) ) { start_sequence ( ) ; if ( ! TARGET_INTER_UNIT_MOVES_TO_VEC ) { rtx tmp = assign_386_stack_local ( DImode , SLOT_STV_TEMP ) ; emit_move_insn ( adjust_address ( tmp , SImode , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ; emit_move_insn ( adjust_address ( tmp , SImode , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ; emit_move_insn ( vreg , tmp ) ; } else if ( TARGET_SSE4_1 ) { emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_sse4_1_pinsrd ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ) ; } else { rtx tmp = gen_reg_rtx ( DImode ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_sse2_loadld ( gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) , CONST0_RTX ( V4SImode ) , gen_rtx_SUBREG ( SImode , reg , <NUM_LIT> ) ) ) ; emit_insn ( gen_vec_interleave_lowv4si ( gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , vreg , <NUM_LIT> ) , gen_rtx_SUBREG ( V4SImode , tmp , <NUM_LIT> ) ) ) ; } rtx_insn * seq = get_insns ( ) ; end_sequence ( ) ; rtx_insn * insn = DF_REF_INSN ( ref ) ; emit_conversion_insns ( seq , insn ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , regno , REGNO ( vreg ) , INSN_UID ( insn ) ) ; } for ( ref = DF_REG_USE_CHAIN ( regno ) ; ref ; ref = DF_REF_NEXT_REG ( ref ) ) if ( bitmap_bit_p ( insns , DF_REF_INSN_UID ( ref ) ) ) { rtx_insn * insn = DF_REF_INSN ( ref ) ; replace_with_subreg_in_insn ( insn , reg , vreg ) ;


<s> case PTX_ISA_SM70 : return PTX_VERSION_6_0 ; case PTX_ISA_SM75 : return PTX_VERSION_6_3 ; case PTX_ISA_SM80 : return PTX_VERSION_7_0 ; default : gcc_unreachable ( ) ; }


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MachineOperand & MO1 = const_cast < MachineOperand & > ( MI . getOperand ( <NUM_LIT> ) ) ; MachineOperand & MO2 = const_cast < MachineOperand & > ( MI . getOperand ( <NUM_LIT> ) ) ; ShapeT Shape ( & MO1 , & MO2 , MRI ) ;


<s> if ( DisableVSXFMAMutate ) return Changed ; for ( MachineBasicBlock & B : llvm :: make_early_inc_range ( MF ) ) if ( processBlock ( B ) ) Changed = true ; return Changed ;


<s> return ! TYPE_PACKED ( record_type ) ;


<s> push3 ( unsigned i , unsigned j , unsigned k ) : tripleChange ( true , true , true , i , j , k ) {


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ( Subtarget . hasFastVectorShiftMasks ( ) && VT . isVector ( ) ) || ( Subtarget . hasFastScalarShiftMasks ( ) && ! VT . isVector ( ) ) ) { return N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } return TargetLoweringBase :: shouldFoldConstantShiftPairToMask ( N , Level ) ;


<s> if ( HandlerDataLoc . isValid ( ) ) return Error ( L , <STR_LIT> ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) && Parser . getTok ( ) . isNot ( AsmToken :: Dollar ) ) { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } Parser . Lex ( ) ; const MCExpr * OffsetExpr ; SMLoc ExLoc = Parser . getTok ( ) . getLoc ( ) ; SMLoc EndLoc ; if ( getParser ( ) . parseExpression ( OffsetExpr , EndLoc ) ) return Error ( ExLoc , <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( OffsetExpr ) ; if ( ! CE ) return Error ( ExLoc , <STR_LIT> ) ; getTargetStreamer ( ) . emitPad ( CE -> getValue ( ) ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB << <STR_LIT> ) ; for ( auto I = BranchPath . rbegin ( ) ; I != BranchPath . rend ( ) ; ++ I , ++ Index ) { MachineBasicBlock * PMBB = * I ; TargetMBBInfo * PMBBInfo = getMBBInfo ( PMBB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Index << <STR_LIT> << BranchPath . size ( ) << <STR_LIT> << * PMBB ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << PMBBInfo -> BranchCode << <STR_LIT> << PMBBInfo -> CmpValue << <STR_LIT> << PMBBInfo -> CmpBrOnly << <STR_LIT> ) ; } optimizeCondBr ( MBB , BranchPath ) ; Changed = true ; } NumFixedCondBrs += RemoveList . size ( ) ; for ( auto MBBI : RemoveList ) { while ( ! MBBI -> succ_empty ( ) ) MBBI -> removeSuccessor ( MBBI -> succ_end ( ) - <NUM_LIT> ) ; MBBI -> eraseFromParent ( ) ; } return Changed ;


<s> bool isVReg32OrOff ( ) const { return isOff ( ) || isRegClass ( <STR_LIT> ) ;


<s> gcc_assert ( x ) ; aarch64_emit_move ( x , value ) ; return x ; }


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override {


<s> ConstantSDNode * C = dyn_cast < ConstantSDNode > ( FalseVal ) ; if ( ! C ) return false ; if ( AllOnes ) return C -> isAllOnesValue ( ) ;


<s> static bool isAddWithImmediate ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> bool hasVFP2Base ( ) const { return HasVFPv2D16SP ;


<s> return llvm :: make_unique < <ISA_LIT>XCOFFObjectWriter > ( Is64Bit ) ;


<s> using MISet = std :: set < MachineInstr * > ; const TargetRegisterClass * IntRC = & <STR_LIT> ; bool Changed = false ; DEBUG ( dbgs ( ) << <STR_LIT> ; dump_partition ( dbgs ( ) , Part , * TRI ) ; dbgs ( ) << '\n' ) ; UUPairMap PairMap ; MISet SplitIns ; for ( unsigned DR : Part ) { MachineInstr * DefI = MRI -> getVRegDef ( DR ) ; SplitIns . insert ( DefI ) ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) SplitIns . insert ( U -> getParent ( ) ) ; unsigned LoR = MRI -> createVirtualRegister ( IntRC ) ; unsigned HiR = MRI -> createVirtualRegister ( IntRC ) ; DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( DR , TRI ) << <STR_LIT> << PrintReg ( HiR , TRI ) << ':' << PrintReg ( LoR , TRI ) << '\n' ) ; PairMap . insert ( std :: make_pair ( DR , UUPair ( LoR , HiR ) ) ) ; } MISet Erase ; for ( auto MI : SplitIns ) { if ( isFixedInstr ( MI ) ) { collapseRegPairs ( MI , PairMap ) ; } else { bool Done = splitInstr ( MI , PairMap ) ; if ( Done ) Erase . insert ( MI ) ; Changed |= Done ; } } for ( unsigned DR : Part ) { MISet Uses ; for ( auto U = MRI -> use_nodbg_begin ( DR ) , W = MRI -> use_nodbg_end ( ) ; U != W ; ++ U ) Uses . insert ( U -> getParent ( ) ) ; for ( auto M : Uses ) replaceSubregUses ( M , PairMap ) ; } for ( auto MI : Erase ) { MachineBasicBlock * B = MI -> getParent ( ) ; B -> erase ( MI ) ; }


<s> MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ; FrameInfo . setStackID ( FrameIndex , <NUM_LIT> ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg ) ; return ;


<s> void setGPFI ( int FI ) { GPHolder . FI = FI ;


<s> addPass ( createEHContGuardCatchretPass ( ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCompressJumpTables ) addPass ( create<ISA_LIT>CompressJumpTablesPass ( ) ) ;

if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableCollectLOH && TM -> getTargetTriple ( ) . isOSBinFormatMachO ( ) ) addPass ( create<ISA_LIT>CollectLOHPass ( ) ) ;


<s> <ISA_LIT>Operand ( KindTy Kind_ , const <ISA_LIT>AsmParser * AsmParser_ ) : Kind ( Kind_ ) , AsmParser ( AsmParser_ ) {


<s> if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; }


<s> if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { MachineInstr * Old = I ; MachineInstr * New = BuildMI ( MF , Old -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( CalleeAmt ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } MBB . erase ( I ) ;


<s> if ( Src1Regs . empty ( ) ) split64BitValueForMapping ( B , Src1Regs , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; B . buildInstr ( Opc ) . addDef ( DefRegs [ <NUM_LIT> ] ) . addUse ( Src0Regs [ <NUM_LIT> ] ) . addUse ( Src1Regs [ <NUM_LIT> ] ) ; B . buildInstr ( Opc ) . addDef ( DefRegs [ <NUM_LIT> ] ) . addUse ( Src0Regs [ <NUM_LIT> ] ) . addUse ( Src1Regs [ <NUM_LIT> ] ) ; MRI . setRegBank ( DstReg , getRegBank ( <STR_LIT> ) ) ; MI . eraseFromParent ( ) ; return ; } default :


<s> while ( col < indentlen ) { OS << <STR_LIT> ; col ++ ; } OS << <STR_LIT> ;


<s> t = __ev_mwhssf ( a , b ) ; return __ev_addssiaaw ( t ) ;


<s> Op -> RegShiftedReg . ShiftTy = ShTy ; Op -> RegShiftedReg . SrcReg = SrcReg ; Op -> RegShiftedReg . ShiftReg = ShiftReg ; Op -> RegShiftedReg . ShiftImm = ShiftImm ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> return ( unsigned long long ) __builtin_ashrv4hi3 ( ( v4hi ) mm , mn ) ;


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; }


<s> return new <ISA_LIT>PreLegalizerCombiner ( IsOptNone ) ;


<s> } else { unsigned ReservedBufferReg = TRI . reservedPrivateSegmentBufferReg ( MF ) ; unsigned ReservedOffsetReg = TRI . reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; Info . setScratchRSrcReg ( ReservedBufferReg ) ; Info . setScratchWaveOffsetReg ( ReservedOffsetReg ) ; } } else { unsigned ReservedBufferReg = TRI . reservedPrivateSegmentBufferReg ( MF ) ; Info . setScratchRSrcReg ( ReservedBufferReg ) ; if ( HasStackObjects ) { unsigned ScratchWaveOffsetReg = TRI . getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: PRIVATE_SEGMENT_WAVE_BYTE_OFFSET ) ; Info . setScratchWaveOffsetReg ( ScratchWaveOffsetReg ) ;


<s> static <ISA_LIT>Operand :: Ptr CreateImm ( int64_t Val , SMLoc Loc , enum ImmTy Type = ImmTyNone , bool IsFPImm = false ) { auto Op = llvm :: make_unique < <ISA_LIT>Operand > ( Immediate ) ; Op -> Imm . Val = Val ;


<s> static bool tilegx_truly_noop_truncation ( poly_uint64 outprec , poly_uint64 inprec ) { return inprec <= <NUM_LIT> || outprec > <NUM_LIT> ;


<s> SavedRegs . set ( <STR_LIT> ) ; SavedRegs . set ( <STR_LIT> ) ; } if ( hasBP ( MF ) ) SavedRegs . set ( <STR_LIT> ( ) ) ; if ( MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) && MFI . hasCalls ( ) ) { static const MCPhysReg CSRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) SavedRegs . set ( CSRegs [ i ] ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtD ( ) || MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtF ( ) ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = <NUM_LIT> ; Regs [ i ] ; ++ i ) if ( <STR_LIT> . contains ( Regs [ i ] ) || <STR_LIT> . contains ( Regs [ i ] ) ) SavedRegs . set ( Regs [ i ] ) ; }


<s> return getSubtargetImpl ( ) -> getFrameLowering ( ) ;


<s> Value * <ISA_LIT>IREmitter :: visitMOVLHPD ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> MDNode * FPMath = FDiv . getMetadata ( LLVMContext :: MD_fpmath ) ; if ( ! FPMath ) return false ; const FPMathOperator * FPOp = cast < const FPMathOperator > ( & FDiv ) ; float ULP = FPOp -> getFPAccuracy ( ) ; if ( ULP < <NUM_LIT> ) return false ; FastMathFlags FMF = FPOp -> getFastMathFlags ( ) ; bool UnsafeDiv = HasUnsafeFPMath || FMF . unsafeAlgebra ( ) || FMF . allowReciprocal ( ) ; if ( ST -> hasFP32Denormals ( ) && ! UnsafeDiv ) return false ; IRBuilder < > Builder ( FDiv . getParent ( ) , std :: next ( FDiv . getIterator ( ) ) , FPMath ) ; Builder . setFastMathFlags ( FMF ) ; Builder . SetCurrentDebugLocation ( FDiv . getDebugLoc ( ) ) ; Function * Decl = <STR_LIT> ( Mod , <STR_LIT> ) ; Value * Num = FDiv . getOperand ( <NUM_LIT> ) ; Value * Den = FDiv . getOperand ( <NUM_LIT> ) ; Value * NewFDiv = nullptr ; if ( VectorType * VT = dyn_cast < VectorType > ( Ty ) ) { NewFDiv = UndefValue :: get ( VT ) ; for ( unsigned I = <NUM_LIT> , E = VT -> getNumElements ( ) ; I != E ; ++ I ) { Value * NumEltI = Builder . CreateExtractElement ( Num , I ) ; Value * DenEltI = Builder . CreateExtractElement ( Den , I ) ; Value * NewElt ; if ( shouldKeepFDivF32 ( NumEltI , UnsafeDiv ) ) { NewElt = Builder . CreateFDiv ( NumEltI , DenEltI ) ; } else { NewElt = Builder . CreateCall ( Decl , { NumEltI , DenEltI } ) ; } NewFDiv = Builder . CreateInsertElement ( NewFDiv , NewElt , I ) ; } } else { if ( ! shouldKeepFDivF32 ( Num , UnsafeDiv ) ) NewFDiv = Builder . CreateCall ( Decl , { Num , Den } ) ; } if ( NewFDiv ) { FDiv . replaceAllUsesWith ( NewFDiv ) ; NewFDiv -> takeName ( & FDiv ) ; FDiv . eraseFromParent ( ) ; }


<s> } else if ( EltNo != ByteSource / <NUM_LIT> ) { isFourElementShuffle = false ; break ; } } PFIndexes [ i ] = EltNo ; } if ( isFourElementShuffle ) { unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost < <NUM_LIT> ) return GeneratePerfectShuffle ( PFEntry , V1 , V2 , DAG , dl ) ; } if ( V2 . getOpcode ( ) == <STR_LIT> ) V2 = V1 ; EVT EltVT = V1 . getValueType ( ) . getVectorElementType ( ) ; unsigned BytesPerElement = EltVT . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > ResultMask ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) { unsigned SrcElt = PermMask [ i ] < <NUM_LIT> ? <NUM_LIT> : PermMask [ i ] ; for ( unsigned j = <NUM_LIT> ; j != BytesPerElement ; ++ j ) ResultMask . push_back ( DAG . getConstant ( SrcElt * BytesPerElement + j , <STR_LIT> ) ) ; }

SDValue VPermMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ResultMask ) ;


<s> return __arm_vreinterpretq_u32_f32 ( __a ) ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;


<s> AttrEmitter = new ObjectAttributeEmitter ( O ) ; } AttrEmitter -> MaybeSwitchVendor ( <STR_LIT> ) ; std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString == <STR_LIT> || Subtarget -> isCortexA8 ( ) ) { AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasV8Ops ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV7Ops ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasV6T2Ops ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV6Ops ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV5TEOps ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV5TOps ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasV4TOps ( ) ) AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; else AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( Subtarget -> hasNEON ( ) && emitFPU ) { if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; else if ( Subtarget -> hasVFP4 ( ) ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; else AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; emitFPU = false ; } if ( Subtarget -> hasFP<ISA_LIT>v8 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP4 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP3 ( ) ) {


<s> bool PadShortFunc :: cyclesUntilReturn ( MachineBasicBlock * MBB , unsigned int & Cycles ) { DenseMap < MachineBasicBlock * , VisitedBBInfo > :: iterator it = VisitedBBs . find ( MBB ) ; if ( it != VisitedBBs . end ( ) ) { VisitedBBInfo BBInfo = it -> second ; Cycles += BBInfo . Cycles ; return BBInfo . HasReturn ; } unsigned int CyclesToEnd = <NUM_LIT> ; for ( MachineBasicBlock :: iterator MBBI = MBB -> begin ( ) ; MBBI != MBB -> end ( ) ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isReturn ( ) && ! MI -> isCall ( ) ) { VisitedBBs [ MBB ] = VisitedBBInfo ( true , CyclesToEnd ) ;


<s> this -> Options . NoTrapAfterNoreturn = true ; } if ( getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) { this -> Options . TrapUnreachable = true ; } if ( this -> Options . TLSSize == <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( ( getCodeModel ( ) == CodeModel :: Small || getCodeModel ( ) == CodeModel :: Kernel ) && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; else if ( getCodeModel ( ) == CodeModel :: Tiny && this -> Options . TLSSize > <NUM_LIT> ) this -> Options . TLSSize = <NUM_LIT> ; if ( getOptLevel ( ) <= EnableGlobalISelAtO && TT . getArch ( ) != Triple :: aarch64_32 && TT . getEnvironment ( ) != Triple :: GNUILP32 && ! ( getCodeModel ( ) == CodeModel :: Large && TT . isOSBinFormatMachO ( ) ) ) { setGlobalISel ( true ) ; setGlobalISelAbort ( GlobalISelAbortMode :: Disable ) ; } setMachineOutliner ( true ) ; setSupportsDefaultOutlining ( true ) ; setSupportsDebugEntryValues ( true ) ; if ( ! getMCAsmInfo ( ) -> usesWindowsCFI ( ) ) setCFIFixup ( true ) ;


<s> bool Changed = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FixupLocsForFn . size ( ) << <STR_LIT> ) ; for ( AESFixupLocation & FixupLoc : FixupLocsForFn ) { insertAESFixup ( FixupLoc , TII , TRI ) ; Changed |= true ; }


<s> if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> shrinkWrapDisabled ( ) ) return false ; return ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isSVR4ABI ( ) && MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . is<ISA_LIT>64 ( ) ) ;


<s> static bool isInv2Pi ( const APFloat & APF ) {

static const APFloat KF16 ( APFloat :: IEEEhalf ( ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ;


<s> assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( V2 . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > Repeated128Mask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated128Mask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; narrowShuffleMaskElts ( <NUM_LIT> , Repeated128Mask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } SmallVector < int , <NUM_LIT> > Repeated256Mask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128Shuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ;

if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ;


<s> } if ( FP ) { int FPSpillOffset = MFI -> getObjectOffset ( XFI -> getFPSpillSlot ( ) ) ; storeToStack ( MBB , MBBI , <STR_LIT> , FPSpillOffset + FrameSize * <NUM_LIT> , dl ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * SaveR10Label = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( SaveR10Label ) ; MachineLocation CSDst ( MachineLocation :: VirtualFP , FPSpillOffset ) ; MachineLocation CSSrc ( <STR_LIT> ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( SaveR10Label , CSDst , CSSrc ) ) ; } unsigned FramePtr = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FramePtr ) . addImm ( <NUM_LIT> ) ; if ( emitFrameMoves ) { MCSymbol * FrameLabel = MMI -> getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addSym ( FrameLabel ) ; MachineLocation SPDst ( FramePtr ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP ) ; MMI -> getFrameMoves ( ) . push_back ( MachineMove ( FrameLabel , SPDst , SPSrc ) ) ; } } if ( emitFrameMoves ) { std :: vector < MachineMove > & Moves = MMI -> getFrameMoves ( ) ; std :: vector < std :: pair < MCSymbol * , CalleeSavedInfo > > & SpillLabels = XFI -> getSpillLabels ( ) ; for ( unsigned I = <NUM_LIT> , E = SpillLabels . size ( ) ; I != E ; ++ I ) { MCSymbol * SpillLabel = SpillLabels [ I ] . first ; CalleeSavedInfo & CSI = SpillLabels [ I ] . second ; int Offset = MFI -> getObjectOffset ( CSI . getFrameIdx ( ) ) ; unsigned Reg = CSI . getReg ( ) ; MachineLocation CSDst ( MachineLocation :: VirtualFP , Offset ) ; MachineLocation CSSrc ( Reg ) ;

Moves . push_back ( MachineMove ( SpillLabel , CSDst , CSSrc ) ) ;


<s> if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getScalarType ( ) == <STR_LIT> ) return TypeSplitVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;


<s> GEP -> replaceAllUsesWith ( new AddrSpaceCastInst ( NewGEPI , GEP -> getType ( ) , <STR_LIT> , GEPI ) ) ; } else { Constant * NewGEPCE = ConstantExpr :: getGetElementPtr ( GEP -> getSourceElementType ( ) , cast < Constant > ( Cast -> getOperand ( <NUM_LIT> ) ) , Indices , GEP -> isInBounds ( ) ) ; GEP -> replaceAllUsesWith ( ConstantExpr :: getAddrSpaceCast ( NewGEPCE , GEP -> getType ( ) ) ) ; }


<s> static DecodeStatus s4_3ImmDecoder ( MCInst & MI , unsigned tmp , uint64_t , const void * Decoder ) { signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> } if ( strcmp ( Prefix , <STR_LIT> ) == <NUM_LIT> ) { sprintf ( buf , <STR_LIT> , Num ) ; return ;


<s> const DataLayout & DL = MF . getDataLayout ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const Function * F = MF . getFunction ( ) ; SmallVector < EVT , <NUM_LIT> > SplitVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , <NUM_LIT> ) ; if ( SplitVTs . size ( ) == <NUM_LIT> ) { auto Flags = OrigArg . Flags ; unsigned OriginalAlignment = DL . getABITypeAlignment ( OrigArg . Ty ) ; Flags . setOrigAlign ( OriginalAlignment ) ; SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ <NUM_LIT> ] . getTypeForEVT ( Ctx ) , Flags , OrigArg . IsFixed ) ; return ; }

unsigned FirstRegIdx = SplitArgs . size ( ) ;


<s> void printi64mem ( const MachineInstr * MI , unsigned OpNo ) {


<s> SDValue MinusXLen = DAG . getConstant ( - ( int ) Subtarget . getXLen ( ) , DL , VT ) ; SDValue XLenMinus1 = DAG . getConstant ( Subtarget . getXLen ( ) - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusXLen = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusXLen ) ; SDValue XLenMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , XLenMinus1 , Shamt ) ; SDValue LoTrue = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ; SDValue ShiftRight1Lo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , One ) ; SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRight1Lo , XLenMinus1Shamt ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue HiTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ;

SDValue HiFalse = DAG . getNode ( <STR_LIT> , DL , VT , Lo , ShamtMinusXLen ) ;


<s> void <ISA_LIT>ConstantPoolValue :: print ( raw_ostream & O ) const {


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ;

uint64_t StackSize = MFI -> getStackSize ( ) ;


<s> if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) NewPreds . insert ( PredReg ) ; } else for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ;


<s> const MCInstrDesc & Desc = MII . get ( Opc ) ; if ( ( Desc . TSFlags & <STR_LIT> ) == <NUM_LIT> ) return true ; const <STR_LIT> * Info = <STR_LIT> ( Opc ) ; const <STR_LIT> * BaseOpcode = <STR_LIT> ( Info -> BaseOpcode ) ; if ( ! BaseOpcode -> MSAA ) return true ; int DimIdx = <STR_LIT> ( Opc , <STR_LIT> :: dim ) ; assert ( DimIdx != - <NUM_LIT> ) ;

unsigned Dim = Inst . getOperand ( DimIdx ) . getImm ( ) ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( StringRef TT ) {


<s> HOST_WIDE_INT size = int_size_in_bytes ( type ) ;

return ( size == - <NUM_LIT> || size > UNITS_PER_WORD * NUM_ARGUMENT_REGISTERS ) ;


<s> } if ( EltVT == <STR_LIT> ) { SDValue Zeros = getZeroVector ( VT , Subtarget , DAG , DL ) ; SDValue Low = DAG . getNode ( <STR_LIT> , DL , VT , V , Zeros ) ; SDValue High = DAG . getNode ( <STR_LIT> , DL , VT , V , Zeros ) ; Zeros = getZeroVector ( ByteVecVT , Subtarget , DAG , DL ) ; MVT SadVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; Low = DAG . getNode ( <STR_LIT> , DL , SadVecVT , DAG . getBitcast ( ByteVecVT , Low ) , Zeros ) ; High = DAG . getNode ( <STR_LIT> , DL , SadVecVT , DAG . getBitcast ( ByteVecVT , High ) , Zeros ) ; MVT ShortVecVT = <STR_LIT> ( <STR_LIT> , VecSize / <NUM_LIT> ) ; V = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , DAG . getBitcast ( ShortVecVT , Low ) , DAG . getBitcast ( ShortVecVT , High ) ) ; return DAG . getBitcast ( VT , V ) ; } assert ( EltVT == <STR_LIT> && <STR_LIT> ) ; SDValue ShifterV = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getBitcast ( VT , V ) , ShifterV ) ;

V = DAG . getNode ( <STR_LIT> , DL , ByteVecVT , DAG . getBitcast ( ByteVecVT , Shl ) , DAG . getBitcast ( ByteVecVT , V ) ) ;


<s> Entry . IsSExt = shouldSignExtendTypeInLibCall ( ArgVT , isSigned ) ; Entry . IsZExt = ! shouldSignExtendTypeInLibCall ( ArgVT , isSigned ) ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DAG . getDataLayout ( ) ) ) ; EVT RetVT = Node -> getValueType ( <NUM_LIT> ) ; Type * RetTy = RetVT . getTypeForEVT ( * DAG . getContext ( ) ) ; SDValue InChain = DAG . getEntryNode ( ) ; SDValue TCChain = InChain ; const Function & F = DAG . getMachineFunction ( ) . getFunction ( ) ; bool isTailCall = isInTailCallPosition ( DAG , Node , TCChain ) && ( RetTy == F . getReturnType ( ) || F . getReturnType ( ) -> isVoidTy ( ) ) ; if ( isTailCall ) InChain = TCChain ;

TargetLowering :: CallLoweringInfo CLI ( DAG ) ;


<s> <ISA_LIT>PLT1 :: <ISA_LIT>PLT1 ( SectionData & pParent ) : PLT :: Entry < sizeof ( arm_plt1 ) > ( pParent ) {


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_sfence ( void ) { __builtin_ia32_sfence ( ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << MF . getName ( ) << '\n' ) ; const auto & MLI = getAnalysis < MachineLoopInfo > ( ) ;

auto & MDT = getAnalysis < MachineDominatorTree > ( ) ;


<s> switch ( XINT ( x , <NUM_LIT> ) ) { case UNSPEC_UNALIGNED_LOAD : * cost = COSTS_N_INSNS ( ARM_NUM_REGS ( GET_MODE ( x ) ) ) ; if ( speed_p ) * cost += ( ARM_NUM_REGS ( GET_MODE ( x ) ) * extra_cost -> ldst . load + extra_cost -> ldst . load_unaligned ) ; * cost += arm_address_cost ( XEXP ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , GET_MODE ( x ) , ADDR_SPACE_GENERIC , speed_p ) ; return true ; case UNSPEC_UNALIGNED_STORE : * cost = COSTS_N_INSNS ( ARM_NUM_REGS ( GET_MODE ( x ) ) ) ; if ( speed_p ) * cost += ( ARM_NUM_REGS ( GET_MODE ( x ) ) * extra_cost -> ldst . store + extra_cost -> ldst . store_unaligned ) ; * cost += rtx_cost ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , VOIDmode , UNSPEC , <NUM_LIT> , speed_p ) ; * cost += arm_address_cost ( XEXP ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) , GET_MODE ( x ) , ADDR_SPACE_GENERIC , speed_p ) ;


<s> Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasSHA = false ; HasSGX = false ; HasPRFCHW = false ; HasRDSEED = false ; HasSMAP = false ; IsBTMemSlow = false ; IsSHLDSlow = false ;


<s> if ( ( ( EltSize == <NUM_LIT> && TypeSize == <NUM_LIT> ) || ( EltSize == <NUM_LIT> && ( TypeSize == <NUM_LIT> || TypeSize == <NUM_LIT> ) ) ) && TypeSize * NumElems == <NUM_LIT> ) ExtSize = TypeSize ; } } if ( ExtSize * NumElems != <NUM_LIT> || NumElems < <NUM_LIT> ) return ScalarCost ; if ( ExtSize == <NUM_LIT> ) return VectorCost ; if ( ExtSize != <NUM_LIT> && ExtSize != <NUM_LIT> ) return ScalarCost ; if ( const auto * BC = dyn_cast < BitCastInst > ( Ptr ) ) Ptr = BC -> getOperand ( <NUM_LIT> ) ; if ( const auto * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ) { if ( GEP -> getNumOperands ( ) != <NUM_LIT> ) return ScalarCost ; unsigned Scale = DL . getTypeAllocSize ( GEP -> getResultElementType ( ) ) ; if ( Scale != <NUM_LIT> && Scale * <NUM_LIT> != ExtSize ) return ScalarCost ; if ( const auto * ZExt = dyn_cast < ZExtInst > ( GEP -> getOperand ( <NUM_LIT> ) ) ) { if ( ZExt -> getOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarSizeInBits ( ) <= ExtSize ) return VectorCost ; } return ScalarCost ;


<s> SmallVector < MachineInstr * , <NUM_LIT> > BranchInstrs ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; <ISA_LIT>InstrInfo :: BranchType R = TII -> AnalyzeBranch ( MBB , TrueBB , FalseBB , Cond , false , BranchInstrs ) ; if ( ( R == <ISA_LIT>InstrInfo :: BT_None ) || ( R == <ISA_LIT>InstrInfo :: BT_NoBranch ) ) return std :: make_pair ( R , nullptr ) ; if ( R != <ISA_LIT>InstrInfo :: BT_CondUncond ) { if ( ! hasUnoccupiedSlot ( BranchInstrs [ <NUM_LIT> ] ) ) return std :: make_pair ( <ISA_LIT>InstrInfo :: BT_None , nullptr ) ; assert ( ( ( R != <ISA_LIT>InstrInfo :: BT_Uncond ) || ( TrueBB == & Dst ) ) ) ; return std :: make_pair ( R , BranchInstrs [ <NUM_LIT> ] ) ; }

assert ( ( TrueBB == & Dst ) || ( FalseBB == & Dst ) ) ;


<s> SDValue FalseOp = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; Comparison C ( getCmp ( DAG , CmpOp0 , CmpOp1 , CC ) ) ; if ( C . Opcode == <STR_LIT> && C . CCMask != <STR_LIT> && C . CCMask != <STR_LIT> && C . Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( C . Op1 ) -> getZExtValue ( ) == <NUM_LIT> ) { if ( isAbsolute ( C . Op0 , TrueOp , FalseOp ) ) return getAbsolute ( DAG , DL , TrueOp , C . CCMask & <STR_LIT> ) ; if ( isAbsolute ( C . Op0 , FalseOp , TrueOp ) ) return getAbsolute ( DAG , DL , FalseOp , C . CCMask & <STR_LIT> ) ; } SDValue Glue = emitCmp ( DAG , DL , C ) ; auto * TrueC = dyn_cast < ConstantSDNode > ( TrueOp ) ; auto * FalseC = dyn_cast < ConstantSDNode > ( FalseOp ) ; if ( TrueC && FalseC ) { int64_t TrueVal = TrueC -> getSExtValue ( ) ; int64_t FalseVal = FalseC -> getSExtValue ( ) ; if ( ( TrueVal == - <NUM_LIT> && FalseVal == <NUM_LIT> ) || ( TrueVal == <NUM_LIT> && FalseVal == - <NUM_LIT> ) ) { if ( TrueVal == <NUM_LIT> ) C . CCMask ^= C . CCValid ; SDValue Result = emitSETCC ( DAG , DL , Glue , C . CCValid , C . CCMask ) ; EVT VT = Op . getValueType ( ) ; if ( ! is32Bit ( VT ) ) Result = DAG . getNode ( <STR_LIT> , DL , VT , Result ) ; SDValue ShAmt = DAG . getConstant ( VT . getSizeInBits ( ) - <NUM_LIT> , <STR_LIT> ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , DL , VT , Result , ShAmt ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Shl , ShAmt ) ; }


<s> } MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRn ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRm ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRs ( insn ) ) ) ) ; OpIdx += <NUM_LIT> ; if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeRd ( insn ) ) ) ) ; ++ OpIdx ; }


<s> const ELFRelocationEntry & A = * AP ; const ELFRelocationEntry & B = * BP ; if ( A . Offset != B . Offset ) return B . Offset - A . Offset ; if ( B . Type != A . Type ) return A . Type - B . Type ; return <NUM_LIT> ;


<s> static void print_csky_value ( FILE * f , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST_INT : fprintf ( f , HOST_WIDE_INT_PRINT_HEX , INTVAL ( x ) ) ; return ; case CONST_DOUBLE : fprintf ( f , <STR_LIT> , ( long ) XWINT ( x , <NUM_LIT> ) , ( long ) XWINT ( x , <NUM_LIT> ) ) ; return ; case CONST_VECTOR : { int i ; fprintf ( f , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < CONST_VECTOR_NUNITS ( x ) ; i ++ ) { fprintf ( f , HOST_WIDE_INT_PRINT_HEX , INTVAL ( CONST_VECTOR_ELT ( x , i ) ) ) ; if ( i < ( CONST_VECTOR_NUNITS ( x ) - <NUM_LIT> ) ) fputc ( ',' , f ) ; } fprintf ( f , <STR_LIT> ) ; }


<s> int NFI = MFI -> CreateFixedObject ( <NUM_LIT> , FRI -> second , true ) ; <ISA_LIT>FI -> recordReplacement ( FRI -> first , NFI ) ; for ( MachineFunction :: iterator MB = MF . begin ( ) , ME = MF . end ( ) ; MB != ME ; ++ MB ) { MachineBasicBlock :: iterator MBB = MB -> begin ( ) ; const MachineBasicBlock :: iterator MBE = MB -> end ( ) ; for ( ; MBB != MBE ; ++ MBB ) { MachineInstr :: mop_iterator MIB = MBB -> operands_begin ( ) ; const MachineInstr :: mop_iterator MIE = MBB -> operands_end ( ) ; for ( MachineInstr :: mop_iterator MII = MIB ; MII != MIE ; ++ MII ) { if ( ! MII -> isFI ( ) || MII -> getIndex ( ) != FRI -> first ) continue ;

DEBUG ( dbgs ( ) << <STR_LIT> << MII -> getIndex ( ) << <STR_LIT> ) ;


<s> const char * getPassName ( ) const override {


VLIWPacketizerList :: endPacket ( MBB , MI ) ;


<s> const char * mangle ; if ( ( mangle = aarch64_mangle_builtin_vector_type ( type ) ) || ( mangle = aarch64_mangle_builtin_scalar_type ( type ) ) ) return mangle ; return NULL ;


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( formatted_raw_ostream & OS , MCInstPrinter & InstPrinter ) : OS ( OS ) , InstPrinter ( InstPrinter ) {


<s> if ( ! TheTriple . isOSBinFormatCOFF ( ) ) return Printer . getSymbol ( GV ) ; assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; bool IsIndirect = ( TargetFlags & ( <STR_LIT> | <STR_LIT> ) ) ; if ( ! IsIndirect ) return Printer . getSymbol ( GV ) ; SmallString < <NUM_LIT> > Name ; if ( TargetFlags & <STR_LIT> ) Name = <STR_LIT> ; else if ( TargetFlags & <STR_LIT> ) Name = <STR_LIT> ;

Printer . TM . getNameWithPrefix ( Name , GV , Printer . getObjFileLowering ( ) . getMangler ( ) ) ;


<s> index = temp ; } switch ( GET_CODE ( index ) ) { case CONST_INT : fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , reg_names [ REGNO ( base ) ] , INTVAL ( index ) ) ; break ; default : gcc_unreachable ( ) ; } } break ; default : output_addr_const ( stream , x ) ; break ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = M [ i ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; ++ j ) { if ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != <NUM_LIT> * j + WhichResult ) return false ; }


<s> } Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( Opc , dl , VT , Op ) ;


<s> switch ( type ) { default : unreachable ( <STR_LIT> ) ; case ONEBYTE : dec = & ONEBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case TWOBYTE : dec = & TWOBYTE_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_38 : dec = & THREEBYTE38_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; case THREEBYTE_3A : dec = & THREEBYTE3A_SYM . opcodeDecisions [ insnContext ] . modRMDecisions [ opcode ] ; break ; } switch ( dec -> modrm_type ) { default : unreachable ( <STR_LIT> ) ; case MODRM_ONEENTRY : return dec -> instructionIDs [ <NUM_LIT> ] ;


<s> int alpha_using_fp ( ) { alpha_sa_size ( ) ; return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM ;


<s> function_builder :: ~ function_builder ( ) { obstack_free ( & m_string_obstack , NULL ) ;


<s> return ( int16x8_t ) __builtin_neon_vld1_lanev8hi ( ( const __builtin_neon_hi * ) __a , __b , __c ) ;


<s> static bool ShouldXformToMOVLP ( SDNode * V1 , SDNode * V2 , ShuffleVectorSDNode * Op ) { if ( ! <STR_LIT> ( V1 ) && ! isScalarLoadToVector ( V1 ) ) return false ; if ( <STR_LIT> ( V2 ) ) return false ;

unsigned NumElems = Op -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ;


<s> static bool rs6000_debug_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) { bool ret = rs6000_can_change_mode_class ( from , to , rclass ) ;

fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , GET_MODE_NAME ( from ) , GET_MODE_NAME ( to ) , reg_class_names [ rclass ] ) ;


<s> ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , nullptr , nullptr , <NUM_LIT> ) ; assert ( OrigArg . Regs . size ( ) == SplitVTs . size ( ) && <STR_LIT> ) ; if ( SplitVTs . size ( ) == <NUM_LIT> ) { auto Flags = OrigArg . Flags [ <NUM_LIT> ] ; unsigned OriginalAlignment = DL . getABITypeAlignment ( OrigArg . Ty ) ; Flags . setOrigAlign ( OriginalAlignment ) ; SplitArgs . emplace_back ( OrigArg . Regs [ <NUM_LIT> ] , SplitVTs [ <NUM_LIT> ] . getTypeForEVT ( Ctx ) , Flags , OrigArg . IsFixed ) ; return ; } for ( unsigned i = <NUM_LIT> , e = SplitVTs . size ( ) ; i != e ; ++ i ) {


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>ebTargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > Y ( getThe<ISA_LIT>elTarget ( ) ) ; RegisterTargetMachine < <ISA_LIT>ebTargetMachine > A ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>elTargetMachine > B ( getThe<ISA_LIT>64elTarget ( ) ) ; PassRegistry * PR = PassRegistry :: getPassRegistry ( ) ;


<s> unsigned CRm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned opc1 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned cop = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ( cop & ~ <NUM_LIT> ) == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( Rt == Rt2 ) S = MCDisassembler :: SoftFail ; Inst . addOperand ( MCOperand :: createImm ( cop ) ) ;

Inst . addOperand ( MCOperand :: createImm ( opc1 ) ) ;


<s> inline vector signed int vec_cmpeq ( vector float a1 , vector float a2 ) {

return ( vector signed int ) __builtin_altivec_vcmpeqfp ( ( vector float ) a1 , ( vector float ) a2 ) ;


<s> assert ( <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) <= HEXAGON_PACKET_SIZE ) ; std :: string Buffer ; { raw_string_ostream TempStream ( Buffer ) ; InstPrinter . printInst ( & Inst , TempStream , <STR_LIT> , STI ) ; } StringRef Contents ( Buffer ) ; auto PacketBundle = Contents . rsplit ( '\n' ) ; auto HeadTail = PacketBundle . first . split ( '\n' ) ; StringRef Separator = <STR_LIT> ; StringRef Indent = <STR_LIT> ; OS << <STR_LIT> ; while ( ! HeadTail . first . empty ( ) ) { StringRef InstTxt ; auto Duplex = HeadTail . first . split ( '\v' ) ; if ( ! Duplex . second . empty ( ) ) { OS << Indent << Duplex . first << Separator ; InstTxt = Duplex . second ; } else if ( ! HeadTail . first . trim ( ) . startswith ( <STR_LIT> ) ) { InstTxt = Duplex . first ; } if ( ! InstTxt . empty ( ) ) OS << Indent << InstTxt << Separator ; HeadTail = HeadTail . second . split ( '\n' ) ;


<s> if ( Kind != k_VectorIndex ) return false ; return VectorIndex . Val < <NUM_LIT> ;


<s> if ( ( <STR_LIT> ( STI ) || <STR_LIT> ( STI ) ) && ( STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA || STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; getTargetStreamer ( ) -> EmitCodeEnd ( STI ) ; } return AsmPrinter :: doFinalization ( M ) ;


<s> -- K ; switch ( K -> getKind ( ) ) { default : break ; case MCFragment :: FT_Align : { Size = <NUM_LIT> ; break ; } case MCFragment :: FT_Relaxable : { MCContext & Context = Asm . getContext ( ) ; auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < <NUM_LIT> ) { MCInst * Nop = new ( Context ) MCInst ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= <NUM_LIT> ; if ( ! <ISA_LIT>MCChecker ( Context , * MCII , * RF . getSubtargetInfo ( ) , Inst , * Context . getRegisterInfo ( ) , false ) . check ( ) ) { Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ; Size = <NUM_LIT> ; } }

bool Error = <ISA_LIT>MCShuffle ( Context , true , * MCII , * RF . getSubtargetInfo ( ) , Inst ) ;


<s> SDValue Pointer = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getRegister ( <STR_LIT> , PtrVT ) , DAG . getConstant ( CN -> getSExtValue ( ) , PtrVT ) ) ; SDValue ShufMask = DAG . getNode ( <STR_LIT> , dl , VT , Pointer ) ; SDValue result = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , ValOp ) , VecOp , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShufMask ) ) ; return result ;


<s> static inline unsigned getMemExtendImm ( <STR_LIT> ET , bool DoShift ) { return ( getExtendEncoding ( ET ) << <NUM_LIT> ) | unsigned ( DoShift ) ;


<s> MachineFunctionProperties getRequiredProperties ( ) const override { return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ;


<s> if ( InSVT == <STR_LIT> ) return SDValue ( ) ; if ( InSVT == <STR_LIT> && ( OutSVT == <STR_LIT> || ! Subtarget . hasSSE41 ( ) || Subtarget . hasInt256 ( ) ) ) return SDValue ( ) ; } SDLoc DL ( N ) ; if ( Subtarget . hasSSE41 ( ) || OutSVT == <STR_LIT> ) return combineVectorTruncationWithPACKUS ( N , DL , Subtarget , DAG ) ; if ( InSVT == <STR_LIT> ) return combineVectorTruncationWithPACKSS ( N , DL , Subtarget , DAG ) ;


<s> if ( ! fp_consts_inited ) init_fp_table ( ) ;

gcc_assert ( real_equal ( r , & value_fp0 ) ) ;


<s> if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) { addPass ( createInferAddressSpacesPass ( ) ) ; addPass ( create<ISA_LIT>PromoteAlloca ( & TM ) ) ; if ( EnableSROA ) addPass ( createSROAPass ( ) ) ; addStraightLineScalarOptimizationPasses ( ) ; if ( Enable<ISA_LIT>AliasAnalysis ) { addPass ( create<ISA_LIT>AAWrapperPass ( ) ) ; addPass ( createExternalAAWrapperPass ( [ ] ( Pass & P , Function & , AAResults & AAR ) { if ( auto * WrapperPass = P . getAnalysisIfAvailable < <ISA_LIT>AAWrapperPass > ( ) ) AAR . addAAResult ( WrapperPass -> getResult ( ) ) ; } ) ) ; } } TargetPassConfig :: addIRPasses ( ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addEarlyCSEOrGVNPass ( ) ;


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( ) ;