<s> if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : if ( Value & <NUM_LIT> || Value >= <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return Value >> <NUM_LIT> ; case <STR_LIT> : report_fatal_error ( <STR_LIT> ) ; return Value ; case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Value & <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( SignedValue > <NUM_LIT> || SignedValue < - <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( Value & <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; return ( Value >> <NUM_LIT> ) & <NUM_LIT> ; case FK_Data_1 :


<s> assert ( getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) && <STR_LIT> ) ;

MCTargetStreamer & TS = * getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == - <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Convert ; } if ( MI -> isCall ( ) || MI -> mayStore ( ) ) return Exit ; for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; Register Reg = MO . getReg ( ) ; if ( ! Register :: isPhysicalRegister ( Reg ) ) continue ; if ( RegInfo . regsOverlap ( Reg , RegInfo . getStackRegister ( ) ) ) return Exit ;


<s> case I387_CEIL : case I387_MASK_PM : if ( mode != I387_CW_ANY && mode != I387_CW_UNINITIALIZED ) emit_i387_cw_initialization ( mode ) ; break ; default : gcc_unreachable ( ) ; }


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64Bit ) , DL ( Subtarget . getDataLayoutString ( ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , JITInfo ( * this , is64Bit ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) { if ( Subtarget . isBGP ( ) ) setMCUseCFI ( false ) ;


<s> MxCond = <STR_LIT> ; break ; case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( Inverted ) MxCond = <STR_LIT> ( ( <STR_LIT> ) MxCond ) ; if ( CondOpcode == <STR_LIT> ) VTs = DAG . getVTList ( LHS . getValueType ( ) , LHS . getValueType ( ) , <STR_LIT> ) ; else VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue MxOp = DAG . getNode ( MxOpcode , DL , VTs , LHS , RHS ) ; if ( CondOpcode == <STR_LIT> ) Cond = MxOp . getValue ( <NUM_LIT> ) ; else Cond = MxOp . getValue ( <NUM_LIT> ) ; CC = DAG . getConstant ( MxCond , DL , <STR_LIT> ) ; AddTest = false ; } else { unsigned CondOpc ; if ( Cond . hasOneUse ( ) && isAndOrOfSetCCs ( Cond , CondOpc ) ) { SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( CondOpc == <STR_LIT> ) { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) ) { CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Cond = Cmp ; AddTest = false ; } } else { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) && Op . getNode ( ) -> hasOneUse ( ) ) { <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; CC = DAG . getConstant ( CCode , DL , <STR_LIT> ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> ) { SDValue FalseBB = User -> getOperand ( <NUM_LIT> ) ; SDNode * NewBR = DAG . UpdateNodeOperands ( User , User -> getOperand ( <NUM_LIT> ) , Dest ) ; assert ( NewBR == User ) ; ( void ) NewBR ; Dest = FalseBB ; Chain = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddressDarwin ( SDValue Op , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> useMovt ( ) ) { ++ NumMovwMovt ; if ( RelocM == Reloc :: Static ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; unsigned Wrapper = ( RelocM == Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ; return Result ; } unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; } else { <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; }

CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;


<s> Reg = getTargetVShiftNode ( <STR_LIT> , DL , <STR_LIT> , Reg , ShAmt , DAG ) ; } for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) / <NUM_LIT> ; i < e ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Regs [ i * <NUM_LIT> ] , Regs [ i * <NUM_LIT> + <NUM_LIT> ] ) ; if ( Regs . size ( ) > <NUM_LIT> ) { Regs . resize ( Regs . size ( ) / <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , OutVT , Regs ) ;


<s> auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> EmitCodeAlignment ( <NUM_LIT> ) ; OutStreamer -> EmitLabel ( CurSled ) ; auto Target = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitBytes ( <STR_LIT> ) ; EmitNops ( * OutStreamer , <NUM_LIT> , Subtarget -> is64Bit ( ) , getSubtargetInfo ( ) ) ; OutStreamer -> EmitLabel ( Target ) ;

recordSled ( CurSled , MI , SledKind :: FUNCTION_ENTER ) ;


<s> static void avr_expand_nops ( rtx operands0 ) { unsigned HOST_WIDE_INT n_nops = UINTVAL ( operands0 ) & GET_MODE_MASK ( HImode ) ; while ( n_nops -- ) { emit_insn ( gen_nopv ( const1_rtx ) ) ;


<s> assert ( hasValue ( ) && <STR_LIT> ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const TargetFrameInfo & TFI = * TM . getFrameInfo ( ) ;

unsigned StackAlignment = TFI . getStackAlignment ( ) ;


<s> if ( isLd && TID . mayStore ( ) ) return false ; if ( ! isLd ) { if ( TID . mayLoad ( ) ) return false ; if ( TID . mayStore ( ) ) return false ; } for ( unsigned j = <NUM_LIT> , NumOps = I -> getNumOperands ( ) ; j != NumOps ; ++ j ) { MachineOperand & MO = I -> getOperand ( j ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ;

if ( MO . isDef ( ) && TRI -> regsOverlap ( Reg , Base ) ) return false ;


<s> const DataLayout * DL = TM . getDataLayout ( ) ; MCContext & Ctx = AP . OutContext ; bool isDarwin = Triple ( TM . getTargetTriple ( ) ) . isOSDarwin ( ) ; SmallString < <NUM_LIT> > Name ; StringRef Suffix ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { if ( isDarwin ) Suffix = <STR_LIT> ; } else if ( MO . getTargetFlags ( ) & <STR_LIT> ) Suffix = <STR_LIT> ; if ( ! Suffix . empty ( ) ) Name += DL -> getPrivateGlobalPrefix ( ) ; unsigned PrefixLen = Name . size ( ) ; if ( ! MO . isGlobal ( ) ) { assert ( MO . isSymbol ( ) && <STR_LIT> ) ; Mang -> getNameWithPrefix ( Name , MO . getSymbolName ( ) ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; TM . getNameWithPrefix ( Name , GV , * Mang ) ; } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; MCSymbol * Sym = Ctx . GetOrCreateSymbol ( Name ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> && isDarwin ) { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . GetOrCreateSymbol ( OrigName ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( ) & <STR_LIT> ) { MachineModuleInfoMachO & MachO = getMachOMMI ( AP ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ( MO . getTargetFlags ( ) & <STR_LIT> ) ? MachO . getHiddenGVStubEntry ( Sym ) : MachO . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ;


<s> auto IsExpiredFn = [ TII , TRI ] ( const MachineInstr & MI , int ) { if ( <ISA_LIT>InstrInfo :: isVALU ( MI ) ) { if ( TII -> getNamedOperand ( MI , <STR_LIT> :: sdst ) ) return true ; for ( auto MO : MI . implicit_operands ( ) ) if ( MO . isDef ( ) && TRI -> isSGPRClass ( TRI -> getPhysRegClass ( MO . getReg ( ) ) ) ) return true ; } if ( MI . getOpcode ( ) == <STR_LIT> && ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) & <NUM_LIT> ) == <NUM_LIT> ) return true ; return false ; } ;

if ( :: getWaitStatesSince ( IsHazardFn , MI , IsExpiredFn ) == std :: numeric_limits < int > :: max ( ) ) return false ;


<s> vst3_u32 ( uint32_t * __a , uint32x2x3_t val ) { __builtin_aarch64_simd_ci __o ; uint32x4x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u32 ( val . val [ <NUM_LIT> ] , vcreate_u32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u32 ( val . val [ <NUM_LIT> ] , vcreate_u32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u32 ( val . val [ <NUM_LIT> ] , vcreate_u32 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ;

__o = __builtin_aarch64_set_qregciv4si ( __o , ( int32x4_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> const DataLayout * getDataLayout ( ) const override {

return getSubtargetImpl ( ) -> getDataLayout ( ) ;


<s> AlignmentIsInBytes = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: WinEH ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; CommentString = <STR_LIT> ; MaxInstLength = <NUM_LIT> ;


<s> return DecodeVecShiftRImm ( Inst , Imm , <NUM_LIT> ) ;


<s> static rtx frv_expand_binop_builtin ( enum insn_code icode , tree arglist , rtx target ) { rtx pat ; rtx op0 = frv_read_argument ( & arglist ) ;

rtx op1 = frv_read_argument ( & arglist ) ;


<s> InvertAndChangeJumpTarget ( MI , UncondTarget ) ; MBB -> removeSuccessor ( JumpAroundTarget ) ; MBB -> addSuccessor ( UncondTarget ) ; LayoutSucc -> erase ( LayoutSucc -> begin ( ) ) ; LayoutSucc -> removeSuccessor ( UncondTarget ) ; LayoutSucc -> addSuccessor ( JumpAroundTarget ) ; if ( case2 && ! case1 ) { JumpAroundTarget -> moveAfter ( LayoutSucc ) ; if ( ! UncondTarget -> canFallThrough ( ) ) { UncondTarget -> moveAfter ( JumpAroundTarget ) ; } } std :: vector < unsigned > OrigLiveIn ( LayoutSucc -> livein_begin ( ) , LayoutSucc -> livein_end ( ) ) ; std :: vector < unsigned > NewLiveIn ( JumpAroundTarget -> livein_begin ( ) , JumpAroundTarget -> livein_end ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < OrigLiveIn . size ( ) ; ++ i ) { LayoutSucc -> removeLiveIn ( OrigLiveIn [ i ] ) ; } for ( unsigned i = <NUM_LIT> ; i < NewLiveIn . size ( ) ; ++ i ) { LayoutSucc -> addLiveIn ( NewLiveIn [ i ] ) ; } } } }


<s> return isLegalMaskedLoadStore ( DataType , Alignment ) ;


<s> case CodeModel :: Small : { SDValue AddrHi = getTargetNode ( N , DL , Ty , DAG , <STR_LIT> ) ; SDValue AddrLo = getTargetNode ( N , DL , Ty , DAG , <STR_LIT> ) ; SDValue MNHi = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , AddrHi ) , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , MNHi , AddrLo ) , <NUM_LIT> ) ;


<s> default : return ; case VK_<ISA_LIT>_TPREL_HI20 : case VK_<ISA_LIT>_TPREL_LO12 : break ; }

fixELFSymbolsInTLSFixupsImpl ( getSubExpr ( ) , Asm ) ;


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;

SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , TRI -> getFrameRegister ( ) , VT ) ;


<s> if ( TM -> getTargetTriple ( ) . isOSWindows ( ) ) addPass ( createCFGuardLongjmpPass ( ) ) ;


__b = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __B ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> auto SectionLHS = GetFixupSection ( BinOp -> getLHS ( ) ) ; auto SectionRHS = GetFixupSection ( BinOp -> getRHS ( ) ) ; return SectionLHS == SectionRHS ? nullptr : SectionLHS ; } if ( auto UnOp = dyn_cast < MCUnaryExpr > ( Expr ) ) return GetFixupSection ( UnOp -> getSubExpr ( ) ) ;


<s> if ( Ptr -> getOpcode ( ) != <STR_LIT> && Ptr -> getOpcode ( ) != <STR_LIT> ) return false ; Base = Ptr -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Ptr -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( RHSC < <NUM_LIT> && RHSC > - <NUM_LIT> ) { assert ( Ptr -> getOpcode ( ) == <STR_LIT> ) ; isInc = false ; Offset = DAG . getConstant ( - RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ; return true ; } else if ( RHSC > <NUM_LIT> && RHSC < <NUM_LIT> ) { isInc = Ptr -> getOpcode ( ) == <STR_LIT> ;

Offset = DAG . getConstant ( RHSC , SDLoc ( Ptr ) , RHS -> getValueType ( <NUM_LIT> ) ) ;


<s> case TargetOpcode :: G_INTRINSIC_W_SIDE_EFFECTS : switch ( MI . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned MaxLen = EnableOpt ? <NUM_LIT> : <NUM_LIT> ; return ( ! EnableMinSize ) ? Helper . tryCombineMemCpyFamily ( MI , MaxLen ) : false ; } default : break ; } } if ( Generated . tryCombineAll ( Observer , MI , B ) ) return true ;


<s> const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; printOperand ( MI , OpNo , O ) ; if ( OffsetOp . isImm ( ) ) { int64_t Offset = OffsetOp . getImm ( ) ; if ( Offset >= <NUM_LIT> ) O << '+' ; O << Offset ; } else if ( OffsetOp . isExpr ( ) ) { O << * OffsetOp . getExpr ( ) ;


<s> nelt = d -> nelt ; eltsz = GET_MODE_UNIT_SIZE ( d -> vmode ) ; m128 = GEN_INT ( - <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { unsigned j , k , e = d -> perm [ i ] ; unsigned which = ( e >= nelt ) ; if ( e >= nelt ) e -= nelt ; for ( j = <NUM_LIT> ; j < eltsz ; ++ j ) { rperm [ which ] [ i * eltsz + j ] = GEN_INT ( e * eltsz + j ) ; rperm [ <NUM_LIT> - which ] [ i * eltsz + j ] = m128 ; } for ( k = i * eltsz + j ; k < <NUM_LIT> ; ++ k ) rperm [ <NUM_LIT> ] [ k ] = rperm [ <NUM_LIT> ] [ k ] = m128 ;


<s> } return MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return nullptr ;


return SubRegFromChannelTable [ Channel ] ;


<s> union { uint64_t x ; char a [ <NUM_LIT> ] ; } temp64 ; temp64 . x = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = strlen ( str ) ; i != e ; ++ i ) temp64 . a [ i ] = str [ e - <NUM_LIT> - i ] ; char encoded [ <NUM_LIT> ] ;


<s> Register VReg1 = MIB . getReg ( <NUM_LIT> ) ; ( void ) VReg1 ; assert ( MRI . getType ( VReg1 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg1 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ; Register VReg2 = MIB . getReg ( <NUM_LIT> ) ; ( void ) VReg2 ;

assert ( MRI . getType ( VReg2 ) . getSizeInBits ( ) == <NUM_LIT> && RBI . getRegBank ( VReg2 , MRI , TRI ) -> getID ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> if ( Parser . parseExpression ( IndexExpression ) || parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) { return true ; } UC . recordPersonalityIndex ( L ) ; if ( ! UC . hasFnStart ( ) ) { return Error ( L , <STR_LIT> ) ; } if ( UC . cantUnwind ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitCantUnwindLocNotes ( ) ; return true ; } if ( UC . hasHandlerData ( ) ) { Error ( L , <STR_LIT> ) ; UC . emitHandlerDataLocNotes ( ) ; return true ; } if ( HasExistingPersonality ) { Error ( L , <STR_LIT> ) ; UC . emitPersonalityLocNotes ( ) ; return true ;


<s> AvailableDomains = <NUM_LIT> << domain ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << PrintMB ( FromB ) << <STR_LIT> ) ; MachineBasicBlock :: iterator End = FromB -> getFirstTerminator ( ) ; MachineBasicBlock :: iterator I , NextI ; for ( I = FromB -> begin ( ) ; I != End ; I = NextI ) { assert ( ! I -> isPHI ( ) ) ; NextI = std :: next ( I ) ;

if ( isSafeToSpeculate ( & * I ) ) ToB -> splice ( At , FromB , I ) ;


<s> void printNegZeroOperand ( const MCInst * MI , unsigned OpNum ) {


return ( int64x2_t ) __builtin_neon_vdup_nv2di ( ( __builtin_neon_di ) __a ) ;


<s> else { rtx cc_reg ; mode = v850_gen_float_compare ( cond , mode , op0 , op1 ) ; cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; emit_insn ( gen_rtx_SET ( cc_reg , gen_rtx_REG ( mode , FCC_REGNUM ) ) ) ; return gen_rtx_fmt_ee ( cond , mode , cc_reg , const0_rtx ) ; }


<s> void fixup_7_pcrel ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) {

adjustRelativeBranch ( Size , Fixup , Value , Ctx ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ;


<s> return StringSwitch < unsigned > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> priority = P_PROC_BMI ; break ; case PROCESSOR_BDVER1 : arg_str = <STR_LIT> ; priority = P_PROC_XOP ; break ; case PROCESSOR_BDVER2 : arg_str = <STR_LIT> ; priority = P_PROC_FMA ; break ; case PROCESSOR_BDVER3 : arg_str = <STR_LIT> ; priority = P_PROC_FMA ; break ; case PROCESSOR_BDVER4 : arg_str = <STR_LIT> ; priority = P_PROC_AVX2 ; break ; case PROCESSOR_ZNVER1 : arg_str = <STR_LIT> ; priority = P_PROC_AVX2 ; break ; } } cl_target_option_restore ( & global_options , & cur_target ) ; if ( predicate_list && arg_str == NULL ) { error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> ) ; return <NUM_LIT> ; } if ( predicate_list ) { predicate_decl = ix86_builtins [ ( int ) IX86_BUILTIN_CPU_IS ] ; predicate_arg = build_string_literal ( strlen ( arg_str ) + <NUM_LIT> , arg_str ) ; predicate_chain = tree_cons ( predicate_decl , predicate_arg , predicate_chain ) ; } } tok_str = ( char * ) xmalloc ( strlen ( attrs_str ) + <NUM_LIT> ) ; strcpy ( tok_str , attrs_str ) ; token = strtok ( tok_str , <STR_LIT> ) ; predicate_decl = ix86_builtins [ ( int ) IX86_BUILTIN_CPU_SUPPORTS ] ; while ( token != NULL ) { if ( strncmp ( token , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { token = strtok ( NULL , <STR_LIT> ) ; continue ; } for ( i = <NUM_LIT> ; i < NUM_FEATURES ; ++ i ) { if ( strcmp ( token , feature_list [ i ] . name ) == <NUM_LIT> ) { if ( predicate_list ) { predicate_arg = build_string_literal ( strlen ( feature_list [ i ] . name ) + <NUM_LIT> , feature_list [ i ] . name ) ; predicate_chain = tree_cons ( predicate_decl , predicate_arg , predicate_chain ) ; } if ( feature_list [ i ] . priority > priority ) priority = feature_list [ i ] . priority ; break ; } } if ( predicate_list && i == NUM_FEATURES ) { error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> , token ) ; return <NUM_LIT> ; } token = strtok ( NULL , <STR_LIT> ) ; } free ( tok_str ) ; if ( predicate_list && predicate_chain == NULL_TREE ) { error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> , attrs_str ) ; return <NUM_LIT> ;


<s> EVT VmovVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , EncodedVal ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , StringRef ABIName , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( TT , CPU , FS , ABIName ) ) , InstrInfo ( ) , RegInfo ( getHwMode ( ) ) , TLInfo ( TM , * this ) {


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override {


<s> bool <ISA_LIT>TargetLowering :: isLegalAddImmediate ( int64_t Imm ) const { return isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , Context ) ;

if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useHVXOps ( ) ) return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>_HVX ) ;


<s> if ( Kind . isMergeableConst8 ( ) ) return MergeableConst8Section ; if ( Kind . isMergeableConst16 ( ) ) return MergeableConst16Section ; } Type * ObjType = GV -> getValueType ( ) ; auto & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( TM . getCodeModel ( ) == CodeModel :: Small || ! ObjType -> isSized ( ) || DL . getTypeAllocSize ( ObjType ) < CodeModelLargeSize ) { if ( Kind . isReadOnly ( ) ) return UseCPRel ? ReadOnlySection : DataRelROSection ; if ( Kind . isBSS ( ) || Kind . isCommon ( ) ) return BSSSection ; if ( Kind . isData ( ) ) return DataSection ; if ( Kind . isReadOnlyWithRel ( ) ) return DataRelROSection ; } else { if ( Kind . isReadOnly ( ) ) return UseCPRel ? ReadOnlySectionLarge : DataRelROSectionLarge ; if ( Kind . isBSS ( ) || Kind . isCommon ( ) ) return BSSSectionLarge ; if ( Kind . isData ( ) ) return DataSectionLarge ; if ( Kind . isReadOnlyWithRel ( ) ) return DataRelROSectionLarge ; }

assert ( ( Kind . isThreadLocal ( ) || Kind . isCommon ( ) ) && <STR_LIT> ) ;


<s> static bool aarch64_scalar_mode_supported_p ( scalar_mode mode ) {

return ( mode == HFmode ? true : default_scalar_mode_supported_p ( mode ) ) ;


<s> case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : return Value ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : {


<s> if ( Vec . getOpcode ( ) == <STR_LIT> ) return Result ; EVT VT = Vec . getValueType ( ) ; assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; EVT ElVT = VT . getVectorElementType ( ) ; EVT ResultVT = Result . getValueType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / ElVT . getSizeInBits ( ) ; unsigned NormalizedIdxVal = ( ( ( IdxVal * ElVT . getSizeInBits ( ) ) / <NUM_LIT> ) * ElemsPerChunk ) ; SDValue VecIdx = DAG . getIntPtrConstant ( NormalizedIdxVal ) ;

return DAG . getNode ( <STR_LIT> , dl , ResultVT , Result , Vec , VecIdx ) ;


<s> static inline std :: string createGlobalValueName ( const Module & M , const std :: string & Propose ) { std :: string Name = Propose ;

while ( M . getNamedGlobal ( Name ) ) Name += <STR_LIT> ;


<s> static bool IsInSmallSection ( uint64_t Size ) {

return Size > <NUM_LIT> && Size <= <NUM_LIT> ;


<s> LowerGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> static void nvptx_assemble_decl_end ( void ) { if ( init_frag . offset ) nvptx_assemble_value ( <NUM_LIT> , init_frag . size - init_frag . offset ) ; fprintf ( asm_out_file , init_frag . started ? <STR_LIT> : <STR_LIT> ) ;


<s> MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) ; int StackSize = MF . getFrameInfo ( ) -> getStackSize ( ) ; DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; DEBUG ( MI . print ( errs ( ) ) ) ; DEBUG ( errs ( ) << <STR_LIT> << FrameIndex << <STR_LIT> ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> ) ; DEBUG ( errs ( ) << <STR_LIT> << StackSize << <STR_LIT> ) ; Offset += StackSize ; Offset += MI . getOperand ( i + <NUM_LIT> ) . getImm ( ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; Offset /= <NUM_LIT> ; bool FP = TFI -> hasFP ( MF ) ; unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; assert ( <STR_LIT> -> contains ( Reg ) && <STR_LIT> ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( FP ) { bool isUs = isImmUs ( Offset ) ; unsigned FramePtr = <STR_LIT> ; if ( ! isUs ) { if ( ! RS ) report_fatal_error ( <STR_LIT> + Twine ( Offset ) ) ; unsigned ScratchReg = RS -> scavengeRegister ( <STR_LIT> , II , SPAdj ) ; loadConstant ( MBB , II , ScratchReg , Offset , dl ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , Reg ) . addReg ( FramePtr ) . addReg ( ScratchReg , RegState :: Kill ) ; break ; case <STR_LIT> :

BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( isKill ) ) . addReg ( FramePtr ) . addReg ( ScratchReg , RegState :: Kill ) ;


<s> const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( TM , DAG ) ;


<s> } if ( ! TLI . isTypeLegal ( OpVT ) ) return SDValue ( <NUM_LIT> , <NUM_LIT> ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , floatVT , Op . getOperand ( <NUM_LIT> ) ) ; unsigned opcode = ( OpVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( opcode , dl , Op . getValueType ( ) , Tmp ) ;


<s> tmp = fold_build_pointer_plus_hwi ( unshare_expr ( args ) , rsize ) ; tmp = build2 ( TRUTH_AND_EXPR , boolean_type_node , build2 ( GT_EXPR , boolean_type_node , tmp , unshare_expr ( skip ) ) , build2 ( LE_EXPR , boolean_type_node , unshare_expr ( args ) , unshare_expr ( skip ) ) ) ; tmp = build3 ( COND_EXPR , ptr_type_node , tmp , build2 ( POINTER_PLUS_EXPR , ptr_type_node , unshare_expr ( skip ) , size_int ( STACK_POINTER_OFFSET ) ) , unshare_expr ( args ) ) ; if ( BYTES_BIG_ENDIAN && rsize > size ) tmp = fold_build_pointer_plus_hwi ( tmp , rsize - size ) ; gimplify_assign ( addr , tmp , pre_p ) ; if ( BYTES_BIG_ENDIAN && rsize > size ) tmp = fold_build_pointer_plus_hwi ( addr , size ) ; else tmp = fold_build_pointer_plus_hwi ( addr , rsize ) ; gimplify_assign ( unshare_expr ( args ) , tmp , pre_p ) ; addr = fold_convert ( build_pointer_type ( type ) , addr ) ; if ( pass_by_reference_p ) addr = build_va_arg_indirect_ref ( addr ) ;

return build_va_arg_indirect_ref ( addr ) ;


<s> MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) { continue ; } if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) { break ; } I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ;


<s> if ( arm_ccfsm_state == <NUM_LIT> && ( unsigned ) arm_target_label == labelno && ! strcmp ( prefix , <STR_LIT> ) ) {


<s> CallingConv :: ID CallerCC = CallerF . getCallingConv ( ) ; if ( CalleeCC != CallingConv :: C || CallerCC != CallingConv :: C ) { return false ; } LLVMContext & C = * DAG . getContext ( ) ; if ( ! CCState :: resultsCompatible ( CalleeCC , CallerCC , MF , C , Ins , RetCC_<ISA_LIT>_C , RetCC_<ISA_LIT>_C ) ) { return false ; } if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , isVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , getCCAssignFn ( CalleeCC ) ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) {


<s> <ISA_LIT>TargetLowering :: <ISA_LIT>TargetLowering ( const TargetMachine & TM , const <ISA_LIT>Subtarget & STI ) : TargetLowering ( TM ) , Subtarget ( & STI ) { setBooleanContents ( ZeroOrOneBooleanContent ) ; setBooleanVectorContents ( ZeroOrOneBooleanContent ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ;

setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ;


<s> unsigned VmcntLo = unpackBits ( Waitcnt , getVmcntBitShiftLo ( ) , getVmcntBitWidthLo ( ) ) ; if ( Version . Major < <NUM_LIT> ) return VmcntLo ; unsigned VmcntHi = unpackBits ( Waitcnt , getVmcntBitShiftHi ( ) , getVmcntBitWidthHi ( ) ) ; VmcntHi <<= getVmcntBitWidthLo ( ) ;


return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true , true , true ) ;


<s> inline int vec_all_nlt ( vector float a1 , vector float a2 ) { return __builtin_altivec_vcmpgtfp_p ( __CR6_EQ , a2 , a1 ) ;


<s> int Splat = getT2SOImmValSplatVal ( Arg ) ; if ( Splat != - <NUM_LIT> ) return Splat ;

int Rot = getT2SOImmValRotateVal ( Arg ) ;


<s> MemDefsUses :: MemDefsUses ( const DataLayout & DL , const MachineFrameInfo * MFI_ ) : InspectMemInstr ( false ) , MFI ( MFI_ ) , DL ( DL ) , SeenNoObjLoad ( false ) , SeenNoObjStore ( false ) {


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_<ISA_LIT> , true , false ) {


<s> IntelExprStateMachine ( ) : State ( IES_INIT ) , PrevState ( IES_ERROR ) , BaseReg ( <NUM_LIT> ) , IndexReg ( <NUM_LIT> ) , TmpReg ( <NUM_LIT> ) , Scale ( <NUM_LIT> ) , Imm ( <NUM_LIT> ) , Sym ( nullptr ) , BracCount ( <NUM_LIT> ) , MemExpr ( false ) , OffsetOperator ( false ) , AttachToOperandIdx ( false ) , IsPIC ( false ) {


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> break ; case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitDataProcessingInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitLoadStoreInstruction ( MI , <NUM_LIT> , <STR_LIT> ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { addPCLabel ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; emitMiscLoadStoreInstruction ( MI , <STR_LIT> ) ; break ; } case <STR_LIT> :


return ( uint64x1_t ) { ( __a [ <NUM_LIT> ] & __b [ <NUM_LIT> ] ) ? - <NUM_LIT> : <NUM_LIT> } ;


<s> int lobit , hibit ; if ( x == <NUM_LIT> ) return - <NUM_LIT> ; for ( lobit = <NUM_LIT> ; lobit < <NUM_LIT> ; lobit ++ ) if ( x & ( <NUM_LIT> << lobit ) ) break ; for ( hibit = <NUM_LIT> ; hibit >= <NUM_LIT> ; hibit -- ) if ( x & ( <NUM_LIT> << hibit ) ) break ; int width = <NUM_LIT> + hibit - lobit ; if ( width > <NUM_LIT> ) return - <NUM_LIT> ; if ( x != ( NBITS ( width ) << lobit ) ) return - <NUM_LIT> ; return ( ( width & <NUM_LIT> ) << <NUM_LIT> ) | lobit ;


<s> explicit <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , true ) {


<s> static rtx gen_stack_pointer_inc ( rtx increment ) { return gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , increment ) ) ;


<s> if ( code == ASHIFT ) emit_insn ( gen_ashlv2di3 ( tmp3 , tmp2 , GEN_INT ( bits - <NUM_LIT> ) ) ) ; else emit_insn ( gen_lshrv2di3 ( tmp3 , tmp2 , GEN_INT ( bits - <NUM_LIT> ) ) ) ; } else { rtx tmp4 = force_reg ( V2DImode , gen_lowpart ( V2DImode , op1 ) ) ; rtx tmp5 = gen_reg_rtx ( V2DImode ) ; if ( code == ASHIFT ) emit_insn ( gen_ashlv2di3 ( tmp5 , tmp4 , GEN_INT ( bits ) ) ) ; else emit_insn ( gen_lshrv2di3 ( tmp5 , tmp4 , GEN_INT ( bits ) ) ) ; rtx tmp6 = gen_reg_rtx ( V2DImode ) ; if ( code == ASHIFT ) emit_insn ( gen_lshrv2di3 ( tmp6 , tmp2 , GEN_INT ( <NUM_LIT> - bits ) ) ) ; else emit_insn ( gen_ashlv2di3 ( tmp6 , tmp2 , GEN_INT ( <NUM_LIT> - bits ) ) ) ; emit_insn ( gen_iorv2di3 ( tmp3 , tmp5 , tmp6 ) ) ;


<s> <ISA_LIT>TargetWasmStreamer :: <ISA_LIT>TargetWasmStreamer ( MCStreamer & S ) : <ISA_LIT>TargetStreamer ( S ) {


<s> if ( code >= RS6000_BUILTIN_COUNT ) return error_mark_node ; fnmask = rs6000_builtin_info [ code ] . mask ; if ( ( fnmask & rs6000_builtin_mask ) != fnmask ) { rs6000_invalid_builtin ( ( enum rs6000_builtins ) code ) ; return error_mark_node ; }


<s> h8_reg_names = names_extended ; h8_push_op = h8_push_ops [ cpu_type ] ; h8_pop_op = h8_pop_ops [ cpu_type ] ; h8_mov_op = h8_mov_ops [ cpu_type ] ; if ( TARGET_H8300S ) target_flags &= ~ MASK_H8300H ; if ( ! TARGET_H8300S && TARGET_MAC ) { error ( <STR_LIT> ) ; target_flags |= MASK_H8300S_1 ; } if ( ! TARGET_H8300S && TARGET_EXR ) { error ( <STR_LIT> ) ; target_flags |= MASK_H8300S_1 ; } if ( ( ! TARGET_H8300S && TARGET_EXR ) && ( ! TARGET_H8300SX && TARGET_EXR ) ) { error ( <STR_LIT> ) ; target_flags |= MASK_H8300S_1 ; } if ( ( ! TARGET_H8300S && TARGET_NEXR ) && ( ! TARGET_H8300SX && TARGET_NEXR ) ) { warning ( OPT_mno_exr , <STR_LIT> <STR_LIT> ) ; } if ( ( TARGET_NORMAL_MODE ) ) { error ( <STR_LIT> ) ; target_flags ^= MASK_NORMAL_MODE ; } if ( optimize_size ) { shift_alg_hi [ H8_300H ] [ SHIFT_ASHIFT ] [ <NUM_LIT> ] = SHIFT_LOOP ; shift_alg_hi [ H8_300H ] [ SHIFT_ASHIFT ] [ <NUM_LIT> ] = SHIFT_LOOP ; shift_alg_hi [ H8_300H ] [ SHIFT_LSHIFTRT ] [ <NUM_LIT> ] = SHIFT_LOOP ; shift_alg_hi [ H8_300H ] [ SHIFT_LSHIFTRT ] [ <NUM_LIT> ] = SHIFT_LOOP ; shift_alg_hi [ H8_300H ] [ SHIFT_ASHIFTRT ] [ <NUM_LIT> ] = SHIFT_LOOP ; shift_alg_hi [ H8_300H ] [ SHIFT_ASHIFTRT ] [ <NUM_LIT> ] = SHIFT_LOOP ;


<s> bool <ISA_LIT>InstPrinter :: printAlias ( const MCInst * MI , raw_ostream & OS ) { switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : return printMemoryLoadIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return printMemoryLoadIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return printMemoryLoadIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return printMemoryLoadIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return printMemoryLoadIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return printMemoryStoreIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return printMemoryStoreIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return printMemoryStoreIncrement ( MI , OS , <STR_LIT> , <NUM_LIT> ) ;


<s> if ( GET_CODE ( op ) == REG ) regno = REGNO ( op ) ; else if ( GET_CODE ( op ) == SUBREG && GET_CODE ( SUBREG_REG ( op ) ) == REG ) { if ( REGNO ( SUBREG_REG ( op ) ) < FIRST_PSEUDO_REGISTER ) regno = subreg_regno ( op ) ;

else regno = REGNO ( SUBREG_REG ( op ) ) ;


<s> MCWinCOFFStreamer * llvm :: create<ISA_LIT>WinCOFFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , bool RelaxAll , bool IncrementalLinkerCompatible ) {

auto * S = new <ISA_LIT>WinCOFFStreamer ( Context , std :: move ( MAB ) , std :: move ( Emitter ) , std :: move ( OW ) ) ;


<s> static const char * m68hc11_strip_name_encoding ( const char * str ) { return str + ( * str == '*' || * str == '@' || * str == '&' ) ;


<s> inline const type_suffix_info & function_instance :: type_suffix ( unsigned int i ) const {

return type_suffixes [ type_suffix_ids [ i ] ] ;


<s> EVT ValTy = Op . getValueType ( ) ; bool HasGotOfst = ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ; unsigned GotFlag = Has<ISA_LIT>64 ? ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) : ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , ValTy , <NUM_LIT> , GotFlag ) ; GA = DAG . getNode ( <STR_LIT> , dl , ValTy , GetGlobalReg ( DAG , ValTy ) , GA ) ; SDValue ResNode = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , GA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; if ( ! HasGotOfst ) return ResNode ;

SDValue GALo = DAG . getTargetGlobalAddress ( GV , dl , ValTy , <NUM_LIT> , Has<ISA_LIT>64 ? <STR_LIT> :


<s> switch ( IntNo ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoadOp = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = false ; isLoadOp = false ; break ; } } EVT VecTy ; if ( isLoadOp ) { VecTy = N -> getValueType ( <NUM_LIT> ) ; } else if ( isIntrinsic ) { VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; } else { assert ( isStore && <STR_LIT> ) ; VecTy = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; } unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint64_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ;

} else if ( NumBytes >= <NUM_LIT> * <NUM_LIT> ) {


<s> if ( GET_MODE ( address ) == VOIDmode ) return <NUM_LIT> ; REAL_VALUE_TO_TARGET_DOUBLE ( * CONST_DOUBLE_REAL_VALUE ( address ) , sval ) ; if ( ( sval [ <NUM_LIT> ] & <NUM_LIT> ) == <NUM_LIT> && sval [ <NUM_LIT> ] == <NUM_LIT> ) return <NUM_LIT> ;


<s> pass_remove_partial_avx_dependency ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_remove_partial_avx_dependency , ctxt ) {


<s> if ( Subtarget -> getTrapHandlerAbi ( ) != GCNSubtarget :: TrapHandlerAbiHsa || ! Subtarget -> isTrapHandlerEnabled ( ) ) { DiagnosticInfoUnsupported NoTrap ( MF . getFunction ( ) , <STR_LIT> , Op . getDebugLoc ( ) , DS_Warning ) ; LLVMContext & Ctx = MF . getFunction ( ) . getContext ( ) ; Ctx . diagnose ( NoTrap ) ; return Chain ; }


<s> if ( schedulerCreator != NULL ) addPass ( schedulerCreator ( <STR_LIT> ) ) ;

addPass ( create<ISA_LIT>NopFillerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> HRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: UsrOverflowMutation > ( ) ) ; addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ; addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: BankConflictMutation > ( ) ) ;


<s> static bool s390_use_by_pieces_infrastructure_p ( unsigned HOST_WIDE_INT size , unsigned int align ATTRIBUTE_UNUSED , enum by_pieces_operation op ATTRIBUTE_UNUSED , bool speed_p ATTRIBUTE_UNUSED ) { return ( size == <NUM_LIT> || size == <NUM_LIT> || size == <NUM_LIT> || ( TARGET_ZARCH && size == <NUM_LIT> ) ) ;


<s> SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , DL , OpLo , OpHi , ShufMask ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget -> hasInt256 ( ) ) { In = DAG . getBitcast ( <STR_LIT> , In ) ; SmallVector < SDValue , <NUM_LIT> > pshufbMask ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) pshufbMask . push_back ( DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } SDValue BV = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , pshufbMask ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , BV ) ; In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , DAG . getUNDEF ( <STR_LIT> ) , & ShufMask [ <NUM_LIT> ] ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> SDValue Arg0 = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue Arg1 = Op . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ;

if ( Arg0 . getValueType ( ) != <STR_LIT> || Arg1 . getValueType ( ) != <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ;


<s> unsigned OffsetIdx = MI . getNumExplicitOperands ( ) - <NUM_LIT> ; assert ( MI . getOperand ( OffsetIdx - <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; MachineOperand & OffsetOpnd = MI . getOperand ( OffsetIdx ) ;

assert ( LocalStackSize % <NUM_LIT> == <NUM_LIT> ) ;


<s> unsigned getCacheLineSize ( ) const override { return <NUM_LIT> ;


<s> unsigned <ISA_LIT>Subtarget :: getMethodCacheSize ( ) const {


<s> TargetPassConfig :: addIRPasses ( ) ;


<s> static bool renderGraphFromBottomUp ( ) { return true ;


<s> Changed |= MaybeRewriteToDrop ( OldReg , NewReg , MO , MFI , MRI ) ; } } } break ; } case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ; break ; case <STR_LIT> : Changed |= MaybeRewriteToFallthrough ( MI , MBB , MF , MFI , MRI , TII , <STR_LIT> , <STR_LIT> ) ;


<s> BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( std :: next ( IP ) , NewBB ) ; else WaterList . insert ( IP , OrigBB ) ; NewWaterList . insert ( OrigBB ) ; computeBlockSize ( MF , OrigBB , BBInfo [ OrigBB -> getNumber ( ) ] ) ; computeBlockSize ( MF , NewBB , BBInfo [ NewBB -> getNumber ( ) ] ) ; adjustBBOffsetsAfter ( OrigBB ) ; return NewBB ;


<s> const llvm :: <STR_LIT> * NewFormatInfo = llvm :: <STR_LIT> ( OldFormatInfo -> BitsPerComp , ComponentCount , OldFormatInfo -> NumFormat , STI ) ; if ( ! NewFormatInfo ) return <NUM_LIT> ;

assert ( NewFormatInfo -> NumFormat == OldFormatInfo -> NumFormat && NewFormatInfo -> BitsPerComp == OldFormatInfo -> BitsPerComp ) ;


<s> bool intersects ( const RegisterSet & Rs ) const {


<s> sri -> t_icode = CODE_FOR_nothing ; sri -> extra_cost = <NUM_LIT> ; icode = ( ( in_p ) ? reg_addr [ mode ] . reload_load : reg_addr [ mode ] . reload_store ) ; if ( REG_P ( x ) || register_operand ( x , mode ) ) { enum rs6000_reg_type to_type = reg_class_to_reg_type [ ( int ) rclass ] ; bool altivec_p = ( rclass == ALTIVEC_REGS ) ; enum rs6000_reg_type from_type = register_to_reg_type ( x , & altivec_p ) ; if ( ! in_p ) std :: swap ( to_type , from_type ) ; if ( rs6000_secondary_reload_move ( to_type , from_type , mode , sri , altivec_p ) ) { icode = ( enum insn_code ) sri -> icode ; default_p = false ; done_p = true ; ret = NO_REGS ; } } if ( x == CONST0_RTX ( mode ) && VSX_REG_CLASS_P ( rclass ) ) { ret = NO_REGS ; default_p = false ; done_p = true ; } if ( ! done_p && reg_addr [ mode ] . scalar_in_vmx_p && ! mode_supports_vmx_dform ( mode ) && ( rclass == VSX_REGS || rclass == ALTIVEC_REGS ) && ( memory_p || CONST_DOUBLE_P ( x ) ) ) { ret = FLOAT_REGS ; default_p = false ; done_p = true ; } if ( ! done_p && icode != CODE_FOR_nothing && memory_p ) { int extra_cost = rs6000_secondary_reload_memory ( XEXP ( x , <NUM_LIT> ) , rclass , mode ) ; if ( extra_cost >= <NUM_LIT> ) { done_p = true ; ret = NO_REGS ; if ( extra_cost > <NUM_LIT> ) { sri -> extra_cost = extra_cost ; sri -> icode = icode ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ;


<s> return expandUnalignedStore ( Store , DAG ) ; } unsigned AS = Store -> getAddressSpace ( ) ; if ( Subtarget -> hasLDSMisalignedBug ( ) && AS == <ISA_LIT>AS :: FLAT_ADDRESS && Store -> getAlignment ( ) < VT . getStoreSize ( ) && VT . getSizeInBits ( ) > <NUM_LIT> ) { return SplitVectorStore ( Op , DAG ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( AS == <ISA_LIT>AS :: FLAT_ADDRESS && ! Subtarget -> hasMultiDwordFlatScratchAddressing ( ) ) AS = MFI -> hasFlatScratchInit ( ) ? <ISA_LIT>AS :: PRIVATE_ADDRESS : <ISA_LIT>AS :: GLOBAL_ADDRESS ; unsigned NumElements = VT . getVectorNumElements ( ) ; if ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) { if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; if ( NumElements == <NUM_LIT> && ! Subtarget -> hasDwordx3LoadStores ( ) ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; } else if ( AS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) { switch ( Subtarget -> getMaxPrivateElementSize ( ) ) { case <NUM_LIT> : return scalarizeVectorStore ( Store , DAG ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ; return SDValue ( ) ; case <NUM_LIT> : if ( NumElements > <NUM_LIT> || NumElements == <NUM_LIT> ) return SplitVectorStore ( Op , DAG ) ;


<s> unsigned ByteOffset = DwordOffset * <NUM_LIT> ; PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_BUFFER_0 ) ;

assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ;


<s> switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_RegisterMask : continue ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = LowerSymbolOperand ( MO , GetBlockAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = LowerSymbolOperand ( MO , GetJumpTableSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = LowerSymbolOperand ( MO , GetConstantPoolIndexSymbol ( MO ) ) ; break ; default :


<s> else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>16InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MBB . getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ) ; FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II , DL , NewImm ) ; Offset = SignExtend64 < <NUM_LIT> > ( NewImm ) ; IsKill = true ; } MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false , false , IsKill ) ;

MI . getOperand ( OpNo + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( DestReg ) ) MF . getRegInfo ( ) . constrainRegClass ( DestReg , & <STR_LIT> ) ; else assert ( DestReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( getSubTarget ( ) . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( getSubTarget ( ) . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( getSubTarget ( ) . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( getSubTarget ( ) . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( getSubTarget ( ) . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( getSubTarget ( ) . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> , Offset = false ; } break ;


<s> uint64_t const F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ;

return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> return <STR_LIT> ; } loongarch_config_target ( & la_target , opt_switches , opt_arch_driver , opt_tune_driver , opt_fpu_driver , opt_abi_base_driver , opt_abi_ext_driver , opt_cmodel_driver , ! no_link ) ; obstack_blank ( & opts_obstack , <NUM_LIT> ) ; obstack_grow ( & opts_obstack , ( const void * ) ( S ) , \ sizeof ( ( S ) ) / sizeof ( char ) - <NUM_LIT> ) obstack_grow ( & opts_obstack , ( const void * ) ( S ) , strlen ( ( S ) ) ) APPEND_LTR ( <STR_LIT> OPTSTR_ ## NAME <STR_LIT> \ <STR_LIT> OPTSTR_ ## NAME <STR_LIT> ) for ( int i = <NUM_LIT> ; i < N_SWITCH_TYPES ; i ++ ) { APPEND_LTR ( <STR_LIT> ) ;

APPEND_VAL ( loongarch_switch_strings [ i ] ) ;


<s> MachineInstr * <ISA_LIT>InstrInfo :: foldMemoryOperandImpl ( MachineFunction & MF , MachineInstr * MI , ArrayRef < unsigned > Ops , MachineInstr * LoadMI ) const {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( <NUM_LIT> <= Offset && Offset <= <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( Offset ) ; case <STR_LIT> : return true ; } llvm_unreachable ( <STR_LIT> <STR_LIT> ) ;


<s> return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( Is64Bit , CPUType , CPUSubtype ) , OS , true ) ;


<s> void addImm0_15Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue ( ) ) ) ;


<s> switch ( parser . getAssemblerDialect ( ) ) { case <NUM_LIT> : ParseBytes = PrintAsEncoded ; break ;

case <NUM_LIT> : ParseBytes = PrintCallAsBytes ; break ;


<s> assert ( MRI . getType ( Reg ) . isVector ( ) && <STR_LIT> ) ;

MachineInstr * OpMI = MRI . getVRegDef ( Reg ) ;


<s> State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) {


<s> if ( GET_MODE ( op0 ) == BImode ) { gcc_assert ( ( code == NE || code == EQ ) && op1 == const0_rtx ) ; tem = op0 , code2 = code ; } else { switch ( code ) { case EQ : case LT : case LE : case LEU : case LTU :


<s> case LT : case LE : case GT : case GE : return CCFPEmode ; case UNEQ : case LTGT : default : gcc_unreachable ( ) ; } } if ( op1 == constm1_rtx ) return CCCmode ; if ( ( code == LTU || code == GEU ) && GET_CODE ( op0 ) == PLUS && rtx_equal_p ( XEXP ( op0 , <NUM_LIT> ) , op1 ) ) return CCCmode ; if ( ( code == EQ || code == NE ) && GET_CODE ( op1 ) == UNSPEC && ( XINT ( op1 , <NUM_LIT> ) == UNSPEC_ADDV || XINT ( op1 , <NUM_LIT> ) == UNSPEC_SUBV || XINT ( op1 , <NUM_LIT> ) == UNSPEC_NEGV ) ) return CCVmode ; if ( op1 != const0_rtx ) return CCmode ; switch ( GET_CODE ( op0 ) ) { case PLUS : case MINUS : case NEG : case ASHIFT : case LTU : case LT : return CCNZmode ; case ZERO_EXTRACT : return CCCmode ; case REG : case AND :


<s> return parseRegs ( Operands , ( int ) <STR_LIT> ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {

addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;


<s> } else if ( M == SM_SentinelZero ) { ZeroElts . setBit ( i ) ; continue ; } assert ( <NUM_LIT> <= M && M < ( int ) ( NumMaskElts * NumOps ) ) ; unsigned SrcOpIdx = ( unsigned ) M / NumMaskElts ; unsigned SrcMaskIdx = ( unsigned ) M % NumMaskElts ; auto & SrcUndefElts = UndefEltsOps [ SrcOpIdx ] ; if ( SrcUndefElts [ SrcMaskIdx ] ) { UndefElts . setBit ( i ) ; continue ; } auto & SrcEltBits = RawBitsOps [ SrcOpIdx ] ; APInt & Bits = SrcEltBits [ SrcMaskIdx ] ; if ( ! Bits ) { ZeroElts . setBit ( i ) ; continue ; } ConstantElts . setBit ( i ) ; ConstantBitData [ i ] = Bits ; } assert ( ( UndefElts | ZeroElts | ConstantElts ) . isAllOnesValue ( ) ) ; if ( ( UndefElts | ZeroElts ) . isAllOnesValue ( ) ) return getZeroVector ( Root . getSimpleValueType ( ) , Subtarget , DAG , DL ) ; MVT MaskSVT ;

if ( VT . isFloatingPoint ( ) && ( MaskSizeInBits == <NUM_LIT> || MaskSizeInBits == <NUM_LIT> ) ) MaskSVT = <STR_LIT> ( MaskSizeInBits ) ;


<s> SDValue Size = Tmp2 . getOperand ( <NUM_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Tmp3 ) -> getZExtValue ( ) ; const TargetFrameLowering & TFI = * Subtarget -> getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Align , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ; Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , SDValue ( ) , SDLoc ( Node ) ) ; SDValue Ops [ <NUM_LIT> ] = { Tmp1 , Tmp2 } ; return DAG . getMergeValues ( Ops , dl ) ; } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) ; bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = getPointerTy ( ) ; if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; }

const TargetRegisterClass * AddrRegClass = getRegClassFor ( getPointerTy ( ) ) ;


<s> static void mmix_file_end ( void ) { switch_to_section ( data_section ) ;


<s> case IOR : case XOR : case NOT : case NEG : if ( ! speed ) * total = COSTS_N_INSNS ( LM32_NUM_REGS ( mode ) ) ; else * total = COSTS_N_INSNS ( arithmetic_latency + ( LM32_NUM_REGS ( mode ) - <NUM_LIT> ) ) ; break ; case COMPARE : if ( small_mode ) { if ( ! speed ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( compare_latency ) ; } else { * total = COSTS_N_INSNS ( LM32_NUM_REGS ( mode ) * ( <NUM_LIT> + <NUM_LIT> ) / <NUM_LIT> ) ; } break ; case ASHIFT : case ASHIFTRT : case LSHIFTRT : if ( TARGET_BARREL_SHIFT_ENABLED && small_mode ) { if ( ! speed ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( shift_latency ) ; } else if ( TARGET_BARREL_SHIFT_ENABLED ) { * total = COSTS_N_INSNS ( LM32_NUM_REGS ( mode ) * <NUM_LIT> ) ; } else if ( small_mode && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { * total = COSTS_N_INSNS ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ; } else { if ( ! speed ) * total = COSTS_N_INSNS ( libcall_size_cost ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } break ; case MULT : if ( TARGET_MULTIPLY_ENABLED && small_mode ) { if ( ! speed ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( multiply_latency ) ; } else { if ( ! speed ) * total = COSTS_N_INSNS ( libcall_size_cost ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } break ; case DIV : case MOD : case UDIV : case UMOD : if ( TARGET_DIVIDE_ENABLED && small_mode ) { if ( ! speed ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else { if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT ) { int cycles = <NUM_LIT> ; unsigned HOST_WIDE_INT i = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; while ( i ) { i >>= <NUM_LIT> ; cycles ++ ; } if ( IN_RANGE ( i , <NUM_LIT> , <NUM_LIT> ) ) * total = COSTS_N_INSNS ( <NUM_LIT> + <NUM_LIT> + cycles ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> + <NUM_LIT> + cycles ) ; return true ; } else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG ) { * total = COSTS_N_INSNS ( <NUM_LIT> + GET_MODE_SIZE ( mode ) / <NUM_LIT> ) ; return true ; } else { * total = COSTS_N_INSNS ( <NUM_LIT> + GET_MODE_SIZE ( mode ) / <NUM_LIT> ) ; return false ; } } } else { if ( ! speed ) * total = COSTS_N_INSNS ( libcall_size_cost ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } break ; case HIGH : case LO_SUM :


<s> for ( auto & MI : MBB ) FnSize += TII . getInstSizeInBytes ( MI ) ; }


<s> static rtx riscv_swap_instruction ( rtx inst ) { gcc_assert ( GET_MODE ( inst ) == SImode ) ;

if ( BYTES_BIG_ENDIAN ) inst = expand_unop ( SImode , bswap_optab , inst , gen_reg_rtx ( SImode ) , <NUM_LIT> ) ;


<s> if ( Subtarget . useHVXOps ( ) ) { ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: find ( Tys , ElemTy ) != Tys . end ( ) ) { unsigned HwWidth = <NUM_LIT> * Subtarget . getVectorLength ( ) ; unsigned VecWidth = VT . getSizeInBits ( ) ;

if ( VecWidth >= HwWidth / <NUM_LIT> && VecWidth < HwWidth ) return TargetLoweringBase :: TypeWidenVector ;


<s> assert ( isMem ( MI , Op ) && <STR_LIT> ) ; const MachineOperand & Segment = MI -> getOperand ( Op + <NUM_LIT> ) ; if ( Segment . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , Modifier ) ; O << ':' ;


<s> if ( ! Op . isReg ( ) || Op . isImplicit ( ) || ! Op . isUse ( ) ) continue ; unsigned Reg = Op . getReg ( ) ; MachineInstr * Def = MRI . getUniqueVRegDef ( Reg ) ; if ( ! Def ) continue ; if ( Def -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) continue ; if ( Def -> getOpcode ( ) == TargetOpcode :: INLINEASM ) continue ; if ( Def -> getOpcode ( ) == TargetOpcode :: PHI ) continue ; if ( Def -> getOpcode ( ) == <STR_LIT> || Def -> getOpcode ( ) == <STR_LIT> || Def -> getOpcode ( ) == <STR_LIT> || Def -> getOpcode ( ) == <STR_LIT> ) continue ; if ( ! MRI . hasOneUse ( Reg ) ) continue ; if ( Def -> getParent ( ) != & MBB ) continue ; if ( ! IsSafeToMove ( Def , Insert , AA , LIS , MRI ) ) continue ; Changed = true ; AnyStackified = true ; MBB . splice ( Insert , & MBB , Def ) ; LIS . handleMove ( Def ) ; MFI . stackifyVReg ( Reg ) ; ImposeStackOrdering ( Def ) ; Insert = Def ; } if ( AnyStackified ) ImposeStackOrdering ( & MI ) ; } } if ( Changed ) { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; for ( MachineBasicBlock & MBB : MF ) MBB . addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > Stack ; for ( MachineBasicBlock & MBB : MF ) {


<s> SDValue Lo = Op . getOperand ( <NUM_LIT> ) ; SDValue Hi = Op . getOperand ( <NUM_LIT> ) ; SDValue Shift = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Width = DAG . getConstant ( VT . getSizeInBits ( ) , DL , VT ) ; SDValue Width1 = DAG . getConstant ( VT . getSizeInBits ( ) - <NUM_LIT> , DL , VT ) ; SDValue BigShift = DAG . getNode ( <STR_LIT> , DL , VT , Shift , Width ) ; SDValue CompShift = DAG . getNode ( <STR_LIT> , DL , VT , Width1 , Shift ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Lo , CompShift ) ; Overflow = DAG . getNode ( <STR_LIT> , DL , VT , Overflow , One ) ; SDValue HiSmall = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shift ) ;

HiSmall = DAG . getNode ( <STR_LIT> , DL , VT , HiSmall , Overflow ) ;


<s> Value * <ISA_LIT>IREmitter :: visitATOMADD64_DAG ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } return ; } if ( dump_file ) fprintf ( dump_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , size ) ; HOST_WIDE_INT rounded_size = ROUND_DOWN ( size , guard_size ) ; HOST_WIDE_INT residual = size - rounded_size ; if ( rounded_size <= STACK_CLASH_MAX_UNROLL_PAGES * guard_size ) { for ( HOST_WIDE_INT i = <NUM_LIT> ; i < rounded_size ; i += guard_size ) { aarch64_sub_sp ( NULL , temp2 , guard_size , true ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , guard_used_by_caller ) ) ; emit_insn ( gen_blockage ( ) ) ; } dump_stack_clash_frame_info ( PROBE_INLINE , size != rounded_size ) ; } else { aarch64_add_offset ( Pmode , temp1 , stack_pointer_rtx , - rounded_size , temp1 , NULL , false , true ) ; rtx_insn * insn = get_last_insn ( ) ; if ( frame_related_p ) { add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , temp1 , rounded_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } insn = emit_insn ( gen_probe_stack_range ( stack_pointer_rtx , stack_pointer_rtx , temp1 ) ) ; if ( frame_related_p ) { add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , rounded_size ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } emit_insn ( gen_blockage ( ) ) ; dump_stack_clash_frame_info ( PROBE_LOOP , size != rounded_size ) ; } if ( residual ) { HOST_WIDE_INT residual_probe_offset = guard_used_by_caller ; if ( final_adjustment_p && rounded_size != <NUM_LIT> ) min_probe_threshold = <NUM_LIT> ; else if ( final_adjustment_p && rounded_size == <NUM_LIT> ) residual_probe_offset = <NUM_LIT> ; aarch64_sub_sp ( temp1 , temp2 , residual , frame_related_p ) ; if ( residual >= min_probe_threshold ) { if ( dump_file ) fprintf ( dump_file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> <STR_LIT> , residual ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , residual_probe_offset ) ) ; emit_insn ( gen_blockage ( ) ) ; }


<s> LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , RM . getValueOr ( Reloc :: Model :: Static ) , CM . getValueOr ( CodeModel :: Model :: Tiny ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) , DefaultSubtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ;


<s> if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true ;


<s> unsigned AlignMask = TargetAlign - <NUM_LIT> ; bool DisableRedZone = MF . getFunction ( ) -> getFnAttributes ( ) . hasNoRedZoneAttr ( ) ; if ( ! DisableRedZone && FrameSize <= <NUM_LIT> && ! MFI -> hasVarSizedObjects ( ) && ! MFI -> adjustsStack ( ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) && spillsCR ( MF ) ) && ( ! ALIGN_STACK || MaxAlign <= TargetAlign ) ) { MFI -> setStackSize ( <NUM_LIT> ) ; return ; } unsigned maxCallFrameSize = MFI -> getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getMinCallFrameSize ( Subtarget . is<ISA_LIT>64 ( ) , Subtarget . isDarwinABI ( ) ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI -> hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; MFI -> setMaxCallFrameSize ( maxCallFrameSize ) ;


<s> unsigned StElts = MemVT . getSizeInBits ( ) / VT . getScalarSizeInBits ( ) ; APInt DemandedElts = APInt :: getLowBitsSet ( VT . getVectorNumElements ( ) , StElts ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . SimplifyDemandedVectorElts ( StoredVal , DemandedElts , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ;


<s> static unsigned RegistersByIndex [ ] = {


<s> case GE : return <STR_LIT> ; case LT : return <STR_LIT> ; default : gcc_unreachable ( ) ;


<s> machine_mode mode = GET_MODE ( dest ) ; rtx ptrue = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; if ( ! register_operand ( src , mode ) && ! register_operand ( dest , mode ) ) { rtx tmp = gen_reg_rtx ( mode ) ; if ( MEM_P ( src ) ) aarch64_emit_sve_pred_move ( tmp , ptrue , src ) ; else emit_move_insn ( tmp , src ) ;


<s> return function_instance ( <STR_LIT> , bases :: read_vl , shapes :: read_vl , none_ops [ <NUM_LIT> ] , PRED_TYPE_none , & p_none_void_ops ) ;


<s> case LTU : case GT : case GTU : inverted_p = ! inverted_p ; case LE : case LEU : case GE : case GEU : branch [ ! inverted_p ] = LARCH_BRANCH ( <STR_LIT> , <STR_LIT> ) ; branch [ inverted_p ] = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } } else { switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case LE : case LEU : case GT : case GTU : case LT : case LTU : case GE : case GEU : branch [ ! inverted_p ] = LARCH_BRANCH ( <STR_LIT> , <STR_LIT> ) ; branch [ inverted_p ] = LARCH_BRANCH ( <STR_LIT> , <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } } } else { switch ( GET_CODE ( operands [ <NUM_LIT> ] ) ) { case LEU : case GTU : case LTU : case GEU : case LE : case GT : case LT : case GE : branch [ ! inverted_p ] = LARCH_BRANCH ( <STR_LIT> , <STR_LIT> ) ; branch [ inverted_p ] = LARCH_BRANCH ( <STR_LIT> , <STR_LIT> ) ; break ; default :


<s> const MCSymbol * Sym = Mang -> getSymbol ( GV ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; return MCBinaryExpr :: CreateAdd ( Res , Four , getContext ( ) ) ; } return TargetLoweringObjectFileMachO ::

getTTypeGlobalReference ( GV , Mang , MMI , Encoding , Streamer ) ;


<s> addPass ( create<ISA_LIT>InsertWaitcntsPass ( ) ) ; addPass ( create<ISA_LIT>ShrinkInstructionsPass ( ) ) ; addPass ( create<ISA_LIT>ModeRegisterPass ( ) ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & <ISA_LIT>InsertHardClausesID ) ; addPass ( & <ISA_LIT>RemoveShortExecBranchesID ) ; addPass ( & <ISA_LIT>InsertSkipsPassID ) ; addPass ( & <ISA_LIT>PreEmitPeepholeID ) ; addPass ( & PostRAHazardRecognizerID ) ;


<s> Header . amd_machine_version_stepping = Version . Stepping ; Header . kernel_code_entry_byte_offset = sizeof ( Header ) ; Header . wavefront_size = <NUM_LIT> ; Header . call_convention = - <NUM_LIT> ; Header . kernarg_segment_alignment = <NUM_LIT> ; Header . group_segment_alignment = <NUM_LIT> ;

Header . private_segment_alignment = <NUM_LIT> ;


<s> AddDefaultPred ( BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> } case <STR_LIT> : { unsigned LabelId = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPIdx = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; EmitAlignment ( <NUM_LIT> ) ; OutStreamer . EmitLabel ( GetCPISymbol ( LabelId ) ) ; const MachineConstantPoolEntry & MCPE = MCP -> getConstants ( ) [ CPIdx ] ; if ( MCPE . isMachineConstantPoolEntry ( ) ) EmitMachineConstantPoolValue ( MCPE . Val . MachineCPVal ) ; else EmitGlobalConstant ( MCPE . Val . ConstVal ) ; return ; } case <STR_LIT> : { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ImmVal = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned SOImmValV1 = <STR_LIT> ( ImmVal ) ; unsigned SOImmValV2 = <STR_LIT> ( ImmVal ) ; { MCInst TmpInst ; TmpInst . setOpcode ( <STR_LIT> ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( DstReg ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( SOImmValV1 ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; OutStreamer . EmitInstruction ( TmpInst ) ; } { MCInst TmpInst ;


<s> <ISA_LIT>PLT :: <ISA_LIT>PLT ( LDSection & pSection , const LinkerConfig & pConfig , int got_size ) : PLT ( pSection ) , m_Config ( pConfig ) { assert ( LinkerConfig :: DynObj == m_Config . codeGenType ( ) || LinkerConfig :: Exec == m_Config . codeGenType ( ) || LinkerConfig :: Binary == m_Config . codeGenType ( ) ) ; if ( got_size == <NUM_LIT> ) { if ( LinkerConfig :: DynObj == m_Config . codeGenType ( ) ) { m_PLT0 = x86_32_dyn_plt0 ; m_PLT1 = x86_32_dyn_plt1 ; m_PLT0Size = sizeof ( x86_32_dyn_plt0 ) ; m_PLT1Size = sizeof ( x86_32_dyn_plt1 ) ; new <ISA_LIT>_32DynPLT0 ( * m_pSectionData ) ; } else { m_PLT0 = x86_32_exec_plt0 ; m_PLT1 = x86_32_exec_plt1 ; m_PLT0Size = sizeof ( x86_32_exec_plt0 ) ; m_PLT1Size = sizeof ( x86_32_exec_plt1 ) ; new <ISA_LIT>_32ExecPLT0 ( * m_pSectionData ) ; } } else { assert ( got_size == <NUM_LIT> ) ; m_PLT0 = x86_64_plt0 ; m_PLT1 = x86_64_plt1 ; m_PLT0Size = sizeof ( x86_64_plt0 ) ; m_PLT1Size = sizeof ( x86_64_plt1 ) ; new <ISA_LIT>_64PLT0 ( * m_pSectionData ) ;


<s> unsigned IndexSize = DL . getPointerSizeInBits ( ) ; GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ; if ( IndexSize < <NUM_LIT> || ! GEP ) return IndexSize ; unsigned NumOfVarIndices = <NUM_LIT> ; Value * Ptrs = GEP -> getPointerOperand ( ) ; if ( Ptrs -> getType ( ) -> isVectorTy ( ) && ! getSplatValue ( Ptrs ) ) return IndexSize ; for ( unsigned i = <NUM_LIT> ; i < GEP -> getNumOperands ( ) ; ++ i ) { if ( isa < Constant > ( GEP -> getOperand ( i ) ) ) continue ; Type * IndxTy = GEP -> getOperand ( i ) -> getType ( ) ; if ( auto * IndexVTy = dyn_cast < VectorType > ( IndxTy ) ) IndxTy = IndexVTy -> getElementType ( ) ; if ( ( IndxTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> && ! isa < SExtInst > ( GEP -> getOperand ( i ) ) ) || ++ NumOfVarIndices > <NUM_LIT> ) return IndexSize ; } return ( unsigned ) <NUM_LIT> ; } ; unsigned IndexSize = ( ST -> hasAVX512 ( ) && VF >= <NUM_LIT> ) ? getIndexSizeInBits ( Ptr , DL ) : DL . getPointerSizeInBits ( ) ;

Type * IndexVTy = VectorType :: get ( IntegerType :: get ( SrcVTy -> getContext ( ) , IndexSize ) , VF ) ;


<s> void relaxInstruction ( const MCInst & Inst , MCInst & Res ) const { assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else instantiateCondBranch ( MBB , DL , TBB , Cond ) ; return <NUM_LIT> ; } instantiateCondBranch ( MBB , DL , TBB , Cond ) ;

BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> if ( CurFile != <STR_LIT> ) OS . EmitRawText ( StringRef ( <STR_LIT> ) ) ; OS . EmitRawText ( <STR_LIT> + Twine ( FilePath ) + <STR_LIT> ) ;


<s> call = get_call_rtx_from ( insn ) ; symbol = XEXP ( XEXP ( call , <NUM_LIT> ) , <NUM_LIT> ) ;

if ( GET_CODE ( symbol ) != SYMBOL_REF ) return false ;


<s> if ( arg . aggregate_type_p ( ) ) size = int_size_in_bytes ( arg . type ) ; if ( size < <NUM_LIT> ) return true ; if ( aarch64_vfp_is_call_or_return_candidate ( arg . mode , arg . type , & dummymode , & nregs , NULL , ! pcum || pcum -> silent_p ) ) return false ; return size > <NUM_LIT> * UNITS_PER_WORD ;


<s> void <ISA_LIT>InstPrinter :: printSVELogicalImm ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { typedef std :: make_signed_t < T > SignedT ; typedef std :: make_unsigned_t < T > UnsignedT ; uint64_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ; UnsignedT PrintVal = <STR_LIT> ( Val , <NUM_LIT> ) ; if ( ( int16_t ) PrintVal == ( SignedT ) PrintVal ) printImmSVE ( ( T ) PrintVal , O ) ;

else if ( ( uint16_t ) PrintVal == PrintVal ) printImmSVE ( PrintVal , O ) ;


return ( __m64 ) __builtin_arm_wmaddux ( ( __v4hi ) a , ( __v4hi ) b ) ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> savePacket ( ) ; Packet . clear ( ) ; TotalPackets ++ ; startNewCycle = true ; } if ( ! SU -> getInstr ( ) -> isPseudo ( ) ) { ResourcesModel -> reserveResources ( * SU -> getInstr ( ) ) ; Packet . push_back ( SU ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TotalPackets << <STR_LIT> ) ;

for ( unsigned i = <NUM_LIT> , e = Packet . size ( ) ; i != e ; ++ i ) {


<s> I != E ; ++ I ) { if ( Offset < I -> Offset ) { MemOps . insert ( I , MemOpQueueEntry ( Offset , Position , MBBI ) ) ; NumMemOps ++ ; Advance = true ; break ; } else if ( Offset == I -> Offset ) { break ; } } } } } } if ( Advance ) { ++ Position ; ++ MBBI ; } else TryMerge = true ; if ( TryMerge ) { if ( NumMemOps > <NUM_LIT> ) { AdvanceRS ( MBB , MemOps ) ; unsigned Scratch = RS -> FindUnusedReg ( & <STR_LIT> ) ; RS -> forward ( prior ( MBBI ) ) ; Merges . clear ( ) ; MergeLDR_STR ( MBB , <NUM_LIT> , CurrBase , CurrOpc , CurrSize , CurrPred , CurrPredReg , Scratch , MemOps , Merges ) ; for ( unsigned i = <NUM_LIT> , e = Merges . size ( ) ; i < e ; ++ i ) if ( MergeBaseUpdateLSMultiple ( MBB , Merges [ i ] , Advance , MBBI ) ) ++ NumMerges ; NumMerges += Merges . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumMemOps ; ++ i ) if ( ! MemOps [ i ] . Merged ) if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ i ] . MBBI , TII , Advance , MBBI ) ) ++ NumMerges ; RS -> skipTo ( prior ( MBBI ) ) ; } else if ( NumMemOps == <NUM_LIT> ) { if ( MergeBaseUpdateLoadStore ( MBB , MemOps [ <NUM_LIT> ] . MBBI , TII , Advance , MBBI ) ) { ++ NumMerges ; RS -> forward ( prior ( MBBI ) ) ; } } CurrBase = <NUM_LIT> ;


<s> for ( const Function & F : M ) { const <ISA_LIT>Subtarget & STI = TM . getSubtarget < <ISA_LIT>Subtarget > ( F ) ; unsigned FDir = STI . getCPUDirective ( ) ; Directive = Directive > FDir ? FDir : STI . getCPUDirective ( ) ; if ( STI . hasMFOCRF ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( STI . hasAltivec ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; if ( STI . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; } assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; assert ( Directive < array_lengthof ( CPUDirectives ) && <STR_LIT> ) ; <ISA_LIT>TargetStreamer & TStreamer = * static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) ; TStreamer . emitMachine ( CPUDirectives [ Directive ] ) ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer -> SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { OutStreamer -> SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_SYMBOL_STUBS | MachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ;


<s> if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ;

for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) OW -> Write32 ( <NUM_LIT> ) ;


<s> if ( fkind != SUBROUTINE ) { expand_interrupt_handler_epilogue ( spreg , fkind ) ; return ; } do_unlink ( spreg , get_frame_size ( ) , false ) ; expand_epilogue_reg_restore ( spreg , false , false ) ;


<s> static <STR_LIT> getPredicate ( const MachineInstr * MI , unsigned & PredReg ) { unsigned Opc = MI -> getOpcode ( ) ;

if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) return <STR_LIT> ;


<s> switch ( Ordering ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicOrdering :: Monotonic : return <STR_LIT> ; case AtomicOrdering :: Acquire : return <STR_LIT> ; case AtomicOrdering :: Release : return <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return <STR_LIT> ;

case AtomicOrdering :: SequentiallyConsistent :


<s> insn = emit_insn ( pat ) ; REG_NOTES ( insn ) = reg_notes ; if ( frame_related ) { rtx real = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , imm_rtx ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;

add_reg_note ( insn , REG_CFA_ADJUST_CFA , real ) ;


<s> const TargetRegisterClass * MandarinRegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const {


<s> return type == RAInfo :: LocType :: Register ;


<s> static rtx cris_function_incoming_arg ( cumulative_args_t ca , const function_arg_info & arg ) { return cris_function_arg_1 ( ca , arg , true ) ;


<s> } else { if ( DestReg != BaseReg ) DstNotEqBase = true ; NumBits = <NUM_LIT> ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; isTwoAddr = true ; } unsigned NumMIs = calcNumMI ( Opc , ExtraOpc , Bytes , NumBits , Scale ) ; unsigned Threshold = ( DestReg == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( NumMIs > Threshold ) { emitThumbRegPlusImmInReg ( MBB , MBBI , DestReg , BaseReg , NumBytes , true , TII , MRI , dl ) ; return ; } if ( DstNotEqBase ) { if ( MRI . isLowRegister ( DestReg ) && MRI . isLowRegister ( BaseReg ) ) { unsigned Chunk = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ; BuildMI ( MBB , MBBI , dl , TII . get ( isSub ? <STR_LIT> : <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) . addImm ( ThisVal ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg , RegState :: Kill ) ; } BaseReg = DestReg ; } unsigned Chunk = ( ( <NUM_LIT> << NumBits ) - <NUM_LIT> ) * Scale ; while ( Bytes ) { unsigned ThisVal = ( Bytes > Chunk ) ? Chunk : Bytes ; Bytes -= ThisVal ;


<s> return ( CONST_INT_P ( x ) ? <NUM_LIT> : GET_CODE ( x ) == PLUS ? <NUM_LIT> : <NUM_LIT> ) ;


<s> auto Src = getValueSource ( C . Origin -> getOperand ( <NUM_LIT> ) ) ; AllocOperands AO = getRangeForAllocation ( Src ) ; if ( AO != AllocOperands ( ) ) ConstantCasts . push_back ( pair < AllocOperands , ConstantCast > ( AO , C ) ) ; }


<s> unsigned Opc = <STR_LIT> ( ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; copy0MBB -> addSuccessor ( sinkMBB ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ;


<s> tree id ; if ( deferred_plabels == <NUM_LIT> ) deferred_plabels = ( struct deferred_plabel * ) ggc_alloc ( sizeof ( struct deferred_plabel ) ) ; else deferred_plabels = ( struct deferred_plabel * ) ggc_realloc ( deferred_plabels , ( ( n_deferred_plabels + <NUM_LIT> ) * sizeof ( struct deferred_plabel ) ) ) ; i = n_deferred_plabels ++ ; deferred_plabels [ i ] . internal_label = gen_label_rtx ( ) ; deferred_plabels [ i ] . symbol = symbol ; id = maybe_get_identifier ( targetm . strip_name_encoding ( fname ) ) ;


<s> FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ;


<s> return ( __m512i ) __builtin_ia32_prorq512_mask ( ( __v8di ) __A , __B , ( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> const MachineMemOperand * MMO = * MI . memoperands_begin ( ) ; return <STR_LIT> ( MMO ) ;


<s> <ISA_LIT>XCOFFObjectWriter :: <ISA_LIT>XCOFFObjectWriter ( bool Is64Bit ) : MCXCOFFObjectTargetWriter ( Is64Bit ) {


<s> gcc_assert ( ptr -> arch < PROCESSOR_max ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , ptr -> arch , processor_names [ ptr -> arch ] ) ; gcc_assert ( ptr -> tune < PROCESSOR_max ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , ptr -> tune , processor_names [ ptr -> tune ] ) ; fprintf ( file , <STR_LIT> , indent , <STR_LIT> , ptr -> branch_cost ) ;


<s> Type * VecWidth = VecInst -> getType ( ) ; ( void ) VecWidth ; assert ( VecWidth -> isVectorTy ( ) && DL . getTypeSizeInBits ( VecWidth ) >= DL . getTypeSizeInBits ( SubVecTy ) * NumSubVectors && <STR_LIT> ) ; if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( VecInst ) ) { Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Indices [ i ] , SubVecTy -> getNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ;


<s> const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ;

return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & , EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( DL ) ; return VT . changeVectorElementTypeToInteger ( ) ;


<s> addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; } computeRegisterProperties ( ) ; setShiftAmountType ( <STR_LIT> ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setSchedulingPreference ( Sched :: RegPressure ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ;


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , isLittle ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DL ( computeDataLayout ( Subtarget ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameLowering ( Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( Subtarget ) ) { initAsmInfo ( ) ;


<s> static NodeType * getEntryNode ( const SpillCostAnalysisGraph & G ) { return G . getRoot ( ) ;


<s> extern __inline __m512 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm512_setzero ( void ) { return _mm512_setzero_ps ( ) ;


<s> if ( GET_CODE ( op5 ) == REG ) regs ++ ; if ( regs != <NUM_LIT> ) return <NUM_LIT> ;

if ( GET_CODE ( op0 ) == REG && ( ( GET_CODE ( op4 ) == MEM && reg_mentioned_p ( op0 , XEXP ( op4 , <NUM_LIT> ) ) ) || ( GET_CODE ( op5 ) == MEM && reg_mentioned_p ( op0 , XEXP ( op5 , <NUM_LIT> ) ) ) ) ) return <NUM_LIT> ;


<s> return Def -> getOpcode ( ) == <STR_LIT> ? Def -> getOperand ( <NUM_LIT> ) . getReg ( ) : Register ( ) ;


<s> bool <ISA_LIT>TargetLowering :: isZExtFree ( Type * SrcTy , Type * DstTy ) const { if ( ! SrcTy -> isIntegerTy ( ) || ! DstTy -> isIntegerTy ( ) ) return false ;

return SrcTy -> getPrimitiveSizeInBits ( ) < DstTy -> getPrimitiveSizeInBits ( ) ;


<s> if ( ! ( Subtarget -> hasFMA ( ) || Subtarget -> hasFMA4 ( ) || Subtarget -> hasAVX512 ( ) ) ) return false ; VT = VT . getScalarType ( ) ;

if ( ! VT . isSimple ( ) ) return false ;


<s> else if ( regno == REG_VOLATILE ) rws_insn [ <NUM_LIT> ] = <NUM_LIT> ;


<s> int nregs = <NUM_LIT> ; int regno ; if ( ! TARGET_64BIT_MS_ABI ) return <NUM_LIT> ;

for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true , true ) ) nregs ++ ;


<s> bool <ISA_LIT>LowerRefTypesIntPtrConv :: isRefType ( Type * T ) { return <ISA_LIT>TargetLowering :: isFuncrefType ( T ) || <ISA_LIT>TargetLowering :: isExternrefType ( T ) ;


<s> const Module * M = MMI -> getModule ( ) ; for ( const GlobalVariable & Global : M -> globals ( ) ) { if ( ! Global . hasInitializer ( ) && Global . hasExternalLinkage ( ) ) continue ; SmallVector < DIGlobalVariableExpression * , <NUM_LIT> > GVs ; Global . getDebugInfo ( GVs ) ; uint32_t GVTypeId = <NUM_LIT> ; for ( auto * GVE : GVs ) { visitTypeEntry ( GVE -> getVariable ( ) -> getType ( ) , GVTypeId ) ; break ; } auto Linkage = Global . getLinkage ( ) ; if ( Linkage != GlobalValue :: InternalLinkage && ( Linkage != GlobalValue :: ExternalLinkage || ! Global . hasSection ( ) ) ) continue ; uint32_t GVarInfo = Linkage == GlobalValue :: ExternalLinkage ? <STR_LIT> : <STR_LIT> ; auto VarEntry = llvm :: make_unique < BTFKindVar > ( Global . getName ( ) , GVTypeId , GVarInfo ) ; uint32_t VarId = addType ( std :: move ( VarEntry ) ) ; std :: string SecName ; if ( Global . hasSection ( ) ) { SecName = Global . getSection ( ) . str ( ) ; } else { if ( Global . isConstant ( ) ) SecName += <STR_LIT> ; else SecName += Global . getInitializer ( ) -> isZeroValue ( ) ? <STR_LIT> : <STR_LIT> ; } if ( DataSecEntries . find ( SecName ) == DataSecEntries . end ( ) ) { DataSecEntries [ SecName ] = llvm :: make_unique < BTFKindDataSec > ( Asm , SecName ) ;


<s> return TYPE_VECTOR_OPAQUE ( type ) ;


<s> virtual void schedNoop ( bool IsTopNode ) {


<s> MachineBasicBlock :: iterator I = MBB -> getFirstTerminator ( ) ; if ( I == MBB -> end ( ) ) return nullptr ; if ( I -> getOpcode ( ) != <STR_LIT> ) return nullptr ; for ( auto SuccBB : MBB -> successors ( ) ) if ( SuccBB -> isLiveIn ( <STR_LIT> ) ) return nullptr ; for ( MachineBasicBlock :: iterator B = MBB -> begin ( ) ; I != B ; ) { -- I ; assert ( ! I -> isTerminator ( ) && <STR_LIT> ) ; if ( I -> readsRegister ( <STR_LIT> ) ) return nullptr ; switch ( I -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShiftAmt = <STR_LIT> ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( ! I -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) << ShiftAmt >= <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } else if ( ! MRI -> use_empty ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; return nullptr ; } return & * I ; }


<s> if ( ! INT14_OK_STRICT && ( strict || ! ( reload_in_progress || reload_completed ) ) && mode != QImode && mode != HImode ) return false ; return base14_operand ( index , mode ) ; } if ( ! TARGET_DISABLE_INDEXING && ( TARGET_NO_SPACE_REGS ? REG_P ( index ) : ( base == XEXP ( x , <NUM_LIT> ) && REG_P ( index ) && ( reload_completed || ( reload_in_progress && HARD_REGISTER_P ( base ) ) || REG_POINTER ( base ) ) && ( reload_completed || ( reload_in_progress && HARD_REGISTER_P ( index ) ) || ! REG_POINTER ( index ) ) ) ) && MODE_OK_FOR_UNSCALED_INDEXING_P ( mode ) && ( strict ? STRICT_REG_OK_FOR_INDEX_P ( index ) : REG_OK_FOR_INDEX_P ( index ) ) && borx_reg_operand ( base , Pmode ) && borx_reg_operand ( index , Pmode ) ) return true ; if ( ! TARGET_DISABLE_INDEXING && GET_CODE ( index ) == MULT && MODE_OK_FOR_SCALED_INDEXING_P ( mode ) && REG_P ( XEXP ( index , <NUM_LIT> ) ) && GET_MODE ( XEXP ( index , <NUM_LIT> ) ) == Pmode && ( strict ? STRICT_REG_OK_FOR_INDEX_P ( XEXP ( index , <NUM_LIT> ) ) : REG_OK_FOR_INDEX_P ( XEXP ( index , <NUM_LIT> ) ) ) && GET_CODE ( XEXP ( index , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( index , <NUM_LIT> ) ) == ( HOST_WIDE_INT ) GET_MODE_SIZE ( mode ) && borx_reg_operand ( base , Pmode ) ) return true ; return false ; } if ( GET_CODE ( x ) == LO_SUM ) { rtx y = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( y ) == SUBREG ) y = SUBREG_REG ( y ) ; if ( REG_P ( y ) && ( strict ? STRICT_REG_OK_FOR_BASE_P ( y ) : REG_OK_FOR_BASE_P ( y ) ) ) { if ( mode == Pmode && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == UNSPEC ) return true ;


<s> bool CallingConvSupportsAllImplicits = ( CC != CallingConv :: <ISA_LIT>_Gfx ) ; if ( <STR_LIT> ( F -> getCallingConv ( ) ) ) { indicatePessimisticFixpoint ( ) ; return ; } for ( StringRef Attr : ImplicitAttrNames ) { if ( F -> hasFnAttribute ( Attr ) ) Attributes . insert ( Attr ) ; } if ( CallingConvSupportsAllImplicits && F -> hasAddressTaken ( nullptr , true , true , true ) ) { for ( StringRef AttrName : ImplicitAttrNames ) {


<s> } if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return ; if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ; O << <STR_LIT> ; if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isGlobal ( ) || MI -> getOperand ( opNum + <NUM_LIT> ) . isCPI ( ) ) { O << <STR_LIT> ; printOperand ( MI , opNum + <NUM_LIT> , O ) ; O << <STR_LIT> ; } else { printOperand ( MI , opNum + <NUM_LIT> , O ) ; }


<s> } if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && isCalleeSavedRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , CSRegs ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return true ;


<s> return ( int8x16_t ) __builtin_neon_vqabsv16qi ( __a ) ;


<s> return ( uint64x1_t ) __builtin_neon_vdup_lanedi ( ( int64x1_t ) __a , __b ) ;


<s> if ( cond ) pattern = gen_rtx_COND_EXEC ( VOIDmode , copy_rtx ( cond ) , pattern ) ; emit_insn ( pattern ) ;


<s> switch ( x ) { case S_Special : return SlotParser :: Special ; case S_Load : return SlotParser :: Load ;

case S_Scalar : return SlotParser :: Scalar ;


<s> MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <NUM_LIT> ) ;


<s> else abi = <STR_LIT> ; return build_string_literal ( strlen ( abi ) + <NUM_LIT> , abi ) ;