<s> return false ; } const ArrayRef < MCPhysReg > GPR32ArgRegs = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const ArrayRef < MCPhysReg > FGR32ArgRegs = { <STR_LIT> , <STR_LIT> } ; const ArrayRef < MCPhysReg > AFGR64ArgRegs = { <STR_LIT> , <STR_LIT> } ; ArrayRef < MCPhysReg > :: iterator NextGPR32 = GPR32ArgRegs . begin ( ) ; ArrayRef < MCPhysReg > :: iterator NextFGR32 = FGR32ArgRegs . begin ( ) ; ArrayRef < MCPhysReg > :: iterator NextAFGR64 = AFGR64ArgRegs . begin ( ) ; struct AllocatedReg { const TargetRegisterClass * RC ; unsigned Reg ; AllocatedReg ( const TargetRegisterClass * RC , unsigned Reg ) : RC ( RC ) , Reg ( Reg ) { } } ; SmallVector < AllocatedReg , <NUM_LIT> > Allocation ; unsigned Idx = <NUM_LIT> ; for ( const auto & FormalArg : F -> args ( ) ) { if ( F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: InReg ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: StructRet ) || F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ByVal ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Type * ArgTy = FormalArg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; DEBUG ( dbgs ( ) << <STR_LIT> << ( Idx - <NUM_LIT> ) << <STR_LIT> << ArgVT . getEVTString ( ) << <STR_LIT> ) ; if ( ! ArgVT . isSimple ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: SExt ) && ! F -> getAttributes ( ) . hasAttribute ( Idx , Attribute :: ZExt ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( NextGPR32 == GPR32ArgRegs . end ( ) ) {


<s> const MCExpr * <ISA_LIT>TargetLowering :: LowerCustomJumpTableEntry ( const MachineJumpTableInfo * MJTI , const MachineBasicBlock * MBB , unsigned uid , MCContext & Ctx ) const {

return MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , MCSymbolRefExpr :: VK_GOTOFF , Ctx ) ;


<s> return ( __m512i ) __builtin_ia32_loaddqusi512_mask ( ( const __v16si * ) __P , ( __v16si ) _mm512_setzero_si512 ( ) , ( __mmask16 ) __U ) ;


<s> <ISA_LIT>MCExpr :: <ISA_LIT>MCExpr ( MCExpr const * Expr ) : Expr ( Expr ) , MustNotExtend ( false ) , MustExtend ( false ) , S27_2_reloc ( false ) , SignMismatch ( false ) {


<s> O << <STR_LIT> << formatDec ( Imm & <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { O << ',' << formatDec ( ( Imm >> ( <NUM_LIT> * i ) ) & <NUM_LIT> ) ; }


if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ;


<s> riscv_builtin_decls [ i ] = add_builtin_function ( d -> name , type , i , BUILT_IN_MD , NULL , NULL ) ; riscv_builtin_decl_index [ d -> icode ] = i ; }


<s> return false ; } if ( Addr . getOpcode ( ) != <STR_LIT> && Addr . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( Addr ) ) { if ( Addr . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Addr ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } else { Base = Addr ; } Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { int32_t RHSC = RHS -> getSExtValue ( ) ; if ( Addr . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ;

if ( ! isInt < <NUM_LIT> > ( RHSC ) ) return false ;


<s> void <ISA_LIT>CompilationCallback ( ) { assert ( <NUM_LIT> && <STR_LIT> ) ; abort ( ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , <ISA_LIT>Subtarget ( TT , getFeatureBits ( ) ) , InstrInfo ( * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) , FMA ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , DX10Clamp ( false ) , HasVertexCache ( false ) , <ISA_LIT>ALUInst ( false ) , FP64 ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , Gen ( <ISA_LIT> ) , TLInfo ( TM , initializeSubtargetDependencies ( TT , GPU , FS ) ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) {


<s> unsigned SPReg = <STR_LIT> ; if ( StackSize ) SPReg = MRI . createVirtualRegister ( PtrRC ) ; const char * ES = <STR_LIT> ; auto * SPSymbol = MF . createExternalSymbolName ( ES ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addExternalSymbol ( SPSymbol , <STR_LIT> ) ; bool HasBP = hasBP ( MF ) ; if ( HasBP ) { auto FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned BasePtr = MRI . createVirtualRegister ( PtrRC ) ; FI -> setBasePointerVreg ( BasePtr ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , BasePtr ) . addReg ( SPReg ) ; } if ( StackSize ) { unsigned OffsetReg = MRI . createVirtualRegister ( PtrRC ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( StackSize ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SPReg ) . addReg ( OffsetReg ) ; } if ( HasBP ) { unsigned BitmaskReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned Alignment = MFI . getMaxAlignment ( ) ;

assert ( ( <NUM_LIT> << countTrailingZeros ( Alignment ) ) == Alignment && <STR_LIT> ) ;


<s> const unsigned long __mask = <NUM_LIT> ; unsigned long __m = __M ; unsigned long __c , __t ; unsigned long __p ; __p = <NUM_LIT> - __builtin_popcountl ( __M ) ; while ( __m != <NUM_LIT> ) {


<s> mp -> value = fix -> value ; mp -> refcount = <NUM_LIT> ; mp -> min_address = - <NUM_LIT> ; if ( max_mp == NULL ) { mp -> max_address = max_address ; mp -> next = NULL ; mp -> prev = minipool_vector_tail ; if ( mp -> prev == NULL ) { minipool_vector_head = mp ; minipool_vector_label = gen_label_rtx ( ) ; } else mp -> prev -> next = mp ; minipool_vector_tail = mp ; } else { if ( max_address > max_mp -> max_address - mp -> fix_size ) mp -> max_address = max_mp -> max_address - mp -> fix_size ; else mp -> max_address = max_address ; mp -> next = max_mp ; mp -> prev = max_mp -> prev ; max_mp -> prev = mp ; if ( mp -> prev != NULL ) mp -> prev -> next = mp ;


<s> if ( ! isInt < <NUM_LIT> > ( IntVal ) && ! isUInt < <NUM_LIT> > ( IntVal ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( Negate ) IntVal *= - <NUM_LIT> ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IntVal , S ) ) ; return MatchOperand_Success ; } case AsmToken :: Real : { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; int64_t IntVal ; if ( getParser ( ) . parseAbsoluteExpression ( IntVal ) ) return MatchOperand_ParseFail ; APFloat F ( ( float ) BitsToDouble ( IntVal ) ) ; if ( Negate ) F . changeSign ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( F . bitcastToAPInt ( ) . getZExtValue ( ) , S ) ) ; return MatchOperand_Success ; } case AsmToken :: Identifier : { SMLoc S , E ; unsigned RegNo ; if ( ! ParseRegister ( RegNo , S , E ) ) { unsigned Modifiers = <NUM_LIT> ; if ( Negate ) Modifiers |= <NUM_LIT> ; if ( Abs ) { if ( getLexer ( ) . getKind ( ) != AsmToken :: Pipe ) return MatchOperand_ParseFail ;


<s> return ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) && ( ( offset ) & <NUM_LIT> ) == <NUM_LIT> ) ;


<s> char * tmpName = new char [ name . size ( ) + <NUM_LIT> ] ; memcpy ( tmpName , name . c_str ( ) , name . size ( ) + <NUM_LIT> ) ; return tmpName ;


<s> static __inline__ float __fsqrts ( float x ) { float r ; __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) ) ; return r ;


<s> return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail : { FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getToken ( ) , FBS ) ; return Error ( IDLoc , <STR_LIT> + Suggestion , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ;


<s> if ( isVerbose ( ) ) { MCSectionELF * CommentSection = Context . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ; OutStreamer -> SwitchSection ( CommentSection ) ; if ( STM . getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) { OutStreamer -> emitRawComment ( <STR_LIT> , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . CodeLen ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . NumSGPR ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . NumVGPR ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . FloatMode ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . IEEEMode ) , false ) ; OutStreamer -> emitRawComment ( <STR_LIT> + Twine ( KernelInfo . ScratchSize ) , false ) ; } else { <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; OutStreamer -> emitRawComment ( Twine ( <STR_LIT> + Twine ( MFI -> StackSize ) ) ) ; } }


<s> const TargetRegisterClass * <ISA_LIT>TargetLowering :: getRepRegClassFor ( MVT VT ) const {

if ( VT == <STR_LIT> ) return & <STR_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: SafeInForbiddenSlot ( const MachineInstr & MI ) const {

if ( MI . isInlineAsm ( ) ) return false ;


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const {

Streamer . visitUsedExpr ( * getSubExpr ( ) ) ;


<s> const int align = INTVAL ( align_rtx ) ; rtx dst_reg ; tree dst_expr ; if ( ! CONST_INT_P ( bytes_rtx ) || INTVAL ( bytes_rtx ) <= <NUM_LIT> ) return <NUM_LIT> ; dst_reg = copy_addr_to_reg ( XEXP ( dst , <NUM_LIT> ) ) ;

if ( align >= <NUM_LIT> ) expand_block_set_4 ( dst , dst_reg , value_rtx , bytes_rtx ) ;


<s> unsigned <ISA_LIT>InstrInfo :: RemoveBranch ( MachineBasicBlock & MBB ) const { if ( MBB . empty ( ) ) return <NUM_LIT> ; unsigned NumRemoved = <NUM_LIT> ; auto I = MBB . end ( ) ; do {


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _enqcmd ( void * __P , const void * __Q ) {


<s> Arg . Ty = Arg . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Args . push_back ( Arg ) ; } CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( CallingConv :: <ISA_LIT>_AAPCS_VFP , VT . getTypeForEVT ( * DAG . getContext ( ) ) , ES , std :: move ( Args ) ) ;


<s> return ( __m512d ) __builtin_ia32_cvtdq2pd512_mask ( ( __v8si ) __A , ( __v8df ) _mm512_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFastFDIV ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; bool Unsafe = DAG . getTarget ( ) . Options . UnsafeFPMath ; if ( const ConstantFPSDNode * CLHS = dyn_cast < ConstantFPSDNode > ( LHS ) ) { if ( ( Unsafe || ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) ) && CLHS -> isExactlyValue ( <NUM_LIT> ) ) { if ( RHS . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SL , VT , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; } } if ( Unsafe ) {

SDValue Recip = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ;


<s> int NVOpcode = <STR_LIT> ( MI . getOpcode ( ) ) ; if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI . getOpcode ( ) ) { default : report_fatal_error ( std :: string ( <STR_LIT> ) + std :: to_string ( MI . getOpcode ( ) ) ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> <ISA_LIT>SERegisterInfo :: <ISA_LIT>SERegisterInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>RegisterInfo ( ST ) {


<s> if ( isPositionIndependent ( ) || Subtarget -> isROPI ( ) ) Expr = MCBinaryExpr :: createSub ( Expr , MCSymbolRefExpr :: create ( JTISymbol , OutContext ) , OutContext ) ; else if ( AFI -> isThumbFunction ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; OutStreamer -> EmitValue ( Expr , <NUM_LIT> ) ; } OutStreamer -> EmitDataRegion ( MCDR_DataRegionEnd ) ;


<s> CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; int64_t Offset = cast < BlockAddressSDNode > ( Op ) -> getOffset ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( ) , Offset , OpFlags ) ; if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;

else Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> if ( ! RM . hasValue ( ) ) { if ( TT . isOSDarwin ( ) ) return Reloc :: DynamicNoPIC ; return Reloc :: Static ; } return * RM ;


<s> void MetadataStreamer :: emitKernelArgs ( const Function & Func ) { for ( auto & Arg : Func . args ( ) ) emitKernelArg ( Arg ) ; if ( ! Func . getParent ( ) -> getNamedMetadata ( <STR_LIT> ) ) return ; auto & DL = Func . getParent ( ) -> getDataLayout ( ) ; auto Int64Ty = Type :: getInt64Ty ( Func . getContext ( ) ) ;

emitKernelArg ( DL , Int64Ty , ValueKind :: HiddenGlobalOffsetX ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getBaseRegister ( const MachineFunction & MF ) const {

const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: CreateReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: CreateImm ( MO . getImm ( ) ) ; break ;

case MachineOperand :: MO_MachineBasicBlock :


<s> } } for ( auto * T : Truncs ) { if ( T -> hasOneUse ( ) && ! isa < StoreInst > ( * T -> user_begin ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * T << <STR_LIT> ) ; return true ; } } for ( auto * E : Exts ) { if ( ! E -> hasOneUse ( ) || cast < Instruction > ( * E -> user_begin ( ) ) -> getOpcode ( ) != Instruction :: Mul ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * E << <STR_LIT> ) ;


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) : FastISel ( FuncInfo , LibInfo ) , TM ( FuncInfo . MF -> getTarget ( ) ) , <ISA_LIT>SubTarget ( & FuncInfo . MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) , Subtarget ( & FuncInfo . MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ) , <ISA_LIT>FuncInfo ( FuncInfo . MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ) , TII ( * Subtarget -> getInstrInfo ( ) ) , TLI ( * Subtarget -> getTargetLowering ( ) ) , Context ( & FuncInfo . Fn -> getContext ( ) ) {


<s> } for ( unsigned i = MaxWorkGroupVGPRCount ; i < NumVGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchWaveOffsetReg ) ; } unsigned ScratchRSrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ScratchRSrcReg != <STR_LIT> ) { reserveRegisterTuples ( Reserved , ScratchRSrcReg ) ; assert ( ! isSubRegister ( ScratchRSrcReg , ScratchWaveOffsetReg ) ) ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . debuggerReserveRegs ( ) ) { unsigned ReservedVGPRFirst = MaxWorkGroupVGPRCount - MFI -> getDebuggerReservedVGPRCount ( ) ; for ( unsigned i = ReservedVGPRFirst ; i < MaxWorkGroupVGPRCount ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } } return Reserved ;


<s> assert ( ( NumOps == <ISA_LIT>AddrNumOperands + <NUM_LIT> || NumOps == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI -> getOperand ( NumOps - <NUM_LIT> ) ) ; bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( ! KillsSrc && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) { duplicateToTop ( Reg , <NUM_LIT> , I ) ; } else { moveToTop ( Reg , I ) ; } MI -> RemoveOperand ( NumOps - <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ;

if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) {


<s> ( void ) MO ; assert ( MO . isReg ( ) && <STR_LIT> ) ; if ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> ) { O << <STR_LIT> ; } else { assert ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; O << <STR_LIT> ; }

unsigned OpFlags = MI -> getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) ;


<s> if ( ! SLC . getNode ( ) ) SLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; TFE = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; DLC = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Idxen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offen = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * C1 = nullptr ; SDValue N0 = Addr ; if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { C1 = cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isUInt < <NUM_LIT> > ( C1 -> getZExtValue ( ) ) ) N0 = Addr . getOperand ( <NUM_LIT> ) ; else C1 = nullptr ; } if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N3 = N0 . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; if ( N2 -> isDivergent ( ) ) { if ( N3 -> isDivergent ( ) ) { Ptr = SDValue ( buildSMovImm64 ( DL , <NUM_LIT> , <STR_LIT> ) , <NUM_LIT> ) ; VAddr = N0 ; } else { Ptr = N3 ; VAddr = N2 ; } } else { Ptr = N2 ; VAddr = N3 ; } Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else if ( N0 -> isDivergent ( ) ) {


pValue . setStringValue ( std :: string ( new_value , sizeof ( new_value ) ) ) ;


<s> unsigned Opcode = N -> getOpcode ( ) ; assert ( ( <STR_LIT> == Opcode || <STR_LIT> == Opcode || <STR_LIT> == Opcode ) && <STR_LIT> ) ; bool LogicalShift = <STR_LIT> == Opcode || <STR_LIT> == Opcode ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; unsigned NumBitsPerElt = VT . getScalarSizeInBits ( ) ; assert ( VT == N0 . getValueType ( ) && ( NumBitsPerElt % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; assert ( N -> getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned ShiftVal = N -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShiftVal >= NumBitsPerElt ) { if ( LogicalShift ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; else ShiftVal = NumBitsPerElt - <NUM_LIT> ; } if ( ! ShiftVal ) return N0 ; if ( <STR_LIT> ( N0 . getNode ( ) ) ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; if ( Opcode == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> ) {

unsigned ShiftVal2 = cast < ConstantSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v16s32 , v8s64 } ) setAction ( { MemOp , Ty } , Legal ) ; if ( ! Subtarget . hasVLX ( ) ) return ; const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( auto Ty : { v4s32 , v8s32 } ) setAction ( { G_MUL , Ty } , Legal ) ;


<s> if ( TARGET_E500_DOUBLE && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return false ; x = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_ELF || TARGET_MACHO ) { bool large_toc_ok ; if ( DEFAULT_ABI == ABI_V4 && flag_pic ) return false ; large_toc_ok = ( lra_in_progress && TARGET_CMODEL != CMODEL_SMALL && small_toc_ref ( x , VOIDmode ) ) ; if ( TARGET_TOC && ! large_toc_ok ) return false ; if ( GET_MODE_NUNITS ( mode ) != <NUM_LIT> ) return false ; if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) return false ;

return CONSTANT_P ( x ) || large_toc_ok ;


<s> int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ;

if ( Base . getOpcode ( ) == <STR_LIT> ) {


<s> void <ISA_LIT>SinglePathInfo :: print ( raw_ostream & os , const Module * M ) const {


<s> return __builtin_mve_vrndnq_m_fv8hf ( __arm_vuninitializedq_f16 ( ) , __a , __p ) ;


<s> Iter Filler ; auto * Fn = MBB . getParent ( ) ; for ( MachineBasicBlock :: pred_iterator PI = SuccBB -> pred_begin ( ) , PE = SuccBB -> pred_end ( ) ; PI != PE ; ++ PI ) if ( ! examinePred ( * * PI , * SuccBB , RegDU , HasMultipleSuccs , BrMap ) ) return false ; RegDU . setUnallocatableRegs ( * Fn ) ; if ( HasMultipleSuccs ) { IM . reset ( new LoadFromStackOrConst ( ) ) ; } else { const MachineFrameInfo & MFI = Fn -> getFrameInfo ( ) ; IM . reset ( new MemDefsUses ( Fn -> getDataLayout ( ) , & MFI ) ) ; } if ( ! searchRange ( MBB , SuccBB -> begin ( ) , SuccBB -> end ( ) , RegDU , * IM , Slot , Filler ) ) return false ; insertDelayFiller ( Filler , BrMap ) ; addLiveInRegs ( Filler , * SuccBB ) ; Filler -> eraseFromParent ( ) ; return true ;


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT Ty = MRI . getType ( DstReg ) ; if ( Ty != S32 && Ty != S64 ) return false ; const bool IsDiv = MI . getOpcode ( ) == <STR_LIT> ; Register LHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register RHS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto SignBitOffset = B . buildConstant ( S32 , Ty . getSizeInBits ( ) - <NUM_LIT> ) ; auto LHSign = B . buildAShr ( Ty , LHS , SignBitOffset ) ; auto RHSign = B . buildAShr ( Ty , RHS , SignBitOffset ) ; LHS = B . buildAdd ( Ty , LHS , LHSign ) . getReg ( <NUM_LIT> ) ; RHS = B . buildAdd ( Ty , RHS , RHSign ) . getReg ( <NUM_LIT> ) ; LHS = B . buildXor ( Ty , LHS , LHSign ) . getReg ( <NUM_LIT> ) ; RHS = B . buildXor ( Ty , RHS , RHSign ) . getReg ( <NUM_LIT> ) ; Register UDivRem = MRI . createGenericVirtualRegister ( Ty ) ; if ( Ty == S32 ) legalizeUDIV_UREM32Impl ( B , UDivRem , LHS , RHS , IsDiv ) ; else legalizeUDIV_UREM64Impl ( B , UDivRem , LHS , RHS , IsDiv ) ; Register Sign ; if ( IsDiv ) Sign = B . buildXor ( Ty , LHSign , RHSign ) . getReg ( <NUM_LIT> ) ; else Sign = LHSign . getReg ( <NUM_LIT> ) ; UDivRem = B . buildXor ( Ty , UDivRem , Sign ) . getReg ( <NUM_LIT> ) ; B . buildSub ( DstReg , UDivRem , Sign ) ; MI . eraseFromParent ( ) ; return true ;


<s> MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) ) return <NUM_LIT> ; if ( ! isUncondBranchOpcode ( I -> getOpcode ( ) ) && ! isCondBranchOpcode ( I -> getOpcode ( ) ) ) return <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ;


<s> auto Not = B . buildNot ( S64 , Shr ) ; auto Tmp0 = B . buildAnd ( S64 , Src , Not ) ; auto FiftyOne = B . buildConstant ( S32 , FractBits - <NUM_LIT> ) ; auto ExpLt0 = B . buildICmp ( CmpInst :: ICMP_SLT , S1 , Exp , Zero32 ) ; auto ExpGt51 = B . buildICmp ( CmpInst :: ICMP_SGT , S1 , Exp , FiftyOne ) ; auto Tmp1 = B . buildSelect ( S64 , ExpLt0 , SignBit64 , Tmp0 ) ;

B . buildSelect ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ExpGt51 , Src , Tmp1 ) ;


<s> int getGPFI ( ) const { return GPFI ;


<s> return MemopCost + ValueSplitCost + MaskSplitCost + MaskCmpCost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , SrcVTy ) ; auto VT = TLI -> getValueType ( DL , SrcVTy ) ; int Cost = <NUM_LIT> ; if ( VT . isSimple ( ) && LT . second != VT . getSimpleVT ( ) && LT . second . getVectorNumElements ( ) == NumElem ) Cost += getShuffleCost ( TTI :: SK_PermuteTwoSrc , SrcVTy , <NUM_LIT> , nullptr ) + getShuffleCost ( TTI :: SK_PermuteTwoSrc , MaskTy , <NUM_LIT> , nullptr ) ; else if ( LT . second . getVectorNumElements ( ) > NumElem ) { auto * NewMaskTy = FixedVectorType :: get ( MaskTy -> getElementType ( ) , LT . second . getVectorNumElements ( ) ) ; Cost += getShuffleCost ( TTI :: SK_InsertSubvector , NewMaskTy , <NUM_LIT> , MaskTy ) ;


<s> int numMatch = <NUM_LIT> ; numMatch += serialPatternMatch ( curBlk ) ; numMatch += ifPatternMatch ( curBlk ) ; numMatch += loopendPatternMatch ( curBlk ) ;

numMatch += loopPatternMatch ( curBlk ) ;


<s> for ( Module :: const_iterator I = M -> getFunctionList ( ) . begin ( ) , E = M -> getFunctionList ( ) . end ( ) ; I != E ; ++ I ) { if ( I -> getName ( ) == <STR_LIT> ) { NaClReadTp = I ; break ; } } SDValue TlsReadTp ; if ( NaClReadTp == NULL ) TlsReadTp = DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) ; else TlsReadTp = DAG . getGlobalAddress ( NaClReadTp , DL , PtrVT ) ; ArgListTy Args ;

TargetLowering :: CallLoweringInfo CLI ( DAG . getEntryNode ( ) , PtrTy , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , false , true , TlsReadTp , Args , DAG , DL ) ;


<s> return true ; } switch ( Addr . getOpcode ( ) ) { case <STR_LIT> : if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { uint64_t CVal = CN -> getZExtValue ( ) ; if ( ( ( CVal << <NUM_LIT> ) >> <NUM_LIT> ) == CVal ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( N0 ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; else Base = N0 ; Disp = CurDAG -> getTargetConstant ( CVal , <STR_LIT> ) ; return true ; } }


__builtin_ia32_movntq ( ( unsigned long long * ) __P , ( unsigned long long ) __A ) ;


<s> const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; unsigned Imm = MO2 . getImm ( ) ; bool isAdd = <STR_LIT> ( Imm ) == <STR_LIT> ; bool isImm = MO1 . getReg ( ) == <NUM_LIT> ;


<s> return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; int Idx = cast < JumpTableSDNode > ( Op ) -> getIndex ( ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: PIC_ ) {

SDValue T = DAG . getTargetJumpTable ( Idx , VT , <STR_LIT> ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { return & <STR_LIT> ;


<s> Name = NewOpcode ; } size_t Dot = Name . find ( '.' ) ; StringRef Mnemonic = Name . slice ( <NUM_LIT> , Dot ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateTokenWithStringCopy ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Mnemonic , NameLoc , is<ISA_LIT>64 ( ) ) ) ; if ( Dot != StringRef :: npos ) { SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateTokenWithStringCopy ( DotStr , DotLoc , is<ISA_LIT>64 ( ) ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( DotStr , DotLoc , is<ISA_LIT>64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ; } if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] && Operands . size ( ) == <NUM_LIT> && ( Name == <STR_LIT> || Name == <STR_LIT> ) ) { std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; } return false ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> bool isVecListThreeQ ( ) const { if ( ! isDoubleSpacedVectorList ( ) ) return false ; return VectorList . Count == <NUM_LIT> ;


<s> auto CmpMI = MIRBuilder . buildInstr ( Opc , { ZReg } , { LHS . getReg ( ) } ) ; if ( ImmFns ) { for ( auto & RenderFn : * ImmFns ) RenderFn ( CmpMI ) ; } else { CmpMI . addUse ( RHS . getReg ( ) ) ; }

constrainSelectedInstRegOperands ( * CmpMI , TII , TRI , RBI ) ;


<s> bool <ISA_LIT>Subtarget :: hasPostRAScheduler ( CodeGenOpt :: Level OptLevel ) const { if ( OptLevel == CodeGenOpt :: None ) return false ;


<s> const Function * F = MF . getFunction ( ) ; P<ISA_LIT>nputAddr = <STR_LIT> ( * F ) ; const MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; if ( ! <STR_LIT> ( F -> getCallingConv ( ) ) ) { KernargSegmentPtr = true ; WorkGroupIDX = true ; WorkItemIDX = true ; } if ( F -> hasFnAttribute ( <STR_LIT> ) || ST . debuggerEmitPrologue ( ) ) WorkGroupIDY = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) || ST . debuggerEmitPrologue ( ) ) WorkGroupIDZ = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) || ST . debuggerEmitPrologue ( ) ) WorkItemIDY = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) || ST . debuggerEmitPrologue ( ) ) WorkItemIDZ = true ; if ( WorkItemIDZ ) WorkItemIDY = true ; bool MaySpill = ST . isVGPRSpillingEnabled ( * F ) ; bool HasStackObjects = FrameInfo . hasStackObjects ( ) ; if ( HasStackObjects || MaySpill ) PrivateSegmentWaveByteOffset = true ; if ( ST . isAmdCodeObjectV2 ( MF ) ) { if ( HasStackObjects || MaySpill ) PrivateSegmentBuffer = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) DispatchPtr = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) QueuePtr = true ; if ( F -> hasFnAttribute ( <STR_LIT> ) ) DispatchID = true ; } else if ( ST . isMesaGfxShader ( MF ) ) {

if ( HasStackObjects || MaySpill ) PrivateMemoryInputPtr = true ;


<s> uint64_t flags ( ) const { return <NUM_LIT> ;


<s> while ( I != MBB -> instr_end ( ) && I -> isInsideBundle ( ) ) { EmitInstruction ( & * I ) ; ++ I ; } } else { if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) { SmallVector < char , <NUM_LIT> > BBStr ; raw_svector_ostream Str ( BBStr ) ; const MachineBasicBlock * MBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; const MCSymbolRefExpr * Expr = MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , OutContext ) ; Expr -> print ( Str , MAI ) ; OutStreamer -> emitRawComment ( <STR_LIT> + BBStr ) ; } return ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { if ( isVerbose ( ) ) OutStreamer -> emitRawComment ( <STR_LIT> ) ; return ; } MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ;


<s> const std :: vector < const BasicBlock * > & getBasicBlocks ( ) const { return BasicBlocks ;


<s> bool Filler :: runOnMachineBasicBlock ( MachineBasicBlock & MBB ) { bool Changed = false ; const <ISA_LIT>Subtarget & STI = MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool InMicro<ISA_LIT>Mode = STI . inMicro<ISA_LIT>Mode ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( InMicro<ISA_LIT>Mode && STI . has<ISA_LIT>32r6 ( ) ) { return Changed ; } for ( Iter I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! hasUnoccupiedSlot ( & * I ) ) continue ; ++ FilledSlots ; Changed = true ; if ( ! DisableDelaySlotFiller && ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) ) { bool Filled = false ;

if ( <ISA_LIT>CompactBranchPolicy . getValue ( ) != CB_Always || ! TII -> getEquivalentCompactForm ( I ) ) {


<s> if ( ! isa < VectorType > ( DataTy ) ) return false ; if ( ! ST -> hasAVX512 ( ) ) return false ; if ( cast < VectorType > ( DataTy ) -> getNumElements ( ) == <NUM_LIT> ) return false ;

Type * ScalarTy = cast < VectorType > ( DataTy ) -> getElementType ( ) ;


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> if ( isa < ConstantSDNode > ( Size ) ) return lowerDYNAMIC_STACKALLOCImpl ( Op , DAG ) ;

return <ISA_LIT>TargetLowering :: LowerDYNAMIC_STACKALLOC ( Op , DAG ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveArch ( SMLoc L ) {


<s> fputs ( <STR_LIT> , file ) ; switch ( size ) { case <NUM_LIT> : break ; case <NUM_LIT> : fputs ( <STR_LIT> , file ) ; break ; default : gcc_unreachable ( ) ; }


<s> for ( arg = arglist ; arg ; arg = TREE_CHAIN ( arg ) ) { const char * str = TREE_STRING_POINTER ( TREE_VALUE ( arg ) ) ; size_t len = strlen ( str ) ; str_len_sum += len + <NUM_LIT> ; if ( arg != arglist ) argnum ++ ; for ( i = <NUM_LIT> ; i < strlen ( str ) ; i ++ ) if ( str [ i ] == ',' ) argnum ++ ; } attr_str = XNEWVEC ( char , str_len_sum ) ; str_len_sum = <NUM_LIT> ; for ( arg = arglist ; arg ; arg = TREE_CHAIN ( arg ) ) { const char * str = TREE_STRING_POINTER ( TREE_VALUE ( arg ) ) ; size_t len = strlen ( str ) ; memcpy ( attr_str + str_len_sum , str , len ) ; attr_str [ str_len_sum + len ] = TREE_CHAIN ( arg ) ? ',' : '\0' ; str_len_sum += len + <NUM_LIT> ; } for ( i = <NUM_LIT> ; i < strlen ( attr_str ) ; i ++ ) if ( attr_str [ i ] == '=' || attr_str [ i ] == '-' ) attr_str [ i ] = '_' ; if ( argnum == <NUM_LIT> ) return attr_str ; args = XNEWVEC ( char * , argnum ) ; i = <NUM_LIT> ;

attr = strtok ( attr_str , <STR_LIT> ) ;


<s> if ( in_use & EV5_E0 ) { if ( ! ( in_use & EV5_E01 ) || ( in_use & EV5_E1 ) ) goto done ; in_use |= EV5_E1 ; } in_use |= EV5_E0 ; break ; case EV5_E1 : if ( in_use & EV5_E1 ) goto done ; in_use |= EV5_E1 ; break ; case EV5_FAM : if ( in_use & EV5_FA ) { if ( in_use & EV5_FM ) goto done ; in_use |= EV5_FM ; } else in_use |= EV5_FA | EV5_FAM ; break ; case EV5_FA : if ( in_use & EV5_FA ) goto done ; in_use |= EV5_FA ; break ; case EV5_FM : if ( in_use & EV5_FM ) goto done ; in_use |= EV5_FM ; break ; case EV5_NONE : break ; default : gcc_unreachable ( ) ; }


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const BitVector Reserved = RI . getReservedRegs ( MF ) ; bool SaveS2 = Reserved [ <STR_LIT> ] ; MachineInstrBuilder MIB ; unsigned Opc = ( ( FrameSize <= <NUM_LIT> ) && ! SaveS2 ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; addSaveRestoreRegs ( MIB , CSI ) ; if ( SaveS2 ) MIB . addReg ( <STR_LIT> ) ;

if ( isUInt < <NUM_LIT> > ( FrameSize ) ) MIB . addImm ( FrameSize ) ;


<s> SMRange getLocRange ( ) const { return SMRange ( StartLoc , EndLoc ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Nodes ( Factor ) ; if ( ! reverse ) { for ( unsigned i = <NUM_LIT> ; i < Factor ; ++ i ) { SDValue Op0 = Ops [ i * <NUM_LIT> ] ; SDValue Op1 = Ops [ i * <NUM_LIT> + <NUM_LIT> ] ; Nodes [ i ] = DAG . getNode ( Opcode , dl , Op0 . getValueType ( ) , Op0 , Op1 ) ; } } else { for ( unsigned i = <NUM_LIT> ; i < Factor ; ++ i ) { SDValue Op0 = Ops [ i * <NUM_LIT> ] ; SDValue Op1 = Ops [ i * <NUM_LIT> + <NUM_LIT> ] ; Nodes [ Factor - <NUM_LIT> - i ] = DAG . getNode ( Opcode , dl , Op0 . getValueType ( ) , Op0 , Op1 ) ; }


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ShortenInstPass ( get<ISA_LIT>TargetMachine ( ) ) , false ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ElimComparePass ( get<ISA_LIT>TargetMachine ( ) ) , false ) ; addPass ( create<ISA_LIT>LongBranchPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { if ( MISchedPostRA ) addPass ( & PostMachineSchedulerID ) ; else addPass ( & PostRASchedulerID ) ; }


<s> enum machine_mode mode = insn_data [ icode ] . operand [ <NUM_LIT> ] . mode ; if ( ! target || GET_MODE ( target ) != mode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , mode ) ) return gen_reg_rtx ( mode ) ; else return target ;


<s> void setWasmEHFuncInfo ( WasmEHFuncInfo * Info ) {


<s> for ( const struct cpu_arch_extension * opt = arch -> common . extensions ; opt -> name != NULL ; opt ++ ) { if ( ! opt -> remove ) { arm_initialize_isa ( opt_bits , opt -> isa_bits ) ; if ( bitmap_subset_p ( opt_bits , arm_active_target . isa ) && ! bitmap_subset_p ( opt_bits , isa_all_fpubits ) ) asm_fprintf ( asm_out_file , <STR_LIT> , opt -> name ) ; } } } arm_last_printed_arch_string = arch_to_print ; } fprintf ( stream , <STR_LIT> ) ; if ( TARGET_THUMB ) { if ( is_called_in_ARM_mode ( decl ) || ( TARGET_THUMB1 && ! TARGET_THUMB1_ONLY && cfun -> is_thunk ) ) fprintf ( stream , <STR_LIT> ) ; else if ( TARGET_THUMB1 ) fprintf ( stream , <STR_LIT> ) ; else fprintf ( stream , <STR_LIT> ) ; } else fprintf ( stream , <STR_LIT> ) ; std :: string fpu_to_print = TARGET_SOFT_FLOAT ? <STR_LIT> : arm_identify_fpu_from_isa ( arm_active_target . isa ) ; if ( fpu_to_print != arm_last_printed_arch_string ) { asm_fprintf ( asm_out_file , <STR_LIT> , fpu_to_print . c_str ( ) ) ; arm_last_printed_fpu_string = fpu_to_print ; } if ( TARGET_POKE_FUNCTION_NAME ) arm_poke_function_name ( stream , ( const char * ) name ) ;


<s> if ( ForceTopDown ) { SU = Top . pickOnlyChoice ( ) ; if ( ! SU ) { SchedCandidate TopCand ; CandResult TopResult = pickNodeFromQueue ( Top , DAG -> getTopRPTracker ( ) , TopCand ) ; assert ( TopResult != NoCand && <STR_LIT> ) ; ( void ) TopResult ; SU = TopCand . SU ; } IsTopNode = true ; } else if ( ForceBottomUp ) { SU = Bot . pickOnlyChoice ( ) ; if ( ! SU ) { SchedCandidate BotCand ; CandResult BotResult = pickNodeFromQueue ( Bot , DAG -> getBotRPTracker ( ) , BotCand ) ; assert ( BotResult != NoCand && <STR_LIT> ) ; ( void ) BotResult ; SU = BotCand . SU ; } IsTopNode = false ; } else { SU = pickNodeBidrectional ( IsTopNode ) ; } if ( SU -> isTopReady ( ) ) Top . removeReady ( SU ) ; if ( SU -> isBottomReady ( ) ) Bot . removeReady ( SU ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( IsTopNode ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ( IsTopNode ? Top . CurrCycle : Bot . CurrCycle ) << <STR_LIT> << reportPackets ( ) << <STR_LIT> ;


<s> } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = getOppositeCondition ( BranchCode ) ; unsigned JNCC = getBrCond ( BranchCode ) . getOpcode ( ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) { return true ; } <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) { continue ; } return true ; }


<s> switch ( get_attr_type ( dep_insn ) ) { case TYPE_FDIV : case TYPE_FSQRT : case TYPE_FTOI : case TYPE_ITOF : case TYPE_FP : case TYPE_FMOVE : return insn_default_latency ( dep_insn ) ; default : return <NUM_LIT> ; } } } else if ( attr_type == TYPE_RET && visium_cpu == PROCESSOR_GR6 ) { rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( dep_pat ) == SET && REG_P ( SET_DEST ( dep_pat ) ) && REGNO ( SET_DEST ( dep_pat ) ) == LINK_REGNUM ) return <NUM_LIT> ; } return <NUM_LIT> ; } else if ( dep_type == REG_DEP_OUTPUT ) { if ( attr_type == TYPE_REG_FP && visium_cpu == PROCESSOR_GR5 ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return <NUM_LIT> ; if ( reg_mentioned_p ( SET_DEST ( pat ) , SET_DEST ( dep_pat ) ) ) { if ( recog_memoized ( dep_insn ) < <NUM_LIT> ) return <NUM_LIT> ; switch ( get_attr_type ( dep_insn ) ) { case TYPE_FDIV : case TYPE_FSQRT :


<s> } if ( riscv_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { riscv_emit_set ( dest , src ) ; return ; } if ( riscv_tls_symbol_p ( src ) ) { riscv_emit_move ( dest , riscv_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || can_create_pseudo_p ( ) ) ) { base = riscv_force_temporary ( dest , base ) ; riscv_emit_move ( dest , riscv_add_offset ( NULL , base , INTVAL ( offset ) ) ) ; return ; } src = force_const_mem ( mode , src ) ; riscv_split_symbol ( dest , XEXP ( src , <NUM_LIT> ) , mode , & XEXP ( src , <NUM_LIT> ) ) ; riscv_emit_move ( dest , src ) ;


<s> static DCTranslator * create<ISA_LIT>DCTranslator ( const Triple & TT , LLVMContext & Ctx , const DataLayout & DL , unsigned OptLevel , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCInstPrinter & MIP ) { ( void ) TT ; return new <ISA_LIT>DCTranslator ( Ctx , DL , OptLevel , MII , MRI , STI , MIP ) ;


<s> union { long long l ; double d ; } u ; u . l = mm ; return u . d ;


<s> if ( GET_CODE ( op ) == CONST_INT ) { int ival ; ival = INTVAL ( op ) ; switch ( get_attr_type ( insn ) ) { case TYPE_ALUQ_L : if ( IN_RANGE ( ival , <NUM_LIT> , <NUM_LIT> ) || IN_RANGE ( ival , - <NUM_LIT> , - <NUM_LIT> ) ) return OP_TYPE_IMM_Q ; gcc_assert ( ! reload_completed ) ; break ; case TYPE_MOVEQ_L : if ( USE_MOVQ ( ival ) ) return OP_TYPE_IMM_Q ; gcc_assert ( ! reload_completed ) ; break ; case TYPE_MOV3Q_L : if ( valid_mov3q_const ( ival ) ) return OP_TYPE_IMM_Q ; gcc_assert ( ! reload_completed ) ; break ; default : break ; } if ( IN_RANGE ( ival , - <NUM_LIT> , <NUM_LIT> ) ) return OP_TYPE_IMM_W ; return OP_TYPE_IMM_L ; } if ( GET_CODE ( op ) == CONST_DOUBLE ) { switch ( GET_MODE ( op ) ) { case SFmode : return OP_TYPE_IMM_W ; case VOIDmode : case DFmode : return OP_TYPE_IMM_L ; default : gcc_unreachable ( ) ; } } if ( GET_CODE ( op ) == CONST || symbolic_operand ( op , VOIDmode ) || LABEL_P ( op ) ) { switch ( GET_MODE ( op ) ) { case QImode : return OP_TYPE_IMM_Q ; case HImode :


return ( __m128i ) __builtin_ia32_pmovsdw256_mask ( ( __v8si ) __A , ( __v8hi ) _mm_setzero_si128 ( ) , __M ) ;


<s> EVT VecVT = EVT :: getEVT ( VecTy ) ; if ( ! VecVT . isSimple ( ) || VecVT . getSizeInBits ( ) <= <NUM_LIT> ) return false ; if ( ST . isHVXVectorType ( VecVT . getSimpleVT ( ) ) ) return true ;

auto Action = TLI . getPreferredVectorAction ( VecVT . getSimpleVT ( ) ) ;


<s> const auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; const auto & DL = MF . getDataLayout ( ) ; const auto & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( STI . genLongCalls ( ) ) return false ; if ( STI . isThumb1Only ( ) ) return false ; auto CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; bool IsDirect = ! Callee . isReg ( ) ; auto CallOpcode = getCallOpcode ( STI , IsDirect ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( CallOpcode ) ; bool IsThumb = STI . isThumb ( ) ; if ( IsThumb ) MIB . add ( predOps ( <STR_LIT> ) ) ; MIB . add ( Callee ) ; if ( ! IsDirect ) { auto CalleeReg = Callee . getReg ( ) ; if ( CalleeReg && ! TRI -> isPhysicalRegister ( CalleeReg ) ) { unsigned CalleeIdx = IsThumb ? <NUM_LIT> : <NUM_LIT> ; MIB -> getOperand ( CalleeIdx ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB . getInstr ( ) , MIB -> getDesc ( ) , Callee , CalleeIdx ) ) ; } } MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , CallConv ) ) ; bool IsVarArg = false ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; for ( auto Arg : OrigArgs ) { if ( ! isSupportedType ( DL , TLI , Arg . Ty ) ) return false ; if ( ! Arg . IsFixed ) IsVarArg = true ; if ( Arg . Flags . isByVal ( ) ) return false ; SmallVector < unsigned , <NUM_LIT> > Regs ; splitToValueTypes ( Arg , ArgInfos , MF , [ & ] ( unsigned Reg ) { Regs . push_back ( Reg ) ; } ) ;

if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , Arg . Reg ) ;


<s> bool <ISA_LIT>TTIImpl :: isLegalToVectorizeReduction ( RecurrenceDescriptor RdxDesc , ElementCount VF ) const { if ( ! VF . isScalable ( ) ) return true ; Type * Ty = RdxDesc . getRecurrenceType ( ) ; if ( Ty -> isBFloatTy ( ) || ! isLegalElementTypeForSVE ( Ty ) ) return false ;

switch ( RdxDesc . getRecurrenceKind ( ) ) {


<s> strcpy ( filename_buff , filespec ) ; decc$to_vms ( filespec , translate_unix , <NUM_LIT> , <NUM_LIT> ) ; strcpy ( new_host_filespec , filename_buff ) ; return new_host_filespec ; }


<s> CASE_CFN_ASIN : CASE_CFN_ASINH : CASE_CFN_ATAN : CASE_CFN_ATANH : CASE_CFN_CBRT : CASE_CFN_COS : CASE_CFN_COSH : CASE_CFN_ERF : CASE_CFN_ERFC : CASE_CFN_EXP2 : CASE_CFN_EXP : CASE_CFN_EXPM1 : CASE_CFN_LGAMMA : CASE_CFN_LOG10 : CASE_CFN_LOG1P : CASE_CFN_LOG2 : CASE_CFN_LOG : CASE_CFN_SIN : CASE_CFN_SINH : CASE_CFN_SQRT : CASE_CFN_TAN : CASE_CFN_TANH : if ( el_mode == DFmode && n == <NUM_LIT> ) { bdecl = mathfn_built_in ( double_type_node , fn ) ; suffix = <STR_LIT> ; } else if ( el_mode == SFmode && n == <NUM_LIT> ) { bdecl = mathfn_built_in ( float_type_node , fn ) ; suffix = <STR_LIT> ; } else return NULL_TREE ; if ( ! bdecl ) return NULL_TREE ; break ; default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + sizeof ( <STR_LIT> ) - <NUM_LIT> ) ; strcat ( name , suffix ) ; if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ;

new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ;


<s>
OS
<<
' '
;
printAccessQualifier
(
MI
,
FirstVariableIndex
,
OS
)
;
break
;
case
<STR_LIT>
:
OS
<<
' '
;
printOperand
(
MI
,
FirstVariableIndex
,
OS
)
;
break
;
case
<STR_LIT>
:
{
printRemainingVariableOps
(
MI
,
NumFixedOps
,
OS
,
false
,
true
)
;
break
;
}
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
{
printRemainingVariableOps
(
MI
,
NumFixedOps
,
OS
)
;
break
;
}
default
:
break
;
}
}
else
{
switch
(
OpCode
)
{
case
<STR_LIT>
:
case
<STR_LIT>
:
OS
<<
' '
;
printMemoryOperand
(
MI
,
FirstVariableIndex
,
OS
)
;
printRemainingVariableOps
(
MI
,
FirstVariableIndex
+
<NUM_LIT>
,
OS
)
;
break
;
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
case
<STR_LIT>
:
OS
<<
' '
;
printImageOperand
(
MI
,
FirstVariableIndex
,
OS
)
;
printRemainingVariableOps
(
MI
,
NumFixedOps
+
<NUM_LIT>
,
OS
)
;
break
;
case
<STR_LIT>
:
case
<STR_LIT>
:
{
const
unsigned
NumOps
=
MI
->
getNumOperands
(
)
;
for
(
unsigned
i
=
NumFixedOps
;
i
<
NumOps
;
++
i
)
{
OS
<<
' '
;
printMemoryOperand
(
MI
,
i
,
OS
)
;
if
(
MI
->
getOperand
(
i
)
.
getImm
(
)
&
static_cast
<
unsigned
>
(
<STR_LIT>
::
Aligned
)
)
{
assert
(
i
+
<NUM_LIT>
<
NumOps
&&
<STR_LIT>
)
;
OS
<<
' '
;
printOperand
(
MI
,
i
+
<NUM_LIT>
,
OS
)
;
i
+=
<NUM_LIT>
;
}
}
break
;
}
case
<STR_LIT>
:
case
<STR_LIT>
:
printOpConstantVarOps
(
MI
,
NumFixedOps
,
OS
)
;
break
;
default
:
printRemainingVariableOps
(
MI
,
NumFixedOps
,
OS
)
;
break
;
}
}


<s> std :: pair < MachineInstr * , <STR_LIT> > <ISA_LIT>InstructionSelector :: emitOverflowOp ( unsigned Opcode , Register Dst , MachineOperand & LHS , MachineOperand & RHS , MachineIRBuilder & MIRBuilder ) const { switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case TargetOpcode :: G_SADDO : return std :: make_pair ( emitADDS ( Dst , LHS , RHS , MIRBuilder ) , <STR_LIT> ) ; case TargetOpcode :: G_UADDO : return std :: make_pair ( emitADDS ( Dst , LHS , RHS , MIRBuilder ) , <STR_LIT> ) ; case TargetOpcode :: G_SSUBO : return std :: make_pair ( emitSUBS ( Dst , LHS , RHS , MIRBuilder ) , <STR_LIT> ) ; case TargetOpcode :: G_USUBO : return std :: make_pair ( emitSUBS ( Dst , LHS , RHS , MIRBuilder ) , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const {


<s> return __builtin_mve_vcmpltq_sv4si ( __a , __b ) ;


<s> bool useCompound ( ) const { return UseCompound ;


<s> case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , dl , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ;

SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ;


<s> Value * <ISA_LIT>IREmitter :: visitWIN_ALLOCA ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> unsigned Opc = MI . getOpcode ( ) ; if ( TII -> isSDWA ( Opc ) ) return true ; if ( <STR_LIT> ( Opc ) == - <NUM_LIT> ) Opc = <STR_LIT> ( Opc ) ; if ( <STR_LIT> ( Opc ) == - <NUM_LIT> ) return false ; if ( ! ST . hasSDWAOmod ( ) && TII -> hasModifiersSet ( MI , <STR_LIT> :: omod ) ) return false ; if ( TII -> isVOPC ( Opc ) ) { if ( ! ST . hasSDWASdst ( ) ) { const MachineOperand * SDst = TII -> getNamedOperand ( MI , <STR_LIT> :: sdst ) ; if ( SDst && SDst -> getReg ( ) != <STR_LIT> ) return false ;


<s> BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; } return <NUM_LIT> ; }


<s> for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( I -> getOpcode ( ) == <STR_LIT> ) Changes |= insertWait ( MBB , I , LastIssued ) ;

else Changes |= insertWait ( MBB , I , handleOperands ( * I ) ) ;


<s> } } for ( unsigned I = <NUM_LIT> ; I != Order . size ( ) ; ++ I ) { if ( ! Needed . count ( I ) ) continue ; Node C = conj ( I ) ;


if ( mask ) current_frame_info . gp_offset = ( total_size - gp_reg_size ) ;


<s> if ( N -> getOpcode ( ) == <STR_LIT> && ( ( N -> getOperand ( <NUM_LIT> ) == C . Op0 && N -> getOperand ( <NUM_LIT> ) == C . Op1 ) || ( N -> getOperand ( <NUM_LIT> ) == C . Op1 && N -> getOperand ( <NUM_LIT> ) == C . Op0 ) ) ) { C . Op0 = SDValue ( N , <NUM_LIT> ) ; C . Op1 = DAG . getConstant ( <NUM_LIT> , DL , N -> getValueType ( <NUM_LIT> ) ) ;


<s> if ( InVec . getOpcode ( ) == <STR_LIT> ) { unsigned NumElts = ResVT . getVectorNumElements ( ) ; VecOp = DAG . getNode ( <STR_LIT> , dl , ResVT , VecOp ) ; VecOp = DAG . getNode ( <STR_LIT> , dl , ResVT , VecOp , InVec . getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( NumElts / <NUM_LIT> + <NUM_LIT> ) ) ; } else { InVec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InVec ) ;

SDValue VecOp2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , InVec ) ;


<s> if ( type == bool_char_type_node ) return <STR_LIT> ; if ( type == bool_short_type_node ) return <STR_LIT> ; if ( type == pixel_type_node ) return <STR_LIT> ; if ( type == bool_int_type_node ) return <STR_LIT> ; if ( type == bool_long_long_type_node ) return <STR_LIT> ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IBM_P ( TYPE_MODE ( type ) ) ) return <STR_LIT> ; if ( SCALAR_FLOAT_TYPE_P ( type ) && FLOAT128_IEEE_P ( TYPE_MODE ( type ) ) ) return <STR_LIT> ;

if ( type == vector_pair_type_node ) return <STR_LIT> ;


<s> if ( ! I -> isCall ( ) ) return false ; unsigned structSizeOpNum = <NUM_LIT> ; switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : structSizeOpNum = <NUM_LIT> ; break ; case <STR_LIT> : return false ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , TargetOptions Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OptLevel ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , getGPUOrDefault ( TT , CPU ) , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OptLevel ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) { initAsmInfo ( ) ;


<s> unsigned Opc = N -> getMachineOpcode ( ) ; switch ( Opc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool isSVEDataVectorRegOfWidth ( ) const { return isSVEDataVectorReg ( ) && ( ElementWidth == - <NUM_LIT> || Reg . ElementWidth == ElementWidth ) ;


<s> return ( float32x2_t ) __builtin_neon_vrintxv2sf ( __a ) ;


<s> op = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( op ) != LO_SUM ) { return GET_CODE ( op ) == SYMBOL_REF && GET_MODE ( op ) == Pmode && SYMBOL_REF_FUNCTION_P ( op ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFP_TO_SINT ( SDValue Op , SelectionDAG & DAG ) const { MVT VT = Op . getSimpleValueType ( ) ; if ( VT . isVector ( ) ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , VT , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ) ; return SDValue ( ) ; } std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> ) return Op ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FIST ;


<s> if ( ! isInt64Immediate ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) , Imm64 ) || ! isMask_64 ( ~ Imm64 ) ) return false ; unsigned MB = <NUM_LIT> - countTrailingOnes ( ~ Imm64 ) ; unsigned SH = <NUM_LIT> ; SDLoc dl ( N ) ;

SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , getI32Imm ( SH , dl ) , getI32Imm ( MB , dl ) } ;


<s> LCOMMDirectiveAlignmentType = LCOMM :: Log2Alignment ; HasDotTypeDotSizeDirective = false ; HasSingleParameterDotFile = false ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: None ;


<s> BalTgtMBB -> addSuccessor ( TgtMBB ) ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; unsigned BalOp = <STR_LIT> ; if ( ! ABI . IsN64 ( ) ) { Pos = LongBrMBB -> begin ( ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( * LongBrMBB , Pos , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; MIBundleBuilder ( * LongBrMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addMBB ( TgtMBB ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addMBB ( TgtMBB ) . addMBB ( BalTgtMBB ) ) . append ( BuildMI ( * MF , DL , TII -> get ( BalOp ) ) . addMBB ( BalTgtMBB ) ) ; Pos = BalTgtMBB -> begin ( ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BalTgtMBB , Pos , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetNaCl ( ) ) { MIBundleBuilder ( * BalTgtMBB , Pos ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ) . append ( BuildMI ( * MF , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ) ; } else {


<s> AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; case <STR_LIT> : AtomicOp = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned OldVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Ptr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Scratch = RegInfo . createVirtualRegister ( RegInfo . getRegClass ( OldVal ) ) ;

MachineBasicBlock :: iterator II ( MI ) ;


<s> if ( isThumb ( ) ) { assert ( ( ( Count & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ; Count /= <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) OW -> Write16 ( <NUM_LIT> ) ;


<s> int WaitStatesNeeded = <NUM_LIT> ; WaitStatesNeeded = checkSoftClauseHazards ( SMRD ) ; if ( ST . getGeneration ( ) != <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return WaitStatesNeeded ; int SmrdSgprWaitStates = <NUM_LIT> ; auto IsHazardDefFn = [ this ] ( MachineInstr * MI ) { return TII . isVALU ( * MI ) ; } ; auto IsBufferHazardDefFn = [ this ] ( MachineInstr * MI ) { return TII . isSALU ( * MI ) ; } ; bool IsBufferSMRD = TII . isBufferSMRD ( * SMRD ) ; for ( const MachineOperand & Use : SMRD -> uses ( ) ) { if ( ! Use . isReg ( ) ) continue ;

int WaitStatesNeededForUse = SmrdSgprWaitStates - getWaitStatesSinceDef ( Use . getReg ( ) , IsHazardDefFn ) ;


<s> unsigned EltOffset = SplatVal . getValueType ( ) . getSizeInBits ( ) / <NUM_LIT> ; SDLoc DL ( & St ) ; SDValue BasePtr = St . getBasePtr ( ) ; const MachinePointerInfo & PtrInfo = St . getPointerInfo ( ) ; SDValue NewST1 = DAG . getStore ( St . getChain ( ) , DL , SplatVal , BasePtr , PtrInfo , OrigAlignment , St . getMemOperand ( ) -> getFlags ( ) ) ; unsigned Offset = EltOffset ; while ( -- NumVecElts ) { unsigned Alignment = MinAlign ( OrigAlignment , Offset ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( Offset , DL , <STR_LIT> ) ) ;

NewST1 = DAG . getStore ( NewST1 . getValue ( <NUM_LIT> ) , DL , SplatVal , OffsetPtr , PtrInfo . getWithOffset ( Offset ) , Alignment , St . getMemOperand ( ) -> getFlags ( ) ) ;


<s> explicit <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) {


<s> void addBDVAddrOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

assert ( isMem ( BDVMem ) && <STR_LIT> ) ;


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && <STR_LIT> ( I -> getOpcode ( ) ) == <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ;


<s> int mmix_opposite_regno ( int regno , int incoming ) { if ( incoming && regno == MMIX_OUTGOING_RETURN_VALUE_REGNUM ) return MMIX_RETURN_VALUE_REGNUM ; if ( ! incoming && regno == MMIX_RETURN_VALUE_REGNUM ) return MMIX_OUTGOING_RETURN_VALUE_REGNUM ; if ( ! mmix_function_arg_regno_p ( regno , incoming ) ) return regno ; return regno - ( incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM - MMIX_FIRST_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM - MMIX_FIRST_INCOMING_ARG_REGNUM ) ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) MI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; else llvm_unreachable ( <STR_LIT> ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( EvenDestReg ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( EvenSrcReg ) ; DOUT << <STR_LIT> << * MI ; if ( DestDReg != SrcDReg ) { MI = BuildMI ( MBB , I , dl , TM . getInstrInfo ( ) -> get ( <STR_LIT> ) , OddDestReg ) . addReg ( OddSrcReg ) ; DOUT << <STR_LIT> << * MI ; } ++ NumFpDs ;


<s> int m68hc11_function_arg_padding ( enum machine_mode mode , tree type ) { if ( type != <NUM_LIT> && AGGREGATE_TYPE_P ( type ) ) return upward ; return DEFAULT_FUNCTION_ARG_PADDING ( mode , type ) ;


<s> MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( DestReg , & <STR_LIT> ) ; } FrameInfo . setStackID ( FrameIndex , <NUM_LIT> ) ; MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( SpillSize ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getFrameOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> if ( y != const0_rtx ) return CCmode ; return mode_from_flags ( flags_from_code ( cmp_code ) ) ;


<s> return false ; case <STR_LIT> : case <STR_LIT> : return true ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPhysRegClass ( unsigned Reg ) const { assert ( ! Register :: isVirtualRegister ( Reg ) ) ; static const TargetRegisterClass * const BaseClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , } ;

for ( const TargetRegisterClass * BaseClass : BaseClasses ) {


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return isTypeDeclInstr ( MI ) || isConstantInstr ( MI ) || isDecorationInstr ( MI ) ; }


<s> short <ISA_LIT>InstrInfo :: getEquivalentHWInstr ( const MachineInstr * MI ) const {

return <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> ) ;


<s> case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; } } else { switch ( CI . Width0 + CI . Width1 ) { default : return nullptr ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; } }


<s> const TargetSubtargetInfo * getST ( ) const { return ST ;


<s> if ( VT . getSizeInBits ( ) / <NUM_LIT> > LS -> getAlignment ( ) ) { assert ( <STR_LIT> ) ; if ( VT == <STR_LIT> ) return false ; } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , ValTy ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ;

Offset = Addr . getOperand ( <NUM_LIT> ) ;


<s> info -> symbol_type = SYMBOL_TYPE_GENERAL ; info -> symbol = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; if ( XINT ( x , <NUM_LIT> ) == UNSPEC_GOTOFF ) { info -> regA = gen_rtx_REG ( SImode , PIC_OFFSET_TABLE_REGNUM ) ; info -> type = ADDRESS_GOTOFF ; } else if ( XINT ( x , <NUM_LIT> ) == UNSPEC_PLT ) { info -> type = ADDRESS_PLT ;


<s> insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { DebugLoc DL ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) ;


<s> explicit <ISA_LIT>Z80MachineFunctionInfo ( MachineFunction & MF ) : needFP ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) {


<s> static void EmitDefCfaRegister ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc dl , const TargetInstrInfo & TII , MachineModuleInfo * MMI , unsigned DRegNum ) {

unsigned CFIIndex = MMI -> addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , DRegNum ) ) ;


<s> if ( ST -> isThumb1Only ( ) && N -> getOpcode ( ) == <STR_LIT> && VT == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) -> hasOneUse ( ) ) { if ( DCI . isBeforeLegalize ( ) || DCI . isCalledByLegalizer ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ShiftAmtNode = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! ShiftAmtNode ) return SDValue ( ) ; uint32_t ShiftAmt = static_cast < uint32_t > ( ShiftAmtNode -> getZExtValue ( ) ) ; ConstantSDNode * AndMaskNode = dyn_cast < ConstantSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; if ( ! AndMaskNode ) return SDValue ( ) ; uint32_t AndMask = static_cast < uint32_t > ( AndMaskNode -> getZExtValue ( ) ) ; if ( AndMask == <NUM_LIT> || AndMask == <NUM_LIT> ) return SDValue ( ) ; if ( isMask_32 ( AndMask ) ) { uint32_t MaskedBits = countLeadingZeros ( AndMask ) ; if ( MaskedBits > ShiftAmt ) { SDLoc DL ( N ) ; SDValue SHL = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N0 -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MaskedBits , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SHL , DAG . getConstant ( MaskedBits - ShiftAmt , DL , <STR_LIT> ) ) ; } } } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! VT . isVector ( ) || ! TLI . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( ST -> hasMVEIntegerOps ( ) && VT == <STR_LIT> ) return SDValue ( ) ; int64_t Cnt ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) { SDLoc dl ( N ) ; return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , dl , <STR_LIT> ) ) ; }


<s> MachineFunction :: iterator MBBI = MBB ; if ( llvm :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ; MachineBasicBlock * NextBB = llvm :: next ( MBBI ) ;

for ( MachineBasicBlock :: succ_iterator I = MBB -> succ_begin ( ) , E = MBB -> succ_end ( ) ; I != E ; ++ I ) if ( * I == NextBB ) return true ;


<s> MRI . setPhysRegUnused ( <STR_LIT> ) ; MRI . setPhysRegUnused ( <STR_LIT> ) ;


<s> assert ( LHS . getValueType ( ) . is64BitVector ( ) && RHS . getValueType ( ) . is64BitVector ( ) && <STR_LIT> ) ; if ( isEssentiallyExtractHighSubvector ( LHS ) ) { RHS = tryExtendDUPToExtractHigh ( RHS , DAG ) ; if ( ! RHS . getNode ( ) ) return SDValue ( ) ; } else if ( isEssentiallyExtractHighSubvector ( RHS ) ) { LHS = tryExtendDUPToExtractHigh ( LHS , DAG ) ;

if ( ! LHS . getNode ( ) ) return SDValue ( ) ;


<s> EVT ResTy = Op -> getValueType ( <NUM_LIT> ) ; APInt BitImm = APInt ( ResTy . getVectorElementType ( ) . getSizeInBits ( ) , <NUM_LIT> ) << cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; SDValue BitMask = DAG . getConstant ( ~ BitImm , DL , ResTy ) ;

return DAG . getNode ( <STR_LIT> , DL , ResTy , Op -> getOperand ( <NUM_LIT> ) , BitMask ) ;


<s> unsigned i = <NUM_LIT> ; while ( ! MI -> getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI -> getNumOperands ( ) && <STR_LIT> ) ; } if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) return Offset == <NUM_LIT> ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; bool isSigned = true ; switch ( AddrMode ) { case <STR_LIT> : case <STR_LIT> : Scale = <NUM_LIT> ; if ( Offset < <NUM_LIT> ) { NumBits = <NUM_LIT> ; Offset = - Offset ; } else { NumBits = <NUM_LIT> ; } break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; break ; case <STR_LIT> : NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; isSigned = false ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ; } Offset += getFrameIndexInstrOffset ( MI , i ) ; if ( ( Offset & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; if ( isSigned && Offset < <NUM_LIT> ) Offset = - Offset ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ;

if ( ( unsigned ) Offset <= Mask * Scale ) return true ;


<s> MachineLoopInfo & MLI = getAnalysis < MachineLoopInfo > ( ) ; auto * AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; auto * MBPI = & getAnalysis < MachineBranchProbabilityInfo > ( ) ; <ISA_LIT>PacketizerList Packetizer ( Func , MLI , AA , MBPI ) ; NumReplaced = <NUM_LIT> ; MachineBasicBlock * MBB ; unsigned instr_count = <NUM_LIT> ; unsigned nest_count = PRECOUNT ; unsigned last_loop = EMPTYREF ; InitSPScale ( ) ; for ( MachineFunction :: iterator MBBI = MF -> begin ( ) , MBBE = MF -> end ( ) ; MBBI != MBBE ; ++ MBBI ) { MBB = & * MBBI ; for ( MachineBasicBlock :: iterator mi = MBB -> begin ( ) , me = MBB -> end ( ) ; mi != me ; ) { MachineBasicBlock :: iterator nmi = std :: next ( mi ) ; MachineInstr * MI = & * mi ; instr_count ++ ; auto opc = MI -> getOpcode ( ) ; if ( isLoopInstr ( MI ) ) { nest_count ++ ; ProcessStartLoop ( MI , nest_count , instr_count ) ; } else if ( opc == <STR_LIT> ) { last_loop = ProcessEndLoop ( MI , instr_count ) ; nest_count -- ; } else { ProcessNotLoopInstr ( MI ) ; if ( InstrWithLoopReg ( MI ) ) { unsigned ls ; if ( CurrentTopLoop != EMPTYREF ) { ls = hwloops [ CurrentTopLoop ] . LastClosedSon ; if ( ls == EMPTYREF ) { ls = CurrentTopLoop ; } hwloops [ ls ] . LoopRegInstr . insert ( MI ) ; } else if ( last_loop != EMPTYREF ) { ls = hwloops [ last_loop ] . LastClosedSon ; if ( ls == EMPTYREF ) { ls = last_loop ; } hwloops [ ls ] . LoopRegInstr . insert ( MI ) ; } } } mi = nmi ; } } assert ( nest_count == PRECOUNT ) ; if ( AtLeastOneLoopWasToTRansform ) { SetNewRoots ( <NUM_LIT> ) ; SetNewCounts ( ) ; EscalateSpoiled ( ) ; for ( unsigned int i = <NUM_LIT> ; i < size ( hwloops ) ; i ++ ) { if ( TransformHWLoopBack ( i , Func ) ) {


<s> if ( Sleds . empty ( ) ) return ; if ( Subtarget -> isTargetELF ( ) ) { auto PrevSection = OutStreamer -> getCurrentSectionOnly ( ) ; auto Fn = MF -> getFunction ( ) ; MCSection * Section = nullptr ; if ( Fn -> hasComdat ( ) ) { Section = OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_GROUP , <NUM_LIT> , Fn -> getComdat ( ) -> getName ( ) ) ; OutStreamer -> SwitchSection ( Section ) ; } else { Section = OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ; } OutStreamer -> SwitchSection ( Section ) ; for ( const auto & Sled : Sleds ) { OutStreamer -> EmitSymbolValue ( Sled . Sled , <NUM_LIT> ) ; OutStreamer -> EmitSymbolValue ( CurrentFnSym , <NUM_LIT> ) ; auto Kind = static_cast < uint8_t > ( Sled . Kind ) ; OutStreamer -> EmitBytes ( StringRef ( reinterpret_cast < const char * > ( & Kind ) , <NUM_LIT> ) ) ; OutStreamer -> EmitBytes ( StringRef ( reinterpret_cast < const char * > ( & Sled . AlwaysInstrument ) , <NUM_LIT> ) ) ; OutStreamer -> EmitZeros ( <NUM_LIT> ) ; } OutStreamer -> SwitchSection ( PrevSection ) ;


<s> BuildMI ( MBB , & * MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , & * MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; MachineFrameInfo & MFI = MBB . getParent ( ) -> getFrameInfo ( ) ; MFI . setObjectAlignment ( CSI [ i ] . getFrameIdx ( ) , STI . getCapAlignment ( ) ) ; } bool IsLOHI = ( Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> || Reg == <STR_LIT> ) ; const Function & Func = MBB . getParent ( ) -> getFunction ( ) ; if ( IsLOHI && Func . hasFnAttribute ( <STR_LIT> ) ) { DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Op = <NUM_LIT> ; if ( ! STI . getABI ( ) . ArePtrs64bit ( ) ) { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } else { Op = ( Reg == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; Reg = <STR_LIT> ; } BuildMI ( MBB , MI , DL , TII . get ( Op ) , <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; }

bool IsKill = ! IsRAAndRetAddrIsTaken && KillRAOnSpill ;


<s> return ! ElemTy -> isVoidTy ( ) && ! ElemTy -> isLabelTy ( ) && ! ElemTy -> isMetadataTy ( ) && ! ElemTy -> isTokenTy ( ) && ! ElemTy -> isX86_AMXTy ( ) ;


<s> SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { if ( ! isOneConstant ( N0 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ; if ( VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue DivRem8 = getDivRem8 ( N , DAG ) ) return DivRem8 ; if ( SDValue NewAdd = promoteExtBeforeAdd ( N , DAG , Subtarget ) ) return NewAdd ; if ( SDValue R = combineOrCmpEqZeroToCtlzSrl ( N , DAG , DCI , Subtarget ) ) return R ;


<s> default : gcc_unreachable ( ) ; case SH_CONST_VECTOR : { gcc_assert ( GET_CODE ( body ) == SET ) ; swap_const_vector_halves ( & SET_SRC ( body ) ) ; if ( dump_file ) fprintf ( dump_file , <STR_LIT> , i ) ; break ; } case SH_SUBREG : adjust_subreg_index ( body ) ;


<s> USet Rs ; for ( MachineLoop * L : WorkQ ) { Rs . clear ( ) ; collectIndRegsForLoop ( L , Rs ) ;

if ( ! Rs . empty ( ) ) IRM . insert ( std :: make_pair ( L , Rs ) ) ;


<s> void addImm0_65535Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> o << getTagName ( PREFIX_SYMBOL ) << <STR_LIT> << num << <STR_LIT> ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseFGR32Regs ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseRegs ( Operands , ( int ) <STR_LIT> ) ;


<s> return false ; } DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; DominatorTreeWrapperPass * const DTW = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTW ? & DTW -> getDomTree ( ) : nullptr ; const TargetPassConfig & TPC = getAnalysis < TargetPassConfig > ( ) ; const TargetMachine & TM = TPC . getTM < TargetMachine > ( ) ; const GCNSubtarget & ST = TM . getSubtarget < GCNSubtarget > ( F ) ; HasDPP = ST . hasDPP ( ) ; IsPixelShader = F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS ; visit ( F ) ; const bool Changed = ! ToReplace . empty ( ) ; for ( ReplacementInfo & Info : ToReplace ) { optimizeAtomic ( * Info . I , Info . Op , Info . ValIdx , Info . ValDivergent ) ; }


<s> PMAI = static_cast < const <ISA_LIT>MCAsmInfo * > ( TM . getMCAsmInfo ( ) ) ;

PTOF = ( <ISA_LIT>TargetObjectFile * ) & PTLI -> getObjFileLowering ( ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> parent -> Priv -> Subscopes . push_back ( this ) ; assert ( parent ) ; MachineBasicBlock * header = loop . getHeader ( ) ; SmallVector < std :: pair < const MachineBasicBlock * , const MachineBasicBlock * > , <NUM_LIT> > ExitEdges ; loop . getExitEdges ( ExitEdges ) ; for ( auto edge : ExitEdges ) {

auto found = std :: find_if ( Priv -> Blocks . begin ( ) , Priv -> Blocks . end ( ) , [ & ] ( auto block ) { return block -> getMBB ( ) == edge . first ; } ) ;


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <STR_LIT> << StringRef ( getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : O << GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> getName ( ) ; break ;

case MachineOperand :: MO_ExternalSymbol :


<s> unsigned BitWidth = VT . getSizeInBits ( ) - NumberOfIgnoredHighBits ; APInt SignificantDstMask = APInt ( BitWidth , DstMask ) ; APInt SignificantBitsToBeInserted = BitsToBeInserted . zextOrTrunc ( BitWidth ) ;

return ( SignificantDstMask & SignificantBitsToBeInserted ) == <NUM_LIT> && ( SignificantDstMask | SignificantBitsToBeInserted ) . isAllOnesValue ( ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & OS , unsigned RegNo ) const { OS << StringRef ( getRegisterName ( RegNo ) ) . lower ( ) ;


<s> int getSEHRegNum ( unsigned i ) const { return getEncodingValue ( i ) ;


<s> if ( ! is_weak && SYMBOL_REF_LOCAL_P ( sym ) ) emit_insn ( gen_sym_label2reg ( reg , sym , lab ) ) ; else if ( sibcall_p && SYMBOL_REF_LOCAL_P ( sym ) ) emit_insn ( gen_symPCREL_label2reg ( reg , sym , lab ) ) ;

else emit_insn ( gen_symPLT_label2reg ( reg , sym , lab ) ) ;


<s> if ( MCO . isImm ( ) && ( ParseBytes == PrintAllAsBytes || ( ParseBytes == PrintCallAsBytes && Inst . getOpcode ( ) == <STR_LIT> ) ) ) { unsigned ImmShift = get<ISA_LIT>ImmediateShift ( MID . TSFlags ) ; MCO . setImm ( MCO . getImm ( ) / ( <NUM_LIT> << ImmShift ) ) ; } } unsigned ALUlOpcode ; if ( Format == <STR_LIT> && HasImm ) { MCOperand & MCO = Inst . getOperand ( ImmOpNo ) ; if ( MCO . isExpr ( ) ) { if ( HasALUlVariant ( Inst . getOpcode ( ) , ALUlOpcode ) ) { if ( InBundle ) { return Error ( IDLoc , <STR_LIT> ) ; } else { Inst . setOpcode ( ALUlOpcode ) ; BundleCounter ++ ; } } } else { assert ( MCO . isImm ( ) && <STR_LIT> ) ; if ( ! isUInt < <NUM_LIT> > ( MCO . getImm ( ) ) ) { if ( isUInt < <NUM_LIT> > ( - MCO . getImm ( ) ) && Inst . getOpcode ( ) == <STR_LIT> ) { MCO . setImm ( - MCO . getImm ( ) ) ; Inst . setOpcode ( <STR_LIT> ) ; } else if ( HasALUlVariant ( Inst . getOpcode ( ) , ALUlOpcode ) ) { if ( InBundle || BundleCounter ) { return Error ( IDLoc , <STR_LIT> <STR_LIT> ) ; } Inst . setOpcode ( ALUlOpcode ) ; BundleCounter ++ ; if ( ! isInt < <NUM_LIT> > ( MCO . getImm ( ) ) && ! isUInt < <NUM_LIT> > ( MCO . getImm ( ) ) ) { return Error ( IDLoc , <STR_LIT> ) ; } } else { return Error ( IDLoc , <STR_LIT> <STR_LIT> ) ; } } } if ( BundleCounter > IssueWidth ) { return Error ( IDLoc , <STR_LIT> <STR_LIT> ) ; } } else if ( Format == <STR_LIT> ) { if ( InBundle || BundleCounter ) { return Error ( IDLoc , <STR_LIT> ) ; } BundleCounter ++ ; MCOperand & MCO = Inst . getOperand ( ImmOpNo ) ; if ( MCO . isImm ( ) && ! isInt < <NUM_LIT> > ( MCO . getImm ( ) ) && ! isUInt < <NUM_LIT> > ( MCO . getImm ( ) ) ) { return Error ( IDLoc , <STR_LIT> ) ;


<s> OutOps . push_back ( Op ) ; return false ;


<s> explicit <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) {


<s> case <STR_LIT> : case <STR_LIT> : return EmitLoweredSelect ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> :


<s> MCSection * findAssociatedSection ( ) const override { return getSubExpr ( ) -> findAssociatedSection ( ) ;


<s> if ( parseSymbolicImmVal ( ImmVal ) ) return true ; E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E , getContext ( ) ) ) ; return false ; } case AsmToken :: Equal : { SMLoc Loc = getLoc ( ) ; if ( Mnemonic != <STR_LIT> ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; const MCExpr * SubExprVal ; if ( getParser ( ) . parseExpression ( SubExprVal ) ) return true ; if ( Operands . size ( ) < <NUM_LIT> || ! static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) . isScalarReg ( ) ) return Error ( Loc , <STR_LIT> ) ; bool IsXReg = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Operands [ <NUM_LIT> ] -> getReg ( ) ) ; MCContext & Ctx = getContext ( ) ; E = SMLoc :: getFromPointer ( Loc . getPointer ( ) - <NUM_LIT> ) ; if ( isa < MCConstantExpr > ( SubExprVal ) ) { uint64_t Imm = ( cast < MCConstantExpr > ( SubExprVal ) ) -> getValue ( ) ; uint32_t ShiftAmt = <NUM_LIT> , MaxShiftAmt = IsXReg ? <NUM_LIT> : <NUM_LIT> ; while ( Imm > <NUM_LIT> && countTrailingZeros ( Imm ) >= <NUM_LIT> ) { ShiftAmt += <NUM_LIT> ; Imm >>= <NUM_LIT> ; } if ( ShiftAmt <= MaxShiftAmt && Imm <= <NUM_LIT> ) { Operands [ <NUM_LIT> ] = <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , Loc , Ctx ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( Imm , Ctx ) , S , E , Ctx ) ) ;

if ( ShiftAmt ) Operands . push_back ( <ISA_LIT>Operand :: CreateShiftExtend ( <STR_LIT> , ShiftAmt , true , S , E , Ctx ) ) ;


<s> bool enablePostRAScheduler ( ) const {


<s> if ( ST -> isThumb1Only ( ) ) { if ( Val <= <NUM_LIT> || ~ Val <= <NUM_LIT> ) return DAG . getConstant ( Val , <STR_LIT> ) ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> || <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return DAG . getConstant ( Val , <STR_LIT> ) ;


<s> if ( Subtarget -> getGeneration ( ) >= <ISA_LIT>Subtarget :: SEA_ISLANDS || Subtarget -> unsafeDSOffsetFoldingEnabled ( ) ) return true ; return CurDAG -> SignBitIsZero ( Base ) ;


<s> } for ( available = regs_available_for_popping , required = regs_to_pop ; required != <NUM_LIT> && available != <NUM_LIT> ; available &= ~ ( available & - available ) , required &= ~ ( required & - required ) ) -- pops_needed ; if ( available > <NUM_LIT> ) regs_available_for_popping &= ~ available ; else if ( pops_needed ) { if ( regs_available_for_popping == <NUM_LIT> && reg_containing_return_addr == LAST_ARG_REGNUM ) { asm_fprintf ( f , <STR_LIT> , LR_REGNUM , LAST_ARG_REGNUM ) ; reg_containing_return_addr = LR_REGNUM ; } else if ( size > <NUM_LIT> ) { restore_a4 = TRUE ; asm_fprintf ( f , <STR_LIT> , IP_REGNUM , LAST_ARG_REGNUM ) ; } if ( reg_containing_return_addr != LAST_ARG_REGNUM ) { regs_available_for_popping |= <NUM_LIT> << LAST_ARG_REGNUM ; -- pops_needed ; } } thumb_pop ( f , regs_available_for_popping ) ; if ( reg_containing_return_addr == - <NUM_LIT> ) { regs_to_pop &= ~ ( <NUM_LIT> << LR_REGNUM ) ; reg_containing_return_addr = number_of_first_bit_set ( regs_available_for_popping ) ; regs_available_for_popping &= ~ ( <NUM_LIT> << reg_containing_return_addr ) ; } if ( regs_available_for_popping ) { int frame_pointer ; frame_pointer = number_of_first_bit_set ( regs_available_for_popping ) ; asm_fprintf ( f , <STR_LIT> , ARM_HARD_FRAME_POINTER_REGNUM , frame_pointer ) ; regs_available_for_popping &= ~ ( <NUM_LIT> << frame_pointer ) ; regs_to_pop &= ~ ( <NUM_LIT> << ARM_HARD_FRAME_POINTER_REGNUM ) ; if ( regs_available_for_popping ) { int stack_pointer ; stack_pointer = number_of_first_bit_set ( regs_available_for_popping ) ; asm_fprintf ( f , <STR_LIT> , SP_REGNUM , stack_pointer ) ; } else { regs_available_for_popping |= ( <NUM_LIT> << frame_pointer ) ; } } if ( regs_available_for_popping == <NUM_LIT> && pops_needed > <NUM_LIT> ) { regs_available_for_popping |= <NUM_LIT> << reg_containing_return_addr ; asm_fprintf ( f , <STR_LIT> , LR_REGNUM , reg_containing_return_addr ) ; reg_containing_return_addr = LR_REGNUM ; } if ( pops_needed > <NUM_LIT> ) { int popped_into ; int move_to ; thumb_pop ( f , regs_available_for_popping ) ; popped_into = number_of_first_bit_set ( regs_available_for_popping ) ; move_to = number_of_first_bit_set ( regs_to_pop ) ; asm_fprintf ( f , <STR_LIT> , move_to , popped_into ) ; regs_to_pop &= ~ ( <NUM_LIT> << move_to ) ; -- pops_needed ; } if ( pops_needed > <NUM_LIT> ) { int popped_into ; thumb_pop ( f , regs_available_for_popping ) ; popped_into = number_of_first_bit_set ( regs_available_for_popping ) ; asm_fprintf ( f , <STR_LIT> , SP_REGNUM , popped_into ) ; } if ( restore_a4 ) {

if ( reg_containing_return_addr != LR_REGNUM ) {


<s> const auto * MLoad = cast < MaskedLoadSDNode > ( Op ) ; Mask = MLoad -> getMask ( ) ; PassThru = MLoad -> getPassThru ( ) ; } MVT XLenVT = Subtarget . getXLenVT ( ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , ContainerVT . getVectorElementCount ( ) ) ; Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ; PassThru = convertToScalableVector ( ContainerVT , PassThru , DAG , Subtarget ) ; }

if ( ! VL ) VL = getDefaultVLOps ( VT , ContainerVT , DL , DAG , Subtarget ) . second ;


<s> unsigned CPI = MCP . getConstantPoolIndex ( cast < Constant > ( CFP ) , Align ) ; unsigned ADRPReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( ADRPReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printBrigSegCvtModifierMask ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { switch ( MI -> getOperand ( OpNo ) . getImm ( ) ) {


<s> if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true ;


<s> Deleted . clear ( ) ; NodeAddr < FuncNode * > FA = DFG -> getFunc ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Print < NodeAddr < FuncNode * >> ( FA , * DFG ) << <STR_LIT> ) ; for ( NodeAddr < BlockNode * > BA : FA . Addr -> members ( * DFG ) ) Changed |= processBlock ( BA ) ; for ( auto MI : Deleted ) MI -> eraseFromParent ( ) ;


<s> obstack_grow ( & m_string_obstack , name , strlen ( name ) ) ;


<s> MachineInstr * <ISA_LIT>FrameLowering :: emitStackProbeInlineStub ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL , bool InProlog ) const { assert ( InProlog && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) ;


<s> unsigned Reg ; int64_t Offset ; L = getLoc ( ) ;

if ( parseRegisterInRange ( Reg , <STR_LIT> , <STR_LIT> , <STR_LIT> ) || parseComma ( ) || parseImmExpr ( Offset ) ) return true ;


getAdrLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const {


<s> unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( size == <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned type = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ; if ( type == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ;

unsigned load = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> enum rtx_code code = GET_CODE ( op ) ; rtx op0 = XEXP ( op , <NUM_LIT> ) ; rtx op1 = XEXP ( op , <NUM_LIT> ) ; machine_mode compare_mode = GET_MODE ( op0 ) ; machine_mode result_mode = GET_MODE ( dest ) ; bool max_p = false ; if ( result_mode != compare_mode ) return <NUM_LIT> ; if ( code == GE || code == GT ) max_p = true ; else if ( code == LE || code == LT ) max_p = false ; else return <NUM_LIT> ; if ( rtx_equal_p ( op0 , true_cond ) && rtx_equal_p ( op1 , false_cond ) ) ; else if ( rtx_equal_p ( op1 , true_cond ) && rtx_equal_p ( op0 , false_cond ) ) max_p = ! max_p ; else return <NUM_LIT> ; rs6000_emit_minmax ( dest , max_p ? SMAX : SMIN , op0 , op1 ) ; return <NUM_LIT> ;


<s> assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_ACC ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT> ;

return RegIdx . RegInfo -> getRegClass ( ClassID ) . getRegister ( RegIdx . Index ) ;


<s> return MCDisassembler :: Fail ; } StringRef Name = Symbol . Name ; if ( Symbol . Type == ELF :: STT_OBJECT && Name . endswith ( StringRef ( <STR_LIT> ) ) ) { Size = <NUM_LIT> ; return decodeKernelDescriptor ( Name . drop_back ( <NUM_LIT> ) , Bytes , Address ) ; } return None ;


<s> int easy_di_const ( rtx op ) { rtx high_rtx , low_rtx ; HOST_WIDE_INT high , low ; split_double ( op , & high_rtx , & low_rtx ) ;


<s> Tile64Subtarget :: Tile64Subtarget ( StringRef TT , StringRef CPU , StringRef FS ) : Tile64GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( CPU . str ( ) ) { ParseSubtargetFeatures ( CPU , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ;


<s> const struct cpu_regmove_cost * regmove_cost = aarch64_tune_params . regmove_cost ; if ( to == TAILCALL_ADDR_REGS || to == POINTER_REGS ) to = GENERAL_REGS ; if ( from == TAILCALL_ADDR_REGS || from == POINTER_REGS ) from = GENERAL_REGS ; if ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL && hard_reg_set_subset_p ( reg_class_contents [ from_i ] , reg_class_contents [ FFR_REGS ] ) ) return <NUM_LIT> ; if ( ( from == GENERAL_REGS && to == STACK_REG ) || ( to == GENERAL_REGS && from == STACK_REG ) ) return regmove_cost -> GP2GP ; if ( to == STACK_REG || from == STACK_REG ) return aarch64_register_move_cost ( mode , from , GENERAL_REGS ) + aarch64_register_move_cost ( mode , GENERAL_REGS , to ) ; if ( known_eq ( GET_MODE_SIZE ( mode ) , <NUM_LIT> ) ) { if ( from == GENERAL_REGS && to == GENERAL_REGS ) return regmove_cost -> GP2GP * <NUM_LIT> ; else if ( from == GENERAL_REGS ) return regmove_cost -> GP2FP * <NUM_LIT> ; else if ( to == GENERAL_REGS ) return regmove_cost -> FP2GP * <NUM_LIT> ; if ( ! TARGET_SIMD ) return regmove_cost -> GP2FP + regmove_cost -> FP2GP + regmove_cost -> FP2FP ; return regmove_cost -> FP2FP ; } if ( from == GENERAL_REGS && to == GENERAL_REGS ) return regmove_cost -> GP2GP ; else if ( from == GENERAL_REGS ) return regmove_cost -> GP2FP ;

else if ( to == GENERAL_REGS ) return regmove_cost -> FP2GP ;


<s> assert ( K != TargetTransformInfo :: RGK_Scalar ) ;

return K == TargetTransformInfo :: RGK_FixedWidthVector ;


<s> EVT SrcVT = TLI . getValueType ( Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; if ( DestVT != <STR_LIT> && DestVT != <STR_LIT> && DestVT != <STR_LIT> ) return false ;

unsigned SrcReg = getRegForValue ( Src ) ;


<s> addPass ( create<ISA_LIT>LowerRefTypesIntPtrConv ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerSETCC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Cond = createFPCmp ( DAG , Op ) ; assert ( Cond . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ;

SDValue True = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> printMemReference ( MI , OpNo , O ) ;


<s> static bool isHWRegProducer ( const MachineInstr & MI ) { if ( MI . getNumDefs ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return isHWReg ( MI , <NUM_LIT> ) ;


<s> static SDValue extract128BitVector ( SDValue Vec , unsigned IdxVal , SelectionDAG & DAG , const SDLoc & dl ) { assert ( ( Vec . getValueType ( ) . is256BitVector ( ) || Vec . getValueType ( ) . is512BitVector ( ) ) && <STR_LIT> ) ; return extractSubVector ( Vec , IdxVal , DAG , dl , <NUM_LIT> ) ;


<s> USItype c = <NUM_LIT> ; while ( a != <NUM_LIT> ) {


<s> MachineFunctionProperties getRequiredProperties ( ) const override { return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ;


<s> Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOVolatile | MachineMemOperand :: MOLoad ;


<s> { static unsigned seqno ; char buf [ <NUM_LIT> ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; else emit_insn ( gen_auipcsi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ; * low_out = gen_rtx_LO_SUM ( Pmode , temp , label ) ; seqno ++ ; } break ; default : gcc_unreachable ( ) ; }


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) {

addPass ( create<ISA_LIT>BranchFinalizePass ( ) ) ;


<s> int sh_loop_align ( rtx_insn * label ) { rtx_insn * next = label ; if ( ! optimize || optimize_size ) return <NUM_LIT> ; do next = next_nonnote_insn ( next ) ; while ( next && LABEL_P ( next ) ) ;

if ( ! next || ! INSN_P ( next ) || recog_memoized ( next ) == CODE_FOR_consttable_2 ) return <NUM_LIT> ;


<s> return <NUM_LIT> * TargetTransformInfo :: TCC_Basic ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { unsigned Opc = <STR_LIT> ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; MachineFunction & MF = DAG . getMachineFunction ( ) ; CCState CCInfo ( CallConv , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; if ( MF . getFunction ( ) . getReturnType ( ) -> isAggregateType ( ) ) { fail ( DL , DAG , <STR_LIT> ) ; return DAG . getNode ( Opc , DL , <STR_LIT> , Chain ) ; } CCInfo . AnalyzeReturn ( Outs , getHasAlu32 ( ) ? RetCC_<ISA_LIT>32 : RetCC_<ISA_LIT>64 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ;

for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) {


<s> MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> void addHI32DSPAsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getHI32DSPReg ( ) ) ) ;


<s> CopyGeneration ( BitTracker & bt , const <ISA_LIT>InstrInfo & hii , const <ISA_LIT>RegisterInfo & hri , MachineRegisterInfo & mri ) : Transformation ( true ) , HII ( hii ) , HRI ( hri ) , MRI ( mri ) , BT ( bt ) {


<s> streamer . EmitFunctionEntryLabel ( CurrentFnSym -> getName ( ) ) ;


<s> case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; default :


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> MapSignedDivide ( ) : MapDivide ( false ) {