<s> bool <ISA_LIT>16FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction * MF = MBB . getParent ( ) ; MachineBasicBlock * EntryBlock = & MF -> front ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; bool IsRAAndRetAddrIsTaken = ( Reg == <STR_LIT> ) && MF -> getFrameInfo ( ) -> isReturnAddressTaken ( ) ; if ( ! IsRAAndRetAddrIsTaken ) EntryBlock -> addLiveIn ( Reg ) ; } return true ;


<s> static void s390_code_end ( void ) { int i ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( indirect_branch_z10thunk_mask & ( <NUM_LIT> << i ) ) s390_output_indirect_thunk_function ( i , true ) ; if ( indirect_branch_prez10thunk_mask & ( <NUM_LIT> << i ) ) s390_output_indirect_thunk_function ( i , false ) ; } if ( TARGET_INDIRECT_BRANCH_TABLE ) { int o ; int i ; for ( o = <NUM_LIT> ; o < INDIRECT_BRANCH_NUM_OPTIONS ; o ++ ) { if ( indirect_branch_table_label_no [ o ] == <NUM_LIT> ) continue ; switch_to_section ( get_section ( indirect_branch_table_name [ o ] , <NUM_LIT> , NULL_TREE ) ) ; for ( i = <NUM_LIT> ; i < indirect_branch_table_label_no [ o ] ; i ++ ) { char label_start [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( label_start , indirect_branch_table_label [ o ] , i ) ; fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , label_start ) ; fputs ( <STR_LIT> , asm_out_file ) ; } } }


<s> Function * Caller = CB . getCaller ( ) ; Function * Callee = CB . getCalledFunction ( ) ; bool InlineHint = Callee && ! Callee -> isDeclaration ( ) && Callee -> hasFnAttribute ( Attribute :: InlineHint ) ; if ( InlineHint && Params . HintThreshold && Params . HintThreshold > Thres && ! Caller -> hasFnAttribute ( Attribute :: MinSize ) ) Thres = Params . HintThreshold . getValue ( ) * TTIWP -> getTTI ( * Callee ) . getInliningThresholdMultiplier ( ) ; const DataLayout & DL = Caller -> getParent ( ) -> getDataLayout ( ) ; if ( ! Callee ) return ( unsigned ) Thres ; uint64_t AllocaSize = <NUM_LIT> ; SmallPtrSet < const AllocaInst * , <NUM_LIT> > AIVisited ; for ( Value * PtrArg : CB . args ( ) ) { PointerType * Ty = dyn_cast < PointerType > ( PtrArg -> getType ( ) ) ;

if ( ! Ty || ( Ty -> getAddressSpace ( ) != <ISA_LIT>AS :: PRIVATE_ADDRESS && Ty -> getAddressSpace ( ) != <ISA_LIT>AS :: FLAT_ADDRESS ) ) continue ;


<s> static bool mips_use_debug_exception_return_p ( tree type ) { return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) != NULL ;


<s> unsigned getCoproc ( ) const { assert ( ( Kind == k_CoprocNum || Kind == k_CoprocReg ) && <STR_LIT> ) ; return Cop . Val ;


<s> assert ( Reg != <NUM_LIT> && <STR_LIT> ) ; ScratchWaveOffsetReg = Reg ;


<s> if ( ( old_flags ^ target_flags ) & ( MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH4 ) ) return _ ( <STR_LIT> ) ; if ( ( old_flags ^ target_flags ) & MASK_HITACHI ) return _ ( <STR_LIT> ) ; if ( ( old_flags ^ target_flags ) & MASK_LITTLE_ENDIAN ) return _ ( <STR_LIT> ) ;


<s> if ( ix86_expand_sse_fp_minmax ( operands [ <NUM_LIT> ] , code , op0 , op1 , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) return true ; tmp = ix86_expand_sse_cmp ( operands [ <NUM_LIT> ] , code , op0 , op1 , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; ix86_expand_sse_movcc ( operands [ <NUM_LIT> ] , tmp , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true ; } if ( GET_MODE ( op0 ) == TImode || ( GET_MODE ( op0 ) == DImode && ! TARGET_64BIT ) ) return false ; compare_op = ix86_expand_compare ( code , op0 , op1 ) ; if ( ! fcmov_comparison_operator ( compare_op , VOIDmode ) ) { tmp = gen_reg_rtx ( QImode ) ; ix86_expand_setcc ( tmp , code , op0 , op1 ) ; compare_op = ix86_expand_compare ( NE , tmp , const0_rtx ) ; }

emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_IF_THEN_ELSE ( mode , compare_op , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectUnMergeValues ( MachineInstr & MI ) { Register Lo = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Hi = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineIRBuilder Builder ( MI ) ; MachineInstr * SrcMI = getDefIgnoringCopies ( Src , * Builder . getMRI ( ) ) ; Optional < std :: pair < Register , Register >> LoHi ; switch ( SrcMI -> getOpcode ( ) ) { case <STR_LIT> : LoHi = selectFrameIndexLoHi ( * SrcMI ) ; break ; case <STR_LIT> : case <STR_LIT> : LoHi = selectAddrLoHi ( * SrcMI ) ; break ; } MachineInstrBuilder LoCopy ; MachineInstrBuilder HiCopy ; if ( LoHi ) { LoCopy = Builder . buildCopy ( Lo , LoHi -> first ) ; HiCopy = Builder . buildCopy ( Hi , LoHi -> second ) ; } else { LoCopy = Builder . buildCopy ( Lo , Src ) ; LoCopy -> getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; HiCopy = Builder . buildCopy ( Hi , Src ) ; HiCopy -> getOperand ( <NUM_LIT> ) . setSubReg ( <STR_LIT> ) ; } constrainGenericOp ( * LoCopy ) ; constrainGenericOp ( * HiCopy ) ; MI . eraseFromParent ( ) ;


<s> break ; case ADDRESS_CONST_INT : fprintf ( file , <STR_LIT> , reg_names [ REGNO ( info . regA ) ] ) ; output_addr_const ( file , info . offset ) ; break ; case ADDRESS_SYMBOLIC : case ADDRESS_SYMBOLIC_TXT_REL : case ADDRESS_GOTOFF : case ADDRESS_PLT : case ADDRESS_TLS : if ( info . regA ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( info . regA ) ] ) ; output_addr_const ( file , info . symbol ) ; if ( type == ADDRESS_GOTOFF ) { fputs ( <STR_LIT> , file ) ; } else if ( type == ADDRESS_PLT ) { fputs ( <STR_LIT> , file ) ; } else if ( type == ADDRESS_SYMBOLIC_TXT_REL ) { if ( info . offset != NULL && CONST_INT_P ( info . offset ) && INTVAL ( info . offset ) > <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , info . offset ) ; } fputs ( <STR_LIT> , file ) ; }


<s> int NumBytes = ( int ) MFI -> getStackSize ( ) ; const unsigned * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( ! AFI -> hasStackFrame ( ) ) { if ( NumBytes != <NUM_LIT> ) emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } else { if ( MBBI != MBB . begin ( ) ) { do -- MBBI ; while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ; } NumBytes -= ( AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitThumbRegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , TII , * RegInfo ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } else { if ( MBBI -> getOpcode ( ) == <STR_LIT> && & MBB . front ( ) != MBBI && prior ( MBBI ) -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator PMBBI = prior ( MBBI ) ; emitSPUpdate ( MBB , PMBBI , TII , dl , * RegInfo , NumBytes ) ; } else emitSPUpdate ( MBB , MBBI , TII , dl , * RegInfo , NumBytes ) ; } } if ( VARegSaveSize ) { while ( MBBI != MBB . end ( ) && isCSRestore ( MBBI , CSRegs ) ) ++ MBBI ;

AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ) . addReg ( <STR_LIT> , RegState :: Define ) ;


<s> unsigned NumElts = AccessSize / EltSize ; if ( AccessSize != EltSize * NumElts ) return <NUM_LIT> ; if ( Idx + NumElts > ValueVTs . size ( ) ) return <NUM_LIT> ; if ( NumElts != <NUM_LIT> && NumElts != <NUM_LIT> ) return <NUM_LIT> ;

for ( unsigned j = Idx + <NUM_LIT> ; j < Idx + NumElts ; ++ j ) {


<s> bool <ISA_LIT>TargetLowering :: isHvxOperation ( SDNode * N , SelectionDAG & DAG ) const { if ( ! Subtarget . useHVXOps ( ) ) return false ; auto IsHvxTy = [ this ] ( EVT Ty ) { return Ty . isSimple ( ) && Subtarget . isHVXVectorType ( Ty . getSimpleVT ( ) , true ) ; } ; auto IsHvxOp = [ this ] ( SDValue Op ) { return Op . getValueType ( ) . isSimple ( ) && Subtarget . isHVXVectorType ( ty ( Op ) , true ) ; } ; if ( llvm :: any_of ( N -> values ( ) , IsHvxTy ) || llvm :: any_of ( N -> ops ( ) , IsHvxOp ) ) return true ; auto IsWidenedToHvx = [ this , & DAG ] ( SDValue Op ) { if ( ! Op . getValueType ( ) . isSimple ( ) ) return false ; MVT ValTy = ty ( Op ) ; return ValTy . isVector ( ) && shouldWidenToHvx ( ValTy , DAG ) ; } ; for ( int i = <NUM_LIT> , e = N -> getNumValues ( ) ; i != e ; ++ i ) { if ( IsWidenedToHvx ( SDValue ( N , i ) ) ) return true ; } return llvm :: any_of ( N -> ops ( ) , IsWidenedToHvx ) ;


<s> if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Val = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; unsigned Width ; if ( ! Val . getAsInteger ( <NUM_LIT> , Width ) ) { Key += <STR_LIT> ; Key += Val ; PreferVectorWidthOverride = Width ; } } FS = Key . slice ( CPU . size ( ) , CPUFSWidth ) ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , Options . StackAlignmentOverride , PreferVectorWidthOverride ) ; } return I . get ( ) ;


<s> InsertNOPsLoadStore = false ; std :: string CPUName = CPU ; if ( CPUName . empty ( ) ) CPUName = ( Is64Bit ) ? <STR_LIT> : <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; if ( ! IsV9 ) UsePopc = false ;


<s> case <STR_LIT> : return SelectAdd ( N ) ; case <STR_LIT> : return SelectSHL ( N ) ; case <STR_LIT> : return SelectLoad ( N ) ; case <STR_LIT> : return SelectStore ( N ) ; case <STR_LIT> : return SelectSelect ( N ) ; case <STR_LIT> : return SelectTruncate ( N ) ; case <STR_LIT> : return SelectMul ( N ) ; case <STR_LIT> :


<s> Uses . push_back ( Extract ) ; } if ( ExtractedElements != <NUM_LIT> ) return SDValue ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; SDValue Vals [ <NUM_LIT> ] ; if ( TLI . isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Cst = DAG . getBitcast ( <STR_LIT> , InputVector ) ; auto & DL = DAG . getDataLayout ( ) ; EVT VecIdxTy = DAG . getTargetLoweringInfo ( ) . getVectorIdxTy ( DL ) ; SDValue BottomHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue TopHalf = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cst , DAG . getConstant ( <NUM_LIT> , dl , VecIdxTy ) ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , dl , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( <STR_LIT> , DL ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BottomHalf , ShAmt ) ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf ) ; Vals [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TopHalf , ShAmt ) ) ; } else { SDValue StackPtr = DAG . CreateStackTemporary ( InputVector . getValueType ( ) ) ; SDValue Ch = DAG . getStore ( DAG . getEntryNode ( ) , dl , InputVector , StackPtr , MachinePointerInfo ( ) ) ; EVT ElementType = InputVector . getValueType ( ) . getVectorElementType ( ) ; unsigned EltSize = ElementType . getSizeInBits ( ) / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t Offset = EltSize * i ; auto PtrVT = TLI . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue OffsetVal = DAG . getConstant ( Offset , dl , PtrVT ) ; SDValue ScalarAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackPtr , OffsetVal ) ; Vals [ i ] = DAG . getLoad ( ElementType , dl , Ch , ScalarAddr , MachinePointerInfo ( ) ) ; } } for ( SmallVectorImpl < SDNode * > :: iterator UI = Uses . begin ( ) , UE = Uses . end ( ) ; UI != UE ; ++ UI ) { SDNode * Extract = * UI ; SDValue Idx = Extract -> getOperand ( <NUM_LIT> ) ;

uint64_t IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ;


<s> SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; assert ( VT != <STR_LIT> && <STR_LIT> ) ; if ( HasSSE2 && VT == <STR_LIT> ) return getTargetShuffleNode ( <STR_LIT> , dl , VT , V1 , V2 , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VT , getTargetShuffleNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V2 ) , DAG ) ) ;


<s> Results . push_back ( lowerFP_TO_<ISA_LIT>NT ( N -> getOperand ( <NUM_LIT> ) , DAG ) ) ; return ; } SDValue Result ; if ( expandFP_TO_<ISA_LIT>NT ( N , Result , DAG ) ) Results . push_back ( Result ) ; return ; } case <STR_LIT> : { SDValue Op = SDValue ( N , <NUM_LIT> ) ; SDValue RES = LowerSDIVREM ( Op , DAG ) ; Results . push_back ( RES ) ; Results . push_back ( RES . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { SDValue Op = SDValue ( N , <NUM_LIT> ) ; LowerUDIVREM64 ( Op , DAG , Results ) ;


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; } computeRegisterProperties ( Subtarget -> getRegisterInfo ( ) ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto T : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , T , Legal ) ; for ( auto CC : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setCondCodeAction ( CC , T , Expand ) ; for ( auto Op : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Op , T , Expand ) ; for ( auto Op : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Op , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Expand ) ; setOperationAction ( <STR_LIT> , T , Expand ) ; setLoadExtAction ( <STR_LIT> , T , <STR_LIT> , Expand ) ; setTruncStoreAction ( T , <STR_LIT> , Expand ) ; }


<s> SDValue DescAddr = LowerGlobalAddressDarwin ( Op , DAG ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( * F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ;

return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>IntelInstPrinter :: printU8Imm ( const MCInst * MI , unsigned Op , raw_ostream & O ) { if ( MI -> getOperand ( Op ) . isExpr ( ) ) return MI -> getOperand ( Op ) . getExpr ( ) -> print ( O , & MAI ) ; O << formatImm ( MI -> getOperand ( Op ) . getImm ( ) & <NUM_LIT> ) ;


<s> if ( TARGET_PIC ) { if ( GET_CODE ( oldx ) == SYMBOL_REF || GET_CODE ( oldx ) == LABEL_REF ) { rtx ptr = gen_reg_rtx ( Pmode ) ;

emit_insn ( gen_rtx_SET ( VOIDmode , ptr , gen_rtx_LO_SUM ( pic_reg , oldx ) ) ) ;


<s> for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OS << '\x7' ; return true ;


<s> MF = & MFParm ; TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ;


<s> Register LoReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register HiReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DstRC = & <STR_LIT> ; int FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getMoveF64FrameIndex ( MF ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( MF , FI ) ; MachineMemOperand * MMOLo = MF . getMachineMemOperand ( MPI , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; MachineMemOperand * MMOHi = MF . getMachineMemOperand ( MPI . getWithOffset ( <NUM_LIT> ) , MachineMemOperand :: MOStore , <NUM_LIT> , Align ( <NUM_LIT> ) ) ;

BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( LoReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMOLo ) ;


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : return SelectIndexedLoad ( N ) ; case <STR_LIT> : return SelectIndexedStore ( N ) ; case <STR_LIT> : return SelectFrameIndex ( N ) ; case <STR_LIT> : return ConstantToRegisterExpand ( N , SDValue ( N , <NUM_LIT> ) ) . getNode ( ) ; case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SelectTargetGlobalAddressforADD ( N , N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; break ; case <STR_LIT> : return SelectCompare ( N ) ; case <STR_LIT> : return SelectConditionalBranch ( N ) ; case <STR_LIT> : if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; const GlobalValue * GV = GA -> getGlobal ( ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext & ctx ) : MCII ( mcii ) , STI ( sti ) , Ctx ( ctx ) {


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return false ;

return ( VT . getVectorNumElements ( ) == <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isMOVLMask ( M , VT ) || isSHUFPMask ( M , VT , Subtarget -> hasAVX ( ) ) || isPSHUFDMask ( M , VT ) || isPSHUFHWMask ( M , VT ) || isPSHUFLWMask ( M , VT ) || isPALIGNRMask ( M , VT , Subtarget ) || isUNPCKLMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKHMask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKL_v_undef_Mask ( M , VT , Subtarget -> hasAVX2 ( ) ) || isUNPCKH_v_undef_Mask ( M , VT , Subtarget -> hasAVX2 ( ) ) ) ;


<s> return Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC | ELF :: SHF_WRITE | ELF :: SHF_<ISA_LIT>_HSA_GLOBAL ) ;


<s> static SDValue performFirstTrueTestVectorCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { assert ( N -> getOpcode ( ) == <STR_LIT> ) ; if ( ! Subtarget -> hasSVE ( ) || DCI . isBeforeLegalize ( ) ) return SDValue ( ) ; SDValue SetCC = N -> getOperand ( <NUM_LIT> ) ; EVT VT = SetCC . getValueType ( ) ; if ( ! VT . isScalableVector ( ) || VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; auto * Idx = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Idx || ! Idx -> isZero ( ) || SetCC . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Pg = getPTrue ( DAG , SDLoc ( N ) , VT , <STR_LIT> ) ; return getPTest ( DAG , N -> getValueType ( <NUM_LIT> ) , Pg , SetCC , <STR_LIT> ) ;


<s> OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; getTargetStreamer ( ) -> EmitCodeEnd ( ) ; } return AsmPrinter :: doFinalization ( M ) ;


<s> emit<ISA_LIT>Adjustment ( MF , MBB , MBBI , - NumBytes , SAVErr , SAVEri ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; unsigned regFP = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , regFP ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createWindowSave ( nullptr ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; unsigned regInRA = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; unsigned regOutRA = RegInfo . getDwarfRegNum ( <STR_LIT> , true ) ; CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createRegister ( nullptr , regOutRA , regInRA ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; if ( NeedsStackRealignment ) { int MaxAlign = MFI -> getMaxAlignment ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( MaxAlign - <NUM_LIT> ) ;


<s> int check_use_sfunc_addr ( rtx insn , rtx reg ) { while ( ( insn = NEXT_INSN ( insn ) ) ) { if ( GET_CODE ( insn ) == CODE_LABEL || GET_CODE ( insn ) == JUMP_INSN ) break ; if ( ! INSN_P ( insn ) ) continue ; if ( GET_CODE ( PATTERN ( insn ) ) == SEQUENCE ) insn = XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( PATTERN ( insn ) ) != PARALLEL || get_attr_type ( insn ) != TYPE_SFUNC ) continue ; return rtx_equal_p ( extract_sfunc_addr ( insn ) , reg ) ;


<s> NodeAddr < StmtNode * > SA = AddAslUN . Addr -> getOwner ( * DFG ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * AddAslMI << <STR_LIT> ) ; NodeList UNodeList ; getAllRealUses ( SA , UNodeList ) ; for ( auto I = UNodeList . rbegin ( ) , E = UNodeList . rend ( ) ; I != E ; ++ I ) { NodeAddr < UseNode * > UseUN = * I ; assert ( ! ( UseUN . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) && <STR_LIT> ) ; NodeAddr < StmtNode * > UseIA = UseUN . Addr -> getOwner ( * DFG ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Print < NodeAddr < InstrNode * >> ( UseIA , * DFG ) << <STR_LIT> ) ; MachineInstr * UseMI = UseIA . Addr -> getCode ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * UseMI -> getParent ( ) ) << <STR_LIT> << * UseMI << <STR_LIT> ) ; const MCInstrDesc & UseMID = UseMI -> getDesc ( ) ; assert ( HII -> getAddrMode ( * UseMI ) == <STR_LIT> ) ; auto UsePos = MachineBasicBlock :: iterator ( UseMI ) ; MachineBasicBlock :: instr_iterator InsertPt = UsePos . getInstrIterator ( ) ; short NewOpCode = getBaseWithLongOffset ( * UseMI ) ; assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ; unsigned OpStart ; unsigned OpEnd = UseMI -> getNumOperands ( ) ; MachineBasicBlock * BB = UseMI -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * BB , InsertPt , UseMI -> getDebugLoc ( ) , HII -> get ( NewOpCode ) ) ; if ( UseMID . mayLoad ( ) ) { MIB . add ( UseMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( AddAslMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( AddAslMI -> getOperand ( <NUM_LIT> ) ) ; const GlobalValue * GV = ImmOp . getGlobal ( ) ; MIB . addGlobalAddress ( GV , UseMI -> getOperand ( <NUM_LIT> ) . getImm ( ) + ImmOp . getOffset ( ) , ImmOp . getTargetFlags ( ) ) ; OpStart = <NUM_LIT> ; } else if ( UseMID . mayStore ( ) ) { MIB . add ( AddAslMI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( AddAslMI -> getOperand ( <NUM_LIT> ) ) ; const GlobalValue * GV = ImmOp . getGlobal ( ) ; MIB . addGlobalAddress ( GV , UseMI -> getOperand ( <NUM_LIT> ) . getImm ( ) + ImmOp . getOffset ( ) , ImmOp . getTargetFlags ( ) ) ; MIB . add ( UseMI -> getOperand ( <NUM_LIT> ) ) ; OpStart = <NUM_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; for ( unsigned i = OpStart ; i < OpEnd ; ++ i ) MIB . add ( UseMI -> getOperand ( i ) ) ;


<s> static unsigned countMCSymbolRefExpr ( const MCExpr * Expr ) { if ( isa < MCSymbolRefExpr > ( Expr ) ) return <NUM_LIT> ; if ( const MCBinaryExpr * BExpr = dyn_cast < MCBinaryExpr > ( Expr ) ) return countMCSymbolRefExpr ( BExpr -> getLHS ( ) ) + countMCSymbolRefExpr ( BExpr -> getRHS ( ) ) ; if ( const MCUnaryExpr * UExpr = dyn_cast < MCUnaryExpr > ( Expr ) ) return countMCSymbolRefExpr ( UExpr -> getSubExpr ( ) ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;

RegisterAsmInfo < <ISA_LIT>TargetAsmInfo > Y ( The<ISA_LIT>Target ) ;


<s> SDValue GlobalBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) ; SDValue RelAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue AbsAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GlobalBase , RelAddr ) ;

return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , AbsAddr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> bool ExtraLoadRequired = Subtarget . GVRequiresExtraLoad ( GV , getTargetMachine ( ) , false ) ; SDValue Result ; if ( ! IsPic && ! ExtraLoadRequired ) { Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { unsigned char OpFlags = <NUM_LIT> ; if ( ExtraLoadRequired ) OpFlags = <STR_LIT> ; Result = DAG . getTargetGlobalAddress ( GV , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; }

Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned size = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( size == <NUM_LIT> && align == <NUM_LIT> ) return MCDisassembler :: Fail ; align *= ( <NUM_LIT> << size ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> bool <ISA_LIT>Packetizer :: runOnMachineFunction ( MachineFunction & MF ) { MF . getProperties ( ) . set ( MachineFunctionProperties :: Property :: FailsVerification ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = HST . getInstrInfo ( ) ; HRI = HST . getRegisterInfo ( ) ; auto & MLI = getAnalysis < MachineLoopInfo > ( ) ; auto * AA = & getAnalysis < AAResultsWrapperPass > ( ) . getAAResults ( ) ; auto * MBPI = & getAnalysis < MachineBranchProbabilityInfo > ( ) ; if ( EnableGenAllInsnClass ) HII -> genAllInsnTimingClasses ( MF ) ; bool MinOnly = Minimal || DisablePacketizer || ! HST . usePackets ( ) || skipFunction ( MF . getFunction ( ) ) ; <ISA_LIT>PacketizerList Packetizer ( MF , MLI , AA , MBPI , MinOnly ) ; assert ( Packetizer . getResourceTracker ( ) && <STR_LIT> ) ; for ( MachineBasicBlock & MB : MF ) { for ( MachineInstr & MI : llvm :: make_early_inc_range ( MB ) ) if ( MI . isKill ( ) ) MB . erase ( & MI ) ; } if ( HST . isTinyCoreWithDuplex ( ) ) HII -> translateInstrsForDup ( MF , true ) ; for ( auto & MB : MF ) { auto Begin = MB . begin ( ) , End = MB . end ( ) ; while ( Begin != End ) { MachineBasicBlock :: iterator RB = Begin ;

while ( RB != End && HII -> isSchedulingBoundary ( * RB , & MB , MF ) ) ++ RB ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: aarch64 , true > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> } LoadSDNode * LD = cast < LoadSDNode > ( N ) ; unsigned Align = LD -> getAlignment ( ) ; unsigned PrefAlign = TD -> getPrefTypeAlignment ( ResVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) , DL ) ) ;

SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ;


<s> return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( AddressSpace ) ) ;


<s> return addr_cost -> register_offset ; } } switch ( info . type ) { case ADDRESS_LO_SUM : case ADDRESS_SYMBOLIC : case ADDRESS_REG_IMM : cost += addr_cost -> imm_offset ; break ; case ADDRESS_REG_WB : if ( c == PRE_INC || c == PRE_DEC || c == PRE_MODIFY ) cost += addr_cost -> pre_modify ; else if ( c == POST_INC || c == POST_DEC || c == POST_MODIFY ) cost += addr_cost -> post_modify ; else gcc_unreachable ( ) ; break ; case ADDRESS_REG_REG : cost += addr_cost -> register_offset ; break ; case ADDRESS_REG_SXTW : cost += addr_cost -> register_sextend ; break ; case ADDRESS_REG_UXTW : cost += addr_cost -> register_zextend ; break ; default : gcc_unreachable ( ) ; }


<s> auto MMOFlags = Subtarget . hasInvariantFunctionDescriptors ( ) ? MachineMemOperand :: MOInvariant : MachineMemOperand :: MONone ; MachinePointerInfo MPI ( CS ? CS -> getCalledValue ( ) : nullptr ) ; SDValue LoadFuncPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , Callee , MPI , <NUM_LIT> , MMOFlags ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , AddPtr , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> , MMOFlags ) ; SDValue TOCOff = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , TOCOff ) ; SDValue TOCPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , AddTOC , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> , MMOFlags ) ; setUsesTOCBasePtr ( DAG ) ; SDValue TOCVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , TOCPtr , InFlag ) ; Chain = TOCVal . getValue ( <NUM_LIT> ) ; InFlag = TOCVal . getValue ( <NUM_LIT> ) ; if ( ! hasNest ) { SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ; } MTCTROps [ <NUM_LIT> ] = Chain ; MTCTROps [ <NUM_LIT> ] = LoadFuncPtr ; MTCTROps [ <NUM_LIT> ] = InFlag ; } Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , makeArrayRef ( MTCTROps , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; NodeTys . clear ( ) ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; Ops . push_back ( Chain ) ; CallOpc = <STR_LIT> ; Callee . setNode ( nullptr ) ;

if ( isSVR4ABI && is<ISA_LIT>64 && ! isELFv2ABI && ! hasNest ) Ops . push_back ( DAG . getRegister ( <STR_LIT> , PtrVT ) ) ;


<s> Use = false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) {


<s> gcc_assert ( DECL_P ( fun ) ) ; result = DECL_RESULT ( fun ) ; } else result = TREE_TYPE ( fntype ) ; if ( result && aggregate_value_p ( result , fntype ) ) { if ( ! TYPE_P ( result ) ) result = TREE_TYPE ( result ) ; result = build_pointer_type ( result ) ; rs6000_parm_needs_stack ( args_so_far , result ) ; } if ( incoming ) { tree parm ; for ( parm = DECL_ARGUMENTS ( fun ) ; parm && parm != void_list_node ; parm = TREE_CHAIN ( parm ) ) if ( rs6000_parm_needs_stack ( args_so_far , TREE_TYPE ( parm ) ) ) return true ; } else { function_args_iterator args_iter ; tree arg_type ; FOREACH_FUNCTION_ARGS ( fntype , arg_type , args_iter ) if ( rs6000_parm_needs_stack ( args_so_far , arg_type ) ) return true ; }


<s> MCInst I ; if ( Opcode == <STR_LIT> ) { unsigned Temp = Reg1 ; Reg1 = Reg2 ; Reg2 = Temp ; }


<s> void <ISA_LIT>Subtarget :: getPostRAMutations ( std :: vector < std :: unique_ptr < ScheduleDAGMutation >> & Mutations ) const {

Mutations . push_back ( llvm :: make_unique < MemOpClusterMutation > ( & InstrInfo ) ) ;


<s> bool hasOp1 ( unsigned Opc ) const { return OpSet1 . count ( Opc ) != <NUM_LIT> ;


<s> dbgs ( ) << <STR_LIT> << Disp << '\n' << <STR_LIT> ; if ( GV ) GV -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( CP ) CP -> dump ( ) ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << '\n' << <STR_LIT> ; if ( ES ) dbgs ( ) << ES ; else dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; if ( MCSym ) dbgs ( ) << MCSym ; else dbgs ( ) << <STR_LIT> ;

dbgs ( ) << <STR_LIT> << JT << <STR_LIT> << Alignment . value ( ) << '\n' ;


<s> void rs6000_expand_extract_even ( rtx target , rtx op0 , rtx op1 ) { machine_mode vmode = GET_MODE ( target ) ; unsigned i , nelt = GET_MODE_NUNITS ( vmode ) ; vec_perm_builder perm ( nelt , nelt , <NUM_LIT> ) ;

for ( i = <NUM_LIT> ; i < nelt ; i ++ ) perm . quick_push ( i * <NUM_LIT> ) ;


<s> int64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI . getOperand ( <NUM_LIT> ) . getReg ( ) << <STR_LIT> << Imm << <STR_LIT> ) ; MFI . setWAReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Imm ) ; } unsigned NumVRegs = MF . getRegInfo ( ) . getNumVirtRegs ( ) ; unsigned NumStackRegs = <NUM_LIT> ; unsigned CurReg = MFI . getParams ( ) . size ( ) ; for ( unsigned VRegIdx = <NUM_LIT> ; VRegIdx < NumVRegs ; ++ VRegIdx ) { Register VReg = Register :: index2VirtReg ( VRegIdx ) ; if ( MRI . use_empty ( VReg ) ) continue ; if ( MFI . isVRegStackified ( VReg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VReg << <STR_LIT> << ( INT32_MIN | NumStackRegs ) << <STR_LIT> ) ; MFI . setWAReg ( VReg , INT32_MIN | NumStackRegs ++ ) ; continue ; } if ( MFI . getWAReg ( VReg ) == <ISA_LIT>FunctionInfo :: UnusedReg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << VReg << <STR_LIT> << CurReg << <STR_LIT> ) ; MFI . setWAReg ( VReg , CurReg ++ ) ; }


<s> bool isSupported ( ) const { return Supported ;


<s> uint64_t src = pIsland . getParent ( ) -> getSection ( ) . addr ( ) + pIsland . offset ( ) + pIsland . size ( ) ; if ( isValidForADRP ( src , dest ) ) { m_pData = ADRP_TEMPLATE ; m_Name = <STR_LIT> ; m_Size = sizeof ( ADRP_TEMPLATE ) ; getFixupList ( ) . clear ( ) ;

addFixup ( <NUM_LIT> , <NUM_LIT> , llvm :: ELF :: R_AARCH64_ADR_PREL_PG_HI21 ) ;


<s> MCAsmBackend * create<ISA_LIT>AsmBackend ( Target const & T , MCRegisterInfo const & , const Triple & TT , StringRef CPU , const MCTargetOptions & Options ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new <ISA_LIT>AsmBackend ( T , OSABI , CPU ) ;


<s> static DecodeStatus DecodeStoreI64 ( MCInst & Inst , uint64_t insn , uint64_t Address , const void * Decoder ) { return DecodeMem ( Inst , insn , Address , Decoder , false , DecodeI64RegisterClass ) ;


<s> int ar7_reg_operand ( rtx op , enum machine_mode mode ) {

return c4x_arn_reg_operand ( op , mode , AR7_REGNO ) ;


<s> if ( MBB . isEHPad ( ) ) { Changed = true ; auto InsertPos = MBB . begin ( ) ; if ( InsertPos -> isEHLabel ( ) ) ++ InsertPos ; Register DstReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , InsertPos , MBB . begin ( ) -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , DstReg ) ;


<s> bool CS1Spilled = false ; bool LRSpilled = false ; unsigned NumGPRSpills = <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > UnspilledCS1GPRs ; SmallVector < unsigned , <NUM_LIT> > UnspilledCS2GPRs ; const <ISA_LIT>BaseRegisterInfo * RegInfo = static_cast < const <ISA_LIT>BaseRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned FramePtr = RegInfo -> getFrameRegister ( MF ) ; if ( AFI -> isThumb2Function ( ) && ( MFI -> hasVarSizedObjects ( ) || RegInfo -> needsStackRealignment ( MF ) ) ) MF . getRegInfo ( ) . setPhysRegUsed ( <STR_LIT> ) ; if ( AFI -> isThumb1OnlyFunction ( ) ) { if ( AFI -> getVarArgsRegSaveSize ( ) > <NUM_LIT> ) MF . getRegInfo ( ) . setPhysRegUsed ( <STR_LIT> ) ; unsigned StackSize = estimateStackSize ( MF ) ; if ( MFI -> hasVarSizedObjects ( ) || RegInfo -> needsStackRealignment ( MF ) || StackSize > <NUM_LIT> ) MF . getRegInfo ( ) . setPhysRegUsed ( <STR_LIT> ) ; } if ( RegInfo -> hasBasePointer ( MF ) ) MF . getRegInfo ( ) . setPhysRegUsed ( RegInfo -> getBaseRegister ( ) ) ; const unsigned * CSRegs = RegInfo -> getCalleeSavedRegs ( ) ; for ( unsigned i = <NUM_LIT> ; CSRegs [ i ] ; ++ i ) { unsigned Reg = CSRegs [ i ] ; bool Spilled = false ; if ( MF . getRegInfo ( ) . isPhysRegUsed ( Reg ) ) { Spilled = true ; CanEliminateFrame = false ; } else { for ( const unsigned * Aliases = RegInfo -> getAliasSet ( Reg ) ; * Aliases ; ++ Aliases ) { if ( MF . getRegInfo ( ) . isPhysRegUsed ( * Aliases ) ) { Spilled = true ; CanEliminateFrame = false ; } } } if ( ! <STR_LIT> -> contains ( Reg ) ) continue ; if ( Spilled ) { NumGPRSpills ++ ; if ( ! STI . isTargetDarwin ( ) ) { if ( Reg == <STR_LIT> ) LRSpilled = true ; CS1Spilled = true ; continue ; } switch ( Reg ) { case <STR_LIT> : LRSpilled = true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CS1Spilled = true ; break ; default :


<s> bool <ISA_LIT>FrameLowering :: assignCalleeSavedSpillSlots ( MachineFunction & MF , const TargetRegisterInfo * TRI , std :: vector < CalleeSavedInfo > & CSI ) const {


<s> const struct builtin_description * d ; size_t i ; * expandedp = true ; switch ( fcode ) { case PAIRED_BUILTIN_STX : return paired_expand_stv_builtin ( CODE_FOR_paired_stx , exp ) ; case PAIRED_BUILTIN_LX : return paired_expand_lv_builtin ( CODE_FOR_paired_lx , exp , target ) ; default : break ; } d = bdesc_paired_preds ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_paired_preds ) ; i ++ , d ++ ) if ( d -> code == fcode ) return paired_expand_predicate_builtin ( d -> icode , exp , target ) ; * expandedp = false ; return NULL_RTX ;


<s> MachineFunctionProperties getRequiredProperties ( ) const override {

return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ;


<s> static SDValue PerformLOADCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; EVT RegVT = Ld -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Ld -> getMemoryVT ( ) ; SDLoc dl ( Ld ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; <STR_LIT> Ext = Ld -> getExtensionType ( ) ; bool Fast ; unsigned AddressSpace = Ld -> getAddressSpace ( ) ; unsigned Alignment = Ld -> getAlignment ( ) ; if ( RegVT . is256BitVector ( ) && ! DCI . isBeforeLegalizeOps ( ) && Ext == <STR_LIT> && TLI . allowsMemoryAccess ( * DAG . getContext ( ) , DAG . getDataLayout ( ) , RegVT , AddressSpace , Alignment , & Fast ) && ! Fast ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ; if ( NumElems < <NUM_LIT> ) return SDValue ( ) ; SDValue Ptr = Ld -> getBasePtr ( ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Alignment ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , std :: min ( <NUM_LIT> , Alignment ) ) ; SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ; SDValue NewVec = DAG . getUNDEF ( RegVT ) ;

NewVec = Insert128BitVector ( NewVec , Load1 , <NUM_LIT> , DAG , dl ) ;


<s> static unsigned getStOpcode ( unsigned StSize , bool IsThumb1 , bool IsThumb2 ) { if ( StSize >= <NUM_LIT> ) return StSize == <NUM_LIT> ? <STR_LIT> : StSize == <NUM_LIT> ? <STR_LIT> : <NUM_LIT> ; if ( IsThumb1 ) return StSize == <NUM_LIT> ? <STR_LIT> : StSize == <NUM_LIT> ? <STR_LIT> : StSize == <NUM_LIT> ? <STR_LIT> : <NUM_LIT> ; if ( IsThumb2 ) return StSize == <NUM_LIT> ? <STR_LIT> : StSize == <NUM_LIT> ? <STR_LIT> : StSize == <NUM_LIT> ? <STR_LIT> : <NUM_LIT> ; return StSize == <NUM_LIT> ? <STR_LIT> : StSize == <NUM_LIT> ? <STR_LIT> : StSize == <NUM_LIT> ? <STR_LIT> : <NUM_LIT> ;


<s> unsigned Align = getStackAlignment ( ) ; int64_t Amount = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Amount = RoundUpToAlignment ( Amount , Align ) ; if ( ! IsDestroy ) Amount = - Amount ; if ( CalleePopAmount == <NUM_LIT> ) { assert ( Amount > - <NUM_LIT> && Amount < <NUM_LIT> && <STR_LIT> ) ; emitSPUpdate ( MBB , MI , dl , TII , <STR_LIT> , Amount ) ; } } else if ( CalleePopAmount != <NUM_LIT> ) { assert ( CalleePopAmount < <NUM_LIT> && <STR_LIT> ) ; emitSPUpdate ( MBB , MI , dl , TII , <STR_LIT> , - CalleePopAmount ) ;


<s> vpmaxnm_f32 ( float32x2_t a , float32x2_t b ) {

return __builtin_aarch64_smaxpv2sf ( a , b ) ;


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const { OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; MCOperand MCOp = LowerOperand ( MO ) ; if ( MCOp . isValid ( ) ) OutMI . addOperand ( MCOp ) ; }


<s> if ( Use -> isMachineOpcode ( ) ) { const TargetInstrDesc & TID = TII -> get ( Use -> getMachineOpcode ( ) ) ; if ( TID . mayStore ( ) ) return true ; unsigned Opcode = TID . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) return true ; return TII -> isFpMLxInstruction ( Opcode ) ; }


<s> void printThumbITMask ( const MCInst * MI , unsigned OpNum ) {


<s> <ISA_LIT>AsmBackend ( uint8_t OSABI , bool Is64Bit ) : MCAsmBackend ( ) , OSABI ( OSABI ) , Is64Bit ( Is64Bit ) {


<s> void addu32MustExtOperands ( MCInst & Inst , unsigned N ) const { addImmOperands ( Inst , N ) ;


<s> BitVector Reserved ( getNumRegs ( ) ) ; for ( size_t Reg = <NUM_LIT> ; Reg < getNumRegs ( ) ; Reg ++ ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isRegisterReservedByUser ( Reg ) ) markSuperRegs ( Reserved , Reg ) ; } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ;


<s> BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( i ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( j ) ) ; if ( ! BVN0 || ! BVN1 ) continue ; bool FoundMatch = true ; for ( unsigned k = <NUM_LIT> ; k < VT . getVectorNumElements ( ) ; ++ k ) { ConstantSDNode * CN0 = dyn_cast < ConstantSDNode > ( BVN0 -> getOperand ( k ) ) ; ConstantSDNode * CN1 = dyn_cast < ConstantSDNode > ( BVN1 -> getOperand ( k ) ) ; if ( ! CN0 || ! CN1 || CN0 -> getZExtValue ( ) != ( BitMask & ~ CN1 -> getZExtValue ( ) ) ) { FoundMatch = false ; break ; } } if ( FoundMatch ) return DAG . getNode ( <STR_LIT> , DL , VT , SDValue ( BVN0 , <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> - i ) , N1 -> getOperand ( <NUM_LIT> - j ) ) ; } return SDValue ( ) ;


<s> int32_t NumBytes = AFI -> getFramePtrSpillOffset ( ) ; unsigned FramePtr = RI . getFrameRegister ( MF ) ; assert ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) llvm :: emitT2RegPlusImmediate ( * MBB , MBBI , MI -> getDebugLoc ( ) , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , * AII ) ; else if ( AFI -> isThumbFunction ( ) ) llvm :: emitThumbRegPlusImmediate ( * MBB , MBBI , MI -> getDebugLoc ( ) , <STR_LIT> , FramePtr , - NumBytes , * AII , RI ) ; else llvm :: emit<ISA_LIT>RegPlusImmediate ( * MBB , MBBI , MI -> getDebugLoc ( ) , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , * AII ) ; if ( ! RI . needsStackRealignment ( MF ) ) return ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; unsigned MaxAlign = MFI -> getMaxAlignment ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) ) ; unsigned bicOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ;

AddDefaultCC ( AddDefaultPred ( BuildMI ( * MBB , MBBI , MI -> getDebugLoc ( ) , TII -> get ( bicOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( MaxAlign - <NUM_LIT> ) ) ) ;


<s> MachineInstr * RHSDef = getDefIgnoringCopies ( RHS . getReg ( ) , MRI ) ; CmpInst :: Predicate P = ( CmpInst :: Predicate ) Predicate . getPredicate ( ) ; const <STR_LIT> CC = changeICMPPredTo<ISA_LIT>CC ( P ) ; if ( IsCMN ( LHSDef , CC ) ) return emitCMN ( LHSDef -> getOperand ( <NUM_LIT> ) , RHS , MIRBuilder ) ; if ( IsCMN ( RHSDef , CC ) ) return emitCMN ( LHS , RHSDef -> getOperand ( <NUM_LIT> ) , MIRBuilder ) ; if ( ! isUnsignedICMPPred ( P ) && LHSDef && LHSDef -> getOpcode ( ) == TargetOpcode :: G_AND ) { auto ValAndVReg = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI ) ; if ( ! ValAndVReg || ValAndVReg -> Value != <NUM_LIT> ) return nullptr ; return emitTST ( LHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , LHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIRBuilder ) ;


<s> auto Int32Ty = IRB . getInt32Ty ( ) ; auto * GV = dyn_cast < GlobalVariable > ( M . getOrInsertGlobal ( Name , Int32Ty ) ) ;

if ( ! GV ) report_fatal_error ( Twine ( <STR_LIT> ) + Name ) ;


<s> } else if ( <STR_LIT> . contains ( BP ) ) { MinGPR = std :: min < unsigned > ( MinGPR , BP ) ; HasGPSaveArea = true ; } } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } for ( unsigned i = <NUM_LIT> , e = G8Regs . size ( ) ; i != e ; ++ i ) { int FI = G8Regs [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } unsigned MinReg = std :: min < unsigned > ( TRI -> getEncodingValue ( MinGPR ) , TRI -> getEncodingValue ( MinG8R ) ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } else { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } } if ( spillsCR ( MF ) && ! ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( ( Subtarget . isSVR4ABI ( ) && Reg == <STR_LIT> ) || ( ! Subtarget . isSVR4ABI ( ) && ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) ) ) { int FI = CSI [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } } LowerBound -= <NUM_LIT> ; } if ( HasVRSAVESaveArea ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { int FI = CSI [ i ] . getFrameIdx ( ) ; MFI . setObjectOffset ( FI , LowerBound + MFI . getObjectOffset ( FI ) ) ; } } LowerBound -= <NUM_LIT> ; } if ( HasVRSaveArea ) { assert ( LowerBound <= <NUM_LIT> && <STR_LIT> ) ; LowerBound &= ~ ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = VRegs . size ( ) ; i != e ; ++ i ) {

int FI = VRegs [ i ] . getFrameIdx ( ) ;


<s> b = ( __vector unsigned short ) vec_splats ( __B ) ; c = vec_avg ( a , b ) ;

return ( __builtin_unpack_vector_int128 ( ( __vector __int128 ) c , <NUM_LIT> ) ) ;


<s> static SDValue detectAVX512USatPattern ( SDValue In , EVT VT , const <ISA_LIT>Subtarget & Subtarget ) {

if ( ! isSATValidOnAVX512Subtarget ( In . getValueType ( ) , VT , Subtarget ) ) return SDValue ( ) ;


<s> int skip ; while ( ( skip = sh_symbian_get_strip_length ( * name ) ) ) name += skip ; return name ;


<s> MCContext & Ctx = AP . OutContext ; bool isDarwin = TM . getTargetTriple ( ) . isOSDarwin ( ) ; SmallString < <NUM_LIT> > Name ; StringRef Suffix ; if ( MO . getTargetFlags ( ) == <STR_LIT> ) { if ( isDarwin ) Suffix = <STR_LIT> ; } else if ( MO . getTargetFlags ( ) & <STR_LIT> ) Suffix = <STR_LIT> ; if ( ! Suffix . empty ( ) ) Name += DL . getPrivateGlobalPrefix ( ) ; unsigned PrefixLen = Name . size ( ) ; if ( ! MO . isGlobal ( ) ) { assert ( MO . isSymbol ( ) && <STR_LIT> ) ; Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else { const GlobalValue * GV = MO . getGlobal ( ) ; TM . getNameWithPrefix ( Name , GV , * Mang ) ; } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( Name ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; if ( MO . getTargetFlags ( ) == <STR_LIT> && isDarwin ) { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( AP ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AP . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . getOrCreateSymbol ( OrigName ) , false ) ; } return Sym ; } if ( MO . getTargetFlags ( ) & <STR_LIT> ) { MachineModuleInfoMachO & MachO = getMachOMMI ( AP ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = ( MO . getTargetFlags ( ) & <STR_LIT> ) ? MachO . getHiddenGVStubEntry ( Sym ) : MachO . getGVStubEntry ( Sym ) ;


<s> StringRef getPassName ( ) const override {


<s> else { return false ; } int Num1s = ( ImmS & ( Width - <NUM_LIT> ) ) + <NUM_LIT> ; if ( Num1s == Width ) return false ; int Rotation = ( ImmR & ( Width - <NUM_LIT> ) ) ; uint64_t Mask = ( <NUM_LIT> << Num1s ) - <NUM_LIT> ; uint64_t WidthMask = Width == <NUM_LIT> ? - <NUM_LIT> : ( <NUM_LIT> << Width ) - <NUM_LIT> ; Mask = ( Mask >> Rotation ) | ( ( Mask << ( Width - Rotation ) ) & WidthMask ) ; Imm = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < RegWidth / Width ; ++ i ) { Imm |= Mask ;


<s> TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;

TargetRegistry :: RegisterAsmTargetStreamer ( The<ISA_LIT>Target , createTargetAsmStreamer ) ;


<s> static int CompareOffset ( const RelEntry & R0 , const RelEntry & R1 ) { return ( R0 . Offset > R1 . Offset ) ? <NUM_LIT> : ( ( R0 . Offset == R1 . Offset ) ? <NUM_LIT> : - <NUM_LIT> ) ;


<s> Shift += NBits ; } MachineInstr * FirstSt = OG . front ( ) ; DebugLoc DL = OG . back ( ) -> getDebugLoc ( ) ; const MachineMemOperand & OldM = getStoreTarget ( FirstSt ) ; MachineMemOperand * NewM = MF -> getMachineMemOperand ( OldM . getPointerInfo ( ) , OldM . getFlags ( ) , TotalSize , OldM . getAlign ( ) , OldM . getAAInfo ( ) ) ; if ( Acc < <NUM_LIT> ) { unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc && <STR_LIT> ) ; int Val = ( TotalSize == <NUM_LIT> ) ? int16_t ( Acc ) : int ( Acc ) ; const MCInstrDesc & StD = TII -> get ( WOpc ) ; MachineOperand & MR = FirstSt -> getOperand ( <NUM_LIT> ) ; int64_t Off = FirstSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * StI = BuildMI ( * MF , DL , StD ) . addReg ( MR . getReg ( ) , getKillRegState ( MR . isKill ( ) ) , MR . getSubReg ( ) ) . addImm ( Off ) . addImm ( Val ) ; StI -> addMemOperand ( * MF , NewM ) ; NG . push_back ( StI ) ; } else { const MCInstrDesc & TfrD = TII -> get ( <STR_LIT> ) ; const TargetRegisterClass * RC = TII -> getRegClass ( TfrD , <NUM_LIT> , TRI , * MF ) ; Register VReg = MF -> getRegInfo ( ) . createVirtualRegister ( RC ) ; MachineInstr * TfrI = BuildMI ( * MF , DL , TfrD , VReg ) . addImm ( int ( Acc ) ) ; NG . push_back ( TfrI ) ; unsigned WOpc = ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : ( TotalSize == <NUM_LIT> ) ? <STR_LIT> : <NUM_LIT> ; assert ( WOpc && <STR_LIT> ) ; const MCInstrDesc & StD = TII -> get ( WOpc ) ; MachineOperand & MR = FirstSt -> getOperand ( <NUM_LIT> ) ; int64_t Off = FirstSt -> getOperand ( <NUM_LIT> ) . getImm ( ) ;

MachineInstr * StI = BuildMI ( * MF , DL , StD ) . addReg ( MR . getReg ( ) , getKillRegState ( MR . isKill ( ) ) , MR . getSubReg ( ) ) . addImm ( Off ) . addReg ( VReg , RegState :: Kill ) ;


<s> if ( CmpR2 && MRI -> getRegClass ( CmpR2 ) != DoubleRC ) CmpR2 = <NUM_LIT> ; if ( ! CmpR1 && ! CmpR2 ) return ; typedef std :: vector < unsigned > UVect ; UVect DP ; for ( auto & MI : * HB ) { if ( ! MI . isPHI ( ) ) break ; const MachineOperand & MD = MI . getOperand ( <NUM_LIT> ) ; unsigned R = MD . getReg ( ) ; if ( MRI -> getRegClass ( R ) == DoubleRC ) DP . push_back ( R ) ; } if ( DP . empty ( ) ) return ; auto NoIndOp = [ this , CmpR1 , CmpR2 ] ( unsigned R ) -> bool { for ( auto I = MRI -> use_nodbg_begin ( R ) , E = MRI -> use_nodbg_end ( ) ; I != E ; ++ I ) { const MachineInstr * UseI = I -> getParent ( ) ; if ( UseI -> getOpcode ( ) != <STR_LIT> ) continue ; unsigned T = UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

if ( T == CmpR1 || T == CmpR2 ) return false ;


<s> if ( V2 . isUndef ( ) ) { SmallVector < int , <NUM_LIT> > Repeated128Mask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated128Mask ) ) { SmallVector < int , <NUM_LIT> > PSHUFDMask ; scaleShuffleMask ( <NUM_LIT> , Repeated128Mask , PSHUFDMask ) ; return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , getV4<ISA_LIT>ShuffleImm8ForMask ( PSHUFDMask , DL , DAG ) ) ) ; } SmallVector < int , <NUM_LIT> > Repeated256Mask ; if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ;

if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ;


<s> void Closure :: visitRegister ( unsigned Reg , SmallVectorImpl < unsigned > & Worklist ) { if ( EnclosedEdges . count ( Reg ) ) return ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Reg ) ) return ;

if ( ! MRI -> hasOneDef ( Reg ) ) return ;


memcpy ( type_suffix_ids , type_suffix_ids_in , sizeof ( type_suffix_ids ) ) ;


<s> const char * hsa_error_msg ; hsa_fns . hsa_status_string_fn ( status , & hsa_error_msg ) ; fprintf ( stderr , <STR_LIT> , str , hsa_error_msg ) ;


if ( TARGET_BIG_ENDIAN ) builtin_define ( <STR_LIT> ) ;


<s> return __builtin_ia32_rorqi ( __X , __C ) ;


<s> if ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) swap = true ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == MEM ) { rtx op = XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ; if ( GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ; if ( GET_CODE ( op ) == REG && REGNO ( op ) == REGNO ( operands [ <NUM_LIT> ] ) ) swap = true ; if ( GET_CODE ( op ) == PLUS ) { rtx x = XEXP ( op , <NUM_LIT> ) ; rtx y = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( x ) == REG && REGNO ( x ) == REGNO ( operands [ <NUM_LIT> ] ) ) swap = true ; if ( GET_CODE ( y ) == REG && REGNO ( y ) == REGNO ( operands [ <NUM_LIT> ] ) ) swap = true ; } } if ( swap ) { operands [ <NUM_LIT> ] = operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , mode ) ; operands [ <NUM_LIT> ] = operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , mode ) ; operands [ <NUM_LIT> ] = operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , mode ) ; operands [ <NUM_LIT> ] = operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , mode ) ; } else { operands [ <NUM_LIT> ] = operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , mode ) ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> unsigned int regno ; if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) regno = FIRST_MMX_REG ; else if ( mode == TImode || ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) ) regno = FIRST_SSE_REG ; else if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) regno = FIRST_SSE_REG ; else if ( VECTOR_MODE_P ( mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) regno = FIRST_SSE_REG ; else if ( X87_FLOAT_MODE_P ( mode ) && TARGET_FLOAT_RETURNS_IN_80387 ) regno = FIRST_FLOAT_REG ; else regno = AX_REG ; if ( mode == HFmode || mode == BFmode ) regno = FIRST_SSE_REG ; if ( mode == HCmode ) {

rtx ret = gen_rtx_PARALLEL ( mode , rtvec_alloc ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {

PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;


<s> unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return <NUM_LIT> ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return <NUM_LIT> ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return <NUM_LIT> ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return <NUM_LIT> ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == <NUM_LIT> || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == <NUM_LIT> ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != <NUM_LIT> ) ) return <NUM_LIT> ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == <NUM_LIT> && ! arm_arch5 && TARGET_ARM ) {

if ( ! call_used_regs [ <NUM_LIT> ] ) return <NUM_LIT> ;


<s> return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> SDValue Sub = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPointer , Size ) ; Chain = DAG . getCopyToReg ( StackPointer . getValue ( <NUM_LIT> ) , dl , <STR_LIT> , Sub , SDValue ( ) ) ; SDVTList VTLs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ptr = DAG . getFrameIndex ( <ISA_LIT>FI -> getDynAllocFI ( ) , getPointerTy ( ) ) ;

SDValue Ops [ ] = { Chain , Ptr , Chain . getValue ( <NUM_LIT> ) } ;


<s> <ISA_LIT>ELFWriterInfo :: ~ <ISA_LIT>ELFWriterInfo ( ) {


<s> unsigned Rd = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Rd |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned align = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned size = <NUM_LIT> << fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; align *= <NUM_LIT> * size ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairSpacedRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; } if ( Rm != <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> && Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; }


<s> void <ISA_LIT>AsmParser :: eatComma ( ) { if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; } else { }


<s> unsigned RegNum = <ISA_LIT>RegisterInfo :: getRegisterNumbering ( CSI [ i ] . getReg ( ) ) ; if ( CSI [ i ] . getRegClass ( ) == <STR_LIT> ) CPUBitmask |= ( <NUM_LIT> << RegNum ) ; else FPUBitmask |= ( <NUM_LIT> << RegNum ) ; } if ( RI . hasFP ( * MF ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getFrameRegister ( * MF ) ) ) ; if ( MFI -> hasCalls ( ) ) CPUBitmask |= ( <NUM_LIT> << <ISA_LIT>RegisterInfo :: getRegisterNumbering ( RI . getRARegister ( ) ) ) ; O << <STR_LIT> ; printHex32 ( CPUBitmask ) ; O << ',' << <ISA_LIT>FI -> getCPUTopSavedRegOff ( ) << '\n' ;

O << <STR_LIT> ; printHex32 ( FPUBitmask ) ; O << <STR_LIT> << <ISA_LIT>FI -> getFPUTopSavedRegOff ( ) << '\n' ;


<s> if ( upper == lower ) { SDValue Val = DAG . getTargetConstant ( upper , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , Val , Val , Val ) ) ; } else { bool upper_special , lower_special ; upper_special = ( upper == <NUM_LIT> || upper == <NUM_LIT> || upper == <NUM_LIT> ) ; lower_special = ( lower == <NUM_LIT> || lower == <NUM_LIT> || lower == <NUM_LIT> ) ; if ( lower_special && upper_special ) { SDValue SplatValCN = DAG . getConstant ( SplatVal , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SplatValCN , SplatValCN ) ; } SDValue LO32 ; SDValue HI32 ; SmallVector < SDValue , <NUM_LIT> > ShufBytes ; SDValue Result ; if ( ! lower_special ) { SDValue LO32C = DAG . getConstant ( lower , <STR_LIT> ) ; LO32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LO32C , LO32C , LO32C , LO32C ) ) ; } if ( ! upper_special ) { SDValue HI32C = DAG . getConstant ( upper , <STR_LIT> ) ; HI32 = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HI32C , HI32C , HI32C , HI32C ) ) ; } if ( lower_special ) LO32 = HI32 ; if ( upper_special ) HI32 = LO32 ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { uint64_t val = <NUM_LIT> ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) { SDValue V ; bool process_upper , process_lower ;


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;

else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ;


<s> emit_insn ( gen_avx2_permv4di_1 ( op , gen_lowpart ( V4DImode , h [ i ] ) , const2_rtx , GEN_INT ( <NUM_LIT> ) , const0_rtx , const1_rtx ) ) ; h [ i ] = gen_lowpart ( V32QImode , op ) ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! used [ <NUM_LIT> * i ] ) { l [ i ] = NULL_RTX ; continue ; } vperm = gen_rtx_CONST_VECTOR ( V32QImode , gen_rtvec_v ( <NUM_LIT> , rperm [ <NUM_LIT> * i ] ) ) ; vperm = force_reg ( V32QImode , vperm ) ; l [ i ] = gen_reg_rtx ( V32QImode ) ; op = gen_lowpart ( V32QImode , i ? d -> op1 : d -> op0 ) ; emit_insn ( gen_avx2_pshufbv32qi3 ( l [ i ] , op , vperm ) ) ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( h [ i ] && l [ i ] ) { op = gen_reg_rtx ( V32QImode ) ; emit_insn ( gen_iorv32qi3 ( op , l [ i ] , h [ i ] ) ) ; l [ i ] = op ; } else if ( h [ i ] ) l [ i ] = h [ i ] ; } gcc_assert ( l [ <NUM_LIT> ] && l [ <NUM_LIT> ] ) ; op = d -> target ; if ( d -> vmode != V32QImode ) op = gen_reg_rtx ( V32QImode ) ; emit_insn ( gen_iorv32qi3 ( op , l [ <NUM_LIT> ] , l [ <NUM_LIT> ] ) ) ;

if ( op != d -> target ) emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , op ) ) ;


<s> static bool isModuleLinkage ( const GlobalValue & GV ) { return ! isProgramLinkage ( GV ) ;


<s> AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ;


<s> if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( IMod != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; ProcessorIMod = IMod ; } } if ( Mnemonic . startswith ( <STR_LIT> ) ) {

ITMask = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) ) ;


<s> Res . Tok . Length = Str . size ( ) ;


<s> MachineOperand & getCount ( ) { return IsTailPredicationLegal ( ) ? VCTP -> getOperand ( <NUM_LIT> ) : Start -> getOperand ( <NUM_LIT> ) ;


<s> SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDValue Val = Op . getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget . is64Bit ( ) || VecVT . getVectorElementType ( ) != <STR_LIT> ) { if ( isNullConstant ( Idx ) ) return Op ; SDValue Slidedown = DAG . getNode ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , Vec , Idx ) ;

SDValue InsertElt0 = DAG . getNode ( <STR_LIT> , DL , VecVT , Slidedown , Val , DAG . getConstant ( <NUM_LIT> , DL , Subtarget . getXLenVT ( ) ) ) ;


<s> std :: string FS ; FS = <STR_LIT> ; return FS ;


<s> if ( first + size <= <NUM_LIT> ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ;

rtx r0 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ;


<s> LocVT = <STR_LIT> ; } if ( ValVT . isFloatingPoint ( ) && ! IntRegUsed ) { if ( ValVT == <STR_LIT> ) Reg = State . AllocateReg ( F32Regs , FloatRegsSize ) ; else Reg = State . AllocateReg ( F64Regs , FloatRegsSize ) ; } if ( ValVT == <STR_LIT> && IntRegUsed ) { if ( UnallocIntReg != IntRegsSize ) { if ( IntRegs [ UnallocIntReg ] != ( unsigned ( <STR_LIT> ) ) ) Reg = <STR_LIT> ; for ( ; UnallocIntReg < IntRegsSize ; ++ UnallocIntReg ) State . AllocateReg ( UnallocIntReg ) ; } LocVT = <STR_LIT> ; } if ( ! Reg ) { unsigned SizeInBytes = ValVT . getSizeInBits ( ) >> <NUM_LIT> ; unsigned Offset = State . AllocateStack ( SizeInBytes , SizeInBytes ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ; } else State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { StartLoc = Parser . getTok ( ) . getLoc ( ) ; RegNo = parseRegister ( true ) ; EndLoc = Parser . getTok ( ) . getLoc ( ) ;

if ( RegNo == <STR_LIT> ) return MatchOperand_NoMatch ;


<s> emitFunctionHeader ( MF ) ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( ! VerboseAsm && ( I -> pred_empty ( ) || I -> isOnlyReachableByFallthrough ( ) ) ) { } else {

printBasicBlockLabel ( I , true , true , VerboseAsm ) ;


<s> HOST_WIDE_INT high ; if ( add_operand ( op2 , SImode ) ) return false ; if ( ! CONST_INT_P ( op2 ) ) return false ; temp = create_temp_reg_if_possible ( SImode , op0 ) ; n = INTVAL ( op2 ) ; high = ( n + ( n & <NUM_LIT> ) ) & ~ <NUM_LIT> ; emit_move_insn ( temp , gen_rtx_PLUS ( SImode , op1 , gen_int_si ( high ) ) ) ; emit_move_insn ( op0 , gen_rtx_PLUS ( SImode , temp , gen_int_si ( n - high ) ) ) ;


<s> <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , IsO32 , CCInfo ) ; <ISA_LIT>CCInfo . analyzeReturn ( Outs , getTargetMachine ( ) . Options . UseSoftFloat , MF . getFunction ( ) -> getReturnType ( ) ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;

unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ;


<s> unsigned Reg = <NUM_LIT> ; if ( parseSEHRegisterNumber ( <STR_LIT> , Reg ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; getParser ( ) . Lex ( ) ;

getStreamer ( ) . emitWinCFIPushReg ( Reg , Loc ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMemEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { assert ( MI . getOperand ( OpNo ) . isReg ( ) ) ;

unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo ) , Fixups ) ;


<s> SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , <STR_LIT> , Base , TargetConstVal , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_3 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_3 ; } SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) ) ; SDNode * Result_4 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ;


<s> inline vector unsigned char vec_lvsl ( int a1 , float * a2 ) { return ( vector unsigned char ) __builtin_altivec_lvsl ( a1 , ( void * ) a2 ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; assert ( Kind == KindImmTLS && <STR_LIT> ) ;


static_cast < <ISA_LIT>TargetStreamer * > ( getTargetStreamer ( ) ) -> reset ( ) ;


<s> return ( __m64 ) __builtin_ia32_psrlw ( ( __v4hi ) __m , __count ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_ABS_LO : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_ABS_HI : OS << <STR_LIT> ; break ;


<s> const DataLayout * TD = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; const PointerType * PTy = GVar -> getType ( ) ; Type * ETy = PTy -> getElementType ( ) ; O << <STR_LIT> ; emitPTXAddressSpace ( PTy -> getAddressSpace ( ) , O ) ; if ( GVar -> getAlignment ( ) == <NUM_LIT> ) O << <STR_LIT> << ( int ) TD -> getPrefTypeAlignment ( ETy ) ; else O << <STR_LIT> << GVar -> getAlignment ( ) ; if ( ETy -> isSingleValueType ( ) ) { O << <STR_LIT> ; O << getPTXFundamentalTypeStr ( ETy ) ; O << <STR_LIT> ; O << * getSymbol ( GVar ) ; return ; } int64_t ElementSize = <NUM_LIT> ; switch ( ETy -> getTypeID ( ) ) { case Type :: StructTyID : case Type :: ArrayTyID :


<s> SDValue AMDGPUTargetLowering :: CreateLiveInRegister ( SelectionDAG & DAG , const TargetRegisterClass * RC , unsigned Reg , EVT VT ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned VirtualRegister ; if ( ! MRI . isLiveIn ( Reg ) ) { VirtualRegister = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( Reg , VirtualRegister ) ;


<s> const MCExpr * AssemblerConstantPools :: addEntry ( MCStreamer & Streamer , const MCExpr * Expr ) { const MCSection * Section = Streamer . getCurrentSection ( ) . first ;

return getOrCreateConstantPool ( Section ) . addEntry ( Expr , Streamer . getContext ( ) ) ;


<s> unsigned Width = Op . getValueType ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( ShAmt >= Width && ! isPowerOf2_64 ( ShAmt ) ) return None ; if ( BitmanipMasks . size ( ) == <NUM_LIT> && ShAmt >= ( Width / <NUM_LIT> ) ) return None ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; bool SHLExpMask = IsSHL ; if ( ! Mask ) { if ( Src . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Src . getOperand ( <NUM_LIT> ) ) ) { Mask = Src . getConstantOperandVal ( <NUM_LIT> ) ; Src = Src . getOperand ( <NUM_LIT> ) ; SHLExpMask = ! SHLExpMask ; } else { Mask = maskTrailingOnes < uint64_t > ( Width ) ; * Mask &= ( IsSHL ? * Mask << ShAmt : * Mask >> ShAmt ) ; }


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo * MMI = & MF . getMMI ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; bool FP = hasFP ( MF ) ; const AttributeSet & PAL = MF . getFunction ( ) -> getAttributes ( ) ; if ( PAL . hasAttrSomewhere ( Attribute :: Nest ) ) loadFromStack ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , dl , TII ) ; int FrameSize = MFI -> getStackSize ( ) ; assert ( FrameSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; FrameSize /= <NUM_LIT> ; bool isU6 = isImmU6 ( FrameSize ) ; if ( ! isU6 && ! isImmU16 ( FrameSize ) ) { report_fatal_error ( <STR_LIT> + Twine ( FrameSize ) ) ; } bool emitFrameMoves = <ISA_LIT>RegisterInfo :: needsFrameMoves ( MF ) ; bool saveLR = XFI -> getUsesLR ( ) ; if ( FrameSize ) { int Opcode ; if ( saveLR && ( MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) == <NUM_LIT> ) ) { Opcode = ( isU6 ) ? <STR_LIT> : <STR_LIT> ; MBB . addLiveIn ( <STR_LIT> ) ;


<s> for ( const MDOperand & Op : Node -> operands ( ) ) { const ConstantInt * CI = mdconst :: extract < ConstantInt > ( Op ) ;

V . push_back ( CI -> getZExtValue ( ) ) ;


<s> TargetRegistry :: RegisterMCSubtargetInfo ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCAsmBackend ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterELFStreamer ( getThe<ISA_LIT>Target ( ) , createMCStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( getThe<ISA_LIT>Target ( ) , createMCAsmTargetStreamer ) ;

TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>MCInstPrinter ) ;


<s> function_sym_iterator ( object :: elf_symbol_iterator It , object :: elf_symbol_iterator End , PredicateTy P ) : conditional_iterator < object :: elf_symbol_iterator > ( It , End , P ) {


<s> const Function * F = MF . getFunction ( ) ; unsigned StackAlign = MF . getTarget ( ) . getFrameInfo ( ) -> getStackAlignment ( ) ; bool requiresRealignment = ( ( MFI -> getLocalFrameMaxAlign ( ) > StackAlign ) || F -> hasFnAttr ( Attribute :: StackAlignment ) ) ;

return requiresRealignment && canRealignStack ( MF ) ;


<s> static DecodeStatus DecodeFPR64CRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) { return MCDisassembler :: Fail ;


<s> assert ( ImmMO && RegMO && <STR_LIT> ) ; int64_t Imm = <NUM_LIT> ; if ( ! isImmElgibleForForwarding ( * ImmMO , DefMI , III , Imm ) ) return false ; if ( ! isRegElgibleForForwarding ( * RegMO , DefMI , MI , KillDefMI ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MI . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( DefMI . dump ( ) ) ; MI . getOperand ( III . OpNoForForwarding ) . ChangeToRegister ( RegMO -> getReg ( ) , false , false , RegMO -> isKill ( ) ) ; if ( ImmMO -> isImm ( ) ) { MI . getOperand ( III . ZeroIsSpecialOrig ) . ChangeToImmediate ( Imm ) ; } else {

if ( DefMI . getOpcode ( ) == <STR_LIT> ) ImmMO -> setTargetFlags ( <STR_LIT> ) ;


<s> assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Count ++ ; if ( FBB ) {

BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> Function * Wrapper = Function :: Create ( Ty , Function :: PrivateLinkage , <STR_LIT> , M ) ; BasicBlock * BB = BasicBlock :: Create ( M -> getContext ( ) , <STR_LIT> , Wrapper ) ; SmallVector < Value * , <NUM_LIT> > Args ; Function :: arg_iterator AI = Wrapper -> arg_begin ( ) ; FunctionType :: param_iterator PI = F -> getFunctionType ( ) -> param_begin ( ) ; FunctionType :: param_iterator PE = F -> getFunctionType ( ) -> param_end ( ) ; for ( ; AI != Wrapper -> arg_end ( ) && PI != PE ; ++ AI , ++ PI ) { if ( AI -> getType ( ) != * PI ) { Wrapper -> eraseFromParent ( ) ; return nullptr ; } Args . push_back ( & * AI ) ;


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ;

if ( MO . isImm ( ) ) return <ISA_LIT>RDToVal ( static_cast < <STR_LIT> > ( getMachineOpValue ( MI , MO , Fixups , STI ) ) ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> return addParam ( <ISA_LIT>_PARAM_TYPE_RETURN , Ty , ParamName ) ;


<s> bool Changed = false ; BasicBlock & EntryBB = * F . begin ( ) ; SmallVector < AllocaInst * , <NUM_LIT> > Allocas ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> MCE . addRelocation ( MachineRelocation :: getBB ( MCE . getCurrentPCOffset ( ) , Reloc , BB , JTBase ) ) ;


<s> if ( DA -> isUniform ( & I ) ) return false ; Value * LHS = I . getOperand ( <NUM_LIT> ) ; Value * RHS = I . getOperand ( <NUM_LIT> ) ; IRBuilder < > Builder ( & I ) ; Builder . SetCurrentDebugLocation ( I . getDebugLoc ( ) ) ; <STR_LIT> IntrID = <STR_LIT> ; unsigned LHSBits = <NUM_LIT> , RHSBits = <NUM_LIT> ; if ( ST -> hasMulU24 ( ) && ( LHSBits = numBitsUnsigned ( LHS , Size ) ) <= <NUM_LIT> && ( RHSBits = numBitsUnsigned ( RHS , Size ) ) <= <NUM_LIT> ) { if ( Size > <NUM_LIT> && LHSBits + RHSBits > <NUM_LIT> ) return false ; IntrID = <STR_LIT> ; } else if ( ST -> hasMulI24 ( ) && ( LHSBits = numBitsSigned ( LHS , Size ) ) < <NUM_LIT> && ( RHSBits = numBitsSigned ( RHS , Size ) ) < <NUM_LIT> ) { if ( Size > <NUM_LIT> && LHSBits + RHSBits > <NUM_LIT> ) return false ; IntrID = <STR_LIT> ; } else return false ; SmallVector < Value * , <NUM_LIT> > LHSVals ; SmallVector < Value * , <NUM_LIT> > RHSVals ; SmallVector < Value * , <NUM_LIT> > ResultVals ; extractValues ( Builder , LHSVals , LHS ) ; extractValues ( Builder , RHSVals , RHS ) ; IntegerType * I32Ty = Builder . getInt32Ty ( ) ; FunctionCallee Intrin = <STR_LIT> ( Mod , IntrID ) ; for ( int I = <NUM_LIT> , E = LHSVals . size ( ) ; I != E ; ++ I ) { Value * LHS , * RHS ; if ( IntrID == <STR_LIT> ) { LHS = Builder . CreateZExtOrTrunc ( LHSVals [ I ] , I32Ty ) ; RHS = Builder . CreateZExtOrTrunc ( RHSVals [ I ] , I32Ty ) ; } else { LHS = Builder . CreateSExtOrTrunc ( LHSVals [ I ] , I32Ty ) ; RHS = Builder . CreateSExtOrTrunc ( RHSVals [ I ] , I32Ty ) ; } Value * Result = Builder . CreateCall ( Intrin , { LHS , RHS } ) ; if ( IntrID == <STR_LIT> ) { ResultVals . push_back ( Builder . CreateZExtOrTrunc ( Result , LHSVals [ I ] -> getType ( ) ) ) ;


<s> void streamIsaVersion ( const MCSubtargetInfo * STI , raw_ostream & Stream ) { auto TargetTriple = STI -> getTargetTriple ( ) ;

auto ISAVersion = IsaInfo :: getIsaVersion ( STI -> getFeatureBits ( ) ) ;


<s> SDNode * EnableDenorm ; if ( Subtarget -> hasDenormModeInst ( ) ) { const SDValue EnableDenormValue = getSPDenormModeValue ( FP_DENORM_FLUSH_NONE , DAG , SL , Subtarget ) ; EnableDenorm = DAG . getNode ( <STR_LIT> , SL , BindParamVTs , DAG . getEntryNode ( ) , EnableDenormValue ) . getNode ( ) ; } else { const SDValue EnableDenormValue = DAG . getConstant ( FP_DENORM_FLUSH_NONE , SL , <STR_LIT> ) ; EnableDenorm = DAG . getMachineNode ( <STR_LIT> , SL , BindParamVTs , { EnableDenormValue , BitField , DAG . getEntryNode ( ) } ) ; } SDValue Ops [ <NUM_LIT> ] = { NegDivScale0 , SDValue ( EnableDenorm , <NUM_LIT> ) , SDValue ( EnableDenorm , <NUM_LIT> ) } ; NegDivScale0 = DAG . getMergeValues ( Ops , SL ) ; } SDValue Fma0 = getFPTernOp ( DAG , <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , ApproxRcp , One , NegDivScale0 , Flags ) ; SDValue Fma1 = getFPTernOp ( DAG , <STR_LIT> , SL , <STR_LIT> , Fma0 , ApproxRcp , ApproxRcp , Fma0 , Flags ) ; SDValue Mul = getFPBinOp ( DAG , <STR_LIT> , SL , <STR_LIT> , NumeratorScaled , Fma1 , Fma1 , Flags ) ; SDValue Fma2 = getFPTernOp ( DAG , <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Mul , NumeratorScaled , Mul , Flags ) ; SDValue Fma3 = getFPTernOp ( DAG , <STR_LIT> , SL , <STR_LIT> , Fma2 , Fma1 , Mul , Fma2 , Flags ) ; SDValue Fma4 = getFPTernOp ( DAG , <STR_LIT> , SL , <STR_LIT> , NegDivScale0 , Fma3 , NumeratorScaled , Fma3 , Flags ) ; if ( ! HasFP32Denormals ) { SDNode * DisableDenorm ; if ( Subtarget -> hasDenormModeInst ( ) ) { const SDValue DisableDenormValue = getSPDenormModeValue ( FP_DENORM_FLUSH_IN_FLUSH_OUT , DAG , SL , Subtarget ) ; DisableDenorm = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Fma4 . getValue ( <NUM_LIT> ) , DisableDenormValue , Fma4 . getValue ( <NUM_LIT> ) ) . getNode ( ) ; } else {

const SDValue DisableDenormValue = DAG . getConstant ( FP_DENORM_FLUSH_IN_FLUSH_OUT , SL , <STR_LIT> ) ;


<s> } if ( HII -> isV60VectorInstruction ( I ) ) { for ( auto J : OldPacketMIs ) { if ( ! HII -> isV60VectorInstruction ( * J ) ) continue ; if ( isDependent ( * J , I ) && ! HII -> isVecUsableNextPacket ( * J , I ) ) return true ; } return false ; } for ( auto J : CurrentPacketMIs ) if ( ! HII -> isV60VectorInstruction ( * J ) && isDependent ( * J , I ) ) return false ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . useBSBScheduling ( ) ) { for ( auto J : OldPacketMIs ) { if ( HII -> isV60VectorInstruction ( * J ) ) continue ; if ( ! HII -> isLateInstrFeedsEarlyInstr ( * J , I ) ) continue ; if ( isDependent ( * J , I ) && ! HII -> canExecuteInBundle ( * J , I ) ) return true ;


<s> static int mep_reg_size ( int regno ) { if ( CR_REGNO_P ( regno ) && TARGET_64BIT_CR_REGS ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DCI . isBeforeLegalizeOps ( ) && N -> getOpcode ( ) == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue Setcc = DAG . getNode ( <STR_LIT> , dl , VT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) ) ; bool ReplaceOtherUses = ! N0 . hasOneUse ( ) ; DCI . CombineTo ( N , Setcc ) ; if ( ReplaceOtherUses ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , N0 . getValueType ( ) , Setcc ) ; DCI . CombineTo ( N0 . getNode ( ) , Trunc ) ; } return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ;

if ( DCI . isBeforeLegalizeOps ( ) ) if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ;


<s> unsigned <ISA_LIT>MachineFunctionInfo :: getScheduledCycles ( const MachineBasicBlock * BB ) const {

assert ( ScheduledCycles . find ( BB ) != ScheduledCycles . end ( ) ) ;


<s> Mem . Off -> print ( OS ) ; OS << <STR_LIT> ; break ; case k_PhysRegister : OS << <STR_LIT> << PhysReg . Num << <STR_LIT> ; break ; case k_RegisterIndex : OS << <STR_LIT> << RegIdx . Index << <STR_LIT> << RegIdx . Kind << <STR_LIT> ; break ; case k_Token : OS << Tok . Data ; break ; }


<s> auto III = Instructions . find ( & MI ) ; if ( III != Instructions . end ( ) ) { if ( III -> second . Needs & StateWWM ) Needs = StateWWM ; else if ( III -> second . Needs & StateWQM ) Needs = StateWQM ; else Needs &= ~ III -> second . Disabled ; OutNeeds = III -> second . OutNeeds ; } } else { Needs = StateExact | StateWQM | StateWWM ; } if ( MI . isTerminator ( ) && OutNeeds == StateExact ) Needs = StateExact ; if ( MI . getOpcode ( ) == <STR_LIT> && BI . OutNeeds == StateExact ) MI . getOperand ( <NUM_LIT> ) . setImm ( <NUM_LIT> ) ; ++ Next ; } else { if ( BI . OutNeeds & StateWQM ) Needs = StateWQM ; else if ( BI . OutNeeds == StateExact ) Needs = StateExact ; else Needs = StateWQM | StateExact ; } if ( ! ( Needs & State ) ) { MachineBasicBlock :: iterator First ; if ( State == StateWWM || Needs == StateWWM ) { First = FirstWWM ; } else { First = FirstWQM ; } MachineBasicBlock :: iterator Before = prepareInsertion ( MBB , First , II , Needs == StateWQM , Needs == StateExact || WQMFromExec ) ; if ( State == StateWWM ) { assert ( SavedNonWWMReg ) ; fromWWM ( MBB , Before , SavedNonWWMReg ) ; State = NonWWMState ; } if ( Needs == StateWWM ) { NonWWMState = State ; SavedNonWWMReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; toWWM ( MBB , Before , SavedNonWWMReg ) ; State = StateWWM ; } else { if ( State == StateWQM && ( Needs & StateExact ) && ! ( Needs & StateWQM ) ) { if ( ! WQMFromExec && ( OutNeeds & StateWQM ) ) SavedWQMReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; toExact ( MBB , Before , SavedWQMReg , LiveMaskReg ) ; State = StateExact ; } else if ( State == StateExact && ( Needs & StateWQM ) && ! ( Needs & StateExact ) ) { assert ( WQMFromExec == ( SavedWQMReg == <NUM_LIT> ) ) ; toWQM ( MBB , Before , SavedWQMReg ) ; if ( SavedWQMReg ) { LIS -> createAndComputeVirtRegInterval ( SavedWQMReg ) ; SavedWQMReg = <NUM_LIT> ; } State = StateWQM ;


<s> if ( regno2 == INVALID_REGNUM ) return aarch64_pushwb_single_reg ( mode , regno1 , adjustment ) ; rtx reg1 = gen_rtx_REG ( mode , regno1 ) ; rtx reg2 = gen_rtx_REG ( mode , regno2 ) ; insn = emit_insn ( aarch64_gen_storewb_pair ( mode , stack_pointer_rtx , reg1 , reg2 , adjustment ) ) ;

RTX_FRAME_RELATED_P ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) = <NUM_LIT> ;


<s> return getRegisterBitWidth ( true ) ;


<s> void printi16mem ( const MachineInstr * MI , unsigned OpNo ) {


<s> bool Emitter < CodeEmitter > :: runOnMachineFunction ( MachineFunction & MF ) { assert ( ( MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Default || MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static ) && <STR_LIT> ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do { MovePCtoLROffset = <NUM_LIT> ; MCE . startFunction ( MF ) ;

for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) emitBasicBlock ( * BB ) ;


<s> int type = TARGET_32BIT ? DW_EH_PE_sdata4 : DW_EH_PE_sdata8 ; return ( global ? DW_EH_PE_indirect : <NUM_LIT> ) | DW_EH_PE_pcrel | type ;


<s> EVT VecVT = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , OpVT , ( <NUM_LIT> / OpVT . getSizeInBits ( ) ) ) ; SDValue ShiftAmt = N -> getOperand ( <NUM_LIT> ) ; EVT ShiftAmtVT = ShiftAmt . getValueType ( ) ; SDNode * VecOp0 , * SelMask , * ZeroFill , * Shift = <NUM_LIT> ; SDValue SelMaskVal ; DebugLoc dl = N -> getDebugLoc ( ) ; VecOp0 = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , Op0 ) ; SelMaskVal = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SelMask = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SelMaskVal ) ; ZeroFill = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , CurDAG -> getTargetConstant ( <NUM_LIT> , OpVT ) ) ; VecOp0 = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( ZeroFill , <NUM_LIT> ) , SDValue ( VecOp0 , <NUM_LIT> ) , SDValue ( SelMask , <NUM_LIT> ) ) ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( ShiftAmt ) ) { unsigned bytes = unsigned ( CN -> getZExtValue ( ) ) >> <NUM_LIT> ; unsigned bits = unsigned ( CN -> getZExtValue ( ) ) & <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( VecOp0 , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ; }


<s> Has<ISA_LIT>_64 = false ; HasPOPCNT = false ; HasSSE4A = false ; HasAES = false ; HasPCLMUL = false ; HasFMA = false ; HasFMA4 = false ; HasXOP = false ; HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasRTM = false ; HasHLE = false ; HasERI = false ;


<s> const <ISA_LIT>TargetLowering * getTLI ( ) const {


<s> else if ( ix86_user_incoming_stack_boundary ) incoming_stack_boundary = ix86_user_incoming_stack_boundary ; else if ( ! sibcall && ix86_force_align_arg_pointer && crtl -> stack_alignment_estimated == <NUM_LIT> ) incoming_stack_boundary = MIN_STACK_BOUNDARY ; else incoming_stack_boundary = ix86_default_incoming_stack_boundary ;


if ( AGGREGATE_TYPE_P ( type ) && ( mode == BLKmode || TYPE_NEEDS_CONSTRUCTING ( type ) ) ) return true ;


<s> static SDValue combineFAndn ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N -> getOperand ( <NUM_LIT> ) ;


<s> bool hasTRACEV8_4 ( ) const { return HasTRACEV8_4 ;


<s> if ( bitmap_empty_p ( to_clear_core_bitmap ) ) return ; nb_regs = bitmap_count_bits ( to_clear_core_bitmap ) ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( nb_regs + <NUM_LIT> ) ) ; start_sequence ( ) ; for ( j = <NUM_LIT> , i = minregno ; j < nb_regs ; i ++ ) { if ( ! bitmap_bit_p ( to_clear_core_bitmap , i ) ) continue ; reg = gen_rtx_REG ( SImode , i ) ; set = gen_rtx_SET ( reg , const0_rtx ) ; XVECEXP ( par , <NUM_LIT> , j ++ ) = set ; emit_use ( reg ) ; } vunspec_vec = gen_rtvec ( <NUM_LIT> , gen_int_mode ( <NUM_LIT> , SImode ) ) ; vunspec = gen_rtx_UNSPEC_VOLATILE ( SImode , vunspec_vec , VUNSPEC_CLRM_APSR ) ; XVECEXP ( par , <NUM_LIT> , j ++ ) = vunspec ; rtx ccreg = gen_rtx_REG ( CCmode , CC_REGNUM ) ; rtx clobber = gen_rtx_CLOBBER ( VOIDmode , ccreg ) ; XVECEXP ( par , <NUM_LIT> , j ) = clobber ; use_seq = get_insns ( ) ; end_sequence ( ) ; emit_insn_after ( use_seq , emit_insn ( par ) ) ; } else { if ( clearing_regno <= maxregno && bitmap_bit_p ( to_clear_bitmap , clearing_regno ) ) { emit_move_insn ( clearing_reg , const0_rtx ) ; emit_use ( clearing_reg ) ; bitmap_clear_bit ( to_clear_bitmap , clearing_regno ) ; } for ( regno = minregno ; regno <= maxregno ; regno ++ ) { if ( ! bitmap_bit_p ( to_clear_bitmap , regno ) ) continue ; if ( IS_VFP_REGNUM ( regno ) ) { if ( TARGET_VFP_DOUBLE && VFP_REGNO_OK_FOR_DOUBLE ( regno ) && bitmap_bit_p ( to_clear_bitmap , regno + <NUM_LIT> ) ) { emit_move_insn ( gen_rtx_REG ( DFmode , regno ) , CONST1_RTX ( DFmode ) ) ; emit_use ( gen_rtx_REG ( DFmode , regno ) ) ;


<s> if ( SDValue V = transformAddShlImm ( N , DAG , Subtarget ) ) return V ; return combineSelectAndUseCommutative ( N , DAG , false ) ;


<s> fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; fprintf ( asm_out_file , <STR_LIT> , GET_MODE_BITSIZE ( Pmode ) ) ;


<s> void addRotImmOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;

assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;


<s> BitVector UsedInsts ( NumVectorMemOps , false ) ; std :: vector < BitVector > ValueVecs ( Factor , BitVector ( NumVectorMemOps , false ) ) ; for ( unsigned Index : Indices ) for ( unsigned Elt = <NUM_LIT> ; Elt < VF ; ++ Elt ) { unsigned Vec = ( Index + Elt * Factor ) / NumEltsPerVecReg ; UsedInsts . set ( Vec ) ; ValueVecs [ Index ] . set ( Vec ) ; } NumVectorMemOps = UsedInsts . count ( ) ; for ( unsigned Index : Indices ) { unsigned NumSrcVecs = ValueVecs [ Index ] . count ( ) ; unsigned NumDstVecs = ceil ( VF * getScalarSizeInBits ( VecTy ) , <NUM_LIT> ) ; assert ( NumSrcVecs >= NumDstVecs && <STR_LIT> ) ; NumPermutes += std :: max ( <NUM_LIT> , NumSrcVecs - NumDstVecs ) ;


<s> if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; SDValue Op = N -> getOperand ( <NUM_LIT> ) ; unsigned OpOpcode = Op . getNode ( ) -> getOpcode ( ) ; if ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) || ( OpOpcode != <STR_LIT> && OpOpcode != <STR_LIT> ) ) return SDValue ( ) ; SDValue ConstVec = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < BuildVectorSDNode > ( ConstVec ) ) return SDValue ( ) ; MVT FloatTy = N -> getSimpleValueType ( <NUM_LIT> ) . getVectorElementType ( ) ; uint32_t FloatBits = FloatTy . getSizeInBits ( ) ; MVT IntTy = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . getVectorElementType ( ) ; uint32_t IntBits = IntTy . getSizeInBits ( ) ; unsigned NumLanes = Op . getValueType ( ) . getVectorNumElements ( ) ; if ( FloatBits != <NUM_LIT> || IntBits > <NUM_LIT> || NumLanes > <NUM_LIT> ) { return SDValue ( ) ; } BitVector UndefElements ; BuildVectorSDNode * BV = cast < BuildVectorSDNode > ( ConstVec ) ; int32_t C = BV -> getConstantFPSplatPow2ToLog2Int ( & UndefElements , <NUM_LIT> ) ; if ( C == - <NUM_LIT> || C == <NUM_LIT> || C > <NUM_LIT> ) return SDValue ( ) ; SDLoc dl ( N ) ; bool isSigned = OpOpcode == <STR_LIT> ; SDValue ConvInput = Op . getOperand ( <NUM_LIT> ) ; if ( IntBits < FloatBits ) ConvInput = DAG . getNode ( isSigned ? <STR_LIT> : <STR_LIT> , dl , NumLanes == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , ConvInput ) ; unsigned IntrinsicOpcode = isSigned ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getConstant ( IntrinsicOpcode , dl , <STR_LIT> ) , ConvInput , DAG . getConstant ( C , dl , <STR_LIT> ) ) ;


<s> return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreatePSBHint ( PSB -> Encoding , Tok . getString ( ) , S , getContext ( ) ) ) ; Lex ( ) ;


<s> if ( T . getOS ( ) == Triple :: OpenBSD && T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = <NUM_LIT> ;


<s> const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) { Addr = LHS ; ImmOffset = COffsetVal ; } else if ( ! LHS -> isDivergent ( ) && COffsetVal > <NUM_LIT> ) { SDLoc SL ( N ) ; int64_t SplitImmOffset , RemainderOffset ; std :: tie ( SplitImmOffset , RemainderOffset ) = TII -> splitFlatOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ; if ( isUInt < <NUM_LIT> > ( RemainderOffset ) ) { SDNode * VMov = CurDAG -> getMachineNode ( <STR_LIT> , SL , <STR_LIT> , CurDAG -> getTargetConstant ( RemainderOffset , SDLoc ( ) , <STR_LIT> ) ) ;


<s> virtual void Reset ( ) { ResourceAssignment :: Reset ( ) ;


<s> ReturnBBs . clear ( ) ; findReturns ( MF . begin ( ) ) ; bool MadeChange = false ; MachineBasicBlock :: iterator ReturnLoc ; MachineBasicBlock * MBB ; unsigned int Cycles = <NUM_LIT> ; unsigned int BBCycles ; for ( DenseMap < MachineBasicBlock * , unsigned int > :: iterator I = ReturnBBs . begin ( ) ; I != ReturnBBs . end ( ) ; ++ I ) { MBB = I -> first ; Cycles = I -> second ; if ( Cycles < Threshold ) { if ( ! cyclesUntilReturn ( MBB , BBCycles , & ReturnLoc ) ) continue ; addPadding ( MBB , ReturnLoc , Threshold - Cycles ) ;


<s> SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; if ( ! IsNakedFunction ) printSavedRegsBitmask ( OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ;

if ( ! Subtarget -> in<ISA_LIT>16Mode ( ) ) {


<s> assert ( I -> getOperand ( <NUM_LIT> ) . isReg ( ) && I -> getOperand ( <NUM_LIT> ) . isFI ( ) ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>RegisterInfo & RegInfo = * static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const TargetRegisterClass * RC = RegInfo . intRegClass ( <NUM_LIT> ) ; unsigned VR = MRI . createVirtualRegister ( RC ) ;

unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> if ( ! TLI . isTypeLegal ( SrcVT ) ) return false ; unsigned InputReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! InputReg ) return false ; if ( SrcVT == <STR_LIT> ) { updateValueMap ( I , InputReg ) ; return true ; } if ( ! Subtarget -> is64Bit ( ) ) { const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ;

unsigned CopyReg = createResultReg ( CopyRC ) ;