<s> SMLoc DotLoc = SMLoc :: getFromPointer ( NameLoc . getPointer ( ) + Dot ) ; StringRef DotStr = Name . slice ( Dot , StringRef :: npos ) ; if ( ! NewOpcode . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateTokenWithStringCopy ( DotStr , DotLoc , is<ISA_LIT>64 ( ) ) ) ; else Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( DotStr , DotLoc , is<ISA_LIT>64 ( ) ) ) ; } if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) return false ; if ( ParseOperand ( Operands ) ) return true ; while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) && getLexer ( ) . is ( AsmToken :: Comma ) ) { getLexer ( ) . Lex ( ) ; if ( ParseOperand ( Operands ) ) return true ;


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'd' : case 'y' : case 'r' : if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { if ( Subtarget -> in<ISA_LIT>16Mode ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( VT == <STR_LIT> && ! Has<ISA_LIT>64 ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT == <STR_LIT> && Has<ISA_LIT>64 ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( <NUM_LIT> ) ) ; case 'f' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; if ( ( VT == <STR_LIT> ) && ( ! Subtarget -> isSingleFloat ( ) ) ) { if ( Subtarget -> isFP64bit ( ) ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } break ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; case 'l' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ;


<s> static void rs6000_xcoff_unique_section ( tree decl , int reloc ATTRIBUTE_UNUSED ) {


<s> bool iss9Ext ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true , true , true ) ;


<s> insn = NEXT_INSN ( insn ) ; if ( insn == <NUM_LIT> || ! NOTE_P ( insn ) ) break ; if ( NOTE_INSN_BASIC_BLOCK_P ( insn ) ) return NULL ; }


<s> using namespace <ISA_LIT> ; case PCALL_INDIRECT_VOID : return CALL_INDIRECT_VOID ; case PCALL_INDIRECT_I32 : return CALL_INDIRECT_I32 ; case PCALL_INDIRECT_I64 : return CALL_INDIRECT_I64 ;

case PCALL_INDIRECT_F32 : return CALL_INDIRECT_F32 ;


<s> return & pass . getAnalysis < MachineLoopInfo > ( ) ;


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { if ( Subtarget . isDarwinABI ( ) ) return Subtarget . is<ISA_LIT>64 ( ) ? CSR_Darwin64_SaveList : CSR_Darwin32_SaveList ; return Subtarget . is<ISA_LIT>64 ( ) ? CSR_SVR464_SaveList : CSR_SVR432_SaveList ;


<s> if ( ! x || ! INSN_P ( x ) ) return false ; rtx pat = PATTERN ( x ) ; if ( GET_CODE ( pat ) == SET ) { rtx tmp = XEXP ( pat , <NUM_LIT> ) ; if ( tmp && ( ( GET_CODE ( tmp ) == UNSPEC && XINT ( tmp , <NUM_LIT> ) == UNSPEC_PAC_NOP ) || ( GET_CODE ( tmp ) == UNSPEC_VOLATILE && XINT ( tmp , <NUM_LIT> ) == VUNSPEC_PACBTI_NOP ) ) ) return true ; }


<s> <ISA_LIT>ISelAddressMode ( ) : BaseType ( RegBase ) , Base_FrameIndex ( <NUM_LIT> ) , Scale ( <NUM_LIT> ) , IndexReg ( ) , Disp ( <NUM_LIT> ) , Segment ( ) , GV ( nullptr ) , CP ( nullptr ) , BlockAddr ( nullptr ) , ES ( nullptr ) , JT ( - <NUM_LIT> ) , Align ( <NUM_LIT> ) , SymbolFlags ( <STR_LIT> ) {


<s> static void block_move_call ( rtx dest_reg , rtx src_reg , rtx bytes_rtx ) { if ( GET_MODE ( bytes_rtx ) != VOIDmode && GET_MODE ( bytes_rtx ) != Pmode ) bytes_rtx = convert_to_mode ( Pmode , bytes_rtx , <NUM_LIT> ) ; emit_library_call ( m32r_function_symbol ( <STR_LIT> ) , <NUM_LIT> , VOIDmode , <NUM_LIT> , dest_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ;


<s> static DecodeStatus decodeSImmNonZeroOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { if ( Imm == <NUM_LIT> ) return MCDisassembler :: Fail ; return decodeSImmOperand < N > ( Inst , Imm , Address , Decoder ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , PTXVersion ( <NUM_LIT> ) , SmVersion ( <NUM_LIT> ) , TM ( TM ) , InstrInfo ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) , FrameLowering ( ) {


<s> return ( int8x8_t ) __builtin_neon_vqrshlsv8qi ( __a , __b ) ;


<s> SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , <STR_LIT> , Base , TargetConstVal , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , TargetConst0 , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ; return Result_2 ; } SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue TargetConstVal = CurDAG -> getTargetConstant ( Val , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Base , TargetConst0 , Chain ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , TargetConst0 , SDValue ( Result_1 , <NUM_LIT> ) ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Base , TargetConstVal , SDValue ( Result_1 , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ; cast < MachineSDNode > ( Result_1 ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; const SDValue Froms [ ] = { SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) , SDValue ( LD , <NUM_LIT> ) } ; const SDValue Tos [ ] = { SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_3 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) } ; ReplaceUses ( Froms , Tos , <NUM_LIT> ) ;


<s> } if ( St -> isTruncatingStore ( ) ) return SDValue ( ) ; MVT StoreVT = StoredVal . getSimpleValueType ( ) ; if ( StoreVT . is256BitVector ( ) ) { SmallVector < SDValue , <NUM_LIT> > CatOps ; if ( StoredVal . hasOneUse ( ) && collectConcatOps ( StoredVal . getNode ( ) , CatOps ) ) return splitVectorStore ( St , DAG ) ; return SDValue ( ) ; } const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; assert ( StoreVT . isVector ( ) && StoreVT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( TLI . getTypeAction ( * DAG . getContext ( ) , StoreVT ) == TargetLowering :: TypeWidenVector && <STR_LIT> ) ; EVT WideVT = TLI . getTypeToTransformTo ( * DAG . getContext ( ) , StoreVT ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , WideVT , StoredVal , DAG . getUNDEF ( StoreVT ) ) ; if ( Subtarget . hasSSE2 ( ) ) { MVT StVT = Subtarget . is64Bit ( ) && StoreVT . isInteger ( ) ? <STR_LIT> : <STR_LIT> ; MVT CastVT = <STR_LIT> ( StVT , <NUM_LIT> ) ; StoredVal = DAG . getBitcast ( CastVT , StoredVal ) ; StoredVal = DAG . getNode ( <STR_LIT> , dl , StVT , StoredVal , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; return DAG . getStore ( St -> getChain ( ) , dl , StoredVal , St -> getBasePtr ( ) , St -> getPointerInfo ( ) , St -> getAlignment ( ) , St -> getMemOperand ( ) -> getFlags ( ) ) ; }

assert ( Subtarget . hasSSE1 ( ) && <STR_LIT> ) ;


<s> fprintf ( file , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , actual_fsize ) ; if ( crtl -> is_leaf ) fputs ( <STR_LIT> , file ) ; else fputs ( <STR_LIT> , file ) ; if ( rp_saved ) fputs ( <STR_LIT> , file ) ; if ( frame_pointer_needed ) fputs ( <STR_LIT> , file ) ;

if ( gr_saved ) fprintf ( file , <STR_LIT> , gr_saved + <NUM_LIT> ) ;


<s> TargetLoweringObjectFileELF ( ) , AttributesSection ( NULL ) {


<s> void <ISA_LIT>TargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( Align ( std :: max ( <NUM_LIT> , TextSection . getAlignment ( ) ) ) ) ; DataSection . setAlignment ( Align ( std :: max ( <NUM_LIT> , DataSection . getAlignment ( ) ) ) ) ; BSSSection . setAlignment ( Align ( std :: max ( <NUM_LIT> , BSSSection . getAlignment ( ) ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ; for ( MCSection & S : MCA ) { MCSectionELF & Section = static_cast < MCSectionELF & > ( S ) ; unsigned Alignment = Section . getAlignment ( ) ; if ( Alignment ) { OS . SwitchSection ( & Section ) ; if ( Section . UseCodeAlign ( ) ) OS . EmitCodeAlignment ( Alignment , Alignment ) ; else OS . EmitValueToAlignment ( Alignment , <NUM_LIT> , <NUM_LIT> , Alignment ) ; } } } const FeatureBitset & Features = STI . getFeatureBits ( ) ; unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( getABI ( ) . IsO32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI_O32 ; else if ( getABI ( ) . IsN32 ( ) ) EFlags |= ELF :: EF_MIPS_ABI2 ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FramePtr ) ; if ( hasBasePointer ( MF ) ) Reserved . set ( BasePtr ) ; if ( STI . isR9Reserved ( ) ) Reserved . set ( <STR_LIT> ) ;

if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) {


<s> return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ;


<s> } else { if ( Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , false , Addr . getShift ( ) , true ) ; else if ( Addr . getExtendType ( ) == <STR_LIT> ) ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , false , Addr . getShift ( ) , false ) ; else ResultReg = emitLSL_ri ( <STR_LIT> , <STR_LIT> , Addr . getOffsetReg ( ) , false , Addr . getShift ( ) ) ; } if ( ! ResultReg ) return false ; Addr . setReg ( ResultReg ) ; Addr . setOffsetReg ( <NUM_LIT> ) ; Addr . setShift ( <NUM_LIT> ) ; Addr . setExtendType ( <STR_LIT> ) ; } if ( ImmediateOffsetNeedsLowering ) { unsigned ResultReg = <NUM_LIT> ; if ( Addr . getReg ( ) ) ResultReg = FastEmit_ri_ ( <STR_LIT> , <STR_LIT> , Addr . getReg ( ) , false , Offset , <STR_LIT> ) ; else ResultReg = FastEmit_i ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Offset ) ; if ( ! ResultReg ) return false ; Addr . setReg ( ResultReg ) ; Addr . setOffset ( <NUM_LIT> ) ;


<s> const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; int64_t NumOfVReg = Amount / <NUM_LIT> ; Register VL = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . setMIFlag ( Flag ) ; assert ( isInt < <NUM_LIT> > ( NumOfVReg ) && <STR_LIT> ) ; if ( isPowerOf2_32 ( NumOfVReg ) ) { uint32_t ShiftAmount = Log2_32 ( NumOfVReg ) ; if ( ShiftAmount == <NUM_LIT> ) return VL ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; } else if ( isPowerOf2_32 ( NumOfVReg - <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg - <NUM_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else if ( isPowerOf2_32 ( NumOfVReg + <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg + <NUM_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { Register N = MRI . createVirtualRegister ( & <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( NumOfVReg ) ) movImm ( MBB , II , DL , N , NumOfVReg ) ; else { BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , N ) . addReg ( <STR_LIT> ) . addImm ( NumOfVReg ) . setMIFlag ( Flag ) ; } if ( ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasStdExtM ( ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addReg ( N , RegState :: Kill ) . setMIFlag ( Flag ) ; } return VL ;


return ( __m64 ) __builtin_arm_wsubaddhx ( ( __v4hi ) a , ( __v4hi ) b ) ;


<s> void <ISA_LIT>AsmPrinter :: emitFunctionBodyStart ( ) {


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( create<ISA_LIT>BranchSelectionPass ( ) ) ;


SDValue CastV1 = DAG . getBitcast ( <STR_LIT> , V1 ) ;


<s> <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * Mang , * this ) ;


<s> if ( matchANDXORWithAllOnesAsANDNP ( N , X , Y ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , X , Y ) ;


<s> MachineBasicBlock * DestBB = getDestBlock ( MI ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstr * BMI = & MBB -> back ( ) ; bool NeedSplit = ( BMI != MI ) || ! BBHasFallthrough ( MBB ) ; if ( BMI != MI ) { if ( std :: next ( MachineBasicBlock :: iterator ( MI ) ) == std :: prev ( MBB -> getLastNonDebugInstr ( ) ) && BMI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock * NewDest = BMI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( isBlockInRange ( MI , NewDest , getBranchDisplacementBits ( MI -> getOpcode ( ) ) ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * BMI ) ; BMI -> getOperand ( <NUM_LIT> ) . setMBB ( DestBB ) ; unsigned OpNum = ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MI -> getOperand ( OpNum ) . setMBB ( NewDest ) ; MI -> setDesc ( TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) invertBccCondition ( MI ) ; return true ; } } } if ( NeedSplit ) { MachineBasicBlock * TBB , * FBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; TII -> AnalyzeBranch ( * MBB , TBB , FBB , Cond , false ) ; MachineBasicBlock * NewBB = splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( MBB -> back ( ) ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; MBB -> replaceSuccessor ( FBB , NewBB ) ; NewBB -> addSuccessor ( FBB ) ; } MachineBasicBlock * NextBB = & * std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ;

MachineInstrBuilder MIB = BuildMI ( MBB , DebugLoc ( ) , TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( const auto * BKey = mdconst :: extract_or_null < ConstantInt > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) return BKey -> getZExtValue ( ) ; return false ; } const StringRef Key = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ;

assert ( Key . equals_insensitive ( <STR_LIT> ) || Key . equals_insensitive ( <STR_LIT> ) ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>32Target ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>64Target ( ) ) ;

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Z ( getThe<ISA_LIT>LogicalTarget ( ) ) ;


<s> static bool aarch64_validate_mbranch_protection ( const char * const_str ) { char * str = ( char * ) xmalloc ( strlen ( const_str ) ) ; enum aarch64_parse_opt_result res = aarch64_parse_branch_protection ( const_str , & str ) ; if ( res == AARCH64_PARSE_INVALID_ARG ) error ( <STR_LIT> , str ) ;

else if ( res == AARCH64_PARSE_MISSING_ARG ) error ( <STR_LIT> ) ;


<s> if ( SubRegMask == LaneMask ) { Func ( Idx ) ; return ; } if ( ( SubRegMask & ~ LaneMask ) . any ( ) || ( SubRegMask & LaneMask ) . none ( ) ) continue ; CoveringSubregs . push_back ( Idx ) ; } llvm :: sort ( CoveringSubregs . begin ( ) , CoveringSubregs . end ( ) , [ this ] ( unsigned A , unsigned B ) { LaneBitmask MaskA = TRI -> getSubRegIndexLaneMask ( A ) ; LaneBitmask MaskB = TRI -> getSubRegIndexLaneMask ( B ) ; unsigned NA = MaskA . getNumLanes ( ) ; unsigned NB = MaskB . getNumLanes ( ) ; if ( NA != NB ) return NA > NB ; return MaskA . getHighestLane ( ) > MaskB . getHighestLane ( ) ;


<s> bool <ISA_LIT>InstrInfo :: getMachineCombinerPatterns ( MachineInstr & Root , SmallVectorImpl < MachineCombinerPattern > & Patterns , bool DoRegPressureReduce ) const { if ( Subtarget . getTargetMachine ( ) . getOptLevel ( ) != CodeGenOpt :: Aggressive ) return false ;

if ( getFMAPatterns ( Root , Patterns , DoRegPressureReduce ) ) return true ;


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , CSI [ i ] . getReg ( ) ) ;


<s> static std :: unique_ptr < AMDGPUOperand > CreateReg ( unsigned RegNo , SMLoc S , SMLoc E , const MCRegisterInfo * TRI ) { auto Op = llvm :: make_unique < AMDGPUOperand > ( Register ) ; Op -> Reg . RegNo = RegNo ; Op -> Reg . TRI = TRI ;


<s> for ( unsigned i = <NUM_LIT> , e = Constants . size ( ) ; i != e ; ++ i ) { if ( Constants [ i ] . isMachineConstantPoolEntry ( ) && ( Constants [ i ] . getAlignment ( ) & AlignMask ) == <NUM_LIT> ) { <ISA_LIT>ConstantPoolValue * CPV = ( <ISA_LIT>ConstantPoolValue * ) Constants [ i ] . Val . MachineCPVal ; if ( Derived * APC = dyn_cast < Derived > ( CPV ) ) if ( cast < Derived > ( this ) -> equals ( APC ) ) return i ;


<s> return ( ! TARGET_64BIT && mode == TImode && type && TREE_CODE ( type ) != VECTOR_TYPE ) ;


<s> return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ;


<s> } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( Subtarget . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) || <ISA_LIT>FI -> hasSaveS2 ( ) ) Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . useSmallSection ( ) ) {


Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> if ( Reg . isVirtual ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , TRI ) << <STR_LIT> ) ; if ( PHIInfo . isSource ( Reg ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printReg ( Reg , TRI ) << <STR_LIT> ) ; addLiveOut ( Reg ) ; } else {

for ( auto & UI : MRI -> use_operands ( Reg ) ) {


<s> void <ISA_LIT>TargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , std :: string & Constraint , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const {

if ( Constraint . length ( ) == <NUM_LIT> && Constraint [ <NUM_LIT> ] == 'A' ) {


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , true , false ) ;


<s> const <ISA_LIT>RegisterInfo & TRI = TII -> getRegisterInfo ( ) ; for ( MachineInstr :: const_mop_iterator MOI = Def -> operands_begin ( ) , MOE = Def -> operands_end ( ) ; MOI != MOE ; ++ MOI ) {

if ( ! MOI -> isReg ( ) || ! MOI -> isDef ( ) || TRI . isPhysRegLiveAcrossClauses ( MOI -> getReg ( ) ) ) continue ;


<s> YIO . enumCase ( EN , <STR_LIT> , ValueType :: I8 ) ; YIO . enumCase ( EN , <STR_LIT> , ValueType :: U8 ) ; YIO . enumCase ( EN , <STR_LIT> , ValueType :: I16 ) ; YIO . enumCase ( EN , <STR_LIT> , ValueType :: U16 ) ; YIO . enumCase ( EN , <STR_LIT> , ValueType :: F16 ) ; YIO . enumCase ( EN , <STR_LIT> , ValueType :: I32 ) ; YIO . enumCase ( EN , <STR_LIT> , ValueType :: U32 ) ; YIO . enumCase ( EN , <STR_LIT> , ValueType :: F32 ) ; YIO . enumCase ( EN , <STR_LIT> , ValueType :: I64 ) ; YIO . enumCase ( EN , <STR_LIT> , ValueType :: U64 ) ;

YIO . enumCase ( EN , <STR_LIT> , ValueType :: F64 ) ;


<s> while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator I = std :: prev ( MBBI ) ; unsigned Opc = I -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! I -> isTerminator ( ) ) break ; MBBI -- ; } if ( NumBytes ) { unsigned FP = TII . getRegisterInfo ( ) . getFrameRegister ( MF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FP ) . addImm ( NumBytes ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( FP , RegState :: Kill ) ;


<s> switch ( VLMUL ) { case <STR_LIT> :: LMUL_RESERVED : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :: LMUL_1 : case <STR_LIT> :: LMUL_2 : case <STR_LIT> :: LMUL_4 : case <STR_LIT> :: LMUL_8 : { unsigned LMul = <NUM_LIT> << static_cast < unsigned > ( VLMUL ) ; OS << <STR_LIT> << LMul ; break ; } case <STR_LIT> :: LMUL_F2 : case <STR_LIT> :: LMUL_F4 : case <STR_LIT> :: LMUL_F8 : { unsigned LMul = <NUM_LIT> << ( <NUM_LIT> - static_cast < unsigned > ( VLMUL ) ) ; OS << <STR_LIT> << LMul ; break ; } } if ( isTailAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ; if ( isMaskAgnostic ( VType ) ) OS << <STR_LIT> ;


<s> if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } } int64_t ShiftAmount = Parser . getTok ( ) . getIntVal ( ) ; if ( ShiftAmount < <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImmWithLSL ( Imm , ShiftAmount , false , S , E ) ) ;


<s> static SDValue unpackFromRegLoc ( SelectionDAG & DAG , SDValue Chain , const CCValAssign & VA , const SDLoc & DL , const <ISA_LIT>TargetLowering & TLI ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; SDValue Val ;

const TargetRegisterClass * RC = TLI . getRegClassFor ( LocVT . getSimpleVT ( ) ) ;


<s> <ISA_LIT>AsmBackendELF ( const Target & T , StringRef TT , uint8_t OSABI , bool IsLittle ) : <ISA_LIT>AsmBackend ( T , TT , IsLittle ) , OSABI ( OSABI ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) {


<s> return new <ISA_LIT>MCELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( CE ) ) ;


<s> unsigned Alignment = IntrAlign -> getLimitedValue ( ) < MemAlign ? MemAlign : IntrAlign -> getLimitedValue ( ) ; if ( ! isPowerOf2_32 ( Alignment ) ) return nullptr ; auto * BCastInst = Builder . CreateBitCast ( II . getArgOperand ( <NUM_LIT> ) , PointerType :: get ( II . getType ( ) , <NUM_LIT> ) ) ;

return Builder . CreateAlignedLoad ( II . getType ( ) , BCastInst , Align ( Alignment ) ) ;


<s> if ( auto * Icmp1 = dyn_cast < ICmpInst > ( Inst ) ) { Value * Icmp1Op1 = Icmp1 -> getOperand ( <NUM_LIT> ) ; if ( ! isa < Constant > ( Icmp1Op1 ) ) return false ; isCandidate = true ; continue ; } if ( Inst -> getParent ( ) == I . getParent ( ) ) continue ; for ( auto & I2 : * Inst -> getParent ( ) ) { if ( dyn_cast < CallInst > ( & I2 ) ) return false ; if ( dyn_cast < LoadInst > ( & I2 ) || dyn_cast < StoreInst > ( & I2 ) ) return false ; if ( & I2 == Inst ) break ; } if ( Inst -> getOpcode ( ) == Instruction :: ZExt || Inst -> getOpcode ( ) == Instruction :: SExt ) { PassThroughInfo Info ( & I , Inst , <NUM_LIT> ) ; Candidates . push_back ( Info ) ; } else if ( auto * GI = dyn_cast < GetElementPtrInst > ( Inst ) ) { unsigned i , e ; for ( i = <NUM_LIT> , e = GI -> getNumOperands ( ) ; i != e ; ++ i ) { Value * V = GI -> getOperand ( i ) ; if ( V == & I ) break ; } if ( i == e ) continue ; PassThroughInfo Info ( & I , GI , i ) ; Candidates . push_back ( Info ) ; }


<s> Register <ISA_LIT>RegisterInfo :: getBaseRegister ( ) const { return <STR_LIT> ;


<s> return TargetAsmInfo :: PreferredEHDataFormat ( Reason , Global ) ;


<s> if ( CI -> isCallee ( & U ) ) Printfs . push_back ( CI ) ; } } if ( Printfs . empty ( ) ) return false ; if ( auto HostcallFunction = M . getFunction ( <STR_LIT> ) ) { for ( auto & U : HostcallFunction -> uses ( ) ) { if ( auto * CI = dyn_cast < CallInst > ( U . getUser ( ) ) ) { M . getContext ( ) . emitError ( CI , <STR_LIT> ) ; } } } TD = & M . getDataLayout ( ) ; auto DTWP = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTWP ? & DTWP -> getDomTree ( ) : nullptr ; auto GetTLI = [ this ] ( Function & F ) -> TargetLibraryInfo & {

return this -> getAnalysis < TargetLibraryInfoWrapperPass > ( ) . getTLI ( F ) ;


<s> Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } Ops . push_back ( TexRef ) ; Ops . push_back ( SampRef ) ; for ( unsigned i = <NUM_LIT> ; i < N -> getNumOperands ( ) ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; } Ops . push_back ( Chain ) ;

Ret = CurDAG -> getMachineNode ( Opc , SDLoc ( N ) , N -> getVTList ( ) , Ops ) ;


return ( __m128i ) ( vec_vsx_ld ( <NUM_LIT> , ( signed int const * ) __P ) ) ;


<s> if ( Val >= - <NUM_LIT> && Val <= <NUM_LIT> ) {


<s> explicit <ISA_LIT>MCExpr ( VariantKind Kind , const MCExpr * Expr ) : Kind ( Kind ) , Expr ( Expr ) {


<s> return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> if ( CONST_INT_P ( length ) ) { if ( INTVAL ( length ) <= MIPS_MAX_MOVE_BYTES_STRAIGHT ) { mips_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { mips_block_move_loop ( dest , src , INTVAL ( length ) , MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER ) ; return true ; } }


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> OP_COPY = <NUM_LIT> , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR } ; if ( OpNum == OP_COPY ) { if ( LHSID == ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) return LHS ; assert ( LHSID == ( ( <NUM_LIT> * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> && <STR_LIT> ) ; return RHS ; } SDValue OpLHS , OpRHS ; OpLHS = GeneratePerfectShuffle ( PerfectShuffleTable [ LHSID ] , LHS , RHS , DAG , dl ) ; OpRHS = GeneratePerfectShuffle ( PerfectShuffleTable [ RHSID ] , LHS , RHS , DAG , dl ) ; EVT VT = OpLHS . getValueType ( ) ; switch ( OpNum ) { default : llvm_unreachable ( <STR_LIT> ) ; case OP_VREV : if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; assert ( VT . getVectorElementType ( ) == <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , OpLHS ) ; case OP_VDUP0 : case OP_VDUP1 : case OP_VDUP2 : case OP_VDUP3 : { EVT EltTy = VT . getVectorElementType ( ) ; unsigned Opcode ;

if ( EltTy == <STR_LIT> ) Opcode = <STR_LIT> ;


<s> uint64_t Result = ExplicitKernArgSize ; ExplicitKernArgSize += Size ; MaxKernArgAlign = std :: max ( Align , MaxKernArgAlign ) ; return Result ;


<s> case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = false ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SubIdx = <STR_LIT> ; SwapOps = true ; break ; case <STR_LIT> : SubIdx = <NUM_LIT> ; SwapOps = false ; break ; case <STR_LIT> : SubIdx = <NUM_LIT> ; SwapOps = true ; break ; } Register FirstReg = SwapOps ? FalseReg : TrueReg , SecondReg = SwapOps ? TrueReg : FalseReg ; if ( MRI . getRegClass ( FirstReg ) -> contains ( <STR_LIT> ) || MRI . getRegClass ( FirstReg ) -> contains ( <STR_LIT> ) ) { const TargetRegisterClass * FirstRC = MRI . getRegClass ( FirstReg ) -> contains ( <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; Register OldFirstReg = FirstReg ;

FirstReg = MRI . createVirtualRegister ( FirstRC ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( isUnsupportedFloatingType ( LHS . getValueType ( ) ) ) { DAG . getTargetLoweringInfo ( ) . softenSetCCOperands ( DAG , LHS . getValueType ( ) , LHS , RHS , CC , dl , LHS , RHS ) ; if ( ! RHS . getNode ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , dl , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } unsigned Opc = LHS . getOpcode ( ) ; bool OptimizeMul = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && ! Subtarget -> isThumb1Only ( ) ; if ( LHS . getResNo ( ) == <NUM_LIT> && ( isOneConstant ( RHS ) || isNullConstant ( RHS ) ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || OptimizeMul ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( LHS -> getValueType ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Value , OverflowCmp ; SDValue <ISA_LIT>cc ; std :: tie ( Value , OverflowCmp ) = get<ISA_LIT>XALUOOp ( LHS . getValue ( <NUM_LIT> ) , DAG , <ISA_LIT>cc ) ; if ( ( CC == <STR_LIT> ) != isOneConstant ( RHS ) ) { <STR_LIT> CondCode = ( <STR_LIT> ) cast < const ConstantSDNode > ( <ISA_LIT>cc ) -> getZExtValue ( ) ; CondCode = <STR_LIT> ( CondCode ) ; <ISA_LIT>cc = DAG . getConstant ( CondCode , SDLoc ( <ISA_LIT>cc ) , <STR_LIT> ) ; } SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , <ISA_LIT>cc , CCR , OverflowCmp ) ;


<s> BranchesOut [ Target ] = make_unique < Branch > ( Condition , Code ) ;


<s> RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = alloc_EXPR_LIST ( REG_FRAME_RELATED_EXPR , dwarf_pattern , REG_NOTES ( insn ) ) ;


<s> bool AMDGPUInstrInfo :: canFoldMemoryOperand ( const MachineInstr * MI , const SmallVectorImpl < unsigned > & Ops ) const {


<s> unsigned <ISA_LIT>FastISel :: TargetMaterializeAlloca ( const AllocaInst * AI ) { if ( ! FuncInfo . StaticAllocaMap . count ( AI ) ) return <NUM_LIT> ; MVT VT ; if ( ! isLoadTypeLegal ( AI -> getType ( ) , VT ) ) return false ;

DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ;


<s> if ( RC == NOREXRegClasses [ RegIdx ] ) return false ; const TargetRegisterClass * GPRRegClasses [ ] = { & <STR_LIT> , & <STR_LIT> , & <STR_LIT> , & <STR_LIT> } ; return RC -> hasSuperClassEq ( GPRRegClasses [ RegIdx ] ) ;


<s> unsigned Reg = HalfWidthLowDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> bool <ISA_LIT>TargetLowering :: isCFIntrinsic ( const SDNode * Intr ) const { if ( Intr -> getOpcode ( ) == <STR_LIT> ) { switch ( cast < ConstantSDNode > ( Intr -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; } } if ( Intr -> getOpcode ( ) == <STR_LIT> ) { switch ( cast < ConstantSDNode > ( Intr -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; } } return false ;


<s> bool Tile64VLIWPacketizerList :: isDirectJump ( const MachineInstr * MI ) const {

return ( MI -> getOpcode ( ) == <STR_LIT> ) ;


<s> if ( MEM_P ( SET_DEST ( in_set ) ) ) { out_set = single_set ( out_insn ) ; if ( ! out_set ) { out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) == PARALLEL ) { for ( i = <NUM_LIT> ; i < XVECLEN ( out_pat , <NUM_LIT> ) ; i ++ ) { out_exp = XVECEXP ( out_pat , <NUM_LIT> , i ) ; if ( ( GET_CODE ( out_exp ) == CLOBBER ) || ( GET_CODE ( out_exp ) == USE ) ) continue ; else if ( GET_CODE ( out_exp ) != SET ) return false ; } } } } } else { in_pat = PATTERN ( in_insn ) ; if ( GET_CODE ( in_pat ) != PARALLEL ) return false ; for ( i = <NUM_LIT> ; i < XVECLEN ( in_pat , <NUM_LIT> ) ; i ++ ) { in_exp = XVECEXP ( in_pat , <NUM_LIT> , i ) ; if ( ( GET_CODE ( in_exp ) == CLOBBER ) || ( GET_CODE ( in_exp ) == USE ) ) continue ; else if ( GET_CODE ( in_exp ) != SET ) return false ; if ( MEM_P ( SET_DEST ( in_exp ) ) ) { out_set = single_set ( out_insn ) ; if ( ! out_set ) { out_pat = PATTERN ( out_insn ) ; if ( GET_CODE ( out_pat ) != PARALLEL ) return false ; for ( j = <NUM_LIT> ; j < XVECLEN ( out_pat , <NUM_LIT> ) ; j ++ ) { out_exp = XVECEXP ( out_pat , <NUM_LIT> , j ) ; if ( ( GET_CODE ( out_exp ) == CLOBBER ) || ( GET_CODE ( out_exp ) == USE ) ) continue ; else if ( GET_CODE ( out_exp ) != SET ) return false ; } } }


<s> if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } } if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . hasOneUse ( ) && N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) { SDValue N00 = N0 . getOperand ( <NUM_LIT> ) ; if ( N00 . getOpcode ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , N00 . getOperand ( <NUM_LIT> ) , N00 . getOperand ( <NUM_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; } }

if ( VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return R ;


<s> bool hasDot1Insts ( ) const { return HasDot1Insts ;


<s> BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( ) ;


<s> report_fatal_error ( <STR_LIT> <STR_LIT> + GV -> getName ( ) , false ) ; } auto GlobalGet = PtrVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; const char * BaseName = MF . createExternalSymbolName ( <STR_LIT> ) ; SDValue BaseAddr ( DAG . getMachineNode ( GlobalGet , DL , PtrVT , DAG . getTargetExternalSymbol ( BaseName , PtrVT ) ) , <NUM_LIT> ) ; SDValue TLSOffset = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , GA -> getOffset ( ) , <STR_LIT> ) ; SDValue SymOffset = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSOffset ) ;

return DAG . getNode ( <STR_LIT> , DL , PtrVT , BaseAddr , SymOffset ) ;


<s> bool <ISA_LIT>MCAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OS << <STR_LIT> ; return true ;


<s> bool defaultTokenHasSuffix ( ) const {

StringRef Token ( Tok . Data , Tok . Length ) ;


<s> OptimizeSize = MinimizeSize = false ; for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReduceTable ) ; i != e ; ++ i ) { unsigned FromOpc = ReduceTable [ i ] . WideOpc ;

if ( ! ReduceOpcodeMap . insert ( std :: make_pair ( FromOpc , i ) ) . second ) assert ( false && <STR_LIT> ) ;


<s> return ( __m512i ) __builtin_ia32_cvtps2udq512_mask ( ( __v16sf ) __A , ( __v16si ) _mm512_undefined_si512 ( ) , ( __mmask16 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> void <ISA_LIT>InstPrinter :: printT2AddrModeImm12Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; O << <STR_LIT> << getRegisterName ( MO1 . getReg ( ) ) ; unsigned OffImm = MO2 . getImm ( ) ;

if ( OffImm ) O << <STR_LIT> << OffImm ;


<s> if ( TARGET_HARD_FLOAT ) { cmp = gen_float_relational ( test_code , cmp0 , cmp1 ) ; break ; } case E_DFmode : default : fatal_insn ( <STR_LIT> , gen_rtx_fmt_ee ( test_code , VOIDmode , cmp0 , cmp1 ) ) ; case E_SImode :


<s> return ( GET_CODE ( op ) == EQ || GET_CODE ( op ) == NE ) ;


<s> SrcMO . setReg ( NewVReg ) ; } else if ( ! IsVSReg ( DstMO . getReg ( ) , MRI ) && IsVSReg ( SrcMO . getReg ( ) , MRI ) ) { Changed = true ; const TargetRegisterClass * DstRC = & <STR_LIT> ; assert ( ( IsF8Reg ( DstMO . getReg ( ) , MRI ) || IsVSFReg ( DstMO . getReg ( ) , MRI ) || IsVSSReg ( DstMO . getReg ( ) , MRI ) ) && <STR_LIT> ) ; Register NewVReg = MRI . createVirtualRegister ( DstRC ) ;

BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVReg ) . add ( SrcMO ) ;


<s> MachineOperand & Base = getBaseOperand ( MI ) ; MachineOperand & Disp = getDispOperand ( MI ) ; MachineOperand & Scale = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; MachineOperand & Index = MI -> getOperand ( AddrOffset + <STR_LIT> ) ; MachineOperand & Segment = MI -> getOperand ( AddrOffset + <STR_LIT> ) ;

if ( ! ( ( Base . isReg ( ) && Base . getReg ( ) != <STR_LIT> ) || Base . isFI ( ) ) ) return false ;


<s> void <ISA_LIT>InstPrinter :: printFRMArg ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {

auto FRMArg = static_cast < <STR_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ;


<s> Value * opr1 = CI -> getArgOperand ( <NUM_LIT> ) ; ConstantFP * CF0 = dyn_cast < ConstantFP > ( opr0 ) ; ConstantFP * CF1 = dyn_cast < ConstantFP > ( opr1 ) ; if ( ( CF0 && CF1 ) || ( CF1 && ( getArgType ( FInfo ) == <ISA_LIT>LibFunc :: F32 ) ) ) { Value * nval1 = B . CreateFDiv ( ConstantFP :: get ( opr1 -> getType ( ) , <NUM_LIT> ) , opr1 , <STR_LIT> ) ; Value * nval = B . CreateFMul ( opr0 , nval1 , <STR_LIT> ) ; replaceCall ( nval ) ; return true ; }


<s> unsigned NumElems = OutVT . getVectorNumElements ( ) ; if ( ! Subtarget -> hasSSE2 ( ) || Subtarget -> hasAVX2 ( ) ) return SDValue ( ) ; EVT OutSVT = OutVT . getVectorElementType ( ) ; EVT InSVT = InVT . getVectorElementType ( ) ; if ( ! ( ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) && ( OutSVT == <STR_LIT> || OutSVT == <STR_LIT> ) && isPowerOf2_32 ( NumElems ) && NumElems >= <NUM_LIT> ) ) return SDValue ( ) ; if ( Subtarget -> hasSSSE3 ( ) && NumElems == <NUM_LIT> && ( ( OutSVT == <STR_LIT> && InSVT != <STR_LIT> ) || ( InSVT == <STR_LIT> && OutSVT == <STR_LIT> ) ) ) return SDValue ( ) ; SDLoc DL ( N ) ;

unsigned RegNum = InVT . getSizeInBits ( ) / <NUM_LIT> ;


<s> <ISA_LIT>AS AS = ST -> get<ISA_LIT>AS ( ) ; if ( AddrSpace == AS . GLOBAL_ADDRESS || AddrSpace == AS . CONSTANT_ADDRESS || AddrSpace == AS . CONSTANT_ADDRESS_32BIT ) { if ( ST -> getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( AddrSpace == AS . FLAT_ADDRESS || AddrSpace == AS . LOCAL_ADDRESS || AddrSpace == AS . REGION_ADDRESS ) return <NUM_LIT> ; if ( AddrSpace == AS . PRIVATE_ADDRESS ) return <NUM_LIT> * ST -> getMaxPrivateElementSize ( ) ;

if ( ST -> getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS && ( AddrSpace == AS . PARAM_D_ADDRESS || AddrSpace == AS . PARAM_I_ADDRESS || ( AddrSpace >= AS . CONSTANT_BUFFER_0 && AddrSpace <= AS . CONSTANT_BUFFER_15 ) ) ) return <NUM_LIT> ;


<s> unsigned OpSubReg = Op . getSubReg ( ) ; const TargetRegisterClass * OpRC = RI . getSubClassWithSubReg ( RI . getRegClassForReg ( MRI , OpReg ) , OpSubReg ) ; if ( DstRC == OpRC ) return ; unsigned DstReg = MRI . createVirtualRegister ( DstRC ) ; MachineInstr * Copy = BuildMI ( InsertMBB , I , DL , get ( <STR_LIT> ) , DstReg ) . add ( Op ) ; Op . setReg ( DstReg ) ; Op . setSubReg ( <NUM_LIT> ) ; MachineInstr * Def = MRI . getVRegDef ( OpReg ) ; if ( ! Def ) return ;

if ( Def -> isMoveImmediate ( ) && DstRC != & <STR_LIT> ) FoldImmediate ( * Copy , * Def , OpReg , & MRI ) ;


<s> Register Op0Reg = getRegForValue ( Op0 ) ; if ( Op0Reg == <NUM_LIT> ) return false ; if ( isa < ConstantPointerNull > ( Op1 ) ) Op1 = Constant :: getNullValue ( DL . getIntPtrType ( Op0 -> getContext ( ) ) ) ; if ( const ConstantInt * Op1C = dyn_cast < ConstantInt > ( Op1 ) ) { if ( unsigned CompareImmOpc = <ISA_LIT>ChooseCmpImmediateOpcode ( VT , Op1C ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , CurDbgLoc , TII . get ( CompareImmOpc ) ) . addReg ( Op0Reg ) . addImm ( Op1C -> getSExtValue ( ) ) ; return true ; }


<s> Value * MVEGatherScatterLowering :: tryCreateMaskedGatherBaseWB ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder , int64_t Increment ) { using namespace PatternMatch ; auto * Ty = cast < FixedVectorType > ( I -> getType ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;

if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ;


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : break ; }

return Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ;


<s> if ( MRI . hasOneDef ( Reg ) && MRI . hasOneUse ( Reg ) ) { MFI . stackifyVReg ( Reg ) ; } else { unsigned NewReg = MRI . createVirtualRegister ( MRI . getRegClass ( Reg ) ) ; Def -> getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; Op . setReg ( NewReg ) ; LIS . createAndComputeVirtRegInterval ( NewReg ) ; LiveInterval & LI = LIS . getInterval ( Reg ) ; LI . removeSegment ( LIS . getInstructionIndex ( * Def ) . getRegSlot ( ) , LIS . getInstructionIndex ( * Op . getParent ( ) ) . getRegSlot ( ) , true ) ; MFI . stackifyVReg ( NewReg ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Def -> dump ( ) ) ;


<s> unsigned isLS = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; bool isOnlyStoreBarrier = ( isLL == <NUM_LIT> && isLS == <NUM_LIT> ) ; <STR_LIT> DMBOpt ; if ( isDeviceBarrier ) DMBOpt = isOnlyStoreBarrier ? <STR_LIT> : <STR_LIT> ; else DMBOpt = isOnlyStoreBarrier ? <STR_LIT> : <STR_LIT> ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( DMBOpt , <STR_LIT> ) ) ;


<s> AMDGPU :: sub0 , AMDGPU :: sub1 , AMDGPU :: sub2 , AMDGPU :: sub3 , AMDGPU :: sub4 , AMDGPU :: sub5 , AMDGPU :: sub6 , AMDGPU :: sub7 , AMDGPU :: sub8 , AMDGPU :: sub9 , AMDGPU :: sub10 , AMDGPU :: sub11 , AMDGPU :: sub12 , AMDGPU :: sub13 , AMDGPU :: sub14 , AMDGPU :: sub15 } ; assert ( Channel < array_lengthof ( SubRegs ) ) ;


<s> void EmitARM64WinCFISetFP ( ) override {


<s> InstructionCost <ISA_LIT>TTIImpl :: getMaskedMemoryOpCost ( unsigned Opcode , Type * Src , Align Alignment , unsigned AddressSpace , TTI :: TargetCostKind CostKind ) { if ( ! isa < ScalableVectorType > ( Src ) ) return BaseT :: getMaskedMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; return getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ;


<s> if ( isAbsolute ( C . Op0 , FalseOp , TrueOp ) ) return getAbsolute ( DAG , DL , FalseOp , C . CCMask & <STR_LIT> ) ; } SDValue CCReg = emitCmp ( DAG , DL , C ) ; SDValue Ops [ ] = { TrueOp , FalseOp , DAG . getTargetConstant ( C . CCValid , DL , <STR_LIT> ) , DAG . getTargetConstant ( C . CCMask , DL , <STR_LIT> ) , CCReg } ;

return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Ops ) ;


<s> auto * Def = MRI -> getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( isTypeFoldingSupported ( Def -> getOpcode ( ) ) ) { auto Res = selectImpl ( I , * CoverageInfo ) ; assert ( Res || Def -> getOpcode ( ) == TargetOpcode :: G_CONSTANT ) ; if ( Res ) return Res ; } MRI -> replaceRegWith ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; I . removeFromParent ( ) ; } else if ( I . getNumDefs ( ) == <NUM_LIT> ) { MRI -> setType ( I . getOperand ( <NUM_LIT> ) . getReg ( ) , LLT :: scalar ( <NUM_LIT> ) ) ; } return true ; } if ( I . getNumOperands ( ) != I . getNumExplicitOperands ( ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; auto regSeq = getRegSeq ( ) ; Inst . addOperand ( MCOperand :: createReg ( regSeq . first ) ) ; Inst . addOperand ( MCOperand :: createReg ( regSeq . second ) ) ;


<s> void WinEHStatePass :: insertStateNumberStore ( Value * ParentRegNode , Instruction * IP , int State ) {


<s> if ( DstVT == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: getUINTTOFP ( SrcVT , DstVT ) ) ; if ( DstVT . isVector ( ) ) return lowerUINT_TO_FP_vec ( Op , DAG , Subtarget ) ; if ( SDValue Extract = vectorizeExtractedCast ( Op , DAG , Subtarget ) ) return Extract ; if ( Subtarget . hasAVX512 ( ) && isScalarFPTypeInSSEReg ( DstVT ) && ( SrcVT == <STR_LIT> || ( SrcVT == <STR_LIT> && Subtarget . is64Bit ( ) ) ) ) { return Op ; } if ( SrcVT == <STR_LIT> && Subtarget . is64Bit ( ) ) { Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; if ( IsStrict ) return DAG . getNode ( <STR_LIT> , dl , { DstVT , <STR_LIT> } , { Chain , Src } ) ; return DAG . getNode ( <STR_LIT> , dl , DstVT , Src ) ; } if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i64 ( Op , DAG , Subtarget ) ; if ( SrcVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 && DstVT != <STR_LIT> ) return LowerUINT_TO_FP_i32 ( Op , DAG , Subtarget ) ; if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; Align SlotAlign ( <NUM_LIT> ) ; MachinePointerInfo MPI = MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ; if ( SrcVT == <STR_LIT> ) {

SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , TypeSize :: Fixed ( <NUM_LIT> ) , dl ) ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> :


<s> SDValue DescAddr = LowerGlobalAddressDarwin ( Op , DAG ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , Align ( <NUM_LIT> ) , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFunction & F = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = F . getFrameInfo ( ) ; MFI . setAdjustsStack ( true ) ; auto TRI = getTargetMachine ( ) . getSubtargetImpl ( F . getFunction ( ) ) -> getRegisterInfo ( ) ; auto ARI = static_cast < const <ISA_LIT>RegisterInfo * > ( TRI ) ; const uint32_t * Mask = ARI -> getTLSCallPreservedMask ( DAG . getMachineFunction ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , FuncTLVGet , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getRegisterMask ( Mask ) , Chain . getValue ( <NUM_LIT> ) ) ;

return DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ;


<s> if ( optab_handler ( movmisalign_optab , mode ) == CODE_FOR_nothing ) return false ; if ( misalignment == - <NUM_LIT> ) {

if ( aarch64_simd_vector_alignment_reachable ( type , is_packed ) ) {


<s> static CodeModel :: Model getEffective<ISA_LIT>CodeModel ( Optional < CodeModel :: Model > CM ) { if ( CM ) {

if ( * CM != CodeModel :: Small && * CM != CodeModel :: Large ) report_fatal_error ( <STR_LIT> ) ;


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectSIToFP ( const Instruction * I ) {

return <ISA_LIT>SelectIntToFP ( I , true ) ;


<s> void <ISA_LIT>WinCOFFStreamer :: EmitWinEHHandlerData ( ) {

MCStreamer :: EmitWinEHHandlerData ( ) ;


<s> static DecodeStatus DecodeModImmTiedInstruction ( MCInst & Inst , uint32_t insn , uint64_t Addr , const void * Decoder ) { unsigned Rd = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned cmode = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ;

unsigned imm = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ;


<s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : SRetReturnReg ( <NUM_LIT> ) , HasClobberLR ( <NUM_LIT> ) {


<s> <ISA_LIT>TargetELFStreamer :: <ISA_LIT>TargetELFStreamer ( MCStreamer & S ) : <ISA_LIT>TargetStreamer ( S ) {


<s> if ( ( Imm & ~ <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; return CountTrailingZeros_32 ( Imm ) ;


<s> if ( NaClDontBreakABI ) { PointerSize = ( is64Bit && ! isX32 ) ? <NUM_LIT> : <NUM_LIT> ; } CalleeSaveStackSlotSize = is64Bit ? <NUM_LIT> : <NUM_LIT> ; AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> bool <ISA_LIT>RegisterInfo :: needsStackRealignment ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const Function * F = MF . getFunction ( ) ; unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ;

bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> hasFnAttr ( Attribute :: StackAlignment ) ) ;


<s> switch ( Modifier ) { case MCSymbolRefExpr :: VK_COFF_IMGREL32 : return COFF :: IMAGE_REL_<ISA_LIT>_ADDR32NB ; case MCSymbolRefExpr :: VK_SECREL : return COFF :: IMAGE_REL_<ISA_LIT>_SECREL ; default : return COFF :: IMAGE_REL_<ISA_LIT>_ADDR32 ; } case FK_SecRel_2 : return COFF :: IMAGE_REL_<ISA_LIT>_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_<ISA_LIT>_SECREL ; case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BRANCH20T ; case <STR_LIT> : return COFF :: IMAGE_REL_<ISA_LIT>_BRANCH24T ; case <STR_LIT> : case <STR_LIT> :

return COFF :: IMAGE_REL_<ISA_LIT>_BLX23T ;


<s> assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; assert ( DstVT . isVector ( ) && <STR_LIT> ) ; if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; EVT SrcVT = In . getValueType ( ) ; if ( SrcVT == DstVT ) return In ; unsigned DstSizeInBits = DstVT . getSizeInBits ( ) ; unsigned SrcSizeInBits = SrcVT . getSizeInBits ( ) ; if ( ( DstSizeInBits % <NUM_LIT> ) != <NUM_LIT> || ( SrcSizeInBits % <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; unsigned NumElems = SrcVT . getVectorNumElements ( ) ; if ( ! isPowerOf2_32 ( NumElems ) ) return SDValue ( ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; assert ( DstVT . getVectorNumElements ( ) == NumElems && <STR_LIT> ) ; assert ( SrcSizeInBits > DstSizeInBits && <STR_LIT> ) ; EVT PackedSVT = EVT :: getIntegerVT ( Ctx , SrcVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ; EVT InVT = <STR_LIT> , OutVT = <STR_LIT> ; if ( SrcVT . getScalarSizeInBits ( ) > <NUM_LIT> && ( Opcode == <STR_LIT> || Subtarget . hasSSE41 ( ) ) ) { InVT = <STR_LIT> ; OutVT = <STR_LIT> ; } if ( SrcVT . is128BitVector ( ) ) { InVT = EVT :: getVectorVT ( Ctx , InVT , <NUM_LIT> / InVT . getSizeInBits ( ) ) ; OutVT = EVT :: getVectorVT ( Ctx , OutVT , <NUM_LIT> / OutVT . getSizeInBits ( ) ) ; In = DAG . getBitcast ( InVT , In ) ; SDValue Res = DAG . getNode ( Opcode , DL , OutVT , In , DAG . getUNDEF ( InVT ) ) ; Res = extractSubVector ( Res , <NUM_LIT> , DAG , DL , <NUM_LIT> ) ; return DAG . getBitcast ( DstVT , Res ) ; }

unsigned NumSubElts = NumElems / <NUM_LIT> ;


<s> prefer_subfunc_size = std :: min ( max_subfunc_size , prefer_subfunc_size ) ; if ( prefer_subfunc_size < <NUM_LIT> ) { report_fatal_error ( <STR_LIT> ) ; } prefer_scc_size = std :: min ( max_subfunc_size , prefer_scc_size ) ; unsigned total_size = <NUM_LIT> ; bool blocks_splitted = false ; MachineDominatorTree & MDT = getAnalysis < MachineDominatorTree > ( ) ; MachinePostDominatorTree & MPDT = getAnalysis < MachinePostDominatorTree > ( ) ; for ( MachineFunction :: iterator i ( MF . begin ( ) ) , ie ( MF . end ( ) ) ; i != ie ; i ++ ) { unsigned bb_size = agraph :: getBBSize ( & * i , PTM ) ; if ( bb_size + agraph :: getMaxBlockMargin ( PTM , & * i ) > max_subfunc_size ) { bb_size = agraph :: splitBlock ( & * i , max_subfunc_size , PTM , MDT , MPDT ) ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __lwpval32 ( unsigned int __data2 , unsigned int __data1 , unsigned int __flags ) {


<s> return true ; case UNSPEC_TPOFF : if ( ! TARGET_64BIT ) return true ; break ; default : break ;


<s> SDValue Op = BVN -> getOperand ( I ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { unsigned Elem = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; GS . add ( Op . getOperand ( <NUM_LIT> ) , Elem ) ; FoundOne = true ; } else if ( Op . isUndef ( ) ) { GS . addUndef ( ) ; } else { GS . add ( SDValue ( ) , ResidueOps . size ( ) ) ; ResidueOps . push_back ( BVN -> getOperand ( I ) ) ; } } if ( ! FoundOne ) return SDValue ( ) ; if ( ! ResidueOps . empty ( ) ) { while ( ResidueOps . size ( ) < NumElements ) ResidueOps . push_back ( DAG . getUNDEF ( ResidueOps [ <NUM_LIT> ] . getValueType ( ) ) ) ; for ( auto & Op : GS . Ops ) { if ( ! Op . getNode ( ) ) { Op = DAG . getBuildVector ( VT , SDLoc ( BVN ) , ResidueOps ) ;


<s> FrameIdx = CRSpillFrameIdx ; } else { MachineFrameInfo * MFI = ( ( MachineFunction & ) MF ) . getFrameInfo ( ) ; FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) <NUM_LIT> , ( int64_t ) - <NUM_LIT> , true ) ; CRSpillFrameIdx = FrameIdx ; } return true ; } return false ;


<s> static bool isVSplat ( SDValue N , APInt & Imm , bool IsLittleEndian ) { BuildVectorSDNode * Node = dyn_cast < BuildVectorSDNode > ( N . getNode ( ) ) ; if ( Node == NULL ) return false ;


<s> auto PState = <STR_LIT> ( Tok . getString ( ) ) ; unsigned PStateImm = - <NUM_LIT> ; if ( PState && PState -> haveFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) PStateImm = PState -> Encoding ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , MRSReg , MSRReg , PStateImm , getContext ( ) ) ) ;


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ;


<s> <ISA_LIT>ConstantPoolJT :: <ISA_LIT>ConstantPoolJT ( Type * Ty , int JTIndex , unsigned PCAdj , <STR_LIT> Modifier , bool AddCurrentAddress ) : <ISA_LIT>ConstantPoolValue ( Ty , <STR_LIT> , PCAdj , Modifier , AddCurrentAddress ) , JTI ( JTIndex ) {


<s> unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; switch ( IntNo ) {


return VT . getSizeInBits ( ) >= <NUM_LIT> && ( VT . getSizeInBits ( ) - DAG . ComputeNumSignBits ( Op ) ) < <NUM_LIT> ;


<s> return createELFObjectWriter ( MOTW , OS , true ) ;


<s> fprintf ( stream , <STR_LIT> , value ) ;


<s> MachineInstr * MI = MBB -> getParent ( ) -> CreateMachineInstr ( TII -> get ( NewOpcode ) , DL ) ;

if ( ! MBB -> empty ( ) ) MBB -> insert ( MBB -> begin ( ) , MI ) ;


<s> getAddrMode6AddressOpValue ( const MCInst & MI , unsigned Op , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & Reg = MI . getOperand ( Op ) ; const MCOperand & Imm = MI . getOperand ( Op + <NUM_LIT> ) ;

unsigned RegNo = CTX . getRegisterInfo ( ) -> getEncodingValue ( Reg . getReg ( ) ) ;


<s> Inserter ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , TII ( tm . getInstrInfo ( ) ) {


<s> SDValue <ISA_LIT>TargetLowering :: ExtractBitFromMaskVector ( SDValue Op , SelectionDAG & DAG ) const { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Vec ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; MVT EltVT = Op . getSimpleValueType ( ) ; assert ( ( EltVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> || Subtarget -> hasBWI ( ) ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { MVT ExtVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtVT . getVectorElementType ( ) , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , EltVT , Elt ) ; } unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; const TargetRegisterClass * rc = getRegClassFor ( VecVT ) ; if ( ! Subtarget -> hasDQI ( ) && ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> ) ) rc = getRegClassFor ( <STR_LIT> ) ; unsigned MaxSift = rc -> getSize ( ) * <NUM_LIT> - <NUM_LIT> ;

Vec = DAG . getNode ( <STR_LIT> , dl , VecVT , Vec , DAG . getConstant ( MaxSift - IdxVal , dl , <STR_LIT> ) ) ;


<s> void <ISA_LIT>InstPrinter :: printCoprocOptionImm ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm ( ) << <STR_LIT> ;


<s> int64_t Imm ; bool Success = MI -> getOperand ( OpNo ) . getExpr ( ) -> evaluateAsAbsolute ( Imm ) ; Imm = SignExtend64 < <NUM_LIT> > ( Imm ) ; assert ( Success ) ; ( void ) Success ;

assert ( ( ( Imm & <NUM_LIT> ) == <NUM_LIT> ) && <STR_LIT> ) ;


<s> bool has65C02 ( ) const { return Has65C02Insns ;


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > x ( The<ISA_LIT>Target ) ;


<s> const char * output_probe_stack_range ( rtx reg1 , rtx reg2 ) { static int labelno = <NUM_LIT> ; char loop_lab [ <NUM_LIT> ] ; rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; output_asm_insn ( <STR_LIT> , xops ) ; if ( TARGET_ARCH64 ) fputs ( <STR_LIT> , asm_out_file ) ; else fputs ( <STR_LIT> , asm_out_file ) ; assemble_name_raw ( asm_out_file , loop_lab ) ; fputc ( '\n' , asm_out_file ) ; xops [ <NUM_LIT> ] = GEN_INT ( SPARC_STACK_BIAS ) ;


<s> void EmitRegModRMByte ( const MCOperand & ModRMReg , unsigned RegOpcodeFld , unsigned & CurByte , raw_ostream & OS ) const { EmitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeFld , Get<ISA_LIT>RegNum ( ModRMReg ) ) , CurByte , OS ) ;


<s> rtx a_hi8 = NULL_RTX ; if ( avr_mem_flash_p ( xop [ <NUM_LIT> ] ) ) return false ; if ( ! CONST_INT_P ( xop [ <NUM_LIT> ] ) ) return false ; count = INTVAL ( xop [ <NUM_LIT> ] ) ; if ( count <= <NUM_LIT> ) return false ; a_src = XEXP ( xop [ <NUM_LIT> ] , <NUM_LIT> ) ; a_dest = XEXP ( xop [ <NUM_LIT> ] , <NUM_LIT> ) ; if ( PSImode == GET_MODE ( a_src ) ) { gcc_assert ( as == ADDR_SPACE_MEMX ) ; loop_mode = ( count < <NUM_LIT> ) ? QImode : HImode ; loop_reg = gen_rtx_REG ( loop_mode , <NUM_LIT> ) ; emit_move_insn ( loop_reg , gen_int_mode ( count , loop_mode ) ) ; addr1 = simplify_gen_subreg ( HImode , a_src , PSImode , <NUM_LIT> ) ; a_hi8 = simplify_gen_subreg ( QImode , a_src , PSImode , <NUM_LIT> ) ; } else { int segment = avr_addrspace [ as ] . segment ; if ( segment && avr_n_flash > <NUM_LIT> ) { a_hi8 = GEN_INT ( segment ) ; emit_move_insn ( rampz_rtx , a_hi8 = copy_to_mode_reg ( QImode , a_hi8 ) ) ;


<s> const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = std :: next ( MachineFunction :: iterator ( BB ) ) ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * FBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * TBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * Sink = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , FBB ) ; F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; Register VR2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ;

Register VR1 = RegInfo . createVirtualRegister ( RC ) ;


<s> else if ( from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM ) return pdp11_reg_save_size ( ) + <NUM_LIT> ;

else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) return pdp11_reg_save_size ( ) + <NUM_LIT> + get_frame_size ( ) ;


<s> Elements . push_back ( dwarf :: DW_OP_constu ) ; Elements . push_back ( Coef + <NUM_LIT> ) ; Elements . push_back ( dwarf :: DW_OP_mul ) ; } else { if ( Op && Op2 . getReg ( ) != <STR_LIT> ) { int dwarfReg = TRI -> getDwarfRegNum ( Op2 . getReg ( ) , false ) ; if ( dwarfReg < <NUM_LIT> ) return None ; else if ( dwarfReg < <NUM_LIT> ) Elements . push_back ( dwarf :: DW_OP_reg0 + dwarfReg ) ; else { Elements . push_back ( dwarf :: DW_OP_regx ) ; Elements . push_back ( dwarfReg ) ; } } else if ( ! Op ) { assert ( Op2 . getReg ( ) != <STR_LIT> ) ; Op = & Op2 ; } if ( Coef > <NUM_LIT> ) { assert ( Op2 . getReg ( ) != <STR_LIT> ) ; Elements . push_back ( dwarf :: DW_OP_constu ) ; Elements . push_back ( Coef ) ; Elements . push_back ( dwarf :: DW_OP_mul ) ; } if ( ( ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) || Op1 . isFI ( ) ) && Op2 . getReg ( ) != <STR_LIT> ) { Elements . push_back ( dwarf :: DW_OP_plus ) ; } } if ( Offset < <NUM_LIT> ) { Elements . push_back ( dwarf :: DW_OP_constu ) ; Elements . push_back ( - Offset ) ; Elements . push_back ( dwarf :: DW_OP_minus ) ; } else if ( Offset > <NUM_LIT> ) { Elements . push_back ( dwarf :: DW_OP_constu ) ; Elements . push_back ( Offset ) ; Elements . push_back ( dwarf :: DW_OP_plus ) ; } Expr = DIExpression :: get ( MI . getMF ( ) -> getFunction ( ) . getContext ( ) , Elements ) ;

return ParamLoadedValue ( Op , Expr ) ; ;


<s> bool isImmSExti32i8 ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return true ; uint64_t Value = CE -> getValue ( ) ; return ( ( Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) || ( <NUM_LIT> <= Value && Value <= <NUM_LIT> ) ) ;


<s> assert ( Subtarget . hasP9Vector ( ) && <STR_LIT> ) ; NumPESpillVSR += <NUM_LIT> ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , Dst ) . addReg ( VSRContainingGPRs [ Dst ] . first , getKillRegState ( true ) ) . addReg ( VSRContainingGPRs [ Dst ] . second , getKillRegState ( true ) ) ; } else if ( VSRContainingGPRs [ Dst ] . second == <NUM_LIT> ) { assert ( Subtarget . hasP8Vector ( ) && <STR_LIT> ) ; ++ NumPESpillVSR ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , TRI -> getSubReg ( Dst , <STR_LIT> ) ) . addReg ( VSRContainingGPRs [ Dst ] . first , getKillRegState ( true ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } Spilled . set ( Dst ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; if ( Subtarget . needsSwapsForVSXMemOps ( ) && ! MF -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) TII . storeRegToStackSlotNoUpd ( MBB , MI , Reg , ! IsLiveIn , I . getFrameIdx ( ) , RC , TRI ) ; else TII . storeRegToStackSlot ( MBB , MI , Reg , ! IsLiveIn , I . getFrameIdx ( ) , RC , TRI ) ; } }


<s> <ISA_LIT>16InstrInfo :: <ISA_LIT>16InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>InstrInfo ( STI , <STR_LIT> ) , RI ( STI ) {


<s> } else if ( ( DarwinRefKind == MCSymbolRefExpr :: VK_GOTPAGE || DarwinRefKind == MCSymbolRefExpr :: VK_TLVPPAGE ) && Addend != <NUM_LIT> ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } else if ( DarwinRefKind != MCSymbolRefExpr :: VK_PAGE && DarwinRefKind != MCSymbolRefExpr :: VK_GOTPAGE && DarwinRefKind != MCSymbolRefExpr :: VK_TLVPPAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_ABS_PAGE_NC && ELFRefKind != <ISA_LIT>MCExpr :: VK_GOT_PAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_GOT_PAGE_LO15 && ELFRefKind != <ISA_LIT>MCExpr :: VK_GOTTPREL_PAGE && ELFRefKind != <ISA_LIT>MCExpr :: VK_TLSDESC_PAGE ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } SMLoc E = SMLoc :: getFromPointer ( getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( Expr , S , E , getContext ( ) ) ) ;


<s> map < unsigned , Location > :: iterator findCurUseLoc = curLocs . find ( usePred ) ; assert ( findCurUseLoc != curLocs . end ( ) ) ; Location & curUseLoc = findCurUseLoc -> second ; if ( curUseLoc . isStack ( ) ) { auto useloc_newloc = handleIfNotInRegister ( blockIndex , FreeLocs , curLocs , curUseLoc . getLoc ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << usePred << <STR_LIT> << useloc_newloc . second << <STR_LIT> ) ; curUseLoc = useloc_newloc . second ; return useloc_newloc . first ; } else {

return UseLoc ( curUseLoc . getLoc ( ) ) ;


<s> return llvm :: make_unique < <ISA_LIT>TargetObjectFile > ( ) ;


<s> const MCRegisterInfo * getRegInfo ( ) const { return RegInfo ;


<s> emit_library_call ( gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) , <NUM_LIT> , VOIDmode , <NUM_LIT> ) ;


<s> while ( I1 != List . end ( ) ) { MachineInstr & First = * * I1 ; auto I2 = std :: next ( I1 ) ; while ( I2 != List . end ( ) ) { MachineInstr & Last = * * I2 ; int64_t AddrDispShift ; assert ( calcInstrDist ( First , Last ) > <NUM_LIT> && <STR_LIT> ) ; if ( ! isReplaceable ( First , Last , AddrDispShift ) ) { ++ I2 ; continue ; } Register FirstVReg = First . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register LastVReg = Last . getOperand ( <NUM_LIT> ) . getReg ( ) ; for ( auto UI = MRI -> use_begin ( LastVReg ) , UE = MRI -> use_end ( ) ; UI != UE ; ) { MachineOperand & MO = * UI ++ ; MachineInstr & MI = * MO . getParent ( ) ; if ( MI . isDebugValue ( ) ) { replaceDebugValue ( MI , FirstVReg , AddrDispShift ) ; continue ; } const MCInstrDesc & Desc = MI . getDesc ( ) ; int MemOpNo = <STR_LIT> ( Desc . TSFlags ) + <STR_LIT> ( Desc ) ; MO . setReg ( FirstVReg ) ; MachineOperand & Op = MI . getOperand ( MemOpNo + <STR_LIT> ) ; if ( Op . isImm ( ) ) Op . setImm ( Op . getImm ( ) + AddrDispShift ) ;

else if ( ! Op . isJTI ( ) ) Op . setOffset ( Op . getOffset ( ) + AddrDispShift ) ;


<s> if ( known_eq ( UINTVAL ( offset1 ) + size , UINTVAL ( offset2 ) ) ) { * reversed = false ; return true ; } if ( known_eq ( UINTVAL ( offset2 ) + size , UINTVAL ( offset1 ) ) ) { * reversed = true ; return true ; }


<s> bool hasNegativeUnalignedScratchOffsetBug ( ) const {


<s> Position . Address = alignTo ( Position . Address , Block . Alignment ) ; Block . Address = Position . Address ;


<s> bool isFPCloseToIncomingSP ( ) const override {


<s> static SDValue lowerVectorShuffleAsLanePermuteAndBlend ( SDLoc DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , SelectionDAG & DAG ) { assert ( VT . is256BitVector ( ) && <STR_LIT> ) ; int LaneSize = Mask . size ( ) / <NUM_LIT> ; bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; if ( ! LaneCrossing [ <NUM_LIT> ] || ! LaneCrossing [ <NUM_LIT> ] ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; if ( isSingleInputShuffleMask ( Mask ) ) { SmallVector < int , <NUM_LIT> > FlippedBlendMask ;

for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) FlippedBlendMask . push_back ( Mask [ i ] < <NUM_LIT> ? - <NUM_LIT> : ( ( ( Mask [ i ] % Size ) / LaneSize == i / LaneSize ) ? Mask [ i ] : Mask [ i ] % LaneSize + ( i / LaneSize ) * LaneSize + Size ) ) ;


<s> case LT : case UNLT : if ( code == LT && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , const1_rtx ) ) ; intcmp_mode = CCmode ; code = EQ ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , const1_rtx ) ) ; code = NE ; } break ; case GE : case UNGE : if ( code == GE || ! TARGET_IEEE_FP ) { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = EQ ; } else { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_xorqi_cc_ext_1 ( scratch , scratch , const1_rtx ) ) ; code = NE ; } break ; case LE : case UNLE : if ( code == LE && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_addqi_ext_1 ( scratch , scratch , constm1_rtx ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; intcmp_mode = CCmode ; code = LTU ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = NE ; } break ; case EQ : case UNEQ : if ( code == EQ && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; intcmp_mode = CCmode ; code = EQ ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = NE ; } break ; case NE : case LTGT : if ( code == NE && TARGET_IEEE_FP ) {


<s> if ( isa < ConstantPointerNull > ( Phi -> getIncomingValue ( I ) ) ) Phi -> setIncomingValue ( I , ConstantPointerNull :: get ( NewTy ) ) ; } } continue ; } IntrinsicInst * Intr = dyn_cast < IntrinsicInst > ( Call ) ; if ( ! Intr ) { std :: vector < Type * > ArgTypes ; for ( unsigned ArgIdx = <NUM_LIT> , ArgEnd = Call -> getNumArgOperands ( ) ; ArgIdx != ArgEnd ; ++ ArgIdx ) { ArgTypes . push_back ( Call -> getArgOperand ( ArgIdx ) -> getType ( ) ) ; } Function * F = Call -> getCalledFunction ( ) ; FunctionType * NewType = FunctionType :: get ( Call -> getType ( ) , ArgTypes , F -> isVarArg ( ) ) ; Constant * C = Mod -> getOrInsertFunction ( ( F -> getName ( ) + <STR_LIT> ) . str ( ) , NewType , F -> getAttributes ( ) ) ; Function * NewF = cast < Function > ( C ) ; Call -> setCalledFunction ( NewF ) ; continue ; } Builder . SetInsertPoint ( Intr ) ; switch ( Intr -> getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : Intr -> eraseFromParent ( ) ; continue ; case <STR_LIT> : { MemCpyInst * MemCpy = cast < MemCpyInst > ( Intr ) ; Builder . CreateMemCpy ( MemCpy -> getRawDest ( ) , MemCpy -> getRawSource ( ) , MemCpy -> getLength ( ) , MemCpy -> getAlignment ( ) , MemCpy -> isVolatile ( ) ) ; Intr -> eraseFromParent ( ) ; continue ; } case <STR_LIT> : { MemMoveInst * MemMove = cast < MemMoveInst > ( Intr ) ; Builder . CreateMemMove ( MemMove -> getRawDest ( ) , MemMove -> getRawSource ( ) , MemMove -> getLength ( ) , MemMove -> getAlignment ( ) , MemMove -> isVolatile ( ) ) ; Intr -> eraseFromParent ( ) ; continue ; } case <STR_LIT> : { MemSetInst * MemSet = cast < MemSetInst > ( Intr ) ; Builder . CreateMemSet ( MemSet -> getRawDest ( ) , MemSet -> getValue ( ) , MemSet -> getLength ( ) , MemSet -> getAlignment ( ) , MemSet -> isVolatile ( ) ) ; Intr -> eraseFromParent ( ) ; continue ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Intr -> eraseFromParent ( ) ; continue ; case <STR_LIT> : {

Value * Src = Intr -> getOperand ( <NUM_LIT> ) ;


<s> static bool arc_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) {

return ( arc_hard_regno_modes [ regno ] & arc_mode_class [ mode ] ) != <NUM_LIT> ;


<s> if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { SrcReg = <ISA_LIT>EmitIntExt ( SrcVT , SrcReg , <STR_LIT> , ! isSigned ) ; if ( SrcReg == <NUM_LIT> ) return false ; } unsigned FP = <ISA_LIT>MoveToFPReg ( <STR_LIT> , SrcReg ) ; if ( FP == <NUM_LIT> ) return false ; unsigned Opc ; if ( Ty -> isFloatTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ; else if ( Ty -> isDoubleTy ( ) ) Opc = isSigned ? <STR_LIT> : <STR_LIT> ;


<s> uint32_t <ISA_LIT>MCCodeEmitter :: getAdrLabelOpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand MO = MI . getOperand ( OpIdx ) ; if ( MO . isExpr ( ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups ) ; int32_t offset = MO . getImm ( ) ; uint32_t Val = <NUM_LIT> ;


<s> <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ i ] ) ; if ( ( Op . isReg ( ) || Op . isImm ( ) ) && ! Op . hasModifiers ( ) ) Op . setModifiers ( <NUM_LIT> ) ; } } return Res ; } return MatchOperand_NoMatch ;


<s> return __builtin_aarch64_lceiluv4sfv4si_us ( __a ) ;


<s> uint64_t UValue = CN -> getZExtValue ( ) ; uint32_t upper = uint32_t ( UValue >> <NUM_LIT> ) ; uint32_t lower = uint32_t ( UValue ) ; if ( upper != lower ) return SDValue ( ) ; Value = Value >> <NUM_LIT> ; }

if ( Value <= <NUM_LIT> ) return DAG . getTargetConstant ( Value , ValueType ) ;


<s> fputc ( '"' , stream ) ; while ( * string && ( unsigned char ) * string < <NUM_LIT> && ! ISCNTRL ( * string ) && strchr ( unwanted_chars , * string ) == NULL && string < string_end ) { fputc ( * string , stream ) ; string ++ ; } fputc ( '"' , stream ) ; if ( string < string_end ) fprintf ( stream , <STR_LIT> ) ; } if ( string < string_end ) { fprintf ( stream , <STR_LIT> , * string & <NUM_LIT> ) ;


<s> SDNode * In128 = DAG . getMachineNode ( Extend , DL , <STR_LIT> , Op0 ) ; SDValue Result = DAG . getNode ( Opcode , DL , <STR_LIT> , SDValue ( In128 , <NUM_LIT> ) , Op1 ) ; bool Is32Bit = is32Bit ( VT ) ;

Even = DAG . getTargetExtractSubreg ( <STR_LIT> ( Is32Bit ) , DL , VT , Result ) ;


<s> virtual void EmitARM64WinCFINop ( ) {


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc Loc ( N ) ; const uint16_t * OurOpcodes ; switch ( VT . getVectorElementType ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : OurOpcodes = Opcodes [ <NUM_LIT> ] ; break ; case <NUM_LIT> : OurOpcodes = Opcodes [ <NUM_LIT> ] ; break ; case <NUM_LIT> : OurOpcodes = Opcodes [ <NUM_LIT> ] ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } EVT DataTy = EVT :: getVectorVT ( * CurDAG -> getContext ( ) , <STR_LIT> , NumVecs * <NUM_LIT> ) ; EVT ResultTys [ ] = { DataTy , <STR_LIT> } ; auto Data = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , Loc , DataTy ) , <NUM_LIT> ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; for ( unsigned Stage = <NUM_LIT> ; Stage < NumVecs ; ++ Stage ) { SDValue Ops [ ] = { Data , N -> getOperand ( <NUM_LIT> ) , Chain } ; auto LoadInst = CurDAG -> getMachineNode ( OurOpcodes [ Stage ] , Loc , ResultTys , Ops ) ; Data = SDValue ( LoadInst , <NUM_LIT> ) ; Chain = SDValue ( LoadInst , <NUM_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i < NumVecs ; i ++ ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( <STR_LIT> + i , Loc , VT , Data ) ) ;

ReplaceUses ( SDValue ( N , NumVecs ) , Chain ) ;


<s> unsigned Reg0 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SubReg1 = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned SubReg2 = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; bool Reg1IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool Reg2IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ChangeReg0 = false ; if ( Reg0 == Reg1 ) { assert ( MI -> getDesc ( ) . getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) == SubReg1 && <STR_LIT> ) ; Reg2IsKill = false ; ChangeReg0 = true ; } unsigned MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( NewMI ) { unsigned Reg0 = ChangeReg0 ? Reg2 : MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Reg0IsDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; return BuildMI ( MF , MI -> getDebugLoc ( ) , MI -> getDesc ( ) ) . addReg ( Reg0 , RegState :: Define | getDeadRegState ( Reg0IsDead ) ) . addReg ( Reg2 , getKillRegState ( Reg2IsKill ) ) . addReg ( Reg1 , getKillRegState ( Reg1IsKill ) ) . addImm ( ( ME + <NUM_LIT> ) & <NUM_LIT> ) . addImm ( ( MB - <NUM_LIT> ) & <NUM_LIT> ) ; } if ( ChangeReg0 ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( Reg2 ) ;

MI -> getOperand ( <NUM_LIT> ) . setSubReg ( SubReg2 ) ;


<s> bool <ISA_LIT>InstrInfo :: optimizeCompareInstr ( MachineInstr * Compare , unsigned SrcReg , unsigned SrcReg2 , int Mask , int Value , const MachineRegisterInfo * MRI ) const { assert ( ! SrcReg2 && <STR_LIT> ) ; bool IsLogical = ( Compare -> getDesc ( ) . TSFlags & <STR_LIT> ) != <NUM_LIT> ; if ( Value == <NUM_LIT> && ! IsLogical && removeIPMBasedCompare ( Compare , SrcReg , MRI , TM . getRegisterInfo ( ) ) ) return true ; return false ;


<s> ArrayRef < int > Mask = SVOp -> getMask ( ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; int NumElements = VT . getVectorNumElements ( ) ; SDLoc DL ( Op ) ; bool Is1BitVector = ( VT . getVectorElementType ( ) == <STR_LIT> ) ; assert ( ( VT . getSizeInBits ( ) != <NUM_LIT> || Is1BitVector ) && <STR_LIT> ) ; bool V1IsUndef = V1 . isUndef ( ) ; bool V2IsUndef = V2 . isUndef ( ) ; if ( V1IsUndef && V2IsUndef ) return DAG . getUNDEF ( VT ) ; if ( V1IsUndef ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( V2IsUndef ) for ( int M : Mask ) if ( M >= NumElements ) { SmallVector < int , <NUM_LIT> > NewMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int & M : NewMask ) if ( M >= NumElements ) M = - <NUM_LIT> ; return DAG . getVectorShuffle ( VT , DL , V1 , V2 , NewMask ) ; } int MaskUpperLimit = Mask . size ( ) * ( V2IsUndef ? <NUM_LIT> : <NUM_LIT> ) ; ( void ) MaskUpperLimit ; assert ( llvm :: all_of ( Mask , [ & ] ( int M ) { return - <NUM_LIT> <= M && M < MaskUpperLimit ; } ) && <STR_LIT> ) ; APInt Zeroable = computeZeroableShuffleElements ( Mask , V1 , V2 ) ; if ( Zeroable . isAllOnesValue ( ) ) return getZeroVector ( VT , Subtarget , DAG , DL ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( VT . getScalarSizeInBits ( ) < <NUM_LIT> && ! Is1BitVector && canWidenShuffleElements ( Mask , WidenedMask ) ) { MVT NewEltVT = VT . isFloatingPoint ( ) ? <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) : <STR_LIT> ( VT . getScalarSizeInBits ( ) * <NUM_LIT> ) ; MVT NewVT = <STR_LIT> ( NewEltVT , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; if ( DAG . getTargetLoweringInfo ( ) . isTypeLegal ( NewVT ) ) { V1 = DAG . getBitcast ( NewVT , V1 ) ; V2 = DAG . getBitcast ( NewVT , V2 ) ; return DAG . getBitcast ( VT , DAG . getVectorShuffle ( NewVT , DL , V1 , V2 , WidenedMask ) ) ; } } if ( canonicalizeShuffleMaskWithCommute ( Mask ) ) return DAG . getCommutedVectorShuffle ( * SVOp ) ; if ( VT . is128BitVector ( ) ) return lower128BitVectorShuffle ( DL , Mask , VT , V1 , V2 , Zeroable , Subtarget , DAG ) ; if ( VT . is256BitVector ( ) ) return lower256BitVectorShuffle ( DL , Mask , VT , V1 , V2 , Zeroable , Subtarget , DAG ) ;

if ( VT . is512BitVector ( ) ) return lower512BitVectorShuffle ( DL , Mask , VT , V1 , V2 , Zeroable , Subtarget , DAG ) ;


<s> MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src1 , Src1RC , <STR_LIT> , Src1SubRC ) ; unsigned LoOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * LoHalf = BuildMI ( MBB , MII , DL , get ( LoOpc ) , DestSub0 ) . addReg ( CarryReg , RegState :: Define ) . add ( SrcReg0Sub0 ) . add ( SrcReg1Sub0 ) ; unsigned HiOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , get ( HiOpc ) , DestSub1 ) . addReg ( DeadCarryReg , RegState :: Define | RegState :: Dead ) . add ( SrcReg0Sub1 ) . add ( SrcReg1Sub1 ) . addReg ( CarryReg , RegState :: Kill ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; legalizeOperands ( * LoHalf ) ;


<s> TargetMachine * TM = & getAnalysis < TargetPassConfig > ( ) . getTM < TargetMachine > ( ) ; TargetLibraryInfo * TLI = & getAnalysis < TargetLibraryInfoWrapperPass > ( ) . getTLI ( F ) ; <ISA_LIT>LowerAMXCast LAC ( F ) ;


return DecodeRegisterClass ( Inst , RegNo , HvxWRDecoderTable ) ;


<s> } if ( ! RMin ) return getInt64Direct ( CurDAG , dl , Imm ) ; auto getI32Imm = [ CurDAG , dl ] ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ; } ; SDValue Val = SDValue ( getInt64Direct ( CurDAG , dl , MatImm ) , <NUM_LIT> ) ; return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Val , getI32Imm ( <NUM_LIT> - RMin ) , getI32Imm ( MaskEnd ) ) ;


<s> DebugLoc dl ; <ISA_LIT>FunctionInfo * AFI = MBB . getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; int BOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; int BccOpc = ! AFI -> isThumbFunction ( ) ? <STR_LIT> : ( AFI -> isThumb2Function ( ) ? <STR_LIT> : <STR_LIT> ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ;


<s> void maybe_unlink ( const char * file ) { if ( ! save_temps ) {

if ( unlink_if_ordinary ( file ) && errno != ENOENT ) fatal_error ( input_location , <STR_LIT> , file ) ;


<s> return ( __m128d ) __builtin_ia32_cmplepd ( ( __v2df ) __A , ( __v2df ) __B ) ;


return isUImm < <NUM_LIT> , <NUM_LIT> > ( ) ;


<s> <ISA_LIT>NewValueJump ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>NewValueJumpPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> operands [ <NUM_LIT> * i + <NUM_LIT> ] = src [ i ] ; } } else { for ( i = <NUM_LIT> ; i < count ; i ++ ) { operands [ <NUM_LIT> * i ] = dest [ count - i - <NUM_LIT> ] ;

operands [ <NUM_LIT> * i + <NUM_LIT> ] = src [ count - i - <NUM_LIT> ] ;


<s> assert ( isalpha ( RegName [ <NUM_LIT> ] ) && isdigit ( RegName [ <NUM_LIT> ] ) ) ; O << ( RegName + <NUM_LIT> ) ;


<s> bool <ISA_LIT>RegisterInfo :: isAsmClobberable ( const MachineFunction & MF , MCRegister PhysReg ) const {

return ! MF . getRegInfo ( ) . isReserved ( PhysReg ) ;


<s> assert ( frameSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; } else { frameSize += <NUM_LIT> ;

frameSize = RoundUpToAlignment ( frameSize , <NUM_LIT> ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineBranchProbabilityInfo > ( ) ; AU . addRequired < MachineDominatorTree > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> MachineBasicBlock * finish = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loop ) ; F -> insert ( It , finish ) ; finish -> splice ( finish -> begin ( ) , MBB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; finish -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( loop ) ; MBB -> addSuccessor ( finish ) ; loop -> addSuccessor ( finish ) ; loop -> addSuccessor ( loop ) ; unsigned IAMT = R . createVirtualRegister ( <STR_LIT> ) ; BuildMI ( MBB , dl , TII -> get ( <STR_LIT> ) , IAMT ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) ; unsigned IVAL = R . createVirtualRegister ( <STR_LIT> ) ; BuildMI ( MBB , dl , TII -> get ( <STR_LIT> ) , IVAL ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , dl , TII -> get ( <STR_LIT> ) ) . addReg ( IAMT ) . addMBB ( finish ) ; unsigned DST = R . createVirtualRegister ( <STR_LIT> ) ; unsigned NDST = R . createVirtualRegister ( <STR_LIT> ) ; BuildMI ( loop , dl , TII -> get ( <STR_LIT> ) , DST ) . addReg ( IVAL ) . addMBB ( MBB ) . addReg ( NDST ) . addMBB ( loop ) ; unsigned SAMT = R . createVirtualRegister ( <STR_LIT> ) ; unsigned NAMT = R . createVirtualRegister ( <STR_LIT> ) ;

BuildMI ( loop , dl , TII -> get ( <STR_LIT> ) , SAMT ) . addReg ( IAMT ) . addMBB ( MBB ) . addReg ( NAMT ) . addMBB ( loop ) ;


<s> unsigned CPELogAlign = getCPELogAlign ( * CPEMI ) ; MachineBasicBlock * UserMBB = UserMI -> getParent ( ) ; const BasicBlockInfo & UserBBI = BBInfo [ UserMBB -> getNumber ( ) ] ; if ( BBHasFallthrough ( UserMBB ) ) { unsigned Delta = <NUM_LIT> ; unsigned CPEOffset = UserBBI . postOffset ( CPELogAlign ) + Delta ; if ( isOffsetInRange ( UserOffset , CPEOffset , U ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << UserMBB -> getNumber ( ) << format ( <STR_LIT> , CPEOffset ) ) ; NewMBB = & * ++ UserMBB -> getIterator ( ) ; int UncondBr = <STR_LIT> ; BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBInfo [ UserMBB -> getNumber ( ) ] . Size += Delta ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ;

unsigned CPUIndex = CPUserIndex + <NUM_LIT> ;


<s> case <STR_LIT> : { auto ConstNode = cast < ConstantSDNode > ( Node ) ; if ( VT == XLenVT && ConstNode -> isNullValue ( ) ) { SDValue New = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( Node ) , <STR_LIT> , XLenVT ) ; ReplaceNode ( Node , New . getNode ( ) ) ; return ; } int64_t Imm = ConstNode -> getSExtValue ( ) ; if ( XLenVT == <STR_LIT> ) { ReplaceNode ( Node , selectImm ( CurDAG , SDLoc ( Node ) , Imm , XLenVT ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , XLenVT ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; ReplaceNode ( Node , CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , TFI , Imm ) ) ; return ; } case <STR_LIT> : { if ( ! Subtarget -> is64Bit ( ) ) break ; SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; uint64_t Mask ; if ( Op1 . getOpcode ( ) == <STR_LIT> && isConstantMask ( Op0 . getNode ( ) , Mask ) ) { uint64_t ShAmt = cast < ConstantSDNode > ( Op1 . getNode ( ) ) -> getZExtValue ( ) ; if ( ( Mask | maskTrailingOnes < uint64_t > ( ShAmt ) ) == <NUM_LIT> ) {

SDValue ShAmtVal = CurDAG -> getTargetConstant ( ShAmt , SDLoc ( Node ) , XLenVT ) ;


<s> if ( MSB >= Imm ) { uint64_t Width = MSB - Imm + <NUM_LIT> ; uint64_t LSB = Imm ; OpUsefulBits <<= Width ; -- OpUsefulBits ; if ( Op . getOperand ( <NUM_LIT> ) == Orig ) { Mask = ResultUsefulBits & OpUsefulBits ; Mask <<= LSB ; } if ( Op . getOperand ( <NUM_LIT> ) == Orig ) Mask |= ( ResultUsefulBits & ~ OpUsefulBits ) ; } else { uint64_t Width = MSB + <NUM_LIT> ; uint64_t LSB = UsefulBits . getBitWidth ( ) - Imm ; OpUsefulBits <<= Width ; -- OpUsefulBits ; OpUsefulBits <<= LSB ; if ( Op . getOperand ( <NUM_LIT> ) == Orig ) {


<s> Thumb2ITBlock ( ) : MachineFunctionPass ( ID ) {


<s> return __builtin_mve_vcmpeqq_n_sv8hi ( __a , __b ) ;


<s> assert ( std :: is_sorted ( MI -> begin ( ) + OpNum , MI -> end ( ) , [ & ] ( const MCOperand & LHS , const MCOperand & RHS ) { return MRI . getEncodingValue ( LHS . getReg ( ) ) < MRI . getEncodingValue ( RHS . getReg ( ) ) ; } ) ) ; } O << <STR_LIT> ; for ( unsigned i = OpNum , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {


<s> MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; assert ( MF . getSubtarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) && <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> && Offset < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) ) { MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( - Offset ) ; } else if ( Offset < <NUM_LIT> ) { MI . setDesc ( TII -> get ( getRegOpForImmOpVariant ( MI . getOpcode ( ) ) ) ) ;

unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: reportParseError ( StringRef ErrorMsg ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ;


<s> virtual void emitARM64WinCFISaveFReg ( unsigned Reg , int Offset ) {


<s> const <ISA_LIT>MachineFunctionInfo * MFI = B . getMF ( ) . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! MFI -> isEntryFunction ( ) ) { return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; } B . setInstr ( MI ) ; uint64_t Offset = ST . getTargetLowering ( ) -> getImplicitParameterOffset ( B . getMF ( ) , <ISA_LIT>TargetLowering :: FIRST_IMPLICIT ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { switch ( ( unsigned ) Fixup . getKind ( ) ) { default :


<s> assert ( MCID . hasOptionalDef ( ) && <STR_LIT> ) ; assert ( MCID . NumOperands == Inst . getNumOperands ( ) && <STR_LIT> ) ; unsigned OpNo ; for ( OpNo = <NUM_LIT> ; ! MCID . OpInfo [ OpNo ] . isOptionalDef ( ) && OpNo < MCID . NumOperands ; ++ OpNo ) ; if ( isThumbOne ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> ) return Match_RequiresFlagSetting ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) != <STR_LIT> && ! inITBlock ( ) ) return Match_RequiresITBlock ; if ( isThumbTwo ( ) && Inst . getOperand ( OpNo ) . getReg ( ) == <STR_LIT> && inITBlock ( ) ) return Match_RequiresNotITBlock ; } else if ( isThumbOne ( ) ) { if ( Opc == <STR_LIT> && ! hasV6MOps ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresThumb2 ; else if ( Opc == <STR_LIT> && ! hasV6Ops ( ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) && is<ISA_LIT>LowRegister ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Match_RequiresV6 ; } for ( unsigned I = <NUM_LIT> ; I < MCID . NumOperands ; ++ I ) if ( MCID . OpInfo [ I ] . RegClass == <STR_LIT> ) {

if ( ( Inst . getOperand ( I ) . getReg ( ) == <STR_LIT> ) && ! hasV8Ops ( ) ) return Match_RequiresV8 ;


<s> return ; } if ( TARGET_MIPS16 ) { mips_emit_move ( temp , mips_cprestore_slot ( temp , true ) ) ;

mips_emit_move ( pic_offset_table_rtx , temp ) ;


<s> <ISA_LIT>FIHolder ( int FrameIndex , int StackPointerOffset ) : FI ( FrameIndex ) , SPOffset ( StackPointerOffset ) {


<s> if ( s390_is_longrunning ( insn ) ) { if ( s390_is_fxd ( insn ) ) fxd_longrunning [ sched_state . side ] = latency ; else fpd_longrunning [ sched_state . side ] = latency ; } if ( s390_tune >= PROCESSOR_2964_Z13 ) { int units , i ; unsigned unit_mask , m = <NUM_LIT> ; unit_mask = s390_get_unit_mask ( insn , & units ) ; gcc_assert ( units <= MAX_SCHED_UNITS ) ; for ( i = <NUM_LIT> ; i < units ; i ++ , m <<= <NUM_LIT> ) if ( m & unit_mask ) last_scheduled_unit_distance [ i ] [ sched_state . side ] = <NUM_LIT> ; else if ( last_scheduled_unit_distance [ i ] [ sched_state . side ] < MAX_SCHED_MIX_DISTANCE ) last_scheduled_unit_distance [ i ] [ sched_state . side ] ++ ; } if ( ( mask & S390_SCHED_ATTR_MASK_CRACKED ) != <NUM_LIT> || ( mask & S390_SCHED_ATTR_MASK_EXPANDED ) != <NUM_LIT> || ( mask & S390_SCHED_ATTR_MASK_GROUPALONE ) != <NUM_LIT> || ( mask & S390_SCHED_ATTR_MASK_ENDGROUP ) != <NUM_LIT> ) { sched_state . group_state = <NUM_LIT> ; ends_group = true ; } else { switch ( sched_state . group_state ) { case <NUM_LIT> : sched_state . group_state ++ ; break ; case <NUM_LIT> : sched_state . group_state ++ ; if ( sched_state . group_of_two ) { sched_state . group_state = <NUM_LIT> ; ends_group = true ; } break ; case <NUM_LIT> : sched_state . group_state ++ ; ends_group = true ; break ; } } if ( verbose > <NUM_LIT> ) { unsigned int sched_mask ; sched_mask = s390_get_sched_attrmask ( insn ) ; fprintf ( file , <STR_LIT> , INSN_UID ( insn ) ) ; PRINT_SCHED_ATTR ( S390_SCHED_ATTR_MASK_CRACKED , cracked ) ; PRINT_SCHED_ATTR ( S390_SCHED_ATTR_MASK_EXPANDED , expanded ) ; PRINT_SCHED_ATTR ( S390_SCHED_ATTR_MASK_ENDGROUP , endgroup ) ; PRINT_SCHED_ATTR ( S390_SCHED_ATTR_MASK_GROUPALONE , groupalone ) ; if ( s390_tune >= PROCESSOR_2964_Z13 ) { unsigned int unit_mask , m = <NUM_LIT> ; int units , j ; unit_mask = s390_get_unit_mask ( insn , & units ) ; fprintf ( file , <STR_LIT> ) ; for ( j = <NUM_LIT> ; j < units ; j ++ , m <<= <NUM_LIT> ) if ( m & unit_mask ) fprintf ( file , <STR_LIT> , j ) ; fprintf ( file , <STR_LIT> ) ; } fprintf ( file , <STR_LIT> , sched_state . group_state ) ; if ( s390_tune >= PROCESSOR_2964_Z13 ) { int units , j ;


<s> static void CreateMCInst ( MCInst & Inst , unsigned Opc , const MCOperand & Operand0 , const MCOperand & Operand1 , const MCOperand & Operand2 = MCOperand ( ) ) { Inst . setOpcode ( Opc ) ; Inst . addOperand ( Operand0 ) ; Inst . addOperand ( Operand1 ) ;

if ( Operand2 . isValid ( ) ) Inst . addOperand ( Operand2 ) ;


<s> static void mips_emit_probe_stack_range ( HOST_WIDE_INT first , HOST_WIDE_INT size ) { if ( TARGET_MIPS16 ) sorry ( <STR_LIT> ) ; if ( first + size <= <NUM_LIT> ) { HOST_WIDE_INT i ; for ( i = PROBE_INTERVAL ; i < size ; i += PROBE_INTERVAL ) emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + i ) ) ) ; emit_stack_probe ( plus_constant ( Pmode , stack_pointer_rtx , - ( first + size ) ) ) ; } else { HOST_WIDE_INT rounded_size ; rtx r3 = MIPS_PROLOGUE_TEMP ( Pmode ) ; rtx r12 = MIPS_PROLOGUE_TEMP2 ( Pmode ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> ) { SDNode * BVN = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( BVN -> getValueType ( <NUM_LIT> ) != <STR_LIT> || BVN -> getOpcode ( ) != <STR_LIT> ) return false ; unsigned LoElt = DAG . getDataLayout ( ) . isBigEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; unsigned HiElt = <NUM_LIT> - LoElt ; ConstantSDNode * Lo0 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt ) ) ; ConstantSDNode * Hi0 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( HiElt ) ) ;

ConstantSDNode * Lo1 = dyn_cast < ConstantSDNode > ( BVN -> getOperand ( LoElt + <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveCFINegateRAState ( ) {

if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ;


<s> const <ISA_LIT>ElfTargetObjectFile & TLOFELF = static_cast < const <ISA_LIT>ElfTargetObjectFile & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFELF . getAttributesSection ( ) ) ;

OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> const uint16_t * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_O32_SaveList ;


<s> return isa < ICmpInst > ( I . getOperand ( <NUM_LIT> ) ) ? cast < ICmpInst > ( I . getOperand ( <NUM_LIT> ) ) -> isSigned ( ) : false ;


<s> void <ISA_LIT>InstPrinter :: printPostIdxRegOperand ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO1 = MI -> getOperand ( OpNum ) ; const MCOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ;

O << ( MO2 . getImm ( ) ? <STR_LIT> : <STR_LIT> ) ;