<s> if ( ! issetmem ) { srcmem = offset_address ( srcmem , copy_rtx ( tmp ) , piece_size_n ) ; srcmem = adjust_address ( srcmem , mode , <NUM_LIT> ) ; if ( ! TARGET_64BIT && <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) { destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; srcmem = adjust_address ( copy_rtx ( srcmem ) , mode , GET_MODE_SIZE ( mode ) ) ; } emit_move_insn ( destmem , srcmem ) ; } } else { rtx tmpreg [ <NUM_LIT> ] ; gcc_assert ( unroll <= <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { tmpreg [ i ] = gen_reg_rtx ( mode ) ; if ( i ) srcmem = adjust_address ( copy_rtx ( srcmem ) , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( tmpreg [ i ] , srcmem ) ; } for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( destmem , tmpreg [ i ] ) ; } } } else for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( destmem , value ) ; } tmp = expand_simple_binop ( iter_mode , PLUS , iter , piece_size , iter , true , OPTAB_LIB_WIDEN ) ; if ( tmp != iter ) emit_move_insn ( iter , tmp ) ; emit_cmp_and_jump_insns ( iter , size , LT , NULL_RTX , iter_mode , true , top_label ) ; if ( expected_size != - <NUM_LIT> ) { expected_size /= GET_MODE_SIZE ( mode ) * unroll ; if ( expected_size == <NUM_LIT> ) predict_jump ( <NUM_LIT> ) ; else if ( expected_size > REG_BR_PROB_BASE ) predict_jump ( REG_BR_PROB_BASE - <NUM_LIT> ) ; else predict_jump ( REG_BR_PROB_BASE - ( REG_BR_PROB_BASE + expected_size / <NUM_LIT> ) / expected_size ) ; } else predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; iter = ix86_zero_extend_to_Pmode ( iter ) ; tmp = expand_simple_binop ( Pmode , PLUS , destptr , iter , destptr , true , OPTAB_LIB_WIDEN ) ; if ( tmp != destptr ) emit_move_insn ( destptr , tmp ) ; if ( ! issetmem ) {

tmp = expand_simple_binop ( Pmode , PLUS , srcptr , iter , srcptr , true , OPTAB_LIB_WIDEN ) ;


return new <ISA_LIT>HazardRecognizer970 ( * DAG ) ;


<s> case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: CreateExpr ( MCSymbolRefExpr :: Create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = LowerSymbolOperand ( MO , GetJumpTableSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = LowerSymbolOperand ( MO , GetConstantPoolIndexSymbol ( MO ) ) ; break ; case MachineOperand :: MO_BlockAddress :

MCOp = LowerSymbolOperand ( MO , GetBlockAddressSymbol ( MO ) ) ;


<s> assert ( Entry -> getParent ( ) -> getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) && <STR_LIT> ) ; Entry -> addLiveIn ( * I ) ; BuildMI ( * Entry , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVR ) . addReg ( * I ) ; for ( auto * Exit : Exits ) BuildMI ( * Exit , Exit -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , * I ) . addReg ( NewVR ) ; }


<s> const GCNSubtarget & ST = TM . getSubtarget < GCNSubtarget > ( F ) ; return ST . getFlatWorkGroupSizes ( F ) ;


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; EVT WideVecVT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue WideVec = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( Subtarget . hasAVX ( ) && ! Subtarget . hasAVX2 ( ) && TLI . isTypeLegal ( WideVecVT ) && WideVecVT . getSizeInBits ( ) == <NUM_LIT> && WideVec . getOpcode ( ) == <STR_LIT> ) { auto isConcatenatedNot = [ ] ( SDValue V ) { V = peekThroughBitcasts ( V ) ; if ( ! isBitwiseNot ( V ) ) return false ; SDValue NotOp = V -> getOperand ( <NUM_LIT> ) ; return peekThroughBitcasts ( NotOp ) . getOpcode ( ) == <STR_LIT> ; } ; if ( isConcatenatedNot ( WideVec . getOperand ( <NUM_LIT> ) ) || isConcatenatedNot ( WideVec . getOperand ( <NUM_LIT> ) ) ) { SDValue Concat = split256IntArith ( WideVec , DAG ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , DAG . getBitcast ( WideVecVT , Concat ) , N -> getOperand ( <NUM_LIT> ) ) ; } } if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; SDValue InVec = N -> getOperand ( <NUM_LIT> ) ; unsigned IdxVal = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) return getZeroVector ( VT , Subtarget , DAG , SDLoc ( N ) ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) {

if ( VT . getScalarType ( ) == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ;


<s> inline bool isProgramMemoryAccess ( MemSDNode const * N ) {

auto V = N -> getMemOperand ( ) -> getValue ( ) ;


<s> crtl -> uses_pic_offset_table = <NUM_LIT> ; return nios2_large_got_address ( offset , tmp ) ; } return gen_const_mem ( Pmode , nios2_got_address ( sym , unspec ) ) ;


<s> return llvm :: make_unique < <ISA_LIT>MachObjectWriter > ( CPUType , CPUSubtype , IsILP32 ) ;


addPass ( create<ISA_LIT>FlagsCopyLoweringPass ( ) ) ;


<s> if ( matchVectorShuffleAsEXTRQ ( VT , V1 , V2 , Mask , BitLen , BitIdx , Zeroable ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 , DAG . getConstant ( BitLen , DL , <STR_LIT> ) , DAG . getConstant ( BitIdx , DL , <STR_LIT> ) ) ; if ( matchVectorShuffleAsINSERTQ ( VT , V1 , V2 , Mask , BitLen , BitIdx ) ) return DAG . getNode ( <STR_LIT> , DL , VT , V1 ? V1 : DAG . getUNDEF ( VT ) , V2 ? V2 : DAG . getUNDEF ( VT ) , DAG . getConstant ( BitLen , DL , <STR_LIT> ) , DAG . getConstant ( BitIdx , DL , <STR_LIT> ) ) ; return SDValue ( ) ;


<s> case AMDGPU :: S_LSHL_B64 : return AMDGPU :: V_LSHL_B64 ; case AMDGPU :: S_LSHR_B32 : return AMDGPU :: V_LSHR_B32_e32 ; case AMDGPU :: S_LSHR_B64 : return AMDGPU :: V_LSHR_B64 ; case AMDGPU :: S_SEXT_I32_I8 : return AMDGPU :: V_BFE_I32 ; case AMDGPU :: S_SEXT_I32_I16 : return AMDGPU :: V_BFE_I32 ; case AMDGPU :: S_BFE_U32 : return AMDGPU :: V_BFE_U32 ; case AMDGPU :: S_BFE_I32 : return AMDGPU :: V_BFE_I32 ; case AMDGPU :: S_NOT_B32 : return AMDGPU :: V_NOT_B32_e32 ; case AMDGPU :: S_CMP_EQ_I32 : return AMDGPU :: V_CMP_EQ_I32_e32 ; case AMDGPU :: S_CMP_LG_I32 : return AMDGPU :: V_CMP_NE_I32_e32 ; case AMDGPU :: S_CMP_GT_I32 : return AMDGPU :: V_CMP_GT_I32_e32 ; case AMDGPU :: S_CMP_GE_I32 : return AMDGPU :: V_CMP_GE_I32_e32 ; case AMDGPU :: S_CMP_LT_I32 : return AMDGPU :: V_CMP_LT_I32_e32 ; case AMDGPU :: S_CMP_LE_I32 : return AMDGPU :: V_CMP_LE_I32_e32 ; case AMDGPU :: S_LOAD_DWORD_IMM : case AMDGPU :: S_LOAD_DWORD_SGPR : return AMDGPU :: BUFFER_LOAD_DWORD_ADDR64 ; case AMDGPU :: S_LOAD_DWORDX2_IMM : case AMDGPU :: S_LOAD_DWORDX2_SGPR : return AMDGPU :: BUFFER_LOAD_DWORDX2_ADDR64 ;


<s> virtual unsigned getNumFixupKinds ( ) const LLVM_OVERRIDE {


<s> bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) Modified |= RescheduleLoadStoreInstrs ( MFI ) ; return Modified ;


<s> <ISA_LIT>AsmBackend ( const Target & T , const Triple & TT , uint8_t OSABI , StringRef CPU ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( OSABI ) , CPU ( CPU ) , MCII ( T . createMCInstrInfo ( ) ) , RelaxTarget ( new MCInst * ) , Extender ( nullptr ) {


<s> if ( reg_renumber ) { regno = reg_renumber [ regno ] ; if ( regno == REG_Z ) { return true ; } } return false ; } if ( regno < FIRST_PSEUDO_REGISTER && ( regno == REG_X || regno == REG_Y || regno == REG_Z || regno == ARG_POINTER_REGNUM ) ) { ok = true ; } else if ( reg_renumber ) { regno = reg_renumber [ regno ] ; if ( regno == REG_X || regno == REG_Y || regno == REG_Z || regno == ARG_POINTER_REGNUM ) { ok = true ; } }

if ( avr_strict_X && PLUS == outer_code && regno == REG_X ) {


<s> if ( isNEONByteReplicate ( <NUM_LIT> ) ) return false ; if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; unsigned Value = CE -> getValue ( ) ; return <STR_LIT> ( Value ) ;


<s> if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar ) { int64_t Imm ; uint32_t Reloc ; if ( GVar -> hasAttribute ( <STR_LIT> ) || GVar -> hasAttribute ( <STR_LIT> ) ) { Imm = PatchImms [ GVar ] . first ; Reloc = PatchImms [ GVar ] . second ; } else { return false ; } if ( Reloc == <STR_LIT> || Reloc == <STR_LIT> ) OutMI . setOpcode ( <STR_LIT> ) ; else OutMI . setOpcode ( <STR_LIT> ) ; OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; OutMI . addOperand ( MCOperand :: createImm ( Imm ) ) ; return true ; } } } else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GVal = MO . getGlobal ( ) ; auto * GVar = dyn_cast < GlobalVariable > ( GVal ) ; if ( GVar && GVar -> hasAttribute ( <STR_LIT> ) ) { uint32_t Imm = PatchImms [ GVar ] . first ; OutMI . setOpcode ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) OutMI . addOperand ( MCOperand :: createImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ;

else OutMI . addOperand ( MCOperand :: createReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ;


<s> WL . append ( MBB -> succ_begin ( ) , MBB -> succ_end ( ) ) ; for ( auto * Succ : Succs ) MBB -> removeSuccessor ( Succ ) ; MBB -> eraseFromParent ( ) ;


<s> unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildCopy ( PhysReg , ExtReg ) ;

MIB . addUse ( PhysReg , RegState :: Implicit ) ;


<s> return isLegalToVectorizeMemChain ( ChainSizeInBytes , Alignment , AddrSpace ) ;


<s> switch ( Opcode ) { default : { if ( MI . getParent ( ) && MI . getParent ( ) -> getParent ( ) ) { const auto MF = MI . getMF ( ) ; const auto & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF -> getTarget ( ) ) ; const MCRegisterInfo & MRI = * TM . getMCRegisterInfo ( ) ; const MCSubtargetInfo & STI = * TM . getMCSubtargetInfo ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( isCompressibleInst ( MI , & ST , MRI , STI ) ) return <NUM_LIT> ; } return get ( Opcode ) . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case <STR_LIT> :


<s> <ISA_LIT>SplitConst32AndConst64 ( ) : MachineFunctionPass ( ID ) {


<s> * no_add_attrs = true ; } else if ( ( is_attribute_p ( <STR_LIT> , name ) && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * type ) ) ) || ( ( is_attribute_p ( <STR_LIT> , name ) && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( * type ) ) ) ) ) { warning ( OPT_Wattributes , <STR_LIT> , name ) ; * no_add_attrs = true ; } return NULL_TREE ;


<s> errs ( ) << <STR_LIT> << this << '\n' ; errs ( ) << <STR_LIT> ; if ( Base . getNode ( ) != <NUM_LIT> ) Base . getNode ( ) -> dump ( ) ; else errs ( ) << <STR_LIT> ; if ( hasIndexField ( ) ) { errs ( ) << <STR_LIT> ; if ( Index . getNode ( ) != <NUM_LIT> ) Index . getNode ( ) -> dump ( ) ; else errs ( ) << <STR_LIT> ; } errs ( ) << <STR_LIT> << Disp ;

if ( IncludesDynAlloc ) errs ( ) << <STR_LIT> ;


<s> MVT VecVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; unsigned NumElemsPerChunk = vecWidth / VecVT . getScalarSizeInBits ( ) ;


<s> ArgRegs . reserve ( I -> getNumOperands ( ) ) ; ArgVTs . reserve ( I -> getNumOperands ( ) ) ; ArgFlags . reserve ( I -> getNumOperands ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; ++ i ) { Value * Op = I -> getOperand ( i ) ; unsigned Arg = getRegForValue ( Op ) ; if ( Arg == <NUM_LIT> ) return false ; const Type * ArgTy = Op -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) ) return false ; <STR_LIT> Flags ; unsigned OriginalAlignment = TD . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( Op ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes ) ) return false ; MachineInstrBuilder MIB ; unsigned CallOpc = <ISA_LIT>SelectCallOp ( NULL ) ; if ( isThumb ) MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ; else MIB = AddDefaultPred ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( CallOpc ) ) . addExternalSymbol ( TLI . getLibcallName ( Call ) ) ) ; for ( unsigned i = <NUM_LIT> , e = RegArgs . size ( ) ; i != e ; ++ i ) MIB . addReg ( RegArgs [ i ] ) ; SmallVector < unsigned , <NUM_LIT> > UsedRegs ; if ( ! FinishCall ( RetVT , UsedRegs , I , CC , NumBytes ) ) return false ; static_cast < MachineInstr * > ( MIB ) -> setPhysRegsDeadExcept ( UsedRegs , TRI ) ;


<s> SDNode * SignRot = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( VecOp0 , <NUM_LIT> ) , SignRotAmt ) ; SDNode * UpperHalfSign = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( SignRot , <NUM_LIT> ) ) ; SDNode * UpperHalfSignMask = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperHalfSign , <NUM_LIT> ) ) ; SDNode * UpperLowerMask = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDNode * UpperLowerSelect = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperHalfSignMask , <NUM_LIT> ) , SDValue ( VecOp0 , <NUM_LIT> ) , SDValue ( UpperLowerMask , <NUM_LIT> ) ) ; SDNode * Shift = <NUM_LIT> ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( ShiftAmt ) ) { unsigned bytes = unsigned ( CN -> getZExtValue ( ) ) >> <NUM_LIT> ; unsigned bits = unsigned ( CN -> getZExtValue ( ) ) & <NUM_LIT> ; if ( bytes > <NUM_LIT> ) { bytes = <NUM_LIT> - bytes ; Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperLowerSelect , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ; } if ( bits > <NUM_LIT> ) { bits = <NUM_LIT> - bits ; Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( ( Shift != <NUM_LIT> ? Shift : UpperLowerSelect ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bits , ShiftAmtVT ) ) ; } } else { SDNode * NegShift = CurDAG -> getMachineNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( UpperLowerSelect , <NUM_LIT> ) , SDValue ( NegShift , <NUM_LIT> ) ) ; Shift = CurDAG -> getMachineNode ( <STR_LIT> , dl , VecVT , SDValue ( Shift , <NUM_LIT> ) , SDValue ( NegShift , <NUM_LIT> ) ) ; } return CurDAG -> getMachineNode ( <STR_LIT> , dl , OpVT , SDValue ( Shift , <NUM_LIT> ) ) ;


<s> extern __inline long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __TM_is_illegal ( void * const tdb_ptr ) { struct __htm_tdb * tdb = ( struct __htm_tdb * ) tdb_ptr ; return ( tdb -> format == <NUM_LIT> && ( tdb -> abort_code == <NUM_LIT> || tdb -> abort_code == <NUM_LIT> ) ) ;


<s> } if ( ArchV . empty ( ) ) { if ( CPU . empty ( ) ) CPU = DefaultArch ; return CPU ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Opc = MI -> getOpcode ( ) ; unsigned DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && <STR_LIT> ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned TmpR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , It , DL , HII . get ( <STR_LIT> ) , TmpR ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ;

unsigned TfrOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> void emitInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI ) override { EmitMappingSymbol ( <STR_LIT> ) ;

MCELFStreamer :: emitInstruction ( Inst , STI ) ;


<s> MachineInstr * SecondLastInst = NULL ; do { if ( & * I != LastInst && ! I -> isBundle ( ) && isUnpredicatedTerminator ( I ) ) { if ( ! SecondLastInst ) SecondLastInst = I ; else return true ; } if ( I == MBB . instr_begin ( ) ) break ; -- I ; } while ( I ) ; int LastOpcode = LastInst -> getOpcode ( ) ; bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNot = PredOpcodeHasNot ( LastOpcode ) ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( LastOpcodeHasNot ) { Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } return true ; } int SecLastOpcode = SecondLastInst -> getOpcode ( ) ; bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( SecLastOpcode ) ; bool SecLastOpcodeHasNot = PredOpcodeHasNot ( SecLastOpcode ) ; if ( SecLastOpcodeHasJMP_c && ( LastOpcode == <STR_LIT> ) ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( SecLastOpcodeHasNot ) Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; I = LastInst ; if ( AllowModify ) I -> eraseFromParent ( ) ; return false ; } if ( SecLastOpcode == <STR_LIT> && LastOpcode == <STR_LIT> ) { TBB = SecondLastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( SecondLastInst -> getOperand ( <NUM_LIT> ) ) ; FBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Op = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Op ) ;


<s> auto It = llvm :: find_if ( Range , P ) ; assert ( It != std :: end ( Range ) ) ;


<s> assert ( ( Opc >= <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; KnownZero = KnownOne = APInt ( Mask . getBitWidth ( ) , <NUM_LIT> ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) break ; case <STR_LIT> :

KnownZero |= APInt :: getHighBitsSet ( Mask . getBitWidth ( ) , Mask . getBitWidth ( ) - <NUM_LIT> ) ;


<s> MachineBasicBlock * BrBB = FuncInfo . MBB ; MachineBasicBlock * TBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; MachineBasicBlock * FBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; if ( const CmpInst * CI = dyn_cast < CmpInst > ( BI -> getCondition ( ) ) ) { if ( isValueAvailable ( CI ) ) { Optional < <STR_LIT> > Opt<ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( ! Opt<ISA_LIT>Pred ) return false ; <STR_LIT> <ISA_LIT>Pred = Opt<ISA_LIT>Pred . getValue ( ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; <ISA_LIT>Pred = <STR_LIT> ( <ISA_LIT>Pred ) ; } Register CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg , <ISA_LIT>Pred ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( Subtarget -> hasSPE ( ) ? <STR_LIT> : <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; finishCondBranch ( BI -> getParent ( ) , TBB , FBB ) ; return true ; } } else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) { uint64_t Imm = CI -> getZExtValue ( ) ; MachineBasicBlock * Target = ( Imm == <NUM_LIT> ) ? FBB : TBB ; fastEmitBranch ( Target , DbgLoc ) ;


<s> return map . lookup ( name ) - <NUM_LIT> ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) {


if ( IsNarrowSequence < <NUM_LIT> > ( MulOp0 , LHS ) && IsNarrowSequence < <NUM_LIT> > ( MulOp1 , RHS ) ) {


<s> bool loongarch_can_use_return_insn ( void ) {

return reload_completed && cfun -> machine -> frame . total_size == <NUM_LIT> ;


<s> if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ; return false ;


<s> const char * getPassName ( ) const override {


<s> if ( Kind . isMergeableConst16 ( ) ) return MergeableConst16Section ;

assert ( ( Kind . isReadOnly ( ) || Kind . isReadOnlyWithRel ( ) ) && <STR_LIT> ) ;


<s> void insert ( unsigned BBNum , BasicBlockInfo BBI ) {

BBInfo . insert ( BBInfo . begin ( ) + BBNum , BBI ) ;


<s> if ( ( OpVT == <STR_LIT> && Op0VT == <STR_LIT> ) || Op0VT == <STR_LIT> ) { RTLIB :: Libcall LC = ( Op . getOpcode ( ) == <STR_LIT> ) ? RTLIB :: getSINTTOFP ( Op0VT , OpVT ) : RTLIB :: getUINTTOFP ( Op0VT , OpVT ) ; assert ( LC != RTLIB :: UNKNOWN_LIBCALL && <STR_LIT> ) ; SDValue Dummy ; return ExpandLibCall ( LC , Op , DAG , false , Dummy , TLI ) ; }


<s> if ( Strs . first . trim ( ) . getAsInteger ( <NUM_LIT> , Ints . first ) ) { Ctx . emitError ( <STR_LIT> + Name ) ; return Default ; } if ( Strs . second . trim ( ) . getAsInteger ( <NUM_LIT> , Ints . second ) ) { if ( ! OnlyFirstRequired || Strs . second . trim ( ) . size ( ) ) { Ctx . emitError ( <STR_LIT> + Name ) ; return Default ; }


<s> next_feature_string = strchr ( curr_feature_string , ',' ) ; if ( next_feature_string ) * next_feature_string ++ = '\0' ; if ( * curr_feature_string == '^' ) { curr_feature_string ++ ; clear = true ; } for ( i = <NUM_LIT> ; i < X86_TUNE_LAST ; i ++ ) { if ( ! strcmp ( curr_feature_string , ix86_tune_feature_names [ i ] ) ) {


<s> gcc_assert ( mode == CCFPmode || ( code != ORDERED && code != UNORDERED && code != UNEQ && code != LTGT && code != UNGT && code != UNLT && code != UNGE && code != UNLE ) ) ;

gcc_assert ( mode != CCFPmode || flag_finite_math_only || ( code != LE && code != GE && code != UNEQ && code != LTGT && code != UNGT && code != UNLT ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { unsigned Opcode = MI . getOpcode ( ) ; switch ( Opcode ) { default : { const MCInstrDesc & Desc = get ( Opcode ) ; return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : case TargetOpcode :: INLINEASM_BR : {

const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ;


<s> return Kind == Memory && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) && getMemIndexReg ( ) >= <STR_LIT> && getMemIndexReg ( ) <= <STR_LIT> ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , TargetMachine & TM , unsigned SyntaxVariant , const MCAsmInfo & MAI ) {

if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( TM , MAI ) ;


<s> return ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) || CONSTANT_ADDRESS_P ( x ) || flag_pic ) ;


<s> bool MultiplePreds = MBB && ( MBB -> pred_size ( ) > <NUM_LIT> ) ; if ( ! MultiplePreds ) return false ; unsigned BlkSize = MBB -> size ( ) ;

return ( ( BlkSize > BlockSizeThreshold ) && ( BlkSize * ( MBB -> pred_size ( ) - <NUM_LIT> ) > CloneInstrThreshold ) ) ;


<s> for ( unsigned I = <NUM_LIT> ; I < NumOps ; ++ I ) Ops . push_back ( Op . getOperand ( I ) ) ; if ( Op -> getNumValues ( ) == <NUM_LIT> ) return DAG . getNode ( Opcode , SDLoc ( Op ) , <STR_LIT> , Ops ) ; assert ( Op -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; SDVTList RawVTs = DAG . getVTList ( Op -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; return DAG . getNode ( Opcode , SDLoc ( Op ) , RawVTs , Ops ) ;


<s> AllUsesAcceptSReg = false ; SDNode * User = * U ; if ( User -> isMachineOpcode ( ) ) { unsigned Opc = User -> getMachineOpcode ( ) ; MCInstrDesc Desc = <ISA_LIT>I -> get ( Opc ) ; if ( Desc . isCommutable ( ) ) { unsigned OpIdx = Desc . getNumDefs ( ) + U . getOperandNo ( ) ; unsigned CommuteIdx1 = TargetInstrInfo :: CommuteAnyOperandIndex ; if ( <ISA_LIT>I -> findCommutedOpIndices ( Desc , OpIdx , CommuteIdx1 ) ) { unsigned CommutedOpNo = CommuteIdx1 - Desc . getNumDefs ( ) ; const TargetRegisterClass * CommutedRC = getOperandRegClass ( * U , CommutedOpNo ) ; if ( CommutedRC == & <STR_LIT> ) AllUsesAcceptSReg = true ; } }


<s> MCAsmInfo * MAI ; if ( TheTriple . isOSDarwin ( ) || TheTriple . isOSBinFormatMachO ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( TheTriple ) ; else if ( TheTriple . isWindowsMSVCEnvironment ( ) ) MAI = new <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) ; else if ( TheTriple . isOSWindows ( ) ) MAI = new <ISA_LIT>COFFMCAsmInfoGNU ( ) ;

else MAI = new <ISA_LIT>ELFMCAsmInfo ( TheTriple ) ;


<s> <ISA_LIT>PacketizerList :: <ISA_LIT>PacketizerList ( MachineFunction & MF , MachineLoopInfo & MLI , MachineDominatorTree & MDT ) : VLIWPacketizerList ( MF , MLI , MDT , true ) {


<s> if ( ! Dis -> tryAddingSymbolicOperand ( Inst , imm * <NUM_LIT> , Addr , true , <NUM_LIT> , <NUM_LIT> ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ;


<s> if ( ! isStoreInst ( MCInstD ) ) return false ; switch ( getSlotOpCode ( MCInstD ) ) { case ST_L : return true ; }


<s> return ( int32x4_t ) __builtin_neon_vqabsv4si ( __a ) ;


<s> } else for ( unsigned int ti = <NUM_LIT> ; group . types [ ti ] [ <NUM_LIT> ] != NUM_TYPE_SUFFIXES ; ++ ti ) { type_suffix_pair types = { explicit_type0 ? group . types [ ti ] [ <NUM_LIT> ] : NUM_TYPE_SUFFIXES , explicit_type1 ? group . types [ ti ] [ <NUM_LIT> ] : NUM_TYPE_SUFFIXES } ; function_instance instance ( group . base_name , * group . base , * group . shape , mode , types , group . preds [ pi ] ) ;

add_overloaded_function ( instance , group . required_extensions ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override {


<s> } } if ( ArgFlags . isSplitEnd ( ) && PendingLocs . size ( ) <= <NUM_LIT> ) { assert ( PendingLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; CCValAssign VA = PendingLocs [ <NUM_LIT> ] ; <STR_LIT> AF = PendingArgFlags [ <NUM_LIT> ] ; PendingLocs . clear ( ) ; PendingArgFlags . clear ( ) ; return CC_<ISA_LIT>Assign2XLen ( XLen , State , VA , AF , ValNo , ValVT , LocVT , ArgFlags ) ; } unsigned Reg = State . AllocateReg ( ArgGPRs ) ; unsigned StackOffset = Reg ? <NUM_LIT> : State . AllocateStack ( XLen / <NUM_LIT> , XLen / <NUM_LIT> ) ; if ( ! PendingLocs . empty ( ) ) { assert ( ArgFlags . isSplitEnd ( ) && <STR_LIT> ) ; assert ( PendingLocs . size ( ) > <NUM_LIT> && <STR_LIT> ) ; for ( auto & It : PendingLocs ) { if ( Reg ) It . convertToReg ( Reg ) ; else It . convertToMem ( StackOffset ) ; State . addLoc ( It ) ; }


<s> rtx brtmp ; int reverse_regs , invert ; switch ( test_code ) { case EQ : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_seq_sf ; break ; case NE : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_seq_sf ; break ; case LE : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_sle_sf ; break ; case GT : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_slt_sf ; break ; case LT : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_slt_sf ; break ; case GE : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_sle_sf ; break ; case UNEQ : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_suneq_sf ; break ; case LTGT : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_suneq_sf ; break ; case UNLE : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_sunle_sf ; break ; case UNGT : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_sunlt_sf ; break ; case UNLT : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_sunlt_sf ; break ; case UNGE : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_sunle_sf ; break ; case UNORDERED : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_sunordered_sf ; break ; case ORDERED : reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = gen_sunordered_sf ; break ; default : fatal_insn ( <STR_LIT> , gen_rtx_fmt_ee ( test_code , VOIDmode , cmp0 , cmp1 ) ) ; reverse_regs = <NUM_LIT> ; invert = <NUM_LIT> ; gen_fn = <NUM_LIT> ;


<s> static unsigned getLogicalBitOpcode ( unsigned Opc , bool Is64 ) { switch ( Opc ) { case <STR_LIT> : return Is64 ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return Is64 ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> :


<s> case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) break ; return MCOperand :: CreateReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate :

return MCOperand :: CreateImm ( MO . getImm ( ) + offset ) ;


<s> int OperandToKeep = LII . SetCR ? <NUM_LIT> : <NUM_LIT> ; for ( int i = MI . getNumOperands ( ) - <NUM_LIT> ; i > OperandToKeep ; i -- ) MI . RemoveOperand ( i ) ; if ( LII . SetCR ) { MI . setDesc ( get ( LII . Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( LII . Imm ) . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ; return ; }

else MI . setDesc ( get ( LII . Is64Bit ? <STR_LIT> : <STR_LIT> ) ) ;


<s> Init<ISA_LIT>65816MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> void printT2AddrModeImm8OffsetOperand ( const MCInst * MI , unsigned OpNum ) {


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ;


<s> disablePass ( & TailDuplicateID ) ; disablePass ( & StackMapLivenessID ) ; disablePass ( & LiveDebugValuesID ) ; disablePass ( & PostRAMachineSinkingID ) ; disablePass ( & PostRASchedulerID ) ; disablePass ( & FuncletLayoutID ) ; disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; addPass ( createNVVMReflectPass ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ImageOptimizerPass ( ) ) ;


<s> bool <ISA_LIT>NaClRewritePass :: ApplyStackSFI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) { const bool UseZeroBasedSandbox = FlagUseZeroBasedSandbox ; TraceLog ( <STR_LIT> , MBB , MBBI ) ; assert ( Is64Bit ) ; MachineInstr & MI = * MBBI ; if ( ! IsStackChange ( MI ) ) return false ; if ( IsPushPop ( MI ) ) return false ; if ( MI . getDesc ( ) . isCall ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( DestReg == <STR_LIT> || DestReg == <STR_LIT> ) ; unsigned NewOpc = <NUM_LIT> ; switch ( Opc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } if ( NewOpc ) { BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( UseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; Opc = <STR_LIT> ; } if ( Opc == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { return true ; } assert ( Opc != <STR_LIT> && <STR_LIT> ) ; if ( Opc == <STR_LIT> ) { unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BaseReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Scale = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;

unsigned IndexReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> const <ISA_LIT>MCExpr * expr = <ISA_LIT>MCExpr :: create ( Kind , MCSym , OutContext ) ; return MCOperand :: createExpr ( expr ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldConvertPhiType ( Type * From , Type * To ) const {

if ( ! Subtarget . is64Bit ( ) ) return false ;


<s> if ( ( ValVT == <STR_LIT> && ( ValLoc == <STR_LIT> || ValLoc == <STR_LIT> ) ) || ( ValVT == <STR_LIT> && ( ValLoc == <STR_LIT> || ValLoc == <STR_LIT> ) ) ) { EVT TempValLoc = ValVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue ValToCopy = DAG . getBitcast ( TempValLoc , ValArg ) ; if ( ValLoc == <STR_LIT> ) ValToCopy = DAG . getNode ( <STR_LIT> , Dl , ValLoc , ValToCopy ) ; return ValToCopy ; } else if ( ( ValVT == <STR_LIT> && ValLoc == <STR_LIT> ) || ( ValVT == <STR_LIT> && ValLoc == <STR_LIT> ) ) {

return DAG . getBitcast ( ValLoc , ValArg ) ;


<s> bool function_checker :: require_immediate_lane_index ( unsigned int rel_argno , unsigned int group_size ) { unsigned int argno = m_base_arg + rel_argno ; if ( ! argument_exists_p ( argno ) ) return true ; machine_mode mode = TYPE_MODE ( type_argument_type ( m_fntype , argno ) ) ;


<s> int mmix_function_value_regno_p ( int regno ) { return regno == MMIX_RETURN_VALUE_REGNUM ;


<s> case <STR_LIT> : if ( ! matchWrapper ( N , AM ) ) return false ; break ;


<s> <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>FL = STI -> getFrameLowering ( ) ;

bool Modified = ExpandPseudosWhichAffectControlFlow ( MF ) ;


<s> <ISA_LIT>MCExpr :: VariantKind VK ; int64_t Imm ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; return IsConstantImm && isUInt < <NUM_LIT> > ( Imm ) && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> return ( __m64 ) __builtin_arm_wqmulm ( ( __v4hi ) a , ( __v4hi ) b ) ;


<s> const MachineOperand & MO = MI -> getOperand ( opNum ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : if ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) ) O << TM . getRegisterInfo ( ) -> get ( MO . getReg ( ) ) . AsmName ; else assert ( <NUM_LIT> && <STR_LIT> ) ; return ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << Mang -> getValueName ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : O << MO . getSymbolName ( ) ; break ;

case MachineOperand :: MO_MachineBasicBlock :


<s> assemble_external ( decl ) ; SET_SYMBOL_REF_DECL ( x , NULL ) ; } } if ( size == UNITS_PER_WORD && aligned_p && function_label_operand ( x , VOIDmode ) ) { fputs ( size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> , asm_out_file ) ; if ( ! TARGET_FAST_INDIRECT_CALLS ) fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputc ( '\n' , asm_out_file ) ; result = true ; }

else result = default_assemble_integer ( x , size , aligned_p ) ;


<s> bool isPostIdxImm8 ( ) const { if ( Kind != k_Immediate ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Val = CE -> getValue ( ) ;

return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || ( Val == INT32_MIN ) ;


<s> unsigned <ISA_LIT>FastISel :: emitSubs_rr ( MVT RetVT , unsigned LHSReg , bool LHSIsKill , unsigned RHSReg , bool RHSIsKill , bool WantResult ) { return emitAddSub_rr ( false , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , true , WantResult ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>TOCRegDepsPass ( ) {


<s> return false ; } if ( Start -> getOpcode ( ) == <STR_LIT> && ( BBUtils -> getOffsetOf ( Start ) > BBUtils -> getOffsetOf ( Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) || ! BBUtils -> isBBInRange ( Start , Start -> getOperand ( <NUM_LIT> ) . getMBB ( ) , <NUM_LIT> ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } return true ; } ; auto FindStartInsertionPoint = [ ] ( MachineInstr * Start , MachineInstr * Dec , MachineBasicBlock :: iterator & InsertPt , MachineBasicBlock * & InsertBB , ReachingDefAnalysis & RDA , InstSet & ToRemove ) { if ( isDo ( Start ) || Start -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; }

if ( ! RDA . isSafeToDefRegAt ( Start , MCRegister :: from ( <STR_LIT> ) ) ) return false ;


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) {


<s> arc_jli_section * sec = arc_jli_sections , * new_section ; tree decl = SYMBOL_REF_DECL ( pat ) ; if ( ! pat ) return ; if ( decl ) { attrs = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( <STR_LIT> , attrs ) ) return ; } name = XSTR ( pat , <NUM_LIT> ) ; while ( sec != NULL ) { if ( strcmp ( name , sec -> name ) == <NUM_LIT> ) return ; sec = sec -> next ; } new_section = ( arc_jli_section * ) xmalloc ( sizeof ( arc_jli_section ) ) ;


<s> if ( ( COp0 && ! COp0 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) || ( COp1 && ! COp1 -> getAPIntValue ( ) . isSignedIntN ( <NUM_LIT> ) ) ) { unsigned ExtendOp = is<ISA_LIT>CCSigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ; if ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( DAG . ComputeMaxSignificantBits ( Op0 . getOperand ( <NUM_LIT> ) ) <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } else if ( Op1 . getOpcode ( ) == <STR_LIT> ) { if ( DAG . ComputeMaxSignificantBits ( Op1 . getOperand ( <NUM_LIT> ) ) <= <NUM_LIT> ) ExtendOp = <STR_LIT> ; } } CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( ExtendOp , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( ExtendOp , dl , CmpVT , Op1 ) ; } } if ( CmpVT == <STR_LIT> && isa < ConstantSDNode > ( Op1 ) && ! is<ISA_LIT>CCSigned ( <ISA_LIT>CC ) && Op0 . hasOneUse ( ) && cast < ConstantSDNode > ( Op1 ) -> getAPIntValue ( ) . getActiveBits ( ) <= <NUM_LIT> && DAG . MaskedValueIsZero ( Op0 , APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ) ) { CmpVT = <STR_LIT> ; Op0 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op0 ) ; Op1 = DAG . getNode ( <STR_LIT> , dl , CmpVT , Op1 ) ; }

if ( Op0 . getOpcode ( ) == <STR_LIT> && isNullConstant ( Op0 . getOperand ( <NUM_LIT> ) ) && Op0 . hasOneUse ( ) && ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) ) {


<s> bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( MF . getFunction ( ) . getCallingConv ( ) == CallingConv :: GHC ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue NewSP = Op . getOperand ( <NUM_LIT> ) ; SDValue Backchain ; SDLoc DL ( Op ) ; if ( StoreBackchain ) { SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> ) ;

Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , getBackchainAddress ( OldSP , DAG ) , MachinePointerInfo ( ) ) ;


<s> Value * I8Ptr = Builder . CreateBitCast ( LD -> getOperand ( <NUM_LIT> ) , Builder . getInt8PtrTy ( ) ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Bitcast -> replaceAllUsesWith ( NewInst ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> switch ( mode ) { case E_QImode : gen = gen_arm_store_exclusiveqi ; break ; case E_HImode : gen = gen_arm_store_exclusivehi ; break ; case E_SImode : gen = gen_arm_store_exclusivesi ; break ; case E_DImode : gen = gen_arm_store_exclusivedi ; break ; default : gcc_unreachable ( ) ; } } emit_insn ( gen ( bval , rval , mem ) ) ;


<s> } if ( cr16_data_model ) { if ( strcmp ( cr16_data_model , <STR_LIT> ) == <NUM_LIT> ) data_model = DM_DEFAULT ; else if ( strcmp ( cr16_data_model , <STR_LIT> ) == <NUM_LIT> ) data_model = DM_NEAR ; else if ( strcmp ( cr16_data_model , <STR_LIT> ) == <NUM_LIT> ) { if ( TARGET_CR16CP ) data_model = DM_FAR ; else error ( <STR_LIT> ) ; } else error ( <STR_LIT> , cr16_data_model ) ; }


<s> assert ( Size >= <NUM_LIT> ) ; RegInterval Result ; Result . first = TRI -> getEncodingValue ( Reg . getReg ( ) ) ; Result . second = Result . first + Size / <NUM_LIT> ;


<s> Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == <NUM_LIT> ) return ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

if ( Offset < <NUM_LIT> ) BuildMI ( MBB , std :: next ( II ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ;


<s> } else { const MCSymbol * BaseSym = AFI -> getJumpTableEntryPCRelSymbol ( JTI ) ; const MCExpr * Base = MCSymbolRefExpr :: create ( BaseSym , OutContext ) ; Value = MCBinaryExpr :: createSub ( Value , Base , OutContext ) ; Value = MCBinaryExpr :: createLShr ( Value , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; } OutStreamer -> EmitValue ( Value , Size ) ;


<s> if ( FP_REGNUM_P ( REGNO ( dst ) ) ) return REG_P ( src ) && ! FP_REGNUM_P ( REGNO ( src ) ) ; return true ;


<s> else if ( MEM_P ( x ) ) { rtx addr = XEXP ( x , <NUM_LIT> ) ; if ( code == 'm' ) { if ( ! CONSTANT_P ( addr ) ) fatal_insn ( <STR_LIT> , addr ) ; if ( text_segment_operand ( addr , VOIDmode ) ) if ( warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ) { output_addr_const ( stderr , addr ) ; fprintf ( stderr , <STR_LIT> ) ; } output_addr_const ( file , addr ) ; } else if ( code == 'i' ) { avr_print_operand ( file , addr , 'i' ) ; } else if ( code == 'o' ) { if ( GET_CODE ( addr ) != PLUS ) fatal_insn ( <STR_LIT> , addr ) ; avr_print_operand ( file , XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; } else if ( code == 'b' ) { if ( GET_CODE ( addr ) != PLUS ) fatal_insn ( <STR_LIT> , addr ) ; avr_print_operand_address ( file , VOIDmode , XEXP ( addr , <NUM_LIT> ) ) ; } else if ( code == 'p' || code == 'r' ) { if ( GET_CODE ( addr ) != POST_INC && GET_CODE ( addr ) != PRE_DEC ) fatal_insn ( <STR_LIT> , addr ) ; if ( code == 'p' ) avr_print_operand_address ( file , VOIDmode , XEXP ( addr , <NUM_LIT> ) ) ; else avr_print_operand ( file , XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; } else if ( GET_CODE ( addr ) == PLUS ) { avr_print_operand_address ( file , VOIDmode , XEXP ( addr , <NUM_LIT> ) ) ; if ( REGNO ( XEXP ( addr , <NUM_LIT> ) ) == REG_X ) fatal_insn ( <STR_LIT> , addr ) ; fputc ( '+' , file ) ; avr_print_operand ( file , XEXP ( addr , <NUM_LIT> ) , code ) ; } else avr_print_operand_address ( file , VOIDmode , addr ) ; } else if ( code == 'i' ) { if ( SYMBOL_REF_P ( x ) && ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_IO ) ) avr_print_operand_address ( file , VOIDmode , plus_constant ( HImode , x , - avr_arch -> sfr_offset ) ) ; else fatal_insn ( <STR_LIT> , x ) ; } else if ( code == 'x' ) { if ( text_segment_operand ( x , VOIDmode ) == <NUM_LIT> ) if ( warning ( <NUM_LIT> , <STR_LIT> <STR_LIT> ) ) { output_addr_const ( stderr , x ) ; fprintf ( stderr , <STR_LIT> ) ; } output_addr_const ( file , x ) ; } else if ( CONST_FIXED_P ( x ) ) { HOST_WIDE_INT ival = INTVAL ( avr_to_int_mode ( x ) ) ; if ( code != <NUM_LIT> ) output_operand_lossage ( <STR_LIT> , code ) ; fprintf ( file , HOST_WIDE_INT_PRINT_DEC , ival ) ; } else if ( CONST_DOUBLE_P ( x ) ) {


<s> SDValue Result = AddCombineToVPADDL ( N , N0 , N1 , DCI , Subtarget ) ; if ( Result . getNode ( ) ) return Result ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getNode ( ) -> hasOneUse ( ) ) { SDValue Result = combineSelectAndUse ( N , N0 , N1 , DCI ) ; if ( Result . getNode ( ) ) return Result ; }


<s> if ( AM . hasSymbolicDisplacement ( ) ) return true ; SDValue N0 = N . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; } else { AM . BlockAddr = cast < BlockAddressSDNode > ( N0 ) -> getBlockAddress ( ) ; }


<s> break ; default : V = ( V << ( <NUM_LIT> - Bits ) ) >> ( <NUM_LIT> - Bits ) ; break ; } Result = APInt ( Width , V , true ) ; return true ; } if ( Bits < BW ) Result = A1 . trunc ( Bits ) . sext ( Width ) ;


<s> const char * <ISA_LIT>TargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ;


<s> if ( GET_CODE ( base ) == SYMBOL_REF || GET_CODE ( base ) == LABEL_REF ) { if ( aarch64_classify_symbol ( base , offset ) != SYMBOL_FORCE_TO_MEM ) return true ; else return mode != ptr_mode ;


<s> for ( auto Pos = InsertPos , E = MBB -> begin ( ) ; Pos != E ; -- Pos ) assert ( ! AfterSet . count ( & * std :: prev ( Pos ) ) ) ; break ; } -- InsertPos ;


<s> EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned FrameReg = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; return FrameAddr ;


<s> unsigned StallCycles ; unsigned UsedBanks ; std :: tie ( StallCycles , UsedBanks ) = analyzeInst ( MI , Reg , SubReg , Bank ) ; TotalStallCycles += StallCycles ; if ( Collect ) collectCandidates ( MI , UsedBanks , StallCycles ) ;


<s> <STR_LIT> ; } else { Opcode = CI . IsX2 ? <STR_LIT> : <STR_LIT> ; } const TargetRegisterClass * SuperRC = CI . IsX2 ? & <STR_LIT> : & <STR_LIT> ; unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; unsigned MergedOffset = std :: min ( CI . Offset0 , CI . Offset1 ) ; auto MIB = BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) , DestReg ) ; if ( CI . InstClass == BUFFER_LOAD_OFFEN ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ; MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( MergedOffset ) . addImm ( CI . GLC0 ) . addImm ( CI . SLC0 ) . addImm ( <NUM_LIT> ) . cloneMergedMemRefs ( { & * CI . I , & * CI . Paired } ) ;


<s> <ISA_LIT>MCELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter ) : MCELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) , MCII ( create<ISA_LIT>MCInstrInfo ( ) ) {


<s> uint64_t <ISA_LIT>InstrInfo :: getScratchRsrcWords23 ( ) const { uint64_t Rsrc23 = getDefaultRsrcDataFormat ( ) | <STR_LIT> | <NUM_LIT> ; if ( ST . getGeneration ( ) <= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { uint64_t EltSizeValue = Log2_32 ( ST . getMaxPrivateElementSize ( ) ) - <NUM_LIT> ; Rsrc23 |= EltSizeValue << <STR_LIT> ;


<s> return <STR_LIT> ( <STR_LIT> , Name ) ;


<s> for ( unsigned I = <NUM_LIT> ; I < Mask . size ( ) ; ++ I ) if ( Mask [ I ] != Mask [ I - <NUM_LIT> ] + <NUM_LIT> ) return false ; return true ;


<s> Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; } if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) , Result ) ; } if ( isGlobalStubReference ( OpFlags ) ) Result = DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , Result , PseudoSourceValue :: getGOT ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; if ( Offset != <NUM_LIT> ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result , DAG . getConstant ( Offset , getPointerTy ( ) ) ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: agc > A ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> OS << <STR_LIT> << Reg << <STR_LIT> << Offset << <STR_LIT> ;


<s> SDLoc Dl ( N ) ; unsigned Opcode = N -> getOpcode ( ) ; bool IsSelected = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : IsSelected = selectAddCarry ( N ) ; break ; case <STR_LIT> : IsSelected = selectSubCarry ( N ) ; break ; case <STR_LIT> : { Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ; ReplaceNode ( N , CurDAG -> getRegister ( GP , N -> getValueType ( <NUM_LIT> ) ) . getNode ( ) ) ; IsSelected = true ; break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , <STR_LIT> ) ; ReplaceNode ( N , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? <STR_LIT> : <STR_LIT> , Dl , <STR_LIT> , TFI , Imm ) ) ; IsSelected = true ; break ; } case <STR_LIT> : case <STR_LIT> : IsSelected = selectInlineAsm ( N ) ;


<s> if ( ! reg_classes_intersect_p ( to , GENERAL_REGS ) ) from = to ; if ( from == FLOAT_REGS || from == ALTIVEC_REGS ) return ( rs6000_memory_move_cost ( mode , from , <NUM_LIT> ) + rs6000_memory_move_cost ( mode , GENERAL_REGS , <NUM_LIT> ) ) ; else if ( from == CR_REGS ) return <NUM_LIT> ; else return <NUM_LIT> * hard_regno_nregs [ <NUM_LIT> ] [ mode ] ; }

else if ( reg_classes_intersect_p ( to , from ) ) return mode == TFmode ? <NUM_LIT> : <NUM_LIT> ;


<s> return __builtin_mve_vrev32q_sv8hi ( __a ) ;


<s> break ; } case k_Register : OS << <STR_LIT> << getReg ( ) << <STR_LIT> ; break ; case k_ShifterImmediate : OS << <STR_LIT> << ( ShifterImm . isASR ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << ShifterImm . Imm << <STR_LIT> ; break ; case k_ShiftedRegister : OS << <STR_LIT> << RegShiftedReg . SrcReg << <STR_LIT> << <STR_LIT> ( RegShiftedReg . ShiftTy ) << <STR_LIT> << RegShiftedReg . ShiftReg << <STR_LIT> ; break ; case k_ShiftedImmediate : OS << <STR_LIT> << RegShiftedImm . SrcReg << <STR_LIT> << <STR_LIT> ( RegShiftedImm . ShiftTy ) << <STR_LIT> << RegShiftedImm . ShiftImm << <STR_LIT> ; break ; case k_RotateImmediate : OS << <STR_LIT> << <STR_LIT> << ( RotImm . Imm * <NUM_LIT> ) << <STR_LIT> ; break ; case k_ModifiedImmediate : OS << <STR_LIT> << ModImm . Bits << <STR_LIT> << ModImm . Rot << <STR_LIT> ; break ; case k_ConstantPoolImmediate : OS << <STR_LIT> << * getConstantPoolImm ( ) ; break ; case k_BitfieldDescriptor : OS << <STR_LIT> << <STR_LIT> << Bitfield . LSB << <STR_LIT> << Bitfield . Width << <STR_LIT> ; break ; case k_RegisterList : case k_DPRRegisterList : case k_SPRRegisterList : { OS << <STR_LIT> ; const SmallVectorImpl < unsigned > & RegList = getRegList ( ) ; for ( SmallVectorImpl < unsigned > :: const_iterator I = RegList . begin ( ) , E = RegList . end ( ) ; I != E ; ) { OS << * I ; if ( ++ I < E ) OS << <STR_LIT> ; } OS << <STR_LIT> ; break ;


<s> unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

BuildMI ( * MI -> getParent ( ) , MI , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( LiveMaskReg ) ;


<s> int getInstrLatency ( const InstrItineraryData * ItinData , SDNode * Node ) const override {


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> if ( offset < - <NUM_LIT> || offset + <NUM_LIT> * UNITS_PER_WORD > <NUM_LIT> ) { base = emit_adjust_base_to_offset ( base , offset ) ; offset = <NUM_LIT> ;


<s> unsigned <ISA_LIT>AsmParser :: validateTargetOperandClass ( MCParsedAsmOperand * AsmOp , unsigned Kind ) { <ISA_LIT>Operand * Op = static_cast < <ISA_LIT>Operand * > ( AsmOp ) ; if ( Kind == MCK__35_0 && Op -> isImm ( ) ) { const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op -> getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ; if ( CE -> getValue ( ) == <NUM_LIT> ) return Match_Success ;


<s> return <STR_LIT> ; case BRIG_TYPE_F64 : return <STR_LIT> ; case BRIG_TYPE_U8 : return <STR_LIT> ; case BRIG_TYPE_S8 : return <STR_LIT> ; case BRIG_TYPE_U16 : return <STR_LIT> ; case BRIG_TYPE_S16 : return <STR_LIT> ; default :


<s> unsigned OrderingVal = Ordering -> getZExtValue ( ) ; if ( OrderingVal > static_cast < unsigned > ( AtomicOrdering :: SequentiallyConsistent ) ) return false ; Info . PtrVal = Inst -> getArgOperand ( <NUM_LIT> ) ; Info . Ordering = static_cast < AtomicOrdering > ( OrderingVal ) ;


<s> tree parent = DECL_CONTEXT ( field ) ; tree prev = NULL_TREE ; tree cur ; for ( cur = TYPE_FIELDS ( parent ) ; cur && cur != field ; cur = DECL_CHAIN ( cur ) ) { if ( TREE_CODE ( cur ) != FIELD_DECL ) continue ; prev = cur ; } gcc_assert ( cur ) ; if ( prev && ! DECL_PACKED ( field ) && ! integer_zerop ( DECL_SIZE ( field ) ) && DECL_BIT_FIELD_TYPE ( field ) != DECL_BIT_FIELD_TYPE ( prev ) ) { int prev_align = TYPE_ALIGN ( TREE_TYPE ( prev ) ) ; int cur_align = TYPE_ALIGN ( TREE_TYPE ( field ) ) ; computed = ( prev_align > cur_align ) ? prev_align : cur_align ; } } return computed ;


<s> MCInst TmpInst ; MCInstLowering . lower ( MI , TmpInst ) ; EmitToStreamer ( * OutStreamer , TmpInst ) ; if ( STI . dumpCode ( ) ) { DisasmLines . resize ( DisasmLines . size ( ) + <NUM_LIT> ) ; std :: string & DisasmLine = DisasmLines . back ( ) ; raw_string_ostream DisasmStream ( DisasmLine ) ; <ISA_LIT>InstPrinter InstPrinter ( * TM . getMCAsmInfo ( ) , * STI . getInstrInfo ( ) , * STI . getRegisterInfo ( ) ) ; InstPrinter . printInst ( & TmpInst , DisasmStream , StringRef ( ) , STI ) ; SmallVector < MCFixup , <NUM_LIT> > Fixups ; SmallVector < char , <NUM_LIT> > CodeBytes ; raw_svector_ostream CodeStream ( CodeBytes ) ; auto & ObjStreamer = static_cast < MCObjectStreamer & > ( * OutStreamer ) ; MCCodeEmitter & InstEmitter = ObjStreamer . getAssembler ( ) . getEmitter ( ) ; InstEmitter . encodeInstruction ( TmpInst , CodeStream , Fixups , MF -> getSubtarget < MCSubtargetInfo > ( ) ) ; HexLines . resize ( HexLines . size ( ) + <NUM_LIT> ) ; std :: string & HexLine = HexLines . back ( ) ; raw_string_ostream HexStream ( HexLine ) ; for ( size_t i = <NUM_LIT> ; i < CodeBytes . size ( ) ; i += <NUM_LIT> ) {

unsigned int CodeDWord = * ( unsigned int * ) & CodeBytes [ i ] ;


<s> unsigned <ISA_LIT>FastISel :: TargetMaterializeConstant ( const Constant * C ) { EVT CEVT = TLI . getValueType ( C -> getType ( ) , true ) ; if ( ! CEVT . isSimple ( ) ) return <NUM_LIT> ;


<s> static bool isNullConstantOrUndef ( SDValue V ) {


<s> if ( current_function_saves_lr ( ) ) { operands [ <NUM_LIT> ] = regno_reg_rtx [ LINK_REGNUM ] ; spilled = false ; } else if ( ! df_regs_ever_live_p ( long_branch_regnum ) ) { operands [ <NUM_LIT> ] = regno_reg_rtx [ long_branch_regnum ] ; spilled = false ; } else { operands [ <NUM_LIT> ] = regno_reg_rtx [ long_branch_regnum ] ; spilled = true ; gcc_assert ( current_function_has_lr_slot ( ) ) ; } if ( spilled ) { if ( final_sequence ) { rtx_insn * delay = NEXT_INSN ( insn ) ; gcc_assert ( delay ) ; final_scan_insn ( delay , asm_out_file , optimize , <NUM_LIT> , NULL ) ; PATTERN ( delay ) = gen_blockage ( ) ; INSN_CODE ( delay ) = - <NUM_LIT> ; } if ( current_function_saves_fp ( ) ) output_asm_insn ( <STR_LIT> , operands ) ; else output_asm_insn ( <STR_LIT> , operands ) ;


<s> output_btfext_header ( ) ; output_btfext_core_sections ( ) ;


<s> if ( Subtarget -> getGeneration ( ) != <ISA_LIT>Subtarget :: SEA_ISLANDS ) return false ; bool Imm ; if ( ! SelectSMRDOffset ( Addr , Offset , Imm ) ) return false ; return ! Imm && isa < ConstantSDNode > ( Offset ) ;


<s> SDValue <ISA_LIT>TargetLowering :: combineBSWAP ( SDNode * N , DAGCombinerInfo & DCI ) const { SelectionDAG & DAG = DCI . DAG ; if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) && N -> getOperand ( <NUM_LIT> ) . hasOneUse ( ) && ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> || N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) && ! cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> isVolatile ( ) ) { SDValue Load = N -> getOperand ( <NUM_LIT> ) ; LoadSDNode * LD = cast < LoadSDNode > ( Load ) ; SDValue Ops [ ] = { LD -> getChain ( ) , LD -> getBasePtr ( ) , DAG . getValueType ( N -> getValueType ( <NUM_LIT> ) ) } ; SDValue BSLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , SDLoc ( N ) , DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , <STR_LIT> ) , Ops , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SDValue ResVal = BSLoad ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ResVal = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , BSLoad ) ; DCI . CombineTo ( N , ResVal ) ;

DCI . CombineTo ( Load . getNode ( ) , ResVal , BSLoad . getValue ( <NUM_LIT> ) ) ;


<s> if ( bytes > <NUM_LIT> ) { Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( VecOp0 , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bytes , ShiftAmtVT ) ) ; } if ( bits > <NUM_LIT> ) { Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( ( Shift != <NUM_LIT> ? Shift : VecOp0 ) , <NUM_LIT> ) , CurDAG -> getTargetConstant ( bits , ShiftAmtVT ) ) ; } } else { SDNode * Bytes = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; SDNode * Bits = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , ShiftAmt , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; Bytes = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , SDValue ( Bytes , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; Bits = CurDAG -> getTargetNode ( <STR_LIT> , dl , ShiftAmtVT , SDValue ( Bits , <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , ShiftAmtVT ) ) ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( VecOp0 , <NUM_LIT> ) , SDValue ( Bytes , <NUM_LIT> ) ) ; Shift = CurDAG -> getTargetNode ( <STR_LIT> , dl , VecVT , SDValue ( Shift , <NUM_LIT> ) , SDValue ( Bits , <NUM_LIT> ) ) ; } return CurDAG -> getTargetNode ( <STR_LIT> , dl , OpVT , SDValue ( Shift , <NUM_LIT> ) ) ;


<s> const BitTracker :: BitValue & BV = RC [ i ] ; if ( BV . is ( <NUM_LIT> ) ) V |= B ; else if ( ! BV . is ( <NUM_LIT> ) ) return false ; B <<= <NUM_LIT> ; }

if ( W == <NUM_LIT> ) return isInt < <NUM_LIT> > ( V ) ;


<s> const <ISA_LIT>FunctionArgInfo & <ISA_LIT>ArgumentUsageInfo :: lookupFuncArgInfo ( const Function & F ) const {


<s> if ( Val < MinLog || Val > MaxLog ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> << Val ) ) ;


<s> static DecodeStatus DecodeGPRnospRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) {

DecodeStatus S = MCDisassembler :: Success ;


<s> MachineBasicBlock :: iterator BundleStart = BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( ClearMask >> <NUM_LIT> ) ;

BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( I -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> unsigned getCalleeSavedFrameSize ( ) const { return CalleeSavedFrameSize ;


<s> void triplicateInstructionsTZDC ( MachineFunction & MF ) { for ( MachineFunction :: iterator MBB = MF . begin ( ) , MBE = MF . end ( ) ; MBB != MBE ; ++ MBB ) { for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( ! ( I -> isBranch ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) && ( I -> getOpcode ( ) != <STR_LIT> ) && ( I -> getOpcode ( ) != <STR_LIT> ) ) { MachineInstr * slaveinst1 = MF . CloneMachineInstr ( & * I ) ; MachineInstr * slaveinst2 = MF . CloneMachineInstr ( & * I ) ; slaveinst1 -> setFlags ( <NUM_LIT> ) ; slaveinst2 -> setFlags ( <NUM_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < I -> getNumOperands ( ) ; opcount ++ ) { if ( I -> getOperand ( opcount ) . isReg ( ) ) { slaveinst1 -> getOperand ( opcount ) . setReg ( getSlaveReg1 ( I -> getOperand ( opcount ) . getReg ( ) ) ) ; slaveinst2 -> getOperand ( opcount ) . setReg ( getSlaveReg2 ( I -> getOperand ( opcount ) . getReg ( ) ) ) ; } else if ( I -> getOperand ( opcount ) . isImm ( ) && ( I -> mayStore ( ) || I -> mayLoad ( ) ) ) { slaveinst1 -> getOperand ( opcount ) . setImm ( I -> getOperand ( opcount ) . getImm ( ) - TZDC_OFFSET ) ; slaveinst2 -> getOperand ( opcount ) . setImm ( I -> getOperand ( opcount ) . getImm ( ) - <NUM_LIT> * TZDC_OFFSET ) ; } } MBB -> insert ( I , slaveinst1 ) ; MBB -> insert ( I , slaveinst2 ) ; } }


<s> static <ISA_LIT>Operand * createAccessReg ( unsigned Num , SMLoc StartLoc , SMLoc EndLoc ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( KindAccessReg , StartLoc , EndLoc ) ; Op -> AccessReg = Num ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = SPRDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ;


<s> default : return NULL_TREE ; } gcc_assert ( suffix != NULL ) ; bname = IDENTIFIER_POINTER ( DECL_NAME ( bdecl ) ) ; if ( ! bname ) return NULL_TREE ; strcpy ( name , bname + strlen ( <STR_LIT> ) ) ; strcat ( name , suffix ) ; if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , NULL ) ; else if ( n_args == <NUM_LIT> ) fntype = build_function_type_list ( type_out , type_in , type_in , NULL ) ; else gcc_unreachable ( ) ; new_fndecl = build_decl ( BUILTINS_LOCATION , FUNCTION_DECL , get_identifier ( name ) , fntype ) ; TREE_PUBLIC ( new_fndecl ) = <NUM_LIT> ; DECL_EXTERNAL ( new_fndecl ) = <NUM_LIT> ; DECL_IS_NOVOPS ( new_fndecl ) = <NUM_LIT> ; TREE_READONLY ( new_fndecl ) = <NUM_LIT> ;


static const std :: pair < unsigned , const char * > TargetFlags [ ] = {


<s> const int align = floor_log2 ( FUNCTION_BOUNDARY / BITS_PER_UNIT ) ; switch_to_section ( text_section ) ; if ( align > <NUM_LIT> ) ASM_OUTPUT_ALIGN ( asm_out_file , align ) ; ASM_OUTPUT_LABEL ( asm_out_file , name ) ; } do_cfi = dwarf2out_do_cfi_asm ( ) ; if ( do_cfi ) fprintf ( asm_out_file , <STR_LIT> ) ; if ( flag_delayed_branch ) fprintf ( asm_out_file , <STR_LIT> , reg_name , reg_name ) ; else fprintf ( asm_out_file , <STR_LIT> , reg_name , reg_name ) ; if ( do_cfi ) fprintf ( asm_out_file , <STR_LIT> ) ; } if ( NEED_INDICATE_EXEC_STACK ) file_end_indicate_exec_stack ( ) ; solaris_file_end ( ) ;


<s> case TargetOpcode :: G_FCEIL : return legalizeFceil ( MI , MRI , B ) ; case TargetOpcode :: G_FREM : return legalizeFrem ( MI , MRI , B ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C_TRUNC : return legalizeIntrinsicTrunc ( MI , MRI , B ) ; case TargetOpcode :: G_<ISA_LIT>TOFP : return legalizeITOFP ( MI , MRI , B , true ) ; case TargetOpcode :: G_UITOFP : return legalizeITOFP ( MI , MRI , B , false ) ; case TargetOpcode :: G_FPTO<ISA_LIT> : return legalizeFPTOI ( MI , MRI , B , true ) ; case TargetOpcode :: G_FPTOUI : return legalizeFPTOI ( MI , MRI , B , false ) ; case TargetOpcode :: G_FMINNUM : case TargetOpcode :: G_FMAXNUM : case TargetOpcode :: G_FMINNUM_IEEE : case TargetOpcode :: G_FMAXNUM_IEEE : return legalizeMinNumMaxNum ( Helper , MI ) ; case TargetOpcode :: G_EXTRACT_VECTOR_ELT : return legalizeExtractVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_INSERT_VECTOR_ELT : return legalizeInsertVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return legalizeShuffleVector ( MI , MRI , B ) ; case TargetOpcode :: G_F<ISA_LIT>N : case TargetOpcode :: G_FCOS : return legalizeSinCos ( MI , MRI , B ) ; case TargetOpcode :: G_GLOBAL_VALUE : return legalizeGlobalValue ( MI , MRI , B ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : return legalizeLoad ( Helper , MI ) ; case TargetOpcode :: G_FMAD : return legalizeFMad ( MI , MRI , B ) ; case TargetOpcode :: G_FDIV : return legalizeFDIV ( MI , MRI , B ) ; case TargetOpcode :: G_UDIV : case TargetOpcode :: G_UREM : case TargetOpcode :: G_UDIVREM : return legalizeUnsignedDIV_REM ( MI , MRI , B ) ; case TargetOpcode :: G_SDIV : case TargetOpcode :: G_SREM : case TargetOpcode :: G_SDIVREM : return legalizeSignedDIV_REM ( MI , MRI , B ) ; case TargetOpcode :: G_ATOMIC_CMPXCHG : return legalizeAtomicCmpXChg ( MI , MRI , B ) ;


<s> SmallSetVector < MachineBasicBlock * , <NUM_LIT> > Blocks ; for ( MachineBasicBlock & MBB : MF ) { if ( MBB . succ_size ( ) <= <NUM_LIT> ) continue ; auto TermIt = MBB . getFirstTerminator ( ) ; if ( TermIt == MBB . end ( ) || ! TermIt -> isBranch ( ) ) continue ; for ( MachineBasicBlock * SuccMBB : MBB . successors ( ) ) if ( ! SuccMBB -> isEHPad ( ) ) Blocks . insert ( SuccMBB ) ; } for ( MachineBasicBlock * MBB : Blocks ) { auto InsertPt = MBB -> SkipPHIsAndLabels ( MBB -> begin ( ) ) ; BuildMI ( * MBB , InsertPt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; ++ NumInstsInserted ; ++ NumLFENCEsInserted ;


<s> case DCmode : mode = DFmode ; break ; case TCmode : mode = TFmode ; break ; default : break ; } rs6000_darwin64_record_arg_flush ( cum , bitpos , rvec , k ) ; rvec [ ( * k ) ++ ] = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , cum -> fregno ++ ) , GEN_INT ( bitpos / BITS_PER_UNIT ) ) ; if ( mode == TFmode ) cum -> fregno ++ ; } else if ( cum -> named && USE_ALTIVEC_FOR_ARG_P ( cum , mode , ftype , <NUM_LIT> ) ) {


<s> if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( <ISA_LIT>InstrInfo :: isMAI ( * MI ) && checkMAIHazards ( MI ) > <NUM_LIT> ) return NoopHazard ;

if ( MI -> mayLoadOrStore ( ) && checkMAILdStHazards ( MI ) > <NUM_LIT> ) return NoopHazard ;


<s> Register InReg = PHI -> getOperand ( PHIOp ) . getReg ( ) ; MachineBasicBlock * PBB = PHI -> getOperand ( PHIOp + <NUM_LIT> ) . getMBB ( ) ; const BlockData & PBBInfo = BlockInfo [ PBB -> getNumber ( ) ] ; if ( PBBInfo . Exit . isUnknown ( ) || ! PBBInfo . Exit . hasSameVTYPE ( Require ) ) return true ; MachineInstr * DefMI = MRI -> getVRegDef ( InReg ) ;

if ( ! DefMI || ( DefMI -> getOpcode ( ) != <STR_LIT> && DefMI -> getOpcode ( ) != <STR_LIT> ) ) return true ;


<s> FI -> setMustSaveLR ( MustSaveLR ( MF , LR ) ) ; MF . getRegInfo ( ) . setPhysRegUnused ( LR ) ; int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool Is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool IsELF32_ABI = Subtarget . isELF32_ABI ( ) ; bool IsMachoABI = Subtarget . isMachoABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && ( NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ) && IsELF32_ABI ) { int FPOffset = <ISA_LIT>FrameInfo :: getFramePointerSaveOffset ( Is<ISA_LIT>64 , IsMachoABI ) ;

FPSI = MF . getFrameInfo ( ) -> CreateFixedObject ( Is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset ) ;


<s> Instruction * OldInstr = IPI -> first ; InsertPts [ NewPt ] = std :: move ( IPI -> second ) ;


<s> RegisterSubReg OutR ( Op0 ) ; const TargetRegisterClass * PredRC = & <STR_LIT> ; RegisterSubReg NewPR = MRI -> createVirtualRegister ( PredRC ) ; MachineInstrBuilder MIB = BuildMI ( B , MI , DL , TII -> get ( NewOpc ) , NewPR . R ) ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i ) { RegisterSubReg GPR = MI -> getOperand ( i ) ; RegisterSubReg Pred = getPredRegFor ( GPR ) ; MIB . addReg ( Pred . R , <NUM_LIT> , Pred . S ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( OutR . R ) ; Register NewOutR = MRI -> createVirtualRegister ( RC ) ; BuildMI ( B , MI , DL , TII -> get ( TargetOpcode :: COPY ) , NewOutR ) . addReg ( NewPR . R , <NUM_LIT> , NewPR . S ) ; MRI -> replaceRegWith ( OutR . R , NewOutR ) ; MI -> eraseFromParent ( ) ; if ( ! isPredReg ( NewOutR ) ) { RegisterSubReg R ( NewOutR ) ; PredGPRs . insert ( R ) ; processPredicateGPR ( R ) ; } return true ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> ExpectingFlags = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( ! ExpectingFlags ) { enum <STR_LIT> cc0 = ( enum <STR_LIT> ) N0 . getConstantOperandVal ( <NUM_LIT> ) ; enum <STR_LIT> cc1 = ( enum <STR_LIT> ) N1 . getConstantOperandVal ( <NUM_LIT> ) ; if ( cc1 == <STR_LIT> || cc1 == <STR_LIT> ) { <STR_LIT> tmp = cc0 ; cc0 = cc1 ; cc1 = tmp ; } if ( ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) || ( cc0 == <STR_LIT> && cc1 == <STR_LIT> ) ) { unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget -> hasAVX512 ( ) ) { SDValue FSetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; if ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , FSetCC ) ; return FSetCC ; } SDValue OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , CMP00 . getValueType ( ) , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; MVT IntVT = is64BitFP ? <STR_LIT> : <STR_LIT> ; if ( is64BitFP && ! Subtarget -> is64Bit ( ) ) { SDValue Vector64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesF ) ; SDValue Vector32 = DAG . getBitcast ( <STR_LIT> , Vector64 ) ; OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Vector32 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; IntVT = <STR_LIT> ; } SDValue OnesOrZeroesI = DAG . getBitcast ( IntVT , OnesOrZeroesF ) ; SDValue ANDed = DAG . getNode ( <STR_LIT> , DL , IntVT , OnesOrZeroesI , DAG . getConstant ( <NUM_LIT> , DL , IntVT ) ) ; SDValue OneBitOfTruth = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ANDed ) ;


<s> Register TmpReg = MRI -> createVirtualRegister ( PS -> RC ) ; BuildMI ( MBB , InsertPt , Loc , TII -> get ( TargetOpcode :: COPY ) , TmpReg ) . addReg ( <STR_LIT> ) ; auto ShiftI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( <STR_LIT> ) , PredStateReg ) . addReg ( TmpReg , RegState :: Kill ) . addImm ( TRI -> getRegSizeInBits ( * PS -> RC ) - <NUM_LIT> ) ; ShiftI -> addRegisterDead ( <STR_LIT> , TRI ) ;


<s> using namespace <ISA_LIT>II ; static const std :: pair < unsigned , const char * > TargetFlags [ ] = {

{ MO_ABS_HI , <STR_LIT> } , { MO_ABS_LO , <STR_LIT> } , { MO_NO_FLAG , <STR_LIT> } } ;


<s> if ( VT == <STR_LIT> ) return Subtarget -> hasDSP ( ) ? & <STR_LIT> :


<s> CopyPropagation ( const <ISA_LIT>RegisterInfo & hri , MachineRegisterInfo & mri ) : Transformation ( false ) , MRI ( mri ) {


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) , Subtarget ( STI ) , RI ( STI ) {


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) {

MCRegisterInfo * X = new MCRegisterInfo ( ) ;


<s> unsigned SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: createDefCfa ( nullptr , SP , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ;


<s> uint64_t <ISA_LIT>AsmPrinter :: getFunctionCodeSize ( const MachineFunction & MF ) const { const GCNSubtarget & STM = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = STM . getInstrInfo ( ) ; uint64_t CodeSize = <NUM_LIT> ; for ( const MachineBasicBlock & MBB : MF ) { for ( const MachineInstr & MI : MBB ) { if ( MI . isDebugInstr ( ) ) continue ; CodeSize += TII -> getInstSizeInBytes ( MI ) ; } }


<s> <ISA_LIT>ISelAddressMode ( ) : BaseType ( RegBase ) , Base_FrameIndex ( <NUM_LIT> ) , Scale ( <NUM_LIT> ) , IndexReg ( ) , Disp ( <NUM_LIT> ) , Segment ( ) , GV ( nullptr ) , CP ( nullptr ) , BlockAddr ( nullptr ) , ES ( nullptr ) , MCSym ( nullptr ) , JT ( - <NUM_LIT> ) , SymbolFlags ( <STR_LIT> ) {


<s> return true ; } } } else { if ( auto * inst = dyn_cast < Instruction > ( InVal ) ) { auto InBB = inst -> getParent ( ) ; if ( ! LI -> getLoopFor ( InBB ) ) { done = true ; } else { Loop * InLoop = LI -> getLoopFor ( InBB ) ; int InDepth = InLoop -> getLoopDepth ( ) ; if ( InDepth > Currdepth ) { } else { done = false ; } } } }


<s> gcc_assert ( is_valid != <NUM_LIT> ) ; if ( quad ) sprintf ( templ , <STR_LIT> , mnem , sign , width ) ; else sprintf ( templ , <STR_LIT> , mnem , sign , width ) ; return templ ;


<s> if ( Amount != <NUM_LIT> ) { Amount = alignSPAdjust ( Amount ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; adjustReg ( MBB , MI , DL , SPReg , SPReg , Amount , MachineInstr :: NoFlags ) ; } }


<s> case KindTy :: VectorRegister : OS << <STR_LIT> << getVecReg ( ) << '>' ; break ; case KindTy :: VTypeImm : SmallVector < char , <NUM_LIT> > VTypeBuf ; OS << <STR_LIT> << getVTypeImm ( VTypeBuf ) << '>' ;


<s> static std :: string getNodeAttributes ( const MCGNode * N , const MCallSubGraph & G ) { std :: string result ; if ( N -> isDead ( ) ) result += <STR_LIT> ; if ( N -> isInSCC ( ) ) {

if ( ! result . empty ( ) ) result += <STR_LIT> ;


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ;

Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


<s> bool <ISA_LIT>PassConfig :: addIRTranslator ( ) { addPass ( new IRTranslator ( getOptLevel ( ) ) ) ; return false ;


<s> } Carry = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Carry , DAG . getConstant ( CCValid , DL , <STR_LIT> ) , DAG . getConstant ( CCMask , DL , <STR_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; SDValue Result = DAG . getNode ( BaseOp , DL , VTs , LHS , RHS , Carry ) ; SDValue SetCC = emitSETCC ( DAG , DL , Result . getValue ( <NUM_LIT> ) , CCValid , CCMask ) ;

if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SetCC ) ;


<s> } if ( ! args ) { cur_tree = ( ( pop_target ) ? pop_target : target_option_default_node ) ; cl_target_option_restore ( & global_options , & global_options_set , TREE_TARGET_OPTION ( cur_tree ) ) ; } else { rs6000_cpu_index = rs6000_tune_index = - <NUM_LIT> ; if ( ! rs6000_inner_target_options ( args , false ) || ! rs6000_option_override_internal ( false ) || ( cur_tree = build_target_option_node ( & global_options , & global_options_set ) ) == NULL_TREE ) { if ( TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET ) fprintf ( stderr , <STR_LIT> ) ; return false ; } } target_option_current_node = cur_tree ; rs6000_activate_target_options ( target_option_current_node ) ; if ( rs6000_target_modify_macros_ptr ) { prev_opt = TREE_TARGET_OPTION ( prev_tree ) ; prev_flags = prev_opt -> x_rs6000_isa_flags ; cur_opt = TREE_TARGET_OPTION ( cur_tree ) ; cur_flags = cur_opt -> x_rs6000_isa_flags ;


<s> int LaneElts = <NUM_LIT> / VT . getScalarSizeInBits ( ) ; for ( int i = <NUM_LIT> , NumLanes = VT . getSizeInBits ( ) / <NUM_LIT> ; i < NumLanes ; ++ i ) for ( int j = <NUM_LIT> ; j < LaneElts ; ++ j ) assert ( Mask [ j ] == Mask [ i * LaneElts + j ] - ( LaneElts * i ) && <STR_LIT> ) ; Mask . resize ( LaneElts ) ; } switch ( N . getOpcode ( ) ) { case <STR_LIT> : return Mask ; case <STR_LIT> : Mask . resize ( <NUM_LIT> ) ; return Mask ; case <STR_LIT> : Mask . erase ( Mask . begin ( ) , Mask . begin ( ) + <NUM_LIT> ) ; for ( int & M : Mask ) M -= <NUM_LIT> ;


<s> aligned_p = true ; mips_sim_init ( & state , alloca ( state_size ( ) ) ) ; for ( insn = get_insns ( ) ; insn != <NUM_LIT> ; insn = next ) { unsigned int length ; next = NEXT_INSN ( insn ) ; vr4130_avoid_branch_rt_conflict ( insn ) ; if ( USEFUL_INSN_P ( insn ) ) FOR_EACH_SUBINSN ( subinsn , insn ) { mips_sim_wait_insn ( & state , subinsn ) ; if ( state . insns_left != state . issue_rate && ! CALL_P ( subinsn ) ) { if ( subinsn == SEQ_BEGIN ( insn ) && aligned_p ) { emit_insn_after ( gen_nop ( ) , last2 ) ; aligned_p = false ; }

else if ( subinsn != SEQ_BEGIN ( insn ) && ! aligned_p ) {


<s> if ( ArgFlags . isInReg ( ) && ! Subtarget . isLittle ( ) ) { if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExtUpper ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExtUpper ; else LocInfo = CCValAssign :: AExtUpper ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } unsigned Reg ; bool AllocateFloatsInIntReg = State . isVarArg ( ) || ValNo > <NUM_LIT> || State . getFirstUnallocated ( F32Regs , FloatRegsSize ) != ValNo ; unsigned OrigAlign = ArgFlags . getOrigAlign ( ) ; bool isI64 = ( ValVT == <STR_LIT> && OrigAlign == <NUM_LIT> ) ; if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; if ( isI64 && ( Reg == <STR_LIT> || Reg == <STR_LIT> ) ) Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; LocVT = <STR_LIT> ; } else if ( ValVT == <STR_LIT> && AllocateFloatsInIntReg ) {


<s> static __inline vec_double2 spu_rlqw ( vec_double2 a , int count ) {

return ( ( vec_double2 ) ( si_rotqbi ( ( qword ) ( a ) , si_from_int ( count ) ) ) ) ;


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isExpr ( ) && MO . getExpr ( ) -> getKind ( ) != MCExpr :: Constant ) { const auto * Expr = dyn_cast < MCSymbolRefExpr > ( MO . getExpr ( ) ) ; MCFixupKind Kind ; if ( Expr && Expr -> getSymbol ( ) . isExternal ( ) ) Kind = FK_Data_4 ; else Kind = FK_PCRel_4 ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ; } unsigned OpNo = <NUM_LIT> ; for ( unsigned e = MI . getNumOperands ( ) ; OpNo < e ; ++ OpNo ) { if ( & MO == & MI . getOperand ( OpNo ) ) break ;


<s> SDValue In = N -> getOperand ( <NUM_LIT> ) ; EVT InVT = In . getValueType ( ) ; EVT OutVT = N -> getValueType ( <NUM_LIT> ) ;

In = DAG . getNode ( <STR_LIT> , DL , InVT , In , DAG . getValueType ( OutVT ) ) ;


<s> static bool ft32_function_value_regno_p ( const unsigned int regno ) {


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> func_md_iterator func_md_begin ( ) {


<s> ReduceEntry ( enum ReduceType RType , struct OpCodes Op , bool ( * F ) ( MachineInstr * MI , const ReduceEntry & Entry ) , struct OpInfo OpInf , struct ImmField Imm ) : eRType ( RType ) , ReduceFunction ( F ) , Ops ( Op ) , OpInf ( OpInf ) , Imm ( Imm ) {


<s> rtx insn ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) ) { rtx pat = PATTERN ( insn ) ; int i ; if ( GET_CODE ( pat ) == PARALLEL ) for ( i = <NUM_LIT> ; i < XVECLEN ( PATTERN ( insn ) , <NUM_LIT> ) ; i ++ ) if ( GET_CODE ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , i ) ) == UNSPEC && XINT ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , i ) , <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; }


<s> unsigned int needed_reg_count ; unsigned int remaining_reg_count ; CUMULATIVE_ARGS * cum ; cum = get_cumulative_args ( ca ) ; if ( TARGET_HARD_FLOAT ) return <NUM_LIT> ;

if ( NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , mode , type ) >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS ) return <NUM_LIT> ;


<s> llvm_unreachable ( <STR_LIT> ) ; } virtual bool writeNopData ( uint64_t Count , MCObjectWriter * OW ) const LLVM_OVERRIDE ; virtual MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const LLVM_OVERRIDE { return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ; } virtual bool doesSectionRequireSymbols ( const MCSection & Section ) const LLVM_OVERRIDE { return false ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const { MCFixupKind Kind = Fixup . getKind ( ) ; unsigned Offset = Fixup . getOffset ( ) ; unsigned Size = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; assert ( Offset + Size <= DataSize && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -= <NUM_LIT> ; }


<s> return __builtin_mve_vcvtq_m_n_to_f_sv4sf ( __arm_vuninitializedq_f32 ( ) , __a , __imm6 , __p ) ;


<s> SDValue ArgValue = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { unsigned ArgSize = NextVA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( ArgSize , NextVA . getLocMemOffset ( ) , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , PseudoSourceValue :: getFixedStack ( FI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> unsigned Off = LoLoop . Dec == LoLoop . End ? <NUM_LIT> : <NUM_LIT> ; MIB . add ( End -> getOperand ( Off + <NUM_LIT> ) ) ; MIB . add ( End -> getOperand ( Off + <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; LoLoop . ToRemove . insert ( LoLoop . Dec ) ; LoLoop . ToRemove . insert ( End ) ; return & * MIB ; } ; auto RemoveDeadBranch = [ ] ( MachineInstr * I ) { MachineBasicBlock * BB = I -> getParent ( ) ; MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) {

if ( isWhileLoopStart ( * LoLoop . Start ) ) RevertWhile ( LoLoop . Start ) ;


<s> std :: pair < Register , int > <ISA_LIT>InstructionSelector :: selectFlatOffsetImpl ( MachineOperand & Root ) const { MachineInstr * MI = Root . getParent ( ) ; auto Default = std :: make_pair ( Root . getReg ( ) , <NUM_LIT> ) ; if ( ! STI . hasFlatInstOffsets ( ) ) return Default ; const MachineInstr * OpDef = MRI -> getVRegDef ( Root . getReg ( ) ) ; if ( ! OpDef || OpDef -> getOpcode ( ) != <STR_LIT> ) return Default ; Optional < int64_t > Offset = getConstantVRegVal ( OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) , * MRI ) ; if ( ! Offset . hasValue ( ) ) return Default ; unsigned AddrSpace = ( * MI -> memoperands_begin ( ) ) -> getAddrSpace ( ) ; if ( ! TII . isLegalFLATOffset ( Offset . getValue ( ) , AddrSpace , Signed ) ) return Default ; Register BasePtr = OpDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return std :: make_pair ( BasePtr , Offset . getValue ( ) ) ;


<s> } if ( TARGET_64BIT ) { enum calling_abi call_abi = cum ? cum -> call_abi : ix86_abi ; if ( call_abi == MS_ABI ) nregs = function_arg_advance_ms_64 ( cum , bytes , words ) ; else nregs = function_arg_advance_64 ( cum , mode , type , words , named ) ; } else nregs = function_arg_advance_32 ( cum , mode , type , bytes , words ) ; if ( cum -> stdarg ) cum -> force_bnd_pass = nregs ;

if ( ! nregs ) cum -> bnds_in_bt = chkp_type_bounds_count ( type ) ;


<s> Register getExceptionSelectorRegister ( const Constant * PersonalityFn ) const override { return <STR_LIT> ;


<s> if ( MI -> isInlineAsm ( ) || isTile64SoloInstruction ( MI ) ) { return true ; } else {


<s> SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Arg , StoreRet ; unsigned RetVals = TheCall -> getNumRetVals ( ) ; for ( unsigned i = <NUM_LIT> , ArgOffset = RetVals ; i < NumOps ; i ++ ) { Arg = TheCall -> getArg ( i ) ; Ops . clear ( ) ; Ops . push_back ( Chain ) ; Ops . push_back ( Arg ) ; Ops . push_back ( DataAddr_Lo ) ; Ops . push_back ( DataAddr_Hi ) ; Ops . push_back ( DAG . getConstant ( ArgOffset , <STR_LIT> ) ) ; Ops . push_back ( InFlag ) ; StoreRet = DAG . getNode ( <STR_LIT> , dl , Tys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; Chain = getChain ( StoreRet ) ; InFlag = getOutFlag ( StoreRet ) ; ArgOffset ++ ; }


<s> if ( nvptxSubtarget . getDrvInterface ( ) != <STR_LIT> ) { Type * ETy = PTy -> getElementType ( ) ; int addrSpace = PTy -> getAddressSpace ( ) ; switch ( addrSpace ) { default : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_CONST : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; case llvm :: ADDRESS_SPACE_GLOBAL : O << <STR_LIT> ; break ; } O << <STR_LIT> << ( int ) getOpenCLAlignment ( TD , ETy ) << <STR_LIT> ; } printParamName ( I , paramIndex , O ) ; continue ; } O << <STR_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) O << <STR_LIT> ; else O << getPTXFundamentalTypeStr ( Ty ) ; O << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = thePointerTy . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; if ( isABI ) O << <STR_LIT> << sz << <STR_LIT> ; else O << <STR_LIT> << sz << <STR_LIT> ; printParamName ( I , paramIndex , O ) ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; if ( isABI || isKernelFunc ) { unsigned align = PAL . getParamAlignment ( paramIndex + <NUM_LIT> ) ; if ( align == <NUM_LIT> ) align = TD -> getABITypeAlignment ( ETy ) ; unsigned sz = TD -> getTypeAllocSize ( ETy ) ; O << <STR_LIT> << align << <STR_LIT> ;


<s> if ( ! ExitB || ( ExitB -> getSinglePredecessor ( ) != LoopB ) ) return false ; IntegerType * DestTy = getPmpyType ( ) ; unsigned DestBW = DestTy -> getBitWidth ( ) ; for ( PHINode & P : ExitB -> phis ( ) ) { if ( P . getNumIncomingValues ( ) != <NUM_LIT> ) return false ; assert ( P . getIncomingBlock ( <NUM_LIT> ) == LoopB ) ; IntegerType * T = dyn_cast < IntegerType > ( P . getType ( ) ) ; if ( ! T || T -> getBitWidth ( ) > DestBW ) return false ; } for ( Instruction & In : * LoopB ) if ( ! In . isTerminator ( ) && ! isPromotableTo ( & In , DestTy ) ) return false ; std :: vector < Instruction * > LoopIns ; std :: transform ( LoopB -> begin ( ) , LoopB -> end ( ) , std :: back_inserter ( LoopIns ) , [ ] ( Instruction & In ) { return & In ; } ) ; for ( Instruction * In : LoopIns ) if ( ! In -> isTerminator ( ) ) promoteTo ( In , DestTy , LoopB ) ; Instruction * EndI = ExitB -> getFirstNonPHI ( ) ; BasicBlock :: iterator End = EndI ? EndI -> getIterator ( ) : ExitB -> end ( ) ; for ( auto I = ExitB -> begin ( ) ; I != End ; ++ I ) { PHINode * P = dyn_cast < PHINode > ( I ) ; if ( ! P ) break ; Type * Ty0 = P -> getIncomingValue ( <NUM_LIT> ) -> getType ( ) ; Type * PTy = P -> getType ( ) ; if ( PTy != Ty0 ) { assert ( Ty0 == DestTy ) ; P -> mutateType ( Ty0 ) ; Value * T = IRBuilder < > ( ExitB , End ) . CreateTrunc ( P , PTy ) ; P -> mutateType ( PTy ) ;


<s> unsigned StartIndex , OpNo0 , OpNo1 ; if ( isShlDoublePermute ( Bytes , StartIndex , OpNo0 , OpNo1 ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops [ OpNo0 ] , Ops [ OpNo1 ] , DAG . getTargetConstant ( StartIndex , DL , <STR_LIT> ) ) ; unsigned ZeroVecIdx = isZeroVector ( Ops [ <NUM_LIT> ] ) ? <NUM_LIT> : ( isZeroVector ( Ops [ <NUM_LIT> ] ) ? <NUM_LIT> : UINT_MAX ) ; if ( ZeroVecIdx != UINT_MAX ) { bool MaskFirst = true ; int ZeroIdx = - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I < <STR_LIT> ; ++ I ) { unsigned OpNo = unsigned ( Bytes [ I ] ) / <STR_LIT> ; unsigned Byte = unsigned ( Bytes [ I ] ) % <STR_LIT> ; if ( OpNo == ZeroVecIdx && I == <NUM_LIT> ) { ZeroIdx = <NUM_LIT> ; break ; } if ( OpNo != ZeroVecIdx && Byte == <NUM_LIT> ) { ZeroIdx = I + <STR_LIT> ; MaskFirst = false ; break ; } } if ( ZeroIdx != - <NUM_LIT> ) { SDValue IndexNodes [ <STR_LIT> ] ;


<s> else if ( hi_only ) { if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) && ( REG_P ( operands [ <NUM_LIT> ] ) && MEM_P ( operands [ <NUM_LIT> ] ) ) ) { emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; } operands [ <NUM_LIT> ] = fixup_mathdi_operand ( operands [ <NUM_LIT> ] , DImode ) ; operands [ <NUM_LIT> ] = fixup_mathdi_operand ( operands [ <NUM_LIT> ] , DImode ) ; operands [ <NUM_LIT> ] = fixup_mathdi_operand ( operands [ <NUM_LIT> ] , DImode ) ; if ( ! rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) emit_move_insn ( operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , DImode ) , operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , DImode ) ) ; emit_insn ( ( * gen_si_insn ) ( operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , DImode ) , operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , DImode ) , operand_subword ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> , DImode ) ) ) ; } else { if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { if ( code == PLUS ) emit_insn ( gen_ashldi3 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , const1_rtx ) ) ; else emit_move_insn ( operands [ <NUM_LIT> ] , const0_rtx ) ; return ; } operands [ <NUM_LIT> ] = fixup_mathdi_operand ( operands [ <NUM_LIT> ] , DImode ) ; if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; else operands [ <NUM_LIT> ] = fixup_mathdi_operand ( operands [ <NUM_LIT> ] , DImode ) ; if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; else operands [ <NUM_LIT> ] = fixup_mathdi_operand ( operands [ <NUM_LIT> ] , DImode ) ; if ( code == PLUS && operands [ <NUM_LIT> ] == const0_rtx ) { temp = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = temp ;


<s> { MO_COFFSTUB , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_NC , <STR_LIT> } , { MO_TLS , <STR_LIT> } , { MO_DLLIMPORT , <STR_LIT> } } ; return makeArrayRef ( TargetFlags ) ; } else { static const std :: pair < unsigned , const char * > TargetFlags [ ] = { { MO_GOTOFF , <STR_LIT> } , { MO_POT , <STR_LIT> } , { MO_SEC , <STR_LIT> } , { MO_GOT , <STR_LIT> } , { MO_NC , <STR_LIT> } , { MO_TLS , <STR_LIT> } } ;


<s> Operator * ASC = dyn_cast < Operator > ( MI -> getOperand ( Idx ) ) ; MI -> setOperand ( Idx , ASC -> getOperand ( <NUM_LIT> ) ) ; return true ;


<s> const MCFixupKindInfo & <ISA_LIT>AsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { static llvm :: DenseMap < unsigned , MCFixupKindInfo > Infos = { { <STR_LIT> :: fixup_csky_addr32 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_addr_hi16 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_addr_lo16 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_pcrel_imm16_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_pcrel_uimm16_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } } , { <STR_LIT> :: fixup_csky_pcrel_uimm8_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } } , { <STR_LIT> :: fixup_csky_pcrel_imm26_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_pcrel_imm18_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_got32 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_got_imm18_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_gotoff , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_gotpc , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_plt32 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_plt_imm18_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_pcrel_imm10_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } , { <STR_LIT> :: fixup_csky_pcrel_uimm7_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } } , { <STR_LIT> :: fixup_csky_doffset_imm18 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_doffset_imm18_scale2 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } , { <STR_LIT> :: fixup_csky_doffset_imm18_scale4 , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } } ; assert ( Infos . size ( ) == <STR_LIT> && <STR_LIT> ) ; if ( FirstTargetFixupKind <= Kind && Kind < FirstLiteralRelocationKind ) { assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind ] ; } else if ( Kind < FirstTargetFixupKind ) { return MCAsmBackend :: getFixupKindInfo ( Kind ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return & InstrInfo ;


<s> MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; EVT ArgVT = Arg . getValueType ( ) ; Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; ArgListEntry Entry ; Entry . Node = Arg ; Entry . Ty = ArgTy ;


<s> Val ( unsigned int Op , std :: vector < unsigned int > Nums ) : Op ( Op ) , Nums ( Nums ) {


<s> if ( ! MLxEntryMap . insert ( std :: make_pair ( <ISA_LIT>_MLxTable [ i ] . MLxOpc , i ) ) . second ) assert ( false && <STR_LIT> ) ;

MLxHazardOpcodes . insert ( <ISA_LIT>_MLxTable [ i ] . AddSubOpc ) ;


<s> if ( ! set -> insn ( ) -> is_phi ( ) ) return nullptr ; hash_set < set_info * > sets = get_all_sets ( set , true , false , true ) ; insn_info * first_insn = ( * sets . begin ( ) ) -> insn ( ) ;

if ( first_insn -> is_artificial ( ) ) return nullptr ;


<s> return new <ISA_LIT>LowerAMXTypeLegacyPass ( ) ;


<s> MVT OpsVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue NewN0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N0 ) ; SDValue NewN1 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , N1 ) ; if ( NumElts >= OpsVT . getVectorNumElements ( ) ) { SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; if ( Mode == MULU8 || Mode == MULS8 ) { return DAG . getNode ( ( Mode == MULU8 ) ? <STR_LIT> : <STR_LIT> , DL , VT , MulLo ) ; } else { MVT ResVT = <STR_LIT> ( <STR_LIT> , NumElts / <NUM_LIT> ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , ReducedVT , NewN0 , NewN1 ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts ; } SDValue ResLo = DAG . getVectorShuffle ( ReducedVT , DL , MulLo , MulHi , ShuffleMask ) ; ResLo = DAG . getBitcast ( ResVT , ResLo ) ; for ( unsigned i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; i ++ ) { ShuffleMask [ <NUM_LIT> * i ] = i + NumElts / <NUM_LIT> ; ShuffleMask [ <NUM_LIT> * i + <NUM_LIT> ] = i + NumElts * <NUM_LIT> / <NUM_LIT> ;


<s> case TYPE_VECSIMPLE : case TYPE_VECCOMPLEX : case TYPE_VECDIV : case TYPE_VECCMP : case TYPE_VECPERM : case TYPE_VECFLOAT :


<s> MachineFunctionProperties getRequiredProperties ( ) const override { return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: AllVRegsAllocated ) ;