<s> static SDValue PerformLOADCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { LoadSDNode * Ld = cast < LoadSDNode > ( N ) ; EVT RegVT = Ld -> getValueType ( <NUM_LIT> ) ; EVT MemVT = Ld -> getMemoryVT ( ) ; SDLoc dl ( Ld ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; <STR_LIT> Ext = Ld -> getExtensionType ( ) ; unsigned Alignment = Ld -> getAlignment ( ) ; bool IsAligned = Alignment == <NUM_LIT> || Alignment >= MemVT . getSizeInBits ( ) / <NUM_LIT> ; if ( RegVT . is256BitVector ( ) && ! Subtarget -> hasInt256 ( ) && ! DCI . isBeforeLegalizeOps ( ) && ! IsAligned && Ext == <STR_LIT> ) { unsigned NumElems = RegVT . getVectorNumElements ( ) ;

if ( NumElems < <NUM_LIT> ) return SDValue ( ) ;


<s> void setGlobalBaseReg ( unsigned Reg ) {


<s> if ( TARGET_THUMB2 && rclass == GENERAL_REGS ) return LO_REGS ; else return NO_REGS ;


<s> } ; if ( Kind < FirstTargetFixupKind ) return MCCodeEmitter :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ;


<s> if ( ScalarTy -> isPointerTy ( ) ) return true ; if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ; if ( ! ScalarTy -> isIntegerTy ( ) ) return false ; unsigned IntWidth = ScalarTy -> getIntegerBitWidth ( ) ;

return IntWidth == <NUM_LIT> || IntWidth == <NUM_LIT> || ( ( IntWidth == <NUM_LIT> || IntWidth == <NUM_LIT> ) && ST -> hasBWI ( ) ) ;


<s> static tree add_attribute ( const char * name , tree attrs ) { return tree_cons ( get_identifier ( name ) , NULL_TREE , attrs ) ;


<s> static int arm_sched_reorder ( FILE * file , int verbose , rtx_insn * * ready , int * n_readyp , int clock ) { switch ( arm_tune ) { case cortexa7 : cortexa7_sched_reorder ( file , verbose , ready , n_readyp , clock ) ; break ; default : break ;


<s> MachineInstr & MI = * I ; if ( MI . getOpcode ( ) == <STR_LIT> ) { } else if ( MI . getOpcode ( ) == <STR_LIT> ) { } else { llvm_unreachable ( <STR_LIT> ) ;


<s> return VectorList . Count == <NUM_LIT> && VectorList . LaneIndex <= <NUM_LIT> ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > B ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > C ( getThe<ISA_LIT>64LETarget ( ) ) ;

PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ;


<s> CallInst * R = B . CreateCall ( Callee , { Arg1 , Arg2 } , Name ) ;

if ( Function * F = dyn_cast < Function > ( Callee ) ) R -> setCallingConv ( F -> getCallingConv ( ) ) ;


<s> return ( __m512i ) __builtin_ia32_psllqi512_mask ( ( __v8di ) __A , __B , ( __v8di ) _mm512_undefined_si512 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <STR_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;


<s> return __aarch64_vdupq_laneq_s64 ( __a , __b ) ;


return isMemDisp12 ( BDMem , GR64Reg ) ;


<s> MachineInstr * MI = T2JumpTables [ i ] ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned NumOps = TID . getNumOperands ( ) ; unsigned JTOpIdx = NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; int JTNumber = MI -> getParent ( ) -> getNumber ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & , LLVMContext & , EVT VT ) const {


<s> static unsigned getLoadStoreMaskRegOpcode ( const TargetRegisterClass * RC , bool load ) { switch ( RC -> getSize ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : return load ? <STR_LIT> : <STR_LIT> ;


<s> unsigned KnownSize = VT . getSizeInBits ( ) . getKnownMinValue ( ) ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) KnownSize *= <NUM_LIT> ; switch ( KnownSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : return <STR_LIT> :: LMUL_F8 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_F4 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_F2 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_1 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_2 ; case <NUM_LIT> : return <STR_LIT> :: LMUL_4 ; case <NUM_LIT> :


<s> if ( ! ( IsFreelyInvertable ( N0 ) || IsFreelyInvertable ( N1 ) ) ) return SDValue ( ) ; SDValue NewN0 = DCI . DAG . getLogicalNOT ( DL , N0 , VT ) ; SDValue NewN1 = DCI . DAG . getLogicalNOT ( DL , N1 , VT ) ; SDValue And = DCI . DAG . getNode ( <STR_LIT> , DL , VT , NewN0 , NewN1 ) ; return DCI . DAG . getLogicalNOT ( DL , And , VT ) ;


<s> return isTransOnly ( MI -> getOpcode ( ) ) ;


<s> } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } else if ( ( MulAmt % <NUM_LIT> ) == <NUM_LIT> ) { MulAmt1 = <NUM_LIT> ; MulAmt2 = MulAmt / <NUM_LIT> ; } SDLoc DL ( N ) ; SDValue NewMul ; if ( MulAmt2 && ( isPowerOf2_64 ( MulAmt2 ) || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> || MulAmt2 == <NUM_LIT> ) ) { if ( isPowerOf2_64 ( MulAmt2 ) && ! ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) ) std :: swap ( MulAmt1 , MulAmt2 ) ; if ( isPowerOf2_64 ( MulAmt1 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Log2_64 ( MulAmt1 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( MulAmt1 , DL , VT ) ) ; if ( isPowerOf2_64 ( MulAmt2 ) ) NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( Log2_64 ( MulAmt2 ) , DL , <STR_LIT> ) ) ; else NewMul = DAG . getNode ( <STR_LIT> , DL , VT , NewMul , DAG . getConstant ( MulAmt2 , DL , VT ) ) ; } else if ( ! Subtarget . slowLEA ( ) ) NewMul = combineMulSpecial ( MulAmt , N , DAG , VT , DL ) ; if ( ! NewMul ) {

assert ( MulAmt != <NUM_LIT> && MulAmt != ( VT == <STR_LIT> ? UINT64_MAX : UINT32_MAX ) && <STR_LIT> <STR_LIT> ) ;


<s> void DecodeMOVSHDUPMask ( MVT VT , SmallVectorImpl < int > & ShuffleMask ) { unsigned NumElts = VT . getVectorNumElements ( ) ; for ( int i = <NUM_LIT> , e = NumElts / <NUM_LIT> ; i < e ; ++ i ) { ShuffleMask . push_back ( <NUM_LIT> * i + <NUM_LIT> ) ; ShuffleMask . push_back ( <NUM_LIT> * i + <NUM_LIT> ) ; }


<s> return MRI . getRegClass ( Register ) -> getID ( ) == <STR_LIT> ;


<s> unsigned NumElts = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDNode * Elt = N -> getOperand ( i ) . getNode ( ) ; if ( <STR_LIT> ( Elt ) && ! cast < LoadSDNode > ( Elt ) -> isVolatile ( ) ) return true ; }


<s> bool isMem ( ) const override { assert ( false ) ;


<s> call_insn = emit_call_insn ( call_insn ) ; use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , gen_rtx_REG ( Pmode , REG_B3 ) ) ; } else { if ( retval == NULL_RTX ) call_insn = emit_call_insn ( call_insn ) ; else call_insn = emit_call_insn ( gen_rtx_SET ( GET_MODE ( retval ) , retval , call_insn ) ) ; }

if ( flag_pic ) use_reg ( & CALL_INSN_FUNCTION_USAGE ( call_insn ) , pic_offset_table_rtx ) ;


<s> else if ( insn_op -> mode == V1SImode && GET_MODE ( op [ arg_count ] ) == SImode ) op [ arg_count ] = gen_lowpart ( V1SImode , op [ arg_count ] ) ; if ( ! ( * insn_data [ icode ] . operand [ idx ] . predicate ) ( op [ arg_count ] , insn_op -> mode ) ) op [ arg_count ] = copy_to_mode_reg ( insn_op -> mode , op [ arg_count ] ) ;


<s> return ( uint64x1_t ) { vcvtpd_u64_f64 ( __a [ <NUM_LIT> ] ) } ;


<s> static VariantKind getAddressFrag ( VariantKind Kind ) {

return static_cast < VariantKind > ( Kind & VK_AddressFragBits ) ;


<s> if ( auto Off = MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( Off , Ctx ) , Ctx ) ;

return MCOperand :: createExpr ( Expr ) ;


<s> unsigned Value , SH = <NUM_LIT> ; TargetMask = ~ TargetMask ; InsertMask = ~ InsertMask ; if ( Op0Opc == <STR_LIT> && Op1Opc == <STR_LIT> ) { if ( Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { if ( Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } } else if ( Op0Opc == <STR_LIT> || Op0Opc == <STR_LIT> ) { if ( Op1Opc == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { std :: swap ( Op0 , Op1 ) ; std :: swap ( Op0Opc , Op1Opc ) ; std :: swap ( TargetMask , InsertMask ) ; } } unsigned MB , ME ; if ( InsertMask && isRunOfOnes ( InsertMask , MB , ME ) ) { SDValue Tmp1 , Tmp2 ; if ( ( Op1Opc == <STR_LIT> || Op1Opc == <STR_LIT> ) && isInt32Immediate ( Op1 . getOperand ( <NUM_LIT> ) , Value ) ) { Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SH = ( Op1Opc == <STR_LIT> ) ? Value : <NUM_LIT> - Value ;


<s> if ( ! LCREVT . isSimple ( ) ) return <NUM_LIT> ; GlobalValue * GV = new GlobalVariable ( M , Type :: getInt32Ty ( * Context ) , false , GlobalValue :: ExternalLinkage , nullptr , Name ) ;

assert ( GV -> getType ( ) == GVTy && <STR_LIT> ) ;


<s> MCOperand <ISA_LIT>MCInstLower :: LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const { assert ( ! MO . getTargetFlags ( ) && <STR_LIT> ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ; if ( auto Off = MO . getOffset ( ) ) { Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( Off , Ctx ) , Ctx ) ;


<s> BitTracker :: RegisterRef RS = MI -> getOperand ( <NUM_LIT> ) ; unsigned F , W ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( ! BT . has ( RS . Reg ) || ! HBS :: getSubregMask ( RS , F , W , MRI ) ) return false ; MachineBasicBlock & B = * MI -> getParent ( ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; const BitTracker :: BitValue & V = SC [ F + BN ] ; if ( V . Type == BitTracker :: BitValue :: Ref && V . RefI . Reg != RS . Reg ) { const TargetRegisterClass * TC = MRI . getRegClass ( V . RefI . Reg ) ; unsigned P = UINT_MAX ; BitTracker :: RegisterRef RR ( V . RefI . Reg , <NUM_LIT> ) ; if ( TC == & <STR_LIT> ) { P = V . RefI . Pos ; RR . Sub = <STR_LIT> ; if ( P >= <NUM_LIT> ) { P -= <NUM_LIT> ; RR . Sub = <STR_LIT> ; } } else if ( TC == & <STR_LIT> ) { P = V . RefI . Pos ; } if ( P != UINT_MAX ) { unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( B , At , DL , HII . get ( <STR_LIT> ) , NewR ) . addReg ( RR . Reg , <NUM_LIT> , RR . Sub ) . addImm ( P ) ; HBS :: replaceReg ( RD . Reg , NewR , MRI ) ; BT . put ( NewR , RC ) ; return true ; } } else if ( V . is ( <NUM_LIT> ) || V . is ( <NUM_LIT> ) ) { unsigned NewR = MRI . createVirtualRegister ( & <STR_LIT> ) ;

unsigned NewOpc = V . is ( <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> bool <ISA_LIT>GOT :: reserveTLSLdmEntry ( ) { if ( m_HasTLSLdmSymbol ) return false ; m_HasTLSLdmSymbol = true ; m_MultipartList . back ( ) . m_TLSNum += <NUM_LIT> ; m_MultipartList . back ( ) . m_TLSDynNum += <NUM_LIT> ; return true ;


<s> rtx last_real_insn = prev_real_insn ( insn ) ;

if ( last_real_insn && NONJUMP_INSN_P ( last_real_insn ) && GET_CODE ( PATTERN ( last_real_insn ) ) == SEQUENCE ) last_real_insn = XVECEXP ( PATTERN ( last_real_insn ) , <NUM_LIT> , <NUM_LIT> ) ;


<s> MVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ;

C = ConstantVector :: getSplat ( NumElts , C ) ;


<s> if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( isDarwin ( ) ) HasLazyResolverStubs = true ; IsQPXStackUnaligned = QPXStackUnaligned ; StackAlignment = getPlatformStackAlignment ( ) ;

IsLittleEndian = ( TargetTriple . getArch ( ) == Triple :: ppc64le ) ;


<s> void <ISA_LIT>InstPrinter :: printNOneImmOperand ( MCInst const * MI , unsigned OpNo , raw_ostream & O ) const { O << - <NUM_LIT> ;


<s> unsigned Result = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , Result ) . addReg ( Reg ) ; return Result ; }

return signExtendToI32 ( Reg , V , From ) ;


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; MI . getOperand ( OpNo ) . ChangeToImmediate ( Offset ) ; assert ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; std :: advance ( MII , <NUM_LIT> ) ;

BuildMI ( MBB , MII , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( FrameReg ) ;


<s> return isTargetMachO ( ) ? ( ReserveR9 || ! HasV6Ops ) : ReserveR9 ;


<s> res = gen_reg_rtx ( mode ) ; emit_move_insn ( res , operand1 ) ; xa = ix86_expand_sse_fabs ( res , & mask ) ; TWO52 = ix86_gen_TWO52 ( mode ) ; label = ix86_expand_sse_compare_and_jump ( UNLE , TWO52 , xa , false ) ; xa = expand_simple_binop ( mode , PLUS , xa , TWO52 , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ; xa = expand_simple_binop ( mode , MINUS , xa , TWO52 , xa , <NUM_LIT> , OPTAB_DIRECT ) ; ix86_sse_copysign_to_positive ( res , xa , res , mask ) ;


<s> DirectXSubtarget :: DirectXSubtarget ( const Triple & TT , StringRef CPU , StringRef FS , const DirectXTargetMachine & TM ) : DirectXGenSubtargetInfo ( TT , CPU , CPU , FS ) , TL ( TM , * this ) {


<s> static Waitcnt allZero ( bool HasVscnt ) { return Waitcnt ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , HasVscnt ? <NUM_LIT> : ~ <NUM_LIT> ) ;


<s> auto MI = MB . begin ( ) ; while ( MI != End ) { auto NextI = std :: next ( MI ) ; if ( MI -> isKill ( ) ) { MB . erase ( MI ) ; End = MB . end ( ) ; } MI = NextI ; } } for ( auto & MB : MF ) { auto Begin = MB . begin ( ) , End = MB . end ( ) ; while ( Begin != End ) { MachineBasicBlock :: iterator RB = Begin ; while ( RB != End && HII -> isSchedulingBoundary ( * RB , & MB , MF ) ) ++ RB ; MachineBasicBlock :: iterator RE = RB ; while ( RE != End && ! HII -> isSchedulingBoundary ( * RE , & MB , MF ) ) ++ RE ; if ( RE != End ) ++ RE ;

if ( RB != End ) Packetizer . PacketizeMIs ( & MB , RB , RE ) ;


<s> initialize<ISA_LIT>LoopReschedulingPass ( * PassRegistry :: getPassRegistry ( ) ) ;


return <ISA_LIT>PropagateAttributes ( TM , true ) . process ( M ) ;


<s> if ( DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 ) return ( sel & SAVRES_REG ) == SAVRES_FPR || ( sel & SAVRES_LR ) ? <NUM_LIT> : <NUM_LIT> ; return DEFAULT_ABI == ABI_DARWIN && ( sel & SAVRES_REG ) == SAVRES_FPR ? <NUM_LIT> : <NUM_LIT> ;


<s> unsigned getEUsPerCU ( const MCSubtargetInfo * STI ) {


<s> void setAttributeItem ( unsigned Attribute , StringRef Value , bool OverwriteExisting ) { if ( AttributeItem * Item = getAttributeItem ( Attribute ) ) { if ( ! OverwriteExisting ) return ; Item -> Type = AttributeItem :: TextAttribute ;

Item -> StringValue = std :: string ( Value ) ;


<s> if ( ! ST -> hasMVEIntegerOps ( ) || DisableTailPredication ) return false ; return true ;


<s> static bool isFlatGlobalAddrSpace ( unsigned AS ) {

return AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS > <ISA_LIT>AS :: MAX_<ISA_LIT>_ADDRESS ;


<s> Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) Ctx -> reportFatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ;


<s> if ( FoldOffsetIntoAddress ( CP -> getOffset ( ) , AM ) ) { AM = Backup ; return true ; } } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else if ( BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( N0 ) ) { <ISA_LIT>ISelAddressMode Backup = AM ; AM . BlockAddr = BA -> getBlockAddress ( ) ; AM . SymbolFlags = BA -> getTargetFlags ( ) ; if ( FoldOffsetIntoAddress ( BA -> getOffset ( ) , AM ) ) { AM = Backup ; return true ; } } else llvm_unreachable ( <STR_LIT> ) ; if ( N . getOpcode ( ) == <STR_LIT> ) AM . setBaseReg ( CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) ; return false ; } if ( ! Subtarget -> is64Bit ( ) || M == CodeModel :: Small || M == CodeModel :: Kernel ) { assert ( N . getOpcode ( ) != <STR_LIT> && <STR_LIT> ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Align = CP -> getAlignment ( ) ; AM . Disp += CP -> getOffset ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( JumpTableSDNode * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else if ( BlockAddressSDNode * BA = dyn_cast < BlockAddressSDNode > ( N0 ) ) { AM . BlockAddr = BA -> getBlockAddress ( ) ; AM . Disp += BA -> getOffset ( ) ; AM . SymbolFlags = BA -> getTargetFlags ( ) ; } else llvm_unreachable ( <STR_LIT> ) ;


<s> return static_cast < <ISA_LIT>TargetMachine & > ( TM ) ;


<s> return insertVector ( Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , VecTy . getVectorElementType ( ) , DAG ) ;


<s> int LoadStoreOp = IsStore ? getOffsetMUBUFStore ( Opc ) : getOffsetMUBUFLoad ( Opc ) ; if ( LoadStoreOp == - <NUM_LIT> ) return false ; const MachineOperand * Reg = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) ; MachineInstrBuilder NewMI = BuildMI ( * MBB , MI , DL , TII -> get ( LoadStoreOp ) ) . add ( * Reg ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * MI , <STR_LIT> :: soffset ) ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . cloneMemRefs ( * MI ) ; const MachineOperand * VDataIn = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata_in ) ; if ( VDataIn ) NewMI . add ( * VDataIn ) ;


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( static_cast < uint32_t > ( OldOpnd -> getImm ( ) ) == std :: numeric_limits < uint32_t > :: max ( ) ) return true ; break ; case <STR_LIT> : case <STR_LIT> : if ( static_cast < int32_t > ( OldOpnd -> getImm ( ) ) == std :: numeric_limits < int32_t > :: max ( ) ) return true ; break ; case <STR_LIT> : case <STR_LIT> : if ( static_cast < int32_t > ( OldOpnd -> getImm ( ) ) == std :: numeric_limits < int32_t > :: min ( ) ) return true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( OldOpnd -> getImm ( ) == <NUM_LIT> ) return true ;


<s> std :: unique_ptr < MCObjectWriter > createObjectWriter ( raw_pwrite_stream & OS ) const override {

return create<ISA_LIT>WinCOFFObjectWriter ( OS , false ) ;


<s> } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; if ( flag_delayed_branch ) { funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; } else { rtx spill_reg , spill_reg2 , seq , scratch = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; if ( flag_pic ) { spill_reg = gen_rtx_REG ( word_mode , <NUM_LIT> ) ; spill_reg2 = gen_rtx_REG ( word_mode , PIC_OFFSET_TABLE_REGNUM ) ; start_sequence ( ) ; load_pic_register ( true ) ; scratch = legitimize_pic_address ( funexp , Pmode , scratch ) ; seq = get_insns ( ) ; end_sequence ( ) ; emit_and_preserve ( seq , spill_reg , spill_reg2 ) ; } else if ( TARGET_ARCH32 ) { emit_insn ( gen_rtx_SET ( VOIDmode , scratch , gen_rtx_HIGH ( SImode , funexp ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , scratch , gen_rtx_LO_SUM ( SImode , scratch , funexp ) ) ) ; } else { switch ( sparc_cmodel ) { case CM_MEDLOW : case CM_MEDMID : sparc_emit_set_symbolic_const64 ( scratch , funexp , scratch ) ; break ; case CM_MEDANY : case CM_EMBMEDANY : spill_reg = gen_rtx_REG ( DImode , <NUM_LIT> ) ; start_sequence ( ) ; sparc_emit_set_symbolic_const64 ( scratch , funexp , spill_reg ) ; seq = get_insns ( ) ; end_sequence ( ) ; emit_and_preserve ( seq , spill_reg , <NUM_LIT> ) ; break ; default : gcc_unreachable ( ) ; } } emit_jump_insn ( gen_indirect_jump ( scratch ) ) ; } emit_barrier ( ) ; insn = get_insns ( ) ;


<s> Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail :


<s> auto * Mask = dyn_cast < ConstantSDNode > ( C . Op0 . getOperand ( <NUM_LIT> ) ) ; if ( ! Mask ) return ; KnownBits Known ;

DAG . computeKnownBits ( C . Op0 . getOperand ( <NUM_LIT> ) , Known ) ;


<s> SDLoc dl ( Op ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ;

const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> if ( ! get<ISA_LIT>Subtarget ( ) . isTargetNaCl ( ) && ( ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) ) addPass ( createGlobalMergePass ( TM , <NUM_LIT> ) ) ; return false ;


<s> return ( spu_extract ( spu_gather ( spu_nor ( spu_cmpabsgt ( a , b ) , ( vec_uint4 ) ( spu_rlmaska ( ( vec_int4 ) ( b ) , - <NUM_LIT> ) ) ) ) , <NUM_LIT> ) != <NUM_LIT> ) ;


<s> EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasFP16 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && ! DCI . isBeforeLegalizeOps ( ) ) { unsigned FPOpcode = convertIntLogicToFPLogicOpcode ( N -> getOpcode ( ) ) ; SDValue FPLogic = DAG . getNode ( FPOpcode , DL , N00Type , N00 , N10 ) ; return DAG . getBitcast ( VT , FPLogic ) ; } if ( VT != <STR_LIT> || N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) || ! N1 . hasOneUse ( ) ) return SDValue ( ) ; <STR_LIT> CC0 = cast < CondCodeSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; <STR_LIT> CC1 = cast < CondCodeSDNode > ( N1 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( ! Subtarget . hasAVX ( ) && ! ( cheap<ISA_LIT>FSETCC_SSE ( CC0 ) && cheap<ISA_LIT>FSETCC_SSE ( CC1 ) ) ) return SDValue ( ) ;

unsigned NumElts = <NUM_LIT> / N00Type . getSizeInBits ( ) ;


<s> void BTFTypeFunc :: emitType ( MCStreamer & OS ) {


<s> ~ <ISA_LIT>Disassembler ( ) override { if ( MII ) delete MII ;


<s> rtx l1 , labelno , pic_tmp , pic_tmp2 , pic_rtx ; rtx global_offset_table ; if ( current_function_uses_pic_offset_table == <NUM_LIT> || TARGET_SINGLE_PIC_BASE ) return ; gcc_assert ( flag_pic ) ; labelno = GEN_INT ( pic_labelno ++ ) ; l1 = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; l1 = gen_rtx_CONST ( VOIDmode , l1 ) ; global_offset_table = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; pic_tmp = plus_constant ( l1 , TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ; if ( GOT_PCREL ) pic_tmp2 = gen_rtx_CONST ( VOIDmode , gen_rtx_PLUS ( Pmode , global_offset_table , pc_rtx ) ) ; else pic_tmp2 = gen_rtx_CONST ( VOIDmode , global_offset_table ) ; pic_rtx = gen_rtx_CONST ( Pmode , gen_rtx_MINUS ( Pmode , pic_tmp2 , pic_tmp ) ) ;


<s> for ( auto UI = MRI -> use_begin ( CondReg ) , E = MRI -> use_end ( ) ; UI != E ; ++ UI ) { ( * UI ) . setIsKill ( false ) ; }


<s> int GLCPos = <STR_LIT> ( Inst . getOpcode ( ) , <STR_LIT> :: glc1 ) ; if ( GLCPos != - <NUM_LIT> ) { if ( Inst . getOperand ( GLCPos ) . getImm ( ) == - <NUM_LIT> ) { Error ( IDLoc , <STR_LIT> ) ; return false ; }


<s> case HImode : case QImode : s390_expand_cs_hqi ( mode , btarget , vtarget , mem , cmp , new_rtx , is_weak ) ; break ; default : gcc_unreachable ( ) ; }


<s> rtx ret = gen_rtx_REG ( SImode , TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; emit_move_insn ( gen_rtx_REG ( SImode , <NUM_LIT> ) , operands [ <NUM_LIT> ] ) ; emit ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , gen_rtx_SET ( VOIDmode , gen_rtx_REG ( SImode , <NUM_LIT> ) , gen_rtx_fmt_ee ( unsignedp ? UDIV : DIV , SImode , gen_rtx_REG ( SImode , <NUM_LIT> ) , operands [ <NUM_LIT> ] ) ) , gen_rtx_CLOBBER ( VOIDmode , operands [ <NUM_LIT> ] ) , gen_rtx_CLOBBER ( VOIDmode , operands [ <NUM_LIT> ] ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( SImode , <NUM_LIT> ) ) , gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( SImode , <NUM_LIT> ) ) , gen_rtx_CLOBBER ( VOIDmode , ret ) ) ) ) ; emit_move_insn ( operands [ <NUM_LIT> ] , gen_rtx_REG ( SImode , <NUM_LIT> ) ) ;


<s> switch ( Opc ) { case <STR_LIT> : V = int8_t ( U ) ; break ; case <STR_LIT> : V = int16_t ( U ) ; break ; case <STR_LIT> : V = int32_t ( U ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( ! isInt < <NUM_LIT> > ( V ) ) return false ; MI -> removeOperand ( <NUM_LIT> ) ; switch ( Opc ) { case <STR_LIT> : MI -> setDesc ( HII . get ( <STR_LIT> ) ) ; break ; case <STR_LIT> : MI -> setDesc ( HII . get ( <STR_LIT> ) ) ; break ; case <STR_LIT> : MI -> setDesc ( HII . get ( <STR_LIT> ) ) ; break ; }

MI -> addOperand ( MachineOperand :: CreateImm ( V ) ) ;


<s> int FPSI = FI -> getFramePointerSaveIndex ( ) ; bool is<ISA_LIT>64 = Subtarget . is<ISA_LIT>64 ( ) ; bool isDarwinABI = Subtarget . isDarwinABI ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; if ( ! FPSI && needsFP ( MF ) ) { int FPOffset = getFramePointerSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; FPSI = MFI -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ; FI -> setFramePointerSaveIndex ( FPSI ) ; } int TCSPDelta = <NUM_LIT> ; if ( MF . getTarget ( ) . Options . GuaranteedTailCallOpt && ( TCSPDelta = FI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { MFI -> CreateFixedObject ( - <NUM_LIT> * TCSPDelta , TCSPDelta , true ) ; } if ( ! is<ISA_LIT>64 && ! isDarwinABI && ( MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) || MRI . isPhysRegUsed ( <STR_LIT> ) ) ) { int FrameIdx = MFI -> CreateFixedObject ( ( uint64_t ) <NUM_LIT> , ( int64_t ) - <NUM_LIT> , true ) ;

FI -> setCRSpillFrameIndex ( FrameIdx ) ;


<s> unsigned OpNo = Op . getNode ( ) -> isStrictFPOpcode ( ) ? <NUM_LIT> : <NUM_LIT> ; SDValue N0 = Op . getOperand ( OpNo ) ; MVT SrcVT = N0 . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; switch ( SrcVT . SimpleTy ) { default :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> for ( Use & U : I . operands ( ) ) { Constant * Cst = dyn_cast < Constant > ( U ) ; if ( ! Cst || isa < GlobalValue > ( Cst ) || isa < ConstantExpr > ( Cst ) ) continue ;

if ( ! shouldConvert ( * Cst , PromotionCache ) ) continue ;


<s> void AMDGPUAsmPrinter :: EmitEndOfAsmFile ( Module & M ) { const TargetLoweringObjectFile & TLOF = getObjFileLowering ( ) ;

OutStreamer -> SwitchSection ( TLOF . getTextSection ( ) ) ;


<s> bool isPIC = ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) ; bool isCodeLarge = ( TM . getCodeModel ( ) == CodeModel :: Large ) ; if ( MI -> getOpcode ( ) == <STR_LIT> && ! MO . isReg ( ) && ! MO . isImm ( ) ) { if ( ( isPIC ) && ( isCodeLarge ) ) O << <STR_LIT> ; else O << <STR_LIT> ; closeP = true ; } else if ( ( MI -> getOpcode ( ) == <STR_LIT> ) && ! MO . isReg ( ) && ! MO . isImm ( ) ) { const MachineOperand & firstMO = MI -> getOperand ( opNum - <NUM_LIT> ) ; if ( firstMO . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ; else O << <STR_LIT> ; closeP = true ;

} else if ( ( isPIC ) && ( MI -> getOpcode ( ) == <STR_LIT> ) && ( ! MO . isReg ( ) ) && ( ! MO . isImm ( ) ) ) {


<s> for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; } } else { assert ( ( Offset + FulleSizeInBytes ) <= Data . size ( ) && <STR_LIT> ) ; assert ( NumBytes <= FulleSizeInBytes && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = FulleSizeInBytes - <NUM_LIT> - i ; Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; } }


<s> Binary |= ( RegN & <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ( RegN >> <NUM_LIT> ) & <NUM_LIT> ) << <STR_LIT> ;


<s> restore_fpr ( frame_pointer , offset + next_offset , i ) ; cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( DFmode , i ) , cfa_restores ) ; next_offset += <NUM_LIT> ; } else if ( ! TARGET_PACKED_STACK ) next_offset += <NUM_LIT> ; } } if ( cfun_frame_layout . first_restore_gpr != - <NUM_LIT> ) { rtx insn , addr ; int i ; for ( i = cfun_frame_layout . first_restore_gpr ; i <= cfun_frame_layout . last_restore_gpr ; i ++ ) { if ( global_not_special_regno_p ( i ) ) { addr = plus_constant ( Pmode , frame_pointer , offset + cfun_frame_layout . gprs_offset + ( i - cfun_frame_layout . first_save_gpr_slot ) * UNITS_PER_LONG ) ; addr = gen_rtx_MEM ( Pmode , addr ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; emit_move_insn ( addr , gen_rtx_REG ( Pmode , i ) ) ; } else cfa_restores = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( Pmode , i ) , cfa_restores ) ; } if ( ! sibcall && cfun_gpr_save_slot ( RETURN_REGNUM ) == SAVE_SLOT_STACK && s390_tune <= PROCESSOR_2097_Z10 ) { int return_regnum = find_unused_clobbered_reg ( ) ; if ( ! return_regnum || ( TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION && ! TARGET_CPU_Z10 && return_regnum == INDIRECT_BRANCH_THUNK_REGNUM ) ) { gcc_assert ( INDIRECT_BRANCH_THUNK_REGNUM != <NUM_LIT> ) ; return_regnum = <NUM_LIT> ; } return_reg = gen_rtx_REG ( Pmode , return_regnum ) ; addr = plus_constant ( Pmode , frame_pointer , offset + cfun_frame_layout . gprs_offset + ( RETURN_REGNUM - cfun_frame_layout . first_save_gpr_slot ) * UNITS_PER_LONG ) ; addr = gen_rtx_MEM ( Pmode , addr ) ; set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ; emit_move_insn ( return_reg , addr ) ; cfun_frame_layout . save_return_addr_p = true ; } insn = restore_gprs ( frame_pointer , offset + cfun_frame_layout . gprs_offset + ( cfun_frame_layout . first_restore_gpr - cfun_frame_layout . first_save_gpr_slot ) * UNITS_PER_LONG , cfun_frame_layout . first_restore_gpr , cfun_frame_layout . last_restore_gpr ) ; insn = emit_insn ( insn ) ; REG_NOTES ( insn ) = cfa_restores ; add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , stack_pointer_rtx , STACK_POINTER_OFFSET ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } s390_restore_gprs_from_fprs ( ) ;


<s> unsigned BaseReg = getLdStBaseOp ( MemMI ) . getReg ( ) ; int MIUnscaledOffset = getLdStOffsetOp ( MemMI ) . getImm ( ) * getMemScale ( MemMI ) ; if ( MIUnscaledOffset != UnscaledOffset ) return E ; bool IsPairedInsn = isPairedLdSt ( MemMI ) ; for ( unsigned i = <NUM_LIT> , e = IsPairedInsn ? <NUM_LIT> : <NUM_LIT> ; i != e ; ++ i ) { unsigned DestReg = getLdStRegOp ( MemMI , i ) . getReg ( ) ; if ( DestReg == BaseReg || TRI -> isSubRegister ( BaseReg , DestReg ) ) return E ; }


<s> Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ;


<s> if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { unsigned TCOpcode = ( RetOpcode == <STR_LIT> ) ? ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) : ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; }

if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> static void cris_operand_lossage ( const char * msgid , rtx op ) { debug_rtx ( op ) ;

output_operand_lossage ( <STR_LIT> , msgid ) ;


<s> rtx tmp2 = gen_reg_rtx ( mode ) ; emit_insn ( intfn ( tmp1 , op1 , tmp2 ) ) ; emit_move_insn ( mem , tmp1 ) ; mem = adjust_address ( mem , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( mem , tmp2 ) ;


<s> return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , <NUM_LIT> ) ;


<s> SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue WordOff = DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ; SDValue OffsetSlot = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackSlot , WordOff ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FudgePtr , Offset ) ;

SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , FudgePtr , MachinePointerInfo :: getConstantPool ( ) , <STR_LIT> , false , false , <NUM_LIT> ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>AnnotateControlFlowPass ( ) {

return new <ISA_LIT>AnnotateControlFlow ( ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectCmp ( MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF ) const { assert ( ( I . getOpcode ( ) == TargetOpcode :: G_ICMP ) && <STR_LIT> ) ; <STR_LIT> CC ; bool SwapArgs ; std :: tie ( CC , SwapArgs ) = <STR_LIT> ( ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) ) ; unsigned OpSet = <STR_LIT> ( CC ) ; unsigned LHS = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RHS = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( SwapArgs ) std :: swap ( LHS , RHS ) ; unsigned OpCmp ; LLT Ty = MRI . getType ( LHS ) ; switch ( Ty . getSizeInBits ( ) ) { default : return false ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; } MachineInstr & CmpInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( OpCmp ) ) . addReg ( LHS ) . addReg ( RHS ) ; MachineInstr & SetInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( OpSet ) , I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; constrainSelectedInstRegOperands ( CmpInst , TII , TRI , RBI ) ; constrainSelectedInstRegOperands ( SetInst , TII , TRI , RBI ) ;


<s> bool <ISA_LIT>TTIImpl :: areInlineCompatible ( const Function * Caller , const Function * Callee ) const { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; const FeatureBitset & CallerBits = TM . getSubtargetImpl ( * Caller ) -> getFeatureBits ( ) ;

const FeatureBitset & CalleeBits = TM . getSubtargetImpl ( * Callee ) -> getFeatureBits ( ) ;


<s> } if ( ( OpVT . is256BitVector ( ) || OpVT . is512BitVector ( ) ) && SubVecVT . is128BitVector ( ) ) return Insert128BitVector ( Vec , SubVec , IdxVal , DAG , dl ) ; if ( OpVT . is512BitVector ( ) && SubVecVT . is256BitVector ( ) ) return Insert256BitVector ( Vec , SubVec , IdxVal , DAG , dl ) ; if ( OpVT . getVectorElementType ( ) == <STR_LIT> ) { if ( IdxVal == <NUM_LIT> && Vec . getOpcode ( ) == <STR_LIT> ) return Op ; SDValue ZeroIdx = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Undef = DAG . getUNDEF ( OpVT ) ; unsigned NumElems = OpVT . getVectorNumElements ( ) ; SDValue ShiftBits = DAG . getConstant ( NumElems / <NUM_LIT> , dl , <STR_LIT> ) ; if ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) { Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , ShiftBits ) ; Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , ShiftBits ) ;

SDValue Vec2 = DAG . getNode ( <STR_LIT> , dl , OpVT , Undef , SubVec , ZeroIdx ) ;


<s> if ( TM . getSubtargetImpl ( ) -> isDarwin ( ) ) return new TargetLoweringObjectFileMachO ( ) ;

if ( TM . getSubtargetImpl ( ) -> isSVR4ABI ( ) ) return new <ISA_LIT>64LinuxTargetObjectFile ( ) ;


<s> get<ISA_LIT>ProgramInfo ( KernelInfo , * MF ) ; getAmdKernelCode ( KernelCode , KernelInfo , * MF ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; getTargetStreamer ( ) . EmitAMDKernelCodeT ( KernelCode ) ; } if ( TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA ) return ;

getTargetStreamer ( ) . EmitKernelCodeObjectMetadata ( * MF -> getFunction ( ) , KernelCode ) ;


<s> isT2 = true ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else { return false ; } if ( ! Op0 -> hasOneMemOperand ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function * Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func -> getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( * Op0 ) ; if ( isT2 ) { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = OffImm ; } else { <STR_LIT> AddSub = <STR_LIT> ; if ( OffImm < <NUM_LIT> ) { AddSub = <STR_LIT> ; OffImm = - OffImm ; } int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ; if ( OffImm >= Limit || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ; Offset = <STR_LIT> ( AddSub , OffImm ) ; } FirstReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SecondReg = Op1 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( FirstReg == SecondReg ) return false ; BaseReg = Op0 -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Pred = getInstrPredicate ( * Op0 , PredReg ) ; dl = Op0 -> getDebugLoc ( ) ; return true ;


<s> int32_t Log2IfPositive = ( Mask -> getAPIntValue ( ) + <NUM_LIT> ) . exactLogBase2 ( ) ; if ( Log2IfPositive <= <NUM_LIT> ) return SDValue ( ) ; SDValue Op0Op2 = Op0 -> getOperand ( <NUM_LIT> ) ; EVT ExtendTy = cast < VTSDNode > ( Op0Op2 ) -> getVT ( ) ; unsigned ExtendTySize = ExtendTy . getSizeInBits ( ) ; unsigned Log2 = Log2IfPositive ; if ( ( Op0Opcode == <STR_LIT> && Log2 >= ExtendTySize ) || Log2 == ExtendTySize ) { SDValue Ops [ ] = { Op0 -> getOperand ( <NUM_LIT> ) , Op0 -> getOperand ( <NUM_LIT> ) , Op0Op2 } ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op0 ) , Op0 -> getVTList ( ) , makeArrayRef ( Ops , Op0 -> getNumOperands ( ) ) ) ; }


<s> unsigned I = <NUM_LIT> ; for ( ; I < <STR_LIT> ; ++ I ) { uint64_t Byte = IntBits . lshr ( I * <NUM_LIT> ) . trunc ( <NUM_LIT> ) . getZExtValue ( ) ; if ( Byte == <NUM_LIT> ) Mask |= <NUM_LIT> << I ; else if ( Byte != <NUM_LIT> ) break ; } if ( I == <STR_LIT> ) { Opcode = <STR_LIT> ; OpVals . push_back ( Mask ) ; VecVT = <STR_LIT> ( <STR_LIT> ( <NUM_LIT> ) , <NUM_LIT> ) ; return true ; } if ( SplatBitSize > <NUM_LIT> ) return false ; auto tryValue = [ & ] ( uint64_t Value ) -> bool { int64_t SignedValue = SignExtend64 ( Value , SplatBitSize ) ; if ( isInt < <NUM_LIT> > ( SignedValue ) ) { OpVals . push_back ( ( ( unsigned ) SignedValue ) ) ; Opcode = <STR_LIT> ; VecVT = <STR_LIT> ( <STR_LIT> ( SplatBitSize ) , <STR_LIT> / SplatBitSize ) ; return true ; } unsigned Start , End ; if ( TII -> isRxSBGMask ( Value , SplatBitSize , Start , End ) ) { OpVals . push_back ( Start - ( <NUM_LIT> - SplatBitSize ) ) ; OpVals . push_back ( End - ( <NUM_LIT> - SplatBitSize ) ) ; Opcode = <STR_LIT> ; VecVT = <STR_LIT> ( <STR_LIT> ( SplatBitSize ) , <STR_LIT> / SplatBitSize ) ;


<s> char * buf ; if ( symtab -> state != PARSING ) return ; size = strlen ( string ) + <NUM_LIT> ; if ( size <= microblaze_section_threshold ) section_asm_op = SDATA2_SECTION_ASM_OP ; else section_asm_op = READONLY_DATA_SECTION_ASM_OP ; buf = ACONCAT ( ( section_asm_op , <STR_LIT> , string , <STR_LIT> , NULL ) ) ;

symtab -> finalize_toplevel_asm ( build_string ( strlen ( buf ) , buf ) ) ;


<s> const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getValueType ( ) ) ; unsigned Align = GV -> getAlignment ( ) ; if ( ! Align ) Align = <NUM_LIT> ; emitVisibility ( GVSym , GV -> getVisibility ( ) , ! GV -> isDeclaration ( ) ) ; emitLinkage ( GV , GVSym ) ; if ( auto TS = getTargetStreamer ( ) ) TS -> emit<ISA_LIT>LDS ( GVSym , Size , Align ) ;


<s> case <STR_LIT> : addLeaRegOffset ( MIB , leaInReg , true , MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : { unsigned Src2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill2 = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; unsigned leaInReg2 = <NUM_LIT> ; MachineInstr * InsMI2 = <NUM_LIT> ; if ( Src == Src2 ) { addRegReg ( MIB , leaInReg , true , leaInReg , false ) ; } else { leaInReg2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) ; InsMI2 = BuildMI ( * MFI , MIB , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , leaInReg2 ) . addReg ( leaInReg2 ) . addReg ( Src2 , getKillRegState ( isKill2 ) ) . addImm ( <STR_LIT> ) ; addRegReg ( MIB , leaInReg , true , leaInReg2 , true ) ; } if ( LV && isKill2 && InsMI2 ) LV -> replaceKillInstruction ( Src2 , MI , InsMI2 ) ; break ; } } MachineInstr * NewMI = MIB ; MachineInstr * ExtMI = BuildMI ( * MFI , MBBI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( Dest , RegState :: Define | getDeadRegState ( isDead ) ) . addReg ( leaOutReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ; if ( LV ) {

LV -> getVarInfo ( leaInReg ) . Kills . push_back ( NewMI ) ;


<s> else __rshift = ( __v2du ) vec_splats ( ( unsigned long long ) __B ) ; } else __rshift = ( __v2du ) vec_splats ( ( unsigned int ) __B ) ; __result = vec_sr ( ( __v2di ) __A , __rshift ) ;


<s> else { unsigned Wt = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Wt ) . addReg ( Ws ) . addImm ( <NUM_LIT> ) ; BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , Fd ) . addReg ( Wt , <NUM_LIT> , <STR_LIT> ) ; } MI -> eraseFromParent ( ) ; return BB ;


<s> static void addOperands ( MachineInstrBuilder & MIB , ArrayRef < MachineOperand > MOs , int PtrOffset = <NUM_LIT> ) { unsigned NumAddrOps = MOs . size ( ) ; if ( NumAddrOps < <NUM_LIT> ) { for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) MIB . addOperand ( MOs [ i ] ) ; addOffset ( MIB , PtrOffset ) ; } else { assert ( MOs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) { const MachineOperand & MO = MOs [ i ] ; if ( i == <NUM_LIT> && PtrOffset != <NUM_LIT> ) { assert ( ( MO . isImm ( ) || MO . isGlobal ( ) ) && <STR_LIT> ) ;


<s> return ( ( vec_double2 ) ( si_rotqby ( ( qword ) ( a ) , si_from_int ( count ) ) ) ) ;


<s> if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> ) { for ( SDNode :: use_iterator UI = Addr . getNode ( ) -> use_begin ( ) , UE = Addr . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { if ( UI -> getOpcode ( ) == <STR_LIT> ) { MatchAddressBase ( Addr , AM12 ) ; Done = true ; break ; } } } } if ( ! Done && MatchAddress ( Addr , AM12 , true ) ) return false ; if ( ! Done && ! is12BitOnly && ! MatchAddress ( Addr , AM20 , false ) ) if ( AM12 . Disp == <NUM_LIT> && AM20 . Disp != <NUM_LIT> ) return false ;

DEBUG ( errs ( ) << <STR_LIT> ; AM12 . dump ( ) ) ;


<s> if ( ! MF . getName ( ) . startswith ( getDerived ( ) . getThunkPrefix ( ) ) ) { if ( InsertedThunks ) return false ; if ( ! getDerived ( ) . mayUseThunk ( MF ) ) return false ; getDerived ( ) . insertThunks ( MMI ) ; InsertedThunks = true ; return true ; }


<s> AU . setPreservesAll ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> return ( __m512i ) __builtin_ia32_broadcastmw512 ( __A ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: Static ) {

SDValue A = DAG . getTargetBlockAddress ( BA , PtrVT ) ;


<s> } printOperand ( MI , OpNo , STI , O ) ; O << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT> , STI , O ) ;


<s> RawVectorOstream :: RawVectorOstream ( raw_pwrite_stream * other ) : Data ( AllocationChunk ) , Position ( <NUM_LIT> ) , Other ( other ) {


<s> auto * Shift = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! Shift ) return false ; uint64_t Amount = Shift -> getZExtValue ( ) ; if ( Amount >= N . getValueSizeInBits ( ) ) return false ;


<s> static bool riscv_allocate_stack_slots_for_args ( ) { return ! riscv_naked_function_p ( current_function_decl ) ;


<s> constexpr aarch64_simd_vec_issue_info ( aarch64_base_vec_issue_info base , unsigned int ld2_st2_general_ops , unsigned int ld3_st3_general_ops , unsigned int ld4_st4_general_ops ) : aarch64_base_vec_issue_info ( base ) , ld2_st2_general_ops ( ld2_st2_general_ops ) , ld3_st3_general_ops ( ld3_st3_general_ops ) , ld4_st4_general_ops ( ld4_st4_general_ops ) {


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , StringRef CPU ) : <ISA_LIT>AsmBackend ( T , CPU ) {


<s> switch ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) ) { case CONST_INT : fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] , INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ; break ; case SYMBOL_REF : output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; break ; case CONST : { rtx plus = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( plus , <NUM_LIT> ) ) == SYMBOL_REF && CONST_INT_P ( XEXP ( plus , <NUM_LIT> ) ) ) {

output_addr_const ( file , XEXP ( plus , <NUM_LIT> ) ) ;


<s> SDValue Addic = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , AddInput , getI32Imm ( ~ <NUM_LIT> , dl ) ) , <NUM_LIT> ) ;

return SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Addic , Addic , Addic . getValue ( <NUM_LIT> ) ) , <NUM_LIT> ) ;


<s> unsigned <ISA_LIT>CodeEmitter :: getMachineOpValue ( const MachineInstr & MI , const MachineOperand & MO ) const { if ( MO . isReg ( ) ) return II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; else if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ;

else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , <STR_LIT> , true , false ) ;


<s> MachineInstr * NewMI = BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . add ( Dest ) . add ( Src ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; return NewMI ; } } if ( ! MI . isConvertibleTo3Addr ( ) ) return nullptr ; switch ( MI . getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> const Loop * L = LI -> getLoopFor ( Start ) ; if ( L ) { const Loop * P = L ; do { L = P ; P = P -> getParentLoop ( ) ; } while ( P ) ;

Checklist . insert ( L -> block_begin ( ) , L -> block_end ( ) ) ;


<s> } if ( ! validateSOPLiteral ( Inst ) ) { Error ( getLitLoc ( Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateVOPLiteral ( Inst , Operands ) ) { return false ; } if ( ! validateConstantBusLimitations ( Inst , Operands ) ) { return false ; } if ( ! validateEarlyClobberLimitations ( Inst , Operands ) ) { return false ; } if ( ! validateIntClampSupported ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateOpSel ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyOpSel , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateDPP ( Inst , Operands ) ) { return false ; } if ( ! validateMIMGD16 ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyD16 , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateMIMGDim ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGMSAA ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyDim , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateMIMGDataSize ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGAddrSize ( Inst ) ) { Error ( IDLoc , <STR_LIT> ) ; return false ; } if ( ! validateMIMGAtomicDMask ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyDMask , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateMIMGGatherDMask ( Inst ) ) { Error ( getImmLoc ( <ISA_LIT>Operand :: ImmTyDMask , Operands ) , <STR_LIT> ) ; return false ; } if ( ! validateMovrels ( Inst , Operands ) ) { return false ; } if ( ! validateFlatOffset ( Inst , Operands ) ) { return false ; } if ( ! validateSMEMOffset ( Inst , Operands ) ) { return false ; } if ( ! validateMAIAccWrite ( Inst , Operands ) ) { return false ; } if ( ! validateMFMA ( Inst , Operands ) ) { return false ; } if ( ! validateCoherencyBits ( Inst , Operands , IDLoc ) ) { return false ; } if ( ! validateAGPRLdSt ( Inst ) ) { Error ( IDLoc , getFeatureBits ( ) [ <STR_LIT> ] ? <STR_LIT> : <STR_LIT> ) ; return false ; }


<s> bool <ISA_LIT>AsmParser :: MatchRegisterName ( unsigned & RegNo , int64_t & IntVal ) { if ( getParser ( ) . getTok ( ) . is ( AsmToken :: Percent ) ) getParser ( ) . Lex ( ) ; if ( ! getParser ( ) . getTok ( ) . is ( AsmToken :: Identifier ) ) return true ; StringRef Name = getParser ( ) . getTok ( ) . getString ( ) ; if ( Name . equals_lower ( <STR_LIT> ) ) { RegNo = is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; IntVal = <NUM_LIT> ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { RegNo = is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; IntVal = <NUM_LIT> ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { RegNo = <STR_LIT> ; IntVal = <NUM_LIT> ;

} else if ( Name . startswith_lower ( <STR_LIT> ) && ! Name . substr ( <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , IntVal ) && IntVal < <NUM_LIT> ) {


<s> ScheduleHazardRecognizer * <ISA_LIT>InstrInfo :: CreateTargetHazardRecognizer ( const TargetMachine * TM , const ScheduleDAG * DAG ) const { unsigned Directive = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new <ISA_LIT>ScoreboardHazardRecognizer ( II , DAG ) ; } return TargetInstrInfo :: CreateTargetHazardRecognizer ( TM , DAG ) ;


<s> Lane = SubIdx2Lane ( I -> getConstantOperandVal ( <NUM_LIT> ) ) ; unsigned Comp ; for ( unsigned i = <NUM_LIT> , Dmask = OldDmask ; i <= Lane ; i ++ ) { assert ( Dmask ) ; Comp = countTrailingZeros ( Dmask ) ; Dmask &= ~ ( <NUM_LIT> << Comp ) ; } if ( Users [ Lane ] ) return ; Users [ Lane ] = * I ; NewDmask |= <NUM_LIT> << Comp ; } if ( NewDmask == OldDmask ) return ; std :: vector < SDValue > Ops ; Ops . push_back ( DAG . getTargetConstant ( NewDmask , SDLoc ( Node ) , <STR_LIT> ) ) ; Ops . insert ( Ops . end ( ) , Node -> op_begin ( ) + <NUM_LIT> , Node -> op_end ( ) ) ; Node = ( MachineSDNode * ) DAG . UpdateNodeOperands ( Node , Ops ) ; if ( NewDmask && ( NewDmask & ( NewDmask - <NUM_LIT> ) ) == <NUM_LIT> ) { SDValue RC = DAG . getTargetConstant ( <STR_LIT> , SDLoc ( ) , <STR_LIT> ) ; SDNode * Copy = DAG . getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( ) , Users [ Lane ] -> getValueType ( <NUM_LIT> ) , SDValue ( Node , <NUM_LIT> ) , RC ) ; DAG . ReplaceAllUsesWith ( Users [ Lane ] , Copy ) ; return ; } for ( unsigned i = <NUM_LIT> , Idx = <STR_LIT> ; i < <NUM_LIT> ; ++ i ) { SDNode * User = Users [ i ] ; if ( ! User ) continue ; SDValue Op = DAG . getTargetConstant ( Idx , SDLoc ( User ) , <STR_LIT> ) ; DAG . UpdateNodeOperands ( User , User -> getOperand ( <NUM_LIT> ) , Op ) ; switch ( Idx ) { default : break ; case <STR_LIT> : Idx = <STR_LIT> ; break ; case <STR_LIT> : Idx = <STR_LIT> ; break ; case <STR_LIT> : Idx = <STR_LIT> ; break ; }


<s> sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;

BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ;


<s> } } return false ; } switch ( ValVT . SimpleTy ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : assert ( Is<ISA_LIT>64 && <STR_LIT> ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : { const unsigned Offset = State . AllocateStack ( PtrAlign . value ( ) , PtrAlign ) ; if ( ValVT . getSizeInBits ( ) < RegVT . getSizeInBits ( ) ) LocInfo = ArgFlags . isSExt ( ) ? CCValAssign :: LocInfo :: SExt : CCValAssign :: LocInfo :: ZExt ; if ( unsigned Reg = State . AllocateReg ( Is<ISA_LIT>64 ? GPR_64 : GPR_32 ) ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , RegVT , LocInfo ) ) ; else State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , RegVT , LocInfo ) ) ; return false ; } case <STR_LIT> : case <STR_LIT> : { const unsigned StoreSize = LocVT . getStoreSize ( ) ; const unsigned Offset = State . AllocateStack ( Is<ISA_LIT>64 ? <NUM_LIT> : StoreSize , Align ( <NUM_LIT> ) ) ; unsigned FReg = State . AllocateReg ( FPR ) ; if ( FReg ) State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , FReg , LocVT , LocInfo ) ) ;

for ( unsigned I = <NUM_LIT> ; I < StoreSize ; I += PtrAlign . value ( ) ) {


<s> Switches . erase ( std :: remove_if ( Switches . begin ( ) , Switches . end ( ) , [ & ] ( const SwitchInfo * E ) -> bool { return ( E -> Options & OptAlias ) || ! E -> fitsTargetFeatures ( Features ) || ( E -> OpType & T_Type ) == <NUM_LIT> ; } ) , Switches . end ( ) ) ;


<s> int Offset = getLdStOffsetOp ( FirstMI ) . getImm ( ) ; int OffsetStride = IsUnscaled ? getMemScale ( FirstMI ) : <NUM_LIT> ; bool IsPromotableZeroStore = isPromotableZeroStoreInst ( FirstMI ) ; ModifiedRegs . reset ( ) ; UsedRegs . reset ( ) ; SmallVector < MachineInstr * , <NUM_LIT> > MemInsns ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isDebugValue ( ) ) continue ; ++ Count ; Flags . setSExtIdx ( - <NUM_LIT> ) ; if ( areCandidatesToMergeOrPair ( FirstMI , MI , Flags , TII ) && getLdStOffsetOp ( MI ) . isImm ( ) ) { assert ( MI -> mayLoadOrStore ( ) && <STR_LIT> ) ; unsigned MIBaseReg = getLdStBaseOp ( MI ) . getReg ( ) ; int MIOffset = getLdStOffsetOp ( MI ) . getImm ( ) ; bool MIIsUnscaled = TII -> isUnscaledLdSt ( MI ) ; if ( IsUnscaled != MIIsUnscaled ) { int MemSize = getMemScale ( MI ) ; if ( MIIsUnscaled ) { if ( MIOffset % MemSize ) continue ; MIOffset /= MemSize ; } else { MIOffset *= MemSize ; } } if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( FindNarrowMerge ) { if ( ( ! IsUnscaled && alignTo ( MinOffset , <NUM_LIT> ) != MinOffset ) || ( IsPromotableZeroStore && Reg != getLdStRegOp ( MI ) . getReg ( ) ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } } else { if ( ! inBoundsForPair ( IsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ; continue ; } if ( IsUnscaled && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; MemInsns . push_back ( MI ) ;


<s> static unsigned GetAnalyzableBrOpc ( unsigned Opc ) {

return ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ? Opc : <NUM_LIT> ;


<s> if ( Vec ) return <NUM_LIT> ; if ( ST -> getGeneration ( ) >= AMDGPUSubtarget :: SOUTHERN_ISLANDS ) return <NUM_LIT> ;


<s> MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> && ! MO . isDead ( ) ) { return true ; } } return false ;


<s> SDValue Other = N00 ; if ( ! Shuffle ) { Shuffle = dyn_cast < ShuffleVectorSDNode > ( N00 ) ; Other = N01 ; } if ( Shuffle && Shuffle -> getMaskElt ( <NUM_LIT> ) == <NUM_LIT> && Other == Shuffle -> getOperand ( <NUM_LIT> ) ) { SDValue Extract1 = DAG . getNode ( <STR_LIT> , DL , VT , Other , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Extract2 = DAG . getNode ( <STR_LIT> , DL , VT , Other , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; if ( ! IsStrict ) return DAG . getNode ( N0 -> getOpcode ( ) , DL , VT , Extract1 , Extract2 ) ; SDValue Ret = DAG . getNode ( N0 -> getOpcode ( ) , DL , { VT , <STR_LIT> } , { N0 -> getOperand ( <NUM_LIT> ) , Extract1 , Extract2 } ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Ret ) ; DAG . ReplaceAllUsesOfValueWith ( N0 . getValue ( <NUM_LIT> ) , Ret . getValue ( <NUM_LIT> ) ) ; return SDValue ( N , <NUM_LIT> ) ; } } return SDValue ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: EmitCmp ( SDValue Op0 , SDValue Op1 , unsigned <ISA_LIT>CC , const SDLoc & DL , SelectionDAG & DAG ) const { if ( isNullConstant ( Op1 ) ) return EmitTest ( Op0 , <ISA_LIT>CC , DL , DAG ) ; assert ( ! ( isa < ConstantSDNode > ( Op1 ) && Op0 . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { if ( ( Op0 . getValueType ( ) == <STR_LIT> && ( isa < ConstantSDNode > ( Op0 ) || isa < ConstantSDNode > ( Op1 ) ) ) && ! DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ;

Op0 = DAG . getNode ( ExtendOp , DL , <STR_LIT> , Op0 ) ;


<s> if ( TT . isOSBinFormatXCOFF ( ) ) return new <ISA_LIT>TargetXCOFFStreamer ( S ) ;

return new <ISA_LIT>TargetMachOStreamer ( S ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . addReg ( DestReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . addReg ( DestReg , RegState :: Kill ) . add ( predOps ( Pred , PredReg ) ) . add ( condCodeOp ( ) ) . setMIFlags ( MIFlags ) ; } return ; } } while ( NumBytes ) { unsigned ThisVal = NumBytes ; unsigned Opc = <NUM_LIT> ; if ( DestReg == <STR_LIT> && BaseReg != <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , DestReg ) . addReg ( BaseReg ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; BaseReg = <STR_LIT> ; continue ; } assert ( ( DestReg != <STR_LIT> || BaseReg == <STR_LIT> ) && <STR_LIT> ) ; if ( ( DestReg == <STR_LIT> ) && ( ThisVal < ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ) { assert ( ( ThisVal & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) . addReg ( BaseReg ) . addImm ( ThisVal / <NUM_LIT> ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; break ; } bool HasCCOut = true ; int ImmIsT2SO = <STR_LIT> ( ThisVal ) ; Opc = isSub ? <STR_LIT> : <STR_LIT> ; if ( ImmIsT2SO != - <NUM_LIT> ) { NumBytes = <NUM_LIT> ; } else if ( ThisVal < <NUM_LIT> ) { Opc = isSub ? <STR_LIT> : <STR_LIT> ; HasCCOut = false ; NumBytes = <NUM_LIT> ;


<s> <ISA_LIT>OpenCLImageTypeLoweringPass ( ) : ModulePass ( ID ) {


<s> MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> void <ISA_LIT>InstPrinter :: printVectorListFourSpaced ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {

O << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> << getRegisterName ( MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) << <STR_LIT> ;


<s> if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getNode ( ) == Op1 . getNode ( ) && Op0 . getResNo ( ) == <NUM_LIT> && Op1 . getResNo ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ;


<s> if ( ! Ty -> isFloatTy ( ) && ( ! Subtarget -> hasGFX90AInsts ( ) || ! Ty -> isDoubleTy ( ) ) ) return AtomicExpansionKind :: CmpXChg ; unsigned AS = RMW -> getPointerAddressSpace ( ) ; if ( ( AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ) && Subtarget -> hasAtomicFaddInsts ( ) ) { if ( RMW -> getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) != <STR_LIT> ) return AtomicExpansionKind :: CmpXChg ; if ( Subtarget -> hasGFX90AInsts ( ) ) { if ( Ty -> isFloatTy ( ) && AS == <ISA_LIT>AS :: FLAT_ADDRESS ) return AtomicExpansionKind :: CmpXChg ; auto S<ISA_LIT>D = RMW -> getSyncScopeID ( ) ; if ( S<ISA_LIT>D == SyncScope :: System || S<ISA_LIT>D == RMW -> getContext ( ) . getOrInsertSyncScopeID ( <STR_LIT> ) ) return AtomicExpansionKind :: CmpXChg ;


<s> MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; auto CCFunction = CCAssignFnForReturn ( CallConv ) ; CCInfo . AnalyzeReturn ( Outs , CCFunction ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned e = RVLocs . size ( ) ; if ( e > <NUM_LIT> ) { std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ; } SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ;

RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


<s> if ( Subtarget . is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue OffsetSlot = DAG . getMemBasePlusOffset ( StackSlot , <NUM_LIT> , dl ) ; SDValue Store1 = DAG . getStore ( Chain , dl , Src , StackSlot , MachinePointerInfo ( ) ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) ) ; std :: pair < SDValue , SDValue > Tmp = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; if ( IsStrict ) return DAG . getMergeValues ( { Tmp . first , Tmp . second } , dl ) ; return Tmp . first ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue ValueToStore = Src ; if ( isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && ! Subtarget . is64Bit ( ) ) { ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; } SDValue Store = DAG . getStore ( Chain , dl , ValueToStore , StackSlot , MachinePointerInfo ( ) ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; Chain = Fild . getValue ( <NUM_LIT> ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( OpNo ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , PtrVT ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue Offset = DAG . getSelect ( dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , FudgePtr , Offset ) ;

SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , FudgePtr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) , <STR_LIT> , <NUM_LIT> ) ;


<s> pat = gen_rtx_CONST ( SImode , gen_rtx_PLUS ( Pmode , pat , GEN_INT ( - <NUM_LIT> ) ) ) ; emit_insn ( gen_lo_sum ( pic_offset_table_rtx , pic_offset_table_rtx , pat ) ) ; emit_insn ( gen_add_pc ( pic_offset_table_rtx , pic_offset_table_rtx ) ) ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & outputStream ) {


<s> return ( ( qword ) ( vec_unpackh ( vec_perm ( av , av , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) ) ) ;


<s> auto MIB = BuildMI ( * SetCCI . getParent ( ) , SetCCI . getIterator ( ) , SetCCI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; for ( int i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( SetCCI . getOperand ( i ) ) ; MIB . addReg ( CondReg ) ; MIB . setMemRefs ( SetCCI . memoperands ( ) ) ;


<s> BlockToRegSet Kill ; initReachingDef ( MF , ColorOpToReachedUses , Gen , Kill , ReachableUses , RegToId , DummyOp , ADRPMode ) ; if ( ! DummyOp ) reachingDefAlgorithm ( MF , ColorOpToReachedUses , In , Out , Gen , Kill , ReachableUses , RegToId . size ( ) ) ; finitReachingDef ( In , Out , Gen , ReachableUses ) ;


<s> <ISA_LIT>ProgramInfo ( ) : NumSGPR ( <NUM_LIT> ) , NumVGPR ( <NUM_LIT> ) {


<s> dbgs ( ) << <STR_LIT> << getLoopDepth ( ContLoop ) << <STR_LIT> << getLoopDepth ( ContingLoop ) << <STR_LIT> ; ) ; settleLoopcontBlock ( ContingMBB , ContMBB ) ;


<s> enum aarch64_parse_opt_result parse_res = aarch64_parse_arch ( str , & tmp_arch , & aarch64_isa_flags , & invalid_extension ) ; if ( parse_res == AARCH64_PARSE_OK ) { gcc_assert ( tmp_arch ) ; selected_arch = tmp_arch ; explicit_arch = selected_arch -> arch ; return true ; } switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> ) ; break ; case AARCH64_PARSE_INVALID_ARG : error ( <STR_LIT> , str ) ; aarch64_print_hint_for_arch ( str ) ; break ; case AARCH64_PARSE_INVALID_FEATURE : error ( <STR_LIT> <STR_LIT> , invalid_extension . c_str ( ) , str ) ; aarch64_print_hint_for_extensions ( invalid_extension ) ; break ; default : gcc_unreachable ( ) ; }


<s> MachineBasicBlock :: iterator At = FP . SplitB -> getFirstTerminator ( ) ; predicateBlockNB ( FP . SplitB , At , FP . FalseB , FP . PredR , false ) ; } MachineBasicBlock * SSB = <NUM_LIT> ; FP . SplitB -> erase ( OldTI , FP . SplitB -> end ( ) ) ; while ( FP . SplitB -> succ_size ( ) > <NUM_LIT> ) { MachineBasicBlock * T = * FP . SplitB -> succ_begin ( ) ; if ( T != FP . TrueB && T != FP . FalseB ) { assert ( ! SSB ) ; SSB = T ; } FP . SplitB -> removeSuccessor ( FP . SplitB -> succ_begin ( ) ) ; } if ( FP . JoinB ) { assert ( ! SSB || SSB == FP . JoinB ) ; BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addMBB ( FP . JoinB ) ; FP . SplitB -> addSuccessor ( FP . JoinB ) ; } else { bool HasBranch = false ; if ( TSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addReg ( FP . PredR ) . addMBB ( TSB ) ; FP . SplitB -> addSuccessor ( TSB ) ; HasBranch = true ; } if ( FSB ) { const MCInstrDesc & D = HasBranch ? HII -> get ( <STR_LIT> ) : HII -> get ( <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , D ) ; if ( ! HasBranch ) MIB . addReg ( FP . PredR ) ; MIB . addMBB ( FSB ) ; FP . SplitB -> addSuccessor ( FSB ) ; } if ( SSB ) { BuildMI ( * FP . SplitB , FP . SplitB -> end ( ) , DL , HII -> get ( <STR_LIT> ) ) . addMBB ( SSB ) ; FP . SplitB -> addSuccessor ( SSB ) ; } } if ( FP . JoinB ) { updatePhiNodes ( FP . JoinB , FP ) ; } else {

if ( TSB ) updatePhiNodes ( TSB , FP ) ;


<s> return Kind == Immediate && isUInt < <NUM_LIT> > ( getImm ( ) ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: fpga32 , false > X ( The<ISA_LIT>32Target , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;

RegisterTarget < Triple :: fpga64 , false > Y ( The<ISA_LIT>64Target , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> if ( MFI -> getLocalFrameSize ( ) < <NUM_LIT> ) return false ; return true ; }


<s> if ( VT . getVectorNumElements ( ) != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> , e = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i + <NUM_LIT> ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( Op -> getMaskElt ( i ) , i + <NUM_LIT> ) ) return false ;


<s> case MachineOperand :: MO_Register : { if ( MO . isImplicit ( ) ) continue ; const <ISA_LIT>FunctionInfo & MFI = * MI -> getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned WAReg = MFI . getWAReg ( MO . getReg ( ) ) ; MCOp = MCOperand :: createReg ( WAReg ) ; break ; } case MachineOperand :: MO_Immediate : { unsigned DescIndex = I - NumVariadicDefs ; if ( DescIndex < Desc . NumOperands ) { const MCOperandInfo & Info = Desc . OpInfo [ DescIndex ] ; if ( Info . OperandType == <STR_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Returns ; SmallVector < <STR_LIT> , <NUM_LIT> > Params ; const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; for ( const MachineOperand & MO : MI -> defs ( ) ) Returns . push_back ( getType ( MRI . getRegClass ( MO . getReg ( ) ) ) ) ; for ( const MachineOperand & MO : MI -> explicit_uses ( ) ) if ( MO . isReg ( ) ) Params . push_back ( getType ( MRI . getRegClass ( MO . getReg ( ) ) ) ) ; if ( <STR_LIT> ( MI -> getOpcode ( ) ) ) Params . pop_back ( ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) getFunctionReturns ( MI , Returns ) ; MCOp = lowerTypeIndexOperand ( std :: move ( Returns ) , std :: move ( Params ) ) ; break ; } else if ( Info . OperandType == <STR_LIT> ) { auto BT = static_cast < <STR_LIT> > ( MO . getImm ( ) ) ; assert ( BT != <STR_LIT> :: Invalid ) ; if ( BT == <STR_LIT> :: Multivalue ) { SmallVector < <STR_LIT> , <NUM_LIT> > Returns ; getFunctionReturns ( MI , Returns ) ; MCOp = lowerTypeIndexOperand ( std :: move ( Returns ) , SmallVector < <STR_LIT> , <NUM_LIT> > ( ) ) ; break ; } } } MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ;


<s> Ops . push_back ( Chain ) ; return CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; } SDValue V0 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V1 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V2 = N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue V3 = ( NumVecs == <NUM_LIT> ) ? SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , VT ) , <NUM_LIT> ) : N -> getOperand ( <NUM_LIT> + <NUM_LIT> ) ; SDValue RegSeq = SDValue ( QuadQRegs ( <STR_LIT> , V0 , V1 , V2 , V3 ) , <NUM_LIT> ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( RegSeq ) ; Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; unsigned Opc = QOpcodes0 [ OpcodeIndex ] ; SDNode * VStA = CurDAG -> getMachineNode ( Opc , dl , MemAddr . getValueType ( ) , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; Chain = SDValue ( VStA , <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = SDValue ( VStA , <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = Chain ; Opc = QOpcodes1 [ OpcodeIndex ] ; SDNode * VStB = CurDAG -> getMachineNode ( Opc , dl , MemAddr . getValueType ( ) , <STR_LIT> , Ops . data ( ) , <NUM_LIT> ) ; Chain = SDValue ( VStB , <NUM_LIT> ) ;

ReplaceUses ( SDValue ( N , <NUM_LIT> ) , Chain ) ;


<s> static void EmitComment ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc dl , const <ISA_LIT>ompactInstrInfo & TII , std :: string Comment ) { MDNode * CommentMDNode = MDNode :: get ( getGlobalContext ( ) , ArrayRef < Value * > ( MDString :: get ( getGlobalContext ( ) , Comment ) ) ) ;

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addMetadata ( CommentMDNode ) ;


<s> CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ;

* cum = ( ROUND_REG ( * cum , mode ) + ( int ) named * mcore_num_arg_regs ( mode , type ) ) ;


<s> return __builtin_neon_vcvts_nv4hi ( __a , __b ) ;


<s> Data64bitsDirective = nullptr ; ZeroDirective = <STR_LIT> ; CommentString = <STR_LIT> ; LCOMMDirectiveAlignmentType = LCOMM :: ByteAlignment ; InlineAsmStart = <STR_LIT> ; InlineAsmEnd = <STR_LIT> ; ZeroDirective = <STR_LIT> ; AscizDirective = <STR_LIT> ; SupportsDebugInformation = true ; MinInstAlignment = <NUM_LIT> ; UsesELFSectionDirectiveForBSS = true ;

ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> } else { operands [ <NUM_LIT> ] = force_reg ( SImode , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = gen_lowpart_SUBREG ( mode , operands [ <NUM_LIT> ] ) ; } } } if ( ! ( reload_in_progress | reload_completed ) && ! xtensa_valid_move ( mode , operands ) ) operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ;

operands [ <NUM_LIT> ] = xtensa_copy_incoming_a7 ( operands [ <NUM_LIT> ] ) ;


<s> use_pblendvb : for ( i = <NUM_LIT> ; i < nelt ; ++ i ) rperm [ i ] = ( d -> perm [ i ] < nelt ? const0_rtx : constm1_rtx ) ; finish_pblendvb : vperm = gen_rtx_CONST_VECTOR ( vmode , gen_rtvec_v ( nelt , rperm ) ) ; vperm = force_reg ( vmode , vperm ) ; if ( GET_MODE_SIZE ( vmode ) == <NUM_LIT> ) emit_insn ( gen_sse4_1_pblendvb ( target , op0 , op1 , vperm ) ) ; else emit_insn ( gen_avx2_pblendvb ( target , op0 , op1 , vperm ) ) ; if ( target != d -> target ) emit_move_insn ( d -> target , gen_lowpart ( d -> vmode , target ) ) ; return true ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V8HImode ; do_subreg : target = gen_reg_rtx ( vmode ) ; op0 = gen_lowpart ( vmode , op0 ) ; op1 = gen_lowpart ( vmode , op1 ) ; break ; case V32QImode : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) goto use_pblendvb ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) break ; if ( i < <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) goto use_pblendvb ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V16HImode ; goto do_subreg ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) mask |= ( d -> perm [ i * <NUM_LIT> ] >= <NUM_LIT> ) << i ; vmode = V8SImode ; goto do_subreg ; case V16HImode : for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i += <NUM_LIT> ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) break ; if ( i < <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( d -> perm [ i ] + <NUM_LIT> != d -> perm [ i + <NUM_LIT> ] ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) rperm [ i ] = ( d -> perm [ i / <NUM_LIT> ] < <NUM_LIT> ? const0_rtx : constm1_rtx ) ;


<s> void <ISA_LIT>IRDecorator :: DropAllReferences ( User * V ) { for ( Use & U : V -> operands ( ) ) { if ( isa < ConstantExpr > ( U . get ( ) ) ) DropAllReferences ( cast < User > ( U . get ( ) ) ) ;


<s> } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , DL , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , DL , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; MachineMemOperand * MMO = cast < AtomicSDNode > ( Op ) -> getMemOperand ( ) ; SDValue Result = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , T , MMO ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , DL , Reg , T , Result . getValue ( <NUM_LIT> ) ) ; SDValue EFLAGS = DAG . getCopyFromReg ( cpOut . getValue ( <NUM_LIT> ) , DL , <STR_LIT> , <STR_LIT> , cpOut . getValue ( <NUM_LIT> ) ) ;

SDValue Success = DAG . getNode ( <STR_LIT> , DL , Op -> getValueType ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , EFLAGS ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( CoprocOption . Val ) ) ;


<s> const <ISA_LIT>Subtarget & ST = Func . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! ST . LEAusesAG ( ) && ! ST . slowLEA ( ) ) return false ;


<s> bool hasStdExtZvamo ( ) const { return HasStdExtZvamo ;


<s> if ( ! isDarwin ( ) ) { if ( IDVal == <STR_LIT> ) return ParseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveTC ( is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> , DirectiveID . getLoc ( ) ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveMachine ( DirectiveID . getLoc ( ) ) ; } else { if ( IDVal == <STR_LIT> ) return ParseDarwinDirectiveMachine ( DirectiveID . getLoc ( ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ; int64_t Val = ~ MCE -> getValue ( ) & <NUM_LIT> ; uint64_t encoding = <STR_LIT> ( Val , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( encoding ) ) ;


<s> if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , OS ) ) return false ; if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_Register : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; default : break ; }


<s> bool PolynomialMultiplyRecognize :: highBitsAreZero ( Value * V , unsigned IterCount ) { auto * T = dyn_cast < IntegerType > ( V -> getType ( ) ) ; if ( ! T ) return false ; unsigned BW = T -> getBitWidth ( ) ; APInt K0 ( BW , <NUM_LIT> ) , K1 ( BW , <NUM_LIT> ) ; computeKnownBits ( V , K0 , K1 , DL ) ; return K0 . countLeadingOnes ( ) >= IterCount ;


<s> void Reset ( ) { TentativelyCommuting = false ;


<s> if ( Res != MatchOperand_Success ) return Res ; if ( ParseSuffix && Kind . empty ( ) ) return MatchOperand_NoMatch ; const auto & KindRes = parseVectorKind ( Kind , RegKind :: SVEDataVector ) ; if ( ! KindRes ) return MatchOperand_NoMatch ; unsigned ElementWidth = KindRes -> second ; if ( ! ParseShiftExtend || getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateVectorReg ( RegNum , RegKind :: SVEDataVector , ElementWidth , S , S , getContext ( ) ) ) ; return MatchOperand_Success ; }


<s> if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ;

if ( Op . getResNo ( ) == <NUM_LIT> && Opc == <STR_LIT> ) return true ;


<s> bool isSSrcF64 ( ) const { return isSCSrcB64 ( ) || isLiteralImm ( <STR_LIT> ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , false ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Argument . getValue ( <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , CPAddr ) ; } else { unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Argument = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Argument ) ; Argument = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Argument , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; Chain = Argument . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; Argument = DAG . getNode ( <STR_LIT> , dl , PtrVT , Argument , PICLabel ) ; } ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ;

Entry . Ty = ( Type * ) Type :: getInt32Ty ( * DAG . getContext ( ) ) ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; auto LoopHeadMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto LoopTailMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; auto DoneMBB = MF -> CreateMachineBasicBlock ( MBB . getBasicBlock ( ) ) ; MF -> insert ( ++ MBB . getIterator ( ) , LoopHeadMBB ) ; MF -> insert ( ++ LoopHeadMBB -> getIterator ( ) , LoopTailMBB ) ; MF -> insert ( ++ LoopTailMBB -> getIterator ( ) , DoneMBB ) ; LoopHeadMBB -> addSuccessor ( LoopTailMBB ) ; LoopHeadMBB -> addSuccessor ( DoneMBB ) ; LoopTailMBB -> addSuccessor ( DoneMBB ) ; LoopTailMBB -> addSuccessor ( LoopHeadMBB ) ; DoneMBB -> splice ( DoneMBB -> end ( ) , & MBB , MI , MBB . end ( ) ) ; DoneMBB -> transferSuccessors ( & MBB ) ; MBB . addSuccessor ( LoopHeadMBB ) ; Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register AddrReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register CmpValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NewValReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; AtomicOrdering Ordering = static_cast < AtomicOrdering > ( MI . getOperand ( IsMasked ? <NUM_LIT> : <NUM_LIT> ) . getImm ( ) ) ; if ( ! IsMasked ) { BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( PtrIsCap , Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( DestReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( getSCForRMW ( PtrIsCap , Ordering , Width ) ) , ScratchReg ) . addReg ( AddrReg ) . addReg ( NewValReg ) ; BuildMI ( LoopTailMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( <STR_LIT> ) . addMBB ( LoopHeadMBB ) ; } else { assert ( ! PtrIsCap && <STR_LIT> ) ; Register MaskReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( getLRForRMW ( false , Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( MaskReg ) ; BuildMI ( LoopHeadMBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( ScratchReg ) . addReg ( CmpValReg ) . addMBB ( DoneMBB ) ;

insertMaskedMerge ( TII , DL , LoopTailMBB , ScratchReg , DestReg , NewValReg , MaskReg , ScratchReg ) ;


<s> SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; bool Invert = false ; bool Shift = false ; bool Convert = true ; switch ( cast < ConstantSDNode > ( TargetCC ) -> getZExtValue ( ) ) { default : Convert = false ; break ; case <STR_LIT> : break ; case <STR_LIT> : Invert = true ; break ; case <STR_LIT> : if ( andCC ) { } else { Shift = true ; Invert = true ; } break ; case <STR_LIT> : Shift = true ; break ; } EVT VT = Op . getValueType ( ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , VT ) ; if ( Convert ) { SDValue SR = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , <STR_LIT> , Flag ) ; if ( Shift ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; if ( Invert ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; return SR ; } else { SDValue Zero = DAG . getConstant ( <NUM_LIT> , VT ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( One ) ; Ops . push_back ( Zero ) ; Ops . push_back ( TargetCC ) ; Ops . push_back ( Flag ) ; return DAG . getNode ( <STR_LIT> , dl , VTs , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ;


<s> static DecodeStatus DecodeGPR32RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> CCAssignFn * <ISA_LIT>Z80TargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC ) const { switch ( CC ) { default : return RetCC_<ISA_LIT>Z80 ;


<s> EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; case <STR_LIT> : EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ;


<s> unsigned SaveExecOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned XorTermOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; unsigned AndOpc = ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ; const auto * BoolXExecRC = TRI -> getRegClass ( <STR_LIT> ) ; MachineBasicBlock :: iterator I = LoopBB . begin ( ) ; SmallVector < Register , <NUM_LIT> > ReadlanePieces ; Register CondReg = <STR_LIT> ; Register VRsrc = Rsrc . getReg ( ) ; unsigned VRsrcUndef = getUndefRegState ( Rsrc . isUndef ( ) ) ; unsigned RegSize = TRI -> getRegSizeInBits ( Rsrc . getReg ( ) , MRI ) ; unsigned NumSubRegs = RegSize / <NUM_LIT> ; assert ( NumSubRegs % <NUM_LIT> == <NUM_LIT> && NumSubRegs <= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned Idx = <NUM_LIT> ; Idx < NumSubRegs ; Idx += <NUM_LIT> ) { Register CurRegLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; Register CurRegHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurRegLo ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx ) ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurRegHi ) . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx + <NUM_LIT> ) ) ; ReadlanePieces . push_back ( CurRegLo ) ; ReadlanePieces . push_back ( CurRegHi ) ; Register CurReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , CurReg ) . addReg ( CurRegLo ) . addImm ( <STR_LIT> ) . addReg ( CurRegHi ) . addImm ( <STR_LIT> ) ; Register NewCondReg = MRI . createVirtualRegister ( BoolXExecRC ) ; auto Cmp = BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , NewCondReg ) . addReg ( CurReg ) ; if ( NumSubRegs <= <NUM_LIT> ) Cmp . addReg ( VRsrc ) ; else Cmp . addReg ( VRsrc , VRsrcUndef , TRI -> getSubRegFromChannel ( Idx , <NUM_LIT> ) ) ; if ( CondReg == <STR_LIT> ) CondReg = NewCondReg ; else { Register AndReg = MRI . createVirtualRegister ( BoolXExecRC ) ; BuildMI ( LoopBB , I , DL , TII . get ( AndOpc ) , AndReg ) . addReg ( CondReg ) . addReg ( NewCondReg ) ; CondReg = AndReg ; } } auto SRsrcRC = TRI -> getEquivalentSGPRClass ( MRI . getRegClass ( VRsrc ) ) ; Register SRsrc = MRI . createVirtualRegister ( SRsrcRC ) ; auto Merge = BuildMI ( LoopBB , I , DL , TII . get ( <STR_LIT> ) , SRsrc ) ; unsigned Channel = <NUM_LIT> ; for ( Register Piece : ReadlanePieces ) { Merge . addReg ( Piece ) . addImm ( TRI -> getSubRegFromChannel ( Channel ++ ) ) ;


<s> else if ( GET_CODE ( vals ) == PARALLEL ) { for ( i = <NUM_LIT> ; i < n_elts ; ++ i ) { rtx x = XVECEXP ( vals , <NUM_LIT> , i ) ; if ( CONST_INT_P ( x ) || CONST_DOUBLE_P ( x ) ) n_const ++ ; } if ( n_const == n_elts ) const_vec = gen_rtx_CONST_VECTOR ( mode , XVEC ( vals , <NUM_LIT> ) ) ; } else gcc_unreachable ( ) ; if ( const_vec != NULL_RTX && aarch64_simd_valid_immediate ( const_vec , mode , false , NULL ) ) return const_vec ; else if ( ( const_dup = aarch64_simd_dup_constant ( vals ) ) != NULL_RTX ) return const_dup ; else if ( const_vec != NULL_RTX ) return const_vec ;


<s> virtual void markPhysRegUsed ( unsigned PhysReg ) override {

MIB . addDef ( PhysReg , RegState :: Implicit ) ;


<s> SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ( Subtarget -> hasSSE3 ( ) || Subtarget -> hasAVX ( ) ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) && isHorizontalBinOp ( LHS , RHS , false ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , LHS , RHS ) ; return SDValue ( ) ;


<s> return is<ISA_LIT> ( STI ) || isCI ( STI ) || isVI ( STI ) || isGFX9 ( STI ) ;


<s> Hi = Builder . CreateZExt ( Hi , ValTy , <STR_LIT> ) ; return Builder . CreateOr ( Lo , Builder . CreateShl ( Hi , ConstantInt :: get ( ValTy , <NUM_LIT> ) ) , <STR_LIT> ) ; } Type * Tys [ ] = { Addr -> getType ( ) } ; <STR_LIT> Int = IsAcquire ? <STR_LIT> : <STR_LIT> ; Function * Ldxr = <STR_LIT> ( M , Int , Tys ) ; Type * EltTy = cast < PointerType > ( Addr -> getType ( ) ) -> getElementType ( ) ; const DataLayout & DL = M -> getDataLayout ( ) ; IntegerType * IntEltTy = Builder . getIntNTy ( DL . getTypeSizeInBits ( EltTy ) ) ; Value * Trunc = Builder . CreateTrunc ( Builder . CreateCall ( Ldxr , Addr ) , IntEltTy ) ; return Builder . CreateBitCast ( Trunc , EltTy ) ;


<s> if ( FP ) { unsigned FramePtr = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( FramePtr ) ; } int FrameSize = MFI -> getStackSize ( ) ; assert ( FrameSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; FrameSize /= <NUM_LIT> ; bool isU6 = isImmU6 ( FrameSize ) ; if ( ! isU6 && ! isImmU16 ( FrameSize ) ) { report_fatal_error ( <STR_LIT> + Twine ( FrameSize ) ) ; } if ( FP ) { int FPSpillOffset = MFI -> getObjectOffset ( XFI -> getFPSpillSlot ( ) ) ; FPSpillOffset += FrameSize * <NUM_LIT> ; loadFromStack ( MBB , MBBI , <STR_LIT> , FPSpillOffset , dl , TII ) ; } bool restoreLR = XFI -> getUsesLR ( ) ; if ( restoreLR && ( FrameSize == <NUM_LIT> || MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) != <NUM_LIT> ) ) { int LRSpillOffset = MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) ; LRSpillOffset += FrameSize * <NUM_LIT> ; loadFromStack ( MBB , MBBI , <STR_LIT> , LRSpillOffset , dl , TII ) ; restoreLR = false ; } if ( FrameSize ) { if ( restoreLR ) { assert ( MFI -> getObjectOffset ( XFI -> getLRSpillSlot ( ) ) == <NUM_LIT> ) ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ; int Opcode = ( isU6 ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opcode ) ) . addImm ( FrameSize ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i < e ; ++ i ) MIB -> addOperand ( MBBI -> getOperand ( i ) ) ; MBB . erase ( MBBI ) ; } else { int Opcode = ( isU6 ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opcode ) , <STR_LIT> ) . addImm ( FrameSize ) ; }


<s> void addSIMDImmType10Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> static const char * const unwanted_chars = <STR_LIT> ; while ( string < string_end ) { if ( * string && ( unsigned char ) * string < <NUM_LIT> && ! ISCNTRL ( * string ) && strchr ( unwanted_chars , * string ) == NULL ) { fputc ( '"' , stream ) ; while ( * string && ( unsigned char ) * string < <NUM_LIT> && ! ISCNTRL ( * string ) && strchr ( unwanted_chars , * string ) == NULL && string < string_end ) { fputc ( * string , stream ) ; string ++ ; } fputc ( '"' , stream ) ;

if ( string < string_end ) fprintf ( stream , <STR_LIT> ) ;