<s> bool <ISA_LIT>AsmParser :: splitIdentifier ( OperandVector & Operands ) { AsmToken const & Token = getParser ( ) . getTok ( ) ; StringRef String = Token . getString ( ) ; SMLoc Loc = Token . getLoc ( ) ; getLexer ( ) . Lex ( ) ; do { std :: pair < StringRef , StringRef > HeadTail = String . split ( '.' ) ; if ( ! HeadTail . first . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( HeadTail . first , Loc ) ) ; if ( ! HeadTail . second . empty ( ) ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( String . substr ( HeadTail . first . size ( ) , <NUM_LIT> ) , Loc ) ) ; String = HeadTail . second ; } while ( ! String . empty ( ) ) ; return false ;


<s> ( * MI . memoperands_begin ( ) ) -> setFlags ( MOSuppressPair << MachineMemOperand :: MOTargetStartBit ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> :


<s> } else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ; } else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) { if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled ( MCB ) ; else return getParser ( ) . Error ( IDLoc , MemNoShuffMsg ) ; } else if ( Option . compare_lower ( <STR_LIT> ) == <NUM_LIT> ) { } else return getParser ( ) . Error ( IDLoc , llvm :: Twine ( <STR_LIT> ) + Option + <STR_LIT> ) ;


<s> use_rtx = extract_mac_non_acc_rtx ( consumer ) ; break ; case TYPE_DIV : if ( INSN_CODE ( consumer ) == CODE_FOR_divmodsi4 || INSN_CODE ( consumer ) == CODE_FOR_udivmodsi4 ) use_rtx = SET_SRC ( parallel_element ( consumer , <NUM_LIT> ) ) ; else use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; break ; case TYPE_MMU : if ( GET_CODE ( PATTERN ( consumer ) ) == SET ) use_rtx = SET_SRC ( PATTERN ( consumer ) ) ; else return true ; break ; case TYPE_LOAD : case TYPE_STORE : use_rtx = extract_mem_rtx ( consumer ) ; break ; case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : use_rtx = extract_base_reg ( consumer ) ; break ; case TYPE_BRANCH : use_rtx = PATTERN ( consumer ) ; break ; default :


<s> void assignValueToAddress ( unsigned ValVReg , unsigned Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override {


<s> if ( DTy ) { const DIType * ResolvedType = DTy -> getBaseType ( ) ; if ( ! ResolvedType ) BTFType . Type = <NUM_LIT> ; else BTFType . Type = BDebug . getTypeId ( ResolvedType ) ;


<s> else if ( this -> m_fpu_balance > <NUM_LIT> ) fprintf ( dump_file , <STR_LIT> <STR_LIT> , this -> m_fpu_balance ) ; else fprintf ( dump_file , <STR_LIT> <STR_LIT> , - this -> m_fpu_balance ) ; }


<s> void avr_asm_asm_output_aligned_bss ( FILE * file , tree decl , const char * name , unsigned HOST_WIDE_INT size , int align , void ( * default_func ) ( FILE * , tree , const char * , unsigned HOST_WIDE_INT , int ) ) { rtx mem = decl == NULL_TREE ? NULL_RTX : DECL_RTL ( decl ) ; rtx symbol ; if ( mem != NULL_RTX && MEM_P ( mem ) && SYMBOL_REF_P ( ( symbol = XEXP ( mem , <NUM_LIT> ) ) ) && ( SYMBOL_REF_FLAGS ( symbol ) & ( SYMBOL_FLAG_IO | SYMBOL_FLAG_ADDRESS ) ) ) { if ( ! ( SYMBOL_REF_FLAGS ( symbol ) & SYMBOL_FLAG_ADDRESS ) ) error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> , decl ) ; avr_asm_output_aligned_decl_common ( file , decl , name , size , align , false ) ;


<s> if ( Subtarget . hasZeroCycleZeroingGP ( ) ) { if ( Opcode == TargetOpcode :: COPY && ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) return true ; } if ( Subtarget . hasExynosCheapAsMoveHandling ( ) ) { if ( isExynosResetFast ( MI ) || isExynosShiftExtFast ( MI ) ) return true ; else return MI . isAsCheapAsAMove ( ) ; } switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> :


<s> AssemblerOptions . pop_back ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( AssemblerOptions . back ( ) -> getFeatures ( ) ) ) ; STI . setFeatureBits ( AssemblerOptions . back ( ) -> getFeatures ( ) ) ; getTargetStreamer ( ) . emitDirectiveSetPop ( ) ; return false ;


<s> static int vax_address_cost_1 ( rtx addr ) { int reg = <NUM_LIT> , indexed = <NUM_LIT> , indir = <NUM_LIT> , offset = <NUM_LIT> , predec = <NUM_LIT> ; rtx plus_op0 = <NUM_LIT> , plus_op1 = <NUM_LIT> ; restart : switch ( GET_CODE ( addr ) ) { case PRE_DEC : predec = <NUM_LIT> ; case REG : case SUBREG : case POST_INC : reg = <NUM_LIT> ; break ; case MULT : case ASHIFT : indexed = <NUM_LIT> ; break ; case CONST_INT : if ( offset == <NUM_LIT> ) offset = ( unsigned HOST_WIDE_INT ) ( INTVAL ( addr ) + <NUM_LIT> ) > <NUM_LIT> ; break ; case CONST : case SYMBOL_REF : offset = <NUM_LIT> ;


<s> if ( ConstraintCode . size ( ) == <NUM_LIT> ) { switch ( ConstraintCode [ <NUM_LIT> ] ) { default : break ; case 'Q' : return InlineAsm :: Constraint_Q ; case 'R' : return InlineAsm :: Constraint_R ; case 'S' : return InlineAsm :: Constraint_S ; case 'T' :


<s> R600InstrInfo :: R600InstrInfo ( const AMDGPUSubtarget & st ) : AMDGPUInstrInfo ( st ) , RI ( st ) {


<s> Constant * FSZero = Constant :: getNullValue ( LinkTy -> getPointerTo ( ) -> getPointerTo ( <NUM_LIT> ) ) ; Value * Next = Builder . CreateLoad ( LinkTy -> getPointerTo ( ) , FSZero ) ;

Builder . CreateStore ( Next , Builder . CreateStructGEP ( LinkTy , Link , <NUM_LIT> ) ) ;


<s> if ( VT == <STR_LIT> && ! Subtarget . hasStdExtZfh ( ) ) return false ; if ( VT == <STR_LIT> && ! Subtarget . hasStdExtF ( ) ) return false ;

if ( VT == <STR_LIT> && ! Subtarget . hasStdExtD ( ) ) return false ;


<s> if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ;


<s> static SDValue PerformVMOVDRRCombine ( SDNode * N , SelectionDAG & DAG ) { SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op0 . getNode ( ) == Op1 . getNode ( ) && Op0 . getResNo ( ) == <NUM_LIT> && Op1 . getResNo ( ) == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext & ctx ) : MCII ( mcii ) , STI ( sti ) , Ctx ( ctx ) {


<s> return riscv_secondary_memory_needed ( mode , from , to ) ? <NUM_LIT> : <NUM_LIT> ;


<s> if ( m2 == CC_NZVCmode ) { if ( m1 == CC_NZVCmode || m1 == CCmode ) return CC_NZVCmode ; return VOIDmode ; }


<s> const Triple & TT = TM . getTargetTriple ( ) ; StringRef CPU = <STR_LIT> ( TT , TM . getTargetCPU ( ) ) ; StringRef FS = TM . getTargetFeatureString ( ) ; const <ISA_LIT>TargetMachine & MTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; const <ISA_LIT>Subtarget STI ( TT , CPU , FS , MTM . isLittleEndian ( ) , MTM ) ; bool IsABICalls = STI . isABICalls ( ) ; const <ISA_LIT>ABIInfo & ABI = MTM . getABI ( ) ; if ( IsABICalls ) { TS . emitDirectiveAbiCalls ( ) ; Reloc :: Model RM = TM . getRelocationModel ( ) ; if ( RM == Reloc :: Static && ! ABI . IsN64 ( ) ) TS . emitDirectiveOptionPic0 ( ) ; } std :: string SectionName = std :: string ( <STR_LIT> ) + getCurrentABIString ( ) ; OutStreamer -> SwitchSection ( OutContext . getELFSection ( SectionName , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ; STI . isNaN2008 ( ) ? TS . emitDirectiveNaN2008 ( ) : TS . emitDirectiveNaNLegacy ( ) ; if ( ABI . IsEABI ( ) ) { if ( STI . isGP32bit ( ) ) OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ;

else OutStreamer -> SwitchSection ( OutContext . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , <NUM_LIT> ) ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res ;


<s> const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ; if ( ST . device ( ) -> getGeneration ( ) <= <STR_LIT> ) { enablePass ( & MachineSchedulerID ) ; MachineSchedRegistry :: setDefault ( createR600MachineScheduler ) ; }


<s> const MCExpr * getMemOffset ( ) const {

assert ( ( Kind == k_MemoryRegRegImm || Kind == k_MemoryRegImmImm || Kind == k_MemoryZeroImmImm || Kind == k_MemoryZeroRegImm ) && <STR_LIT> ) ;


<s> } return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( * this , MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : case 'V' : if ( MO . isReg ( ) ) return printAsmMRegister ( * this , MO , ExtraCode [ <NUM_LIT> ] , O ) ; printOperand ( * this , MI , OpNo , O ) ; return false ; case 'P' : printPCRelImm ( * this , MI , OpNo , O ) ; return false ; case 'n' : if ( MO . isImm ( ) ) { O << - MO . getImm ( ) ; return false ; } O << '-' ; }


<s> unsigned BaseOp = <NUM_LIT> ; unsigned Cond = <NUM_LIT> ; SDLoc DL ( Op ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; }

SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ;


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const { return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> if ( ! Tok . is ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; StringRef RegName = Tok . getString ( ) ; unsigned Encoding = StringSwitch < unsigned > ( RegName . lower ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( Encoding == ~ <NUM_LIT> ) return MatchOperand_NoMatch ; Parser . Lex ( ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreateBankedReg ( Encoding , S ) ) ;


<s> SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , VT ) ; auto DivRemOpcode = OpcodeN0 == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue R = DAG . getNode ( DivRemOpcode , SDLoc ( N ) , NodeTys , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) ) ; DAG . ReplaceAllUsesOfValueWith ( N0 . getValue ( <NUM_LIT> ) , R . getValue ( <NUM_LIT> ) ) ; return R . getValue ( <NUM_LIT> ) ;


<s> HOST_WIDE_INT start = INTVAL ( ops [ <NUM_LIT> ] ) ; HOST_WIDE_INT align_mask ; rtx s0 , s1 , mask , r0 ; gcc_assert ( REG_P ( dst ) && GET_MODE ( dst ) == TImode ) ; if ( MEM_P ( src ) ) { align_mask = - MEM_ALIGN ( src ) ; if ( ( start & align_mask ) == ( ( start + width - <NUM_LIT> ) & align_mask ) ) { s0 = gen_reg_rtx ( TImode ) ; r0 = spu_expand_load ( s0 , <NUM_LIT> , src , start / <NUM_LIT> ) ; start &= <NUM_LIT> ; if ( r0 ) emit_insn ( gen_rotqby_ti ( s0 , s0 , r0 ) ) ; } else { s0 = gen_reg_rtx ( TImode ) ; s1 = gen_reg_rtx ( TImode ) ; r0 = spu_expand_load ( s0 , s1 , src , start / <NUM_LIT> ) ; start &= <NUM_LIT> ; gcc_assert ( start + width <= <NUM_LIT> ) ; if ( r0 ) { rtx r1 = gen_reg_rtx ( SImode ) ; mask = gen_reg_rtx ( TImode ) ; emit_move_insn ( mask , GEN_INT ( - <NUM_LIT> ) ) ; emit_insn ( gen_rotqby_ti ( s0 , s0 , r0 ) ) ; emit_insn ( gen_rotqby_ti ( s1 , s1 , r0 ) ) ; if ( GET_CODE ( r0 ) == CONST_INT ) r1 = GEN_INT ( INTVAL ( r0 ) & <NUM_LIT> ) ; else emit_insn ( gen_andsi3 ( r1 , r0 , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_shlqby_ti ( mask , mask , r1 ) ) ; emit_insn ( gen_selb ( s0 , s1 , s0 , mask ) ) ; } } } else if ( GET_CODE ( src ) == SUBREG ) { rtx r = SUBREG_REG ( src ) ; gcc_assert ( REG_P ( r ) && SCALAR_INT_MODE_P ( GET_MODE ( r ) ) ) ; s0 = gen_reg_rtx ( TImode ) ; if ( GET_MODE_SIZE ( GET_MODE ( r ) ) < GET_MODE_SIZE ( TImode ) ) emit_insn ( gen_rtx_SET ( s0 , gen_rtx_ZERO_EXTEND ( TImode , r ) ) ) ; else emit_move_insn ( s0 , src ) ; } else { gcc_assert ( REG_P ( src ) && GET_MODE ( src ) == TImode ) ;


<s> UnwindOpcodeStreamer ( SmallVectorImpl < uint8_t > & V ) : Vec ( V ) , Pos ( <NUM_LIT> ) {


<s> <ISA_LIT>CodeEmitter ( JITCodeEmitter & mce ) : MachineFunctionPass ( & ID ) , MCE ( mce ) {


<s> if ( Op . getOpcode ( ) == <STR_LIT> ) if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return true ;


<s> MCE . addRelocation ( MachineRelocation :: getBB ( MCE . getCurrentPCOffset ( ) , Reloc , BB ) ) ;


<s> static bool nios2_tls_symbol_p ( rtx x ) { return ( targetm . have_tls && GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ) ;


<s> if ( VT . is64BitVector ( ) || VT . is128BitVector ( ) ) return PerformVMULCombine ( N , DCI , Subtarget ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return SDValue ( ) ; int64_t MulAmt = C -> getSExtValue ( ) ; unsigned ShiftAmt = countTrailingZeros < uint64_t > ( MulAmt ) ; ShiftAmt = ShiftAmt & ( <NUM_LIT> - <NUM_LIT> ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( MulAmt >= <NUM_LIT> ) { if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , DL , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs - <NUM_LIT> ) , DL , <STR_LIT> ) ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Res ) ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _tzcnt_u64 ( unsigned long long __X ) {

return __builtin_ia32_tzcnt_u64 ( __X ) ;


<s> if ( ! Subtarget . hasAnyFMA ( ) ) return false ; VT = VT . getScalarType ( ) ; if ( ! VT . isSimple ( ) ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : return Subtarget . hasFP16 ( ) ; case <STR_LIT> : case <STR_LIT> : return true ; default : break ; }


<s> EVT LdVT = LoadNode -> getMemoryVT ( ) ; if ( LdVT != <STR_LIT> && LdVT != <STR_LIT> && LdVT != <STR_LIT> && LdVT != <STR_LIT> ) return false ; SDValue Undef = StoreNode -> getOffset ( ) ; if ( Undef -> getOpcode ( ) != <STR_LIT> ) return false ; if ( StoredVal . getResNo ( ) != <NUM_LIT> ) return false ; if ( ! StoredVal . getNode ( ) -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( ! LoadNode -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) return false ; if ( StoredVal -> getOperand ( <NUM_LIT> ) . getNode ( ) != LoadNode ) return false ; if ( StoreNode -> isNonTemporal ( ) ) return false ;

SDValue Address = StoreNode -> getBasePtr ( ) ;


<s> return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> if ( ret ) { int64_t c = dyn_cast < ConstantSDNode > ( O ) -> getSExtValue ( ) ;


<s> void <ISA_LIT>TargetStreamer :: emitArchExtension ( uint64_t ArchExt ) {


<s> unsigned NumRegPressureSets = getNumRegPressureSets ( ) ; SGPR32SetID = NumRegPressureSets ; VGPR32SetID = NumRegPressureSets ; for ( unsigned i = <NUM_LIT> ; i < NumRegPressureSets ; ++ i ) {

if ( strncmp ( <STR_LIT> , getRegPressureSetName ( i ) , <NUM_LIT> ) == <NUM_LIT> ) SGPR32SetID = i ;


<s> static void moxie_setup_incoming_varargs ( cumulative_args_t cum_v , const function_arg_info & , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int regno ; int regs = <NUM_LIT> - * cum ; * pretend_size = regs < <NUM_LIT> ? <NUM_LIT> : GET_MODE_SIZE ( SImode ) * regs ; if ( no_rtl ) return ; for ( regno = * cum ; regno < <NUM_LIT> ; regno ++ ) { rtx reg = gen_rtx_REG ( SImode , regno ) ; rtx slot = gen_rtx_PLUS ( Pmode , gen_rtx_REG ( SImode , ARG_POINTER_REGNUM ) , GEN_INT ( UNITS_PER_WORD * ( <NUM_LIT> + ( regno - <NUM_LIT> ) ) ) ) ; emit_move_insn ( gen_rtx_MEM ( SImode , slot ) , reg ) ; }


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {


<s> static bool rs6000_member_type_forces_blk ( const_tree field , machine_mode mode ) {

return ( ( TARGET_SPE && TREE_CODE ( TREE_TYPE ( field ) ) == VECTOR_TYPE ) || ( TARGET_E500_DOUBLE && mode == DFmode ) ) ;


<s> bool NoOpt = ( getOptLevel ( ) == CodeGenOpt :: None ) ; if ( ! NoOpt ) addPass ( create<ISA_LIT>NewValueJump ( ) ) ; addPass ( create<ISA_LIT>ExpandPredSpillCode ( TM ) ) ; addPass ( create<ISA_LIT>SplitTFRCondSets ( TM ) ) ; if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) ) ; addPass ( create<ISA_LIT>Packetizer ( ) ) ; } return false ;


<s> if ( Inst . getOpcode ( ) == <STR_LIT> ) Pos += <NUM_LIT> ; int Size ; if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) Size = ( int ) Insn - Pos + <NUM_LIT> ; else Size = ( int ) Insn - Pos + <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( SignExtend32 < <NUM_LIT> > ( Size ) ) ) ; return MCDisassembler :: Success ;


<s> Size = <NUM_LIT> ; return Result ; } uint32_t insn32 ; if ( ! readInstruction32 ( Bytes , Address , Size , insn32 ) ) { return Fail ; } Result = decodeInstruction ( DecoderTable32 , instr , insn32 , Address , this , STI ) ; if ( Result != Fail ) { Size = <NUM_LIT> ; return Result ;


<s> case SUBREG : fprintf ( file , <STR_LIT> , reg_names [ true_regnum ( addr ) ] ) ; break ; case PLUS : { rtx x = XEXP ( addr , <NUM_LIT> ) , y = XEXP ( addr , <NUM_LIT> ) ; switch ( GET_CODE ( x ) ) { case REG : case SUBREG : if ( CONST_INT_P ( y ) ) { unsigned int regno = true_regnum ( x ) ; HOST_WIDE_INT val = INTVAL ( y ) ;


<s> DominatorTreeWrapperPass * const DTW = getAnalysisIfAvailable < DominatorTreeWrapperPass > ( ) ; DT = DTW ? & DTW -> getDomTree ( ) : nullptr ; const TargetPassConfig & TPC = getAnalysis < TargetPassConfig > ( ) ; const TargetMachine & TM = TPC . getTM < TargetMachine > ( ) ; ST = & TM . getSubtarget < GCNSubtarget > ( F ) ; IsPixelShader = F . getCallingConv ( ) == CallingConv :: <ISA_LIT>_PS ;


<s> if ( TARGET_64BIT ) { output_asm_insn ( <STR_LIT> , & frame_size ) ; output_asm_insn ( <STR_LIT> , & args_size ) ; output_asm_insn ( <STR_LIT> , ops ) ; } else { output_asm_insn ( <STR_LIT> , & frame_size ) ; output_asm_insn ( <STR_LIT> , & args_size ) ;


<s> if ( ! Flags . isSRet ( ) ) return NotStructReturn ;

if ( Flags . isInReg ( ) ) return RegStructReturn ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) {

return new ELF<ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( ) ) ;


<s> static bool nds32_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) {

return ( ! TARGET_V3PUSH && ! nds32_isr_function_p ( current_function_decl ) && ( cfun -> machine -> va_args_size == <NUM_LIT> ) && decl && ! flag_pic ) ;


<s> static void def_builtin ( int mask , const char * name , tree type , int code ) { if ( mask & target_flags ) { if ( rs6000_builtin_decls [ code ] ) abort ( ) ; rs6000_builtin_decls [ code ] = lang_hooks . builtin_function ( name , type , code , BUILT_IN_MD , NULL , NULL_TREE ) ; }


<s> if ( GET_CODE ( op ) != MEM ) return FALSE ; addr = XEXP ( op , <NUM_LIT> ) ;

return frv_legitimate_address_p_1 ( mode , addr , reload_completed , TRUE , FALSE ) ;


<s> static SDValue getOnesVector ( EVT VT , SelectionDAG & DAG , const SDLoc & dl ) { assert ( ( VT . is128BitVector ( ) || VT . is256BitVector ( ) || VT . is512BitVector ( ) ) && <STR_LIT> ) ;

APInt Ones = APInt :: getAllOnesValue ( <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT ; switch ( Intrinsic ) { case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; default : VT = <STR_LIT> ; break ; } Info . opc = <STR_LIT> ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = - VT . getStoreSize ( ) + <NUM_LIT> ; Info . size = <NUM_LIT> * VT . getStoreSize ( ) - <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } default : break ; }


<s> <STR_LIT> SOpc = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; unsigned SBits = <NUM_LIT> ; switch ( SOpc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : SBits = <NUM_LIT> ; break ; case <STR_LIT> : Binary |= <NUM_LIT> ; return Binary ; } Binary |= SBits << <NUM_LIT> ;

unsigned Offset = <STR_LIT> ( MO1 . getImm ( ) ) ;


<s> } uint64_t NumNops = Count / <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != NumNops ; ++ i ) OW -> Write32 ( <NUM_LIT> ) ; switch ( Count % <NUM_LIT> ) { default : break ; case <NUM_LIT> : OW -> Write8 ( <NUM_LIT> ) ; break ; case <NUM_LIT> : OW -> Write16 ( <NUM_LIT> ) ; break ;

case <NUM_LIT> : OW -> Write16 ( <NUM_LIT> ) ; OW -> Write8 ( <NUM_LIT> ) ; break ;


<s> if ( tryParseRegister ( RegNo , StartLoc , EndLoc ) != MatchOperand_Success ) return Error ( StartLoc , <STR_LIT> ) ;


<s> void addUImm7Operands ( MCInst & Inst , unsigned N ) const {


<s> assert ( Section && <STR_LIT> ) ; if ( Section -> useCodeAlign ( ) ) getStreamer ( ) . emitCodeAlignment ( <NUM_LIT> , & getSTI ( ) , <NUM_LIT> ) ;

else getStreamer ( ) . emitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( SrcEltTy . bitsLT ( SmallestEltTy ) ) SmallestEltTy = SrcEltTy ; } unsigned ResMultiplier = VT . getScalarSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; NumElts = VT . getSizeInBits ( ) / SmallestEltTy . getSizeInBits ( ) ; EVT ShuffleVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SmallestEltTy , NumElts ) ; for ( auto & Src : Sources ) { EVT SrcVT = Src . ShuffleVec . getValueType ( ) ; if ( SrcVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) continue ; EVT EltVT = SrcVT . getVectorElementType ( ) ; unsigned NumSrcElts = VT . getSizeInBits ( ) / EltVT . getSizeInBits ( ) ; EVT DestVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumSrcElts ) ; if ( SrcVT . getSizeInBits ( ) < VT . getSizeInBits ( ) ) { if ( <NUM_LIT> * SrcVT . getSizeInBits ( ) != VT . getSizeInBits ( ) ) return SDValue ( ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getUNDEF ( Src . ShuffleVec . getValueType ( ) ) ) ; continue ; } if ( SrcVT . getSizeInBits ( ) != <NUM_LIT> * VT . getSizeInBits ( ) ) return SDValue ( ) ; if ( Src . MaxElt - Src . MinElt >= NumSrcElts ) { return SDValue ( ) ; } if ( Src . MinElt >= NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( NumSrcElts , dl , <STR_LIT> ) ) ; Src . WindowBase = - NumSrcElts ; } else if ( Src . MaxElt < NumSrcElts ) { Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } else { SDValue VEXTSrc1 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue VEXTSrc2 = DAG . getNode ( <STR_LIT> , dl , DestVT , Src . ShuffleVec , DAG . getConstant ( NumSrcElts , dl , <STR_LIT> ) ) ; Src . ShuffleVec = DAG . getNode ( <STR_LIT> , dl , DestVT , VEXTSrc1 , VEXTSrc2 , DAG . getConstant ( Src . MinElt , dl , <STR_LIT> ) ) ; Src . WindowBase = - Src . MinElt ; }


<s> auto const & ST = MIRBuilder . getMF ( ) . getSubtarget < GCNSubtarget > ( ) ; unsigned ReturnOpc = IsShader ? <STR_LIT> : <STR_LIT> ; auto Ret = MIRBuilder . buildInstrNoInsert ( ReturnOpc ) ; Register ReturnAddrVReg ; if ( ReturnOpc == <STR_LIT> ) { ReturnAddrVReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; Ret . addUse ( ReturnAddrVReg ) ; } if ( ! lowerReturnVal ( MIRBuilder , Val , VRegs , Ret ) ) return false ; if ( ReturnOpc == <STR_LIT> ) { const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ;

Register LiveInReturn = MF . addLiveIn ( TRI -> getReturnAddressReg ( MF ) , & <STR_LIT> ) ;


<s> <ISA_LIT>PostRAScheduler ( ) : MachineFunctionPass ( ID ) {

initialize<ISA_LIT>PostRASchedulerPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> O << <STR_LIT> << KCacheBank << ':' ; int KCacheAddr = MI -> getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; int LineSize = ( KCacheMode == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; O << KCacheAddr * <NUM_LIT> << '-' << KCacheAddr * <NUM_LIT> + LineSize ; }


<s> if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;

Inst . addOperand ( MCOperand :: createReg ( Base ) ) ;


<s> case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ;

case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ;


<s> return Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> Base = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) ? CurDAG -> getTargetFrameIndex ( AM . Base . FrameIndex , TLI . getPointerTy ( ) ) : AM . Base . Reg ; Scale = getI8Imm ( AM . Scale ) ; Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ;

else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ;


<s> case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL : FixupKind = <STR_LIT> ; RelaxCandidate = true ; break ; } } else if ( Kind == MCExpr :: SymbolRef && cast < MCSymbolRefExpr > ( Expr ) -> getKind ( ) == MCSymbolRefExpr :: VK_None ) { if ( Desc . getOpcode ( ) == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } else if ( MIFrm == <STR_LIT> ) { FixupKind = <STR_LIT> ; } } assert ( FixupKind != <STR_LIT> && <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) , MI . getLoc ( ) ) ) ; ++ MCNumFixups ; if ( EnableRelax && RelaxCandidate ) { const MCConstantExpr * Dummy = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ;

Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Dummy , MCFixupKind ( <STR_LIT> ) , MI . getLoc ( ) ) ) ;


<s> return __builtin_mve_vornq_m_sv4si ( __arm_vuninitializedq_s32 ( ) , __a , __b , __p ) ;


<s> <ISA_LIT>CallFrameInformation ( ) : MachineFunctionPass ( ID ) {

PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ;


<s> emit_move_insn ( isr_reg_rtx , isr_mem_rtx ) ; emit_move_insn ( isr_msr_rtx , isr_reg_rtx ) ; emit_insn ( gen_rtx_USE ( SImode , isr_reg_rtx ) ) ; emit_insn ( gen_rtx_USE ( SImode , isr_msr_rtx ) ) ; } for ( regno = GP_REG_FIRST ; regno <= GP_REG_LAST ; regno ++ ) { if ( BITSET_P ( mask , regno - GP_REG_FIRST ) ) { if ( regno == MB_ABI_SUB_RETURN_ADDR_REGNUM ) continue ; reg_rtx = gen_rtx_REG ( SImode , regno ) ; insn = gen_rtx_PLUS ( Pmode , base_reg_rtx , GEN_INT ( gp_offset ) ) ; mem_rtx = gen_rtx_MEM ( SImode , insn ) ; if ( microblaze_is_interrupt_variant ( ) || save_volatiles ) MEM_VOLATILE_P ( mem_rtx ) = <NUM_LIT> ; if ( prologue ) { insn = emit_move_insn ( mem_rtx , reg_rtx ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else { insn = emit_move_insn ( reg_rtx , mem_rtx ) ; } gp_offset += GET_MODE_SIZE ( SImode ) ; } } if ( microblaze_is_interrupt_variant ( ) && prologue ) {


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenInstrInfo ( - <NUM_LIT> , - <NUM_LIT> ) , ST ( ST ) {


<s> switch ( Size ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : ldrOpc = <STR_LIT> ; strOpc = <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = <STR_LIT> ; strOpc = <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = <STR_LIT> ; strOpc = <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = <STR_LIT> ; strOpc = <STR_LIT> ;


<s> O << <STR_LIT> ; printMemReference ( MI , OpNo ) ;


<s> int JTIdx = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; auto & JTInfo = * MF -> getJumpTableInfo ( ) ; const MachineJumpTableEntry & JT = JTInfo . getJumpTables ( ) [ JTIdx ] ; if ( JT . MBBs . empty ( ) ) return false ; int MaxOffset = std :: numeric_limits < int > :: min ( ) , MinOffset = std :: numeric_limits < int > :: max ( ) ; MachineBasicBlock * MinBlock = nullptr ; for ( auto Block : JT . MBBs ) { int BlockOffset = BlockInfo [ Block -> getNumber ( ) ] ; assert ( BlockOffset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; MaxOffset = std :: max ( MaxOffset , BlockOffset ) ; if ( BlockOffset <= MinOffset ) { MinOffset = BlockOffset ; MinBlock = Block ; } } assert ( MinBlock && <STR_LIT> ) ; if ( ! isInt < <NUM_LIT> > ( MinOffset - Offset ) ) { ++ NumJT32 ; return false ; } int Span = MaxOffset - MinOffset ; auto AFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( isUInt < <NUM_LIT> > ( Span / <NUM_LIT> ) ) { AFI -> setJumpTableEntryInfo ( JTIdx , <NUM_LIT> , MinBlock -> getSymbol ( ) ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; ++ NumJT8 ; return true ; } else if ( isUInt < <NUM_LIT> > ( Span / <NUM_LIT> ) ) { AFI -> setJumpTableEntryInfo ( JTIdx , <NUM_LIT> , MinBlock -> getSymbol ( ) ) ; MI . setDesc ( TII -> get ( <STR_LIT> ) ) ; ++ NumJT16 ;


<s> static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; addImplySP ( Inst , Address , Decoder ) ;

Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) ) ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; unsigned Rn = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ;

unsigned imm = fieldFromInstruction ( Val , <NUM_LIT> , <NUM_LIT> ) ;


<s> void addRegWithInputModsOperands ( MCInst & Inst , unsigned N ) const {

Inst . addOperand ( MCOperand :: createImm ( Reg . Modifiers == - <NUM_LIT> ? <NUM_LIT> : Reg . Modifiers ) ) ;


<s> width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned hwReg = RI -> getEncodingValue ( reg ) & <NUM_LIT> ; unsigned maxUsed = hwReg + width - <NUM_LIT> ; if ( isSGPR ) { MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR ; } else { MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR ; } } } } unsigned ExtraSGPRs = <NUM_LIT> ; if ( VCCUsed ) ExtraSGPRs = <NUM_LIT> ; if ( STM . getGeneration ( ) < <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( FlatUsed ) ExtraSGPRs = <NUM_LIT> ; } else { if ( STM . isXNACKEnabled ( ) ) ExtraSGPRs = <NUM_LIT> ; if ( FlatUsed ) ExtraSGPRs = <NUM_LIT> ; } MaxSGPR += ExtraSGPRs ; if ( STM . debuggerReserveRegs ( ) ) { ProgInfo . ReservedVGPRFirst = MaxVGPR + <NUM_LIT> ; ProgInfo . ReservedVGPRCount = MFI -> getDebuggerReservedVGPRCount ( ) ; MaxVGPR += MFI -> getDebuggerReservedVGPRCount ( ) ; } ProgInfo . NumVGPR = MaxVGPR + <NUM_LIT> ; ProgInfo . NumSGPR = MaxSGPR + <NUM_LIT> ; if ( STM . hasSGPRInitBug ( ) ) { if ( ProgInfo . NumSGPR > <ISA_LIT>Subtarget :: FIXED_SGPR_COUNT_FOR_INIT_BUG ) { LLVMContext & Ctx = MF . getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> ) ;


<s> static bool definesCPSR ( MachineInstr * MI ) { for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {

const MachineOperand & MO = MI -> getOperand ( i ) ;


<s> if ( Val . countTrailingOnes ( ) >= Width ) return true ;

APInt Mask = Val | CurDAG -> computeKnownBits ( N -> getOperand ( <NUM_LIT> ) ) . Zero ;


<s> int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; bool IsPic = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; bool ExtraLoadRequired = Subtarget . GVRequiresExtraLoad ( GV , getTargetMachine ( ) , false ) ; SDValue Result ; if ( ! IsPic && ! ExtraLoadRequired ) { Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { unsigned char OpFlags = <NUM_LIT> ;

if ( ExtraLoadRequired ) OpFlags = <STR_LIT> ;


<s> <STR_LIT> Pred = getInstrPredicate ( * First , PredReg ) ; DebugLoc DL = First -> getDebugLoc ( ) ; MachineInstr * Merged = nullptr ; if ( Cand . CanMergeToLSDouble ) Merged = CreateLoadStoreDouble ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs , Cand . Instrs ) ; if ( ! Merged && Cand . CanMergeToLSMulti ) Merged = CreateLoadStoreMulti ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs , Cand . Instrs ) ; if ( ! Merged ) return nullptr ; iterator EarliestI ( Cand . Instrs [ Cand . EarliestMIIdx ] ) ; bool EarliestAtBegin = false ; if ( EarliestI == MBB . begin ( ) ) { EarliestAtBegin = true ; } else { EarliestI = std :: prev ( EarliestI ) ; } for ( MachineInstr * MI : Cand . Instrs ) MBB . erase ( MI ) ; if ( EarliestAtBegin ) EarliestI = MBB . begin ( ) ; else EarliestI = std :: next ( EarliestI ) ; auto FixupRange = make_range ( EarliestI , iterator ( Merged ) ) ; if ( isLoadSingle ( Opcode ) ) { for ( MachineInstr & MI : FixupRange ) { for ( unsigned & ImpDefReg : ImpDefs ) { for ( MachineOperand & MO : MI . implicit_operands ( ) ) { if ( ! MO . isReg ( ) || MO . getReg ( ) != ImpDefReg ) continue ; if ( MO . readsReg ( ) ) MO . setIsUndef ( ) ; else if ( MO . isDef ( ) ) ImpDefReg = <NUM_LIT> ; } }


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> rtx p ; p = prev_nonnote_insn ( first_insn ) ; while ( p ) { if ( GET_CODE ( p ) != INSN ) return false ; if ( reg_set_p ( target , p ) ) { rtx set = single_set ( p ) ; rtx dest ; if ( ! set ) return false ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: tryFoldAddLowIntoImm ( MachineInstr & RootDef , unsigned Size , MachineRegisterInfo & MRI ) const { if ( RootDef . getOpcode ( ) != <STR_LIT> ) return None ; MachineInstr & Adrp = * MRI . getVRegDef ( RootDef . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Adrp . getOpcode ( ) != <STR_LIT> ) return None ; assert ( Adrp . getOperand ( <NUM_LIT> ) . getOffset ( ) == <NUM_LIT> && <STR_LIT> ) ; auto GV = Adrp . getOperand ( <NUM_LIT> ) . getGlobal ( ) ; if ( GV -> isThreadLocal ( ) ) return None ; auto & MF = * RootDef . getParent ( ) -> getParent ( ) ; if ( GV -> getPointerAlignment ( MF . getDataLayout ( ) ) < Size ) return None ;

unsigned OpFlags = STI . ClassifyGlobalReference ( GV , MF . getTarget ( ) ) ;


<s> } } } if ( cast < CondCodeSDNode > ( N02 ) -> get ( ) == <STR_LIT> ) { SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N01 == N1 ) { SDValue N2 = N -> getOperand ( <NUM_LIT> ) ; if ( N000 == N2 && N0 . getNode ( ) -> getValueType ( N0 . getResNo ( ) ) == <STR_LIT> && N00 . getNode ( ) -> getValueType ( N00 . getResNo ( ) ) == <STR_LIT> ) { SDNode * SextNode = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , N000 ) ; SDNode * Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( SextNode , <NUM_LIT> ) , N1 ) ; ReplaceUses ( N , Result ) ; return Result ; } }


<s> if ( ReturnAddrIndex == <NUM_LIT> ) { unsigned SlotSize = Subtarget . getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) . CreateFixedObject ( SlotSize , - ( int64_t ) SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; }

return DAG . getFrameIndex ( ReturnAddrIndex , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


<s> static SDValue IsSingleInstrConstant ( SDValue N , SelectionDAG & DAG , const <ISA_LIT>Subtarget * ST , const SDLoc & dl ) { uint64_t Val ; if ( ! isa < ConstantSDNode > ( N ) ) return SDValue ( ) ; Val = cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; if ( ST -> isThumb1Only ( ) ) { if ( Val <= <NUM_LIT> || ~ Val <= <NUM_LIT> ) return DAG . getConstant ( Val , dl , <STR_LIT> ) ; } else { if ( <STR_LIT> ( Val ) != - <NUM_LIT> || <STR_LIT> ( ~ Val ) != - <NUM_LIT> ) return DAG . getConstant ( Val , dl , <STR_LIT> ) ;


return TargetTriple . isOSBinFormatELF ( ) ;


<s> if ( cfun -> machine -> next_fcc > FCC_REG_LAST - FCC_REG_FIRST ) cfun -> machine -> next_fcc = <NUM_LIT> ; regno = FCC_REG_FIRST + cfun -> machine -> next_fcc ; cfun -> machine -> next_fcc += count ;


<s> } if ( IsTrueBlockRequired ) { TrueBlock = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , TrueBlock ) ; } if ( NewSuccessor ) { MF -> insert ( It , NewSuccessor ) ; NewSuccessor -> splice ( NewSuccessor -> end ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( BIL . back ( ) ) ) , MBB -> end ( ) ) ; NewSuccessor -> transferSuccessorsAndUpdatePHIs ( MBB ) ; for ( auto & LI : MBB -> liveins ( ) ) NewSuccessor -> addLiveIn ( LI ) ; LivePhysRegs LPR ( * MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ) ; SmallVector < std :: pair < MCPhysReg , const MachineOperand * > , <NUM_LIT> > Clobbers ; for ( MachineInstr & MI : * MBB ) LPR . stepForward ( MI , Clobbers ) ; for ( auto & LI : LPR ) NewSuccessor -> addLiveIn ( LI ) ;


<s> return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> ConstantSDNode * Offset = nullptr ; if ( Index . getOpcode ( ) == <STR_LIT> ) if ( auto SplatVal = DAG . getSplatValue ( Index . getOperand ( <NUM_LIT> ) ) ) { if ( isa < ConstantSDNode > ( SplatVal ) ) Offset = cast < ConstantSDNode > ( SplatVal ) ; else { BasePtr = SplatVal ; Index = Index -> getOperand ( <NUM_LIT> ) ; return ; }


<s> void setVariadicStackIdx ( int Idx ) { VariadicStackIdx = Idx ;


<s> <ISA_LIT>MCInstLower ( MCContext & Ctx , AsmPrinter & Printer ) : Ctx ( Ctx ) , Printer ( Printer ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


return __builtin_sh_media_FIPR_S ( vg , vh ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateRotImm ( unsigned Imm , SMLoc S , SMLoc E ) {

auto Op = make_unique < <ISA_LIT>Operand > ( k_RotateImmediate ) ;


<s> YamlIO . mapOptional ( <STR_LIT> , MFI . Results , std :: vector < FlowStringValue > ( ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . CFGStackified , false ) ;

YamlIO . mapOptional ( <STR_LIT> , MFI . SrcToUnwindDest ) ;


<s> default : return SDValue ( ) ; } SDValue SraC = Mask . getOperand ( <NUM_LIT> ) ; unsigned SraAmt = cast < ConstantSDNode > ( SraC ) -> getZExtValue ( ) ; unsigned EltBits = MaskVT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( ( SraAmt + <NUM_LIT> ) != EltBits ) return SDValue ( ) ; DebugLoc DL = N -> getDebugLoc ( ) ; X = X . getOperand ( <NUM_LIT> ) ; Y = Y . getOperand ( <NUM_LIT> ) ; if ( Y . getOpcode ( ) == <STR_LIT> && Y . getOperand ( <NUM_LIT> ) == X && <STR_LIT> ( Y . getOperand ( <NUM_LIT> ) . getNode ( ) ) && X . getValueType ( ) == MaskVT && X . getValueType ( ) == Y . getValueType ( ) ) { unsigned Opc = <NUM_LIT> ; switch ( EltBits ) { case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; default : break ; } if ( Opc ) { SDValue Sign = DAG . getNode ( Opc , DL , MaskVT , X , Mask . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Sign ) ; } } if ( ! ( Subtarget -> hasSSE41 ( ) || Subtarget -> hasAVX ( ) ) ) return SDValue ( ) ; X = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X ) ; Y = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Y ) ; Mask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask ) ; Mask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask , X , Y ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mask ) ; } } } if ( N0 . getOpcode ( ) == <STR_LIT> && N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ;

if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ;


<s> if ( cfun -> is_thunk ) return <NUM_LIT> ; if ( cfun -> machine -> lr_save_state ) return cfun -> machine -> lr_save_state - <NUM_LIT> ; push_topmost_sequence ( ) ; top = get_insns ( ) ; pop_topmost_sequence ( ) ; reg = gen_rtx_REG ( Pmode , LR_REGNO ) ; for ( insn = NEXT_INSN ( top ) ; insn != NULL_RTX ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) { if ( CALL_P ( insn ) ) {

if ( ! SIBLING_CALL_P ( insn ) ) return <NUM_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: useF32FTZ ( ) const { if ( FtzEnabled . getNumOccurrences ( ) > <NUM_LIT> ) { return FtzEnabled ; } else { const Function * F = MF -> getFunction ( ) ;

if ( F -> hasFnAttribute ( <STR_LIT> ) ) return F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ;


<s> if ( CC == CallingConv :: Cold ) { return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_SVR64_ColdCC_Altivec_RegMask : CSR_SVR64_ColdCC_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR32_ColdCC_Altivec_RegMask : ( Subtarget . hasSPE ( ) ? CSR_SVR32_ColdCC_SPE_RegMask : CSR_SVR32_ColdCC_RegMask ) ) ; }

return TM . is<ISA_LIT>64 ( ) ? ( Subtarget . hasAltivec ( ) ? CSR_<ISA_LIT>64_Altivec_RegMask : CSR_<ISA_LIT>64_RegMask ) : ( Subtarget . hasAltivec ( ) ? CSR_SVR432_Altivec_RegMask : ( Subtarget . hasSPE ( ) ? CSR_SVR432_SPE_RegMask : CSR_SVR432_RegMask ) ) ;


<s> static const char * ia64_invalid_unary_op ( int op , const_tree type ) { if ( TYPE_MODE ( type ) == RFmode && op != CONVERT_EXPR && op != ADDR_EXPR ) return N_ ( <STR_LIT> ) ; return NULL ;


<s> default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - <NUM_LIT> ) * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool hasSlt ( ) const { return HasSlt ;


<s> return MatchOperand_ParseFail ; } Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLoc ( ) ) ) ; getParser ( ) . Lex ( ) ; if ( parseImmediate ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } } else if ( parseImmediate ( Operands ) != MatchOperand_Success ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ;


<s> if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } addr = XEXP ( orig_src , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_src = replace_equiv_address ( orig_src , addr ) ; } } } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = SImode ; gen_func . mov = gen_movsi ; } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = HImode ; gen_func . mov = gen_movhi ; } else { move_bytes = <NUM_LIT> ; mode = QImode ; gen_func . mov = gen_movqi ; } if ( might_overlap && num_reg + <NUM_LIT> >= MAX_MOVE_REG && bytes > move_bytes ) return <NUM_LIT> ; gcc_assert ( mode != BLKmode ) ; src = adjust_address ( orig_src , mode , offset ) ; dest = adjust_address ( orig_dest , mode , offset ) ; rtx tmp_reg = gen_reg_rtx ( mode ) ; if ( move_with_length ) { loads [ num_reg ] = ( * gen_func . movlen ) ( tmp_reg , src , move_bytes ) ; stores [ num_reg ++ ] = ( * gen_func . movlen ) ( dest , tmp_reg , move_bytes ) ; } else {

loads [ num_reg ] = ( * gen_func . mov ) ( tmp_reg , src ) ;


<s> if ( BitWidth < <NUM_LIT> ) { unsigned MidRegLo = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned MidRegHi = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ResultReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegLo ) . addReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( BitWidth ) ; BuildMI ( MBB , MII , DL , get ( <STR_LIT> ) , MidRegHi ) . addImm ( <NUM_LIT> ) . addReg ( MidRegLo ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , ResultReg ) . addReg ( MidRegLo ) . addImm ( <STR_LIT> ) . addReg ( MidRegHi ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , ResultReg ) ; addUsersToMoveToVALUWorklist ( ResultReg , MRI , Worklist ) ;


<s> return ( int8x8_t ) __builtin_aarch64_srshlv8qi ( __a , __b ) ;


<s> const unsigned MaskWeight = SlotWeight - <NUM_LIT> ; bool Key = ( <NUM_LIT> << s ) & getUnits ( ) ; assert ( SlotWeight * s < <NUM_LIT> && <STR_LIT> ) ; Weight = ( Key << ( SlotWeight * s ) ) * ( ( MaskWeight - countPopulation ( getUnits ( ) ) ) << countTrailingZeros ( getUnits ( ) ) ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & sti ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( sti . getSpecialRegisters ( ) -> getReturnFunctionAddressRegister ( ) ) , STI ( sti ) {


<s> void <ISA_LIT>AsmParser :: AddDefaultSrcDestOperands ( OperandVector & Operands , std :: unique_ptr < llvm :: MCParsedAsmOperand > && Src , std :: unique_ptr < llvm :: MCParsedAsmOperand > && Dst ) { if ( isParsingIntelSyntax ( ) ) { Operands . push_back ( std :: move ( Dst ) ) ; Operands . push_back ( std :: move ( Src ) ) ; } else { Operands . push_back ( std :: move ( Src ) ) ; Operands . push_back ( std :: move ( Dst ) ) ; }


<s> SDNode * <ISA_LIT>SEDAGToDAGISel :: selectAddESubE ( unsigned MOp , SDValue InFlag , SDValue CmpLHS , DebugLoc DL , SDNode * Node ) const { unsigned Opc = InFlag . getOpcode ( ) ; ( void ) Opc ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) , RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; SDNode * Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Ops ) ; SDNode * AddCarry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , SDValue ( Carry , <NUM_LIT> ) , RHS ) ;

return CurDAG -> SelectNodeTo ( Node , MOp , VT , <STR_LIT> , LHS , SDValue ( AddCarry , <NUM_LIT> ) ) ;


<s> return new <ISA_LIT>CA53Erratum835769Stub ( getData ( ) , size ( ) , <STR_LIT> , fixup_begin ( ) , fixup_end ( ) ) ;


<s> bool isu3Imm ( ) const { return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false , false ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> EVT SrcVT ; unsigned Opc = N . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : { EVT T = Opc == <STR_LIT> ? N . getOperand ( <NUM_LIT> ) . getValueType ( ) : cast < VTSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getVT ( ) ; if ( T . getSizeInBits ( ) != <NUM_LIT> ) return false ; R = N . getOperand ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { LoadSDNode * L = cast < LoadSDNode > ( N ) ; if ( L -> getExtensionType ( ) != <STR_LIT> ) return false ; if ( L -> getMemoryVT ( ) . getSizeInBits ( ) > <NUM_LIT> ) return false ; R = N ; break ; } default : return false ; } EVT RT = R . getValueType ( ) ; if ( RT == <STR_LIT> ) return true ; assert ( RT == <STR_LIT> ) ; const SDLoc & dl ( N ) ; SDValue Ops [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , R , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , R , CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) } ; SDNode * T = CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , <STR_LIT> , Ops ) ; R = SDValue ( T , <NUM_LIT> ) ; return true ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> SDValue ExtSrc = RHS . getOperand ( <NUM_LIT> ) ; EVT SrcVT = ExtSrc . getValueType ( ) ; if ( SrcVT == <STR_LIT> ) { SDLoc SL ( N ) ; SDValue LowLHS , HiBits ; std :: tie ( LowLHS , HiBits ) = split64BitValue ( LHS , DAG ) ; SDValue LowOr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LowLHS , ExtSrc ) ; DCI . AddToWorklist ( LowOr . getNode ( ) ) ; DCI . AddToWorklist ( HiBits . getNode ( ) ) ; SDValue Vec = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , LowOr , HiBits ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ; } } } if ( LHS . getOpcode ( ) == <STR_LIT> && RHS . getOpcode ( ) == <STR_LIT> ) { SDValue Src = LHS . getOperand ( <NUM_LIT> ) ; if ( Src != RHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; const ConstantSDNode * CLHS = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; const ConstantSDNode * CRHS = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! CLHS || ! CRHS ) return SDValue ( ) ; static const uint32_t MaxMask = <NUM_LIT> ; uint32_t NewMask = ( CLHS -> getZExtValue ( ) | CRHS -> getZExtValue ( ) ) & MaxMask ; SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , DAG . getConstant ( NewMask , DL , <STR_LIT> ) ) ;


<s> void addPreRegAlloc ( ) override { if ( getOptLevel ( ) == CodeGenOpt :: None ) { addPass ( & DeadMachineInstructionElimID ) ;


<s> } return AM . Scale == <NUM_LIT> && ( AM . BaseOffs == <NUM_LIT> || Subtarget -> getInstrInfo ( ) -> isLegalFLATOffset ( AM . BaseOffs , <ISA_LIT>AS :: FLAT_ADDRESS , false ) ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: isImm ( const SDValue & operand ) {

return ConstantSDNode :: classof ( operand . getNode ( ) ) ;


<s> ClassDef += ClassName ; ClassDef += <STR_LIT> ; EmitClassFields ( ClassDef , STy , CompFields ) ; ClassDef += <STR_LIT> ; for ( auto & TyFIDPair : CompFields ) EmitFieldAllocation ( ClassDef , TyFIDPair . first , ClassName , TyFIDPair . second ) ; ClassDef += <STR_LIT> ; return ClassDef ;


<s> FunctionPass * llvm :: create<ISA_LIT>CodePrinterPass ( raw_ostream & o , TargetMachine & tm , CodeGenOpt :: Level OptLevel , bool verbose ) { return new <ISA_LIT>AsmPrinter ( o , tm , tm . getTargetAsmInfo ( ) , OptLevel , verbose ) ;


return __builtin_ia32_vcvtw2ph128_mask ( ( __v8hi ) __A , _mm_setzero_ph ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return __builtin_aarch64_frecpedf ( __a ) ;


<s> Reg , Expr ) , Start ( S ) , End ( E ) {


<s> enum resolver_ident arm_describe_resolver ( tree fndecl ) { if ( DECL_MD_FUNCTION_CODE ( fndecl ) >= ARM_BUILTIN_vcx1qv16qi && DECL_MD_FUNCTION_CODE ( fndecl ) < ARM_BUILTIN_MVE_BASE ) return arm_cde_resolver ;


<s> switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : return TargetLowering :: getPICJumpTableRelocBaseExpr ( MF , JTI , Ctx ) ; default :

return MCSymbolRefExpr :: create ( MF -> getPICBaseSymbol ( ) , Ctx ) ;


<s> case Function :: WeakODRLinkage : O << TAI -> getGlobalDirective ( ) << CurrentFnName << <STR_LIT> ; O << TAI -> getWeakDefDirective ( ) << CurrentFnName << <STR_LIT> ; break ; } EmitAlignment ( MF . getAlignment ( ) , F , <NUM_LIT> ) ; if ( TAI -> hasDotTypeDotSizeDirective ( ) ) { O << <STR_LIT> << CurrentFnName << <STR_LIT> ; }


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ;

Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>MCAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU ) { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; return new <ISA_LIT>MCAsmBackend ( OSABI ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) {


<s> return ( this -> storage & <NUM_LIT> ) ? RegName :: a1 : RegName :: a0 ;


<s> rtvec vec = rtvec_alloc ( nelts ) ; for ( unsigned int i = <NUM_LIT> ; i < nelts ; ++ i ) RTVEC_ELT ( vec , i ) = gen_int_mode ( base + i * step , DImode ) ;

return gen_rtx_PARALLEL ( VOIDmode , vec ) ;


<s> bool <ISA_LIT>AsmParser :: cvtLdrdPre ( MCInst & Inst , unsigned Opcode , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;

( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAddrMode3Operands ( Inst , <NUM_LIT> ) ;


<s> if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode0 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode1 ) ) op2 = copy_to_mode_reg ( mode0 , op2 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op3 , mode1 ) ) op3 = copy_to_mode_reg ( mode0 , op3 ) ; scratch = gen_reg_rtx ( CCmode ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return const0_rtx ; emit_insn ( pat ) ; if ( mode0 == V2SImode ) emit_insn ( gen_spe_evsel ( target , op2 , op3 , scratch ) ) ;

else emit_insn ( gen_spe_evsel_fs ( target , op2 , op3 , scratch ) ) ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> <ISA_LIT>FrameInfo :: <ISA_LIT>FrameInfo ( const <ISA_LIT>Subtarget & sti ) : TargetFrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( sti ) {


<s> void <ISA_LIT>LongBranch :: relaxBranches ( ) { SmallVector < TerminatorInfo , <NUM_LIT> > :: iterator TI = Terminators . begin ( ) ; BlockPosition Position ( Log2 ( MF -> getAlignment ( ) ) ) ; for ( auto & Block : MBBs ) { skipNonTerminators ( Position , Block ) ;

for ( unsigned BTI = <NUM_LIT> , BTE = Block . NumTerminators ; BTI != BTE ; ++ BTI ) {


<s> void printAS16Mem ( const MCInst * MI , int opNum , raw_ostream & O ) { printAbsMem ( MI , opNum , O ) ;


<s> return cast < MCSectionELF > ( DataGlobalAgentSection ) -> getSectionName ( ) . equals ( SectionName ) ;


<s> return BEGIN_CONTROL ; case UNSPEC_LDS_A : case UNSPEC_LDSA : return BEGIN_DATA | BEGIN_CONTROL ; default : return <NUM_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: matchLoadInAddress ( LoadSDNode * N , <ISA_LIT>ISelAddressMode & AM ) { return false ;


<s> <ISA_LIT>SPMark ( <ISA_LIT>TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) {


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: updatedRC ( const TargetRegisterClass * RC ) const { if ( Subtarget . hasVSX ( ) && RC == & <STR_LIT> ) return & <STR_LIT> ; return RC ;


<s> static int rs6000_hard_regno_nregs_internal ( int regno , machine_mode mode ) { unsigned HOST_WIDE_INT reg_size ; if ( FP_REGNO_P ( regno ) ) reg_size = ( VECTOR_MEM_VSX_P ( mode ) || VECTOR_ALIGNMENT_P ( mode ) ? UNITS_PER_VSX_WORD : UNITS_PER_FP_WORD ) ; else if ( ALTIVEC_REGNO_P ( regno ) ) reg_size = UNITS_PER_ALTIVEC_WORD ; else reg_size = UNITS_PER_WORD ; return ( GET_MODE_SIZE ( mode ) + reg_size - <NUM_LIT> ) / reg_size ;


<s> if ( DispSpec . isImm ( ) ) { O << formatImm ( DispSpec . getImm ( ) ) ; } else { assert ( DispSpec . isExpr ( ) && <STR_LIT> ) ; DispSpec . getExpr ( ) -> print ( O , & MAI ) ; }


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( Triple ( TT ) . getOS ( ) ) ;

return new ELF<ISA_LIT>AsmBackend ( T , OSABI ) ;


<s> assert ( EHPad && <STR_LIT> ) ; if ( Call -> getParent ( ) == EHPad && Call -> getNextNode ( ) -> getOpcode ( ) == <STR_LIT> ) continue ; Changed = true ; MachineInstr * Catch = & * EHPad -> begin ( ) ; assert ( <STR_LIT> ( * Catch ) ) ; Call -> getOperand ( <NUM_LIT> ) . setReg ( Catch -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; auto InsertPos = std :: next ( MachineBasicBlock :: iterator ( Catch ) ) ; EHPad -> insert ( InsertPos , Call -> removeFromParent ( ) ) ; BuildMI ( * EHPad , InsertPos , Call -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; EHPad -> erase ( InsertPos , EHPad -> end ( ) ) ; for ( auto * Succ : EHPad -> successors ( ) ) EraseBBAndChildren ( Succ ) ; } return Changed ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & subtarget , const TargetInstrInfo & tii ) :

<ISA_LIT>GenRegisterInfo ( <STR_LIT> , <STR_LIT> ) , Subtarget ( subtarget ) , TII ( tii ) {


<s> void <ISA_LIT>MCInstrInfo :: tryCompound ( MCInstrInfo const & MCII , MCContext & Context , MCInst & MCI ) { assert ( <ISA_LIT>MCInstrInfo :: isBundle ( MCI ) && <STR_LIT> ) ; if ( MCI . size ( ) < <NUM_LIT> ) return ;

while ( lookForCompound ( MCII , Context , MCI ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>MCLowerPrePass ( ) { return new <ISA_LIT>MCLowerPrePass ( ) ;


<s> else if ( RC == & <STR_LIT> ) CopyOpcode = <STR_LIT> ; else if ( RC == & <STR_LIT> ) CopyOpcode = <STR_LIT> ; else if ( RC == & <STR_LIT> ) CopyOpcode = <STR_LIT> ; else if ( RC == & <STR_LIT> ) CopyOpcode = <STR_LIT> ; else if ( RC == & <STR_LIT> ) CopyOpcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;

BuildMI ( MBB , I , DL , get ( CopyOpcode ) , DestReg ) . addReg ( SrcReg , KillSrc ? RegState :: Kill : <NUM_LIT> ) ;


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) ) { O << <STR_LIT> ; printU8ImmDecOperand ( MI , OpNo , O ) ; }


<s> if ( NumLanes ) Suffix += itostr ( NumLanes ) + LaneKind ; else Suffix += LaneKind ; printVectorList ( MI , OpNum , O , Suffix ) ;


<s> } if ( ! TM ) return true ; const TargetLowering * TLI = TM -> getSubtargetImpl ( ) -> getTargetLowering ( ) ; if ( Function * F = CI -> getCalledFunction ( ) ) { unsigned Opcode ; if ( F -> getIntrinsicID ( ) != <STR_LIT> ) { switch ( F -> getIntrinsicID ( ) ) { default : continue ; ! defined ( setjmp_undefined_for_msvc ) case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : if ( CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> getScalarType ( ) -> is<ISA_LIT>_FP128Ty ( ) ) return true ; else continue ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } } LibFunc :: Func Func ; if ( ! F -> hasLocalLinkage ( ) && F -> hasName ( ) && LibInfo && LibInfo -> getLibFunc ( F -> getName ( ) , Func ) && LibInfo -> hasOptimizedCodeGen ( Func ) ) { if ( ! CI -> onlyReadsMemory ( ) ) return true ; if ( ! CI -> getArgOperand ( <NUM_LIT> ) -> getType ( ) -> isFloatingPointTy ( ) ) return true ; switch ( Func ) { default : return true ; case LibFunc :: copysign : case LibFunc :: copysignf : continue ; case LibFunc :: copysignl : return true ; case LibFunc :: fabs : case LibFunc :: fabsf : case LibFunc :: fabsl : continue ; case LibFunc :: sqrt : case LibFunc :: sqrtf : case LibFunc :: sqrtl : Opcode = <STR_LIT> ; break ; case LibFunc :: floor : case LibFunc :: floorf : case LibFunc :: floorl : Opcode = <STR_LIT> ; break ; case LibFunc :: nearbyint : case LibFunc :: nearbyintf : case LibFunc :: nearbyintl : Opcode = <STR_LIT> ; break ;


<s> if ( TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: GLOBAL_ADDRESS , true ) ) { Addr = LHS ; ImmOffset = COffsetVal ; } } if ( Addr . getOpcode ( ) != <STR_LIT> ) return false ; SDValue LHS = Addr . getOperand ( <NUM_LIT> ) ; SDValue RHS = Addr . getOperand ( <NUM_LIT> ) ; if ( ! LHS -> isDivergent ( ) ) { if ( SDValue ZextRHS = matchZExtFromI32 ( RHS ) ) { SAddr = LHS ; VOffset = ZextRHS ;


<s> void <ISA_LIT>IfConversion :: insertPredCopies ( BBInfo & blockInfo , std :: set < PHIEntryInfo > & deadPhis , SmallPredVector & predicates ) { MachineBasicBlock * MBB = blockInfo . MBB ; assert ( blockInfo . MBB && <STR_LIT> ) ; std :: set < PHIEntryInfo > :: iterator PI ; for ( PI = deadPhis . begin ( ) ; PI != deadPhis . end ( ) ; ++ PI ) { const unsigned destReg = PI -> first ; const unsigned sourceRegTBB = PI -> second . first ; const unsigned sourceRegFBB = PI -> second . second ; MachineInstr * predSelectMI = BuildMI ( * MBB , MBB -> getFirstTerminator ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , destReg ) . addReg ( sourceRegTBB ) . addReg ( sourceRegFBB ) ; if ( ! TII -> PredicateInstruction ( predSelectMI , predicates ) ) DEBUG ( dbgs ( ) << <STR_LIT> << * predSelectMI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * predSelectMI ) ;


<s> int mmix_function_arg_regno_p ( int regno , int incoming ) { int first_arg_regnum = incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM ; return regno >= first_arg_regnum && regno < first_arg_regnum + MMIX_MAX_ARGS_IN_REGS ;


<s> SmallVector < int , <NUM_LIT> > SrcLaneMask ( NumLanes , SM_SentinelUndef ) ; SmallVector < int , <NUM_LIT> > PermMask ( NumElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != NumElts ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; int SrcLane = M / NumEltsPerLane ; int DstLane = i / NumEltsPerLane ; if ( ! isUndefOrEqual ( SrcLaneMask [ DstLane ] , SrcLane ) ) return SDValue ( ) ; SrcLaneMask [ DstLane ] = SrcLane ; PermMask [ i ] = ( DstLane * NumEltsPerLane ) + ( M % NumEltsPerLane ) ; } SmallVector < int , <NUM_LIT> > LaneMask ( NumElts , SM_SentinelUndef ) ;

for ( int DstLane = <NUM_LIT> ; DstLane != NumLanes ; ++ DstLane ) {


<s> if ( AS == AMDGPUA<ISA_LIT> . GLOBAL_ADDRESS || AS == AMDGPUA<ISA_LIT> . FLAT_ADDRESS ) { return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> * <NUM_LIT> ) ; } else if ( AS == AMDGPUA<ISA_LIT> . PRIVATE_ADDRESS ) { unsigned MaxPrivateBits = <NUM_LIT> * getSubtarget ( ) -> getMaxPrivateElementSize ( ) ; return ( MemVT . getSizeInBits ( ) <= MaxPrivateBits ) ;

} else if ( AS == AMDGPUA<ISA_LIT> . LOCAL_ADDRESS ) {


<s> const int maxDForm2Offset = ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ; return DFormAddressPredicate ( Op , N , Disp , Base , minDForm2Offset , maxDForm2Offset ) ;


<s> if ( ! Reg . isVirtual ( ) ) return nullptr ; if ( ! MRI -> hasOneNonDBGUse ( Reg ) ) return nullptr ; MachineInstr & DefMI = * MRI -> getVRegDef ( Reg ) ;

if ( ( DefMI . getOpcode ( ) != <STR_LIT> && DefMI . getOpcode ( ) != <STR_LIT> ) || DefMI . getParent ( ) != FrameSetup -> getParent ( ) ) return nullptr ;


<s> if ( GV -> getName ( ) . startswith ( <STR_LIT> ) ) { if ( ! Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ) report_fatal_error ( <STR_LIT> ) ; PreserveDITypeCalls . push_back ( Call ) ; } } } if ( PreserveDITypeCalls . empty ( ) ) return false ; std :: string BaseName = <STR_LIT> ; static int Count = <NUM_LIT> ; for ( auto Call : PreserveDITypeCalls ) { const ConstantInt * Flag = dyn_cast < ConstantInt > ( Call -> getArgOperand ( <NUM_LIT> ) ) ; assert ( Flag ) ; uint64_t FlagValue = Flag -> getValue ( ) . getZExtValue ( ) ; if ( FlagValue >= <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; MDNode * MD = Call -> getMetadata ( LLVMContext :: MD_preserve_access_index ) ; uint32_t Reloc ; if ( FlagValue == <STR_LIT> ) { Reloc = <STR_LIT> ; } else { Reloc = <STR_LIT> ; DIType * Ty = cast < DIType > ( MD ) ; while ( auto * DTy = dyn_cast < DIDerivedType > ( Ty ) ) { unsigned Tag = DTy -> getTag ( ) ; if ( Tag != dwarf :: DW_TAG_const_type && Tag != dwarf :: DW_TAG_volatile_type ) break ; Ty = DTy -> getBaseType ( ) ; } if ( Ty -> getName ( ) . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; MD = Ty ; } BasicBlock * BB = Call -> getParent ( ) ; IntegerType * VarType = Type :: getInt64Ty ( BB -> getContext ( ) ) ; std :: string GVName = BaseName + std :: to_string ( Count ) + <STR_LIT> + std :: to_string ( Reloc ) ; GlobalVariable * GV = new GlobalVariable ( * M , VarType , false , GlobalVariable :: ExternalLinkage , NULL , GVName ) ; GV -> addAttribute ( <STR_LIT> ) ; GV -> setMetadata ( LLVMContext :: MD_preserve_access_index , MD ) ; auto * LDInst = new LoadInst ( Type :: getInt64Ty ( BB -> getContext ( ) ) , GV , <STR_LIT> , Call ) ; Instruction * PassThroughInst = <STR_LIT> ( M , BB , LDInst , Call ) ; Call -> replaceAllUsesWith ( PassThroughInst ) ; Call -> eraseFromParent ( ) ; Count ++ ; } return true ;


<s> auto End = It -> getParent ( ) -> instr_end ( ) ; MachineBasicBlock :: const_instr_iterator I = It . getInstrIterator ( ) ; while ( ++ I != End && I -> isBundled ( ) ) if ( I -> getOpcode ( ) == <STR_LIT> ) return true ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += VecSize ) { SDValue StoreVal ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( DAG . getConstant ( Offset , <STR_LIT> ) ) ; unsigned Opc = <STR_LIT> ; EVT ExtendedVT = ( NeedExtend ) ? <STR_LIT> : OutVals [ <NUM_LIT> ] . getValueType ( ) ; StoreVal = OutVals [ i ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; Ops . push_back ( StoreVal ) ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; if ( VecSize == <NUM_LIT> ) { Opc = <STR_LIT> ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; if ( i + <NUM_LIT> < NumElts ) { StoreVal = OutVals [ i + <NUM_LIT> ] ; if ( NeedExtend ) StoreVal = DAG . getNode ( <STR_LIT> , dl , ExtendedVT , StoreVal ) ; } else { StoreVal = DAG . getUNDEF ( ExtendedVT ) ; } Ops . push_back ( StoreVal ) ; } Chain = DAG . getMemIntrinsicNode ( Opc , dl , DAG . getVTList ( <STR_LIT> ) , Ops , EltVT , MachinePointerInfo ( ) ) ; Offset += PerStoreOffset ; } } } else { SmallVector < EVT , <NUM_LIT> > ValVTs ; ComputePTXValueVTs ( * this , RetTy , ValVTs ) ; assert ( ValVTs . size ( ) == OutVals . size ( ) && <STR_LIT> ) ; unsigned SizeSoFar = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Outs . size ( ) ; i != e ; ++ i ) { SDValue theVal = OutVals [ i ] ; EVT TheValType = theVal . getValueType ( ) ; unsigned numElems = <NUM_LIT> ; if ( TheValType . isVector ( ) ) numElems = TheValType . getVectorNumElements ( ) ;

for ( unsigned j = <NUM_LIT> , je = numElems ; j != je ; ++ j ) {


<s> void FillFinishOpcode ( ) { while ( Pos < Vec . size ( ) ) EmitByte ( <STR_LIT> :: UNWIND_OPCODE_FINISH ) ;


<s> } continue ; } if ( auto * LD = dyn_cast < LoadInst > ( & I ) ) { if ( ! LD -> hasOneUser ( ) ) continue ; auto * Call = dyn_cast < CallInst > ( * LD -> user_begin ( ) ) ; if ( ! Call ) continue ; auto * GV = dyn_cast < GlobalValue > ( Call -> getCalledOperand ( ) ) ; if ( ! GV ) continue ; if ( ! GV -> getName ( ) . equals ( <STR_LIT> ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I . dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Call -> dump ( ) ; dbgs ( ) << '\n' ) ; Changed = true ; Call -> eraseFromParent ( ) ; ToErase = & I ; } }


<s> } if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { return & <STR_LIT> ; } return RC ;


<s> StringRef getPassName ( ) const override {


<s> rtx gen_easy_altivec_constant ( rtx op ) { enum machine_mode mode = GET_MODE ( op ) ; int nunits = GET_MODE_NUNITS ( mode ) ; rtx last = CONST_VECTOR_ELT ( op , nunits - <NUM_LIT> ) ; unsigned step = nunits / <NUM_LIT> ; unsigned copies = <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V4SImode , gen_lowpart ( SImode , last ) ) ; if ( step == <NUM_LIT> ) copies <<= <NUM_LIT> ; else step >>= <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return gen_rtx_VEC_DUPLICATE ( V8HImode , gen_lowpart ( HImode , last ) ) ;


<s> <ISA_LIT>PLT1 * plt1_entry = new ( std :: nothrow ) <ISA_LIT>PLT1 ( * m_pSectionData ) ; if ( ! plt1_entry ) fatal ( diag :: fail_allocate_memory_plt ) ; return plt1_entry ;


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ;

return createELFObjectWriter ( MOTW , OS , true ) ;


<s> void setManipulatesSP ( bool MSP ) {


<s> MF . push_back ( CaptureSpec ) ; MF . push_back ( CallTarget ) ; const unsigned CallOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; const unsigned RetOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; Entry -> addLiveIn ( ThunkReg ) ; BuildMI ( Entry , DebugLoc ( ) , TII -> get ( CallOpc ) ) . addSym ( TargetSym ) ; Entry -> addSuccessor ( CaptureSpec ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; BuildMI ( CaptureSpec , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( CaptureSpec ) ; CaptureSpec -> setHasAddressTaken ( ) ; CaptureSpec -> addSuccessor ( CaptureSpec ) ; CallTarget -> addLiveIn ( ThunkReg ) ; CallTarget -> setHasAddressTaken ( ) ; CallTarget -> setAlignment ( Align ( <NUM_LIT> ) ) ; const unsigned MovOpc = Is64Bit ? <STR_LIT> : <STR_LIT> ; const Register SPReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( CallTarget , DebugLoc ( ) , TII -> get ( MovOpc ) ) , SPReg , false , <NUM_LIT> ) . addReg ( ThunkReg ) ; CallTarget -> back ( ) . setPreInstrSymbol ( MF , TargetSym ) ; BuildMI ( CallTarget , DebugLoc ( ) , TII -> get ( RetOpc ) ) ;


<s> unsigned Threshold = isOptSize ( MF ) ? SpillFuncThresholdOs - <NUM_LIT> : SpillFuncThreshold ;


<s> JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; EmitBranchToAt ( ( intptr_t ) Addr , ( intptr_t ) Fn , false , is64Bit ) ; sys :: Memory :: InvalidateInstructionCache ( Addr , <NUM_LIT> * <NUM_LIT> ) ; return Addr ; } void * Addr = ( void * ) JCE . getCurrentPCValue ( ) ; if ( is64Bit ) { JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; JCE . emitWordBE ( <NUM_LIT> ) ; } else if ( Subtarget . isDarwinABI ( ) ) { JCE . emitWordBE ( <NUM_LIT> ) ;


<s> void <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { bool GPRDest = <STR_LIT> . contains ( DestReg ) ; bool GPRSrc = <STR_LIT> . contains ( SrcReg ) ; if ( GPRDest && GPRSrc ) { AddDefaultCC ( AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ) ; return ; } bool SPRDest = <STR_LIT> . contains ( DestReg ) ; bool SPRSrc = <STR_LIT> . contains ( SrcReg ) ; unsigned Opc = <NUM_LIT> ; if ( SPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( GPRDest && SPRSrc ) Opc = <STR_LIT> ; else if ( SPRDest && GPRSrc ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; if ( Opc ) { MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) ; MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; if ( Opc == <STR_LIT> ) MIB . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; AddDefaultPred ( MIB ) ; return ; } unsigned BeginIdx = <NUM_LIT> ; unsigned SubRegs = <NUM_LIT> ; int Spacing = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ;

else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> , BeginIdx = <STR_LIT> , SubRegs = <NUM_LIT> ;


<s> return ( __m256 ) __builtin_ia32_maskloadps256 ( ( const __v8sf * ) __P , ( __v8si ) __M ) ;


<s> if ( USE_HIDDEN_LINKONCE ) sprintf ( name , <STR_LIT> , reg_names [ REGNO ( got_register_rtx ) ] + <NUM_LIT> ) ; else ASM_GENERATE_INTERNAL_LABEL ( name , <STR_LIT> , REGNO ( got_register_rtx ) ) ;

got_helper_rtx = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ;


<s> unsigned NumElems = Input . getValueType ( ) . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < N -> getNumOperands ( ) ; i ++ ) { if ( DAG . getDataLayout ( ) . isLittleEndian ( ) ) ShuffleMask [ CorrectElems & <NUM_LIT> ] = Elems & <NUM_LIT> ; else ShuffleMask [ ( CorrectElems & <NUM_LIT> ) >> <NUM_LIT> ] = ( Elems & <NUM_LIT> ) >> <NUM_LIT> ; CorrectElems = CorrectElems >> <NUM_LIT> ; Elems = Elems >> <NUM_LIT> ; } SDValue Shuffle = DAG . getVectorShuffle ( Input . getValueType ( ) , dl , Input , DAG . getUNDEF ( Input . getValueType ( ) ) , ShuffleMask ) ; EVT Ty = N -> getValueType ( <NUM_LIT> ) ; SDValue BV = DAG . getNode ( <STR_LIT> , dl , Ty , Shuffle ) ;


<s> EltTy = AT -> getElementType ( ) ; AT = dyn_cast < ArrayType > ( EltTy ) ; } unsigned EltElts = ~ <NUM_LIT> ; Type * Tmp = analyzeType ( EltTy , EltElts , DL ) ; if ( EltElts != <NUM_LIT> ) NElts *= EltElts ; return Tmp ; } if ( VectorType * VT = dyn_cast < VectorType > ( Ty ) ) { Type * EltTy = VT -> getElementType ( ) ; NElts = DL . getTypeAllocSize ( Ty ) / DL . getTypeAllocSize ( EltTy ) ; assert ( NElts >= VT -> getNumElements ( ) ) ; if ( EltTy -> isIntegerTy ( <NUM_LIT> ) ) report_fatal_error ( <STR_LIT> ) ; return EltTy ; } if ( isa < StructType > ( Ty ) ) { NElts = DL . getTypeAllocSize ( Ty ) ; return Type :: getInt8Ty ( Ty -> getContext ( ) ) ; } assert ( ! Ty -> isAggregateType ( ) ) ; NElts = <NUM_LIT> ; if ( Ty -> isIntegerTy ( <NUM_LIT> ) ) return Type :: getInt8Ty ( Ty -> getContext ( ) ) ;


<s> return combineSVEPrefetchVecBaseImmOff ( N , DAG , <NUM_LIT> ) ; case <STR_LIT> : return combineSVEPrefetchVecBaseImmOff ( N , DAG , <NUM_LIT> ) ; case <STR_LIT> : return combineSVEPrefetchVecBaseImmOff ( N , DAG , <NUM_LIT> ) ; case <STR_LIT> : return combineSVEPrefetchVecBaseImmOff ( N , DAG , <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return legalizeSVEGatherPrefetchOffsVec ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performLDNT1Combine ( N , DAG ) ; case <STR_LIT> : return performLD1RQCombine ( N , DAG ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performLD1Combine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performLD1Combine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performLD1Combine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performST1Combine ( N , DAG ) ; case <STR_LIT> : return performSTNT1Combine ( N , DAG ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performScatterStoreCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ; case <STR_LIT> : return performGatherLoadCombine ( N , DAG , <STR_LIT> , false ) ;


<s> if ( SU -> NumPreds == <NUM_LIT> && SU -> NumSuccs != <NUM_LIT> ) return <NUM_LIT> ;


<s> if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; <ISA_LIT>Pred = <STR_LIT> ( <ISA_LIT>Pred ) ; } unsigned CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; fastEmitBranch ( FBB , DbgLoc ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; }

} else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) {


<s> if ( rtx_equal_p ( dst , op0 ) && register_operand ( op1 , SImode ) ) break ; if ( low_register_operand ( op0 , SImode ) ) { if ( low_register_operand ( op1 , SImode ) ) action = CONV ; else if ( rtx_equal_p ( dst , op0 ) && CONST_INT_P ( op1 ) && IN_RANGE ( INTVAL ( op1 ) , - <NUM_LIT> , <NUM_LIT> ) ) action = CONV ; else if ( CONST_INT_P ( op1 ) && IN_RANGE ( INTVAL ( op1 ) , - <NUM_LIT> , <NUM_LIT> ) ) action = CONV ; } else if ( GET_CODE ( XEXP ( src , <NUM_LIT> ) ) == PLUS && rtx_equal_p ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) , dst ) && low_register_operand ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) , SImode ) && COMPARISON_P ( op1 ) && cc_register ( XEXP ( op1 , <NUM_LIT> ) , VOIDmode ) && maybe_get_arm_condition_code ( op1 ) == ARM_CS && XEXP ( op1 , <NUM_LIT> ) == const0_rtx ) action = CONV ; break ; case MINUS : if ( low_register_operand ( op0 , SImode ) && low_register_operand ( op1 , SImode ) ) action = CONV ; break ; case MULT : if ( ! optimize_size ) break ; case AND : case IOR : case XOR : if ( rtx_equal_p ( dst , op0 ) && low_register_operand ( op1 , SImode ) ) action = action_for_partial_flag_setting ; else if ( rtx_equal_p ( dst , op1 ) && low_register_operand ( op0 , SImode ) ) action = action_for_partial_flag_setting == SKIP ? SKIP : SWAP_CONV ; break ; case ASHIFTRT : case ASHIFT : case LSHIFTRT : if ( rtx_equal_p ( dst , op0 ) && low_register_operand ( op1 , SImode ) ) action = action_for_partial_flag_setting ; else if ( low_register_operand ( op0 , SImode ) && CONST_INT_P ( op1 ) && IN_RANGE ( INTVAL ( op1 ) , <NUM_LIT> , <NUM_LIT> ) ) action = action_for_partial_flag_setting ; break ; case ROTATERT : if ( rtx_equal_p ( dst , op0 ) && low_register_operand ( op1 , SImode ) ) action = action_for_partial_flag_setting ; break ; case NOT : if ( low_register_operand ( op0 , SImode ) ) action = action_for_partial_flag_setting ; break ; case NEG : if ( low_register_operand ( op0 , SImode ) ) action = CONV ; break ; case CONST_INT : if ( CONST_INT_P ( src ) && IN_RANGE ( INTVAL ( src ) , <NUM_LIT> , <NUM_LIT> ) ) action = action_for_partial_flag_setting ;


<s> EVT <ISA_LIT>ompactTargetLowering :: getSetCCResultType ( EVT VT ) const { return <STR_LIT> ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i + <NUM_LIT> ) ; MIB . addOperand ( MO ) ; } for ( unsigned i = NumOps + <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; MIB . addOperand ( MO ) ; } MachineBasicBlock * MBB = InsertPt -> getParent ( ) ;


<s> return false ; } if ( ! TargetRegisterInfo :: isPhysicalRegister ( SrcReg ) ) { const RegClassOrRegBank & RegClassOrBank = MRI . getRegClassOrRegBank ( SrcReg ) ; const TargetRegisterClass * SrcRC = RegClassOrBank . dyn_cast < const TargetRegisterClass * > ( ) ; const RegisterBank * RB = nullptr ; if ( ! SrcRC ) { RB = RegClassOrBank . get < const RegisterBank * > ( ) ; SrcRC = getRegClassForTypeOnBank ( MRI . getType ( SrcReg ) , * RB , RBI , true ) ; } if ( RC == & <STR_LIT> && SrcRC == & <STR_LIT> ) { unsigned PromoteReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addDef ( PromoteReg ) . addImm ( <NUM_LIT> ) . addUse ( SrcReg ) . addImm ( <STR_LIT> ) ; MachineOperand & RegOp = I . getOperand ( <NUM_LIT> ) ; RegOp . setReg ( PromoteReg ) ; } else if ( RC == & <STR_LIT> && SrcRC == & <STR_LIT> ) { selectFP16CopyFromGPR32 ( I , TII , MRI , SrcReg ) ; }


<s> void <ISA_LIT>SplitDoubleRegs :: collapseRegPairs ( MachineInstr * MI , const UUPairMap & PairMap ) { MachineBasicBlock & B = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) ) continue ; unsigned R = Op . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; if ( MRI -> getRegClass ( R ) != DoubleRC || Op . getSubReg ( ) ) continue ; UUPairMap :: const_iterator F = PairMap . find ( R ) ;

if ( F == PairMap . end ( ) ) continue ;


<s> if ( ! Ptr || isa < UndefValue > ( Ptr ) || isa < Constant > ( Ptr ) || isa < GlobalValue > ( Ptr ) ) return true ; if ( const Argument * Arg = dyn_cast < Argument > ( Ptr ) ) return isArgPassedInSGPR ( Arg ) ; const Instruction * I = dyn_cast < Instruction > ( Ptr ) ; return I && I -> getMetadata ( <STR_LIT> ) ;


<s> bool <STR_LIT> ( unsigned v ) { if ( v == <NUM_LIT> ) return false ;


<s> static __inline vec_double2 spu_slqw ( vec_double2 a , unsigned int count ) {

return ( ( vec_double2 ) ( si_shlqbi ( ( qword ) ( a ) , si_from_uint ( count ) ) ) ) ;


<s> static DecodeStatus DecodeRRRRInstruction ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned d = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s3 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeOperandRegister ( Inst , d , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; status = DecodeOperandRegister ( Inst , s3 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ;

status = DecodeOperandRegister ( Inst , s2 , Address , Decoder ) ;


<s> if ( ! getConstantValueForReg ( IdxReg , MRI , LaneIdx ) ) return false ; unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const RegisterBank & EltRB = * RBI . getRegBank ( EltReg , MRI , TRI ) ; MachineIRBuilder MIRBuilder ( I ) ; if ( VecSize < <NUM_LIT> ) { MachineInstr * ScalarToVec = emitScalarToVector ( VecSize , & <STR_LIT> , SrcReg , MIRBuilder ) ; if ( ! ScalarToVec ) return false ; SrcReg = ScalarToVec -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } MachineInstr * InsMI = emitLaneInsert ( None , SrcReg , EltReg , LaneIdx , EltRB , MIRBuilder ) ; if ( VecSize < <NUM_LIT> ) { unsigned DemoteVec = InsMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = getMinClassForRegBank ( * RBI . getRegBank ( DemoteVec , MRI , TRI ) , VecSize ) ; if ( RC != & <STR_LIT> && RC != & <STR_LIT> ) {


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const {


<s> Register OldReg = MO . getReg ( ) ; if ( MO . isDef ( ) ) { assert ( MI . isInlineAsm ( ) ) ; unsigned LocalId = getLocalId ( Reg2Local , MFI , CurLocal , OldReg ) ; MI . untieRegOperand ( MI . getOperandNo ( & MO ) ) ; MO . ChangeToImmediate ( LocalId ) ; continue ; } if ( MFI . isVRegStackified ( OldReg ) ) { InsertPt = findStartOfTree ( MO , MRI , MFI ) ; continue ; } if ( MI . isInlineAsm ( ) ) { unsigned LocalId = getLocalId ( Reg2Local , MFI , CurLocal , OldReg ) ; MI . untieRegOperand ( MI . getOperandNo ( & MO ) ) ; MO . ChangeToImmediate ( LocalId ) ; continue ; } unsigned LocalId = getLocalId ( Reg2Local , MFI , CurLocal , OldReg ) ; const TargetRegisterClass * RC = MRI . getRegClass ( OldReg ) ; Register NewReg = MRI . createVirtualRegister ( RC ) ; unsigned Opc = getLocalGetOpcode ( RC ) ; InsertPt = BuildMI ( MBB , InsertPt , MI . getDebugLoc ( ) , TII -> get ( Opc ) , NewReg ) . addImm ( LocalId ) ; MO . setReg ( NewReg ) ; MFI . stackifyVReg ( NewReg ) ; Changed = true ; } if ( <STR_LIT> ( MI . getOpcode ( ) ) ) { MRI . replaceRegWith ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . eraseFromParent ( ) ; Changed = true ; } } } MFI . setNumLocals ( CurLocal - MFI . getParams ( ) . size ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MRI . getNumVirtRegs ( ) ; I < E ; ++ I ) { unsigned Reg = Register :: index2VirtReg ( I ) ; auto RL = Reg2Local . find ( Reg ) ; if ( RL == Reg2Local . end ( ) || RL -> second < MFI . getParams ( ) . size ( ) ) continue ; MFI . setLocal ( RL -> second - MFI . getParams ( ) . size ( ) , typeForRegClass ( MRI . getRegClass ( Reg ) ) ) ; Changed = true ; } for ( const MachineBasicBlock & MBB : MF ) { for ( const MachineInstr & MI : MBB ) { if ( MI . isDebugInstr ( ) || MI . isLabel ( ) ) continue ; for ( const MachineOperand & MO : MI . explicit_operands ( ) ) {

assert ( ( ! MO . isReg ( ) || MRI . use_empty ( MO . getReg ( ) ) || MFI . isVRegStackified ( MO . getReg ( ) ) ) && <STR_LIT> ) ;


<s> if ( ( type != <NUM_LIT> && GET_CODE ( ind ) == POST_INC ) || ( type == <NUM_LIT> && GET_CODE ( ind ) == PRE_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ; if ( type == <NUM_LIT> && GET_CODE ( ind ) == POST_MODIFY && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) && REG_P ( XEXP ( ind , <NUM_LIT> ) ) && rtx_equal_p ( XEXP ( ind , <NUM_LIT> ) , XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) ) return true ; if ( type == <NUM_LIT> && GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , <NUM_LIT> ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , <NUM_LIT> ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , <NUM_LIT> ) ) && INTVAL ( XEXP ( ind , <NUM_LIT> ) ) > - <NUM_LIT> && ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) < ( VALID_NEON_QREG_MODE ( GET_MODE ( op ) ) ? <NUM_LIT> : <NUM_LIT> ) ) && ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return TRUE ; return FALSE ;


<s> return hasArithmeticBccFusion ( ) || hasArithmeticCbzFusion ( ) || hasFuseAES ( ) || hasFuseLiterals ( ) ;


<s> return GET_CODE ( x ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( x ) != <NUM_LIT> ;


<s> case <STR_LIT> : if ( RI . hasVGPRs ( NewDstRC ) || NewDstRC == & <STR_LIT> ) return nullptr ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) return nullptr ; return NewDstRC ;


<s> unsigned int execute ( function * ) final override { return remove_partial_avx_dependency ( ) ;


<s> static SDValue LowerF128_FPROUND ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI ) { if ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return Op ; if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPROUND_F128_F64 ) , <NUM_LIT> ) ; if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: FPROUND_F128_F32 ) , <NUM_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ;

return SDValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> assert ( IsPCRel ) ; Type = ELF :: R_NYUZI_BRANCH20 ; break ; case <STR_LIT> : assert ( IsPCRel ) ; Type = ELF :: R_NYUZI_BRANCH25 ; break ; case <STR_LIT> : assert ( ! IsPCRel ) ; Type = ELF :: R_NYUZI_HI19 ; break ; case <STR_LIT> : assert ( ! IsPCRel ) ; Type = ELF :: R_NYUZI_IMM_LO13 ; break ; case <STR_LIT> : assert ( ! IsPCRel ) ;


<s> if ( isa < ConstantInt > ( LHS ) && ! isa < ConstantInt > ( RHS ) ) std :: swap ( LHS , RHS ) ; unsigned Opc ; if ( ISDOpc == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( ISDOpc == <STR_LIT> ) { Opc = <STR_LIT> ; } else if ( ISDOpc == <STR_LIT> ) { Opc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; if ( ! ResultReg ) return <NUM_LIT> ; unsigned RHSReg ;


<s> return <STR_LIT> + std :: to_string ( Attributes . size ( ) ) + <STR_LIT> ;


<s> static bool ia64_vms_valid_pointer_mode ( scalar_int_mode mode ) {

return ( mode == SImode || mode == DImode ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> bool <ISA_LIT>Subtarget :: isPositionIndependent ( ) const {


<s> getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) { unsigned Reg = MO . getReg ( ) ; unsigned RegNo = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Reg ) ; return RegNo ; } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ; } else if ( MO . isFPImm ( ) ) {

return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ;


<s> FrameInfo . setStackID ( FrameIndex , <STR_LIT> ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine | RegState :: Dead ) ; } return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillSaveOpcode ( SpillSize ) ; MFI -> setHasSpilledVGPRs ( ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> assert ( Symbol -> isUndefined ( ) && <STR_LIT> ) ; assert ( getCurrentSection ( ) . first && <STR_LIT> ) ;

AssignSection ( Symbol , getCurrentSection ( ) . first ) ;


<s> bool isVoidFunc = ( F -> getReturnType ( ) -> getTypeID ( ) == Type :: VoidTyID ) ; if ( isVoidFunc ) ReservedFrameCount = NumArgs ; else ReservedFrameCount = NumArgs + <NUM_LIT> ;


<s> unsigned Reg = MO . getReg ( ) ; if ( Reg == AMDGPU :: ALU_CONST ) { unsigned Sel = MI -> getOperand ( getOperandIdx ( MI -> getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) . getImm ( ) ; Result . push_back ( std :: pair < MachineOperand * , int64_t > ( & MO , Sel ) ) ; continue ; } } return Result ; } static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { AMDGPU :: OpName :: src0 , AMDGPU :: OpName :: src0_sel } , { AMDGPU :: OpName :: src1 , AMDGPU :: OpName :: src1_sel } , { AMDGPU :: OpName :: src2 , AMDGPU :: OpName :: src2_sel } , } ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { int SrcIdx = getOperandIdx ( MI -> getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ; if ( SrcIdx < <NUM_LIT> ) break ; MachineOperand & MO = MI -> getOperand ( SrcIdx ) ; unsigned Reg = MI -> getOperand ( SrcIdx ) . getReg ( ) ; if ( Reg == AMDGPU :: ALU_CONST ) { unsigned Sel = MI -> getOperand ( getOperandIdx ( MI -> getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) . getImm ( ) ; Result . push_back ( std :: pair < MachineOperand * , int64_t > ( & MO , Sel ) ) ; continue ; } if ( Reg == AMDGPU :: ALU_LITERAL_X ) { unsigned Imm = MI -> getOperand ( getOperandIdx ( MI -> getOpcode ( ) , AMDGPU :: OpName :: literal ) ) . getImm ( ) ; Result . push_back ( std :: pair < MachineOperand * , int64_t > ( & MO , Imm ) ) ; continue ; } Result . push_back ( std :: pair < MachineOperand * , int64_t > ( & MO , <NUM_LIT> ) ) ;


<s> static rtx m68k_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) {

return gen_rtx_REG ( Pmode , M68K_STRUCT_VALUE_REGNUM ) ;


<s> if ( <STR_LIT> ( Opc ) ) { result |= VADDR ; } if ( <STR_LIT> ( Opc ) ) { result |= SRSRC ; } if ( <STR_LIT> ( Opc ) ) { result |= SOFFSET ; } return result ; } if ( TII . isMIMG ( Opc ) ) { unsigned result = VADDR | SRSRC ; const <STR_LIT> * Info = <STR_LIT> ( Opc ) ; if ( Info && <STR_LIT> ( Info -> BaseOpcode ) -> Sampler ) result |= SSAMP ; return result ; } if ( TII . isMTBUF ( Opc ) ) { unsigned result = <NUM_LIT> ; if ( <STR_LIT> ( Opc ) ) { result |= VADDR ; } if ( <STR_LIT> ( Opc ) ) { result |= SRSRC ; } if ( <STR_LIT> ( Opc ) ) { result |= SOFFSET ; } return result ; } switch ( Opc ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SBASE ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ADDR ; }


<s> if ( CM ) return * CM ; return CodeModel :: Medium ;