<s> void LinearizedRegion :: replaceRegisterOutsideRegion ( unsigned Register , unsigned NewRegister , bool IncludeLoopPHIs , MachineRegisterInfo * MRI ) { replaceRegister ( Register , NewRegister , MRI , false , true , IncludeLoopPHIs ) ;


<s> IncomingArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , CCAssignFn * AssignFn ) : ValueHandler ( MIRBuilder , MRI , AssignFn ) , StackUsed ( <NUM_LIT> ) {


<s> if ( mode == SFmode || mode == DFmode ) { if ( TARGET_HARD_FLOAT ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else if ( mode == DImode ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } else { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } return false ; } case NEG : { if ( mode == DImode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return false ; } case MULT : { if ( mode == SFmode ) { if ( TARGET_HARD_FLOAT ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else if ( ! TARGET_SOFT_MUL ) { if ( MICROBLAZE_VERSION_COMPARE ( microblaze_select_cpu , <STR_LIT> ) >= <NUM_LIT> ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; } case DIV : case UDIV : { if ( mode == SFmode ) { if ( TARGET_HARD_FLOAT ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; }


<s> if ( MO . isImplicit ( ) ) return false ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_RegisterMask : return false ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = lowerSymbolOperand ( MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = lowerSymbolOperand ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ;


<s> if ( MO . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( MO . getReg ( ) ) ) MI = MRI . getUniqueVRegDef ( MO . getReg ( ) ) ; if ( ! MI || MI -> getParent ( ) != & MBB || ( unsigned ) MI -> getOpcode ( ) != MulOpc ) return false ; assert ( MI -> getNumOperands ( ) >= <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ;

if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != ZeroReg ) return false ;


<s> bool isLegalMaskedGather ( Type * DataType , Align Alignment ) {

return isLegalMaskedGatherScatter ( DataType , Alignment ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; break ; } switch ( Opcode ) { default : return Fail ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsDisjointWritebackTransfer = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedsDisjointWritebackTransfer = true ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR128RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR128RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR64RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : DecodeFPR32RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeFPR32RegisterClass ( Inst , Rt2 , Addr , Decoder ) ; break ; } DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( offset ) ) ;

if ( IsLoad && Rt == Rt2 ) return SoftFail ;


<s> return ( uint16x8_t ) __builtin_neon_vcgev8hi ( __a , __b ) ;


<s> MCInst Inst ; Inst . setLoc ( IDLoc ) ; unsigned MatchResult = MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ; switch ( MatchResult ) { case Match_Success : { ensureLocals ( Out ) ; auto Align = <STR_LIT> ( Inst . getOpcode ( ) ) ; if ( Align != - <NUM_LIT> ) { auto & Op0 = Inst . getOperand ( <NUM_LIT> ) ; if ( Op0 . getImm ( ) == - <NUM_LIT> ) Op0 . setImm ( Align ) ; }

Out . emitInstruction ( Inst , getSTI ( ) ) ;


<s> if ( testing_p ) { op0 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; op1 = gen_raw_REG ( vmode , LAST_VIRTUAL_REGISTER + <NUM_LIT> ) ; } if ( rs6000_expand_vec_perm_const_1 ( target , op0 , op1 , sel [ <NUM_LIT> ] , sel [ <NUM_LIT> ] ) ) return true ; } if ( TARGET_ALTIVEC ) {

if ( vmode != V16QImode ) return false ;


<s> bool useIndirectThunkCalls ( ) const { return useRetpolineIndirectCalls ( ) || useLVIControlFlowIntegrity ( ) ;


<s> FunctionPass * llvm :: createMVEVPTOptimisationsPass ( ) { return new MVEVPTOptimisations ( ) ;


<s> OutStreamer . AddBlankLine ( ) ; for ( unsigned j = <NUM_LIT> ; j < Items . size ( ) ; j ++ ) OutStreamer . EmitRawText ( MAI -> getGlobalDirective ( ) + Twine ( Mang -> getSymbol ( Items [ j ] ) -> getName ( ) ) ) ; OutStreamer . AddComment ( <STR_LIT> ) ;


<s> unsigned <ISA_LIT>InstrInfo :: reversePrediction ( unsigned Opcode ) const { int PredRevOpcode = - <NUM_LIT> ; if ( isPredictedTaken ( Opcode ) ) PredRevOpcode = <STR_LIT> ( Opcode ) ; else PredRevOpcode = <STR_LIT> ( Opcode ) ; assert ( PredRevOpcode > <NUM_LIT> ) ;


<s> unsigned getPointerWidth ( ) { if ( is16BitMode ( ) ) return <NUM_LIT> ;

if ( is32BitMode ( ) ) return <NUM_LIT> ;


<s> ssize_t n ; n = read ( fd , buf , sizeof ( buf ) ) ; close ( fd ) ; if ( n > <NUM_LIT> ) { for ( av = ( ElfW ( auxv_t ) * ) buf ; av -> a_type != AT_NULL ; ++ av ) switch ( av -> a_type ) { case AT_PLATFORM : return ( const char * ) av -> a_un . a_val ; default : break ; } }


<s> FnHasLiveInYmm = checkFnHasLiveInYmm ( MRI ) ; assert ( BBState . empty ( ) ) ; BBState . resize ( MF . getNumBlockIDs ( ) , <NUM_LIT> ) ; BBSolved . resize ( MF . getNumBlockIDs ( ) , <NUM_LIT> ) ; while ( <NUM_LIT> ) { bool MadeChange = false ;

for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) MadeChange |= processBasicBlock ( MF , * I ) ;


<s> if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;

else if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ;


<s> return Cost ; } if ( ST -> hasNEON ( ) && ValTy -> isVectorTy ( ) && ISD == <STR_LIT> && CondTy ) { static const TypeConversionCostTblEntry NEONVectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; EVT SelCondTy = TLI -> getValueType ( DL , CondTy ) ; EVT SelValTy = TLI -> getValueType ( DL , ValTy ) ; if ( SelCondTy . isSimple ( ) && SelValTy . isSimple ( ) ) { if ( const auto * Entry = ConvertCostTableLookup ( NEONVectorSelectTbl , ISD , SelCondTy . getSimpleVT ( ) , SelValTy . getSimpleVT ( ) ) ) return Entry -> Cost ; } std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ; return LT . first ; }


<s> bool hasSEL2 ( ) const { return HasSEL2 ;


<s> return restricted ? std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) : std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ; if ( ! Res . second ) { unsigned Size = Constraint . size ( ) ; if ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && Constraint [ <NUM_LIT> ] == '{' && tolower ( Constraint [ <NUM_LIT> ] ) == 'v' && Constraint [ Size - <NUM_LIT> ] == '}' ) { int RegNo ; bool Failed = Constraint . slice ( <NUM_LIT> , Size - <NUM_LIT> ) . getAsInteger ( <NUM_LIT> , RegNo ) ;

if ( ! Failed && RegNo >= <NUM_LIT> && RegNo <= <NUM_LIT> ) {


<s> for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && IsCallReturnTwice ( I -> getOperand ( <NUM_LIT> ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) { for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( MBB . isEHPad ( ) ) { if ( I -> isDebugInstr ( ) ) continue ; Changed |= addENDBR ( MBB , I ) ; break ; } else if ( I -> isEHLabel ( ) ) {

MCSymbol * Sym = I -> getOperand ( <NUM_LIT> ) . getMCSymbol ( ) ;


<s> switch ( Opc ) { default : Op . getNode ( ) -> dumpr ( & DAG ) ; if ( Opc > <STR_LIT> && Opc < <STR_LIT> ) errs ( ) << <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerCONCAT_VECTORS ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVECTOR_SHIFT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ;

case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ;


<s> bool EnableOpt = getOptLevel ( ) > CodeGenOpt :: None ; bool Internalize = InternalizeSymbols ; bool EarlyInline = EarlyInlineAll && EnableOpt && ! EnableFunctionCalls ; bool <ISA_LIT>AA = Enable<ISA_LIT>AliasAnalysis && EnableOpt ; bool LibCallSimplify = EnableLibCallSimplify && EnableOpt ; if ( EnableFunctionCalls ) { delete Builder . Inliner ; Builder . Inliner = createFunctionInliningPass ( ) ; } Builder . addExtension ( PassManagerBuilder :: EP_ModuleOptimizerEarly , [ Internalize , EarlyInline , <ISA_LIT>AA , this ] ( const PassManagerBuilder & , legacy :: PassManagerBase & PM ) { if ( <ISA_LIT>AA ) { PM . add ( create<ISA_LIT>AAWrapperPass ( ) ) ;

PM . add ( create<ISA_LIT>ExternalAAWrapperPass ( ) ) ;


return SelectSMRD ( Addr , SBase , Offset , Imm ) && ! Imm && ! isa < ConstantSDNode > ( Offset ) ;


<s> lowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { if ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ) {

DAG . getContext ( ) -> emitError ( <STR_LIT> ) ;


<s> std :: string Comment ; auto GetRegisterName = [ ] ( unsigned RegNum ) -> StringRef { return <ISA_LIT>ATTInstPrinter :: getRegisterName ( RegNum ) ; } ; StringRef DstName = DstOp . isReg ( ) ? GetRegisterName ( DstOp . getReg ( ) ) : <STR_LIT> ; StringRef SrcName = SrcOp . isReg ( ) ? GetRegisterName ( SrcOp . getReg ( ) ) : <STR_LIT> ; raw_string_ostream CS ( Comment ) ; CS << DstName << <STR_LIT> ;


<s> SDNode * Lo = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Imm & <NUM_LIT> , DL , <STR_LIT> ) ) ; SDNode * Hi = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Imm >> <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << MFI . getStackSize ( ) << <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ; if ( MFI . hasStackObjects ( ) ) { int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlignment ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; DEBUG ( dbgs ( ) << <STR_LIT> << RegScavFI << <STR_LIT> ) ;


<s> llvm :: drop_begin ( OldMI . operands ( ) , Desc . getNumOperands ( ) ) ) { assert ( MO . isReg ( ) && MO . getReg ( ) ) ; if ( MO . isUse ( ) ) UseMI . add ( MO ) ;


<s> unsigned isExtendable = ( F >> <STR_LIT> ) & <STR_LIT> ; if ( ! isExtendable ) return false ; short ExtOpNum = getCExtOpNum ( MI ) ; const MachineOperand & MO = MI -> getOperand ( ExtOpNum ) ; if ( MO . getTargetFlags ( ) && <STR_LIT> ) return true ; if ( MO . isMBB ( ) ) return false ; if ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isBlockAddress ( ) || MO . isJTI ( ) || MO . isCPI ( ) ) return true ;

assert ( MO . isImm ( ) && <STR_LIT> ) ;


<s> <ISA_LIT>ExceptionChecker ( JNIEnv * jenv ) : env ( jenv ) {


<s> static SDValue lowerVectorShuffleAsRotate ( const SDLoc & DL , MVT VT , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( ( VT . getScalarType ( ) == <STR_LIT> || VT . getScalarType ( ) == <STR_LIT> ) && <STR_LIT> ) ;

assert ( ( Subtarget . hasVLX ( ) || ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) ) ) && <STR_LIT> ) ;


<s> assert ( FIST . getNode ( ) && <STR_LIT> ) ;

if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> if ( MFI . isFrameBaseVirtual ( ) && MFI . getFrameBaseVreg ( ) == Reg ) MFI . clearFrameBaseVreg ( ) ; } else if ( shouldRematerialize ( * DefI , AA , TII ) ) { Insert = rematerializeCheapDef ( Reg , Use , * DefI , MBB , Insert -> getIterator ( ) , LIS , MFI , MRI , TII , TRI ) ; } else if ( CanMove && oneUseDominatesOtherUses ( Reg , Use , MBB , MRI , MDT , LIS , MFI ) ) { Insert = moveAndTeeForMultiUse ( Reg , Use , DefI , MBB , Insert , LIS , MFI , MRI , TII ) ; } else { if ( ! CanMove && SameBlock ) Commuting . maybeCommute ( Insert , TreeWalker , TII ) ; continue ; } auto * SubsequentDef = Insert -> defs ( ) . begin ( ) ; auto * SubsequentUse = & Use ; while ( SubsequentDef != Insert -> defs ( ) . end ( ) && SubsequentUse != Use . getParent ( ) -> uses ( ) . end ( ) ) { if ( ! SubsequentDef -> isReg ( ) || ! SubsequentUse -> isReg ( ) ) break ; unsigned DefReg = SubsequentDef -> getReg ( ) ; unsigned UseReg = SubsequentUse -> getReg ( ) ; if ( DefReg != UseReg || ! MRI . hasOneUse ( DefReg ) ) break ; MFI . stackifyVReg ( MRI , DefReg ) ; ++ SubsequentDef ; ++ SubsequentUse ; } if ( Insert -> getOpcode ( ) == TargetOpcode :: IMPLICIT_DEF ) convertImplicitDefToConstZero ( Insert , MRI , TII , MF , LIS ) ; Commuting . reset ( ) ; TreeWalker . pushOperands ( Insert ) ; } if ( Insert != & * MII ) { imposeStackOrdering ( & * MII ) ; MII = MachineBasicBlock :: iterator ( Insert ) . getReverse ( ) ; Changed = true ; } } } if ( Changed ) { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; for ( MachineBasicBlock & MBB : MF ) MBB . addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > Stack ;


<s> ReferenceMap :: iterator F = Map . find ( RR . Reg ) ; if ( F == Map . end ( ) ) return false ; unsigned Mask = getMaskForSub ( RR . Sub ) | Exec ; if ( Mask & F -> second ) return true ; return false ;


<s> return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( HRI . getRARegister ( ) , getRegClassFor ( <STR_LIT> ) ) ;

return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Reg , VT ) ;


<s> MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm ( MII , MRI , Src0 , Src0RC , <STR_LIT> , Src0SubRC ) ; unsigned DestSub1 = MRI . createVirtualRegister ( DestSubRC ) ; MachineInstr * HiHalf = BuildMI ( MBB , MII , DL , InstDesc , DestSub1 ) . addOperand ( SrcReg0Sub1 ) ; unsigned FullDestReg = MRI . createVirtualRegister ( DestRC ) ; BuildMI ( MBB , MII , DL , get ( TargetOpcode :: REG_SEQUENCE ) , FullDestReg ) . addReg ( DestSub0 ) . addImm ( <STR_LIT> ) . addReg ( DestSub1 ) . addImm ( <STR_LIT> ) ; MRI . replaceRegWith ( Dest . getReg ( ) , FullDestReg ) ; Worklist . push_back ( LoHalf ) ;


<s> vrsqrteq_f32 ( float32x4_t a ) { float32x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result ;


<s>
RefMap
&
LOX
=
PhiLOX
[
PrA
.
Addr
->
getCode
(
)
]
;
for
(
const
std
::
pair
<
RegisterId
,
NodeRefSet
>
&
RS
:
RUs
)
{
for
(
std
::
pair
<
NodeId
,
LaneBitmask
>
P
:
RS
.
second
)
{
RegisterRef
S
(
RS
.
first
,
P
.
second
)
;
NodeList
Ds
=
getAllReachingDefs
(
S
,
PUA
,
true
,
false
,
NoRegs
)
;
for
(
NodeAddr
<
DefNode
*
>
D
:
Ds
)
{
RegisterAggr
TA
(
PRI
)
;
TA
.
insert
(
D
.
Addr
->
getRegRef
(
DFG
)
)
.
intersect
(
S
)
;
LaneBitmask
TM
=
TA
.
makeRegRef
(
)
.
Mask
;
LOX
[
S
.
Reg
]
.
insert
(
{
D
.
Id
,
TM
}
)
;
}
}
}
for
(
NodeAddr
<
PhiUseNode
*
>
T
:
DFG
.
getRelatedRefs
(
PA
,
PUA
)
)
SeenUses
.
insert
(
T
.
Id
)
;
}
}
}
if
(
Trace
)
{
dbgs
(
)
<<
<STR_LIT>
;
for
(
auto
&
I
:
PhiLOX
)
dbgs
(
)
<<
<STR_LIT>
<<
I
.
first
->
getNumber
(
)
<<
<STR_LIT>
<<
Print
<
RefMap
>
(
I
.
second
,
DFG
)
<<
'\n'
;
}
RefMap
LiveIn
;
traverse
(
&
MF
.
front
(
)
,
LiveIn
)
;
LiveMap
[
&
MF
.
front
(
)
]
.
insert
(
DFG
.
getLiveIns
(
)
)
;
if
(
Trace
)
{
for
(
MachineBasicBlock
&
B
:
MF
)
{
std
::
vector
<
RegisterRef
>
LV
;
for
(
auto
I
=
B
.
livein_begin
(
)
,
E
=
B
.
livein_end
(
)
;
I
!=
E
;
++
I
)
LV
.
push_back
(
RegisterRef
(
I
->
PhysReg
,
I
->
LaneMask
)
)
;
llvm
::
sort
(
LV
.
begin
(
)
,
LV
.
end
(
)
)
;
dbgs
(
)
<<
printMBBReference
(
B
)
<<
<STR_LIT>
;
for
(
auto
I
:
LV
)
dbgs
(
)
<<
' '
<<
Print
<
RegisterRef
>
(
I
,
DFG
)
;
dbgs
(
)
<<
<STR_LIT>
;
LV
.
clear
(
)
;
const
RegisterAggr
&
LG
=
LiveMap
[
&
B
]
;
for
(
auto
I
=
LG
.
rr_begin
(
)
,
E
=
LG
.
rr_end
(
)
;
I
!=
E
;
++
I
)
LV
.
push_back
(
*
I
)
;
llvm
::
sort
(
LV
.
begin
(
)
,
LV
.
end
(
)
)
;
dbgs
(
)
<<
<STR_LIT>
;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { if ( Subtarget -> is64Bit ( ) ) return LowerReturn_64 ( Chain , CallConv , IsVarArg , Outs , OutVals , DL , DAG ) ; return LowerReturn_32 ( Chain , CallConv , IsVarArg , Outs , OutVals , DL , DAG ) ;


<s> unsigned NumWords = numWords ( ) ; <ISA_LIT>InstructionBuffer MaskBuffer ( Mask . begin ( ) , Mask . begin ( ) + NumWords ) ; <ISA_LIT>InstructionBuffer ValueBuffer ( Value . begin ( ) , Value . begin ( ) + NumWords ) ; <ISA_LIT>InstructionLookup Ret ; Ret . OpCode = OpCode ; Ret . Mask = MaskBuffer ; Ret . Value = ValueBuffer ;


<s> if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) return false ; if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; R1 = Addr . getOperand ( <NUM_LIT> ) ; R2 = Addr . getOperand ( <NUM_LIT> ) ; return true ; } R1 = Addr ; R2 = CurDAG -> getRegister ( <STR_LIT> , getTargetLowering ( ) -> getPointerTy ( ) ) ;


<s> if ( Subtarget . hasCMov ( ) ) if ( SDValue RV = combineIntegerAbs ( N , DAG ) ) return RV ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( isFNEG ( N ) ) return combineFneg ( N , DAG , Subtarget ) ; return SDValue ( ) ;


<s> int <ISA_LIT>AsmParser :: matchRegisterByNumber ( unsigned RegNum , StringRef Mnemonic ) { if ( RegNum > <NUM_LIT> ) return - <NUM_LIT> ;


<s> return __builtin_ia32_movmskps ( ( __v4sf ) __A ) ;


<s> for ( Function :: iterator it = F -> begin ( ) , ie = F -> end ( ) ; it != ie ; ++ it ) { BasicBlock * B = it ; if ( strcmp ( B -> getName ( ) . data ( ) , blockName ) == <NUM_LIT> ) { B -> dump ( ) ; return ; } }


<s> NodeList CodeNode :: members ( const DataFlowGraph & G ) const {

static auto True = [ ] ( NodeAddr < NodeBase * > ) -> bool { return true ; } ;


<s> MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( Reg != FoldAsLoadDefReg ) continue ; if ( MO . getSubReg ( ) || MO . isDef ( ) || FoundSrcOperand ) return <NUM_LIT> ; SrcOperandId = i ; FoundSrcOperand = true ; } if ( ! FoundSrcOperand ) return <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > Ops ; Ops . push_back ( SrcOperandId ) ; MachineInstr * FoldMI = foldMemoryOperand ( MI , Ops , DefMI ) ; if ( FoldMI ) { FoldAsLoadDefReg = <NUM_LIT> ; return FoldMI ; } if ( Idx == <NUM_LIT> ) { commuteInstruction ( MI , false ) ; return <NUM_LIT> ; } if ( MI -> isCommutable ( ) ) { MachineInstr * NewMI = commuteInstruction ( MI , false ) ; if ( ! NewMI ) return <NUM_LIT> ; if ( NewMI != MI ) { NewMI -> eraseFromParent ( ) ; return <NUM_LIT> ; } }


<s> unsigned SecondOpcode = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; return expandAuipcInstPair ( MBB , MBBI , NextMBBI , <STR_LIT> , SecondOpcode ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> return ggc_cleared_alloc < machine_function > ( ) ;


<s> default : break ; case <STR_LIT> : case <STR_LIT> : DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; DAG . ComputeMaskedBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero2 , KnownOne2 , Depth + <NUM_LIT> ) ;

assert ( ( KnownZero & KnownOne ) == <NUM_LIT> && <STR_LIT> ) ;


<s> return ( uint32x4_t ) __builtin_neon_vreinterpretv4siv4sf ( __a ) ;


<s> case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : AccessSize = <NUM_LIT> ; break ; default : return ; } const bool IsWrite = MII . get ( Inst . getOpcode ( ) ) . mayStore ( ) ;

for ( unsigned Ix = <NUM_LIT> ; Ix < Operands . size ( ) ; ++ Ix ) {


<s> bool <ISA_LIT>HazardRecognizer :: ShouldPreferAnother ( SUnit * SU ) { return UsesDotCur && ( ( SU == UsesDotCur ) ^ ( DotCurPNum == ( int ) PacketNum ) ) ;


<s> assert ( <STR_LIT> == <NUM_LIT> && <STR_LIT> ) ; unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineOperand & Base = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Scale = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Index = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Disp = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Segment = MI -> getOperand ( <NUM_LIT> ) ; unsigned ArgSize = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ArgMode = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Align = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( MI -> hasOneMemOperand ( ) && <STR_LIT> ) ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; const TargetInstrInfo * TII = MBB -> getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * AddrRegClass = getRegClassFor ( <STR_LIT> ) ; const TargetRegisterClass * OffsetRegClass = getRegClassFor ( <STR_LIT> ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned TotalNumIntRegs = <NUM_LIT> ; unsigned TotalNumXMMRegs = <NUM_LIT> ; bool UseGPOffset = ( ArgMode == <NUM_LIT> ) ; bool UseFPOffset = ( ArgMode == <NUM_LIT> ) ; unsigned MaxOffset = TotalNumIntRegs * <NUM_LIT> + ( UseFPOffset ? TotalNumXMMRegs * <NUM_LIT> : <NUM_LIT> ) ; unsigned ArgSizeA8 = ( ArgSize + <NUM_LIT> ) & ~ <NUM_LIT> ; bool NeedsAlign = ( Align > <NUM_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * overflowMBB ; MachineBasicBlock * offsetMBB ; MachineBasicBlock * endMBB ; unsigned OffsetDestReg = <NUM_LIT> ; unsigned OverflowDestReg = <NUM_LIT> ; unsigned OffsetReg = <NUM_LIT> ; if ( ! UseGPOffset && ! UseFPOffset ) { OffsetDestReg = <NUM_LIT> ; OverflowDestReg = DestReg ; offsetMBB = nullptr ; overflowMBB = thisMBB ; endMBB = thisMBB ; } else { OffsetDestReg = MRI . createVirtualRegister ( AddrRegClass ) ; OverflowDestReg = MRI . createVirtualRegister ( AddrRegClass ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ;

MachineFunction * MF = MBB -> getParent ( ) ;


<s> <STR_LIT> <STR_LIT> ( <STR_LIT> Opcode ) { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Address ; case <STR_LIT> : return SP ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( TheTriple . isOSDarwin ( ) ) return new <ISA_LIT>MCAsmInfoDarwin ( ) ; <ISA_LIT>ELFMCAsmInfo * MAI = new <ISA_LIT>ELFMCAsmInfo ( ) ;


<s> case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && ! Subtarget -> hasFP32Denormals ( ) ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { SDValue A = LHS . getOperand ( <NUM_LIT> ) ; if ( A == LHS . getOperand ( <NUM_LIT> ) ) { const SDValue Two = DAG . getConstantFP ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue NegRHS = DAG . getNode ( <STR_LIT> , DL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Two , A , NegRHS ) ; } } if ( RHS . getOpcode ( ) == <STR_LIT> ) { SDValue A = RHS . getOperand ( <NUM_LIT> ) ; if ( A == RHS . getOperand ( <NUM_LIT> ) ) { const SDValue NegTwo = DAG . getConstantFP ( - <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NegTwo , A , LHS ) ; } } return SDValue ( ) ; } break ; } } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( DCI . isBeforeLegalize ( ) ) break ; MemSDNode * MemNode = cast < MemSDNode > ( N ) ; SDValue Ptr = MemNode -> getBasePtr ( ) ;

unsigned AS = MemNode -> getAddressSpace ( ) ;


<s> assert ( LI -> weight == <NUM_LIT> ) ; LI -> weight = computeWeight ( MRI , MBFI , VReg ) ; DEBUG ( LI -> dump ( ) ) ; SortedIntervals . push_back ( LI ) ; } DEBUG ( dbgs ( ) << '\n' ) ; llvm :: sort ( SortedIntervals . begin ( ) , SortedIntervals . end ( ) , [ MRI ] ( LiveInterval * LHS , LiveInterval * RHS ) { if ( MRI -> isLiveIn ( LHS -> reg ) != MRI -> isLiveIn ( RHS -> reg ) ) return MRI -> isLiveIn ( LHS -> reg ) ; if ( LHS -> weight != RHS -> weight ) return LHS -> weight > RHS -> weight ; if ( LHS -> empty ( ) || RHS -> empty ( ) ) return ! LHS -> empty ( ) && RHS -> empty ( ) ; return * LHS < * RHS ; } ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SmallVector < unsigned , <NUM_LIT> > SlotMapping ( SortedIntervals . size ( ) , - <NUM_LIT> ) ; SmallVector < SmallVector < LiveInterval * , <NUM_LIT> > , <NUM_LIT> > Assignments ( SortedIntervals . size ( ) ) ; BitVector UsedColors ( SortedIntervals . size ( ) ) ; bool Changed = false ; for ( size_t i = <NUM_LIT> , e = SortedIntervals . size ( ) ; i < e ; ++ i ) { LiveInterval * LI = SortedIntervals [ i ] ; unsigned Old = LI -> reg ; size_t Color = i ; const TargetRegisterClass * RC = MRI -> getRegClass ( Old ) ; if ( ! MRI -> isLiveIn ( Old ) ) for ( unsigned C : UsedColors . set_bits ( ) ) { if ( MRI -> getRegClass ( SortedIntervals [ C ] -> reg ) != RC ) continue ; for ( LiveInterval * OtherLI : Assignments [ C ] ) if ( ! OtherLI -> empty ( ) && OtherLI -> overlaps ( * LI ) ) goto continue_outer ; Color = C ; break ; continue_outer : ; } unsigned New = SortedIntervals [ Color ] -> reg ; SlotMapping [ i ] = New ;


<s> virtual ~ <ISA_LIT>Disassembler ( ) {


<s> const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>BaseInstrInfo & TII = * static_cast < const <ISA_LIT>BaseInstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ! LastMI -> isBarrier ( ) && ! ( TII . getSubtarget ( ) . isLikeA9 ( ) && LastMI -> mayLoadOrStore ( ) ) && ( LastMCID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ;

if ( I != LastMI -> getParent ( ) -> begin ( ) ) {


<s> if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; EVT VT = Extract -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( ! VT . isSimple ( ) || ! ( VT . getVectorElementType ( ) . getSizeInBits ( ) > <NUM_LIT> ) ) return SDValue ( ) ; unsigned RegSize = <NUM_LIT> ; if ( Subtarget . hasBWI ( ) ) RegSize = <NUM_LIT> ; else if ( Subtarget . hasAVX2 ( ) ) RegSize = <NUM_LIT> ; if ( RegSize / VT . getVectorNumElements ( ) < <NUM_LIT> ) return SDValue ( ) ; unsigned BinOp = <NUM_LIT> ; SDValue Root = matchBinOpReduction ( Extract , BinOp , { <STR_LIT> } ) ; if ( Root && ( Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> || Root . getOpcode ( ) == <STR_LIT> ) ) Root = Root . getOperand ( <NUM_LIT> ) ; if ( ! Root || ( Root . getOpcode ( ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Zext0 , Zext1 ; if ( ! detectZextAbsDiff ( Root , Zext0 , Zext1 ) ) return SDValue ( ) ; SDLoc DL ( Extract ) ; SDValue SAD = createPSADBW ( DAG , Zext0 , Zext1 , DL ) ; unsigned Stages = Log2_32 ( VT . getVectorNumElements ( ) ) ; MVT SadVT = SAD . getSimpleValueType ( ) ; if ( Stages > <NUM_LIT> ) { unsigned SadElems = SadVT . getVectorNumElements ( ) ; for ( unsigned i = Stages - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { SmallVector < int , <NUM_LIT> > Mask ( SadElems , - <NUM_LIT> ) ; for ( unsigned j = <NUM_LIT> , MaskEnd = <NUM_LIT> << ( i - <NUM_LIT> ) ; j < MaskEnd ; ++ j ) Mask [ j ] = MaskEnd + j ;

SDValue Shuffle = DAG . getVectorShuffle ( SadVT , DL , SAD , DAG . getUNDEF ( SadVT ) , Mask ) ;


<s> static unsigned FirstRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned FirstReg = FirstRegs [ NumRegs - <NUM_LIT> ] ;

Inst . addOperand ( MCOperand :: CreateReg ( FirstReg + getVectorListStart ( ) - <STR_LIT> ) ) ;


<s> static bool isAddCarryChain ( SDValue Carry ) { while ( Carry . getOpcode ( ) == <STR_LIT> ) Carry = Carry . getOperand ( <NUM_LIT> ) ; return Carry . getOpcode ( ) == <STR_LIT> ;


<s> addr = XEXP ( mem , <NUM_LIT> ) ; switch ( GET_CODE ( addr ) ) { case PRE_DEC : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = reg ; break ; case POST_INC : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = XEXP ( addr , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = reg ; break ; default : templ = <STR_LIT> ; ops [ <NUM_LIT> ] = reg ; ops [ <NUM_LIT> ] = mem ; break ;


<s> MVT SPTy = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result ; if ( ! Lower ) { const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned SPReg = TLI . getStackPointerRegisterToSaveRestore ( ) ; assert ( SPReg && <STR_LIT> <STR_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; const TargetFrameLowering & TFI = * Subtarget . getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Result = DAG . getNode ( <STR_LIT> , dl , VT , SP , Size ) ; if ( Align > StackAlign ) Result = DAG . getNode ( <STR_LIT> , dl , VT , Result , DAG . getConstant ( - ( uint64_t ) Align , dl , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Result ) ; } else if ( SplitStack ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function & F = MF . getFunction ( ) ; for ( const auto & A : F . args ( ) ) { if ( A . hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; }


<s> Value * <ISA_LIT>IREmitter :: visitVSHLI ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> MVT <ISA_LIT>TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT . isVector ( ) ) { if ( Subtarget . isABI_O32 ( ) ) { return <STR_LIT> ; } else { return ( VT . getSizeInBits ( ) == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; }


<s> void ft32_expand_epilogue ( void ) { int regno ; int pretend = crtl -> args . pretend_args_size ; if ( ! must_link ( ) && ( cfun -> machine -> size_for_adjusting_sp == <NUM_LIT> ) && ( cfun -> machine -> callee_saved_reg_size == <NUM_LIT> ) ) { emit_jump_insn ( gen_returner24 ( ) ) ; return ; } int epilog24 = ( ! must_link ( ) && ( cfun -> machine -> size_for_adjusting_sp == <NUM_LIT> ) && optimize_size ) ; if ( must_link ( ) ) { emit_insn ( gen_unlink ( ) ) ; }

else if ( ! epilog24 && ( cfun -> machine -> size_for_adjusting_sp > <NUM_LIT> ) ) {


<s> if ( ! Subtarget . is64Bit ( ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> || Src . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; switch ( Src . getOpcode ( ) ) { default : return SDValue ( ) ; case <STR_LIT> : if ( ! Subtarget . hasStdExtM ( ) ) return SDValue ( ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : break ; } if ( none_of ( N -> uses ( ) , [ ] ( SDNode * User ) { return User -> getOpcode ( ) == <STR_LIT> ; } ) ) return SDValue ( ) ; SmallVector < SDNode * , <NUM_LIT> > SetCCs ; for ( SDNode :: use_iterator UI = Src . getNode ( ) -> use_begin ( ) , UE = Src . getNode ( ) -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( User == N ) continue ; if ( UI . getUse ( ) . getResNo ( ) != Src . getResNo ( ) ) continue ; if ( User -> getOpcode ( ) == <STR_LIT> ) { SetCCs . push_back ( User ) ; continue ; } break ; } if ( SetCCs . empty ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue SExt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; DCI . CombineTo ( N , SExt ) ;


<s> int mmix_shiftable_wyde_value ( unsigned HOST_WIDEST_INT value ) { int i ; int has_candidate = <NUM_LIT> ;

for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) {


<s> switch ( AddrMode ) { case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) && Imm % <NUM_LIT> == <NUM_LIT> ; case <STR_LIT> : return std :: abs ( Imm ) < ( ( ( <NUM_LIT> << <NUM_LIT> ) * <NUM_LIT> ) - <NUM_LIT> ) ; case <STR_LIT> :


<s> static MCOperand create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VariantKind Kind , MCSymbol * Sym , MCContext & OutContext ) { const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Sym , OutContext ) ;

const <ISA_LIT>MCExpr * expr = <ISA_LIT>MCExpr :: create ( Kind , MCSym , OutContext ) ;


<s> if ( Lexer . getKind ( ) == AsmToken :: Identifier ) { StringRef RegName = Lexer . getTok ( ) . getIdentifier ( ) ; RegNo = MatchRegisterName ( RegName ) ; if ( ! RegNo ) {

RegNo = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ;


<s> if ( GET_CODE ( pat ) == SET ) pat = SET_SRC ( pat ) ; pat = XEXP ( XEXP ( pat , <NUM_LIT> ) , <NUM_LIT> ) ; return REG_P ( pat ) ;


<s> if ( Constants [ i ] . isMachineConstantPoolEntry ( ) && ( Constants [ i ] . getAlignment ( ) & AlignMask ) == <NUM_LIT> ) { <ISA_LIT>ConstantPoolValue * CPV = ( <ISA_LIT>ConstantPoolValue * ) Constants [ i ] . Val . MachineCPVal ; <ISA_LIT>ConstantPoolSymbol * APS = dyn_cast < <ISA_LIT>ConstantPoolSymbol > ( CPV ) ; if ( ! APS ) continue ; if ( APS -> S == S && equals ( APS ) ) return i ;


<s> unsigned int <ISA_LIT>InstrInfo :: getInstrLatency ( const InstrItineraryData * ItinData , const MachineInstr * MI , unsigned * PredCost ) const { if ( PredCost ) * PredCost = <NUM_LIT> ; return <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: getBaseAndOffsetPosition ( const MachineInstr & MI , unsigned & BasePos , unsigned & OffsetPos ) const { if ( isMemOp ( MI ) ) { BasePos = <NUM_LIT> ; OffsetPos = <NUM_LIT> ; } else if ( MI . mayStore ( ) ) { BasePos = <NUM_LIT> ;


<s> bool hasStoreVarArgs ( ) const { return HasStoreVarArgs ;


<s> MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; bool IsStore = MI -> mayStore ( ) ; bool RanOutOfSGPRs = false ; bool Scavenged = false ; unsigned SOffset = ScratchOffset ; unsigned OriginalImmOffset = Offset ; unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; unsigned Size = NumSubRegs * <NUM_LIT> ; if ( ! isUInt < <NUM_LIT> > ( Offset + Size ) ) { SOffset = <STR_LIT> ; if ( RS ) SOffset = RS -> FindUnusedReg ( & <STR_LIT> ) ; if ( SOffset == <STR_LIT> ) { RanOutOfSGPRs = true ; SOffset = ScratchOffset ;


<s> for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) { ShuffleMask . push_back ( Imm % NElts + NElts ) ;


<s> bool function_instance :: reads_global_state_p ( ) const {

unsigned int flags = call_properties ( ) ;


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedLoad ( Type * DataTy ) { Type * ScalarTy = DataTy -> getScalarType ( ) ; int DataWidth = isa < PointerType > ( ScalarTy ) ? DL . getPointerSizeInBits ( ) : ScalarTy -> getPrimitiveSizeInBits ( ) ; return ( DataWidth >= <NUM_LIT> && ST -> hasAVX ( ) ) || ( DataWidth >= <NUM_LIT> && ST -> hasBWI ( ) ) ;


<s> ShuffleMask . append ( NumElts - <NUM_LIT> , SM_SentinelZero ) ;


<s> bool IsUndef = RegOp . isUndef ( ) ; bool IsDebug = RegOp . isDebug ( ) ; if ( NonRegOp . isImm ( ) ) RegOp . ChangeToImmediate ( NonRegOp . getImm ( ) ) ; else if ( NonRegOp . isFI ( ) ) RegOp . ChangeToFrameIndex ( NonRegOp . getIndex ( ) ) ; else return nullptr ; NonRegOp . ChangeToRegister ( Reg , false , false , IsKill , IsDead , IsUndef , IsDebug ) ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isSafeTruncation ( Val , <NUM_LIT> ) && <STR_LIT> ( static_cast < int32_t > ( Val ) , AsmParser -> hasInv2PiInlineImm ( ) ) ) { Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; setImmKindConst ( ) ; return ; } Inst . addOperand ( MCOperand :: createImm ( Val & <NUM_LIT> ) ) ; setImmKindLiteral ( ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( <STR_LIT> ( Val , AsmParser -> hasInv2PiInlineImm ( ) ) ) { Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; setImmKindConst ( ) ; return ; } Inst . addOperand ( MCOperand :: createImm ( Lo_32 ( Val ) ) ) ; setImmKindLiteral ( ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isSafeTruncation ( Val , <NUM_LIT> ) && <STR_LIT> ( static_cast < int16_t > ( Val ) , AsmParser -> hasInv2PiInlineImm ( ) ) ) { Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; setImmKindConst ( ) ; return ; } Inst . addOperand ( MCOperand :: createImm ( Val & <NUM_LIT> ) ) ; setImmKindLiteral ( ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { assert ( isSafeTruncation ( Val , <NUM_LIT> ) ) ; assert ( <STR_LIT> ( static_cast < int16_t > ( Val ) , AsmParser -> hasInv2PiInlineImm ( ) ) ) ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return ;


<s> HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasHLE = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasMPX = false ; IsBTMemSlow = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ; case <STR_LIT> :


<s> set = single_set ( insn ) ; if ( set && ! riscv_split_64bit_move_p ( SET_DEST ( set ) , SET_SRC ( set ) ) ) might_split_p = false ; } return riscv_address_insns ( XEXP ( mem , <NUM_LIT> ) , mode , might_split_p ) ;


<s> static SDValue emitRemovedIntrinsicError ( SelectionDAG & DAG , const SDLoc & DL , EVT VT ) { DiagnosticInfoUnsupported BadIntrin ( * DAG . getMachineFunction ( ) . getFunction ( ) , <STR_LIT> , DL . getDebugLoc ( ) ) ; DAG . getContext ( ) -> diagnose ( BadIntrin ) ;


<s> std :: string Sym = addPrefix ( Sym1 ) ;

size_t func_name_end = Sym . find ( '.' ) ;


<s> SDValue Val = DAG . getCopyFromReg ( Chain , DL , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ;


<s> } if ( ! Value . getNode ( ) ) return DAG . getUNDEF ( VT ) ; if ( isOnlyLowElement ) return DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( usesOnlyOneValue && EltSize <= <NUM_LIT> ) { if ( ! isConstant ) return DAG . getNode ( <STR_LIT> , dl , VT , Value ) ; if ( VT . getVectorElementType ( ) . isFloatingPoint ( ) ) { SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) Ops . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( i ) ) ) ; EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , NumElts ) ; SDValue Val = DAG . getNode ( <STR_LIT> , dl , VecVT , & Ops [ <NUM_LIT> ] , NumElts ) ; Val = LowerBUILD_VECTOR ( Val , DAG , ST ) ; if ( Val . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } SDValue Val = IsSingleInstrConstant ( Value , DAG , ST , dl ) ; if ( Val . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , Val ) ; } if ( isConstant ) return SDValue ( ) ; if ( NumElts >= <NUM_LIT> ) { SDValue shuffle = ReconstructShuffle ( Op , DAG ) ; if ( shuffle != SDValue ( ) ) return shuffle ; } if ( EltSize >= <NUM_LIT> ) { EVT EltVT = EVT :: getFloatingPointVT ( EltSize ) ;

EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , EltVT , NumElts ) ;


<s> static __inline unsigned long long sh_media_MMULFX_L ( unsigned long long mm , unsigned long long mn ) {

typedef float v2si __attribute__ ( ( mode ( V2SI ) ) ) ;


<s> DebugLoc DL ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( hasBP ( MF ) ) BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; if ( hasGOT ( MF ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; } if ( ! FuncInfo -> isLeafProc ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; }


<s> for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = IsLittleEndian ? i : ( FullSizeBytes - <NUM_LIT> - i ) ;

Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> case TargetTransformInfo :: CacheLevel :: L1D : LLVM_FALLTHROUGH ; case TargetTransformInfo :: CacheLevel :: L2D : return <NUM_LIT> ; }


<s> if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( computeOffset ( I -> Br ) / <NUM_LIT> ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * <NUM_LIT> ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = <NUM_LIT> ; for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ;


<s> SDValue Sub = DAG . getNode ( <STR_LIT> , DL , VT , X , Y ) ; SDValue Cmp = DAG . getSetCC ( DL , SetCCResultType , X , Y , <STR_LIT> ) ; if ( SetCCResultType == VT && DAG . ComputeNumSignBits ( Cmp ) == VT . getScalarSizeInBits ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Cmp , Sub ) ; return DAG . getSelect ( DL , VT , Cmp , Sub , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && ( ! VT . isVector ( ) || VT == <STR_LIT> ) ) { unsigned BitWidth = VT . getScalarSizeInBits ( ) ; APInt MinVal = APInt :: getSignedMinValue ( BitWidth ) ; APInt MaxVal = APInt :: getSignedMaxValue ( BitWidth ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue Result = DAG . getNode ( Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( VT , SetCCResultType ) , X , Y ) ;

SDValue SumDiff = Result . getValue ( <NUM_LIT> ) ;


<s> if ( ! RegNum ) { RegNum = StringSwitch < unsigned > ( lowerCase ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } if ( ! RegNum ) { StringMap < unsigned > :: const_iterator Entry = RegisterReqs . find ( lowerCase ) ; if ( Entry == RegisterReqs . end ( ) ) return - <NUM_LIT> ; Parser . Lex ( ) ; return Entry -> getValue ( ) ;


hi = a / ( ( ( UDItype ) <NUM_LIT> ) << ( sizeof ( SItype ) * <NUM_LIT> ) ) ;


<s> Type * MemAccessTy = ( isa < LoadInst > ( I ) ? I -> getType ( ) : I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ;

if ( ! isUInt < <NUM_LIT> > ( Offset ) && ( MemAccessTy -> isFloatingPointTy ( ) || MemAccessTy -> isVectorTy ( ) ) ) return false ;


<s> SDValue Reg0 = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; SDNode * VLd ; SmallVector < SDValue , <NUM_LIT> > Ops ; if ( is64BitVector || NumVecs <= <NUM_LIT> ) { unsigned Opc = ( is64BitVector ? DOpcodes [ OpcodeIndex ] : QOpcodes0 [ OpcodeIndex ] ) ; Ops . push_back ( MemAddr ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; if ( ( NumVecs <= <NUM_LIT> ) && ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Opc = getVLDSTRegisterUpdateOpcode ( Opc ) ; if ( ( NumVecs > <NUM_LIT> && ! isVLDfixed ( Opc ) ) || ! isa < ConstantSDNode > ( Inc . getNode ( ) ) ) Ops . push_back ( isa < ConstantSDNode > ( Inc . getNode ( ) ) ? Reg0 : Inc ) ; } Ops . push_back ( Pred ) ; Ops . push_back ( Reg0 ) ; Ops . push_back ( Chain ) ; VLd = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; } else { EVT AddrTy = MemAddr . getValueType ( ) ; SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , ResTy ) , <NUM_LIT> ) ; const SDValue OpsA [ ] = { MemAddr , Align , Reg0 , ImplDef , Pred , Reg0 , Chain } ; SDNode * VLdA = CurDAG -> getMachineNode ( QOpcodes0 [ OpcodeIndex ] , dl , ResTy , AddrTy , <STR_LIT> , OpsA ) ; Chain = SDValue ( VLdA , <NUM_LIT> ) ; Ops . push_back ( SDValue ( VLdA , <NUM_LIT> ) ) ; Ops . push_back ( Align ) ; if ( isUpdating ) { SDValue Inc = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) ; assert ( isa < ConstantSDNode > ( Inc . getNode ( ) ) && <STR_LIT> ) ; ( void ) Inc ;


<s> if ( ! MO . isDef ( ) && ! MRI . hasOneDef ( Reg ) ) MutableRegisters . push_back ( Reg ) ; } bool Read = false , Write = false , Effects = false , StackPointer = false ; query ( * Def , AA , Read , Write , Effects , StackPointer ) ; bool HasMutableRegisters = ! MutableRegisters . empty ( ) ; if ( ! Read && ! Write && ! Effects && ! StackPointer && ! HasMutableRegisters ) return true ; MachineBasicBlock :: const_iterator D ( Def ) , I ( Insert ) ; for ( -- I ; I != D ; -- I ) { bool InterveningRead = false ; bool InterveningWrite = false ; bool InterveningEffects = false ; bool InterveningStackPointer = false ; query ( * I , AA , InterveningRead , InterveningWrite , InterveningEffects , InterveningStackPointer ) ; if ( Effects && InterveningEffects ) return false ; if ( Read && InterveningWrite ) return false ; if ( Write && ( InterveningRead || InterveningWrite ) ) return false ;

if ( StackPointer && InterveningStackPointer ) return false ;


return getParser ( ) . getTok ( ) . getLoc ( ) ;


<s> return <ISA_LIT>_EXPAND_PSEUDO_NAME ;


<s> return ( __a == __AARCH64_UINT64_C ( <NUM_LIT> ) ) ;


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; unsigned PrevRegNum = <NUM_LIT> ; SmallVector < std :: pair < unsigned , SMLoc > , <NUM_LIT> > Registers ; do { bool IsRange = Parser . getTok ( ) . is ( AsmToken :: Minus ) ; Parser . Lex ( ) ; const AsmToken & RegTok = Parser . getTok ( ) ; SMLoc RegLoc = RegTok . getLoc ( ) ; if ( RegTok . isNot ( AsmToken :: Identifier ) ) { Error ( RegLoc , <STR_LIT> ) ; return true ; } int RegNum = TryParseRegister ( ) ; if ( RegNum == - <NUM_LIT> ) { Error ( RegLoc , <STR_LIT> ) ; return true ; } if ( IsRange ) { int Reg = PrevRegNum ; do { ++ Reg ; Registers . push_back ( std :: make_pair ( Reg , RegLoc ) ) ; } while ( Reg != RegNum ) ; } else { Registers . push_back ( std :: make_pair ( RegNum , RegLoc ) ) ; } PrevRegNum = RegNum ; } while ( Parser . getTok ( ) . is ( AsmToken :: Comma ) || Parser . getTok ( ) . is ( AsmToken :: Minus ) ) ; const AsmToken & RCurlyTok = Parser . getTok ( ) ; if ( RCurlyTok . isNot ( AsmToken :: RCurly ) ) { Error ( RCurlyTok . getLoc ( ) , <STR_LIT> ) ; return true ; } SMLoc E = RCurlyTok . getLoc ( ) ; Parser . Lex ( ) ; SmallVectorImpl < std :: pair < unsigned , SMLoc > > :: const_iterator RI = Registers . begin ( ) , RE = Registers . end ( ) ; DenseMap < unsigned , bool > RegMap ; RegMap [ RI -> first ] = true ; unsigned HighRegNum = RI -> first ; bool EmittedWarning = false ; for ( ++ RI ; RI != RE ; ++ RI ) { const std :: pair < unsigned , SMLoc > & RegInfo = * RI ; unsigned Reg = RegInfo . first ; if ( RegMap [ Reg ] ) { Error ( RegInfo . second , <STR_LIT> ) ; return true ; } if ( ! EmittedWarning && Reg < HighRegNum ) Warning ( RegInfo . second , <STR_LIT> ) ; RegMap [ Reg ] = true ; HighRegNum = std :: max ( Reg , HighRegNum ) ;


<s> if ( isStrongerThanMonotonic ( cast < AtomicSDNode > ( Op ) -> getSuccessOrdering ( ) ) ) { return SDValue ( ) ; }


<s> void addAFGR64AsmRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateReg ( getAFGR64Reg ( ) ) ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) {

RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> DIExpression * Expr = const_cast < DIExpression * > ( MI . getDebugExpression ( ) ) ; if ( AddrDispShift != <NUM_LIT> ) Expr = DIExpression :: prepend ( Expr , DIExpression :: StackValue , AddrDispShift ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; bool IsIndirect = MI . isIndirectDebugValue ( ) ; const MDNode * Var = MI . getDebugVariable ( ) ;

if ( IsIndirect ) assert ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ;


return SignExtend < <NUM_LIT> , u32 > ( this -> storage ) ;


<s> RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ;

if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return Val ;


<s> const MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & CCSI : CSI ) { unsigned Reg = CCSI . getReg ( ) ; assert ( TRI -> getMinimalPhysRegClass ( Reg ) -> getSize ( ) == <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) ; }


<s> unsigned <ISA_LIT>TargetLowering :: getRegisterByName ( const char * RegName , EVT VT ) const { unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ; report_fatal_error ( <STR_LIT> ) ;


<s> return ( nullptr != Disassembler && Disassembler -> tryAddingSymbolicOperand ( Inst , Value , Address , true , <NUM_LIT> , atLeast ) ) ;


<s> inline vector signed short vec_vpkswss ( vector signed int a1 , vector signed int a2 ) { return ( vector signed short ) __builtin_altivec_vpkswss ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> unsigned NumBytes = AFI -> getLocalStackSize ( ) ;

return ! ( MFI -> hasCalls ( ) || hasFP ( MF ) || NumBytes > <NUM_LIT> ) ;


<s> } ; if ( ! ( IsFreelyInvertable ( N0 ) || IsFreelyInvertable ( N1 ) ) ) return SDValue ( ) ; SDValue NewN0 = DAG . getLogicalNOT ( DL , N0 , VT ) ; SDValue NewN1 = DAG . getLogicalNOT ( DL , N1 , VT ) ; SDValue And = DAG . getNode ( <STR_LIT> , DL , VT , NewN0 , NewN1 ) ; return DAG . getLogicalNOT ( DL , And , VT ) ;


<s> static DecodeStatus DecodeMISCRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const MCDisassembler * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = MiscRegDecoderTable [ RegNo ] ; if ( Reg == <STR_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> return MAI != nullptr ; } ; MachineInstr * MI = SU -> getInstr ( ) ; if ( IsMFMAFn ( MI ) ) { int W = getWaitStatesSince ( IsMFMAFn , <NUM_LIT> ) ; if ( MAI ) return W < ( int ) TSchedModel . computeInstrLatency ( MAI ) ;


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , CurDbgLoc , TII . get ( CompareImmOpc ) ) . addReg ( Op0Reg ) . addImm ( Op1C -> getSExtValue ( ) ) ; return true ; } } unsigned CompareOpc = <ISA_LIT>ChooseCmpOpcode ( VT , Subtarget ) ; if ( CompareOpc == <NUM_LIT> ) return false ; unsigned Op1Reg = getRegForValue ( Op1 ) ; if ( Op1Reg == <NUM_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , CurDbgLoc , TII . get ( CompareOpc ) ) . addReg ( Op0Reg ) . addReg ( Op1Reg ) ; return true ;


<s> next_cum = * get_cumulative_args ( args_so_far ) ; arc_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , <NUM_LIT> ) ; first_anon_arg = next_cum ; if ( first_anon_arg < MAX_ARC_PARM_REGS ) { int first_reg_offset = first_anon_arg ;


<s> bool isAddSubImmNeg ( ) const { if ( ! isShiftedImm ( ) && ! isImm ( ) ) return false ; const MCExpr * Expr ; if ( isShiftedImm ( ) ) { unsigned Shift = ShiftedImm . ShiftAmount ; Expr = ShiftedImm . Val ; if ( Shift != <NUM_LIT> && Shift != Width ) return false ; } else Expr = getImm ( ) ;

const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ;


<s> if ( StackSize || MFFrame -> hasVarSizedObjects ( ) || MFFrame -> hasCalls ( ) ) StackSize += <STR_LIT> ;


<s> printDisp ( MI , opNum + <STR_LIT> , O ) ; O << ',' ; printOperand ( MI , opNum + <STR_LIT> , O ) ; O << ',' ; printOperand ( MI , opNum + <STR_LIT> , O ) ; O << ')' ;


<s> MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Op0 . isDef ( ) ) ; RegisterSubReg OutR ( Op0 ) ; const TargetRegisterClass * PredRC = & <STR_LIT> ; RegisterSubReg NewPR = MRI -> createVirtualRegister ( PredRC ) ; MachineInstrBuilder MIB = BuildMI ( B , MI , DL , TII -> get ( NewOpc ) , NewPR . R ) ; for ( unsigned i = <NUM_LIT> ; i < NumOps ; ++ i ) { RegisterSubReg GPR = MI -> getOperand ( i ) ; RegisterSubReg Pred = getPredRegFor ( GPR ) ; MIB . addReg ( Pred . R , <NUM_LIT> , Pred . S ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( OutR . R ) ;

unsigned NewOutR = MRI -> createVirtualRegister ( RC ) ;


<s> Relocator :: Address S = pReloc . symValue ( ) ; Relocator :: DWord A = pReloc . addend ( ) ; Relocator :: DWord P = pReloc . place ( ) ; FragmentRef & target_fragref = pReloc . targetRef ( ) ; Fragment * target_frag = target_fragref . frag ( ) ; LDSection & target_sect = target_frag -> getParent ( ) -> getSection ( ) ; result = ( int64_t ) ( S + A - P ) ; if ( ( llvm :: ELF :: SHF_ALLOC & target_sect . flag ( ) ) == <NUM_LIT> ) {


<s> widest_int min_size = constant_lower_bound ( wi :: to_poly_widest ( TYPE_SIZE ( type ) ) ) ;

return wi :: umin ( min_size , <NUM_LIT> ) . to_uhwi ( ) ;


<s> bitmap_clear_bit ( to_clear_bitmap , IP_REGNUM ) ; emit_use ( gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; bitmap_clear_bit ( to_clear_bitmap , <NUM_LIT> ) ; } } for ( regno = NUM_ARG_REGS ; regno <= maxregno ; regno ++ ) { if ( IN_RANGE ( regno , FIRST_VFP_REGNUM , D7_VFP_REGNUM ) ) continue ; if ( IN_RANGE ( regno , IP_REGNUM , PC_REGNUM ) ) continue ; if ( ! callee_saved_reg_p ( regno ) && ( ! IN_RANGE ( regno , FIRST_VFP_REGNUM , LAST_VFP_REGNUM ) || TARGET_HARD_FLOAT ) ) bitmap_set_bit ( to_clear_bitmap , regno ) ; } result_type = TREE_TYPE ( DECL_RESULT ( current_function_decl ) ) ; if ( ! VOID_TYPE_P ( result_type ) ) { uint64_t to_clear_return_mask ; result_rtl = arm_function_value ( result_type , current_function_decl , <NUM_LIT> ) ; gcc_assert ( REG_P ( result_rtl ) ) ; to_clear_return_mask = compute_not_to_clear_mask ( result_type , result_rtl , <NUM_LIT> , & padding_bits_to_clear ) ; if ( to_clear_return_mask ) { gcc_assert ( ( unsigned ) maxregno < sizeof ( long long ) * __CHAR_BIT__ ) ; for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) {

if ( to_clear_return_mask & ( <NUM_LIT> << regno ) ) bitmap_clear_bit ( to_clear_bitmap , regno ) ;


<s> return __builtin_neon_vrndphf ( __a ) ;


<s> raw_svector_ostream ( Name ) << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << uid << '_' << uid2 ;

return OutContext . GetOrCreateSymbol ( Name . str ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : { auto * UnfoldedRC = getRegClassForUnfoldedLoad ( MF , * TII , MI . getOpcode ( ) ) ; if ( ! UnfoldedRC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; report_fatal_error ( <STR_LIT> ) ; } unsigned Reg = MRI -> createVirtualRegister ( UnfoldedRC ) ; SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; bool Unfolded = TII -> unfoldMemoryOperand ( MF , MI , Reg , true , false , NewMIs ) ; ( void ) Unfolded ; assert ( Unfolded && <STR_LIT> ) ; for ( auto * NewMI : NewMIs ) MBB . insert ( MI . getIterator ( ) , NewMI ) ; MI . eraseFromParent ( ) ; LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( auto * NewMI : NewMIs ) { NewMI -> dump ( ) ; dbgs ( ) << <STR_LIT> ; } } ) ; continue ;


<s> static const char * get_some_local_dynamic_name ( void ) { rtx insn ; if ( cfun -> machine -> some_ld_name ) return cfun -> machine -> some_ld_name ; for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) if ( INSN_P ( insn ) && for_each_rtx ( & PATTERN ( insn ) , get_some_local_dynamic_name_1 , <NUM_LIT> ) ) return cfun -> machine -> some_ld_name ; gcc_unreachable ( ) ;


<s> case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performShlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSrlCombine ( N , DCI ) ; } case <STR_LIT> : { if ( DCI . getDAGCombineLevel ( ) < AfterLegalizeDAG ) break ; return performSraCombine ( N , DCI ) ; } case <STR_LIT> : return performTruncateCombine ( N , DCI ) ; case <STR_LIT> : return performMulCombine ( N , DCI ) ; case <STR_LIT> : return performMulhsCombine ( N , DCI ) ; case <STR_LIT> : return performMulhuCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { simplifyI24 ( N , <NUM_LIT> , DCI ) || simplifyI24 ( N , <NUM_LIT> , DCI ) ; return SDValue ( ) ; } case <STR_LIT> : case <STR_LIT> : return performMulLoHi24Combine ( N , DCI ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performFNegCombine ( N , DCI ) ; case <STR_LIT> : return performFAbsCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : { assert ( ! N -> getValueType ( <NUM_LIT> ) . isVector ( ) && <STR_LIT> ) ; ConstantSDNode * Width = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Width ) break ; uint32_t WidthVal = Width -> getZExtValue ( ) & <NUM_LIT> ; if ( WidthVal == <NUM_LIT> ) return DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ;

if ( OpSignBits >= SignBits ) return BitsFrom ;


<s> ProtectReturnSupportPass ( ) : MachineFunctionPass ( ID ) {


<s> std :: pair < SDNode * , SDNode * > <ISA_LIT>DAGToDAGISel :: SelectMULT ( SDNode * N , unsigned Opc , DebugLoc dl , EVT Ty , bool HasLo , bool HasHi ) { SDNode * Lo = <NUM_LIT> , * Hi = <NUM_LIT> ; SDNode * Mul = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; SDValue InFlag = SDValue ( Mul , <NUM_LIT> ) ; if ( HasLo ) { Lo = CurDAG -> getMachineNode ( Ty == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , Ty , <STR_LIT> , InFlag ) ; InFlag = SDValue ( Lo , <NUM_LIT> ) ; } if ( HasHi ) Hi = CurDAG -> getMachineNode ( Ty == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , Ty , InFlag ) ; return std :: make_pair ( Lo , Hi ) ;


<s> AU . addRequired < <ISA_LIT>PerfHintAnalysis > ( ) ; AU . addRequired < LegacyDivergenceAnalysis > ( ) ;

SelectionDAGISel :: getAnalysisUsage ( AU ) ;


<s> for ( SrcNum = <NUM_LIT> ; SrcNum < <NUM_LIT> && <STR_LIT> ( Opc , Ops [ SrcNum ] ) != - <NUM_LIT> ; ++ SrcNum ) ; assert ( SrcNum > <NUM_LIT> ) ; int OpSelIdx = <STR_LIT> ( Opc , <STR_LIT> :: op_sel ) ; unsigned OpSel = Inst . getOperand ( OpSelIdx ) . getImm ( ) ; if ( ( OpSel & ( <NUM_LIT> << SrcNum ) ) != <NUM_LIT> ) { int ModIdx = <STR_LIT> ( Opc , <STR_LIT> :: src0_modifiers ) ; uint32_t ModVal = Inst . getOperand ( ModIdx ) . getImm ( ) ; Inst . getOperand ( ModIdx ) . setImm ( ModVal | <STR_LIT> ) ; }


<s> bool listContainsBase ; if ( checkLowRegisterList ( Inst , <NUM_LIT> , Rn , <NUM_LIT> , listContainsBase ) && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> + hasWritebackToken ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( ! listContainsBase && ! hasWritebackToken && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( listContainsBase && hasWritebackToken ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : { if ( listContainsReg ( Inst , <NUM_LIT> , Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; break ; } case <STR_LIT> : { if ( Operands . size ( ) == <NUM_LIT> && ( ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getReg ( ) != ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getReg ( ) ) && ( ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getReg ( ) != ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getReg ( ) ) ) { return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; } break ; } case <STR_LIT> : { bool listContainsBase ; if ( checkLowRegisterList ( Inst , <NUM_LIT> , <NUM_LIT> , <STR_LIT> , listContainsBase ) && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; break ; } case <STR_LIT> : { bool listContainsBase ; if ( checkLowRegisterList ( Inst , <NUM_LIT> , <NUM_LIT> , <STR_LIT> , listContainsBase ) && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; break ; } case <STR_LIT> : { bool listContainsBase ;

if ( checkLowRegisterList ( Inst , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , listContainsBase ) && ! isThumbTwo ( ) ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ;


<s> EVT SVT = In . getValueType ( ) ; if ( ! VT . is256BitVector ( ) || ! SVT . is128BitVector ( ) || VT . getVectorNumElements ( ) != SVT . getVectorNumElements ( ) ) return SDValue ( ) ; assert ( Subtarget -> hasFp256 ( ) && <STR_LIT> ) ;

if ( Subtarget -> hasInt256 ( ) ) return DAG . getNode ( <STR_LIT> , DL , VT , In ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; uint64_t And_imm = <NUM_LIT> ; if ( ! isOpcWithIntImmediate ( N , <STR_LIT> , And_imm ) ) return false ; const SDNode * Op0 = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; And_imm |= ( <NUM_LIT> << NumberOfIgnoredLowBits ) - <NUM_LIT> ; if ( And_imm & ( And_imm + <NUM_LIT> ) ) return false ; bool ClampMSB = false ; uint64_t Srl_imm = <NUM_LIT> ; if ( VT == <STR_LIT> && Op0 -> getOpcode ( ) == <STR_LIT> && isOpcWithIntImmediate ( Op0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Srl_imm ) ) { Opd0 = Widen ( CurDAG , Op0 -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; ClampMSB = true ; } else if ( VT == <STR_LIT> && Op0 -> getOpcode ( ) == <STR_LIT> && isOpcWithIntImmediate ( Op0 -> getOperand ( <NUM_LIT> ) . getNode ( ) , <STR_LIT> , Srl_imm ) ) { Opd0 = Op0 -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; VT = Opd0 -> getValueType ( <NUM_LIT> ) ; } else if ( isOpcWithIntImmediate ( Op0 , <STR_LIT> , Srl_imm ) ) { Opd0 = Op0 -> getOperand ( <NUM_LIT> ) ; } else if ( BiggerPattern ) { Opd0 = N -> getOperand ( <NUM_LIT> ) ; } else return false ; if ( ! BiggerPattern && ( Srl_imm <= <NUM_LIT> || Srl_imm >= VT . getSizeInBits ( ) ) ) { DEBUG ( ( dbgs ( ) << N << <STR_LIT> ) ) ; return false ; } LSB = Srl_imm ; MSB = Srl_imm + ( VT == <STR_LIT> ? countTrailingOnes < uint32_t > ( And_imm ) : countTrailingOnes < uint64_t > ( And_imm ) ) - <NUM_LIT> ; if ( ClampMSB ) MSB = MSB > <NUM_LIT> ? <NUM_LIT> : MSB ;

Opc = VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ;


<s> bool <ISA_LIT>SpeculationHardening :: slhLoads ( MachineBasicBlock & MBB ) { bool Modified = false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB ) ; RegsAlreadyMasked . reset ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; MachineBasicBlock :: iterator NextMBBI ; for ( ; MBBI != E ; MBBI = NextMBBI ) { MachineInstr & MI = * MBBI ; NextMBBI = std :: next ( MBBI ) ; if ( ! MI . mayLoad ( ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; bool AllDefsAreGPR = llvm :: all_of ( MI . defs ( ) , [ & ] ( MachineOperand & Op ) { return Op . isReg ( ) && ( <STR_LIT> . contains ( Op . getReg ( ) ) || <STR_LIT> . contains ( Op . getReg ( ) ) ) ; } ) ; bool HardenLoadedData = AllDefsAreGPR ; bool HardenAddressLoadedFrom = ! HardenLoadedData ; for ( MachineOperand Op : MI . defs ( ) ) for ( MCRegAliasIterator AI ( Op . getReg ( ) , TRI , true ) ; AI . isValid ( ) ; ++ AI ) RegsAlreadyMasked . reset ( * AI ) ; if ( HardenLoadedData ) for ( auto Def : MI . defs ( ) ) { if ( Def . isDead ( ) ) continue ; Modified |= makeGPRSpeculationSafe ( MBB , NextMBBI , MI , Def . getReg ( ) ) ; } if ( HardenAddressLoadedFrom ) for ( auto Use : MI . uses ( ) ) { if ( ! Use . isReg ( ) ) continue ; unsigned Reg = Use . getReg ( ) ; if ( ! ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) ) continue ; Modified |= makeGPRSpeculationSafe ( MBB , MBBI , MI , Reg ) ; }


<s> Inst . addOperand ( MCOperand :: CreateReg ( FCCRegDecoderTable [ RegNo ] ) ) ;


<s> } for ( unsigned i = <NUM_LIT> ; i < IDATASections . size ( ) ; i ++ ) { delete IDATASections [ i ] ; } for ( unsigned i = <NUM_LIT> ; i < AutosSections . size ( ) ; i ++ ) { delete AutosSections [ i ] ; } delete ROSection ;


<s> addr = XEXP ( mem , <NUM_LIT> ) ; struct csky_address caddr ; decompose_csky_address ( addr , & caddr ) ; ops [ <NUM_LIT> ] = reg ; ops [ <NUM_LIT> ] = mem ; sprintf ( buff , templ , isload ? <STR_LIT> : <STR_LIT> , caddr . index ? <STR_LIT> : <STR_LIT> , type ) ; output_asm_insn ( buff , ops ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( getReg ( ) ) ) ;


<s> if ( misalignment == - <NUM_LIT> ) { if ( rs6000_vector_alignment_reachable ( type , is_packed ) ) { int element_size = TREE_INT_CST_LOW ( TYPE_SIZE ( type ) ) ; if ( element_size == <NUM_LIT> || element_size == <NUM_LIT> ) return true ; } return false ; }

if ( misalignment % <NUM_LIT> == <NUM_LIT> ) return true ;


<s> return __builtin_ia32_cvtss2si64 ( ( __v4sf ) __A ) ;


<s> TargetRegistry :: RegisterMCCodeGenInfo ( TheBlackfinTarget , createBlackfinMCCodeGenInfo ) ;

TargetRegistry :: RegisterMCInstrInfo ( TheBlackfinTarget , createBlackfinMCInstrInfo ) ;


<s> const bool IsRegImm = SelectAddrModeIndexedSVE < - <NUM_LIT> , <NUM_LIT> > ( N , OldBase , NewBase , NewOffset ) ; const bool IsRegReg = ! IsRegImm && SelectSVERegRegAddrMode < Scale > ( OldBase , NewBase , NewOffset ) ; return std :: make_tuple ( IsRegReg ? Opc_rr : Opc_ri , NewBase , NewOffset ) ;


<s> return isSimpleMove ( MI , FrameIndex , <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: decomposeMulByConstant ( LLVMContext & Context , EVT VT , SDValue C ) const { APInt MulC ; if ( ! <STR_LIT> ( C . getNode ( ) , MulC ) ) return false ; while ( getTypeAction ( Context , VT ) != TypeLegal ) VT = getTypeToTransformTo ( Context , VT ) ; if ( isOperationLegal ( <STR_LIT> , VT ) ) return false ; return ( MulC + <NUM_LIT> ) . isPowerOf2 ( ) || ( MulC - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - MulC ) . isPowerOf2 ( ) || ( - ( MulC + <NUM_LIT> ) ) . isPowerOf2 ( ) ;


<s> void addImm1_31Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> if ( isTypeLegal ( Ty , VT ) ) return true ;

if ( VT == <STR_LIT> || VT == <STR_LIT> ) return true ;


<s> BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; return ; } MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( ABI . IsN32 ( ) ) { const GlobalValue * FName = & MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ;

BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ;


<s> Register UnhardenedReg = MRI -> createVirtualRegister ( DefRC ) ; DefOp . setReg ( UnhardenedReg ) ; unsigned HardenedReg = hardenValueInRegister ( UnhardenedReg , MBB , std :: next ( MI . getIterator ( ) ) , Loc ) ; MRI -> replaceRegWith ( OldDefReg , HardenedReg ) ; ++ NumPostLoadRegsHardened ; return HardenedReg ;


<s> FunctionPass * llvm :: create<ISA_LIT>LowerTileCopyPass ( ) { return new <ISA_LIT>LowerTileCopy ( ) ;


<s> void <ISA_LIT>AsmPrinter :: emitStartOfAsmFile ( Module & M ) {

OutStreamer -> emitSyntaxDirective ( ) ;


<s> unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ; unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IdxRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; MachineBasicBlock :: iterator PrevI = MI ; MachineBasicBlock :: iterator B = MBB -> begin ( ) ; while ( PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ) -- PrevI ; if ( ! PrevI -> definesRegister ( BaseReg ) ) continue ; MachineInstr * AddrMI = PrevI ; bool OptOk = true ; for ( unsigned k = <NUM_LIT> , eee = AddrMI -> getNumOperands ( ) ; k != eee ; ++ k ) { const MachineOperand & MO = AddrMI -> getOperand ( k ) ; if ( ! MO . isReg ( ) || ! MO . getReg ( ) ) continue ; if ( MO . isDef ( ) && MO . getReg ( ) != BaseReg ) { OptOk = false ; break ; } if ( MO . isUse ( ) && ! MO . isKill ( ) && MO . getReg ( ) != IdxReg ) { OptOk = false ; break ; } } if ( ! OptOk ) continue ; for ( -- PrevI ; PrevI != B && ! PrevI -> definesRegister ( BaseReg ) ; -- PrevI ) ; MachineInstr * LeaMI = PrevI ; if ( ( LeaMI -> getOpcode ( ) != <STR_LIT> && LeaMI -> getOpcode ( ) != <STR_LIT> ) || LeaMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != BaseReg ) OptOk = false ; if ( ! OptOk ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> << * AddrMI << <STR_LIT> << * LeaMI ) ; unsigned Opc = ByteOk ? <STR_LIT> : <STR_LIT> ; MachineInstr * NewJTMI = BuildMI ( MBB , MI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . addReg ( IdxReg , getKillRegState ( IdxRegKill ) ) . addJumpTableIndex ( JTI , JTOP . getTargetFlags ( ) ) . addImm ( MI -> getOperand ( JTOpIdx + <NUM_LIT> ) . getImm ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> << * NewJTMI ) ;

unsigned NewSize = TII -> GetInstSizeInBytes ( NewJTMI ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirectiveSEHPrologEnd ( SMLoc L ) {

getTargetStreamer ( ) . EmitARM64WinCFIPrologEnd ( ) ;


<s> return TYPE_MODE ( builtin_types [ type . index ] . vector ) ;


<s> unsigned <ISA_LIT>TTI :: getMaximumUnrollFactor ( ) const { unsigned Directive = ST -> getDarwinDirective ( ) ; if ( Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> ) return <NUM_LIT> ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> void <ISA_LIT>FrameLowering :: emitCalleeSavedSVERestores ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI ) const {

emitCalleeSavedRestores ( MBB , MBBI , true ) ;


<s> LLVM_DEBUG ( const MachineLoop * Loop = MLI -> getLoopFor ( MBB ) ; if ( Loop && Loop -> getHeader ( ) == MBB ) dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; ) ; MachineBasicBlock * SinglePredMBB = getSingleSchedPred ( MBB , MLI -> getLoopFor ( MBB ) ) ; if ( SinglePredMBB == nullptr || SchedStates . find ( SinglePredMBB ) == SchedStates . end ( ) ) return ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * SinglePredMBB ) << <STR_LIT> ; ) ; HazardRec -> copyState ( SchedStates [ SinglePredMBB ] ) ; LLVM_DEBUG ( HazardRec -> dumpState ( ) ; ) ; for ( MachineInstr & MI : SinglePredMBB -> terminators ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; ) ; bool TakenBranch = ( MI . isBranch ( ) && ( TII -> getBranchInfo ( MI ) . isIndirect ( ) || TII -> getBranchInfo ( MI ) . getMBBTarget ( ) == MBB ) ) ;

HazardRec -> emitInstruction ( & MI , TakenBranch ) ;


<s> unsigned DiffReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; bool IsCopy = MI -> getOpcode ( ) == <STR_LIT> ; unsigned ResultReg = IsCopy ? MI -> getOperand ( <NUM_LIT> ) . getReg ( ) : MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , DiffReg ) . addReg ( MFI -> getFrameOffsetReg ( ) ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) ) ; int64_t Offset = FrameInfo . getObjectOffset ( Index ) ; if ( Offset == <NUM_LIT> ) { BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , ResultReg ) . addImm ( Log2_32 ( ST . getWavefrontSize ( ) ) ) . addReg ( DiffReg ) ; } else { unsigned CarryOut = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ScaledReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , ScaledReg ) . addImm ( Log2_32 ( ST . getWavefrontSize ( ) ) ) . addReg ( DiffReg , RegState :: Kill ) ; if ( <STR_LIT> ( Offset , ST . hasInv2PiInlineImm ( ) ) ) { BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , ResultReg ) . addReg ( CarryOut , RegState :: Define | RegState :: Dead ) . addImm ( Offset ) . addReg ( ScaledReg , RegState :: Kill ) ; } else { unsigned ConstOffsetReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , ConstOffsetReg ) . addImm ( Offset ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , ResultReg ) . addReg ( CarryOut , RegState :: Define | RegState :: Dead ) . addReg ( ConstOffsetReg , RegState :: Kill ) . addReg ( ScaledReg , RegState :: Kill ) ; } MRI . setRegAllocationHint ( CarryOut , <NUM_LIT> , <STR_LIT> ) ; } if ( IsCopy ) MI -> eraseFromParent ( ) ; else FIOp . ChangeToRegister ( ResultReg , false , false , true ) ; return ; } if ( IsMUBUF ) { assert ( static_cast < int > ( FIOperandNum ) == <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: vaddr ) ) ; assert ( TII -> getNamedOperand ( * MI , <STR_LIT> :: soffset ) -> getReg ( ) == MFI -> getFrameOffsetReg ( ) ) ; int64_t Offset = FrameInfo . getObjectOffset ( Index ) ; int64_t OldImm = TII -> getNamedOperand ( * MI , <STR_LIT> :: offset ) -> getImm ( ) ;


<s> MIB . addReg ( <STR_LIT> ) ; MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ; MIB . addReg ( <STR_LIT> ) ; MI -> eraseFromParent ( ) ;


<s> assert ( ! isSoloInstruction ( MI ) && <STR_LIT> ) ; if ( MI -> isDebugValue ( ) ) { return true ; } else {

assert ( ResourceTracker -> getInstrItins ( ) -> beginStage ( MI -> getDesc ( ) . getSchedClass ( ) ) -> getUnits ( ) && <STR_LIT> ) ;


<s> for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; if ( MI . getOpcode ( ) == AMDGPU :: V_MOV_I1 ) { I1Defs . push_back ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . setDesc ( TII -> get ( AMDGPU :: V_MOV_B32_e32 ) ) ; continue ; } if ( MI . getOpcode ( ) == AMDGPU :: V_AND_I1 ) { I1Defs . push_back ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; MI . setDesc ( TII -> get ( AMDGPU :: V_AND_B32_e32 ) ) ; continue ; } if ( MI . getOpcode ( ) == AMDGPU :: V_OR_I1 ) {


<s> const uint32_t * <ISA_LIT>Z80RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { if ( MF . getFunction ( ) . getFunctionType ( ) -> getNumParams ( ) <= <NUM_LIT> ) return CSR_0_1_RegMask ;


<s> } if ( MI . isDebugValue ( ) ) continue ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : { int Immed = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Immed != <NUM_LIT> ) { unsigned TrueReg1 = lookThruCopyLike ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned TrueReg2 = lookThruCopyLike ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( TrueReg1 == TrueReg2 && TargetRegisterInfo :: isVirtualRegister ( TrueReg1 ) ) { MachineInstr * DefMI = MRI -> getVRegDef ( TrueReg1 ) ; if ( DefMI && DefMI -> getOpcode ( ) == <STR_LIT> ) { unsigned FeedImmed = DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned FeedReg1 = lookThruCopyLike ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned FeedReg2 = lookThruCopyLike ( DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ( FeedImmed == <NUM_LIT> || FeedImmed == <NUM_LIT> ) && FeedReg1 == FeedReg2 ) { DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; DEBUG ( MI . dump ( ) ) ; BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; ToErase = & MI ; Simplified = true ; } else if ( ( Immed == <NUM_LIT> || Immed == <NUM_LIT> ) && FeedImmed == <NUM_LIT> && FeedReg1 == FeedReg2 ) {


<s> return make_unique < <ISA_LIT>Operand > ( RegNum , S , E ) ;


<s> void <ISA_LIT>DAGToDAGISel :: emitFunctionEntryCode ( ) { const Function & F = MF -> getFunction ( ) ;

if ( F . hasExternalLinkage ( ) && F . getName ( ) == <STR_LIT> ) emitSpecialCodeForMain ( ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>BundlingPass ( <ISA_LIT>TargetMachine & tm ) {

return new <ISA_LIT>BundlingPass ( tm ) ;


<s> <ISA_LIT>PassConfig :: addPreISel ( ) ; addPass ( & <ISA_LIT>AnnotateKernelFeaturesID ) ; addPass ( createSinkingPass ( ) ) ; addPass ( create<ISA_LIT>TypeRewriter ( ) ) ; addPass ( create<ISA_LIT>AnnotateControlFlowPass ( ) ) ; return false ;


<s> Attribute GPUAttr = F . getFnAttribute ( <STR_LIT> ) ; return GPUAttr . hasAttribute ( Attribute :: None ) ? getTargetCPU ( ) : GPUAttr . getValueAsString ( ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx ) : MCII ( mcii ) , Ctx ( ctx ) {


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>PrepareForLiveIntervals ( ) ) ; addPass ( create<ISA_LIT>OptimizeLiveIntervals ( ) ) ; addPass ( create<ISA_LIT>MemIntrinsicResults ( ) ) ; addPass ( create<ISA_LIT>RegStackify ( ) ) ; addPass ( create<ISA_LIT>RegColoring ( ) ) ; } addPass ( create<ISA_LIT>ExplicitLocals ( ) ) ; addPass ( create<ISA_LIT>CFGSort ( ) ) ; addPass ( create<ISA_LIT>CFGStackify ( ) ) ; addPass ( create<ISA_LIT>LowerBrUnless ( ) ) ;

if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>Peephole ( ) ) ;


<s> if ( unsorted_regs [ i ] < <NUM_LIT> || ( TARGET_THUMB1 && unsorted_regs [ i ] > LAST_LO_REGNUM ) || unsorted_regs [ i ] > <NUM_LIT> || ( i != nops - <NUM_LIT> && unsorted_regs [ i ] == base_reg ) ) return <NUM_LIT> ; if ( unsorted_regs [ i ] == SP_REGNUM && base_reg != SP_REGNUM ) return <NUM_LIT> ; unsorted_offsets [ i ] = INTVAL ( offset ) ; if ( i == <NUM_LIT> || unsorted_offsets [ i ] < unsorted_offsets [ order [ <NUM_LIT> ] ] ) order [ <NUM_LIT> ] = i ; } else return <NUM_LIT> ; } if ( ! compute_offset_order ( nops , unsorted_offsets , order , check_regs ? unsorted_regs : NULL ) ) return <NUM_LIT> ; if ( saved_order ) memcpy ( saved_order , order , sizeof order ) ; if ( base ) { * base = base_reg ; for ( i = <NUM_LIT> ; i < nops ; i ++ ) regs [ i ] = unsorted_regs [ check_regs ? order [ i ] : i ] ; * load_offset = unsorted_offsets [ order [ <NUM_LIT> ] ] ; } if ( TARGET_THUMB1 && ! peep2_reg_dead_p ( nops , base_reg_rtx ) ) return <NUM_LIT> ; if ( unsorted_offsets [ order [ <NUM_LIT> ] ] == <NUM_LIT> ) ldm_case = <NUM_LIT> ; else if ( TARGET_ARM && unsorted_offsets [ order [ <NUM_LIT> ] ] == <NUM_LIT> ) ldm_case = <NUM_LIT> ; else if ( TARGET_ARM && unsorted_offsets [ order [ nops - <NUM_LIT> ] ] == <NUM_LIT> ) ldm_case = <NUM_LIT> ; else if ( TARGET_32BIT && unsorted_offsets [ order [ nops - <NUM_LIT> ] ] == - <NUM_LIT> ) ldm_case = <NUM_LIT> ; else if ( const_ok_for_arm ( unsorted_offsets [ order [ <NUM_LIT> ] ] ) || const_ok_for_arm ( - unsorted_offsets [ order [ <NUM_LIT> ] ] ) ) ldm_case = <NUM_LIT> ; else return <NUM_LIT> ;

if ( ! multiple_operation_profitable_p ( false , nops , ldm_case == <NUM_LIT> ? unsorted_offsets [ order [ <NUM_LIT> ] ] : <NUM_LIT> ) ) return <NUM_LIT> ;


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( ID ) {


<s> if ( isPopOpcode ( MI -> getOpcode ( ) ) ) { for ( int i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) if ( ! isCalleeSavedRegister ( MI -> getOperand ( i ) . getReg ( ) , CSRegs ) ) return false ; return true ;


<s> const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned IgnoredFrameReg ; Offset = TFL -> getFrameIndexReference ( MF , - <NUM_LIT> , IgnoredFrameReg ) ;

return getIndirectIndexBegin ( MF ) + Offset ;


<s> if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; StringRef Str = Parser . getTok ( ) . getString ( ) ; int Slot = StringSwitch < int > ( Str ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ;

SMLoc S = Parser . getTok ( ) . getLoc ( ) ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : TM ( TM ) , STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , {


<s> dbgs ( ) << <STR_LIT> << printReg ( RU . Reg , & ME . TRI , RU . Sub ) << <STR_LIT> << ME . getCell ( RU , Map ) << <STR_LIT> ; } dbgs ( ) << <STR_LIT> ; for ( const std :: pair < const unsigned , RegisterCell > & P : ResMap ) { RegisterRef RD ( P . first ) ; dbgs ( ) << <STR_LIT> << printReg ( P . first , & ME . TRI ) << <STR_LIT> << ME . getCell ( RD , ResMap ) << <STR_LIT> ; } } for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; RegisterRef RD ( MO ) ; assert ( RD . Sub == <NUM_LIT> && <STR_LIT> ) ; if ( ! Register :: isVirtualRegister ( RD . Reg ) ) continue ; bool Changed = false ; if ( ! Eval || ResMap . count ( RD . Reg ) == <NUM_LIT> ) { uint16_t DefBW = ME . getRegBitWidth ( RD ) ; RegisterCell RefC = RegisterCell :: self ( RD . Reg , DefBW ) ; if ( RefC != ME . getCell ( RD , Map ) ) { ME . putCell ( RD , RefC , Map ) ; Changed = true ; } } else { RegisterCell DefC = ME . getCell ( RD , Map ) ;

RegisterCell ResC = ME . getCell ( RD , ResMap ) ;


<s> Value * <ISA_LIT>InstrSema :: translatePop ( unsigned OpSize ) { Value * OldSP = getReg ( <STR_LIT> ) ; Type * OpTy = IntegerType :: get ( * Ctx , OpSize * <NUM_LIT> ) ;

Value * OpSizeVal = ConstantInt :: get ( IntegerType :: get ( * Ctx , OldSP -> getType ( ) -> getIntegerBitWidth ( ) ) , OpSize ) ;


<s> next_cum = ( ROUND_ADVANCE_CUM ( next_cum , arg . mode , arg . type ) + ROUND_ADVANCE_ARG ( arg . mode , arg . type ) ) ; first_anon_arg = next_cum ; if ( first_anon_arg < MAX_EPIPHANY_PARM_REGS && ! no_rtl ) { int first_reg_offset = first_anon_arg ; * pretend_size = ( ( MAX_EPIPHANY_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ; } mf -> args_parsed = <NUM_LIT> ; mf -> pretend_args_odd = ( ( * pretend_size & UNITS_PER_WORD ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> op1 = operands [ <NUM_LIT> ] ; mask = operands [ <NUM_LIT> ] ; mode = GET_MODE ( dest ) ; vmode = GET_MODE ( mask ) ; dest = simplify_gen_subreg ( vmode , dest , mode , <NUM_LIT> ) ; x = gen_rtx_AND ( vmode , dest , mask ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , x ) ) ; if ( op0 != CONST0_RTX ( vmode ) ) {

x = gen_rtx_IOR ( vmode , dest , op0 ) ;


<s> static void nios2_asm_file_end ( void ) {

if ( TARGET_LINUX_ABI && trampolines_created ) file_end_indicate_exec_stack ( ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( CallingConv :: ID ) const { if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_RegMask ;

if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ;


<s> EVT SetCCType = DAG . getTargetLoweringInfo ( ) . getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue Max = DAG . getNode ( <STR_LIT> , DL , VT , Op1 , Op0 ) ; SDValue IsOp0Nan = DAG . getSetCC ( DL , SetCCType , Op0 , Op0 , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , IsOp0Nan , Op1 , Max ) ;


<s> case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ; case <STR_LIT> : return true ;


<s> gcc_assert ( REG_P ( op1 ) ) ; vperm = gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , op1 , op1 , sel ) , UNSPEC_VPERM ) ; emit_insn ( gen_rtx_SET ( VOIDmode , tmp , vperm ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , op0 , stvx ) ) ;


<s> else if ( CONSTANT_ADDRESS_P ( addr ) ) emit_call_insn ( gen_call_direct_clobber ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; else return <NUM_LIT> ; } else { if ( GET_CODE ( addr ) == REG ) emit_call_insn ( gen_call_indirect ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; else if ( CONSTANT_ADDRESS_P ( addr ) ) emit_call_insn ( gen_call_direct ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; else return <NUM_LIT> ; }


<s> bool enableInterleavedAccessVectorization ( ) {


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( bool Is64Bit , uint8_t OSABI ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , ELF :: EM_NONE , true ) {


<s> if ( Features . test ( FeatureISAVersion8_0_2 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion8_0_3 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion8_1_0 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureVolcanicIslands ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion9_0_0 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion9_0_2 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion9_0_4 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureISAVersion9_0_6 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( Features . test ( FeatureGFX9 ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ! Features . test ( FeatureGCN ) || Features . test ( FeatureSouthernIslands ) ) return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ;


<s> int opno = i - <NUM_LIT> + has_result ; if ( arg & <NUM_LIT> ) arg_type = ptr_type_node ; else if ( arg ) arg_type = ( * lang_hooks . types . type_for_mode ) ( insn_data [ d -> icode ] . operand [ opno ] . mode , ( arg & <NUM_LIT> ) ) ; else if ( i ) continue ; else arg_type = void_type_node ; if ( i == <NUM_LIT> ) break ; args [ i - <NUM_LIT> ] = arg_type ; } type = build_function_type_list ( arg_type , args [ <NUM_LIT> ] , args [ <NUM_LIT> ] , args [ <NUM_LIT> ] , NULL_TREE ) ; if ( signature < SH_BLTIN_NUM_SHARED_SIGNATURES ) shared [ signature ] = type ; } d -> fndecl = add_builtin_function ( d -> name , type , d - bdesc , BUILT_IN_MD , NULL , NULL_TREE ) ; if ( d -> icode == CODE_FOR_sts_fpscr ) sh_builtin_get_fpscr = d -> fndecl ; else if ( d -> icode == CODE_FOR_set_fpscr ) sh_builtin_set_fpscr = d -> fndecl ; }


<s> if ( NumBytes >= - <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; } else { unsigned OffHi = ( unsigned ) NumBytes >> <NUM_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( OffHi ) ;

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ;


<s> } if ( IS_IWMMXT_GR_REGNUM ( regno ) ) return <NUM_LIT> + regno - FIRST_IWMMXT_GR_REGNUM ; if ( IS_IWMMXT_REGNUM ( regno ) ) return <NUM_LIT> + regno - FIRST_IWMMXT_REGNUM ; return DWARF_FRAME_REGISTERS ;


if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MI -> getOperand ( i ) , MCOp , AP , IsDarwin ) ) OutMI . addOperand ( MCOp ) ;


<s> } getTargetStreamer ( ) -> emitFunctionType ( Sym ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Name = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; Sym -> setImportModule ( storeName ( Name ) ) ; getTargetStreamer ( ) -> emitImportModule ( Sym , Name ) ; } if ( F . hasFnAttribute ( <STR_LIT> ) ) { StringRef Name = InvokeDetected ? Sym -> getName ( ) : F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; Sym -> setImportName ( storeName ( Name ) ) ; getTargetStreamer ( ) -> emitImportName ( Sym , Name ) ; } } if ( F . hasFnAttribute ( <STR_LIT> ) ) { auto * Sym = cast < MCSymbolWasm > ( getSymbol ( & F ) ) ; StringRef Name = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; Sym -> setExportName ( storeName ( Name ) ) ; getTargetStreamer ( ) -> emitExportName ( Sym , Name ) ; }


<s> unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ;

if ( I -> getOpcode ( ) != <STR_LIT> && getCondFromBranchOpc ( I -> getOpcode ( ) ) == <STR_LIT> ) break ;


<s>
switch
(
Inst
)
{
case
OpenCL_std
::
vstore_half_r
:
case
OpenCL_std
::
vstore_halfn_r
:
case
OpenCL_std
::
vstorea_halfn_r
:
{
for
(
unsigned
i
=
NumFixedOps
;
i
<
NumOps
<NUM_LIT>
;
++
i
)
{
printOperand
(
MI
,
i
,
O
)
;
O
<<
' '
;
}
printSymbolicOperand
<
OperandCategory
::
FPRoundingModeOperand
>
(
MI
,
NumOps
<NUM_LIT>
,
O
)
;
break
;
}
default
:
printRemainingVariableOps
(
MI
,
NumFixedOps
,
O
,
true
)
;
}
}
else
{


<s> if ( Kind . isData ( ) && IsGlobalInSmallSection ( GV , TM , Kind ) ) return SmallDataSection ; return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV , Kind , Mang , TM ) ;


<s> void printCallOperand ( const MachineInstr * MI , unsigned OpNo ) { printOp ( MI -> getOperand ( OpNo ) ) ;


<s> case FK_Data_8 : Type = ELF :: R_MIPS_64 ; break ; case FK_GPRel_4 : Type = ELF :: R_MIPS_GPREL32 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GPREL16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_26 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_GOTTPREL ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_TPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_LDM ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_TLS_DTPREL_LO16 ; break ; case <STR_LIT> : case <STR_LIT> : Type = ELF :: R_MIPS_PC16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_DISP ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHER ; break ;


<s> return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ;


<s> <ISA_LIT>InstrAnalyzer ( MCContext & Ctx , const MCInstrInfo & MII ) : MCStreamer ( Ctx ) , MII ( MII ) , count ( <NUM_LIT> ) , size ( <NUM_LIT> ) , call ( false ) {


<s> const char * mips_output_load_label ( void ) { if ( TARGET_EXPLICIT_RELOCS ) switch ( mips_abi ) { case ABI_N32 : return <STR_LIT> ; case ABI_64 : return <STR_LIT> ;


<s> MachineFunction :: iterator FJ = F . begin ( ) ; if ( FJ != F . end ( ) ) FJ ++ ;

if ( FJ == F . end ( ) ) return Changed ;


<s> auto F = NBMap . find ( RN ) ; if ( F != NBMap . end ( ) ) return F -> second ; llvm_unreachable ( <STR_LIT> ) ;


<s> bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reserveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t InternalAmt = ( isDestroy && Amount ) ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const auto & Fn = MF . getFunction ( ) ; bool DwarfCFI = MMI . hasDebugInfo ( ) || Fn . needsUnwindTableEntry ( ) ; bool HasDwarfEHHandlers = ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) { BuildCFI ( MBB , I , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; } if ( Amount == <NUM_LIT> ) return I ; Amount -= InternalAmt ; if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , I , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ; int64_t StackAdjustment = isDestroy ? Amount : - Amount ; int64_t CfaAdjustment = - StackAdjustment ; if ( StackAdjustment ) { StackAdjustment += mergeSPUpdates ( MBB , I , true ) ; StackAdjustment += mergeSPUpdates ( MBB , I , false ) ; if ( StackAdjustment ) { BuildStackAdjustment ( MBB , I , DL , StackAdjustment , false ) ;