<s> if ( VectorWidth != <NUM_LIT> && VectorWidth != <NUM_LIT> && VectorWidth != <NUM_LIT> ) return false ; ConstantInt * ConstElemCount = nullptr ; if ( ! SE -> isLoopInvariant ( EC , L ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ( ConstElemCount = dyn_cast < ConstantInt > ( ElemCount ) ) ) { ConstantInt * TC = dyn_cast < ConstantInt > ( TripCount ) ; if ( ! TC ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } uint64_t TC1 = TC -> getZExtValue ( ) ; uint64_t TC2 = ( ConstElemCount -> getZExtValue ( ) + VectorWidth - <NUM_LIT> ) / VectorWidth ; if ( TC1 != TC2 ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TC1 << <STR_LIT> << TC2 << <STR_LIT> ) ; return false ; } } else if ( ! ForceTailPredication ) { auto * VW = SE -> getSCEV ( ConstantInt :: get ( TripCount -> getType ( ) , VectorWidth ) ) ; auto * ECPlusVWMinus1 = SE -> getAddExpr ( EC , SE -> getSCEV ( ConstantInt :: get ( TripCount -> getType ( ) , VectorWidth - <NUM_LIT> ) ) ) ; auto * Ceil = SE -> getUDivExpr ( ECPlusVWMinus1 , VW ) ; ( void ) TC ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; TC -> dump ( ) ; dbgs ( ) << <STR_LIT> ; EC -> dump ( ) ; dbgs ( ) << <STR_LIT> << VectorWidth << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; Ceil -> dump ( ) ; ) ; bool Zero = SE -> getMinusSCEV ( SE -> getBackedgeTakenCount ( L ) , SE -> getUDivExpr ( SE -> getAddExpr ( SE -> getMulExpr ( Ceil , VW ) , SE -> getNegativeSCEV ( VW ) ) , VW ) ) -> isZero ( ) ; if ( ! Zero ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ;


<s> if ( WithPreDec ) { O << '-' ; } if ( Base . getReg ( ) ) { printRegister ( Base . getReg ( ) , O ) ; } if ( WithPostInc ) { O << '+' ; } O << <STR_LIT> ; if ( Offset . isImm ( ) ) { O << Offset . getImm ( ) ; } else if ( Offset . isExpr ( ) ) { O << * Offset . getExpr ( ) ;


<s> Worklist . push_back ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; Worklist . push_back ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( N -> hasOneUse ( ) && Opcode == N -> use_begin ( ) -> getOpcode ( ) ) continue ; if ( RootWeights . count ( N ) ) continue ; RootWeights [ N ] = - <NUM_LIT> ; } RootWeights [ BasePtr . getNode ( ) ] = - <NUM_LIT> ; SDValue NewBasePtr = balanceSubTree ( BasePtr . getNode ( ) , true ) ; if ( N -> getOpcode ( ) == <STR_LIT> ) N = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , NewBasePtr , N -> getOperand ( <NUM_LIT> ) ) ; else N = CurDAG -> UpdateNodeOperands ( N , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NewBasePtr , N -> getOperand ( <NUM_LIT> ) ) ;


<s> bool isI16IntU10Immediate ( SDNode * N ) {

return ( N -> getOpcode ( ) == <STR_LIT> && isI16IntU10Immediate ( cast < ConstantSDNode > ( N ) ) ) ;


<s> SmallVector < PartialMappingIdx , <NUM_LIT> > OpRegBankIdx ( NumOperands ) ; getInstrPartialMappingIdxs ( MI , MRI , false , OpRegBankIdx ) ; SmallVector < const ValueMapping * , <NUM_LIT> > OpdsMapping ( NumOperands ) ; if ( ! getInstrValueMapping ( MI , OpRegBankIdx , OpdsMapping ) ) return InstructionMapping ( ) ; return InstructionMapping { DefaultMappingID , <NUM_LIT> , getOperandsMapping ( OpdsMapping ) , NumOperands } ;


<s> unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( Reg == <STR_LIT> ) { if ( isVarArg ) continue ; Reg = <STR_LIT> ; ( * MIB ) . setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . copyImplicitOps ( & * MI ) ; MI = MBB . erase ( MI ) ; } MIB . addReg ( Reg , getDefRegState ( true ) ) ; NumRegs = true ; } if ( NumRegs ) MBB . insert ( MI , & * MIB ) ; else MF . DeleteMachineInstr ( MIB ) ; return true ;


<s> <ISA_LIT>WinCOFFAsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter & InstPrinter ) : <ISA_LIT>TargetStreamer ( S ) , OS ( OS ) , InstPrinter ( InstPrinter ) {


<s> static __inline__ void spu_mfcdma32 ( volatile void * ls , unsigned int ea , unsigned int size , unsigned int tagid , unsigned int cmd ) {

si_wrch ( MFC_LSA , si_from_ptr ( ls ) ) ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> std :: vector < SpilledReg > & SpillLanes = SGPRToVGPRSpills [ FI ] ; if ( ! SpillLanes . empty ( ) ) return true ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned WaveSize = ST . getWavefrontSize ( ) ; unsigned Size = FrameInfo . getObjectSize ( FI ) ; assert ( Size >= <NUM_LIT> && Size <= <NUM_LIT> && <STR_LIT> ) ; assert ( TRI -> spillSGPRToVGPR ( ) && <STR_LIT> ) ; int NumLanes = Size / <NUM_LIT> ;

const MCPhysReg * CSRegs = MRI . getCalleeSavedRegs ( ) ;


<s> BitVector ReservedRegs = Subtarget . getRegisterInfo ( ) -> getReservedRegs ( MF ) ;

if ( ! ReservedRegs . test ( Reg ) && ! Subtarget . isRegisterReservedByUser ( Reg ) ) report_fatal_error ( Twine ( <STR_LIT> + StringRef ( RegName ) + <STR_LIT> ) ) ;


<s> int Size = Mask . size ( ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { if ( Mask [ i ] < <NUM_LIT> ) continue ; if ( ( Mask [ i ] % Size ) / LaneSize != i / LaneSize ) return false ; int LocalM = Mask [ i ] < Size ? Mask [ i ] % LaneSize : Mask [ i ] % LaneSize + LaneSize ;

if ( RepeatedMask [ i % LaneSize ] < <NUM_LIT> ) RepeatedMask [ i % LaneSize ] = LocalM ;


<s> In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ; return DAG . getNode ( ExtendInVecOpc , dl , VT , In ) ; } if ( Subtarget . hasInt256 ( ) ) return Op ; MVT HalfVT = VT . getHalfNumVectorElementsVT ( ) ; SDValue OpLo = DAG . getNode ( ExtendInVecOpc , dl , HalfVT , In ) ; if ( auto * Shuf = dyn_cast < ShuffleVectorSDNode > ( In ) ) if ( hasIdenticalHalvesShuffleMask ( Shuf -> getMask ( ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , OpLo , OpLo ) ; SDValue ZeroVec = DAG . getConstant ( <NUM_LIT> , dl , InVT ) ; SDValue Undef = DAG . getUNDEF ( InVT ) ; bool NeedZero = Opc == <STR_LIT> ;

SDValue OpHi = getUnpackh ( DAG , dl , InVT , In , NeedZero ? ZeroVec : Undef ) ;


<s> switch ( mode ) { case E_QImode : rotate_mode = QIshift ; break ; case E_HImode : rotate_mode = HIshift ; break ; case E_SImode : rotate_mode = SIshift ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ROTATERT : rotate_type = SHIFT_ASHIFT ; break ; case ROTATE : rotate_type = SHIFT_LSHIFTRT ; break ; default : gcc_unreachable ( ) ; } amount = INTVAL ( rotate_amount ) ; if ( amount < <NUM_LIT> ) amount = <NUM_LIT> ; if ( ( unsigned int ) amount > GET_MODE_BITSIZE ( mode ) ) amount = GET_MODE_BITSIZE ( mode ) ; if ( ( unsigned int ) amount > GET_MODE_BITSIZE ( mode ) / ( unsigned ) <NUM_LIT> ) { amount = GET_MODE_BITSIZE ( mode ) - amount ;


<s> XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , gen_frame_mem ( BLKmode , gen_rtx_PRE_MODIFY ( Pmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * num_regs ) ) ) , gen_rtx_UNSPEC ( BLKmode , gen_rtvec ( <NUM_LIT> , reg ) , UNSPEC_PUSH_MULT ) ) ; if ( dwarf_regs_mask & ( <NUM_LIT> << i ) ) { tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( SImode , stack_pointer_rtx ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_par_index ++ ) = tmp ; } break ; } } for ( j = <NUM_LIT> , i ++ ; j < num_regs ; i ++ ) { if ( mask & ( <NUM_LIT> << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; XVECEXP ( par , <NUM_LIT> , j ) = gen_rtx_USE ( VOIDmode , reg ) ; if ( dwarf_regs_mask & ( <NUM_LIT> << i ) ) { tmp = gen_rtx_SET ( VOIDmode , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * j ) ) , reg ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , dwarf_par_index ++ ) = tmp ; } j ++ ; } } par = emit_insn ( par ) ; tmp = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( dwarf , <NUM_LIT> , <NUM_LIT> ) = tmp ; add_reg_note ( par , REG_FRAME_RELATED_EXPR , dwarf ) ; return par ;


<s> const SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , In2L , In2H , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops ) ; cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; return ResNode ;


<s> if ( ValVT == <STR_LIT> || ( ValVT == <STR_LIT> && IntRegUsed ) ) { Reg = State . AllocateReg ( IntRegs , IntRegsSize ) ; IntRegUsed = true ; LocVT = <STR_LIT> ; } if ( ValVT . isFloatingPoint ( ) && ! IntRegUsed ) { if ( ValVT == <STR_LIT> ) Reg = State . AllocateReg ( F32Regs , FloatRegsSize ) ; else Reg = State . AllocateReg ( F64Regs , FloatRegsSize ) ; } if ( ValVT == <STR_LIT> && IntRegUsed ) { if ( UnallocIntReg != IntRegsSize ) { if ( IntRegs [ UnallocIntReg ] != ( unsigned ( <STR_LIT> ) ) ) Reg = <STR_LIT> ; for ( ; UnallocIntReg < IntRegsSize ; ++ UnallocIntReg ) State . AllocateReg ( UnallocIntReg ) ; } LocVT = <STR_LIT> ;


<s> const char * getPassName ( ) const override {


<s> const DataLayout * getDataLayout ( ) const override { return getSubtargetImpl ( ) -> getDataLayout ( ) ;


<s> DiagnosticPredicate isMatrixRegOperand ( ) const { if ( ! isMatrix ( ) ) return DiagnosticPredicateTy :: NoMatch ;

if ( getMatrixKind ( ) != Kind || ! <ISA_LIT>MCRegisterClasses [ RegClass ] . contains ( getMatrixReg ( ) ) || EltSize != getMatrixElementWidth ( ) ) return DiagnosticPredicateTy :: NearMatch ;


<s> virtual void emitARM64WinCFIClearUnwoundToCall ( ) {


<s> if ( TRI -> getEncodingValue ( DestReg ) < <NUM_LIT> ) { MIB -> setDesc ( LoadDesc ) ; } else { MIB -> setDesc ( BroadcastDesc ) ; DestReg = TRI -> getMatchingSuperReg ( DestReg , SubIdx , & <STR_LIT> ) ; MIB -> getOperand ( <NUM_LIT> ) . setReg ( DestReg ) ;


<s> RCPair <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' :


<s> return ( float32x2_t ) __builtin_neon_vpaddv2sf ( __a , __b ) ;


<s> EVT VecEVT = Vec . getValueType ( ) ; if ( ! isTypeLegal ( VecEVT ) ) return SDValue ( ) ; MVT VecVT = VecEVT . getSimpleVT ( ) ; MVT VecEltVT = VecVT . getVectorElementType ( ) ; unsigned RVVOpcode = getRVVVPReductionOp ( Op . getOpcode ( ) ) ; MVT ContainerVT = VecVT ; if ( VecVT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VecVT ) ;

Vec = convertToScalableVector ( ContainerVT , Vec , DAG , Subtarget ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TargetMachine ) : SelectionDAGISel ( TargetMachine ) {


<s> setAttributes ( * NewF , NewProps . Attributes ) ; NewF -> setVisibility ( GlobalValue :: DefaultVisibility ) ; NewF -> setLinkage ( GlobalValue :: InternalLinkage ) ; if ( F . hasName ( ) && F . hasLocalLinkage ( ) ) {

std :: string NewName = std :: string ( NewF -> getName ( ) ) ;


<s> if ( ( State . I == <NUM_LIT> ) && ( State . SaveCount == <NUM_LIT> ) ) { switch ( Inst . getOpcode ( ) ) { default : return false ; case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; case <STR_LIT> : State . SaveCount = <NUM_LIT> ; break ; } } if ( State . I < State . SaveCount ) { assert ( State . I < State . MaxSaved && <STR_LIT> ) ; State . Saved [ State . I ++ ] = Inst ; if ( State . I < State . SaveCount ) return true ; } assert ( State . I == State . SaveCount && State . SaveCount > <NUM_LIT> && <STR_LIT> ) ; State . RecursiveCall = true ; switch ( State . Saved [ <NUM_LIT> ] . getOpcode ( ) ) { default : break ; case <STR_LIT> : EmitDataMask ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : assert ( <NUM_LIT> && <STR_LIT> ) ; break ; case <STR_LIT> : EmitDirectGuardCall ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitIndirectGuardCall ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitIndirectGuardJmp ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> : EmitGuardReturn ( State . I , State . Saved , Out ) ; break ; case <STR_LIT> :

EmitGuardLoadOrStore ( State . I , State . Saved , Out ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;

PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ;


<s> case PROCESSOR_PPCE300C2 : case PROCESSOR_PPCE300C3 : case PROCESSOR_PPCE500MC : case PROCESSOR_PPCE500MC64 : case PROCESSOR_PPCE5500 : case PROCESSOR_PPCE6500 : case PROCESSOR_TITAN : return <NUM_LIT> ; case PROCESSOR_PPC476 : case PROCESSOR_PPC604 : case PROCESSOR_PPC604e : case PROCESSOR_PPC620 : case PROCESSOR_PPC630 : return <NUM_LIT> ; case PROCESSOR_POWER4 : case PROCESSOR_POWER5 : case PROCESSOR_POWER6 : case PROCESSOR_POWER7 : return <NUM_LIT> ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Changed = false ; for ( auto & MBB : MF ) processMachineBasicBlock ( MBB ) ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( ( int ) CI -> getSExtValue ( ) == CI -> getSExtValue ( ) ) Opc = <STR_LIT> ; break ; } if ( Opc ) { addFullAddress ( BuildMI ( MBB , DL , TII . get ( Opc ) ) , AM ) . addImm ( Signed ? CI -> getSExtValue ( ) : CI -> getZExtValue ( ) ) ; return true ; }


<s> if ( <ISA_LIT>MCInstrInfo :: isBundle ( MCB ) ) { bool hasConditional = false ; unsigned Branches = <NUM_LIT> , Returns = <NUM_LIT> , NewIndirectBranches = <NUM_LIT> , NewValueBranches = <NUM_LIT> , Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE , Unconditional = HEXAGON_PRESHUFFLE_PACKET_SIZE ; for ( unsigned i = <ISA_LIT>MCInstrInfo :: bundleInstructionsOffset ; i < MCB . size ( ) ; ++ i ) { MCInst const & MCI = * MCB . begin ( ) [ i ] . getInst ( ) ; if ( <ISA_LIT>MCInstrInfo :: isImmext ( MCI ) ) continue ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isBranch ( ) || <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isCall ( ) ) { ++ Branches ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . isIndirectBranch ( ) && <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) ++ NewIndirectBranches ; if ( <ISA_LIT>MCInstrInfo :: isNewValue ( MCII , MCI ) ) ++ NewValueBranches ; if ( <ISA_LIT>MCInstrInfo :: isPredicated ( MCII , MCI ) || <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) { hasConditional = true ;


<s> if ( ! isKnownNeverSNan ( DAG , Var ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SL , K0 -> getValueType ( <NUM_LIT> ) , Var , SDValue ( K0 , <NUM_LIT> ) , SDValue ( K1 , <NUM_LIT> ) ) ;


<s> if ( GET_CODE ( left ) == SIGN_EXTEND && GET_CODE ( right ) == SIGN_EXTEND ) * total = s390_cost -> m ; else if ( GET_CODE ( left ) == ZERO_EXTEND && GET_CODE ( right ) == ZERO_EXTEND && TARGET_CPU_ZARCH ) * total = s390_cost -> ml ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; } break ; } case SFmode : case DFmode : * total = s390_cost -> mult_df ; break ; case TFmode : * total = s390_cost -> mxbr ; break ; default : return false ; } return false ; case UDIV : case UMOD : if ( GET_MODE ( x ) == TImode ) * total = s390_cost -> dlgr ; else if ( GET_MODE ( x ) == DImode ) { rtx right = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( right ) == ZERO_EXTEND ) * total = s390_cost -> dlr ; else * total = s390_cost -> dlgr ; } else if ( GET_MODE ( x ) == SImode ) * total = s390_cost -> dlr ; return false ; case DIV : case MOD : if ( GET_MODE ( x ) == DImode ) { rtx right = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( right ) == ZERO_EXTEND ) if ( TARGET_64BIT ) * total = s390_cost -> dsgfr ; else * total = s390_cost -> dr ; else * total = s390_cost -> dsgr ; } else if ( GET_MODE ( x ) == SImode ) * total = s390_cost -> dlr ; else if ( GET_MODE ( x ) == SFmode ) { if ( TARGET_IEEE_FLOAT ) * total = s390_cost -> debr ; else * total = s390_cost -> der ; } else if ( GET_MODE ( x ) == DFmode ) { if ( TARGET_IEEE_FLOAT ) * total = s390_cost -> ddbr ; else * total = s390_cost -> ddr ; } else if ( GET_MODE ( x ) == TFmode ) { if ( TARGET_IEEE_FLOAT ) * total = s390_cost -> dxbr ; else * total = s390_cost -> dxr ; } return false ; case SQRT : if ( GET_MODE ( x ) == SFmode ) * total = s390_cost -> sqebr ; else if ( GET_MODE ( x ) == DFmode ) * total = s390_cost -> sqdbr ; else * total = s390_cost -> sqxbr ; return false ; case SIGN_EXTEND : case ZERO_EXTEND :

if ( outer_code == MULT || outer_code == DIV || outer_code == MOD || outer_code == PLUS || outer_code == MINUS || outer_code == COMPARE ) * total = <NUM_LIT> ;


<s> if ( ( Control & GPRControlBit [ I ] ) == <NUM_LIT> ) { unsigned Reg = <STR_LIT> [ I ] ; MI . addOperand ( MachineOperand :: CreateReg ( Reg , true , true ) ) ; } } if ( ! NoFloat && ( Control & <NUM_LIT> ) != <NUM_LIT> ) { if ( Subtarget . hasVector ( ) ) { for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; I ++ ) { unsigned Reg = <STR_LIT> [ I ] ; MI . addOperand ( MachineOperand :: CreateReg ( Reg , true , true ) ) ; }


<s> bool <ISA_LIT>RegisterInfo :: requiresFrameIndexScavenging ( const MachineFunction & MF ) const { return true ;


<s> const MCSection * <ISA_LIT>64LinuxTargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const { const MCSection * DefaultSection = TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV , Kind , Mang , TM ) ; if ( DefaultSection != ReadOnlySection ) return DefaultSection ;

const GlobalVariable * GVar = dyn_cast < GlobalVariable > ( GV ) ;


<s> rtx_code_label * neglab , * donelab ; rtx i0 , i1 , f0 , in , out ; machine_mode mode , inmode ; inmode = GET_MODE ( operands [ <NUM_LIT> ] ) ; gcc_assert ( inmode == SImode || inmode == DImode ) ; out = operands [ <NUM_LIT> ] ; in = force_reg ( inmode , operands [ <NUM_LIT> ] ) ; mode = GET_MODE ( out ) ; neglab = gen_label_rtx ( ) ; donelab = gen_label_rtx ( ) ; f0 = gen_reg_rtx ( mode ) ;

emit_cmp_and_jump_insns ( in , const0_rtx , LT , const0_rtx , inmode , <NUM_LIT> , neglab ) ;


<s> OutStreamer . SwitchSection ( fCodeSection ) ; O << <STR_LIT> << PAN :: getFrameLabel ( CurrentFnSym -> getName ( ) ) << <STR_LIT> ; O << <STR_LIT> << PAN :: getFrameLabel ( CurrentFnSym -> getName ( ) ) << <STR_LIT> ; O << * CurrentFnSym << <STR_LIT> ; DebugLoc CurDL ; O << <STR_LIT> ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { EmitBasicBlockStart ( I ) ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ;


<s> memset ( & new_opts_set , <NUM_LIT> , sizeof ( new_opts_set ) ) ; if ( ! s390_valid_target_attribute_inner_p ( args , opts , & new_opts_set , force_pragma ) ) return error_mark_node ; if ( new_opts_set . x_target_flags || new_opts_set . x_s390_arch || new_opts_set . x_s390_tune || new_opts_set . x_s390_stack_guard || new_opts_set . x_s390_stack_size || new_opts_set . x_s390_branch_cost || new_opts_set . x_s390_warn_framesize || new_opts_set . x_s390_warn_dynamicstack_p ) { const unsigned char * src = ( const unsigned char * ) opts_set ; unsigned char * dest = ( unsigned char * ) & new_opts_set ; unsigned int i ; for ( i = <NUM_LIT> ; i < sizeof ( * opts_set ) ; i ++ ) dest [ i ] |= src [ i ] ;

s390_option_override_internal ( opts , & new_opts_set ) ;


<s> FullFS += FS ; ParseSubtargetFeatures ( GPU , FullFS ) ; if ( getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS ) { FP32Denormals = false ;


<s> size_t DotPos = LowerReg . find ( '.' ) ; RegNum = MatchRegisterName ( LowerReg . substr ( <NUM_LIT> , DotPos ) ) ; if ( RegNum == <STR_LIT> ) { RegNum = StringSwitch < unsigned > ( LowerReg . substr ( <NUM_LIT> , DotPos ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; } if ( RegNum == <STR_LIT> ) return false ; SMLoc S = Tok . getLoc ( ) ; RegEndLoc = SMLoc :: getFromPointer ( S . getPointer ( ) + DotPos ) ; if ( DotPos == StringRef :: npos ) { Layout = StringRef ( ) ; } else { LayoutLoc = SMLoc :: getFromPointer ( S . getPointer ( ) + DotPos + <NUM_LIT> ) ; std :: string LayoutText = LowerReg . substr ( DotPos , StringRef :: npos ) ; Layout = StringSwitch < const char * > ( LayoutText ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ; if ( Layout . size ( ) == <NUM_LIT> ) { return false ; }


<s> enum attr_amdfam10_decode path = get_attr_amdfam10_decode ( insn ) ; if ( ( int ) path == <NUM_LIT> ) return path_single ;

if ( ( int ) path == <NUM_LIT> ) return path_double ;


<s> __rv . __o = __builtin_neon_vld4v8bf ( ( const __builtin_neon_bf * ) __ptr ) ;


<s> void setSVECalleeSavedStackSize ( unsigned Size ) {


<s> else if ( In16BitMode ) ToggleFeature ( <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <ISA_LIT>SSELevel << <STR_LIT> << <ISA_LIT>3DNowLevel << <STR_LIT> << Has<ISA_LIT>_64 << <STR_LIT> ) ; assert ( ( ! In64BitMode || Has<ISA_LIT>_64 ) && <STR_LIT> ) ; if ( StackAlignOverride ) stackAlignment = StackAlignOverride ;

else if ( isTargetDarwin ( ) || isTargetLinux ( ) || isTargetSolaris ( ) || isTargetNaCl ( ) || In64BitMode ) stackAlignment = <NUM_LIT> ;


<s> printAndVerify ( <STR_LIT> ) ; if ( addILPOpts ( ) ) printAndVerify ( <STR_LIT> ) ; addPass ( & MachineLICMID ) ; addPass ( & MachineCSEID ) ; addPass ( & MachineSinkingID ) ; printAndVerify ( <STR_LIT> ) ; addPass ( & PeepholeOptimizerID ) ; printAndVerify ( <STR_LIT> ) ;


<s> switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( stdarg_p ( fntype ) ) ix86_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , true ) ; max = cum -> regno + cfun -> va_list_gpr_size / UNITS_PER_WORD ; if ( max > X86_64_REGPARM_MAX ) max = X86_64_REGPARM_MAX ;


return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , true , false ) ;


<s> std :: vector < Type * > LocalVarTypes ; LocalVarTypes . reserve ( LocalVars . size ( ) ) ; std :: transform ( LocalVars . cbegin ( ) , LocalVars . cend ( ) , std :: back_inserter ( LocalVarTypes ) , [ ] ( const GlobalVariable * V ) -> Type * { return V -> getValueType ( ) ; } ) ; StructType * LDSTy = StructType :: create ( Ctx , LocalVarTypes , llvm :: StringRef ( <STR_LIT> ) ) ; Align MaxAlign = <STR_LIT> ( DL , LocalVars [ <NUM_LIT> ] ) ; Constant * InstanceAddress = Constant :: getIntegerValue ( PointerType :: get ( LDSTy , <ISA_LIT>AS :: LOCAL_ADDRESS ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; GlobalVariable * SGV = new GlobalVariable ( M , LDSTy , false , GlobalValue :: InternalLinkage , UndefValue :: get ( LDSTy ) , <STR_LIT> , nullptr , GlobalValue :: NotThreadLocal , <ISA_LIT>AS :: LOCAL_ADDRESS , false ) ; SGV -> setAlignment ( MaxAlign ) ; appendToCompilerUsed ( M , { static_cast < GlobalValue * > ( ConstantExpr :: getPointerBitCastOrAddrSpaceCast ( cast < Constant > ( SGV ) , Type :: getInt8PtrTy ( Ctx ) ) ) } ) ; removeFromUsedLists ( M , LocalVars ) ; Type * I32 = Type :: getInt32Ty ( Ctx ) ; for ( size_t I = <NUM_LIT> ; I < LocalVars . size ( ) ; I ++ ) { GlobalVariable * GV = LocalVars [ I ] ; Constant * GEPIdx [ ] = { ConstantInt :: get ( I32 , <NUM_LIT> ) , ConstantInt :: get ( I32 , I ) } ; GV -> replaceAllUsesWith ( ConstantExpr :: getGetElementPtr ( LDSTy , InstanceAddress , GEPIdx ) ) ; GV -> eraseFromParent ( ) ; } { IRBuilder < > Builder ( Ctx ) ; SmallPtrSet < Function * , <NUM_LIT> > Kernels ;


a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ;


<s> unsigned Type = cast < MCSymbolELF > ( Sym ) -> getType ( ) ; if ( ( Type == ELF :: STT_FUNC || Type == ELF :: STT_GNU_IFUNC ) ) { if ( Asm . isThumbFunc ( Sym ) && ( FixupKind == <STR_LIT> ) ) return true ; if ( ! Asm . isThumbFunc ( Sym ) && ( FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> ) ) return true ; } } if ( A && ( FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> || FixupKind == <STR_LIT> ) ) return true ; return false ;


<s> SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg2 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg3 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 , V2 , SubReg2 , V3 , SubReg3 } ;

return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops , <NUM_LIT> ) ;


<s> unsigned fastEmitInst_riir ( uint64_t inst , const TargetRegisterClass * RC , unsigned Op0 , uint64_t imm1 , uint64_t imm2 , unsigned Op3 ) { return <NUM_LIT> ;


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget -> getInstrInfo ( ) ) ;

return TII -> isInlineConstant ( Imm ) ;


<s> assert ( Displacement >= MinAllowedDisplacement && Displacement <= MaxAllowedDisplacement ) ;


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) { initialize<ISA_LIT>VSXFMAMutatePass ( * PassRegistry :: getPassRegistry ( ) ) ; insertPass ( VSXFMAMutateEarly ? & RegisterCoalescerID : & MachineSchedulerID , & <ISA_LIT>VSXFMAMutateID ) ; } if ( get<ISA_LIT>TargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) {


<s> else if ( ( thumb_index_register_rtx_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) || XEXP ( x , <NUM_LIT> ) == arg_pointer_rtx ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && thumb_legitimate_offset_p ( mode , INTVAL ( XEXP ( x , <NUM_LIT> ) ) ) ) return <NUM_LIT> ; else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( x , <NUM_LIT> ) ) == STACK_POINTER_REGNUM && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> && INTVAL ( XEXP ( x , <NUM_LIT> ) ) + GET_MODE_SIZE ( mode ) <= <NUM_LIT> && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; else if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && REGNO ( XEXP ( x , <NUM_LIT> ) ) == FRAME_POINTER_REGNUM && GET_MODE_SIZE ( mode ) >= <NUM_LIT> && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ;


<s> return create<ISA_LIT>MachineScheduler ( C ) ;


<s> else if ( DestRC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( DestRC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else if ( DestRC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; else {


<s> static <ISA_LIT>Operand * CreateBarrier ( unsigned Val , SMLoc S , MCContext & Ctx ) { <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Barrier , Ctx ) ; Op -> Barrier . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = S ;


<s> int size ; gcc_assert ( arg . mode != BLKmode ) ; if ( targetm . calls . strict_argument_naming ( arg_regs_used_so_far_v ) ) arg_regs_used_so_far += fr30_num_arg_regs ( arg ) ;

size = FR30_NUM_ARG_REGS - ( * arg_regs_used_so_far ) ;


<s> unsigned Opcode = OrOpc ; MachineBasicBlock * SplitBB = & MBB ; if ( NeedBlockSplit ) { SplitBB = MBB . splitAt ( MI , true , LIS ) ; Opcode = OrTermrOpc ; InsPt = MI ; } MachineInstr * NewMI = BuildMI ( MBB , InsPt , DL , TII -> get ( Opcode ) , Exec ) . addReg ( Exec ) . add ( MI . getOperand ( <NUM_LIT> ) ) ;


<s> print_mcus ( n_mcus ) ; n_mcus = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < sizeof ( avr_texinfo ) / sizeof ( * avr_texinfo ) ; i ++ ) if ( arch_id == avr_texinfo [ i ] . arch_id ) printf ( <STR_LIT> , mcu -> name , avr_texinfo [ i ] . texinfo ) ; }

else if ( arch_id == ( enum avr_arch_id ) mcu -> arch_id ) {


<s> if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType != MCOI :: OPERAND_PCREL ) return false ; int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; Target = Addr + Imm + <NUM_LIT> ; return true ;


<s> unsigned <ISA_LIT>TargetELFStreamer :: getEFlags ( ) { switch ( STI . getTargetTriple ( ) . getArch ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: r600 : return getEFlags<ISA_LIT> ( ) ; case Triple :: amdgcn :


<s> static const char * GetFPUName ( unsigned ID ) { switch ( ID ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; }


<s> if ( MFI -> hasVarSizedObjects ( ) ) { if ( needsStackRealignment ( MF ) ) return true ;

if ( MFI -> getLocalFrameSize ( ) < <NUM_LIT> ) return false ;


<s> if ( ! Subtarget -> supportsTailCall ( ) ) return false ; auto Attr = CI -> getParent ( ) -> getParent ( ) -> getFnAttribute ( <STR_LIT> ) ;

if ( ! CI -> isTailCall ( ) || Attr . getValueAsString ( ) == <STR_LIT> ) return false ;


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , RegScavenger * RS ) const { unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; DebugLoc dl = II -> getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } MachineOperand & SPOp = MI . getOperand ( i ) ; int FrameIndex = SPOp . getIndex ( ) ; int Offset = MFI -> getObjectOffset ( FrameIndex ) ;


<s> void <ISA_LIT>InstPrinter :: printPCLabel ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { abort ( ) ;


<s> return LowerSymbolOperand ( MI , MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; case MachineOperand :: MO_GlobalAddress : return LowerSymbolOperand ( MI , MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_JumpTableIndex : return LowerSymbolOperand ( MI , MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; case MachineOperand :: MO_MachineBasicBlock : return LowerSymbolOperand ( MI , MO , MO . getMBB ( ) -> getSymbol ( ) , AP ) ; case MachineOperand :: MO_RegisterMask : break ;


<s> SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewOp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) ) ; SDValue NewWOp = DAG . getNode ( N -> getOpcode ( ) , DL , <STR_LIT> , NewOp0 , NewOp1 ) ;

SDValue NewRes = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewWOp , DAG . getValueType ( <STR_LIT> ) ) ;


<s> UP . Partial = UP . Runtime = true ; UP . AllowExpensiveTripCount = true ; }

BaseT :: getUnrollingPreferences ( L , SE , UP ) ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( IsNotLiveIn ) {


<s> fprintf ( file , <STR_LIT> ) ; for ( i = CONST_VECTOR_NUNITS ( x ) ; i -- ; ) { rtx element ; element = CONST_VECTOR_ELT ( x , i ) ; fprintf ( file , pattern , INTVAL ( element ) ) ; }


<s> return <NUM_LIT> ; } MachineInstrBuilder MIB = BuildMI ( & MBB , DL , get ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ; for ( int i = <NUM_LIT> , e = Cond . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Cond [ i ] ) ; MIB . addMBB ( TBB ) ;

BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) { report_fatal_error ( <STR_LIT> ) ; } MachineBasicBlock & MBB = * MI . getParent ( ) ; if ( MFI . getStackID ( FrameIndex ) == TargetStackID :: <ISA_LIT>Vector ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : { MachineOperand StackSlot = MI . getOperand ( FIOperandNum ) ; unsigned Opcode = getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstr * StoreAddr = BuildMI ( MBB , II , DL , TII -> get ( Opcode ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( StackSlot ) . addImm ( <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return eliminateFrameIndex ( StoreAddr , <NUM_LIT> , <NUM_LIT> , RS ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand StackSlot = MI . getOperand ( FIOperandNum ) ; unsigned Opcode = getRegSizeInBits ( <STR_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; Register addr = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * StoreAddr = BuildMI ( MBB , II , DL , TII -> get ( Opcode ) , addr ) . add ( StackSlot ) . addImm ( <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( addr , false , false , false ) ; return eliminateFrameIndex ( StoreAddr , <NUM_LIT> , <NUM_LIT> , RS ) ; } default :


<s> bool IsTailCallReturn = false ; if ( MBB . end ( ) != MBBI ) { unsigned RetOpcode = MBBI -> getOpcode ( ) ; IsTailCallReturn = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; }

<ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;


<s> } if ( ! flag_non_call_exceptions || ! aarch64_could_trap_p ( f , mode ) ) attrs = aarch64_add_attribute ( <STR_LIT> , attrs ) ;

return aarch64_add_attribute ( <STR_LIT> , attrs ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: nvptx > X ( getThe<ISA_LIT>Target32 ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;

RegisterTarget < Triple :: nvptx64 > Y ( getThe<ISA_LIT>Target64 ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setExceptionPointerRegister ( <STR_LIT> ) ;

setExceptionSelectorRegister ( <STR_LIT> ) ;


<s> case <NUM_LIT> : return createRegOperand ( TBA_HI ) ; case <NUM_LIT> : return createRegOperand ( TMA_LO ) ; case <NUM_LIT> : return createRegOperand ( TMA_HI ) ; case <NUM_LIT> : return createRegOperand ( M0 ) ; case <NUM_LIT> : return createRegOperand ( SGPR_NULL ) ; case <NUM_LIT> : return createRegOperand ( EXEC_LO ) ; case <NUM_LIT> : return createRegOperand ( EXEC_HI ) ; case <NUM_LIT> : return createRegOperand ( SRC_SHARED_BASE ) ; case <NUM_LIT> : return createRegOperand ( SRC_SHARED_LIMIT ) ; case <NUM_LIT> : return createRegOperand ( SRC_PRIVATE_BASE ) ; case <NUM_LIT> : return createRegOperand ( SRC_PRIVATE_LIMIT ) ; case <NUM_LIT> : return createRegOperand ( SRC_POPS_EXITING_WAVE_ID ) ; case <NUM_LIT> : break ; case <NUM_LIT> : break ;

case <NUM_LIT> : return createRegOperand ( SCC ) ;


<s> if ( RsrcIntr -> IsImage ) { Info . ptrVal = MFI -> getImagePSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; Info . align . reset ( ) ; } else { Info . ptrVal = MFI -> getBufferPSV ( * MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) , CI . getArgOperand ( RsrcIntr -> RsrcArg ) ) ; } Info . flags = MachineMemOperand :: MODereferenceable ; if ( Attr . hasFnAttribute ( Attribute :: ReadOnly ) ) { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) , true ) ; if ( Info . memVT == <STR_LIT> ) { Info . memVT = memVTFromAggregate ( CI . getType ( ) ) ; } Info . flags |= MachineMemOperand :: MOLoad ; } else if ( Attr . hasFnAttribute ( Attribute :: WriteOnly ) ) { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getArgOperand ( <NUM_LIT> ) -> getType ( ) ) ; Info . flags |= MachineMemOperand :: MOStore ; } else { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MODereferenceable ; Info . flags |= MachineMemOperand :: MOVolatile ; } return true ; } switch ( IntrID ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ( CI . getType ( ) ) ; Info . ptrVal = CI . getOperand ( <NUM_LIT> ) ; Info . align . reset ( ) ;

Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerF128Call ( SDValue Op , SelectionDAG & DAG , RTLIB :: Libcall Call ) const { SmallVector < SDValue , <NUM_LIT> > Ops ( Op -> op_begin ( ) , Op -> op_end ( ) ) ; return makeLibCall ( DAG , Call , <STR_LIT> , Ops , false , SDLoc ( Op ) ) . first ;


<s> <ISA_LIT>Z80Subtarget :: <ISA_LIT>Z80Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , <ISA_LIT>Z80TargetMachine & TM ) : <ISA_LIT>Z80GenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM ) , TSInfo ( ) , m_MBC1 ( false ) , m_MBC2 ( false ) , m_MBC3 ( false ) , m_RAM ( false ) , m_Battery ( false ) , m_RTC ( false ) {


<s> unsigned getOccupancy ( ) const { return Occupancy ;


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBDXAddr20Encoding ( const MCInst & MI , unsigned OpNum , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const {

uint64_t Base = getMachineOpValue ( MI , MI . getOperand ( OpNum ) , Fixups , STI ) ;


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'b' : case 'r' : case 'f' : case 'd' : case 'v' : case 'y' : return C_RegisterClass ; case 'Z' : return C_Memory ; } } else if ( Constraint == <STR_LIT> ) { return C_RegisterClass ; } else if ( Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> || Constraint == <STR_LIT> ) { return C_RegisterClass ; } return TargetLowering :: getConstraintType ( Constraint ) ;


<s> unsigned OffsetOperandNo = ( FIOperandNum == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;

if ( MI . isInlineAsm ( ) ) OffsetOperandNo = FIOperandNum - <NUM_LIT> ;


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;


<s> if ( XINT ( x , <NUM_LIT> ) == UNSPEC_TLS ) return <NUM_LIT> ; default : return <NUM_LIT> ; }


<s> <ISA_LIT>AsmBackend ( const Target & T ) : TargetAsmBackend ( ) , TheTarget ( T ) {


<s> static void i386_solaris_elf_named_section ( const char * name , unsigned int flags , tree decl ) {

if ( TARGET_64BIT && strcmp ( name , <STR_LIT> ) == <NUM_LIT> ) {


<s> return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> rtx reg ; if ( GET_CODE ( set ) == SET && REG_P ( reg = SET_DEST ( set ) ) && find_reg_note ( insn , REG_UNUSED , reg ) == NULL_RTX ) { emit_insn_after ( nvptx_gen_shuffle ( reg , reg , master , SHUFFLE_IDX ) , insn ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreserved < SlotIndexes > ( ) ; AU . addPreserved < LiveIntervals > ( ) ; AU . addPreserved < LiveVariables > ( ) ; AU . addRequired < LiveIntervals > ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & F ) const override { return & Subtarget ;


<s> case <STR_LIT> : return PerformSELECTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformANDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformORCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> :

return PerformADDCombine ( N , DAG , DCI , Subtarget ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) {


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return hasFP ( MF ) ;


<s> TII = static_cast < const <ISA_LIT>InstrInfo * > ( ST . getInstrInfo ( ) ) ; TRI = ST . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; SchedModel . init ( & ST ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } for ( auto & MBB : MF ) { bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; MachineOperand * BaseOp ; int64_t Offset ; if ( TII -> getMemOperandWithOffset ( MI , BaseOp , Offset , TRI ) && BaseOp -> isReg ( ) ) { unsigned BaseReg = BaseOp -> getReg ( ) ; if ( PrevBaseReg == BaseReg ) { if ( ! SuppressSTP && shouldAddSTPToBlock ( MI . getParent ( ) ) ) break ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; SuppressSTP = true ; TII -> suppressLdStPair ( MI ) ; }


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> tmp = gen_rtx_PLUS ( word_mode , hard_frame_pointer_rtx , TARGET_64BIT ? GEN_INT ( - <NUM_LIT> ) : GEN_INT ( - <NUM_LIT> ) ) ; tmp = gen_rtx_MEM ( word_mode , tmp ) ; tmp -> volatil = <NUM_LIT> ;


<s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {


<s> return ( __m128i ) vec_mergeh ( ( __vector long ) __A , ( __vector long ) __B ) ;


<s> SDValue getAddrGPRel ( NodeTy * N , const SDLoc & DL , EVT Ty , SelectionDAG & DAG , bool IsN64 ) const { assert ( ! ABI . IsCheriPureCap ( ) ) ; assert ( ! Ty . isFatPointer ( ) ) ; SDValue GPRel = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getRegister ( IsN64 ? <STR_LIT> : <STR_LIT> , Ty ) , DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( Ty ) , GPRel ) ) ;


<s> unsigned RegClass = Desc . OpInfo [ OpNo ] . RegClass ; return ( AMDGPU :: SSrc_32RegClassID == RegClass ) || ( AMDGPU :: SSrc_64RegClassID == RegClass ) || ( AMDGPU :: VSrc_32RegClassID == RegClass ) || ( AMDGPU :: VSrc_64RegClassID == RegClass ) ;


<s> return ( uint8x8_t ) __builtin_aarch64_popcountv8qi ( ( int8x8_t ) __a ) ;


<s> b4 = remainder & <NUM_LIT> ; if ( loc > <NUM_LIT> ) { unsigned int tmp = b1 & b2 & b3 & b4 ; unsigned int tmp2 = tmp + ( tmp << <NUM_LIT> ) + ( tmp << <NUM_LIT> ) + ( tmp << <NUM_LIT> ) ; unsigned int matching_bytes = ( tmp == b1 ) + ( tmp == b2 ) + ( tmp == b3 ) + ( tmp == b4 ) ; if ( tmp && ( matching_bytes >= <NUM_LIT> || ( matching_bytes == <NUM_LIT> && const_ok_for_op ( remainder & ~ tmp2 , code ) ) ) ) { result = tmp2 ; i = tmp != b1 ? <NUM_LIT> : tmp != b2 ? <NUM_LIT> : tmp != b3 ? <NUM_LIT> : <NUM_LIT> ; } else if ( b1 == b3 && ( ! b2 || ! b4 || ( remainder & <NUM_LIT> & ~ result ) ) ) { result = remainder & <NUM_LIT> ; i = <NUM_LIT> ; } } else if ( loc > <NUM_LIT> ) { if ( b2 == b4 ) { result = remainder & <NUM_LIT> ; i = <NUM_LIT> ; } } } return_sequence -> i [ insns ++ ] = result ; remainder &= ~ result ; if ( code == SET || code == MINUS ) code = PLUS ; } while ( remainder ) ; return insns ;


<s> MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> static SDValue lowerV16F32VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ;

return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> } case <STR_LIT> : { int64_t StackAdj = MBBI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstrBuilder MIB ; if ( StackAdj == <NUM_LIT> ) { MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) ; } else if ( isUInt < <NUM_LIT> > ( StackAdj ) ) { MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( STI -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) . addImm ( StackAdj ) ; } else { assert ( ! STI -> is64Bit ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) ; <ISA_LIT>FL -> emitSPUpdate ( MBB , MBBI , DL , StackAdj , true ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; } for ( unsigned I = <NUM_LIT> , E = MBBI -> getNumOperands ( ) ; I != E ; ++ I ) MIB . add ( MBBI -> getOperand ( I ) ) ; MBB . erase ( MBBI ) ; return true ; } case <STR_LIT> : { bool IsSEH = isAsynchronousEHPersonality ( classifyEHPersonality ( MBB . getParent ( ) -> getFunction ( ) . getPersonalityFn ( ) ) ) ; <ISA_LIT>FL -> restoreWin32EHStackPointers ( MBB , MBBI , DL , IsSEH ) ; MBBI -> eraseFromParent ( ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const MachineOperand & InArg = MBBI -> getOperand ( <NUM_LIT> ) ; unsigned SaveRbx = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ActualInArg = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; TII -> copyPhysReg ( MBB , MBBI , DL , ActualInArg , InArg . getReg ( ) , InArg . isKill ( ) ) ; unsigned ActualOpc = Opcode == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; MachineInstr * NewInstr = BuildMI ( MBB , MBBI , DL , TII -> get ( ActualOpc ) ) ;

for ( unsigned Idx = <NUM_LIT> ; Idx < <NUM_LIT> ; ++ Idx ) NewInstr -> addOperand ( MBBI -> getOperand ( Idx ) ) ;


<s> Opc = StartBaseIsConstant ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : Opc = StartBaseIsConstant ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : Opc = StartBaseIsConstant ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : Opc = StartBaseIsConstant ? <STR_LIT> : <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( StartBase ) ; Ops . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , DL , ET ) ) ; SDNode * NewN = CurDAG -> getMachineNode ( Opc , DL , VT , Ops ) ; UnscaledOp = SDValue ( NewN , <NUM_LIT> ) ; return true ; } } if ( N . getOpcode ( ) == <STR_LIT> ) { SDValue Mod = N . getOperand ( <NUM_LIT> ) ; if ( Mod . getOpcode ( ) == <STR_LIT> || Mod . getOpcode ( ) == <STR_LIT> ) { auto * SplatVal = dyn_cast < ConstantSDNode > ( Mod . getOperand ( <NUM_LIT> ) ) ; if ( SplatVal && ( SplatVal -> getSExtValue ( ) == ( <NUM_LIT> << Scale ) ) ) { UnscaledOp = N . getOperand ( <NUM_LIT> ) ; return true ;


<s> FunctionPass * llvm :: create<ISA_LIT>ConstExtenders ( ) { return new <ISA_LIT>ConstExtenders ( ) ;


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> int Opc = Lookup ( OpcodeTable , Opcode ) ; assert ( Opc != - <NUM_LIT> && <STR_LIT> ) ;


<s> static bool eco32_return_in_memory ( const_tree type , const_tree fntype ATTRIBUTE_UNUSED ) { const HOST_WIDE_INT size = int_size_in_bytes ( type ) ; return ( size == - <NUM_LIT> || size > UNITS_PER_WORD ) ;


<s> bool Is64Bit = TT . isArch64Bit ( ) ; std :: string CPUName = std :: string ( CPU ) ; std :: string TuneCPUName = std :: string ( TuneCPU ) ; if ( CPUName . empty ( ) ) CPUName = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; ParseSubtargetFeatures ( CPUName , TuneCPUName , FS ) ; if ( Is64Bit ) {


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> const TargetRegisterClass * RC = getPhysRegClass ( SuperReg ) ; ArrayRef < int16_t > SplitParts = getRegSplitParts ( RC , EltSize ) ; unsigned NumSubRegs = SplitParts . empty ( ) ? <NUM_LIT> : SplitParts . size ( ) ; Register TmpVGPR ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : getSubReg ( SuperReg , SplitParts [ i ] ) ; if ( SpillToVGPR ) { <ISA_LIT>MachineFunctionInfo :: SpilledReg Spill = VGPRSpills [ i ] ; bool VGPRDefined = true ; if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; BuildMI ( * MBB , MI , DL , TII -> getMCOpcodeFromPseudo ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( IsKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; } else { if ( OnlyToVGPR ) return false ; if ( ! TmpVGPR . isValid ( ) ) TmpVGPR = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; MachineInstrBuilder Mov = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addReg ( SubReg , SubKillState ) ; if ( NumSubRegs > <NUM_LIT> ) { unsigned SuperKillState = <NUM_LIT> ; if ( i + <NUM_LIT> == e ) SuperKillState |= getKillRegState ( IsKill ) ; Mov . addReg ( SuperReg , RegState :: Implicit | SuperKillState ) ; } unsigned Align = FrameInfo . getObjectAlignment ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , Index , EltSize * i ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , EltSize , MinAlign ( Align , EltSize * i ) ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( TmpVGPR , RegState :: Kill ) . addFrameIndex ( Index ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getStackPtrOffsetReg ( ) ) . addImm ( i * <NUM_LIT> ) . addMemOperand ( MMO ) ; } } MI -> eraseFromParent ( ) ; MFI -> addToSpilledSGPRs ( NumSubRegs ) ; return true ;


return ( int16x4_t ) __builtin_neon_vmovnv4si ( __a ) ;


<s> return ( STI . isRV64 ( ) || STI . isRV32 ( ) ) ? <NUM_LIT> : <NUM_LIT> ;


<s> storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL = MBB . findDebugLoc ( I ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;

} else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> for ( unsigned i = <NUM_LIT> ; i < Ins . size ( ) ; ++ i ) { OriginalArgWasF128 . push_back ( originalTypeIsF128 ( RetTy , Call ) ) ; OriginalArgWasFloat . push_back ( RetTy -> isFloatingPointTy ( ) ) ;


<s> rtx aarch64_ptrue_all ( unsigned int elt_size ) { rtx_vector_builder builder ( VNx16BImode , elt_size , <NUM_LIT> ) ; builder . quick_push ( const1_rtx ) ;

for ( unsigned int i = <NUM_LIT> ; i < elt_size ; ++ i ) builder . quick_push ( const0_rtx ) ;


<s> return VT . bitsLE ( <STR_LIT> ) || Subtarget . atLeastM68020 ( ) ;


<s> SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } case <STR_LIT> : { SmallVector < SDValue , <NUM_LIT> > Ops = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , VTs , Ops ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } ReplaceUses ( N , Result ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( Result , <NUM_LIT> ) ) ;


<s> const TargetRegisterClass * RC64 = TLI . getRegClassFor ( <STR_LIT> ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { if ( I -> use_empty ( ) ) continue ; bool is32Bit = TLI . getValueType ( I -> getType ( ) ) == <STR_LIT> ; const TargetRegisterClass * RC = is32Bit ? RC32 : RC64 ; unsigned SrcReg = is32Bit ? GPR32ArgRegs [ Idx ] : GPR64ArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ;


<s> return selectVSplatCommon ( N , Imm , false , <NUM_LIT> ) ;


<s> static bool alpha_mode_dependent_address_p ( const_rtx addr , addr_space_t as ATTRIBUTE_UNUSED ) { return GET_CODE ( addr ) == AND ;


<s> if ( MO . isUse ( ) ) LocalUses . push_back ( Reg ) ; else LocalDefs . push_back ( Reg ) ; } for ( unsigned i = <NUM_LIT> , e = LocalUses . size ( ) ; i != e ; ++ i ) { unsigned Reg = LocalUses [ i ] ; Uses . insert ( Reg ) ; for ( MCSubRegIterator Subreg ( Reg , TRI ) ; Subreg . isValid ( ) ; ++ Subreg ) Uses . insert ( * Subreg ) ; } for ( unsigned i = <NUM_LIT> , e = LocalDefs . size ( ) ; i != e ; ++ i ) { unsigned Reg = LocalDefs [ i ] ; Defs . insert ( Reg ) ; for ( MCSubRegIterator Subreg ( Reg , TRI ) ; Subreg . isValid ( ) ; ++ Subreg ) Defs . insert ( * Subreg ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { default :


<s> SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; } else { SDValue Cst = DAG . getTargetConstantFP ( + <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ; } } else if ( VT . is512BitVector ( ) ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; } else if ( VT . getScalarType ( ) == <STR_LIT> ) { assert ( VT . getVectorNumElements ( ) <= <NUM_LIT> && <STR_LIT> ) ; SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops , VT . getVectorNumElements ( ) ) ;


<s> assert ( ValVT . getFixedSizeInBits ( ) < LocVT . getFixedSizeInBits ( ) ) ;

if ( Flags . isSExt ( ) ) ArgValue = DAG . getNode ( <STR_LIT> , dl , LocVT , ArgValue , DAG . getValueType ( ValVT ) ) ;


<s> } msp430x = xisa ; break ; } if ( i < <NUM_LIT> ) { if ( msp430_hwmult_type == AUTO ) { if ( msp430_warn_mcu ) { if ( target_cpu == NULL ) warning ( <NUM_LIT> , <STR_LIT> , target_mcu ) ; else warning ( <NUM_LIT> , <STR_LIT> , target_mcu ) ; } msp430_hwmult_type = NONE ; } else if ( target_cpu == NULL ) { if ( msp430_warn_mcu ) warning ( <NUM_LIT> , <STR_LIT> , target_mcu ) ; msp430x = false ; } else if ( msp430_warn_mcu ) warning ( <NUM_LIT> , <STR_LIT> , target_mcu ) ; } } if ( target_cpu == NULL && target_mcu == NULL && msp430_hwmult_type == F5SERIES ) msp430x = true ; if ( TARGET_LARGE && ! msp430x ) error ( <STR_LIT> ) ;

if ( msp430_code_region == UPPER && ! msp430x ) error ( <STR_LIT> ) ;


<s> return MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_SBREL , getContext ( ) ) ;


<s> extern __inline void __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _MM_SET_FLUSH_ZERO_MODE ( unsigned int __mode ) { _mm_setcsr ( ( _mm_getcsr ( ) & ~ _MM_FLUSH_ZERO_MASK ) | __mode ) ;


<s> Observer . changingInstr ( MI ) ; MI . setDesc ( ST . getInstrInfo ( ) -> get ( getDSFPAtomicOpcode ( IID ) ) ) ; for ( int I = <NUM_LIT> ; I > <NUM_LIT> ; -- I ) MI . removeOperand ( I ) ; MI . removeOperand ( <NUM_LIT> ) ; Observer . changedInstr ( MI ) ; return true ;


<s> TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ;

MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) :


<s> unsigned EFlags = MCA . getELFHeaderEFlags ( ) ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64R6 ; else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64R2 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_64 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_5 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_4 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_3 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_32R6 ; else if ( Features [ <STR_LIT> ] || Features [ <STR_LIT> ] || Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_32R2 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_32 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_ARCH_2 ; else EFlags |= ELF :: EF_MIPS_ARCH_1 ; if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_MIPS_NAN2008 ; EFlags |= ELF :: EF_MIPS_CPIC ;


<s> void <ISA_LIT>Z80AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) {

<ISA_LIT>Z80MCInstLower MCInstLowering ( OutContext , * this ) ;


<s> assert ( AS != <NUM_LIT> && <STR_LIT> ) ; if ( ! Ptr ) return false ;

return Ptr -> getType ( ) -> getPointerAddressSpace ( ) == AS ;


<s> static std :: string computeDataLayout ( const Triple & TT ) { std :: string Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; if ( ( TT . isArch64Bit ( ) && ( TT . getEnvironment ( ) == Triple :: GNUX32 || TT . isOSNaCl ( ) ) ) || ! TT . isArch64Bit ( ) ) Ret += <STR_LIT> ; if ( TT . isArch64Bit ( ) || TT . isOSWindows ( ) || TT . isOSNaCl ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( TT . isOSNaCl ( ) ) ; else if ( TT . isArch64Bit ( ) || TT . isOSDarwin ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ;

if ( TT . isArch64Bit ( ) ) Ret += <STR_LIT> ;


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( ! isPositionIndependent ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ;


<s> SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ; if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; SmallVector < int , <NUM_LIT> > RepeatedMask ; if ( is128BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , RepeatedMask ) ) { assert ( RepeatedMask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DAG ) ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ;

return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ;


<s> if ( GET_CODE ( op ) == CONST ) op = XEXP ( op , <NUM_LIT> ) ;

return ( GET_CODE ( op ) == PLUS && function_label_operand ( XEXP ( op , <NUM_LIT> ) , Pmode ) && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) ;


<s> Changed |= runEHOnFunction ( F ) ; } } if ( DoSjLj ) { Changed = true ; if ( LongjmpF ) { EmLongjmpJmpbufF = Function :: Create ( LongjmpF -> getFunctionType ( ) , GlobalValue :: ExternalLinkage , EmLongjmpJmpbufFName , & M ) ; LongjmpF -> replaceAllUsesWith ( EmLongjmpJmpbufF ) ; } if ( SetjmpF ) { FunctionType * SetjmpFTy = SetjmpF -> getFunctionType ( ) ; SmallVector < Type * , <NUM_LIT> > Params = { SetjmpFTy -> getParamType ( <NUM_LIT> ) , IRB . getInt32Ty ( ) , Type :: getInt32PtrTy ( C ) , IRB . getInt32Ty ( ) } ; FunctionType * FTy = FunctionType :: get ( Type :: getInt32PtrTy ( C ) , Params , false ) ; SaveSetjmpF = Function :: Create ( FTy , GlobalValue :: ExternalLinkage , SaveSetjmpFName , & M ) ; Params = { IRB . getInt32Ty ( ) , Type :: getInt32PtrTy ( C ) , IRB . getInt32Ty ( ) } ; FTy = FunctionType :: get ( IRB . getInt32Ty ( ) , Params , false ) ; TestSetjmpF = Function :: Create ( FTy , GlobalValue :: ExternalLinkage , TestSetjmpFName , & M ) ;

FTy = FunctionType :: get ( IRB . getVoidTy ( ) , { IRB . getInt32Ty ( ) , IRB . getInt32Ty ( ) } , false ) ;


<s> return __builtin_aarch64_cmgehf_uss ( __a , __b ) ;


<s> bool <ISA_LIT>PromoteKernelArguments :: promotePointer ( Value * Ptr ) { enqueueUsers ( Ptr ) ; PointerType * PT = cast < PointerType > ( Ptr -> getType ( ) ) ; if ( PT -> getAddressSpace ( ) != <ISA_LIT>AS :: FLAT_ADDRESS ) return false ; bool IsArg = isa < Argument > ( Ptr ) ; IRBuilder < > B ( IsArg ? ArgCastInsertPt : & * std :: next ( cast < Instruction > ( Ptr ) -> getIterator ( ) ) ) ; PointerType * NewPT = PointerType :: getWithSamePointeeType ( PT , <ISA_LIT>AS :: GLOBAL_ADDRESS ) ; Value * Cast = B . CreateAddrSpaceCast ( Ptr , NewPT , Twine ( Ptr -> getName ( ) , <STR_LIT> ) ) ; Value * CastBack = B . CreateAddrSpaceCast ( Cast , PT , Twine ( Ptr -> getName ( ) , <STR_LIT> ) ) ;

Ptr -> replaceUsesWithIf ( CastBack , [ Cast ] ( Use & U ) { return U . getUser ( ) != Cast ; } ) ;


<s> kill = false ; break ; } } if ( kill ) kill = ! LiveRegs . test ( Reg ) ; } if ( MO . isKill ( ) != kill ) { DEBUG ( dbgs ( ) << <STR_LIT> << MO << <STR_LIT> ) ; toggleKillFlag ( MI , MO ) ; DEBUG ( MI -> dump ( ) ) ; } killedRegs . set ( Reg ) ; } for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isUse ( ) || MO . isUndef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ( Reg == <NUM_LIT> ) || MRI . isReserved ( Reg ) ) continue ; LiveRegs . set ( Reg ) ; for ( MCSubRegIterator SubRegs ( Reg , TRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) LiveRegs . set ( * SubRegs ) ; }


<s> static bool RetCC_<ISA_LIT>32 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ;


<s> unsigned NumBytes = MFI -> getStackSize ( ) ; if ( FP ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } if ( NumBytes != <NUM_LIT> ) { if ( NumBytes <= <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( NumBytes ) ;

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> return ( int8x8_t ) __builtin_aarch64_subhnv8hi ( __a , __b ) ;


<s> assert ( Base . isReg ( ) && <STR_LIT> ) ; if ( ! Offset . isImm ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } Register B = Base . getReg ( ) ; if ( Register :: isStackSlot ( B ) || ! Register :: isVirtualRegister ( B ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } for ( auto & Add : MRI -> use_nodbg_instructions ( B ) ) { int64_t Incr ; if ( ! isAddConstantOp ( Add , Incr ) ) continue ; if ( ! isValidLoadStoreOffset ( Incr ) ) continue ; SmallVector < MachineInstr * , <NUM_LIT> > Uses ; MachineInstr * MoveTo = canJoinInstructions ( & Ldst , & Add , & Uses ) ; if ( ! MoveTo ) continue ; if ( ! canFixPastUses ( Uses , Add . getOperand ( <NUM_LIT> ) , B ) ) continue ; LLVM_DEBUG ( MachineInstr * First = & Ldst ; MachineInstr * Last = & Add ; if ( MDT -> dominates ( Last , First ) ) std :: swap ( First , Last ) ; dbgs ( ) << <STR_LIT> << * First << <STR_LIT> << * Last << <STR_LIT> ; ) ; MachineInstr * Result = Ldst . getNextNode ( ) ; if ( MoveTo == & Add ) { Ldst . removeFromParent ( ) ; Add . getParent ( ) -> insertAfter ( Add . getIterator ( ) , & Ldst ) ; } if ( Result == & Add ) Result = Result -> getNextNode ( ) ; fixPastUses ( Uses , B , Incr ) ;

int NewOpcode = <STR_LIT> ( Ldst . getOpcode ( ) ) ;


<s> if ( Ptr . getOpcode ( ) == <STR_LIT> ) { PtrOffsetC = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } GlobalAddressSDNode * PtrN = cast < GlobalAddressSDNode > ( Ptr . getNode ( ) ) ; SDValue TPtr = DAG . getTargetGlobalAddress ( PtrN -> getGlobal ( ) , DL , VT , <NUM_LIT> , <NUM_LIT> ) ; PtrOffsetC += PtrN -> getOffset ( ) ; assert ( PtrN -> getTargetFlags ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( SDValue Ld = LowerPtrAuthGlobalAddressViaGOT ( Wrapper , ( <STR_LIT> ) KeyC , HasAddrDiversity , PtrN , DAG ) ) return Ld ; if ( HasAddrDiversity ) { SDValue BlendIntID = DAG . getTargetConstant ( <STR_LIT> , DL , VT ) ; AddrDiscriminator = DAG . getNode ( <STR_LIT> , DL , VT , BlendIntID , AddrDiscriminator , Discriminator ) ; DiscriminatorC = <NUM_LIT> ; } SDValue PtrOffset = DAG . getTargetConstant ( PtrOffsetC , DL , <STR_LIT> ) ; SDValue Key = DAG . getTargetConstant ( KeyC , DL , <STR_LIT> ) ; Discriminator = DAG . getTargetConstant ( DiscriminatorC , DL , VT ) ; SDValue X16Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , SDValue ( ) ) ; SDValue X17Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , X16Copy . getValue ( <NUM_LIT> ) ) ;

SDNode * MOV = DAG . getMachineNode ( <STR_LIT> , DL , { <STR_LIT> , <STR_LIT> } , { TPtr , PtrOffset , Key , AddrDiscriminator , Discriminator , X17Copy . getValue ( <NUM_LIT> ) } ) ;


<s> rtx fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; emit_block_move ( tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ;

emit_move_insn ( adjust_address ( tramp , SImode , <NUM_LIT> ) , fnaddr ) ;


<s> bool <ISA_LIT>InstSelectorPass :: bounce_predicate ( SDNode * & op , SDValue & N , SDValue & out ) { int sz ; sz = op -> getNumOperands ( ) ; out = op -> getOperand ( sz - <NUM_LIT> ) ;


<s> if ( ! isTypeLegal ( RetTy , VT ) ) return false ; Value * Op1 = I . getOperand ( <NUM_LIT> ) ; Value * Op2 = I . getOperand ( <NUM_LIT> ) ; unsigned Reg1 = getRegForValue ( Op1 ) ; unsigned Reg2 = getRegForValue ( Op2 ) ; if ( Reg1 == <NUM_LIT> || Reg2 == <NUM_LIT> ) return false ; unsigned OpC = <NUM_LIT> ; if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else if ( VT == <STR_LIT> ) OpC = <STR_LIT> ; else return false ;

unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ;


<s> else FullFS = <STR_LIT> ; } if ( OL >= CodeGenOpt :: Default ) { if ( ! FullFS . empty ( ) ) FullFS = <STR_LIT> + FullFS ;


<s> StringRef getPassName ( ) const override {


<s> bool runOnMachineFunction ( MachineFunction & MF ) override {

if ( skipFunction ( MF . getFunction ( ) ) ) return false ;


<s> default : if ( AM . BaseOffs ) return false ; if ( ! VT . isSimple ( ) ) return false ; if ( Subtarget -> isThumb2 ( ) ) return isLegalT2ScaledAddressingMode ( AM , VT ) ; int Scale = AM . Scale ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Scale < <NUM_LIT> ) Scale = - Scale ; if ( Scale == <NUM_LIT> ) return true ; return isPowerOf2_32 ( Scale & ~ <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= <NUM_LIT> ) return true ; return false ; case <STR_LIT> : if ( Scale & <NUM_LIT> ) return false ;


<s> bool <ISA_LIT>AsmParser :: ParseDirectiveSubsection ( SMLoc L ) { const MCExpr * Subsection = nullptr ; int64_t Res ; assert ( ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) && <STR_LIT> ) ; getParser ( ) . parseExpression ( Subsection ) ; if ( ! Subsection -> evaluateAsAbsolute ( Res ) ) return Error ( L , <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return TokError ( <STR_LIT> ) ; if ( ( Res < <NUM_LIT> ) && ( Res > - <NUM_LIT> ) ) Subsection = <ISA_LIT>MCExpr :: create ( MCConstantExpr :: create ( <NUM_LIT> + Res , getContext ( ) ) , getContext ( ) ) ;

getStreamer ( ) . SubSection ( Subsection ) ;


<s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( TM -> getSubtargetImpl ( F ) ) , TLI ( ST -> getTargetLowering ( ) ) {


<s> static unsigned getFixupKindLog2Size ( unsigned Kind ) { switch ( Kind ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case FK_PCRel_1 : case FK_Data_1 : return <NUM_LIT> ; case FK_PCRel_2 : case FK_Data_2 : return <NUM_LIT> ; case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( ! Check ( S , DecodeDPairRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairSpacedRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; } if ( Rm != <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> && Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> unsigned NewReg = MRI . createVirtualRegister ( RegClass ) ; unsigned TeeReg = MRI . createVirtualRegister ( RegClass ) ; MRI . replaceRegWith ( Reg , NewReg ) ; MachineInstr * Tee = BuildMI ( MBB , Insert , Insert -> getDebugLoc ( ) , TII -> get ( GetTeeLocalOpcode ( RegClass ) ) , TeeReg ) . addReg ( NewReg , RegState :: Define ) . addReg ( Reg ) ; Op . setReg ( TeeReg ) ; Def -> getOperand ( <NUM_LIT> ) . setReg ( Reg ) ; LIS . InsertMachineInstrInMaps ( Tee ) ; LIS . shrinkToUses ( & LIS . getInterval ( Reg ) ) ;

LIS . createAndComputeVirtRegInterval ( NewReg ) ;


<s> TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; return true ; }


<s> const char * getPassName ( ) const override {


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N ) { unsigned NumElems = N -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> ) return false ; return isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) && isUndefOrEqual ( N -> getMaskElt ( <NUM_LIT> ) , <NUM_LIT> ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getThisReturnPreservedMask ( CallingConv :: ID CC ) const {

assert ( CC != CallingConv :: GHC && <STR_LIT> ) ;


<s> return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Imm & <NUM_LIT> || Imm > <NUM_LIT> ) return false ; if ( ! is<ISA_LIT>LowRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) && MI -> getOperand ( MCID . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return false ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm / <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; ++ NumNarrows ; return true ; } if ( Entry . LowRegs1 && ! VerifyLowRegs ( MI ) ) return false ; if ( MI -> mayLoadOrStore ( ) ) return ReduceLoadStore ( MBB , MI , Entry ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( * MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; LLVM_FALLTHROUGH ; case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , IsSelfLoop ) ) return true ;


<s> const char * fmt ; int used = <NUM_LIT> ; if ( ! x ) return used ; code = GET_CODE ( x ) ; switch ( code ) { case REG : if ( REGNO ( x ) < <NUM_LIT> ) return ( ( ( <NUM_LIT> << HARD_REGNO_NREGS ( <NUM_LIT> , GET_MODE ( x ) ) ) - <NUM_LIT> ) << ( REGNO ( x ) + is_dest ) ) ; return <NUM_LIT> ; case SUBREG : { rtx y = SUBREG_REG ( x ) ; if ( ! REG_P ( y ) ) break ;

if ( REGNO ( y ) < <NUM_LIT> ) return ( ( ( <NUM_LIT> << HARD_REGNO_NREGS ( <NUM_LIT> , GET_MODE ( x ) ) ) - <NUM_LIT> ) << ( REGNO ( y ) + subreg_regno_offset ( REGNO ( y ) , GET_MODE ( y ) , SUBREG_BYTE ( x ) , GET_MODE ( x ) ) + is_dest ) ) ;


<s> UpdateType Type = classifyUpdateByMask ( M ) ; if ( Type == Intermixed ) return false ; if ( Start == INT_MIN ) { Start = Stop = O ; updateMask ( M ) ; return true ; } else if ( Type == Descending && O == Start - <NUM_LIT> ) { Start -= <NUM_LIT> ; updateMask ( M ) ; return true ; } else if ( Type == Ascending && O == Stop + <NUM_LIT> ) { Stop += <NUM_LIT> ; updateMask ( M ) ;


<s> I ++ ; MachineBasicBlock & MBB = * MIB -> getParent ( ) ; MachineOperand MO = MIB -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = MIB -> getDebugLoc ( ) ; if ( isPush ) {

BuildMI ( MBB , I , DL , Desc ) . addReg ( RI . getStackRegister ( ) ) . add ( MO ) ;


<s> if ( ST -> hasMVEIntegerOps ( ) ) return true ; return false ;


<s> explicit <ISA_LIT>Z80MachineFunctionInfo ( MachineFunction & MF ) : HasSpills ( false ) , HasAllocas ( false ) , HasStackArgs ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) {


<s> <ISA_LIT>Z80PassConfig ( <ISA_LIT>Z80TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> static void concatenateMemOperands ( MachineInstr * MI , MachineInstr * Op0 , MachineInstr * Op1 ) { assert ( MI -> memoperands_empty ( ) && <STR_LIT> ) ; size_t numMemRefs = ( Op0 -> memoperands_end ( ) - Op0 -> memoperands_begin ( ) ) + ( Op1 -> memoperands_end ( ) - Op1 -> memoperands_begin ( ) ) ; MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; MachineSDNode :: mmo_iterator MemBegin = MF -> allocateMemRefsArray ( numMemRefs ) ; MachineSDNode :: mmo_iterator MemEnd = std :: copy ( Op0 -> memoperands_begin ( ) , Op0 -> memoperands_end ( ) , MemBegin ) ;

MemEnd = std :: copy ( Op1 -> memoperands_begin ( ) , Op1 -> memoperands_end ( ) , MemEnd ) ;


<s> OperandMatchResultTy Res = tryParseScalarRegister ( RegNum ) ; if ( Res != MatchOperand_Success ) return Res ; if ( ! ParseShiftExtend || getParser ( ) . getTok ( ) . isNot ( AsmToken :: Comma ) ) {

Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNum , RegKind :: Scalar , StartLoc , getLoc ( ) , getContext ( ) , EqTy ) ) ;


<s> const TargetMachine & TM = FuncInfo . MF -> getTarget ( ) ;

const <ISA_LIT>Subtarget * Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> void <ISA_LIT>PassConfig :: addFastRegAlloc ( ) {


<s> unsigned VF = cast < FixedVectorType > ( SrcTy ) -> getNumElements ( ) ; for ( unsigned P = <NUM_LIT> ; P < Log2Diff ; ++ P ) { if ( NumParts > <NUM_LIT> ) NumParts /= <NUM_LIT> ; Cost += NumParts ; }

if ( VF == <NUM_LIT> && SrcTy -> getScalarSizeInBits ( ) == <NUM_LIT> && DstTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) Cost -- ;


<s> <ISA_LIT>JITInfo * getJITInfo ( ) override {


<s> bool <ISA_LIT>MCInstrInfo :: isHVX ( MCInstrInfo const & MCII , MCInst const & MCI ) { const uint64_t V = getType ( MCII , MCI ) ; return <STR_LIT> <= V && V <= <STR_LIT> ;


<s> Value * <ISA_LIT>IREmitter :: visitHSUB ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> if ( ! IsLegalType ) return false ; if ( Op -> getOpcode ( ) != <STR_LIT> ) return false ; Base = Op -> getOperand ( <NUM_LIT> ) ; Offset = Op -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( Offset . getNode ( ) ) ) return false ; AM = <STR_LIT> ; int32_t V = cast < ConstantSDNode > ( Offset . getNode ( ) ) -> getSExtValue ( ) ; return Subtarget . getInstrInfo ( ) -> isValidAutoIncImm ( VT , V ) ;


<s> Register <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {

const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ;


<s> assert ( isInt < N > ( Value ) && <STR_LIT> ) ; O << Value ;


<s> if ( STI -> getFeatureBits ( ) . test ( FeatureSGPRInitBug ) ) return FIXED_NUM_SGPRS_FOR_INIT_BUG ; IsaVersion Version = getIsaVersion ( STI -> getCPU ( ) ) ; if ( Version . Major >= <NUM_LIT> ) return <NUM_LIT> ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; const MachineOperand & MO = MI -> getOperand ( OpNo ) ; assert ( MO . isReg ( ) && <STR_LIT> ) ; OS << <STR_LIT> << <ISA_LIT>InstPrinter :: getRegisterName ( MO . getReg ( ) ) << <STR_LIT> ;


<s> std :: map < unsigned , unsigned > & getFiTmpOffsetMap ( ) { return FiTmpOffsetMap ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> StringRef getPassName ( ) const override {


<s> } } break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; MemOpChains . push_back ( passArgOnStack ( StackPtr , VA . getLocMemOffset ( ) , Chain , Arg , DL , IsTailCall , DAG ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; bool IsPICCall = ( IsN64 || IsPIC ) ; bool GlobalOrExternal = false , InternalLinkage = false ; SDValue CalleeLo ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { if ( IsPICCall ) { InternalLinkage = G -> getGlobal ( ) -> hasInternalLinkage ( ) ; if ( InternalLinkage ) Callee = getAddrLocal ( Callee , DAG , Has<ISA_LIT>64 ) ; else if ( LargeGOT ) Callee = getAddrGlobalLargeGOT ( Callee , DAG , <STR_LIT> , <STR_LIT> ) ; else Callee = getAddrGlobal ( Callee , DAG , <STR_LIT> ) ; } else Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , getPointerTy ( ) , <NUM_LIT> , <STR_LIT> ) ; GlobalOrExternal = true ; } else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { if ( ! IsN64 && ! IsPIC ) Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , <STR_LIT> ) ; else if ( LargeGOT ) Callee = getAddrGlobalLargeGOT ( Callee , DAG , <STR_LIT> , <STR_LIT> ) ; else Callee = getAddrGlobal ( Callee , DAG , <STR_LIT> ) ; GlobalOrExternal = true ; } SmallVector < SDValue , <NUM_LIT> > Ops ( <NUM_LIT> , Chain ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; getOpndList ( Ops , RegsToPass , IsPICCall , GlobalOrExternal , InternalLinkage , CLI , Callee , Chain ) ; if ( IsTailCall ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; Chain = DAG . getNode ( <STR_LIT> , DL , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; SDValue InFlag = Chain . getValue ( <NUM_LIT> ) ;

Chain = DAG . getCALLSEQ_END ( Chain , NextStackOffsetVal , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , InFlag , DL ) ;


<s> if ( MaxMaxAlign >= <NUM_LIT> && VTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) >= <NUM_LIT> ) MaxAlign = <NUM_LIT> ; else if ( VTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) >= <NUM_LIT> && MaxAlign < <NUM_LIT> ) MaxAlign = <NUM_LIT> ; } else if ( ArrayType * ATy = dyn_cast < ArrayType > ( Ty ) ) { unsigned EltAlign = <NUM_LIT> ; getMaxByValAlign ( ATy -> getElementType ( ) , EltAlign , MaxMaxAlign ) ; if ( EltAlign > MaxAlign ) MaxAlign = EltAlign ; } else if ( StructType * STy = dyn_cast < StructType > ( Ty ) ) { for ( auto * EltTy : STy -> elements ( ) ) {


<s> static struct machine_function * tilegx_init_machine_status ( void ) {

return ggc_cleared_alloc < machine_function > ( ) ;


<s> return ( __mmask32 ) __builtin_ia32_kshiftrisi ( ( __mmask32 ) __A , ( __mmask8 ) __B ) ;


<s> if ( ! MEM_P ( mem ) ) return false ; if ( get_attr_indexed ( insn ) == INDEXED_YES || get_attr_update ( insn ) == UPDATE_YES ) return false ; machine_mode mem_mode = GET_MODE ( mem ) ; rtx addr = XEXP ( mem , <NUM_LIT> ) ; enum non_prefixed_form non_prefixed = reg_to_non_prefixed ( reg , mem_mode ) ; if ( non_prefixed == NON_PREFIXED_X && is_lfs_stfs_insn ( insn ) ) return address_is_prefixed ( addr , mem_mode , NON_PREFIXED_DEFAULT ) ;

else return address_is_prefixed ( addr , mem_mode , non_prefixed ) ;


<s> bool function_instance :: could_trap_p ( ) const { unsigned int flags = call_properties ( ) ;

if ( flags & CP_RAISE_FP_EXCEPTIONS ) return true ;


<s> break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; break ; case MachineOperand :: MO_BlockAddress :

MCOp = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP , isDarwin ) ;


<s> tmpInst . clear ( ) ; tmpInst . setOpcode ( is64Bit ? <STR_LIT> : <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: createReg ( AtRegNum ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createImm ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; tmpInst . addOperand ( MCOperand :: createReg ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; tmpInst . setLoc ( IDLoc ) ; Out . emitInstruction ( tmpInst , * STI ) ;


<s> return __aarch64_vdupq_lane_p8 ( __a , __b ) ;


<s> SDLoc DL ( Addr ) ; if ( ( C = dyn_cast < ConstantSDNode > ( Addr ) ) ) { Base = CurDAG -> getRegister ( AMDGPU :: INDIRECT_BASE_ADDR , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , DL , <STR_LIT> ) ; } else if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) && ( C = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( C -> getZExtValue ( ) , DL , <STR_LIT> ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_ostream & OS , uint8_t OSABI , bool IsLittleEndian ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ;

return createELFObjectWriter ( MOTW , OS , IsLittleEndian ) ;


<s> SDValue Op1 = convertToScalableVector ( DAG , ContainerVT , Op -> getOperand ( <NUM_LIT> ) ) ; SDValue Op2 = convertToScalableVector ( DAG , ContainerVT , Op -> getOperand ( <NUM_LIT> ) ) ; EVT MaskVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT MaskContainerVT = getContainerForFixedLengthVector ( DAG , MaskVT ) ; auto Mask = convertToScalableVector ( DAG , MaskContainerVT , Op . getOperand ( <NUM_LIT> ) ) ; Mask = DAG . getNode ( <STR_LIT> , DL , MaskContainerVT . changeVectorElementType ( <STR_LIT> ) , Mask ) ; auto ScalableRes = DAG . getNode ( <STR_LIT> , DL , ContainerVT , Mask , Op1 , Op2 ) ;

return convertFromScalableVector ( DAG , VT , ScalableRes ) ;


<s> if ( ( ! IsI1LowReg && ! IsI2LowReg ) || ! isEvenReg ( FirstRegIndex ) ) continue ; if ( ( IsI2LowReg && ! areCombinableOperations ( TRI , I1 , I2 ) ) || ( IsI1LowReg && ! areCombinableOperations ( TRI , I2 , I1 ) ) ) break ; if ( isSafeToMoveTogether ( I1 , I2 , I1DestReg , I2DestReg , DoInsertAtI1 ) ) return I2 ;


<s> SMLoc Loc = getLoc ( ) ; auto Res = parseIntWithPrefix ( Pref , Val ) ; if ( Res == MatchOperand_ParseFail ) return false ; if ( Res == MatchOperand_NoMatch ) return true ; if ( Val < <NUM_LIT> || Val > MaxVal ) { Error ( Loc , Twine ( <STR_LIT> , StringRef ( Pref ) ) ) ; return false ; }


<s> if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MachineInstr * Addi = BuildMI ( MBB , I , DL , TII -> get ( Opc1 ) , GPR3 ) . addReg ( InReg ) ; Addi -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; MachineBasicBlock :: iterator First = I ; -- First ; MachineInstr * Call = ( BuildMI ( MBB , I , DL , TII -> get ( Opc2 ) , GPR3 ) . addReg ( GPR3 ) ) ; Call -> addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( NeedFence ) BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , TII -> get ( TargetOpcode :: COPY ) , OutReg ) . addReg ( GPR3 ) ; MachineBasicBlock :: iterator Last = I ; -- Last ;


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ;

return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ;


<s> return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> bool hasScalarMulHiInsts ( ) const { return GFX9Insts ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList ) ) { State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; } else { State . addLoc ( CCValAssign :: getCustomMem ( ValNo , ValVT , State . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) , LocVT , LocInfo ) ) ;


<s> Instruction * InsertPos = PredBB -> getTerminator ( ) ; Instruction * NewInst = createReplacementInstr ( CE , InsertPos ) ; PN -> setOperand ( I , NewInst ) ; } } else if ( Instruction * Instr = dyn_cast < Instruction > ( WU ) ) { Instruction * NewInst = createReplacementInstr ( CE , Instr ) ; Instr -> replaceUsesOfWith ( CE , NewInst ) ; } else { ConstantExpr * CExpr = dyn_cast < ConstantExpr > ( WU ) ; if ( ! CExpr || ! replaceConstantExprOp ( CExpr , P ) ) return false ; } } } while ( CE -> hasNUsesOrMore ( <NUM_LIT> ) ) ; CE -> destroyConstant ( ) ;


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const { return LI -> getPointerAddressSpace ( ) == <ISA_LIT>AS :: PRIVATE_ADDRESS ? AtomicExpansionKind :: NotAtomic : AtomicExpansionKind :: None ;


<s> unsigned Reg = MO . getReg ( ) ; if ( ! MFI . isVRegStackified ( Reg ) ) { unsigned NewReg = MRI . createVirtualRegister ( MRI . getRegClass ( Reg ) ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( CopyLocalOpc ) , NewReg ) . addReg ( Reg ) ; MO . setReg ( NewReg ) ; MFI . stackifyVReg ( NewReg ) ; }


<s> if ( GV ) { if ( Optional < ConstantRange > CR = GV -> getAbsoluteSymbolRange ( ) ) { if ( CR -> getUnsignedMax ( ) . ult ( <NUM_LIT> ) ) return <STR_LIT> ; else return <STR_LIT> ; } } if ( TM . shouldAssumeDSOLocal ( M , GV ) ) return classifyLocalReference ( GV ) ; if ( isTargetCOFF ( ) ) { if ( GV -> hasDLLImportStorageClass ( ) ) return <STR_LIT> ; return <STR_LIT> ; } if ( isOSWindows ( ) ) return <STR_LIT> ; if ( is64Bit ( ) ) { if ( TM . getCodeModel ( ) == CodeModel :: Large ) return isTargetELF ( ) ? <STR_LIT> : <STR_LIT> ; return <STR_LIT> ; } if ( isTargetDarwin ( ) ) { if ( ! isPositionIndependent ( ) ) return <STR_LIT> ; return <STR_LIT> ; } return <STR_LIT> ;


<s> bool <ISA_LIT>MCInst :: isExtended ( void ) const { const uint64_t F = getDesc ( ) . TSFlags ;


<s> return getFromCapTable ( N , DL , Ty , DAG , Chain , PtrInfo , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> void addVTypeIOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> if ( N -> isMachineOpcode ( ) ) { N -> setNodeId ( - <NUM_LIT> ) ; return ; } switch ( N -> getOpcode ( ) ) { case <STR_LIT> : SelectConstant ( N ) ; return ; case <STR_LIT> : SelectConstantFP ( N ) ; return ; case <STR_LIT> : SelectFrameIndex ( N ) ;


<s> static std :: string computeDataLayout ( const <ISA_LIT>Subtarget & ST ) { std :: string Ret = <STR_LIT> ;

if ( ST . isLittle ( ) ) Ret += <STR_LIT> ;


<ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle ) , DL ( isLittle ? ( <STR_LIT> ) :


<s> if ( sign1 != sign2 ) return MCDisassembler :: Fail ; unsigned Val = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Val |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Val |= fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Val |= sign1 << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val ) ) ) ;


<s> auto AlignVectors :: createAlignedLoad ( IRBuilder < > & Builder , Type * ValTy , Value * Ptr , int Alignment , Value * Mask , Value * PassThru ) const -> Value * { assert ( ! HVC . isUndef ( Mask ) ) ; if ( HVC . isZero ( Mask ) ) return PassThru ;

if ( Mask == ConstantInt :: getTrue ( Mask -> getType ( ) ) ) return Builder . CreateAlignedLoad ( ValTy , Ptr , Align ( Alignment ) ) ;


<s> bool <ISA_LIT>AsmParser :: parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) { if ( ! parseAuthExpr ( Res , EndLoc ) ) return false ;

return getParser ( ) . parsePrimaryExpr ( Res , EndLoc ) ;


<s> if ( ! GWSResourcePSV ) { GWSResourcePSV = std :: make_unique < <ISA_LIT>GWSResourcePseudoSourceValue > ( TII ) ;