<s> extendOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : ldrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; strOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; extendOpc = <NUM_LIT> ; break ; } MachineBasicBlock * loopMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * exitMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; const TargetRegisterClass * TRC = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned scratch = MRI . createVirtualRegister ( TRC ) ; unsigned scratch2 = MRI . createVirtualRegister ( TRC ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; MachineInstrBuilder MIB = BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ; if ( ldrOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( MIB ) ; if ( signExtend && extendOpc ) { oldval = MRI . createVirtualRegister ( <STR_LIT> ) ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( extendOpc ) , oldval ) . addReg ( dest ) . addImm ( <NUM_LIT> ) ) ; } AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( oldval ) . addReg ( incr ) ) ; BuildMI ( BB , dl , TII -> get ( isThumb2 ? <STR_LIT> : <STR_LIT> ) , scratch2 ) . addReg ( oldval ) . addReg ( incr ) . addImm ( Cond ) . addReg ( <STR_LIT> ) ; MIB = BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ; if ( strOpc == <STR_LIT> ) MIB . addImm ( <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { return allocateCCRegs ( ValNo , ValVT , LocVT , LocInfo , ArgFlags , State , & <STR_LIT> , <NUM_LIT> ) ;


<s> if ( ! Subtarget . hasAVX2 ( ) ) { bool LaneCrossing [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> && ( ( Mask [ i ] % Size ) / LaneSize ) != ( i / LaneSize ) ) LaneCrossing [ ( Mask [ i ] % Size ) / LaneSize ] = true ; AllLanes = LaneCrossing [ <NUM_LIT> ] && LaneCrossing [ <NUM_LIT> ] ; } else { bool LaneUsed [ <NUM_LIT> ] = { false , false } ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) if ( Mask [ i ] >= <NUM_LIT> ) LaneUsed [ ( Mask [ i ] % Size ) / LaneSize ] = true ; AllLanes = LaneUsed [ <NUM_LIT> ] && LaneUsed [ <NUM_LIT> ] ; } assert ( V2 . isUndef ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > InLaneMask ( Mask . begin ( ) , Mask . end ( ) ) ; for ( int i = <NUM_LIT> ; i < Size ; ++ i ) { int & M = InLaneMask [ i ] ; if ( M < <NUM_LIT> ) continue ; if ( ( ( M % Size ) / LaneSize ) != ( i / LaneSize ) ) M = ( M % LaneSize ) + ( ( i / LaneSize ) * LaneSize ) + Size ; } assert ( ! is128BitLaneCrossingShuffleMask ( VT , InLaneMask ) && <STR_LIT> ) ; if ( ! AllLanes && ! is128BitLaneRepeatedShuffleMask ( VT , InLaneMask ) ) return splitAndLowerShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; MVT PVT = VT . isFloatingPoint ( ) ? <STR_LIT> : <STR_LIT> ;

SDValue Flipped = DAG . getBitcast ( PVT , V1 ) ;


<s> assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { Data [ Offset + i ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ; }


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> const MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction * MF = MBB . getParent ( ) ; const MCAsmInfo * MAI = MF -> getTarget ( ) . getMCAsmInfo ( ) ; { auto Op = MI . getOpcode ( ) ; if ( Op == <STR_LIT> || Op == <STR_LIT> ) return getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * MAI ) ; } if ( MI . isMetaInstruction ( ) ) return <NUM_LIT> ; unsigned NumBytes = <NUM_LIT> ; const MCInstrDesc & Desc = MI . getDesc ( ) ; switch ( Desc . getOpcode ( ) ) { default : NumBytes = <NUM_LIT> ; break ; case TargetOpcode :: STACKMAP : NumBytes = StackMapOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; break ; case TargetOpcode :: PATCHPOINT : NumBytes = PatchPointOpers ( & MI ) . getNumPatchBytes ( ) ; assert ( NumBytes % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; break ;


<s> SDLoc dl ( N ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && VT == <STR_LIT> ) { SDValue Ops64 [ ] = { Opd0 , CurDAG -> getTargetConstant ( LSB , dl , <STR_LIT> ) , CurDAG -> getTargetConstant ( MSB , dl , <STR_LIT> ) } ; SDNode * BFM = CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops64 ) ;

SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ;


<s> inline static CondCode suffixTo<ISA_LIT>CondCode ( StringRef S ) { return StringSwitch < CondCode > ( S ) . EndsWith ( <STR_LIT> , LPCC :: ICC_F ) . EndsWith ( <STR_LIT> , LPCC :: ICC_HI ) . EndsWith ( <STR_LIT> , LPCC :: ICC_UGT ) . EndsWith ( <STR_LIT> , LPCC :: ICC_LS ) . EndsWith ( <STR_LIT> , LPCC :: ICC_ULE ) . EndsWith ( <STR_LIT> , LPCC :: ICC_CC ) . EndsWith ( <STR_LIT> , LPCC :: ICC_ULT ) . EndsWith ( <STR_LIT> , LPCC :: ICC_CS ) . EndsWith ( <STR_LIT> , LPCC :: ICC_UGE ) . EndsWith ( <STR_LIT> , LPCC :: ICC_NE ) . EndsWith ( <STR_LIT> , LPCC :: ICC_EQ ) . EndsWith ( <STR_LIT> , LPCC :: ICC_VC ) . EndsWith ( <STR_LIT> , LPCC :: ICC_VS ) . EndsWith ( <STR_LIT> , LPCC :: ICC_PL ) . EndsWith ( <STR_LIT> , LPCC :: ICC_MI ) . EndsWith ( <STR_LIT> , LPCC :: ICC_GE ) . EndsWith ( <STR_LIT> , LPCC :: ICC_LT ) . EndsWith ( <STR_LIT> , LPCC :: ICC_GT ) . EndsWith ( <STR_LIT> , LPCC :: ICC_LE ) . EndsWith ( <STR_LIT> , LPCC :: ICC_T ) . Default ( LPCC :: UNKNOWN ) ;


<s> } unsigned LHSPenalty = <NUM_LIT> ; if ( ISD == <STR_LIT> || ISD == <STR_LIT> ) return LHSPenalty + TargetTransformInfo :: getVectorInstrCost ( Opcode , Val , Index ) ; return TargetTransformInfo :: getVectorInstrCost ( Opcode , Val , Index ) ;


<s> bool ProtectJTSupportPass :: runOnMachineFunction ( MachineFunction & Func ) { if ( ! Func . protectJT ( ) ) return false ; bool modified = false ; for ( MachineFunction :: iterator MBB = Func . begin ( ) ; MBB != Func . end ( ) ; MBB ++ ) { MachineBasicBlock :: iterator MI = MBB -> begin ( ) ; while ( MI != MBB -> end ( ) ) {

MachineBasicBlock :: iterator NMI = std :: next ( MI ) ;


return TARGET_RED_ZONE && ! TARGET_64BIT_MS_ABI ;


<s> MCContext & Ctx ; <ISA_LIT>AsmPrinter & AsmPrinter ; public : <ISA_LIT>MCInstLower ( Mangler * mang , MCContext & ctx , <ISA_LIT>AsmPrinter & asmPrinter ) ; void lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand lowerOperand ( const MachineOperand & MO ) const ; const MCExpr * getExpr ( const MachineOperand & MO , MCSymbolRefExpr :: VariantKind Kind ) const ;


<s> rtx set = XVECEXP ( real , <NUM_LIT> , i ) ; RTX_FRAME_RELATED_P ( set ) = <NUM_LIT> ; } RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; return insn ; } if ( reg == reg2 ) reg = gen_raw_REG ( GET_MODE ( reg ) , REGNO ( reg ) ) ; if ( reg == rreg ) reg = gen_raw_REG ( GET_MODE ( reg ) , REGNO ( reg ) ) ; real = copy_rtx ( PATTERN ( insn ) ) ; if ( reg2 != NULL_RTX ) real = replace_rtx ( real , reg2 , rreg ) ; if ( REGNO ( reg ) == STACK_POINTER_REGNUM ) gcc_checking_assert ( val == <NUM_LIT> ) ; else real = replace_rtx ( real , reg , gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) , GEN_INT ( val ) ) ) ; if ( GET_CODE ( real ) == SET ) { rtx set = real ;

temp = simplify_rtx ( SET_SRC ( set ) ) ;


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) {

Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ;


<s> bool isRegList ( ) const { return Kind == RegisterList ;


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) { KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - <NUM_LIT> ) ; } break ; case <STR_LIT> : { unsigned IntNo = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IntNo ) { case <STR_LIT> : KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : KnownZero = APInt :: getHighBitsSet ( KnownZero . getBitWidth ( ) , KnownZero . getBitWidth ( ) - <NUM_LIT> ) ;


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * ) const {


<s> StringRef getToken ( ) const { assert ( Kind == Token && <STR_LIT> ) ; return StringRef ( Tok . Data , Tok . Length ) ;


<s> AsmPrinter :: emitLinkage ( GV , Sym ) ;

const_cast < <ISA_LIT>AsmPrinter * > ( this ) -> emitExternalDecls ( * MMI -> getModule ( ) ) ;


<s> for ( SDValue V : Op . getNode ( ) -> ops ( ) ) DAG . ExtractVectorElements ( V , Elems ) ; return DAG . getBuildVector ( VecTy , dl , Elems ) ; } assert ( VecTy . getVectorElementType ( ) == <STR_LIT> ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; assert ( isPowerOf2_32 ( NumOp ) && HwLen % NumOp == <NUM_LIT> ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Subtarget . isHVXVectorType ( ty ( Op0 ) , true ) ) { if ( NumOp == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VecTy , Op0 , Op . getOperand ( <NUM_LIT> ) ) ; ArrayRef < SDUse > U ( Op . getNode ( ) -> ops ( ) ) ; SmallVector < SDValue , <NUM_LIT> > SV ( U . begin ( ) , U . end ( ) ) ; ArrayRef < SDValue > Ops ( SV ) ; MVT HalfTy = typeSplit ( VecTy ) . first ; SDValue V0 = DAG . getNode ( <STR_LIT> , dl , HalfTy , Ops . take_front ( NumOp / <NUM_LIT> ) ) ; SDValue V1 = DAG . getNode ( <STR_LIT> , dl , HalfTy , Ops . take_back ( NumOp / <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VecTy , V0 , V1 ) ; } unsigned BitBytes = HwLen / VecTy . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > Prefixes ; for ( SDValue V : Op . getNode ( ) -> op_values ( ) ) { SDValue P = createHvxPrefixPred ( V , dl , BitBytes , true , DAG ) ; Prefixes . push_back ( P ) ; } unsigned InpLen = ty ( Op . getOperand ( <NUM_LIT> ) ) . getVectorNumElements ( ) ; MVT ByteTy = <STR_LIT> ( <STR_LIT> , HwLen ) ; SDValue S = DAG . getConstant ( InpLen * BitBytes , dl , <STR_LIT> ) ; SDValue Res = getZero ( dl , ByteTy , DAG ) ; for ( unsigned i = <NUM_LIT> , e = Prefixes . size ( ) ; i != e ; ++ i ) { Res = DAG . getNode ( <STR_LIT> , dl , ByteTy , Res , S ) ; Res = DAG . getNode ( <STR_LIT> , dl , ByteTy , Res , Prefixes [ e - i - <NUM_LIT> ] ) ;


<s> if ( TARGET_FPU_DOUBLE && ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) ) return SH_ARG_FLOAT ; return SH_ARG_INT ;


<s> SDValue Ops [ <NUM_LIT> ] ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Ops [ i ] = DAG . getConstant ( i + Amt , <STR_LIT> ) ;

SDValue T = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ) ;


<s> <ISA_LIT>ExpandPseudo ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) {


<s> SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; if ( isI32Insn ( User , N ) ) continue ; return SDValue ( ) ; }

SDValue SubI32 = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ;


<s> MF -> insert ( It , loopMBB ) ; MF -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; unsigned scratch = RegInfo . createVirtualRegister ( <STR_LIT> ) ; unsigned scratch2 = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( ldrOpc ) , dest ) . addReg ( ptr ) ) ; if ( BinOpcode ) { if ( BinOpcode == <STR_LIT> || BinOpcode == <STR_LIT> ) AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( incr ) . addReg ( dest ) ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( BinOpcode ) , scratch2 ) . addReg ( dest ) . addReg ( incr ) ) . addReg ( <NUM_LIT> ) ; }

AddDefaultPred ( BuildMI ( BB , dl , TII -> get ( strOpc ) , scratch ) . addReg ( scratch2 ) . addReg ( ptr ) ) ;


<s> return h8300_move_length ( operands , & movl_length_table ) ; case LENGTH_TABLE_MOVA : return h8300_mova_length ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; case LENGTH_TABLE_MOVA_ZERO : return h8300_mova_length ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , const0_rtx ) ; case LENGTH_TABLE_UNARY : return h8300_unary_length ( operands [ <NUM_LIT> ] ) ; case LENGTH_TABLE_MOV_IMM4 : return <NUM_LIT> + h8300_classify_operand ( operands [ <NUM_LIT> ] , <NUM_LIT> , <NUM_LIT> ) ; case LENGTH_TABLE_SHORT_IMMEDIATE : return h8300_short_immediate_length ( operands [ <NUM_LIT> ] ) ; case LENGTH_TABLE_BITFIELD : return h8300_bitfield_length ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ;


<s> bool <ISA_LIT>InstrInfo :: hasVALU32BitEncoding ( unsigned Opcode ) const { return AMDGPU :: getVOPe32 ( Opcode ) != - <NUM_LIT> ;


<s> if ( useSVEForFixedLengthVectorVT ( Op . getValueType ( ) ) ) return LowerFixedLengthInsertVectorElt ( Op , DAG ) ; EVT VT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; ConstantSDNode * CI = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; if ( ! CI || CI -> getZExtValue ( ) >= VT . getVectorNumElements ( ) ) return SDValue ( ) ;

if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return Op ;


<s> return TargetTriple . isOSNaCl ( ) ;


<s> FCmp32Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: UO_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB :: OLT_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UGT ] = { { RTLIB :: OLE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULE ] = { { RTLIB :: OGT_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_ULT ] = { { RTLIB :: OGE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNE ] = { { RTLIB :: UNE_F32 , CmpInst :: ICMP_EQ } } ; FCmp32Libcalls [ CmpInst :: FCMP_UNO ] = { { RTLIB :: UO_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_ONE ] = { { RTLIB :: OGT_F32 , CmpInst :: BAD_ICMP_PREDICATE } , { RTLIB :: OLT_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp32Libcalls [ CmpInst :: FCMP_UEQ ] = { { RTLIB :: OEQ_F32 , CmpInst :: BAD_ICMP_PREDICATE } , { RTLIB :: UO_F32 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp64Libcalls . resize ( CmpInst :: LAST_FCMP_PREDICATE + <NUM_LIT> ) ; FCmp64Libcalls [ CmpInst :: FCMP_OEQ ] = { { RTLIB :: OEQ_F64 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp64Libcalls [ CmpInst :: FCMP_OGE ] = { { RTLIB :: OGE_F64 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp64Libcalls [ CmpInst :: FCMP_OGT ] = { { RTLIB :: OGT_F64 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp64Libcalls [ CmpInst :: FCMP_OLE ] = { { RTLIB :: OLE_F64 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp64Libcalls [ CmpInst :: FCMP_OLT ] = { { RTLIB :: OLT_F64 , CmpInst :: BAD_ICMP_PREDICATE } } ; FCmp64Libcalls [ CmpInst :: FCMP_ORD ] = { { RTLIB :: UO_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_UGE ] = { { RTLIB :: OLT_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_UGT ] = { { RTLIB :: OLE_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_ULE ] = { { RTLIB :: OGT_F64 , CmpInst :: ICMP_EQ } } ; FCmp64Libcalls [ CmpInst :: FCMP_ULT ] = { { RTLIB :: OGE_F64 , CmpInst :: ICMP_EQ } } ;

FCmp64Libcalls [ CmpInst :: FCMP_UNE ] = { { RTLIB :: UNE_F64 , CmpInst :: ICMP_EQ } } ;


<s> Input . erase ( InputIt ) ; return Temp ; } } TensorInfo * Temp = new TensorInfo ; Temp -> Order = INVALID_SCEV ; return * Temp ; } else if ( Type1 == TensorType :: Output ) { for ( auto OutputIt = Output . begin ( ) ; OutputIt != Output . end ( ) ; ++ OutputIt ) { TensorInfo Temp = * OutputIt ; if ( Temp . Order == TensorId ) { Output . erase ( OutputIt ) ; return Temp ; } } TensorInfo * Temp = new TensorInfo ; Temp -> Order = INVALID_SCEV ; return * Temp ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpMask = ~ <NUM_LIT> ; CmpValue = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ; CmpMask = ~ <NUM_LIT> ; CmpValue = ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) ; return true ; case <STR_LIT> : case <STR_LIT> : SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg2 = <NUM_LIT> ;


<s> return getParser ( ) . Error ( L , Msg , Ranges ) ;


<s> SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ;

if ( ( T . getOS ( ) == Triple :: OpenBSD || T . getOS ( ) == Triple :: Bitrig ) && T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = nullptr ;


<s> static void arm_option_restore ( struct gcc_options * , struct cl_target_option * ptr ) { arm_configure_build_target ( & arm_active_target , ptr , & global_options_set , false ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < NumElm ; i ++ ) { APInt Val = SplatValue . extractBits ( ScalarSize , ScalarSize * i ) ; Constant * Const ; if ( VT . isFloatingPoint ( ) ) { assert ( ( ScalarSize == <NUM_LIT> || ScalarSize == <NUM_LIT> ) && <STR_LIT> ) ;

if ( ScalarSize == <NUM_LIT> ) Const = ConstantFP :: get ( Type :: getFloatTy ( C ) , Val . bitsToFloat ( ) ) ;


<s> enum machine_mode mode = GET_MODE ( mem ) ; rtx label , x , cond = gen_rtx_REG ( DImode , REGNO ( scratch ) ) ; emit_insn ( gen_memory_barrier ( ) ) ; label = gen_label_rtx ( ) ; emit_label ( label ) ; label = gen_rtx_LABEL_REF ( DImode , label ) ;

if ( before == NULL ) before = scratch ;


<s> unsigned StackAlignment = TFI . getStackAlignment ( ) ; uint64_t AlignMask = StackAlignment - <NUM_LIT> ; int64_t Offset = StackSize ; unsigned SlotSize = RegInfo -> getSlotSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask ) ) ; } else { Offset = ( ( ~ AlignMask ) & Offset ) + StackAlignment + ( StackAlignment - SlotSize ) ; }


<s> for ( int i = <NUM_LIT> ; i < n ; i ++ ) if ( ! SCALAR_FLOAT_TYPE_P ( fields [ i ] . type ) ) return <NUM_LIT> ; return n > <NUM_LIT> ? n : <NUM_LIT> ;


if ( REG_P ( dest ) && REGNO ( dest ) == other_def -> regno ( ) && REG_NREGS ( dest ) == <NUM_LIT> && parallelize_insns ( cc_def , cc_set , other_def , other_set ) ) return ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {


<s> const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; assert ( MO . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; MCOperand MCRegOP = MCOperand :: createReg ( MO . getReg ( ) ) ; if ( ! isPositionIndependent ( ) ) { switch ( TM . getCodeModel ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , MCRegOP , OutContext , STI ) ; break ; case CodeModel :: Medium : { EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_H44 , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_M44 , MCRegOP , OutContext , STI ) ; MCOperand imm = MCOperand :: createExpr ( MCConstantExpr :: create ( <NUM_LIT> , OutContext ) ) ; EmitSHL ( * OutStreamer , MCRegOP , imm , MCRegOP , STI ) ; MCOperand lo = create<ISA_LIT>MCOperand ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_L44 , GOTLabel , OutContext ) ; EmitOR ( * OutStreamer , MCRegOP , lo , MCRegOP , STI ) ; break ; } case CodeModel :: Large : { EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HH , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HM , MCRegOP , OutContext , STI ) ; MCOperand imm = MCOperand :: createExpr ( MCConstantExpr :: create ( <NUM_LIT> , OutContext ) ) ; EmitSHL ( * OutStreamer , MCRegOP , imm , MCRegOP , STI ) ; MCOperand RegO7 = MCOperand :: createReg ( <STR_LIT> ) ; EmitHiLo ( * OutStreamer , GOTLabel , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO , RegO7 , OutContext , STI ) ; EmitADD ( * OutStreamer , MCRegOP , RegO7 , MCRegOP , STI ) ; } } return ; } MCSymbol * StartLabel = OutContext . createTempSymbol ( ) ; MCSymbol * EndLabel = OutContext . createTempSymbol ( ) ; MCSymbol * SethiLabel = OutContext . createTempSymbol ( ) ; MCOperand RegO7 = MCOperand :: createReg ( <STR_LIT> ) ; OutStreamer -> EmitLabel ( StartLabel ) ; MCOperand Callee = createPCXCallOP ( EndLabel , OutContext ) ; EmitCall ( * OutStreamer , Callee , STI ) ; OutStreamer -> EmitLabel ( SethiLabel ) ;

MCOperand hiImm = createPCXRelExprOp ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PC22 , GOTLabel , StartLabel , SethiLabel , OutContext ) ;


<s> void MLxExpansion :: pushStack ( MachineInstr * MI ) { LastMIs [ MIIdx ] = MI ;

if ( ++ MIIdx == <NUM_LIT> ) MIIdx = <NUM_LIT> ;


<s> RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ;

TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ;


<s> initialize<ISA_LIT>TransformIntrinPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> assert ( ! convertAddSubFlagsOpcode ( MI -> getOpcode ( ) ) && <STR_LIT> ) ; return ; } const MCInstrDesc * MCID = & MI -> getDesc ( ) ; unsigned NewOpc = convertAddSubFlagsOpcode ( MI -> getOpcode ( ) ) ; if ( NewOpc ) { const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getInstrInfo ( ) ) ; MCID = & TII -> get ( NewOpc ) ; assert ( MCID -> getNumOperands ( ) == MI -> getDesc ( ) . getNumOperands ( ) + <NUM_LIT> && <STR_LIT> ) ; MI -> setDesc ( * MCID ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <NUM_LIT> , true ) ) ; } unsigned ccOutIdx = MCID -> getNumOperands ( ) - <NUM_LIT> ; if ( ! MI -> hasOptionalDef ( ) || ! MCID -> OpInfo [ ccOutIdx ] . isOptionalDef ( ) ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } bool definesCPSR = false ; bool deadCPSR = false ; for ( unsigned i = MCID -> getNumOperands ( ) , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) { definesCPSR = true ; if ( MO . isDead ( ) ) deadCPSR = true ; MI -> RemoveOperand ( i ) ; break ; } } if ( ! definesCPSR ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } assert ( deadCPSR == ! Node -> hasAnyUseOfValue ( <NUM_LIT> ) && <STR_LIT> ) ;


<s> explicit CountValue ( int64_t i ) : Kind ( CV_Immediate ) , Contents ( i ) , isNegative ( i < <NUM_LIT> ) {


<s> static SDNode * getInt64 ( SelectionDAG * CurDAG , SDNode * N ) { SDLoc dl ( N ) ; int64_t Imm = cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ;


<s> LLVM_DEBUG ( dbgs ( ) << '?' ) ; } break ; case <STR_LIT> : KnownZero = HalfCarry | Subtract | Carry ; KnownOne = <NUM_LIT> ; break ; case <STR_LIT> : KnownZero = HalfCarry | Subtract ; KnownOne = Carry ; break ;


<s> if ( fn -> decl == NULL ) return true ; if ( fn -> stdarg ) return true ; for ( t = DECL_ARGUMENTS ( fn -> decl ) ; t ; t = TREE_CHAIN ( t ) ) { if ( ! use_register_for_decl ( t ) ) return true ; if ( DECL_MODE ( t ) != SImode ) return true ; }


<s> FunctionPass * llvm :: create<ISA_LIT>WinAllocaExpander ( ) { return new <ISA_LIT>WinAllocaExpander ( ) ;


<s> <STR_LIT> To = getLegalType ( getSimpleType ( ZExt -> getType ( ) ) ) ; unsigned In = getRegForValue ( Op ) ; if ( In == <NUM_LIT> ) return false ; unsigned Reg = zeroExtend ( In , Op , From , To ) ;


<s> if ( ! isTypeSupported ( I -> getType ( ) , VT , true ) || cast < LoadInst > ( I ) -> isAtomic ( ) ) return false ; Address Addr ; if ( ! computeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr , I -> getType ( ) ) ) return false ; bool WantZExt = true ; MVT RetVT = VT ; const Value * IntExtVal = nullptr ; if ( I -> hasOneUse ( ) ) { if ( const auto * ZE = dyn_cast < ZExtInst > ( I -> use_begin ( ) -> getUser ( ) ) ) { if ( isTypeSupported ( ZE -> getType ( ) , RetVT ) ) IntExtVal = ZE ; else RetVT = VT ; } else if ( const auto * SE = dyn_cast < SExtInst > ( I -> use_begin ( ) -> getUser ( ) ) ) { if ( isTypeSupported ( SE -> getType ( ) , RetVT ) ) IntExtVal = SE ; else RetVT = VT ; WantZExt = false ; } } unsigned ResultReg = emitLoad ( VT , RetVT , Addr , WantZExt , createMachineMemOperandFor ( I ) ) ; if ( ! ResultReg ) return false ; if ( IntExtVal ) { unsigned Reg = lookUpRegForValue ( IntExtVal ) ; if ( ! Reg ) { if ( RetVT == <STR_LIT> && VT <= <STR_LIT> ) { if ( WantZExt ) { std :: prev ( FuncInfo . InsertPt ) -> eraseFromParent ( ) ; ResultReg = std :: prev ( FuncInfo . InsertPt ) -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else ResultReg = fastEmitInst_extractsubreg ( <STR_LIT> , ResultReg , true , <STR_LIT> ) ; } updateValueMap ( I , ResultReg ) ; return true ; } while ( Reg ) { auto * MI = MRI . getUniqueVRegDef ( Reg ) ; if ( ! MI ) break ; Reg = <NUM_LIT> ; for ( auto & Opnd : MI -> uses ( ) ) { if ( Opnd . isReg ( ) ) { Reg = Opnd . getReg ( ) ; break ; } } MI -> eraseFromParent ( ) ; } updateValueMap ( IntExtVal , ResultReg ) ; return true ;


<s> maskcmp = true ; cmp_mode = nbits > <NUM_LIT> ? int_mode_for_size ( nbits , <NUM_LIT> ) . require ( ) : E_QImode ; } else cmp_mode = cmp_ops_mode ; cmp_op0 = force_reg ( cmp_ops_mode , cmp_op0 ) ; int ( * op1_predicate ) ( rtx , machine_mode ) = VECTOR_MODE_P ( cmp_ops_mode ) ? vector_operand : nonimmediate_operand ; if ( ! op1_predicate ( cmp_op1 , cmp_ops_mode ) ) cmp_op1 = force_reg ( cmp_ops_mode , cmp_op1 ) ; if ( optimize || ( maskcmp && cmp_mode != mode ) || ( op_true && reg_overlap_mentioned_p ( dest , op_true ) ) || ( op_false && reg_overlap_mentioned_p ( dest , op_false ) ) ) dest = gen_reg_rtx ( maskcmp ? cmp_mode : mode ) ; if ( maskcmp ) { bool ok = ix86_expand_mask_vec_cmp ( dest , code , cmp_op0 , cmp_op1 ) ; gcc_assert ( ok ) ; return dest ; } x = gen_rtx_fmt_ee ( code , cmp_mode , cmp_op0 , cmp_op1 ) ; if ( cmp_mode != mode ) {


<s> virtual const char * getPassName ( ) const {


<s> SDValue <ISA_LIT>TargetLowering :: lowerLog10 ( SDValue Op , SelectionDAG & DAG ) const {

return lowerLibCallBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , Op , DAG ) ;


<s> return ( uint8x16_t ) __builtin_mve_vcaddq_rot270v16qi ( ( int8x16_t ) __a , ( int8x16_t ) __b ) ;


<s> <ISA_LIT>MachineFunctionInfo ( const MachineFunction & MF ) {


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const {

TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;


<s> return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( ! CNum ) return false ; return UnsafeDiv || CNum -> isExactlyValue ( + <NUM_LIT> ) ;


<s> if ( ! Suggestion . empty ( ) ) Msg += <STR_LIT> + Suggestion + <STR_LIT> ; return TokError ( Msg ) ; } Lex ( ) ; if ( invertCondCode ) { if ( CC == <STR_LIT> || CC == <STR_LIT> ) return TokError ( <STR_LIT> ) ; CC = <STR_LIT> ( <STR_LIT> ( CC ) ) ; } Operands . push_back ( <ISA_LIT>Operand :: CreateCondCode ( CC , S , getLoc ( ) , getContext ( ) ) ) ; return false ;


<s> if ( Alignment == <NUM_LIT> ) Alignment = DL . getABITypeAlignment ( LI -> getType ( ) ) ; SmallVector < MachineOperand , <NUM_LIT> > AddrOps ; AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , * MI , OpNo , AddrOps , FuncInfo . InsertPt , Size , Alignment , true ) ; if ( ! Result ) return false ; unsigned OperandNo = <NUM_LIT> ; for ( MachineInstr :: mop_iterator I = Result -> operands_begin ( ) , E = Result -> operands_end ( ) ; I != E ; ++ I , ++ OperandNo ) { MachineOperand & MO = * I ;

if ( ! MO . isReg ( ) || MO . isDef ( ) || MO . getReg ( ) != AM . IndexReg ) continue ;


<s> return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> Values ( int64_t i ) : ImmVal ( i ) {


<s> DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ; BuildMI ( & MBB , dl , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> break ; case MCK__35_24 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_3 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_32 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_4 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_48 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_6 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_64 : ExpectedVal = <NUM_LIT> ; break ; case MCK__35_8 : ExpectedVal = <NUM_LIT> ; break ; } if ( ! Op -> isImm ( ) ) return Match_InvalidOperand ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Op -> getImm ( ) ) ; if ( ! CE ) return Match_InvalidOperand ;

if ( CE -> getValue ( ) == ExpectedVal ) return Match_Success ;


<s> if ( regnum >= <NUM_LIT> && regnum <= ( <NUM_LIT> + FP_ARG_NUM_REG ) ) set_mem_alias_set ( addr , get_varargs_alias_set ( ) ) ;

else set_mem_alias_set ( addr , get_frame_alias_set ( ) ) ;


<s> * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || VT . getStoreSize ( ) != <NUM_LIT> || Align <= <NUM_LIT> || VT == <STR_LIT> ; } return true ;


<s> if ( ( cond == LT || cond == GE ) && target_mode == cmp_mode && cmp_op2 == CONST0_RTX ( cmp_mode ) && op == CONST0_RTX ( target_mode ) && s390_vector_mode_supported_p ( target_mode ) && GET_MODE_CLASS ( target_mode ) == MODE_VECTOR_INT ) { rtx negop = ( cond == LT ) ? then : els ; int shift = GET_MODE_BITSIZE ( GET_MODE_INNER ( target_mode ) ) - <NUM_LIT> ; if ( negop == CONST1_RTX ( target_mode ) ) { rtx res = expand_simple_binop ( cmp_mode , LSHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , <NUM_LIT> , OPTAB_DIRECT ) ; if ( res != target ) emit_move_insn ( target , res ) ; return ; } else if ( all_ones_operand ( negop , target_mode ) ) {

rtx res = expand_simple_binop ( cmp_mode , ASHIFTRT , cmp_op1 , GEN_INT ( shift ) , target , <NUM_LIT> , OPTAB_DIRECT ) ;


<s> static unsigned arm_add_stmt_cost ( vec_info * vinfo , void * data , int count , enum vect_cost_for_stmt kind , struct _stmt_vec_info * stmt_info , tree vectype , int misalign , enum vect_cost_model_location where ) { unsigned * cost = ( unsigned * ) data ; unsigned retval = <NUM_LIT> ; if ( flag_vect_cost_model ) {

int stmt_cost = arm_builtin_vectorization_cost ( kind , vectype , misalign ) ;


<s> return ( ( qword ) ( vec_or ( ( vec_uint4 ) ( a ) , vec_splat ( ( vec_uint4 ) ( si_from_uint ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> legalizeOperands ( Inst ) ; continue ; } const MCInstrDesc & NewDesc = get ( NewOpcode ) ; Inst -> setDesc ( NewDesc ) ; for ( unsigned i = Inst -> getNumOperands ( ) - <NUM_LIT> ; i > <NUM_LIT> ; -- i ) { MachineOperand & Op = Inst -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) == <STR_LIT> ) Inst -> RemoveOperand ( i ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { unsigned Size = ( Opcode == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Size ) ) ; } else if ( Opcode == <STR_LIT> ) { Inst -> addOperand ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; } addDescImplicitUseDef ( NewDesc , Inst ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const MachineOperand & OffsetWidthOp = Inst -> getOperand ( <NUM_LIT> ) ; assert ( OffsetWidthOp . isImm ( ) && <STR_LIT> ) ; uint32_t Imm = OffsetWidthOp . getImm ( ) ; uint32_t Offset = Imm & <NUM_LIT> ; uint32_t BitWidth = ( Imm & <NUM_LIT> ) >> <NUM_LIT> ; Inst -> RemoveOperand ( <NUM_LIT> ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( Offset ) ) ; Inst -> addOperand ( MachineOperand :: CreateImm ( BitWidth ) ) ; } const TargetRegisterClass * NewDstRC = getOpRegClass ( * Inst , <NUM_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( RI . hasVGPRs ( NewDstRC ) ) continue ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) continue ; break ; default : break ; } unsigned DstReg = Inst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ; MRI . replaceRegWith ( DstReg , NewDstReg ) ; legalizeOperands ( Inst ) ; for ( MachineRegisterInfo :: use_iterator I = MRI . use_begin ( NewDstReg ) , E = MRI . use_end ( ) ; I != E ; ++ I ) {

MachineInstr & UseMI = * I -> getParent ( ) ;


<s> computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog , hasFP ( MF ) ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( NeedShadowCallStackProlog ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( NeedsWinCFI ) BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) { static const char CFIInst [ ] = { dwarf :: DW_CFA_val_expression , <NUM_LIT> , <NUM_LIT> , static_cast < char > ( unsigned ( dwarf :: DW_OP_breg18 ) ) , static_cast < char > ( - <NUM_LIT> ) & <NUM_LIT> , } ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createEscape ( nullptr , StringRef ( CFIInst , sizeof ( CFIInst ) ) ) ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } MBB . addLiveIn ( <STR_LIT> ) ; } for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; unsigned Size , Align ; switch ( RPI . Type ) { case RegPairInfo :: GPR : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR64 : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: FPR128 : StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: ZPR : StrOpc = <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ; case RegPairInfo :: PPR : StrOpc = <STR_LIT> ; Size = <NUM_LIT> ; Align = <NUM_LIT> ; break ;


<s> unsigned e = VT . getVectorNumElements ( ) / <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ e + i ] , i ) ) return false ; return true ;


<s> bool <ISA_LIT>TargetLowering :: shouldAvoidTransformToShift ( EVT VT , unsigned Amount ) const { return ! ( Subtarget -> has<ISA_LIT>X ( ) || Amount == <NUM_LIT> || Amount == <NUM_LIT> || Amount <= <NUM_LIT> ) ;


if ( ! argument_exists_p ( argno ) ) return true ;


<s> const ConstantInt * CI = cast < ConstantInt > ( C ) ; int64_t Imm ; if ( CI -> isNegative ( ) ) Imm = CI -> getSExtValue ( ) ;


<s> BuildMI ( MBB , MIB . getInstr ( ) , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Undef ) . addReg ( Reg , RegState :: Undef ) ; MIB -> setDesc ( TII . get ( MinusOne ? <STR_LIT> : <STR_LIT> ) ) ;


<s> bool Thumb2SizeReduce :: ReduceSpecial ( MachineBasicBlock & MBB , MachineInstr * MI , const ReduceEntry & Entry , bool LiveCPSR ) { if ( Entry . LowRegs1 && ! VerifyLowRegs ( MI ) ) return false ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; if ( TID . mayLoad ( ) || TID . mayStore ( ) ) return ReduceLoadStore ( MBB , MI , Entry ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; if ( getInstrPredicate ( MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : { if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR ) ) return true ; } case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR ) ; } }


<s> return NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ;


<s> bool IsArrayed = MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; bool IsMultisampled = MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; bool NoSampler = MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ; assert ( MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; switch ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) { case Dim :: DIM_1D : Reqs . addRequirements ( NoSampler ? Capability :: Image1D : Capability :: Sampled1D ) ; break ; case Dim :: DIM_2D : if ( IsMultisampled && NoSampler ) Reqs . addRequirements ( Capability :: ImageMSArray ) ; break ; case Dim :: DIM_Cube : Reqs . addRequirements ( Capability :: Shader ) ; if ( IsArrayed ) Reqs . addRequirements ( NoSampler ? Capability :: ImageCubeArray : Capability :: SampledCubeArray ) ; break ; case Dim :: DIM_Rect : Reqs . addRequirements ( NoSampler ? Capability :: ImageRect : Capability :: SampledRect ) ; break ; case Dim :: DIM_Buffer :

Reqs . addRequirements ( NoSampler ? Capability :: ImageBuffer : Capability :: SampledBuffer ) ;


<s> AAUniformWorkGroupSize ( const IRPosition & IRP , Attributor & A ) : Base ( IRP ) {


<s> void startVisit ( const MachineInstr * MI ) { Types . try_emplace ( MI , InstType :: NotDetermined ) ;


if ( TFI -> hasFP ( * MF ) ) return ( F -> getCallingConv ( ) == CallingConv :: <ISA_LIT>_INTR ? CalleeSavedRegsIntrFP : CalleeSavedRegsFP ) ;


<s> return UNKNOWN ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return BUFFER_LOAD ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return BUFFER_STORE ; } } if ( TII . isMIMG ( Opc ) ) { if ( <STR_LIT> ( Opc , <STR_LIT> :: vaddr ) == - <NUM_LIT> && <STR_LIT> ( Opc , <STR_LIT> :: vaddr0 ) == - <NUM_LIT> ) return UNKNOWN ; if ( TII . get ( Opc ) . mayStore ( ) || ! TII . get ( Opc ) . mayLoad ( ) || TII . isGather4 ( Opc ) ) return UNKNOWN ; return MIMG ; } if ( TII . isMTBUF ( Opc ) ) { switch ( <STR_LIT> ( Opc ) ) { default : return UNKNOWN ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return TBUFFER_LOAD ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return TBUFFER_STORE ; } } return UNKNOWN ;


<s> ErrorLoc = ( ( <ISA_LIT>Operand * ) Operands [ ErrorInfo ] ) -> getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> ) ; case Match_ConversionFail : return true ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock :


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredSegAlloca ( MachineInstr & MI , MachineBasicBlock * BB ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( ! x ) return ; code = GET_CODE ( x ) ; switch ( code ) { case REG : { int regno = REGNO ( x ) ; int nregs = ( regno < FIRST_PSEUDO_REGISTER ? HARD_REGNO_NREGS ( regno , GET_MODE ( x ) ) : <NUM_LIT> ) ; do { reg_set_block [ regno + nregs - <NUM_LIT> ] = <NUM_LIT> ; } while ( -- nregs ) ; break ; } case SET : {


<s> bool isInlinableIntLiteral ( int64_t Literal ) { return Literal >= - <NUM_LIT> && Literal <= <NUM_LIT> ;


<s> const MachineBasicBlock & B = * FP . JoinB ; for ( auto & MI : B ) { if ( ! MI . isPHI ( ) ) break ; if ( usesUndefVReg ( & MI ) ) return false ; unsigned DefR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( DefR ) ; if ( RC == & <STR_LIT> ) return false ; } }


<s> AU . setPreservesCFG ( ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> SortRegionInfo ( const MachineLoopInfo & MLI , const <ISA_LIT>ExceptionInfo & WEI ) : MLI ( MLI ) , WEI ( WEI ) {


<s> const MCObjectFileInfo :: Environment Format = getContext ( ) . getObjectFileInfo ( ) -> getObjectFileType ( ) ; bool IsMachO = Format == MCObjectFileInfo :: IsMachO ; StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == <STR_LIT> ) parseDirectiveArch ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveInst ( Loc ) ; else if ( IsMachO ) {

if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ;


<s> return ( int32x2_t ) __builtin_neon_vpmaxsv2si ( __a , __b ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! AM . hasIndexReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Index = AM . IndexReg ; if ( getSymbolicDisplacement ( AM , SDLoc ( N ) , Disp ) ) { assert ( ! AM . Disp && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ;


<s> return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_1 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_32 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_33 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_0_Report_UImm6 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm5_Lsl2 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm6_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_SImm6 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm7_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ; case Match_UImm8_0 : return Error ( RefineErrorLoc ( IDLoc , Operands , ErrorInfo ) , <STR_LIT> ) ;


<s> Instruction * MVEGatherScatterLowering :: tryCreateMaskedGatherBase ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder , int64_t Increment ) { using namespace PatternMatch ; auto * Ty = cast < FixedVectorType > ( I -> getType ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Ty -> getNumElements ( ) != <NUM_LIT> || Ty -> getScalarSizeInBits ( ) != <NUM_LIT> ) return nullptr ; Value * Mask = I -> getArgOperand ( <NUM_LIT> ) ;

if ( match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { Ty , Ptr -> getType ( ) } , { Ptr , Builder . getInt32 ( Increment ) } ) ;


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; updateValueMap ( I , ResultReg ) ; return true ; } }


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _tzcnt_u64 ( unsigned long long __X ) { return __builtin_ctzll ( __X ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS ) , DataLayout ( <STR_LIT> <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) {


<s> void <ISA_LIT>PreAllocateWWMRegs :: rewriteRegs ( MachineFunction & MF ) { for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { for ( MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) ) continue ; const Register VirtReg = MO . getReg ( ) ; if ( Register :: isPhysicalRegister ( VirtReg ) ) continue ; if ( ! VRM -> hasPhys ( VirtReg ) ) continue ; Register PhysReg = VRM -> getPhys ( VirtReg ) ; const unsigned SubReg = MO . getSubReg ( ) ; if ( SubReg != <NUM_LIT> ) { PhysReg = TRI -> getSubReg ( PhysReg , SubReg ) ; MO . setSubReg ( <NUM_LIT> ) ; }


<s> unsigned HOST_WIDE_INT high_bits ; if ( is_neg ) high_bits = ( ~ low_bits ) & <NUM_LIT> ; else high_bits = low_bits ; emit_insn ( gen_safe_HIGH64 ( temp , high_bits ) ) ; if ( ! is_neg ) { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_safe_OR64 ( temp , ( high_bits & <NUM_LIT> ) ) ) ) ; } else { if ( ( low_bits & <NUM_LIT> ) == <NUM_LIT> ) { emit_insn ( gen_rtx_SET ( VOIDmode , op0 , gen_rtx_NOT ( DImode , temp ) ) ) ; }


<s> gcc_assert ( insn_length == <NUM_LIT> || insn_length == <NUM_LIT> ) ; long_jump_p = ( insn_length == <NUM_LIT> ) ? true : false ; code = GET_CODE ( operands [ <NUM_LIT> ] ) ; switch ( code ) { case GT : case GE :


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> MachineBasicBlock * BrBB = FuncInfo . MBB ; MachineBasicBlock * TBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; MachineBasicBlock * FBB = FuncInfo . MBBMap [ BI -> getSuccessor ( <NUM_LIT> ) ] ; if ( const CmpInst * CI = dyn_cast < CmpInst > ( BI -> getCondition ( ) ) ) { if ( isValueAvailable ( CI ) ) { Optional < <STR_LIT> > Opt<ISA_LIT>Pred = getComparePred ( CI -> getPredicate ( ) ) ; if ( ! Opt<ISA_LIT>Pred ) return false ; <STR_LIT> <ISA_LIT>Pred = Opt<ISA_LIT>Pred . getValue ( ) ; if ( FuncInfo . MBB -> isLayoutSuccessor ( TBB ) ) { std :: swap ( TBB , FBB ) ; <ISA_LIT>Pred = <STR_LIT> ( <ISA_LIT>Pred ) ; } unsigned CondReg = createResultReg ( & <STR_LIT> ) ; if ( ! <ISA_LIT>EmitCmp ( CI -> getOperand ( <NUM_LIT> ) , CI -> getOperand ( <NUM_LIT> ) , CI -> isUnsigned ( ) , CondReg ) ) return false ; BuildMI ( * BrBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>Pred ) . addReg ( CondReg ) . addMBB ( TBB ) ; fastEmitBranch ( FBB , DbgLoc ) ; FuncInfo . MBB -> addSuccessor ( TBB ) ; return true ; }

} else if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( BI -> getCondition ( ) ) ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS ) , DataLayout ( <STR_LIT> ) , InstrInfo ( * this ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget ) {


<s> InstrItins = getInstrItineraryForCPU ( CPUName ) ; ParseSubtargetFeatures ( CPUName , CPUName , FS ) ; if ( Is<ISA_LIT>64 && has64BitSupport ( ) ) Use64BitRegs = true ; if ( ( TargetTriple . isOSFreeBSD ( ) && TargetTriple . getOSMajorVersion ( ) >= <NUM_LIT> ) || TargetTriple . isOSNetBSD ( ) || TargetTriple . isOSOpenBSD ( ) || TargetTriple . isMusl ( ) ) SecurePlt = true ; if ( HasSPE && Is<ISA_LIT>64 ) report_fatal_error ( <STR_LIT> , false ) ; if ( HasSPE && ( HasAltivec || HasVSX || HasFPU ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( ! HasSPE ) HasFPU = true ; StackAlignment = getPlatformStackAlignment ( ) ;

IsLittleEndian = ( TargetTriple . getArch ( ) == Triple :: ppc64le ) ;


<s> bool checkRegisterEqual ( const TargetRegisterInfo * TRI , unsigned Reg1 , unsigned Reg2 ) {

if ( ! TRI -> isPhysicalRegister ( Reg1 ) || ! TRI -> isPhysicalRegister ( Reg2 ) ) {


<s> return <ISA_LIT>3DNowLevel >= ThreeDNow ;


<s> BTFStringTable ( ) : Size ( <NUM_LIT> ) {


<s> MFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ;

return AsmPrinter :: runOnMachineFunction ( MF ) ;


<s> const <ISA_LIT>FrameLowering * TFI = static_cast < const <ISA_LIT>FrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; assert ( ! AFI -> isThumb1OnlyFunction ( ) && <STR_LIT> ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } int FrameIndex = MI . getOperand ( i ) . getIndex ( ) ; unsigned FrameReg ; int Offset = TFI -> ResolveFrameIndexReference ( MF , FrameIndex , FrameReg , SPAdj ) ; if ( RS && FrameReg == <STR_LIT> && FrameIndex == RS -> getScavengingFrameIndex ( ) ) { assert ( TFI -> hasReservedCallFrame ( MF ) && <STR_LIT> <STR_LIT> ) ; assert ( ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) && <STR_LIT> <STR_LIT> ) ; } if ( MI . isDebugValue ( ) ) { MI . getOperand ( i ) . ChangeToRegister ( FrameReg , false ) ; MI . getOperand ( i + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; }


<s> ( void ) BW ; assert ( Width >= Bits && BW >= Bits ) ; APInt Mask = APInt :: getLowBitsSet ( Width , Bits ) ; Result = A1 . zextOrTrunc ( Width ) & Mask ; return true ;


<s> FunctionPass * llvm :: create<ISA_LIT>SPBundlingPass ( const <ISA_LIT>TargetMachine & tm ) {


<s> if ( RI . isSGPRClass ( RC ) ) { switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S32_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S64_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S128_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S256_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_S512_SAVE ; break ; } } else if ( shouldTryToSpillVGPRs ( MF ) && RI . hasVGPRs ( RC ) ) { switch ( RC -> getSize ( ) * <NUM_LIT> ) { case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_V32_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_V64_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_V96_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_V128_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_V256_SAVE ; break ; case <NUM_LIT> : Opcode = AMDGPU :: <ISA_LIT>_SPILL_V512_SAVE ; break ; } } if ( Opcode != - <NUM_LIT> ) {

FrameInfo -> setObjectAlignment ( FrameIndex , <NUM_LIT> ) ;


<s> case <STR_LIT> : { const RegisterSDNode * R = cast < RegisterSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; const MachineRegisterInfo & MRI = FLI -> MF -> getRegInfo ( ) ; const <ISA_LIT>RegisterInfo * TRI = Subtarget -> getRegisterInfo ( ) ; Register Reg = R -> getReg ( ) ; if ( Reg . isPhysical ( ) || MRI . isLiveIn ( Reg ) ) return ! TRI -> isSGPRReg ( MRI , Reg ) ; if ( const Value * V = FLI -> getValueFromVirtualReg ( R -> getReg ( ) ) ) return KDA -> isDivergent ( V ) ; assert ( Reg == FLI -> DemoteRegister || isCopyFromRegOfInlineAsm ( N ) ) ; return ! TRI -> isSGPRReg ( MRI , Reg ) ; } case <STR_LIT> : { const LoadSDNode * L = cast < LoadSDNode > ( N ) ; unsigned AS = L -> getAddressSpace ( ) ; return AS == <ISA_LIT>AS :: PRIVATE_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ;


<s> if ( StubSym == <NUM_LIT> ) StubSym = GetGlobalValueSymbol ( GV ) ; } } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; O << * GetExternalSymbolSymbol ( ACPV -> getSymbol ( ) ) ; } if ( ACPV -> hasModifier ( ) ) O << <STR_LIT> << ACPV -> getModifier ( ) << <STR_LIT> ; if ( ACPV -> getPCAdjustment ( ) != <NUM_LIT> ) { O << <STR_LIT> << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << ACPV -> getLabelId ( ) << <STR_LIT> << ( unsigned ) ACPV -> getPCAdjustment ( ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) O << <STR_LIT> ;


<s> SUnit * <ISA_LIT>PostRASchedStrategy :: pickNode ( bool & IsTopNode ) { IsTopNode = true ; if ( Available . empty ( ) ) return nullptr ; if ( Available . size ( ) == <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> ; HazardRec . dumpSU ( * Available . begin ( ) , dbgs ( ) ) ; dbgs ( ) << <STR_LIT> ; ) ; return * Available . begin ( ) ; } DEBUG ( dbgs ( ) << <STR_LIT> ; Available . dump ( HazardRec ) ; ) ; Candidate Best ; for ( auto * SU : Available ) { Candidate c ( SU , HazardRec ) ; if ( Best . SU == nullptr || c < Best ) { Best = c ; DEBUG ( dbgs ( ) << <STR_LIT> ; HazardRec . dumpSU ( Best . SU , dbgs ( ) ) ; if ( Best . GroupingCost != <NUM_LIT> ) dbgs ( ) << <STR_LIT> << Best . GroupingCost ; if ( Best . ResourcesCost != <NUM_LIT> ) dbgs ( ) << <STR_LIT> << Best . ResourcesCost ; dbgs ( ) << <STR_LIT> << Best . SU -> getHeight ( ) ; dbgs ( ) << <STR_LIT> ; ) ; } if ( ! SU -> isScheduleHigh && Best . noCost ( ) ) break ; } assert ( Best . SU != nullptr ) ; return Best . SU ;


<s> assert ( VecWidth -> isVectorTy ( ) && DL . getTypeSizeInBits ( VecWidth ) >= DL . getTypeSizeInBits ( SubVecTy ) * NumSubVectors && <STR_LIT> ) ; if ( auto * SVI = dyn_cast < ShuffleVectorInst > ( VecInst ) ) { Value * Op0 = SVI -> getOperand ( <NUM_LIT> ) ; Value * Op1 = SVI -> getOperand ( <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; ++ i ) DecomposedVectors . push_back ( cast < ShuffleVectorInst > ( Builder . CreateShuffleVector ( Op0 , Op1 , createSequentialMask ( Builder , Indices [ i ] , SubVecTy -> getVectorNumElements ( ) , <NUM_LIT> ) ) ) ) ; return ; } LoadInst * LI = cast < LoadInst > ( VecInst ) ; Type * VecBaseTy , * VecBasePtrTy ; Value * VecBasePtr ; unsigned int NumLoads = NumSubVectors ;

unsigned VecLength = DL . getTypeSizeInBits ( VecWidth ) ;


<s> if ( Subtarget . has<ISA_LIT>64 ( ) ) { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16Mode ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . useSmallSection ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } return Reserved ;


<s> SmallString < <NUM_LIT> > Name ; raw_svector_ostream ( Name ) << DL . getPrivateGlobalPrefix ( ) << <STR_LIT> << Printer . getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } return Ctx . getOrCreateSymbol ( Name ) ;


<s> RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: registerMCAdjustCodeGenOpts ( The<ISA_LIT>Target , adjustCodeGenOpts ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterAsmTargetStreamer ( The<ISA_LIT>Target , createTargetAsmStreamer ) ;


<s> clobber = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( BImode , <NUM_LIT> ) ) ; insn = emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , clobber ) ) ) ; return insn ;


<s> if ( PredSU -> NumSuccsLeft == <NUM_LIT> ) { dbgs ( ) << <STR_LIT> ; PredSU -> dump ( this ) ; dbgs ( ) << <STR_LIT> ;


<s> errs ( ) << <STR_LIT> << YamlString << '\n' ;


<s> if ( IntegerType * ITy = dyn_cast < IntegerType > ( Ty ) ) return ITy -> getBitWidth ( ) > ( Is32Bit ? <NUM_LIT> : <NUM_LIT> ) ; return false ;


<s> PrintRegister ( HCE :: Register R , const <ISA_LIT>RegisterInfo & I ) : Rs ( R ) , HRI ( I ) {


<s> const <ISA_LIT>RegisterInfo & <ISA_LIT>InstrInfo :: getRegisterInfo ( ) const {


<s> int64_t Dummy ; if ( isAddConstantOp ( * MI , Dummy ) ) { if ( isValidIncrementOffset ( Dummy + NewOffset ) ) continue ; return false ; } if ( isLoadStoreThatCanHandleDisplacement ( AII , * MI , - NewOffset ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << - NewOffset << <STR_LIT> << * MI ) ; return false ;


<s> MCSymbol * <ISA_LIT>FunctionInfo :: getGlobalEPSymbol ( MachineFunction & MF ) const {

const DataLayout & DL = MF . getDataLayout ( ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Disassembler ( ) { TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target32 ( ) , create<ISA_LIT>Disassembler ) ; TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target64 ( ) , create<ISA_LIT>Disassembler ) ;


<s> <STR_LIT> ET = getShiftExtendType ( ) ; bool IsSigned = ET == <STR_LIT> || ET == <STR_LIT> ; Inst . addOperand ( MCOperand :: createImm ( IsSigned ) ) ;

Inst . addOperand ( MCOperand :: createImm ( hasShiftExtendAmount ( ) ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , FS ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffective<ISA_LIT>CodeModel ( CM , getEffectiveRelocModel ( RM ) , JIT ) , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) {


<s> switch ( Opcode ) { case Instruction :: ExtractElement : case Instruction :: InsertElement :

return Index == ~ <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ;


<s> } else if ( <STR_LIT> . contains ( Reg ) ) { unsigned XReg = TRI -> getSubReg ( Reg , <STR_LIT> ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , XReg ) . addReg ( XReg , RegState :: Undef ) . addReg ( XReg , RegState :: Undef ) . addReg ( Reg , RegState :: ImplicitDefine ) ;


<s> assert ( I != AttributeListMap . end ( ) && <STR_LIT> ) ; return I -> second ;


<s> if ( MFI -> hasCalls ( ) && isPIC ) { <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MFI -> setObjectOffset ( <ISA_LIT>FI -> getGPFI ( ) , <ISA_LIT>FI -> getGPStackOffset ( ) ) ;


<s> MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ; const MachinePointerInfo & PtrInfo = cast < MemSDNode > ( Parent ) -> getPointerInfo ( ) ; SOffset = isStackPtrRelative ( PtrInfo ) ? CurDAG -> getRegister ( Info -> getStackPtrOffsetReg ( ) , <STR_LIT> ) : CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CAddr -> getZExtValue ( ) , DL , <STR_LIT> ) ;


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ;


<s> const char * Name = <STR_LIT> ; PassInfo * PI = new PassInfo ( Name , <STR_LIT> , & <ISA_LIT>ExpandPredSpillCode :: ID , nullptr , false , false ) ;

Registry . registerPass ( * PI , true ) ;


<s> unsigned <ISA_LIT>EarlyIfConversion :: computePhiCost ( MachineBasicBlock * B ) const { assert ( B -> pred_size ( ) <= <NUM_LIT> ) ; if ( B -> pred_size ( ) < <NUM_LIT> ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; MachineBasicBlock :: const_iterator I , E = B -> getFirstNonPHI ( ) ; for ( I = B -> begin ( ) ; I != E ; ++ I ) {

const MachineOperand & RO1 = I -> getOperand ( <NUM_LIT> ) ;


<s> const SDValue Ops [ ] = { V0 , SubReg0 , V1 , SubReg1 } ;

return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops , <NUM_LIT> ) ;


<s> if ( ! isTypeLegal ( I -> getType ( ) , RetVT ) ) return false ; unsigned Opc ; if ( RetVT == <STR_LIT> && SrcVT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( RetVT == <STR_LIT> && SrcVT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( RetVT == <STR_LIT> && SrcVT == <STR_LIT> ) Opc = <STR_LIT> ; else if ( RetVT == <STR_LIT> && SrcVT == <STR_LIT> ) Opc = <STR_LIT> ; else return false ; const TargetRegisterClass * RC = nullptr ; switch ( RetVT . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ;


<s> KdStream << <STR_LIT> << KdName << '\n' ; DataExtractor :: Cursor C ( <NUM_LIT> ) ; while ( C && C . tell ( ) < Bytes . size ( ) ) { MCDisassembler :: DecodeStatus Status = decodeKernelDescriptorDirective ( C , Bytes , KdStream ) ; cantFail ( C . takeError ( ) ) ; if ( Status == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; }


<s> MCInst * Result = Extender ; const_cast < <ISA_LIT>AsmBackend * > ( this ) -> Extender = nullptr ;


<s> unsigned getCheriHWRegsReg ( ) const { assert ( isRegIdx ( ) && ( RegIdx . Kind & RegKind_CheriHWRegs ) && <STR_LIT> ) ; unsigned ClassID = <STR_LIT> ;

return RegIdx . RegInfo -> getRegClass ( ClassID ) . getRegister ( RegIdx . Index ) ;


<s> AM . getFullAddress ( AddrOps ) ; MachineInstr * Result = XII . foldMemoryOperandImpl ( * FuncInfo . MF , MI , OpNo , AddrOps , Size , Alignment ) ; if ( Result == <NUM_LIT> ) return false ; FuncInfo . MBB -> insert ( FuncInfo . InsertPt , Result ) ; MI -> eraseFromParent ( ) ; return true ;


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) {


<s> return new <ISA_LIT>FrameAnalyzer ( ) ;


<s> __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> if ( N -> getOpcode ( ) == <STR_LIT> ) { assert ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ; ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N ) ; APFloat Value = C -> getValueAPF ( ) ; float FloatValue = Value . convertToFloat ( ) ; if ( FloatValue == <NUM_LIT> ) { ImmReg = AMDGPU :: ZERO ; } else if ( FloatValue == <NUM_LIT> ) { ImmReg = AMDGPU :: HALF ; } else if ( FloatValue == <NUM_LIT> ) { ImmReg = AMDGPU :: ONE ; } else { ImmValue = Value . bitcastToAPInt ( ) . getZExtValue ( ) ; } } else { assert ( N -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( N ) ; if ( C -> getZExtValue ( ) == <NUM_LIT> ) { ImmReg = AMDGPU :: ZERO ; } else if ( C -> getZExtValue ( ) == <NUM_LIT> ) { ImmReg = AMDGPU :: ONE_INT ; } else { ImmValue = C -> getZExtValue ( ) ; } } for ( SDNode :: use_iterator Use = N -> use_begin ( ) , Next = llvm :: next ( Use ) ; Use != SDNode :: use_end ( ) ; Use = Next ) { Next = llvm :: next ( Use ) ; std :: vector < SDValue > Ops ; for ( unsigned i = <NUM_LIT> ; i < Use -> getNumOperands ( ) ; ++ i ) { Ops . push_back ( Use -> getOperand ( i ) ) ; } if ( ! Use -> isMachineOpcode ( ) ) { if ( ImmReg == AMDGPU :: ALU_LITERAL_X ) { continue ; } } else { if ( ! TII -> isALUInstr ( Use -> getMachineOpcode ( ) ) ) { continue ; } int ImmIdx = TII -> getOperandIdx ( Use -> getMachineOpcode ( ) , <STR_LIT> ) ; assert ( ImmIdx != - <NUM_LIT> ) ;


<s> unsigned Kind = Fixup . getKind ( ) ; switch ( Kind ) { case FK_<ISA_LIT>_HO_7 : Value >>= <NUM_LIT> ; break ; case FK_<ISA_LIT>_WO_7 : case FK_<ISA_LIT>_abs_CFLi : case FK_<ISA_LIT>_PCrel :


<s> for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { SSA . Initialize ( I . getType ( ) , I . getName ( ) ) ; SSA . AddAvailableValue ( & BB , & I ) ; for ( auto UI = I . use_begin ( ) , UE = I . use_end ( ) ; UI != UE ; ) { Use & U = * UI ; ++ UI ; auto * User = cast < Instruction > ( U . getUser ( ) ) ; if ( auto * UserPN = dyn_cast < PHINode > ( User ) ) if ( UserPN -> getIncomingBlock ( U ) == & BB ) continue ; if ( DT . dominates ( & I , User ) ) continue ;


<s> dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ . CVI . getUnits ( ) ) << '|' ;


<s> rtx_insn * insn = get_last_insn ( ) ; rtx src = XEXP ( SET_SRC ( PATTERN ( insn ) ) , <NUM_LIT> ) ; ASSERT_TRUE ( rtx_equal_p ( src , CONSTM1_RTX ( mode ) ) ) ;


<s> void LLVMInitialize<ISA_LIT>Disassembler ( ) {

TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ;


<s> if ( VT != <STR_LIT> ) return SDValue ( ) ; SDLoc SL ( N ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOpcode ( ) == <STR_LIT> ) { auto C = dyn_cast < ConstantSDNode > ( LHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C || ! C -> isNullValue ( ) ) return SDValue ( ) ;

SDValue Args [ ] = { LHS . getOperand ( <NUM_LIT> ) , RHS , LHS . getOperand ( <NUM_LIT> ) } ;


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getString ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveHSACodeObjectVersion ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveHSACodeObjectISA ( ) ; if ( IDVal == <STR_LIT> :: MetadataAssemblerDirectiveBegin ) return ParseDirectiveCodeObjectMetadata ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveAMDKernelCodeT ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirective<ISA_LIT>HsaKernel ( ) ; return true ;


<s> HasFRES = false ; HasFRSQRTE = false ; HasFRSQRTES = false ; HasRecipPrec = false ; HasSTFIWX = false ; HasLFIWAX = false ; HasFPRND = false ; HasFPCVT = false ; HasISEL = false ; HasPOPCNTD = false ; HasCMPB = false ; HasLDBRX = false ; IsBookE = false ; HasOnlyMSYNC = false ; Is<ISA_LIT>4xx = false ; Is<ISA_LIT>6xx = false ; IsE500 = false ; DeprecatedMFTB = false ; DeprecatedDST = false ; HasLazyResolverStubs = false ; HasICBT = false ; HasInvariantFunctionDescriptors = false ;


<s> if ( ! isEligibleForITBlock ( & MI ) ) return false ; <ISA_LIT>FunctionInfo * AFI = MI . getParent ( ) -> getParent ( ) -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( AFI -> isThumb2Function ( ) ) { if ( getSubtarget ( ) . restrictIT ( ) ) return isV8EligibleForIT ( & MI ) ; } else { if ( ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) == <STR_LIT> ) return false ; } return true ;


<s> TrueOp = <NUM_LIT> ; FalseOp = <NUM_LIT> ; Cond . push_back ( MI . getOperand ( <NUM_LIT> ) ) ; Cond . push_back ( MI . getOperand ( <NUM_LIT> ) ) ; Optimizable = true ;


<s> BuildMI ( & bb , dl , get ( <STR_LIT> ) ) . addOperand ( cond [ <NUM_LIT> ] ) . addMBB ( tbb ) ; n ++ ; if ( fbb ) { BuildMI ( & bb , dl , get ( <STR_LIT> ) ) . addMBB ( fbb ) ; n ++ ; } } return n ;


<s> Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ; SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSP , ArgAdjust ) ; if ( RequiredAlign > StackAlign ) { Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( ~ ( RequiredAlign - <NUM_LIT> ) , DL , <STR_LIT> ) ) ;


<s> static bool iq2000_print_operand_punct_valid_p ( unsigned char code ) {

return iq2000_print_operand_punct [ code ] ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectPred ( SDValue N , SDValue & Reg , SDValue & Inv ) { SDLoc dl ( N ) ;

if ( ConstantSDNode * Imm = dyn_cast < ConstantSDNode > ( N . getNode ( ) ) ) {


<s> static MCCodeGenInfo * create<ISA_LIT>ompactMCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM , CM ) ;


<s> SDValue Or = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ShiftLeftHi , ShiftRightLo ) ; SDValue ShiftLeftLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Shamt ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftLeftLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftLeftLo , Or ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , <NUM_LIT> , DL ) ;


<s> rtx func ; int mode ; rtx out_operands [ <NUM_LIT> ] ; func = alpha_lookup_xfloating_lib_func ( code ) ; mode = alpha_compute_xfloating_mode_arg ( code , alpha_fprm ) ;

out_operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ;


<s> if ( ST . device ( ) -> getGeneration ( ) <= <STR_LIT> ) { enablePass ( & MachineSchedulerID ) ;

MachineSchedRegistry :: setDefault ( createR600MachineScheduler ) ;


<s> bool WordInt = Src . getSimpleValueType ( ) . SimpleTy == <STR_LIT> ; bool Signed = Op . getOpcode ( ) == <STR_LIT> ; unsigned MovOpc = ( WordInt && ! Signed ) ? <STR_LIT> : <STR_LIT> ; SDValue Mov = DAG . getNode ( MovOpc , dl , <STR_LIT> , Src ) ; return convertIntToFP ( Op , Mov , DAG , Subtarget ) ;


<s> unsigned SPReg = getSPReg ( STI ) ; auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; uint64_t FPOffset = StackSize - RVFI -> getVarArgsSaveSize ( ) ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; adjustReg ( MBB , LastFrameDestroy , DL , SPReg , FPReg , - FPOffset , MachineInstr :: FrameDestroy ) ; } if ( hasFP ( MF ) ) { for ( auto & I = LastFrameDestroy ; I != MBBI ; ++ I ) { if ( I -> mayLoad ( ) && I -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { unsigned DestReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( DestReg == FPReg ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfa ( nullptr , RI -> getDwarfRegNum ( SPReg , true ) , - FPOffset ) ) ; BuildMI ( MBB , std :: next ( I ) , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; break ; } } }


<s> __o = __builtin_aarch64_ld2rv4sf ( ( const __builtin_aarch64_simd_sf * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregoiv4sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x4_t ) __builtin_aarch64_get_qregoiv4sf ( __o , <NUM_LIT> ) ;


<s> assert ( ( ~ STI . getFeatureBits ( ) & llvm :: <STR_LIT> ) && <STR_LIT> ) ; assert ( MI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; for ( unsigned OI = <NUM_LIT> , OE = MI . getNumOperands ( ) ; OI < OE ; ++ OI ) { assert ( MI . getOperand ( OI ) . isReg ( ) && <STR_LIT> ) ; if ( MI . getOperand ( OI ) . getReg ( ) == <STR_LIT> || MI . getOperand ( OI ) . getReg ( ) == <STR_LIT> ) { Info = <STR_LIT> ;


<s> const TargetRegisterClass * RC = RI . getRegClass ( RCID ) ; unsigned Size = TRI -> getRegSizeInBits ( * RC ) ; unsigned Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( MO . isReg ( ) ) Opcode = <STR_LIT> ; else if ( RI . isSGPRClass ( RC ) ) Opcode = ( Size == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ;

const TargetRegisterClass * VRC = RI . getEquivalentVGPRClass ( RC ) ;


<s> return optimize > <NUM_LIT> && io_address_operand ( x , QImode ) ? avr_asm_len ( <STR_LIT> , op , plen , - <NUM_LIT> ) : avr_asm_len ( <STR_LIT> , op , plen , - n_words ) ; } if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { int disp = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( AVR_TINY ) return avr_out_movqi_r_mr_reg_disp_tiny ( insn , op , plen ) ; if ( disp - GET_MODE_SIZE ( GET_MODE ( src ) ) >= <NUM_LIT> ) { if ( REGNO ( XEXP ( x , <NUM_LIT> ) ) != REG_Y ) fatal_insn ( <STR_LIT> , insn ) ; if ( disp <= <NUM_LIT> + MAX_LD_OFFSET ( GET_MODE ( src ) ) ) return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , op , plen , - <NUM_LIT> ) ; } else if ( REGNO ( XEXP ( x , <NUM_LIT> ) ) == REG_X ) {


<s> if ( const auto * F = dyn_cast < const Function > ( V ) ) {

if ( F -> isIntrinsic ( ) ) return false ;


__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> <ISA_LIT>Z80RegisterInfo :: <ISA_LIT>Z80RegisterInfo ( ) : <ISA_LIT>Z80GenRegisterInfo ( <NUM_LIT> ) {


<s> bool <ISA_LIT>AnnotateKernelFeatures :: hasAddrSpaceCast ( const Function & F ) { for ( const BasicBlock & BB : F ) { for ( const Instruction & I : BB ) { if ( const AddrSpaceCastInst * ASC = dyn_cast < AddrSpaceCastInst > ( & I ) ) {

if ( castRequiresQueuePtr ( ASC ) ) return true ;


<s> } if ( <STR_LIT> ( Op . getNode ( ) ) ) { SDValue Cst = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( VT . getVectorNumElements ( ) , Cst ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops ) ; } bool AllContants = true ; uint64_t Immediate = <NUM_LIT> ; int NonConstIdx = - <NUM_LIT> ; bool IsSplat = true ; unsigned NumNonConsts = <NUM_LIT> ; unsigned NumConsts = <NUM_LIT> ; for ( unsigned idx = <NUM_LIT> , e = Op . getNumOperands ( ) ; idx < e ; ++ idx ) { SDValue In = Op . getOperand ( idx ) ; if ( In . getOpcode ( ) == <STR_LIT> ) continue ; if ( ! isa < ConstantSDNode > ( In ) ) { AllContants = false ; NonConstIdx = idx ; NumNonConsts ++ ; } else { NumConsts ++ ; if ( cast < ConstantSDNode > ( In ) -> getZExtValue ( ) ) Immediate |= ( <NUM_LIT> << idx ) ; } if ( In != Op . getOperand ( <NUM_LIT> ) ) IsSplat = false ; } if ( AllContants ) { SDValue FullMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( Immediate , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FullMask , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } if ( NumNonConsts == <NUM_LIT> && NonConstIdx != <NUM_LIT> ) { SDValue DstVec ; if ( NumConsts ) { SDValue VecAsImm = DAG . getConstant ( Immediate , <STR_LIT> ( VT . getSizeInBits ( ) ) ) ; DstVec = DAG . getNode ( <STR_LIT> , dl , VT , VecAsImm ) ; } else DstVec = DAG . getUNDEF ( VT ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DstVec , Op . getOperand ( NonConstIdx ) , DAG . getIntPtrConstant ( NonConstIdx ) ) ; } if ( ! IsSplat && ( NonConstIdx != <NUM_LIT> ) ) llvm_unreachable ( <STR_LIT> ) ; MVT SelectVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Select ; if ( IsSplat ) Select = DAG . getNode ( <STR_LIT> , dl , SelectVT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( - <NUM_LIT> , SelectVT ) , DAG . getConstant ( <NUM_LIT> , SelectVT ) ) ; else Select = DAG . getNode ( <STR_LIT> , dl , SelectVT , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ( Immediate | <NUM_LIT> ) , SelectVT ) , DAG . getConstant ( Immediate , SelectVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Select ) ;


<s> APInt DefBits ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; APInt UndefBits ( VT . getSizeInBits ( ) , <NUM_LIT> ) ; if ( resolveBuildVector ( BVN , DefBits , UndefBits ) ) { SDValue NewOp ; DefBits = ~ DefBits ; if ( ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , DefBits , & LHS ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , DefBits , & LHS ) ) ) return NewOp ; UndefBits = ~ UndefBits ;

if ( ( NewOp = tryAdvSIMDModImm32 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , UndefBits , & LHS ) ) || ( NewOp = tryAdvSIMDModImm16 ( <STR_LIT> , SDValue ( N , <NUM_LIT> ) , DAG , UndefBits , & LHS ) ) ) return NewOp ;


<s> return LowerSymbolOperand ( MO , AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ) ; case MachineOperand :: MO_ConstantPoolIndex : return LowerSymbolOperand ( MO , AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) ) ; case MachineOperand :: MO_BlockAddress :

return LowerSymbolOperand ( MO , AsmPrinter . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ;


<s> for ( auto I = From ; I != To ; ++ I ) if ( I -> modifiesRegister ( Reg , TRI ) ) return true ;


<s> if ( I != MBB . end ( ) && ! I -> isDebugValue ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> if ( ! isMemory ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ;

if ( ! Memory . OffsetImm ) return true ;


<s> const TargetRegisterInfo & <ISA_LIT>InstrInfo :: getRegisterInfo ( ) const {


<s> bool <ISA_LIT>AsmParser :: parseDirectiveReq ( StringRef Name , SMLoc L ) { MCAsmParser & Parser = getParser ( ) ; Parser . Lex ( ) ; SMLoc SRegLoc = getLoc ( ) ; unsigned RegNum = tryParseRegister ( ) ; bool IsVector = false ; if ( RegNum == static_cast < unsigned > ( - <NUM_LIT> ) ) { StringRef Kind ; RegNum = tryMatchVectorRegister ( Kind , false ) ; if ( ! Kind . empty ( ) ) return Error ( SRegLoc , <STR_LIT> ) ; IsVector = true ; } if ( RegNum == static_cast < unsigned > ( - <NUM_LIT> ) ) return Error ( SRegLoc , <STR_LIT> ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ;

auto pair = std :: make_pair ( IsVector , RegNum ) ;


<s> bool MVEVPTOptimisations :: runOnMachineFunction ( MachineFunction & Fn ) { const <ISA_LIT>Subtarget & STI = static_cast < const <ISA_LIT>Subtarget & > ( Fn . getSubtarget ( ) ) ;

if ( ! STI . isThumb2 ( ) || ! STI . hasMVEIntegerOps ( ) ) return false ;


<s> void addRegOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> static bool isProfitableToUseFlagOp ( SDValue Op ) { for ( SDNode * U : Op -> uses ( ) ) if ( U -> getOpcode ( ) != <STR_LIT> && U -> getOpcode ( ) != <STR_LIT> && U -> getOpcode ( ) != <STR_LIT> ) return false ; return true ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS ) , DL ( <STR_LIT> ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> default : break ; case <STR_LIT> : return instCombineConvertFromSVBool ( IC , II ) ; case <STR_LIT> : return instCombineSVEDup ( IC , II ) ; case <STR_LIT> : case <STR_LIT> : return instCombineSVELast ( IC , II ) ;


<s> SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Load -> getBasePtr ( ) , DAG . getConstant ( i * ( MemEltVT . getSizeInBits ( ) / <NUM_LIT> ) , PtrVT ) ) ;

SDValue NewLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , EltVT , Load -> getChain ( ) , Ptr , MachinePointerInfo ( Load -> getMemOperand ( ) -> getValue ( ) ) , MemEltVT , Load -> isVolatile ( ) , Load -> isNonTemporal ( ) , Load -> getAlignment ( ) ) ;


<s> if ( Reg == <STR_LIT> ) { MachineFunction & MF = * MBB . getParent ( ) ; if ( MF . getFrameInfo ( ) -> isReturnAddressTaken ( ) && MF . getRegInfo ( ) . isLiveIn ( Reg ) ) isKill = false ; } if ( isKill ) MBB . addLiveIn ( Reg ) ; MIB . addReg ( Reg , getKillRegState ( isKill ) ) ;


<s> virtual void EmitARM64WinCFIEpilogEnd ( ) {


<s> ConstantSDNode * CN = <NUM_LIT> ; if ( ! ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) ) { return false ; } int64_t off = CN -> getSExtValue ( ) ; const SDValue & Base = Addr . getOperand ( <NUM_LIT> ) ; const SDValue * Root = & Base ; if ( Base . getOpcode ( ) == <STR_LIT> && Base . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( CN && ( CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Root = & Base . getOperand ( <NUM_LIT> ) ; }


<s> if ( VTBits == <NUM_LIT> && STI . getSmVersion ( ) >= <NUM_LIT> ) { SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShOpHi , ShAmt ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl ) ; } else { SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue Cmp = DAG . getSetCC ( dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , Cmp , TrueVal , FalseVal ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , dl ) ;


<s> if ( frv_cpu_type != FRV_CPU_FR550 ) return ACC_GROUP_NONE ; return for_each_rtx ( & PATTERN ( insn ) , frv_acc_group_1 , <NUM_LIT> ) ;


<s> poly8x16x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p8 ( val . val [ <NUM_LIT> ] , vcreate_p8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;

return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ;

( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addAddrMode2Operands ( Inst , <NUM_LIT> ) ;


<s> return ( __mmask32 ) __builtin_ia32_kmovd ( * __A ) ;


<s> if ( SW != DW ) return false ; BitVector Used ( DC . width ( ) ) ; if ( ! computeUsedBits ( RD . Reg , Used ) ) return false ;

for ( unsigned i = <NUM_LIT> ; i != DW ; ++ i ) if ( Used [ i + DB ] && DC [ DB + i ] != SC [ SB + i ] ) return false ;


<s> else if ( ( f & <NUM_LIT> ) == <NUM_LIT> ) { if ( TARGET_64BIT ) fprintf ( file , <STR_LIT> , s , reg_names [ gparg ] , reg_names [ fparg ] ) ; else { if ( ( fparg & <NUM_LIT> ) != <NUM_LIT> ) ++ fparg ; if ( TARGET_BIG_ENDIAN ) fprintf ( file , <STR_LIT> , s , reg_names [ gparg ] , reg_names [ fparg + <NUM_LIT> ] , s , reg_names [ gparg + <NUM_LIT> ] , reg_names [ fparg ] ) ; else fprintf ( file , <STR_LIT> , s , reg_names [ gparg ] , reg_names [ fparg ] , s , reg_names [ gparg + <NUM_LIT> ] , reg_names [ fparg + <NUM_LIT> ] ) ; ++ gparg ; ++ fparg ; } } else gcc_unreachable ( ) ; ++ gparg ; ++ fparg ;


<s> if ( ( CI . Offset0 % CI . EltSize != <NUM_LIT> ) || ( CI . Offset1 % CI . EltSize != <NUM_LIT> ) ) return false ; unsigned EltOffset0 = CI . Offset0 / CI . EltSize ; unsigned EltOffset1 = CI . Offset1 / CI . EltSize ; CI . UseST64 = false ; CI . BaseOff = <NUM_LIT> ; if ( ( EltOffset0 % <NUM_LIT> == <NUM_LIT> ) && ( EltOffset1 % <NUM_LIT> ) == <NUM_LIT> && isUInt < <NUM_LIT> > ( EltOffset0 / <NUM_LIT> ) && isUInt < <NUM_LIT> > ( EltOffset1 / <NUM_LIT> ) ) { CI . Offset0 = EltOffset0 / <NUM_LIT> ; CI . Offset1 = EltOffset1 / <NUM_LIT> ; CI . UseST64 = true ; return true ; } if ( isUInt < <NUM_LIT> > ( EltOffset0 ) && isUInt < <NUM_LIT> > ( EltOffset1 ) ) { CI . Offset0 = EltOffset0 ; CI . Offset1 = EltOffset1 ; return true ; } unsigned OffsetDiff = std :: abs ( ( int ) EltOffset1 - ( int ) EltOffset0 ) ; CI . BaseOff = std :: min ( CI . Offset0 , CI . Offset1 ) ; if ( ( OffsetDiff % <NUM_LIT> == <NUM_LIT> ) && isUInt < <NUM_LIT> > ( OffsetDiff / <NUM_LIT> ) ) { CI . Offset0 = ( EltOffset0 - CI . BaseOff / CI . EltSize ) / <NUM_LIT> ; CI . Offset1 = ( EltOffset1 - CI . BaseOff / CI . EltSize ) / <NUM_LIT> ; CI . UseST64 = true ; return true ; } if ( isUInt < <NUM_LIT> > ( OffsetDiff ) ) { CI . Offset0 = EltOffset0 - CI . BaseOff / CI . EltSize ; CI . Offset1 = EltOffset1 - CI . BaseOff / CI . EltSize ; return true ; }


<s> indicatePessimisticFixpoint ( ) ; return ; } if ( <STR_LIT> ( F -> getCallingConv ( ) ) ) { indicatePessimisticFixpoint ( ) ; return ; } for ( StringRef Attr : ImplicitAttrNames ) { if ( F -> hasFnAttribute ( Attr ) ) Attributes . insert ( Attr ) ; } if ( CallingConvSupportsAllImplicits && F -> hasAddressTaken ( nullptr , true , true , true ) ) { for ( StringRef AttrName : ImplicitAttrNames ) {


<s> if ( Directive == <STR_LIT> ) { const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new <ISA_LIT>HazardRecognizer440 ( II , DAG ) ;


<s> explicit <ISA_LIT>LinuxAsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCContext & Ctx , MCStreamer & Streamer , const MCAsmInfo * T ) : <ISA_LIT>AsmPrinter ( O , TM , Ctx , Streamer , T ) {


<s> unsigned ADDiu = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( isInt < <NUM_LIT> > ( Amount ) ) BuildMI ( MBB , I , DL , get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( Amount ) ; else { unsigned Reg = loadImmediate ( Amount , MBB , I , DL , <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( ADDu ) , SP ) . addReg ( SP ) . addReg ( Reg , RegState :: Kill ) ;


<s> fn = gen_store_conditionalqi ; break ; case E_HImode : fn = gen_store_conditionalhi ; break ; case E_SImode : fn = gen_store_conditionalsi ; break ; case E_DImode : fn = gen_store_conditionaldi ; break ; case E_TImode : fn = gen_store_conditionalti ; break ; default : gcc_unreachable ( ) ; } if ( PPC405_ERRATUM77 ) emit_insn ( gen_hwsync ( ) ) ;


<s> static hsa_status_t get_kernarg_region ( hsa_region_t region , void * data __attribute__ ( ( unused ) ) ) {

return get_memory_region ( region , & kernargs_region , HSA_REGION_GLOBAL_FLAG_KERNARG ) ;


<s> MCELFStreamer * create<ISA_LIT>ELFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > MOW , std :: unique_ptr < MCCodeEmitter > MCE , bool RelaxAll ) { <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( C , std :: move ( MAB ) , std :: move ( MOW ) , std :: move ( MCE ) ) ; S -> getAssembler ( ) . setRelaxAll ( RelaxAll ) ;


<s> DebugLoc DL = MIB -> getDebugLoc ( ) ; Register Reg = MIB . getReg ( <NUM_LIT> ) ; const GlobalValue * GV = cast < GlobalValue > ( ( * MIB -> memoperands_begin ( ) ) -> getValue ( ) ) ; auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flags , <NUM_LIT> , <NUM_LIT> ) ; MachineBasicBlock :: iterator I = MIB . getInstr ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addMemOperand ( MMO ) ; MIB -> setDebugLoc ( DL ) ; MIB -> setDesc ( TII . get ( <STR_LIT> ) ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> static std :: string computeDataLayout ( const Triple & TT ) { std :: string Ret = <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ; if ( ( TT . isArch64Bit ( ) && ( TT . getEnvironment ( ) == Triple :: GNUX32 || TT . isOSNaCl ( ) ) ) || ! TT . isArch64Bit ( ) ) Ret += <STR_LIT> ;


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; BuildMI ( * BB , MI , dl , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * BB , MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> FunctionPass * llvm :: createAnnotationsInferencePass ( ) {


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) { unsigned Res = MO . getImm ( ) ; assert ( Res > <NUM_LIT> && <STR_LIT> ) ; return Res - <NUM_LIT> ; } return getImmOpValue ( MI , OpNo , Fixups , STI ) ;


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> || MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = P . getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = P . MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = P . getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = P . MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getHiddenGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } else if ( MO . getTargetFlags ( ) == <STR_LIT> ) { MCSymbol * Sym = P . getSymbolWithGlobalValueBase ( GV , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = P . MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) StubSym = MachineModuleInfoImpl :: StubValueTy ( P . getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ; } if ( GVSym -> getName ( ) [ <NUM_LIT> ] != '$' ) GVSym -> print ( O , P . MAI ) ; else { O << '(' ; GVSym -> print ( O , P . MAI ) ; O << ')' ; } P . printOffset ( MO . getOffset ( ) , O ) ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : O << <STR_LIT> ; P . MF -> getPICBaseSymbol ( ) -> print ( O , P . MAI ) ; O << ']' ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : O << '-' ;


<s> virtual void dump ( raw_ostream & OS ) const {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isa < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) || isa < ConstantSDNode > ( U -> getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || U -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; break ; } } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue SHL = N -> getOperand ( <NUM_LIT> ) ; auto * C1ShlC2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; auto * C2 = dyn_cast < ConstantSDNode > ( SHL . getOperand ( <NUM_LIT> ) ) ; if ( ! C1ShlC2 || ! C2 ) return SDValue ( ) ; APInt C2Int = C2 -> getAPIntValue ( ) ; APInt C1Int = C1ShlC2 -> getAPIntValue ( ) ; APInt Mask = APInt :: getHighBitsSet ( C2Int . getBitWidth ( ) , C2Int . getBitWidth ( ) - C2 -> getZExtValue ( ) ) ; if ( ( C1Int & Mask ) != C1Int ) return SDValue ( ) ; C1Int . lshrInPlace ( C2Int ) ; auto LargeImm = [ ] ( const APInt & Imm ) { unsigned Zeros = Imm . countLeadingZeros ( ) + Imm . countTrailingZeros ( ) ; return Imm . getBitWidth ( ) - Zeros > <NUM_LIT> ; } ; if ( LargeImm ( C1Int ) || LargeImm ( C2Int ) ) return SDValue ( ) ;


<s> if ( MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; else FrameReg = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FrameAddr ;


<s> const <ISA_LIT>Subtarget * Subtarget = & get<ISA_LIT>Subtarget ( ) ;

if ( Subtarget -> isTargetELF ( ) && ! Subtarget -> isThumb1Only ( ) && TM -> Options . EnableFastISel ) addPass ( create<ISA_LIT>GlobalBaseRegPass ( ) ) ;


<s> printRegName ( O , Reg ) ; } else if ( Op . isImm ( ) ) { O << markup ( <STR_LIT> ) << formatImm ( Op . getImm ( ) ) << markup ( <STR_LIT> ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ;


<s> static __inline __m128d __attribute__ ( ( __always_inline__ ) ) _mm_loaddup_pd ( double const * __P ) {


<s> case PROCESSOR_BDVER2 : case PROCESSOR_BDVER3 : case PROCESSOR_BDVER4 : case PROCESSOR_ZNVER1 : case PROCESSOR_ZNVER2 : case PROCESSOR_ZNVER3 : case PROCESSOR_ZNVER4 : case PROCESSOR_CORE2 : case PROCESSOR_NEHALEM : case PROCESSOR_SANDYBRIDGE : case PROCESSOR_HASWELL : case PROCESSOR_TREMONT : case PROCESSOR_SKYLAKE : case PROCESSOR_SKYLAKE_AVX512 : case PROCESSOR_CASCADELAKE : case PROCESSOR_CANNONLAKE : case PROCESSOR_ALDERLAKE : case PROCESSOR_GENERIC : return <NUM_LIT> ; case PROCESSOR_ICELAKE_CLIENT : case PROCESSOR_ICELAKE_SERVER : case PROCESSOR_TIGERLAKE : case PROCESSOR_COOPERLAKE :


<s> bool <ISA_LIT>PassConfig :: addGlobalInstructionSelect ( ) { addPass ( new InstructionSelect ( ) ) ; return false ;


<s> case Instruction :: FCmp : return false ; case Instruction :: ICmp : case Instruction :: Add : return ScalarBits < <NUM_LIT> && ( ScalarBits * cast < VectorType > ( Ty ) -> getNumElements ( ) ) % <NUM_LIT> == <NUM_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> virtual uint32_t SMRDmemriEncode ( const MachineInstr & MI , unsigned OpNo ) const { return <NUM_LIT> ;


<s> return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> return ( uint16x8_t ) __builtin_aarch64_ld1v8hi ( ( const __builtin_aarch64_simd_hi * ) a ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , STI , Ctx ) ;


<s> static SDValue LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>Subtarget * Subtarget ) { DebugLoc dl = Op . getDebugLoc ( ) ; if ( ! Subtarget -> hasDataBarrier ( ) ) { assert ( Subtarget -> hasV6Ops ( ) && ! Subtarget -> isThumb ( ) && <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; }

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) ) ;


<s> return MI . mayStore ( ) && hasStoreToStackSlot ( MI , Dummy , FrameIndex ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>32 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( SDValue ( ) ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } unsigned RetAddrOffset = <NUM_LIT> ; if ( MF . getFunction ( ) -> hasStructRetAttr ( ) ) { <ISA_LIT>MachineFunctionInfo * SFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = SFI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( <STR_LIT> , getPointerTy ( ) ) ) ;


<s> asm_fprintf ( asm_out_file , <STR_LIT> , to_print . c_str ( ) ) ; aarch64_last_printed_arch_string = to_print ; } const struct processor * this_tune = aarch64_get_tune_cpu ( targ_options -> x_explicit_tune_core ) ; if ( flag_debug_asm && aarch64_last_printed_tune_string != this_tune -> name ) { asm_fprintf ( asm_out_file , <STR_LIT> ASM_COMMENT_START <STR_LIT> , this_tune -> name ) ; aarch64_last_printed_tune_string = this_tune -> name ; } ASM_OUTPUT_TYPE_DIRECTIVE ( stream , name , <STR_LIT> ) ;


<s> SDValue FCC0 = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; return DAG . getNode ( ( invert ? <STR_LIT> : <STR_LIT> ) , DL , True . getValueType ( ) , True , FCC0 , False , Cond ) ;


<s> const Section * fCodeSection = TAI -> getNamedSection ( codeSection , SectionFlags :: Code ) ; O << <STR_LIT> ; SwitchToSection ( fCodeSection ) ; O << <STR_LIT> << PAN :: getFrameLabel ( CurrentFnName ) << <STR_LIT> ; O << <STR_LIT> << PAN :: getFrameLabel ( CurrentFnName ) << <STR_LIT> ; O << CurrentFnName << <STR_LIT> ; unsigned CurLine = <NUM_LIT> ; O << <STR_LIT> ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseFGR32Regs ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { return parseRegs ( Operands , ( int ) <STR_LIT> ) ;