<s> if ( CallMI . isCall ( ) && CallMI . getOperand ( <NUM_LIT> ) . isGlobal ( ) ) { const Function * CalleeFn = dyn_cast < Function > ( CallMI . getOperand ( <NUM_LIT> ) . getGlobal ( ) ) ; if ( ! CalleeFn ) return false ; const IntegerType * IntTy = dyn_cast < IntegerType > ( CalleeFn -> getReturnType ( ) ) ; const AttributeSet & Attrs = CalleeFn -> getAttributes ( ) . getRetAttrs ( ) ; if ( IntTy && IntTy -> getBitWidth ( ) <= <NUM_LIT> ) return Attrs . hasAttribute ( SignExt ? Attribute :: SExt : Attribute :: ZExt ) ; } } } } if ( ! Register :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI != NULL ) return isSignOrZeroExtended ( * SrcMI , SignExt , Depth ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI != NULL ) return isSignOrZeroExtended ( * SrcMI , SignExt , Depth ) ; return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( Depth >= MAX_DEPTH ) return false ; unsigned E = <NUM_LIT> , D = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> ) { E = MI . getNumOperands ( ) ; D = <NUM_LIT> ; } for ( unsigned I = <NUM_LIT> ; I != E ; I += D ) { if ( MI . getOperand ( I ) . isReg ( ) ) { Register SrcReg = MI . getOperand ( I ) . getReg ( ) ; if ( ! Register :: isVirtualRegister ( SrcReg ) ) return false ; const MachineInstr * SrcMI = MRI -> getVRegDef ( SrcReg ) ; if ( SrcMI == NULL || ! isSignOrZeroExtended ( * SrcMI , SignExt , Depth + <NUM_LIT> ) ) return false ; } else return false ; }


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ;

const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ;


<s> bool Unsigned = false ; if ( ! isInt < <NUM_LIT> > ( Val ) ) { ShiftAmount = findFirstSet ( ( uint64_t ) Val ) ; Val >>= ShiftAmount ; if ( ShiftAmount > <NUM_LIT> && ! isInt < <NUM_LIT> > ( Val ) ) { if ( isInt < <NUM_LIT> > ( ( uint64_t ) Val << <NUM_LIT> ) ) { ShiftAmount -= <NUM_LIT> ; Val = ( uint64_t ) Val << <NUM_LIT> ; } else if ( isUInt < <NUM_LIT> > ( ( uint64_t ) Val << <NUM_LIT> ) && ActiveFeatures [ <STR_LIT> ] ) { ShiftAmount -= <NUM_LIT> ; Val = ( ( uint64_t ) Val << <NUM_LIT> ) | ( <NUM_LIT> << <NUM_LIT> ) ; Unsigned = true ; } } if ( isUInt < <NUM_LIT> > ( ( uint64_t ) Val ) && ! isInt < <NUM_LIT> > ( ( uint64_t ) Val ) && ActiveFeatures [ <STR_LIT> ] ) { Val = ( ( uint64_t ) Val ) | ( <NUM_LIT> << <NUM_LIT> ) ; Unsigned = true ; } }

generateInstSeqImpl ( Val , ActiveFeatures , Res ) ;


<s> for ( unsigned J = <NUM_LIT> ; J < Desc . getNumDefs ( ) ; ++ J ) { ( ( <ISA_LIT>Operand & ) * Operands [ I ++ ] ) . addRegOperands ( Inst , <NUM_LIT> ) ; } for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( BasicInstType == <STR_LIT> && Op . isReg ( ) && Op . Reg . RegNo == <STR_LIT> ) { continue ; } else if ( Op . isRegOrImmWithInputMods ( ) ) { Op . addRegOrImmWithInputModsOperands ( Inst , <NUM_LIT> ) ; } else if ( Op . isImm ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS && TREE_CODE ( decl ) == FUNCTION_DECL ) { static const char * const visibility_types [ ] = { NULL , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * name , * type ; name = ( ( * targetm . strip_name_encoding ) ( IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ) ) ; type = visibility_types [ vis ] ; fprintf ( asm_out_file , <STR_LIT> , type , name ) ; fprintf ( asm_out_file , <STR_LIT> , type , name ) ; } else default_assemble_visibility ( decl , vis ) ;


<s> } Options . setMacro ( ) ; Parser . Lex ( ) ;


<s> static rtx mips_prepare_builtin_target ( enum insn_code icode , unsigned int op , rtx target ) { enum machine_mode mode ; mode = insn_data [ icode ] . operand [ op ] . mode ;

if ( target == <NUM_LIT> || ! insn_data [ icode ] . operand [ op ] . predicate ( target , mode ) ) target = gen_reg_rtx ( mode ) ;


<s> if ( ! FI ) return ; const MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; unsigned FrameIndexAlign = MFI . getObjectAlign ( FI -> getIndex ( ) ) . value ( ) ; if ( ( FrameIndexAlign % <NUM_LIT> ) != <NUM_LIT> ) FlagSet &= ~ <STR_LIT> ;


<s> static bool MayFoldLoad ( SDValue Op ) {

return Op . hasOneUse ( ) && <STR_LIT> ( Op . getNode ( ) ) ;


<s> int num_income = num_predic - <NUM_LIT> ; Value * polar = intrins -> getOperand ( num_polar ) ; Value * predic = intrins -> getOperand ( num_predic ) ; Type * predic_type = predic -> getType ( ) ; if ( predic_type -> isVectorTy ( ) ) { return true ; } ConstantInt * CPre = dyn_cast < ConstantInt > ( predic ) ; ConstantInt * CPol = cast < ConstantInt > ( polar ) ; unsigned vpola = CPol -> getZExtValue ( ) ; if ( HasIncome ( inid ) ) { Value * income = intrins -> getOperand ( num_income ) ; Type * ti = income -> getType ( ) ; if ( ( ! ( CPre && CPre -> getZExtValue ( ) == <NUM_LIT> ) || vpola == <NUM_LIT> || ti -> isVectorTy ( ) ) && ! isa < UndefValue > ( income ) ) { } } } else if ( dyn_cast < StoreInst > ( & I ) ) { return true ; } else if ( dyn_cast < CallInst > ( & I ) ) { return true ; } else if ( bbk [ rbb ] != EndBB && dyn_cast < ReturnInst > ( & I ) ) { return true ; } else if ( dyn_cast < SwitchInst > ( & I ) ) { return true ; } else { BranchInst * bi = dyn_cast < BranchInst > ( & I ) ; if ( bi ) { int nuo = bi -> getNumSuccessors ( ) ; if ( nuo > <NUM_LIT> ) { return true ; } } for ( auto Usr : I . users ( ) ) { Instruction * instr = dyn_cast < Instruction > ( Usr ) ; BasicBlock * users_bb = instr -> getParent ( ) ; if ( users_bb != rbb ) { if ( PHINode * phi = dyn_cast < PHINode > ( instr ) ) { Value * tv , * fv , * cond ; if ( DecomposePHIAccordingBranch ( bia , phi , & tv , & fv , & cond ) == StopShow ) return true ; else continue ; } return true ; } } } } return instr_count > TOO_MANY_INSTR ;


<s> if ( I -> isCall ( ) || I -> isTerminator ( ) || I -> hasUnmodeledSideEffects ( ) ) return false ; if ( I -> mayStore ( ) || ( ! isLd && I -> mayLoad ( ) ) ) for ( MachineInstr * MemOp : MemOps ) if ( I -> mayAlias ( AA , * MemOp , false ) ) return false ; for ( unsigned j = <NUM_LIT> , NumOps = I -> getNumOperands ( ) ; j != NumOps ; ++ j ) { MachineOperand & MO = I -> getOperand ( j ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( MO . isDef ( ) && TRI -> regsOverlap ( Reg , Base ) ) return false ; if ( Reg != Base && ! MemRegs . count ( Reg ) ) AddedRegPressure . insert ( Reg ) ; } } if ( MemRegs . size ( ) <= <NUM_LIT> ) return true ;

return AddedRegPressure . size ( ) <= MemRegs . size ( ) * <NUM_LIT> ;


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> if ( <ISA_LIT>MCInstrInfo :: isPredicatedNew ( MCII , MCI ) ) NewPreds . insert ( PredReg ) ; }

else for ( MCRegAliasIterator SRI ( R , & RI , ! MCSubRegIterator ( R , & RI ) . isValid ( ) ) ;


<s> return is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> const <ISA_LIT>RegisterInfo * RI = MF . getSubtarget < GCNSubtarget > ( ) . getRegisterInfo ( ) ;

FrameReg = RI -> getFrameRegister ( MF ) ;


<s> Target & llvm :: getThe<ISA_LIT>beTarget ( ) {


<s> case BUILT_IN_SQRT : if ( out_mode == DFmode && out_n == <NUM_LIT> && in_mode == DFmode && in_n == <NUM_LIT> ) return MIPS_GET_BUILTIN ( msa_fsqrt_d ) ; break ; case BUILT_IN_SQRTF :

if ( out_mode == SFmode && out_n == <NUM_LIT> && in_mode == SFmode && in_n == <NUM_LIT> ) return MIPS_GET_BUILTIN ( msa_fsqrt_w ) ;


<s> unsigned Count = getInt64CountDirect ( Imm ) ; if ( Count == <NUM_LIT> ) return getInt64Direct ( CurDAG , dl , Imm ) ; unsigned RMin = <NUM_LIT> ; int64_t MatImm ; unsigned MaskEnd ; for ( unsigned r = <NUM_LIT> ; r < <NUM_LIT> ; ++ r ) { uint64_t RImm = Rot64 ( Imm , r ) ; unsigned RCount = getInt64CountDirect ( RImm ) + <NUM_LIT> ; if ( RCount < Count ) { Count = RCount ; RMin = r ; MatImm = RImm ; MaskEnd = <NUM_LIT> ;


<s> return new <ISA_LIT>MCAsmInfo ( TT ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionPop ( ) {


<s> else { unsigned HOST_WIDE_INT p [ <NUM_LIT> ] ; long l [ <NUM_LIT> ] ; real_to_target ( l , CONST_DOUBLE_REAL_VALUE ( in ) , TFmode ) ; if ( FLOAT_WORDS_BIG_ENDIAN ) { p [ <NUM_LIT> ] = ( ( ( unsigned HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) + l [ <NUM_LIT> ] ; p [ <NUM_LIT> ] = ( ( ( unsigned HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) + l [ <NUM_LIT> ] ; } else { p [ <NUM_LIT> ] = ( ( ( unsigned HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) + l [ <NUM_LIT> ] ; p [ <NUM_LIT> ] = ( ( ( unsigned HOST_WIDE_INT ) l [ <NUM_LIT> ] ) << <NUM_LIT> ) + l [ <NUM_LIT> ] ; } out [ <NUM_LIT> ] = GEN_INT ( p [ <NUM_LIT> ] ) ; out [ <NUM_LIT> ] = GEN_INT ( p [ <NUM_LIT> ] ) ; } break ; case MEM : { rtx base = XEXP ( in , <NUM_LIT> ) ; rtx offset ; switch ( GET_CODE ( base ) ) { case REG : if ( ! reversed ) { out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , gen_rtx_POST_INC ( Pmode , base ) , <NUM_LIT> ) ; out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , dead ? <NUM_LIT> : gen_rtx_POST_DEC ( Pmode , base ) , <NUM_LIT> ) ; } else { emit_insn ( gen_adddi3 ( base , base , GEN_INT ( <NUM_LIT> ) ) ) ; out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , gen_rtx_POST_DEC ( Pmode , base ) , <NUM_LIT> ) ; out [ <NUM_LIT> ] = adjust_address ( in , DImode , <NUM_LIT> ) ; } break ; case POST_INC : gcc_assert ( ! reversed && ! dead ) ; out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , <NUM_LIT> , <NUM_LIT> ) ; out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , <NUM_LIT> , <NUM_LIT> ) ; break ; case POST_DEC : gcc_assert ( ! reversed && ! dead ) ; base = XEXP ( base , <NUM_LIT> ) ; out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , gen_rtx_POST_INC ( Pmode , base ) , <NUM_LIT> ) ; out [ <NUM_LIT> ] = adjust_automodify_address ( in , DImode , gen_rtx_POST_MODIFY ( Pmode , base , plus_constant ( Pmode , base , - <NUM_LIT> ) ) , <NUM_LIT> ) ; break ; case POST_MODIFY : gcc_assert ( ! reversed && ! dead ) ; offset = XEXP ( base , <NUM_LIT> ) ;


<s> vec_char16 av ; av = ( vec_char16 ) ( a ) ; return ( ( qword ) ( vec_unpackh ( vec_perm ( av , av , ( ( vec_uchar16 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) ) ) ;


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> if ( frv_packet . num_insns > <NUM_LIT> && NONJUMP_INSN_P ( insn ) && GET_MODE ( insn ) == TImode && GET_CODE ( PATTERN ( insn ) ) != COND_EXEC ) return false ; if ( get_attr_type ( insn ) != TYPE_SETLO ) if ( frv_registers_conflict_p ( PATTERN ( insn ) ) ) return false ;

return state_transition ( frv_packet . dfa_state , insn ) < <NUM_LIT> ;


<s> if ( auto PT = dyn_cast < PointerType > ( V -> getType ( ) ) ) { unsigned As = PT -> getAddressSpace ( ) ; return As == AS . CONSTANT_ADDRESS || As == AS . CONSTANT_ADDRESS_32BIT ; } return false ;


<s> if ( ! selectBDXAddr ( <STR_LIT> , <STR_LIT> , Op , Base , Disp , Index ) ) return true ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MRI ) {


<s> DEBUG ( dbgs ( ) << <STR_LIT> << ( * SExt ) << '\n' ) ; bool insert = false ; for ( const User * U : SExt -> users ( ) ) { const Instruction * Inst = dyn_cast < GetElementPtrInst > ( U ) ; if ( Inst && Inst -> getNumOperands ( ) > <NUM_LIT> ) { DEBUG ( dbgs ( ) << <STR_LIT> << * Inst << '\n' ) ; insert = true ; break ; } } Instruction * Inst = SExt ; Value * Last ; do { int OpdIdx = <NUM_LIT> ; const BinaryOperator * BinOp = dyn_cast < BinaryOperator > ( Inst ) ; if ( BinOp && isa < ConstantInt > ( BinOp -> getOperand ( <NUM_LIT> ) ) ) OpdIdx = <NUM_LIT> ; Last = Inst -> getOperand ( OpdIdx ) ; Inst = dyn_cast < Instruction > ( Last ) ; } while ( Inst && canGetThrough ( Inst ) && shouldGetThrough ( Inst ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * Last << '\n' ) ; DenseMap < Value * , Instruction * > :: iterator AlreadySeen = SeenChains . find ( Last ) ;

if ( insert || AlreadySeen != SeenChains . end ( ) ) {


<s> if ( ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge == cl :: BOU_UNSET ) || EnableGlobalMerge == cl :: BOU_TRUE ) { bool OnlyOptimizeForSize = ( TM -> getOptLevel ( ) < CodeGenOpt :: Aggressive ) && ( EnableGlobalMerge == cl :: BOU_UNSET ) ; addPass ( createGlobalMergePass ( TM , <NUM_LIT> , OnlyOptimizeForSize ) ) ; } if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>AddressTypePromotionPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableSVEPostVec ) { addPass ( createSVEAddressingModesPass ( ) ) ; addPass ( createDeadCodeEliminationPass ( ) ) ;


<s> static bool multiple_operation_profitable_p ( bool is_store ATTRIBUTE_UNUSED , int nops , HOST_WIDE_INT add_offset ) { if ( nops == <NUM_LIT> && arm_ld_sched && add_offset != <NUM_LIT> ) return false ; if ( nops <= <NUM_LIT> && arm_tune_xscale && ! optimize_size ) return false ; return true ;


<s> if ( CC == CallingConv :: WebKit_JS ) return CC_<ISA_LIT>_WebKit_JS ; if ( CC == CallingConv :: GHC ) return CC_<ISA_LIT>_GHC ;

if ( CC == CallingConv :: CFGuard_Check ) return CC_<ISA_LIT>_Win64_CFGuard_Check ;


<s> SDValue TES = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , <STR_LIT> ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TES , Offset ) ;

SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TES , Offset ) ;


<s> if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> ) ) return true ;


<s> return ( __m64 ) __builtin_ia32_vec_init_v2si ( __i , <NUM_LIT> ) ;


<s> unsigned FPReg = TRI -> getFrameRegister ( MF ) ; for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) { if ( TRI -> regsOverlap ( CSI [ i ] . getReg ( ) , FPReg ) ) { CSI . erase ( CSI . begin ( ) + i ) ; break ; } } } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) continue ; SpillSlotOffset -= SlotSize ; CalleeSavedFrameSize += SlotSize ; int SlotIndex = MFI . CreateFixedSpillStackObject ( SlotSize , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; unsigned Align = TRI -> getSpillAlignment ( * RC ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % Align ; SpillSlotOffset -= Size ; int SlotIndex = MFI . CreateFixedSpillStackObject ( Size , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; MFI . ensureMaxAlignment ( Align ) ; } return true ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool is64Bit ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , is64Bit ) , DataLayout ( Subtarget . getTargetDataString ( ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , JITInfo ( * this , is64Bit ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) ) ;


<s> bool <ISA_LIT>IntrinsicInfo :: isOverloaded ( unsigned id ) const {


<s> add_reg_note ( prev0 , REG_SAVE_NOTE , GEN_INT ( <NUM_LIT> ) ) ; emit_insn_before ( gen_nopv ( ) , insn ) ; continue ; } offset = get_attr_length ( prev0 ) ; if ( get_attr_length ( prev0 ) == <NUM_LIT> && get_attr_iscompact ( prev0 ) != ISCOMPACT_TRUE ) { wantlong = true ; offset += <NUM_LIT> ; } rtx_insn * prev = prev_active_insn ( prev0 ) ; if ( prev ) offset += get_attr_length ( prev ) ; prev = prev_active_insn ( prev ) ; if ( prev ) offset += get_attr_length ( prev ) ; switch ( offset ) { case <NUM_LIT> :

prev = emit_insn_before ( gen_nopv ( ) , insn ) ;


<s> static __inline qword si_orc ( qword a , qword b ) { return ( ( qword ) ( vec_or ( ( vec_uchar16 ) ( a ) , vec_nor ( ( vec_uchar16 ) ( b ) , ( vec_uchar16 ) ( b ) ) ) ) ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> static void mn10300_gen_multiple_store ( unsigned int mask ) { static const unsigned int store_order [ <NUM_LIT> ] = { FIRST_EXTENDED_REGNUM + <NUM_LIT> , FIRST_EXTENDED_REGNUM + <NUM_LIT> , FIRST_EXTENDED_REGNUM + <NUM_LIT> , FIRST_EXTENDED_REGNUM + <NUM_LIT> , FIRST_DATA_REGNUM + <NUM_LIT> , FIRST_DATA_REGNUM + <NUM_LIT> , FIRST_ADDRESS_REGNUM + <NUM_LIT> , FIRST_ADDRESS_REGNUM + <NUM_LIT> , } ; rtx x , elts [ <NUM_LIT> ] ; unsigned int i ; int count ; if ( mask == <NUM_LIT> ) return ;

for ( i = count = <NUM_LIT> ; i < ARRAY_SIZE ( store_order ) ; ++ i ) {


<s> default : return <NUM_LIT> ; case AsmToken :: Identifier : unsigned reg = MatchFslRegister ( getLexer ( ) . getTok ( ) . getIdentifier ( ) ) ; if ( reg >= <NUM_LIT> ) return <NUM_LIT> ; getLexer ( ) . Lex ( ) ;

const MCExpr * EVal = MCConstantExpr :: Create ( reg , getContext ( ) ) ;


<s> assert ( false && <STR_LIT> <STR_LIT> ) ; return <NUM_LIT> ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectThumbAddrModeS4 ( SDValue Op , SDValue N , SDValue & Base , SDValue & OffImm , SDValue & Offset ) {

return SelectThumbAddrModeRI5 ( Op , N , <NUM_LIT> , Base , OffImm , Offset ) ;


<s> else if ( ( rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7 || rs6000_tune == PROCESSOR_POWER8 || rs6000_tune == PROCESSOR_POWER9 ) && reg_classes_intersect_p ( rclass , LINK_OR_CTR_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; else ret = <NUM_LIT> * hard_regno_nregs ( <NUM_LIT> , mode ) ; } else if ( VECTOR_MEM_VSX_P ( mode ) && reg_classes_intersect_p ( to , VSX_REGS ) && reg_classes_intersect_p ( from , VSX_REGS ) ) ret = <NUM_LIT> * hard_regno_nregs ( FIRST_FPR_REGNO , mode ) ; else if ( reg_classes_intersect_p ( to , from ) ) ret = ( FLOAT128_2REG_P ( mode ) ) ? <NUM_LIT> : <NUM_LIT> ; else ret = ( rs6000_register_move_cost ( mode , GENERAL_REGS , to ) + rs6000_register_move_cost ( mode , from , GENERAL_REGS ) ) ; if ( TARGET_DEBUG_COST ) { if ( dbg_cost_ctrl == <NUM_LIT> ) fprintf ( stderr , <STR_LIT> , ret , GET_MODE_NAME ( mode ) , reg_class_names [ from ] , reg_class_names [ to ] ) ; dbg_cost_ctrl -- ; }


<s> Lexer . Lex ( ) ; bool Contigious = Lexer . getTok ( ) . getString ( ) . data ( ) == Lookahead . back ( ) . getString ( ) . data ( ) + Lookahead . back ( ) . getString ( ) . size ( ) ; bool Type = Lexer . is ( AsmToken :: Identifier ) || Lexer . is ( AsmToken :: Dot ) || Lexer . is ( AsmToken :: Integer ) || Lexer . is ( AsmToken :: Real ) || Lexer . is ( AsmToken :: Colon ) ; bool Workaround = Lexer . is ( AsmToken :: Colon ) || Lookahead . back ( ) . is ( AsmToken :: Colon ) ; Again = ( Contigious && Type ) || ( Workaround && Type ) ; NeededWorkaround = NeededWorkaround || ( Again && ! ( Contigious && Type ) ) ; } std :: string Collapsed = RawString ; Collapsed . erase ( std :: remove_if ( Collapsed . begin ( ) , Collapsed . end ( ) , isspace ) , Collapsed . end ( ) ) ; StringRef FullString = Collapsed ; std :: pair < StringRef , StringRef > DotSplit = FullString . split ( '.' ) ; unsigned DotReg = matchRegister ( DotSplit . first . lower ( ) ) ; if ( DotReg != <STR_LIT> && RegisterMatchesArch ( DotReg ) ) { if ( DotSplit . second . empty ( ) ) { RegNo = DotReg ;


<s> void <ISA_LIT>InstPrinter :: printMRSSystemRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; if ( Val == <STR_LIT> ) { O << <STR_LIT> ; return ; }


<s> if ( HighPressureSets [ P . getPSet ( ) ] ) return ( isBotUp ? P . getUnitInc ( ) : - P . getUnitInc ( ) ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: allowFMA ( ) const { const <ISA_LIT>TargetLowering * TL = Subtarget -> getTargetLowering ( ) ; return TL -> allowFMA ( * MF , OptLevel ) ;


<s> Type * ElemTy = Val -> isVectorTy ( ) ? cast < VectorType > ( Val ) -> getElementType ( ) : Val ; if ( Opcode == Instruction :: InsertElement ) { unsigned Cost = ( Index != <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( ElemTy -> isIntegerTy ( <NUM_LIT> ) ) return Cost ; return Cost + getVectorInstrCost ( Instruction :: ExtractElement , Val , Index ) ; }

if ( Opcode == Instruction :: ExtractElement ) return <NUM_LIT> ;


<s> case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_REDWOOD : AK = GK_REDWOOD ; break ; case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_SUMO : AK = GK_SUMO ; break ; case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_BARTS : AK = GK_BARTS ; break ; case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CAICOS : AK = GK_CAICOS ; break ; case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CAYMAN : AK = GK_CAYMAN ; break ; case ELF :: EF_AMDGPU_MACH_<ISA_LIT>_TURKS : AK = GK_TURKS ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX600 : AK = GK_GFX600 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX601 : AK = GK_GFX601 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX700 : AK = GK_GFX700 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX701 : AK = GK_GFX701 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX702 : AK = GK_GFX702 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX703 : AK = GK_GFX703 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX704 : AK = GK_GFX704 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX801 : AK = GK_GFX801 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX802 : AK = GK_GFX802 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX803 : AK = GK_GFX803 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX810 : AK = GK_GFX810 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX900 : AK = GK_GFX900 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX902 : AK = GK_GFX902 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX904 : AK = GK_GFX904 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX906 : AK = GK_GFX906 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX908 : AK = GK_GFX908 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX909 : AK = GK_GFX909 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1010 : AK = GK_GFX1010 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1011 : AK = GK_GFX1011 ; break ; case ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1012 : AK = GK_GFX1012 ; break ;

case ELF :: EF_<ISA_LIT>_MACH_NONE : AK = GK_NONE ; break ;


<s> ParsedValues ( ) : M ( nullptr ) , P ( nullptr ) , Q ( nullptr ) , R ( nullptr ) , X ( nullptr ) , Res ( nullptr ) , IterCount ( <NUM_LIT> ) , Left ( false ) , Inv ( false ) {


<s> if ( ( static_cast < uint8_t > ( data [ <NUM_LIT> ] ) == <ISA_LIT>ELFAttributeData :: Tag_CPU_arch ) && ( ( data [ <NUM_LIT> ] == <ISA_LIT>ELFAttributeData :: CPU_Arch_<ISA_LIT>_V4T ) || ( data [ <NUM_LIT> ] == <ISA_LIT>ELFAttributeData :: CPU_Arch_<ISA_LIT>_V6_M ) ) ) return static_cast < uint32_t > ( data [ <NUM_LIT> ] ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { bool SCS = MF . getFunction ( ) . hasFnAttribute ( Attribute :: ShadowCallStack ) ; if ( CC == CallingConv :: GHC ) return SCS ? CSR_<ISA_LIT>_NoRegs_SCS_RegMask : CSR_<ISA_LIT>_NoRegs_RegMask ; if ( CC == CallingConv :: AnyReg ) return SCS ? CSR_<ISA_LIT>_AllRegs_SCS_RegMask : CSR_<ISA_LIT>_AllRegs_RegMask ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isTargetDarwin ( ) ) { if ( SCS ) report_fatal_error ( <STR_LIT> ) ;

return getDarwinCallPreservedMask ( MF , CC ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _rdpkru_u32 ( void ) {


<s> MachineBasicBlock * Pred = * MBB . pred_begin ( ) ; if ( ! Pred -> empty ( ) ) { MachineInstr * LastMI = & * Pred -> rbegin ( ) ; if ( LastMI -> getOpcode ( ) == <STR_LIT> ) { MachineBasicBlock :: iterator CmpMI = LastMI ; if ( CmpMI != Pred -> begin ( ) ) { -- CmpMI ; if ( CmpMI -> getOpcode ( ) == <STR_LIT> || CmpMI -> getOpcode ( ) == <STR_LIT> ) { unsigned Reg = CmpMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> P = getInstrPredicate ( CmpMI , PredReg ) ; if ( P == <STR_LIT> && CmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && is<ISA_LIT>LowRegister ( Reg ) ) return false ; } } } } } unsigned UnpredCost = Probability . getNumerator ( ) * NumCycles ;

UnpredCost /= Probability . getDenominator ( ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) { return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ;


<s> static Optional < Instruction * > instCombineSVEDupX ( InstCombiner & IC , IntrinsicInst & II ) { IRBuilder < > Builder ( II . getContext ( ) ) ; Builder . SetInsertPoint ( & II ) ;

auto * RetTy = cast < ScalableVectorType > ( II . getType ( ) ) ;


<s> case <STR_LIT> : lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , <ISA_LIT>MCExpr :: MEK_LO ) ; return true ; case <STR_LIT> : unsigned TargetFlags = MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ; if ( TargetFlags == <STR_LIT> ) lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , <ISA_LIT>MCExpr :: MEK_HI ) ; else if ( TargetFlags == <STR_LIT> ) lowerLongBranchADDiu ( MI , OutMI , <STR_LIT> , <ISA_LIT>MCExpr :: MEK_LO ) ; else report_fatal_error ( <STR_LIT> ) ;


<s> bool isSramEccSupported ( ) const { return SramEccSetting != TargetIDSetting :: Unsupported ;


<s> static unsigned int rx_pid_base_regnum ( void ) { if ( rx_pid_base_regnum_val == INVALID_REGNUM ) gcc_unreachable ( ) ;


<s> SDValue Value1 = extractSubVector ( StoredVal , NumElems / <NUM_LIT> , DAG , DL , HalfSize ) ; SDValue Ptr0 = Store -> getBasePtr ( ) ; SDValue Ptr1 = DAG . getMemBasePlusOffset ( Ptr0 , HalfAlign , DL ) ; unsigned Alignment = Store -> getAlignment ( ) ; SDValue Ch0 = DAG . getStore ( Store -> getChain ( ) , DL , Value0 , Ptr0 , Store -> getPointerInfo ( ) , Alignment , Store -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Ch1 = DAG . getStore ( Store -> getChain ( ) , DL , Value1 , Ptr1 , Store -> getPointerInfo ( ) . getWithOffset ( HalfAlign ) , MinAlign ( Alignment , HalfAlign ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ch0 , Ch1 ) ;


<s> TS -> EmitDirectiveHSACodeObjectVersion ( <NUM_LIT> , <NUM_LIT> ) ; <STR_LIT> ISA = <STR_LIT> ( STI -> getFeatureBits ( ) ) ; TS -> EmitDirectiveHSACodeObjectISA ( ISA . Major , ISA . Minor , ISA . Stepping , <STR_LIT> , <STR_LIT> ) ; emitStartOfRuntimeMetadata ( M ) ;


<s> MI . setDesc ( get ( III . ImmOpcode ) ) ; if ( ConstantOpNo == III . OpNoForForwarding ) { if ( SpecialShift32 || SpecialShift64 ) { LoadImmediateInfo LII ; LII . Imm = <NUM_LIT> ; LII . SetCR = SetCR ; LII . Is64Bit = SpecialShift64 ; uint64_t ShAmt = Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ; if ( Imm & ( SpecialShift32 ? <NUM_LIT> : <NUM_LIT> ) ) replaceInstrWithLI ( MI , LII ) ; else if ( ! SetCR && ShAmt == <NUM_LIT> && ! PostRA ) { MI . RemoveOperand ( <NUM_LIT> ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; } else { if ( SpecialShift32 ) { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t MB = RightShift ? ShAmt : <NUM_LIT> ; uint64_t ME = RightShift ? <NUM_LIT> : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( MB ) . addImm ( ME ) ; } else { uint64_t SH = RightShift ? <NUM_LIT> - ShAmt : ShAmt ; uint64_t ME = RightShift ? ShAmt : <NUM_LIT> - ShAmt ; replaceInstrOperandWithImm ( MI , III . OpNoForForwarding , SH ) ; MachineInstrBuilder ( * MI . getParent ( ) -> getParent ( ) , MI ) . addImm ( ME ) ; } } } else replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; } else if ( III . IsCommutative ) { replaceInstrOperandWithImm ( MI , ConstantOpNo , Imm ) ; swapMIOperands ( MI , ConstantOpNo , III . OpNoForForwarding ) ; } else llvm_unreachable ( <STR_LIT> ) ; if ( III . OpNoForForwarding != III . ImmOpNo ) swapMIOperands ( MI , III . OpNoForForwarding , III . ImmOpNo ) ; if ( ! PostRA && III . ZeroIsSpecialOrig != III . ZeroIsSpecialNew ) { if ( III . ZeroIsSpecialNew ) { unsigned RegToModify = MI . getOperand ( III . ZeroIsSpecialNew ) . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( RegToModify ) ) { const TargetRegisterClass * NewRC = MRI . getRegClass ( RegToModify ) -> hasSuperClassEq ( & <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; MRI . setRegClass ( RegToModify , NewRC ) ; } } }

if ( ForwardKilledOperandReg != ~ <NUM_LIT> ) fixupIsDeadOrKill ( DefMI , MI , ForwardKilledOperandReg ) ;


<s> const TargetInstrInfo * TII = Fn . getTarget ( ) . getInstrInfo ( ) ; MachineLoopInfo & MLI = getAnalysis < MachineLoopInfo > ( ) ; MachineDominatorTree & MDT = getAnalysis < MachineDominatorTree > ( ) ; Tile64VLIWPacketizerList Packetizer ( Fn , MLI , MDT ) ; assert ( Packetizer . getResourceTracker ( ) && <STR_LIT> ) ;

for ( MachineFunction :: iterator MBB = Fn . begin ( ) , MBBe = Fn . end ( ) ;


<s> const MCOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <STR_LIT> . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <STR_LIT> . contains ( IndexReg . getReg ( ) ) ) ) return true ; return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> - <NUM_LIT> - ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) - MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX18Reserved ( ) - MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isX20Reserved ( ) - hasBasePointer ( MF ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> :


<s> SDValue NewX = DAG . getNode ( <STR_LIT> , X . getDebugLoc ( ) , VT , X ) ; InsertDAGNode ( DAG , N , NewX ) ; X = NewX ; } DebugLoc DL = N . getDebugLoc ( ) ; SDValue NewSRLAmt = DAG . getConstant ( ShiftAmt + AMShiftAmt , <STR_LIT> ) ; SDValue NewSRL = DAG . getNode ( <STR_LIT> , DL , VT , X , NewSRLAmt ) ; SDValue NewSHLAmt = DAG . getConstant ( AMShiftAmt , <STR_LIT> ) ; SDValue NewSHL = DAG . getNode ( <STR_LIT> , DL , VT , NewSRL , NewSHLAmt ) ; InsertDAGNode ( DAG , N , NewSRLAmt ) ; InsertDAGNode ( DAG , N , NewSRL ) ; InsertDAGNode ( DAG , N , NewSHLAmt ) ; InsertDAGNode ( DAG , N , NewSHL ) ;

DAG . ReplaceAllUsesWith ( N , NewSHL ) ;


<s> ~ <ISA_LIT>AsmPrinter ( ) override { delete reader ;


<s> rtx prev_set = single_set ( prev ) ; rtx curr_set = single_set ( curr ) ; if ( ! prev_set || ! curr_set ) return false ; if ( any_condjump_p ( curr ) ) return false ; if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT && arm_sets_movw_movt_fusible_p ( prev_set , curr_set ) ) return true ;


<s> MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;


<s> static MachineInstr * MakeM0Inst ( const TargetInstrInfo & TII , unsigned Opcode , ArrayRef < MachineOperand > MOs , MachineBasicBlock :: iterator InsertPt , MachineInstr * MI ) {

MachineInstrBuilder MIB = BuildMI ( * InsertPt -> getParent ( ) , InsertPt , MI -> getDebugLoc ( ) , TII . get ( Opcode ) ) ;


<s> bool Res = SelectVOP3Mods0 ( In , Src , SrcMods , Clamp , Omod ) ; return Res && cast < ConstantSDNode > ( SrcMods ) -> isNullValue ( ) && cast < ConstantSDNode > ( Clamp ) -> isNullValue ( ) && cast < ConstantSDNode > ( Omod ) -> isNullValue ( ) ;


<s> if ( CostKind == TTI :: TCK_RecipThroughput && ( ST -> hasNEON ( ) || ST -> hasMVEIntegerOps ( ) ) ) { return <NUM_LIT> ;


<s> Register FrameReg = FrameInfo . isFixedObjectIndex ( Index ) && hasBasePointer ( SB . MF ) ? getBaseRegister ( ) : getFrameRegister ( SB . MF ) ; Align Alignment = FrameInfo . getObjectAlign ( Index ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( SB . MF , Index ) ; MachineMemOperand * MMO = SB . MF . getMachineMemOperand ( PtrInfo , IsLoad ? MachineMemOperand :: MOLoad : MachineMemOperand :: MOStore , SB . EltSize , Alignment ) ; if ( IsLoad ) {

unsigned Opc = ST . enableFlatScratch ( ) ? <STR_LIT> : <STR_LIT> ;


<s> SDValue Lo = DAG . getLoad ( <STR_LIT> , DL , Chain , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , Nd . getAlignment ( ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , PtrVT , Ptr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue Hi = DAG . getLoad ( <STR_LIT> , DL , Lo . getValue ( <NUM_LIT> ) , Ptr , MachinePointerInfo ( ) , Nd . isVolatile ( ) , Nd . isNonTemporal ( ) , Nd . isInvariant ( ) , std :: min ( Nd . getAlignment ( ) , <NUM_LIT> ) ) ;

if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo , Hi ) ;


<s> Value * Undef = UndefValue :: get ( B . getFloatTy ( ) ) ; B . CreateIntrinsic ( <STR_LIT> , { B . getFloatTy ( ) } , { B . getInt32 ( <STR_LIT> :: ET_NULL ) , B . getInt32 ( <NUM_LIT> ) , Undef , Undef , Undef , Undef , B . getTrue ( ) , B . getTrue ( ) , } ) ; } PHINode * PN = nullptr ; if ( F . getReturnType ( ) -> isVoidTy ( ) ) { B . CreateRetVoid ( ) ; } else {

PN = B . CreatePHI ( F . getReturnType ( ) , ReturningBlocks . size ( ) , <STR_LIT> ) ;


<s> case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; case <NUM_LIT> : LoadMnemonic = <STR_LIT> ; StoreMnemonic = <STR_LIT> ; break ; } const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction * F = BB -> getParent ( ) ; MachineFunction :: iterator It = ++ BB -> getIterator ( ) ; Register dest = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ptrA = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ptrB = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register incr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineBasicBlock * loopMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * loop2MBB = CmpOpcode ? F -> CreateMachineBasicBlock ( LLVM_BB ) : nullptr ; MachineBasicBlock * exitMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , loopMBB ) ; if ( CmpOpcode ) F -> insert ( It , loop2MBB ) ; F -> insert ( It , exitMBB ) ; exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; MachineRegisterInfo & RegInfo = F -> getRegInfo ( ) ; Register TmpReg = ( ! BinOpcode ) ? incr : RegInfo . createVirtualRegister ( AtomicSize == <NUM_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; BB -> addSuccessor ( loopMBB ) ; BB = loopMBB ; BuildMI ( BB , dl , TII -> get ( LoadMnemonic ) , dest ) . addReg ( ptrA ) . addReg ( ptrB ) ;

if ( BinOpcode ) BuildMI ( BB , dl , TII -> get ( BinOpcode ) , TmpReg ) . addReg ( incr ) . addReg ( dest ) ;


<s> case <STR_LIT> : \ return # name switch ( Opcode ) { default : return nullptr ; NODE ( RET_FLAG ) ; NODE ( RETI_FLAG ) ; NODE ( CALL ) ; NODE ( WRAPPER ) ;


<s> uint64_t Index = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isInt < <NUM_LIT> > ( Disp ) && isUInt < <NUM_LIT> > ( Index ) ) ; return ( Index << <NUM_LIT> ) | ( Base << <NUM_LIT> ) | ( ( Disp & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Disp & <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> initialize<ISA_LIT>ExpandSSRPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> rtx m , a ; if ( ! rl78_virt_insns_ok ( ) ) return false ; fprintf ( stderr , <STR_LIT> ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; debug_rtx ( operands [ <NUM_LIT> ] ) ; fprintf ( stderr , <STR_LIT> ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && GET_CODE ( operands [ <NUM_LIT> ] ) != REG ) { fprintf ( stderr , <STR_LIT> ) ; return false ; } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { fprintf ( stderr , <STR_LIT> ) ; return false ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( GET_CODE ( operands [ i ] ) != GET_CODE ( operands [ i + <NUM_LIT> ] ) ) { fprintf ( stderr , <STR_LIT> ) ; return false ; } if ( GET_MODE ( operands [ i ] ) != GET_MODE ( operands [ i + <NUM_LIT> ] ) ) { fprintf ( stderr , <STR_LIT> ) ; return false ; } switch ( GET_CODE ( operands [ i ] ) ) { case REG : if ( REGNO ( operands [ i ] ) + <NUM_LIT> != REGNO ( operands [ i + <NUM_LIT> ] ) || GET_MODE ( operands [ i ] ) != QImode ) { fprintf ( stderr , <STR_LIT> , REGNO ( operands [ i ] ) , REGNO ( operands [ i + <NUM_LIT> ] ) , i ) ; return false ; } if ( ! rl78_hard_regno_mode_ok ( REGNO ( operands [ i ] ) , HImode ) ) { fprintf ( stderr , <STR_LIT> , REGNO ( operands [ i ] ) ) ; return false ; } break ; case CONST_INT : break ; case MEM : if ( GET_MODE ( operands [ i ] ) != QImode ) return false ; if ( MEM_ALIGN ( operands [ i ] ) < <NUM_LIT> ) return false ; a = XEXP ( operands [ i ] , <NUM_LIT> ) ; if ( GET_CODE ( a ) == CONST ) a = XEXP ( a , <NUM_LIT> ) ;

if ( GET_CODE ( a ) == PLUS ) a = XEXP ( a , <NUM_LIT> ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> if ( optimize && optimize_function_for_speed_p ( cfun ) ) { if ( TARGET_SSE2 ) ix86_split_stlf_stall_load ( ) ; if ( TARGET_PAD_SHORT_FUNCTION ) ix86_pad_short_function ( ) ; else if ( TARGET_PAD_RETURNS ) ix86_pad_returns ( ) ;

if ( TARGET_FOUR_JUMP_LIMIT ) ix86_avoid_jump_mispredicts ( ) ;


<s> unsigned MaxOffset = TLI -> getMaximalGlobalOffset ( ) ; std :: stable_sort ( Globals . begin ( ) , Globals . end ( ) , GlobalCmp ( TD ) ) ; Type * Int32Ty = Type :: getInt32Ty ( M . getContext ( ) ) ; for ( size_t i = <NUM_LIT> , e = Globals . size ( ) ; i != e ; ) { size_t j = <NUM_LIT> ; uint64_t MergedSize = <NUM_LIT> ; std :: vector < Type * > Tys ; std :: vector < Constant * > Inits ; for ( j = i ; j != e ; ++ j ) { Type * Ty = Globals [ j ] -> getType ( ) -> getElementType ( ) ; MergedSize += TD -> getTypeAllocSize ( Ty ) ; if ( MergedSize > MaxOffset ) { break ; } Tys . push_back ( Ty ) ; Inits . push_back ( Globals [ j ] -> getInitializer ( ) ) ; } StructType * MergedTy = StructType :: get ( M . getContext ( ) , Tys ) ; Constant * MergedInit = ConstantStruct :: get ( MergedTy , Inits ) ; GlobalVariable * MergedGV = new GlobalVariable ( M , MergedTy , isConst , GlobalValue :: InternalLinkage , MergedInit , <STR_LIT> ) ; for ( size_t k = i ; k < j ; ++ k ) { Constant * Idx [ <NUM_LIT> ] = { ConstantInt :: get ( Int32Ty , <NUM_LIT> ) , ConstantInt :: get ( Int32Ty , k - i ) } ; Constant * GEP = ConstantExpr :: getInBoundsGetElementPtr ( MergedGV , Idx ) ; Globals [ k ] -> replaceAllUsesWith ( GEP ) ; Globals [ k ] -> eraseFromParent ( ) ; } i = j ;


<s> EVT <ISA_LIT>TargetLowering :: getAsmOperandValueType ( const DataLayout & DL , llvm :: Type * Ty , bool AllowUnknown ) const { if ( Subtarget -> hasLS64 ( ) && Ty -> isIntegerTy ( <NUM_LIT> ) ) return EVT ( <STR_LIT> ) ; return TargetLowering :: getAsmOperandValueType ( DL , Ty , AllowUnknown ) ;


<s> if ( MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) ) NumRegs = <NUM_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) ) NumRegs = <NUM_LIT> ; else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) || MRI . getRegClass ( <STR_LIT> ) . contains ( Reg ) ) NumRegs = <NUM_LIT> ;

if ( unsigned FirstReg = MRI . getSubReg ( Reg , <STR_LIT> ) ) Reg = FirstReg ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerAtomicFence ( SDValue Op , SelectionDAG & DAG ) const {


<s> int ret = decodeInstruction ( & internalInstr , regionReader , ( void * ) & region , logger , ( void * ) & vStream , address , fMode ) ; if ( ret ) { size = internalInstr . readerCursor - address ; return false ; } else { size = internalInstr . length ; return ! translateInstruction ( instr , internalInstr ) ;


<s> bool IsFixed ( unsigned ValNo ) { return ArgIsFixed [ ValNo ] ;


<s> ElementTypeId = ArrayInfo . ElemType ; LocOffset = Loc * ElemSize ;


<s> assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , OutContext ) ) ; break ; case MachineOperand :: MO_GlobalAddress : { MCOp = GetSymbolRef ( MO , Get<ISA_LIT>GVSymbol ( MO . getGlobal ( ) , MO . getTargetFlags ( ) ) ) ; break ; } case MachineOperand :: MO_ExternalSymbol : MCOp = GetSymbolRef ( MO , GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = GetSymbolRef ( MO , GetJTISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : if ( Subtarget -> genExecuteOnly ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCOp = GetSymbolRef ( MO , GetCPISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = GetSymbolRef ( MO , GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ; break ; case MachineOperand :: MO_FPImmediate : { APFloat Val = MO . getFPImm ( ) -> getValueAPF ( ) ; bool ignored ; Val . convert ( APFloat :: IEEEdouble ( ) , APFloat :: rmTowardZero , & ignored ) ; MCOp = MCOperand :: createFPImm ( Val . convertToDouble ( ) ) ; break ; } case MachineOperand :: MO_RegisterMask : return false ; } return true ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {


<s> static LegalizerInfo :: SizeAndActionsVec widen_1_8 ( const LegalizerInfo :: SizeAndActionsVec & v ) { assert ( v . size ( ) >= <NUM_LIT> ) ; assert ( v [ <NUM_LIT> ] . first > <NUM_LIT> ) ; LegalizerInfo :: SizeAndActionsVec result = { { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } , { <NUM_LIT> , LegalizerInfo :: WidenScalar } , { <NUM_LIT> , LegalizerInfo :: Unsupported } } ; addAndInterleaveWithUnsupported ( result , v ) ;

auto Largest = result . back ( ) . first ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ;

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( The<ISA_LIT>elTarget ) ;


<s> return create<ISA_LIT>ObjectWriter ( OS , OSABI ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getEHExceptionRegister ( ) const {


<s> assert ( I . getOpcode ( ) == TargetOpcode :: G_CONSTANT && <STR_LIT> ) ; uint64_t CstVal = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; uint64_t Enc = <STR_LIT> ( CstVal , <NUM_LIT> ) ; MIB . addImm ( Enc ) ;


<s> unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , TRI -> getFrameRegister ( ) , VT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FrameAddr ;


<s> u . i [ <NUM_LIT> ] = b ; u . i [ <NUM_LIT> ] = c ; u . i [ <NUM_LIT> ] = d ;


<s> unsigned long arm_current_func_type ( ) {

if ( ARM_FUNC_TYPE ( cfun -> machine -> func_type ) == ARM_FT_UNKNOWN ) cfun -> machine -> func_type = arm_compute_func_type ( ) ;


<s> case <STR_LIT> : { SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue RTB = DAG . getNode ( <STR_LIT> , dl , VTs , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( RTB ) ; Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; Results . push_back ( RTB . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <STR_LIT> ) break ; assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; EVT SVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , N -> getValueType ( <NUM_LIT> ) ) ; SDVTList VTs = DAG . getVTList ( SVT , <STR_LIT> ) ; SDValue NewInt = DAG . getNode ( N -> getOpcode ( ) , dl , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; Results . push_back ( NewInt ) ; Results . push_back ( NewInt . getValue ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : { if ( ! Subtarget . isSVR4ABI ( ) || Subtarget . is<ISA_LIT>64 ( ) ) return ; EVT VT = N -> getValueType ( <NUM_LIT> ) ;


<s> <ISA_LIT>ompactTargetMachine :: <ISA_LIT>ompactTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) {


<s> IRB . SetInsertPoint ( InsertPt ) ; IRB . SetInsertPoint ( BB ) ; BasicBlock * ThenBB1 = BasicBlock :: Create ( C , <STR_LIT> , F ) ; BasicBlock * ElseBB1 = BasicBlock :: Create ( C , <STR_LIT> , F ) ; BasicBlock * EndBB1 = BasicBlock :: Create ( C , <STR_LIT> , F ) ; Value * ThrewCmp = IRB . CreateICmpNE ( Threw , IRB . getInt32 ( <NUM_LIT> ) ) ; Value * ThrewValue = IRB . CreateLoad ( ThrewValueGV , ThrewValueGV -> getName ( ) + <STR_LIT> ) ; Value * ThrewValueCmp = IRB . CreateICmpNE ( ThrewValue , IRB . getInt32 ( <NUM_LIT> ) ) ; Value * Cmp1 = IRB . CreateAnd ( ThrewCmp , ThrewValueCmp , <STR_LIT> ) ; IRB . CreateCondBr ( Cmp1 , ThenBB1 , ElseBB1 ) ; IRB . SetInsertPoint ( ThenBB1 ) ; BasicBlock * ThenBB2 = BasicBlock :: Create ( C , <STR_LIT> , F ) ; BasicBlock * EndBB2 = BasicBlock :: Create ( C , <STR_LIT> , F ) ; Value * ThrewInt = IRB . CreateIntToPtr ( Threw , Type :: getInt32PtrTy ( C ) , Threw -> getName ( ) + <STR_LIT> ) ; Value * LoadedThrew = IRB . CreateLoad ( ThrewInt , ThrewInt -> getName ( ) + <STR_LIT> ) ; Value * ThenLabel = IRB . CreateCall ( TestSetjmpF , { LoadedThrew , SetjmpTable , SetjmpTableSize } , <STR_LIT> ) ; Value * Cmp2 = IRB . CreateICmpEQ ( ThenLabel , IRB . getInt32 ( <NUM_LIT> ) ) ; IRB . CreateCondBr ( Cmp2 , ThenBB2 , EndBB2 ) ; IRB . SetInsertPoint ( ThenBB2 ) ; IRB . CreateCall ( EmLongjmpF , { Threw , ThrewValue } ) ; IRB . CreateUnreachable ( ) ; IRB . SetInsertPoint ( EndBB2 ) ;

IRB . CreateStore ( ThrewValue , TempRet0GV ) ;


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ( Rd + <NUM_LIT> ) % <NUM_LIT> , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , wb , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ; } if ( ! Check ( S , DecodeAddrMode6Operand ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { default : if ( Rm == <NUM_LIT> ) { Inst . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( sti ) {


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> Cmp ( DenseMap < const MachineInstr * , unsigned > & Map ) : Dist ( Map ) {


<s> bool <ISA_LIT>ExpandPseudo :: expandAtomicBinaryOp ( unsigned Opcode , Block & MBB , BlockIt MBBI ) {

return expandAtomicBinaryOp ( Opcode , MBB , MBBI , [ ] ( MachineInstr & MI ) { } ) ;


<s> case TargetOpcode :: G_ADD : case TargetOpcode :: G_OR : { assert ( ( OpdMapper . getInstrMapping ( ) . getID ( ) == <NUM_LIT> || OpdMapper . getInstrMapping ( ) . getID ( ) == <NUM_LIT> ) && <STR_LIT> ) ;

return applyDefaultMapping ( OpdMapper ) ;


<s> F -> insert ( It , TBB ) ; F -> insert ( It , Sink ) ; Sink -> splice ( Sink -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; Sink -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( FBB ) ; BB -> addSuccessor ( TBB ) ; FBB -> addSuccessor ( Sink ) ; TBB -> addSuccessor ( Sink ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) ; unsigned VR2 = RegInfo . createVirtualRegister ( RC ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , VR2 ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( * FBB , FBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( Sink ) ;

unsigned VR1 = RegInfo . createVirtualRegister ( RC ) ;


<s> rtx mips_strip_unspec_address ( rtx op ) { rtx base , offset ; split_const ( op , & base , & offset ) ;

if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ;


<s> if ( isa < AtomicRMWInst > ( V ) || isa < AtomicCmpXchgInst > ( V ) ) return true ; if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) { const TargetMachine & TM = getTLI ( ) -> getTargetMachine ( ) ; return isIntrinsicSourceOfDivergence ( TM . getIntrinsicInfo ( ) , Intrinsic ) ; } if ( isa < CallInst > ( V ) || isa < InvokeInst > ( V ) ) return true ; return false ;


<s> } <ISA_LIT>FI -> setCalleeSavedFrameSize ( CalleeSavedFrameSize ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; unsigned Align = TRI -> getSpillAlignment ( * RC ) ; SpillSlotOffset -= std :: abs ( SpillSlotOffset ) % Align ; SpillSlotOffset -= Size ; int SlotIndex = MFI . CreateFixedSpillStackObject ( Size , SpillSlotOffset ) ; CSI [ i - <NUM_LIT> ] . setFrameIdx ( SlotIndex ) ; MFI . ensureMaxAlignment ( Align ) ;


<s> } else if ( LocVT == <STR_LIT> ) { unsigned Req = HST . useHVX128BOps ( ) ? <STR_LIT> : <STR_LIT> ; if ( unsigned Reg = State . AllocateReg ( Req ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } else if ( LocVT == <STR_LIT> ) { if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;


<s> assert ( NumBits % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; SDValue ShiftVal = DAG . getConstant ( NumBits / <NUM_LIT> , ScalarShiftTy ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , ShiftVal ) ) ;


<s> assert ( HasAVX ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasAVX2 ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else if ( IsNonTemporal && Alignment >= <NUM_LIT> ) return false ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasAVX2 ) Opc = <STR_LIT> ; else if ( IsNonTemporal && Alignment >= <NUM_LIT> ) return false ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( HasAVX ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> && HasAVX2 ) Opc = <STR_LIT> ; else if ( IsNonTemporal && Alignment >= <NUM_LIT> ) return false ; else if ( Alignment >= <NUM_LIT> ) Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; else Opc = HasVLX ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX512 ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> ) Opc = <STR_LIT> ; else Opc = ( Alignment >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : assert ( HasAVX512 ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> ) Opc = <STR_LIT> ; else Opc = ( Alignment >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( HasAVX512 ) ; if ( IsNonTemporal && Alignment >= <NUM_LIT> ) Opc = <STR_LIT> ; else Opc = ( Alignment >= <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ;


<s> NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) && Op -> hasOneUse ( ) && isa < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) && ! hasNonFlagsUse ( Op ) ) { EVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt >= BitWidth ) break ; APInt Mask = ArithOp . getOpcode ( ) == <STR_LIT> ? APInt :: getHighBitsSet ( BitWidth , BitWidth - ShAmt ) : APInt :: getLowBitsSet ( BitWidth , BitWidth - ShAmt ) ; if ( ! Mask . isSignedIntN ( <NUM_LIT> ) ) break ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , DL , VT ) ) ; } break ; case <STR_LIT> : if ( ! hasNonFlagsUse ( Op ) ) { SDValue Op0 = ArithOp -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = ArithOp -> getOperand ( <NUM_LIT> ) ; EVT VT = ArithOp . getValueType ( ) ; bool IsAndn = isBitwiseNot ( Op0 ) || isBitwiseNot ( Op1 ) ; bool IsLegalAndnType = VT == <STR_LIT> || VT == <STR_LIT> ; if ( ! IsAndn || ! IsLegalAndnType ) break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( const auto * U : Op . getNode ( ) -> uses ( ) ) if ( U -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( NeedTruncation ) { EVT VT = Op . getValueType ( ) ; SDValue WideVal = Op -> getOperand ( <NUM_LIT> ) ; EVT WideVT = WideVal . getValueType ( ) ; unsigned ConvertedOp = <NUM_LIT> ; switch ( WideVal . getOpcode ( ) ) { default : break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ;


<s> for ( unsigned I = <NUM_LIT> , E = BVN -> getNumOperands ( ) ; I != E ; ++ I ) { SDValue Op = BVN -> getOperand ( I ) ; if ( ! Op . isUndef ( ) ) { uint64_t Value ; if ( Op . getOpcode ( ) == <STR_LIT> ) Value = cast < ConstantSDNode > ( Op ) -> getZExtValue ( ) ; else if ( Op . getOpcode ( ) == <STR_LIT> ) Value = ( cast < ConstantFPSDNode > ( Op ) -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ) ; else return false ; for ( unsigned J = <NUM_LIT> ; J < BytesPerElement ; ++ J ) { uint64_t Byte = ( Value >> ( J * <NUM_LIT> ) ) & <NUM_LIT> ; if ( Byte == <NUM_LIT> ) Mask |= <NUM_LIT> << ( ( E - I - <NUM_LIT> ) * BytesPerElement + J ) ; else if ( Byte != <NUM_LIT> ) return false ;


<s> if ( ! ETy . isSimple ( ) ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ; static const CostTblEntry AVX2InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; static const CostTblEntry AVX2InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( Opcode == Instruction :: Load ) { if ( const auto * Entry = CostTableLookup ( AVX2InterleavedLoadTbl , Factor , ETy . getSimpleVT ( ) ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; } else { assert ( Opcode == Instruction :: Store && <STR_LIT> ) ;

if ( const auto * Entry = CostTableLookup ( AVX2InterleavedStoreTbl , Factor , ETy . getSimpleVT ( ) ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ;


<s> addr2 = XEXP ( mem2 , <NUM_LIT> ) ; if ( GET_CODE ( addr1 ) == PLUS ) { if ( ! REG_P ( XEXP ( addr1 , <NUM_LIT> ) ) ) return <NUM_LIT> ; else { reg1 = REGNO ( XEXP ( addr1 , <NUM_LIT> ) ) ; if ( ! CONST_INT_P ( XEXP ( addr1 , <NUM_LIT> ) ) ) return <NUM_LIT> ; offset1 = INTVAL ( XEXP ( addr1 , <NUM_LIT> ) ) ; } } else if ( ! REG_P ( addr1 ) ) return <NUM_LIT> ; else { reg1 = REGNO ( addr1 ) ; offset1 = <NUM_LIT> ; } if ( GET_CODE ( addr2 ) == PLUS ) { if ( ! REG_P ( XEXP ( addr2 , <NUM_LIT> ) ) ) return <NUM_LIT> ; else { reg2 = REGNO ( XEXP ( addr2 , <NUM_LIT> ) ) ; if ( ! CONST_INT_P ( XEXP ( addr2 , <NUM_LIT> ) ) ) return <NUM_LIT> ; offset2 = INTVAL ( XEXP ( addr2 , <NUM_LIT> ) ) ; } } else if ( ! REG_P ( addr2 ) ) return <NUM_LIT> ; else { reg2 = REGNO ( addr2 ) ;


<s> if ( AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base . Reg . getNode ( ) == <NUM_LIT> ) { AM . Base . Reg = AM . IndexReg ; AM . Scale = <NUM_LIT> ; } if ( TM . getCodeModel ( ) == CodeModel :: Small && Subtarget -> is64Bit ( ) && AM . Scale == <NUM_LIT> && AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && AM . Base . Reg . getNode ( ) == <NUM_LIT> && AM . IndexReg . getNode ( ) == <NUM_LIT> && AM . SymbolFlags == <STR_LIT> && AM . hasSymbolicDisplacement ( ) ) AM . Base . Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ;


<s> case <NUM_LIT> : { uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; for ( int ByteNum = <NUM_LIT> ; ByteNum < <NUM_LIT> ; ++ ByteNum ) { if ( ( ( SplatBits | SplatUndef ) & BitMask ) == BitMask ) Val |= BitMask ; else if ( ( SplatBits & BitMask ) != <NUM_LIT> ) return SDValue ( ) ; BitMask <<= <NUM_LIT> ; } return DAG . getTargetConstant ( Val , <STR_LIT> ) ; } default : llvm_unreachable ( <STR_LIT> ) ; break ; } return SDValue ( ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) {


<s> } switch ( RegNo ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! isGFX9 ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! isCI ( ) && ! is<ISA_LIT> ( ) && hasXNACK ( ) ; default : break ; } if ( isInlineValue ( RegNo ) ) return ! isCI ( ) && ! is<ISA_LIT> ( ) && ! isVI ( ) ; if ( isCI ( ) ) return true ; if ( is<ISA_LIT> ( ) ) { switch ( RegNo ) {


<s> auto & MF = State . getMachineFunction ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; ValVT = <STR_LIT> ; if ( ArgFlags . isSExt ( ) ) LocInfo = CCValAssign :: SExt ; else if ( ArgFlags . isZExt ( ) ) LocInfo = CCValAssign :: ZExt ; else LocInfo = CCValAssign :: AExt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ; LocInfo = CCValAssign :: BCvt ; } else if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { LocVT = <STR_LIT> ;


<s> static DecodeStatus DecodeSImm ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) {

Inst . addOperand ( MCOperand :: createImm ( ( ( int64_t ) Imm << ( <NUM_LIT> - sz ) ) >> ( <NUM_LIT> - sz ) ) ) ;


<s> for ( MachineBasicBlock * S : MBB -> successors ( ) ) if ( S != Succ ) return S ;


<s> rtx not_result = gen_reg_rtx ( CCEQmode ) ; rtx not_op , rev_cond_rtx ; machine_mode cc_mode ; cc_mode = GET_MODE ( XEXP ( condition_rtx , <NUM_LIT> ) ) ; rev_cond_rtx = gen_rtx_fmt_ee ( rs6000_reverse_condition ( cc_mode , cond_code ) , SImode , XEXP ( condition_rtx , <NUM_LIT> ) , const0_rtx ) ; not_op = gen_rtx_COMPARE ( CCEQmode , rev_cond_rtx , const0_rtx ) ; emit_insn ( gen_rtx_SET ( not_result , not_op ) ) ; condition_rtx = gen_rtx_EQ ( VOIDmode , not_result , const0_rtx ) ; } op_mode = GET_MODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( op_mode == VOIDmode ) op_mode = GET_MODE ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) ) ; if ( TARGET_POWERPC64 && ( op_mode == DImode || FLOAT_MODE_P ( mode ) ) ) { PUT_MODE ( condition_rtx , DImode ) ; convert_move ( result , condition_rtx , <NUM_LIT> ) ; } else { PUT_MODE ( condition_rtx , SImode ) ; emit_insn ( gen_rtx_SET ( result , condition_rtx ) ) ;


<s> if ( SrcReg == <STR_LIT> ) { Warning ( IDLoc , <STR_LIT> ) ; if ( loadImmediate ( <NUM_LIT> , DstReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ; return false ; } unsigned Opc ; if ( ImmValue > - <NUM_LIT> && ImmValue < <NUM_LIT> ) { ImmValue = - ImmValue ; Opc = isGP64bit ( ) ? <STR_LIT> : <STR_LIT> ; } else { Opc = <STR_LIT> ; } if ( isUInt < <NUM_LIT> > ( ImmValue ) ) { TOut . emitRRI ( Opc , DstReg , SrcReg , ImmValue , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , DstReg , <STR_LIT> , DstReg , IDLoc , STI ) ; return false ; } unsigned ATReg = getATReg ( IDLoc ) ;


<s> SDValue <STR_LIT> ( SDNode * N , SelectionDAG & DAG , MVT ValueType ) { if ( ConstantSDNode * CN = getVecImm ( N ) ) { int Value = ( int ) CN -> getZExtValue ( ) ; if ( ValueType == <STR_LIT> && Value <= <NUM_LIT> && ( ( short ) Value >> <NUM_LIT> ) == ( ( short ) Value & <NUM_LIT> ) ) return DAG . getTargetConstant ( Value & <NUM_LIT> , ValueType ) ; else if ( ValueType == <STR_LIT> && ( Value & <NUM_LIT> ) == Value ) return DAG . getTargetConstant ( Value , ValueType ) ; }


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { llvm_unreachable ( <STR_LIT> ) ;


<s> <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & FrameInfo = MF -> getFrameInfo ( ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; unsigned Size = FrameInfo . getObjectSize ( FrameIndex ) ; unsigned Align = FrameInfo . getObjectAlignment ( FrameIndex ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , Size , Align ) ; unsigned SpillSize = TRI -> getSpillSize ( * RC ) ; if ( RI . isSGPRClass ( RC ) ) { MFI -> setHasSpilledSGPRs ( ) ; const MCInstrDesc & OpDesc = get ( getSGPRSpillSaveOpcode ( SpillSize ) ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SrcReg ) && SpillSize == <NUM_LIT> ) { MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MRI . constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder Spill = BuildMI ( MBB , MI , DL , OpDesc ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) . addReg ( MFI -> getScratchRSrcReg ( ) , RegState :: Implicit ) . addReg ( MFI -> getFrameOffsetReg ( ) , RegState :: Implicit ) ; if ( ST . hasScalarStores ( ) ) { Spill . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( VectorList . RegNum ) ) ; Inst . addOperand ( MCOperand :: createImm ( VectorList . LaneIndex ) ) ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;


<s> SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , VT ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , Neg , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , SDValue ( Cmp . getNode ( ) , <NUM_LIT> ) ) ; } return SDValue ( ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>Subtarget & st ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , Subtarget ( st ) {


<s> return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( insn_entry [ i ] . is_store ) { if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) != UNSPEC && GET_CODE ( SET_SRC ( body ) ) != VEC_SELECT ) { rtx lhs = SET_DEST ( body ) ; if ( ! MEM_P ( lhs ) ) return <NUM_LIT> ; if ( GET_CODE ( XEXP ( lhs , <NUM_LIT> ) ) == AND ) return <NUM_LIT> ; * special = SH_NOSWAP_ST ; return <NUM_LIT> ; } else return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == UNSPEC && XINT ( SET_SRC ( body ) , <NUM_LIT> ) == UNSPEC_VSX_CVDPSPN ) { df_ref def ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; FOR_EACH_INSN_INFO_DEF ( def , insn_info ) { struct df_link * link = DF_REF_CHAIN ( def ) ; if ( ! link ) return <NUM_LIT> ; for ( ; link ; link = link -> next ) { rtx use_insn = DF_REF_INSN ( link -> ref ) ; rtx use_body = PATTERN ( use_insn ) ; if ( GET_CODE ( use_body ) != SET || GET_CODE ( SET_SRC ( use_body ) ) != UNSPEC || XINT ( SET_SRC ( use_body ) , <NUM_LIT> ) != UNSPEC_VSX_XXSPLTW || XVECEXP ( SET_SRC ( use_body ) , <NUM_LIT> , <NUM_LIT> ) != const0_rtx ) return <NUM_LIT> ; } } return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == VEC_CONCAT && ( GET_MODE ( SET_SRC ( body ) ) == V2DFmode || GET_MODE ( SET_SRC ( body ) ) == V2DImode ) ) { * special = SH_CONCAT ; return <NUM_LIT> ; } if ( GET_CODE ( body ) == PARALLEL ) { rtx expr = XVECEXP ( body , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( expr ) == SET && v2df_reduction_p ( SET_SRC ( expr ) ) ) return <NUM_LIT> ; } if ( GET_CODE ( body ) == SET && GET_CODE ( SET_SRC ( body ) ) == UNSPEC && XINT ( SET_SRC ( body ) , <NUM_LIT> ) == UNSPEC_VPERM && XVECLEN ( SET_SRC ( body ) , <NUM_LIT> ) == <NUM_LIT> && REG_P ( XVECEXP ( SET_SRC ( body ) , <NUM_LIT> , <NUM_LIT> ) ) ) { rtx mask_reg = XVECEXP ( SET_SRC ( body ) , <NUM_LIT> , <NUM_LIT> ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) if ( rtx_equal_p ( DF_REF_REG ( use ) , mask_reg ) ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ;

if ( def_link && ! def_link -> next && const_load_sequence_p ( insn_entry , DF_REF_INSN ( def_link -> ref ) ) ) {


<s> Stream << TargetTriple . getArchName ( ) << '-' << TargetTriple . getVendorName ( ) << '-' << TargetTriple . getOSName ( ) << '-' << TargetTriple . getEnvironmentName ( ) << '-' << <STR_LIT> << Version . Major << Version . Minor << Version . Stepping ;

if ( hasXNACK ( * STI ) ) Stream << <STR_LIT> ;


<s> StringRef getPassName ( ) const override {


<s> return MatchOperand_NoMatch ; case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Dot : { const MCExpr * EVal ; if ( ! getParser ( ) . parseExpression ( EVal , E ) ) Offset = <STR_LIT> ( EVal , S , E ) ; else return MatchOperand_NoMatch ; break ; } case AsmToken :: Identifier : { StringRef Identifier ; if ( ! getParser ( ) . parseIdentifier ( Identifier ) ) { E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * EVal = parseIdentifier ( Identifier ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Offset = <STR_LIT> ( EVal , S , E ) ; } break ; } case AsmToken :: LParen : Offset = <STR_LIT> ( MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , S , E ) ; break ; } switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_ParseFail ; case AsmToken :: EndOfStatement : Operands . push_back ( <STR_LIT> ( MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , std :: move ( Offset ) ) ) ; return MatchOperand_Success ; case AsmToken :: LParen : Parser . Lex ( ) ; break ; } const MCExpr * IndexValue = nullptr ; unsigned IndexReg = <NUM_LIT> ; switch ( getLexer ( ) . getKind ( ) ) { default : if ( ParseRegister ( IndexReg , S , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: Dot : if ( getParser ( ) . parseExpression ( IndexValue , E ) ) return MatchOperand_ParseFail ; break ; case AsmToken :: Comma :

IndexValue = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ;


<s> <ISA_LIT>CommonGEP ( ) : FunctionPass ( ID ) {

initialize<ISA_LIT>CommonGEPPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ! Subtarget . useMovt ( MF ) ) { if ( RM == Reloc :: PIC_ ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ; else expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ; return ; } if ( RM != Reloc :: PIC_ ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ; return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( ! Subtarget . GVIsIndirectSymbol ( GV , RM ) ) { expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> , RM ) ; return ; } MachineBasicBlock & MBB = * MI -> getParent ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned Reg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstrBuilder MIB ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; MIB = BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; MIB . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; AddDefaultPred ( MIB ) ;


<s> unsigned MB = <NUM_LIT> - countTrailingOnes ( Imm64 ) ; unsigned SH = <NUM_LIT> ; unsigned Imm ; SDValue Val = N -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( Val . getOpcode ( ) == <STR_LIT> ) { auto Op0 = Val . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && isInt32Immediate ( Op0 . getOperand ( <NUM_LIT> ) . getNode ( ) , Imm ) && Imm <= MB ) { auto ResultType = Val . getNode ( ) -> getValueType ( <NUM_LIT> ) ; auto ImDef = CurDAG -> getMachineNode ( <STR_LIT> , dl , ResultType ) ; SDValue IDVal ( ImDef , <NUM_LIT> ) ; Val = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , ResultType , IDVal , Op0 . getOperand ( <NUM_LIT> ) , getI32Imm ( <NUM_LIT> , dl ) ) , <NUM_LIT> ) ; SH = <NUM_LIT> - Imm ; } } if ( Val . getOpcode ( ) == <STR_LIT> && isInt32Immediate ( Val . getOperand ( <NUM_LIT> ) . getNode ( ) , Imm ) && Imm <= MB ) { assert ( Imm < <NUM_LIT> && <STR_LIT> ) ; Val = Val . getOperand ( <NUM_LIT> ) ; SH = <NUM_LIT> - Imm ; } SDValue Ops [ ] = { Val , getI32Imm ( SH , dl ) , getI32Imm ( MB , dl ) } ; CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , Ops ) ;


<s> return ( Subtarget . hasDQI ( ) && ( SizeInBits == <NUM_LIT> || SizeInBits == <NUM_LIT> ) ) || ( Subtarget . hasBWI ( ) && ( SizeInBits == <NUM_LIT> || SizeInBits == <NUM_LIT> ) ) ; } ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; MVT Op0VT = Op0 . getValueType ( ) . getSimpleVT ( ) ; if ( Op0VT . isVector ( ) && Op0VT . getVectorElementType ( ) == <STR_LIT> && hasKTEST ( Op0VT ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op0VT , Op0 , Op0 ) ; }


<s> default : llvm_unreachable ( <STR_LIT> ) ; \ VPTESTM_CASE ( v4i32 , DZ128 ## SUFFIX ) \ VPTESTM_CASE ( v2i64 , QZ128 ## SUFFIX ) \ VPTESTM_CASE ( v8i32 , DZ256 ## SUFFIX ) \ VPTESTM_CASE ( v4i64 , QZ256 ## SUFFIX ) \ VPTESTM_CASE ( v16i32 , DZ ## SUFFIX ) \ VPTESTM_CASE ( v8i64 , QZ ## SUFFIX ) VPTESTM_BROADCAST_CASES ( SUFFIX ) \ VPTESTM_CASE ( v16i8 , BZ128 ## SUFFIX ) \ VPTESTM_CASE ( v8i16 , WZ128 ## SUFFIX ) \ VPTESTM_CASE ( v32i8 , BZ256 ## SUFFIX ) \ VPTESTM_CASE ( v16i16 , WZ256 ## SUFFIX ) \ VPTESTM_CASE ( v64i8 , BZ ## SUFFIX ) \ VPTESTM_CASE ( v32i16 , WZ ## SUFFIX ) if ( FoldedLoad ) { switch ( TestVT . SimpleTy ) {


<s> void applyFixup ( const MCFixup & Fixup , char * Data , unsigned DataSize , uint64_t Value ) const override { unsigned Size = <NUM_LIT> << getFixupKindLog2Size ( Fixup . getKind ( ) ) ;

assert ( Fixup . getOffset ( ) + Size <= DataSize && <STR_LIT> ) ;


<s> enum machine_mode mode ; tree type = TREE_TYPE ( field ) ; if ( TARGET_64BIT || TARGET_ALIGN_DOUBLE ) return computed ; mode = TYPE_MODE ( TREE_CODE ( type ) == ARRAY_TYPE ? get_inner_array_type ( type ) : type ) ; if ( mode == DFmode || mode == DCmode || GET_MODE_CLASS ( mode ) == MODE_INT || GET_MODE_CLASS ( mode ) == MODE_COMPLEX_INT ) return MIN ( <NUM_LIT> , computed ) ;


<s> __builtin_ia32_pmovqb128mem_mask ( ( unsigned short * ) __P , ( __v2di ) __A , __M ) ;


<s> if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) ; assert ( MO . isExpr ( ) ) ; const MCExpr * Expr = MO . getExpr ( ) ; if ( const <ISA_LIT>MCExpr * SExpr = dyn_cast < <ISA_LIT>MCExpr > ( Expr ) ) { MCFixupKind Kind = ( MCFixupKind ) SExpr -> getFixupKind ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind ) ) ; return <NUM_LIT> ; } int64_t Res ; if ( Expr -> EvaluateAsAbsolute ( Res ) ) return Res ; assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getFGR64Reg ( ) ) ) ;


<s> return isSImmScaled < Width , <NUM_LIT> > ( ) ;


<s> Op = MI -> getOperand ( Operand + <NUM_LIT> ) ; if ( Op . isImm ( ) ) AM . IndexReg = Op . getImm ( ) ; Op = MI -> getOperand ( Operand + <NUM_LIT> ) ; if ( Op . isGlobal ( ) ) { AM . GV = Op . getGlobal ( ) ; } else { AM . Disp = Op . getImm ( ) ;


<s> <ISA_LIT>TargetLowering :: <STR_LIT> <ISA_LIT>TargetLowering :: getSpecialCallingConv ( SDValue Callee ) const { <STR_LIT> SpecialCallingConv = <STR_LIT> ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseSysReg ( OperandVector & Operands ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ;


<s> MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ;

CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Result ) , { MemOp } ) ;


<s> else { assert ( ! MFI -> getPristineRegs ( MF ) . test ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ; } } else if ( NumBytes && ! tryFoldSPUpdateIntoPushPop ( STI , MF , & * MBBI , NumBytes ) ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; if ( AFI -> getDPRCalleeSavedAreaSize ( ) ) { MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; }

if ( AFI -> getDPRCalleeSavedGapSize ( ) ) {


<s> static void addAsmInstr ( MachineBasicBlock * MBB , unsigned Reg , MachineBasicBlock :: instr_iterator I , const DebugLoc & DL , const <ISA_LIT>InstrInfo * QII , MachineFunction & Fn ) { std :: string VDescStr = <STR_LIT> + getStringReg ( Reg ) ; const char * cstr = Fn . createExternalSymbolName ( VDescStr ) ; unsigned ExtraInfo = InlineAsm :: Extra_HasSideEffects ;

BuildMI ( * MBB , I , DL , QII -> get ( TargetOpcode :: INLINEASM ) ) . addExternalSymbol ( cstr ) . addImm ( ExtraInfo ) ;


<s> tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned fcode = ( unsigned ) DECL_FUNCTION_CODE ( fndecl ) ; unsigned i ; struct builtin_description * d ; if ( fcode < FRV_BUILTIN_FIRST_NONMEDIA && ! TARGET_MEDIA ) { error ( <STR_LIT> ) ; return NULL_RTX ; } switch ( fcode ) { case FRV_BUILTIN_MCOP1 : case FRV_BUILTIN_MCOP2 : case FRV_BUILTIN_MDUNPACKH : case FRV_BUILTIN_MBTOHE : if ( ! TARGET_MEDIA_REV1 ) { error ( <STR_LIT> ) ; return NULL_RTX ; } break ; case FRV_BUILTIN_MQXMACHS : case FRV_BUILTIN_MQXMACXHS : case FRV_BUILTIN_MQMACXHS : case FRV_BUILTIN_MADDACCS : case FRV_BUILTIN_MSUBACCS : case FRV_BUILTIN_MASACCS : case FRV_BUILTIN_MDADDACCS : case FRV_BUILTIN_MDSUBACCS : case FRV_BUILTIN_MDASACCS : case FRV_BUILTIN_MABSHS : case FRV_BUILTIN_MDROTLI : case FRV_BUILTIN_MCPLHI : case FRV_BUILTIN_MCPLI : case FRV_BUILTIN_MDCUTSSI : case FRV_BUILTIN_MQSATHS : case FRV_BUILTIN_MHSETLOS : case FRV_BUILTIN_MHSETLOH : case FRV_BUILTIN_MHSETHIS : case FRV_BUILTIN_MHSETHIH : case FRV_BUILTIN_MHDSETS : case FRV_BUILTIN_MHDSETH : if ( ! TARGET_MEDIA_REV2 ) { error ( <STR_LIT> <STR_LIT> ) ; return NULL_RTX ; } break ; case FRV_BUILTIN_SMASS : case FRV_BUILTIN_SMSSS : case FRV_BUILTIN_SMU : case FRV_BUILTIN_ADDSS : case FRV_BUILTIN_SUBSS : case FRV_BUILTIN_SLASS : case FRV_BUILTIN_SCUTSS : case FRV_BUILTIN_IACCreadll : case FRV_BUILTIN_IACCreadl : case FRV_BUILTIN_IACCsetll : case FRV_BUILTIN_IACCsetl : if ( ! TARGET_FR405_BUILTINS ) { error ( <STR_LIT> <STR_LIT> ) ; return NULL_RTX ; } break ; case FRV_BUILTIN_PREFETCH : if ( ! TARGET_FR500_FR550_BUILTINS ) { error ( <STR_LIT> <STR_LIT> ) ; return NULL_RTX ; } break ; case FRV_BUILTIN_MQLCLRHS : case FRV_BUILTIN_MQLMTHS : case FRV_BUILTIN_MQSLLHI : case FRV_BUILTIN_MQSRAHI : if ( ! TARGET_MEDIA_FR450 ) { error ( <STR_LIT> ) ; return NULL_RTX ; } break ; default : break ; } switch ( fcode ) { case FRV_BUILTIN_MTRAP : return frv_expand_noargs_builtin ( CODE_FOR_mtrap ) ; case FRV_BUILTIN_MCLRACC : return frv_expand_mclracc_builtin ( exp ) ; case FRV_BUILTIN_MCLRACCA : if ( TARGET_ACC_8 ) return frv_expand_noargs_builtin ( CODE_FOR_mclracca8 ) ; else return frv_expand_noargs_builtin ( CODE_FOR_mclracca4 ) ; case FRV_BUILTIN_MRDACC : return frv_expand_mrdacc_builtin ( CODE_FOR_mrdacc , exp ) ; case FRV_BUILTIN_MRDACCG : return frv_expand_mrdacc_builtin ( CODE_FOR_mrdaccg , exp ) ; case FRV_BUILTIN_MWTACC : return frv_expand_mwtacc_builtin ( CODE_FOR_mwtacc , exp ) ; case FRV_BUILTIN_MWTACCG : return frv_expand_mwtacc_builtin ( CODE_FOR_mwtaccg , exp ) ; case FRV_BUILTIN_MDPACKH : return frv_expand_mdpackh_builtin ( exp , target ) ; case FRV_BUILTIN_IACCreadll : { rtx src = frv_read_iacc_argument ( DImode , exp , <NUM_LIT> ) ; if ( target == <NUM_LIT> || ! REG_P ( target ) ) target = gen_reg_rtx ( DImode ) ; frv_split_iacc_move ( target , src ) ; return target ; } case FRV_BUILTIN_IACCreadl : return frv_read_iacc_argument ( SImode , exp , <NUM_LIT> ) ; case FRV_BUILTIN_IACCsetll : {

rtx dest = frv_read_iacc_argument ( DImode , exp , <NUM_LIT> ) ;


<s> i != NumOps ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isImplicit ( ) ) continue ; RegList . push_back ( MO . getReg ( ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } OutStreamer . EmitRegSave ( RegList , Opc == <STR_LIT> ) ; } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : { unsigned CPI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; const MachineConstantPool * MCP = MF . getConstantPool ( ) ; if ( CPI >= MCP -> getConstants ( ) . size ( ) ) CPI = AFI . getOriginalCPIdx ( CPI ) ; assert ( CPI != - <NUM_LIT> && <STR_LIT> ) ; const MachineConstantPoolEntry & CPE = MCP -> getConstants ( ) [ CPI ] ; assert ( ! CPE . isMachineConstantPoolEntry ( ) && <STR_LIT> ) ; Offset = - cast < ConstantInt > ( CPE . Val . ConstVal ) -> getSExtValue ( ) ; break ;


<s> <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; assert ( Inst . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Inst . getOperand ( <NUM_LIT> ) . isReg ( ) && Inst . getOperand ( <NUM_LIT> ) . isImm ( ) && <STR_LIT> ) ; unsigned FirstReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t ImmOp64 = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; ImmOp64 = convertIntToDoubleImm ( ImmOp64 ) ; uint32_t ImmOp32 = covertDoubleImmToSingleImm ( ImmOp64 ) ; unsigned TmpReg = <STR_LIT> ; if ( ImmOp32 != <NUM_LIT> ) { TmpReg = getATReg ( IDLoc ) ; if ( ! TmpReg ) return true ; } if ( Lo_32 ( ImmOp64 ) == <NUM_LIT> ) {

if ( TmpReg != <STR_LIT> && loadImmediate ( ImmOp32 , TmpReg , <STR_LIT> , true , false , IDLoc , Out , STI ) ) return true ;


<s> return ( __m128i ) __builtin_ia32_vpcomlew ( ( __v8hi ) __A , ( __v8hi ) __B ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( Op . dump ( ) ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerPOT ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerSPONENTRY ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerADDROFRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerShiftRightParts ( Op , DAG ) ; case <STR_LIT> : return LowerCTPOP ( Op , DAG ) ; case <STR_LIT> : return LowerFCOPYSIGN ( Op , DAG ) ; case <STR_LIT> : return LowerVectorAND ( Op , DAG ) ;


<s> return new <ISA_LIT>PassConfig ( this , PM ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & DL , SelectionDAG & DAG ) const { const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; analyzeOutputArgs ( DAG . getMachineFunction ( ) , CCInfo , Outs , true , nullptr ) ; if ( CallConv == CallingConv :: GHC && ! RVLocs . empty ( ) ) report_fatal_error ( <STR_LIT> ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ;

SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ;


<s> Vec = extract128BitVector ( Vec , IdxVal , DAG , dl ) ; MVT EltVT = VecVT . getVectorElementType ( ) ; unsigned ElemsPerChunk = <NUM_LIT> / EltVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ElemsPerChunk - <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Vec , DAG . getIntPtrConstant ( IdxVal , dl ) ) ; } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( VT == <STR_LIT> ) { if ( IdxVal == <NUM_LIT> && ! MayFoldIntoZeroExtend ( Op ) && ! ( Subtarget . hasSSE41 ( ) && MayFoldIntoStore ( Op ) ) ) { if ( Subtarget . hasFP16 ( ) ) return Op ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Idx ) ) ; } SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , DAG . getTargetConstant ( IdxVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Extract ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Op -> isOnlyUserOf ( Vec . getNode ( ) ) ) { int DWordIdx = IdxVal / <NUM_LIT> ; if ( DWordIdx == <NUM_LIT> ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( DWordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } int WordIdx = IdxVal / <NUM_LIT> ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( WordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } if ( VT == <STR_LIT> || VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; SmallVector < int , <NUM_LIT> > Mask ( VecVT . getVectorNumElements ( ) , - <NUM_LIT> ) ;

Mask [ <NUM_LIT> ] = static_cast < int > ( IdxVal ) ;


<s> } else cur_seq = <NUM_LIT> ; } } if ( ! frame_pointer_needed ) { if ( regs_ever_live [ REG_Y ] ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = <NUM_LIT> ; if ( regs_ever_live [ REG_Y + <NUM_LIT> ] ) { ++ live_seq ; ++ cur_seq ; } else cur_seq = <NUM_LIT> ; } else { cur_seq += <NUM_LIT> ; live_seq += <NUM_LIT> ; }


<s> if ( ! REG_P ( operands [ <NUM_LIT> ] ) || ! REG_P ( operands [ <NUM_LIT> ] ) ) return false ; regno0 = true_regnum ( operands [ <NUM_LIT> ] ) ; regno1 = true_regnum ( operands [ <NUM_LIT> ] ) ;

return ix86_lea_outperforms ( insn , regno0 , regno1 , INVALID_REGNUM , <NUM_LIT> , false ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalTLSAddressWindows ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue CurrentTEB = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ;

TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ;


<s> __builtin_neon_vst1v8qi ( ( __builtin_neon_qi * ) __a , ( int8x8_t ) __b ) ;


<s> MachineInstr * CommutedMI = TII -> commuteInstruction ( * MI , false , CommOpIdx1 , CommOpIdx2 ) ; if ( ! CommutedMI ) return false ; } if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg0 ) ) return false ; if ( Entry . Imm2Limit ) { unsigned Imm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Limit = ( <NUM_LIT> << Entry . Imm2Limit ) - <NUM_LIT> ; if ( Imm > Limit ) return false ; } else { unsigned Reg2 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Entry . LowRegs2 && ! is<ISA_LIT>LowRegister ( Reg2 ) ) return false ; } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc2 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ;

HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ;


<s> CopyPropagation ( const <ISA_LIT>RegisterInfo & hri , MachineRegisterInfo & mri ) : Transformation ( false ) , HRI ( hri ) , MRI ( mri ) {


<s> void <ISA_LIT>AsmPrinter :: EmitToStreamer ( MCStreamer & S , const MCInst & Inst ) { MCInst CInst ;

bool Res = compressInst ( CInst , Inst , * Subtarget , OutStreamer -> getContext ( ) ) ;


<s> SDValue Ptr = N -> getBasePtr ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc SL ( N ) ; unsigned AS = N -> getAddressSpace ( ) ; if ( Ptr . getOpcode ( ) == <STR_LIT> && AS != <ISA_LIT>AS :: PRIVATE_ADDRESS ) { SDValue NewPtr = performSHLPtrCombine ( Ptr . getNode ( ) , AS , DCI ) ; if ( NewPtr ) { SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ] = NewPtr ; return SDValue ( DAG . UpdateNodeOperands ( N , NewOps ) , <NUM_LIT> ) ; }


<s> assemble_integer ( GEN_INT ( bits ) , <NUM_LIT> , BITS_PER_WORD , <NUM_LIT> ) ;

if ( ! WORDS_BIG_ENDIAN ) assemble_zeros ( <NUM_LIT> ) ;


<s> static bool crx_fixed_condition_code_regs ( unsigned int * p1 , unsigned int * p2 ) { * p1 = CC_REGNUM ; * p2 = INVALID_REGNUM ; return true ;


<s> unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI . definesRegister ( DstRegD , TRI ) || MI . readsRegister ( DstRegD , TRI ) ) return false ; if ( MI . getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI . findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI . RemoveOperand ( ImpDefIdx ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; MIB . add ( predOps ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; MIB . addReg ( SrcRegS , RegState :: Implicit ) ; if ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) { MI . getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; MI . addRegisterKilled ( SrcRegS , TRI , true ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; return true ;


<s> memset ( & emitted_frame_related_regs , <NUM_LIT> , sizeof ( emitted_frame_related_regs ) ) ;


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( ( MI . getOpcode ( ) == <STR_LIT> ) ? ( MCFixupKind ) <STR_LIT> : ( MCFixupKind ) <STR_LIT> ) ) ) ;


<s> auto & SymA = cast < MCSymbolWasm > ( RefA -> getSymbol ( ) ) ; MCSymbolRefExpr :: VariantKind Modifier = Target . getAccessVariant ( ) ; switch ( Modifier ) { case MCSymbolRefExpr :: VK_GOT : return <STR_LIT> ; case MCSymbolRefExpr :: VK_WASM_TBREL : assert ( SymA . isFunction ( ) ) ; return is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; case MCSymbolRefExpr :: VK_WASM_TLSREL : return <STR_LIT> ; case MCSymbolRefExpr :: VK_WASM_MBREL : assert ( SymA . isData ( ) ) ; return is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; case MCSymbolRefExpr :: VK_WASM_TYPEINDEX : return <STR_LIT> ; default : break ; } switch ( unsigned ( Fixup . getKind ( ) ) ) { case <STR_LIT> : if ( SymA . isFunction ( ) ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( SymA . isFunction ( ) ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> : if ( SymA . isGlobal ( ) ) return <STR_LIT> ; if ( SymA . isFunction ( ) ) return <STR_LIT> ; if ( SymA . isEvent ( ) ) return <STR_LIT> ; if ( SymA . isTable ( ) ) return <STR_LIT> ; return <STR_LIT> ; case <STR_LIT> :


<s> VectorType * VT0 = dyn_cast < VectorType > ( Ty0 ) ; VectorType * VT1 = dyn_cast < VectorType > ( Ty1 ) ; if ( ! VT0 || ! VT1 ) return false ; if ( VT0 -> getNumElements ( ) != <NUM_LIT> || VT1 -> getNumElements ( ) != <NUM_LIT> ) return false ;

return DL -> getTypeSizeInBits ( VT0 -> getElementType ( ) ) == DL -> getTypeSizeInBits ( VT1 -> getElementType ( ) ) ;


<s> virtual raw_ostream & GetCommentOS ( ) { if ( ! IsVerboseAsm ) return nulls ( ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>BranchCoalescingPass ( ) { return new <ISA_LIT>BranchCoalescing ( ) ;


<s> return ( __m64 ) __builtin_ia32_psrlq ( ( __v1di ) __m , ( __v1di ) __count ) ;


const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> EmitMappingSymbol ( <STR_LIT> ) ; LastEMS = EMS_A64 ;


<s> return parseOptionalOps ( DSOptionalOps , Operands ) ;


<s> if ( ST -> getNumElements ( ) != NumElts ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { if ( Inst -> getArgOperand ( i ) -> getType ( ) != ST -> getElementType ( i ) ) return nullptr ; } Value * Res = UndefValue :: get ( ExpectedType ) ; IRBuilder < > Builder ( Inst ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { Value * L = Inst -> getArgOperand ( i ) ; Res = Builder . CreateInsertValue ( Res , L , i ) ; } return Res ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

if ( Inst -> getType ( ) == ExpectedType ) return Inst ;


<s> if ( Subtarget -> getTargetTriple ( ) . isOSMSVCRT ( ) ) return <NUM_LIT> ; if ( CC == CallingConv :: Fast || CC == CallingConv :: GHC || CC == CallingConv :: HiPE ) return <NUM_LIT> ; if ( CS ) if ( CS -> arg_empty ( ) || ! CS -> paramHasAttr ( <NUM_LIT> , Attribute :: StructRet ) || CS -> paramHasAttr ( <NUM_LIT> , Attribute :: InReg ) || Subtarget -> isTargetMCU ( ) ) return <NUM_LIT> ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ;


<s> return StringRef ( Token . Data , Token . Length ) ;