<s> if ( ! QII -> isPredicated ( * VIN ) ) continue ; SUnit * PacketSU = MIToSUnit [ * VIN ] ; if ( PacketSU -> isSucc ( PacketSUDep ) ) { for ( unsigned i = <NUM_LIT> ; i < PacketSU -> Succs . size ( ) ; ++ i ) { if ( ( PacketSU -> Succs [ i ] . getSUnit ( ) == PacketSUDep ) && ( PacketSU -> Succs [ i ] . getKind ( ) == SDep :: Anti ) && ( PacketSU -> Succs [ i ] . getReg ( ) == DepReg ) ) { return true ;


<s> const ConstantSDNode * RotConstant = dyn_cast < ConstantSDNode > ( V ) ;


<s> const char * <ISA_LIT>Subtarget :: getABIOptionString ( ) const {


<s> FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } Align RequiredAlign ( VT . getSizeInBits ( ) / <NUM_LIT> ) ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlign ( Ptr ) < RequiredAlign ) { if ( MFI . isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI . setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % RequiredAlign . value ( ) ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ int64_t ( RequiredAlign . value ( ) - <NUM_LIT> ) ; if ( StartOffset ) { SDLoc DL ( Ptr ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , DL , Ptr . getValueType ( ) ) ) ; } int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; unsigned NumElems = VT . getVectorNumElements ( ) ; EVT NVT = EVT :: getVectorVT ( * DAG . getContext ( ) , PVT , NumElems ) ; SDValue V1 = DAG . getLoad ( NVT , dl , Chain , Ptr , LD -> getPointerInfo ( ) . getWithOffset ( StartOffset ) ) ; SmallVector < int , <NUM_LIT> > Mask ( NumElems , EltNo ) ; return DAG . getVectorShuffle ( NVT , dl , V1 , DAG . getUNDEF ( NVT ) , Mask ) ;


<s> gcc_unreachable ( ) ; } } if ( GET_CODE ( x ) == SYMBOL_REF ) { if ( aarch64_tls_symbol_p ( x ) ) return aarch64_classify_tls_symbol ( x ) ; switch ( aarch64_cmodel ) { case AARCH64_CMODEL_TINY : if ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_FORCE_TO_MEM ; if ( ! ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) || offset_within_block_p ( x , offset ) ) ) return SYMBOL_FORCE_TO_MEM ; return SYMBOL_TINY_ABSOLUTE ; case AARCH64_CMODEL_SMALL : if ( SYMBOL_REF_WEAK ( x ) && ! aarch64_symbol_binds_local_p ( x ) ) return SYMBOL_FORCE_TO_MEM ; if ( ! ( IN_RANGE ( offset , - <NUM_LIT> , <NUM_LIT> ) || offset_within_block_p ( x , offset ) ) ) return SYMBOL_FORCE_TO_MEM ;


<s> if ( RegNum ) { if ( Next != StringRef :: npos ) { Kind = Name . slice ( Next , StringRef :: npos ) ; if ( ! isValidVectorKind ( Kind , MatchKind ) ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } } Parser . Lex ( ) ;


<s> static SDValue combineExtSetcc ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ! Subtarget . hasAVX512 ( ) || ! VT . isVector ( ) || N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT SVT = VT . getVectorElementType ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; if ( N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; unsigned Size = VT . getSizeInBits ( ) ; if ( Size > <NUM_LIT> && Subtarget . useAVX512Regs ( ) ) return SDValue ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( N0 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( <STR_LIT> ( CC ) ) return SDValue ( ) ; EVT N00VT = N0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT MatchingVecType = N00VT . changeVectorElementTypeToInteger ( ) ; if ( Size != MatchingVecType . getSizeInBits ( ) ) return SDValue ( ) ; SDValue Res = DAG . getSetCC ( dl , VT , N0 . getOperand ( <NUM_LIT> ) , N0 . getOperand ( <NUM_LIT> ) , CC ) ;

if ( N -> getOpcode ( ) == <STR_LIT> ) Res = DAG . getZeroExtendInReg ( Res , dl , N0 . getValueType ( ) ) ;


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , unsigned VReg ) const { if ( Val ) return false ;


<s> if ( Immed == <NUM_LIT> ) return false ; if ( N . getValueType ( ) == <STR_LIT> ) Immed = ~ ( ( uint32_t ) Immed ) + <NUM_LIT> ;


<s> BB -> setAlignment ( MaxAlign ) ; Align FuncAlign = MaxAlign ; if ( MaxAlign == <NUM_LIT> ) FuncAlign = Align ( <NUM_LIT> ) ; MF -> ensureAlignment ( FuncAlign ) ; SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > InsPoint ( MaxLogAlign + <NUM_LIT> , BB -> end ( ) ) ; const std :: vector < MachineConstantPoolEntry > & CPs = MCP -> getConstants ( ) ; const DataLayout & TD = MF -> getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = CPs . size ( ) ; i != e ; ++ i ) { unsigned Size = CPs [ i ] . getSizeInBytes ( TD ) ; Align Alignment = CPs [ i ] . getAlign ( ) ; assert ( isAligned ( Alignment , Size ) && <STR_LIT> ) ;

unsigned LogAlign = Log2 ( Alignment ) ;


<s> return has3DNow ( ) || hasPRFCHW ( ) || hasPREFETCHWT1 ( ) ;


<s> do { MCE . startFunction ( MF ) ; for ( MachineFunction :: iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) emitBasicBlock ( * I ) ; } while ( MCE . finishFunction ( MF ) ) ;


<s> createHalfInstr ( A2_and , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_and , MI , PairMap , isub_hi ) ; Split = true ; break ; case A2_orp : createHalfInstr ( A2_or , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_or , MI , PairMap , isub_hi ) ; Split = true ; break ; case A2_xorp : createHalfInstr ( A2_xor , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_xor , MI , PairMap , isub_hi ) ; Split = true ; break ; case L2_loadrd_io : case L2_loadrd_pi : case S2_storerd_io : case S2_storerd_pi : splitMemRef ( MI , PairMap ) ; Split = true ; break ; case A2_tfrpi : case CONST64 : splitImmediate ( MI , PairMap ) ; Split = true ; break ; case A2_combineii : case A4_combineir : case A4_combineii : case A4_combineri : case A2_combinew : splitCombine ( MI , PairMap ) ; Split = true ; break ; case A2_sxtw : splitExt ( MI , PairMap ) ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ;

BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( DestReg ) . addFrameIndex ( FI ) ;


<s> return new AMDGPUPeepholeOpt ( tm ) ;


<s> emit_insn ( gen_cstoresf4 ( comp_reg , operands [ <NUM_LIT> ] , cmp_op0 , cmp_op1 ) ) ;

condition = gen_rtx_NE ( SImode , comp_reg , const0_rtx ) ;


<s> return alignTo ( MFI . getStackSize ( ) + RVFI -> getRVVPadding ( ) , getStackAlign ( ) ) ;


<s> if ( rtx n = find_regno_note ( i , REG_UNUSED , regno ) ) remove_note ( i , n ) ;


<s> } else { DispVal = Op3 . getImm ( ) ; } const MachineOperand & Base = MI . getOperand ( Op ) ; const MachineOperand & Scale = MI . getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & IndexReg = MI . getOperand ( Op + <NUM_LIT> ) ; unsigned BaseReg = Base . getReg ( ) ; bool IsPCRel = MCE . earlyResolveAddresses ( ) ? true : false ; if ( ( ! Is64BitMode || DispForReloc || BaseReg != <NUM_LIT> ) && IndexReg . getReg ( ) == <NUM_LIT> && ( ( BaseReg == <NUM_LIT> && MCE . earlyResolveAddresses ( ) ) || BaseReg == <STR_LIT> || ( BaseReg != <NUM_LIT> && get<ISA_LIT>RegNum ( BaseReg ) != N86 :: ESP ) ) ) { if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , true ) ; } else { unsigned BaseRegNo = get<ISA_LIT>RegNum ( BaseReg ) ; if ( ! DispForReloc && DispVal == <NUM_LIT> && BaseRegNo != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; } else if ( ! DispForReloc && isDisp8 ( DispVal ) ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitConstant ( DispVal , <NUM_LIT> ) ; } else { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , BaseRegNo ) ) ; emitDisplacementField ( DispForReloc , DispVal , PCAdj , IsPCRel ) ; } } } else { assert ( IndexReg . getReg ( ) != <STR_LIT> && IndexReg . getReg ( ) != <STR_LIT> && <STR_LIT> ) ; bool ForceDisp32 = false ; bool ForceDisp8 = false ; if ( BaseReg == <NUM_LIT> ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp32 = true ; } else if ( DispForReloc ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp32 = true ; } else if ( DispVal == <NUM_LIT> && get<ISA_LIT>RegNum ( BaseReg ) != N86 :: EBP ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; } else if ( isDisp8 ( DispVal ) ) { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; ForceDisp8 = true ; } else { MCE . emitByte ( ModRMByte ( <NUM_LIT> , RegOpcodeField , <NUM_LIT> ) ) ; } static const unsigned SSTable [ ] = { ~ <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , ~ <NUM_LIT> , <NUM_LIT> } ; unsigned SS = SSTable [ Scale . getImm ( ) ] ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getJumpTargetOpValue ( const MCInst & Inst , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & SubtargetInfo ) const {

const MCOperand & MCOp = Inst . getOperand ( OpNo ) ;


<s> static rtx mips_force_temporary ( rtx dest , rtx value ) { if ( can_create_pseudo_p ( ) ) return force_reg ( Pmode , value ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _get_ssp ( void ) {


<s> break ; case CC_DLTmode : ne = AARCH64_LT ; eq = AARCH64_GE ; break ; case CC_DGTmode : ne = AARCH64_GT ; eq = AARCH64_LE ; break ; case CC_DLEmode : ne = AARCH64_LE ; eq = AARCH64_GT ; break ; case CC_DGEUmode : ne = AARCH64_CS ; eq = AARCH64_CC ; break ; case CC_DLTUmode : ne = AARCH64_CC ; eq = AARCH64_CS ; break ; case CC_DGTUmode : ne = AARCH64_HI ; eq = AARCH64_LS ; break ; case CC_DLEUmode : ne = AARCH64_LS ; eq = AARCH64_HI ; break ; case CCmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_GE ; case GT : return AARCH64_GT ; case LE : return AARCH64_LE ; case LT : return AARCH64_LT ; case GEU : return AARCH64_CS ; case GTU : return AARCH64_HI ; case LEU : return AARCH64_LS ; case LTU : return AARCH64_CC ; default : return - <NUM_LIT> ; } break ; case CC_SWPmode : case CC_ZESWPmode : case CC_SESWPmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_LE ; case GT : return AARCH64_LT ; case LE : return AARCH64_GE ; case LT : return AARCH64_GT ; case GEU : return AARCH64_LS ; case GTU : return AARCH64_CC ; case LEU : return AARCH64_CS ; case LTU : return AARCH64_HI ; default : return - <NUM_LIT> ; } break ; case CC_NZmode : switch ( comp_code ) { case NE : return AARCH64_NE ; case EQ : return AARCH64_EQ ; case GE : return AARCH64_PL ; case LT : return AARCH64_MI ;


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;


<s> unsigned Last = <NUM_LIT> ; for ( auto Reg : CSI ) { assert ( Reg . getReg ( ) >= <STR_LIT> && Reg . getReg ( ) <= <STR_LIT> && <STR_LIT> ) ; if ( Reg . getReg ( ) > Last ) Last = Reg . getReg ( ) ; } return Last ;


<s> return TargetTriple . isOSFuchsia ( ) ;


<s> InlineAsmIdentifierInfo & getIdentifierInfo ( ) { return Info ;


<s> bool fixupNeedsRelaxation ( const MCFixup & Fixup , uint64_t Value , const MCRelaxableFragment * DF , const MCAsmLayout & Layout ) const override { return false ;


<s> if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CPUDirectives [ Directive ] ) ) ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ;

if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) {


<s> static __inline unsigned int _MM_GET_FLUSH_ZERO_MODE ( void ) { return _mm_getcsr ( ) & _MM_FLUSH_ZERO_MASK ;


<s> unsigned VecWidth = DataType -> getPrimitiveSizeInBits ( ) ; return VecWidth == <NUM_LIT> ; } Type * ScalarTy = DataType -> getScalarType ( ) ; if ( ScalarTy -> isPointerTy ( ) ) return true ;

if ( ScalarTy -> isFloatTy ( ) || ScalarTy -> isDoubleTy ( ) ) return true ;


<s> bool Is64BitMode = TM . getSubtargetImpl ( ) -> is64Bit ( ) ; unsigned Size = GetInstSizeWithDesc ( * MI , & Desc , IsPIC , Is64BitMode ) ; if ( Desc . getOpcode ( ) == <STR_LIT> ) { Size += GetInstSizeWithDesc ( * MI , & get ( <STR_LIT> ) , IsPIC , Is64BitMode ) ; }


<s> case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandPseudoMTLoHi ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandCvtFPInt ( MBB , MI , Opc , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : Opc = isMicro<ISA_LIT> ? <STR_LIT> : <STR_LIT> ; expandCvtFPInt ( MBB , MI , Opc , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , isMicro<ISA_LIT> , false ) ; break ; case <STR_LIT> : expandBuildPairF64 ( MBB , MI , isMicro<ISA_LIT> , true ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , isMicro<ISA_LIT> , false ) ; break ; case <STR_LIT> : expandExtractElementF64 ( MBB , MI , isMicro<ISA_LIT> , true ) ; break ; case <STR_LIT> : case <STR_LIT> : expandEhReturn ( MBB , MI ) ; break ; case <STR_LIT> : BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : { auto Op = MI . getOperand ( <NUM_LIT> ) . isImm ( ) ? <STR_LIT> : <STR_LIT> ; if ( Op == <STR_LIT> ) assert ( isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; else assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) ; assert ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && <STR_LIT> ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , get ( Op ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; break ;


<s> if ( N -> getMachineOpcode ( ) != <STR_LIT> ) continue ; if ( N -> getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> || N -> getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> ) continue ; SDValue ISR = N -> getOperand ( <NUM_LIT> ) ; if ( ! ISR . isMachineOpcode ( ) || ISR . getMachineOpcode ( ) != TargetOpcode :: INSERT_SUBREG ) continue ; if ( ! ISR . hasOneUse ( ) ) continue ; if ( ISR . getConstantOperandVal ( <NUM_LIT> ) != <STR_LIT> ) continue ; SDValue IDef = ISR . getOperand ( <NUM_LIT> ) ; if ( ! IDef . isMachineOpcode ( ) || IDef . getMachineOpcode ( ) != TargetOpcode :: IMPLICIT_DEF ) continue ; SDValue Op32 = ISR -> getOperand ( <NUM_LIT> ) ; if ( ! Op32 . isMachineOpcode ( ) ) continue ; SmallPtrSet < SDNode * , <NUM_LIT> > ToPromote ; if ( ! Peephole<ISA_LIT>64ZExtGather ( Op32 , ToPromote ) ) continue ; bool OutsideUse = false ; for ( SDNode * PN : ToPromote ) { for ( SDNode * UN : PN -> uses ( ) ) { if ( ! ToPromote . count ( UN ) && UN != ISR . getNode ( ) ) { OutsideUse = true ; break ; } } if ( OutsideUse ) break ; } if ( OutsideUse ) continue ; MadeChange = true ; for ( SDNode * PN : ToPromote ) { unsigned NewOpcode ; switch ( PN -> getMachineOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ; case <STR_LIT> : NewOpcode = <STR_LIT> ; break ;


<s> for ( auto & It : * MLI ) for ( MachineLoop * ML : depth_first ( It ) ) NestedLoops . push_front ( ML ) ; if ( NestedLoops . empty ( ) ) return <NUM_LIT> ; int Num = <NUM_LIT> ; for ( MachineLoop * ExaminedLoop : NestedLoops ) { if ( ExaminedLoop -> getNumBlocks ( ) == <NUM_LIT> || Visited [ ExaminedLoop ] ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> ; ExaminedLoop -> dump ( ) ; ) ; int NumBreak = mergeLoop ( ExaminedLoop ) ; if ( NumBreak == - <NUM_LIT> ) break ; Num += NumBreak ; }


<s> case fixup_<ISA_LIT>_LD_GOT_HI16 : return ELF :: R_HEX_LD_GOT_HI16 ; case fixup_<ISA_LIT>_LD_GOT_32 : return ELF :: R_HEX_LD_GOT_32 ; case fixup_<ISA_LIT>_LD_GOT_16 : return ELF :: R_HEX_LD_GOT_16 ; case fixup_<ISA_LIT>_IE_LO16 : return ELF :: R_HEX_IE_LO16 ; case fixup_<ISA_LIT>_IE_HI16 : return ELF :: R_HEX_IE_HI16 ; case fixup_<ISA_LIT>_IE_32 : return ELF :: R_HEX_IE_32 ; case fixup_<ISA_LIT>_IE_GOT_LO16 : return ELF :: R_HEX_IE_GOT_LO16 ; case fixup_<ISA_LIT>_IE_GOT_HI16 : return ELF :: R_HEX_IE_GOT_HI16 ; case fixup_<ISA_LIT>_IE_GOT_32 : return ELF :: R_HEX_IE_GOT_32 ; case fixup_<ISA_LIT>_IE_GOT_16 : return ELF :: R_HEX_IE_GOT_16 ; case fixup_<ISA_LIT>_TPREL_LO16 : return ELF :: R_HEX_TPREL_LO16 ; case fixup_<ISA_LIT>_TPREL_HI16 : return ELF :: R_HEX_TPREL_HI16 ; case fixup_<ISA_LIT>_TPREL_32 : return ELF :: R_HEX_TPREL_32 ; case fixup_<ISA_LIT>_TPREL_16 : return ELF :: R_HEX_TPREL_16 ; case fixup_<ISA_LIT>_6_PCREL_X : return ELF :: R_HEX_6_PCREL_X ; case fixup_<ISA_LIT>_GOTREL_32_6_X : return ELF :: R_HEX_GOTREL_32_6_X ; case fixup_<ISA_LIT>_GOTREL_16_X : return ELF :: R_HEX_GOTREL_16_X ; case fixup_<ISA_LIT>_GOTREL_11_X : return ELF :: R_HEX_GOTREL_11_X ; case fixup_<ISA_LIT>_GOT_32_6_X : return ELF :: R_HEX_GOT_32_6_X ; case fixup_<ISA_LIT>_GOT_16_X : return ELF :: R_HEX_GOT_16_X ; case fixup_<ISA_LIT>_GOT_11_X : return ELF :: R_HEX_GOT_11_X ; case fixup_<ISA_LIT>_DTPREL_32_6_X : return ELF :: R_HEX_DTPREL_32_6_X ; case fixup_<ISA_LIT>_DTPREL_16_X : return ELF :: R_HEX_DTPREL_16_X ; case fixup_<ISA_LIT>_DTPREL_11_X : return ELF :: R_HEX_DTPREL_11_X ; case fixup_<ISA_LIT>_GD_GOT_32_6_X : return ELF :: R_HEX_GD_GOT_32_6_X ; case fixup_<ISA_LIT>_GD_GOT_16_X : return ELF :: R_HEX_GD_GOT_16_X ; case fixup_<ISA_LIT>_GD_GOT_11_X : return ELF :: R_HEX_GD_GOT_11_X ; case fixup_<ISA_LIT>_LD_GOT_32_6_X : return ELF :: R_HEX_LD_GOT_32_6_X ; case fixup_<ISA_LIT>_LD_GOT_16_X : return ELF :: R_HEX_LD_GOT_16_X ; case fixup_<ISA_LIT>_LD_GOT_11_X : return ELF :: R_HEX_LD_GOT_11_X ; case fixup_<ISA_LIT>_IE_32_6_X : return ELF :: R_HEX_IE_32_6_X ; case fixup_<ISA_LIT>_IE_16_X : return ELF :: R_HEX_IE_16_X ; case fixup_<ISA_LIT>_IE_GOT_32_6_X : return ELF :: R_HEX_IE_GOT_32_6_X ; case fixup_<ISA_LIT>_IE_GOT_16_X : return ELF :: R_HEX_IE_GOT_16_X ; case fixup_<ISA_LIT>_IE_GOT_11_X : return ELF :: R_HEX_IE_GOT_11_X ; case fixup_<ISA_LIT>_TPREL_32_6_X : return ELF :: R_HEX_TPREL_32_6_X ; case fixup_<ISA_LIT>_TPREL_16_X : return ELF :: R_HEX_TPREL_16_X ; case fixup_<ISA_LIT>_TPREL_11_X : return ELF :: R_HEX_TPREL_11_X ; case fixup_<ISA_LIT>_23_REG : return ELF :: R_HEX_23_REG ; case fixup_<ISA_LIT>_27_REG : return ELF :: R_HEX_27_REG ; case fixup_<ISA_LIT>_GD_PLT_B22_PCREL_X : return ELF :: R_HEX_GD_PLT_B22_PCREL_X ; case fixup_<ISA_LIT>_GD_PLT_B32_PCREL_X : return ELF :: R_HEX_GD_PLT_B32_PCREL_X ; case fixup_<ISA_LIT>_LD_PLT_B22_PCREL_X : return ELF :: R_HEX_LD_PLT_B22_PCREL_X ;


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo ;


<ISA_LIT>TargetStreamer :: emitDirectiveSetAt ( ) ;


<s> static SmallVector < CalleeSavedInfo , <NUM_LIT> > getNonLibcallCSI ( const std :: vector < CalleeSavedInfo > & CSI ) { SmallVector < CalleeSavedInfo , <NUM_LIT> > NonLibcallCSI ;

for ( auto & CS : CSI ) if ( CS . getFrameIdx ( ) >= <NUM_LIT> ) NonLibcallCSI . push_back ( CS ) ;


<s> if ( I -> isDebugInstr ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && <STR_LIT> ( * I ) == <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; }


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; Unsigned = true ; break ; case <STR_LIT> : Swap = true ; SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Unsigned = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; } if ( Swap ) std :: swap ( Op0 , Op1 ) ; if ( Opc ) return DAG . getNode ( Opc , dl , VT , Op0 , Op1 ) ;

Opc = Unsigned ? <STR_LIT> : <STR_LIT> ;


<s> if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , Glue ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> ) ; Glue = TPR . getValue ( <NUM_LIT> ) ; } else { RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , Glue ) ;

Glue = RetVal . getValue ( <NUM_LIT> ) ;


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator MI , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ; MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; auto * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; int FrameIndex = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; unsigned BasePtr = getFrameRegister ( MF ) ; int64_t Offset = ( TFI -> getFrameIndexOffset ( MF , FrameIndex ) + MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ) ; if ( MI -> isDebugValue ( ) ) {

MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ;


<s> O << <STR_LIT> ; printPredicateOperand ( MI , <NUM_LIT> ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> ) ; O << <STR_LIT> ; printSOImm ( O , V2 , VerboseAsm , MAI ) ;


<s> SDValue In2H = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Node -> getOperand ( <NUM_LIT> ) , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; SDValue Ops [ ] = { Chain , In1 , In2L , In2H } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getMemIntrinsicNode ( NewOp , dl , Tys , Ops , <NUM_LIT> , <STR_LIT> , cast < MemSDNode > ( Node ) -> getMemOperand ( ) ) ; SDValue OpsF [ ] = { Result . getValue ( <NUM_LIT> ) , Result . getValue ( <NUM_LIT> ) } ; Results . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , OpsF , <NUM_LIT> ) ) ;

Results . push_back ( Result . getValue ( <NUM_LIT> ) ) ;


<s> return ( uint16x8_t ) __builtin_neon_vcgeuv8hi ( ( int16x8_t ) __b , ( int16x8_t ) __a ) ;


<s> bool isImmCom8 ( ) const { if ( ! isImm ( ) ) return false ; const auto * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ;


<s> void <ISA_LIT>AdjustOptImpl :: adjustBasicBlock ( BasicBlock & BB ) { if ( ! Disable<ISA_LIT>serializeICMP && serializeICMPCrossBB ( BB ) ) return ;


<s> <ISA_LIT>CustomDAG ( SelectionDAG & DAG , const SDNode * WhereN ) : DAG ( DAG ) , DL ( WhereN ) {


<s> initTIs ( M , TIs ) ; return false ;


<s> const MachineOperand & Index = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) ; const MachineOperand & Offset = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) ; const MachineOperand & Segment = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) ; if ( Segment . getReg ( ) != <NUM_LIT> || ! Offset . isImm ( ) || MBB . computeRegisterLiveness ( TRI , <STR_LIT> , I , <NUM_LIT> ) != MachineBasicBlock :: LQR_Dead ) return ; const Register DstR = Dst . getReg ( ) ; const Register SrcR1 = Base . getReg ( ) ; const Register SrcR2 = Index . getReg ( ) ; if ( ( SrcR1 == <NUM_LIT> || SrcR1 != DstR ) && ( SrcR2 == <NUM_LIT> || SrcR2 != DstR ) ) return ; if ( Scale . getImm ( ) > <NUM_LIT> ) return ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ; ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; MachineInstr * NewMI = nullptr ; if ( SrcR1 != <NUM_LIT> && SrcR2 != <NUM_LIT> ) { const MCInstrDesc & ADDrr = TII -> get ( getADDrrFromLEA ( Opcode ) ) ; const MachineOperand & Src = SrcR1 == DstR ? Index : Base ; NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , ADDrr , DstR ) . addReg ( DstR ) . add ( Src ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; } if ( Offset . getImm ( ) != <NUM_LIT> ) { const MCInstrDesc & ADDri = TII -> get ( getADDriFromLEA ( Opcode , Offset ) ) ; const MachineOperand & SrcR = SrcR1 == DstR ? Base : Index ; NewMI = BuildMI ( MBB , I , MI . getDebugLoc ( ) , ADDri , DstR ) . add ( SrcR ) . addImm ( Offset . getImm ( ) ) ; LLVM_DEBUG ( NewMI -> dump ( ) ; ) ; } if ( NewMI ) { MBB . getParent ( ) -> substituteDebugValuesForInst ( * I , * NewMI , <NUM_LIT> ) ; MBB . erase ( I ) ; I = NewMI ;


<s> SDValue CmpOp0 = Op . getOperand ( <NUM_LIT> ) ; SDValue CmpOp1 = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueOp = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseOp = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; unsigned CCMask ; SDValue Flags = emitCmp ( DAG , CmpOp0 , CmpOp1 , CC , CCMask ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( TrueOp ) ; Ops . push_back ( FalseOp ) ; Ops . push_back ( DAG . getConstant ( CCMask , <STR_LIT> ) ) ; Ops . push_back ( Flags ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , VTs , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ;


<s> void LLVMInitialize<ISA_LIT>AsmLexer ( ) { RegisterAsmLexer < <ISA_LIT>AsmLexer > X ( The<ISA_LIT>Target ) ;

RegisterAsmLexer < ThumbAsmLexer > Y ( TheThumbTarget ) ;


<s> Lea . addOperand ( MCOperand :: CreateReg ( StackReg ) ) ; Lea . addOperand ( MCOperand :: CreateReg ( StackReg ) ) ; Lea . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; Lea . addOperand ( MCOperand :: CreateReg ( <STR_LIT> ) ) ; Lea . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;

Lea . addOperand ( MCOperand :: CreateReg ( <NUM_LIT> ) ) ;


<s> addr = SET_SRC ( addr ) ; } else { int i ; extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( GET_CODE ( recog_data . operand [ i ] ) == MEM ) {

addr = XEXP ( recog_data . operand [ i ] , <NUM_LIT> ) ;


<s> assert ( Kind == k_TraceSyncBarrierOpt && <STR_LIT> ) ; return TSBOpt . Val ;


<s> int i ; extract_insn_cached ( insn ) ; for ( i = recog_data . n_operands - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) if ( CONSTANT_P ( recog_data . operand [ i ] ) ) { enum attr_mode mode = get_attr_mode ( insn ) ; gcc_assert ( ! len ) ; if ( shortform && CONST_INT_P ( recog_data . operand [ i ] ) ) { HOST_WIDE_INT ival = INTVAL ( recog_data . operand [ i ] ) ; switch ( mode ) { case MODE_QI : len = <NUM_LIT> ; continue ; case MODE_HI : ival = trunc_int_for_mode ( ival , HImode ) ; break ; case MODE_SI : ival = trunc_int_for_mode ( ival , SImode ) ; break ; default : break ; } if ( IN_RANGE ( ival , - <NUM_LIT> , <NUM_LIT> ) ) {


<s> if ( RegName [ <NUM_LIT> ] == 's' ) return RegName + <NUM_LIT> ; return RegName + <NUM_LIT> ; case 'c' : if ( RegName [ <NUM_LIT> ] == 'r' ) return RegName + <NUM_LIT> ; } return RegName ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCCCCallTo ( SDValue Chain , SDValue Callee , CallingConv :: ID CallConv , bool isVarArg , bool isTailCall , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const {


<s> assert ( OpVT == <STR_LIT> || OpVT == <STR_LIT> ) ;

if ( Op . getValueType ( ) != <STR_LIT> || ( hasHardQuad && TLI . isTypeLegal ( OpVT ) ) ) return SDValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> Target & getThe<ISA_LIT>beTarget ( ) { static Target The<ISA_LIT>beTarget ; return The<ISA_LIT>beTarget ;


<s> codes [ cost ] . code = UNKNOWN ; codes [ cost ] . method = METHOD_NORMAL ; codes [ cost ] . value = low_part & ~ ( IMM_REACH - <NUM_LIT> ) ; codes [ cost ] . curr_value = codes [ cost ] . value ; cost ++ ; HOST_WIDE_INT iorv = low_part & ( IMM_REACH - <NUM_LIT> ) ; if ( iorv != <NUM_LIT> ) { codes [ cost ] . code = IOR ; codes [ cost ] . method = METHOD_NORMAL ; codes [ cost ] . value = iorv ; codes [ cost ] . curr_value = low_part ; cost ++ ; } } if ( TARGET_64BIT ) { bool lu32i [ <NUM_LIT> ] = { ( value & LU32I_B ) == <NUM_LIT> , ( value & LU32I_B ) == LU32I_B } ; bool lu52i [ <NUM_LIT> ] = { ( value & LU52I_B ) == <NUM_LIT> , ( value & LU52I_B ) == LU52I_B } ; int sign31 = ( value & ( HOST_WIDE_INT_1U << <NUM_LIT> ) ) >> <NUM_LIT> ; int sign51 = ( value & ( HOST_WIDE_INT_1U << <NUM_LIT> ) ) >> <NUM_LIT> ; if ( lu32i [ sign31 ] && lu52i [ sign31 ] ) return cost ; else if ( lu32i [ sign31 ] ) { codes [ cost ] . method = METHOD_LU52I ; codes [ cost ] . value = value & LU52I_B ; codes [ cost ] . curr_value = value ; return cost + <NUM_LIT> ; } codes [ cost ] . method = METHOD_LU32I ;

codes [ cost ] . value = ( value & LU32I_B ) | ( sign51 ? LU52I_B : <NUM_LIT> ) ;


<s> const LLT ScalarTy = LLT :: scalar ( Op1Ty . getSizeInBits ( ) ) ; const RegisterBank & FPRBank = * RBI . getRegBank ( Op1 , MRI , TRI ) ; const TargetRegisterClass * DstRC = getRegClassForTypeOnBank ( Op1Ty . multiplyElements ( <NUM_LIT> ) , FPRBank ) ; MachineInstr * WidenedOp1 = emitScalarToVector ( ScalarTy . getSizeInBits ( ) , DstRC , Op1 , MIRBuilder ) ; MachineInstr * WidenedOp2 = emitScalarToVector ( ScalarTy . getSizeInBits ( ) , DstRC , Op2 , MIRBuilder ) ; if ( ! WidenedOp1 || ! WidenedOp2 ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } unsigned InsertOpc , InsSubRegIdx ; std :: tie ( InsertOpc , InsSubRegIdx ) = getInsertVecEltOpInfo ( FPRBank , ScalarTy . getSizeInBits ( ) ) ; if ( ! Dst ) Dst = MRI . createVirtualRegister ( DstRC ) ; auto InsElt = MIRBuilder . buildInstr ( InsertOpc , { * Dst } , { WidenedOp1 -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) . addImm ( <NUM_LIT> ) . addUse ( WidenedOp2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) ; constrainSelectedInstRegOperands ( * InsElt , TII , TRI , RBI ) ; return & * InsElt ;


<s> CriticalPathRCs . push_back ( has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; return OptLevel >= CodeGenOpt :: Aggressive ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const {


<s> CanAcceptCarrySet = Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ; if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic . startswith ( <STR_LIT> ) || Mnemonic . startswith ( <STR_LIT> ) || ( FullInst . startswith ( <STR_LIT> ) && FullInst . endswith ( <STR_LIT> ) ) || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) { CanAcceptPredicationCode = false ; } else if ( ! isThumb ( ) ) { CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && ! Mnemonic . startswith ( <STR_LIT> ) && ! Mnemonic . startswith ( <STR_LIT> ) ; } else if ( isThumbOne ( ) ) { if ( hasV6MOps ( ) ) CanAcceptPredicationCode = Mnemonic != <STR_LIT> ;

else CanAcceptPredicationCode = Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ;


<s> SDValue imm = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; unsigned Opc = <STR_LIT> ; if ( Node -> hasOneUse ( ) ) CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI , imm ) ; else ReplaceNode ( Node , CurDAG -> getMachineNode ( Opc , dl , VT , TFI , imm ) ) ; return ; }


<s> if ( <ISA_LIT>II :: isLoadInst ( MCI ) ) { idx = <NUM_LIT> ; } else if ( <ISA_LIT>II :: isSPUInst ( MCI ) ) { idx = <NUM_LIT> ; } else if ( <ISA_LIT>II :: isVPUInst ( MCI ) ) {


<s> if ( TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE ( valtype ) == DCmode ) { return gen_rtx_PARALLEL ( DCmode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( SImode , GP_ARG_RETURN + <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ) ) ; } if ( ( INTEGRAL_TYPE_P ( valtype ) && TYPE_PRECISION ( valtype ) < BITS_PER_WORD ) || POINTER_TYPE_P ( valtype ) ) mode = TARGET_32BIT ? SImode : DImode ;


<s> do { frame_size = cfun_frame_layout . frame_size ; base_used = cfun -> machine -> split_branches_pending_p || crtl -> uses_const_pool || ( ! DISP_IN_RANGE ( frame_size ) && ! CONST_OK_FOR_K ( frame_size ) ) ; if ( ! base_used ) cfun -> machine -> base_reg = NULL_RTX ;

else if ( crtl -> is_leaf && ! df_regs_ever_live_p ( <NUM_LIT> ) ) cfun -> machine -> base_reg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ;


<s> if ( ! isTypeLegal ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM ;

if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM ) ) return false ;


<s> MachineInstr * Terminator = & BB -> instr_back ( ) ; if ( Terminator -> isUnconditionalBranch ( ) && I != Terminator ) { MachineBasicBlock * Succ = Terminator -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BB -> isLayoutSuccessor ( Succ ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Terminator ) ; Terminator -> eraseFromParent ( ) ; } } } ; if ( LoLoop . Revert ) { if ( LoLoop . Start -> getOpcode ( ) == <STR_LIT> ) RevertWhile ( LoLoop . Start ) ; else LoLoop . Start -> eraseFromParent ( ) ; bool FlagsAlreadySet = RevertLoopDec ( LoLoop . Dec , true ) ; RevertLoopEnd ( LoLoop . End , FlagsAlreadySet ) ; } else {

LoLoop . Start = ExpandLoopStart ( LoLoop ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & ST ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , ST . is64Bit ( ) ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) , <NUM_LIT> , ST . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) {


<s> unsigned DWord3 = MRI . createVirtualRegister ( & AMDGPU :: SGPR_32RegClass ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: S_MOV_B32 ) , DWord1 ) . addImm ( <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: S_MOV_B32 ) , DWord2 ) . addImm ( AMDGPU :: RSRC_DATA_FORMAT & <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: S_MOV_B32 ) , DWord3 ) . addImm ( AMDGPU :: RSRC_DATA_FORMAT >> <NUM_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: REG_SEQUENCE ) , SRsrc ) . addReg ( DWord0 ) . addImm ( AMDGPU :: sub0 ) . addReg ( DWord1 ) . addImm ( AMDGPU :: sub1 ) . addReg ( DWord2 ) . addImm ( AMDGPU :: sub2 ) . addReg ( DWord3 ) . addImm ( AMDGPU :: sub3 ) ; MI -> setDesc ( get ( NewOpcode ) ) ; if ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } else { MI -> getOperand ( <NUM_LIT> ) . ChangeToRegister ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , false ) ; } MI -> getOperand ( <NUM_LIT> ) . setReg ( SRsrc ) ; MI -> addOperand ( * MBB -> getParent ( ) , MachineOperand :: CreateImm ( ImmOffset ) ) ; const TargetRegisterClass * NewDstRC = RI . getRegClass ( get ( NewOpcode ) . OpInfo [ <NUM_LIT> ] . RegClass ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned NewDstReg = MRI . createVirtualRegister ( NewDstRC ) ; MRI . replaceRegWith ( DstReg , NewDstReg ) ; break ; } case AMDGPU :: S_LOAD_DWORDX8_IMM : case AMDGPU :: S_LOAD_DWORDX8_SGPR : { MachineInstr * Lo , * Hi ; splitSMRD ( MI , & AMDGPU :: SReg_128RegClass , AMDGPU :: S_LOAD_DWORDX4_IMM , AMDGPU :: S_LOAD_DWORDX4_SGPR , Lo , Hi ) ; MI -> eraseFromParent ( ) ; moveSMRDToVALU ( Lo , MRI ) ; moveSMRDToVALU ( Hi , MRI ) ; break ; } case AMDGPU :: S_LOAD_DWORDX16_IMM : case AMDGPU :: S_LOAD_DWORDX16_SGPR : {


<s> case V4DFmode : case V4DImode : case V16SFmode : case V16SImode : case V64QImode : case V32HImode : case V8DFmode : case V8DImode : if ( ! named ) return NULL ; break ; } return construct_container ( mode , orig_mode , type , <NUM_LIT> , cum -> nregs , cum -> sse_nregs , & x86_64_int_parameter_registers [ cum -> regno ] , cum -> sse_regno ) ;


<s> assert ( hasAVLReg ( ) ) ; return AVLReg ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = insn & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodePredRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value ) ) ; break ; case ( <STR_LIT> ) : ++ shift ; case <STR_LIT> : case <STR_LIT> : ++ shift ; case <STR_LIT> : case <STR_LIT> : Value |= insn & UINT64_C ( <NUM_LIT> ) ; DecodeIntRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << shift ) ) ; break ; case <STR_LIT> : Value = insn & UINT64_C ( <NUM_LIT> ) ; DecodeDoubleRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT> ) ) ; break ; case <STR_LIT> : Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= insn & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << <NUM_LIT> ) ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; DecodeDoubleRegsRegisterClass ( MI , Value , <NUM_LIT> , nullptr ) ; break ; case <STR_LIT> : ++ shift ; case <STR_LIT> : ++ shift ; case <STR_LIT> : Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ; Value |= insn & UINT64_C ( <NUM_LIT> ) ; MI . addOperand ( MCOperand :: createImm ( Value << shift ) ) ; Value = ( insn >> <NUM_LIT> ) & UINT64_C ( <NUM_LIT> ) ;


<s> bool No<ISA_LIT>16Attr = FnAttrs . hasAttribute ( AttributeSet :: FunctionIndex , <STR_LIT> ) ; assert ( ! ( <ISA_LIT>16Attr && No<ISA_LIT>16Attr ) && <STR_LIT> ) ; if ( <ISA_LIT>16Attr ) Subtarget = & <ISA_LIT>16Subtarget ; else if ( No<ISA_LIT>16Attr ) Subtarget = & No<ISA_LIT>16Subtarget ; else Subtarget = & DefaultSubtarget ; MF -> setSubtarget ( Subtarget ) ; return ;


<s> bool IsIndirectCall ; if ( isCall ( Inst . getOpcode ( ) , & IsIndirectCall ) ) { if ( PendingCall ) report_fatal_error ( <STR_LIT> ) ; EmitBundleLock ( true ) ; if ( IsIndirectCall ) { unsigned TargetReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; emitMask ( TargetReg , IndirectBranchMaskReg , STI ) ; } <ISA_LIT>ELFStreamer :: EmitInstruction ( Inst , STI ) ; PendingCall = true ; return ; } if ( PendingCall ) { <ISA_LIT>ELFStreamer :: EmitInstruction ( Inst , STI ) ; EmitBundleUnlock ( ) ; PendingCall = false ; return ; }


<s> return ( ( qword ) ( vec_mulo ( ( vec_ushort8 ) ( a ) , vec_splat ( ( vec_ushort8 ) ( si_from_ushort ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> if ( ! matchShuffleWithSHUFPD ( VT , V1 , V2 , ForceV1Zero , ForceV2Zero , Immediate , Mask , Zeroable ) ) return SDValue ( ) ; if ( ForceV1Zero ) V1 = getZeroVector ( VT , Subtarget , DAG , DL ) ; if ( ForceV2Zero ) V2 = getZeroVector ( VT , Subtarget , DAG , DL ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getTargetConstant ( Immediate , DL , <STR_LIT> ) ) ;


<s> OutStreamer . emitLabel ( StubLabel ) ; OutStreamer . emitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ;

if ( MCSym . getInt ( ) ) OutStreamer . emitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;


<s> static unsigned int insn_is_load_p ( rtx insn ) { rtx body = PATTERN ( insn ) ; if ( GET_CODE ( body ) == SET ) { if ( GET_CODE ( SET_SRC ( body ) ) == MEM ) return <NUM_LIT> ;

if ( GET_CODE ( SET_SRC ( body ) ) == VEC_SELECT && GET_CODE ( XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ) == MEM ) return <NUM_LIT> ;


<s> if ( mem ) return MIB . addImm ( Offset ) . addFrameIndex ( FI ) ;

else return MIB . addFrameIndex ( FI ) . addImm ( Offset ) ;


<s> bool <ISA_LIT>CodeEmitter :: runOnMachineFunction ( MachineFunction & MF ) { assert ( ( MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Default || MF . getTarget ( ) . getRelocationModel ( ) != Reloc :: Static ) && <STR_LIT> ) ; MCE . setModuleInfo ( & getAnalysis < MachineModuleInfo > ( ) ) ; do {


<s> unsigned short base_mode_size = GET_MODE_SIZE ( base_mode ) ; int nregs = size / base_mode_size , i ; rtx regs ; regs = gen_rtx_PARALLEL ( BLKmode , rtvec_alloc ( nregs ) ) ; for ( i = <NUM_LIT> ; i < nregs ; i ++ ) { XVECEXP ( regs , <NUM_LIT> , i ) = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( base_mode , regno ) , GEN_INT ( base_mode_size * i ) ) ;


<s> case CmpInst :: FCMP_TRUE : { ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addImm ( <NUM_LIT> ) ; break ; } } if ( ResultReg ) { updateValueMap ( I , ResultReg ) ; return true ; } const Value * LHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * RHS = CI -> getOperand ( <NUM_LIT> ) ; if ( Predicate == CmpInst :: FCMP_ORD || Predicate == CmpInst :: FCMP_UNO ) { const auto * RHSC = dyn_cast < ConstantFP > ( RHS ) ; if ( RHSC && RHSC -> isNullValue ( ) ) RHS = LHS ; } static const uint16_t SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; const uint16_t * SETFOpc = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } ResultReg = createResultReg ( & <STR_LIT> ) ; if ( SETFOpc ) { if ( ! <ISA_LIT>FastEmitCompare ( LHS , RHS , VT , I -> getDebugLoc ( ) ) ) return false ; Register FlagReg1 = createResultReg ( & <STR_LIT> ) ; Register FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg1 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , FlagReg2 ) . addImm ( SETFOpc [ <NUM_LIT> ] ) ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ;


<s> if ( TARGET_CPU_ZARCH && larl_operand ( op , VOIDmode ) ) return <NUM_LIT> ; if ( TLS_SYMBOLIC_CONST ( op ) ) return <NUM_LIT> ; if ( flag_pic ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedLdStVT . getSimpleVT ( ) ) ; } EVT ElemTy = VT . getVectorElementType ( ) ; if ( ElemTy != <STR_LIT> && ElemTy != <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy == <STR_LIT> || ElemTy == <STR_LIT> ) setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; if ( ElemTy != <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; } setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Legal ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ;


<s> static bool mep_vector_mode_supported_p ( machine_mode mode ATTRIBUTE_UNUSED ) {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateImm ( ShiftExtend . Amount ) ) ;


<s> if ( ! readInstruction32 ( Region , Address , Size , insn32 ) ) { return Fail ; } Result = decodeInstruction ( DecoderTable32 , instr , insn32 , Address , this , STI ) ; if ( Result != Fail ) { Size = <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } for ( auto CS : AvailableRegs ) if ( ! Uses . count ( CS ) && CS != <STR_LIT> ) return CS ; }


<s> case PseudoSourceValue :: GOT : case PseudoSourceValue :: JumpTable : case PseudoSourceValue :: GlobalValueCallEntry : case PseudoSourceValue :: ExternalSymbolCallEntry :

case PseudoSourceValue :: TargetCustom :


<s> return packConstantV2I16 ( N , DAG , true ) ;


<s> Comparison C ( getCmp ( DAG , CmpOp0 , CmpOp1 , CC , DL ) ) ; if ( C . Opcode == <STR_LIT> && C . CCMask != <STR_LIT> && C . CCMask != <STR_LIT> && C . Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( C . Op1 ) -> getZExtValue ( ) == <NUM_LIT> ) { if ( isAbsolute ( C . Op0 , TrueOp , FalseOp ) ) return getAbsolute ( DAG , DL , TrueOp , C . CCMask & <STR_LIT> ) ; if ( isAbsolute ( C . Op0 , FalseOp , TrueOp ) ) return getAbsolute ( DAG , DL , FalseOp , C . CCMask & <STR_LIT> ) ; } SDValue Glue = emitCmp ( DAG , DL , C ) ; auto * TrueC = dyn_cast < ConstantSDNode > ( TrueOp ) ; auto * FalseC = dyn_cast < ConstantSDNode > ( FalseOp ) ; if ( TrueC && FalseC ) { int64_t TrueVal = TrueC -> getSExtValue ( ) ; int64_t FalseVal = FalseC -> getSExtValue ( ) ; if ( ( TrueVal == - <NUM_LIT> && FalseVal == <NUM_LIT> ) || ( TrueVal == <NUM_LIT> && FalseVal == - <NUM_LIT> ) ) {

if ( TrueVal == <NUM_LIT> ) C . CCMask ^= C . CCValid ;


<s> explicit <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> SMLoc E ; if ( getParser ( ) . parseExpression ( Value , E ) ) return true ; getParser ( ) . getStreamer ( ) . EmitValue ( Value , Size ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) break ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; } } Parser . Lex ( ) ; return false ;


<s> } return getAddrLarge ( CP , DAG ) ; } else if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Tiny ) { return getAddrTiny ( CP , DAG ) ; } else { return getAddr ( CP , DAG ) ; }


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> unsigned EncodedVal = ( RegWidth - CE -> getValue ( ) ) % RegWidth ; Inst . addOperand ( MCOperand :: CreateImm ( EncodedVal ) ) ;


<s> O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; unsigned PTXVersion = STI . getPTXVersion ( ) ; O << <STR_LIT> << ( PTXVersion / <NUM_LIT> ) << <STR_LIT> << ( PTXVersion % <NUM_LIT> ) << <STR_LIT> ; O << <STR_LIT> ; O << STI . getTargetName ( ) ; const <ISA_LIT>TargetMachine & NTM = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) ; if ( NTM . getDrvInterface ( ) == <STR_LIT> ) O << <STR_LIT> ; bool HasFullDebugInfo = false ; for ( DICompileUnit * CU : M . debug_compile_units ( ) ) { switch ( CU -> getEmissionKind ( ) ) { case DICompileUnit :: NoDebug : case DICompileUnit :: DebugDirectivesOnly : break ; case DICompileUnit :: LineTablesOnly : case DICompileUnit :: FullDebug : HasFullDebugInfo = true ; break ; } if ( HasFullDebugInfo ) break ; }

if ( MMI && MMI -> hasDebugInfo ( ) && HasFullDebugInfo ) O << <STR_LIT> ;


<s> case <STR_LIT> : if ( ( VT == <STR_LIT> && C != INT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != INT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != UINT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != UINT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , VT ) ; } break ; } } } if ( ( CC == <STR_LIT> || CC == <STR_LIT> ) && isa < ConstantSDNode > ( RHS ) ) { if ( ( cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) >> <NUM_LIT> == <NUM_LIT> ) && isa < LoadSDNode > ( LHS ) ) { if ( cast < LoadSDNode > ( LHS ) -> getExtensionType ( ) == <STR_LIT> && cast < LoadSDNode > ( LHS ) -> getMemoryVT ( ) == <STR_LIT> && LHS . getNode ( ) -> hasNUsesOfValue ( <NUM_LIT> , <NUM_LIT> ) ) {

int16_t ValueofRHS = cast < ConstantSDNode > ( RHS ) -> getZExtValue ( ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , ELFArch ( <NUM_LIT> ) , m_hasSRAM ( false ) , m_hasJMPCALL ( false ) , m_hasIJMPCALL ( false ) , m_hasEIJMPCALL ( false ) , m_hasADDSUBIW ( false ) , m_hasSmallStack ( false ) , m_hasMOVW ( false ) , m_hasLPM ( false ) , m_hasLPMX ( false ) , m_hasELPM ( false ) , m_hasELPMX ( false ) , m_hasSPM ( false ) , m_hasSPMX ( false ) , m_hasDES ( false ) , m_supportsRMW ( false ) , m_supportsMultiplication ( false ) , m_hasBREAK ( false ) , m_hasTinyEncoding ( false ) , m_FeatureSetDummy ( false ) , InstrInfo ( ) , FrameLowering ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS , TM ) ) , TSInfo ( ) { ParseSubtargetFeatures ( CPU , FS ) ;


<s> bool <ISA_LIT>FastISel :: SelectFPExt ( const Instruction * I ) { Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = TLI . getValueType ( Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ;


<s> dbgs ( ) << <STR_LIT> << getLoopDepth ( ContLoop ) << <STR_LIT> << getLoopDepth ( ContingLoop ) << <STR_LIT> ; ) ;

settleLoopcontBlock ( ContingMBB , ContMBB ) ;


<s> Value * PassThru = I -> getArgOperand ( <NUM_LIT> ) ; if ( ! isLegalTypeAndAlignment ( Ty -> getNumElements ( ) , Ty -> getScalarSizeInBits ( ) , Alignment ) ) return nullptr ; lookThroughBitcast ( Ptr ) ; assert ( Ptr -> getType ( ) -> isVectorTy ( ) && <STR_LIT> ) ; IRBuilder < > Builder ( I -> getContext ( ) ) ; Builder . SetInsertPoint ( I ) ; Builder . SetCurrentDebugLocation ( I -> getDebugLoc ( ) ) ; Instruction * Root = I ; Value * Load = tryCreateMaskedGatherOffset ( I , Ptr , Root , Builder ) ; if ( ! Load ) Load = tryCreateMaskedGatherBase ( I , Ptr , Builder ) ; if ( ! Load ) return nullptr ; if ( ! isa < UndefValue > ( PassThru ) && ! match ( PassThru , m_Zero ( ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; Load = Builder . CreateSelect ( Mask , Load , PassThru ) ;


<s> if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { if ( SelectT2AddrModeImm8 ( N , Base , OffImm ) ) return false ; int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( ) ) ; }

OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ;


<s> OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VSXVectorSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VectorFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_VRSaveSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat8Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadFloat4Spill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_QuadBitSpill ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { OpcodeIndex = SOK_SpillToVSR ; } else { llvm_unreachable ( <STR_LIT> ) ; } } else { if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int4Spill ; } else if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Int8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float8Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_Float4Spill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_CRBitSpill ; } else if ( <STR_LIT> . contains ( Reg ) ) { OpcodeIndex = SOK_VRVectorSpill ;


<s> if ( Ps & ConstantProperties :: NaN ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: PosOrZero ) os << <STR_LIT> ; if ( Ps & ConstantProperties :: NegOrZero ) os << <STR_LIT> ; os << '}' ; return ; } os << <STR_LIT> ; if ( isBottom ( ) ) { os << <STR_LIT> ; } else if ( isTop ( ) ) { os << <STR_LIT> ; } else { for ( unsigned i = <NUM_LIT> ; i < size ( ) ; ++ i ) { const Constant * C = Values [ i ] ;


<s> HABaseType Base = HA_UNKNOWN ; uint64_t Members = <NUM_LIT> ; bool result = isHomogeneousAggregate ( Ty , Base , Members ) ; DEBUG ( dbgs ( ) << <STR_LIT> << result << <STR_LIT> ; Ty -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ;


<s> unsigned Reg , RegNum , RegWidth ; if ( ! Parse<ISA_LIT>Register ( RegKind , Reg , RegNum , RegWidth ) ) { return nullptr ; } if ( isHsaAbiVersion3 ( & getSTI ( ) ) ) { if ( ! updateGprCountSymbols ( RegKind , RegNum , RegWidth ) ) return nullptr ; } else KernelScope . usesRegister ( RegKind , RegNum , RegWidth ) ;

return <ISA_LIT>Operand :: CreateReg ( this , Reg , StartLoc , EndLoc ) ;


<s> if ( First ) { if ( NumZero ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else V = DAG . getUNDEF ( <STR_LIT> ) ; First = false ; } V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , Op . getOperand ( i ) , DAG . getIntPtrConstant ( i ) ) ; }


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; const MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; int64_t FrameOffset = MFI . getStackSize ( ) + MFI . getObjectOffset ( FrameIndex ) ; if ( MI . mayLoadOrStore ( ) ) { assert ( FrameOffset >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ) ; int64_t Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) + FrameOffset ; if ( static_cast < uint64_t > ( Offset ) > std :: numeric_limits < uint32_t > :: max ( ) ) { report_fatal_error ( <STR_LIT> ) ; }

MI . getOperand ( <NUM_LIT> ) . setImm ( Offset ) ;


<s> if ( TARGET_E500_DOUBLE && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return false ; x = XEXP ( x , <NUM_LIT> ) ; if ( TARGET_ELF || TARGET_MACHO ) { bool large_toc_ok ; if ( DEFAULT_ABI == ABI_V4 && flag_pic ) return false ; large_toc_ok = ( lra_in_progress && TARGET_CMODEL != CMODEL_SMALL && small_toc_ref ( x , VOIDmode ) ) ; if ( TARGET_TOC && ! large_toc_ok ) return false ; if ( GET_MODE_NUNITS ( mode ) != <NUM_LIT> ) return false ;

if ( GET_MODE_SIZE ( mode ) > UNITS_PER_WORD && ! ( TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && ( mode == DFmode || mode == DDmode ) ) ) return false ;


<s> HOST_WIDE_INT result ; if ( ! GET_MODE_BITSIZE ( TYPE_MODE ( type ) ) . is_constant ( & result ) || ! pow2p_hwi ( result ) ) result = TYPE_ALIGN ( TREE_TYPE ( type ) ) ; return result ; } return TYPE_ALIGN ( type ) ;


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; assert ( Amount % <NUM_LIT> == <NUM_LIT> ) ; Amount /= <NUM_LIT> ; bool isU6 = isImmU6 ( Amount ) ; if ( ! isU6 && ! isImmU16 ( Amount ) ) { errs ( ) << <STR_LIT> << Amount << <STR_LIT> ; llvm_unreachable ( <NUM_LIT> ) ; }


<s> explicit <ISA_LIT>AsmBackend ( bool Is64Bit ) : MCAsmBackend ( <STR_LIT> ) , Is64Bit ( Is64Bit ) {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; Ld0 -> dump ( ) ; dbgs ( ) << <STR_LIT> ; Ld1 -> dump ( ) ; ) ;

if ( ! Ld0 -> hasOneUse ( ) || ! Ld1 -> hasOneUse ( ) ) {


<s> if ( llvm :: findAllNVVMAnnotation ( func , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISWRITEONLY_IMAGE_PARAM ] , annot ) ) { if ( std :: find ( annot . begin ( ) , annot . end ( ) , arg -> getArgNo ( ) ) != annot . end ( ) ) return true ; } }


<s> ret . val [ <NUM_LIT> ] = ( uint8x8_t ) __builtin_aarch64_get_dregoiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint8x8_t ) __builtin_aarch64_get_dregoiv8qi ( __o , <NUM_LIT> ) ;


<s> return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: ExtractValue : return <ISA_LIT>SelectExtractValue ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ;

if ( DstVT . bitsLT ( SrcVT ) ) return <ISA_LIT>SelectTrunc ( I ) ;


<s> } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( MCConstantExpr :: Create ( Cc , getContext ( ) ) , NameLoc , E ) ) ; } else { return parseMathOperation ( Name , NameLoc , Operands ) ; } Format = Name . slice ( Dot , StringRef :: npos ) ; Operands . push_back ( <STR_LIT> ( Format , NameLoc ) ) ; } setFpFormat ( Format ) ; } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ParseOperand ( Operands , Mnemonic ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( ParseOperand ( Operands , Name ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; Parser . eatToEndOfStatement ( ) ; return Error ( Loc , <STR_LIT> ) ; } Parser . Lex ( ) ; return false ;


<s> spill_fill_data . save_gr_used_mask = current_frame_info . gr_used_mask ; spill_fill_data . n_iter = <NUM_LIT> + ( n_spills > <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < spill_fill_data . n_iter ; ++ i ) { int regno = next_scratch_gr_reg ( ) ; spill_fill_data . iter_reg [ i ] = gen_rtx_REG ( DImode , regno ) ; current_frame_info . gr_used_mask |= <NUM_LIT> << regno ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>BaseTargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) {


<s> SDValue InFlag ; Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , Chain , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; return GetDynamicTLSAddr ( DAG , Chain , GA , & InFlag , PtrVT , <STR_LIT> , <STR_LIT> ) ;


<s> return hasStandardEncoding ( ) || allowMixed16_32 ( ) ;


<s> AMDGPUAsmParser :: OperandMatchResultTy AMDGPUAsmParser :: parseGLC ( OperandVector & Operands ) {

return parseNamedBit ( <STR_LIT> , Operands ) ;


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; } case <STR_LIT> : { if ( Commute ) return false ; ImmVal = - ImmVal ; NewUseOpc = <STR_LIT> ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! <STR_LIT> ( ImmVal ) ) return false ; SOImmValV1 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; SOImmValV2 = ( uint32_t ) <STR_LIT> ( ImmVal ) ; switch ( UseOpc ) { default : break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; case <STR_LIT> : NewUseOpc = <STR_LIT> ; break ; } break ; } } } } unsigned OpIdx = Commute ? <NUM_LIT> : <NUM_LIT> ; unsigned Reg1 = UseMI -> getOperand ( OpIdx ) . getReg ( ) ; bool isKill = UseMI -> getOperand ( OpIdx ) . isKill ( ) ; unsigned NewReg = MRI -> createVirtualRegister ( MRI -> getRegClass ( Reg ) ) ; AddDefaultCC ( AddDefaultPred ( BuildMI ( * UseMI -> getParent ( ) , UseMI , UseMI -> getDebugLoc ( ) , get ( NewUseOpc ) , NewReg ) . addReg ( Reg1 , getKillRegState ( isKill ) ) . addImm ( SOImmValV1 ) ) ) ; UseMI -> setDesc ( get ( NewUseOpc ) ) ; UseMI -> getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; UseMI -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ; UseMI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( SOImmValV2 ) ; DefMI -> eraseFromParent ( ) ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return AluT_XYZW ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) { return AluDiscarded ; } break ; default : break ; } if ( TII -> isVector ( * MI ) || TII -> isCubeOp ( MI -> getOpcode ( ) ) || TII -> isReductionOp ( MI -> getOpcode ( ) ) || MI -> getOpcode ( ) == <STR_LIT> ) { return AluT_XYZW ; } if ( TII -> isLD<ISA_LIT>nstr ( MI -> getOpcode ( ) ) ) { return AluT_X ; } unsigned DestSubReg = MI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) ; switch ( DestSubReg ) { case <STR_LIT> : return AluT_X ; case <STR_LIT> : return AluT_Y ; case <STR_LIT> : return AluT_Z ;


<s> return ( GET_CODE ( op ) == CONST && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == UNSPEC && ! nios2_large_offset_p ( XINT ( XEXP ( op , <NUM_LIT> ) , <NUM_LIT> ) ) ) ;


<s> if ( MFI -> hasCalls ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( RAOffset ) . addReg ( <STR_LIT> ) ; } if ( hasFP ( MF ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( FPOffset ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } if ( ( isPIC ) && ( MFI -> hasCalls ( ) ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addImm ( <ISA_LIT>FI -> getGPStackOffset ( ) ) ; }


<s> if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N -> getOperand ( <NUM_LIT> ) ; if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) if ( C -> getValueAPF ( ) . isPosZero ( ) ) return N -> getOperand ( <NUM_LIT> ) ; return lower<ISA_LIT>FPLogicOp ( N , DAG , Subtarget ) ;


<s> return gen_rtx_SET ( VOIDmode , dest , GEN_INT ( val ) ) ;


<s> PrintExpr ( const HCE :: ExtExpr & E , const <ISA_LIT>RegisterInfo & I ) : Ex ( E ) , HRI ( I ) {


<s> <ISA_LIT>AbsoluteStub :: ~ <ISA_LIT>AbsoluteStub ( ) {


<s> BitVector Reserved ( getNumRegs ( ) ) ; for ( auto Reg : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) Reserved . set ( Reg ) ;


<s> OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( N . getOpcode ( ) == <STR_LIT> && ! ( Subtarget -> useMovt ( ) && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; } else Base = N ; OffImm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( RHSC >= <NUM_LIT> && RHSC < <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; } OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ; return true ; } } Base = N ;


return ( isConstantImm ( ) && isShiftedUInt < <NUM_LIT> , <NUM_LIT> > ( getConstantImm ( ) ) ) ;


<s> const unsigned Size = Ty . getSizeInBits ( ) ; if ( Size <= <NUM_LIT> ) { return LLT :: scalar ( Size ) ; } return LLT :: scalarOrVector ( ElementCount :: getFixed ( Size / <NUM_LIT> ) , <NUM_LIT> ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( RV32 ) , HasM ( false ) , HasA ( false ) , HasF ( false ) , HasD ( false ) , IsR5CY ( false ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( ) , FrameLowering ( ) {


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( getThe<ISA_LIT>beTarget ( ) ) ;

RegisterMCAsmParser < <ISA_LIT>AsmParser > Z ( getTheARM64Target ( ) ) ;


<s> return __builtin_mve_vcvtq_m_from_f_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __p ) ;


<s> <STR_LIT> :: write < uint32_t > ( & Data [ Fixup . getOffset ( ) + <NUM_LIT> ] , static_cast < uint32_t > ( Value ) , Endian ) ; } else if ( Fixup . getKind ( ) == FK_Data_4 ) { <STR_LIT> :: write < uint32_t > ( & Data [ Fixup . getOffset ( ) ] , Value , Endian ) ; } else if ( Fixup . getKind ( ) == FK_Data_8 ) { <STR_LIT> :: write < uint64_t > ( & Data [ Fixup . getOffset ( ) ] , Value , Endian ) ; } else if ( Fixup . getKind ( ) == FK_PCRel_4 ) { Value = ( uint32_t ) ( ( Value - <NUM_LIT> ) / <NUM_LIT> ) ; if ( Endian == <STR_LIT> ) { Data [ Fixup . getOffset ( ) + <NUM_LIT> ] = <NUM_LIT> ; <STR_LIT> :: write32le ( & Data [ Fixup . getOffset ( ) + <NUM_LIT> ] , Value ) ; } else { Data [ Fixup . getOffset ( ) + <NUM_LIT> ] = <NUM_LIT> ; <STR_LIT> :: write32be ( & Data [ Fixup . getOffset ( ) + <NUM_LIT> ] , Value ) ; } } else { assert ( Fixup . getKind ( ) == FK_PCRel_2 ) ; Value = ( uint16_t ) ( ( Value - <NUM_LIT> ) / <NUM_LIT> ) ;

<STR_LIT> :: write < uint16_t > ( & Data [ Fixup . getOffset ( ) + <NUM_LIT> ] , Value , Endian ) ;


<s> SmallVector < SDValue , <NUM_LIT> > NewOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; NewOps [ N -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ] = NewPtr ; return SDValue ( DAG . UpdateNodeOperands ( N , NewOps ) , <NUM_LIT> ) ; } } return SDValue ( ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ;


<s> return new NPEnginePassConfig ( this , PM ) ;


<s> SDValue Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) ; SDValue RelAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue AbsAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GlobalBase , RelAddr ) ;

return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , AbsAddr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( uint64_t Count , MCObjectWriter * OW ) const {

if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ;


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; SDValue Target = N -> getOperand ( <NUM_LIT> ) ; EVT CompareTys [ ] = { <STR_LIT> , <STR_LIT> } ;

SDVTList CompareVT = CurDAG -> getVTList ( CompareTys ) ;


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , const Triple & TT ) : <ISA_LIT>AsmBackend ( T , TT ) {


<s> Inst . addOperand ( MCOperand :: CreateReg ( VectorList . RegNum ) ) ;

Inst . addOperand ( MCOperand :: CreateImm ( VectorList . LaneIndex ) ) ;


<s> assert ( ( Size || MI . isDebugOrPseudoInstr ( ) || MI . isPosition ( ) || MI . isKill ( ) || MI . isImplicitDef ( ) || MI . getOpcode ( ) == <STR_LIT> || MI . isInlineAsm ( ) || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; return Size ;


<s> SDValue <ISA_LIT>CC ; SDValue EFLAGS = emitFlagsForSetcc ( Op0 , Op1 , CC , dl , DAG , <ISA_LIT>CC ) ; if ( ! EFLAGS ) return SDValue ( ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , <ISA_LIT>CC , EFLAGS ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> MachineInstr * FirstOp = nullptr ; MachineInstr * LastOp = nullptr ; int LastOffset = <NUM_LIT> ; unsigned LastOpcode = <NUM_LIT> ; unsigned LastBytes = <NUM_LIT> ; unsigned NumMove = <NUM_LIT> ; for ( int i = Ops . size ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { MachineInstr * Op = Ops [ i ] ; unsigned Loc = MI2LocMap [ Op ] ; if ( Loc <= FirstLoc ) { FirstLoc = Loc ; FirstOp = Op ; } if ( Loc >= LastLoc ) { LastLoc = Loc ; LastOp = Op ; } unsigned LSMOpcode = getLoadStoreMultipleOpcode ( Op -> getOpcode ( ) , <STR_LIT> ) ; if ( LastOpcode && LSMOpcode != LastOpcode ) break ; int Offset = getMemoryOpOffset ( Op ) ; unsigned Bytes = getLSMultipleTransferSize ( Op ) ; if ( LastBytes ) { if ( Bytes != LastBytes || Offset != ( LastOffset + ( int ) Bytes ) ) break ; } LastOffset = Offset ; LastBytes = Bytes ; LastOpcode = LSMOpcode ; if ( ++ NumMove == <NUM_LIT> ) break ; } if ( NumMove <= <NUM_LIT> ) Ops . pop_back ( ) ; else { SmallPtrSet < MachineInstr * , <NUM_LIT> > MemOps ; SmallSet < unsigned , <NUM_LIT> > MemRegs ; for ( int i = NumMove - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { MemOps . insert ( Ops [ i ] ) ; MemRegs . insert ( Ops [ i ] -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } bool DoMove = ( LastLoc - FirstLoc ) <= NumMove * <NUM_LIT> ; if ( DoMove ) DoMove = IsSafeAndProfitableToMove ( isLd , Base , FirstOp , LastOp , MemOps , MemRegs , TRI ) ; if ( ! DoMove ) { for ( unsigned i = <NUM_LIT> ; i != NumMove ; ++ i ) Ops . pop_back ( ) ; } else { MachineBasicBlock :: iterator InsertPos = isLd ? FirstOp : LastOp ; while ( InsertPos != MBB -> end ( ) && ( MemOps . count ( InsertPos ) || InsertPos -> isDebugValue ( ) ) ) ++ InsertPos ; MachineInstr * Op0 = Ops . back ( ) ; MachineInstr * Op1 = Ops [ Ops . size ( ) - <NUM_LIT> ] ; unsigned FirstReg = <NUM_LIT> , SecondReg = <NUM_LIT> ; unsigned BaseReg = <NUM_LIT> , PredReg = <NUM_LIT> ; <STR_LIT> Pred = <STR_LIT> ; bool isT2 = false ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val < <NUM_LIT> ) ;


AMDHSA_BITS_SET ( KD . compute_pgm_rsrc1 , amdhsa :: COMPUTE_PGM_RSRC1_WGP_MODE , STI -> getFeatureBits ( ) . test ( FeatureCuMode ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: allowsMisalignedMemoryAccesses ( EVT , unsigned , unsigned , MachineMemOperand :: Flags , bool * Fast ) const { if ( Fast ) * Fast = true ; return true ;


assert ( ( Imm == <NUM_LIT> || Imm == <NUM_LIT> ) && <STR_LIT> ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> unsigned <ISA_LIT>Subtarget :: getMaxLocalMemSizeWithWaveCount ( unsigned NWaves , const Function & F ) const { if ( NWaves == <NUM_LIT> ) return getLocalMemorySize ( ) ;

unsigned WorkGroupSize = getFlatWorkGroupSizes ( F ) . second ;


<s> const DenseMap < int , unsigned > & getWinEHXMMSlotInfo ( ) const {


<s> const <ISA_LIT>FrameLowering * <ISA_LIT>FI = static_cast < const <ISA_LIT>FrameLowering * > ( MF . getTarget ( ) . getFrameLowering ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . isDarwinABI ( ) ) { Reserved . set ( <STR_LIT> ) ;


<s> if ( isValueAvailable ( ZExt ) && isTypeSupported ( ZExt -> getSrcTy ( ) , VT ) ) { SrcVT = VT ; IsZExt = true ; Src0 = ZExt -> getOperand ( <NUM_LIT> ) ; } } } else if ( const auto * SExt = dyn_cast < SExtInst > ( Src0 ) ) { if ( ! isIntExtFree ( SExt ) ) { MVT VT ; if ( isValueAvailable ( SExt ) && isTypeSupported ( SExt -> getSrcTy ( ) , VT ) ) { SrcVT = VT ; IsZExt = false ; Src0 = SExt -> getOperand ( <NUM_LIT> ) ; } } } Register Src0Reg = getRegForValue ( Src0 ) ; if ( ! Src0Reg ) return false ; unsigned ResultReg = emitLSL_ri ( VT , SrcVT , Src0Reg , ShiftVal , IsZExt ) ; if ( ResultReg ) { updateValueMap ( I , ResultReg ) ; return true ; }


<s> static void def_or_undef_macro ( cpp_reader * pfile , const char * name , bool def_p ) { if ( def_p ) cpp_define ( pfile , name ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: lc3b > X ( The<ISA_LIT>Target , <STR_LIT> , <STR_LIT> ) ;


<s> for ( unit = <NUM_LIT> ; unit < ARRAY_SIZE ( frv_unit_groups ) ; unit ++ ) { group = frv_unit_groups [ unit ] ; packet_group = & frv_packet . groups [ group ] ; if ( cursor [ group ] < packet_group -> num_insns ) { gcc_assert ( packet_group -> sorted [ cursor [ group ] ] != packet_group -> nop ) ; insns [ to ++ ] = packet_group -> sorted [ cursor [ group ] ++ ] ; } } gcc_assert ( to == frv_packet . num_insns ) ; CLEAR_PACKING_FLAG ( insns [ to - <NUM_LIT> ] ) ; for ( from = <NUM_LIT> ; from < to - <NUM_LIT> ; from ++ ) { remove_insn ( insns [ from ] ) ; add_insn_before ( insns [ from ] , insns [ to - <NUM_LIT> ] ) ;


<s> if ( ! Opcode || ! adjustCCMasksForInstr ( MI , Compare , CCUsers , Opcode ) ) return false ; MachineInstr * BuiltMI = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , TII -> get ( Opcode ) ) ; for ( const auto & MO : MI . operands ( ) ) BuiltMI -> addOperand ( MO ) ; BuiltMI -> setMemRefs ( MI . memoperands_begin ( ) , MI . memoperands_end ( ) ) ;


<s> MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( hasFP ( MF ) ) { MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; MachineBasicBlock :: iterator MBBI_end = MBB . end ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int NumBytes = ( int ) MFI -> getStackSize ( ) ; const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; if ( STI . hasV4TOps ( ) && MBBI -> getOpcode ( ) == <STR_LIT> && ! DisableDeallocRet ) { MBB . erase ( MBBI ) ; BuildMI ( MBB , MBBI_end , dl , TII . get ( <STR_LIT> ) ) . addImm ( NumBytes ) ; } else { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addImm ( NumBytes ) ;


<s> operands [ <NUM_LIT> ] = gen_rtx_NEG ( SImode , operands [ <NUM_LIT> ] ) ; operands [ <NUM_LIT> ] = gen_rtx_PLUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; } else if ( val >= <NUM_LIT> && val < <NUM_LIT> ) { operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; operands [ <NUM_LIT> ] = gen_rtx_MINUS ( SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return ; }


<s> return false ; case FK_Data_1 : Log2Size = Log2_32 ( <NUM_LIT> ) ; return true ; case FK_Data_2 : Log2Size = Log2_32 ( <NUM_LIT> ) ; return true ; case FK_Data_4 : Log2Size = Log2_32 ( <NUM_LIT> ) ; if ( Sym -> getKind ( ) == MCSymbolRefExpr :: VK_GOT ) RelocType = unsigned ( MachO :: ARM64_RELOC_POINTER_TO_GOT ) ; return true ; case FK_Data_8 : Log2Size = Log2_32 ( <NUM_LIT> ) ; if ( Sym -> getKind ( ) == MCSymbolRefExpr :: VK_GOT ) RelocType = unsigned ( MachO :: ARM64_RELOC_POINTER_TO_GOT ) ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Log2Size = Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : return false ; case MCSymbolRefExpr :: VK_PAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGEOFF12 ) ; return true ; case MCSymbolRefExpr :: VK_TLVPPAGEOFF : RelocType = unsigned ( MachO :: ARM64_RELOC_TLVP_LOAD_PAGEOFF12 ) ; return true ; } case <STR_LIT> : Log2Size = Log2_32 ( <NUM_LIT> ) ; switch ( Sym -> getKind ( ) ) { default : Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return false ; case MCSymbolRefExpr :: VK_PAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_PAGE21 ) ; return true ; case MCSymbolRefExpr :: VK_GOTPAGE : RelocType = unsigned ( MachO :: ARM64_RELOC_GOT_LOAD_PAGE21 ) ; return true ;


<s> if ( ( ( GET_CODE ( insn ) == INSN && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) || GET_CODE ( insn ) == CALL_INSN || ( GET_CODE ( insn ) == JUMP_INSN && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC ) ) && GET_CODE ( PATTERN ( NEXT_INSN ( PREV_INSN ( insn ) ) ) ) != SEQUENCE && get_attr_needs_delay_slot ( insn ) == NEEDS_DELAY_SLOT_YES ) return <NUM_LIT> ; if ( sh_cpu == CPU_SH2E && GET_CODE ( insn ) == JUMP_INSN && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && get_attr_type ( insn ) == TYPE_CBRANCH && GET_CODE ( PATTERN ( NEXT_INSN ( PREV_INSN ( insn ) ) ) ) != SEQUENCE ) return <NUM_LIT> ; if ( GET_CODE ( insn ) == INSN ) { int sum = <NUM_LIT> ; rtx body = PATTERN ( insn ) ; const char * template ; char c ; int maybe_label = <NUM_LIT> ; if ( GET_CODE ( body ) == ASM_INPUT ) template = XSTR ( body , <NUM_LIT> ) ; else if ( asm_noperands ( body ) >= <NUM_LIT> ) template = decode_asm_operands ( body , NULL , NULL , NULL , NULL ) ; else return <NUM_LIT> ; do { int ppi_adjust = <NUM_LIT> ;


<s> return { IncDec , Addr , Load , AA } ;


<s> bool hasMOVW ( ) const { return m_hasMOVW ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = TM . getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ;

return CurDAG -> getRegister ( GlobalBaseReg , TLI -> getPointerTy ( ) ) . getNode ( ) ;


<s> MachineFrameInfo & MFrameInfo = MF . getFrameInfo ( ) ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOLoad , MFrameInfo . getObjectSize ( FrameIdx ) , MFrameInfo . getObjectAlignment ( FrameIdx ) ) ;

assert ( ( RC == & <STR_LIT> || RC == & <STR_LIT> ) && <STR_LIT> ) ;


<s> unsigned Opcode = N -> getOpcode ( ) ; bool ConsumeCarry = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; bool ProduceCarry = ConsumeCarry || Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool IsAdd = ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; SDValue Sub0 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * Lo0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub0 ) ; SDNode * Hi0 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , LHS , Sub1 ) ; SDNode * Lo1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub0 ) ; SDNode * Hi1 = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , RHS , Sub1 ) ; SDVTList VTList = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; unsigned Opc = IsAdd ? <STR_LIT> : <STR_LIT> ; unsigned CarryOpc = IsAdd ? <STR_LIT> : <STR_LIT> ; SDNode * AddLo ; if ( ! ConsumeCarry ) { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( Opc , DL , VTList , Args ) ; } else { SDValue Args [ ] = { SDValue ( Lo0 , <NUM_LIT> ) , SDValue ( Lo1 , <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; AddLo = CurDAG -> getMachineNode ( CarryOpc , DL , VTList , Args ) ; }


<s> <ISA_LIT>DebuggerInsertNops ( ) : MachineFunctionPass ( ID ) {


<s> if ( flags & SECTION_CODE ) * f ++ = 'x' ;

if ( strncmp ( name , LTO_SECTION_NAME_PREFIX , strlen ( LTO_SECTION_NAME_PREFIX ) ) == <NUM_LIT> ) * f ++ = '0' ;


<s> reg_iterator retreg_end ( ) const { return RegRets . end ( ) ;


<s> static bool readInstruction16 ( const MemoryObject & region , uint64_t address , uint64_t & size , uint16_t & insn ) { uint8_t Bytes [ <NUM_LIT> ] ; if ( region . readBytes ( address , <NUM_LIT> , Bytes ) == - <NUM_LIT> ) { size = <NUM_LIT> ; return false ; }

insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> void <ISA_LIT>AsmParser :: onLabelParsed ( MCSymbol * Symbol ) { if ( NextSymbolIsThumb ) {

getParser ( ) . getStreamer ( ) . emitThumbFunc ( Symbol ) ;


<s> OperandMatchResultTy parseVR64 ( OperandVector & Operands ) { return parseRegister ( Operands , RegV , <STR_LIT> , VR64Reg ) ;


<s> if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) ) { return false ; } Base = Op -> getOperand ( <NUM_LIT> ) ; Offset = DAG . getConstant ( RHSC , DL , <STR_LIT> ) ; AM = <STR_LIT> ;


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return <ISA_LIT>RDToVal ( static_cast < <STR_LIT> > ( getMachineOpValue ( MI , MO , Fixups , STI ) ) ) ; return <NUM_LIT> ;


<s> } return true ; case 'c' : if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isGlobal ( ) || MO . isCPI ( ) || MO . isJTI ( ) || MO . isSymbol ( ) ) printSymbolOperand ( MO , O ) ; else printOperand ( MI , OpNo , O ) ; return false ; case 'A' : if ( MO . isReg ( ) ) { O << '*' ; printOperand ( MI , OpNo , O ) ; return false ; } return true ; case 'b' : case 'h' : case 'w' : case 'k' : case 'q' : if ( MO . isReg ( ) ) return printAsmMRegister ( MO , ExtraCode [ <NUM_LIT> ] , O ) ;


<s> } else if ( modify ) SUBREG_REG ( x ) = new ; return x ; } else if ( GET_CODE ( x ) == REG ) { unsigned regno = REGNO ( x ) ; unsigned nregs = ( regno < FIRST_PSEUDO_REGISTER ? HARD_REGNO_NREGS ( regno , GET_MODE ( x ) ) : <NUM_LIT> ) ; rtx result = NULL_RTX ; for ( i = n_replacements - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { rtx from = replacements [ i * <NUM_LIT> ] ; rtx to = replacements [ i * <NUM_LIT> + <NUM_LIT> ] ; unsigned from_regno , from_nregs , to_regno , new_regno ; if ( GET_CODE ( from ) != REG ) continue ; from_regno = REGNO ( from ) ; from_nregs = ( from_regno < FIRST_PSEUDO_REGISTER ? HARD_REGNO_NREGS ( from_regno , GET_MODE ( from ) ) : <NUM_LIT> ) ; if ( regno < from_regno + from_nregs && regno + nregs > from_regno ) { if ( regno < from_regno || regno + nregs > from_regno + nregs || GET_CODE ( to ) != REG || result ) return NULL_RTX ; to_regno = REGNO ( to ) ; if ( to_regno < FIRST_PSEUDO_REGISTER ) { new_regno = regno + to_regno - from_regno ; if ( ( unsigned ) HARD_REGNO_NREGS ( new_regno , GET_MODE ( x ) ) != nregs ) return NULL_RTX ; result = gen_rtx_REG ( GET_MODE ( x ) , new_regno ) ;


<s> static bool allStackObjectsAreDead ( const MachineFunction & MF ) { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ;

const <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> static SDValue skipExtensionForVectorMULL ( SDNode * N , SelectionDAG & DAG ) { if ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) return addRequiredExtensionForVectorMULL ( N -> getOperand ( <NUM_LIT> ) , DAG , N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) , N -> getValueType ( <NUM_LIT> ) , N -> getOpcode ( ) ) ; assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ;

unsigned NumElts = VT . getVectorNumElements ( ) ;


<s> bool <ISA_LIT>AsmParser :: emit ( MCInst & Inst , SMLoc const & Loc , MCStreamer & Out ) const { Inst . setLoc ( Loc ) ;


<s> <ISA_LIT>_32Relocator :: <ISA_LIT>_32Relocator ( <ISA_LIT>_32GNULDBackend & pParent , const LinkerConfig & pConfig ) : <ISA_LIT>Relocator ( pConfig ) , m_Target ( pParent ) {


<s> StringRef getPassName ( ) const override {


<s> static bool mips_can_change_mode_class ( machine_mode from , machine_mode to , reg_class_t rclass ) {

if ( GET_MODE_SIZE ( from ) == <NUM_LIT> && GET_MODE_SIZE ( to ) == <NUM_LIT> && INTEGRAL_MODE_P ( from ) && INTEGRAL_MODE_P ( to ) ) return true ;


<s> for ( int i = ( Size - <NUM_LIT> ) * <NUM_LIT> ; i >= <NUM_LIT> ; i -= <NUM_LIT> ) EmitByte ( ( Val >> i ) & <NUM_LIT> , CurByte , OS ) ;


<s> <ISA_LIT>ELFStreamer ( MCContext & Context , MCTargetStreamer * TargetStreamer , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , bool IsThumb ) : MCELFStreamer ( Context , TargetStreamer , TAB , OS , Emitter ) , IsThumb ( IsThumb ) , MappingSymbolCounter ( <NUM_LIT> ) , LastEMS ( EMS_None ) { Reset ( ) ;


<s> case <STR_LIT> : { uint64_t TopLabel = ControlFlowCounter ++ ; ControlFlowStack . push_back ( std :: make_pair ( ControlFlowCounter ++ , false ) ) ; printAnnotation ( OS , <STR_LIT> + utostr ( TopLabel ) + ':' ) ; ControlFlowStack . push_back ( std :: make_pair ( TopLabel , true ) ) ; break ; } case <STR_LIT> : ControlFlowStack . push_back ( std :: make_pair ( ControlFlowCounter ++ , false ) ) ; break ; case <STR_LIT> : ControlFlowStack . pop_back ( ) ; printAnnotation ( OS , <STR_LIT> + utostr ( ControlFlowStack . pop_back_val ( ) . first ) + ':' ) ; break ; case <STR_LIT> : printAnnotation ( OS , <STR_LIT> + utostr ( ControlFlowStack . pop_back_val ( ) . first ) + ':' ) ; break ; } unsigned NumFixedOperands = Desc . NumOperands ; SmallSet < uint64_t , <NUM_LIT> > Printed ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i < e ; ++ i ) { const MCOperandInfo & Info = Desc . OpInfo [ i ] ; if ( ! ( i < NumFixedOperands ? ( Info . OperandType == <STR_LIT> ) : ( Desc . TSFlags & <STR_LIT> ) ) ) continue ; uint64_t Depth = MI -> getOperand ( i ) . getImm ( ) ; if ( ! Printed . insert ( Depth ) . second ) continue ; const auto & Pair = ControlFlowStack . rbegin ( ) [ Depth ] ; printAnnotation ( OS , utostr ( Depth ) + <STR_LIT> + ( Pair . second ? <STR_LIT> : <STR_LIT> ) + <STR_LIT> + utostr ( Pair . first ) ) ;


<s> continue ; } int Input = Idx / NumLaneElems ; Idx -= Input * NumLaneElems ; unsigned OpNo ; for ( OpNo = <NUM_LIT> ; OpNo < array_lengthof ( InputUsed ) ; ++ OpNo ) { if ( InputUsed [ OpNo ] == Input ) break ; if ( InputUsed [ OpNo ] < <NUM_LIT> ) { InputUsed [ OpNo ] = Input ; break ; } } if ( OpNo >= array_lengthof ( InputUsed ) ) { UseBuildVector = true ; break ; } Mask . push_back ( Idx + OpNo * NumLaneElems ) ; } if ( UseBuildVector ) { SmallVector < SDValue , <NUM_LIT> > SVOps ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i + LaneStart ) ; if ( Idx < <NUM_LIT> ) { SVOps . push_back ( DAG . getUNDEF ( EltVT ) ) ; continue ; } int Input = Idx / NumElems ; Idx -= Input * NumElems ; SVOps . push_back ( DAG . getNode ( <STR_LIT> , dl , EltVT , SVOp -> getOperand ( Input ) , DAG . getIntPtrConstant ( Idx ) ) ) ; } Output [ l ] = DAG . getNode ( <STR_LIT> , dl , NVT , & SVOps [ <NUM_LIT> ] , SVOps . size ( ) ) ; } else if ( InputUsed [ <NUM_LIT> ] < <NUM_LIT> ) { Output [ l ] = DAG . getUNDEF ( NVT ) ; } else { SDValue Op0 = Extract128BitVector ( SVOp -> getOperand ( InputUsed [ <NUM_LIT> ] / <NUM_LIT> ) , ( InputUsed [ <NUM_LIT> ] % <NUM_LIT> ) * NumLaneElems , DAG , dl ) ; SDValue Op1 = ( InputUsed [ <NUM_LIT> ] < <NUM_LIT> ) ? DAG . getUNDEF ( NVT ) :


<s> SrcBBSym = MCBinaryExpr :: createAdd ( SrcBBSym , One , Ctx ) ; if ( MO . getTargetFlags ( ) == <ISA_LIT>InstrInfo :: MO_LONG_BRANCH_FORWARD ) return MCBinaryExpr :: createSub ( DestBBSym , SrcBBSym , Ctx ) ; assert ( MO . getTargetFlags ( ) == <ISA_LIT>InstrInfo :: MO_LONG_BRANCH_BACKWARD ) ; return MCBinaryExpr :: createSub ( SrcBBSym , DestBBSym , Ctx ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> PredReg = MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ;

return ( <STR_LIT> ) MI . getOperand ( PIdx ) . getImm ( ) ;


<s> Data64bitsDirective = <NUM_LIT> ; CommentString = <STR_LIT> ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: SjLj ;


<s> switch ( REG_NOTE_KIND ( link ) ) { default : dep = <STR_LIT> ; break ; case REG_DEP_TRUE : dep = <STR_LIT> ; break ; case REG_DEP_OUTPUT : dep = <STR_LIT> ; break ; case REG_DEP_ANTI : dep = <STR_LIT> ; break ; }

fprintf ( stderr , <STR_LIT> <STR_LIT> , ret , cost , dep ) ;


<s> <ISA_LIT>PromoteAllocaToVectorPass ( TargetMachine & TM ) : TM ( TM ) {


<s> pandn_uw ( uint32x2_t s , uint32x2_t t ) {

return __builtin_loongson_pandn_uw ( s , t ) ;


<s> bool isMUBUF ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> static int nds32_register_move_cost ( machine_mode mode ATTRIBUTE_UNUSED , reg_class_t from , reg_class_t to ) { if ( from == HIGH_REGS || to == HIGH_REGS ) return <NUM_LIT> ;


<s> return makeArrayRef ( <STR_LIT> . begin ( ) , <STR_LIT> . getNumRegs ( ) ) ;


<s> for ( Module :: const_global_iterator I = M . global_begin ( ) , E = M . global_end ( ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddrMode4 ( SDNode * Op , SDValue N , SDValue & Addr , SDValue & Mode ) { Addr = N ;

Mode = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & OS ) { if ( AsmVariant != <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; if ( ! AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , OS ) ) return false ; if ( ! ExtraCode ) { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; switch ( MO . getType ( ) ) { case MachineOperand :: MO_Immediate : OS << MO . getImm ( ) ; return false ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_Register : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : assert ( <NUM_LIT> && <STR_LIT> ) ; return false ; default :


<s> unsigned Size = TD . getTypeAllocSize ( CPs [ i ] . getType ( ) ) ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; unsigned Align = CPs [ i ] . getAlignment ( ) ; assert ( isPowerOf2_32 ( Align ) && <STR_LIT> ) ; assert ( ( Size % Align ) == <NUM_LIT> && <STR_LIT> ) ; unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , i ) ) ; ++ NumCPEs ; DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> << Align << '\n' ) ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT ) const { return <STR_LIT> ;


<s> assert ( Offset + Size <= Data . size ( ) && <STR_LIT> ) ; Value = extractBitsForFixup ( Kind , Value ) ; if ( BitSize < <NUM_LIT> ) Value &= ( ( uint64_t ) <NUM_LIT> << BitSize ) - <NUM_LIT> ; unsigned ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned I = <NUM_LIT> ; I != Size ; ++ I ) { Data [ Offset + I ] |= uint8_t ( Value >> ShiftValue ) ; ShiftValue -= <NUM_LIT> ; }


<s> static bool helper_use_relative_reloc ( const ResolveInfo & pSym , const <ISA_LIT>Relocator & pFactory ) {

if ( pSym . isDyn ( ) || pSym . isUndef ( ) || pFactory . getTarget ( ) . isSymbolPreemptible ( pSym ) ) return false ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;


<s> x = gen_rtx_AND ( vmode , scratch , mask ) ; emit_insn ( gen_rtx_SET ( scratch , x ) ) ; dest = mask ; op0 = lowpart_subreg ( vmode , op0 , mode ) ; x = gen_rtx_NOT ( vmode , dest ) ; x = gen_rtx_AND ( vmode , x , op0 ) ; emit_insn ( gen_rtx_SET ( dest , x ) ) ; } else { if ( REGNO ( op1 ) == REGNO ( scratch ) ) { x = gen_rtx_AND ( vmode , scratch , mask ) ; } else { gcc_assert ( REGNO ( mask ) == REGNO ( scratch ) ) ; op1 = lowpart_subreg ( vmode , op1 , mode ) ; x = gen_rtx_AND ( vmode , scratch , op1 ) ; } emit_insn ( gen_rtx_SET ( scratch , x ) ) ; if ( REGNO ( op0 ) == REGNO ( dest ) ) { dest = lowpart_subreg ( vmode , op0 , mode ) ; x = gen_rtx_AND ( vmode , dest , nmask ) ; }


<s> addPass ( create<ISA_LIT>RemoveExtendOps ( get<ISA_LIT>TargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ;

addPass ( create<ISA_LIT>Peephole ( ) ) ;


<s> if ( IsDereferenceable ) F |= MachineMemOperand :: MODereferenceable ; if ( IsInvariant ) F |= MachineMemOperand :: MOInvariant ; return F ;


<s> unsigned N = countTrailingOnes ( STReturns ) ; assert ( STReturns == <NUM_LIT> || ( isMask_32 ( STReturns ) && N <= <NUM_LIT> ) ) ;

for ( unsigned I = <NUM_LIT> ; I < N ; ++ I ) pushReg ( N - I - <NUM_LIT> ) ;


<s> static __inline qword si_from_uchar ( unsigned char c ) { union { qword q ;


<s> unsigned numRegs = info -> getNumRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numRegs ; ++ i ) {

const char * regName = info -> getName ( i ) ;


<s> int i ; if ( GET_CODE ( dep_rtx ) == SET && addr_generation_dependency_p ( dep_rtx , insn ) ) return <NUM_LIT> ; else if ( GET_CODE ( dep_rtx ) == PARALLEL ) { for ( i = <NUM_LIT> ; i < XVECLEN ( dep_rtx , <NUM_LIT> ) ; i ++ ) { if ( addr_generation_dependency_p ( XVECEXP ( dep_rtx , <NUM_LIT> , i ) , insn ) ) return <NUM_LIT> ;