<s> CurrentSize = Type . first ; IsTypeCorrect = true ; break ; } } if ( ! IsTypeCorrect ) { std :: string SuffixMsg = <STR_LIT> ; for ( auto It = <ISA_LIT>MetadataTypeDirectives . begin ( ) ; It != <ISA_LIT>MetadataTypeDirectives . end ( ) ; ++ It ) { SuffixMsg += formatv ( <STR_LIT> , It -> second ) ; if ( std :: next ( It ) != <ISA_LIT>MetadataTypeDirectives . end ( ) ) SuffixMsg += <STR_LIT> ; else SuffixMsg += '.' ; } Error ( Tok . getLoc ( ) , Twine ( <ISA_LIT>HeaderParseBaseError , Tok . getString ( ) ) . concat ( SuffixMsg ) , Tok . getLocRange ( ) ) ; return false ; } if ( CurrentSize != ExpectedSize ) { assert ( <ISA_LIT>MetadataTypeDirectives . find ( ExpectedSize ) != <ISA_LIT>MetadataTypeDirectives . end ( ) ) ; std :: string SuffixMsg = formatv ( <STR_LIT> , <ISA_LIT>MetadataTypeDirectives . at ( ExpectedSize ) ) ;


<s> std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( Src -> isVectorTy ( ) && Alignment != <NUM_LIT> && Src -> getVectorElementType ( ) -> isDoubleTy ( ) ) { return LT . first * <NUM_LIT> ; } return LT . first ;


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : FramePointerSaveIndex ( <NUM_LIT> ) , ReturnAddrSaveIndex ( <NUM_LIT> ) , HasSpills ( false ) , HasNonRISpills ( false ) , SpillsCR ( false ) , LRStoreRequired ( false ) , MinReservedArea ( <NUM_LIT> ) , TailCallSPDelta ( <NUM_LIT> ) , HasFastCall ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , VarArgsStackOffset ( <NUM_LIT> ) , VarArgsNumGPR ( <NUM_LIT> ) , VarArgsNumFPR ( <NUM_LIT> ) , CRSpillFrameIndex ( <NUM_LIT> ) {


<s> Value * Offset [ <NUM_LIT> ] = { ConstantInt :: get ( Int32Type , <NUM_LIT> ) , ConstantInt :: get ( Int32Type , <NUM_LIT> ) , ConstantInt :: get ( Int32Type , <NUM_LIT> ) } ; bool useShadowVariant ; getAdjustmentFromTextureTarget ( TextureType , hasLOD , SrcSelect , CT , useShadowVariant ) ; ReplaceCallInst ( I , FT , useShadowVariant ? ShadowInt : VanillaInt , SrcSelect , Offset , ResourceId , SamplerId , CT , Coord ) ;


<s> std :: unique_ptr < WinEHFuncInfo > FuncInfoPtr ; if ( ! MMI ) FuncInfoPtr . reset ( new WinEHFuncInfo ( ) ) ; WinEHFuncInfo & FuncInfo = * ( MMI ? & MMI -> getWinEHFuncInfo ( & F ) : FuncInfoPtr . get ( ) ) ; FuncInfo . EHRegNode = RegNode ; switch ( Personality ) { default : llvm_unreachable ( <STR_LIT> ) ; case EHPersonality :: MSVC_CXX : addCXXStateStores ( F , FuncInfo ) ; break ; case EHPersonality :: MSVC_<ISA_LIT>SEH :


<s> IsRightShift = true ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = true ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; IsRightShift = false ; break ; } if ( IsRightShift && ShiftAmount <= - <NUM_LIT> && ShiftAmount >= - ( int ) ElemBits ) return DAG . getNode ( Opcode , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( - ShiftAmount , <STR_LIT> ) ) ;

else if ( ! IsRightShift && ShiftAmount >= <NUM_LIT> && ShiftAmount <= ElemBits ) return DAG . getNode ( Opcode , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ShiftAmount , <STR_LIT> ) ) ;


<s> tmp = gen_rtx_EXPR_LIST ( VOIDmode , tmp , const0_rtx ) ; tmp = gen_rtx_PARALLEL ( orig_mode , gen_rtvec ( <NUM_LIT> , tmp ) ) ; }


<s> if ( Src . isUndef ( ) || <STR_LIT> ( Mask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ; Mask = DAG . getBitcast ( MaskVT , Mask ) ; MemIntrinsicSDNode * MemIntr = cast < MemIntrinsicSDNode > ( Op ) ; SDValue Ops [ ] = { Chain , Src , Mask , Base , Index , Scale } ; SDValue Res = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , VTs , Ops , MemIntr -> getMemoryVT ( ) , MemIntr -> getMemOperand ( ) ) ;

return DAG . getMergeValues ( { Res , Res . getValue ( <NUM_LIT> ) } , dl ) ;


<s> addPass ( createSROAPass ( ) ) ; addPass ( create<ISA_LIT>LowerAllocaPass ( ) ) ;

addPass ( createInferAddressSpacesPass ( ) ) ;


<s> clonei -> vecsize_float = <NUM_LIT> ; break ; case 'd' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; break ; case 'e' : clonei -> vecsize_int = <NUM_LIT> ; clonei -> vecsize_float = <NUM_LIT> ; if ( TYPE_MODE ( base_type ) == QImode ) clonei -> mask_mode = DImode ; else clonei -> mask_mode = SImode ; break ; } if ( clonei -> simdlen == <NUM_LIT> ) { if ( SCALAR_INT_MODE_P ( TYPE_MODE ( base_type ) ) ) clonei -> simdlen = clonei -> vecsize_int ; else clonei -> simdlen = clonei -> vecsize_float ; clonei -> simdlen = clonei -> simdlen / GET_MODE_BITSIZE ( TYPE_MODE ( base_type ) ) ; } else if ( clonei -> simdlen > <NUM_LIT> ) { tree ctype = ret_type ; if ( TREE_CODE ( ret_type ) == VOID_TYPE ) ctype = base_type ; int cnt = GET_MODE_BITSIZE ( TYPE_MODE ( ctype ) ) * clonei -> simdlen ; if ( SCALAR_INT_MODE_P ( TYPE_MODE ( ctype ) ) ) cnt /= clonei -> vecsize_int ; else cnt /= clonei -> vecsize_float ; if ( cnt > ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ) {

if ( explicit_p ) warning_at ( DECL_SOURCE_LOCATION ( node -> decl ) , <NUM_LIT> , <STR_LIT> , clonei -> simdlen . to_constant ( ) ) ;


<s> PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( PR ) ; initializeWinEHStatePassPass ( PR ) ; initializeFixupBWInstPassPass ( PR ) ; initializeEvexToVexInstPassPass ( PR ) ;


<s> long double __negxf2 ( long double x1 ) {


<s> HighBitsOf32BitAddress = YamlMFI . HighBitsOf32BitAddress ; IsEntryFunction = YamlMFI . IsEntryFunction ; NoSignedZerosFPMath = YamlMFI . NoSignedZerosFPMath ; MemoryBound = YamlMFI . MemoryBound ; WaveLimiter = YamlMFI . WaveLimiter ; HasSpilledSGPRs = YamlMFI . HasSpilledSGPRs ;

HasSpilledVGPRs = YamlMFI . HasSpilledVGPRs ;


<s> case FK_Data_4 : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : Value -= <NUM_LIT> ; break ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ;


<s> const <ISA_LIT>TargetObjectFile & TLOF = static_cast < const <ISA_LIT>TargetObjectFile & > ( getObjFileLowering ( ) ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) { return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> MCSymbol * MCSym ; if ( ACPV -> isLSDA ( ) ) { MCSym = getCurExceptionSym ( ) ; } else if ( ACPV -> isBlockAddress ( ) ) { const BlockAddress * BA = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) ; MCSym = GetBlockAddressSymbol ( BA ) ; } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) ; unsigned char TF = Subtarget -> isTargetMachO ( ) ? <STR_LIT> : <NUM_LIT> ; MCSym = Get<ISA_LIT>GVSymbol ( GV , TF ) ; } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; auto Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL . getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: createAdd ( PCRelExpr , MCConstantExpr :: create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; OutStreamer -> EmitLabel ( DotSym ) ; const MCExpr * DotExpr = MCSymbolRefExpr :: create ( DotSym , OutContext ) ; PCRelExpr = MCBinaryExpr :: createSub ( PCRelExpr , DotExpr , OutContext ) ;


<s> case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ; if ( ! Reg ) continue ; for ( MCRegAliasIterator AI ( Reg , & TRI , true ) ; AI . isValid ( ) ; ++ AI ) Uses . insert ( * AI ) ; } const uint16_t * CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit ; for ( ; * CS ; ++ CS ) if ( ! Uses . count ( * CS ) ) return * CS ; } } return <NUM_LIT> ;


<s> return hasTinyEncoding ( ) ? <NUM_LIT> : <NUM_LIT> ;


<s> void <ISA_LIT>DAGToDAGISel :: transferMemOperands ( SDNode * N , SDNode * Result ) { MachineMemOperand * MemOp = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Result ) , { MemOp } ) ;


<s> case InlineAsm :: Constraint_ZC : if ( Subtarget -> inMicro<ISA_LIT>Mode ( ) ) { if ( selectAddrRegImm12 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } } else if ( Subtarget -> has<ISA_LIT>32r6 ( ) ) { if ( selectAddrRegImm9 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } } else if ( selectAddrRegImm16 ( Op , Base , Offset ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Offset ) ; return false ; } OutOps . push_back ( Op ) ; OutOps . push_back ( CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ) ;


<s> CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= ( Value & Mask ) << TargetOffset ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) {

unsigned Idx = IsLittle ? i : ( FullSize - <NUM_LIT> - i ) ;


<s> int64_t Done = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; int64_t VM = getConstant ( MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; BuildMI ( * BB , & I , DL , TII . get ( <STR_LIT> ) , Undef ) ; MachineInstr * Exp = buildEXP ( TII , & I , Tgt , Reg0 , Reg1 , Undef , Undef , VM , true , Enabled , Done ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * Exp , TII , TRI , RBI ) ; } case <STR_LIT> : { BuildMI ( * BB , & I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) ; Register Reg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; I . eraseFromParent ( ) ; if ( ! MRI . getRegClassOrNull ( Reg ) ) MRI . setRegClass ( Reg , TRI . getWaveMaskRegClass ( ) ) ; return true ; } default : return selectImpl ( I , * CoverageInfo ) ;


<s> DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) && ( isZeroImm ( MI . getOperand ( <NUM_LIT> ) ) ) ) { DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> BasicBlock :: iterator ItNew = getEntryIns ( UI ) ; Function * UCallee = UI -> getCalledFunction ( ) ; Type * RetType = UCallee -> getReturnType ( ) ;


<s> unsigned RegClassBase = OpInfo [ <NUM_LIT> ] . RegClass ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRd ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassPair , decodeRs ( insn ) ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassBase , decodeRn ( insn ) ) ) ) ; int Offset = getImm8 ( insn ) * <NUM_LIT> ; if ( getUBit ( insn ) == <NUM_LIT> ) Offset = - Offset ; MI . addOperand ( MCOperand :: CreateImm ( Offset ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>LDCleanupPass ( <ISA_LIT>TargetMachine & TM ) {


<s> const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator I = ++ MBB -> getIterator ( ) ; MachineBasicBlock * thisMBB = MBB ; MachineFunction * MF = MBB -> getParent ( ) ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * fallMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , fallMBB ) ; MF -> insert ( I , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ;

MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ;


<s> MachineInstr * Branch = & ( * TI ) ; MachineFunction * MF = IfEntry -> getParent ( ) ; MachineRegisterInfo & MRI = IfEntry -> getParent ( ) -> getRegInfo ( ) ; if ( Branch -> getOpcode ( ) == <STR_LIT> ) { unsigned DstReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr * <ISA_LIT>IF = BuildMI ( * MF , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * <ISA_LIT>END = BuildMI ( * MF , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( DstReg ) ;


<s> rtx regbuf ; ns = cfun -> machine -> arg_regs_to_save ; if ( TARGET_IVC2 ) { bufsize = <NUM_LIT> * ( ( ns + <NUM_LIT> ) / <NUM_LIT> ) + <NUM_LIT> * ns ; regbuf = assign_stack_local ( SImode , bufsize , <NUM_LIT> ) ; } else { bufsize = ns * <NUM_LIT> ; regbuf = assign_stack_local ( SImode , bufsize , <NUM_LIT> ) ; } move_block_from_reg ( <NUM_LIT> - ns , regbuf , ns ) ; if ( TARGET_IVC2 ) { rtx tmp = gen_rtx_MEM ( DImode , XEXP ( regbuf , <NUM_LIT> ) ) ; int ofs = <NUM_LIT> * ( ( ns + <NUM_LIT> ) / <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < ns ; i ++ ) { int rn = ( <NUM_LIT> - ns ) + i + <NUM_LIT> ; rtx ptr ; ptr = offset_address ( tmp , GEN_INT ( ofs ) , <NUM_LIT> ) ; emit_move_insn ( ptr , gen_rtx_REG ( DImode , rn ) ) ;


<s> static bool MaskRegClassContains ( unsigned Reg ) { return <STR_LIT> . contains ( Reg ) ;


<s> MF -> insert ( ++ MBB -> getIterator ( ) , ContBB ) ; ContBB -> splice ( ContBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; ContBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MachineBasicBlock * TrapBB = MF -> CreateMachineBasicBlock ( ) ; MF -> push_back ( TrapBB ) ; BuildMI ( TrapBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; MBB -> addSuccessor ( TrapBB ) ; BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( TrapBB ) ;

AddDefaultPred ( BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( ContBB ) ) ;


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> tryParseRegisterOperand ( SmallVectorImpl < MCParsedAsmOperand * > & Operands , StringRef Mnemonic ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ; int RegNo = - <NUM_LIT> ; if ( ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) && Operands . size ( ) == <NUM_LIT> && Parser . getTok ( ) . is ( AsmToken :: Integer ) ) { RegNo = Parser . getTok ( ) . getIntVal ( ) ; if ( RegNo == <NUM_LIT> ) RegNo = <STR_LIT> ; } else RegNo = tryParseRegister ( Mnemonic ) ;

if ( RegNo == - <NUM_LIT> ) return true ;


<s> void <ISA_LIT>TargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; MCA . setELFHeaderEFlags ( getEFlags ( ) ) ; std :: string Blob ;

const char * Vendor = getPALMetadata ( ) -> getVendor ( ) ;


<s> const MCExpr * Expr = MCSymbolRefExpr :: create ( getSymbol ( GV ) , Ctx ) ; return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM , Expr , false , Ctx ) ; }


<s> uint16_t Flags = RA . Addr -> getFlags ( ) | NodeAttrs :: Shadow ; auto IsShadow = [ Flags ] ( NodeAddr < RefNode * > TA ) -> bool { return TA . Addr -> getFlags ( ) == Flags ; } ; return locateNextRef ( IA , RA , IsShadow ) . second ;


<s> MachineFunctionProperties getRequiredProperties ( ) const override {

return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ;


<s> MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI , IsLittleEndian ) ; return createELFObjectWriter ( MOTW , OS , IsLittleEndian ) ;


<s> static tree rs6000_fold_builtin ( tree fndecl ATTRIBUTE_UNUSED , int n_args ATTRIBUTE_UNUSED , tree * args ATTRIBUTE_UNUSED , bool ignore ATTRIBUTE_UNUSED ) {

return SUBTARGET_FOLD_BUILTIN ( fndecl , n_args , args , ignore ) ;


<s> for ( unsigned i = <NUM_LIT> , e = NumElems / <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + NumElems ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> , e = NumElems ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ;


<s> Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; } else if ( VT == <STR_LIT> && N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) { Opd0 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; TruncBits = Opd0 -> getValueType ( <NUM_LIT> ) . getSizeInBits ( ) - VT . getSizeInBits ( ) ; VT = Opd0 . getValueType ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; } else if ( BiggerPattern ) { Opd0 = N -> getOperand ( <NUM_LIT> ) ; } else return false ; if ( ShlImm >= VT . getSizeInBits ( ) ) { DEBUG ( ( dbgs ( ) << N << <STR_LIT> ) ) ; return false ; }


<s> int i ; def_align = <NUM_LIT> ; m68k_align_loops = def_align ; if ( m68k_align_loops_string ) { i = atoi ( m68k_align_loops_string ) ; if ( i < <NUM_LIT> || i > MAX_CODE_ALIGN ) error ( <STR_LIT> , i , MAX_CODE_ALIGN ) ; else m68k_align_loops = i ; } m68k_align_jumps = def_align ; if ( m68k_align_jumps_string ) { i = atoi ( m68k_align_jumps_string ) ; if ( i < <NUM_LIT> || i > MAX_CODE_ALIGN ) error ( <STR_LIT> , i , MAX_CODE_ALIGN ) ; else m68k_align_jumps = i ; } m68k_align_funcs = def_align ; if ( m68k_align_funcs_string ) { i = atoi ( m68k_align_funcs_string ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , { } , <STR_LIT> ) } ) ; } else { unsigned Opc = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; CurDAG -> SelectNodeTo ( N , Opc , N -> getVTList ( ) , { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ) ;


<s> DFAPacketizer * <ISA_LIT>InstrInfo :: CreateTargetScheduleState ( const TargetSubtargetInfo & STI ) const { const InstrItineraryData * II = STI . getInstrItineraryData ( ) ; return static_cast < const <ISA_LIT>Subtarget & > ( STI ) . createDFAPacketizer ( II ) ;


<s> <ISA_LIT>TargetWinCOFFStreamer ( llvm :: MCStreamer & S ) : <ISA_LIT>TargetStreamer ( S ) {


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const {


<s> if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) { if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ;


<s> InlineAsmIdentifierInfo Info ; StringRef Identifier = Tok . getString ( ) ; if ( ParseIntelIdentifier ( Val , Identifier , Info , false , End ) ) return nullptr ; if ( ! getLexer ( ) . is ( AsmToken :: LBrac ) ) return CreateMemForInlineAsm ( <NUM_LIT> , Val , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , Start , End , Size , Identifier , Info ) ; Parser . Lex ( ) ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( ParseIntelExpression ( SM , End ) ) return nullptr ; if ( SM . getSym ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getBaseReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; } if ( SM . getIndexReg ( ) ) { Error ( Start , <STR_LIT> ) ; return nullptr ; }

const MCExpr * Disp = MCConstantExpr :: Create ( SM . getImm ( ) , getContext ( ) ) ;


<s> SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Shamt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Shift31 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , ShiftRightHi , Or ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Cond , IsSRA ? Shift31 : DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftRightHi ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ;

return DAG . getMergeValues ( Ops , DL ) ;


<s> <ISA_LIT>16InstrInfo :: <ISA_LIT>16InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>InstrInfo ( STI , <STR_LIT> ) {


<s> } if ( Mask [ i ] == SM_SentinelZero || Mask [ i + <NUM_LIT> ] == SM_SentinelZero ) { if ( ( Mask [ i ] == SM_SentinelZero || Mask [ i ] == SM_SentinelUndef ) && ( Mask [ i + <NUM_LIT> ] == SM_SentinelZero || Mask [ i + <NUM_LIT> ] == SM_SentinelUndef ) ) { WidenedMask [ i / <NUM_LIT> ] = SM_SentinelZero ; continue ; } return false ; } if ( Mask [ i ] != SM_SentinelUndef && Mask [ i ] % <NUM_LIT> == <NUM_LIT> && Mask [ i ] + <NUM_LIT> == Mask [ i + <NUM_LIT> ] ) { WidenedMask [ i / <NUM_LIT> ] = Mask [ i ] / <NUM_LIT> ;


<s> if ( Enable<ISA_LIT>SlrGeneration ) { if ( SDValue Res = tryLowerToSLI ( Op . getNode ( ) , DAG ) ) return Res ; } SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; if ( ! BVN ) {


<s> AVL = Op -> getOperand ( AVLIdx ) ; } else { AVL = CDAG . getConstant ( OpVecVT . getVectorNumElements ( ) , <STR_LIT> ) ; SDValue ConstTrue = CDAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; Mask = CDAG . getBroadcast ( MaskVT , ConstTrue , AVL ) ; } if ( isVVPBinaryOp ( VVPOpcode ) ) { assert ( LegalVecVT . isSimple ( ) ) ; return CDAG . getNode ( VVPOpcode , LegalVecVT , { Op -> getOperand ( <NUM_LIT> ) , Op -> getOperand ( <NUM_LIT> ) , Mask , AVL } ) ; } if ( VVPOpcode == <STR_LIT> ) { auto Mask = Op -> getOperand ( <NUM_LIT> ) ;

auto OnTrue = Op -> getOperand ( <NUM_LIT> ) ;


<s> rtx offset ; for ( c = pool -> execute ; c != NULL ; c = c -> next ) if ( INSN_UID ( insn ) == INSN_UID ( c -> value ) ) break ;


<s> int FrameIndex = StoreByValRegs ( CCInfo , DAG , dl , Chain , nullptr , CCInfo . getInRegsParamsCount ( ) , <NUM_LIT> , ArgOffset , <NUM_LIT> , ForceMutable , <NUM_LIT> , TotalArgRegsSaveSize ) ;

AFI -> setVarArgsFrameIndex ( FrameIndex ) ;


<s> if ( NumElems != <NUM_LIT> ) return false ; int QuarterSize = NumElems / <NUM_LIT> ; int HalfSize = QuarterSize * <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < QuarterSize ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , <NUM_LIT> , HalfSize ) ) return false ; for ( int i = QuarterSize ; i < QuarterSize * <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , NumElems , NumElems + HalfSize ) ) return false ; for ( int i = QuarterSize * <NUM_LIT> ; i < QuarterSize * <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , HalfSize , NumElems ) ) return false ; for ( int i = QuarterSize * <NUM_LIT> ; i < NumElems ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , NumElems + HalfSize , NumElems * <NUM_LIT> ) ) return false ;


<s> void addImm8s4Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;


<s> FOR_EACH_INSN_DEF ( ref , insn ) if ( HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) && ! DF_REF_FLAGS_IS_SET ( ref , DF_REF_MUST_CLOBBER ) && DF_REF_REGNO ( ref ) != FLAGS_REG ) return true ; FOR_EACH_INSN_USE ( ref , insn ) if ( ! DF_REF_REG_MEM_P ( ref ) && HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) ) return true ; return false ;


<s> static SDValue combineExtSetcc ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ; if ( ! Subtarget . hasAVX512 ( ) || ! VT . isVector ( ) || N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; EVT SVT = VT . getVectorElementType ( ) ; if ( SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> && SVT != <STR_LIT> ) return SDValue ( ) ; unsigned Size = VT . getSizeInBits ( ) ;

if ( Size > <NUM_LIT> ) return SDValue ( ) ;


<s> const LLT S16 = LLT :: scalar ( <NUM_LIT> ) ; LLT StoreVT = MRI . getType ( Reg ) ; if ( ! StoreVT . isVector ( ) || StoreVT . getElementType ( ) != S16 ) return Reg ; auto Unmerge = B . buildUnmerge ( S16 , Reg ) ;

SmallVector < Register , <NUM_LIT> > WideRegs ;


<s> if ( any_offset_symbol_operand ( sym , mode ) ) addend = <NUM_LIT> ; else if ( aligned_offset_symbol_operand ( sym , mode ) ) { HOST_WIDE_INT addend_lo , addend_hi ; addend_lo = ( ( addend & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ; addend_hi = addend - addend_lo ; if ( addend_lo != <NUM_LIT> ) { op1 = plus_constant ( mode , sym , addend_hi ) ; addend = addend_lo ; } else addend = <NUM_LIT> ; } else op1 = sym ; if ( reload_completed ) { gcc_assert ( addend == <NUM_LIT> ) ; if ( ia64_expand_load_address ( op0 , op1 ) ) return NULL_RTX ; } if ( addend ) { rtx subtarget = ! can_create_pseudo_p ( ) ? op0 : gen_reg_rtx ( mode ) ;

emit_insn ( gen_rtx_SET ( subtarget , op1 ) ) ;


<s> return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectIToFP ( I , true ) ; case Instruction :: UIToFP : return SelectIToFP ( I , false ) ; case Instruction :: FPToSI : return SelectFPToI ( I , true ) ; case Instruction :: FPToUI : return SelectFPToI ( I , false ) ; case Instruction :: Add : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Call : if ( dyn_cast < IntrinsicInst > ( I ) ) return false ; return SelectCall ( I ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction :: Trunc :


<s> bool nds32_valid_CVp5_p ( rtx op ) { HOST_WIDE_INT ival = const_vector_to_hwint ( op ) ;

return ( ival < ( ( <NUM_LIT> << <NUM_LIT> ) + <NUM_LIT> ) ) && ( ival >= ( <NUM_LIT> + <NUM_LIT> ) ) ;


<s> while ( Count > <NUM_LIT> ) { int Arg ; if ( Count >= <NUM_LIT> ) Arg = <NUM_LIT> ; else Arg = Count - <NUM_LIT> ; Count -= <NUM_LIT> ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addImm ( Arg ) ;


<s> bool useNEONForSinglePrecisionFP ( ) const {

return hasNEON ( ) && UseNEONForSinglePrecisionFP ; }


<s> static SDValue getVShift ( bool isLeft , EVT VT , SDValue SrcOp , unsigned NumBits , SelectionDAG & DAG , const TargetLowering & TLI , SDLoc dl ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; EVT ShVT = <STR_LIT> ; unsigned Opc = isLeft ? <STR_LIT> : <STR_LIT> ; SrcOp = DAG . getNode ( <STR_LIT> , dl , ShVT , SrcOp ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opc , dl , ShVT , SrcOp , DAG . getConstant ( NumBits , TLI . getScalarShiftAmountTy ( SrcOp . getValueType ( ) ) ) ) ) ;


return __builtin_mve_vmvnq_n_sv8hi ( __imm ) ;


<s> return static_cast < MCELFStreamer & > ( Streamer ) ;


<s> DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstReg ) . addFrameIndex ( FrameIndex ) ;


<s> if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; SDValue LHS ; uint32_t ShiftLHS = <NUM_LIT> ; bool LHSFromHi = <NUM_LIT> ; if ( ! findEXTRHalf ( N -> getOperand ( <NUM_LIT> ) , LHS , ShiftLHS , LHSFromHi ) ) return SDValue ( ) ; SDValue RHS ; uint32_t ShiftRHS = <NUM_LIT> ; bool RHSFromHi = <NUM_LIT> ; if ( ! findEXTRHalf ( N -> getOperand ( <NUM_LIT> ) , RHS , ShiftRHS , RHSFromHi ) ) return SDValue ( ) ; if ( LHSFromHi == RHSFromHi ) return SDValue ( ) ; if ( ShiftLHS + ShiftRHS != VT . getSizeInBits ( ) ) return SDValue ( ) ; if ( LHSFromHi ) { std :: swap ( LHS , RHS ) ; std :: swap ( ShiftLHS , ShiftRHS ) ;


<s> unsigned Opc = MI -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { const MachineOperand * Src0 = TII -> getNamedOperand ( * MI , <STR_LIT> :: src0 ) ; const MachineOperand * Src1 = TII -> getNamedOperand ( * MI , <STR_LIT> :: src1 ) ; if ( Src1 -> isIdenticalTo ( * Src0 ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; int Src2Idx = <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ; if ( Src2Idx != - <NUM_LIT> ) MI -> RemoveOperand ( Src2Idx ) ; MI -> RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src1 ) ) ;

mutateCopyOp ( * MI , TII -> get ( Src0 -> isReg ( ) ? ( unsigned ) <STR_LIT> : getMovOpc ( false ) ) ) ;


<s> ShapeSwitch ( Root , [ & ] ( SimpleShape * Simple ) { MultipleShape * Fused = dyn_cast < MultipleShape > ( Root -> Next ) ; if ( Fused && Fused -> Breaks ) LoopStack . push ( Fused ) ; if ( Simple -> Inner -> BranchVar ) LoopStack . push ( nullptr ) ; if ( Fused ) { if ( Fused -> UseSwitch ) LoopStack . push ( nullptr ) ; for ( const auto & iter : Fused -> InnerMap ) { FindLabeledLoops ( iter . second ) ; } } for ( const auto & iter : Simple -> Inner -> ProcessedBranchesOut ) { Branch * Details = iter . second . get ( ) ; if ( Details -> Type == Branch :: Break || Details -> Type == Branch :: Continue ) { assert ( ! LoopStack . empty ( ) ) ; if ( Details -> Ancestor != LoopStack . top ( ) && Details -> Labeled ) { if ( MultipleShape * Multiple = dyn_cast < MultipleShape > ( Details -> Ancestor ) ) { Multiple -> Labeled = true ; } else { LoopShape * Loop = cast < LoopShape > ( Details -> Ancestor ) ; Loop -> Labeled = true ; } } else { Details -> Labeled = false ;


<s> MachineInstr * newHeadMI = TII -> duplicate ( tailMI , MF ) ; headMBB -> push_back ( newHeadMI ) ; } } SmallVector < MachineBasicBlock * , <NUM_LIT> > Succs ( tailMBB -> succ_begin ( ) , tailMBB -> succ_end ( ) ) ; for ( unsigned SI = <NUM_LIT> ; SI < Succs . size ( ) ; ++ SI ) { MachineBasicBlock * succ = Succs [ SI ] ; if ( ! headMBB -> isSuccessor ( succ ) ) { headMBB -> addSuccessor ( succ ) ; MachineBasicBlock :: iterator succMI ; for ( succMI = succ -> begin ( ) ; succMI != succ -> end ( ) ; ++ succMI ) { if ( ! succMI -> isPHI ( ) ) continue ; assert ( ! getPHISourceRegIndex ( * succMI , headMBB ) && <STR_LIT> ) ; const unsigned phiIndex = getPHISourceRegIndex ( * succMI , tailMBB ) ; if ( ! phiIndex ) continue ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << * succMI ) ; MachineOperand & mbbMO = succMI -> getOperand ( phiIndex + <NUM_LIT> ) ; assert ( mbbMO . isMBB ( ) && <STR_LIT> ) ; mbbMO . setMBB ( headMBB ) ; } } tailMBB -> removeSuccessor ( succ ) ; } tailMBB -> eraseFromParent ( ) ;


<s> fputs ( <STR_LIT> , file ) ; assemble_name ( file , XSTR ( XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; putc ( '\n' , file ) ;


<s> break ; case <STR_LIT> : Opc = <ISA_LIT>SubTarget -> hasSPE ( ) ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = <ISA_LIT>SubTarget -> hasSPE ( ) ? <STR_LIT> : <STR_LIT> ; break ; } unsigned IndexReg = <NUM_LIT> ; <ISA_LIT>SimplifyAddress ( Addr , UseOffset , IndexReg ) ; bool IsVSSRC = isVSSRCRegClass ( RC ) ; bool IsVSFRC = isVSFRCRegClass ( RC ) ; bool Is32VSXStore = IsVSSRC && Opc == <STR_LIT> ; bool Is64VSXStore = IsVSFRC && Opc == <STR_LIT> ; if ( ( Is32VSXStore || Is64VSXStore ) && ( Addr . BaseType != Address :: FrameIndexBase ) && UseOffset && ( Addr . Offset == <NUM_LIT> ) ) { UseOffset = false ; } if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( Is32VSXStore || Is64VSXStore ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( Is32VSXStore || Is64VSXStore ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = IsVSSRC ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = IsVSFRC ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } auto MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) ; if ( IndexReg ) MIB . addReg ( Addr . Base . Reg ) . addReg ( IndexReg ) ; else MIB . addReg ( <STR_LIT> ) . addReg ( Addr . Base . Reg ) ;


<s> MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> && ! MayFoldIntoZeroExtend ( Op ) && ! ( Subtarget . hasSSE41 ( ) && MayFoldIntoStore ( Op ) ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Idx ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Extract ) ; } if ( Subtarget . hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; if ( VT . getSizeInBits ( ) == <NUM_LIT> && Op -> isOnlyUserOf ( Vec . getNode ( ) ) ) { int DWordIdx = IdxVal / <NUM_LIT> ; if ( DWordIdx == <NUM_LIT> ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( DWordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } int WordIdx = IdxVal / <NUM_LIT> ;

SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( WordIdx , dl ) ) ;


<s> unsigned <ISA_LIT>_MC :: GetELFFlags ( const MCSubtargetInfo & STI ) { static std :: map < StringRef , unsigned > ElfFlags = { { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V4 } , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V5 } , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V55 } , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V60 } , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V62 } , { <STR_LIT> , ELF :: EF_HEXAGON_MACH_V65 } , } ; auto F = ElfFlags . find ( STI . getCPU ( ) ) ;

assert ( F != ElfFlags . end ( ) && <STR_LIT> ) ;


<s> void <ISA_LIT>PeepholeSDWA :: matchSDWAOperands ( MachineFunction & MF ) { for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) {

if ( auto Operand = matchSDWAOperand ( MI ) ) {


<s> CallFlags ( CallingConv :: ID CC , bool IsTailCall , bool IsVarArg , bool IsPatchPoint , bool IsIndirect , bool HasNest , bool NoMerge ) : CallConv ( CC ) , IsTailCall ( IsTailCall ) , IsVarArg ( IsVarArg ) , IsPatchPoint ( IsPatchPoint ) , IsIndirect ( IsIndirect ) , HasNest ( HasNest ) , NoMerge ( NoMerge ) {


<s> if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( isTargetWindows ( ) ) No<ISA_LIT> = true ; if ( isAAPCS_ABI ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; if ( isTargetMachO ( ) ) SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; else SupportsTailCall = ! isThumb1Only ( ) ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ; if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ;


<s> unsigned MaxReg = getMaxCalleeSavedReg ( CSI , HRI ) ; bool StkOvrFlowEnabled = EnableStackOVFSanitizer ; const char * SpillFun = getSpillFunctionFor ( MaxReg , SK_ToMem , StkOvrFlowEnabled ) ; auto & HTM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; bool IsPIC = HTM . getRelocationModel ( ) == Reloc :: PIC_ ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned SpillOpc ; if ( StkOvrFlowEnabled ) SpillOpc = IsPIC ? <STR_LIT> : <STR_LIT> ; else SpillOpc = IsPIC ? <STR_LIT> : <STR_LIT> ; MachineInstr * SaveRegsCall = BuildMI ( MBB , MI , DL , HII . get ( SpillOpc ) ) . addExternalSymbol ( SpillFun ) ; addCalleeSaveRegistersAsImpOperand ( SaveRegsCall , CSI , false , true ) ; for ( unsigned I = <NUM_LIT> ; I < CSI . size ( ) ; ++ I ) MBB . addLiveIn ( CSI [ I ] . getReg ( ) ) ; return true ;


<s> GlobalAddressSDNode * GA = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; if ( Subtarget -> isTargetELF ( ) ) { TLSModel :: Model model = DAG . getTarget ( ) . getTLSModel ( GV ) ; switch ( model ) { case TLSModel :: GeneralDynamic : if ( Subtarget -> is64Bit ( ) ) return LowerToTLSGeneralDynamicModel64 ( GA , DAG , getPointerTy ( ) ) ; return LowerToTLSGeneralDynamicModel32 ( GA , DAG , getPointerTy ( ) ) ; case TLSModel :: LocalDynamic : return LowerToTLSLocalDynamicModel ( GA , DAG , getPointerTy ( ) , Subtarget -> is64Bit ( ) ) ; case TLSModel :: InitialExec : case TLSModel :: LocalExec : return LowerToTLSExecModel ( GA , DAG , getPointerTy ( ) , model , Subtarget -> is64Bit ( ) , DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) ; } llvm_unreachable ( <STR_LIT> ) ; } if ( Subtarget -> isTargetDarwin ( ) ) { unsigned char OpFlag = <NUM_LIT> ; unsigned WrapperKind = Subtarget -> isPICStyleRIPRel ( ) ? <STR_LIT> : <STR_LIT> ; bool PIC32 = ( DAG . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) && ! Subtarget -> is64Bit ( ) ; if ( PIC32 ) OpFlag = <STR_LIT> ; else OpFlag = <STR_LIT> ; SDLoc DL ( Op ) ; SDValue Result = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , DL , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OpFlag ) ; SDValue Offset = DAG . getNode ( WrapperKind , DL , getPointerTy ( ) , Result ) ; if ( PIC32 ) Offset = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( ) ) , Offset ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;


<s> const uint64_t Chunk = getChunk ( Imm , FromIdx ) << ShiftAmt ; Imm &= ~ ( <NUM_LIT> << ShiftAmt ) ;


<s> Cand . AtTop = AtTop ; RegPressureTracker & TempTracker = const_cast < RegPressureTracker & > ( RPTracker ) ; std :: vector < unsigned > Pressure ; std :: vector < unsigned > MaxPressure ; if ( AtTop ) TempTracker . getDownwardPressure ( SU -> getInstr ( ) , Pressure , MaxPressure ) ; else { TempTracker . getUpwardPressure ( SU -> getInstr ( ) , Pressure , MaxPressure ) ; } unsigned NewSGPRPressure = Pressure [ SRI -> getSGPRPressureSet ( ) ] ; unsigned NewVGPRPressure = Pressure [ SRI -> getVGPRPressureSet ( ) ] ; const unsigned MaxVGPRPressureInc = <NUM_LIT> ; bool ShouldTrackVGPRs = VGPRPressure + MaxVGPRPressureInc >= VGPRExcessLimit ; bool ShouldTrackSGPRs = ! ShouldTrackVGPRs && SGPRPressure >= SGPRExcessLimit ; if ( ShouldTrackVGPRs && NewVGPRPressure >= VGPRExcessLimit ) { Cand . RPDelta . Excess = PressureChange ( SRI -> getVGPRPressureSet ( ) ) ; Cand . RPDelta . Excess . setUnitInc ( NewVGPRPressure - VGPRExcessLimit ) ; } if ( ShouldTrackSGPRs && NewSGPRPressure >= SGPRExcessLimit ) { Cand . RPDelta . Excess = PressureChange ( SRI -> getSGPRPressureSet ( ) ) ; Cand . RPDelta . Excess . setUnitInc ( NewSGPRPressure - SGPRExcessLimit ) ; } int SGPRDelta = NewSGPRPressure - SGPRCriticalLimit ; int VGPRDelta = NewVGPRPressure - VGPRCriticalLimit ; if ( SGPRDelta >= <NUM_LIT> || VGPRDelta >= <NUM_LIT> ) { if ( SGPRDelta > VGPRDelta ) { Cand . RPDelta . CriticalMax = PressureChange ( SRI -> getSGPRPressureSet ( ) ) ; Cand . RPDelta . CriticalMax . setUnitInc ( SGPRDelta ) ; } else { Cand . RPDelta . CriticalMax = PressureChange ( SRI -> getVGPRPressureSet ( ) ) ;

Cand . RPDelta . CriticalMax . setUnitInc ( VGPRDelta ) ;


<s> return __builtin_aarch64_lceiluv2sfv2si_us ( __a ) ;


<s> return ( uint8x16_t ) __builtin_neon_vrshru_nv16qi ( ( int8x16_t ) __a , __b ) ;


<s> static rtx get_tls_get_addr ( void ) { if ( ! tls_get_addr_libfunc ) tls_get_addr_libfunc = init_one_libfunc ( <STR_LIT> ) ; return tls_get_addr_libfunc ;


<s> final_start_function ( emit_barrier ( ) , stream , <NUM_LIT> ) ; if ( delta > <NUM_LIT> ) fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , ADDITIVE_SIZE_MODIFIER ( delta ) , delta , reg_names [ CRIS_FIRST_ARG_REG ] ) ; else if ( delta < <NUM_LIT> ) fprintf ( stream , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , ADDITIVE_SIZE_MODIFIER ( - delta ) , - delta , reg_names [ CRIS_FIRST_ARG_REG ] ) ; fprintf ( stream , <STR_LIT> ) ; assemble_name ( stream , XSTR ( XEXP ( DECL_RTL ( funcdecl ) , <NUM_LIT> ) , <NUM_LIT> ) ) ; fprintf ( stream , <STR_LIT> ) ;


<s> unsigned Requested = <STR_LIT> ( F , <STR_LIT> , MaxNumSGPRs ) ; if ( Requested && ( Requested <= ReservedNumSGPRs ) ) Requested = <NUM_LIT> ; unsigned InputNumSGPRs = PreloadedSGPRs ; if ( Requested && Requested < InputNumSGPRs ) Requested = InputNumSGPRs ; if ( Requested && Requested > getMaxNumSGPRs ( WavesPerEU . first , false ) ) Requested = <NUM_LIT> ; if ( WavesPerEU . second && Requested && Requested < getMinNumSGPRs ( WavesPerEU . second ) ) Requested = <NUM_LIT> ; if ( Requested ) MaxNumSGPRs = Requested ; } if ( hasSGPRInitBug ( ) ) MaxNumSGPRs = <STR_LIT> :: FIXED_NUM_SGPRS_FOR_INIT_BUG ; return std :: min ( MaxNumSGPRs - ReservedNumSGPRs , MaxAddressableNumSGPRs ) ;


<s> unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , II , dl , TII . get ( TargetOpcode :: KILL ) , getCRFromCRBit ( SrcReg ) ) . addReg ( SrcReg , getKillRegState ( MI . getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( getCRFromCRBit ( SrcReg ) ) ; unsigned Reg1 = Reg ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( LP64 ? G8RC : GPRC ) ; BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) , Reg ) . addReg ( Reg1 , RegState :: Kill ) . addImm ( getEncodingValue ( SrcReg ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; addFrameReference ( BuildMI ( MBB , II , dl , TII . get ( LP64 ? <STR_LIT> : <STR_LIT> ) ) . addReg ( Reg , RegState :: Kill ) , FrameIndex ) ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : VarArgsFirstGPR ( <NUM_LIT> ) , VarArgsFirstFPR ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , RegSaveFrameIndex ( <NUM_LIT> ) , FramePointerSaveIndex ( <NUM_LIT> ) , NumLocalDynamics ( <NUM_LIT> ) {


<s> return visium_function_value_1 ( TYPE_MODE ( ret_type ) ) ;


<s> if ( IsSigned ) ++ DivBits ; Type * I32Ty = Builder . getInt32Ty ( ) ; Type * F32Ty = Builder . getFloatTy ( ) ; ConstantInt * One = Builder . getInt32 ( <NUM_LIT> ) ; Value * JQ = One ; if ( IsSigned ) { JQ = Builder . CreateXor ( Num , Den ) ; JQ = Builder . CreateAShr ( JQ , Builder . getInt32 ( <NUM_LIT> ) ) ; JQ = Builder . CreateOr ( JQ , One ) ; } Value * IA = Num ; Value * IB = Den ; Value * FA = IsSigned ? Builder . Create<ISA_LIT>ToFP ( IA , F32Ty ) : Builder . CreateUIToFP ( IA , F32Ty ) ; Value * FB = IsSigned ? Builder . Create<ISA_LIT>ToFP ( IB , F32Ty ) : Builder . CreateUIToFP ( IB , F32Ty ) ; Value * RCP = Builder . CreateFDiv ( ConstantFP :: get ( F32Ty , <NUM_LIT> ) , FB ) ; Value * FQM = Builder . CreateFMul ( FA , RCP ) ; CallInst * FQ = Builder . CreateUnaryIntrinsic ( <STR_LIT> , FQM ) ; FQ -> copyFastMathFlags ( Builder . getFastMathFlags ( ) ) ; Value * FQNeg = Builder . CreateFNeg ( FQ ) ; Value * FR = Builder . CreateIntrinsic ( <STR_LIT> , { FQNeg -> getType ( ) } , { FQNeg , FB , FA } , FQ ) ; Value * IQ = IsSigned ? Builder . CreateFPTo<ISA_LIT> ( FQ , I32Ty ) : Builder . CreateFPToUI ( FQ , I32Ty ) ; FR = Builder . CreateUnaryIntrinsic ( <STR_LIT> , FR , FQ ) ; FB = Builder . CreateUnaryIntrinsic ( <STR_LIT> , FB , FQ ) ; Value * CV = Builder . CreateFCmpOGE ( FR , FB ) ; JQ = Builder . CreateSelect ( CV , JQ , Builder . getInt32 ( <NUM_LIT> ) ) ; Value * Div = Builder . CreateAdd ( IQ , JQ ) ; Value * Res = Div ; if ( ! IsDiv ) { Value * Rem = Builder . CreateMul ( Div , Den ) ; Res = Builder . CreateSub ( Num , Rem ) ; } if ( IsSigned ) { Res = Builder . CreateShl ( Res , <NUM_LIT> - DivBits ) ; Res = Builder . CreateAShr ( Res , <NUM_LIT> - DivBits ) ; } else { ConstantInt * TruncMask = Builder . getInt32 ( ( UINT64_C ( <NUM_LIT> ) << DivBits ) - <NUM_LIT> ) ; Res = Builder . CreateAnd ( Res , TruncMask ) ;


<s> uint64_t Size = TM . getDataLayout ( ) -> getTypeAllocSize ( ZCPV -> getType ( ) ) ; OutStreamer -> EmitValue ( Expr , Size ) ;


<s> void <ISA_LIT>TargetStreamer :: emitUnwindRaw ( int64_t StackOffset , const SmallVectorImpl < uint8_t > & Opcodes ) { llvm_unreachable ( <STR_LIT> ) ;


<s> inline SDValue XformM5ToU5Imm ( signed Imm , SDLoc DL ) {

assert ( ( Imm >= - <NUM_LIT> && Imm <= - <NUM_LIT> ) && <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> : if ( Subtarget . isTarget64BitLP64 ( ) ) return & <STR_LIT> ; return & <STR_LIT> ; case <NUM_LIT> :


<s> ELF<ISA_LIT>AsmBackend ( Target const & T , uint8_t OSABI ) : <ISA_LIT>AsmBackend ( T ) , OSABI ( OSABI ) {


<s> FixedValue += SecAddr ; uint32_t Value2 = <NUM_LIT> ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { MCSymbolData * B_SD = & Asm . getSymbolData ( B -> getSymbol ( ) ) ; if ( ! B_SD -> getFragment ( ) ) report_fatal_error ( <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> , false ) ; Type = A_SD -> isExternal ( ) ? ( unsigned ) MachO :: GENERIC_RELOC_SECTDIFF : ( unsigned ) MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B_SD , Layout ) ; FixedValue -= Writer -> getSectionAddress ( B_SD -> getFragment ( ) -> getParent ( ) ) ; } if ( Type == MachO :: GENERIC_RELOC_SECTDIFF || Type == MachO :: GENERIC_RELOC_LOCAL_SECTDIFF ) { if ( FixupOffset > <NUM_LIT> ) { char Buffer [ <NUM_LIT> ] ; format ( <STR_LIT> , FixupOffset ) . print ( Buffer , sizeof ( Buffer ) ) ; Asm . getContext ( ) . FatalError ( Fixup . getLoc ( ) , Twine ( <STR_LIT> <STR_LIT> ) + Buffer + <STR_LIT> <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ;


<s> PM . add ( create<ISA_LIT>DelaySlotFillerPass ( * this ) ) ; return true ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , PTXVersion ( <NUM_LIT> ) , SmVersion ( <NUM_LIT> ) , TM ( TM ) , InstrInfo ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) , FrameLowering ( ) {


<s> int gr5_hazard_bypass_p ( rtx_insn * out_insn , rtx_insn * in_insn ) { rtx out_set , in_set , dest , memexpr ; unsigned int out_reg , in_reg ; if ( GET_CODE ( out_insn ) == CALL_INSN ) return <NUM_LIT> ; out_set = single_set_and_flags ( out_insn ) ; dest = SET_DEST ( out_set ) ; if ( GET_CODE ( dest ) == MEM ) return <NUM_LIT> ; if ( GET_CODE ( dest ) == STRICT_LOW_PART ) dest = XEXP ( dest , <NUM_LIT> ) ; if ( GET_CODE ( dest ) == SUBREG ) dest = SUBREG_REG ( dest ) ; out_reg = REGNO ( dest ) ; in_set = single_set_and_flags ( in_insn ) ; if ( GET_CODE ( SET_SRC ( in_set ) ) == MEM ) memexpr = XEXP ( SET_SRC ( in_set ) , <NUM_LIT> ) ; else memexpr = XEXP ( SET_DEST ( in_set ) , <NUM_LIT> ) ; if ( GET_CODE ( memexpr ) == PLUS ) { memexpr = XEXP ( memexpr , <NUM_LIT> ) ; if ( GET_CODE ( memexpr ) == SUBREG ) in_reg = REGNO ( SUBREG_REG ( memexpr ) ) ; else in_reg = REGNO ( memexpr ) ; if ( in_reg == out_reg ) return <NUM_LIT> ; } else if ( TARGET_MCM ) { if ( GET_CODE ( memexpr ) == STRICT_LOW_PART ) memexpr = XEXP ( memexpr , <NUM_LIT> ) ; if ( GET_CODE ( memexpr ) == SUBREG ) memexpr = SUBREG_REG ( memexpr ) ; in_reg = REGNO ( memexpr ) ; if ( in_reg == out_reg ) return <NUM_LIT> ; } return <NUM_LIT> ;


<s> } } break ; } case <STR_LIT> : { switch ( cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : break ; case <STR_LIT> : return std :: make_pair ( true , CurDAG -> getMachineNode ( <STR_LIT> , DL , Node -> getValueType ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) ) ) ; } break ; } case <STR_LIT> : { switch ( cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : break ; case <STR_LIT> : { SDValue ChainIn = Node -> getOperand ( <NUM_LIT> ) ; SDValue RegIdx = Node -> getOperand ( <NUM_LIT> ) ; SDValue Value = Node -> getOperand ( <NUM_LIT> ) ; SDValue ChainOut = CurDAG -> getCopyToReg ( ChainIn , DL , getMSACtrlReg ( RegIdx ) , Value ) ; return std :: make_pair ( true , ChainOut . getNode ( ) ) ; } } break ; } case <STR_LIT> : { EVT PtrVT = getTargetLowering ( ) -> getPointerTy ( ) ; unsigned RdhwrOpc , DestReg ; if ( PtrVT == <STR_LIT> ) { RdhwrOpc = <STR_LIT> ; DestReg = <STR_LIT> ; } else { RdhwrOpc = <STR_LIT> ; DestReg = <STR_LIT> ; } SDNode * Rdhwr = CurDAG -> getMachineNode ( RdhwrOpc , SDLoc ( Node ) , Node -> getValueType ( <NUM_LIT> ) , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) ; SDValue Chain = CurDAG -> getCopyToReg ( CurDAG -> getEntryNode ( ) , DL , DestReg , SDValue ( Rdhwr , <NUM_LIT> ) ) ; SDValue ResNode = CurDAG -> getCopyFromReg ( Chain , DL , DestReg , PtrVT ) ; ReplaceUses ( SDValue ( Node , <NUM_LIT> ) , ResNode ) ; return std :: make_pair ( true , ResNode . getNode ( ) ) ; } case <STR_LIT> : { BuildVectorSDNode * BVN = cast < BuildVectorSDNode > ( Node ) ; APInt SplatValue , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; unsigned LdiOp ; EVT ResVecTy = BVN -> getValueType ( <NUM_LIT> ) ; EVT ViaVecTy ; if ( ! Subtarget -> hasMSA ( ) || ! BVN -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) ) return std :: make_pair ( false , nullptr ) ; if ( ! BVN -> isConstantSplat ( SplatValue , SplatUndef , SplatBitSize , HasAnyUndefs , <NUM_LIT> , ! Subtarget -> isLittle ( ) ) ) return std :: make_pair ( false , nullptr ) ; switch ( SplatBitSize ) { default : return std :: make_pair ( false , nullptr ) ; case <NUM_LIT> : LdiOp = <STR_LIT> ; ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : LdiOp = <STR_LIT> ; ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : LdiOp = <STR_LIT> ; ViaVecTy = <STR_LIT> ; break ; case <NUM_LIT> : LdiOp = <STR_LIT> ; ViaVecTy = <STR_LIT> ; break ; }

if ( ! SplatValue . isSignedIntN ( <NUM_LIT> ) ) return std :: make_pair ( false , nullptr ) ;


<s> const char * name ; if ( ! TREE_PUBLIC ( decl ) || DECL_COMMON ( decl ) || DECL_INITIAL ( decl ) == NULL_TREE || DECL_INITIAL ( decl ) == error_mark_node || ( flag_zero_initialized_in_bss && initializer_zerop ( DECL_INITIAL ( decl ) ) ) ) return ;

name = IDENTIFIER_POINTER ( DECL_ASSEMBLER_NAME ( decl ) ) ;


<s> SDValue newLoad = DAG . getLoad ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Op , load -> getChain ( ) , load -> getBasePtr ( ) , load -> getOffset ( ) , <STR_LIT> , load -> getMemOperand ( ) ) ; SDValue newTrunc = DAG . getZExtOrTrunc ( newLoad , Op , <STR_LIT> ) ;

SDValue Ops [ <NUM_LIT> ] = { newTrunc , newLoad . getOperand ( <NUM_LIT> ) } ;


<s> comparison = reverse_condition ( comparison ) ; branch_expander = gen_branch_false ; default : ; } emit_insn ( gen_rtx_SET ( get_t_reg_rtx ( ) , gen_rtx_fmt_ee ( comparison , SImode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ) ;

rtx_insn * jump = emit_jump_insn ( branch_expander ( operands [ <NUM_LIT> ] ) ) ;


<s> static bool isSupportedType ( const DataLayout & DL , const <ISA_LIT>TargetLowering & TLI , Type * T ) { EVT VT = TLI . getValueType ( DL , T , true ) ; if ( ! VT . isSimple ( ) || VT . isVector ( ) || ! ( VT . isInteger ( ) || VT . isFloatingPoint ( ) ) ) return false ;

unsigned VTSize = VT . getSimpleVT ( ) . getSizeInBits ( ) ;


<s> return gen_frame_mem ( Pmode , plus_constant ( Pmode , frame , - UNITS_PER_WORD ) ) ;


<s> return LHS ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> ( CC , true ) , CCVal , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CCVal , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; SDValue Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <STR_LIT> CC1 , CC2 ; changeFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 ) ; if ( CC2 == <STR_LIT> ) { changeFPCCTo<ISA_LIT>CC ( <STR_LIT> ( CC , false ) , CC1 , CC2 ) ; SDValue CC1Val = DAG . getConstant ( CC1 , dl , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CC1Val , Cmp ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( Immediate ) ; Op -> Imm . Val = MCConstantExpr :: create ( value , Ctx ) ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> void AMDGPUStructurizeCFG :: analyzeBlock ( BasicBlock * BB ) { pred_iterator PI = pred_begin ( BB ) , PE = pred_end ( BB ) ; BBPredicates & Pred = Predicates [ BB ] ; for ( ; PI != PE ; ++ PI ) { BranchInst * Term = cast < BranchInst > ( ( * PI ) -> getTerminator ( ) ) ; for ( unsigned i = <NUM_LIT> , e = Term -> getNumSuccessors ( ) ; i != e ; ++ i ) { BasicBlock * Succ = Term -> getSuccessor ( i ) ; if ( Succ != BB ) continue ;

buildPredicate ( Term , i , Pred , false ) ;


<s> uint64_t NumBytes = <NUM_LIT> ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { assert ( ! isAsynchronousEHPersonality ( classifyEHPersonality ( MF . getFunction ( ) -> getPersonalityFn ( ) ) ) && <STR_LIT> ) ; NumBytes = getWinEHFuncletFrameSize ( MF ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; TargetMBB = MBBI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { NumBytes = getWinEHFuncletFrameSize ( MF ) ; assert ( hasFP ( MF ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; NumBytes = FrameSize - CSSize ; if ( TRI -> needsStackRealignment ( MF ) && ! IsWin64Prologue ) NumBytes = RoundUpToAlignment ( FrameSize , MaxAlign ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , MachineFramePtr ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else { NumBytes = StackSize - CSSize ; } uint64_t SEHStackAllocAmt = NumBytes ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && ( Opc != <STR_LIT> || ! PI -> getFlag ( MachineInstr :: FrameDestroy ) ) && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) break ; -- MBBI ; } MachineBasicBlock :: iterator FirstCSPop = MBBI ; if ( TargetMBB ) { unsigned ReturnReg = STI . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( STI . is64Bit ( ) ) { BuildMI ( MBB , FirstCSPop , DL , TII . get ( <STR_LIT> ) , ReturnReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( TargetMBB ) . addReg ( <NUM_LIT> ) ; } else { BuildMI ( MBB , FirstCSPop , DL , TII . get ( <STR_LIT> ) , ReturnReg ) . addMBB ( TargetMBB ) ; }


<s> assert ( Kind == Immediate && <STR_LIT> ) ; return Imm . Val ;


<s> rtx mem , disp , fnaddr = XEXP ( DECL_RTL ( fndecl ) , <NUM_LIT> ) ; disp = expand_binop ( SImode , sub_optab , fnaddr , plus_constant ( Pmode , XEXP ( m_tramp , <NUM_LIT> ) , <NUM_LIT> ) , NULL_RTX , <NUM_LIT> , OPTAB_DIRECT ) ;

mem = adjust_address ( m_tramp , SImode , <NUM_LIT> ) ;


<s> static MachineOperand & getDispOperand ( MachineInstr * MI ) { int AddrOffset = getAddrOffset ( MI ) ;

return MI -> getOperand ( AddrOffset + <STR_LIT> ) ;


<s> SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue Val = OutVals [ i ] ; CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( RVLocs [ i ] . getValVT ( ) != RVLocs [ i ] . getLocVT ( ) ) Val = DAG . getNode ( <STR_LIT> , DL , RVLocs [ i ] . getLocVT ( ) , Val ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( MF . getFunction ( ) . hasStructRetAttr ( ) ) { <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned Reg = <ISA_LIT>FI -> getSRetReturnReg ( ) ; if ( ! Reg ) llvm_unreachable ( <STR_LIT> ) ; SDValue Val = DAG . getCopyFromReg ( Chain , DL , Reg , getPointerTy ( DAG . getDataLayout ( ) ) ) ; unsigned V0 = <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , V0 , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( V0 , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; }


<s> MachineInstr * Def = MRI -> getVRegDef ( InputReg ) ; if ( TRI -> isVectorRegister ( * MRI , InputReg ) ) { if ( Def -> isCopy ( ) ) { Register SrcReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getRegClassForReg ( * MRI , SrcReg ) ; if ( TRI -> isSGPRClass ( RC ) ) continue ; } hasVGPRInput = true ; break ; } else if ( Def -> isCopy ( ) && TRI -> isVectorRegister ( * MRI , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Register SrcReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * SrcDef = MRI -> getVRegDef ( SrcReg ) ; unsigned SMovOp ; int64_t Imm ; if ( ! isSafeToFoldImmIntoCopy ( Def , SrcDef , TII , SMovOp , Imm ) ) { hasVGPRInput = true ; break ; } else { MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; Def -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Imm ) ; Def -> addImplicitDefUseOperands ( * MF ) ; Def -> setDesc ( TII -> get ( SMovOp ) ) ; } } } if ( ( ! TRI -> isVectorRegister ( * MRI , PHIRes ) && RC0 != & <STR_LIT> ) && ( hasVGPRInput || numVGPRUses > <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> moveToVALU ( MI ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; TII -> legalizeOperands ( MI , MDT ) ;


<s> else if ( MemTy == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; MVT RegTy = MemTy == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; SDNode * CmpSwap = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , CurDAG -> getVTList ( RegTy , <STR_LIT> , <STR_LIT> ) , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( CmpSwap ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( CmpSwap , <NUM_LIT> ) ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SDValue ( CmpSwap , <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>AsmBackend :: MayNeedRelaxation ( const MCInst & Inst ) const {

if ( getRelaxedOpcode ( Inst . getOpcode ( ) ) == Inst . getOpcode ( ) ) return false ;


o << getTagName ( PREFIX_SYMBOL ) << prefix << <STR_LIT> << num << <STR_LIT> ;


<s> return CreateReg ( Index , RegKind_Numeric , RegInfo , S , E , Parser ) ;


<s> MachineFunctionInfo ( ) , LocalMemoryObjects ( ) , ExplicitKernArgSize ( <NUM_LIT> ) , LDSSize ( <NUM_LIT> ) , Mode ( MF . getFunction ( ) ) , IsEntryFunction ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) , NoSignedZerosFPMath ( MF . getTarget ( ) . Options . NoSignedZerosFPMath ) , MemoryBound ( false ) , WaveLimiter ( false ) {

const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( MF ) ;


<s> bool ia64_member_type_forces_blk ( const_tree , machine_mode mode ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( HII -> isNewValueJump ( * FirstTerm ) ) TBB = FirstTerm -> getOperand ( HII -> getCExtOpNum ( * FirstTerm ) ) . getMBB ( ) ; } if ( TBB && & MI == & * FirstTerm ) { Distance = std :: abs ( ( long long ) InstOffset - BlockToInstOffset [ TBB ] ) + BranchRelaxSafetyBuffer ; return ! HII -> isJumpWithinBranchRange ( * FirstTerm , Distance ) ; } if ( FBB ) {

auto SecondTerm = std :: next ( FirstTerm ) ;


<s> if ( S == MCDisassembler :: Success ) { DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ;

DecodeGRRegsRegisterClass ( Inst , Op2 , Address , Decoder ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TII ( tii ) {


<s> void <ISA_LIT>InstPrinter :: printAddSubImmLSL12Operand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {

printAddSubImmLSL0Operand ( MI , OpNum , O ) ;


<s> static __inline__ float __fmuls ( float a , float b ) { float d ; __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) ) ; return d ;


<s> SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RetOps ) ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) {


<s> SDValue Ext1 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue Ext2 = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Ext1 . getOpcode ( ) != <STR_LIT> || Ext2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; ConstantSDNode * Ext1Op = dyn_cast < ConstantSDNode > ( Ext1 . getOperand ( <NUM_LIT> ) ) ; ConstantSDNode * Ext2Op = dyn_cast < ConstantSDNode > ( Ext2 . getOperand ( <NUM_LIT> ) ) ; if ( ! Ext1Op || ! Ext2Op ) return SDValue ( ) ; if ( Ext1 . getValueType ( ) != <STR_LIT> || Ext2 . getValueType ( ) != <STR_LIT> ) if ( Ext1 . getOperand ( <NUM_LIT> ) != Ext2 . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; int FirstElem = Ext1Op -> getZExtValue ( ) ; int SecondElem = Ext2Op -> getZExtValue ( ) ; int SubvecIdx ; if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else if ( FirstElem == <NUM_LIT> && SecondElem == <NUM_LIT> ) SubvecIdx = Subtarget . isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ; else return SDValue ( ) ; SDValue SrcVec = Ext1 . getOperand ( <NUM_LIT> ) ;

auto NodeType = ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ;


<s> rtx hi ; rtx lo ; rtx addr ; const char * load_string ; int r ; if ( GET_CODE ( mem ) == FLOAT_EXTEND || GET_CODE ( mem ) == ZERO_EXTEND ) { mem = XEXP ( mem , <NUM_LIT> ) ; mode = GET_MODE ( mem ) ; } if ( GET_CODE ( reg ) == SUBREG ) { gcc_assert ( SUBREG_BYTE ( reg ) == <NUM_LIT> ) ; reg = SUBREG_REG ( reg ) ; } if ( ! REG_P ( reg ) ) fatal_insn ( <STR_LIT> , reg ) ; r = REGNO ( reg ) ; if ( FP_REGNO_P ( r ) ) { if ( mode == SFmode ) load_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) load_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( ALTIVEC_REGNO_P ( r ) && TARGET_P9_VECTOR ) { if ( mode == SFmode ) load_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) load_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( INT_REGNO_P ( r ) ) { switch ( mode ) { case E_QImode : load_string = <STR_LIT> ; break ; case E_HImode : load_string = <STR_LIT> ; break ; case E_SImode :


<s> void <ISA_LIT>InstPrinter :: printImplicitlyTypedVectorList ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {

printVectorList ( MI , OpNum , O , <STR_LIT> ) ;


<s> auto VectorInfo = VectorizePTXValueVTs ( VTs , Offsets , RetTy -> isSized ( ) ? DL . getABITypeAlignment ( RetTy ) : <NUM_LIT> ) ; bool ExtendIntegerRetVal = RetTy -> isIntegerTy ( ) && DL . getTypeAllocSizeInBits ( RetTy ) < <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > StoreOperands ; for ( unsigned i = <NUM_LIT> , e = VTs . size ( ) ; i != e ; ++ i ) { if ( VectorInfo [ i ] & PVF_FIRST ) { assert ( StoreOperands . empty ( ) && <STR_LIT> ) ; StoreOperands . push_back ( Chain ) ; StoreOperands . push_back ( DAG . getConstant ( Offsets [ i ] , dl , <STR_LIT> ) ) ; } SDValue RetVal = OutVals [ i ] ; if ( ExtendIntegerRetVal ) { RetVal = DAG . getNode ( Outs [ i ] . Flags . isSExt ( ) ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } else if ( RetVal . getValueSizeInBits ( ) < <NUM_LIT> ) { RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetVal ) ; } StoreOperands . push_back ( RetVal ) ; if ( VectorInfo [ i ] & PVF_LAST ) { <STR_LIT> Op ; unsigned NumElts = StoreOperands . size ( ) - <NUM_LIT> ; switch ( NumElts ) { case <NUM_LIT> : Op = <STR_LIT> ; break ; case <NUM_LIT> :


<s> cfun -> machine -> intr_pushmem [ i - MEM0_REGNO ] = <NUM_LIT> ; } if ( ppt == PP_pushm && byte_count ) { rtx note = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( n_dwarfs + <NUM_LIT> ) ) ; rtx pushm ; if ( reg_mask ) { XVECEXP ( note , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , gen_rtx_PLUS ( GET_MODE ( stack_pointer_rtx ) , stack_pointer_rtx , GEN_INT ( - byte_count ) ) ) ; F ( XVECEXP ( note , <NUM_LIT> , <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < n_dwarfs ; i ++ ) XVECEXP ( note , <NUM_LIT> , i + <NUM_LIT> ) = dwarf_set [ i ] ; pushm = F ( emit_insn ( gen_pushm ( GEN_INT ( reg_mask ) ) ) ) ; add_reg_note ( pushm , REG_FRAME_RELATED_EXPR , note ) ; } if ( cfun -> machine -> is_interrupt ) for ( i = MEM0_REGNO ; i <= MEM7_REGNO ; i ++ ) if ( cfun -> machine -> intr_pushmem [ i - MEM0_REGNO ] ) { if ( TARGET_A16 ) pushm = emit_insn ( gen_pushhi_16 ( gen_rtx_REG ( HImode , i ) ) ) ; else pushm = emit_insn ( gen_pushhi_24 ( gen_rtx_REG ( HImode , i ) ) ) ; F ( pushm ) ; } } if ( ppt == PP_popm && byte_count ) { if ( cfun -> machine -> is_interrupt ) for ( i = MEM7_REGNO ; i >= MEM0_REGNO ; i -- ) if ( cfun -> machine -> intr_pushmem [ i - MEM0_REGNO ] ) { if ( TARGET_A16 ) emit_insn ( gen_pophi_16 ( gen_rtx_REG ( HImode , i ) ) ) ; else emit_insn ( gen_pophi_24 ( gen_rtx_REG ( HImode , i ) ) ) ; }

if ( reg_mask ) emit_insn ( gen_popm ( GEN_INT ( reg_mask ) ) ) ;


<s> SDValue InputVT = DAG . getValueType ( DataVT ) ; if ( DataVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDValue SrcNew ; if ( Data . getValueType ( ) . isFloatingPoint ( ) ) SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Data ) ; else SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Data ) ;

SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , SrcNew , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , InputVT } ;


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; if ( Triple ( TM -> getTargetTriple ( ) ) . isOSNaCl ( ) && Triple ( TM -> getTargetTriple ( ) ) . isArch64Bit ( ) && NaClDontBreakABI ) { addPass ( createClearPtrToIntTop32Pass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ;


<s> return cfun ? cfun -> machine -> call_abi : ix86_abi ;


<s> IRBuilder < > builder ( secondBB ) ; SmallVector < IntrinsicInst * , <NUM_LIT> > itrin [ <NUM_LIT> ] = { get_list_of < IntrinsicInst , <NUM_LIT> > ( & firstBB ) , get_list_of < IntrinsicInst , <NUM_LIT> > ( & secondBB ) } ; vector < Instruction * > selectItrin [ <NUM_LIT> ] ;

for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) selectItrin [ i ] = extractIntrinFromList ( itrin [ i ] , intrinId ) ;


<s> static bool epiphany_function_ok_for_sibcall ( tree decl , tree exp ) { bool cfun_interrupt_p , call_interrupt_p ; cfun_interrupt_p = EPIPHANY_INTERRUPT_P ( epiphany_compute_function_type ( current_function_decl ) ) ; if ( decl ) call_interrupt_p = EPIPHANY_INTERRUPT_P ( epiphany_compute_function_type ( decl ) ) ; else { tree fn_type = TREE_TYPE ( CALL_EXPR_FN ( exp ) ) ; gcc_assert ( POINTER_TYPE_P ( fn_type ) ) ; fn_type = TREE_TYPE ( fn_type ) ; gcc_assert ( TREE_CODE ( fn_type ) == FUNCTION_TYPE || TREE_CODE ( fn_type ) == METHOD_TYPE ) ; call_interrupt_p = lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fn_type ) ) != NULL ; } if ( cfun_interrupt_p || call_interrupt_p ) return false ;


<s> const <ISA_LIT>RegisterInfo & <ISA_LIT>InstrInfo :: getRegisterInfo ( ) const { return RI ;


<s> while ( sz > <NUM_LIT> ) { OS << static_cast < uint8_t > ( Encoding & <NUM_LIT> ) ; Encoding = Encoding >> <NUM_LIT> ;


<s> while ( ++ I != E && I -> isInsideBundle ( ) ) { if ( I -> getOpcode ( ) != <STR_LIT> ) Latency += getInstrLatency ( ItinData , I , PredCost ) ; } return Latency ; } const MCInstrDesc & MCID = MI -> getDesc ( ) ; unsigned Class = MCID . getSchedClass ( ) ; unsigned UOps = ItinData -> Itineraries [ Class ] . NumMicroOps ;

if ( PredCost && ( MCID . isCall ( ) || MCID . hasImplicitDefOfPhysReg ( <STR_LIT> ) ) ) * PredCost = <NUM_LIT> ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine32 > X ( The<ISA_LIT>Target32 ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine64 > Y ( The<ISA_LIT>Target64 ) ;

PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ;


<s> const TargetInstrDesc & LastTID = LastMI -> getDesc ( ) ; if ( ! LastTID . isBarrier ( ) && ( LastTID . TSFlags & <STR_LIT> ) == <STR_LIT> ) { MachineBasicBlock :: iterator I = LastMI ; if ( I != LastMI -> getParent ( ) -> begin ( ) ) { I = llvm :: prior ( I ) ; DefMI = & * I ; } } if ( TII . isFpMLxInstruction ( DefMI -> getOpcode ( ) ) && ( TII . canCauseFpMLxStall ( MI -> getOpcode ( ) ) || hasRAWHazard ( DefMI , MI , TRI ) ) ) { if ( FpMLxStalls == <NUM_LIT> ) FpMLxStalls = <NUM_LIT> ; return Hazard ; }


<s> if ( width == <NUM_LIT> ) return <NUM_LIT> ; if ( ( ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2 || ix86_tune == PROCESSOR_ZNVER3 ) && INTEGRAL_MODE_P ( mode ) && op != PLUS && op != MINUS ) return <NUM_LIT> ; if ( TARGET_AVX256_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ; else if ( TARGET_SSE_SPLIT_REGS && GET_MODE_BITSIZE ( mode ) > <NUM_LIT> ) div = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> ;

width = ( width + div - <NUM_LIT> ) / div ;


<s> Function * Callee = CS . getCalledFunction ( ) ; if ( ! Callee || Callee -> isDeclaration ( ) ) { ++ FI . InstCount ; continue ; } if ( & F == Callee ) continue ; auto Loc = FIM . find ( Callee ) ; if ( Loc == FIM . end ( ) ) continue ; FI . MemInstCount += Loc -> second . MemInstCount ; FI . InstCount += Loc -> second . InstCount ; FI . IAMInstCount += Loc -> second . IAMInstCount ; FI . LSMInstCount += Loc -> second . LSMInstCount ; } else if ( auto * GEP = dyn_cast < GetElementPtrInst > ( & I ) ) { TargetLoweringBase :: AddrMode AM ; auto * Ptr = GetPointerBaseWithConstantOffset ( GEP , AM . BaseOffs , * DL ) ; AM . BaseGV = dyn_cast_or_null < GlobalValue > ( const_cast < Value * > ( Ptr ) ) ; AM . HasBaseReg = ! AM . BaseGV ; if ( TLI -> isLegalAddressingMode ( * DL , AM , GEP -> getResultElementType ( ) , GEP -> getPointerAddressSpace ( ) ) ) continue ; ++ FI . InstCount ; } else {


<s> unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = NULL ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) {

Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( maybe_ne ( BITS_PER_SVE_VECTOR , <NUM_LIT> ) ) { if ( from_sve_p && ! to_sve_p && maybe_gt ( GET_MODE_BITSIZE ( to ) , <NUM_LIT> ) ) return false ; if ( to_sve_p && ! from_sve_p && maybe_gt ( GET_MODE_BITSIZE ( from ) , <NUM_LIT> ) ) return false ; } if ( BYTES_BIG_ENDIAN ) { if ( from_sve_p != to_sve_p ) return false ; if ( from_sve_p && GET_MODE_UNIT_SIZE ( from ) != GET_MODE_UNIT_SIZE ( to ) ) return false ; } return true ;


<s> if ( isa < FixedVectorType > ( DataType ) && ST -> getMinRVVVectorSizeInBits ( ) == <NUM_LIT> ) return false ; if ( Alignment < DL . getTypeStoreSize ( DataType -> getScalarType ( ) ) . getFixedSize ( ) ) return false ; return isLegalElementTypeForRVV ( DataType -> getScalarType ( ) ) ;


<s> if ( bytes_left == <NUM_LIT> ) return <NUM_LIT> ; if ( bytes > bytes_left ) return bytes_left ; return <NUM_LIT> ;


<s> MachineBasicBlock :: iterator end ( ) { assert ( End != nullptr ) ;


<s> head = dest_op_info -> heads [ i ] ; if ( ! head -> first ) head = regrename_chain_from_id ( head -> id ) ; forest = NULL ; for ( chain = head -> first ; chain ; chain = chain -> next_use ) { fma_node * * fma_slot ; if ( ! is_fmul_fmac_insn ( chain -> insn , true ) ) continue ; if ( chain -> loc != & SET_DEST ( PATTERN ( chain -> insn ) ) ) continue ; if ( chain -> insn == insn ) break ; fma_slot = this -> m_insn_fma_head_map -> get ( chain -> insn ) ; if ( fma_slot && ( * fma_slot ) -> get_children ( ) ) forest = ( * fma_slot ) -> get_forest ( ) ; } if ( chain ) break ; } if ( i < dest_op_info -> n_chains ) this -> analyze_fma_fmul_insn ( forest , chain , head ) ; } } free ( bb_dfs_preorder ) ; if ( dump_file ) this -> dfs ( dump_forest_info , dump_tree_root_info , dump_tree_node_info , false ) ;


<s> assert ( ( Update -> getOpcode ( ) == <STR_LIT> || Update -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock :: iterator NextI = I ; if ( ++ NextI == Update ) ++ NextI ; int Value = Update -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( <STR_LIT> ( Update -> getOperand ( <NUM_LIT> ) . getImm ( ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Update -> getOpcode ( ) == <STR_LIT> ) Value = - Value ; unsigned NewOpc = getPreIndexedOpcode ( I -> getOpcode ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addOperand ( getLdStRegOp ( Update ) ) . addOperand ( getLdStRegOp ( I ) ) . addOperand ( getLdStBaseOp ( I ) ) . addImm ( Value ) ; ( void ) MIB ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( I -> print ( dbgs ( ) ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Update -> print ( dbgs ( ) ) ) ;


<s> if ( T == EXP_CNT ) { unsigned UB = ScoreUBs [ T ] - getWaitCountMax ( EXP_CNT ) ; if ( ScoreLBs [ T ] < UB && UB < ScoreUBs [ T ] ) ScoreLBs [ T ] = UB ;


<s> emit_insn ( gen_movmd ( first_dest , first_src , length , GEN_INT ( factor ) ) ) ; if ( ( n & - factor ) != n ) { dest = adjust_address ( dest , BLKmode , n & - factor ) ; src = adjust_address ( src , BLKmode , n & - factor ) ; dest = replace_equiv_address ( dest , dest_reg ) ; src = replace_equiv_address ( src , src_reg ) ; if ( n & <NUM_LIT> ) emit_move_insn ( adjust_address ( dest , HImode , <NUM_LIT> ) , adjust_address ( src , HImode , <NUM_LIT> ) ) ; if ( n & <NUM_LIT> ) emit_move_insn ( adjust_address ( dest , QImode , n & <NUM_LIT> ) , adjust_address ( src , QImode , n & <NUM_LIT> ) ) ; } return true ; }


<s> printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ; O << <STR_LIT> ( ( <STR_LIT> ) MO . getImm ( ) ) ;


<s> bool isToken ( ) const override { return Kind == k_Token ;


<s> GepNode * N = * NI ; if ( node_class ( N , EqRel ) ) continue ; NodeSet C ; for ( NodeSet :: iterator NJ = std :: next ( NI ) ; NJ != NE ; ++ NJ ) if ( node_eq ( N , * NJ , Eq , Ne ) ) C . insert ( * NJ ) ; if ( ! C . empty ( ) ) { C . insert ( N ) ; std :: pair < NodeSymRel :: iterator , bool > Ins = EqRel . insert ( C ) ; ( void ) Ins ; assert ( Ins . second && <STR_LIT> ) ; } } } LLVM_DEBUG ( { dbgs ( ) << <STR_LIT> ; for ( NodePairSet :: iterator I = Eq . begin ( ) , E = Eq . end ( ) ; I != E ; ++ I ) dbgs ( ) << <STR_LIT> << I -> first << <STR_LIT> << I -> second << <STR_LIT> ; dbgs ( ) << <STR_LIT> ; for ( const NodeSet & S : EqRel ) { dbgs ( ) << '{' ; for ( NodeSet :: const_iterator J = S . begin ( ) , F = S . end ( ) ; J != F ; ++ J ) { if ( J != S . begin ( ) ) dbgs ( ) << ',' ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> Constant * Int = <STR_LIT> ( M , <STR_LIT> , Tys , <NUM_LIT> ) ; Value * Op = CI -> getOperand ( <NUM_LIT> ) ; Op = CallInst :: Create ( Int , Op , CI -> getName ( ) , CI ) ; CI -> replaceAllUsesWith ( Op ) ; CI -> eraseFromParent ( ) ;


<s> ++ MBB ; return MBB != MF -> end ( ) && MBB -> begin ( ) != MBB -> end ( ) && & * MBB -> begin ( ) == CPEMI ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , ( Subtarget . isSVR4ABI ( ) && CallConv == CallingConv :: Cold ) ? RetCC_<ISA_LIT>_Cold : RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , RealResIdx = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i , ++ RealResIdx ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Arg = OutVals [ RealResIdx ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ;


<s> void llvm :: dumpInstRec ( Value * v ) { std :: set < Instruction * > visited ; dumpInstRec ( v , & visited ) ;


<s> gcc_checking_assert ( CONST_INT_P ( source ) ) ; c = INTVAL ( source ) ; switch ( mode ) { case QImode : case HImode : emit_insn ( gen_rtx_SET ( VOIDmode , dest , source ) ) ; return true ; case SImode : temp = ! can_create_pseudo_p ( ) ? dest : gen_reg_rtx ( SImode ) ; emit_insn ( gen_rtx_SET ( VOIDmode , copy_rtx ( temp ) , GEN_INT ( c & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , dest , gen_rtx_IOR ( SImode , copy_rtx ( temp ) , GEN_INT ( c & <NUM_LIT> ) ) ) ) ; break ; case DImode : if ( ! TARGET_POWERPC64 ) { rtx hi , lo ; hi = operand_subword_force ( copy_rtx ( dest ) , WORDS_BIG_ENDIAN == <NUM_LIT> , DImode ) ; lo = operand_subword_force ( dest , WORDS_BIG_ENDIAN != <NUM_LIT> , DImode ) ; emit_move_insn ( hi , GEN_INT ( c >> <NUM_LIT> ) ) ;

c = ( ( c & <NUM_LIT> ) ^ <NUM_LIT> ) - <NUM_LIT> ;


<s> static DecodeStatus decodeSImmOperand ( MCInst & Inst , uint64_t Imm , int64_t Address , const MCDisassembler * Decoder ) { assert ( isUInt < N > ( Imm ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < N > ( Imm ) << S ) ) ; return MCDisassembler :: Success ;


<s> exception_section = get_unnamed_section ( <NUM_LIT> , output_section_asm_op , <STR_LIT> ) ; if ( target_pure_code ) text_section -> unnamed . data = <STR_LIT> ;


<s> if ( FMA3Group . isKMasked ( ) ) { KMaskOp = <NUM_LIT> ; if ( FMA3Group . isKMergeMasked ( ) ) FirstCommutableVecOp = <NUM_LIT> ; LastCommutableVecOp ++ ; } if ( isMem ( MI , LastCommutableVecOp ) ) LastCommutableVecOp -- ; if ( SrcOpIdx1 != CommuteAnyOperandIndex && ( SrcOpIdx1 < FirstCommutableVecOp || SrcOpIdx1 > LastCommutableVecOp || SrcOpIdx1 == KMaskOp ) ) return false ;

if ( SrcOpIdx2 != CommuteAnyOperandIndex && ( SrcOpIdx2 < FirstCommutableVecOp || SrcOpIdx2 > LastCommutableVecOp || SrcOpIdx2 == KMaskOp ) ) return false ;


<s> return MCInstrAnalysis :: isUnconditionalBranch ( Inst ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) {

return new <ISA_LIT>MCCodeEmitter ( MCII , true ) ;


<s> bool Changed = false ; SmallSetVector < Function * , <NUM_LIT> > Functions ; for ( auto & F : M . getFunctionList ( ) ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( User * U : F . users ( ) ) Functions . insert ( cast < Instruction > ( U ) -> getFunction ( ) ) ; break ; default : break ; }


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : CheckCPSRDef = true ; case <STR_LIT> : break ; } if ( Bytes == <NUM_LIT> || ( Limit && Bytes >= Limit ) ) return false ; unsigned Scale = ( MI -> getOpcode ( ) == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( ! ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == Base && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * Scale ) == Bytes && llvm :: getInstrPredicate ( MI , MyPredReg ) == Pred && MyPredReg == PredReg ) ) return false ;

return CheckCPSRDef ? ! definesCPSR ( MI ) : true ;


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } bool EhDataRegFI = <ISA_LIT>FI -> isEhDataRegFI ( FrameIndex ) ; unsigned FrameReg ; if ( ( FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI ) || EhDataRegFI ) FrameReg = isN64 ? <STR_LIT> : <STR_LIT> ; else FrameReg = getFrameRegister ( MF ) ; bool IsKill = false ; int64_t Offset ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) ) { unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits ( MI . getOpcode ( ) ) ; unsigned OffsetAlign = getLoadStoreOffsetAlign ( MI . getOpcode ( ) ) ; if ( OffsetBitSize < <NUM_LIT> && isInt < <NUM_LIT> > ( Offset ) && ( ! isIntN ( OffsetBitSize , Offset ) || OffsetToAlignment ( Offset , OffsetAlign ) != <NUM_LIT> ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned ADDiu = isN64 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isN64 ? & <STR_LIT> : & <STR_LIT> ; MachineRegisterInfo & RegInfo = MBB . getParent ( ) -> getRegInfo ( ) ; unsigned Reg = RegInfo . createVirtualRegister ( RC ) ; const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; BuildMI ( MBB , II , DL , TII . get ( ADDiu ) , Reg ) . addReg ( FrameReg ) . addImm ( Offset ) ; FrameReg = Reg ; Offset = <NUM_LIT> ; IsKill = true ; } else if ( ! isInt < <NUM_LIT> > ( Offset ) ) {


<s> BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addReg ( MaskReg ) ;

BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( OldValReg ) . addReg ( ScratchReg ) ;


<s> int nargs = gimple_call_num_args ( stmt ) ; tree * args = ( nargs > <NUM_LIT> ? gimple_call_arg_ptr ( stmt , <NUM_LIT> ) : & error_mark_node ) ; switch ( fcode ) { BUILTIN_VALL ( UNOP , reduc_plus_scal_ , <NUM_LIT> ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_PLUS_EXPR , args [ <NUM_LIT> ] ) ; break ; BUILTIN_VDQIF ( UNOP , reduc_smax_scal_ , <NUM_LIT> ) BUILTIN_VDQ_BHSI ( UNOPU , reduc_umax_scal_ , <NUM_LIT> ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_MAX_EXPR , args [ <NUM_LIT> ] ) ; break ; BUILTIN_VDQIF ( UNOP , reduc_smin_scal_ , <NUM_LIT> ) BUILTIN_VDQ_BHSI ( UNOPU , reduc_umin_scal_ , <NUM_LIT> ) new_stmt = gimple_build_assign ( gimple_call_lhs ( stmt ) , REDUC_MIN_EXPR , args [ <NUM_LIT> ] ) ; break ; default : break ; } } } if ( new_stmt ) { gsi_replace ( gsi , new_stmt , true ) ;


<s> vld1q_dup_p8 ( const poly8_t * __a ) {


<s> reg = force_reg ( Pmode , addr ) ; ok_label = gen_label_rtx ( ) ; andop = gen_rtx_AND ( Pmode , reg , GEN_INT ( natural_alignment - <NUM_LIT> ) ) ; emit_cmp_and_jump_insns ( force_reg ( SImode , andop ) , const0_rtx , EQ , NULL_RTX , Pmode , <NUM_LIT> , ok_label ) ; jmp = get_last_insn ( ) ; gcc_assert ( JUMP_P ( jmp ) ) ;

predict_insn_def ( jmp , PRED_NORETURN , TAKEN ) ;


<s> <ISA_LIT>DAGToDAGISel :: ~ <ISA_LIT>DAGToDAGISel ( ) {


<s> if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return AsmPrinter :: PrintAsmOperand ( MI , OpNo , AsmVariant , ExtraCode , O ) ; case 'r' :


<s> unsigned <ISA_LIT>FastISel :: emitLogicalOp ( unsigned ISDOpc , MVT RetVT , const Value * LHS , const Value * RHS ) { if ( isa < ConstantInt > ( LHS ) && ! isa < ConstantInt > ( RHS ) ) std :: swap ( LHS , RHS ) ; if ( LHS -> hasOneUse ( ) && isValueAvailable ( LHS ) ) if ( isMulPowOf2 ( LHS ) ) std :: swap ( LHS , RHS ) ; if ( LHS -> hasOneUse ( ) && isValueAvailable ( LHS ) ) if ( const auto * SI = dyn_cast < ShlOperator > ( LHS ) ) if ( isa < ConstantInt > ( SI -> getOperand ( <NUM_LIT> ) ) ) std :: swap ( LHS , RHS ) ; unsigned LHSReg = getRegForValue ( LHS ) ; if ( ! LHSReg ) return <NUM_LIT> ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned ResultReg = <NUM_LIT> ; if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) ) { uint64_t Imm = C -> getZExtValue ( ) ; ResultReg = emitLogicalOp_ri ( ISDOpc , RetVT , LHSReg , LHSIsKill , Imm ) ; } if ( ResultReg ) return ResultReg ; if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) if ( isMulPowOf2 ( RHS ) ) { const Value * MulLHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; const Value * MulRHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; if ( const auto * C = dyn_cast < ConstantInt > ( MulLHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) std :: swap ( MulLHS , MulRHS ) ; assert ( isa < ConstantInt > ( MulRHS ) && <STR_LIT> ) ; uint64_t ShiftVal = cast < ConstantInt > ( MulRHS ) -> getValue ( ) . logBase2 ( ) ; unsigned RHSReg = getRegForValue ( MulLHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( MulLHS ) ; return emitLogicalOp_rs ( ISDOpc , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , ShiftVal ) ; } if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) if ( const auto * SI = dyn_cast < ShlOperator > ( RHS ) ) if ( const auto * C = dyn_cast < ConstantInt > ( SI -> getOperand ( <NUM_LIT> ) ) ) { uint64_t ShiftVal = C -> getZExtValue ( ) ; unsigned RHSReg = getRegForValue ( SI -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHSReg ) return <NUM_LIT> ; bool RHSIsKill = hasTrivialKill ( SI -> getOperand ( <NUM_LIT> ) ) ; return emitLogicalOp_rs ( ISDOpc , RetVT , LHSReg , LHSIsKill , RHSReg , RHSIsKill , ShiftVal ) ;


<s> SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } unsigned Ret = ( CallConv == llvm :: CallingConv :: MBLAZE_INTR ) ? <STR_LIT> : <STR_LIT> ;

unsigned Reg = ( CallConv == llvm :: CallingConv :: MBLAZE_INTR ) ? <STR_LIT> : <STR_LIT> ;


<s> const <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( <ISA_LIT>FI -> hasReplacement ( FI ) ) FI = <ISA_LIT>FI -> getReplacement ( FI ) ; return TargetFrameLowering :: getFrameIndexOffset ( MF , FI ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ;

SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Zero , Zero , LHS , RHS ) ;


<s> bool hasVALUTransUseHazard ( ) const {


<s> <ISA_LIT>AddressSanitizer ( const MCSubtargetInfo & STI ) : <ISA_LIT>AsmInstrumentation ( STI ) , RepPrefix ( false ) , OrigSPOffset ( <NUM_LIT> ) {


<s> addPass ( & BranchRelaxationPassID ) ;


return Kind == k_Register && Reg . Kind == Kind_MSA128WRegs ;


<s> Personality = Per ; UnwindOpAsm . setPersonality ( Per ) ;


<s> return getMachineOpValue ( MI , MI . getOperand ( OpNo ) ) - <NUM_LIT> ;


<s> if ( ! selectLEAAddr ( N , Base , Scale , Index , Disp , Segment ) ) return false ; RegisterSDNode * RN = dyn_cast < RegisterSDNode > ( Base ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Base = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else if ( Base . getValueType ( ) == <STR_LIT> && ! isa < FrameIndexSDNode > ( Base ) ) { SDValue ImplDef = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> ) , <NUM_LIT> ) ; Base = CurDAG -> getTargetInsertSubreg ( <STR_LIT> , DL , <STR_LIT> , ImplDef , Base ) ; } RN = dyn_cast < RegisterSDNode > ( Index ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Index = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ;


<s> return inprec <= <NUM_LIT> && outprec <= inprec ;


__b = ( __vector unsigned short ) vec_splats ( __B ) ;


<s> addPass ( & <ISA_LIT>LateBranchLoweringPassID ) ; if ( getOptLevel ( ) > CodeGenOpt :: None ) addPass ( & <ISA_LIT>PreEmitPeepholeID ) ;

addPass ( & PostRAHazardRecognizerID ) ;


<s> return isThumb ( ) && hasThumb2 ( ) ;


<s> const MCSubtargetInfo & STI = * getGlobalSTI ( ) ; if ( ( <STR_LIT> ( STI ) || <STR_LIT> ( STI ) ) && ( STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDHSA || STI . getTargetTriple ( ) . getOS ( ) == Triple :: AMDPAL ) ) { OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; getTargetStreamer ( ) -> EmitCodeEnd ( STI ) ;


<s> else cr = gen_reg_rtx ( cmpmode ) ; rtx label_ref = gen_rtx_LABEL_REF ( VOIDmode , true_label ) ; if ( a != NULL_RTX ) emit_move_insn ( cr , gen_rtx_COMPARE ( cmpmode , a , b ) ) ; rtx cmp_rtx = gen_rtx_fmt_ee ( comparison , VOIDmode , cr , const0_rtx ) ;

rtx ifelse = gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , label_ref , pc_rtx ) ;


<s> const MCInstrDesc & MID = MI -> getDesc ( ) ; if ( ( MID . mayLoad ( ) || MID . mayStore ( ) ) ) { if ( ! hasRepForm ( MI , tfrDefR ) ) { KeepTfr = true ; continue ; } SizeInc ++ ; CanBeReplaced = true ; } else if ( MI -> getOpcode ( ) == <STR_LIT> ) { NodeList AddaslUseList ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI << <STR_LIT> ) ; getAllRealUses ( SN , AddaslUseList ) ; if ( allValidCandidates ( SN , AddaslUseList ) && canRemoveAddasl ( SN , MI , AddaslUseList ) ) { SizeInc += AddaslUseList . size ( ) ; SizeInc -= <NUM_LIT> ; CanBeReplaced = true ; } else SizeInc ++ ; } else KeepTfr = true ; InstrEvalResult [ MI ] = CanBeReplaced ; HasRepInstr |= CanBeReplaced ; } if ( ! KeepTfr ) SizeInc -= <NUM_LIT> ; return HasRepInstr ;


<s> } else { Val = ~ Val ; if ( isShiftedMask_32 ( Val ) ) { ME = countLeadingZeros ( Val ) - <NUM_LIT> ; MB = countLeadingZeros ( ( Val - <NUM_LIT> ) ^ Val ) + <NUM_LIT> ; return true ; } }


<s> case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : return { <STR_LIT> , FTZ_Any } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOff } ; case <STR_LIT> : return { <STR_LIT> , FTZ_MustBeOn } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: FPToSI } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: FPToUI } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: SIToFP } ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return { Instruction :: UIToFP } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FAdd , FTZ_MustBeOn } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_Any } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_MustBeOff } ; case <STR_LIT> : return { Instruction :: FMul , FTZ_MustBeOn } ; case <STR_LIT> :

return { Instruction :: FDiv , FTZ_Any } ;


<s> if ( ! FoundAllComponents ( ) ) dbgs ( ) << <STR_LIT> ; else if ( ! ( Start && Dec && End ) ) dbgs ( ) << <STR_LIT> ;


<s> <ISA_LIT>beTargetMachine :: <ISA_LIT>beTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , JIT , false ) {


<s> assert ( isRegNumber ( ) && <STR_LIT> ) ;


<s> bool hasGFNI ( ) const { return HasGFNI ;


<s> MachineBasicBlock * target = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ;

BuildMI ( * BB , MI , MI -> getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addReg ( regY ) ;


<s> const char * <ISA_LIT>_64Relocator :: getName ( Relocation :: Type pType ) const {

return <ISA_LIT>_64ApplyFunctions [ pType ] . name ;


<s> void emitConstant ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { emitByte ( Val & <NUM_LIT> , OS ) ;


<s> bool <ISA_LIT>ExpandPseudo :: expandLoadLocalAddress ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , MachineBasicBlock :: iterator & NextMBBI ) {

return expandAuipcInstPair ( MBB , MBBI , NextMBBI , <STR_LIT> , <STR_LIT> ) ;


<s> return & InstrInfo . getRegisterInfo ( ) ;


<s> void setBase ( int Value ) { assert ( ! hasBase ( ) ) ; Base = Value ;


<s> tree idp ; rtx rtlname , newrtl ; rtx symref ; rtlname = XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) ; if ( GET_CODE ( rtlname ) == MEM ) rtlname = XEXP ( rtlname , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( rtlname ) == SYMBOL_REF ) ; oldname = XSTR ( rtlname , <NUM_LIT> ) ; if ( i386_pe_dllexport_name_p ( oldname ) ) { error ( <STR_LIT> , IDENTIFIER_POINTER ( DECL_NAME ( decl ) ) ) ; return ; } else if ( i386_pe_dllimport_name_p ( oldname ) ) { gcc_assert ( DECL_EXTERNAL ( decl ) && TREE_PUBLIC ( decl ) && DECL_DLLIMPORT_P ( decl ) ) ; return ; }

newname = alloca ( strlen ( DLL_IMPORT_PREFIX ) + strlen ( oldname ) + <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddressDarwin ( SDValue Op , SelectionDAG & DAG ) const { EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( Subtarget -> useMovt ( ) && RelocM != Reloc :: Static ) { ++ NumMovwMovt ; if ( RelocM == Reloc :: Static ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; unsigned Wrapper = ( RelocM == Reloc :: PIC_ ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( Wrapper , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; if ( Subtarget -> GVIsIndirectSymbol ( GV , RelocM ) ) Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( ) , false , false , <NUM_LIT> ) ; return Result ; } unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( GV , PtrVT , <NUM_LIT> ) ; } else { <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ;

SDValue Chain = Result . getValue ( <NUM_LIT> ) ;


<s> for ( int i = NumElems / <NUM_LIT> , j = <NUM_LIT> ; i < NumElems ; ++ i , ++ j ) if ( ! isUndefOrEqual ( SVOp -> getMaskElt ( i ) , j ) || SVOp -> getMaskElt ( j ) >= <NUM_LIT> ) return false ;