<s> if ( SETFOpc ) { unsigned FlagReg1 = createResultReg ( & <STR_LIT> ) ; unsigned FlagReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ; auto const & II = TII . get ( SETFOpc [ <NUM_LIT> ] ) ; if ( II . getNumDefs ( ) ) { unsigned TmpReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II , TmpReg ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( FlagReg2 ) . addReg ( FlagReg1 ) ; } } NeedTest = false ; } else if ( fold<ISA_LIT>XALUIntrinsic ( CC , I , Cond ) ) { unsigned TmpReg = getRegForValue ( Cond ) ; if ( TmpReg == <NUM_LIT> ) return false ; NeedTest = false ; } if ( NeedTest ) { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) { unsigned KCondReg = CondReg ; CondReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CondReg ) . addReg ( KCondReg , getKillRegState ( CondIsKill ) ) ; CondReg = fastEmitInst_extractsubreg ( <STR_LIT> , CondReg , true , <STR_LIT> ) ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ;

unsigned RHSReg = getRegForValue ( RHS ) ;


<s> int reg ; int live_regs_mask = <NUM_LIT> ; * count = <NUM_LIT> ; for ( reg = <NUM_LIT> ; reg < FIRST_PSEUDO_REGISTER ; reg ++ ) { if ( df_regs_ever_live_p ( reg ) && ! call_used_regs [ reg ] ) {


<s> void addVectorIndex32Operands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> enum attr_type use_insn_type = get_attr_type ( use_insn ) ; unsigned int use_regno ; rtx use_dest , use_src ; switch ( use_insn_type ) { case TYPE_LOAD : case TYPE_FPLOAD : case TYPE_VECLOAD : if ( addr_reg != get_mem_base_reg ( SET_SRC ( PATTERN ( use_insn ) ) ) ) return ; use_dest = SET_DEST ( PATTERN ( use_insn ) ) ; if ( ! register_operand ( use_dest , GET_MODE ( use_dest ) ) ) return ; use_regno = REGNO ( use_dest ) ; break ; case TYPE_STORE : case TYPE_FPSTORE : case TYPE_VECSTORE : if ( addr_reg != get_mem_base_reg ( SET_DEST ( PATTERN ( use_insn ) ) ) ) return ; use_src = SET_SRC ( PATTERN ( use_insn ) ) ; if ( ! register_operand ( use_src , GET_MODE ( use_src ) ) ) return ; use_regno = REGNO ( use_src ) ; break ; default : return ; } rtx_insn * insn ; for ( insn = NEXT_INSN ( addr_insn ) ; insn != use_insn ; insn = NEXT_INSN ( insn ) ) { if ( CALL_P ( insn ) ) return ; if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) { switch ( get_attr_type ( insn ) ) { case TYPE_LOAD : if ( get_attr_loads_external_address ( insn ) == LOADS_EXTERNAL_ADDRESS_YES ) break ; case TYPE_FPLOAD : case TYPE_VECLOAD : if ( use_insn_type == TYPE_STORE || use_insn_type == TYPE_FPSTORE || use_insn_type == TYPE_VECSTORE ) return ; break ; case TYPE_STORE : case TYPE_FPSTORE : case TYPE_VECSTORE : return ; case TYPE_LOAD_L : case TYPE_STORE_C : case TYPE_HTM : case TYPE_HTMSIMPLE : return ;


<s> const auto * ES = cast < ExternalSymbolSDNode > ( Op ) ; EVT VT = Op . getValueType ( ) ; assert ( ES -> getTargetFlags ( ) == <NUM_LIT> && <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , VT , <STR_LIT> ) ) ;


<s> MachineInstr & UseI = * I -> getParent ( ) ; if ( UseI . isPHI ( ) || UseI . isCopy ( ) ) { Register DefR = UseI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! DefR . isVirtual ( ) ) return false ; Pending . push_back ( DefR ) ; } else { if ( ! computeUsedBits ( UseI , I . getOperandNo ( ) , Used , B ) ) return false ; } } } Bits |= Used ; return true ;


<s> EVT VectorT1 = Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; EVT VectorT2 = Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; uint64_t Size = VectorT1 . getFixedSizeInBits ( ) ; if ( VectorT1 != VectorT2 || ( Size != <NUM_LIT> && Size != <NUM_LIT> ) ) return SDValue ( ) ; EVT VT1 = VectorT1 . getVectorElementType ( ) ; if ( VT1 != <STR_LIT> && VT1 != <STR_LIT> && VT1 != <STR_LIT> ) return SDValue ( ) ;


<s> SmallVector < MachineInstr * , <NUM_LIT> > Queue { MI } ; while ( ! Queue . empty ( ) ) { MI = Queue . pop_back_val ( ) ; if ( ! MI -> isCall ( ) ) { for ( auto & Op : MI -> defs ( ) ) { for ( auto & User : MRI . use_instructions ( Op . getReg ( ) ) ) Queue . push_back ( & User ) ; } MI -> eraseFromParent ( ) ; } else if ( isBXCall ( MI -> getOpcode ( ) ) ) { changeToPCRelativeCall ( MI , Callee ) ; } else { replaceWithDirectCall ( MI , Callee ) ; } }


<s> __vector unsigned char a , b , c ; a = ( __vector unsigned char ) vec_splats ( __A ) ;

b = ( __vector unsigned char ) vec_splats ( __B ) ;


<s> Error ( Tok . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } int Val = StringSwitch < int > ( Tok . getString ( ) ) . Case ( <STR_LIT> , <NUM_LIT> ) . Case ( <STR_LIT> , <NUM_LIT> ) . Default ( - <NUM_LIT> ) ; Parser . Lex ( ) ;


<s> return :: isSHUFPMask ( N -> op_begin ( ) , N -> getNumOperands ( ) ) ;


<s> PointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; AlignmentIsInBytes = false ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; UseDataRegionDirectives = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ; UseLogicalShr = true ;


<s> return ( int32x4_t ) __builtin_neon_vqdmulhv4si ( __a , __b ) ;


<s> tag_insn_info * i = new tag_insn_info ( insn , dest , base , offset , writeback , ldp ) ; rtx tag = GEN_INT ( i -> tag ( ) ) ; tag_map . get_or_insert ( tag ) . safe_push ( i ) ;


<s> const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode ( <NUM_LIT> , SImode ) ; const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode ( <NUM_LIT> , SImode ) ; const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode ( <NUM_LIT> , SImode ) ; unsigned HOST_WIDE_INT addr ;

if ( GET_CODE ( x ) == SYMBOL_REF ) return ( SYMBOL_REF_FLAGS ( x ) & SYMBOL_FLAG_EIGHTBIT_DATA ) != <NUM_LIT> ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MII ) : InstrInfo ( MII ) {


<s> return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <NUM_LIT> ; default : return - <NUM_LIT> ;


<s> auto <STR_LIT> ( int Val ) const -> ConstantInt * { return ConstantInt :: getSigned ( getIntTy ( ) , Val ) ;


<s> for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ; ( * MIB ) . setMemRefs ( MMOBegin , MMOEnd ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << LocationAsBlock ( Loc ) ) ; if ( OptEnableInv ) { for ( NodeVect :: iterator I = Roots . begin ( ) , E = Roots . end ( ) ; I != E ; ++ I ) adjustForInvariance ( * I , NCM , Loc ) ; DEBUG ( dbgs ( ) << <STR_LIT> << LocationAsBlock ( Loc ) ) ; } if ( OptEnableConst ) { for ( NodeVect :: iterator I = Roots . begin ( ) , E = Roots . end ( ) ; I != E ; ++ I ) separateConstantChains ( * I , NCM , Loc ) ; }

DEBUG ( dbgs ( ) << <STR_LIT> << Uses ) ;


<s> SDNode * <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallSDNode * TheCall , unsigned CallingConv , SelectionDAG & DAG ) { bool isVarArg = TheCall -> isVarArg ( ) ; DebugLoc dl = TheCall -> getDebugLoc ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallingConv , isVarArg , getTargetMachine ( ) , RVLocs ) ; CCInfo . AnalyzeCallResult ( TheCall , RetCC_<ISA_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > ResultVals ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ;

InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> return D ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> return static_cast < <ISA_LIT>VLMUL > ( VLMUL ) ;


<s> auto Info = std :: find_if ( Insts . begin ( ) , Insts . end ( ) , [ & ] ( InstInfo & Info ) { return Info . I == I ; } ) ; assert ( Info != Insts . end ( ) && <STR_LIT> ) ;


<s> TotCost += getScalarizationOverhead ( Dst , NeedsInserts , false ) ; if ( VF == <NUM_LIT> && SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) TotCost *= <NUM_LIT> ; return TotCost ; } if ( Opcode == Instruction :: FPTrunc ) { if ( SrcScalarBits == <NUM_LIT> ) return VF + getScalarizationOverhead ( Dst , true , false ) ; else return VF / <NUM_LIT> + std :: max ( <NUM_LIT> , VF / <NUM_LIT> ) ; } if ( Opcode == Instruction :: FPExt ) { if ( SrcScalarBits == <NUM_LIT> && DstScalarBits == <NUM_LIT> ) { return VF * <NUM_LIT> ; } return VF + getScalarizationOverhead ( Src , false , true ) ; } } else { assert ( ! Dst -> isVectorTy ( ) ) ; if ( Opcode == Instruction :: SIToFP || Opcode == Instruction :: UIToFP ) { if ( SrcScalarBits >= <NUM_LIT> || ( I != nullptr && isa < LoadInst > ( I -> getOperand ( <NUM_LIT> ) ) ) ) return <NUM_LIT> ; return SrcScalarBits > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; } if ( ( Opcode == Instruction :: ZExt || Opcode == Instruction :: SExt ) && Src -> isIntegerTy ( <NUM_LIT> ) ) { if ( ST -> hasLoadStoreOnCond2 ( ) ) return <NUM_LIT> ; unsigned Cost = <NUM_LIT> ; if ( Opcode == Instruction :: SExt ) Cost = ( DstScalarBits < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; if ( Opcode == Instruction :: ZExt ) Cost = <NUM_LIT> ;

Type * CmpOpTy = ( ( I != nullptr ) ? getCmpOpsType ( I ) : nullptr ) ;


<s> assert ( VT . isInteger ( ) && VT == LHS . getValueType ( ) && VT == RHS . getValueType ( ) && <STR_LIT> ) ; SDValue CC = DAG . getCondCode ( Cond ) ; SDValue LHS1 , LHS2 ; std :: tie ( LHS1 , LHS2 ) = splitVector ( LHS , DAG , dl ) ; SDValue RHS1 , RHS2 ; std :: tie ( RHS1 , RHS2 ) = splitVector ( RHS , DAG , dl ) ; EVT LoVT , HiVT ;

std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ;


<s> if ( isa < FrameIndexSDNode > ( Addr ) ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) return false ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { ; } else if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( ! CurDAG -> haveNoCommonBitsSet ( Addr . getOperand ( <NUM_LIT> ) , Addr . getOperand ( <NUM_LIT> ) ) ) return false ; } else { return false ; } if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; Base = Addr . getOperand ( <NUM_LIT> ) ;

Index = Addr . getOperand ( <NUM_LIT> ) ;


<s> MI . getParent ( ) -> erase ( MI ) ; return true ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { expandMEMCPY ( MI ) ; return true ; } if ( ! MI . isCopy ( ) || Subtarget . dontWidenVMOVS ( ) || Subtarget . isFPOnlySP ( ) ) return false ; unsigned DstRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ;

if ( ! DstRegD || ! SrcRegD ) return false ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> if ( Mnemonic . endswith ( <STR_LIT> ) && ! ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( Mnemonic == <STR_LIT> && isThumb ( ) ) ) ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; CarrySetting = true ; } if ( Mnemonic . startswith ( <STR_LIT> ) ) { unsigned IMod = StringSwitch < unsigned > ( Mnemonic . substr ( Mnemonic . size ( ) - <NUM_LIT> , <NUM_LIT> ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( ~ <NUM_LIT> ) ; if ( IMod != ~ <NUM_LIT> ) { Mnemonic = Mnemonic . slice ( <NUM_LIT> , Mnemonic . size ( ) - <NUM_LIT> ) ; ProcessorIMod = IMod ; } }

if ( isMnemonicVPTPredicable ( Mnemonic , ExtraToken ) && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> && Mnemonic != <STR_LIT> ) {


<s> return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> return mips_print_operand_punct [ code ] ;


<s> if ( INSN_CODE ( insn ) == CODE_FOR_insn_group_barrier ) { gcc_assert ( GET_MODE ( insn ) != TImode ) ; if ( ! try_issue_nops ( curr_state , before_nops_num ) ) return ; if ( ! try_issue_insn ( curr_state , insn ) ) return ; memcpy ( temp_dfa_state , curr_state -> dfa_state , dfa_state_size ) ; if ( curr_state -> accumulated_insns_num % <NUM_LIT> != <NUM_LIT> ) curr_state -> middle_bundle_stops ++ ; if ( state_transition ( temp_dfa_state , dfa_pre_cycle_insn ) >= <NUM_LIT> && curr_state -> accumulated_insns_num % <NUM_LIT> != <NUM_LIT> ) { free_bundle_state ( curr_state ) ; return ; } } else if ( GET_MODE ( insn ) != TImode ) { if ( ! try_issue_nops ( curr_state , before_nops_num ) ) return ; if ( ! try_issue_insn ( curr_state , insn ) ) return ; curr_state -> accumulated_insns_num ++ ; gcc_assert ( ! unknown_for_bundling_p ( insn ) ) ; if ( ia64_safe_type ( insn ) == TYPE_L ) curr_state -> accumulated_insns_num ++ ; } else { if ( before_nops_num > <NUM_LIT> && get_attr_first_insn ( insn ) == FIRST_INSN_YES ) { free_bundle_state ( curr_state ) ; return ; } state_transition ( curr_state -> dfa_state , dfa_pre_cycle_insn ) ; state_transition ( curr_state -> dfa_state , NULL ) ; curr_state -> cost ++ ; if ( ! try_issue_nops ( curr_state , before_nops_num ) ) return ; if ( ! try_issue_insn ( curr_state , insn ) ) return ; curr_state -> accumulated_insns_num ++ ; if ( unknown_for_bundling_p ( insn ) ) { curr_state -> after_nops_num = <NUM_LIT> - curr_state -> accumulated_insns_num % <NUM_LIT> ; curr_state -> accumulated_insns_num += <NUM_LIT> - curr_state -> accumulated_insns_num % <NUM_LIT> ; } else if ( ia64_safe_type ( insn ) == TYPE_L ) curr_state -> accumulated_insns_num ++ ; } if ( ia64_safe_type ( insn ) == TYPE_B ) curr_state -> branch_deviation += <NUM_LIT> - ( curr_state -> accumulated_insns_num - <NUM_LIT> ) % <NUM_LIT> ; if ( try_bundle_end_p && curr_state -> accumulated_insns_num % <NUM_LIT> != <NUM_LIT> ) { if ( ! only_bundle_end_p && insert_bundle_state ( curr_state ) ) { state_t dfa_state ; struct bundle_state * curr_state1 ; struct bundle_state * allocated_states_chain ; curr_state1 = get_free_bundle_state ( ) ; dfa_state = curr_state1 -> dfa_state ; allocated_states_chain = curr_state1 -> allocated_states_chain ; * curr_state1 = * curr_state ; curr_state1 -> dfa_state = dfa_state ; curr_state1 -> allocated_states_chain = allocated_states_chain ; memcpy ( curr_state1 -> dfa_state , curr_state -> dfa_state , dfa_state_size ) ;


<s> void setForcedEncodingSize ( unsigned Size ) {


<s> break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_DISP ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_HI16 , Type ) ; break ; case <STR_LIT> : Type = setRType ( ( unsigned ) ELF :: R_MIPS_GPREL16 , Type ) ; Type = setRType2 ( ( unsigned ) ELF :: R_MIPS_SUB , Type ) ; Type = setRType3 ( ( unsigned ) ELF :: R_MIPS_LO16 , Type ) ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHER ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_HIGHEST ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_GOT_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_CALL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_26_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_PC7_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_PC16_S1 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_CALL16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_DISP ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_PAGE ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_GOT_OFST ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_GD ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_LDM ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_DTPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_DTPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_TPREL_HI16 ; break ; case <STR_LIT> : Type = ELF :: R_MICROMIPS_TLS_TPREL_LO16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_PC19_S2 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_PC18_S3 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_PC21_S2 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_PC26_S2 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_PCHI16 ; break ; case <STR_LIT> : Type = ELF :: R_MIPS_PCLO16 ; break ;


<s> if ( Width == <NUM_LIT> ) return getLRForRMW32 ( Ordering ) ;

if ( Width == <NUM_LIT> ) return getLRForRMW64 ( Ordering ) ;


<s> enum attr_mode insn_mode = get_attr_mode ( insn ) ; switch ( insn_mode ) { case MODE_XI : case MODE_V8DF : case MODE_V16SF : return ix86_get_ssemov ( operands , <NUM_LIT> , insn_mode , mode ) ; case MODE_OI : case MODE_V4DF : case MODE_V8SF : return ix86_get_ssemov ( operands , <NUM_LIT> , insn_mode , mode ) ; case MODE_TI : case MODE_V2DF : case MODE_V4SF : return ix86_get_ssemov ( operands , <NUM_LIT> , insn_mode , mode ) ; case MODE_DI : if ( GENERAL_REG_P ( operands [ <NUM_LIT> ] ) ) { if ( HAVE_AS_IX86_INTERUNIT_MOVQ ) return <STR_LIT> ; else return <STR_LIT> ; } else if ( GENERAL_REG_P ( operands [ <NUM_LIT> ] ) ) { if ( HAVE_AS_IX86_INTERUNIT_MOVQ ) return <STR_LIT> ; else return <STR_LIT> ; } else return <STR_LIT> ; case MODE_SI :

if ( GENERAL_REG_P ( operands [ <NUM_LIT> ] ) ) return <STR_LIT> ;


<s> actual_fsize = <NUM_LIT> ; } else increment_stack ( - crtl -> args . pretend_args_size , true ) ; } save_all = NULL_RTX ; if ( TARGET_PROLOG_FUNCTION && ! crtl -> args . pretend_args_size && num_save > <NUM_LIT> ) { if ( use_prolog_function ( num_save , actual_fsize ) ) { int alloc_stack = <NUM_LIT> * num_save ; int offset = <NUM_LIT> ; save_all = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_save + <NUM_LIT> + ( TARGET_DISABLE_CALLT ? ( TARGET_LONG_CALLS ? <NUM_LIT> : <NUM_LIT> ) : <NUM_LIT> ) ) ) ; XVECEXP ( save_all , <NUM_LIT> , <NUM_LIT> ) = gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - alloc_stack ) ) ) ; for ( i = <NUM_LIT> ; i < num_save ; i ++ ) { offset -= <NUM_LIT> ; XVECEXP ( save_all , <NUM_LIT> , i + <NUM_LIT> ) = gen_rtx_SET ( gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ) , save_regs [ i ] ) ; } if ( TARGET_DISABLE_CALLT ) { XVECEXP ( save_all , <NUM_LIT> , num_save + <NUM_LIT> ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; if ( TARGET_LONG_CALLS ) XVECEXP ( save_all , <NUM_LIT> , num_save + <NUM_LIT> ) = gen_rtx_CLOBBER ( VOIDmode , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; } v850_all_frame_related ( save_all ) ; code = recog ( save_all , NULL , NULL ) ; if ( code >= <NUM_LIT> ) { rtx insn = emit_insn ( save_all ) ; INSN_CODE ( insn ) = code ; actual_fsize -= alloc_stack ; } else save_all = NULL_RTX ; } } if ( ! save_all ) {

if ( interrupt_handler && ( ( <NUM_LIT> << LINK_POINTER_REGNUM ) & reg_saved ) != <NUM_LIT> ) {


<s> if ( ! func_optimize ) func_optimize = optimization_default_node ; memset ( & func_options , <NUM_LIT> , sizeof ( func_options ) ) ; init_options_struct ( & func_options , NULL ) ; lang_hooks . init_options_struct ( & func_options ) ; cl_optimization_restore ( & func_options , TREE_OPTIMIZATION ( func_optimize ) ) ; cl_target_option_restore ( & func_options , TREE_TARGET_OPTION ( target_option_default_node ) ) ; cur_tree = arm_valid_target_attribute_tree ( args , & func_options , & global_options_set ) ; if ( cur_tree == NULL_TREE ) ret = false ; new_optimize = build_optimization_node ( & func_options ) ; DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) = cur_tree ; DECL_FUNCTION_SPECIFIC_OPTIMIZATION ( fndecl ) = new_optimize ; finalize_options_struct ( & func_options ) ; return ret ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { CmpInfo HeadCmpInfo = adjustCmp ( HeadCmpMI , HeadCmp ) ; CmpInfo TrueCmpInfo = adjustCmp ( TrueCmpMI , TrueCmp ) ; if ( std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) && std :: get < <NUM_LIT> > ( HeadCmpInfo ) == std :: get < <NUM_LIT> > ( TrueCmpInfo ) ) { modifyCmp ( HeadCmpMI , HeadCmpInfo ) ; modifyCmp ( TrueCmpMI , TrueCmpInfo ) ; Changed = true ; } } else if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { bool adjustHeadCond = ( HeadImm < TrueImm ) ; if ( HeadCmp == <STR_LIT> ) { adjustHeadCond = ! adjustHeadCond ; } if ( adjustHeadCond ) {

Changed |= adjustTo ( HeadCmpMI , HeadCmp , TrueCmpMI , TrueImm ) ;


<s> std :: vector < std :: string > labels ; for ( int i = <NUM_LIT> ; i < sgx_function_magic_labels_index ; i ++ ) labels . push_back ( <STR_LIT> + std :: to_string ( i ) ) ; return labels ;


<s> ++ FIOperandNum ; assert ( FIOperandNum < MI . getNumOperands ( ) && <STR_LIT> ) ; } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BaseReg , false ) ; unsigned OffsetOperandNo = getOffsetONFromFION ( MI , FIOperandNum ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ;

const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ;


<s> static SDValue lowerFABS32 ( SDValue Op , SelectionDAG & DAG , bool HasExtractInsert ) { SDValue Res , Const1 = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue X = ( Op . getValueType ( ) == <STR_LIT> ) ? DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) : DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Const1 ) ; if ( HasExtractInsert ) Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Const1 , X ) ; else { SDValue SllX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , Const1 ) ; Res = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SllX , Const1 ) ; } if ( Op . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Res ) ; SDValue LowX = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LowX , Res ) ;


<s> bool is_against_zero ; if ( GET_MODE ( op1 ) != compare_mode && ( ! TARGET_ISEL || ! short_cint_operand ( op1 , VOIDmode ) ) ) return <NUM_LIT> ; if ( GET_MODE ( true_cond ) != result_mode ) return <NUM_LIT> ; if ( GET_MODE ( false_cond ) != result_mode ) return <NUM_LIT> ; if ( TARGET_P9_MINMAX && ( compare_mode == SFmode || compare_mode == DFmode ) && ( result_mode == SFmode || result_mode == DFmode ) ) { if ( rs6000_emit_p9_fp_minmax ( dest , op , true_cond , false_cond ) ) return <NUM_LIT> ; if ( rs6000_emit_p9_fp_cmove ( dest , op , true_cond , false_cond ) ) return <NUM_LIT> ; } if ( FLOAT_MODE_P ( compare_mode ) && ! FLOAT_MODE_P ( result_mode ) ) return <NUM_LIT> ; if ( ! FLOAT_MODE_P ( compare_mode ) ) { if ( TARGET_ISEL ) return rs6000_emit_int_cmove ( dest , op , true_cond , false_cond ) ; return <NUM_LIT> ; } is_against_zero = op1 == CONST0_RTX ( compare_mode ) ; if ( SCALAR_FLOAT_MODE_P ( compare_mode ) && flag_trapping_math && ! is_against_zero ) return <NUM_LIT> ; if ( code == UNLT || code == UNGT || code == UNORDERED || code == NE || code == LTGT || code == LT || code == UNLE ) { code = reverse_condition_maybe_unordered ( code ) ; temp = true_cond ; true_cond = false_cond ; false_cond = temp ; } if ( code == UNEQ && HONOR_NANS ( compare_mode ) ) return <NUM_LIT> ; if ( HONOR_INFINITIES ( compare_mode ) && code != GT && code != UNGE && ( ! CONST_DOUBLE_P ( op1 ) || real_isinf ( CONST_DOUBLE_REAL_VALUE ( op1 ) ) ) && ( ( ! rtx_equal_p ( op0 , false_cond ) && ! rtx_equal_p ( op1 , false_cond ) ) || ( ! rtx_equal_p ( op0 , true_cond ) && ! rtx_equal_p ( op1 , true_cond ) ) ) ) return <NUM_LIT> ; if ( ! is_against_zero ) { temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_MINUS ( compare_mode , op0 , op1 ) ) ) ; op0 = temp ; op1 = CONST0_RTX ( compare_mode ) ; } if ( ! HONOR_NANS ( compare_mode ) ) switch ( code ) { case GT : code = LE ; temp = true_cond ; true_cond = false_cond ; false_cond = temp ; break ; case UNGE : code = GE ; break ; case UNEQ : code = EQ ; break ; default : break ; } switch ( code ) { case GE : break ; case LE : temp = gen_reg_rtx ( compare_mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_NEG ( compare_mode , op0 ) ) ) ; op0 = temp ; break ;


<s> const DataLayout * getDataLayout ( ) const override {


<s> long int <ISA_LIT>ELFWriterInfo :: getDefaultAddendForRelTy ( unsigned RelTy , long int Modifier ) const {


<s> DRNs . push_back ( DFG . addr < RefNode * > ( I ) ) ; continue ; } uint16_t Kind = BA . Addr -> getKind ( ) ; if ( Kind == NodeAttrs :: Stmt || Kind == NodeAttrs :: Phi ) { for ( auto N : NodeAddr < CodeNode * > ( BA ) . Addr -> members ( DFG ) ) DRNs . push_back ( N ) ; DINs . push_back ( DFG . addr < InstrNode * > ( I ) ) ; } else { llvm_unreachable ( <STR_LIT> ) ; return false ; } } auto UsesFirst = [ ] ( NodeAddr < RefNode * > A , NodeAddr < RefNode * > B ) -> bool { uint16_t KindA = A . Addr -> getKind ( ) , KindB = B . Addr -> getKind ( ) ; if ( KindA == NodeAttrs :: Use && KindB == NodeAttrs :: Def ) return true ; if ( KindA == NodeAttrs :: Def && KindB == NodeAttrs :: Use ) return false ; return A . Id < B . Id ; } ; llvm :: sort ( DRNs . begin ( ) , DRNs . end ( ) , UsesFirst ) ; if ( trace ( ) ) dbgs ( ) << <STR_LIT> ; for ( NodeAddr < RefNode * > RA : DRNs ) { if ( trace ( ) ) dbgs ( ) << <STR_LIT> << PrintNode < RefNode * > ( RA , DFG ) << '\n' ; if ( DFG . IsUse ( RA ) ) DFG . unlinkUse ( RA , true ) ; else if ( DFG . IsDef ( RA ) ) DFG . unlinkDef ( RA , true ) ; } for ( NodeAddr < InstrNode * > IA : DINs ) { NodeAddr < BlockNode * > BA = IA . Addr -> getOwner ( DFG ) ; BA . Addr -> removeMember ( IA , DFG ) ; if ( ! DFG . IsCode < NodeAttrs :: Stmt > ( IA ) ) continue ;

MachineInstr * MI = NodeAddr < StmtNode * > ( IA ) . Addr -> getCode ( ) ;


<s> case <NUM_LIT> : return <NUM_LIT> ; case <NUM_LIT> : return <STR_LIT> :: MULTIGRID_SYNC_ARG_OFFSET ;


<s> vld4_dup_u16 ( const uint16_t * __a ) { uint16x4x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4rv4hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint16x4_t ) __builtin_aarch64_get_dregxiv4hi ( __o , <NUM_LIT> ) ;


<s> SDValue Remainder_GE_Den = DAG . getSelectCC ( DL , Remainder , Den , DAG . getConstant ( - <NUM_LIT> , DL , VT ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) , <STR_LIT> ) ; SDValue Remainder_GE_Zero = DAG . getSelectCC ( DL , Num , Num_S_Remainder , DAG . getConstant ( - <NUM_LIT> , DL , VT ) , DAG . getConstant ( <NUM_LIT> , DL , VT ) , <STR_LIT> ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , DL , VT , Remainder_GE_Den , Remainder_GE_Zero ) ; SDValue Quotient_A_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Quotient_S_One = DAG . getNode ( <STR_LIT> , DL , VT , Quotient , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; SDValue Div = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Quotient , Quotient_A_One , <STR_LIT> ) ; Div = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Quotient_S_One , Div , <STR_LIT> ) ; SDValue Remainder_S_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Remainder_A_Den = DAG . getNode ( <STR_LIT> , DL , VT , Remainder , Den ) ; SDValue Rem = DAG . getSelectCC ( DL , Tmp1 , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Remainder , Remainder_S_Den , <STR_LIT> ) ; Rem = DAG . getSelectCC ( DL , Remainder_GE_Zero , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Remainder_A_Den , Rem , <STR_LIT> ) ; SDValue Ops [ <NUM_LIT> ] = { Div , Rem } ; return DAG . getMergeValues ( Ops , DL ) ;


<s> if ( ! hasSourceMods ( U ) ) return false ; if ( ! opMustUseVOP3Encoding ( U , VT ) ) { if ( ++ NumMayIncreaseSize > CostThreshold ) return false ; } }


<s> AddDefaultPred ( BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) ) . addMBB ( TBB ) ; } else { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; } return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addOperand ( Cond [ <NUM_LIT> ] ) . addOperand ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; AddDefaultPred ( BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) ) . addMBB ( FBB ) ;


<s> rtx branch_rtx = gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , cmp_rtx , gen_rtx_LABEL_REF ( VOIDmode , operands [ <NUM_LIT> ] ) , pc_rtx ) ) ; emit_jump_insn ( branch_rtx ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const {


<s> uint64_t Amount = Old . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { Amount = ( Amount + StackAlign - <NUM_LIT> ) / StackAlign * StackAlign ; MachineInstr * New = nullptr ; if ( Old . getOpcode ( ) == TII . getCallFrameSetupOpcode ( ) ) { New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } else { assert ( Old . getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) ; uint64_t CalleeAmt = Old . getOperand ( <NUM_LIT> ) . getImm ( ) ; Amount -= CalleeAmt ; if ( Amount ) New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { MachineInstr & Old = * I ; MachineInstr * New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( CalleeAmt ) ;


<s> set_optab_libfunc ( sdiv_optab , DFmode , CSKY_GCC_SYM ( divdf3 ) ) ; set_optab_libfunc ( neg_optab , SFmode , CSKY_GCC_SYM ( negsf2 ) ) ; set_optab_libfunc ( neg_optab , DFmode , CSKY_GCC_SYM ( negdf2 ) ) ; set_conv_libfunc ( sext_optab , DFmode , SFmode , CSKY_GCC_SYM ( extendsfdf2 ) ) ; set_conv_libfunc ( trunc_optab , SFmode , DFmode , CSKY_GCC_SYM ( truncdfsf2 ) ) ; set_conv_libfunc ( sfix_optab , SImode , SFmode , CSKY_GCC_SYM ( fixsfsi ) ) ; set_conv_libfunc ( sfix_optab , SImode , DFmode , CSKY_GCC_SYM ( fixdfsi ) ) ; set_conv_libfunc ( sfix_optab , DImode , SFmode , CSKY_GCC_SYM ( fixsfdi ) ) ; set_conv_libfunc ( sfix_optab , DImode , DFmode , CSKY_GCC_SYM ( fixdfdi ) ) ; set_conv_libfunc ( ufix_optab , SImode , SFmode , CSKY_GCC_SYM ( fixunssfsi ) ) ; set_conv_libfunc ( ufix_optab , SImode , DFmode , CSKY_GCC_SYM ( fixunsdfsi ) ) ; set_conv_libfunc ( ufix_optab , DImode , SFmode , CSKY_GCC_SYM ( fixunssfdi ) ) ; set_conv_libfunc ( ufix_optab , DImode , DFmode , CSKY_GCC_SYM ( fixunsdfdi ) ) ; set_conv_libfunc ( sfloat_optab , SFmode , SImode , CSKY_GCC_SYM ( floatsisf ) ) ; set_conv_libfunc ( sfloat_optab , DFmode , SImode , CSKY_GCC_SYM ( floatsidf ) ) ; set_conv_libfunc ( sfloat_optab , SFmode , DImode , CSKY_GCC_SYM ( floatdisf ) ) ; set_conv_libfunc ( sfloat_optab , DFmode , DImode , CSKY_GCC_SYM ( floatdidf ) ) ; set_conv_libfunc ( ufloat_optab , SFmode , SImode , CSKY_GCC_SYM ( floatunsisf ) ) ; set_conv_libfunc ( ufloat_optab , DFmode , SImode , CSKY_GCC_SYM ( floatunsidf ) ) ; set_conv_libfunc ( ufloat_optab , SFmode , DImode , CSKY_GCC_SYM ( floatundisf ) ) ; set_conv_libfunc ( ufloat_optab , DFmode , DImode , CSKY_GCC_SYM ( floatundidf ) ) ; set_optab_libfunc ( cmp_optab , SFmode , CSKY_GCC_SYM ( cmpsf2 ) ) ; set_optab_libfunc ( cmp_optab , DFmode , CSKY_GCC_SYM ( cmpdf2 ) ) ; set_optab_libfunc ( unord_optab , SFmode , CSKY_GCC_SYM ( unordsf2 ) ) ; set_optab_libfunc ( unord_optab , DFmode , CSKY_GCC_SYM ( unorddf2 ) ) ; set_optab_libfunc ( eq_optab , SFmode , CSKY_GCC_SYM ( eqsf2 ) ) ; set_optab_libfunc ( eq_optab , DFmode , CSKY_GCC_SYM ( eqdf2 ) ) ; set_optab_libfunc ( ne_optab , SFmode , CSKY_GCC_SYM ( nesf2 ) ) ; set_optab_libfunc ( ne_optab , DFmode , CSKY_GCC_SYM ( nedf2 ) ) ; set_optab_libfunc ( ge_optab , SFmode , CSKY_GCC_SYM ( gesf2 ) ) ; set_optab_libfunc ( ge_optab , DFmode , CSKY_GCC_SYM ( gedf2 ) ) ; set_optab_libfunc ( lt_optab , SFmode , CSKY_GCC_SYM ( ltsf2 ) ) ; set_optab_libfunc ( lt_optab , DFmode , CSKY_GCC_SYM ( ltdf2 ) ) ; set_optab_libfunc ( le_optab , SFmode , CSKY_GCC_SYM ( lesf2 ) ) ; set_optab_libfunc ( le_optab , DFmode , CSKY_GCC_SYM ( ledf2 ) ) ; set_optab_libfunc ( gt_optab , SFmode , CSKY_GCC_SYM ( gtsf2 ) ) ; set_optab_libfunc ( gt_optab , DFmode , CSKY_GCC_SYM ( gtdf2 ) ) ;


<s> void insertSSPDeclarations ( Module & M ) const override {


<s> MCInst LEASLInst ; LEASLInst . setOpcode ( <STR_LIT> ) ; LEASLInst . addOperand ( RD ) ;


<s> static void nds32_emit_mem_move ( rtx src , rtx dst , enum machine_mode mode , int addr_offset ) { gcc_assert ( MEM_P ( src ) && MEM_P ( dst ) ) ; rtx tmp_reg = gen_reg_rtx ( mode ) ; nds32_emit_load_store ( tmp_reg , src , mode , addr_offset , true ) ;

nds32_emit_load_store ( tmp_reg , dst , mode , addr_offset , false ) ;


<s> for ( auto I = MRI . use_nodbg_begin ( FromReg ) , E = MRI . use_nodbg_end ( ) ; I != E ; ) { MachineOperand & O = * I ++ ; MachineInstr * Where = O . getParent ( ) ; if ( & MI == Where || ! MDT . dominates ( & MI , Where ) ) continue ; SlotIndex WhereIdx = LIS . getInstructionIndex ( * Where ) ; VNInfo * WhereVNI = FromLI -> getVNInfoAt ( WhereIdx ) ; if ( WhereVNI && WhereVNI != FromVNI ) continue ; VNInfo * ToVNI = ToLI -> getVNInfoAt ( WhereIdx ) ; if ( ToVNI && ToVNI != FromVNI ) continue ; Changed = true ; DEBUG ( dbgs ( ) << <STR_LIT> << O << <STR_LIT> << * Where << <STR_LIT> << MI << <STR_LIT> ) ; O . setReg ( ToReg ) ; if ( ! O . isUndef ( ) ) { MI . getOperand ( <NUM_LIT> ) . setIsDead ( false ) ; Indices . push_back ( WhereIdx . getRegSlot ( ) ) ;


<s> switch ( Op . getOpcode ( ) ) { default : report_fatal_error ( <STR_LIT> ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : {

assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ;


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const {


<s> Type * ValTy = cast < PointerType > ( AlignedAddr -> getType ( ) ) -> getElementType ( ) ; assert ( ValTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) ; Function * IntCmpXchg = <STR_LIT> ( M , <STR_LIT> ) ; Type * Int64Ty = Type :: getInt64Ty ( M -> getContext ( ) ) ; Value * CmpLo = Builder . CreateTrunc ( CmpVal , Int64Ty , <STR_LIT> ) ; Value * CmpHi = Builder . CreateTrunc ( Builder . CreateLShr ( CmpVal , <NUM_LIT> ) , Int64Ty , <STR_LIT> ) ; Value * NewLo = Builder . CreateTrunc ( NewVal , Int64Ty , <STR_LIT> ) ; Value * NewHi = Builder . CreateTrunc ( Builder . CreateLShr ( NewVal , <NUM_LIT> ) , Int64Ty , <STR_LIT> ) ;

Value * Addr = Builder . CreateBitCast ( AlignedAddr , Type :: getInt8PtrTy ( M -> getContext ( ) ) ) ;


<s> void addMVEVecListOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCRegisterClass * RC_in = & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] ; const MCRegisterClass * RC_out = ( VectorList . Count == <NUM_LIT> ) ? & <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] :


<s> int32_t Val = cast < ConstantSDNode > ( OffsetNode ) -> getSExtValue ( ) ; EVT StoredVT = ST -> getMemoryVT ( ) ; EVT ValueVT = Value . getValueType ( ) ; const <ISA_LIT>InstrInfo & TII = * HST -> getInstrInfo ( ) ; if ( TII . isValidAutoIncImm ( StoredVT , Val ) ) { unsigned Opcode = <NUM_LIT> ; if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( StoredVT == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; if ( ST -> isTruncatingStore ( ) && ValueVT . getSizeInBits ( ) == <NUM_LIT> ) { assert ( StoredVT . getSizeInBits ( ) < <NUM_LIT> && <STR_LIT> ) ; Value = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , Value ) ; } SDValue Ops [ ] = { Base , CurDAG -> getTargetConstant ( Val , <STR_LIT> ) , Value , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = ST -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ;


<s> MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ;

else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ;


<s> if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( V . hasOneUse ( ) && V . getOpcode ( ) == <STR_LIT> ) V = V . getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( V . getNode ( ) ) ) return true ; return false ;


<s> const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF -> getSubtarget ( ) . getInstrInfo ( ) ) ; LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; bool IsLoad = TII -> get ( LoadStoreOp ) . mayLoad ( ) ; bool RanOutOfSGPRs = false ; bool Scavenged = false ; unsigned SOffset = ScratchOffset ; unsigned NumSubRegs = getNumSubRegsForSpillOp ( MI -> getOpcode ( ) ) ; unsigned Size = NumSubRegs * <NUM_LIT> ; if ( ! isUInt < <NUM_LIT> > ( Offset + Size ) ) { SOffset = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; if ( SOffset == <STR_LIT> ) { RanOutOfSGPRs = true ; SOffset = <STR_LIT> ; } else { Scavenged = true ; } BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SOffset ) . addReg ( ScratchOffset ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; } if ( RanOutOfSGPRs ) Ctx . emitError ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i != e ; ++ i , Offset += <NUM_LIT> ) { unsigned SubReg = NumSubRegs > <NUM_LIT> ? getPhysRegSubReg ( Value , & <STR_LIT> , i ) : Value ; unsigned SOffsetRegState = <NUM_LIT> ; if ( i + <NUM_LIT> == e && Scavenged ) SOffsetRegState |= RegState :: Kill ; BuildMI ( * MBB , MI , DL , TII -> get ( LoadStoreOp ) ) . addReg ( SubReg , getDefRegState ( IsLoad ) ) . addReg ( ScratchRsrcReg ) . addReg ( SOffset , SOffsetRegState ) . addImm ( Offset ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( Value , RegState :: Implicit | getDefRegState ( IsLoad ) ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; }


<s> case fixup_<ISA_LIT>_B15_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B22_PCREL : if ( ! ( isIntN ( <NUM_LIT> , sValue ) ) ) HandleFixupError ( <NUM_LIT> , <NUM_LIT> , ( int64_t ) FixupValue , <STR_LIT> ) ; LLVM_FALLTHROUGH ; case fixup_<ISA_LIT>_B22_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; break ; case fixup_<ISA_LIT>_B32_PCREL_X : InstMask = <NUM_LIT> ; Reloc = ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ; break ; case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case fixup_<ISA_LIT>_32 : InstMask = <NUM_LIT> ; Reloc = Value ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << getFixupKindInfo ( Kind ) . Name << <STR_LIT> << ( unsigned ) Kind << <STR_LIT> ) ;

LLVM_DEBUG ( uint32_t OldData = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumBytes ; i ++ ) OldData |= ( InstAddr [ i ] << ( i * <NUM_LIT> ) ) & ( <NUM_LIT> << ( i * <NUM_LIT> ) ) ;


<s> bool <STR_LIT> ( ShuffleVectorSDNode * N , unsigned UnitSize , unsigned ShuffleKind , SelectionDAG & DAG ) { if ( DAG . getTarget ( ) . getDataLayout ( ) -> isLittleEndian ( ) ) { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else return false ; } else { if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , UnitSize , <NUM_LIT> , <NUM_LIT> ) ;


<s> TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( getMalkrzFromFiMalkrz ( I -> getOpcode ( ) ) == <STR_LIT> && <STR_LIT> ) ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( I -> getOpcode ( ) ) ) ; for ( unsigned i = <NUM_LIT> ; i < I -> getNumOperands ( ) ; i ++ ) {

Cond . push_back ( I -> getOperand ( i ) ) ;


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Src = DAG . getFreeze ( Op . getOperand ( <NUM_LIT> ) ) ; SDValue Abs = DAG . getNode ( <STR_LIT> , DL , VT , Src ) ; const fltSemantics & FltSem = DAG . EVTToAPFloatSemantics ( VT ) ; bool Ignored ; APFloat Point5Pred = APFloat ( <NUM_LIT> ) ; Point5Pred . convert ( FltSem , APFloat :: rmNearestTiesToEven , & Ignored ) ; Point5Pred . next ( true ) ; SDValue Adjust = DAG . getNode ( <STR_LIT> , DL , VT , Abs , DAG . getConstantFP ( Point5Pred , DL , VT ) ) ; MVT IntVT = VT . changeVectorElementTypeToInteger ( ) ; SDValue Truncated = DAG . getNode ( <STR_LIT> , DL , IntVT , Adjust ) ; Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated ) ; Truncated = DAG . getNode ( <STR_LIT> , DL , VT , Truncated , Src ) ;

unsigned Precision = APFloat :: semanticsPrecision ( FltSem ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> bool <ISA_LIT>TargetLowering :: useLoadStackGuardNode ( ) const { if ( Subtarget -> isTargetAndroid ( ) || Subtarget -> isTargetFuchsia ( ) ) return TargetLowering :: useLoadStackGuardNode ( ) ; return true ;


<s> unsigned getMaxNumVGPRs ( const MCSubtargetInfo * STI , unsigned WavesPerEU ) { assert ( WavesPerEU != <NUM_LIT> ) ; unsigned MaxNumVGPRs = alignDown ( getTotalNumVGPRs ( STI ) / WavesPerEU , getVGPRAllocGranule ( STI ) ) ; unsigned AddressableNumVGPRs = getAddressableNumVGPRs ( STI ) ;

return std :: min ( MaxNumVGPRs , AddressableNumVGPRs ) ;


<s> void set_color ( auto_vec < unsigned > & color_counts ) {

color = brackets . last ( ) . get_color ( color_counts , brackets . length ( ) ) ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> if ( isInt < <NUM_LIT> > ( CI -> getSExtValue ( ) ) ) { unsigned Opc = <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addReg ( <STR_LIT> ) . addImm ( CI -> getSExtValue ( ) ) ; return ImmReg ; } return <NUM_LIT> ;


<s> const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; unsigned adjustment = <NUM_LIT> ; if ( MF . protectReturnPtr ( ) && ! MF . getName ( ) . equals ( <STR_LIT> ) ) adjustment += RegInfo -> getSlotSize ( ) ;

if ( hasFP ( MF ) && MF . protectFramePtr ( ) ) adjustment += RegInfo -> getSlotSize ( ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , GPU , FS ) , <ISA_LIT>Subtarget ( TT ) , InstrInfo ( * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) , TLInfo ( TM , initializeSubtargetDependencies ( TT , GPU , FS ) ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) {


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return true ;


<s> if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) align = <NUM_LIT> ; break ; case <NUM_LIT> : if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ) return MCDisassembler :: Fail ; index = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) != <NUM_LIT> ) align = <NUM_LIT> ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) {

if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op . getResNo ( ) == <NUM_LIT> ) break ; LLVM_FALLTHROUGH ; case <STR_LIT> : KnownZero . setBits ( <NUM_LIT> , BitWidth ) ; break ; case <STR_LIT> : { unsigned NumLoBits = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorNumElements ( ) ; KnownZero . setBits ( NumLoBits , BitWidth ) ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( auto * ShiftImm = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) { if ( ShiftImm -> getAPIntValue ( ) . uge ( VT . getScalarSizeInBits ( ) ) ) { KnownZero = APInt :: getAllOnesValue ( BitWidth ) ; break ; } DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , KnownZero , KnownOne , Depth + <NUM_LIT> ) ; unsigned ShAmt = ShiftImm -> getZExtValue ( ) ; if ( Opc == <STR_LIT> ) {


<s> explicit <ISA_LIT>MCExpr ( const MCExpr * Expr , VariantKind Kind ) : Expr ( Expr ) , Kind ( Kind ) {


<s> to = mips_canonicalize_move_class ( to ) ; if ( from == FP_REGS ) { if ( to == FP_REGS && mips_mode_ok_for_mov_fmt_p ( mode ) ) return <NUM_LIT> ; } dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS ;

if ( from == dregs ) return mips_move_from_gpr_cost ( to ) ;


<s> assert ( ! TRI -> hasBasePointer ( MF ) && <STR_LIT> ) ;

FrameReg = TRI -> getStackRegister ( ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCSubtargetInfo & sti , MCContext & ctx , bool IsLittle ) :

MCII ( mcii ) , STI ( sti ) , Ctx ( ctx ) , IsLittleEndian ( IsLittle ) {


<s> int type = DW_EH_PE_sdata8 ; if ( ptr_mode == SImode || ix86_cmodel == CM_SMALL_PIC || ( ix86_cmodel == CM_MEDIUM_PIC && ( global || code ) ) ) type = DW_EH_PE_sdata4 ; return ( global ? DW_EH_PE_indirect : <NUM_LIT> ) | DW_EH_PE_pcrel | type ; } if ( ix86_cmodel == CM_SMALL || ( ix86_cmodel == CM_MEDIUM && code ) ) return DW_EH_PE_udata4 ; return DW_EH_PE_absptr ;


<s> bool VGPRDefined = true ; if ( MBB == & MF -> front ( ) ) VGPRDefined = ! SGPRSpillVGPRDefinedSet . insert ( Spill . VGPR ) . second ; auto MIB = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , Spill . VGPR ) . addReg ( SubReg , getKillRegState ( UseKill ) ) . addImm ( Spill . Lane ) . addReg ( Spill . VGPR , VGPRDefined ? <NUM_LIT> : RegState :: Undef ) ; if ( i == <NUM_LIT> && NumSubRegs > <NUM_LIT> ) { MIB . addReg ( SuperReg , RegState :: ImplicitDefine ) ; } if ( NumSubRegs > <NUM_LIT> ) MIB . addReg ( SuperReg , getKillRegState ( UseKill ) | RegState :: Implicit ) ; } } else { Register TmpVGPR = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> ) ; RS -> setRegUsed ( TmpVGPR ) ; unsigned SubKillState = getKillRegState ( ( NumSubRegs == <NUM_LIT> ) && IsKill ) ; unsigned PerVGPR = <NUM_LIT> ; unsigned NumVGPRs = ( NumSubRegs + ( PerVGPR - <NUM_LIT> ) ) / PerVGPR ; int64_t VGPRLanes = ( <NUM_LIT> << std :: min ( PerVGPR , NumSubRegs ) ) - <NUM_LIT> ; for ( unsigned Offset = <NUM_LIT> ; Offset < NumVGPRs ; ++ Offset ) { unsigned TmpVGPRFlags = RegState :: Undef ; for ( unsigned i = Offset * PerVGPR , e = std :: min ( ( Offset + <NUM_LIT> ) * PerVGPR , NumSubRegs ) ; i < e ; ++ i ) { Register SubReg = NumSubRegs == <NUM_LIT> ? SuperReg : Register ( getSubReg ( SuperReg , SplitParts [ i ] ) ) ; MachineInstrBuilder WriteLane = BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addReg ( SubReg , SubKillState ) . addImm ( i % PerVGPR ) . addReg ( TmpVGPR , TmpVGPRFlags ) ; TmpVGPRFlags = <NUM_LIT> ; if ( NumSubRegs > <NUM_LIT> ) { unsigned SuperKillState = <NUM_LIT> ; if ( i + <NUM_LIT> == NumSubRegs ) SuperKillState |= getKillRegState ( IsKill ) ; WriteLane . addReg ( SuperReg , RegState :: Implicit | SuperKillState ) ; } } buildSGPRSpillLoadStore ( MI , Index , Offset , EltSize , TmpVGPR , VGPRLanes , RS , false ) ; }


<s> initialize<ISA_LIT>TransformIntrinPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> SDLoc DL ( N ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) == N1 && isAllOnes ( N0 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 ) ;

if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) == N0 && isAllOnes ( N1 . getOperand ( <NUM_LIT> ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( ( ST -> hasNEON ( ) || ST -> hasMVEIntegerOps ( ) ) && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue Vec = N0 . getOperand ( <NUM_LIT> ) ; SDValue Lane = N0 . getOperand ( <NUM_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT EltVT = N0 . getValueType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( VT == <STR_LIT> && ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && TLI . isTypeLegal ( Vec . getValueType ( ) ) && isa < ConstantSDNode > ( Lane ) ) { unsigned Opc = <NUM_LIT> ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> OutRetAddr = getReturnAddressFrameIndex ( DAG ) ; OutRetAddr = DAG . getLoad ( VT , dl , Chain , OutRetAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;

return SDValue ( OutRetAddr . getNode ( ) , <NUM_LIT> ) ;


<s> case POST_INC : case PRE_DEC : ok = avr_reg_ok_for_addr_p ( XEXP ( x , <NUM_LIT> ) , ADDR_SPACE_GENERIC , GET_CODE ( x ) , strict ) ; break ; case PLUS : { rtx reg = XEXP ( x , <NUM_LIT> ) ; rtx op1 = XEXP ( x , <NUM_LIT> ) ; if ( REG_P ( reg ) && CONST_INT_P ( op1 ) && INTVAL ( op1 ) >= <NUM_LIT> ) { bool fit = IN_RANGE ( INTVAL ( op1 ) , <NUM_LIT> , MAX_LD_OFFSET ( mode ) ) ; if ( fit ) { ok = ( ! strict || avr_reg_ok_for_addr_p ( reg , ADDR_SPACE_GENERIC , PLUS , strict ) ) ; if ( reg == frame_pointer_rtx || reg == arg_pointer_rtx ) { ok = true ; } } else if ( frame_pointer_needed && reg == frame_pointer_rtx ) { ok = true ; } } } break ; default : break ; }

if ( AVR_TINY && CONSTANT_ADDRESS_P ( x ) ) {


<s> case SYMBOL_PCREL : { static unsigned seqno ; char buf [ <NUM_LIT> ] ; rtx label ; ssize_t bytes = snprintf ( buf , sizeof ( buf ) , <STR_LIT> , seqno ) ; gcc_assert ( ( size_t ) bytes < sizeof ( buf ) ) ; label = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( buf ) ) ; SYMBOL_REF_FLAGS ( label ) |= SYMBOL_FLAG_LOCAL ; if ( ! nonzero_address_p ( addr ) ) SYMBOL_REF_WEAK ( label ) = <NUM_LIT> ; if ( temp == NULL ) temp = gen_reg_rtx ( Pmode ) ; if ( Pmode == DImode ) emit_insn ( gen_auipcdi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ;

else emit_insn ( gen_auipcsi ( temp , copy_rtx ( addr ) , GEN_INT ( seqno ) ) ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumLaneElts ; ++ i ) { unsigned Base = i + Offset ; if ( Base >= NumLaneElts ) Base = Unary ? Base % NumLaneElts : Base + NumElts - NumLaneElts ; ShuffleMask . push_back ( Base + l ) ; }


<s> MachineOperand & SrcOp = MI . getOperand ( ArgOffset + I ) ; if ( ! SrcOp . isReg ( ) ) continue ; Register AddrReg = SrcOp . getReg ( ) ; if ( ( I < Intr -> GradientStart ) || ( I >= Intr -> GradientStart && I < Intr -> CoordStart && ! IsG16 ) || ( I >= Intr -> CoordStart && ! IsA16 ) ) { if ( ( I < Intr -> GradientStart ) && IsA16 && ( B . getMRI ( ) -> getType ( AddrReg ) == S16 ) ) { PackedAddrs . push_back ( B . buildBuildVector ( V2S16 , { AddrReg , B . buildUndef ( S16 ) . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ) ; } else { AddrReg = B . buildBitcast ( V2S16 , AddrReg ) . getReg ( <NUM_LIT> ) ; PackedAddrs . push_back ( AddrReg ) ; } } else {

if ( ( ( I + <NUM_LIT> ) >= EndIdx ) || ( ( Intr -> NumGradients / <NUM_LIT> ) % <NUM_LIT> == <NUM_LIT> && ( I == static_cast < unsigned > ( Intr -> GradientStart + ( Intr -> NumGradients / <NUM_LIT> ) - <NUM_LIT> ) || I == static_cast < unsigned > ( Intr -> GradientStart + Intr -> NumGradients - <NUM_LIT> ) ) ) || ! MI . getOperand ( ArgOffset + I + <NUM_LIT> ) . isReg ( ) ) {


<s> __v2df a , b , c ; a = vec_splats ( __A [ <NUM_LIT> ] ) ; b = vec_splats ( __B [ <NUM_LIT> ] ) ;


<s> static rtx altivec_expand_dst_builtin ( tree exp , rtx target ATTRIBUTE_UNUSED , bool * expandedp ) { tree fndecl = TREE_OPERAND ( TREE_OPERAND ( exp , <NUM_LIT> ) , <NUM_LIT> ) ; tree arglist = TREE_OPERAND ( exp , <NUM_LIT> ) ; unsigned int fcode = DECL_FUNCTION_CODE ( fndecl ) ; tree arg0 , arg1 , arg2 ; enum machine_mode mode0 , mode1 , mode2 ; rtx pat , op0 , op1 , op2 ; struct builtin_description * d ; size_t i ; * expandedp = false ; d = ( struct builtin_description * ) bdesc_dst ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_dst ) ; i ++ , d ++ ) if ( d -> code == fcode ) { arg0 = TREE_VALUE ( arglist ) ; arg1 = TREE_VALUE ( TREE_CHAIN ( arglist ) ) ; arg2 = TREE_VALUE ( TREE_CHAIN ( TREE_CHAIN ( arglist ) ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; op1 = expand_expr ( arg1 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; op2 = expand_expr ( arg2 , NULL_RTX , VOIDmode , <NUM_LIT> ) ; mode0 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; mode2 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; * expandedp = true ; STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> , d -> name ) ; return const0_rtx ; } if ( ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( Pmode , op0 ) ; if ( ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ;

pat = GEN_FCN ( d -> icode ) ( op0 , op1 , op2 ) ;


<s> StringRef getPassName ( ) const override {


<s> const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_<ISA_LIT>_DTPREL , getContext ( ) ) ;

return MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) , getContext ( ) ) ;


<s> static_assert ( ! std :: is_void < T > :: value , <STR_LIT> ) ; delete p ;


<s> bool SelectAddrImm ( SDNode * Op , SDValue N , SDValue & Disp , SDValue & Base ) { return <ISA_LIT>Lowering . SelectAddressRegImm ( N , Disp , Base , * CurDAG ) ;


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) {

MachineFunction & MF = DAG . getMachineFunction ( ) ;


<s> <ISA_LIT>FrameInfo ( const TargetMachine & tm , bool LP64 ) : TargetFrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , TM ( tm ) {


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase * PassManager ) : TargetPassConfig ( TM , * PassManager ) {


<s> if ( flag_pic ) nios2_gpopt_option = gpopt_none ; else nios2_gpopt_option = gpopt_local ; } if ( ! TARGET_HAS_MUL && TARGET_HAS_MULX ) target_flags &= ~ MASK_HAS_MULX ; if ( ! TARGET_ARCH_R2 ) { if ( TARGET_HAS_BMX ) error ( <STR_LIT> ) ; if ( TARGET_HAS_CDX ) error ( <STR_LIT> ) ; } if ( TARGET_ARCH_R2 && TARGET_BIG_ENDIAN ) error ( <STR_LIT> ) ;


<s> } } for ( SmallVectorImpl < MachineBasicBlock * > :: iterator It = ContMBB . begin ( ) , E = ContMBB . end ( ) ; It != E ; ++ It ) { ( * It ) -> removeSuccessor ( LoopHeader , true ) ; } numLoopcontPatternMatch += NumCont ; return NumCont ;


<s> __attribute__ ( ( __always_inline__ , __gnu_inline__ , __artificial__ ) ) __ignore_saturation ( void ) {


<s> auto foundIndex = std :: find ( minimalCaps . begin ( ) , minimalCaps . end ( ) , cap ) ; if ( foundIndex != minimalCaps . end ( ) ) { minimalCaps . erase ( foundIndex ) ; } CapabilityList implicitDeclares = getSymbolicOperandCapabilities ( OperandCategory :: CapabilityOperand , cap ) ;

pruneCapabilities ( implicitDeclares ) ;


<s> tree minus_one_vec = build_minus_one_cst ( type ) ; tree temp = create_tmp_reg_or_ssa_name ( cmp_type ) ; gimple * g = gimple_build_assign ( temp , code , arg0 , arg1 ) ;

gsi_insert_before ( gsi , g , GSI_SAME_STMT ) ;


<s> if ( UNSPEC_ADDRESS_P ( x ) ) { * symbol_type = UNSPEC_ADDRESS_TYPE ( x ) ; x = UNSPEC_ADDRESS ( x ) ; } else if ( SYMBOL_REF_P ( x ) || LABEL_REF_P ( x ) ) { * symbol_type = loongarch_classify_symbol ( x ) ; if ( * symbol_type == SYMBOL_TLS ) return true ; } else return false ; if ( offset == const0_rtx ) return true ; switch ( * symbol_type ) { case SYMBOL_GOT_DISP :


<s> std :: vector < MachineInstr * > ToRemove ; int64_t DMBType = - <NUM_LIT> ; for ( auto & MBB : MF ) { bool IsRemovableNextDMB = false ; for ( auto & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> ) { if ( IsRemovableNextDMB ) { if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == DMBType ) { ToRemove . push_back ( & MI ) ; } else { DMBType = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; }


<s> __i1 = __i1 << <NUM_LIT> | ( unsigned char ) __b5 ; __i1 = __i1 << <NUM_LIT> | ( unsigned char ) __b4 ; __i0 = ( unsigned char ) __b3 ; __i0 = __i0 << <NUM_LIT> | ( unsigned char ) __b2 ; __i0 = __i0 << <NUM_LIT> | ( unsigned char ) __b1 ; __i0 = __i0 << <NUM_LIT> | ( unsigned char ) __b0 ; return _mm_set_pi32 ( __i1 , __i0 ) ;


<s> dbgs ( ) << <STR_LIT> << <ISA_LIT> << <STR_LIT> << * LIS . getInstructionFromIndex ( <ISA_LIT> ) ; unsigned Num = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , E = MRI . getNumVirtRegs ( ) ; I != E ; ++ I ) { const unsigned Reg = TargetRegisterInfo :: index2VirtReg ( I ) ; if ( MRI . reg_nodbg_empty ( Reg ) ) continue ; const auto & LI = LIS . getInterval ( Reg ) ; if ( LI . hasSubRanges ( ) ) { bool firstTime = true ; for ( const auto & S : LI . subranges ( ) ) { if ( ! S . liveAt ( <ISA_LIT> ) ) continue ; if ( firstTime ) { dbgs ( ) << <STR_LIT> << PrintReg ( Reg , MRI . getTargetRegisterInfo ( ) ) << '\n' ; firstTime = false ; }


<s> return <ISA_LIT>ArchVersion == <ISA_LIT>r2 ;


<s> SDLoc DL ( N ) ; int Reg = getIntOperandFromRegisterString ( RegString -> getString ( ) ) ; if ( Reg != - <NUM_LIT> ) return CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> PMapper ; bool IsValidSpecialReg ; Reg = PMapper . fromString ( RegString -> getString ( ) , Subtarget -> getFeatureBits ( ) , IsValidSpecialReg ) ; if ( IsValidSpecialReg ) {

assert ( isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ) ;


<s> <ISA_LIT>elTargetMachine :: <ISA_LIT>elTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , JIT , false ) {


<s> V = peekThroughBitcasts ( V ) ; MVT NewVT = V . getSimpleValueType ( ) ; if ( ! NewVT . isVector ( ) || NewVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) return SDValue ( ) ;

if ( V . getOpcode ( ) == <STR_LIT> || ( Idx == <NUM_LIT> && V . getOpcode ( ) == <STR_LIT> ) ) {


<s> PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;


<s> MIB . addReg ( DstReg , RegState :: Define | RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } case <STR_LIT> : { if ( Domain != ExeNEON ) break ; DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLane = <NUM_LIT> , SrcLane = <NUM_LIT> , DDst , DSrc ; DDst = getCorrespondingDRegAndLane ( TRI , DstReg , DstLane ) ; DSrc = getCorrespondingDRegAndLane ( TRI , SrcReg , SrcLane ) ; unsigned ImplicitSReg ; if ( ! getImplicitSPRUseForDPRUse ( TRI , MI , DSrc , SrcLane , ImplicitSReg ) ) break ; for ( unsigned i = MI . getDesc ( ) . getNumOperands ( ) ; i ; -- i ) MI . RemoveOperand ( i - <NUM_LIT> ) ; if ( DSrc == DDst ) { MI . setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState :: Define ) . addReg ( DDst , getUndefRegState ( ! MI . readsRegister ( DDst , TRI ) ) ) . addImm ( SrcLane ) ; AddDefaultPred ( MIB ) ; MIB . addReg ( DstReg , RegState :: Implicit | RegState :: Define ) ; MIB . addReg ( SrcReg , RegState :: Implicit ) ; if ( ImplicitSReg != <NUM_LIT> ) MIB . addReg ( ImplicitSReg , RegState :: Implicit ) ; break ; } MachineInstrBuilder NewMIB ; NewMIB = BuildMI ( * MI . getParent ( ) , MI , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , DDst ) ; unsigned CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; bool CurUndef = ! MI . readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; CurUndef = ! MI . readsRegister ( CurReg , TRI ) ; NewMIB . addReg ( CurReg , getUndefRegState ( CurUndef ) ) ; NewMIB . addImm ( <NUM_LIT> ) ; AddDefaultPred ( NewMIB ) ; if ( SrcLane == DstLane ) NewMIB . addReg ( SrcReg , RegState :: Implicit ) ; MI . setDesc ( get ( <STR_LIT> ) ) ; MIB . addReg ( DDst , RegState :: Define ) ; CurReg = SrcLane == <NUM_LIT> && DstLane == <NUM_LIT> ? DSrc : DDst ; CurUndef = CurReg == DSrc && ! MI . readsRegister ( CurReg , TRI ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OS << <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OS << <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OS << <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OS << <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OS << <STR_LIT> ; break ;


<s> enum tls_model tls_kind = TLS_MODEL_NONE ; rtx sym , addend ; if ( GET_CODE ( addr ) == CONST ) { split_const ( addr , & sym , & addend ) ;

if ( GET_CODE ( sym ) == SYMBOL_REF ) tls_kind = SYMBOL_REF_TLS_MODEL ( sym ) ;


<s> return __builtin_ia32_rsqrtsh_mask ( __B , __A , _mm_setzero_ph ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> else { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; } xop [ <NUM_LIT> ] = xstring_e ; if ( ! AVR_HAVE_ELPMX ) return avr_out_lpm_no_lpmx ( insn , xop , plen ) ; } else if ( ! AVR_HAVE_LPMX ) { return avr_out_lpm_no_lpmx ( insn , xop , plen ) ; } switch ( GET_CODE ( addr ) ) { default : gcc_unreachable ( ) ; case REG : gcc_assert ( REG_Z == REGNO ( addr ) ) ; switch ( n_bytes ) { default : gcc_unreachable ( ) ; case <NUM_LIT> : return avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; case <NUM_LIT> : if ( REGNO ( dest ) == REG_Z ) return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; else { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( ! reg_unused_after ( insn , addr ) ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; } break ; case <NUM_LIT> : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( ! reg_unused_after ( insn , addr ) ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; break ; case <NUM_LIT> : avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( REGNO ( dest ) == REG_Z - <NUM_LIT> ) return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; else { avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( ! reg_unused_after ( insn , addr ) ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; } break ; } break ; case POST_INC : gcc_assert ( REG_Z == REGNO ( XEXP ( addr , <NUM_LIT> ) ) && n_bytes <= <NUM_LIT> ) ; avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( n_bytes >= <NUM_LIT> ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( n_bytes >= <NUM_LIT> ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( n_bytes >= <NUM_LIT> ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; break ;


<s> bool <ISA_LIT>AsmParser :: tryParseRegisterOperand ( OperandVector & Operands , StringRef Mnemonic ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; SMLoc E = Parser . getTok ( ) . getEndLoc ( ) ;

int RegNo = parseRegister ( Mnemonic ) ;


<s> Entry . isSExt = isSigned ; Entry . isZExt = ! isSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( TLI . getLibcallName ( LC ) , TLI . getPointerTy ( ) ) ; const Type * RetTy = Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . getTypeForMVT ( ) ; std :: pair < SDValue , SDValue > CallInfo = TLI . LowerCallTo ( InChain , RetTy , isSigned , ! isSigned , false , false , CallingConv :: C , false , Callee , Args , DAG , Op . getDebugLoc ( ) ) ;


<s> flag_data_sections = fdata ; flags = frodata -> common . flags ; } if ( frodata != readonly_data_section && flags & SECTION_NAMED ) { unsigned int i ; static const char * const prefix [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( i = <NUM_LIT> ; i < sizeof ( prefix ) / sizeof ( * prefix ) ; i += <NUM_LIT> ) { const char * old_prefix = prefix [ i ] ; const char * new_prefix = prefix [ i + <NUM_LIT> ] ; const char * name = frodata -> named . name ; if ( STR_PREFIX_P ( name , old_prefix ) ) { const char * rname = ACONCAT ( ( new_prefix , name + strlen ( old_prefix ) , NULL ) ) ; flags &= ~ SECTION_CODE ;


<s> __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: hasStoreToStackSlot ( const MachineInstr & MI , SmallVectorImpl < const MachineMemOperand * > & Accesses ) const { if ( MI . isBundle ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasStoreToStackSlot ( * MII , Accesses ) ) return true ;


<s> return ( V != nullptr ) ? isProgramMemoryAddress ( V ) : false ;


<s> for ( i = <NUM_LIT> ; i < n ; i ++ ) global_list . insert ( global_list . end ( ) , gv_array [ i ] ) ; clearAnnotationCache ( & M ) ; delete [ ] gv_array ; if ( HasDebugInfo ) OutStreamer -> EmitRawText ( <STR_LIT> ) ;

static_cast < <ISA_LIT>TargetStreamer * > ( OutStreamer -> getTargetStreamer ( ) ) -> outputDwarfFileDirectives ( ) ;


<s> unsigned Size = JT [ JTI ] . MBBs . size ( ) * sizeof ( uint32_t ) ; MachineBasicBlock * JumpTableBB = MF -> CreateMachineBasicBlock ( ) ; MF -> insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , JumpTableBB ) ; MachineInstr * CPEMI = BuildMI ( * JumpTableBB , JumpTableBB -> begin ( ) , DebugLoc ( ) , TII -> get ( JTOpcode ) ) . addImm ( i ++ ) . addJumpTableIndex ( JTI ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , JTI ) ) ; JumpTableEntryIndices . insert ( std :: make_pair ( JTI , CPEntries . size ( ) - <NUM_LIT> ) ) ; if ( ! LastCorrectlyNumberedBB ) LastCorrectlyNumberedBB = & MBB ; }

if ( LastCorrectlyNumberedBB ) MF -> RenumberBlocks ( LastCorrectlyNumberedBB ) ;


<s> const unsigned Opcode = getNewOpcode ( CI ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const TargetRegisterClass * SuperRC = getTargetRegisterClass ( CI ) ; Register SrcReg = MRI -> createVirtualRegister ( SuperRC ) ; const auto * Src0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Src1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , CI . Paired , DL , TII -> get ( <STR_LIT> ) , SrcReg ) . add ( * Src0 ) . addImm ( SubRegIdx0 ) . add ( * Src1 ) . addImm ( SubRegIdx1 ) ; auto MIB = BuildMI ( * MBB , CI . Paired , DL , TII -> get ( Opcode ) ) . addReg ( SrcReg , RegState :: Kill ) ; const unsigned Regs = getRegs ( Opcode , * TII ) ; if ( Regs & VADDR ) MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vaddr ) ) ;

assert ( CI . I -> hasOneMemOperand ( ) && CI . Paired -> hasOneMemOperand ( ) ) ;


<s> return new TargetLoweringObjectFileMachO ( ) ; case <ISA_LIT>Subtarget :: isELF : if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) return new <ISA_LIT>64_ELFTargetObjectFile ( TM ) ; return new <ISA_LIT>32_ELFTargetObjectFile ( TM ) ; case <ISA_LIT>Subtarget :: isMingw : case <ISA_LIT>Subtarget :: isCygwin :


<s> return checkType ( N -> getSrcValue ( ) , <STR_LIT> ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT == <STR_LIT> ) { if ( ! Op . hasOneUse ( ) ) return SDValue ( ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( ( User -> getOpcode ( ) != <STR_LIT> || ( isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) && cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> isNullValue ( ) ) ) && ( User -> getOpcode ( ) != <STR_LIT> || User -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) ) return SDValue ( ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Extract ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const {

JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T , const StringRef TT ) : MCAsmBackend ( ) {


<s> return llvm :: any_of ( N . getNode ( ) -> ops ( ) , [ ] ( const SDUse & U ) { return isAddressBase ( U . get ( ) ) ; } ) ; case <STR_LIT> :


<s> MIB . setMemRefs ( MMOs ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( i == <STR_LIT> ) MIB . addDisp ( MO , LabelOffset ) ; else if ( MO . isReg ( ) ) MIB . addReg ( MO . getReg ( ) ) ; else MIB . add ( MO ) ; } MIB . setMemRefs ( MMOs ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , SP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , SPOffset ) ; else MIB . add ( MI . getOperand ( i ) ) ; } MIB . setMemRefs ( MMOs ) ;

BuildMI ( * thisMBB , MI , DL , TII -> get ( IJmpOpc ) ) . addReg ( Tmp ) ;


<s> return new <ISA_LIT>LowerKernelCalls ( ) ;


<s> unsigned RegBits = getMachineOpValue ( MI , MI . getOperand ( OpNo + <NUM_LIT> ) , Fixups , STI ) << <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return ( ( getMachineOpValue ( MI , MO , Fixups , STI ) >> <NUM_LIT> ) & <NUM_LIT> ) | RegBits ;

Fixups . push_back ( MCFixup :: Create ( IsLittleEndian ? <NUM_LIT> : <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


return ( __m512i ) __builtin_ia32_pbroadcastw512_mask ( ( __v8hi ) __A , ( __v32hi ) _mm512_undefined_si512 ( ) , ( __mmask32 ) - <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RRC = Subtarget -> is64Bit ( ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> unsigned Imm = MI . getOperand ( ShiftAmtOperandIdx ) . getImm ( ) ; return Imm & ShiftCountMask ;


<s> Value * Args [ ] = { Cond , Broken } ; return CallInst :: Create ( IfBreak , Args , <STR_LIT> , Insert ) ; } if ( isa < Constant > ( Cond ) ) { Instruction * Insert = Cond == BoolTrue ? Term : L -> getHeader ( ) -> getTerminator ( ) ; Value * Args [ ] = { Cond , Broken } ; return CallInst :: Create ( IfBreak , Args , <STR_LIT> , Insert ) ; }


<s> else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg ) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; else if ( ( SrcReg == <STR_LIT> ) && ( <STR_LIT> . contains ( DestReg ) ) ) Opc = <STR_LIT> , SrcReg = <NUM_LIT> ; assert ( Opc && <STR_LIT> ) ;

MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( Opc ) ) ;


<s> auto Prepare = [ & ] ( ) { AllocaAddr = CreateAllocaInst ( Builder , Bitcast -> getParent ( ) ) ; I8Ptr = Builder . CreateBitCast ( AllocaAddr , Builder . getInt8PtrTy ( ) ) ; Stride = Builder . getInt64 ( <NUM_LIT> ) ; } ; if ( Bitcast -> getType ( ) -> is<ISA_LIT>_AMXTy ( ) ) { Use & U = * ( Bitcast -> use_begin ( ) ) ; unsigned OpNo = U . getOperandNo ( ) ; auto * II = dyn_cast < IntrinsicInst > ( U . getUser ( ) ) ; if ( ! II ) return false ; Prepare ( ) ; Builder . CreateStore ( Src , AllocaAddr ) ; Value * Row = nullptr , * Col = nullptr ; std :: tie ( Row , Col ) = getShape ( II , OpNo ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride } ; Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Bitcast -> replaceAllUsesWith ( NewInst ) ; } else { auto * II = dyn_cast < IntrinsicInst > ( Src ) ;


<s> poly16x8x2_t ret ; __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_ld2rv8hi ( ( const __builtin_aarch64_simd_hi * ) __a ) ; ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregoiv8hi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( poly16x8_t ) __builtin_aarch64_get_qregoiv8hi ( __o , <NUM_LIT> ) ;


<s> if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasXMM ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasXMMInt ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ;

if ( ! Subtarget -> hasXMMInt ( ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ;


<s> auto reqMinVer = getSymbolicOperandMinVersion ( Category , i ) ; auto reqMaxVer = getSymbolicOperandMaxVersion ( Category , i ) ; auto targetVer = ST . getTarget<ISA_LIT>Version ( ) ; bool minVerOK = ! reqMinVer || ! targetVer || targetVer >= reqMinVer ; bool maxVerOK = ! reqMaxVer || ! targetVer || targetVer <= reqMaxVer ; auto reqCaps = getSymbolicOperandCapabilities ( Category , i ) ; auto reqExts = getSymbolicOperandExtensions ( Category , i ) ; if ( reqCaps . empty ( ) ) { if ( reqExts . empty ( ) ) { if ( minVerOK && maxVerOK ) { return { true , { } , { } , reqMinVer , reqMaxVer } ;


<s> <ISA_LIT>Z80TargetMachine :: <ISA_LIT>Z80TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , DL ( <STR_LIT> ) , FrameLowering ( * this ) , InstrInfo ( * this ) , TSInfo ( * this ) , TLInfo ( * this ) {


<s> else { Binary |= ( ( RegD & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( RegD & <NUM_LIT> ) << <STR_LIT> ; } return Binary ;


<s> TBB = Branch . Target -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = Branch . Target -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( Branch . CCValid ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( Branch . CCMask ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> && TBB && <STR_LIT> ) ; if ( TBB != Branch . Target -> getMBB ( ) ) return true ; unsigned OldCCValid = Cond [ <NUM_LIT> ] . getImm ( ) ; unsigned OldCCMask = Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldCCValid == Branch . CCValid && OldCCMask == Branch . CCMask ) continue ; return false ; } return false ;


<s> const static unsigned NumOps = <NUM_LIT> ; const static bool S = true ; const static bool U = false ; const static unsigned Copy = TargetOpcode :: COPY ; const static struct DivRemEntry { const TargetRegisterClass * RC ; unsigned LowInReg ; unsigned HighInReg ; struct DivRemResult { unsigned OpDivRem ; unsigned OpSignExtend ; unsigned OpCopy ; unsigned DivRemResultReg ; bool IsOpSigned ; } ResultTable [ NumOps ] ; } OpTable [ NumTypes ] = { { & <STR_LIT> , <STR_LIT> , <NUM_LIT> , { { <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> , S } , { <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> , S } , { <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> , U } , { <STR_LIT> , <NUM_LIT> , <STR_LIT> , <STR_LIT> , U } , } } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> , { { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , } } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> , { { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , } } , { & <STR_LIT> , <STR_LIT> , <STR_LIT> , { { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , S } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , { <STR_LIT> , <STR_LIT> , Copy , <STR_LIT> , U } , } } , } ; MVT VT ; if ( ! isTypeLegal ( I -> getType ( ) , VT ) ) return false ; unsigned TypeIndex , OpIndex ; switch ( VT . SimpleTy ) { default : return false ; case <STR_LIT> : TypeIndex = <NUM_LIT> ; break ; case <STR_LIT> : TypeIndex = <NUM_LIT> ; break ; case <STR_LIT> : TypeIndex = <NUM_LIT> ; break ; case <STR_LIT> : TypeIndex = <NUM_LIT> ; if ( ! Subtarget -> is64Bit ( ) ) return false ; break ; } switch ( I -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: SDiv : OpIndex = <NUM_LIT> ; break ; case Instruction :: SRem : OpIndex = <NUM_LIT> ; break ; case Instruction :: UDiv : OpIndex = <NUM_LIT> ; break ;

case Instruction :: URem : OpIndex = <NUM_LIT> ; break ;


<s> gcc_assert ( subset == ADDR_SPACE_GENERIC || subset == ADDR_SPACE_EA ) ; gcc_assert ( superset == ADDR_SPACE_GENERIC || superset == ADDR_SPACE_EA ) ; if ( subset == superset ) return true ; else if ( ! TARGET_ADDRESS_SPACE_CONVERSION ) return false ; else return ( subset == ADDR_SPACE_GENERIC && superset == ADDR_SPACE_EA ) ;


<s> } } else { unsigned Cond = static_cast < <ISA_LIT>Operand & > ( * Operands [ CondOp ] ) . getCondCode ( ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( Cond == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . setOpcode ( Cond == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; break ; } } switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : { <ISA_LIT>Operand & op = static_cast < <ISA_LIT>Operand & > ( * Operands [ ImmOp ] ) ; if ( ! op . isSignedOffset < <NUM_LIT> , <NUM_LIT> > ( ) && isThumbTwo ( ) ) Inst . setOpcode ( <STR_LIT> ) ; break ;


<s> <STR_LIT> CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == <STR_LIT> || PredReg != <STR_LIT> ) return nullptr ; MI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! MI ) return nullptr ; MI -> getOperand ( MI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ; return MI ; } }

return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ;


<s> SDLoc dl ( Op ) ; if ( ( ! Subtarget -> isThumb ( ) && Subtarget -> hasV6Ops ( ) ) || Subtarget -> isThumb2 ( ) ) if ( SDValue SatValue = LowerSaturatingConditional ( Op , DAG ) ) return SatValue ; SDValue LowerSatConstant ; SDValue SatValue ; if ( VT == <STR_LIT> && isLowerSaturatingConditional ( Op , SatValue , LowerSatConstant ) ) { SDValue ShiftV = DAG . getNode ( <STR_LIT> , dl , VT , SatValue , DAG . getConstant ( <NUM_LIT> , dl , VT ) ) ; if ( isNullConstant ( LowerSatConstant ) ) { SDValue NotShiftV = DAG . getNode ( <STR_LIT> , dl , VT , ShiftV , DAG . getAllOnesConstant ( dl , VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , NotShiftV ) ; } else if ( isAllOnesConstant ( LowerSatConstant ) ) return DAG . getNode ( <STR_LIT> , dl , VT , SatValue , ShiftV ) ; } SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TrueVal = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseVal = Op . getOperand ( <NUM_LIT> ) ; ConstantSDNode * CFVal = dyn_cast < ConstantSDNode > ( FalseVal ) ; ConstantSDNode * CTVal = dyn_cast < ConstantSDNode > ( TrueVal ) ; if ( Subtarget -> hasV8_1MMainlineOps ( ) && CFVal && CTVal && LHS . getValueType ( ) == <STR_LIT> && RHS . getValueType ( ) == <STR_LIT> ) { unsigned TVal = CTVal -> getZExtValue ( ) ; unsigned FVal = CFVal -> getZExtValue ( ) ; unsigned Opcode = <NUM_LIT> ; if ( TVal == ~ FVal ) { Opcode = <STR_LIT> ; } else if ( TVal == ~ FVal + <NUM_LIT> ) { Opcode = <STR_LIT> ; } else if ( TVal + <NUM_LIT> == FVal ) { Opcode = <STR_LIT> ; } else if ( TVal == FVal + <NUM_LIT> ) { Opcode = <STR_LIT> ; std :: swap ( TrueVal , FalseVal ) ; std :: swap ( TVal , FVal ) ; CC = <STR_LIT> ( CC , LHS . getValueType ( ) ) ; }


<s> } else { TRI . buildVGPRSpillLoadStore ( * this , Index , Offset , IsLoad , false ) ;

BuildMI ( * MBB , MI , DL , TII . get ( NotOpc ) , ExecReg ) . addReg ( ExecReg ) ;


<s> rtx * labelp ; gcc_assert ( regno < LR_REGNUM ) ; if ( in_section == text_section ) { thumb_call_reg_needed = <NUM_LIT> ; if ( thumb_call_via_label [ regno ] == NULL ) thumb_call_via_label [ regno ] = gen_label_rtx ( ) ; labelp = thumb_call_via_label + regno ;


<s> else ValVT = VA . getValVT ( ) ; if ( Flags . isByVal ( ) ) { int FI = MFI -> CreateFixedObject ( Flags . getByValSize ( ) , VA . getLocMemOffset ( ) , isImmutable , false ) ; return DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; } else {

int FI = MFI -> CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , isImmutable , false ) ;


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>ElimComparePass ( get<ISA_LIT>TargetMachine ( ) ) ) ;

addPass ( create<ISA_LIT>LongBranchPass ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> __extension__ static __inline void vst2_u64 ( uint64_t * __a , uint64x1x2_t val ) { __builtin_aarch64_simd_oi __o ; uint64x2x2_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u64 ( val . val [ <NUM_LIT> ] , vcreate_u64 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregoiv2di ( __o , ( int64x2_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const { Streamer . visitUsedExpr ( * getSubExpr ( ) ) ;


<s> assert ( N == <NUM_LIT> && isBrList ( ) && <STR_LIT> ) ; for ( auto Br : BrL . List ) Inst . addOperand ( MCOperand :: createImm ( Br ) ) ;


<s> virtual const AMDGPURegisterInfo * getRegisterInfo ( ) const {

return & InstrInfo -> getRegisterInfo ( ) ;


<s> if ( OffsetReg != <NUM_LIT> ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; return Offset == <NUM_LIT> ; } MI . RemoveOperand ( FrameRegIdx + <NUM_LIT> ) ; MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; NewOpc = immediateOffsetOpcode ( Opcode ) ; AddrMode = <STR_LIT> ; } unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; if ( AddrMode == <STR_LIT> || AddrMode == <STR_LIT> ) { Offset += MI . getOperand ( FrameRegIdx + <NUM_LIT> ) . getImm ( ) ; if ( Offset < <NUM_LIT> ) { NewOpc = negativeOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; isSub = true ; Offset = - Offset ; } else { NewOpc = positiveOffsetOpcode ( Opcode ) ; NumBits = <NUM_LIT> ; } } else if ( AddrMode == <STR_LIT> ) { const MachineOperand & OffOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int InstrOffs = <STR_LIT> ( OffOp . getImm ( ) ) ; if ( <STR_LIT> ( OffOp . getImm ( ) ) == <STR_LIT> ) InstrOffs *= - <NUM_LIT> ; NumBits = <NUM_LIT> ; Scale = <NUM_LIT> ; Offset += InstrOffs * <NUM_LIT> ; assert ( ( Offset & ( Scale - <NUM_LIT> ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( Offset < <NUM_LIT> ) { Offset = - Offset ; isSub = true ; } } else { llvm_unreachable ( <STR_LIT> ) ; } if ( NewOpc != Opcode ) MI . setDesc ( TII . get ( NewOpc ) ) ; MachineOperand & ImmOp = MI . getOperand ( FrameRegIdx + <NUM_LIT> ) ; int ImmedOffset = Offset / Scale ; unsigned Mask = ( <NUM_LIT> << NumBits ) - <NUM_LIT> ; if ( ( unsigned ) Offset <= Mask * Scale ) { MI . getOperand ( FrameRegIdx ) . ChangeToRegister ( FrameReg , false ) ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset |= <NUM_LIT> << NumBits ; else ImmedOffset = - ImmedOffset ; } ImmOp . ChangeToImmediate ( ImmedOffset ) ; Offset = <NUM_LIT> ; return true ; } ImmedOffset = ImmedOffset & Mask ; if ( isSub ) { if ( AddrMode == <STR_LIT> ) ImmedOffset |= <NUM_LIT> << NumBits ; else { ImmedOffset = - ImmedOffset ; if ( ImmedOffset == <NUM_LIT> ) MI . setDesc ( TII . get ( positiveOffsetOpcode ( NewOpc ) ) ) ;


<s> if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; SDValue Offset = DAG . getConstant ( RegInfo -> getSlotSize ( ) , dl , PtrVT ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , PtrVT , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddressFrameIndex ( DAG ) ; return DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , RetAddrFI , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> bool <ISA_LIT>TTIImpl :: isLegalBroadcastLoad ( Type * ElementTy , unsigned NumElements ) const { return ST -> hasSSE3 ( ) && NumElements == <NUM_LIT> && ElementTy == Type :: getDoubleTy ( ElementTy -> getContext ( ) ) ;


<s> for ( MachineFunction :: iterator MBBI = MF -> begin ( ) , E = MF -> end ( ) ; MBBI != E ; ++ MBBI ) { MachineBasicBlock & MBB = * MBBI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) if ( I -> isBranch ( ) && I -> getOpcode ( ) == <STR_LIT> ) T2JumpTables . push_back ( I ) ;


<s> return true ; case InlineAsm :: Constraint_m : if ( ! selectAddrRr ( Op , Op0 , Op1 , AluOp ) && ! selectAddrRi ( Op , Op0 , Op1 , AluOp ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( AluOp ) ;


<s> const MachineOperand & Op = MI . getOperand ( I ) ; const MCOperandInfo & MCOI = MCID . OpInfo [ I ] ; if ( MCOI . OperandType == MCOI :: OPERAND_MEMORY && ( ( MCOI . RegClass != - <NUM_LIT> && ! Op . isReg ( ) && ! Op . isFI ( ) ) || ( MCOI . RegClass == - <NUM_LIT> && ! Op . isImm ( ) ) ) ) { ErrInfo = <STR_LIT> ;


<s> bool xtensa_const_ok_for_letter_p ( HOST_WIDE_INT v , int c ) { switch ( c ) { case 'I' : return xtensa_simm12b ( v ) ; case 'J' : return xtensa_simm8 ( v ) ; case 'K' : return ( v == <NUM_LIT> || xtensa_b4const ( v ) ) ; case 'L' : return xtensa_b4constu ( v ) ; case 'M' : return ( v >= - <NUM_LIT> && v <= <NUM_LIT> ) ; case 'N' : return xtensa_simm8x256 ( v ) ; case 'O' : return ( v == - <NUM_LIT> || ( v >= <NUM_LIT> && v <= <NUM_LIT> ) ) ;

case 'P' : return xtensa_mask_immediate ( v ) ;


<s> mask = ( d -> one_operand_p ? nelt - <NUM_LIT> : <NUM_LIT> * nelt - <NUM_LIT> ) ; shift = d -> perm [ <NUM_LIT> ] ; if ( BYTES_BIG_ENDIAN && shift > nelt ) return false ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) if ( d -> perm [ i ] != ( ( shift + i ) & mask ) ) return false ; if ( d -> testing_p ) return true ; hi = shift < nelt ? d -> op1 : d -> op0 ; lo = shift < nelt ? d -> op0 : d -> op1 ; shift %= nelt ; shift *= GET_MODE_UNIT_SIZE ( d -> vmode ) * BITS_PER_UNIT ; gcc_assert ( IN_RANGE ( shift , <NUM_LIT> , <NUM_LIT> ) ) ; if ( BYTES_BIG_ENDIAN ) shift = <NUM_LIT> - shift ;


<s> for ( const auto & F : Forwards ) { Register ForwardedReg = F . PReg ; if ( any_of ( MIB -> uses ( ) , [ & ForwardedReg , & TRI ] ( const MachineOperand & Use ) { if ( ! Use . isReg ( ) ) return false ; return TRI -> regsOverlap ( Use . getReg ( ) , ForwardedReg ) ; } ) ) continue ; MIRBuilder . buildCopy ( ForwardedReg , Register ( F . VReg ) ) ; MIB . addReg ( ForwardedReg , RegState :: Implicit ) ; } } if ( ! IsSibCall ) { MIB -> getOperand ( <NUM_LIT> ) . setImm ( FPDiff ) ; CallSeqStart . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( NumBytes ) . addImm ( <NUM_LIT> ) ; } MIRBuilder . insertInstr ( MIB ) ; if ( Info . Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ) ;

MF . getFrameInfo ( ) . setHasTailCall ( ) ;


<s> void function_expander :: prepare_prefetch_operands ( ) { unsigned int prfop = INTVAL ( args . last ( ) ) ; args . quick_push ( GEN_INT ( ( prfop & <NUM_LIT> ) != <NUM_LIT> ) ) ;

args . quick_push ( GEN_INT ( ( ( prfop >> <NUM_LIT> ) & <NUM_LIT> ) + <NUM_LIT> ) ) ;


<s> bool PolynomialMultiplyRecognize :: isPromotableTo ( Value * Val , IntegerType * DestTy ) { IntegerType * T = dyn_cast < IntegerType > ( Val -> getType ( ) ) ; if ( ! T || T -> getBitWidth ( ) > DestTy -> getBitWidth ( ) ) return false ; if ( T -> getBitWidth ( ) == DestTy -> getBitWidth ( ) ) return true ; Instruction * In = dyn_cast < Instruction > ( Val ) ; if ( ! In ) return true ; switch ( In -> getOpcode ( ) ) { case Instruction :: PHI : case Instruction :: ZExt : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: LShr :


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ;

O << format ( <STR_LIT> , Op . getImm ( ) ) ;


<s> virtual SUnit * pickNode ( bool & IsTopNode ) { return <NUM_LIT> ;


<s> return isImmediate < <NUM_LIT> , <NUM_LIT> > ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : FirstOp = <NUM_LIT> ; break ; } if ( ! isa < ConstantSDNode > ( N -> getOperand ( FirstOp ) ) || N -> getConstantOperandVal ( FirstOp ) != <NUM_LIT> ) continue ; SDValue Base = N -> getOperand ( FirstOp + <NUM_LIT> ) ; if ( ! Base . isMachineOpcode ( ) ) continue ; unsigned Flags = <NUM_LIT> ; bool ReplaceFlags = true ; switch ( Base . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ReplaceFlags = false ; if ( ( StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> || StorageOpcode == <STR_LIT> ) && ( ! isa < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) ) || Base . getConstantOperandVal ( <NUM_LIT> ) % <NUM_LIT> != <NUM_LIT> ) ) continue ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; case <STR_LIT> : Flags = <STR_LIT> ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( Base -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SDValue ImmOpnd = Base . getOperand ( <NUM_LIT> ) ; if ( ReplaceFlags ) { if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( ImmOpnd ) ) { DebugLoc dl = GA -> getDebugLoc ( ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; ImmOpnd = CurDAG -> getTargetGlobalAddress ( GV , dl , <STR_LIT> , <NUM_LIT> , Flags ) ; } else if ( ConstantPoolSDNode * CP = dyn_cast < ConstantPoolSDNode > ( ImmOpnd ) ) { const Constant * C = CP -> getConstVal ( ) ; ImmOpnd = CurDAG -> getTargetConstantPool ( C , <STR_LIT> , CP -> getAlignment ( ) , <NUM_LIT> , Flags ) ;