<s> for ( ref = DF_REG_DEF_CHAIN ( regno ) ; ref ; ref = DF_REF_NEXT_REG ( ref ) ) { rtx_insn * insn = DF_REF_INSN ( ref ) ; rtx def_set = single_set ( insn ) ; rtx src = SET_SRC ( def_set ) ; rtx reg = DF_REF_REG ( ref ) ; if ( ! MEM_P ( src ) ) { replace_with_subreg_in_insn ( insn , reg , reg ) ; bitmap_clear_bit ( conv , INSN_UID ( insn ) ) ; } if ( scalar_copy ) { start_sequence ( ) ; if ( TARGET_SSE4_1 ) { rtx tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const0_rtx ) ) ; emit_insn ( gen_rtx_SET ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_VEC_SELECT ( SImode , gen_rtx_SUBREG ( V4SImode , reg , <NUM_LIT> ) , tmp ) ) ) ; tmp = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) ) ; emit_insn ( gen_rtx_SET ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_VEC_SELECT ( SImode , gen_rtx_SUBREG ( V4SImode , reg , <NUM_LIT> ) , tmp ) ) ) ; } else if ( TARGET_INTER_UNIT_MOVES_FROM_VEC ) { rtx vcopy = gen_reg_rtx ( V2DImode ) ; emit_move_insn ( vcopy , gen_rtx_SUBREG ( V2DImode , reg , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , vcopy , <NUM_LIT> ) ) ; emit_move_insn ( vcopy , gen_rtx_LSHIFTRT ( V2DImode , vcopy , GEN_INT ( <NUM_LIT> ) ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , gen_rtx_SUBREG ( SImode , vcopy , <NUM_LIT> ) ) ; } else { rtx tmp = assign_386_stack_local ( DImode , SLOT_STV_TEMP ) ; emit_move_insn ( tmp , reg ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_SUBREG ( SImode , scopy , <NUM_LIT> ) , adjust_address ( tmp , SImode , <NUM_LIT> ) ) ; }


<s> unsigned <ISA_LIT>InstrInfo :: getInstBundleLength ( const MachineInstr & MI ) const { unsigned Size = <NUM_LIT> ; MachineBasicBlock :: const_instr_iterator I = MI . getIterator ( ) ;

MachineBasicBlock :: const_instr_iterator E = MI . getParent ( ) -> instr_end ( ) ;


<s> AMDGPUDAGToDAGISel :: AMDGPUDAGToDAGISel ( TargetMachine & TM ) : SelectionDAGISel ( TM ) , Subtarget ( TM . getSubtarget < AMDGPUSubtarget > ( ) ) {


<s> MIB . addRegMask ( TRI -> getCallPreservedMask ( MF , F . getCallingConv ( ) ) ) ; TargetLowering :: ArgListTy FuncOrigArgs ; FuncOrigArgs . reserve ( OrigArgs . size ( ) ) ; SmallVector < ArgInfo , <NUM_LIT> > ArgInfos ; SmallVector < unsigned , <NUM_LIT> > OrigArgIndices ; unsigned i = <NUM_LIT> ; for ( auto & Arg : OrigArgs ) { TargetLowering :: ArgListEntry Entry ; Entry . Ty = Arg . Ty ; FuncOrigArgs . push_back ( Entry ) ; splitToValueTypes ( Arg , i , ArgInfos , OrigArgIndices ) ; ++ i ; } SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; subTargetRegTypeForCallingConv ( MIRBuilder , ArgInfos , OrigArgIndices , [ & ] ( <STR_LIT> flags , EVT vt , EVT argvt , bool used , unsigned origIdx , unsigned partOffs ) { Outs . emplace_back ( flags , vt , argvt , used , origIdx , partOffs ) ; } ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; <ISA_LIT>CCState CCInfo ( F . getCallingConv ( ) , F . isVarArg ( ) , MF , ArgLocs , F . getContext ( ) ) ; CCInfo . AllocateStack ( ABI . GetCalleeAllocdArgSizeInBytes ( CallConv ) , <NUM_LIT> ) ; const char * Call = Callee . isSymbol ( ) ? Callee . getSymbolName ( ) : nullptr ; CCInfo . AnalyzeCallOperands ( Outs , TLI . CCAssignFnForCall ( ) , FuncOrigArgs , Call ) ; setLocInfo ( ArgLocs , Outs ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , MIB ) ; if ( ! RetHandler . handle ( ArgLocs , ArgInfos ) ) { return false ; } unsigned NextStackOffset = CCInfo . getNextStackOffset ( ) ; const TargetFrameLowering * TFL = MF . getSubtarget ( ) . getFrameLowering ( ) ; unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = alignTo ( NextStackOffset , StackAlignment ) ; CallSeqStart . addImm ( NextStackOffset ) . addImm ( <NUM_LIT> ) ; MIRBuilder . insertInstr ( MIB ) ; if ( OrigRet . Reg ) { ArgInfos . clear ( ) ;

SmallVector < unsigned , <NUM_LIT> > OrigRetIndices ;


<s> static struct machine_function * mt_init_machine_status ( void ) { struct machine_function * f ;

f = ggc_alloc_cleared ( sizeof ( struct machine_function ) ) ;


<s> case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG , * this ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; }


<s> assert ( BasePtrVreg != - <NUM_LIT> && <STR_LIT> ) ; return BasePtrVreg ;


<s> static bool finishStackBlock ( SmallVectorImpl < CCValAssign > & PendingMembers , MVT LocVT , <STR_LIT> & ArgFlags , CCState & State , Align SlotAlign ) { unsigned Size = LocVT . getSizeInBits ( ) / <NUM_LIT> ; const Align StackAlign = State . getMachineFunction ( ) . getDataLayout ( ) . getStackAlignment ( ) ; const Align OrigAlign = ArgFlags . getNonZeroOrigAlign ( ) ;

const Align Alignment = std :: min ( OrigAlign , StackAlign ) ;


<s> } } const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; for ( auto & Arg : F . args ( ) ) { unsigned I = Arg . getArgNo ( ) ; Type * T = Arg . getType ( ) ; auto TypeName = dyn_cast < MDString > ( F . getMetadata ( <STR_LIT> ) -> getOperand ( I ) ) -> getString ( ) ; auto BaseTypeName = cast < MDString > ( F . getMetadata ( <STR_LIT> ) -> getOperand ( I ) ) -> getString ( ) ; StringRef ArgName ; if ( auto ArgNameMD = F . getMetadata ( <STR_LIT> ) ) ArgName = cast < MDString > ( ArgNameMD -> getOperand ( I ) ) -> getString ( ) ; auto TypeQual = cast < MDString > ( F . getMetadata ( <STR_LIT> ) -> getOperand ( I ) ) -> getString ( ) ; auto AccQual = cast < MDString > ( F . getMetadata ( <STR_LIT> ) -> getOperand ( I ) ) -> getString ( ) ; KernelArg :: Kind Kind ; if ( TypeQual . find ( <STR_LIT> ) != StringRef :: npos ) Kind = KernelArg :: Pipe ; else Kind = StringSwitch < KernelArg :: Kind > ( BaseTypeName ) . Case ( <STR_LIT> , KernelArg :: Sampler ) . Case ( <STR_LIT> , KernelArg :: Queue ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , KernelArg :: Image ) . Cases ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , KernelArg :: Image ) . Cases ( <STR_LIT> , <STR_LIT> , KernelArg :: Image ) . Default ( isa < PointerType > ( T ) ? ( T -> getPointerAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS ? KernelArg :: DynamicSharedPointer : KernelArg :: GlobalBuffer ) : KernelArg :: ByValue ) ; Kernel . Args . emplace_back ( getRuntimeMDForKernelArg ( DL , T , Kind , BaseTypeName , TypeName , ArgName , TypeQual , AccQual ) ) ; } if ( F . getParent ( ) -> getNamedMetadata ( <STR_LIT> ) ) { auto Int64T = Type :: getInt64Ty ( F . getContext ( ) ) ; Kernel . Args . emplace_back ( getRuntimeMDForKernelArg ( DL , Int64T , KernelArg :: HiddenGlobalOffsetX ) ) ; Kernel . Args . emplace_back ( getRuntimeMDForKernelArg ( DL , Int64T , KernelArg :: HiddenGlobalOffsetY ) ) ; Kernel . Args . emplace_back ( getRuntimeMDForKernelArg ( DL , Int64T , KernelArg :: HiddenGlobalOffsetZ ) ) ;


<s> <ISA_LIT>TargetObjectFile ( ) : TargetLoweringObjectFile ( ) {


<s> void FPS :: handleOneArgFP ( MachineBasicBlock :: iterator & I ) { MachineInstr * MI = I ; unsigned NumOps = MI -> getDesc ( ) . getNumOperands ( ) ; assert ( ( NumOps == <STR_LIT> + <NUM_LIT> || NumOps == <NUM_LIT> ) && <STR_LIT> ) ; unsigned Reg = getFPReg ( MI -> getOperand ( NumOps - <NUM_LIT> ) ) ; bool KillsSrc = MI -> killsRegister ( <STR_LIT> + Reg ) ; if ( KillsSrc ) duplicatePendingSTBeforeKill ( Reg , I ) ; if ( ! KillsSrc && ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) ) { duplicateToTop ( Reg , getScratchReg ( ) , I ) ; } else { moveToTop ( Reg , I ) ; } MI -> RemoveOperand ( NumOps - <NUM_LIT> ) ; MI -> setDesc ( TII -> get ( getConcreteOpcode ( MI -> getOpcode ( ) ) ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) {

if ( StackTop == <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ;


<s> for ( const MachineOperand & Use : MRI . use_operands ( Reg ) ) { if ( & Use == & OneUse ) continue ; const MachineInstr * UseInst = Use . getParent ( ) ; const MachineInstr * OneUseInst = OneUse . getParent ( ) ; if ( UseInst -> getOpcode ( ) == TargetOpcode :: PHI ) { const MachineBasicBlock * Pred = UseInst -> getOperand ( & Use - & UseInst -> getOperand ( <NUM_LIT> ) + <NUM_LIT> ) . getMBB ( ) ; if ( ! MDT . dominates ( & MBB , Pred ) ) return false ; } else if ( UseInst == OneUseInst ) { if ( & OneUse > & Use ) return false ; } else { if ( ! MDT . dominates ( OneUseInst , UseInst ) ) return false ; }


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> || RHS . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue True = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue False = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue LSEL = DAG . getNode ( <STR_LIT> , dl , True . getValueType ( ) , LHS , True , False , LHS . getOperand ( <NUM_LIT> ) ) ; SDValue RSEL = DAG . getNode ( <STR_LIT> , dl , True . getValueType ( ) , RHS , True , False , RHS . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , LSEL , RSEL ) ;


<s> rtx src = operands [ <NUM_LIT> ] ; rtx dst_addr , src_addr ; HOST_WIDE_INT size ; int align = INTVAL ( operands [ <NUM_LIT> ] ) ; unsigned n_pieces ; int piece = align ; rtx store [ <NUM_LIT> ] ; rtx tmpx [ <NUM_LIT> ] ; int i ; if ( ! CONST_INT_P ( operands [ <NUM_LIT> ] ) ) return false ; size = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( align >= <NUM_LIT> ) { if ( TARGET_LL64 ) n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> + ( ( size >> <NUM_LIT> ) & <NUM_LIT> ) + ( size & <NUM_LIT> ) ; else n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> + ( size & <NUM_LIT> ) ; } else if ( align == <NUM_LIT> ) n_pieces = ( size + <NUM_LIT> ) / <NUM_LIT> ; else n_pieces = size ; if ( n_pieces >= ( unsigned int ) ( optimize_size ? <NUM_LIT> : <NUM_LIT> ) ) return false ; if ( TARGET_LL64 && ( piece >= <NUM_LIT> ) && ( size >= <NUM_LIT> ) ) piece = <NUM_LIT> ; else if ( piece > <NUM_LIT> ) piece = <NUM_LIT> ; dst_addr = force_offsettable ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , size , <NUM_LIT> ) ;

src_addr = force_offsettable ( XEXP ( operands [ <NUM_LIT> ] , <NUM_LIT> ) , size , <NUM_LIT> ) ;


<s> void <ISA_LIT>FunctionInfo :: anchor ( ) {


<s> tree attrs = aarch64_get_attributes ( FLAG_NONE , d -> mode ) ; tree fndecl = aarch64_general_add_builtin ( d -> name , ftype , d -> fcode , attrs ) ; aarch64_builtin_decls [ d -> fcode ] = fndecl ;


<s> return llvm :: any_of ( MBB . liveins ( ) , [ Reg ] ( MachineBasicBlock :: RegisterMaskPair RegMask ) { return RegMask . PhysReg == Reg ;


<s> real_ldexp ( & m , & r , point_pos - exponent ) ; wide_int w = real_to_integer ( & m , & fail , HOST_BITS_PER_WIDE_INT * <NUM_LIT> ) ; mantissa = w . elt ( <NUM_LIT> ) ; mant_hi = w . elt ( <NUM_LIT> ) ; exponent -= <NUM_LIT> ; if ( ! IN_RANGE ( exponent , - <NUM_LIT> , <NUM_LIT> ) ) return <NUM_LIT> ; if ( mantissa != <NUM_LIT> ) return <NUM_LIT> ; point_pos -= HOST_BITS_PER_WIDE_INT ; mantissa = mant_hi ;

mask = ( ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( point_pos - <NUM_LIT> ) ) - <NUM_LIT> ;


<s> IsCap = false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; IsCap = false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; IsCap = false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; IsCap = false ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; IsCap = true ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; IsCap = true ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = <STR_LIT> ; IsCap = true ; } else if ( MI . getOpcode ( ) == <STR_LIT> ) { Func = MI . getOperand ( <NUM_LIT> ) ; Ra = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; IsCap = true ; } uint32_t Binary ; assert ( Func . isExpr ( ) && <STR_LIT> ) ;

const MCExpr * CallExpr = Func . getExpr ( ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result ;


<s> break ; case <STR_LIT> : Cmp = Comparison :: LEs ; break ; case <STR_LIT> : Cmp = Comparison :: LEu ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Cmp = Comparison :: GTu ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Cmp = Comparison :: GTs ; break ; default : return ( Comparison :: Kind ) <NUM_LIT> ; }


<s> O << <STR_LIT> ; printU4ImmOperand ( MI , OpNo , O ) ;


<s> bool andCC = false ; if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) { if ( RHSC -> isNullValue ( ) && LHS . hasOneUse ( ) && ( LHS . getOpcode ( ) == <STR_LIT> || ( LHS . getOpcode ( ) == <STR_LIT> && LHS . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) ) { andCC = true ; } } <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ; bool Invert = false ; bool Shift = false ; bool Convert = true ; switch ( cast < ConstantSDNode > ( TargetCC ) -> getZExtValue ( ) ) { default : Convert = false ; break ; case <STR_LIT> : break ; case <STR_LIT> : Invert = true ; break ; case <STR_LIT> : if ( andCC ) { } else { Shift = true ; Invert = true ; } break ; case <STR_LIT> : Shift = true ; break ; } EVT VT = Op . getValueType ( ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , VT ) ; if ( Convert ) { SDValue SR = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , <STR_LIT> , Flag ) ; if ( Shift ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; if ( Invert ) SR = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SR , One ) ; return SR ; } else { SDValue Zero = DAG . getConstant ( <NUM_LIT> , VT ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( One ) ; Ops . push_back ( Zero ) ;


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const {

TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;


<s> if ( TARGET_VIS ) sparc_vis_init_builtins ( ) ;


<s> SDLoc dl ( N ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( isa < ConstantFPSDNode > ( Src ) && N -> getSimpleValueType ( <NUM_LIT> ) == <STR_LIT> && Src . getSimpleValueType ( ) == <STR_LIT> ) return bitcastConstantFPToInt ( cast < ConstantFPSDNode > ( Src ) , dl , DCI . DAG ) ; return SDValue ( ) ;


<s> return ( int32x2_t ) __builtin_neon_vmvnv2si ( __a ) ;


<s> OutRetAddr = getReturnAddressFrameIndex ( DAG ) ; OutRetAddr = DAG . getLoad ( VT , dl , Chain , OutRetAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return SDValue ( OutRetAddr . getNode ( ) , <NUM_LIT> ) ;


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> unsigned RegSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; unsigned Alignment = std :: min ( Flags . getByValAlign ( ) , RegSizeInBytes ) ; EVT PtrTy = getPointerTy ( ) , RegTy = <STR_LIT> ( RegSizeInBytes * <NUM_LIT> ) ; unsigned NumRegs = LastReg - FirstReg ; if ( NumRegs ) { const ArrayRef < MCPhysReg > ArgRegs = Subtarget . getABI ( ) . GetByValArgRegs ( ) ; bool LeftoverBytes = ( NumRegs * RegSizeInBytes > ByValSizeInBytes ) ; unsigned I = <NUM_LIT> ; for ( ; I < NumRegs - LeftoverBytes ; ++ I , OffsetInBytes += RegSizeInBytes ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( RegTy , DL , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned ArgReg = ArgRegs [ FirstReg + I ] ; RegsToPass . push_back ( std :: make_pair ( ArgReg , LoadVal ) ) ; } if ( ByValSizeInBytes == OffsetInBytes ) return ; if ( LeftoverBytes ) { SDValue Val ; for ( unsigned LoadSizeInBytes = RegSizeInBytes / <NUM_LIT> , TotalBytesLoaded = <NUM_LIT> ; OffsetInBytes < ByValSizeInBytes ; LoadSizeInBytes /= <NUM_LIT> ) { unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes ; if ( RemainingSizeInBytes < LoadSizeInBytes ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , DL , PtrTy , Arg , DAG . getConstant ( OffsetInBytes , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , DL , RegTy , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSizeInBytes * <NUM_LIT> ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned Shamt ; if ( isLittle ) Shamt = TotalBytesLoaded * <NUM_LIT> ; else Shamt = ( RegSizeInBytes - ( TotalBytesLoaded + LoadSizeInBytes ) ) * <NUM_LIT> ;

SDValue Shift = DAG . getNode ( <STR_LIT> , DL , RegTy , LoadVal , DAG . getConstant ( Shamt , <STR_LIT> ) ) ;


<s> if ( REG_P ( op ) ) return REGNO ( op ) ; else if ( SUBREG_P ( op ) ) return subreg_regno ( op ) ;


<s> setArgFlags ( OrigArg , Idx + <NUM_LIT> , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs , ArrayRef < uint64_t > Offsets ) { MIRBuilder . buildSequence ( VRegs [ Idx ] , Regs , Offsets ) ; } ) ; Idx ++ ; } MachineBasicBlock & MBB = MIRBuilder . getMBB ( ) ; if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; FormalArgHandler Handler ( MIRBuilder , MRI , CC_<ISA_LIT> , DL ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ;


<s> MCAsmParser & Parser = getParser ( ) ; if ( Parser . parseEOL ( <STR_LIT> ) ) return addErrorSuffix ( <STR_LIT> ) ; return getTargetStreamer ( ) . emitFPOEndPrologue ( L ) ;


<s> instr_iterator CmpIt = CmpI , NextIt = std :: next ( CmpIt ) ; for ( instr_iterator I = NextIt , E = BB -> instr_end ( ) ; I != E ; ++ I ) { MachineInstr * In = & * I ; for ( unsigned i = <NUM_LIT> , n = In -> getNumOperands ( ) ; i < n ; ++ i ) { MachineOperand & MO = In -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isUse ( ) ) { if ( MO . getReg ( ) == PredR ) return false ; } } if ( In == BumpI ) {


<s> const DebugLoc & DbgLoc = I . getDebugLoc ( ) ; unsigned Opc = getLoadStoreOp ( DstTy , RegBank , TargetOpcode :: G_LOAD , Alignment ) ; const ConstantFP * CFP = I . getOperand ( <NUM_LIT> ) . getFPImm ( ) ; unsigned CPI = MF . getConstantPool ( ) -> getConstantPoolIndex ( CFP , Alignment . value ( ) ) ; MachineInstr * LoadInst = nullptr ; unsigned char OpFlag = STI . classifyLocalReference ( nullptr ) ; if ( CM == CodeModel :: Large && STI . is64Bit ( ) ) { Register AddrReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , MF . getDataLayout ( ) . getPointerSize ( ) , Alignment ) ; LoadInst = addDirectMem ( BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( Opc ) , DstReg ) , AddrReg ) . addMemOperand ( MMO ) ; } else if ( CM == CodeModel :: Small || ! STI . is64Bit ( ) ) { unsigned PICBase = <NUM_LIT> ; if ( OpFlag == <STR_LIT> || OpFlag == <STR_LIT> ) { return false ; } else if ( STI . is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; LoadInst = addConstantPoolReference ( BuildMI ( * I . getParent ( ) , I , DbgLoc , TII . get ( Opc ) , DstReg ) , CPI , PICBase , OpFlag ) ; } else return false ;

constrainSelectedInstRegOperands ( * LoadInst , TII , TRI , RBI ) ;


<s> unsigned postOffset ( unsigned LogAlign = <NUM_LIT> ) const { unsigned PO = Offset + Size ;


<s> if ( I -> getOpcode ( ) != Instruction :: FMul ) return true ; if ( ! I -> hasOneUse ( ) ) return true ; Instruction * User = I -> user_back ( ) ; assert ( User && <STR_LIT> ) ; if ( User -> getOpcode ( ) != Instruction :: FSub && User -> getOpcode ( ) != Instruction :: FAdd ) return true ; const TargetOptions & Options = getTargetMachine ( ) . Options ; const Function * F = I -> getFunction ( ) ;

const DataLayout & DL = F -> getParent ( ) -> getDataLayout ( ) ;


<s> } else if ( <STR_LIT> -> contains ( Reg ) || <STR_LIT> -> contains ( Reg ) ) { } else if ( <STR_LIT> -> contains ( Reg ) ) { HasVRSAVESaveArea = true ; } else if ( <STR_LIT> -> contains ( Reg ) ) { HasVRSaveArea = true ; VRegs . push_back ( CSI [ i ] ) ; if ( Reg < MinVR ) { MinVR = Reg ; } } else { llvm_unreachable ( <STR_LIT> ) ; } } <ISA_LIT>FunctionInfo * PFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t LowerBound = <NUM_LIT> ; int TCSPDelta = <NUM_LIT> ; if ( GuaranteedTailCallOpt && ( TCSPDelta = PFI -> getTailCallSPDelta ( ) ) < <NUM_LIT> ) { LowerBound = TCSPDelta ; } if ( HasFPSaveArea ) { for ( unsigned i = <NUM_LIT> , e = FPRegs . size ( ) ; i != e ; ++ i ) { int FI = FPRegs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } LowerBound -= ( <NUM_LIT> - <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MinFPR ) + <NUM_LIT> ) * <NUM_LIT> ; } if ( hasFP ( MF ) ) { HasGPSaveArea = true ; int FI = PFI -> getFramePointerSaveIndex ( ) ; assert ( FI && <STR_LIT> ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } if ( HasGPSaveArea || HasG8SaveArea ) { for ( unsigned i = <NUM_LIT> , e = GPRegs . size ( ) ; i != e ; ++ i ) { int FI = GPRegs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } for ( unsigned i = <NUM_LIT> , e = G8Regs . size ( ) ; i != e ; ++ i ) { int FI = G8Regs [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ; } unsigned MinReg = std :: min < unsigned > ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MinGPR ) , <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MinG8R ) ) ; if ( Subtarget . is<ISA_LIT>64 ( ) ) { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } else { LowerBound -= ( <NUM_LIT> - MinReg + <NUM_LIT> ) * <NUM_LIT> ; } } if ( HasCRSaveArea ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( <STR_LIT> -> contains ( Reg ) || <STR_LIT> -> contains ( Reg ) ) { int FI = CSI [ i ] . getFrameIdx ( ) ; FFI -> setObjectOffset ( FI , LowerBound + FFI -> getObjectOffset ( FI ) ) ;


<s> Opcode = MCBinaryExpr :: Add ; Parser . Lex ( ) ; break ; case AsmToken :: Minus : Opcode = MCBinaryExpr :: Sub ; Parser . Lex ( ) ; break ; case AsmToken :: Star : Opcode = MCBinaryExpr :: Mul ; Parser . Lex ( ) ; break ; case AsmToken :: Pipe : Opcode = MCBinaryExpr :: Or ; Parser . Lex ( ) ; break ; case AsmToken :: Amp : Opcode = MCBinaryExpr :: And ; Parser . Lex ( ) ; break ; case AsmToken :: LessLess : Opcode = MCBinaryExpr :: Shl ; Parser . Lex ( ) ; break ; case AsmToken :: GreaterGreater : Opcode = MCBinaryExpr :: LShr ; Parser . Lex ( ) ; break ; case AsmToken :: Caret : Opcode = MCBinaryExpr :: Xor ; Parser . Lex ( ) ; break ; case AsmToken :: Slash : Opcode = MCBinaryExpr :: Div ; Parser . Lex ( ) ; break ; case AsmToken :: Percent : Opcode = MCBinaryExpr :: Mod ; Parser . Lex ( ) ; break ; default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const MCExpr * NextExpr ; if ( getParser ( ) . parseExpression ( NextExpr ) ) return MatchOperand_ParseFail ; IdVal = MCBinaryExpr :: create ( Opcode , IdVal , NextExpr , getContext ( ) ) ; } assert ( Parser . getTok ( ) . is ( AsmToken :: LParen ) ) ; Parser . Lex ( ) ; HadLParen = true ;


<s> if ( getOptLevel ( ) != CodeGenOpt :: None ) if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>HardwareLoops ( ) ) ; return false ;


do { \ char buf [ <NUM_LIT> ] ; \ fputs ( integer_asm_op ( UNITS_PER_LONG , TRUE ) , ( FILE ) ) ; \ ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , ( VALUE ) ) ; \ assemble_name ( ( FILE ) , buf ) ; \ fputc ( '\n' , ( FILE ) ) ; \ }


<s> static void record_cc_ref ( rtx insn ) { last_insn_set_cc_p = current_insn_set_cc_p ; switch ( get_attr_cond ( insn ) ) { case COND_SET : case COND_SET_ZN :


<s> return llvm :: cast < llvm :: FixedVectorType > ( Ty ) -> getElementType ( ) ;


return CCIdx >= <NUM_LIT> ? static_cast < <STR_LIT> > ( Instr . getOperand ( CCIdx ) . getImm ( ) ) : <STR_LIT> ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } if ( ! Subtarget . is64Bit ( ) ) Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Subtarget . isV9 ( ) ) { for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; }


<s> void emit_pic_move ( rtx * operands , enum machine_mode mode ATTRIBUTE_UNUSED ) { rtx temp = reload_in_progress ? operands [ <NUM_LIT> ] : gen_reg_rtx ( Pmode ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == MEM && SYMBOLIC_CONST ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = force_reg ( SImode , operands [ <NUM_LIT> ] ) ; else operands [ <NUM_LIT> ] = legitimize_pic_address ( operands [ <NUM_LIT> ] , temp , pic_offset_table_rtx ) ;


<s> bool <ISA_LIT>TargetMachine :: addCodeEmitter ( PassManagerBase & PM , JITCodeEmitter & JCE ) { PM . add ( create<ISA_LIT>JITCodeEmitterPass ( * this , JCE ) ) ;


<s> } assert ( VecVT . is128BitVector ( ) && <STR_LIT> ) ; if ( Subtarget -> hasSSE41 ( ) ) if ( SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ) return Res ; MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; MVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( Idx ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; MVT VVT = Op . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( VVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> int HalfSize = VT . getVectorNumElements ( ) / <NUM_LIT> ; int FstHalf = <NUM_LIT> , SndHalf = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < HalfSize ; ++ i ) { if ( SVOp -> getMaskElt ( i ) > <NUM_LIT> ) { FstHalf = SVOp -> getMaskElt ( i ) / HalfSize ;


<s> void <ISA_LIT>TargetMachine64 :: anchor ( ) {


<s> virtual const <ISA_LIT>Subtarget * getSubtarget ( ) {


<s> short <ISA_LIT>InstrInfo :: changeAddrMode_io_abs ( short Opc ) const {

return Opc >= <NUM_LIT> ? <STR_LIT> ( Opc ) : Opc ;


<s> else if ( GET_CODE ( addr1 ) == PLUS && REG_P ( XEXP ( addr1 , <NUM_LIT> ) ) && GET_CODE ( XEXP ( addr1 , <NUM_LIT> ) ) == CONST_INT ) { reg1 = XEXP ( addr1 , <NUM_LIT> ) ; offset1 = INTVAL ( XEXP ( addr1 , <NUM_LIT> ) ) ; } else return <NUM_LIT> ; if ( REG_P ( addr2 ) ) { reg2 = addr2 ; offset2 = <NUM_LIT> ; } else if ( GET_CODE ( addr2 ) == PLUS && REG_P ( XEXP ( addr2 , <NUM_LIT> ) ) && GET_CODE ( XEXP ( addr2 , <NUM_LIT> ) ) == CONST_INT ) { reg2 = XEXP ( addr2 , <NUM_LIT> ) ;

offset2 = INTVAL ( XEXP ( addr2 , <NUM_LIT> ) ) ;


<s> case <NUM_LIT> : NumVecs = <NUM_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( IsLoad ) { switch ( NumVecs ) { case <NUM_LIT> : Is128BitVec ? DecodeFPR128RegisterClass ( Inst , Rt , Address , Decoder ) : DecodeFPR64RegisterClass ( Inst , Rt , Address , Decoder ) ; break ; case <NUM_LIT> : Is128BitVec ? DecodeQPairRegisterClass ( Inst , Rt , Address , Decoder ) : DecodeDPairRegisterClass ( Inst , Rt , Address , Decoder ) ; break ; case <NUM_LIT> : Is128BitVec ? DecodeQTripleRegisterClass ( Inst , Rt , Address , Decoder ) : DecodeDTripleRegisterClass ( Inst , Rt , Address , Decoder ) ; break ; case <NUM_LIT> : Is128BitVec ? DecodeQQuadRegisterClass ( Inst , Rt , Address , Decoder ) : DecodeDQuadRegisterClass ( Inst , Rt , Address , Decoder ) ; break ; } } DecodeGPR64xspRegisterClass ( Inst , Rn , Address , Decoder ) ; DecodeGPR64xspRegisterClass ( Inst , Rn , Address , Decoder ) ; if ( Rm == <NUM_LIT> ) Inst . addOperand ( MCOperand :: CreateImm ( NumVecs * ( Is128BitVec ? <NUM_LIT> : <NUM_LIT> ) ) ) ; else DecodeGPR64noxzrRegisterClass ( Inst , Rm , Address , Decoder ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isStoreToStackSlot ( const MachineInstr & MI , int & FrameIndex , unsigned & MemBytes ) const {

if ( isFrameStoreOpcode ( MI . getOpcode ( ) , MemBytes ) ) if ( MI . getOperand ( <STR_LIT> ) . getSubReg ( ) == <NUM_LIT> && isFrameOperand ( MI , <NUM_LIT> , FrameIndex ) ) return MI . getOperand ( <STR_LIT> ) . getReg ( ) ;


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; return ( <STR_LIT> ( MF -> getFunction ( ) -> getCallingConv ( ) ) && usesVertexCache ( MI . getOpcode ( ) ) ) || usesTextureCache ( MI . getOpcode ( ) ) ;


<s> else { SDValue Chain = getFLUSHW ( Op , DAG ) ; FrameAddr = DAG . getCopyFromReg ( Chain , dl , FrameReg , VT ) ; for ( uint64_t i = <NUM_LIT> ; i != depth ; ++ i ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FrameAddr , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; FrameAddr = DAG . getLoad ( <STR_LIT> , dl , Chain , Ptr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } }


<s> static void DecodeUNPCKHPMask ( unsigned NElts , SmallVectorImpl < unsigned > & ShuffleMask ) {

for ( unsigned i = <NUM_LIT> ; i != NElts / <NUM_LIT> ; ++ i ) {


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( unsigned RegNo , SMLoc S , SMLoc E ) { auto Op = make_unique < <ISA_LIT>Operand > ( k_Register ) ; Op -> Reg . Num = RegNo ; Op -> StartLoc = S ;


<s> bool isToken ( ) const override { return is ( k_Token ) ;


<s> <ISA_LIT>TTIImpl ( <ISA_LIT>TTIImpl && Arg ) : BaseT ( std :: move ( static_cast < BaseT & > ( Arg ) ) ) , ST ( std :: move ( Arg . ST ) ) , TLI ( std :: move ( Arg . TLI ) ) {


<s> SDValue Result ; if ( OpFlags == <STR_LIT> && <STR_LIT> ( Offset , M ) ) { Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , Offset ) ; Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) , <NUM_LIT> , OpFlags ) ; }

if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> SDLoc SL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; const SDValue K = DAG . getConstantFP ( numbers :: log2e , SL , VT ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , SL , VT , Src , K , Op -> getFlags ( ) ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Mul , Op -> getFlags ( ) ) ;


<s> static DecodeStatus decodePC32DBLOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler * Decoder ) {

return decodePCDBLOperand < <NUM_LIT> > ( Inst , Imm , Address , false , Decoder ) ;


<s> addImplySP ( Inst , Address , Decoder ) ;

Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;


<s> if ( a < b ) return <NUM_LIT> ; else return a - b ;


<s> if ( IntrinsicWithPred ) { SmallVector < SDValue , <NUM_LIT> > Ops ; const MCInstrDesc & MCID = TII -> get ( IntrinsicWithPred ) ; const TargetRegisterInfo * TRI = TM . getRegisterInfo ( ) ; for ( unsigned i = <NUM_LIT> ; i < N -> getNumOperands ( ) ; ++ i ) { SDNode * Arg = N -> getOperand ( i ) . getNode ( ) ; const TargetRegisterClass * RC = TII -> getRegClass ( MCID , i , TRI ) ; if ( RC == <STR_LIT> || RC == <STR_LIT> ) { Ops . push_back ( SDValue ( Arg , <NUM_LIT> ) ) ; } else if ( RC == <STR_LIT> ) { SDNode * PdRs = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Arg , <NUM_LIT> ) ) ; Ops . push_back ( SDValue ( PdRs , <NUM_LIT> ) ) ;

} else if ( RC == NULL && ( dyn_cast < ConstantSDNode > ( Arg ) != NULL ) ) {


<s> } if ( ! Done && MatchAddress ( Addr , AM12 , true ) ) return false ; if ( ! Done && ! is12BitOnly && ! MatchAddress ( Addr , AM20 , false ) ) if ( AM12 . Disp == <NUM_LIT> && AM20 . Disp != <NUM_LIT> ) return false ; DEBUG ( errs ( ) << <STR_LIT> ; AM12 . dump ( ) ) ; EVT VT = Addr . getValueType ( ) ; if ( AM12 . BaseType == <STR_LIT> ) { if ( ! AM12 . Base . Reg . getNode ( ) ) AM12 . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } assert ( AM12 . IndexReg . getNode ( ) == <NUM_LIT> && <STR_LIT> ) ;

getAddressOperandsRI ( AM12 , Base , Disp ) ;


<s> bool isTargetMachO ( const MCSubtargetInfo & STI ) const {

const Triple & TT = STI . getTargetTriple ( ) ;


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << Value ;

} else printOperand ( MI , OpNum , O ) ;


<s> void emitSymbolDesc ( MCSymbol * Symbol , unsigned DescValue ) override {


<s> Liveness ( MachineRegisterInfo & mri , const DataFlowGraph & g ) : DFG ( g ) , TRI ( g . getTRI ( ) ) , MDT ( g . getDT ( ) ) , MDF ( g . getDF ( ) ) , RAI ( g . getRAI ( ) ) , MRI ( mri ) , Empty ( ) , Trace ( false ) {


<s> void VisitGlobalVariableForEmission ( const GlobalVariable * GV , SmallVectorImpl < const GlobalVariable * > & Order , DenseSet < const GlobalVariable * > & Visited , DenseSet < const GlobalVariable * > & Visiting ) { if ( Visited . count ( GV ) ) return ; if ( Visiting . count ( GV ) ) report_fatal_error ( <STR_LIT> ) ; Visiting . insert ( GV ) ;

DenseSet < const GlobalVariable * > Others ;


<s> uint16_t first ( ) const { return B ;


<s> void setCalleeSavedFrameSize ( unsigned bytes ) { CalleeSavedFrameSize = bytes ;


<s> return new <ISA_LIT>ShrinkInstructions ( ) ;


requiresVirtualBaseRegisters ( const MachineFunction & MF ) const {


<s> return __builtin_aarch64_bfcvtbf ( __a ) ;


<s> if ( RC == & <STR_LIT> ) return & <STR_LIT> ;


<s> SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Frame , DAG . getIntPtrConstant ( - TD -> getPointerSize ( ) ) ) ; StoreAddr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StoreAddr , Offset ) ; Chain = DAG . getStore ( Chain , dl , Handler , StoreAddr , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;

Chain = DAG . getCopyToReg ( Chain , dl , StoreAddrReg , StoreAddr ) ;


<s> tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , DImode , & regset ) ; if ( tmp != NULL_RTX ) { operands [ <NUM_LIT> ] = simplify_gen_subreg ( SImode , tmp , DImode , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = simplify_gen_subreg ( SImode , tmp , DImode , <NUM_LIT> ) ; } else { SET_HARD_REG_SET ( regset ) ; CLEAR_HARD_REG_BIT ( regset , regno % <NUM_LIT> == <NUM_LIT> ? regno + <NUM_LIT> : regno - <NUM_LIT> ) ; tmp = peep2_find_free_register ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> , SImode , & regset ) ; if ( tmp == NULL_RTX ) return false ; operands [ regno % <NUM_LIT> == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ] = tmp ; } } gcc_assert ( operands [ <NUM_LIT> ] != NULL_RTX ) ; gcc_assert ( operands [ <NUM_LIT> ] != NULL_RTX ) ; gcc_assert ( REGNO ( operands [ <NUM_LIT> ] ) % <NUM_LIT> == <NUM_LIT> ) ; gcc_assert ( REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) ; } } if ( offsets [ <NUM_LIT> ] > offsets [ <NUM_LIT> ] ) { gap = offsets [ <NUM_LIT> ] - offsets [ <NUM_LIT> ] ; offset = offsets [ <NUM_LIT> ] ; std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; std :: swap ( align [ <NUM_LIT> ] , align [ <NUM_LIT> ] ) ; if ( const_store ) std :: swap ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; } else { gap = offsets [ <NUM_LIT> ] - offsets [ <NUM_LIT> ] ; offset = offsets [ <NUM_LIT> ] ; } if ( gap != <NUM_LIT> ) return false ; if ( ! align_ok_ldrd_strd ( align [ <NUM_LIT> ] , offset ) ) return false ;

if ( operands_ok_ldrd_strd ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , base , offset , false , load ) ) return true ;


<s> } parse_res = aarch64_parse_extension ( str , & isa_flags ) ; if ( parse_res == AARCH64_PARSE_OK ) { aarch64_isa_flags = isa_flags ; return true ; } switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> , pragma_or_attr , str ) ; break ; case AARCH64_PARSE_INVALID_FEATURE : error ( <STR_LIT> , pragma_or_attr , str ) ; break ;


<s> bool SelectAddrImmShift ( SDValue Op , SDValue N , SDValue & Disp , SDValue & Base ) {

return <ISA_LIT>Lowering . SelectAddressRegImmShift ( N , Disp , Base , * CurDAG ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerSELECT_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue True = Op . getOperand ( <NUM_LIT> ) ; SDValue False = Op . getOperand ( <NUM_LIT> ) ; SDValue CC = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue Cond = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , RHS , CC ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Cond , True , False ) ;


<s> size_t <ISA_LIT>PrintfInfo :: getNumOperands ( ) {


<s> if ( c < <NUM_LIT> ) c += <NUM_LIT> ; fprintf ( file , <STR_LIT> , c ) ;

if ( i < size - <NUM_LIT> ) putc ( ',' , file ) ;


<s> SDValue Ops [ ] = { Chain , TGA , DAG . getRegister ( <STR_LIT> , PtrVT ) , * InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops ) ; } else { SDValue Ops [ ] = { Chain , TGA , DAG . getRegister ( <STR_LIT> , PtrVT ) } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops ) ;


<s> FreqMap :: iterator it = BlockFrequencies . find ( MBB ) ; if ( it != BlockFrequencies . end ( ) ) {


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override { return & FrameLowering ;


<s> DOTGraphTraits ( bool isSimple = false ) : DefaultDOTGraphTraits ( isSimple ) {


<s> Changed |= addRangeMetadata ( <NUM_LIT> , MaxBlockSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . x + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . y + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , MaxGridSize . z + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> + <NUM_LIT> , Call ) ; break ; case <STR_LIT> : Changed |= addRangeMetadata ( <NUM_LIT> , <NUM_LIT> , Call ) ;


<s> if ( TREE_CODE ( type ) != RECORD_TYPE ) return false ; const_tree last_field = NULL_TREE ; for ( const_tree f = TYPE_FIELDS ( type ) ; f ; f = TREE_CHAIN ( f ) ) last_field = f ; if ( ! last_field ) return false ; const_tree last_field_type = TREE_TYPE ( last_field ) ; if ( TREE_CODE ( last_field_type ) != ARRAY_TYPE ) return false ;

return ( ! TYPE_DOMAIN ( last_field_type ) || ! TYPE_MAX_VALUE ( TYPE_DOMAIN ( last_field_type ) ) ) ;


<s> } else if ( bytes >= <NUM_LIT> && TARGET_POWERPC64 && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = DImode ; gen_func . mov = gen_movdi ; if ( offset == <NUM_LIT> && align < <NUM_LIT> ) { rtx addr ; addr = XEXP ( orig_dest , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_dest = replace_equiv_address ( orig_dest , addr ) ; } addr = XEXP ( orig_src , <NUM_LIT> ) ; if ( ( GET_CODE ( addr ) == PLUS || GET_CODE ( addr ) == LO_SUM ) && CONST_INT_P ( XEXP ( addr , <NUM_LIT> ) ) && ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) & <NUM_LIT> ) != <NUM_LIT> ) { addr = copy_addr_to_reg ( addr ) ; orig_src = replace_equiv_address ( orig_src , addr ) ; } } } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = SImode ; gen_func . mov = gen_movsi ; } else if ( bytes >= <NUM_LIT> && ( align >= <NUM_LIT> || ! STRICT_ALIGNMENT ) ) { move_bytes = <NUM_LIT> ; mode = HImode ; gen_func . mov = gen_movhi ; } else { move_bytes = <NUM_LIT> ; mode = QImode ; gen_func . mov = gen_movqi ; } src = adjust_address ( orig_src , mode , offset ) ; dest = adjust_address ( orig_dest , mode , offset ) ; if ( mode != BLKmode ) { rtx tmp_reg = gen_reg_rtx ( mode ) ; emit_insn ( ( * gen_func . mov ) ( tmp_reg , src ) ) ; stores [ num_reg ++ ] = ( * gen_func . mov ) ( dest , tmp_reg ) ; } if ( mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes ) { int i ; for ( i = <NUM_LIT> ; i < num_reg ; i ++ ) emit_insn ( stores [ i ] ) ; num_reg = <NUM_LIT> ; } if ( mode == BLKmode ) { if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) ) { rtx src_reg = copy_addr_to_reg ( XEXP ( src , <NUM_LIT> ) ) ; src = replace_equiv_address ( src , src_reg ) ; } set_mem_size ( src , move_bytes ) ; if ( ! REG_P ( XEXP ( dest , <NUM_LIT> ) ) ) { rtx dest_reg = copy_addr_to_reg ( XEXP ( dest , <NUM_LIT> ) ) ;

dest = replace_equiv_address ( dest , dest_reg ) ;


<s> Darwin<ISA_LIT>AsmBackend ( const Target & T , const StringRef TT , object :: mach :: CPUSubtype<ISA_LIT> st ) : <ISA_LIT>AsmBackend ( T , TT ) , Subtype ( st ) {


<s> switch ( reg ) { default : break ; case AMDGPU :: SCC : case AMDGPU :: EXEC : case AMDGPU :: M0 : continue ; } if ( AMDGPU :: SReg_32RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_32RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: SReg_64RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_64RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_96RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: SReg_128RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_128RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: SReg_256RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_256RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: SReg_512RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_512RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned hwReg = RI -> getEncodingValue ( reg ) & <NUM_LIT> ; unsigned maxUsed = hwReg + width - <NUM_LIT> ; if ( isSGPR ) { MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR ; } else { MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR ; } } } } if ( VCCUsed ) MaxSGPR += <NUM_LIT> ; ProgInfo . NumVGPR = MaxVGPR ; ProgInfo . NumSGPR = MaxSGPR ; ProgInfo . FloatMode = getFPMode ( MF ) ; ProgInfo . IEEEMode = <NUM_LIT> ; ProgInfo . DX10Clamp = <NUM_LIT> ;

const MachineFrameInfo * FrameInfo = MF . getFrameInfo ( ) ;


<s> unsigned Num ; if ( F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , Num ) ) return ; emit<ISA_LIT>Nops ( * OutStreamer , Num , Subtarget ) ; return ; } auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> , & getSubtargetInfo ( ) ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) {


<s> MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset += PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) {

Offset -= PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> bool <ISA_LIT>InstrInfo :: isLateInstrFeedsEarlyInstr ( const MachineInstr & LRMI , const MachineInstr & ESMI ) const { bool isLate = isLateResultInstr ( LRMI ) ; bool isEarly = isEarlySourceInstr ( ESMI ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( isLate ? <STR_LIT> : <STR_LIT> ) ) ; LLVM_DEBUG ( LRMI . dump ( ) ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( isEarly ? <STR_LIT> : <STR_LIT> ) ) ;


<s> ExpandREAD_REGISTER ( N , Results , DAG ) ; break ; case <STR_LIT> : Res = ExpandBITCAST ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = Expand64BitShift ( N , DAG , Subtarget ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerREM ( N , DAG ) ; break ; case <STR_LIT> : case <STR_LIT> : Res = LowerDivRem ( SDValue ( N , <NUM_LIT> ) , DAG ) ; assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : Res = LowerSADDSUBSAT ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ;


<s> case <STR_LIT> : Streamer . EmitRawText ( StringRef ( <STR_LIT> ) + String . lower ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> :


<s> if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ; return false ;


<s> bool UseStack = false ; for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ) { MVT VT = Args [ i ] . VT ; unsigned ArgIndex = Args [ i ] . OrigArgIndex ; unsigned TotalBytes = VT . getStoreSize ( ) ; unsigned j = i + <NUM_LIT> ; for ( ; j != NumArgs ; ++ j ) { if ( Args [ j ] . OrigArgIndex != ArgIndex ) break ; TotalBytes += Args [ j ] . VT . getStoreSize ( ) ; } TotalBytes = alignTo ( TotalBytes , <NUM_LIT> ) ; if ( TotalBytes == <NUM_LIT> ) continue ; unsigned RegIdx = RegLastIdx + TotalBytes ; RegLastIdx = RegIdx ; if ( RegIdx >= RegList8 . size ( ) ) { UseStack = true ; } for ( ; i != j ; ++ i ) {


<s> } else { if ( mergeOps ( MBB , ++ Loc , SOffset , Base , false , Opcode , Pred , PredReg , Scratch , Regs , TII ) ) { Merges . push_back ( prior ( Loc ) ) ; for ( unsigned j = SIndex ; j < i ; ++ j ) { MBB . erase ( MemOps [ j ] . MBBI ) ; MemOps [ j ] . Merged = true ; } } SmallVector < MachineBasicBlock :: iterator , <NUM_LIT> > Merges2 = MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch , MemOps ) ; Merges . append ( Merges2 . begin ( ) , Merges2 . end ( ) ) ; return Merges ; } if ( MemOps [ i ] . Position > Pos ) { Pos = MemOps [ i ] . Position ; Loc = MemOps [ i ] . MBBI ; } } bool BaseKill = Loc -> findRegisterUseOperandIdx ( Base , true ) != - <NUM_LIT> ; if ( mergeOps ( MBB , ++ Loc , SOffset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , Regs , TII ) ) { Merges . push_back ( prior ( Loc ) ) ; for ( unsigned i = SIndex , e = MemOps . size ( ) ; i != e ; ++ i ) { MBB . erase ( MemOps [ i ] . MBBI ) ; MemOps [ i ] . Merged = true ;


<s> CopyGeneration ( BitTracker & bt , const <ISA_LIT>InstrInfo & hii , MachineRegisterInfo & mri ) : Transformation ( true ) , HII ( hii ) , MRI ( mri ) , BT ( bt ) {


<s> void setCalleeSavedStackSize ( unsigned Size ) { CalleeSavedStackSize = Size ;


<s> void riscv_d_register_target_info ( void ) {

const struct d_target_info_spec handlers [ ] = {


<s> std :: string ArchFS = Parse<ISA_LIT>Triple ( TT , CPU ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ; else ArchFS = FS ; }

return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , ArchFS ) ;


<s> NumDataVectors = <NUM_LIT> ; NumPredicateVectors = Offset . getScalable ( ) / <NUM_LIT> ; if ( NumPredicateVectors % <NUM_LIT> == <NUM_LIT> || NumPredicateVectors < - <NUM_LIT> || NumPredicateVectors > <NUM_LIT> ) { NumDataVectors = NumPredicateVectors / <NUM_LIT> ;

NumPredicateVectors -= NumDataVectors * <NUM_LIT> ;


<s> off_name = <STR_LIT> ; reg_name = <STR_LIT> ; } else if ( SYMBOL_REF_SDA_P ( addr ) ) { off_name = <STR_LIT> ; reg_name = <STR_LIT> ; } else if ( SYMBOL_REF_TDA_P ( addr ) ) { off_name = <STR_LIT> ; reg_name = <STR_LIT> ; } if ( off_name ) fprintf ( file , <STR_LIT> , off_name ) ; output_addr_const ( file , addr ) ; if ( reg_name ) fprintf ( file , <STR_LIT> , reg_name ) ; } break ; case CONST : if ( special_symbolref_operand ( addr , VOIDmode ) ) { rtx x = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; const char * off_name ; const char * reg_name ; if ( SYMBOL_REF_ZDA_P ( x ) ) { off_name = <STR_LIT> ; reg_name = <STR_LIT> ; } else if ( SYMBOL_REF_SDA_P ( x ) ) { off_name = <STR_LIT> ; reg_name = <STR_LIT> ; } else if ( SYMBOL_REF_TDA_P ( x ) ) { off_name = <STR_LIT> ; reg_name = <STR_LIT> ; } else gcc_unreachable ( ) ; fprintf ( file , <STR_LIT> , off_name ) ; output_addr_const ( file , addr ) ;


<s> int RHSC = ( int ) RHS -> getSExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( RHSC >= - <NUM_LIT> ) && ( RHSC < <NUM_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , TLI . getPointerTy ( ) ) ; }

OffImm = CurDAG -> getTargetConstant ( RHSC , <STR_LIT> ) ;


<s> unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; std :: vector < CPEntry > & CPEs = CPEntries [ CPI ] ; for ( CPEntry & CPE : CPEs ) { if ( CPE . CPEMI == CPEMI ) continue ; if ( CPE . CPEMI == nullptr ) continue ; if ( isCPEntryInRange ( UserMI , UserOffset , CPE . CPEMI , U . getLongFormMaxDisp ( ) , U . NegOk ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPE . CPI << <STR_LIT> ) ; U . CPEMI = CPE . CPEMI ; for ( MachineOperand & MO : UserMI -> operands ( ) ) if ( MO . isCPI ( ) ) { MO . setIndex ( CPE . CPI ) ; break ; } CPE . RefCount ++ ; return decrementCPEReferenceCount ( CPI , CPEMI ) ? <NUM_LIT> : <NUM_LIT> ; }


<s> std :: string Name = Mang -> getValueName ( GV ) ; bool isExt = ( GV -> isDeclaration ( ) || GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) ) ; if ( isExt && isCallOp && Subtarget -> isTargetDarwin ( ) && TM . getRelocationModel ( ) != Reloc :: Static ) { printSuffixedName ( Name , <STR_LIT> ) ; FnStubs . insert ( Name ) ; } else O << Name ; printOffset ( MO . getOffset ( ) ) ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; if ( GV -> hasExternalWeakLinkage ( ) ) ExtWeakSymbols . insert ( GV ) ; break ; } case MachineOperand :: MO_ExternalSymbol : { bool isCallOp = Modifier && ! strcmp ( Modifier , <STR_LIT> ) ; std :: string Name ( TAI -> getGlobalPrefix ( ) ) ; Name += MO . getSymbolName ( ) ; if ( isCallOp && Subtarget -> isTargetDarwin ( ) && TM . getRelocationModel ( ) != Reloc :: Static ) { printSuffixedName ( Name , <STR_LIT> ) ; FnStubs . insert ( Name ) ; } else O << Name ; if ( isCallOp && Subtarget -> isTargetELF ( ) && TM . getRelocationModel ( ) == Reloc :: PIC_ ) O << <STR_LIT> ; break ; } case MachineOperand :: MO_ConstantPoolIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ! ( MI . getOperand ( <NUM_LIT> ) . getTargetFlags ( ) & <STR_LIT> ) ;


<s> assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; unsigned Immediate = <NUM_LIT> ;

if ( ! matchVectorShuffleWithSHUFPD ( VT , V1 , V2 , Immediate , Mask ) ) return SDValue ( ) ;


<s> EmitEndOfAsmFile ( M ) ; return false ;


<s> static void lowerMUL_LOHI32 ( SelectionDAG & DAG , const SDLoc & DL , unsigned Extend , SDValue Op0 , SDValue Op1 , SDValue & Hi , SDValue & Lo ) { Op0 = DAG . getNode ( Extend , DL , <STR_LIT> , Op0 ) ; Op1 = DAG . getNode ( Extend , DL , <STR_LIT> , Op1 ) ; SDValue Mul = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Mul , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;

Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ;


<s> SyncScope :: ID getAgentS<ISA_LIT>D ( ) const {


<s> MachineSDNode * Node = DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , ResTy , ZReg , SubReg ) ;


<s> } if ( isZeroOrAllOnes ( N2 , AllOnes ) ) { Invert = true ; OtherOp = N1 ; return true ; } return false ; } case <STR_LIT> : if ( AllOnes ) return false ; LLVM_FALLTHROUGH ; case <STR_LIT> : { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; CC = N -> getOperand ( <NUM_LIT> ) ; if ( CC . getValueType ( ) != <STR_LIT> ) return false ; Invert = ! AllOnes ; if ( AllOnes ) OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; else if ( N -> getOpcode ( ) == <STR_LIT> ) OtherOp = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; else OtherOp = DAG . getConstant ( APInt :: getAllOnesValue ( VT . getSizeInBits ( ) ) , dl , VT ) ; return true ; }


<s> return Desc . getSize ( ) ; } case TargetOpcode :: EH_LABEL : case TargetOpcode :: IMPLICIT_DEF : case TargetOpcode :: KILL : case TargetOpcode :: DBG_VALUE : return <NUM_LIT> ; case TargetOpcode :: INLINEASM : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ; }


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & ST ) {


<s> KnownBits Known2 ; DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known , Depth + <NUM_LIT> ) ;

DAG . computeKnownBits ( Op -> getOperand ( <NUM_LIT> ) , Known2 , Depth + <NUM_LIT> ) ;


<s> return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : assert ( HasAVX && <STR_LIT> ) ; return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( HasAVX ? <STR_LIT> : <STR_LIT> ) ) ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : MI -> setDesc ( get ( <STR_LIT> ) ) ; return true ; case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : return Expand2AddrUndef ( MIB , get ( <STR_LIT> ) ) ; } return false ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( STI . isTargetIOS ( ) || STI . isTargetWatchOS ( ) ) return true ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

return ( ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) && MFI -> hasCalls ( ) ) || RegInfo -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ;


<s> if ( MI . getParent ( ) -> succ_empty ( ) ) return MachineOutlinerInstrType :: Legal ; return MachineOutlinerInstrType :: Illegal ; } if ( MI . getOpcode ( ) == <STR_LIT> ) return MachineOutlinerInstrType :: Legal ; if ( MI . isCall ( ) ) { const Module * M = MF -> getFunction ( ) . getParent ( ) ; assert ( M && <STR_LIT> ) ; Function * Callee = nullptr ; for ( const MachineOperand & MOP : MI . operands ( ) ) { if ( MOP . isSymbol ( ) ) { Callee = M -> getFunction ( MOP . getSymbolName ( ) ) ; break ; } else if ( MOP . isGlobal ( ) ) { Callee = M -> getFunction ( MOP . getGlobal ( ) -> getGlobalIdentifier ( ) ) ; break ; } } if ( ! Callee ) return MachineOutlinerInstrType :: Illegal ; if ( Callee -> isVarArg ( ) ) return MachineOutlinerInstrType :: Illegal ; for ( Argument & Arg : Callee -> args ( ) ) { if ( Arg . getType ( ) -> isPointerTy ( ) && Arg . getType ( ) -> getPointerElementType ( ) -> isAggregateType ( ) ) return MachineOutlinerInstrType :: Illegal ; } if ( Callee -> doesNotAccessMemory ( ) ) return MachineOutlinerInstrType :: Legal ; MachineFunction * CalleeMF = MF -> getMMI ( ) . getMachineFunction ( * Callee ) ; if ( ! CalleeMF ) return MachineOutlinerInstrType :: Illegal ; if ( CalleeMF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getBytesInStackArgArea ( ) != <NUM_LIT> ) return MachineOutlinerInstrType :: Illegal ; return MachineOutlinerInstrType :: Legal ; }

if ( MI . isPosition ( ) ) return MachineOutlinerInstrType :: Illegal ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , bool IsBigEndian ) : MCDisassembler ( STI , Ctx ) , IsMicro<ISA_LIT> ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) , IsBigEndian ( IsBigEndian ) {


<s> explicit <ISA_LIT>FloatMCExpr ( VariantKind _Kind , APFloat _Flt ) : Kind ( _Kind ) , Flt ( _Flt ) {


<s> unsigned DstReg = MRI . createVirtualRegister ( RI . getBoolRC ( ) ) ; MachineInstr * <ISA_LIT>IF = BuildMI ( * MF , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) . add ( Branch -> getOperand ( <NUM_LIT> ) ) ; MachineInstr * <ISA_LIT>END = BuildMI ( * MF , Branch -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( DstReg ) ; IfEntry -> erase ( TI ) ; IfEntry -> insert ( IfEntry -> end ( ) , <ISA_LIT>IF ) ;

IfEnd -> insert ( IfEnd -> getFirstNonPHI ( ) , <ISA_LIT>END ) ;


<s> static void arm_init_acle_builtins ( void ) { unsigned int i , fcode = ARM_BUILTIN_ACLE_PATTERN_START ;

for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( acle_builtin_data ) ; i ++ , fcode ++ ) {


<s> cumulative_args_t dummy = pack_cumulative_args ( NULL ) ;

return m32r_pass_by_reference ( dummy , TYPE_MODE ( type ) , type , false ) ;


<s> PM . add ( create<ISA_LIT>DelaySlotFillerPass ( * this ) ) ; return true ;


<s> if ( MO . isExpr ( ) ) { if ( HasConditionalBranch ( MI ) ) return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; } return MO . getImm ( ) >> <NUM_LIT> ;


<s> return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> Offset = CurDAG -> getTargetConstant ( IMMOffset -> getZExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } else if ( ( IMMOffset = dyn_cast < ConstantSDNode > ( Addr ) ) && isInt < <NUM_LIT> > ( IMMOffset -> getZExtValue ( ) ) ) { Base = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , SDLoc ( CurDAG -> getEntryNode ( ) ) , AMDGPU :: ZERO , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( IMMOffset -> getZExtValue ( ) , SDLoc ( Addr ) , <STR_LIT> ) ; return true ; } Base = Addr ;

Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , SDLoc ( Addr ) , <STR_LIT> ) ;


<s> Hi = DAG . getBitcast ( ByteVT , Hi ) ; if ( Subtarget . hasSSSE3 ( ) ) { assert ( ( ! VT . is512BitVector ( ) || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , ByteVT , Lo , Hi , DAG . getTargetConstant ( ByteRotation , DL , <STR_LIT> ) ) ) ; } assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; assert ( ByteVT == <STR_LIT> && <STR_LIT> ) ; int LoByteShift = <NUM_LIT> - ByteRotation ; int HiByteShift = ByteRotation ; SDValue LoShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , DAG . getTargetConstant ( LoByteShift , DL , <STR_LIT> ) ) ; SDValue HiShift = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , DAG . getTargetConstant ( HiByteShift , DL , <STR_LIT> ) ) ;

return DAG . getBitcast ( VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LoShift , HiShift ) ) ;


<s> static inline void vec_st ( vec_float4 a , int b , vec_float4 * c ) {

* ( ( vec_float4 * ) ( ( unsigned char * ) ( c ) + b ) ) = a ;


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) {

<ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , TAB , OS , Emitter ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStack ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI , int64_t Offset ) const { DebugLoc DL ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ; unsigned Opc = <NUM_LIT> ; Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ;

BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ;


<s> auto InsertPos = MBB -> begin ( ) ; while ( InsertPos != MBB -> end ( ) ) { if ( AfterSet . count ( & * InsertPos ) ) { for ( auto Pos = InsertPos , E = MBB -> end ( ) ; Pos != E ; ++ Pos ) assert ( ! BeforeSet . count ( & * Pos ) ) ; break ; }


<s> emit_insn ( GEN_FCN ( icode ) ( ops [ <NUM_LIT> ] , from ) ) ; } else emit_insn ( gen_extend_insn ( ops [ <NUM_LIT> ] , from , mode , imode , <NUM_LIT> ) ) ; return <NUM_LIT> ; } if ( ( reload_in_progress | reload_completed ) == <NUM_LIT> && ! register_operand ( ops [ <NUM_LIT> ] , mode ) && ! register_operand ( ops [ <NUM_LIT> ] , mode ) ) { rtx temp = force_reg ( mode , ops [ <NUM_LIT> ] ) ; emit_move_insn ( ops [ <NUM_LIT> ] , temp ) ; return <NUM_LIT> ; } if ( reload_in_progress || reload_completed ) { if ( CONSTANT_P ( ops [ <NUM_LIT> ] ) ) return spu_split_immediate ( ops ) ; return <NUM_LIT> ; } if ( GET_CODE ( ops [ <NUM_LIT> ] ) == CONST_INT ) { HOST_WIDE_INT val = trunc_int_for_mode ( INTVAL ( ops [ <NUM_LIT> ] ) , mode ) ; if ( val != INTVAL ( ops [ <NUM_LIT> ] ) ) { emit_move_insn ( ops [ <NUM_LIT> ] , GEN_INT ( val ) ) ; return <NUM_LIT> ; } } if ( MEM_P ( ops [ <NUM_LIT> ] ) ) { if ( MEM_ADDR_SPACE ( ops [ <NUM_LIT> ] ) ) ops [ <NUM_LIT> ] = expand_ea_mem ( ops [ <NUM_LIT> ] , true ) ; return spu_split_store ( ops ) ;


<s> if ( ExplicitlyBranchesTo ( Pred , & MBB ) ) IsBranchedTo = true ; } if ( ! Header ) return ; if ( ! IsBranchedTo ) return ; assert ( & MBB != & MF . front ( ) && <STR_LIT> ) ; MachineBasicBlock * LayoutPred = & * prev ( MachineFunction :: iterator ( & MBB ) ) ; for ( MachineFunction :: iterator I ( LayoutPred ) , E ( Header ) ; I != E ; -- I ) { if ( MachineBasicBlock * ScopeTop = ScopeTops [ I -> getNumber ( ) ] ) { if ( ScopeTop -> getNumber ( ) > Header -> getNumber ( ) ) { I = next ( MachineFunction :: iterator ( ScopeTop ) ) ; } else { Header = ScopeTop ; break ; } } } for ( MachineLoop * Loop = MLI . getLoopFor ( LayoutPred ) ;

Loop && Loop -> contains ( LayoutPred ) ; Loop = Loop -> getParentLoop ( ) ) if ( Loop && LoopBottom ( Loop ) == LayoutPred && Loop -> contains ( Header ) ) return ;


<s> if ( original_class == limiting_class ) return original_class ; cc = reg_class_contents [ original_class ] ; AND_HARD_REG_SET ( cc , reg_class_contents [ limiting_class ] ) ;

for ( i = <NUM_LIT> ; i < LIM_REG_CLASSES ; i ++ ) {


<s> rtx_insn * insns ; rtx dest ; start_sequence ( ) ; m68k_libcall_value_in_a0_p = true ; a0 = emit_library_call_value ( m68k_get_m68k_read_tp ( ) , NULL_RTX , LCT_PURE , Pmode , <NUM_LIT> ) ; m68k_libcall_value_in_a0_p = false ; insns = get_insns ( ) ; end_sequence ( ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_RELOC32 ) ; gcc_assert ( can_create_pseudo_p ( ) ) ; dest = gen_reg_rtx ( Pmode ) ;

emit_libcall_block ( insns , dest , a0 , eqv ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerLOADi1 ( SDValue Op , SelectionDAG & DAG ) const { SDNode * Node = Op . getNode ( ) ; LoadSDNode * LD = cast < LoadSDNode > ( Node ) ; SDLoc dl ( Node ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> ) ; assert ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && <STR_LIT> ) ; SDValue newLD = DAG . getLoad ( <STR_LIT> , dl , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getPointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue result = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , newLD ) ;

SDValue Ops [ ] = { result , LD -> getChain ( ) } ;


<s> SmallSetVector < MachineLoop * , <NUM_LIT> > OnStack ; OnStack . insert ( nullptr ) ; for ( auto & MBB : MF ) { assert ( MBB . getNumber ( ) >= <NUM_LIT> && <STR_LIT> ) ; MachineLoop * Loop = MLI . getLoopFor ( & MBB ) ; if ( Loop && & MBB == Loop -> getHeader ( ) ) { for ( auto Pred : MBB . predecessors ( ) ) assert ( ( Pred -> getNumber ( ) < MBB . getNumber ( ) || Loop -> contains ( Pred ) ) && <STR_LIT> ) ; assert ( OnStack . insert ( Loop ) && <STR_LIT> ) ; } else { for ( auto Pred : MBB . predecessors ( ) ) assert ( Pred -> getNumber ( ) < MBB . getNumber ( ) && <STR_LIT> ) ; assert ( OnStack . count ( MLI . getLoopFor ( & MBB ) ) && <STR_LIT> ) ; } while ( OnStack . size ( ) > <NUM_LIT> && & MBB == LoopBottom ( OnStack . back ( ) ) ) OnStack . pop_back ( ) ;


<s> unsigned Mods = <NUM_LIT> ; MachineInstr * MI = getDefIgnoringCopies ( Src , * MRI ) ; if ( MI && MI -> getOpcode ( ) == <STR_LIT> ) {

Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> unsigned Lo = Imm & <NUM_LIT> ; unsigned Hi = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; auto getI32Imm = [ CurDAG , dl ] ( unsigned Imm ) { return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ; } ; if ( isInt < <NUM_LIT> > ( Imm ) ) { Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , getI32Imm ( Lo ) ) ; } else if ( Lo ) { unsigned OpC = Hi ? <STR_LIT> : <STR_LIT> ; Result = CurDAG -> getMachineNode ( OpC , dl , <STR_LIT> , getI32Imm ( Hi ) ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Result , <NUM_LIT> ) , getI32Imm ( Lo ) ) ;


<s> if ( ! isABI_O32 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( UseIndirectJumpsHazard ) { if ( InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> ) ; if ( ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> ) ; } if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; } if ( hasDSPR2 ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } } else if ( hasDSP ( ) && ! DspWarningPrinted ) { if ( has<ISA_LIT>64 ( ) && ! has<ISA_LIT>64r2 ( ) ) { errs ( ) << <STR_LIT> << <STR_LIT> ; DspWarningPrinted = true ; } else if ( has<ISA_LIT>32 ( ) && ! has<ISA_LIT>32r2 ( ) ) {


<s> return ( __m256i ) __builtin_ia32_pmovzxbw256 ( ( __v16qi ) __X ) ;


<s> HOST_WIDE_INT val = INTVAL ( op ) ; int count ; if ( val < <NUM_LIT> ) { count = exact_log2 ( - val ) ;

if ( count < <NUM_LIT> ) return <NUM_LIT> ;


<s> CallInst * CreateCallEx ( IRB & B , Value * Callee , Value * Arg , const Twine & Name = <STR_LIT> ) { CallInst * R = B . CreateCall ( Callee , Arg , Name ) ;

if ( Function * F = dyn_cast < Function > ( Callee ) ) R -> setCallingConv ( F -> getCallingConv ( ) ) ;


<s> const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { switch ( Op . getReg ( ) ) { case <STR_LIT> : break ; default : O << getRegisterName ( Op . getReg ( ) ) ; break ; } } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ;


<s> static void EmitIndirectGuardCall ( const MCSubtargetInfo & STI , int I , MCInst Saved [ ] , MCStreamer & Out ) { assert ( I == <NUM_LIT> && ( <STR_LIT> == Saved [ <NUM_LIT> ] . getOpcode ( ) ) && <STR_LIT> ) ; unsigned Reg = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Pred = Saved [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; uint64_t Value = CE -> getValue ( ) ; return ( Value % Angle == Remainder && Value <= <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isPostIncrement ( const MachineInstr & MI ) const { const MCInstrDesc & MID = MI . getDesc ( ) ;


<s> int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isREVMask ( M , VT , <NUM_LIT> ) || isREVMask ( M , VT , <NUM_LIT> ) || isREVMask ( M , VT , <NUM_LIT> ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT , DummyUnsigned ) || isINSMask ( M , VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == <NUM_LIT> ) ) ;


<s> if ( ! ST -> hasMVEFloatOps ( ) ) return SDValue ( ) ; SDLoc dl ( BV ) ; EVT VT = BV . getValueType ( ) ; if ( VT != <STR_LIT> ) return SDValue ( ) ; if ( BV . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; if ( BV . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> || BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; SDValue Op0 = BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; SDValue Op1 = BV . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> || Op1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ;

for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) {


<s> fail ( DL , DAG , <STR_LIT> ) ; return SDValue ( ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerCopyToReg ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerAccessVectorElement ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerIntrinsic ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShift ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT_SAT ( Op , DAG ) ; case <STR_LIT> : return LowerLoad ( Op , DAG ) ; case <STR_LIT> : return LowerStore ( Op , DAG ) ;


<s> return PhysReg == <STR_LIT> || PhysReg == <STR_LIT> || PhysReg == <STR_LIT> ;


<s> __attribute__ ( ( __always_inline__ , __gnu_inline__ , __artificial__ ) ) __ignore_saturation ( void ) {


<s> bool isSPVFP = <STR_LIT> . contains ( RegD ) ; RegD = II -> getRegisterInfo ( ) . getEncodingValue ( RegD ) ;

if ( ! isSPVFP ) Binary |= RegD << <STR_LIT> ;


<s> SramEccSetting = NewSramEccSetting ;


<s> char * buffer ; if ( ! fseek ( stream , <NUM_LIT> , SEEK_END ) ) { long s = ftell ( stream ) ; if ( s >= <NUM_LIT> ) alloc = s + <NUM_LIT> ; fseek ( stream , <NUM_LIT> , SEEK_SET ) ; } buffer = XNEWVEC ( char , alloc ) ; for ( ; ; ) { size_t n = fread ( buffer + base , <NUM_LIT> , alloc - base - <NUM_LIT> , stream ) ; if ( ! n ) break ; base += n ; if ( base + <NUM_LIT> == alloc ) { alloc *= <NUM_LIT> ; buffer = XRESIZEVEC ( char , buffer , alloc ) ; }


<s> if ( ! first && MEM_P ( rtl ) && GET_CODE ( XEXP ( rtl , <NUM_LIT> ) ) == SYMBOL_REF ) old_referenced = SYMBOL_REF_FLAGS ( XEXP ( rtl , <NUM_LIT> ) ) & SYMBOL_FLAG_REFERENCED ; default_encode_section_info ( decl , rtl , first ) ; if ( first && TEXT_SPACE_P ( decl ) ) { SYMBOL_REF_FLAG ( XEXP ( rtl , <NUM_LIT> ) ) = <NUM_LIT> ; if ( TREE_CODE ( decl ) == FUNCTION_DECL ) pa_encode_label ( XEXP ( rtl , <NUM_LIT> ) ) ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ;


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { return <NUM_LIT> ; } break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) != MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) {


<s> assert ( ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) && <STR_LIT> <STR_LIT> ) ; uint64_t Value = CE -> getValue ( ) ; unsigned Elem = encodeNeonVMOVImmediate ( Value & <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( Elem ) ) ;


<s> default : return SDValue ( ) ; } if ( N -> getValueType ( <NUM_LIT> ) != ResVT ) return SDValue ( ) ; if ( Conversion . getValueType ( ) != ExpectedConversionType ) return SDValue ( ) ; auto Source = Conversion . getOperand ( <NUM_LIT> ) ; if ( Source . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! IsZeroSplat ( N -> getOperand ( <NUM_LIT> ) ) || N -> getOperand ( <NUM_LIT> ) . getValueType ( ) != ExpectedConversionType ) return SDValue ( ) ; unsigned Op = GetWasmConversionOp ( ConversionOp ) ; return DAG . getNode ( Op , SDLoc ( N ) , ResVT , Source ) ; } EVT ResVT ; auto ConversionOp = N -> getOpcode ( ) ; switch ( ConversionOp ) { case <STR_LIT> : case <STR_LIT> : ResVT = <STR_LIT> ; break ; case <STR_LIT> : ResVT = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal . startswith ( <STR_LIT> ) ) return parseAddrAsciz ( DirectiveID . getLoc ( ) ) ; return true ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemBase ( ) -> getGPR32Reg ( ) ) ) ; const MCExpr * Expr = getMemOff ( ) ; addExpr ( Inst , Expr ) ;


<s> if ( ! Value ) return ; unsigned TargetSize = getFixupKindInfo ( Kind ) . TargetSize ; unsigned TargetOffset = getFixupKindInfo ( Kind ) . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize = ( TargetOffset + TargetSize + <NUM_LIT> ) / <NUM_LIT> ; uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) {

unsigned Idx = ( FullSize - <NUM_LIT> - i ) ;


<s> static bool isHardwareLoop ( const MachineInstr * MI ) {

return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


<s> if ( Position != MBB . end ( ) ) { DL = Position -> getDebugLoc ( ) ; } if ( ! <STR_LIT> . hasSubClassEq ( RegisterClass ) ) { llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , Position , DL , get ( <STR_LIT> ) , DestinationRegister ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addImm ( LPAC :: ADD ) ;


<s> MI . setDesc ( HII . get ( <STR_LIT> ) ) ;

while ( MI . getNumOperands ( ) > <NUM_LIT> ) MI . RemoveOperand ( <NUM_LIT> ) ;


<s> for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) if ( I -> hasDelaySlot ( ) ) { MachineBasicBlock :: iterator D = MBB . end ( ) ; MachineBasicBlock :: iterator J = I ; if ( ! MBDisableDelaySlotFiller ) D = findDelayInstr ( MBB , I ) ; ++ FilledSlots ; Changed = true ; if ( D == MBB . end ( ) ) BuildMI ( MBB , ++ J , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; else MBB . splice ( ++ J , & MBB , D ) ;


<s> return false ; case <STR_LIT> : expandRetRA ( MBB , MI , <STR_LIT> ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , false ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> : expandCvtFPInt ( MBB , MI , <STR_LIT> , <STR_LIT> , true ) ; break ; case <STR_LIT> :

expandBuildPairF64 ( MBB , MI , false ) ;


<s> const TargetInstrInfo * TII = MF -> getTarget ( ) . getInstrInfo ( ) ; GlobalBaseReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , GlobalBaseReg ) . addReg ( <STR_LIT> ) ; RegInfo . addLiveIn ( <STR_LIT> ) ; <ISA_LIT>FI -> setGlobalBaseReg ( GlobalBaseReg ) ; return GlobalBaseReg ;


<s> initializeWinEHStatePassPass ( PR ) ; initializeFixupBWInstPassPass ( PR ) ; initializeEvexToVexInstPassPass ( PR ) ; initialize<ISA_LIT>ExecutionDepsFixPass ( PR ) ;


<s> } if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , static_cast < const TargetRegisterClass * > ( <NUM_LIT> ) ) ; case 'c' : if ( VT == <STR_LIT> ) return std :: make_pair ( ( unsigned ) <STR_LIT> , & <STR_LIT> ) ; assert ( <STR_LIT> ) ; } } std :: pair < unsigned , const TargetRegisterClass * > R ; R = parseRegForInlineAsmConstraint ( Constraint , VT ) ; if ( R . second ) return R ; return TargetLowering :: getRegForInlineAsmConstraint ( TRI , Constraint , VT ) ;


<s> <ISA_LIT>RegStackify ( ) : MachineFunctionPass ( ID ) {


<s> OutStreamer -> AddComment ( <STR_LIT> ) ; for ( auto & MO : drop_begin ( MI . operands ( ) ) ) if ( auto MaybeOperand = MCIL . LowerMachineOperand ( & MI , MO ) ) TC . addOperand ( MaybeOperand . getValue ( ) ) ;

OutStreamer -> emitInstruction ( TC , getSubtargetInfo ( ) ) ;


<s> if ( nvptxSubtarget . getDrvInterface ( ) == <STR_LIT> ) { if ( ! nvptxSubtarget . hasDouble ( ) ) O << <STR_LIT> ; } if ( MAI -> doesSupportDebugInformation ( ) ) O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ; if ( nvptxSubtarget . is64Bit ( ) ) O << <STR_LIT> ; else O << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> ;


<s> assert ( ( VT . is512BitVector ( ) || VT . is256BitVector ( ) || VT . is128BitVector ( ) ) && <STR_LIT> ) ; SDLoc DL ( Op . getNode ( ) ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( ! Subtarget . hasSSSE3 ( ) ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; return LowerVectorCTPOPBitmath ( Op0 , DL , Subtarget , DAG ) ;


<s> if ( LEGITIMATE_SMALL_DATA_ADDRESS_P ( x ) ) return true ; if ( GET_CODE ( x ) == CONST_INT && LARGE_INT ( INTVAL ( x ) ) ) return true ; if ( ! flag_pic && optimize_size && ! reload_completed && ( GET_CODE ( x ) == CONST ) && ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS ) && ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF ) && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == <NUM_LIT> && ! SYMBOL_REF_FUNCTION_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) { rtx addend = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; gcc_assert ( CONST_INT_P ( addend ) ) ; HOST_WIDE_INT offset = INTVAL ( addend ) ; return ! ( offset > - <NUM_LIT> && offset < <NUM_LIT> ) ; } if ( ( GET_MODE_SIZE ( mode ) != <NUM_LIT> ) && CONSTANT_P ( x ) ) {

if ( flag_pic ? arc_legitimate_pic_addr_p ( x ) : arc_legitimate_constant_p ( Pmode , x ) ) return true ;


<s> return __builtin_mve_vshlltq_n_sv8hi ( __a , __imm ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) {


<s> DebugLoc DL = MI . getDebugLoc ( ) ; int FrameIdx = MI . getOperand ( FIOperandNum ) . getIndex ( ) ;

auto isCalleeSaved = isCalleeSavedIndex ( FrameIdx , MF . getFrameInfo ( ) ) ;


<s> DItype __fixtfdi ( TFtype a ) { if ( a < <NUM_LIT> ) return - __fixunstfdi ( - a ) ;


<s> return mips_symbol_insns_1 ( type , mode ) * ( TARGET_MIPS16 ? <NUM_LIT> : <NUM_LIT> ) ;


<s> default : return <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


return ( __m64 ) ( ( __vector long long ) __c ) [ <NUM_LIT> ] ;


<s> for ( unsigned i = <NUM_LIT> , e = Use -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = Use -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isUndef ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ;

if ( Defs . count ( Reg ) ) return false ;


<s> Node = AdjustRegClass ( Node , DAG ) ;

if ( AMDGPU :: isMIMG ( Node -> getMachineOpcode ( ) ) != - <NUM_LIT> ) adjustWritemask ( Node , DAG ) ;


<s> addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( createUnpackMachineBundles ( [ ] ( const MachineFunction & MF ) { return MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isThumb2 ( ) ; } ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) { addPass ( create<ISA_LIT>BlockPlacementPass ( ) ) ; addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; }


<s> if ( ! DisableOptSZExt && MI -> isCopy ( ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( SrcReg ) ) { MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> addOperand ( MachineOperand :: CreateReg ( PeepholeSrc , false ) ) ; } } } if ( ! DisablePNotP ) { bool Done = false ; if ( QII -> isPredicated ( MI ) ) { MachineOperand & Op0 = MI -> getOperand ( <NUM_LIT> ) ; unsigned Reg0 = Op0 . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( Reg0 ) ; if ( RC0 -> getID ( ) == <STR_LIT> ) { if ( TargetRegisterInfo :: isVirtualRegister ( Reg0 ) ) { if ( unsigned PeepholeSrc = PeepholeMap . lookup ( Reg0 ) ) { MI -> getOperand ( <NUM_LIT> ) . setReg ( PeepholeSrc ) ; int NewOp = QII -> getInvertedPredicatedOpcode ( MI -> getOpcode ( ) ) ; MI -> setDesc ( QII -> get ( NewOp ) ) ; Done = true ; } } } } if ( ! Done ) { unsigned Op = MI -> getOpcode ( ) ; unsigned NewOp = <NUM_LIT> ; unsigned PR = <NUM_LIT> , S1 = <NUM_LIT> , S2 = <NUM_LIT> ; switch ( Op ) {


<s> const unsigned char * src = ( const unsigned char * ) opts_set ; unsigned char * dest = ( unsigned char * ) & new_opts_set ; unsigned int i ; for ( i = <NUM_LIT> ; i < sizeof ( * opts_set ) ; i ++ ) dest [ i ] |= src [ i ] ; s390_option_override_internal ( false , opts , & new_opts_set ) ; t = build_target_option_node ( opts ) ; } return t ;


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O << <STR_LIT> ;


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; if ( MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . hasV60TOpsOnly ( ) && HII . isHVXMemWithAIndirect ( MI , MJ ) ) return true ; if ( MI . isInlineAsm ( ) ) return MJ . isInlineAsm ( ) || MJ . isBranch ( ) || MJ . isBarrier ( ) || MJ . isCall ( ) || MJ . isTerminator ( ) ;


<s> if ( DstIndex == - <NUM_LIT> ) { return ; } unsigned DestReg = MI -> getOperand ( DstIndex ) . getReg ( ) ; for ( MachineInstr :: mop_iterator It = MI -> operands_begin ( ) , E = MI -> operands_end ( ) ; It != E ; ++ It ) { MachineOperand & MO = * It ; if ( MO . isReg ( ) && ! MO . isDef ( ) && MO . getReg ( ) == DestReg ) return ; } switch ( Slot ) { case <NUM_LIT> : MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ; break ;


<s> EVT VT = StVal . getValueType ( ) ; if ( ! VT . isVector ( ) || VT . getVectorNumElements ( ) < <NUM_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , S ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , DL , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ;

SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> isVolatile ( ) , S -> isNonTemporal ( ) , S -> getAlignment ( ) ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res ;


<s> static const TargetRegisterClass * getMinClassForRegBank ( const RegisterBank & RB , unsigned SizeInBits , bool GetAllRegSet = false ) { unsigned RegBankID = RB . getID ( ) ; if ( RegBankID == <STR_LIT> ) {

if ( SizeInBits <= <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ;


<s> static bool CompareSSIOffset ( const StackSlotInfo & a , const StackSlotInfo & b ) { return a . Offset < b . Offset ;


<s> unsigned Align = TD -> getPreferredAlignmentLog ( GVar ) ; printVisibility ( name , GVar -> getVisibility ( ) ) ; SwitchToSection ( TAI -> SectionForGlobal ( GVar ) ) ; if ( C -> isNullValue ( ) && ! GVar -> hasSection ( ) ) { if ( ! GVar -> isThreadLocal ( ) && ( GVar -> hasLocalLinkage ( ) || GVar -> isWeakForLinker ( ) ) ) { if ( Size == <NUM_LIT> ) Size = <NUM_LIT> ; if ( GVar -> hasLocalLinkage ( ) ) { O << <STR_LIT> << name << <STR_LIT> << Size << ',' << ( <NUM_LIT> << Align ) ; O << '\n' ; } else { O << <STR_LIT> << name << <STR_LIT> << Size << ',' << ( <NUM_LIT> << Align ) ; O << '\n' ; } return ; } } switch ( GVar -> getLinkage ( ) ) { case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: CommonLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : O << <STR_LIT> << name << '\n' ; break ; case GlobalValue :: AppendingLinkage : case GlobalValue :: ExternalLinkage : O << TAI -> getGlobalDirective ( ) << name << '\n' ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : break ; case GlobalValue :: GhostLinkage : cerr << <STR_LIT> ;


<s> if ( startswith ( name , lower_prefix ) ) name += strlen ( lower_prefix ) ; else if ( startswith ( name , upper_prefix ) ) name += strlen ( upper_prefix ) ;

else if ( startswith ( name , either_prefix ) ) name += strlen ( either_prefix ) ;


<s> unsigned long m = __M ; unsigned long c ; unsigned long result ; if ( __builtin_constant_p ( __M ) && ( __builtin_popcountl ( __M ) <= <NUM_LIT> ) ) { for ( long i = <NUM_LIT> ; i < __builtin_popcountl ( __M ) ; i ++ ) { c = __builtin_clzl ( m ) ; p = ( p << <NUM_LIT> ) | c ; m ^= ( mask >> c ) ; } result = __builtin_bpermd ( p , __X ) ; } else { p = <NUM_LIT> - __builtin_popcountl ( __M ) ; result = <NUM_LIT> ; while ( m != <NUM_LIT> ) { unsigned long t ; c = __builtin_clzl ( m ) ; t = ( __X & ( mask >> c ) ) >> ( p - c ) ; m ^= ( mask >> c ) ; result |= ( t ) ; p ++ ; }


<s> if ( DA -> isUniform ( & I ) ) setUniformMetadata ( & I ) ;


<s> typedef std :: make_unsigned_t < T > UnsignedT ; uint64_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ; UnsignedT PrintVal = <STR_LIT> ( Val , <NUM_LIT> ) ; if ( ( int16_t ) PrintVal == ( SignedT ) PrintVal ) printImmSVE ( ( T ) PrintVal , O ) ; else if ( ( uint16_t ) PrintVal == PrintVal ) printImmSVE ( PrintVal , O ) ;

else O << '#' << formatHex ( ( uint64_t ) PrintVal ) ;


<s> SDLoc dl ( Op ) ; bool UseHVX = Subtarget . useHVXOps ( ) ; EVT VT = Op . getValueType ( ) ; unsigned NElts = Op . getNumOperands ( ) ; SDValue Vec0 = Op . getOperand ( <NUM_LIT> ) ; EVT VecVT = Vec0 . getValueType ( ) ; unsigned Width = VecVT . getSizeInBits ( ) ; if ( NElts == <NUM_LIT> ) { MVT ST = VecVT . getSimpleVT ( ) ; if ( ST == <STR_LIT> || ST == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op . getOperand ( <NUM_LIT> ) , Vec0 ) ; if ( UseHVX ) { assert ( ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXSglOps ( ) ) || ( Width == <NUM_LIT> * <NUM_LIT> && Subtarget . useHVXDblOps ( ) ) ) ; SDValue Vec1 = Op . getOperand ( <NUM_LIT> ) ; MVT OpTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; MVT ReTy = Subtarget . useHVXSglOps ( ) ? <STR_LIT> : <STR_LIT> ; SDValue B0 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec0 ) ; SDValue B1 = DAG . getNode ( <STR_LIT> , dl , OpTy , Vec1 ) ; SDValue VC = DAG . getNode ( <STR_LIT> , dl , ReTy , B1 , B0 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , VC ) ; } } if ( VT . getSizeInBits ( ) != <NUM_LIT> && VT . getSizeInBits ( ) != <NUM_LIT> ) return SDValue ( ) ; SDValue C0 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue C32 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue W = DAG . getConstant ( Width , dl , <STR_LIT> ) ; SDValue S = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , W , C32 ) ;


<s> SDValue Base1 = Loc , Base2 = BaseLoc ; int64_t Offset1 = <NUM_LIT> , Offset2 = <NUM_LIT> ; getBaseWithConstantOffset ( Loc , Base1 , Offset1 , DAG ) ; getBaseWithConstantOffset ( BaseLoc , Base2 , Offset2 , DAG ) ; if ( Base1 == Base2 && Offset1 == ( Offset2 + Dist * Bytes ) ) return true ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; const GlobalValue * GV1 = nullptr ; const GlobalValue * GV2 = nullptr ; Offset1 = <NUM_LIT> ; Offset2 = <NUM_LIT> ; bool isGA1 = TLI . isGAPlusOffset ( Loc . getNode ( ) , GV1 , Offset1 ) ; bool isGA2 = TLI . isGAPlusOffset ( BaseLoc . getNode ( ) , GV2 , Offset2 ) ; if ( isGA1 && isGA2 && GV1 == GV2 ) return Offset1 == ( Offset2 + Dist * Bytes ) ; return false ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , Options , isLittle ) , TT , CPU , FS , Options , getEffectiveRelocModel ( CM , RM ) , CodeModel :: Medium , OL ) , isLittle ( isLittle ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , ABI ( <ISA_LIT>ABIInfo :: computeTargetABI ( ) ) , DefaultSubtarget ( TT , CPU , FS , isLittle , * this ) {


<s> return HasProcessorActivityInstrumentation ;


<s> bool <ISA_LIT>FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; bool NeedsWinCFI = needsWinCFI ( MF ) ; DebugLoc DL ; SmallVector < RegPairInfo , <NUM_LIT> > RegPairs ; bool NeedShadowCallStackProlog = false ; computeCalleeSaveRegisterPairs ( MF , CSI , TRI , RegPairs , NeedShadowCallStackProlog , hasFP ( MF ) ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( NeedShadowCallStackProlog ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( NeedsWinCFI ) BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( ! MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoUnwind ) ) { static const char CFIInst [ ] = { dwarf :: DW_CFA_val_expression , <NUM_LIT> , <NUM_LIT> , static_cast < char > ( unsigned ( dwarf :: DW_OP_breg18 ) ) , static_cast < char > ( - <NUM_LIT> ) & <NUM_LIT> , } ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createEscape ( nullptr , StringRef ( CFIInst , sizeof ( CFIInst ) ) ) ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } MBB . addLiveIn ( <STR_LIT> ) ; } for ( auto RPII = RegPairs . rbegin ( ) , RPIE = RegPairs . rend ( ) ; RPII != RPIE ; ++ RPII ) { RegPairInfo RPI = * RPII ; unsigned Reg1 = RPI . Reg1 ; unsigned Reg2 = RPI . Reg2 ; unsigned StrOpc ; unsigned Size , Align ; switch ( RPI . Type ) { case RegPairInfo :: GPR :

StrOpc = RPI . isPaired ( ) ? <STR_LIT> : <STR_LIT> ;


return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , false , true , true ) ;


<s> bool <ISA_LIT>AsmParser :: validateMSAIndex ( int Val , int RegKind ) { <STR_LIT> Kind = ( <STR_LIT> ) RegKind ;


if ( ! ( isRegIdx ( ) && RegIdx . Kind & RegKind_FCC ) ) return false ;


<s> CurrentLocalMemUsage = <NUM_LIT> ; for ( GlobalVariable & GV : Mod -> globals ( ) ) { if ( GV . getType ( ) -> getAddressSpace ( ) != AS . LOCAL_ADDRESS ) continue ; for ( const User * U : GV . users ( ) ) { const Instruction * Use = dyn_cast < Instruction > ( U ) ; if ( ! Use ) continue ; if ( Use -> getParent ( ) -> getParent ( ) == & F ) { unsigned Align = GV . getAlignment ( ) ; if ( Align == <NUM_LIT> ) Align = DL . getABITypeAlignment ( GV . getValueType ( ) ) ; uint64_t AllocSize = DL . getTypeAllocSize ( GV . getValueType ( ) ) ; CurrentLocalMemUsage = alignTo ( CurrentLocalMemUsage , Align ) ; CurrentLocalMemUsage += AllocSize ; break ; } } } unsigned MaxOccupancy = ST . getOccupancyWithLocalMemSize ( CurrentLocalMemUsage , F ) ; unsigned OccupancyHint = ST . getWavesPerEU ( F ) . second ; if ( OccupancyHint == <NUM_LIT> ) OccupancyHint = <NUM_LIT> ; OccupancyHint = std :: min ( OccupancyHint , ST . getMaxWavesPerEU ( ) ) ; MaxOccupancy = std :: min ( OccupancyHint , MaxOccupancy ) ; unsigned MaxSizeWithWaveCount = ST . getMaxLocalMemSizeWithWaveCount ( MaxOccupancy , F ) ; if ( CurrentLocalMemUsage > MaxSizeWithWaveCount ) return false ;


<s> if ( ! address_operand ( op [ arg_count ] , SImode ) ) { op [ arg_count ] = convert_memory_address ( Pmode , op [ arg_count ] ) ; op [ arg_count ] = copy_addr_to_reg ( op [ arg_count ] ) ; } op [ arg_count ] = gen_rtx_MEM ( SImode , op [ arg_count ] ) ; } else if ( insn_op -> mode == V1DImode && GET_MODE ( op [ arg_count ] ) == DImode ) op [ arg_count ] = gen_lowpart ( V1DImode , op [ arg_count ] ) ; else if ( insn_op -> mode == V1SImode && GET_MODE ( op [ arg_count ] ) == SImode ) op [ arg_count ] = gen_lowpart ( V1SImode , op [ arg_count ] ) ; if ( ! ( * insn_data [ icode ] . operand [ idx ] . predicate ) ( op [ arg_count ] , insn_op -> mode ) ) op [ arg_count ] = copy_to_mode_reg ( insn_op -> mode , op [ arg_count ] ) ; }


<s> <ISA_LIT>AsmBackend ( T ) , OSABI ( OSABI ) {


<s> const FeatureBitset & Features = STI -> getFeatureBits ( ) ; if ( Features [ <STR_LIT> ] ) emitRR ( <STR_LIT> , <STR_LIT> , <STR_LIT> , IDLoc , STI ) ; else emitRRI ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> , IDLoc , STI ) ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; const Function * Func = MBB . getParent ( ) -> getFunction ( ) ; const std :: string FuncName = Func -> getName ( ) ; const char * tmpName = ESNames :: createESName ( PAN :: getTempdataLabel ( FuncName ) ) ; if ( RC == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( PTLI -> GetTmpOffsetForFI ( FI , <NUM_LIT> ) ) . addExternalSymbol ( tmpName ) . addImm ( <NUM_LIT> ) ;


<s> EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : { errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ; llvm_unreachable ( nullptr ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; SDValue InVal ; <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) { int FI = MFI -> CreateFixedObject ( Flags . getByValSize ( ) , VA . getLocMemOffset ( ) , true ) ; InVal = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; } else { unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ;