<s> gcc_assert ( size <= <NUM_LIT> ) ; if ( mode == BLKmode ) return function_arg_vector_value ( size , TYPE_MODE ( TREE_TYPE ( type ) ) , SPARC_FP_ARG_FIRST + <NUM_LIT> * slotno ) ; else mclass = MODE_FLOAT ; } if ( ( mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT ) && SPARC_FP_REG_P ( regno ) ) { reg = gen_rtx_REG ( mode , regno ) ; if ( cum -> prototype_p || cum -> libcall_p ) { if ( ( regno - SPARC_FP_ARG_FIRST ) >= SPARC_INT_ARG_MAX * <NUM_LIT> ) return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ) ) ; else return reg ; } else { rtx v0 , v1 ; if ( ( regno - SPARC_FP_ARG_FIRST ) < SPARC_INT_ARG_MAX * <NUM_LIT> ) { int intreg ; if ( incoming_p ) return reg ; intreg = ( SPARC_OUTGOING_INT_ARG_FIRST + ( regno - SPARC_FP_ARG_FIRST ) / <NUM_LIT> ) ; v0 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , intreg ) , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , v0 , v1 ) ) ; } else { v0 = gen_rtx_EXPR_LIST ( VOIDmode , NULL_RTX , const0_rtx ) ; v1 = gen_rtx_EXPR_LIST ( VOIDmode , reg , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , v0 , v1 ) ) ; } } } else { reg = gen_rtx_REG ( mode , regno ) ;


<s> IsSameOrSubReg = getRegisterInfo ( ) -> isSubRegisterEq ( DepR , MOReg ) ; } if ( MO . isDef ( ) && IsSameOrSubReg ) DefIdx = OpNum ; } } assert ( DefIdx >= <NUM_LIT> && <STR_LIT> ) ; MachineInstr * DstI = Dst -> getInstr ( ) ; SDep T = I ; for ( unsigned OpNum = <NUM_LIT> ; OpNum < DstI -> getNumOperands ( ) ; OpNum ++ ) { const MachineOperand & MO = DstI -> getOperand ( OpNum ) ; if ( MO . isReg ( ) && MO . isUse ( ) && MO . getReg ( ) == DepR ) { int Latency = ( InstrInfo . getOperandLatency ( & InstrItins , * SrcI , DefIdx , * DstI , OpNum ) ) ; Latency = std :: max ( Latency , <NUM_LIT> ) ; I . setLatency ( Latency ) ; updateLatency ( * SrcI , * DstI , I ) ; } }


<s> return __builtin_neon_vcvtmsv4hf ( __a ) ;


<s> else if ( DEFAULT_ABI != ABI_DARWIN ) { bool is_local = ( fndecl && ! DECL_EXTERNAL ( fndecl ) && ! DECL_WEAK ( fndecl ) && ( * targetm . binds_local_p ) ( fndecl ) ) ; if ( is_local ) ; else if ( flag_plt ) { if ( fntype && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) cum -> call_cookie |= CALL_LONG ; } else { if ( ! ( fntype && lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( fntype ) ) ) ) cum -> call_cookie |= CALL_LONG ; } } if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> ) ; if ( fntype ) { tree ret_type = TREE_TYPE ( fntype ) ; fprintf ( stderr , <STR_LIT> , get_tree_code_name ( TREE_CODE ( ret_type ) ) ) ; } if ( cum -> call_cookie & CALL_LONG ) fprintf ( stderr , <STR_LIT> ) ; fprintf ( stderr , <STR_LIT> , cum -> prototype , cum -> nargs_prototype ) ; } if ( TARGET_ELF && ( TARGET_64BIT || DEFAULT_ABI == ABI_V4 ) ) { cum -> escapes = call_ABI_of_interest ( fndecl ) ; if ( cum -> escapes ) { tree return_type ; if ( fntype ) {


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result ;


<s> static __inline qword si_shli ( qword a , unsigned int b ) { vec_uint4 bv ; vec_uint4 mask ;

bv = vec_splat ( ( vec_uint4 ) ( si_from_uint ( b ) ) , <NUM_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( unsigned ( getProcIFlags ( ) ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : UseOp = MI -> findRegisterUseOperandIdx ( Reg , false , TRI ) ; break ; case <STR_LIT> : UseOp = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( UseOp != - <NUM_LIT> && MI -> getOperand ( UseOp ) . readsReg ( ) ) return <NUM_LIT> ; if ( TargetRegisterInfo :: isVirtualRegister ( Reg ) ) { if ( ! MO . getSubReg ( ) || MI -> readsVirtualRegister ( Reg ) ) return <NUM_LIT> ; } else if ( <STR_LIT> . contains ( Reg ) ) {

unsigned DReg = TRI -> getMatchingSuperReg ( Reg , <STR_LIT> , & <STR_LIT> ) ;


<s> int Offset = <NUM_LIT> ; const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; assert ( ! MFI -> hasVarSizedObjects ( ) ) ;

if ( MFI -> getNumObjects ( ) == <NUM_LIT> ) {


<s> const Module * M = Func . getParent ( ) ; auto & DL = M -> getDataLayout ( ) ; const <ISA_LIT>MachineFunctionInfo & MFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; auto Int64Ty = Type :: getInt64Ty ( Func . getContext ( ) ) ; auto Int32Ty = Type :: getInt32Ty ( Func . getContext ( ) ) ; auto Int16Ty = Type :: getInt16Ty ( Func . getContext ( ) ) ; Offset = alignTo ( Offset , ST . getAlignmentForImplicitArgPtr ( ) ) ; emitKernelArg ( DL , Int32Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int32Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int32Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; Offset += <NUM_LIT> ; Offset += <NUM_LIT> ; emitKernelArg ( DL , Int64Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int64Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int64Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; Offset += <NUM_LIT> ; auto Int8PtrTy = Type :: getInt8PtrTy ( Func . getContext ( ) , <ISA_LIT>AS :: GLOBAL_ADDRESS ) ; if ( M -> getNamedMetadata ( <STR_LIT> ) ) {

emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return createTuple ( Regs , RegClassIDs , SubRegs , MIB ) ;


<s> addPass ( createInterleavedAccessPass ( ) ) ; addPass ( create<ISA_LIT>PartialReductionPass ( ) ) ; } addPass ( createIndirectBrExpandPass ( ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; if ( TT . isOSWindows ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) { addPass ( createCFGuardDispatchPass ( ) ) ;


<s> bool HasReplacedPseudoInst = replacePseudoRegTransferCode ( MF ) ; if ( HasReplacedPseudoInst && needToReserveScavengingSpillSlots ( MF , HRI ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; for ( int i = <NUM_LIT> ; i < NumberScavengerSlots ; i ++ ) RS -> addScavengingFrameIndex ( MFI -> CreateSpillStackObject ( RC . getSize ( ) , RC . getAlignment ( ) ) ) ;


<s> bool return_in_pc = saved_regs_mask & ( <NUM_LIT> << PC_REGNUM ) ; int offset_adj ; int emit_update ; offset_adj = return_in_pc ? <NUM_LIT> : <NUM_LIT> ; for ( i = <NUM_LIT> ; i <= LAST_ARM_REGNUM ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) num_regs ++ ; gcc_assert ( num_regs && num_regs <= <NUM_LIT> ) ; emit_update = ( saved_regs_mask & ( <NUM_LIT> << SP_REGNUM ) ) ? <NUM_LIT> : <NUM_LIT> ; par = gen_rtx_PARALLEL ( VOIDmode , rtvec_alloc ( num_regs + emit_update + offset_adj ) ) ; if ( return_in_pc ) XVECEXP ( par , <NUM_LIT> , <NUM_LIT> ) = ret_rtx ; if ( emit_update ) { tmp = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * num_regs ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , offset_adj ) = tmp ; } for ( j = <NUM_LIT> , i = <NUM_LIT> ; j < num_regs ; i ++ ) if ( saved_regs_mask & ( <NUM_LIT> << i ) ) { reg = gen_rtx_REG ( SImode , i ) ; if ( ( num_regs == <NUM_LIT> ) && emit_update && ! return_in_pc ) { tmp = gen_frame_mem ( SImode , gen_rtx_POST_INC ( Pmode , stack_pointer_rtx ) ) ; tmp = emit_insn ( gen_rtx_SET ( reg , tmp ) ) ; REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; return ; } tmp = gen_rtx_SET ( reg , gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> * j ) ) ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; XVECEXP ( par , <NUM_LIT> , j + emit_update + offset_adj ) = tmp ; if ( i != PC_REGNUM ) dwarf = alloc_reg_note ( REG_CFA_RESTORE , reg , dwarf ) ; j ++ ; } if ( return_in_pc ) par = emit_jump_insn ( par ) ; else par = emit_insn ( par ) ; REG_NOTES ( par ) = dwarf ; if ( ! return_in_pc ) arm_add_cfa_adjust_cfa_note ( par , UNITS_PER_WORD * num_regs , stack_pointer_rtx , stack_pointer_rtx ) ;


<s> if ( PrevTK != AsmToken :: RBrac ) return ; SM . setAppendAfterOperand ( ) ;


<s> virtual bool assignArg ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , const CallLowering :: ArgInfo & Info , CCState & State ) override { if ( Info . IsFixed ) return AssignFn ( ValNo , ValVT , LocVT , LocInfo , Info . Flags , State ) ;

return AssignFnVarArg ( ValNo , ValVT , LocVT , LocInfo , Info . Flags , State ) ;


<s> if ( ( mode == QImode || mode == HImode ) && ! TARGET_BWX ) { if ( GET_CODE ( x ) == MEM || ( GET_CODE ( x ) == REG && REGNO ( x ) >= FIRST_PSEUDO_REGISTER ) || ( GET_CODE ( x ) == SUBREG && ( GET_CODE ( SUBREG_REG ( x ) ) == MEM || ( GET_CODE ( SUBREG_REG ( x ) ) == REG && REGNO ( SUBREG_REG ( x ) ) >= FIRST_PSEUDO_REGISTER ) ) ) ) { if ( ! in || ! aligned_memory_operand ( x , mode ) ) return GENERAL_REGS ; } } if ( class == FLOAT_REGS ) { if ( GET_CODE ( x ) == MEM && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == AND ) return GENERAL_REGS ; if ( GET_CODE ( x ) == SUBREG && ( GET_MODE_SIZE ( GET_MODE ( x ) ) > GET_MODE_SIZE ( GET_MODE ( SUBREG_REG ( x ) ) ) ) ) return GENERAL_REGS ; if ( in && INTEGRAL_MODE_P ( mode ) && ! ( memory_operand ( x , mode ) || x == const0_rtx ) ) return GENERAL_REGS ;


<s> case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_GOT_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_LO ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_HI ; break ; case <STR_LIT> : Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_TPREL_ADD ;


<s> case REG : case PLUS : case LO_SUM : return <NUM_LIT> ; case HIGH : return <NUM_LIT> ; default : return <NUM_LIT> ; }


<s> ErrorOr < PrefetchHints > getPrefetchHints ( const FunctionSamples * TopSamples , const MachineInstr & MI ) { if ( const auto & Loc = MI . getDebugLoc ( ) ) if ( const auto * Samples = TopSamples -> findFunctionSamples ( Loc ) ) return Samples -> findCallTargetMapAt ( FunctionSamples :: getOffset ( Loc ) , Loc -> getBaseDiscriminator ( ) ) ; return std :: error_code ( ) ;


<s> if ( OptLevel != CodeGenOpt :: None ) { PM . add ( createIfConverterPass ( ) ) ; } return true ;


<s> bool B = TII -> analyzeBranch ( * BB , TBB , FBB , Cond ) ; if ( ! B && Cond . empty ( ) && BB != & MF -> front ( ) && ! TII -> analyzeBranch ( * OldPrior , TBB , FBB , CondPrior ) ) { BB -> moveAfter ( JTBB ) ; OldPrior -> updateTerminator ( BB ) ; BB -> updateTerminator ( OldNext != MF -> end ( ) ? & * OldNext : nullptr ) ; MF -> RenumberBlocks ( ) ; ++ NumJTMoved ; return nullptr ; } MachineBasicBlock * NewBB = MF -> CreateMachineBasicBlock ( JTBB -> getBasicBlock ( ) ) ; MachineFunction :: iterator MBBI = ++ JTBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; for ( const MachineBasicBlock :: RegisterMaskPair & RegMaskPair : BB -> liveins ( ) ) NewBB -> addLiveIn ( RegMaskPair ) ; if ( isThumb2 ) BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( NewBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( BB ) . add ( predOps ( <STR_LIT> ) ) ; MF -> RenumberBlocks ( NewBB ) ; NewBB -> addSuccessor ( BB ) ; JTBB -> replaceSuccessor ( BB , NewBB ) ; if ( MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> branchTargetEnforcement ( ) ) fixupBTI ( JTI , * BB , * NewBB ) ; ++ NumJTInserted ; return NewBB ;


<s> bool GenerateTBB = isThumb2 || ( isThumb1 && SynthesizeThumb1TBB ) ; if ( STI -> hardenSlsRetBr ( ) ) GenerateTBB = false ; MF -> RenumberBlocks ( ) ; bool MadeChange = false ; if ( GenerateTBB && AdjustJumpTableBlocks ) { scanFunctionJumpTables ( ) ; MadeChange |= reorderThumb2JumpTables ( ) ; T2JumpTables . clear ( ) ; MF -> RenumberBlocks ( ) ; } MadeChange |= AlignBlocks ( MF ) ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP -> isEmpty ( ) ) doInitialConstPlacement ( CPEMIs ) ; if ( MF -> getJumpTableInfo ( ) ) doInitialJumpTablePlacement ( CPEMIs ) ; AFI -> initPICLabelUId ( CPEMIs . size ( ) ) ; initializeFunctionInfo ( CPEMIs ) ; CPEMIs . clear ( ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! T2JumpTables . empty ( ) ) MF -> ensureAlignment ( Align ( <NUM_LIT> ) ) ; MadeChange |= removeUnusedCPEntries ( ) ; unsigned NoCPIters = <NUM_LIT> , NoBRIters = <NUM_LIT> ; while ( true ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoCPIters << '\n' ) ; bool CPChange = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) CPChange |= handleConstantPoolUser ( i , NoCPIters >= CPMaxIteration / <NUM_LIT> ) ; if ( CPChange && ++ NoCPIters > CPMaxIteration ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; NewWaterList . clear ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << NoBRIters << '\n' ) ; bool BRChange = false ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) BRChange |= fixupImmediateBr ( ImmBranches [ i ] ) ; if ( BRChange && ++ NoBRIters > <NUM_LIT> ) report_fatal_error ( <STR_LIT> ) ; LLVM_DEBUG ( dumpBBs ( ) ) ; if ( ! CPChange && ! BRChange ) break ;


<s> int Imm ; unsigned Opc ; <STR_LIT> Cmp ; std :: tie ( Imm , Opc , Cmp ) = Info ; MachineBasicBlock * const MBB = CmpMI -> getParent ( ) ; BuildMI ( * MBB , CmpMI , CmpMI -> getDebugLoc ( ) , TII -> get ( Opc ) ) . add ( CmpMI -> getOperand ( <NUM_LIT> ) ) . add ( CmpMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Imm ) . add ( CmpMI -> getOperand ( <NUM_LIT> ) ) ; CmpMI -> eraseFromParent ( ) ; MachineInstr & BrMI = * MBB -> getFirstTerminator ( ) ; BuildMI ( * MBB , BrMI , BrMI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( Cmp ) . add ( BrMI . getOperand ( <NUM_LIT> ) ) ; BrMI . eraseFromParent ( ) ; ++ NumConditionsAdjusted ;


<s> static SDValue lowerVectorShuffleAsBroadcast ( SDLoc DL , MVT VT , SDValue V , ArrayRef < int > Mask , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { if ( ! Subtarget . hasAVX ( ) ) return SDValue ( ) ; if ( VT . isInteger ( ) && ! Subtarget . hasAVX2 ( ) ) return SDValue ( ) ; int BroadcastIdx = - <NUM_LIT> ; for ( int M : Mask ) if ( M >= <NUM_LIT> && BroadcastIdx == - <NUM_LIT> ) BroadcastIdx = M ; else if ( M >= <NUM_LIT> && M != BroadcastIdx ) return SDValue ( ) ; assert ( BroadcastIdx < ( int ) Mask . size ( ) && <STR_LIT> <STR_LIT> <STR_LIT> ) ; for ( ; ; ) { switch ( V . getOpcode ( ) ) { case <STR_LIT> : { int OperandSize = Mask . size ( ) / V . getNumOperands ( ) ; V = V . getOperand ( BroadcastIdx / OperandSize ) ; BroadcastIdx %= OperandSize ; continue ; } case <STR_LIT> : { SDValue VOuter = V . getOperand ( <NUM_LIT> ) , VInner = V . getOperand ( <NUM_LIT> ) ; auto ConstantIdx = dyn_cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ; if ( ! ConstantIdx ) break ; int BeginIdx = ( int ) ConstantIdx -> getZExtValue ( ) ; int EndIdx = BeginIdx + ( int ) VInner . getSimpleValueType ( ) . getVectorNumElements ( ) ; if ( BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx ) { BroadcastIdx -= BeginIdx ; V = VInner ; } else { V = VOuter ; }


<s> if ( MF . getFunction ( ) -> hasFnAttribute ( <STR_LIT> ) ) return MF . getFunction ( ) -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) ; if ( ! Subtarget . isOSWindows ( ) || Subtarget . isTargetMachO ( ) ) return <STR_LIT> ;

if ( Subtarget . is64Bit ( ) ) return Subtarget . isTargetCygMing ( ) ? <STR_LIT> : <STR_LIT> ;


<s> unsigned <ISA_LIT>TargetLowering :: getMaxSupportedInterleaveFactor ( ) const { if ( Subtarget -> hasNEON ( ) ) return <NUM_LIT> ;

if ( Subtarget -> hasMVEIntegerOps ( ) ) return MVEMaxSupportedInterleaveFactor ;


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; MemOpsEmitted = <NUM_LIT> ;

uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ;


<s> unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> && ( Subtarget -> hasNEON ( ) || isLegalMVEShuffleOp ( PFEntry ) ) ) return true ; } bool ReverseVEXT , isV_UNDEF ; unsigned Imm , WhichResult ; unsigned EltSize = VT . getScalarSizeInBits ( ) ; if ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || ShuffleVectorInst :: isIdentityMask ( M ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) ) return true ; else if ( Subtarget -> hasNEON ( ) && ( isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) ) ) return true ; else if ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( M , VT ) ) return true ; else if ( Subtarget -> hasMVEIntegerOps ( ) && ( isVMOVNMask ( M , VT , true , false ) || isVMOVNMask ( M , VT , false , false ) || isVMOVNMask ( M , VT , true , true ) ) ) return true ;


<s> return parseAddress ( Operands , <STR_LIT> , ADDR64Reg , BDXMem ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerSETCCCARRY ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Carry = Op . getOperand ( <NUM_LIT> ) ; SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( LHS . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ;

<STR_LIT> CC = TranslateInteger<ISA_LIT>CC ( cast < CondCodeSDNode > ( Cond ) -> get ( ) ) ;


<s> removeUseSoftFloat ( * F ) ; continue ; } if ( F -> isDeclaration ( ) || F -> hasFnAttribute ( <STR_LIT> ) || F -> hasFnAttribute ( <STR_LIT> ) ) continue ; Modified |= fixupFPReturnAndCall ( * F , & M , TM ) ; FPParamVariant V = whichFPParamVariantNeeded ( * F ) ; if ( V != NoSig ) { Modified = true ; createFPFnStub ( & * F , & M , V , TM ) ; }


<s> DEBUG ( dbgs ( ) << <STR_LIT> << j << <STR_LIT> << k << <STR_LIT> << MCB . getOperand ( j ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> << MCB . getOperand ( k ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> ) ; continue ; } else { DEBUG ( dbgs ( ) << <STR_LIT> << j << <STR_LIT> << k << <STR_LIT> << MCB . getOperand ( j ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> << MCB . getOperand ( k ) . getInst ( ) -> getOpcode ( ) << <STR_LIT> ) ; } if ( bisReversable ) { if ( isOrderedDuplexPair ( MCII , * MCB . getOperand ( j ) . getInst ( ) , <ISA_LIT>MCInstrInfo :: hasExtenderForIndex ( MCB , j - <NUM_LIT> ) , * MCB . getOperand ( k ) . getInst ( ) , <ISA_LIT>MCInstrInfo :: hasExtenderForIndex ( MCB , k - <NUM_LIT> ) , bisReversable ) ) { unsigned iClass = iClassOfDuplexPair ( getDuplexCandidateGroup ( * MCB . getOperand ( j ) . getInst ( ) ) , getDuplexCandidateGroup ( * MCB . getOperand ( k ) . getInst ( ) ) ) ;

duplexToTry . push_back ( DuplexCandidate ( k , j , iClass ) ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { emitFrameDirective ( ) ;


<s> Has64BitSupport = false ; Use64BitRegs = false ; UseCRBits = false ; HasHardFloat = false ; HasAltivec = false ; HasSPE = false ; HasFPU = false ; HasQPX = false ; HasVSX = false ; NeedsTwoConstNR = false ; HasP8Vector = false ; HasP8Altivec = false ; HasP8Crypto = false ; HasP9Vector = false ; HasP9Altivec = false ; HasFCPSGN = false ; HasFSQRT = false ; HasFRE = false ; HasFRES = false ; HasFRSQRTE = false ;


<s> SDValue Hi = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; SDValue Lo = getTargetNode ( N , Ty , DAG , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , DAG . getNode ( <STR_LIT> , DL , Ty , Hi ) , DAG . getNode ( <STR_LIT> , DL , Ty , Lo ) ) ;


<s> Op -> VectorList . Count = Count ; Op -> VectorList . NumElements = NumElements ; Op -> VectorList . ElementKind = ElementKind ; Op -> StartLoc = S ;


<s> static SDValue lowerV4I64VectorShuffle ( SDValue Op , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget * Subtarget , SelectionDAG & DAG ) { SDLoc DL ( Op ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget -> hasAVX2 ( ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > WidenedMask ; if ( canWidenShuffleElements ( Mask , WidenedMask ) ) return lowerV2X128VectorShuffle ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ; if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Blend ;

if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TM ( TM ) , STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) {


<s> switch ( N0 . getOpcode ( ) ) { case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; case <STR_LIT> : FPOpcode = <STR_LIT> ; break ; default : return SDValue ( ) ; } if ( ! ( ( Subtarget . hasSSE1 ( ) && VT == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && VT == <STR_LIT> ) ) ) return SDValue ( ) ; SDValue LogicOp0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue LogicOp1 = N0 . getOperand ( <NUM_LIT> ) ; SDLoc DL0 ( N0 ) ; if ( N0 . hasOneUse ( ) && LogicOp0 . getOpcode ( ) == <STR_LIT> && LogicOp0 . hasOneUse ( ) && LogicOp0 . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT && ! isa < ConstantSDNode > ( LogicOp0 . getOperand ( <NUM_LIT> ) ) ) { SDValue CastedOp1 = DAG . getBitcast ( VT , LogicOp1 ) ; return DAG . getNode ( FPOpcode , DL0 , VT , LogicOp0 . getOperand ( <NUM_LIT> ) , CastedOp1 ) ;


<s> return D ( op , MemR ( y , ys ) , MemR ( x , xs ) , R ( a ) ) ;


<s> BuildMI ( MBB , MI , DL , TII . get ( Opc ) ) . addReg ( Reg , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ) continue ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) , RC , TRI ) ; -- MI ; MI -> setFlag ( MachineInstr :: FrameSetup ) ; ++ MI ; } return true ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , InstrInfo ( ) , FrameLowering ( * this ) , TLInfo ( TM , * this ) , TSInfo ( ) {


<s> ++ CurEmitted ; for ( MachineInstr :: mop_iterator It = SU -> getInstr ( ) -> operands_begin ( ) , E = SU -> getInstr ( ) -> operands_end ( ) ; It != E ; ++ It ) { MachineOperand & MO = * It ; if ( MO . isReg ( ) && MO . getReg ( ) == AMDGPU :: ALU_LITERAL_X ) ++ CurEmitted ; } } } } else { ++ CurEmitted ;


<s> rotate_mode = QIshift ; break ; case HImode : rotate_mode = HIshift ; break ; case SImode : rotate_mode = SIshift ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ROTATERT : rotate_type = SHIFT_ASHIFT ; break ; case ROTATE : rotate_type = SHIFT_LSHIFTRT ; break ; default : gcc_unreachable ( ) ; } amount = INTVAL ( rotate_amount ) ; if ( amount < <NUM_LIT> ) amount = <NUM_LIT> ; if ( ( unsigned int ) amount > GET_MODE_BITSIZE ( mode ) ) amount = GET_MODE_BITSIZE ( mode ) ; if ( ( unsigned int ) amount > GET_MODE_BITSIZE ( mode ) / ( unsigned ) <NUM_LIT> ) { amount = GET_MODE_BITSIZE ( mode ) - amount ; rotate_type = ( rotate_type == SHIFT_ASHIFT ) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT ; } if ( ( mode == HImode && TARGET_H8300 && amount >= <NUM_LIT> ) || ( mode == HImode && TARGET_H8300H && amount >= <NUM_LIT> ) || ( mode == HImode && TARGET_H8300S && amount == <NUM_LIT> ) || ( mode == SImode && TARGET_H8300H && amount >= <NUM_LIT> ) || ( mode == SImode && TARGET_H8300S && amount >= <NUM_LIT> ) ) { switch ( mode ) { case HImode : insn_buf = <STR_LIT> ; output_asm_insn ( insn_buf , operands ) ; break ; case SImode : insn_buf = <STR_LIT> ; output_asm_insn ( insn_buf , operands ) ; break ; default : gcc_unreachable ( ) ; }

amount = GET_MODE_BITSIZE ( mode ) / <NUM_LIT> - amount ;


<s> void emitCommonSymbol ( MCSymbol * Symbol , uint64_t Size , unsigned ByteAlignment ) override {


<s> bool AMDGPUPassConfig :: addInstSelector ( ) { addPass ( createAMDGPUISelDag ( getAMDGPUTargetMachine ( ) ) ) ; addPass ( create<ISA_LIT>LowerI1CopiesPass ( ) ) ; return false ;


<s> InitGlobalBaseReg ( MF ) ; MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , MFE = MF . end ( ) ; MFI != MFE ; ++ MFI ) for ( MachineBasicBlock :: iterator I = MFI -> begin ( ) ; I != MFI -> end ( ) ; ++ I ) ReplaceUsesWithZeroReg ( MRI , * I ) ;


<s> bool <ISA_LIT>FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) { return false ; } unsigned CalleeFrameSize = <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ;


<s> const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( STI . isTargetNaCl ( ) ) return CSR_NaCl_SaveList ; const MCPhysReg * RegList = STI . isTargetDarwin ( ) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList ; const Function * F = MF -> getFunction ( ) ; if ( F -> getCallingConv ( ) == CallingConv :: GHC ) { return CSR_NoRegs_SaveList ; } else if ( F -> hasFnAttribute ( <STR_LIT> ) ) { if ( STI . isMClass ( ) ) { return CSR_AAPCS_SaveList ; } else if ( F -> getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ) { return CSR_FIQ_SaveList ; } else { return CSR_GenericInt_SaveList ; } } return RegList ;


<s> PrefixInfo ( ) : Active ( false ) , Predicated ( false ) {


<s> target_flag_set_p ( unsigned int mask ) : m_mask ( mask ) {


<s> unsigned ZeroReg = MRI -> createVirtualRegister ( RC ) ; unsigned InsertReg = MRI -> createVirtualRegister ( RC ) ; BuildMI ( MBB , FlagsDefMI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , ZeroReg ) ; BuildMI ( * ZExt -> getParent ( ) , ZExt , ZExt -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , InsertReg ) . addReg ( ZeroReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <STR_LIT> ) ; MRI -> replaceRegWith ( ZExt -> getOperand ( <NUM_LIT> ) . getReg ( ) , InsertReg ) ; ToErase . push_back ( ZExt ) ; }


<s> Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; Inst . addOperand ( MCOperand :: createImm ( Shift ) ) ; return Success ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>BEAsmBackend ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { return create<ISA_LIT>AsmBackend ( T , MRI , TT , CPU , false ) ;


<s> builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } if ( TARGET_FLOAT128_TYPE ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } builtin_define ( <STR_LIT> ) ; RS6000_CPU_CPP_ENDIAN_BUILTINS ( ) ; if ( TARGET_LONG_DOUBLE_128 ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; if ( TARGET_IEEEQUAD ) { builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ; } else builtin_define ( <STR_LIT> ) ; } switch ( TARGET_CMODEL ) { case CMODEL_MEDIUM : builtin_define ( <STR_LIT> ) ; break ; case CMODEL_LARGE : builtin_define ( <STR_LIT> ) ; break ; default : break ; } switch ( rs6000_current_abi ) { case ABI_V4 : builtin_define ( <STR_LIT> ) ; break ; case ABI_AIX : builtin_define ( <STR_LIT> ) ; builtin_define ( <STR_LIT> ) ;


<s> unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset &= ~ ( ( <NUM_LIT> << LogAlign ) - <NUM_LIT> ) ; BaseInsertOffset -= UPad ; BaseInsertOffset -= <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << <STR_LIT> << KnownBits << <STR_LIT> << UPad << '\n' ) ; if ( BaseInsertOffset >= BBInfo [ UserMBB -> getNumber ( ) + <NUM_LIT> ] . Offset ) BaseInsertOffset = BBInfo [ UserMBB -> getNumber ( ) + <NUM_LIT> ] . Offset - ( isThumb1 ? <NUM_LIT> : <NUM_LIT> ) ; unsigned EndInsertOffset = WorstCaseAlign ( BaseInsertOffset + <NUM_LIT> , LogAlign , KnownBits ) + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; MachineInstr * LastIT = <NUM_LIT> ; for ( unsigned Offset = UserOffset + TII -> GetInstSizeInBytes ( UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> GetInstSizeInBytes ( MI ) , MI = llvm :: next ( MI ) ) { if ( CPUIndex < NumCPUsers && CPUsers [ CPUIndex ] . MI == MI ) { CPUser & U = CPUsers [ CPUIndex ] ; if ( ! isOffsetInRange ( Offset , EndInsertOffset , U ) ) { BaseInsertOffset -= <NUM_LIT> << LogAlign ; EndInsertOffset -= <NUM_LIT> << LogAlign ; } EndInsertOffset = RoundUpToAlignment ( EndInsertOffset , <NUM_LIT> << getCPELogAlign ( U . CPEMI ) ) + U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; CPUIndex ++ ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) LastIT = MI ; } -- MI ; if ( LastIT ) { unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getITInstrPredicate ( MI , PredReg ) ; if ( CC != <STR_LIT> ) MI = LastIT ; }


<s> for ( MachineBasicBlock :: iterator UseI = Def ; UseI != BBEnd ; ++ UseI ) { AluInstCount += OccupiedDwords ( UseI ) ; if ( ! SubstituteKCacheBank ( UseI , KCacheBanks , false ) ) return false ; if ( AluInstCount >= TII -> getMaxAlusPerClause ( ) ) return false ; if ( UseI -> findRegisterUseOperandIdx ( MOI -> getReg ( ) ) ) LastUseCount = AluInstCount ; if ( UseI != Def && UseI -> findRegisterDefOperandIdx ( MOI -> getReg ( ) ) != - <NUM_LIT> ) break ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! MI . findRegisterDefOperand ( <STR_LIT> ) -> isDead ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; return false ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Op0 = getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( ! MI -> killsRegister ( <STR_LIT> + Op0 ) ) { duplicateToTop ( Op0 , getScratchReg ( ) , I ) ; } else { moveToTop ( Op0 , I ) ; } -- StackTop ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Op0 = getFPReg ( MI -> getOperand ( <NUM_LIT> ) ) ; ++ StackTop ; unsigned RegOnTop = getStackEntry ( <NUM_LIT> ) ; if ( ! MI -> killsRegister ( <STR_LIT> + Op0 ) ) { duplicateToTop ( Op0 , getScratchReg ( ) , I ) ; moveToTop ( RegOnTop , I ) ; } else if ( getSTReg ( Op0 ) != <STR_LIT> ) { moveToTop ( getStackEntry ( <NUM_LIT> ) , I ) ; moveToTop ( Op0 , I ) ; moveToTop ( RegOnTop , I ) ; } assert ( StackTop >= <NUM_LIT> && <STR_LIT> ) ; StackTop -= <NUM_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ; unsigned SrcReg = getFPReg ( MO1 ) ; const MachineOperand & MO0 = MI -> getOperand ( <NUM_LIT> ) ; unsigned DestReg = getFPReg ( MO0 ) ; if ( MI -> killsRegister ( <STR_LIT> + SrcReg ) ) { unsigned Slot = getSlot ( SrcReg ) ; assert ( Slot < <NUM_LIT> && DestReg < <NUM_LIT> && <STR_LIT> ) ; Stack [ Slot ] = DestReg ; RegMap [ DestReg ] = Slot ; } else { duplicateToTop ( SrcReg , DestReg , I ) ; } } break ; case TargetOpcode :: INLINEASM : { unsigned Kills = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) || Op . getReg ( ) < <STR_LIT> || Op . getReg ( ) > <STR_LIT> ) continue ; assert ( Op . isUse ( ) && <STR_LIT> ) ; unsigned FPReg = getFPReg ( Op ) ; Op . setReg ( getSTReg ( FPReg ) ) ; if ( Op . isKill ( ) ) Kills |= <NUM_LIT> << FPReg ; } MachineBasicBlock :: iterator InsertPt = MI ; while ( Kills ) { unsigned FPReg = CountTrailingZeros_32 ( Kills ) ; freeStackSlotAfter ( InsertPt , FPReg ) ; Kills &= ~ ( <NUM_LIT> << FPReg ) ; } return ; } case <STR_LIT> : case <STR_LIT> : unsigned FirstFPRegOp = ~ <NUM_LIT> , SecondFPRegOp = ~ <NUM_LIT> ; unsigned LiveMask = <NUM_LIT> ;


<s> bool <ISA_LIT>PeepholeSDWA :: isConvertibleToSDWA ( MachineInstr & MI , const GCNSubtarget & ST ) const { unsigned Opc = MI . getOpcode ( ) ; if ( TII -> isSDWA ( Opc ) ) return true ; if ( <STR_LIT> ( Opc ) == - <NUM_LIT> ) Opc = <STR_LIT> ( Opc ) ; if ( <STR_LIT> ( Opc ) == - <NUM_LIT> ) return false ; if ( ! ST . hasSDWAOmod ( ) && TII -> hasModifiersSet ( MI , <STR_LIT> :: omod ) ) return false ; if ( TII -> isVOPC ( Opc ) ) { if ( ! ST . hasSDWASdst ( ) ) { const MachineOperand * SDst = TII -> getNamedOperand ( MI , <STR_LIT> :: sdst ) ; if ( SDst && ( SDst -> getReg ( ) != <STR_LIT> && SDst -> getReg ( ) != <STR_LIT> ) ) return false ; } if ( ! ST . hasSDWAOutModsVOPC ( ) && ( TII -> hasModifiersSet ( MI , <STR_LIT> :: clamp ) || TII -> hasModifiersSet ( MI , <STR_LIT> :: omod ) ) ) return false ; } else if ( TII -> getNamedOperand ( MI , <STR_LIT> :: sdst ) || ! TII -> getNamedOperand ( MI , <STR_LIT> :: vdst ) ) { return false ; } if ( ! ST . hasSDWAMac ( ) && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return false ; if ( TII -> pseudoToMCOpcode ( Opc ) == - <NUM_LIT> ) return false ;


<s> ParamTypes . push_back ( ResultType ) ; ParamTypes . push_back ( DestTy ) ; Function * CVTAFunction = <STR_LIT> ( M , <STR_LIT> , ParamTypes ) ; CVTA = Builder . CreateCall ( CVTAFunction , CVTA , <STR_LIT> ) ; DestTy = PointerType :: get ( GVType -> getElementType ( ) , llvm :: ADDRESS_SPACE_GENERIC ) ; CVTA = Builder . CreateBitCast ( CVTA , DestTy , <STR_LIT> ) ; } else { SmallVector < Type * , <NUM_LIT> > ParamTypes ; ParamTypes . push_back ( PointerType :: get ( GVType -> getElementType ( ) , llvm :: ADDRESS_SPACE_GENERIC ) ) ; ParamTypes . push_back ( GVType ) ; Function * CVTAFunction = <STR_LIT> ( M , <STR_LIT> , ParamTypes ) ; CVTA = Builder . CreateCall ( CVTAFunction , GV , <STR_LIT> ) ; }


<s> } static const CostTblEntry < <STR_LIT> > SSE2CostTable [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> } , } ; if ( ST -> hasSSE2 ( ) ) { int Idx = CostTableLookup ( SSE2CostTable , ISD , LT . second ) ; if ( Idx != - <NUM_LIT> ) return LT . first * SSE2CostTable [ Idx ] . Cost ; } static const CostTblEntry < <STR_LIT> > AVX1CostTable [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX ( ) && ! ST -> hasAVX2 ( ) ) { EVT VT = LT . second ; if ( ISD == <STR_LIT> && ( VT == <STR_LIT> || VT == <STR_LIT> ) && Op2Info == TargetTransformInfo :: OK_NonUniformConstantValue ) ISD = <STR_LIT> ; int Idx = CostTableLookup ( AVX1CostTable , ISD , VT ) ; if ( Idx != - <NUM_LIT> ) return LT . first * AVX1CostTable [ Idx ] . Cost ; }

static const CostTblEntry < <STR_LIT> > CustomLowered [ ] = {


<s> EVT VT = TLI . getValueType ( DL , Arg . Ty ) ; MVT RegisterVT = TLI . getRegisterTypeForCallingConv ( F . getContext ( ) , F . getCallingConv ( ) , VT ) ; <STR_LIT> Flags = Arg . Flags ;

Flags . setOrigAlign ( TLI . getABIAlignmentForCallingConv ( Arg . Ty , DL ) ) ;


<s> return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> bool isImmXLenLI ( ) const { int64_t Imm ; <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) ) return false ; bool IsConstantImm = evaluateConstantImm ( getImm ( ) , Imm , VK ) ; if ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PCREL_LO ) return true ; return IsConstantImm && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None && ( isRV64 ( ) || ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) ) ;


<s> bool sh_symbian_dllexport_name_p ( const char * symbol ) {

return strncmp ( DLL_EXPORT_PREFIX , symbol , strlen ( DLL_EXPORT_PREFIX ) ) == <NUM_LIT> ;


<s> const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; MachineInstrBuilder MIB ; BuildMI ( MBB , MI , DL , get ( LoadImmOpc ) , Reg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ; if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ;

auto Flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ;


<s> int64_t Disp = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; Register OrigCmpVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OrigSwapVal = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register BitShift = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register NegBitShift = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t BitSize = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ; unsigned LOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , Disp ) ; unsigned CSOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , Disp ) ; assert ( LOpcode && CSOpcode && <STR_LIT> ) ; Register OrigOldVal = MRI . createVirtualRegister ( RC ) ; Register OldVal = MRI . createVirtualRegister ( RC ) ; Register CmpVal = MRI . createVirtualRegister ( RC ) ; Register SwapVal = MRI . createVirtualRegister ( RC ) ; Register StoreVal = MRI . createVirtualRegister ( RC ) ; Register RetryOldVal = MRI . createVirtualRegister ( RC ) ; Register RetryCmpVal = MRI . createVirtualRegister ( RC ) ; Register RetrySwapVal = MRI . createVirtualRegister ( RC ) ; MachineBasicBlock * StartMBB = MBB ; MachineBasicBlock * DoneMBB = splitBlockBefore ( MI , MBB ) ; MachineBasicBlock * LoopMBB = emitBlockAfter ( StartMBB ) ; MachineBasicBlock * SetMBB = emitBlockAfter ( LoopMBB ) ; MBB = StartMBB ; BuildMI ( MBB , DL , TII -> get ( LOpcode ) , OrigOldVal ) . add ( Base ) . addImm ( Disp ) . addReg ( <NUM_LIT> ) ; MBB -> addSuccessor ( LoopMBB ) ; MBB = LoopMBB ;

BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( OrigOldVal ) . addMBB ( StartMBB ) . addReg ( RetryOldVal ) . addMBB ( SetMBB ) ;


<s> return ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) ;


<s> } unsigned FirstRegIdx = SplitArgs . size ( ) ; for ( auto SplitVT : SplitVTs ) { Type * SplitTy = SplitVT . getTypeForEVT ( Ctx ) ; SplitArgs . push_back ( ArgInfo { MRI . createGenericVirtualRegister ( LLT { * SplitTy , DL } ) , SplitTy , OrigArg . Flags } ) ; } SmallVector < uint64_t , <NUM_LIT> > BitOffsets ; for ( auto Offset : Offsets ) BitOffsets . push_back ( Offset * <NUM_LIT> ) ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; for ( auto I = & SplitArgs [ FirstRegIdx ] ; I != SplitArgs . end ( ) ; ++ I ) SplitRegs . push_back ( I -> Reg ) ;

PerformArgSplit ( SplitRegs , BitOffsets ) ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TM ( TM ) , STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , OptForSize ( false ) , OptForMinSize ( false ) , AvailableFeatures ( ) {


<s> } case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_W_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRIN<ISA_LIT>C_VOID ( Op , DAG ) ; case <STR_LIT> : return lowerADDRSPACECAST ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return lowerTRAP ( Op , DAG ) ; case <STR_LIT> : return lowerDEBUGTRAP ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return splitUnaryVectorOp ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return lowerFMINNUM_FMAXNUM ( Op , DAG ) ; case <STR_LIT> : return splitTernaryVectorOp ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return splitBinaryVectorOp ( Op , DAG ) ;


<s> return CC_<ISA_LIT>_Kernel ; case CallingConv :: <ISA_LIT>_VS : case CallingConv :: <ISA_LIT>_GS : case CallingConv :: <ISA_LIT>_PS : case CallingConv :: <ISA_LIT>_CS : case CallingConv :: <ISA_LIT>_HS :


<s> else if ( ( ( regno == R_MDB || regno == R_MDC ) && rclass == FP_REGS ) || ( FP_REGISTER_P ( regno ) && ( rclass == MDB || rclass == MDC ) ) ) return GENERAL_REGS ; else if ( ( regno == R_MDB && rclass == MDC ) || ( rclass == MDB && regno == R_MDC ) ) return GENERAL_REGS ; return NO_REGS ;


<s> ChangeDebugLoc ( MF , DL , true ) ; EmitFunctBeginDI ( MF . getFunction ( ) ) ;


<s> for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( isSingleInputShuffleMask ( Mask ) ) { SDValue VPermMask [ <NUM_LIT> ] ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) VPermMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] , DL , <STR_LIT> ) ; if ( ! is128BitLaneCrossingShuffleMask ( <STR_LIT> , Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VPermMask ) ) ; if ( Subtarget -> hasAVX2 ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , VPermMask ) ) , V1 ) ;

return lowerVectorShuffleAsLanePermuteAndBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ;


<s> static bool hasPartialRegUpdate ( unsigned Opcode ) { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> char State = isEntry ? StateExact : StateWQM ; auto II = MBB . getFirstNonPHI ( ) , IE = MBB . end ( ) ; while ( II != IE ) { MachineInstr & MI = * II ; ++ II ; if ( MI . getDesc ( ) . TSFlags & ( <STR_LIT> | <STR_LIT> ) && ! MI . isBranch ( ) && ! MI . isTerminator ( ) ) continue ; if ( TargetInstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) ) { if ( MI . getNumExplicitOperands ( ) >= <NUM_LIT> ) { const MachineOperand & Op = MI . getOperand ( <NUM_LIT> ) ; if ( Op . isReg ( ) ) { if ( TRI -> isSGPRReg ( * MRI , Op . getReg ( ) ) ) { continue ; } } } } char Needs = <NUM_LIT> ; char OutNeeds = <NUM_LIT> ; auto InstrInfoIt = Instructions . find ( & MI ) ; if ( InstrInfoIt != Instructions . end ( ) ) { Needs = InstrInfoIt -> second . Needs ;

OutNeeds = InstrInfoIt -> second . OutNeeds ;


<s> auto * IntrI = dyn_cast < IntrinsicInst > ( BitCast -> getOperand ( <NUM_LIT> ) ) ; if ( ! IntrI || IntrI -> getIntrinsicID ( ) != <STR_LIT> ) return false ; if ( ! isa < UndefValue > ( IntrI -> getOperand ( <NUM_LIT> ) ) || ! cast < ConstantInt > ( IntrI -> getOperand ( <NUM_LIT> ) ) -> isZero ( ) ) return false ; auto * Load = dyn_cast < LoadInst > ( IntrI -> getOperand ( <NUM_LIT> ) ) ; if ( ! Load || ! Load -> isSimple ( ) ) return false ;

if ( Load -> getType ( ) != FixedPredType ) return false ;


<s> case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } SYSm &= <NUM_LIT> ; if ( Opcode == <STR_LIT> && FeatureBits [ <STR_LIT> ] ) { switch ( SYSm ) { case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } switch ( SYSm ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> :


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: hexagon , false > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> assert ( SrcPartials [ <NUM_LIT> ] . getBitWidth ( ) == NumElts && <STR_LIT> ) ; SDValue PartialBits = DAG . getConstant ( SrcPartials [ <NUM_LIT> ] , dl , MaskVT ) ; Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Mask , PartialBits ) ; return DAG . getSetCC ( dl , <STR_LIT> , Mask , PartialBits , <STR_LIT> ) ; } } } if ( SDValue V = combineScalarAndWithMaskSetcc ( N , DAG , Subtarget ) ) return V ; if ( SDValue R = combineBitOpWithMOVMSK ( N , DAG ) ) return R ; if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( SDValue R = combineCompareEqual ( N , DAG , DCI , Subtarget ) ) return R ; if ( SDValue FPLogic = convertIntLogicToFPLogic ( N , DAG , Subtarget ) ) return FPLogic ; if ( SDValue R = combineANDXORWithAllOnesIntoANDNP ( N , DAG ) ) return R ; if ( SDValue ShiftRight = combineAndMaskToShift ( N , DAG , Subtarget ) ) return ShiftRight ; if ( SDValue R = combineAndLoadToBZHI ( N , DAG , Subtarget ) ) return R ; if ( VT . isVector ( ) && ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } if ( ( VT . getScalarSizeInBits ( ) % <NUM_LIT> ) == <NUM_LIT> && N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { SDValue BitMask = N -> getOperand ( <NUM_LIT> ) ; SDValue SrcVec = N -> getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; EVT SrcVecVT = SrcVec . getValueType ( ) ; APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( VT == SrcVecVT . getScalarType ( ) && N -> getOperand ( <NUM_LIT> ) -> isOnlyUserOf ( SrcVec . getNode ( ) ) && getTargetConstantBitsFromNode ( BitMask , <NUM_LIT> , UndefElts , EltBits ) && llvm :: all_of ( EltBits , [ ] ( APInt M ) { return M . isNullValue ( ) || M . isAllOnesValue ( ) ; } ) ) { unsigned NumElts = SrcVecVT . getVectorNumElements ( ) ; unsigned Scale = SrcVecVT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned Idx = N -> getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ;

SmallVector < int , <NUM_LIT> > ShuffleMask ( NumElts * Scale , SM_SentinelUndef ) ;


<s> if ( get_attr_type ( insn ) == TYPE_LEA ) { rtx set = PATTERN ( insn ) ; if ( GET_CODE ( set ) == PARALLEL ) set = XVECEXP ( set , <NUM_LIT> , <NUM_LIT> ) ;

gcc_assert ( GET_CODE ( set ) == SET ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getMemBase ( ) ) ) ;


<s> MachineSDNode :: mmo_iterator MemRefs0 = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemRefs0 [ <NUM_LIT> ] = cast < MemSDNode > ( N1 ) -> getMemOperand ( ) ; SDValue Ops0 [ ] = { N2 , LD -> getBasePtr ( ) , LD -> getChain ( ) } ; SDNode * ResNode = CurDAG -> SelectNodeTo ( Op , Opc , VT , <STR_LIT> , <STR_LIT> , Ops0 , <NUM_LIT> ) ;

cast < MachineSDNode > ( ResNode ) -> setMemRefs ( MemRefs0 , MemRefs0 + <NUM_LIT> ) ;


<s> MachineFunctionProperties getRequiredProperties ( ) const override { return InstructionSelect :: getRequiredProperties ( ) . reset ( MachineFunctionProperties :: Property :: RegBankSelected ) ;


<s> static DecodeStatus DecodeLDSTPairInstruction ( llvm :: MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { DecodeStatus Result = MCDisassembler :: Success ; unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned SImm7 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned L = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned V = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Opc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Indexed = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Indexed && L == <NUM_LIT> ) { DecodeGPR64xspRegisterClass ( Inst , Rn , Address , Decoder ) ; } if ( L && Rt == Rt2 ) Result = MCDisassembler :: SoftFail ; if ( Indexed && V == <NUM_LIT> && Rn != <NUM_LIT> && ( Rt == Rn || Rt2 == Rn ) ) Result = MCDisassembler :: SoftFail ; if ( V ) { switch ( Opc ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : DecodeFPR32RegisterClass ( Inst , Rt , Address , Decoder ) ; DecodeFPR32RegisterClass ( Inst , Rt2 , Address , Decoder ) ; break ; case <NUM_LIT> : DecodeFPR64RegisterClass ( Inst , Rt , Address , Decoder ) ; DecodeFPR64RegisterClass ( Inst , Rt2 , Address , Decoder ) ; break ; case <NUM_LIT> : DecodeFPR128RegisterClass ( Inst , Rt , Address , Decoder ) ; DecodeFPR128RegisterClass ( Inst , Rt2 , Address , Decoder ) ; break ; } } else { switch ( Opc ) { default : return MCDisassembler :: Fail ; case <NUM_LIT> : DecodeGPR32RegisterClass ( Inst , Rt , Address , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rt2 , Address , Decoder ) ; break ; case <NUM_LIT> : assert ( L && <STR_LIT> ) ; DecodeGPR64RegisterClass ( Inst , Rt , Address , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rt2 , Address , Decoder ) ; break ; case <NUM_LIT> : DecodeGPR64RegisterClass ( Inst , Rt , Address , Decoder ) ; DecodeGPR64RegisterClass ( Inst , Rt2 , Address , Decoder ) ; break ; } } if ( Indexed && L == <NUM_LIT> ) { DecodeGPR64xspRegisterClass ( Inst , Rn , Address , Decoder ) ; } DecodeGPR64xspRegisterClass ( Inst , Rn , Address , Decoder ) ; Inst . addOperand ( MCOperand :: CreateImm ( SImm7 ) ) ; return Result ;


<s> const ConstantArray * InitList = dyn_cast < ConstantArray > ( GV -> getInitializer ( ) ) ;


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasStructRetAttr ( ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ;

<ISA_LIT>MachineFunctionInfo * <ISA_LIT>MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;


<s> return AAResultBase :: pointsToConstantMemory ( Loc , QInfo , OrLocal ) ;


<s> newname = alloca ( strlen ( DLL_EXPORT_PREFIX ) + strlen ( oldname ) + <NUM_LIT> ) ; sprintf ( newname , <STR_LIT> , DLL_EXPORT_PREFIX , oldname ) ; idp = get_identifier ( newname ) ; symref = gen_rtx_SYMBOL_REF ( Pmode , IDENTIFIER_POINTER ( idp ) ) ; SYMBOL_REF_DECL ( symref ) = decl ;

XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) = symref ;


<s> assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineFunction & MF = * Cond [ <NUM_LIT> ] . getParent ( ) -> getParent ( ) -> getParent ( ) ; auto & MRI = MF . getRegInfo ( ) ;

if ( Cond [ <NUM_LIT> ] . isReg ( ) && MRI . getRegClass ( Cond [ <NUM_LIT> ] . getReg ( ) ) == & <STR_LIT> ) return true ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < DataLayoutPass > ( ) ; AU . addPreserved ( <STR_LIT> ) ; AU . addPreserved < MachineFunctionAnalysis > ( ) ;


<s> return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> } else if ( Tok . is ( AsmToken :: Hash ) ) { Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( ParseImmediate ( ImmVal ) != MatchOperand_Success ) return MatchOperand_ParseFail ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! CE || CE -> getValue ( ) < <NUM_LIT> || ! Mapper . validImm ( CE -> getValue ( ) ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; return MatchOperand_Success ; } Error ( S , <STR_LIT> ) ;


<s> int64_t SplatImm = cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getSExtValue ( ) ; if ( ! isUInt < <NUM_LIT> > ( SplatImm ) ) return false ; SplatVal = CurDAG -> getTargetConstant ( SplatImm , SDLoc ( N ) , Subtarget -> getXLenVT ( ) ) ;


<s> if ( GET_CODE ( clobber ) != CLOBBER ) return false ; rtx dest = SET_DEST ( set ) ; rtx src = SET_SRC ( set ) ; rtx scratch = SET_DEST ( clobber ) ; if ( GET_CODE ( src ) != UNSPEC ) return false ; if ( XINT ( src , <NUM_LIT> ) == UNSPEC_SI_FROM_SF && GET_CODE ( dest ) == MEM && GET_MODE ( dest ) == SImode && GET_CODE ( scratch ) == SCRATCH && GET_MODE ( scratch ) == V4SFmode ) return true ; if ( XINT ( src , <NUM_LIT> ) == UNSPEC_SF_FROM_SI && GET_CODE ( dest ) == REG && GET_MODE ( dest ) == SFmode && GET_CODE ( scratch ) == SCRATCH && GET_MODE ( scratch ) == DImode ) return true ;


<s> return isROPI ( ) || ! isTargetELF ( ) ;


<s> static SDValue LowerFNEG ( SDValue Op , SelectionDAG & DAG , const <ISA_LIT>TargetLowering & TLI , bool is64Bit ) { if ( Op . getValueType ( ) == <STR_LIT> ) return LowerF64Op ( Op , DAG ) ; if ( Op . getValueType ( ) == <STR_LIT> ) return TLI . LowerF128Op ( Op , DAG , ( ( is64Bit ) ? <STR_LIT> : <STR_LIT> ) , <NUM_LIT> ) ;


<s> AsmPrinter :: EmitBasicBlockStart ( MBB ) ;


<s> initializeMVEGatherScatterLoweringPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> if ( RelocM == Reloc :: Static ) return false ;

return ! GV -> hasLocalLinkage ( ) && ! GV -> hasHiddenVisibility ( ) ;


<s> for ( unsigned i = <NUM_LIT> , e = CPEs . size ( ) ; i != e ; ++ i ) { if ( CPEs [ i ] . CPEMI == CPEMI ) continue ; if ( CPEs [ i ] . CPEMI == NULL ) continue ; if ( CPEIsInRange ( UserMI , UserOffset , CPEs [ i ] . CPEMI , U . MaxDisp , U . NegOk ) ) { DEBUG ( errs ( ) << <STR_LIT> << CPI << <STR_LIT> << CPEs [ i ] . CPI << <STR_LIT> ) ; U . CPEMI = CPEs [ i ] . CPEMI ; for ( unsigned j = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; j != e ; ++ j ) if ( UserMI -> getOperand ( j ) . isCPI ( ) ) {

UserMI -> getOperand ( j ) . setIndex ( CPEs [ i ] . CPI ) ;


<s> unsigned CCMask = Cond [ <NUM_LIT> ] . getImm ( ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ) . addMBB ( TBB ) ; ++ Count ; if ( FBB ) {

BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) {

if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ;


<s> OS . write ( ( uint8_t ) Byte & <NUM_LIT> ) ;


<s> void emitCommonSymbol ( MCSymbol * Symbol , uint64_t Size , unsigned ByteAlignment ) override {


<s> return __builtin_arm_crypto_sha256su0 ( __w0_3 , __w4_7 ) ;


<s> op2_hi_lo [ i ] = GEN_INT ( sub_value ) ; if ( code == AND && sub_value != - <NUM_LIT> && sub_value != <NUM_LIT> && ! and_operand ( op2_hi_lo [ i ] , SImode ) ) op2_hi_lo [ i ] = force_reg ( SImode , op2_hi_lo [ i ] ) ; } } } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { if ( ( code == IOR || code == XOR ) && GET_CODE ( op2_hi_lo [ i ] ) == CONST_INT && ! complement_final_p && ! complement_op1_p && ! complement_op2_p && ! logical_const_operand ( op2_hi_lo [ i ] , SImode ) ) { HOST_WIDE_INT value = INTVAL ( op2_hi_lo [ i ] ) ; HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C ( <NUM_LIT> ) ; HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C ( <NUM_LIT> ) ; rtx tmp = gen_reg_rtx ( SImode ) ; if ( ( hi_16bits & sign_bit ) != <NUM_LIT> ) hi_16bits |= upper_32bits ;

rs6000_split_logical_inner ( tmp , op1_hi_lo [ i ] , GEN_INT ( hi_16bits ) , code , SImode , false , false , false ) ;


<s> assert ( Kind == k_CondCode && <STR_LIT> ) ;


<s> Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; } bool IsFunction = MO . isGlobal ( ) && isa < Function > ( MO . getGlobal ( ) ) ; if ( TF & <STR_LIT> ) { if ( IsFunction ) { Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_LO8 , Expr , IsNegated , Ctx ) ; } else { Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8 , Expr , IsNegated , Ctx ) ; } } else if ( TF & <STR_LIT> ) { if ( IsFunction ) { Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM_HI8 , Expr , IsNegated , Ctx ) ; } else { Expr = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 , Expr , IsNegated , Ctx ) ; } } else if ( TF != <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> ) ;


<s> auto IsALoadChainInstr = [ ] ( Value * V ) -> bool { if ( isa < GetElementPtrInst > ( V ) || isa < BitCastInst > ( V ) || isa < LoadInst > ( V ) ) return true ; if ( auto * ASC = dyn_cast < AddrSpaceCastInst > ( V ) ) { if ( ASC -> getDestAddressSpace ( ) == ADDRESS_SPACE_PARAM ) return true ; } return false ; } ; while ( ! ValuesToCheck . empty ( ) ) { Value * V = ValuesToCheck . pop_back_val ( ) ; if ( ! IsALoadChainInstr ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Arg << <STR_LIT> << * V << <STR_LIT> ) ; ( void ) Arg ; return false ; } if ( ! isa < LoadInst > ( V ) ) llvm :: append_range ( ValuesToCheck , V -> users ( ) ) ; } return true ; } ; if ( llvm :: all_of ( Arg -> users ( ) , IsALoadChain ) ) { SmallVector < User * , <NUM_LIT> > UsersToUpdate ( Arg -> users ( ) ) ; Value * ArgInParamAS = new AddrSpaceCastInst ( Arg , PointerType :: get ( StructType , ADDRESS_SPACE_PARAM ) , Arg -> getName ( ) , FirstInst ) ; llvm :: for_each ( UsersToUpdate , [ ArgInParamAS ] ( Value * V ) { convertToParamAS ( V , ArgInParamAS ) ; } ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Arg << <STR_LIT> ) ; return ; } const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ; unsigned AS = DL . getAllocaAddrSpace ( ) ;

AllocaInst * AllocA = new AllocaInst ( StructType , AS , Arg -> getName ( ) , FirstInst ) ;


<s> const RegisterBankInfo * <ISA_LIT>Subtarget :: getRegBankInfo ( ) const { return RegBankInfo . get ( ) ;


<s> def_builtin ( <STR_LIT> , v2si_ftype_pushort_int , SPE_BUILTIN_EVLHHOSSPLAT ) ; def_builtin ( <STR_LIT> , v2si_ftype_pushort_int , SPE_BUILTIN_EVLHHOUSPLAT ) ; def_builtin ( <STR_LIT> , v2si_ftype_puint_int , SPE_BUILTIN_EVLWHE ) ; def_builtin ( <STR_LIT> , v2si_ftype_puint_int , SPE_BUILTIN_EVLWHOS ) ; def_builtin ( <STR_LIT> , v2si_ftype_puint_int , SPE_BUILTIN_EVLWHOU ) ; def_builtin ( <STR_LIT> , v2si_ftype_puint_int , SPE_BUILTIN_EVLWHSPLAT ) ; def_builtin ( <STR_LIT> , v2si_ftype_puint_int , SPE_BUILTIN_EVLWWSPLAT ) ; d = bdesc_spe_predicates ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_spe_predicates ) ; ++ i , d ++ ) { tree type ; HOST_WIDE_INT mask = d -> mask ; if ( ( mask & builtin_mask ) != mask ) { if ( TARGET_DEBUG_BUILTIN ) fprintf ( stderr , <STR_LIT> , d -> name ) ; continue ; } gcc_assert ( d -> icode != CODE_FOR_nothing ) ; switch ( insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ) { case V2SImode : type = int_ftype_int_v2si_v2si ; break ; case V2SFmode : type = int_ftype_int_v2sf_v2sf ; break ; default : gcc_unreachable ( ) ; } def_builtin ( d -> name , type , d -> code ) ; } d = bdesc_spe_evsel ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( bdesc_spe_evsel ) ; ++ i , d ++ ) { tree type ; HOST_WIDE_INT mask = d -> mask ; if ( ( mask & builtin_mask ) != mask ) { if ( TARGET_DEBUG_BUILTIN ) fprintf ( stderr , <STR_LIT> , d -> name ) ; continue ; } gcc_assert ( d -> icode != CODE_FOR_nothing ) ; switch ( insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ) { case V2SImode : type = v2si_ftype_4_v2si ; break ; case V2SFmode : type = v2sf_ftype_4_v2sf ;


<s> StringRef getPassName ( ) const override {


<s> vector_size = GET_MODE_SIZE ( vector_mode ) ; gcc_assert ( reg_size % vector_size == <NUM_LIT> ) ; nvectors = reg_size / vector_size ; gcc_assert ( POINTER_TYPE_P ( type ) ) ; elem_type = TREE_TYPE ( type ) ; if ( mem_mode == reg_mode ) nelems = vector_size * nvectors / int_size_in_bytes ( elem_type ) ;


<s> static void pa_output_function_prologue ( FILE * file ) { pa_output_function_label ( file ) ; remove_useless_addtr_insns ( <NUM_LIT> ) ;


<s> bool flatScratchIsPointer ( ) const { return getGeneration ( ) >= GFX9 ;


<s> ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregciv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregciv16qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x16_t ) __builtin_aarch64_get_qregciv16qi ( __o , <NUM_LIT> ) ; return ret ;


<s> else if ( RegClass == AMDGPU :: VSrc_64RegClassID ) RegClass = AMDGPU :: VReg_64RegClassID ; else return ; if ( fitsRegClass ( DAG , Operand , RegClass ) ) return ; if ( ! ScalarSlotUsed ) { ScalarSlotUsed = true ; return ; } SDNode * Node ; if ( isa < FrameIndexSDNode > ( Operand ) || isa < GlobalAddressSDNode > ( Operand ) ) {

unsigned Opcode = Operand . getValueType ( ) == <STR_LIT> ? AMDGPU :: S_MOV_B32 : AMDGPU :: S_MOV_B64 ;


<s> if ( ! Subtarget -> is64Bit ( ) ) { const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? ( const TargetRegisterClass * ) & <STR_LIT> : ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , CopyReg ) . addReg ( InputReg ) ; InputReg = CopyReg ;


<s> switch ( MatchResult ) { default : break ; case Match_Success : { if ( needsExpansion ( Inst ) ) { SmallVector < MCInst , <NUM_LIT> > Instructions ; expandInstruction ( Inst , IDLoc , Instructions ) ; for ( unsigned i = <NUM_LIT> ; i < Instructions . size ( ) ; i ++ ) { Out . EmitInstruction ( Instructions [ i ] , getSTI ( ) ) ; } } else { Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; } return false ; } case Match_MissingFeature : Error ( IDLoc , <STR_LIT> ) ; return true ; case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; }


<s> } if ( scratch != NO_REGS && ! reg_class_subset_p ( test , scratch ) ) return ( mn10300_register_move_cost ( VOIDmode , from , scratch ) + mn10300_register_move_cost ( VOIDmode , scratch , to ) ) ; if ( optimize_size ) { if ( from == to && ( to == ADDRESS_REGS || to == DATA_REGS ) ) return <NUM_LIT> ; if ( from == SP_REGS ) return ( to == ADDRESS_REGS ? <NUM_LIT> : <NUM_LIT> ) ; if ( TARGET_AM33 ) return <NUM_LIT> ; if ( to == SP_REGS ) return ( from == ADDRESS_REGS ? <NUM_LIT> : <NUM_LIT> ) ; if ( ( from == ADDRESS_REGS || from == DATA_REGS ) && ( to == ADDRESS_REGS || to == DATA_REGS ) ) return <NUM_LIT> ; if ( to == EXTENDED_REGS ) return ( to == from ? <NUM_LIT> : <NUM_LIT> ) ; return <NUM_LIT> ; } else { if ( to == FP_REGS ) return <NUM_LIT> ; if ( from == FP_REGS ) return <NUM_LIT> ;


<s> SanityCheckImplicitOperands ( MCI ) ; std :: bitset < <NUM_LIT> > Bits ( MCI . getOperand ( MCI . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ) ; return Bits ;


<s> case HImode : case DImode : case SFmode : case DFmode : if ( ! reload_in_progress && ! reload_completed && ! register_operand ( dest , mode ) && ! reg_or_0_operand ( src , mode ) ) src = copy_to_mode_reg ( mode , src ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const Triple & TT ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TT ( TT ) {


<s> ReplaceTXF ( I ) ; return ; } if ( Name == <STR_LIT> ) { ReplaceTexIntrinsic ( I , false , TexQSign , <STR_LIT> , <STR_LIT> ) ; return ; } if ( Name == <STR_LIT> ) { ReplaceTexIntrinsic ( I , false , TexSign , <STR_LIT> , <STR_LIT> ) ; return ; } if ( Name == <STR_LIT> ) { ReplaceTexIntrinsic ( I , false , TexSign , <STR_LIT> , <STR_LIT> ) ; return ; }


<s> static __inline float sh_media_FMAC_S ( float fg , float fh , float fq ) { return fg * fh + fq ;


<s> assert ( ( ! OptForMinSize || OptForSize ) && <STR_LIT> ) ; for ( SelectionDAG :: allnodes_iterator I = CurDAG -> allnodes_begin ( ) , E = CurDAG -> allnodes_end ( ) ; I != E ; ) { SDNode * N = & * I ++ ; if ( N -> getOpcode ( ) == <STR_LIT> && ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue Res = CurDAG -> getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; -- I ; CurDAG -> ReplaceAllUsesOfValueWith ( SDValue ( N , <NUM_LIT> ) , Res ) ; ++ I ; CurDAG -> DeleteNode ( N ) ; } if ( OptLevel != CodeGenOpt :: None && ! Subtarget -> useRetpoline ( ) && ( ( N -> getOpcode ( ) == <STR_LIT> && ! Subtarget -> slowTwoMemOps ( ) ) || ( N -> getOpcode ( ) == <STR_LIT> && ( Subtarget -> is64Bit ( ) || ! getTargetMachine ( ) . isPositionIndependent ( ) ) ) ) ) { bool HasCallSeq = N -> getOpcode ( ) == <STR_LIT> ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Load = N -> getOperand ( <NUM_LIT> ) ; if ( ! isCalleeLoad ( Load , Chain , HasCallSeq ) ) continue ; moveBelowOrigChain ( CurDAG , Load , SDValue ( N , <NUM_LIT> ) , Chain ) ; ++ NumLoadMoved ; continue ; } if ( N -> getOpcode ( ) != <STR_LIT> && N -> getOpcode ( ) != <STR_LIT> ) continue ; MVT SrcVT = N -> getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) ; MVT DstVT = N -> getSimpleValueType ( <NUM_LIT> ) ; if ( SrcVT . isVector ( ) || DstVT . isVector ( ) ) continue ; const <ISA_LIT>TargetLowering * <ISA_LIT>Lowering = static_cast < const <ISA_LIT>TargetLowering * > ( TLI ) ; bool SrcIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( SrcVT ) ; bool DstIsSSE = <ISA_LIT>Lowering -> isScalarFPTypeInSSEReg ( DstVT ) ; if ( SrcIsSSE && DstIsSSE ) continue ;


<s> if ( ( Val >> ByteNum ) & <NUM_LIT> ) DecodedVal |= ( uint64_t ) <NUM_LIT> << ( <NUM_LIT> * ByteNum ) ; } EltBits = <NUM_LIT> ; } else if ( ( OpCmode & <NUM_LIT> ) == <NUM_LIT> ) { EltBits = <NUM_LIT> ; } else if ( ( OpCmode & <NUM_LIT> ) == <NUM_LIT> ) { EltBits = <NUM_LIT> ; } else if ( ( OpCmode & <NUM_LIT> ) == <NUM_LIT> ) {


<s> while ( lastpos < LINELEN - <NUM_LIT> && ( isalnum ( linebuf [ lastpos + <NUM_LIT> ] ) || linebuf [ lastpos + <NUM_LIT> ] == '_' ) ) ++ lastpos ; if ( lastpos >= LINELEN - <NUM_LIT> ) { diag ( lastpos , <STR_LIT> ) ; exit ( <NUM_LIT> ) ; } if ( lastpos < pos ) return <NUM_LIT> ;

char * buf = ( char * ) malloc ( lastpos - pos + <NUM_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> , TT , CPU , FS , Options , getEffectiveRelocModel ( RM , TT ) , getEffectiveCodeModel ( CM , CodeModel :: Large ) , OL ) , TLOF ( new <ISA_LIT>TargetObjectFile ( ) ) { this -> Options . TrapUnreachable = true ; this -> Options . FunctionSections = true ; this -> Options . DataSections = true ; this -> Options . UniqueSectionNames = true ;


return ( __m128i ) __builtin_ia32_pmovzxbq128 ( ( __v16qi ) __X ) ;


<s> EVT OutVT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; for ( auto & Reg : Regs ) { Reg = getTargetVShiftNode ( <STR_LIT> , DL , <STR_LIT> , Reg , ShAmt , Subtarget , DAG ) ; Reg = getTargetVShiftNode ( <STR_LIT> , DL , <STR_LIT> , Reg , ShAmt , Subtarget , DAG ) ; } for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) / <NUM_LIT> ; i < e ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Regs [ i * <NUM_LIT> ] , Regs [ i * <NUM_LIT> + <NUM_LIT> ] ) ; if ( Regs . size ( ) > <NUM_LIT> ) { Regs . resize ( Regs . size ( ) / <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , OutVT , Regs ) ;


<s> MachineInstr * CurrentMI = & * MII ; if ( CurrentMI -> getOpcode ( ) == DupOpcode && CurrentMI -> getNumOperands ( ) == <NUM_LIT> && CurrentMI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && CurrentMI -> getOperand ( <NUM_LIT> ) . getImm ( ) == LaneNumber ) { * DestReg = CurrentMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return true ; } } return false ;


<s> fprintf ( file , <STR_LIT> ) ; if ( TARGET_LINK_STACK ) { char name [ <NUM_LIT> ] ; get_ppc476_thunk_name ( name ) ; fprintf ( file , <STR_LIT> , name ) ; fprintf ( file , <STR_LIT> , local_label_0 ) ; } else { fprintf ( file , <STR_LIT> , local_label_0 ) ; fprintf ( file , <STR_LIT> , local_label_0 ) ; } fprintf ( file , <STR_LIT> , lazy_ptr_name , local_label_0 ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , ( TARGET_64BIT ? <STR_LIT> : <STR_LIT> ) , lazy_ptr_name , local_label_0 ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> ) ; } else { fprintf ( file , <STR_LIT> ) ;


<s> const LLT SrcTy = MRI . getType ( SrcReg ) ; assert ( ! ( SrcTy == LLT :: scalar ( <NUM_LIT> ) && DstTy == LLT :: scalar ( <NUM_LIT> ) ) && <STR_LIT> ) ; assert ( ! ( SrcTy == LLT :: scalar ( <NUM_LIT> ) && DstTy == LLT :: scalar ( <NUM_LIT> ) ) && <STR_LIT> ) ; const static struct ZextEntry { LLT SrcTy ; LLT DstTy ; unsigned MovOp ; bool NeedSubregToReg ; } OpTable [ ] = { { LLT :: scalar ( <NUM_LIT> ) , LLT :: scalar ( <NUM_LIT> ) , <STR_LIT> , false } , { LLT :: scalar ( <NUM_LIT> ) , LLT :: scalar ( <NUM_LIT> ) , <STR_LIT> , true } , { LLT :: scalar ( <NUM_LIT> ) , LLT :: scalar ( <NUM_LIT> ) , <STR_LIT> , true } , { LLT :: scalar ( <NUM_LIT> ) , LLT :: scalar ( <NUM_LIT> ) , <NUM_LIT> , true } } ; auto ZextEntryIt = std :: find_if ( std :: begin ( OpTable ) , std :: end ( OpTable ) , [ SrcTy , DstTy ] ( const ZextEntry & El ) { return El . DstTy == DstTy && El . SrcTy == SrcTy ; } ) ; if ( ZextEntryIt != std :: end ( OpTable ) ) { const RegisterBank & DstRB = * RBI . getRegBank ( DstReg , MRI , TRI ) ; const RegisterBank & SrcRB = * RBI . getRegBank ( SrcReg , MRI , TRI ) ; const TargetRegisterClass * DstRC = getRegClass ( DstTy , DstRB ) ; const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcRB ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; } unsigned TransitRegTo = DstReg ; unsigned TransitRegFrom = SrcReg ; if ( ZextEntryIt -> MovOp ) { if ( ZextEntryIt -> NeedSubregToReg ) { TransitRegFrom = MRI . createVirtualRegister ( getRegClass ( LLT :: scalar ( <NUM_LIT> ) , DstReg , MRI ) ) ;


<s> if ( TARGET_LONG_DOUBLE_128 ) { if ( ! TARGET_IEEEQUAD ) init_float128_ibm ( TFmode ) ;


<s> for ( MachineOperand & Op : MI . explicit_uses ( ) ) { if ( ! Op . isImm ( ) && ! ( Op . isReg ( ) && ! TRI -> isVGPR ( * MRI , Op . getReg ( ) ) ) ) continue ; unsigned I = MI . getOperandNo ( & Op ) ; if ( Desc . OpInfo [ I ] . RegClass == - <NUM_LIT> || ! TRI -> isVGPRClass ( TRI -> getRegClass ( Desc . OpInfo [ I ] . RegClass ) ) ) continue ; if ( ST . hasSDWAScalar ( ) && ConstantBusCount == <NUM_LIT> && Op . isReg ( ) && TRI -> isSGPRReg ( * MRI , Op . getReg ( ) ) ) { ++ ConstantBusCount ; continue ; } Register VGPR = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto Copy = BuildMI ( * MI . getParent ( ) , MI . getIterator ( ) , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , VGPR ) ; if ( Op . isImm ( ) ) Copy . addImm ( Op . getImm ( ) ) ;

else if ( Op . isReg ( ) ) Copy . addReg ( Op . getReg ( ) , Op . isKill ( ) ? RegState :: Kill : <NUM_LIT> , Op . getSubReg ( ) ) ;


return Kind == KindTy :: Register && Reg . RegNum == <STR_LIT> ;


<s> return getGeneration ( ) != <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ;


<s> explicit Thumb1FrameLowering ( const <ISA_LIT>Subtarget & sti ) : <ISA_LIT>FrameLowering ( sti ) {


<s> fprintf ( asm_out_file , <STR_LIT> ) ; } for ( i = <NUM_LIT> ; i < NDS32_N_ISR_VECTORS ; i ++ ) { if ( nds32_isr_vectors [ i ] . category == NDS32_ISR_INTERRUPT || nds32_isr_vectors [ i ] . category == NDS32_ISR_EXCEPTION ) { fprintf ( asm_out_file , <STR_LIT> , i ) ; fprintf ( asm_out_file , <STR_LIT> ) ; nds32_emit_isr_jmptbl_section ( i ) ; fprintf ( asm_out_file , <STR_LIT> ) ;


<s> C .* ptr &= ( T ) ~ Mask ; C .* ptr |= ( T ) ( ( Value << shift ) & Mask ) ;


<s> const auto & TII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; for ( auto & MBB : MF ) { if ( ! MBB . isEHPad ( ) ) continue ; auto InsertPos = MBB . begin ( ) ; while ( InsertPos != MBB . end ( ) && InsertPos -> isEHLabel ( ) ) InsertPos ++ ; if ( InsertPos == MBB . end ( ) || ! <STR_LIT> ( InsertPos -> getOpcode ( ) ) ) { Changed = true ; BuildMI ( MBB , InsertPos , InsertPos == MBB . end ( ) ? DebugLoc ( ) : InsertPos -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) ; } } return Changed ;


<s> if ( ! STI . hasFeature ( <STR_LIT> ) ) InstrWaitCntInfo [ Index ] . VmCnt = true ; else if ( MCID . mayLoad ( ) && ! ( MCID . TSFlags & <STR_LIT> ) ) InstrWaitCntInfo [ Index ] . VmCnt = true ; else InstrWaitCntInfo [ Index ] . VsCnt = true ; } else if ( isVMEM ( MCID ) && ! <STR_LIT> ( Opcode ) ) { if ( ! STI . hasFeature ( <STR_LIT> ) ) InstrWaitCntInfo [ Index ] . VmCnt = true ; else if ( ( MCID . mayLoad ( ) && ! ( MCID . TSFlags & <STR_LIT> ) ) || ( ( MCID . TSFlags & <STR_LIT> ) && ! MCID . mayLoad ( ) && ! MCID . mayStore ( ) ) ) InstrWaitCntInfo [ Index ] . VmCnt = true ; else if ( MCID . mayStore ( ) ) InstrWaitCntInfo [ Index ] . VsCnt = true ; if ( IV . Major < <NUM_LIT> && ( MCID . mayStore ( ) || ( MCID . TSFlags & <STR_LIT> ) ) ) InstrWaitCntInfo [ Index ] . ExpCnt = true ; } else if ( MCID . TSFlags & <STR_LIT> ) { InstrWaitCntInfo [ Index ] . LgkmCnt = true ; } else if ( MCID . TSFlags & <STR_LIT> ) { InstrWaitCntInfo [ Index ] . ExpCnt = true ; } else { switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> int <ISA_LIT>TTIImpl :: getInterleavedMemoryOpCost ( unsigned Opcode , Type * VecTy , unsigned Factor , ArrayRef < unsigned > Indices , unsigned Alignment , unsigned AddressSpace , bool UseMaskForCond , bool UseMaskForGaps ) { if ( UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , UseMaskForCond , UseMaskForGaps ) ; assert ( isa < VectorType > ( VecTy ) && <STR_LIT> ) ; auto ceil = [ ] ( unsigned A , unsigned B ) { return ( A + B - <NUM_LIT> ) / B ; } ; unsigned NumElts = VecTy -> getVectorNumElements ( ) ; assert ( Factor > <NUM_LIT> && NumElts % Factor == <NUM_LIT> && <STR_LIT> ) ; unsigned VF = NumElts / Factor ; unsigned NumEltsPerVecReg = ( <NUM_LIT> / getScalarSizeInBits ( VecTy ) ) ; unsigned NumVectorMemOps = getNumVectorRegs ( VecTy ) ; unsigned NumPermutes = <NUM_LIT> ; if ( Opcode == Instruction :: Load ) { BitVector UsedInsts ( NumVectorMemOps , false ) ; std :: vector < BitVector > ValueVecs ( Factor , BitVector ( NumVectorMemOps , false ) ) ; for ( unsigned Index : Indices ) for ( unsigned Elt = <NUM_LIT> ; Elt < VF ; ++ Elt ) { unsigned Vec = ( Index + Elt * Factor ) / NumEltsPerVecReg ; UsedInsts . set ( Vec ) ; ValueVecs [ Index ] . set ( Vec ) ; } NumVectorMemOps = UsedInsts . count ( ) ; for ( unsigned Index : Indices ) { unsigned NumSrcVecs = ValueVecs [ Index ] . count ( ) ; unsigned NumDstVecs = ceil ( VF * getScalarSizeInBits ( VecTy ) , <NUM_LIT> ) ;

assert ( NumSrcVecs >= NumDstVecs && <STR_LIT> ) ;


<s> if ( <ISA_LIT>CC == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <ISA_LIT>CC , <STR_LIT> ) , EFLAG ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> return V2HImode ; case QImode : return V4QImode ;


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , true , true , false ) ;


<s> static bool isShiftedMask ( uint64_t Mask , EVT VT ) {

assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ;


<s> SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( ! Subtarget . hasSSSE3 ( ) ) { assert ( VT . is128BitVector ( ) && <STR_LIT> ) ; return LowerVectorCTPOPBitmath ( Op0 , DL , Subtarget , DAG ) ; } if ( VT . is256BitVector ( ) && ! Subtarget . hasInt256 ( ) ) {

unsigned NumElems = VT . getVectorNumElements ( ) ;


<s> const AsmToken & Tok = getParser ( ) . getTok ( ) ; StartLoc = Tok . getLoc ( ) ; EndLoc = Tok . getEndLoc ( ) ; StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( matchRegisterNameHelper ( ( MCRegister & ) RegNo , Name ) ) return MatchOperand_NoMatch ;


<s> static StringRef computeDefaultCPU ( const Triple & TT , StringRef CPU ) { if ( CPU . empty ( ) && TT . getArchName ( ) == <STR_LIT> ) return <STR_LIT> ; return CPU ;


<s> inline bool vgpr_2reg_mode_p ( machine_mode mode ) { return ( mode == DImode || mode == DFmode || mode == V64DImode || mode == V64DFmode ) ;


<s> CallOpc = <STR_LIT> ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , PtrVT ) ; unsigned TOCSaveOffset = Subtarget . getFrameLowering ( ) -> getTOCSaveOffset ( ) ; SDValue TOCOff = DAG . getIntPtrConstant ( TOCSaveOffset , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StackPtr , TOCOff ) ; Ops . insert ( std :: next ( Ops . begin ( ) ) , AddTOC ) ; } else if ( CallOpc == <STR_LIT> && ! callsShareTOCBase ( MF . getFunction ( ) , Callee , DAG . getTarget ( ) ) ) { CallOpc = <STR_LIT> ; } } Chain = DAG . getNode ( CallOpc , dl , NodeTys , Ops ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , dl , true ) , DAG . getIntPtrConstant ( BytesCalleePops , dl , true ) , InFlag , dl ) ; if ( ! Ins . empty ( ) ) InFlag = Chain . getValue ( <NUM_LIT> ) ; return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , dl , DAG , InVals ) ;


<s> cfun -> machine -> next_fcc += - cfun -> machine -> next_fcc & ( count - <NUM_LIT> ) ; if ( cfun -> machine -> next_fcc > FCC_REG_LAST - FCC_REG_FIRST ) cfun -> machine -> next_fcc = <NUM_LIT> ; regno = FCC_REG_FIRST + cfun -> machine -> next_fcc ;


<s> void <ISA_LIT>IntelInstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned CallerCC = MF . getFunction ( ) -> getCallingConv ( ) ; if ( CalleeCC == CallingConv :: Fast && CallerCC == CalleeCC ) { for ( unsigned i = <NUM_LIT> ; i != Ins . size ( ) ; i ++ ) { <STR_LIT> Flags = Ins [ i ] . Flags ; if ( Flags . isByVal ( ) ) return false ; } if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return true ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) return G -> getGlobal ( ) -> hasHiddenVisibility ( ) || G -> getGlobal ( ) -> hasProtectedVisibility ( ) ; } return false ;


<s> __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv8hi ( __o , ( int16x8_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T , Triple :: OSType OST ) : MCAsmBackend ( <STR_LIT> ) , OSType ( OST ) {


<s> Dst |= ( Src << Shift ) & getBitMask ( Shift , Width ) ; return Dst ;


<s> static inline int shiftcosts ( rtx x ) { if ( GET_MODE_SIZE ( GET_MODE ( x ) ) > UNITS_PER_WORD ) { if ( GET_MODE ( x ) == DImode && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) && INTVAL ( XEXP ( x , <NUM_LIT> ) ) == <NUM_LIT> ) return <NUM_LIT> ; return - <NUM_LIT> ; } if ( ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) return SH_DYNAMIC_SHIFT_COST ; int value = INTVAL ( XEXP ( x , <NUM_LIT> ) ) & <NUM_LIT> ; if ( GET_CODE ( x ) == ASHIFTRT ) { int cost = ashiftrt_insns [ value ] ; if ( cost > <NUM_LIT> + SH_DYNAMIC_SHIFT_COST ) cost = <NUM_LIT> + SH_DYNAMIC_SHIFT_COST ; return cost ;


<s> Op = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( Subtarget . is64Bit ( ) ) BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( DispatchBB ) . addReg ( <NUM_LIT> ) ; else BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( DispatchBB , Subtarget . classifyBlockAddressReference ( ) ) . addReg ( <NUM_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , DL , TII -> get ( Op ) ) ; addFrameReference ( MIB , FI , <NUM_LIT> ) ; if ( UseImmLabel ) MIB . addMBB ( DispatchBB ) ; else MIB . addReg ( VR ) ;


<s> case Instruction :: Store : return <ISA_LIT>SelectStore ( I ) ; case Instruction :: Ret : return <ISA_LIT>SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return <ISA_LIT>SelectCmp ( I ) ; case Instruction :: ZExt : return <ISA_LIT>SelectZExt ( I ) ; case Instruction :: Br : return <ISA_LIT>SelectBranch ( I ) ; case Instruction :: Call : return <ISA_LIT>SelectCall ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return <ISA_LIT>SelectShift ( I ) ; case Instruction :: Select : return <ISA_LIT>SelectSelect ( I ) ; case Instruction :: Trunc : return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ;


<s> if ( V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Src = V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; if ( ! SrcVT . is512BitVector ( ) && ! Subtarget . hasVLX ( ) ) return SDValue ( ) ; if ( SrcVT . getVectorElementType ( ) == <STR_LIT> && VT == <STR_LIT> && ! Subtarget . hasBWI ( ) ) return SDValue ( ) ; if ( ! matchShuffleAsVPMOV ( Mask , SwappedOps , <NUM_LIT> ) && ! matchShuffleAsVPMOV ( Mask , SwappedOps , <NUM_LIT> ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Src ) ;


<s> int fromfloat = ( c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS || c1 == FPU_REGS ) ; int tofloat = ( c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS || c2 == FPU_REGS ) ; return ( fromfloat != tofloat ) ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseUNorm ( OperandVector & Operands ) { return parseNamedBit ( <STR_LIT> , Operands , <ISA_LIT>Operand :: ImmTyUNorm ) ;


<s> if ( GET_MODE_SIZE ( mode ) >= <NUM_LIT> ) return <NUM_LIT> ; if ( GET_CODE ( addr ) == SYMBOL_REF ) { tree decl = MEM_EXPR ( mem ) ; if ( decl && TREE_CODE ( decl ) == VAR_DECL && GET_MODE ( mem ) == TYPE_MODE ( TREE_TYPE ( decl ) ) ) return <NUM_LIT> ;


<s> } if ( MI . isPreISelOpcode ( ) || <ISA_LIT>InstrInfo :: isGenericOpcode ( MI . getOpcode ( ) ) || <ISA_LIT>InstrInfo :: isSALU ( MI ) || <ISA_LIT>InstrInfo :: isSMRD ( MI ) ) return false ;


<s> unsigned Reg = F128RegDecoderTable [ RegNo / <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> extern __inline __m128i __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_i64gather_epi64 ( long long int const * base , __m128i index , const int scale ) {


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = & <STR_LIT> ;

if ( ! isInt < <NUM_LIT> > ( MFI . estimateStackSize ( MF ) ) ) {


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; if ( Opc == <STR_LIT> ) { Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; } Ops . push_back ( Node -> getOperand ( <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ;

SDNode * ResNode = CurDAG -> getMachineNode ( Opc , SDLoc ( Node ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , Ops ) ;


return ( uint8x8_t ) ( __a < <NUM_LIT> ) ;


<s> MCSymbol * Func = getParser ( ) . getContext ( ) . getOrCreateSymbol ( Parser . getTok ( ) . getIdentifier ( ) ) ; getParser ( ) . getStreamer ( ) . EmitThumbFunc ( Func ) ; Parser . Lex ( ) ;

if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ;


<s> bool isPKHASRImm ( ) const { if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ;


<s> void <ISA_LIT>AsmParser :: setFpFormat ( StringRef Format ) {

FpFormat = StringSwitch < FpFormatTy > ( Format . lower ( ) ) . Case ( <STR_LIT> , FP_FORMAT_S ) . Case ( <STR_LIT> , FP_FORMAT_D ) . Case ( <STR_LIT> , FP_FORMAT_L ) . Case ( <STR_LIT> , FP_FORMAT_W ) . Default ( FP_FORMAT_NONE ) ;


<s> case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combine<ISA_LIT>INT_TO_FP ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineCVTP2I_CVTTP2I ( N , DAG , DCI ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineExtInVec ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftVar ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> limitOccupancy ( ST . getOccupancyWithLocalMemSize ( getLDSSize ( ) , MF . getFunction ( ) ) ) ;


<s> continue ; } while ( std :: next ( I ) != MBB . end ( ) ) { std :: next ( I ) -> eraseFromParent ( ) ; } Cond . clear ( ) ; FBB = nullptr ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = nullptr ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = getOppositeCondition ( BranchCode ) ; unsigned JNCC = getBrCond ( BranchCode ) . getOpcode ( ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ;


<s> return legalizeLoadStore ( MI , MRI , MIRBuilder , Observer ) ; case TargetOpcode :: G_SHL : case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : return legalizeShlAshrLshr ( MI , MRI , MIRBuilder , Observer ) ; case TargetOpcode :: G_GLOBAL_VALUE : return legalizeSmallCMGlobalValue ( MI , MRI , MIRBuilder , Observer ) ; case TargetOpcode :: G_TRUNC : return legalizeVectorTrunc ( MI , Helper ) ; case TargetOpcode :: G_SBFX : case TargetOpcode :: G_UBFX : return legalizeBitfieldExtract ( MI , MRI , Helper ) ; case TargetOpcode :: G_ROTR : return legalizeRotate ( MI , MRI , Helper ) ; case TargetOpcode :: G_CTPOP : return legalizeCTPOP ( MI , MRI , Helper ) ; case TargetOpcode :: G_ATOMIC_CMPXCHG : return legalizeAtomicCmpxchg128 ( MI , MRI , Helper ) ; case TargetOpcode :: G_CTTZ : return legalizeCTTZ ( MI , Helper ) ;


<s> auto * MD = getTargetStreamer ( ) -> getPALMetadata ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MD -> setFunctionScratchSize ( MF , MFI . getStackSize ( ) ) ;

MD -> setRsrc1 ( CallingConv :: <ISA_LIT>_CS , CurrentProgramInfo . getPGMRSrc1 ( CallingConv :: <ISA_LIT>_CS ) ) ;


<s> assert ( ( N -> getOpcode ( ) == <STR_LIT> || N -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . is128BitVector ( ) && ! VT . is256BitVector ( ) && ! VT . is512BitVector ( ) ) return SDValue ( ) ; APInt SplatVal ; if ( ! isConstantSplat ( N -> getOperand ( <NUM_LIT> ) , SplatVal ) || ! SplatVal . isOneValue ( ) ) return SDValue ( ) ; SDValue AllOnesVec = getOnesVector ( VT , DAG , SDLoc ( N ) ) ; unsigned NewOpcode = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ;

return DAG . getNode ( NewOpcode , SDLoc ( N ) , VT , N -> getOperand ( <NUM_LIT> ) , AllOnesVec ) ;


<s> SSEDomainFixPass ( ) : MachineFunctionPass ( & ID ) {


<s> if ( ( flags & VEC_ANY_SVE ) && costs -> sve ) return costs -> sve ;


<s> for ( const auto & I : B ) { if ( const auto * RetInst = dyn_cast_or_null < ReturnInst > ( & I ) ) { Type * NewRetTy = classifyPointerType ( RetInst -> getReturnValue ( ) ) ; if ( ! RetTy ) RetTy = NewRetTy ; else if ( RetTy != NewRetTy ) RetTy = TypedPointerType :: get ( Type :: getInt8Ty ( I . getContext ( ) ) , F . getReturnType ( ) -> getPointerAddressSpace ( ) ) ; } } } } for ( auto & A : F . args ( ) ) { Type * ArgTy = A . getType ( ) ; if ( ArgTy -> isOpaquePointerTy ( ) ) { TypedPointerType * NewTy = classifyPointerType ( & A ) ; Map [ & A ] = NewTy ; ArgTy = NewTy ;


<s> return DecodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getTheE<ISA_LIT>Target ( ) ) ;


<s> assert ( VT . isVector ( ) && <STR_LIT> ) ; SDValue EncodedVal = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ;

EVT VmovVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ;


<s> return __arm_vrmlaldavhxq_s32 ( __a , __b ) ;


<s> const std :: vector < MVT > & getLocals ( ) const { return Locals ;


<s> ELFAttributeValue * attr_value = NULL ; if ( pTag <= Tag_Max ) { attr_value = & m_Attrs [ pTag ] ; } else { attr_value = & m_UnknownAttrs [ pTag ] ; } assert ( attr_value != NULL ) ; if ( ! attr_value -> isUninitialized ( ) ) { return std :: make_pair ( attr_value , false ) ; } else { attr_value -> setType ( GetAttributeValueType ( pTag ) ) ; return std :: make_pair ( attr_value , true ) ;


<s> unsigned <ISA_LIT>TTI :: getNumberOfRegisters ( bool Vector ) const { if ( Vector && ! ST -> hasSSE1 ( ) ) return <NUM_LIT> ; if ( ST -> is64Bit ( ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> unsigned getBitMask ( unsigned Shift , unsigned Width ) { return ( ( <NUM_LIT> << Width ) - <NUM_LIT> ) << Shift ;


<s> default : break ; } mask = rs6000_emit_vector_compare ( rcode , cc_op0 , cc_op1 , mask_mode ) ; if ( ! mask ) return <NUM_LIT> ; if ( mask_mode != dest_mode ) mask = simplify_gen_subreg ( dest_mode , mask , mask_mode , <NUM_LIT> ) ; if ( invert_move ) std :: swap ( op_true , op_false ) ; if ( GET_MODE_CLASS ( dest_mode ) == MODE_VECTOR_INT && ( GET_CODE ( op_true ) == CONST_VECTOR || GET_CODE ( op_false ) == CONST_VECTOR ) ) { rtx constant_0 = CONST0_RTX ( dest_mode ) ; rtx constant_m1 = CONSTM1_RTX ( dest_mode ) ; if ( op_true == constant_m1 && op_false == constant_0 ) { emit_move_insn ( dest , mask ) ; return <NUM_LIT> ; } else if ( op_true == constant_0 && op_false == constant_m1 ) { emit_insn ( gen_rtx_SET ( dest , gen_rtx_NOT ( dest_mode , mask ) ) ) ; return <NUM_LIT> ; } if ( op_true == constant_m1 ) op_true = mask ; if ( op_false == constant_0 ) op_false = mask ; } if ( ! REG_P ( op_true ) && ! SUBREG_P ( op_true ) ) op_true = force_reg ( dest_mode , op_true ) ; if ( ! REG_P ( op_false ) && ! SUBREG_P ( op_false ) ) op_false = force_reg ( dest_mode , op_false ) ; rtx tmp = gen_rtx_IOR ( dest_mode , gen_rtx_AND ( dest_mode , gen_rtx_NOT ( dest_mode , mask ) , op_false ) , gen_rtx_AND ( dest_mode , mask , op_true ) ) ;

emit_insn ( gen_rtx_SET ( dest , tmp ) ) ;


<s> return AMDGPUTargetLowering :: EmitInstrWithCustomInserter ( MI , BB ) ; case AMDGPU :: BRANCH : return BB ; case AMDGPU :: V_SUB_F64 : { unsigned DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: V_ADD_F64 ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; MI -> eraseFromParent ( ) ; break ; } case AMDGPU :: <ISA_LIT>_RegisterStorePseudo : { MachineRegisterInfo & MRI = BB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & AMDGPU :: SReg_64RegClass ) ; MachineInstrBuilder MIB = BuildMI ( * BB , I , MI -> getDebugLoc ( ) , TII -> get ( AMDGPU :: <ISA_LIT>_RegisterStore ) , Reg ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) MIB . addOperand ( MI -> getOperand ( i ) ) ; MI -> eraseFromParent ( ) ; break ; } }


<s> SMLoc getStartLoc ( ) const override { return StartLoc ;