<s> default : if ( IsValidLdStrOpc ) * IsValidLdStrOpc = false ; return UINT_MAX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool nds32_expand_movmemsi ( rtx dstmem , rtx srcmem , rtx total_bytes , rtx alignment ) { if ( nds32_expand_movmemsi_unroll ( dstmem , srcmem , total_bytes , alignment ) ) return true ;

if ( ! optimize_size && optimize > <NUM_LIT> ) return nds32_expand_movmemsi_loop ( dstmem , srcmem , total_bytes , alignment ) ;


<s> void stackifyVReg ( MachineRegisterInfo & MRI , unsigned VReg ) { assert ( MRI . getUniqueVRegDef ( VReg ) ) ; auto I = Register :: virtReg2Index ( VReg ) ;

if ( I >= VRegStackified . size ( ) ) VRegStackified . resize ( I + <NUM_LIT> ) ;


<s> Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Address , ImmOperand , Base , Modifier , Offset , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , VTs , Ops ) ; MachineMemOperand * MemOp = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; CurDAG -> setNodeMemRefs ( cast < MachineSDNode > ( Result ) , { MemOp } ) ;


<s> BitVector Reserved = MRI . getReservedRegs ( ) ; BitVector CalleeSaved ( TRI -> getNumRegs ( ) ) ; const uint16_t * saved = TRI -> getCalleeSavedRegs ( & MF ) ; while ( * saved ) { CalleeSaved . set ( * saved ++ ) ; } for ( TargetRegisterClass :: iterator i = <STR_LIT> . begin ( ) , e = <STR_LIT> . end ( ) ; i != e ; ++ i ) { if ( MRI . isPhysRegUsed ( * i ) || * i == <STR_LIT> ) continue ; if ( Reserved [ * i ] || CalleeSaved [ * i ] ) continue ; SpillReg = * i ; break ; } if ( SpillReg ) { PMFI . setS0SpillReg ( SpillReg ) ; } } if ( TRI -> requiresRegisterScavenging ( MF ) ) { const TargetRegisterClass & RC = <STR_LIT> ;

int fi = MFI . CreateStackObject ( TRI -> getSpillSize ( RC ) , TRI -> getSpillAlign ( RC ) , false ) ;


<s> return ( opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> || opCode == <STR_LIT> ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AllocateStack ( ArgsPreserved , Align ( <NUM_LIT> ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , getParamCC ( CallConv , false ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( ! VA . needsCustom ( ) && <STR_LIT> ) ; if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ; case CCValAssign :: BCvt : { assert ( VA . getLocVT ( ) == <STR_LIT> ) ; assert ( VA . getValVT ( ) == <STR_LIT> ) ; SDValue Sub_f32 = DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; Arg = SDValue ( DAG . getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , Arg , Sub_f32 ) , <NUM_LIT> ) ; break ; } default : break ; } if ( VA . isExtInLoc ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Arg ) ; InVals . push_back ( Arg ) ; continue ; } assert ( VA . isMemLoc ( ) ) ; unsigned Offset = VA . getLocMemOffset ( ) + ArgsBaseOffset ; unsigned ValSize = VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( VA . getValVT ( ) == <STR_LIT> ) Offset += <NUM_LIT> ;

int FI = MF . getFrameInfo ( ) . CreateFixedObject ( ValSize , Offset , true ) ;


<s> bool ProcessMI ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MOVEMState & State , unsigned Mask , int Offset , unsigned Reg , bool IsStore = false ) { if ( State . hasBase ( ) ) { MOVEMState Temp = State ; if ( State . isStore ( ) == IsStore && State . getBase ( ) == Reg && State . update ( Offset , Mask ) ) {


<s> return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , getLoc ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ; auto Pred = Parser . getTok ( ) . getString ( ) . lower ( ) ; if ( Pred != <STR_LIT> && Pred != <STR_LIT> ) { Error ( getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } const char * ZM = Pred == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ZM , getLoc ( ) , getContext ( ) ) ) ;


<s> tree lhs = gimple_call_lhs ( call ) ; tree ref_to_res = gimple_call_arg ( call , <NUM_LIT> ) ; tree var = gimple_call_arg ( call , <NUM_LIT> ) ; int level = TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; enum tree_code op = ( enum tree_code ) TREE_INT_CST_LOW ( gimple_call_arg ( call , <NUM_LIT> ) ) ; gimple_seq seq = NULL ; tree r = NULL_TREE ; push_gimplify_context ( true ) ; if ( level == GOMP_DIM_VECTOR && oa -> vector_length == PTX_WARP_SIZE ) { for ( int shfl = PTX_WARP_SIZE / <NUM_LIT> ; shfl > <NUM_LIT> ; shfl = shfl >> <NUM_LIT> ) { tree other_var = make_ssa_name ( TREE_TYPE ( var ) ) ; nvptx_generate_vector_shuffle ( gimple_location ( call ) , other_var , var , shfl , & seq ) ; r = make_ssa_name ( TREE_TYPE ( var ) ) ; gimplify_assign ( r , fold_build2 ( op , TREE_TYPE ( var ) , var , other_var ) , & seq ) ; var = r ;


<s> if ( St -> isVolatile ( ) ) return SDValue ( ) ; SDValue StVal = St -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( St -> isTruncatingStore ( ) && VT . isVector ( ) ) { SelectionDAG & DAG = DCI . DAG ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; EVT StVT = St -> getMemoryVT ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; assert ( StVT != VT && <STR_LIT> ) ; unsigned FromEltSz = VT . getScalarSizeInBits ( ) ; unsigned ToEltSz = StVT . getScalarSizeInBits ( ) ; if ( ! isPowerOf2_32 ( NumElems * FromEltSz * ToEltSz ) ) return SDValue ( ) ; if ( <NUM_LIT> != ( NumElems * FromEltSz ) % ToEltSz ) return SDValue ( ) ; unsigned SizeRatio = FromEltSz / ToEltSz ; assert ( SizeRatio * NumElems * ToEltSz == VT . getSizeInBits ( ) ) ; EVT WideVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StVT . getScalarType ( ) , NumElems * SizeRatio ) ; assert ( WideVecVT . getSizeInBits ( ) == VT . getSizeInBits ( ) ) ; SDLoc DL ( St ) ; SDValue WideVec = DAG . getNode ( <STR_LIT> , DL , WideVecVT , StVal ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) ShuffleVec [ i ] = DAG . getDataLayout ( ) . isBigEndian ( ) ? ( i + <NUM_LIT> ) * SizeRatio - <NUM_LIT> : i * SizeRatio ; if ( ! TLI . isTypeLegal ( WideVecVT ) ) return SDValue ( ) ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , DL , WideVec , DAG . getUNDEF ( WideVec . getValueType ( ) ) , ShuffleVec ) ; MVT StoreType = <STR_LIT> ; for ( MVT Tp : <STR_LIT> ( ) ) { if ( TLI . isTypeLegal ( Tp ) && Tp . getSizeInBits ( ) <= NumElems * ToEltSz ) StoreType = Tp ; } if ( ! TLI . isTypeLegal ( StoreType ) ) return SDValue ( ) ;

EVT StoreVecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , StoreType , VT . getSizeInBits ( ) / EVT ( StoreType ) . getSizeInBits ( ) ) ;


<s> x = gen_rtx_VEC_CONCAT ( v2mode , op0 , op1 ) ; return mips_expand_vselect ( target , x , perm , nelt ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , MCInstrInfo const * MCII ) :

MCDisassembler ( STI , Ctx ) , MCII ( MCII ) , MRI ( * Ctx . getRegisterInfo ( ) ) {


<s> MCSectionData & ABIShndxSD = MCA . getOrCreateSectionData ( * Sec ) ; ABIShndxSD . setAlignment ( <NUM_LIT> ) ; OS . SwitchSection ( Sec ) ; OS << ABIFlagsSection ;


<s> void assignValueToReg ( Register ValVReg , Register PhysReg , CCValAssign VA ) override { switch ( VA . getLocVT ( ) . getSizeInBits ( ) ) {


<s> unsigned mask_fixed ; bool fixp_p = true ; rtx xop [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = op [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = op [ <NUM_LIT> ] ; xop [ <NUM_LIT> ] = op [ <NUM_LIT> ] ; gcc_assert ( REG_P ( xop [ <NUM_LIT> ] ) || CONST_INT_P ( xop [ <NUM_LIT> ] ) ) ; if ( plen ) * plen = <NUM_LIT> ; else if ( flag_print_asm_name ) fprintf ( asm_out_file , ASM_COMMENT_START <STR_LIT> , map ) ; mask_fixed = avr_map_metric ( map , MAP_MASK_FIXED_0_7 ) ; if ( REGNO ( xop [ <NUM_LIT> ] ) == REGNO ( xop [ <NUM_LIT> ] ) ) { avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; xop [ <NUM_LIT> ] = tmp_reg_rtx ; fixp_p = false ; } if ( avr_map_metric ( map , MAP_MASK_PREIMAGE_F ) ) { int n_fix = <NUM_LIT> , n_nofix = <NUM_LIT> ; gcc_assert ( REG_P ( xop [ <NUM_LIT> ] ) ) ; avr_move_bits ( xop , map , true , & n_fix ) ; avr_move_bits ( xop , map , false , & n_nofix ) ; if ( fixp_p && n_fix - n_nofix > <NUM_LIT> ) { xop [ <NUM_LIT> ] = gen_int_mode ( ~ mask_fixed , QImode ) ; avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> , xop , plen , <NUM_LIT> ) ; fixp_p = false ; } } else { if ( fixp_p && mask_fixed ) { avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; fixp_p = false ; } }

avr_move_bits ( xop , map , fixp_p , plen ) ;


<s> ModulePass * create<ISA_LIT>ClonerPass ( ) {


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } unsigned Opc = ( CallConv == CallingConv :: <ISA_LIT>_INTR ? <STR_LIT> : <STR_LIT> ) ; if ( Flag . getNode ( ) ) return DAG . getNode ( Opc , dl , <STR_LIT> , Chain , Flag ) ;

return DAG . getNode ( Opc , dl , <STR_LIT> , Chain ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>BranchTargetsPass ( ) { return new <ISA_LIT>BranchTargets ( ) ;


<s> case EQ : case NE : case GTU : case LTU : case GEU : case LEU : return <NUM_LIT> ; case GT : case LT : case GE : case LE :

return ! ( cc_prev_status . flags & CC_NO_OVERFLOW ) ;


<s> int size ; if ( type && TYPE_MODE ( type ) == BLKmode && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && ( size = int_size_in_bytes ( type ) ) > UNITS_PER_WORD && ( size % UNITS_PER_WORD != <NUM_LIT> ) && ( reg + mcore_num_arg_regs ( mode , type ) <= ( FIRST_PARM_REG + NPARM_REGS ) ) ) { rtx arg_regs [ NPARM_REGS ] ; int nregs ; rtx result ; rtvec rtvec ; for ( nregs = <NUM_LIT> ; size > <NUM_LIT> ; size -= UNITS_PER_WORD ) {

arg_regs [ nregs ] = gen_rtx_EXPR_LIST ( SImode , gen_rtx_REG ( SImode , reg ++ ) , GEN_INT ( nregs * UNITS_PER_WORD ) ) ;


<s> bool ix86_fp_jump_nontrivial_p ( enum rtx_code code ) { enum rtx_code bypass_code , first_code , second_code ; if ( ! TARGET_CMOVE ) return true ; ix86_fp_comparison_codes ( code , & bypass_code , & first_code , & second_code ) ;

return bypass_code != UNKNOWN || second_code != UNKNOWN ;


<s> return TM . getABIInfo ( ) . getABIType ( ) == <STR_LIT> ;


<s> uint64_t FrameSize = determineFrameLayout ( MF , UseEstimate , & NewMaxCallFrameSize ) ; MF . getFrameInfo ( ) . setStackSize ( FrameSize ) ;

MF . getFrameInfo ( ) . setMaxCallFrameSize ( NewMaxCallFrameSize ) ;


<s> return __builtin_mve_vctp16q_mhi ( __a , __p ) ;


<s> return ; if ( MBBI == MBB . end ( ) ) return ; MachineBasicBlock :: iterator NI = std :: next ( MBBI ) ; if ( NI == MBB . end ( ) ) return ; unsigned Opc = NI -> getOpcode ( ) ; if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && NI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { if ( NumBytes ) * NumBytes -= NI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( NI ) ; MBBI = NI ;

} else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && NI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) {


<s> MI -> eraseFromParent ( ) ; } for ( const auto & Pair : Info ) { auto TargetMBB = Pair . first ; const auto & Instrs = Pair . second . Instructions ; if ( Instrs . size ( ) < <NUM_LIT> ) continue ; Changed = true ; auto CommonDom = Instrs . front ( ) -> getParent ( ) ; for ( auto CurNextMI : drop_begin ( Instrs , <NUM_LIT> ) ) { assert ( CommonDom && <STR_LIT> ) ; assert ( CurNextMI -> getParent ( ) && <STR_LIT> ) ; CommonDom = MDT -> findNearestCommonDominator ( CommonDom , CurNextMI -> getParent ( ) ) ; } MachineInstr * FoundMI = nullptr ; for ( auto I = CommonDom -> instr_rbegin ( ) , E = CommonDom -> instr_rend ( ) ; I != E ; ++ I ) { MachineInstr & MI = * I ; if ( MI . getOpcode ( ) == <STR_LIT> && MI . getOperand ( <NUM_LIT> ) . getMBB ( ) == TargetMBB ) { FoundMI = & MI ;


<s> Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) << <STR_LIT> ; unsigned Pos = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( MCID . Opcode == <STR_LIT> || MCID . Opcode == <STR_LIT> ) Pos -= <NUM_LIT> ; assert ( ( Pos < <NUM_LIT> || ( Pos < <NUM_LIT> && MCID . Opcode != <STR_LIT> && MCID . Opcode != <STR_LIT> ) ) && <STR_LIT> ) ; Binary |= Pos << <NUM_LIT> ; Binary |= getMachineOpValue ( MI , <NUM_LIT> ) ; if ( MCID . getNumOperands ( ) == <NUM_LIT> ) { unsigned ShiftOp = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; <STR_LIT> Opc = <STR_LIT> ( ShiftOp ) ; if ( Opc == <STR_LIT> ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ; unsigned ShiftAmt = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ShiftAmt == <NUM_LIT> && Opc == <STR_LIT> ) ShiftAmt = <NUM_LIT> ;

assert ( ShiftAmt < <NUM_LIT> && <STR_LIT> ) ;


<s> MachineFunction :: iterator MBBI = OrigBB ; ++ MBBI ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewBB ) ; BlockInfo . insert ( BlockInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ; computeBlockSize ( * OrigBB ) ; computeBlockSize ( * NewBB ) ; adjustBlockOffsets ( * OrigBB ) ; ++ NumSplit ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < MachineBranchProbabilityInfo > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> if ( ST -> hasBranchPredictor ( ) && L -> getNumBlocks ( ) > <NUM_LIT> ) return ; if ( getBooleanLoopAttribute ( L , <STR_LIT> ) ) return ; unsigned Cost = <NUM_LIT> ; for ( auto * BB : L -> getBlocks ( ) ) { for ( auto & I : * BB ) { if ( I . getType ( ) -> isVectorTy ( ) ) return ; if ( isa < CallInst > ( I ) || isa < InvokeInst > ( I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( ! isLoweredToCall ( F ) ) continue ; } return ;


<s> inline static bool isOptSize ( const MachineFunction & MF ) { AttributeSet AF = MF . getFunction ( ) -> getAttributes ( ) ; return AF . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: OptimizeForSize ) ;


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; switch ( CM ) {


<s> PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugValue ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ; if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ; bool DoInsertAtI1 = false ; DbgMItoMove . clear ( ) ; MachineInstr * I2 = findPairable ( I1 , DoInsertAtI1 , OptForSize ) ; if ( I2 ) { HasChanged = true ; combine ( I1 , * I2 , MI , DoInsertAtI1 , OptForSize ) ; } } } return HasChanged ;


<s> explicit <ISA_LIT>TTIImpl ( const <ISA_LIT>TargetMachine * TM , const Function & F ) : BaseT ( TM , F . getParent ( ) -> getDataLayout ( ) ) , ST ( * TM -> getSubtargetImpl ( F ) ) , TLI ( * ST . getTargetLowering ( ) ) {


return ( __m512i ) __builtin_ia32_pternlogd512_mask ( ( __v16si ) __A , ( __v16si ) __B , ( __v16si ) __C , ( unsigned char ) __imm , ( __mmask16 ) - <NUM_LIT> ) ;


<s> enum attr_type type ; if ( LABEL_P ( insn ) ) arc_ccfsm_at_label ( <STR_LIT> , CODE_LABEL_NUMBER ( insn ) , state ) ;

else if ( JUMP_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && ( ( type = get_attr_type ( insn ) ) == TYPE_BRANCH || ( ( type == TYPE_UNCOND_BRANCH || type == TYPE_RETURN ) && ARC_CCFSM_BRANCH_DELETED_P ( state ) ) ) ) {


<s> bool isAligned = ( TM . getFrameLowering ( ) -> getStackAlignment ( ) >= Alignment ) || RI . canRealignStack ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ; DebugLoc DL = MBB . findDebugLoc ( MI ) ;

addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ;


<s> case TargetOpcode :: G_ADDRSPACE_CAST : return legalizeAddrSpaceCast ( MI , MRI , B ) ; case TargetOpcode :: G_FRINT : return legalizeFrint ( MI , MRI , B ) ; case TargetOpcode :: G_FCEIL : return legalizeFceil ( MI , MRI , B ) ; case TargetOpcode :: G_FREM : return legalizeFrem ( MI , MRI , B ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C_TRUNC : return legalizeIntrinsicTrunc ( MI , MRI , B ) ; case TargetOpcode :: G_<ISA_LIT>TOFP : return legalizeITOFP ( MI , MRI , B , true ) ; case TargetOpcode :: G_UITOFP : return legalizeITOFP ( MI , MRI , B , false ) ; case TargetOpcode :: G_FPTO<ISA_LIT> : return legalizeFPTOI ( MI , MRI , B , true ) ; case TargetOpcode :: G_FPTOUI : return legalizeFPTOI ( MI , MRI , B , false ) ; case TargetOpcode :: G_FMINNUM : case TargetOpcode :: G_FMAXNUM : case TargetOpcode :: G_FMINNUM_IEEE : case TargetOpcode :: G_FMAXNUM_IEEE : return legalizeMinNumMaxNum ( Helper , MI ) ; case TargetOpcode :: G_EXTRACT_VECTOR_ELT : return legalizeExtractVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_INSERT_VECTOR_ELT : return legalizeInsertVectorElt ( MI , MRI , B ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return legalizeShuffleVector ( MI , MRI , B ) ; case TargetOpcode :: G_F<ISA_LIT>N : case TargetOpcode :: G_FCOS : return legalizeSinCos ( MI , MRI , B ) ; case TargetOpcode :: G_GLOBAL_VALUE : return legalizeGlobalValue ( MI , MRI , B ) ; case TargetOpcode :: G_LOAD : case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : return legalizeLoad ( Helper , MI ) ; case TargetOpcode :: G_FMAD : return legalizeFMad ( MI , MRI , B ) ; case TargetOpcode :: G_FDIV : return legalizeFDIV ( MI , MRI , B ) ; case TargetOpcode :: G_UDIV : case TargetOpcode :: G_UREM : case TargetOpcode :: G_UDIVREM : return legalizeUnsignedDIV_REM ( MI , MRI , B ) ; case TargetOpcode :: G_SDIV : case TargetOpcode :: G_SREM : case TargetOpcode :: G_SDIVREM : return legalizeSignedDIV_REM ( MI , MRI , B ) ; case TargetOpcode :: G_ATOMIC_CMPXCHG : return legalizeAtomicCmpXChg ( MI , MRI , B ) ; case TargetOpcode :: G_FLOG : return legalizeFlog ( MI , B , numbers :: ln2f ) ; case TargetOpcode :: G_FLOG10 : return legalizeFlog ( MI , B , numbers :: ln2f / numbers :: ln10f ) ; case TargetOpcode :: G_FEXP : return legalizeFExp ( MI , B ) ; case TargetOpcode :: G_FPOW : return legalizeFPow ( MI , B ) ; case TargetOpcode :: G_FFLOOR : return legalizeFFloor ( MI , MRI , B ) ; case TargetOpcode :: G_BUILD_VECTOR :

return legalizeBuildVector ( MI , MRI , B ) ;


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , const Triple & TT , uint8_t OSABI , bool IsLittleEndian , bool IsILP32 ) : <ISA_LIT>AsmBackend ( T , TT , IsLittleEndian ) , OSABI ( OSABI ) , IsILP32 ( IsILP32 ) {


<s> for ( unsigned I = <NUM_LIT> ; I != MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; ++ I ) { unsigned TmpReg = MRI . createVirtualRegister ( isThumb1 ? & <STR_LIT> : & <STR_LIT> ) ; MIB . addReg ( TmpReg , RegState :: Define | RegState :: Dead ) ;


<s> __attribute__ ( ( __always_inline__ ) ) vrsqrte_f32 ( float32x2_t a ) { float32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ; return result ;


<s> MVT VT = A . getSimpleValueType ( ) ;

return DAG -> getNode ( <STR_LIT> , dl , VT , A , B ) ;


<s> static DecodeStatus DecodeDDRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Addr , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = DDDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ;


<s>
SmallSetVector
<
MachineBasicBlock
*
,
<NUM_LIT>
>
ElseBlocks
;
SmallVector
<
Register
>
CandidateRegs
;
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printMBBReference
(
MBB
)
<<
' '
<<
printMBBReference
(
*
IfTarget
)
<<
' '
<<
printMBBReference
(
*
Endif
)
<<
'\n'
)
;
collectElseRegionBlocks
(
IfTarget
,
Endif
,
ElseBlocks
)
;
collectCandidateRegisters
(
&
MBB
,
IfTarget
,
Endif
,
ElseBlocks
,
CandidateRegs
)
;
MadeChange
|=
!
CandidateRegs
.
empty
(
)
;
for
(
auto
Reg
:
CandidateRegs
)
optimizeLiveRange
(
Reg
,
&
MBB
,
IfTarget
,
Endif
,
ElseBlocks
)
;
}
else
if
(
MI
.
getOpcode
(
)
==
<STR_LIT>
)
{
auto
*
LoopHeader
=
MI
.
getOperand
(
<NUM_LIT>
)
.
getMBB
(
)
;
auto
*
LoopEnd
=
&
MBB
;
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
<<
printMBBReference
(
*
LoopHeader
)
<<
'\n'
)
;
SmallSetVector
<
Register
,
<NUM_LIT>
>
CandidateRegs
;
SmallVector
<
MachineInstr
*
,
<NUM_LIT>
>
Instructions
;
SmallSetVector
<
MachineBasicBlock
*
,
<NUM_LIT>
>
Blocks
;
collectWaterfallCandidateRegisters
(
LoopHeader
,
LoopEnd
,
CandidateRegs
,
Blocks
,
Instructions
)
;
MadeChange
|=
!
CandidateRegs
.
empty
(
)
;
for
(
auto
Reg
:
CandidateRegs
)
optimizeWaterfallLiveRange
(
Reg
,
LoopHeader
,
Blocks
,
Instructions
)
;
}
}
}


<s> OPCODE ( STRCMP ) ; OPCODE ( SEARCH_STRING ) ; OPCODE ( IPM ) ; OPCODE ( MEMBARRIER ) ; OPCODE ( TBEGIN ) ; OPCODE ( TBEGIN_NOFLOAT ) ; OPCODE ( TEND ) ; OPCODE ( BYTE_MASK ) ; OPCODE ( ROTATE_MASK ) ; OPCODE ( REPLICATE ) ; OPCODE ( JOIN_DWORDS ) ; OPCODE ( SPLAT ) ; OPCODE ( MERGE_HIGH ) ; OPCODE ( MERGE_LOW ) ; OPCODE ( SHL_DOUBLE ) ; OPCODE ( PERMUTE_DWORDS ) ; OPCODE ( PERMUTE ) ; OPCODE ( PACK ) ; OPCODE ( PACKS_CC ) ; OPCODE ( PACKLS_CC ) ; OPCODE ( UNPACK_HIGH ) ; OPCODE ( UNPACKL_HIGH ) ; OPCODE ( UNPACK_LOW ) ; OPCODE ( UNPACKL_LOW ) ; OPCODE ( VSHL_BY_SCALAR ) ; OPCODE ( VSRL_BY_SCALAR ) ; OPCODE ( VSRA_BY_SCALAR ) ; OPCODE ( VSUM ) ; OPCODE ( VICMPE ) ; OPCODE ( VICMPH ) ; OPCODE ( VICMPHL ) ; OPCODE ( VICMPES ) ; OPCODE ( VICMPHS ) ; OPCODE ( VICMPHLS ) ; OPCODE ( VFCMPE ) ; OPCODE ( STRICT_VFCMPE ) ; OPCODE ( STRICT_VFCMPES ) ; OPCODE ( VFCMPH ) ; OPCODE ( STRICT_VFCMPH ) ; OPCODE ( STRICT_VFCMPHS ) ; OPCODE ( VFCMPHE ) ; OPCODE ( STRICT_VFCMPHE ) ; OPCODE ( STRICT_VFCMPHES ) ; OPCODE ( VFCMPES ) ; OPCODE ( VFCMPHS ) ; OPCODE ( VFCMPHES ) ; OPCODE ( VFTCI ) ; OPCODE ( VEXTEND ) ; OPCODE ( STRICT_VEXTEND ) ; OPCODE ( VROUND ) ; OPCODE ( STRICT_VROUND ) ; OPCODE ( VTM ) ; OPCODE ( VFAE_CC ) ; OPCODE ( VFAEZ_CC ) ; OPCODE ( VFEE_CC ) ; OPCODE ( VFEEZ_CC ) ; OPCODE ( VFENE_CC ) ; OPCODE ( VFENEZ_CC ) ; OPCODE ( VISTR_CC ) ; OPCODE ( VSTRC_CC ) ; OPCODE ( VSTRCZ_CC ) ; OPCODE ( VSTRS_CC ) ; OPCODE ( VSTRSZ_CC ) ; OPCODE ( TDC ) ; OPCODE ( ATOMIC_SWAPW ) ; OPCODE ( ATOMIC_LOADW_ADD ) ; OPCODE ( ATOMIC_LOADW_SUB ) ; OPCODE ( ATOMIC_LOADW_AND ) ; OPCODE ( ATOMIC_LOADW_OR ) ; OPCODE ( ATOMIC_LOADW_XOR ) ; OPCODE ( ATOMIC_LOADW_NAND ) ; OPCODE ( ATOMIC_LOADW_MIN ) ; OPCODE ( ATOMIC_LOADW_MAX ) ; OPCODE ( ATOMIC_LOADW_UMIN ) ; OPCODE ( ATOMIC_LOADW_UMAX ) ; OPCODE ( ATOMIC_CMP_SWAPW ) ; OPCODE ( ATOMIC_CMP_SWAP ) ; OPCODE ( ATOMIC_LOAD_128 ) ; OPCODE ( ATOMIC_STORE_128 ) ; OPCODE ( ATOMIC_CMP_SWAP_128 ) ; OPCODE ( LRV ) ; OPCODE ( STRV ) ; OPCODE ( VLER ) ; OPCODE ( VSTER ) ;


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ;

if ( ( ( Subtarget -> hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget -> hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( LHS , RHS , false ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , LHS , RHS ) ;


<s> bool <ISA_LIT>InstrInfo :: hasLoadFromStackSlot ( const MachineInstr & MI , const MachineMemOperand * & MMO , int & FrameIndex ) const { if ( MI . isBundle ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; MachineBasicBlock :: const_instr_iterator MII = MI . getIterator ( ) ; for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) if ( TargetInstrInfo :: hasLoadFromStackSlot ( * MII , MMO , FrameIndex ) ) return true ; return false ; }

return TargetInstrInfo :: hasLoadFromStackSlot ( MI , MMO , FrameIndex ) ;


<s> if ( ( GET_CODE ( mem_src ) == ZERO_EXTEND ) || ( GET_CODE ( mem_src ) == SIGN_EXTEND ) ) mem_src = XEXP ( mem_src , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( mem_src , <NUM_LIT> ) ) == REG ) return true ;


<s> } count ++ ; break ; case <NUM_LIT> : if ( optimize_size ) goto generate_compact_code ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; sprintf ( buf , <STR_LIT> , count ) ; output_asm_insn ( buf , NULL ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( TARGET_45 ) { sprintf ( buf , <STR_LIT> , count ) ; output_asm_insn ( buf , operands ) ; } else { output_asm_insn ( <STR_LIT> , operands ) ; sprintf ( buf , <STR_LIT> , count ) ; output_asm_insn ( buf , NULL ) ; } count ++ ; break ; default : if ( optimize_size ) goto generate_compact_code ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; sprintf ( buf , <STR_LIT> , count ) ; output_asm_insn ( buf , NULL ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; if ( TARGET_45 ) { sprintf ( buf , <STR_LIT> , count ) ; output_asm_insn ( buf , operands ) ; } else { output_asm_insn ( <STR_LIT> , operands ) ;


<s> static void maybe_set_link_compat ( void ) {


<s> if ( Callee == nullptr ) return false ; BasicBlock * BB = CI -> getParent ( ) ; LLVMContext & Context = CI -> getParent ( ) -> getContext ( ) ; IRBuilder < > B ( Context ) ; B . SetInsertPoint ( BB , CI -> getIterator ( ) ) ; if ( const FPMathOperator * FPOp = dyn_cast < const FPMathOperator > ( CI ) ) B . setFastMathFlags ( FPOp -> getFastMathFlags ( ) ) ; switch ( Callee -> getIntrinsicID ( ) ) { default : break ; case <STR_LIT> : return ! EnablePreLink && fold_wavefrontsize ( CI , B ) ; } FuncInfo FInfo ; if ( ! parseFunctionName ( Callee -> getName ( ) , FInfo ) ) return false ; if ( CI -> arg_size ( ) != FInfo . getNumArgs ( ) ) return false ; if ( TDOFold ( CI , FInfo ) ) return true ; if ( isUnsafeMath ( CI ) && evaluateCall ( CI , FInfo ) ) return true ; switch ( FInfo . getId ( ) ) { case <ISA_LIT>LibFunc :: EI_RECIP : assert ( ( FInfo . getPrefix ( ) == <ISA_LIT>LibFunc :: NATIVE || FInfo . getPrefix ( ) == <ISA_LIT>LibFunc :: HALF ) && <STR_LIT> ) ; return ( getVecSize ( FInfo ) != <NUM_LIT> ) ? false : fold_recip ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc :: EI_DIVIDE : assert ( ( FInfo . getPrefix ( ) == <ISA_LIT>LibFunc :: NATIVE || FInfo . getPrefix ( ) == <ISA_LIT>LibFunc :: HALF ) && <STR_LIT> ) ; return ( getVecSize ( FInfo ) != <NUM_LIT> ) ? false : fold_divide ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc :: EI_POW : case <ISA_LIT>LibFunc :: EI_POWR : case <ISA_LIT>LibFunc :: EI_POWN : return fold_pow ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc :: EI_ROOTN : return ( getVecSize ( FInfo ) != <NUM_LIT> ) ? false : fold_rootn ( CI , B , FInfo ) ; case <ISA_LIT>LibFunc :: EI_FMA : case <ISA_LIT>LibFunc :: EI_MAD :


<s> if ( Subtarget -> isTargetDarwin ( ) ) return LowerDarwinGlobalTLSAddress ( Op , DAG ) ;

if ( Subtarget -> isTargetELF ( ) ) return LowerELFGlobalTLSAddress ( Op , DAG ) ;


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> if ( VT . getSizeInBits ( ) != <NUM_LIT> && VT . getSizeInBits ( ) != <NUM_LIT> ) return false ;

return TargetLowering :: allowsMemoryAccess ( Context , DL , VT , AddrSpace , Alignment , Flags , Fast ) ;


<s> enum machine_mode inner_mode = GET_MODE ( inner ) ; if ( inner_mode == mode ) return inner ; else if ( GET_MODE_SIZE ( inner_mode ) >= GET_MODE_SIZE ( mode ) ) x = inner ; else if ( GET_MODE_SIZE ( inner_mode ) < GET_MODE_SIZE ( mode ) && ( ! need_sign_ext || GET_CODE ( x ) == SIGN_EXTEND ) ) { code = GET_CODE ( x ) ; x = inner ; }


<s> static ReverseIter getNonDebugInstr ( ReverseIter B , const ReverseIter & E ) { for ( ; B != E ; ++ B ) if ( ! B -> isDebugValue ( ) ) return B ; return E ;


<s> case TargetOpcode :: G_FCOS : case TargetOpcode :: G_FSIN : case TargetOpcode :: G_FLOG10 : case TargetOpcode :: G_FLOG : case TargetOpcode :: G_FLOG2 : case TargetOpcode :: G_FSQRT : case TargetOpcode :: G_FABS : case TargetOpcode :: G_FEXP : case TargetOpcode :: G_FRINT : case TargetOpcode :: G_INTRINSIC_TRUNC : case TargetOpcode :: G_INTRINSIC_ROUND :


<s> SDValue <ISA_LIT>TargetLowering :: LowerUMUL_LOHI ( SDValue Op , SelectionDAG & DAG ) { assert ( Op . getValueType ( ) == <STR_LIT> && Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ;

SDValue Zero = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> { <STR_LIT> Isa = <STR_LIT> ( getSTI ( ) . getFeatureBits ( ) ) ; MCContext & Ctx = getContext ( ) ; MCSymbol * Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( Isa . Major , Ctx ) ) ; Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ; Sym -> setVariableValue ( MCConstantExpr :: create ( Isa . Minor , Ctx ) ) ; Sym = Ctx . getOrCreateSymbol ( Twine ( <STR_LIT> ) ) ;

Sym -> setVariableValue ( MCConstantExpr :: create ( Isa . Stepping , Ctx ) ) ;


<s> return isGFX11Plus ( STI ) ? ID_MASK_GFX11Plus_ : ID_MASK_PreGFX11_ ;


return lowerShuffleAsDecomposedShuffleMerge ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ;


<s> <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_ALTERA_NIOS2 , false ) {


<s> if ( FirstRegOp != SecondRegOp ) TOut . emitRRR ( <STR_LIT> , FirstRegOp , SecondRegOp , <STR_LIT> , IDLoc , STI ) ; else TOut . emitEmptyDelaySlot ( false , IDLoc , STI ) ; TOut . emitRRR ( <STR_LIT> , FirstRegOp , <STR_LIT> , SecondRegOp , IDLoc , STI ) ;


<s> static SDValue combineVectorInsert ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { assert ( ( ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) || ( N -> getOpcode ( ) == <STR_LIT> && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( { Op } , <NUM_LIT> , Op , { <NUM_LIT> } , { } , <NUM_LIT> , false , DAG , Subtarget ) ) return Res ; return SDValue ( ) ;


<s> if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> ) return Reg - <STR_LIT> + <STR_LIT> ; return Reg ;


<s> * Alias ; ++ Alias ) if ( RegSet . count ( * Alias ) ) return true ; return false ;


<s> for ( MachineBasicBlock :: iterator I = B . begin ( ) , E = B . end ( ) ; I != E ; ++ I ) { MachineInstr * MI = & * I ; I2X . insert ( std :: make_pair ( MI , Index ) ) ; Defs . reset ( ) ; Uses . reset ( ) ; getDefsUses ( MI , Defs , Uses ) ; DUM . insert ( std :: make_pair ( Index , DefUseInfo ( Defs , Uses ) ) ) ;


<s> SDLoc dl ( Op ) ; assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ; SDValue Tmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; if ( Op . getValueType ( ) == <STR_LIT> && hasHardQuad ) return TLI . LowerF128Op ( Op , DAG , TLI . getLibcallName ( RTLIB :: SINTTOFP_I32_F128 ) , <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Tmp ) ;


<s> WidenVector ( SelectionDAG & DAG ) : DAG ( DAG ) {


<s> MBB . erase ( MergeInstr ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { MIB . addOperand ( Reg0Op ) . addOperand ( Reg1Op ) . addReg ( BaseOp . getReg ( ) , RegState :: Define ) ; } else { assert ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) ; MIB . addReg ( BaseOp . getReg ( ) , RegState :: Define ) . addOperand ( Reg0Op ) . addOperand ( Reg1Op ) ; } MIB . addReg ( BaseOp . getReg ( ) , RegState :: Kill ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; assert ( TII -> get ( Opcode ) . getNumOperands ( ) == <NUM_LIT> && TII -> get ( NewOpc ) . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ;

for ( const MachineOperand & MO : MI . implicit_operands ( ) ) MIB . addOperand ( MO ) ;


<s> static void pm ( uint64_t & Value ) {


<s> return ( int8x8_t ) __builtin_neon_vraddhnv8hi ( __a , __b ) ;


<s> APFloat Zero = APFloat :: getZero ( F . getSemantics ( ) ) ; APFloat :: cmpResult Cmp0 = F . compare ( Zero ) ; if ( Cmp0 == APFloat :: cmpLessThan || ( Cmp0 == APFloat :: cmpUnordered && Subtarget -> enableDX10Clamp ( ) ) ) { return DCI . DAG . getConstantFP ( Zero , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) ) ; }

APFloat One ( F . getSemantics ( ) , <STR_LIT> ) ;


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ; bool IsN64 = TT . isArch64Bit ( ) && ! IsN32 ; bool HasRelocationAddend = TT . isArch64Bit ( ) ; auto * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI , HasRelocationAddend , IsN64 , TT . isLittleEndian ( ) ) ;

return createELFObjectWriter ( MOTW , OS , TT . isLittleEndian ( ) ) ;


<s> } else if ( ! is<ISA_LIT>LowRegister ( BaseReg ) || ( Entry . WideOpc != <STR_LIT> && Entry . WideOpc != <STR_LIT> ) ) { return false ; } isLdStMul = true ; break ; } } unsigned OffsetReg = <NUM_LIT> ; bool OffsetKill = false ; bool OffsetInternal = false ; if ( HasShift ) { OffsetReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; OffsetKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; OffsetInternal = MI -> getOperand ( <NUM_LIT> ) . isInternalRead ( ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) return false ; } unsigned OffsetImm = <NUM_LIT> ; if ( HasImmOffset ) { OffsetImm = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned MaxOffset = ( ( <NUM_LIT> << ImmLimit ) - <NUM_LIT> ) * Scale ; if ( ( OffsetImm & ( Scale - <NUM_LIT> ) ) || OffsetImm > MaxOffset ) return false ; } DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , TII -> get ( Opc ) ) ; if ( Entry . WideOpc == <STR_LIT> ) MIB . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: Define | RegState :: Dead ) ; if ( ! isLdStMul ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( HasImmOffset ) MIB . addImm ( OffsetImm / Scale ) ; assert ( ( ! HasShift || OffsetReg ) && <STR_LIT> ) ; if ( HasOffReg ) MIB . addReg ( OffsetReg , getKillRegState ( OffsetKill ) | getInternalReadRegState ( OffsetInternal ) ) ; } for ( unsigned e = MI -> getNumOperands ( ) ; OpNum != e ; ++ OpNum ) MIB . add ( MI -> getOperand ( OpNum ) ) ; MIB -> setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; MIB . setMIFlags ( MI -> getFlags ( ) ) ; LLVM_DEBUG ( errs ( ) << <STR_LIT> << * MI << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ;


<s> layout_type ( aarch64_bf16_type_node ) ;


<s> UP . Runtime = UP . Partial = true ; if ( L && L -> empty ( ) && canPeel ( L ) && SE . getSmallConstantTripCount ( L ) == <NUM_LIT> && SE . getSmallConstantMaxTripCount ( L ) > <NUM_LIT> && SE . getSmallConstantMaxTripCount ( L ) <= <NUM_LIT> ) { UP . PeelCount = <NUM_LIT> ;


<s> for ( unsigned int i = <NUM_LIT> ; i < TARGET_FPU_auto ; i ++ ) { arm_initialize_isa ( fpubits , all_fpus [ i ] . isa_bits ) ; bitmap_and_compl ( tmpset , isa_all_fpubits_internal , fpubits ) ; bitmap_clear ( isa_all_fpubits_internal ) ; bitmap_copy ( isa_all_fpubits_internal , tmpset ) ; } if ( ! bitmap_empty_p ( isa_all_fpubits_internal ) ) { fprintf ( stderr , <STR_LIT> <STR_LIT> <STR_LIT> ) ;


<s> break ; case <STR_LIT> : Scale = <NUM_LIT> ; break ; } if ( ( V & ( Scale - <NUM_LIT> ) ) != <NUM_LIT> ) return false ; V /= Scale ; return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; } if ( V < <NUM_LIT> ) V = - V ; switch ( VT . getSimpleVT ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; case <STR_LIT> : return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( ( V & <NUM_LIT> ) != <NUM_LIT> ) return false ; V >>= <NUM_LIT> ; return V == ( V & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ;


<s> SDValue MulOp1 = Mul . getOperand ( <NUM_LIT> ) ; SDValue OP0 ; SDValue OP1 ; if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext0 = MulOp0 . getOperand ( <NUM_LIT> ) ; if ( Sext0 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } OP0 = Sext0 ; } else if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp0 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDValue Chain = LD -> getChain ( ) ; SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; OP0 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LD -> getBasePtr ( ) , TargetConst0 , Chain ) , <NUM_LIT> ) ; } else { return SelectCode ( N ) ; } if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext1 = MulOp1 . getOperand ( <NUM_LIT> ) ;

if ( Sext1 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) return SelectCode ( N ) ;


<s> return __builtin_ia32_minph256_mask ( __A , __B , _mm256_setzero_ph ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> MachineBasicBlock :: iterator BeforeI = I ; if ( ! AtStart ) -- BeforeI ; if ( ! TFI -> restoreCalleeSavedRegisters ( * MBB , I , CSI , TRI ) ) { for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( * MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; assert ( I != MBB -> begin ( ) && <STR_LIT> ) ;


<s> return <ISA_LIT>SelectRet ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return <ISA_LIT>SelectCmp ( I ) ; case Instruction :: ZExt : return <ISA_LIT>SelectZExt ( I ) ; case Instruction :: Br : return <ISA_LIT>SelectBranch ( I ) ; case Instruction :: LShr : case Instruction :: AShr : case Instruction :: Shl : return <ISA_LIT>SelectShift ( I ) ; case Instruction :: SDiv : case Instruction :: UDiv : case Instruction :: SRem : case Instruction :: URem : return <ISA_LIT>SelectDivRem ( I ) ; case Instruction :: Select : return <ISA_LIT>SelectSelect ( I ) ; case Instruction :: Trunc : return <ISA_LIT>SelectTrunc ( I ) ; case Instruction :: FPExt : return <ISA_LIT>SelectFPExt ( I ) ; case Instruction :: FPTrunc : return <ISA_LIT>SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return <ISA_LIT>SelectSIToFP ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; EVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return <ISA_LIT>SelectTrunc ( I ) ; unsigned Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Reg == <NUM_LIT> ) return false ; updateValueMap ( I , Reg ) ; return true ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> break ; case BRIG_CONTROL_MAXFLATWORKGROUPSIZE : O << <STR_LIT> ; break ; case BRIG_CONTROL_REQUIREDDIM : O << <STR_LIT> ; break ; case BRIG_CONTROL_REQUIREDGRIDSIZE : O << <STR_LIT> ; break ; case BRIG_CONTROL_REQUIREDWORKGROUPSIZE : O << <STR_LIT> ; break ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MFI . hasVarSizedObjects ( ) ) { return - <NUM_LIT> ; } if ( MFI . getNumObjects ( ) == <NUM_LIT> ) { return - <NUM_LIT> ; } const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const <ISA_LIT>FrameLowering * TFL = ST . getFrameLowering ( ) ;


<s> unsigned IndexReg = Index . getReg ( ) ; if ( STI . hasFeature ( <STR_LIT> ) && BaseReg == <NUM_LIT> && IndexReg == <NUM_LIT> && Disp . isImm ( ) && Disp . getImm ( ) < <NUM_LIT> ) return true ;

if ( ( BaseReg != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg ) ) || ( IndexReg != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg ) ) ) return true ;


<s> unsigned <ISA_LIT>TTIImpl :: getHardwareNumberOfRegisters ( bool Vec ) const {


<s> return <ISA_LIT>ArchVersion >= <ISA_LIT>1 ;


<s> int AddressIdx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: address ) ; const MachineOperand & Base = MI -> getOperand ( AddressIdx + <STR_LIT> ) ; if ( Base . isFI ( ) ) { FrameIndex = Base . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } return <STR_LIT> ;


<s> static DecodeStatus DecodeZPRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = ZPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> void addCondCodeOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( unsigned ( getCondCode ( ) ) ) ) ; unsigned RegNum = getCondCode ( ) == <STR_LIT> ? <NUM_LIT> : <STR_LIT> ;

Inst . addOperand ( MCOperand :: CreateReg ( RegNum ) ) ;


<s> SDLoc dl ( Op ) ; assert ( Mask . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue IMask = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Mask ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ;

if ( PreservedSrc . isUndef ( ) ) PreservedSrc = getZeroVector ( VT , Subtarget , DAG , dl ) ;


<s> if ( DstSize == <NUM_LIT> && VecTy . getScalarSizeInBits ( ) == <NUM_LIT> ) Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstSize == <NUM_LIT> && VecTy . getScalarSizeInBits ( ) == <NUM_LIT> ) Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstSize == <NUM_LIT> && VecTy . getScalarSizeInBits ( ) == <NUM_LIT> ) Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstSize == <NUM_LIT> && VecTy . getScalarSizeInBits ( ) == <NUM_LIT> ) Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; else if ( DstSize == <NUM_LIT> && VecTy . getScalarSizeInBits ( ) == <NUM_LIT> ) Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; MachineInstr * ExtI = nullptr ; if ( DstSize == <NUM_LIT> && ! IsSigned ) { Register NewReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; MIB . buildInstr ( Opcode , { NewReg } , { Src0 } ) . addImm ( Lane ) ; ExtI = MIB . buildInstr ( <STR_LIT> , { DefReg } , { } ) . addImm ( <NUM_LIT> ) . addUse ( NewReg ) . addImm ( <STR_LIT> ) ; RBI . constrainGenericRegister ( DefReg , <STR_LIT> , MRI ) ; } else ExtI = MIB . buildInstr ( Opcode , { DefReg } , { Src0 } ) . addImm ( Lane ) ;

constrainSelectedInstRegOperands ( * ExtI , TII , TRI , RBI ) ;


<s> GCNTargetMachine :: GCNTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , TargetOptions Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) {


<s> if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( <STR_LIT> ) ; BuildMI ( MBB , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ;


<s> <ISA_LIT>ebTargetMachine :: <ISA_LIT>ebTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ;

BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , RestMBB ) ; RestMBB -> splice ( RestMBB -> begin ( ) , & MBB , MI , MBB . end ( ) ) ; RestMBB -> transferSuccessors ( & MBB ) ; for ( MCPhysReg R : LiveRegs ) RestMBB -> addLiveIn ( R ) ; MachineBasicBlock * MoveMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , MoveMBB ) ; MoveMBB -> addLiveIn ( SrcReg ) ; for ( MCPhysReg R : LiveRegs ) MoveMBB -> addLiveIn ( R ) ; BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ^ CCValid ) . addMBB ( RestMBB ) ; MBB . addSuccessor ( RestMBB ) ; MBB . addSuccessor ( MoveMBB ) ; BuildMI ( * MoveMBB , MoveMBB -> end ( ) , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , getRegState ( MI . getOperand ( <NUM_LIT> ) ) ) ;


<s> machine_mode mode ; if ( crtl -> return_rtx != <NUM_LIT> ) mode = GET_MODE ( crtl -> return_rtx ) ; else mode = DECL_MODE ( DECL_RESULT ( current_function_decl ) ) ;


<s> void printi128mem ( const MCInst * MI , unsigned OpNo ) {


<s> case <STR_LIT> : if ( ( Subtarget . hasSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasAVX ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; auto HorizOpcode = IsAdd ? <STR_LIT> : <STR_LIT> ; if ( isHorizontalBinOp ( HorizOpcode , LHS , RHS , DAG , Subtarget , IsAdd , PostShuffleMask ) ) { SDValue HorizBinOp = DAG . getNode ( HorizOpcode , SDLoc ( N ) , VT , LHS , RHS ) ; if ( ! PostShuffleMask . empty ( ) ) HorizBinOp = DAG . getVectorShuffle ( VT , SDLoc ( HorizBinOp ) , HorizBinOp , DAG . getUNDEF ( VT ) , PostShuffleMask ) ; return HorizBinOp ; } } break ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) { SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; auto HorizOpcode = IsAdd ? <STR_LIT> : <STR_LIT> ; if ( isHorizontalBinOp ( HorizOpcode , LHS , RHS , DAG , Subtarget , IsAdd , PostShuffleMask ) ) { auto HOpBuilder = [ HorizOpcode ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( HorizOpcode , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ; SDValue HorizBinOp = SplitOpsAndApply ( DAG , Subtarget , SDLoc ( N ) , VT , { LHS , RHS } , HOpBuilder ) ; if ( ! PostShuffleMask . empty ( ) ) HorizBinOp = DAG . getVectorShuffle ( VT , SDLoc ( HorizBinOp ) , HorizBinOp , DAG . getUNDEF ( VT ) , PostShuffleMask ) ; return HorizBinOp ;


<s> return ( vector unsigned int ) __builtin_altivec_vmrghw ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> <ISA_LIT>Subtarget & <ISA_LIT>Subtarget :: initializeSubtargetDependencies ( StringRef CPU , StringRef FS , const TargetMachine & TM ) { std :: string CPUName = select<ISA_LIT>CPU ( TargetTriple , CPU ) ; ParseSubtargetFeatures ( CPUName , FS ) ; InstrItins = getInstrItineraryForCPU ( CPUName ) ;

if ( In<ISA_LIT>16Mode && ! TM . Options . UseSoftFloat ) In<ISA_LIT>16HardFloat = true ;


<s> BasicBlock * OldExit = SubRegion -> getExit ( ) ; BasicBlock * Dominator = <NUM_LIT> ; for ( pred_iterator I = pred_begin ( OldExit ) , E = pred_end ( OldExit ) ; I != E ; ) { BasicBlock * BB = * I ++ ; if ( ! SubRegion -> contains ( BB ) ) continue ; delPhiValues ( BB , OldExit ) ; BB -> getTerminator ( ) -> replaceUsesOfWith ( OldExit , NewExit ) ; addPhiValues ( BB , NewExit ) ; if ( IncludeDominator ) { if ( ! Dominator ) Dominator = BB ; else Dominator = DT -> findNearestCommonDominator ( Dominator , BB ) ; }


<s> MemRefs . clear ( ) ; for ( auto & TS : TSE ) { MachineInstr * MI = TS . MI ; if ( MI -> memoperands_empty ( ) ) {


<s> if ( TREE_CODE ( type ) == VECTOR_TYPE ) { switch ( tree_to_uhwi ( TYPE_SIZE ( type ) ) ) { case <NUM_LIT> : return builtin_decl_explicit ( BUILT_IN_TM_STORE_M64 ) ; case <NUM_LIT> : return builtin_decl_explicit ( BUILT_IN_TM_STORE_M128 ) ; case <NUM_LIT> : return builtin_decl_explicit ( BUILT_IN_TM_STORE_M256 ) ; }


<s> void <ISA_LIT>MCAsmStreamer :: EmitCodeAlignment ( unsigned ByteAlignment , unsigned MaxBytesToEmit ) {


<s> return e . use_exact_insn ( CODE_FOR_aarch64_wrffr ) ;


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; unsigned Rn = CTX . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ;

uint32_t Binary = getAddrMode2OffsetOpValue ( MI , OpIdx + <NUM_LIT> , Fixups ) ;


<s> static unsigned findFirstFreeSGPR ( CCState & CCInfo ) { unsigned NumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned Reg = <NUM_LIT> ; Reg < NumSGPRs ; ++ Reg ) { if ( ! CCInfo . isAllocated ( <STR_LIT> + Reg ) ) { return <STR_LIT> + Reg ; } } llvm_unreachable ( <STR_LIT> ) ;


<s> const char * s390_host_detect_local_cpu ( int argc , const char * * argv ) { const char * cpu = NULL ; char buf [ <NUM_LIT> ] ; FILE * f ; bool arch ; const char * options = <STR_LIT> ; unsigned int has_features ; unsigned int has_processor ; unsigned int is_cpu_z9_109 = <NUM_LIT> ; unsigned int has_highgprs = <NUM_LIT> ; unsigned int has_dfp = <NUM_LIT> ; unsigned int has_te = <NUM_LIT> ; unsigned int has_vx = <NUM_LIT> ; unsigned int has_opt_esa_zarch = <NUM_LIT> ; int i ; if ( argc < <NUM_LIT> ) return NULL ; arch = strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) == <NUM_LIT> ; if ( ! arch && strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) ) return NULL ; for ( i = <NUM_LIT> ; i < argc ; i ++ ) if ( strcmp ( argv [ i ] , <STR_LIT> ) == <NUM_LIT> ) has_opt_esa_zarch = <NUM_LIT> ; f = fopen ( <STR_LIT> , <STR_LIT> ) ; if ( f == NULL ) return NULL ; for ( has_features = <NUM_LIT> , has_processor = <NUM_LIT> ; ( has_features == <NUM_LIT> || has_processor == <NUM_LIT> ) && fgets ( buf , sizeof ( buf ) , f ) != NULL ; ) { if ( has_processor == <NUM_LIT> && startswith ( buf , <STR_LIT> ) ) { const char * p ; long machine_id ; p = strstr ( buf , <STR_LIT> ) ; if ( p == NULL ) continue ; p += <NUM_LIT> ; has_processor = <NUM_LIT> ; machine_id = strtol ( p , NULL , <NUM_LIT> ) ; switch ( machine_id ) { case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; is_cpu_z9_109 = <NUM_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; default : cpu = <STR_LIT> ; break ;


<s> auto * Scatter = cast < MaskedScatterSDNode > ( GorS ) ; SDValue Ops [ ] = { Scatter -> getChain ( ) , Scatter -> getValue ( ) , Scatter -> getMask ( ) , Base , Index , Scale } ; return DAG . getMaskedScatter ( Scatter -> getVTList ( ) , Scatter -> getMemoryVT ( ) , DL , Ops , Scatter -> getMemOperand ( ) , Scatter -> getIndexType ( ) , Scatter -> isTruncatingStore ( ) ) ;


<s> SDValue EltNo = N -> getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( EltNo ) ) return SDValue ( ) ; EVT OriginalVT = InVec . getValueType ( ) ; if ( InVec . getOpcode ( ) == <STR_LIT> ) { if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; EVT BCVT = InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( BCVT . getVectorNumElements ( ) != OriginalVT . getVectorNumElements ( ) ) return SDValue ( ) ; InVec = InVec . getOperand ( <NUM_LIT> ) ; } EVT CurrentVT = InVec . getValueType ( ) ; if ( ! isTargetShuffle ( InVec . getOpcode ( ) ) ) return SDValue ( ) ; if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , CurrentVT . getSimpleVT ( ) , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = CurrentVT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? - <NUM_LIT> : ShuffleMask [ Elt ] ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getNumOperands ( ) > <NUM_LIT> && InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ; LdNode = LdNode . getOperand ( <NUM_LIT> ) ; } if ( ! <STR_LIT> ( LdNode . getNode ( ) ) ) return SDValue ( ) ; LoadSDNode * LN0 = cast < LoadSDNode > ( LdNode ) ; if ( ! LN0 || ! LN0 -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) || LN0 -> isVolatile ( ) ) return SDValue ( ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; unsigned Align = LN0 -> getAlignment ( ) ;

const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ;


<s> bool <ISA_LIT>BaseInstrInfo :: isAddrMode3OpMinusReg ( const MachineInstr & MI , unsigned Op ) const { const MachineOperand & Offset = MI . getOperand ( Op + <NUM_LIT> ) ; const MachineOperand & Opc = MI . getOperand ( Op + <NUM_LIT> ) ; assert ( Opc . isImm ( ) ) ; assert ( Offset . isReg ( ) ) ; int64_t OpcImm = Opc . getImm ( ) ; bool isSub = <STR_LIT> ( OpcImm ) == <STR_LIT> ;

return ( isSub && Offset . getReg ( ) != <NUM_LIT> ) ;


<s> static bool printAsmMRegister ( <ISA_LIT>AsmPrinter & P , const MachineOperand & MO , char Mode , raw_ostream & O ) { Register Reg = MO . getReg ( ) ; bool EmitPercent = MO . getParent ( ) -> getInlineAsmDialect ( ) == InlineAsm :: AD_ATT ; if ( ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) && ! <STR_LIT> . contains ( Reg ) ) return true ; switch ( Mode ) { default : return true ; case 'b' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <NUM_LIT> ) ; break ; case 'h' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <NUM_LIT> , true ) ; break ; case 'w' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <NUM_LIT> ) ;


<s> if ( C2 > ElemSizeInBits ) return SDValue ( ) ; unsigned ElemMask = ( <NUM_LIT> << ElemSizeInBits ) - <NUM_LIT> ; if ( ( C1 & ElemMask ) != ( ~ C2 & ElemMask ) ) return SDValue ( ) ; SDValue X = And . getOperand ( <NUM_LIT> ) ; SDValue Y = Shift . getOperand ( <NUM_LIT> ) ; unsigned Intrin = IsShiftRight ? <STR_LIT> : <STR_LIT> ; SDValue ResultSLI = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Intrin , DL , <STR_LIT> ) , X , Y , Shift . getOperand ( <NUM_LIT> ) ) ;


<s> int PNewOpcode = <STR_LIT> ( MI -> getOpcode ( ) ) ;


<s> printRegName ( O , Reg ) ; } else if ( Op . isImm ( ) ) { O << markup ( <STR_LIT> ) << '#' << formatImm ( Op . getImm ( ) ) << markup ( <STR_LIT> ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O << <STR_LIT> ; O . write_hex ( ( uint32_t ) Address ) ; }


<s> const char * getPassName ( ) const override {


<s> inline vector signed short vec_cmpgtsh ( vector signed short a1 , vector signed short a2 ) {

return ( vector signed short ) __builtin_altivec_vcmpgtsh ( ( vector signed short ) a1 , ( vector signed short ) a2 ) ;


<s> void <ISA_LIT>InstPrinter :: printIdxen ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { if ( MI -> getOperand ( OpNo ) . getImm ( ) ) O << <STR_LIT> ;


<s> unsigned TyAlign = DL . getABITypeAlignment ( Ty ) ; if ( TyAlign > <NUM_LIT> ) return TyAlign ; return <NUM_LIT> ; } unsigned Align = <NUM_LIT> ;

if ( Subtarget . hasSSE1 ( ) ) getMaxByValAlign ( Ty , Align ) ;


<s> fprintf ( stderr , <STR_LIT> , mode_name [ mode ] , class_names [ rclass ] ) ; if ( mode == QImode ) rclass = reduce_class ( rclass , HL_REGS , rclass ) ; else if ( mode == HImode ) rclass = reduce_class ( rclass , HI_REGS , rclass ) ; else if ( mode == SImode ) rclass = reduce_class ( rclass , SI_REGS , rclass ) ;

if ( rclass != A_REGS ) rclass = reduce_class ( rclass , DI_REGS , rclass ) ;


<s> const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ;

if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , false , IDLoc , Instructions ) ) return true ;


<s> FunctionPass * llvm :: create<ISA_LIT>GenInsert ( ) {


<s> Size += sizeof ( T ) ; if ( std :: is_floating_point < T > :: value ) { MI . addOperand ( MCOperand :: createDFPImm ( bit_cast < uint64_t > ( static_cast < double > ( Val ) ) ) ) ; } else { MI . addOperand ( MCOperand :: createImm ( static_cast < int64_t > ( Val ) ) ) ;


<s> unsigned decodeLgkmcnt ( const IsaVersion & Version , unsigned Waitcnt ) { return unpackBits ( Waitcnt , getLgkmcntBitShift ( Version . Major ) , getLgkmcntBitWidth ( Version . Major ) ) ;


<s> return Stack . empty ( ) || top ( ) == bottom ( ) ;


<s> MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeVFPRn ( insn , true ) ) ) ) ; NumOpsAdded = <NUM_LIT> ;


<s> bool isDPP ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> case <STR_LIT> : break ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> <ISA_LIT>BranchRelaxation ( ) : MachineFunctionPass ( ID ) {

initialize<ISA_LIT>BranchRelaxationPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> EVT InVT = In . getValueType ( ) ; EVT InSVT = InVT . getScalarType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLI . isTypeLegal ( InVT ) && TLI . isTypeLegal ( VT ) && isSATValidOnAVX512Subtarget ( InVT , VT , Subtarget ) ) { if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return DAG . getNode ( <STR_LIT> , DL , VT , SSatVal ) ; if ( auto USatVal = detectUSatPattern ( In , VT ) ) return DAG . getNode ( <STR_LIT> , DL , VT , USatVal ) ; } if ( VT . isVector ( ) && isPowerOf2_32 ( VT . getVectorNumElements ( ) ) && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && ( InSVT == <STR_LIT> || InSVT == <STR_LIT> ) ) { if ( auto SSatVal = detectSSatPattern ( In , VT ) ) return truncateVectorWithPACK ( <STR_LIT> , VT , SSatVal , DL , DAG , Subtarget ) ; if ( auto USatVal = detectSSatPattern ( In , VT , true ) ) { if ( SVT == <STR_LIT> && InSVT == <STR_LIT> ) {

EVT MidVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ;


<s> static void __attribute__ ( ( format ( printf , <NUM_LIT> , <NUM_LIT> ) ) ) bif_diag ( int diagpos , const char * fmt , ... ) {


<s> Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , ValTy ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ;


<s> return false ; } if ( Opc == <STR_LIT> ) TB = T1B , FB = T2B ; else TB = T2B , FB = T1B ; if ( ! MDT -> properlyDominates ( B , TB ) || ! MDT -> properlyDominates ( B , FB ) ) return false ; unsigned TNP = TB -> pred_size ( ) , FNP = FB -> pred_size ( ) ; unsigned TNS = TB -> succ_size ( ) , FNS = FB -> succ_size ( ) ; bool TOk = ( TNP == <NUM_LIT> && TNS == <NUM_LIT> && MLI -> getLoopFor ( TB ) == L ) ; bool FOk = ( FNP == <NUM_LIT> && FNS == <NUM_LIT> && MLI -> getLoopFor ( FB ) == L ) ; if ( SkipExitBranches && MLI -> getLoopFor ( TB ) != MLI -> getLoopFor ( FB ) ) return false ; if ( ! TOk && ! FOk ) return false ; MachineBasicBlock * TSB = ( TNS > <NUM_LIT> ) ? * TB -> succ_begin ( ) : nullptr ; MachineBasicBlock * FSB = ( FNS > <NUM_LIT> ) ? * FB -> succ_begin ( ) : nullptr ; MachineBasicBlock * JB = nullptr ; if ( TOk ) { if ( FOk ) { if ( TSB == FSB ) JB = TSB ; } else { if ( TSB == FB ) JB = FB ; FB = nullptr ;


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const {


<s> if ( MEM_P ( operands_2 [ <NUM_LIT> ] ) ) mem_2 = operands_2 [ <NUM_LIT> ] ; else mem_2 = operands_2 [ <NUM_LIT> ] ; extract_base_offset_in_addr ( mem_1 , & base , & offset_1 ) ; extract_base_offset_in_addr ( mem_2 , & base , & offset_2 ) ;


<s> bool isMem ( ) const override { return false ;


return ( uint8x16_t ) __builtin_neon_vreinterpretv16qiv2di ( ( int64x2_t ) __a ) ;


<s> MachineBasicBlock & MBB = * ( FrameSetup -> getParent ( ) ) ; TII -> setFrameAdjustment ( * FrameSetup , Context . ExpectedDist ) ; const DebugLoc & DL = FrameSetup -> getDebugLoc ( ) ; bool Is64Bit = STI -> is64Bit ( ) ; for ( int Idx = ( Context . ExpectedDist >> Log2SlotSize ) - <NUM_LIT> ; Idx >= <NUM_LIT> ; -- Idx ) { MachineBasicBlock :: iterator Store = * Context . ArgStoreVector [ Idx ] ; const MachineOperand & PushOp = Store -> getOperand ( <STR_LIT> ) ; MachineBasicBlock :: iterator Push = nullptr ; unsigned PushOpcode ; switch ( Store -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( PushOp . isImm ( ) ) { int64_t Val = PushOp . getImm ( ) ; if ( isInt < <NUM_LIT> > ( Val ) ) PushOpcode = Is64Bit ? <STR_LIT> : <STR_LIT> ; } Push = BuildMI ( MBB , Context . Call , DL , TII -> get ( PushOpcode ) ) . add ( PushOp ) ; Push -> cloneMemRefs ( MF , * Store ) ; break ;


<s> V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , V , B . getInt32 ( DPP :: ROW_SHR0 | <NUM_LIT> << Idx ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; } if ( ST -> hasDPPBroadcasts ( ) ) { V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , V , B . getInt32 ( DPP :: BCAST15 ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , V , B . getInt32 ( DPP :: BCAST31 ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; } else { assert ( ST -> hasPermLaneX16 ( ) ) ; Value * const PermX = B . CreateIntrinsic ( <STR_LIT> , { } , { V , V , B . getInt32 ( - <NUM_LIT> ) , B . getInt32 ( - <NUM_LIT> ) , B . getFalse ( ) , B . getFalse ( ) } ) ; V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , PermX , B . getInt32 ( DPP :: QUAD_PERM_ID ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; if ( ! ST -> isWave32 ( ) ) { Value * const Lane31 = B . CreateIntrinsic ( <STR_LIT> , { } , { V , B . getInt32 ( <NUM_LIT> ) } ) ; V = buildNonAtomicBinOp ( B , Op , V , B . CreateCall ( UpdateDPP , { Identity , Lane31 , B . getInt32 ( DPP :: QUAD_PERM_ID ) , B . getInt32 ( <NUM_LIT> ) , B . getInt32 ( <NUM_LIT> ) , B . getFalse ( ) } ) ) ; }


<s> Result = DAG . getTargetConstant ( Val , DL , Type ) ; break ; } } return ; case 'L' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; uint64_t Val = ( uint64_t ) C -> getZExtValue ( ) ; if ( ( isUInt < <NUM_LIT> > ( Val ) ) && ( ( Val & <NUM_LIT> ) == <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , DL , Type ) ; break ; } } return ; case 'N' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; int64_t Val = ( int64_t ) C -> getZExtValue ( ) ; if ( ( Val >= - <NUM_LIT> ) && ( Val <= - <NUM_LIT> ) ) { Result = DAG . getTargetConstant ( Val , DL , Type ) ; break ; } } return ; case 'O' : if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ) { EVT Type = Op . getValueType ( ) ; uint64_t Val = ( uint64_t ) C -> getZExtValue ( ) ; if ( ( isInt < <NUM_LIT> > ( Val ) ) ) { Result = DAG . getTargetConstant ( Val , DL , Type ) ; break ; } }


<s> if ( Zeroable [ EltIdx ] ) { Mask [ EltIdx ] = EltIdx + <NUM_LIT> ; continue ; } Elt = Op -> getOperand ( EltIdx ) ; EltMaskIdx = cast < ConstantSDNode > ( Elt . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Elt . getOperand ( <NUM_LIT> ) != V1 || EltMaskIdx != EltIdx ) break ; Mask [ EltIdx ] = EltIdx ; } if ( EltIdx == <NUM_LIT> ) { SDValue VZero = getZeroVector ( VT , Subtarget , DAG , SDLoc ( Op ) ) ; if ( V1 . getSimpleValueType ( ) != VT ) V1 = DAG . getNode ( <STR_LIT> , SDLoc ( V1 ) , VT , V1 ) ; return DAG . getVectorShuffle ( VT , SDLoc ( V1 ) , V1 , VZero , & Mask [ <NUM_LIT> ] ) ; } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDValue V2 = Elt . getOperand ( <NUM_LIT> ) ; if ( Elt == FirstNonZero && EltIdx == FirstNonZeroIdx ) V1 = SDValue ( ) ; bool CanFold = true ; for ( unsigned i = EltIdx + <NUM_LIT> ; i < <NUM_LIT> && CanFold ; ++ i ) {


<s> int nregs ATTRIBUTE_UNUSED ; if ( aarch64_vfp_is_call_or_return_candidate ( TYPE_MODE ( type ) , type , & mode , & nregs , NULL , false ) ) aarch64_err_no_fpadvsimd ( TYPE_MODE ( type ) ) ; } if ( ! silent_p && ! TARGET_SVE && pcum -> pcs_variant == ARM_PCS_SVE ) { if ( fndecl ) fatal_error ( input_location , <STR_LIT> , fndecl ) ; else fatal_error ( input_location , <STR_LIT> <STR_LIT> , fntype ) ; }


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; SecondaryVCTPs . insert ( MI ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; VCTP = MI ; } } else if ( isVPTOpcode ( MI -> getOpcode ( ) ) ) { if ( MI -> getOpcode ( ) != <STR_LIT> ) { assert ( MI -> findRegisterDefOperandIdx ( <STR_LIT> ) != - <NUM_LIT> && <STR_LIT> ) ; CurrentPredicate . insert ( MI ) ; } VPTBlocks . emplace_back ( MI , CurrentPredicate ) ; CurrentBlock = & VPTBlocks . back ( ) ; return true ; } else if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { return false ; } bool IsUse = false ; bool IsDef = false ; const MCInstrDesc & MCID = MI -> getDesc ( ) ; for ( int i = MI -> getNumOperands ( ) - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . getReg ( ) != <STR_LIT> ) continue ; if ( MO . isDef ( ) ) { CurrentPredicate . insert ( MI ) ; IsDef = true ; } else if ( <STR_LIT> ( MCID . OpInfo [ i ] . OperandType ) ) {

CurrentBlock -> addInst ( MI , CurrentPredicate ) ;


<s> int i ; for ( i = <NUM_LIT> ; i < * p_argc ; i ++ ) { if ( strlen ( argv [ i ] ) < <NUM_LIT> ) continue ; if ( strncmp ( argv [ i ] , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { char * ptr ; int new_len , search_dirs_len ; ptr = to_host_dir_spec ( & argv [ i ] [ <NUM_LIT> ] ) ; new_len = strlen ( ptr ) ; search_dirs_len = strlen ( search_dirs ) ; search_dirs = xrealloc ( search_dirs , search_dirs_len + new_len + <NUM_LIT> ) ; if ( search_dirs_len > <NUM_LIT> ) strcat ( search_dirs , PATH_SEPARATOR_STR ) ; strcat ( search_dirs , ptr ) ; } else if ( strncmp ( argv [ i ] , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { char * ptr ; int new_len , defines_len ; ptr = & argv [ i ] [ <NUM_LIT> ] ; new_len = strlen ( ptr ) ; defines_len = strlen ( defines ) ; defines = xrealloc ( defines , defines_len + new_len + <NUM_LIT> ) ; if ( defines_len > <NUM_LIT> ) strcat ( defines , <STR_LIT> ) ; strcat ( defines , <STR_LIT> ) ; strcat ( defines , ptr ) ;


<s> MachineBasicBlock * TrueBranch = getTrueBranch ( BranchMI ) ; MachineBasicBlock :: iterator I = BranchMI ; if ( TrueBranch != LandMBB ) reversePredicateSetter ( I , * I -> getParent ( ) ) ;

insertCondBranchBefore ( ExitingMBB , I , <STR_LIT> , <STR_LIT> , DL ) ;


<s> int WordSize = TT . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; EmitAlignment ( WordSize == <NUM_LIT> ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> + WordSize , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> EmitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_<ISA_LIT>_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( FeatureFlagsAnd , <NUM_LIT> ) ; EmitAlignment ( WordSize == <NUM_LIT> ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) ; OutStreamer -> endSection ( Nt ) ; OutStreamer -> SwitchSection ( Cur ) ; } } if ( TT . isOSBinFormatMachO ( ) ) OutStreamer -> SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ; if ( TT . isOSBinFormatCOFF ( ) ) { MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer -> BeginCOFFSymbolDef ( S ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( COFF :: IMAGE_SYM_CLASS_STATIC ) ; OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_NULL ) ; OutStreamer -> EndCOFFSymbolDef ( ) ; int64_t Feat00Flags = <NUM_LIT> ; if ( TT . getArch ( ) == Triple :: x86 ) {


<s> case <STR_LIT> : return true ; default : return false ; }


<s> Filler ( TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) , TII ( tm . getInstrInfo ( ) ) {


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> return D ( <STR_LIT> , R ( a ) , R ( b ) ) ;


<s> } EVT ValTy = Op . getValueType ( ) ; bool HasGotOfst = ( GV -> hasInternalLinkage ( ) || ( GV -> hasLocalLinkage ( ) && ! isa < Function > ( GV ) ) ) ; unsigned GotFlag = IsN64 ? ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) : ( HasGotOfst ? <STR_LIT> : <STR_LIT> ) ; SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , ValTy , <NUM_LIT> , GotFlag ) ; GA = DAG . getNode ( <STR_LIT> , dl , ValTy , GetGlobalReg ( DAG , ValTy ) , GA ) ; SDValue ResNode = DAG . getLoad ( ValTy , dl , DAG . getEntryNode ( ) , GA , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; if ( ! HasGotOfst ) return ResNode ;

SDValue GALo = DAG . getTargetGlobalAddress ( GV , dl , ValTy , <NUM_LIT> , IsN64 ? <STR_LIT> :


<s> if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ;


<s> <STR_LIT> CC1 = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; const SDValue Op2 = isa < ConstantSDNode > ( TrueVal1 ) ? FalseVal1 : TrueVal1 ; if ( Op2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue V2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue K2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue TrueVal2 = Op2 . getOperand ( <NUM_LIT> ) ; SDValue FalseVal2 = Op2 . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC2 = cast < CondCodeSDNode > ( Op2 . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue V1Tmp = V1 ; SDValue V2Tmp = V2 ;

if ( V1Tmp != TrueVal1 || V2Tmp != TrueVal2 || K1 != FalseVal1 || K2 != FalseVal2 || ! ( ( isGTorGE ( CC1 ) && isLTorLE ( CC2 ) ) || ( isLTorLE ( CC1 ) && isGTorGE ( CC2 ) ) ) ) return SDValue ( ) ;


<s> if ( ImplicitRn ) Binary |= ( <ISA_LIT>RegisterInfo :: getRegisterNumbering ( ImplicitRn ) << <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; if ( ! Skipped && TID . getOperandConstraint ( OpIdx , TOI :: TIED_TO ) != - <NUM_LIT> ) ++ OpIdx ; const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM3Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM3Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( MO2 . getReg ( ) ) { Binary |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO2 . getReg ( ) ) ; emitWordLE ( Binary ) ; return ; } Binary |= <NUM_LIT> << <STR_LIT> ; if ( unsigned ImmOffs = <STR_LIT> ( AM3Opc ) ) { Binary |= ( ImmOffs >> <NUM_LIT> ) << <STR_LIT> ; Binary |= ( ImmOffs & <NUM_LIT> ) ; } emitWordLE ( Binary ) ;


<s> switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : assert ( ! MO . getSubReg ( ) && <STR_LIT> ) ; assert ( MO . getReg ( ) > <STR_LIT> && MO . getReg ( ) < <STR_LIT> && <STR_LIT> ) ; OutMO = MCOperand :: createReg ( MO . getReg ( ) ) ; return true ; case MachineOperand :: MO_Immediate : OutMO = MCOperand :: createImm ( MO . getImm ( ) ) ; return true ; case MachineOperand :: MO_MachineBasicBlock : OutMO = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ) ; return true ; case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : OutMO = GetSymbolRef ( MO , GetSymbolFromOperand ( MO , AP ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_JumpTableIndex : OutMO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_ConstantPoolIndex : OutMO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_BlockAddress : OutMO = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP , isDarwin ) ; return true ; case MachineOperand :: MO_MCSymbol : OutMO = GetSymbolRef ( MO , MO . getMCSymbol ( ) , AP , isDarwin ) ; return true ;

case MachineOperand :: MO_RegisterMask :


<s> case GT : return <STR_LIT> ; case GE : return <STR_LIT> ; case LTU : return <STR_LIT> ; case LEU : return <STR_LIT> ; case GTU : return <STR_LIT> ; case GEU : return <STR_LIT> ; default :


<s> unsigned PtrCopy = MRI . createVirtualRegister ( MRI . getRegClass ( Ptr ) ) ; unsigned OldValCopy = MRI . createVirtualRegister ( MRI . getRegClass ( OldVal ) ) ; unsigned NewValCopy = MRI . createVirtualRegister ( MRI . getRegClass ( NewVal ) ) ; BuildMI ( * BB , II , DL , TII -> get ( <STR_LIT> ) , PtrCopy ) . addReg ( Ptr ) ; BuildMI ( * BB , II , DL , TII -> get ( <STR_LIT> ) , OldValCopy ) . addReg ( OldVal ) ; BuildMI ( * BB , II , DL , TII -> get ( <STR_LIT> ) , NewValCopy ) . addReg ( NewVal ) ; BuildMI ( * BB , II , DL , TII -> get ( AtomicOp ) ) . addReg ( Dest , RegState :: Define | RegState :: EarlyClobber ) . addReg ( PtrCopy , RegState :: Kill ) . addReg ( OldValCopy , RegState :: Kill ) . addReg ( NewValCopy , RegState :: Kill ) . addReg ( Scratch , RegState :: EarlyClobber | RegState :: Define | RegState :: Dead | RegState :: Implicit ) ;


<s> static unsigned createLaneVGPR ( MachineRegisterInfo & MRI ) {

return MRI . createVirtualRegister ( & AMDGPU :: VReg_32RegClass ) ;


<s> MachineBasicBlock :: const_reverse_iterator It = MI ; MachineBasicBlock :: const_reverse_iterator E = MI . getParent ( ) -> rend ( ) ; It ++ ; for ( ; It != E ; ++ It ) {

if ( It -> modifiesRegister ( Reg , & getRegisterInfo ( ) ) && ( & * It ) != & DefMI ) return false ;


<s> if ( getParser ( ) . parseIdentifier ( Name ) ) return TokError ( <STR_LIT> ) ; if ( parseEOL ( ) ) return true ;

getTargetStreamer ( ) . emitDirectiveVariantPCS ( getContext ( ) . getOrCreateSymbol ( Name ) ) ;


<s> bool isUnspillableTerminatorImpl ( const MachineInstr * MI ) const override {

return MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ;


<s> } } ; for ( auto OpIdx : enumerate ( I -> operands ( ) ) ) { if ( ! IsSinker ( I , OpIdx . index ( ) ) ) continue ; Instruction * Op = dyn_cast < Instruction > ( OpIdx . value ( ) . get ( ) ) ; if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ;


<s> RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , ValVT == <STR_LIT> ? <STR_LIT> : ValVT ) ; if ( ValVT == <STR_LIT> ) ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue ) ; InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; unsigned ArgSize = VA . getLocVT ( ) . getStoreSize ( ) ; int FI = MFI . CreateFixedObject ( ArgSize , VA . getLocMemOffset ( ) , isImmutable ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo ( ) ) ) ; } } SmallVector < CCValAssign , <NUM_LIT> > ByValArgLocs ; CCState CCByValInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ByValArgLocs , * DAG . getContext ( ) ) ; CCByValInfo . AllocateStack ( CCInfo . getNextStackOffset ( ) , PtrByteSize ) ; CCByValInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>32_SVR4_ByVal ) ; unsigned MinReservedArea = CCByValInfo . getNextStackOffset ( ) ; MinReservedArea = std :: max ( MinReservedArea , LinkageSize ) ; MinReservedArea = EnsureStackAlignment ( Subtarget . getFrameLowering ( ) , MinReservedArea ) ; FuncInfo -> setMinReservedArea ( MinReservedArea ) ; SmallVector < SDValue , <NUM_LIT> > MemOps ; if ( isVarArg ) { static const MCPhysReg GPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; const unsigned NumGPArgRegs = array_lengthof ( GPArgRegs ) ; static const MCPhysReg FPArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned NumFPArgRegs = array_lengthof ( FPArgRegs ) ; if ( useSoftFloat ( ) ) NumFPArgRegs = <NUM_LIT> ; FuncInfo -> setVarArgsNumGPR ( CCInfo . getFirstUnallocated ( GPArgRegs ) ) ; FuncInfo -> setVarArgsNumFPR ( CCInfo . getFirstUnallocated ( FPArgRegs ) ) ; int Depth = NumGPArgRegs * PtrVT . getSizeInBits ( ) / <NUM_LIT> + NumFPArgRegs * MVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> ; FuncInfo -> setVarArgsStackOffset ( MFI . CreateFixedObject ( PtrVT . getSizeInBits ( ) / <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ) ;

FuncInfo -> setVarArgsFrameIndex ( MFI . CreateStackObject ( Depth , <NUM_LIT> , false ) ) ;


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectAddrFrameIndexOffset ( SDValue Addr , SDValue & Base , SDValue & Offset , unsigned OffsetBits , unsigned ShiftAmount = <NUM_LIT> ) const { if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isIntN ( OffsetBits + ShiftAmount , CN -> getSExtValue ( ) ) ) { EVT ValTy = Addr . getValueType ( ) ; if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; else { Base = Addr . getOperand ( <NUM_LIT> ) ; const Align Alignment ( <NUM_LIT> << ShiftAmount ) ;

if ( ! isAligned ( Alignment , CN -> getZExtValue ( ) ) ) return false ;


<s> case Kind :: Imm : OS << <STR_LIT> << Imm ; break ; case Kind :: MemOp :


<s> rtx insn ; accessor . base = gen_rtx_REG ( Pmode , OLD_SP_REGNO ) ; accessor . base_offset = info -> total_size ; insn = emit_insn ( gen_movsi ( accessor . base , sp ) ) ; } else { accessor . base = stack_pointer_rtx ; accessor . base_offset = <NUM_LIT> ; } { rtx asm_offset = frv_frame_offset_rtx ( - info -> total_size ) ; rtx dwarf_offset = GEN_INT ( - info -> total_size ) ; frv_frame_insn ( gen_stack_adjust ( sp , sp , asm_offset ) , gen_rtx_SET ( Pmode , sp , gen_rtx_PLUS ( Pmode , sp , dwarf_offset ) ) ) ; } if ( frame_pointer_needed ) { int fp_offset = info -> reg_offset [ FRAME_POINTER_REGNUM ] ; rtx asm_src = plus_constant ( accessor . base , fp_offset - accessor . base_offset ) ; rtx dwarf_src = plus_constant ( sp , fp_offset ) ; frv_frame_access ( & accessor , fp , fp_offset ) ;

frv_frame_insn ( gen_rtx_SET ( VOIDmode , fp , asm_src ) , gen_rtx_SET ( VOIDmode , fp , dwarf_src ) ) ;


<s> } HasHazard = MI . mayStore ( ) && ( OrigSeenLoad || OrigSeenStore ) ; HasHazard |= MI . mayLoad ( ) || OrigSeenStore ; SeenNoObjLoad |= MI . mayLoad ( ) ;


<s> int RegNum = parseRegisterName ( & MatchRegisterName ) ; if ( RegNum == <STR_LIT> ) RegNum = parseRegisterName ( & MatchRegisterAltName ) ;


<s> return isa < GetElementPtrInst > ( LI -> getPointerOperand ( ) ) && LI -> isSimple ( ) ; } case Instruction :: BitCast : return true ; case Instruction :: Store : { StoreInst * <ISA_LIT> = cast < StoreInst > ( Inst ) ; return ( <ISA_LIT> -> getPointerOperand ( ) == User ) && isa < GetElementPtrInst > ( User ) && <ISA_LIT> -> isSimple ( ) ;


<s> while ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || ( Carry . getOpcode ( ) == <STR_LIT> && isOneConstant ( Carry . getOperand ( <NUM_LIT> ) ) ) ) Carry = Carry . getOperand ( <NUM_LIT> ) ; if ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> ) { if ( Carry . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> ) return Carry . getOperand ( <NUM_LIT> ) ; }


<s> bool <ISA_LIT>InstructionSelector :: selectExtInst ( Register ResVReg , const <ISA_LIT>Type * ResType , MachineInstr & I , const ExtInstList & Insts ) const { for ( const auto & Ex : Insts ) { ExtInstSet Set = Ex . first ; uint32_t Opcode = Ex . second ; if ( STI . canUseExtInstSet ( Set ) ) {

MachineBasicBlock & BB = * I . getParent ( ) ;


<s> } if ( IndexOperand ) report_fatal_error ( <STR_LIT> ) ; unsigned Instruction = IntrID == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned ShaderType = <ISA_LIT>InstrInfo :: getDSShaderTypeValue ( * MF ) ; unsigned Offset0 = OrderedCountIndex << <NUM_LIT> ; unsigned Offset1 = WaveRelease | ( WaveDone << <NUM_LIT> ) | ( ShaderType << <NUM_LIT> ) | ( Instruction << <NUM_LIT> ) ; if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) Offset1 |= ( CountDw - <NUM_LIT> ) << <NUM_LIT> ; unsigned Offset = Offset0 | ( Offset1 << <NUM_LIT> ) ; Register M0Val = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( * MBB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( M0Val ) ;

Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( MF , FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , Align ) ; unsigned Opc = <NUM_LIT> ; bool Offset = true ; switch ( TRI -> getSpillSize ( * RC ) ) { case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( Register :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; if ( Register :: isVirtualRegister ( SrcReg ) ) MF . getRegInfo ( ) . constrainRegClass ( SrcReg , & <STR_LIT> ) ; else assert ( SrcReg != <STR_LIT> ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opc = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { storeRegPairToStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , SrcReg , isKill , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { storeRegPairToStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , SrcReg , isKill , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ;


<s> return arm_coproc_mem_operand_wb ( op , wb ? <NUM_LIT> : <NUM_LIT> ) ;


<s> CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = T . getArch ( ) == Triple :: ppc64le ; AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; DollarIsPC = true ; MinInstAlignment = <NUM_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; ZeroDirective = <STR_LIT> ;


<s> } if ( TARGET_AVX && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) { switch ( GET_MODE_CLASS ( mode ) ) { case MODE_VECTOR_INT : case MODE_INT : if ( GET_MODE ( op0 ) != V32QImode ) { if ( ! MEM_P ( op0 ) ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V32QImode ) ; } else op0 = gen_lowpart ( V32QImode , op0 ) ; } op1 = gen_lowpart ( V32QImode , op1 ) ; case MODE_VECTOR_FLOAT : ix86_avx256_split_vector_move_misalign ( op0 , op1 ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; break ; default : gcc_unreachable ( ) ; } return ; } if ( MEM_P ( op1 ) ) { if ( TARGET_AVX && ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) && misaligned_operand ( op1 , GET_MODE ( op1 ) ) ) emit_insn ( gen_rtx_SET ( op0 , op1 ) ) ; else if ( TARGET_SSE2 && GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT ) { if ( GET_MODE ( op0 ) != V16QImode ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V16QImode ) ; } op1 = gen_lowpart ( V16QImode , op1 ) ; emit_insn ( gen_sse2_loaddquv16qi ( op0 , op1 ) ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; } else if ( TARGET_SSE2 && mode == V2DFmode ) { rtx zero ; if ( TARGET_AVX || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL || optimize_insn_for_size_p ( ) ) { emit_insn ( gen_sse2_loadupd ( op0 , op1 ) ) ; return ; } if ( TARGET_SSE_SPLIT_REGS ) { emit_clobber ( op0 ) ; zero = op0 ; } else { zero = CONST0_RTX ( V2DFmode ) ; } m = adjust_address ( op1 , DFmode , <NUM_LIT> ) ; emit_insn ( gen_sse2_loadlpd ( op0 , zero , m ) ) ; m = adjust_address ( op1 , DFmode , <NUM_LIT> ) ; emit_insn ( gen_sse2_loadhpd ( op0 , op0 , m ) ) ; } else { rtx t ; if ( TARGET_AVX || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL || optimize_insn_for_size_p ( ) ) { if ( GET_MODE ( op0 ) != V4SFmode ) { orig_op0 = op0 ; op0 = gen_reg_rtx ( V4SFmode ) ; } op1 = gen_lowpart ( V4SFmode , op1 ) ; emit_insn ( gen_sse_loadups ( op0 , op1 ) ) ; if ( orig_op0 ) emit_move_insn ( orig_op0 , gen_lowpart ( GET_MODE ( orig_op0 ) , op0 ) ) ; return ; }

if ( mode != V4SFmode ) t = gen_reg_rtx ( V4SFmode ) ;


<s> static void s390_add_constant ( struct constant_pool * pool , rtx val , enum machine_mode mode ) { struct constant * c ; int i ; for ( i = <NUM_LIT> ; i < NR_C_MODES ; i ++ ) if ( constant_modes [ i ] == mode ) break ; gcc_assert ( i != NR_C_MODES ) ; for ( c = pool -> constants [ i ] ; c != NULL ; c = c -> next ) if ( rtx_equal_p ( val , c -> value ) ) break ; if ( c == NULL ) { c = ( struct constant * ) xmalloc ( sizeof * c ) ; c -> value = val ; c -> label = gen_label_rtx ( ) ; c -> next = pool -> constants [ i ] ;


<s> break ; } case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : { switch ( Opc ) { case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned EntrySize = ( Opc == <STR_LIT> ) ? <NUM_LIT> : ( ( Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) ; unsigned NumOps = TID . getNumOperands ( ) ; MachineOperand JTOP = MI -> getOperand ( NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ) ; unsigned JTI = JTOP . getIndex ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; assert ( MJTI != <NUM_LIT> ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; assert ( JTI < JT . size ( ) ) ; unsigned InstSize = ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned NumEntries = getNumJTEntries ( JT , JTI ) ; if ( Opc == <STR_LIT> && ( NumEntries & <NUM_LIT> ) ) ++ NumEntries ; return NumEntries * EntrySize + InstSize ; } default : return <NUM_LIT> ;


<s> } else if ( MO . isSymbol ( ) ) { Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else if ( MO . isMBB ( ) ) { assert ( Suffix . empty ( ) ) ; Sym = MO . getMBB ( ) -> getSymbol ( ) ; } unsigned OrigLen = Name . size ( ) - PrefixLen ; Name += Suffix ; if ( ! Sym ) Sym = Ctx . getOrCreateSymbol ( Name ) ; StringRef OrigName = StringRef ( Name ) . substr ( PrefixLen , OrigLen ) ; switch ( MO . getTargetFlags ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } break ; } case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getHiddenGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } break ; } case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl :: StubValueTy ( Ctx . getOrCreateSymbol ( OrigName ) , false ) ; }


<s> switch ( GET_CODE ( x ) ) { case EQ : case NE : case GTU : case LTU : case GEU : case LEU : return <NUM_LIT> ; case GT : case LT : case GE : case LE : return ! ( cc_prev_status . flags & CC_NO_OVERFLOW ) ; default :


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_<ISA_LIT> , true ) {


<s> typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ;

return ( unsigned long long ) __builtin_sh_media_MMULLO_WL ( ( v4hi ) mm , ( v4hi ) mn ) ;


<s> } ) != To -> getParent ( ) -> rend ( ) ) ; for ( -- To ; To != From ; -- To ) { const MachineInstr & Instr = * To ; if ( ( ( AccessToCheck & AK_Write ) && Instr . modifiesRegister ( <STR_LIT> , TRI ) ) || ( ( AccessToCheck & AK_Read ) && Instr . readsRegister ( <STR_LIT> , TRI ) ) ) return true ; } return false ;


<s> if ( ! isInt < <NUM_LIT> > ( AM . BaseOffs >> Log2_32 ( A ) ) ) return false ; } if ( AM . BaseGV ) return false ; int Scale = AM . Scale ; if ( Scale < <NUM_LIT> ) Scale = - Scale ; switch ( Scale ) { case <NUM_LIT> : break ; default : return false ; }


<s> if ( CC >= <STR_LIT> && CC <= <STR_LIT> ) return false ;

assert ( ( CC >= <STR_LIT> && CC <= <STR_LIT> ) && <STR_LIT> ) ;


<s> if ( MCOp . isImm ( ) ) return getMachineOpValue ( Inst , MCOp , Fixups , SubtargetInfo ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MCOp . getExpr ( ) , Kind ) ) ; return <NUM_LIT> ;


<s> bool isMem ( ) const { return false ;


<s> op0 = force_reg ( word_mode , op0 ) ; if ( code == EQ || code == NE ) { op0 = loongarch_zero_if_equal ( op0 , op1 ) ; op1 = const0_rtx ; } else { bool invert = false ; rtx target = gen_reg_rtx ( GET_MODE ( op0 ) ) ; loongarch_emit_int_order_test ( code , & invert , target , op0 , op1 ) ; code = invert ? EQ : NE ; op0 = target ; op1 = const0_rtx ; } } rtx cond = gen_rtx_fmt_ee ( code , GET_MODE ( op0 ) , op0 , op1 ) ; if ( INTEGRAL_MODE_P ( GET_MODE ( operands [ <NUM_LIT> ] ) ) && register_operand ( operands [ <NUM_LIT> ] , VOIDmode ) && register_operand ( operands [ <NUM_LIT> ] , VOIDmode ) ) { machine_mode mode = GET_MODE ( operands [ <NUM_LIT> ] ) ; rtx temp = gen_reg_rtx ( mode ) ; rtx temp2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_rtx_SET ( temp , gen_rtx_IF_THEN_ELSE ( mode , cond , operands [ <NUM_LIT> ] , const0_rtx ) ) ) ;

cond = gen_rtx_fmt_ee ( ( code == EQ ) ? NE : EQ , GET_MODE ( op0 ) , op0 , op1 ) ;


<s> if ( ! canWidenShuffleElements ( Mask , Widened128Mask ) ) return SDValue ( ) ; assert ( Widened128Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Widened128Mask [ <NUM_LIT> ] == <NUM_LIT> && ( Zeroable & <NUM_LIT> ) == <NUM_LIT> && ( Widened128Mask [ <NUM_LIT> ] == <NUM_LIT> || ( Zeroable & <NUM_LIT> ) == <NUM_LIT> ) ) { unsigned NumElts = ( ( Zeroable & <NUM_LIT> ) == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , NumElts ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , getZeroVector ( VT , Subtarget , DAG , DL ) , LoV , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } bool OnlyUsesV1 = isShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 , V2 ) ; if ( OnlyUsesV1 || isShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , V1 , V2 ) ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , SubVec , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } bool IsInsert = true ; int V2Index = - <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { assert ( Widened128Mask [ i ] >= - <NUM_LIT> && <STR_LIT> ) ; if ( Widened128Mask [ i ] < <NUM_LIT> ) continue ; if ( Widened128Mask [ i ] < <NUM_LIT> ) { if ( Widened128Mask [ i ] != i ) { IsInsert = false ; break ; } } else { if ( V2Index >= <NUM_LIT> || Widened128Mask [ i ] != <NUM_LIT> ) { IsInsert = false ; break ; } V2Index = i ; } } if ( IsInsert && V2Index >= <NUM_LIT> ) { MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , <NUM_LIT> ) ; SDValue Subvec = DAG . getNode ( <STR_LIT> , DL , SubVT , V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return insert128BitVector ( V1 , Subvec , V2Index * <NUM_LIT> , DAG , DL ) ;


<s> return gen_rtx_PLUS ( Pmode , force_reg ( Pmode , base ) , arc_unspec_offset ( addr , UNSPEC_TLS_OFF ) ) ; case TLS_MODEL_INITIAL_EXEC : addr = arc_unspec_offset ( addr , UNSPEC_TLS_IE ) ; addr = copy_to_mode_reg ( Pmode , gen_const_mem ( Pmode , addr ) ) ; return gen_rtx_PLUS ( Pmode , gen_rtx_REG ( Pmode , arc_tp_regno ) , addr ) ; case TLS_MODEL_LOCAL_EXEC : addr = arc_unspec_offset ( addr , UNSPEC_TLS_OFF ) ;


<s> gcc_assert ( ! TARGET_FDPIC ) ; reg = arm_tls_descseq_addr ( x , reg ) ; tp = arm_load_tp ( NULL_RTX ) ; dest = gen_rtx_PLUS ( Pmode , tp , reg ) ; } else { if ( TARGET_FDPIC ) insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32_FDPIC ) ; else insns = arm_call_tls_get_addr ( x , reg , & ret , TLS_LDM32 ) ; eqv = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , const1_rtx ) , UNSPEC_TLS ) ; dest = gen_reg_rtx ( Pmode ) ; emit_libcall_block ( insns , dest , ret , eqv ) ; addend = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LDO32 ) ) , UNSPEC_TLS ) ; addend = force_reg ( SImode , gen_rtx_CONST ( SImode , addend ) ) ; dest = gen_rtx_PLUS ( Pmode , dest , addend ) ; } return dest ; case TLS_MODEL_INITIAL_EXEC : if ( TARGET_FDPIC ) { sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_IE32_FDPIC ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; emit_insn ( gen_addsi3 ( reg , reg , gen_rtx_REG ( Pmode , FDPIC_REGNUM ) ) ) ; emit_move_insn ( reg , gen_rtx_MEM ( Pmode , reg ) ) ; } else { labelno = GEN_INT ( pic_labelno ++ ) ; label = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , labelno ) , UNSPEC_PIC_LABEL ) ; label = gen_rtx_CONST ( VOIDmode , label ) ; sum = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_IE32 ) , label , GEN_INT ( TARGET_ARM ? <NUM_LIT> : <NUM_LIT> ) ) , UNSPEC_TLS ) ; reg = load_tls_operand ( sum , reg ) ; if ( TARGET_ARM ) emit_insn ( gen_tls_load_dot_plus_eight ( reg , reg , labelno ) ) ; else if ( TARGET_THUMB2 ) emit_insn ( gen_tls_load_dot_plus_four ( reg , NULL , reg , labelno ) ) ; else { emit_insn ( gen_pic_add_dot_plus_four ( reg , reg , labelno ) ) ; emit_move_insn ( reg , gen_const_mem ( SImode , reg ) ) ; } } tp = arm_load_tp ( NULL_RTX ) ; return gen_rtx_PLUS ( Pmode , tp , reg ) ; case TLS_MODEL_LOCAL_EXEC : tp = arm_load_tp ( NULL_RTX ) ;

reg = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x , GEN_INT ( TLS_LE32 ) ) , UNSPEC_TLS ) ;


<s> return ! hasMovrel ( ) || ( UserEnable && hasVGPRIndexMode ( ) ) ;


<s> __o = __builtin_aarch64_ld2rdi ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int64x1_t ) __builtin_aarch64_get_dregoidi ( __o , <NUM_LIT> ) ;