<s> return ( uint16x4_t ) __builtin_aarch64_umaxv4hi ( ( int16x4_t ) __a , ( int16x4_t ) __b ) ;


<s> if ( ! isa < GlobalObject > ( LHS ) || ! isa < GlobalVariable > ( RHS ) || LHS -> isThreadLocal ( ) || RHS -> isThreadLocal ( ) || RHS -> getName ( ) != <STR_LIT> || ! RHS -> hasExternalLinkage ( ) || cast < GlobalVariable > ( RHS ) -> hasInitializer ( ) || RHS -> hasSection ( ) ) return nullptr ; return MCSymbolRefExpr :: create ( TM . getSymbol ( LHS ) , MCSymbolRefExpr :: VK_COFF_IMGREL32 , getContext ( ) ) ;


<s> auto * WasmSym = cast < MCSymbolWasm > ( GetExternalSymbolSymbol ( Name ) ) ; if ( WasmSym -> getType ( ) . hasValue ( ) ) return WasmSym ; const <ISA_LIT>Subtarget & Subtarget = getSubtarget ( ) ; if ( Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> || Name == <STR_LIT> ) { bool Mutable = Name == <STR_LIT> || Name == <STR_LIT> ; WasmSym -> setType ( <STR_LIT> ) ; WasmSym -> setGlobalType ( <STR_LIT> { uint8_t ( Subtarget . hasAddr64 ( ) ? <STR_LIT> : <STR_LIT> ) , Mutable } ) ; return WasmSym ; } SmallVector < <STR_LIT> , <NUM_LIT> > Returns ; SmallVector < <STR_LIT> , <NUM_LIT> > Params ; if ( Name == <STR_LIT> ) { WasmSym -> setType ( <STR_LIT> ) ; WasmSym -> setTagType ( { <STR_LIT> , <NUM_LIT> } ) ; WasmSym -> setWeak ( true ) ; WasmSym -> setExternal ( true ) ; Params . push_back ( Subtarget . hasAddr64 ( ) ? <STR_LIT> :: I64 : <STR_LIT> :: I32 ) ; } else { WasmSym -> setType ( <STR_LIT> ) ;

getLibcallSignature ( Subtarget , Name , Returns , Params ) ;


<s> if ( AS != <ISA_LIT>AS :: CONSTANT_ADDRESS && AS != <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) return false ; if ( ! LI . isSimple ( ) ) return false ; auto * Ty = LI . getType ( ) ; if ( Ty -> isAggregateType ( ) ) return false ; unsigned TySize = DL -> getTypeStoreSize ( Ty ) ;

if ( TySize >= <NUM_LIT> ) return false ;


<s> if ( Index == <NUM_LIT> && MRI . getVRegDef ( SrcReg ) -> isImplicitDef ( ) ) { if ( ! emitInsertSubreg ( DstReg , InsertReg , I , MRI , MF ) ) return false ; I . eraseFromParent ( ) ; return true ; } bool HasAVX = STI . hasAVX ( ) ; bool HasAVX512 = STI . hasAVX512 ( ) ; bool HasVLX = STI . hasVLX ( ) ; if ( DstTy . getSizeInBits ( ) == <NUM_LIT> && InsertRegTy . getSizeInBits ( ) == <NUM_LIT> ) { if ( HasVLX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ; else if ( HasAVX ) I . setDesc ( TII . get ( <STR_LIT> ) ) ;


<s> else mem = gen_frame_mem ( DImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( DImode , gen_rtx_REG ( DImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ; dwarf = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j + <NUM_LIT> ) , dwarf ) ; REG_NOTES ( tmp ) = dwarf ; offset += <NUM_LIT> ; j += <NUM_LIT> ; } else if ( j != PC_REGNUM ) { if ( offset > <NUM_LIT> ) mem = gen_frame_mem ( SImode , plus_constant ( Pmode , stack_pointer_rtx , offset ) ) ; else mem = gen_frame_mem ( SImode , stack_pointer_rtx ) ; tmp = gen_rtx_SET ( SImode , gen_rtx_REG ( SImode , j ) , mem ) ; tmp = emit_insn ( tmp ) ; RTX_FRAME_RELATED_P ( tmp ) = <NUM_LIT> ;

REG_NOTES ( tmp ) = alloc_reg_note ( REG_CFA_RESTORE , gen_rtx_REG ( SImode , j ) , NULL_RTX ) ;


<s> return __builtin_mve_vldrwq_z_sv4si ( ( __builtin_neon_si * ) __base , __p ) ;


<s> int nds32_address_cost_impl ( rtx address , machine_mode mode ATTRIBUTE_UNUSED , addr_space_t as ATTRIBUTE_UNUSED , bool speed_p ) { if ( speed_p ) { if ( current_pass -> tv_id == TV_FWPROP ) return nds32_address_cost_speed_fwprop ( address ) ; else return nds32_address_cost_speed_prefer ( address ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return nullptr ; } unsigned InsertOpc , InsSubRegIdx ; std :: tie ( InsertOpc , InsSubRegIdx ) = getInsertVecEltOpInfo ( FPRBank , ScalarTy . getSizeInBits ( ) ) ; if ( ! Dst ) Dst = MRI . createVirtualRegister ( DstRC ) ; auto InsElt = MIRBuilder . buildInstr ( InsertOpc , { * Dst } , { WidenedOp1 -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) . addImm ( <NUM_LIT> ) . addUse ( WidenedOp2 -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( <NUM_LIT> ) ;

constrainSelectedInstRegOperands ( * InsElt , TII , TRI , RBI ) ;


<s> static SDValue CreateCopyOfByValArgument ( SDValue Src , SDValue Dst , SDValue Chain , <STR_LIT> Flags , SelectionDAG & DAG , const SDLoc & dl ) { SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , dl , <STR_LIT> ) ;

return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , true , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> MachineBasicBlock * TBB = MBB -> back ( ) . getOperand ( <NUM_LIT> ) . getMBB ( ) ; assert ( TBB && <STR_LIT> ) ; MBB -> back ( ) . eraseFromParent ( ) ; if ( TBB != infoSucc . MBB ) { MachineInstr * branchMI = BuildMI ( * MBB , MBB -> end ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( predicates [ <NUM_LIT> ] . getImm ( ) ) . addReg ( predicates [ <NUM_LIT> ] . getReg ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * branchMI ) ; } } if ( insertExplicitBranch ) { assert ( MBB -> isSuccessor ( succ ) && <STR_LIT> ) ; MachineInstr * branchMI = TII -> addDefaultPred ( BuildMI ( * MBB , MBB -> end ( ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( succ ) ) ;


<s> SDValue NBits ; const bool CanHaveExtraUses = Subtarget -> hasBMI2 ( ) ; auto checkUses = [ CanHaveExtraUses ] ( SDValue Op , unsigned NUses ) { return CanHaveExtraUses || Op . getNode ( ) -> hasNUsesOfValue ( NUses , Op . getResNo ( ) ) ; } ; auto checkOneUse = [ checkUses ] ( SDValue Op ) { return checkUses ( Op , <NUM_LIT> ) ; } ; auto checkTwoUse = [ checkUses ] ( SDValue Op ) { return checkUses ( Op , <NUM_LIT> ) ; } ; auto matchPatternA = [ & checkOneUse , & NBits ] ( SDValue Mask ) -> bool { if ( Mask -> getOpcode ( ) != <STR_LIT> || ! checkOneUse ( Mask ) ) return false ; if ( ! isAllOnesConstant ( Mask -> getOperand ( <NUM_LIT> ) ) ) return false ; SDValue M0 = Mask -> getOperand ( <NUM_LIT> ) ; if ( M0 -> getOpcode ( ) != <STR_LIT> || ! checkOneUse ( M0 ) ) return false ; if ( ! isOneConstant ( M0 -> getOperand ( <NUM_LIT> ) ) ) return false ; NBits = M0 -> getOperand ( <NUM_LIT> ) ; return true ; } ; auto matchPatternB = [ & checkOneUse , & NBits ] ( SDValue Mask ) -> bool { if ( ! isBitwiseNot ( Mask ) || ! checkOneUse ( Mask ) ) return false ; SDValue M0 = Mask -> getOperand ( <NUM_LIT> ) ; if ( M0 -> getOpcode ( ) != <STR_LIT> || ! checkOneUse ( M0 ) ) return false ; if ( ! isAllOnesConstant ( M0 -> getOperand ( <NUM_LIT> ) ) ) return false ; NBits = M0 -> getOperand ( <NUM_LIT> ) ; return true ; } ; auto matchShiftAmt = [ checkOneUse , Size , & NBits ] ( SDValue ShiftAmt ) { if ( ShiftAmt . getOpcode ( ) == <STR_LIT> ) { ShiftAmt = ShiftAmt . getOperand ( <NUM_LIT> ) ; if ( ! checkOneUse ( ShiftAmt ) ) return false ; } if ( ShiftAmt . getOpcode ( ) != <STR_LIT> ) return false ; auto V0 = dyn_cast < ConstantSDNode > ( ShiftAmt . getOperand ( <NUM_LIT> ) ) ; if ( ! V0 || V0 -> getZExtValue ( ) != Size ) return false ; NBits = ShiftAmt . getOperand ( <NUM_LIT> ) ;


<s> if ( HeadCond . empty ( ) || ! parseCond ( HeadCond , HeadCmp ) ) { continue ; } <STR_LIT> TrueCmp ; if ( TrueCond . empty ( ) || ! parseCond ( TrueCond , TrueCmp ) ) { continue ; } const int HeadImm = ( int ) HeadCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const int TrueImm = ( int ) TrueCmpMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( HeadCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << HeadImm << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ( TrueCmp ) << '\n' ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TrueImm << '\n' ) ; if ( ( ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) || ( HeadCmp == <STR_LIT> && TrueCmp == <STR_LIT> ) ) && std :: abs ( TrueImm - HeadImm ) == <NUM_LIT> ) { CmpInfo HeadCmpInfo = adjustCmp ( HeadCmpMI , HeadCmp ) ;

CmpInfo TrueCmpInfo = adjustCmp ( TrueCmpMI , TrueCmp ) ;


<s> std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( Chain , Op . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , CallingConv :: C , false , true , DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) , Args , DAG , dl ) ; SDValue Ops [ ] = { CallResult . first , CallResult . second } ; return DAG . getMergeValues ( Ops , <NUM_LIT> , dl ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; bool is<ISA_LIT>64 = PtrVT == <STR_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; bool is31 = ( getTargetMachine ( ) . Options . DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> getFnAttributes ( ) . hasAttribute ( Attributes :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) : ( is31 ? <STR_LIT> : <STR_LIT> ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; while ( Depth -- ) FrameAddr = DAG . getLoad ( Op . getValueType ( ) , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; return FrameAddr ;


<s> static enum unwind_info_type bpf_debug_unwind_info ( ) {


<s> const unsigned Reg64 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned Reg32 = RI . getSubReg ( Reg64 , <STR_LIT> ) ; BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , Reg32 ) . addReg ( <STR_LIT> ) . addReg ( Reg64 , RegState :: ImplicitDefine ) ;

BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) , Reg64 ) . addReg ( Reg64 ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> int64_t pos = InstIn . getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( InstIn . getOperand ( <NUM_LIT> ) . isImm ( ) ) ; int64_t size = InstIn . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( size <= <NUM_LIT> ) { if ( pos < <NUM_LIT> ) return ; InstIn . getOperand ( <NUM_LIT> ) . setImm ( pos - <NUM_LIT> ) ; InstIn . setOpcode ( ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; return ; }

assert ( pos < <NUM_LIT> && <STR_LIT> ) ;


<s> void HvxSelector :: selectVAlign ( SDNode * N ) { SDValue Vv = N -> getOperand ( <NUM_LIT> ) ;

SDValue Vu = N -> getOperand ( <NUM_LIT> ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {


<s> for ( unsigned int i = <NUM_LIT> ; i < num_of_st ; i ++ ) emit_insn ( gen_rtx_SET ( st_reg , CONST0_RTX ( XFmode ) ) ) ; for ( unsigned int i = <NUM_LIT> ; i < num_of_st ; i ++ ) { rtx insn ; insn = emit_insn ( gen_rtx_SET ( st_reg , st_reg ) ) ; add_reg_note ( insn , REG_DEAD , st_reg ) ; }


<s> unsigned Opc ; switch ( Op . getOpcode ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> :


<s> MCGNode * getMCGNode ( ) const { return Node ;


<s> OutStreamer . EmitInstruction ( TmpInst0 ) ; Directive . setOpcode ( <STR_LIT> ) ; OutStreamer . EmitInstruction ( Directive ) ; } else { MCInstLowering . LowerUnalignedLoadStore ( MI , MCInsts ) ; for ( SmallVector < MCInst , <NUM_LIT> > :: iterator I = MCInsts . begin ( ) ; I != MCInsts . end ( ) ; ++ I ) OutStreamer . EmitInstruction ( * I ) ; } return ; } if ( ! OutStreamer . hasRawTextSupport ( ) ) {

if ( Opc == <STR_LIT> ) MCInstLowering . LowerCPLOAD ( MI , MCInsts ) ;


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; return ! <STR_LIT> ( MF -> getFunction ( ) . getCallingConv ( ) ) && usesVertexCache ( MI . getOpcode ( ) ) ;


<s> Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( <STR_LIT> ( MO . getImm ( ) ) ) Binary |= <NUM_LIT> << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) {

const MachineOperand & MO = MI . getOperand ( i ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : SelectDS_GWS ( N , IntrID ) ; return ; default : break ;


<s> } ; unsigned Opc = OpcTable [ IsZext ] [ Is64Bit ] ; const TargetRegisterClass * RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; if ( SrcVT . SimpleTy <= <STR_LIT> && RetVT == <STR_LIT> ) { unsigned TmpReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addImm ( <NUM_LIT> ) . addReg ( Op0 , getKillRegState ( Op0IsKill ) ) . addImm ( <STR_LIT> ) ; Op0 = TmpReg ; Op0IsKill = true ; }

return FastEmitInst_rii ( Opc , RC , Op0 , Op0IsKill , ImmR , ImmS ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) >= <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; case <STR_LIT> : return isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; case <STR_LIT> : return ! isUInt < <NUM_LIT> > ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ;


<s> bool useUnsafeMath ( ) const { return UseUnsafeMath ;


<s> if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ;

const MCExpr * Expr = MO . getExpr ( ) ;


<s> else JumpOp = HasR6 ? JIC : JR ; if ( JumpOp == <STR_LIT> && STI -> inMicro<ISA_LIT>Mode ( ) ) JumpOp = <STR_LIT> ; unsigned ATReg = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder Instr = BuildMI ( * MBB , Pos , DL , TII -> get ( JumpOp ) ) . addReg ( ATReg ) ;

if ( AddImm ) Instr . addImm ( <NUM_LIT> ) ;


<s> static int ix86_vec_cost ( machine_mode mode , int cost ) {

if ( ! VECTOR_MODE_P ( mode ) ) return cost ;


<s> Value * NewInst = Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Bitcast -> replaceAllUsesWith ( NewInst ) ; } else { auto * II = dyn_cast < IntrinsicInst > ( Src ) ; if ( ! II ) return false ; Prepare ( ) ; Value * Row = II -> getOperand ( <NUM_LIT> ) ; Value * Col = II -> getOperand ( <NUM_LIT> ) ; std :: array < Value * , <NUM_LIT> > Args = { Row , Col , I8Ptr , Stride , Src } ; Builder . CreateIntrinsic ( <STR_LIT> , None , Args ) ; Value * NewInst = Builder . CreateLoad ( Bitcast -> getType ( ) , AllocaAddr ) ; Bitcast -> replaceAllUsesWith ( NewInst ) ; } return true ;


<s> <ISA_LIT>V9TargetMachine :: <ISA_LIT>V9TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , RM , CM , OL , true ) {


<s> if ( IDVal == <STR_LIT> ) parseDirectiveArch ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCPU ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveWord ( <NUM_LIT> , Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveWord ( <NUM_LIT> , Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveWord ( <NUM_LIT> , Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveTLSDescCall ( Loc ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( Loc ) ;

else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( Loc ) ;


<s> return ( isThumb && ( C & ~ <NUM_LIT> ) == <NUM_LIT> ) || ( ! isThumb && <STR_LIT> ( C ) != - <NUM_LIT> ) ;


<s> return ( CPU . empty ( ) || CPU == <STR_LIT> ) ? <STR_LIT> : CPU ;


<s> virtual const char * getPassName ( ) const {


<s> T * getIfUnordered ( T * MaybeT ) { return MaybeT && MaybeT -> isUnordered ( ) ? MaybeT : nullptr ;


<s> static void UpdateLoopRegisters ( MachineInstr * MI ) { unsigned nop = MI -> getNumOperands ( ) ; if ( isLoopInstr ( MI ) ) { nop = <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> ; i < nop ; i ++ ) { MachineOperand * MO = & MI -> getOperand ( i ) ; if ( MO -> isReg ( ) ) { int lreg = SRegToNumber ( MO -> getReg ( ) ) ; if ( lreg >= <NUM_LIT> && lreg <= <NUM_LIT> ) { unsigned rel = lreg - <NUM_LIT> ; unsigned newcount = TransReg [ rel ] ; assert ( newcount >= <NUM_LIT> && newcount <= <NUM_LIT> ) ; if ( ( unsigned ) lreg != newcount ) { Register nreg = NumberToSReg ( newcount ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : FramePointerSaveIndex ( <NUM_LIT> ) , ReturnAddrSaveIndex ( <NUM_LIT> ) , SpillsCR ( false ) , LRStoreRequired ( false ) , MinReservedArea ( <NUM_LIT> ) , TailCallSPDelta ( <NUM_LIT> ) , HasFastCall ( false ) {


<s> SDValue ShAmt0 = N0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShAmt1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShMsk0 ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( ShAmt0 . getOperand ( <NUM_LIT> ) ) && ShAmt0 . getConstantOperandVal ( <NUM_LIT> ) == ( Bits - <NUM_LIT> ) ) { ShMsk0 = ShAmt0 ; ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; } SDValue ShMsk1 ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( ShAmt1 . getOperand ( <NUM_LIT> ) ) && ShAmt1 . getConstantOperandVal ( <NUM_LIT> ) == ( Bits - <NUM_LIT> ) ) { ShMsk1 = ShAmt1 ; ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; } if ( ShAmt0 . getOpcode ( ) == <STR_LIT> ) ShAmt0 = ShAmt0 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) ShAmt1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> || ShAmt0 . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; std :: swap ( Op0 , Op1 ) ; std :: swap ( ShAmt0 , ShAmt1 ) ; std :: swap ( ShMsk0 , ShMsk1 ) ; } auto GetFunnelShift = [ & DAG , & DL , VT , Opc ] ( SDValue Op0 , SDValue Op1 , SDValue Amt ) { if ( Opc == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; return DAG . getNode ( Opc , DL , VT , Op0 , Op1 , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Amt ) ) ; } ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sum = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( auto * SumC = dyn_cast < ConstantSDNode > ( Sum ) ) { SDValue ShAmt1Op1 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( ShAmt1Op1 . getOperand ( <NUM_LIT> ) ) && ShAmt1Op1 . getConstantOperandVal ( <NUM_LIT> ) == ( Bits - <NUM_LIT> ) ) { ShMsk1 = ShAmt1Op1 ;

ShAmt1Op1 = ShAmt1Op1 . getOperand ( <NUM_LIT> ) ;


<s> case <STR_LIT> : handleSpecialFP ( I ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> , e = DeadRegs . size ( ) ; i != e ; ++ i ) { unsigned Reg = DeadRegs [ i ] ; if ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && isLive ( Reg - <STR_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << Reg - <STR_LIT> << <STR_LIT> ) ; freeStackSlotAfter ( I , Reg - <STR_LIT> ) ; } } DEBUG ( { MachineBasicBlock :: iterator PrevI = PrevMI ; if ( I == PrevI ) { dbgs ( ) << <STR_LIT> ; } else { MachineBasicBlock :: iterator Start = I ; while ( Start != BB . begin ( ) && std :: prev ( Start ) != PrevI ) -- Start ; dbgs ( ) << <STR_LIT> ; Start -> print ( dbgs ( ) ) ; while ( ++ Start != std :: next ( I ) ) {


<s> unsigned RegIndex ; StringRef RegIndexStr = SubRegName . drop_front ( <NUM_LIT> ) ; if ( RegIndexStr . getAsInteger ( <NUM_LIT> , RegIndex ) ) { O << Name ; return ; } if ( SubRegName . front ( ) == 'V' ) O << 'v' ; else if ( SubRegName . front ( ) == 'S' ) O << 's' ; else { O << Name ; return ; }


<s> int msp430_hard_regno_nregs_with_padding ( int regno ATTRIBUTE_UNUSED , machine_mode mode ) { if ( mode == PSImode ) return <NUM_LIT> ;

return msp430_hard_regno_nregs ( regno , mode ) ;


<s> if ( F -> doesNotThrow ( ) ) return false ; if ( F -> getName ( ) == CxaBeginCatchFn || F -> getName ( ) == PersonalityWrapperFn || F -> getName ( ) == ClangCallTerminateFn || F -> getName ( ) == StdTerminateFn ) return false ;


<s> static bool isPromotableZeroStoreOpcode ( MachineInstr * MI ) {

return isPromotableZeroStoreOpcode ( MI -> getOpcode ( ) ) ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Insn ) << <NUM_LIT> ) ) ;


<s> MachineInstr & SrcInst = * Src -> getInstr ( ) ; MachineInstr & DstInst = * Dst -> getInstr ( ) ; if ( Dst -> isBoundaryNode ( ) ) return false ; if ( SrcInst . isPHI ( ) || DstInst . isPHI ( ) ) return false ; SUnit * Best = nullptr ; SUnit * DstBest = nullptr ; SUnit * SrcBest = getZeroLatency ( Dst , Dst -> Preds ) ; if ( SrcBest == nullptr || Src -> NodeNum >= SrcBest -> NodeNum ) { DstBest = getZeroLatency ( Src , Src -> Succs ) ; if ( DstBest == nullptr || Dst -> NodeNum <= DstBest -> NodeNum ) Best = Dst ; } if ( Best != Dst ) return false ; if ( Src == SrcBest && Dst == DstBest ) return true ; if ( SrcBest != nullptr ) changeLatency ( SrcBest , SrcBest -> Succs , Dst , <NUM_LIT> ) ;

if ( DstBest != nullptr ) changeLatency ( Src , Src -> Succs , DstBest , <NUM_LIT> ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const {


<s> if ( ! MI -> getOperand ( OpNo ) . isImm ( ) ) return printOperand ( MI , OpNo , O ) ; O << SignExtend32 < <NUM_LIT> > ( ( unsigned ) MI -> getOperand ( OpNo ) . getImm ( ) << <NUM_LIT> ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , PTM ( tm ) , RI ( tm , * this ) , PST ( * tm . getSubtargetImpl ( ) ) {


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> DEBUG ( CurGroupDbg = Incoming -> CurGroupDbg ; ) ; ProcResourceCounters = Incoming -> ProcResourceCounters ;

CriticalResourceIdx = Incoming -> CriticalResourceIdx ;


<s> case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ;


<s> SDValue Mag = Op . getOperand ( <NUM_LIT> ) ; SDValue Sign = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( Sign . getSimpleValueType ( ) . bitsLT ( VT ) ) Sign = DAG . getNode ( <STR_LIT> , dl , VT , Sign ) ; if ( Sign . getSimpleValueType ( ) . bitsGT ( VT ) ) Sign = DAG . getNode ( <STR_LIT> , dl , VT , Sign , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; bool IsF128 = ( VT == <STR_LIT> ) ; assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; const fltSemantics & Sem = SelectionDAG :: EVTToAPFloatSemantics ( VT ) ; bool IsFakeVector = ! VT . isVector ( ) && ! IsF128 ; MVT LogicVT = VT ; if ( IsFakeVector ) LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned EltSizeInBits = VT . getScalarSizeInBits ( ) ; SDValue SignMask = DAG . getConstantFP ( APFloat ( Sem , APInt :: getSignMask ( EltSizeInBits ) ) , dl , LogicVT ) ; SDValue MagMask = DAG . getConstantFP ( APFloat ( Sem , APInt :: getSignedMaxValue ( EltSizeInBits ) ) , dl , LogicVT ) ; if ( IsFakeVector ) Sign = DAG . getNode ( <STR_LIT> , dl , LogicVT , Sign ) ; SDValue SignBit = DAG . getNode ( <STR_LIT> , dl , LogicVT , Sign , SignMask ) ; SDValue MagBits ; if ( ConstantFPSDNode * Op0CN = isConstOrConstSplatFP ( Mag ) ) { APFloat APF = Op0CN -> getValueAPF ( ) ; APF . clearSign ( ) ; MagBits = DAG . getConstantFP ( APF , dl , LogicVT ) ; } else { if ( IsFakeVector ) Mag = DAG . getNode ( <STR_LIT> , dl , LogicVT , Mag ) ; MagBits = DAG . getNode ( <STR_LIT> , dl , LogicVT , Mag , MagMask ) ; } SDValue Or = DAG . getNode ( <STR_LIT> , dl , LogicVT , MagBits , SignBit ) ;

return ! IsFakeVector ? Or : DAG . getNode ( <STR_LIT> , dl , VT , Or , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;


<s> MachineBasicBlock :: iterator MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { MachineBasicBlock :: iterator NMBBI = std :: next ( MBBI ) ; Modified |= runOnMI ( MBB , MBBI , NMBBI ) ; MBBI = NMBBI ; }


<s> return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false , false ) ;


<s> O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( CS -> getInstruction ( ) ) ; if ( ! llvm :: getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) sz = PtrVT . getSizeInBits ( ) ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } const PointerType * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ;

Type * ETy = PTy -> getElementType ( ) ;


<s> if ( <STR_LIT> . contains ( CSRegs [ i ] ) && ! MF . getRegInfo ( ) . isPhysRegUsed ( CSRegs [ i ] ) ) { ExtraReg = CSRegs [ i ] ; break ; } } if ( ExtraReg != <NUM_LIT> ) { MF . getRegInfo ( ) . setPhysRegUsed ( ExtraReg ) ; } else { assert ( RS && <STR_LIT> ) ; const TargetRegisterClass * RC = & <STR_LIT> ;

RS -> addScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ;


<s> unsigned getTotalNumVGPRs ( ) const { return <NUM_LIT> ;


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( Reg ) ; return ResultReg ;


<s> auto * TLIP = getAnalysisIfAvailable < TargetLibraryInfoWrapperPass > ( ) ; LibInfo = TLIP ? & TLIP -> getTLI ( ) : nullptr ; bool MadeChange = false ; for ( LoopInfo :: iterator I = LI -> begin ( ) , E = LI -> end ( ) ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) << <NUM_LIT> ) ) ;


<s> ( ( struct u8 * ) ptr ) -> data = data ; return data ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( The<ISA_LIT>_64Target ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeWinEHStatePassPass ( PR ) ; initializeFixupBWInstPassPass ( PR ) ;


<s> LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return lowerBR_JT ( Op , DAG ) ; case <STR_LIT> : return lowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerJumpTable ( Op , DAG ) ;

case <STR_LIT> : return lowerSELECT ( Op , DAG ) ;


<s> unsigned getVarArgsFirstGPR ( ) const { return VarArgsFirstGPR ;


<s> unsigned x86cc = ( cc0 == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( Subtarget . hasAVX512 ( ) ) { SDValue FSetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getSimpleValueType ( <NUM_LIT> ) , FSetCC , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } SDValue OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , CMP00 . getValueType ( ) , CMP00 , CMP01 , DAG . getConstant ( x86cc , DL , <STR_LIT> ) ) ; bool is64BitFP = ( CMP00 . getValueType ( ) == <STR_LIT> ) ; MVT IntVT = is64BitFP ? <STR_LIT> : <STR_LIT> ; if ( is64BitFP && ! Subtarget . is64Bit ( ) ) { SDValue Vector64 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OnesOrZeroesF ) ; SDValue Vector32 = DAG . getBitcast ( <STR_LIT> , Vector64 ) ; OnesOrZeroesF = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Vector32 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; IntVT = <STR_LIT> ; }

SDValue OnesOrZeroesI = DAG . getBitcast ( IntVT , OnesOrZeroesF ) ;


<s> static const uint16_t * lookup ( unsigned opcode , unsigned domain ) { for ( const uint16_t ( & Row ) [ <NUM_LIT> ] : ReplaceableInstrs ) if ( Row [ domain - <NUM_LIT> ] == opcode ) return Row ;


<s> if ( Topo . IsReachable ( PredDep . getSUnit ( ) , SuccSU ) ) return false ; Topo . AddPred ( SuccSU , PredDep . getSUnit ( ) ) ; }

SuccSU -> addPred ( PredDep , ! PredDep . isArtificial ( ) ) ;


<s> auto & MF = * MBB . getParent ( ) ; if ( Root . getOpcode ( ) != <STR_LIT> && Root . getOpcode ( ) != <STR_LIT> ) return false ; auto & Op = Root . getOperand ( <NUM_LIT> ) ; const auto & MRI = MF . getRegInfo ( ) ; MachineInstr * GenericAddrDef = nullptr ; if ( Op . isReg ( ) && TargetRegisterInfo :: isVirtualRegister ( Op . getReg ( ) ) ) { GenericAddrDef = MRI . getUniqueVRegDef ( Op . getReg ( ) ) ; } if ( ! GenericAddrDef || GenericAddrDef -> getParent ( ) != & MBB || ( GenericAddrDef -> getOpcode ( ) != <STR_LIT> && GenericAddrDef -> getOpcode ( ) != <STR_LIT> ) ) { return false ; } auto & BaseAddrOp = GenericAddrDef -> getOperand ( <NUM_LIT> ) ; if ( BaseAddrOp . isReg ( ) && BaseAddrOp . getReg ( ) == <STR_LIT> ) { return true ; }


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> int first_reg ; for ( first_reg = <NUM_LIT> ; first_reg <= <NUM_LIT> ; first_reg ++ ) if ( regs_ever_live [ first_reg ] && ( ! call_used_regs [ first_reg ] || ( first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM && ( ( DEFAULT_ABI == ABI_V4 && flag_pic != <NUM_LIT> ) || ( DEFAULT_ABI == ABI_DARWIN && flag_pic ) || ( TARGET_TOC && TARGET_MINIMAL_TOC ) ) ) ) ) break ; if ( flag_pic && current_function_uses_pic_offset_table && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM ) return RS6000_PIC_OFFSET_TABLE_REGNUM ; return first_reg ;


<s> Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; DEBUG ( dbgs ( ) << <STR_LIT> << getPassName ( ) << <STR_LIT> << MF . getName ( ) << '\n' ) ; if ( ! SchedModel . hasInstrSchedModel ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } for ( auto & MBB : MF ) { bool SuppressSTP = false ; unsigned PrevBaseReg = <NUM_LIT> ; for ( auto & MI : MBB ) { if ( ! isNarrowFPStore ( MI ) ) continue ; unsigned BaseReg ; int64_t Offset ; if ( TII -> getMemOpBaseRegImmOfs ( & MI , BaseReg , Offset , TRI ) ) { if ( PrevBaseReg == BaseReg ) { if ( ! SuppressSTP && shouldAddSTPToBlock ( MI . getParent ( ) ) ) break ; DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; SuppressSTP = true ; TII -> suppressLdStPair ( & MI ) ; } PrevBaseReg = BaseReg ; } else PrevBaseReg = <NUM_LIT> ; } }


<s> SmallVector < unsigned , <NUM_LIT> > DefsA ; SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( TargetRegisterInfo :: isPhysicalRegister ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ; if ( TargetRegisterInfo :: isPhysicalRegister ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegA == * SubRegs ) return true ;


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return <STR_LIT> ;


<s> EVT VT = Op . getValueType ( ) ; return VT . getSizeInBits ( ) - DAG . ComputeNumSignBits ( Op ) ;


<s> } switch ( SVT ) { case <STR_LIT> : case <STR_LIT> : if ( Fast ) * Fast = true ; return true ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) {


<s> Abbv = std :: make_shared < BitCodeAbbrev > ( ) ; Abbv -> Add ( BitCodeAbbrevOp ( bitc :: TYPE_CODE_STRUCT_ANON ) ) ; Abbv -> Add ( BitCodeAbbrevOp ( BitCodeAbbrevOp :: Fixed , <NUM_LIT> ) ) ; Abbv -> Add ( BitCodeAbbrevOp ( BitCodeAbbrevOp :: Array ) ) ; Abbv -> Add ( BitCodeAbbrevOp ( BitCodeAbbrevOp :: Fixed , NumBits ) ) ; unsigned StructAnonAbbrev = Stream . EmitAbbrev ( std :: move ( Abbv ) ) ; Abbv = std :: make_shared < BitCodeAbbrev > ( ) ; Abbv -> Add ( BitCodeAbbrevOp ( bitc :: TYPE_CODE_STRUCT_NAME ) ) ; Abbv -> Add ( BitCodeAbbrevOp ( BitCodeAbbrevOp :: Array ) ) ; Abbv -> Add ( BitCodeAbbrevOp ( BitCodeAbbrevOp :: Char6 ) ) ; unsigned StructNameAbbrev = Stream . EmitAbbrev ( std :: move ( Abbv ) ) ; Abbv = std :: make_shared < BitCodeAbbrev > ( ) ; Abbv -> Add ( BitCodeAbbrevOp ( bitc :: TYPE_CODE_STRUCT_NAMED ) ) ; Abbv -> Add ( BitCodeAbbrevOp ( BitCodeAbbrevOp :: Fixed , <NUM_LIT> ) ) ; Abbv -> Add ( BitCodeAbbrevOp ( BitCodeAbbrevOp :: Array ) ) ; Abbv -> Add ( BitCodeAbbrevOp ( BitCodeAbbrevOp :: Fixed , NumBits ) ) ; unsigned StructNamedAbbrev = Stream . EmitAbbrev ( std :: move ( Abbv ) ) ; Abbv = std :: make_shared < BitCodeAbbrev > ( ) ; Abbv -> Add ( BitCodeAbbrevOp ( bitc :: TYPE_CODE_ARRAY ) ) ; Abbv -> Add ( BitCodeAbbrevOp ( BitCodeAbbrevOp :: VBR , <NUM_LIT> ) ) ; Abbv -> Add ( BitCodeAbbrevOp ( BitCodeAbbrevOp :: Fixed , NumBits ) ) ; unsigned ArrayAbbrev = Stream . EmitAbbrev ( std :: move ( Abbv ) ) ; TypeVals . push_back ( TypeList . size ( ) ) ; Stream . EmitRecord ( bitc :: TYPE_CODE_NUMENTRY , TypeVals ) ; TypeVals . clear ( ) ; for ( Type * T : TypeList ) { int AbbrevToUse = <NUM_LIT> ; unsigned Code = <NUM_LIT> ; switch ( T -> getTypeID ( ) ) { case Type :: BFloatTyID : case Type :: X86_AMXTyID : case Type :: TokenTyID : case Type :: <ISA_LIT>PointerTyID : llvm_unreachable ( <STR_LIT> ) ; break ; case Type :: VoidTyID : Code = bitc :: TYPE_CODE_VOID ; break ; case Type :: HalfTyID : Code = bitc :: TYPE_CODE_HALF ;


<s> unsigned CCMask = Pred [ <NUM_LIT> ] . getImm ( ) ; unsigned Opc ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( STI . hasLoadStoreOnCond2 ( ) ) Opc = <STR_LIT> ; else { Opc = <STR_LIT> ; MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ; unsigned TReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned FReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( TargetOpcode :: COPY ) , TReg ) . addReg ( TrueReg ) ; BuildMI ( MBB , I , DL , get ( TargetOpcode :: COPY ) , FReg ) . addReg ( FalseReg ) ; TrueReg = TReg ; FalseReg = FReg ; }

} else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ;


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>Z80 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; i ++ ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; }


<s> } break ; case <STR_LIT> : { SDValue Op0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOpcode ( ) != <STR_LIT> ) || ( Subtarget -> hasLoadStoreOnCond2 ( ) && Node -> getValueType ( <NUM_LIT> ) . isInteger ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op1 ) -> getSExtValue ( ) ) && ! ( Op0 . getOpcode ( ) == <STR_LIT> && isInt < <NUM_LIT> > ( cast < ConstantSDNode > ( Op0 ) -> getSExtValue ( ) ) ) ) ) { SDValue CCValid = Node -> getOperand ( <NUM_LIT> ) ; SDValue CCMask = Node -> getOperand ( <NUM_LIT> ) ; uint64_t ConstCCValid = cast < ConstantSDNode > ( CCValid . getNode ( ) ) -> getZExtValue ( ) ; uint64_t ConstCCMask = cast < ConstantSDNode > ( CCMask . getNode ( ) ) -> getZExtValue ( ) ; CCMask = CurDAG -> getConstant ( ConstCCValid ^ ConstCCMask , SDLoc ( Node ) , CCMask . getValueType ( ) ) ; SDValue Op4 = Node -> getOperand ( <NUM_LIT> ) ; SDNode * UpdatedNode = CurDAG -> UpdateNodeOperands ( Node , Op1 , Op0 , CCValid , CCMask , Op4 ) ; if ( UpdatedNode != Node ) { ReplaceNode ( Node , UpdatedNode ) ; Node = UpdatedNode ; } } break ; } case <STR_LIT> : { EVT VT = Node -> getValueType ( <NUM_LIT> ) ; unsigned ElemBitSize = VT . getScalarSizeInBits ( ) ; if ( ElemBitSize == <NUM_LIT> ) { if ( tryGather ( Node , <STR_LIT> ) ) return ; } else if ( ElemBitSize == <NUM_LIT> ) { if ( tryGather ( Node , <STR_LIT> ) ) return ; } break ; } case <STR_LIT> : { auto * BVN = cast < BuildVectorSDNode > ( Node ) ; <ISA_LIT>VectorConstantInfo VCI ( BVN ) ; if ( VCI . isVectorConstantLegal ( * Subtarget ) ) { loadVectorConstant ( VCI , Node ) ; return ; } break ; } case <STR_LIT> : { APFloat Imm = cast < ConstantFPSDNode > ( Node ) -> getValueAPF ( ) ; if ( Imm . isZero ( ) || Imm . isNegZero ( ) ) break ; <ISA_LIT>VectorConstantInfo VCI ( Imm ) ; bool Success = VCI . isVectorConstantLegal ( * Subtarget ) ; ( void ) Success ; assert ( Success && <STR_LIT> ) ; loadVectorConstant ( VCI , Node ) ;


<s> for ( MachineBasicBlock :: const_iterator I = MBB . getFirstTerminator ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , & TRI ) ) return true ; }


<s> switch ( CC ) { default : llvm_unreachable ( <STR_LIT> ) ; case CallingConv :: Fast : ( void ) RetFastCC_<ISA_LIT>_APCS ; ( void ) FastCC_<ISA_LIT>_APCS ; case CallingConv :: C : if ( Subtarget -> isAAPCS_ABI ( ) ) { if ( Subtarget -> hasVFP2 ( ) && FloatABIType == FloatABI :: Hard ) return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; else return ( Return ? RetCC_<ISA_LIT>_AAPCS : CC_<ISA_LIT>_AAPCS ) ; } else return ( Return ? RetCC_<ISA_LIT>_APCS : CC_<ISA_LIT>_APCS ) ; case CallingConv :: <ISA_LIT>_AAPCS_VFP : return ( Return ? RetCC_<ISA_LIT>_AAPCS_VFP : CC_<ISA_LIT>_AAPCS_VFP ) ; case CallingConv :: <ISA_LIT>_AAPCS :


<s> if ( Subtarget . has<ISA_LIT>64 ( ) ) return <STR_LIT> ; return <STR_LIT> ;


<s> bool isInstAtomic ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> unsigned indexOffset = CheckEven ? <NUM_LIT> : <NUM_LIT> ; if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , indexOffset , <NUM_LIT> ) ; else if ( ShuffleKind == <NUM_LIT> ) return isVMerge ( N , indexOffset , <NUM_LIT> ) ; else return false ;


<s> fprintf ( stderr , <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> ) ; debug_rtx ( addr ) ;


<s> } else { SB . prepare ( ) ; unsigned SubKillState = getKillRegState ( ( SB . NumSubRegs == <NUM_LIT> ) && SB . IsKill ) ; auto PVD = SB . getPerVGPRData ( ) ; for ( unsigned Offset = <NUM_LIT> ; Offset < PVD . NumVGPRs ; ++ Offset ) { unsigned TmpVGPRFlags = RegState :: Undef ; for ( unsigned i = Offset * PVD . PerVGPR , e = std :: min ( ( Offset + <NUM_LIT> ) * PVD . PerVGPR , SB . NumSubRegs ) ; i < e ; ++ i ) { Register SubReg = SB . NumSubRegs == <NUM_LIT> ? SB . SuperReg : Register ( getSubReg ( SB . SuperReg , SB . SplitParts [ i ] ) ) ; MachineInstrBuilder WriteLane = BuildMI ( * SB . MBB , MI , SB . DL , SB . TII . get ( <STR_LIT> ) , SB . TmpVGPR ) . addReg ( SubReg , SubKillState ) . addImm ( i % PVD . PerVGPR ) . addReg ( SB . TmpVGPR , TmpVGPRFlags ) ; TmpVGPRFlags = <NUM_LIT> ; if ( LIS ) { if ( i == <NUM_LIT> ) LIS -> ReplaceMachineInstrInMaps ( * MI , * WriteLane ) ; else LIS -> InsertMachineInstrInMaps ( * WriteLane ) ; } if ( SB . NumSubRegs > <NUM_LIT> ) { unsigned SuperKillState = <NUM_LIT> ; if ( i + <NUM_LIT> == SB . NumSubRegs ) SuperKillState |= getKillRegState ( SB . IsKill ) ; WriteLane . addReg ( SB . SuperReg , RegState :: Implicit | SuperKillState ) ; } } SB . readWriteTmpVGPR ( Offset , false ) ; } SB . restore ( ) ; } MI -> eraseFromParent ( ) ; SB . MFI . addToSpilledSGPRs ( SB . NumSubRegs ) ; if ( LIS ) LIS -> removeAllRegUnitsForPhysReg ( SB . SuperReg ) ;


<s> void addMemThumbRIs2Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; if ( ! Memory . OffsetImm ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) / <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: createExpr ( Memory . OffsetImm ) ) ;


<s> SDValue Src = N -> getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Src . getValueType ( ) == <STR_LIT> ) { APInt KnownUndef , KnownZero ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedElts = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; if ( TLI . SimplifyDemandedVectorElts ( Src , DemandedElts , KnownUndef , KnownZero , DCI ) ) { if ( N -> getOpcode ( ) != <STR_LIT> ) DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } if ( IsStrict ) return SDValue ( ) ; if ( <STR_LIT> ( Src . getNode ( ) ) && Src . hasOneUse ( ) ) {

LoadSDNode * LN = cast < LoadSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>MCInstLower :: Initialize ( MCContext * C ) {


<s> } } else if ( N . getOpcode ( ) == <STR_LIT> ) { short imm = <NUM_LIT> ; if ( isIntS16Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) && ( imm & <NUM_LIT> ) == <NUM_LIT> ) { APInt LHSKnownZero , LHSKnownOne ; DAG . ComputeMaskedBits ( N . getOperand ( <NUM_LIT> ) , LHSKnownZero , LHSKnownOne ) ; if ( ( LHSKnownZero . getZExtValue ( ) | ~ ( uint64_t ) imm ) == ~ <NUM_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; Disp = DAG . getTargetConstant ( ( ( int ) imm & <NUM_LIT> ) >> <NUM_LIT> , <STR_LIT> ) ; return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { if ( ( CN -> getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) { short Imm ; if ( isIntS16Immediate ( CN , Imm ) ) { Disp = DAG . getTargetConstant ( ( unsigned short ) Imm >> <NUM_LIT> , getPointerTy ( ) ) ; Base = DAG . getRegister ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> || ( int64_t ) CN -> getZExtValue ( ) == ( int ) CN -> getZExtValue ( ) ) {

int Addr = ( int ) CN -> getZExtValue ( ) ;


<s> __v4su result ; rshift = vec_splat ( ( __v4su ) __B , <NUM_LIT> ) ; rshift = vec_splat ( ( __v4su ) __B , <NUM_LIT> ) ; shmask = rshift < shmax ; result = vec_vsrw ( ( __v4su ) __A , rshift ) ;

result = vec_sel ( shmask , result , shmask ) ;


<s> <ISA_LIT>XCOFFObjectWriter :: <ISA_LIT>XCOFFObjectWriter ( bool Is64Bit ) : MCXCOFFObjectTargetWriter ( Is64Bit ) {


<s> } else if ( BranchInst * BI = dyn_cast < BranchInst > ( BB -> getTerminator ( ) ) ) { ConstantInt * BoolTrue = ConstantInt :: getTrue ( F . getContext ( ) ) ; if ( DummyReturnBB == nullptr ) { DummyReturnBB = BasicBlock :: Create ( F . getContext ( ) , <STR_LIT> , & F ) ; Type * RetTy = F . getReturnType ( ) ; Value * RetVal = RetTy -> isVoidTy ( ) ? nullptr : UndefValue :: get ( RetTy ) ; ReturnInst :: Create ( F . getContext ( ) , RetVal , DummyReturnBB ) ; ReturningBlocks . push_back ( DummyReturnBB ) ; } if ( BI -> isUnconditional ( ) ) { BasicBlock * LoopHeaderBB = BI -> getSuccessor ( <NUM_LIT> ) ; BI -> eraseFromParent ( ) ; BranchInst :: Create ( LoopHeaderBB , DummyReturnBB , BoolTrue , BB ) ; } else { BasicBlock * TransitionBB = BasicBlock :: Create ( F . getContext ( ) , <STR_LIT> , & F ) ; BI -> removeFromParent ( ) ; TransitionBB -> getInstList ( ) . push_back ( BI ) ;

BranchInst :: Create ( TransitionBB , DummyReturnBB , BoolTrue , BB ) ;


<s> switch ( Opcode ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( current_function_decl ) ) || ( cfun -> machine -> callee_saved_first_gpr_regno == SP_REGNUM && cfun -> machine -> callee_saved_last_gpr_regno == SP_REGNUM && ! df_regs_ever_live_p ( FP_REGNUM ) && ! df_regs_ever_live_p ( LP_REGNUM ) && cfun -> machine -> local_size == <NUM_LIT> ) ) { cfun -> machine -> naked_p = <NUM_LIT> ; cfun -> machine -> fp_size = <NUM_LIT> ; cfun -> machine -> gp_size = <NUM_LIT> ; cfun -> machine -> lp_size = <NUM_LIT> ; if ( flag_stack_usage_info ) current_function_static_stack_size = <NUM_LIT> ; return ; } if ( TARGET_V3PUSH && ! nds32_isr_function_p ( current_function_decl ) && ( cfun -> machine -> va_args_size == <NUM_LIT> ) ) { cfun -> machine -> fp_size = <NUM_LIT> ; cfun -> machine -> gp_size = <NUM_LIT> ; cfun -> machine -> lp_size = <NUM_LIT> ; cfun -> machine -> callee_saved_first_gpr_regno = <NUM_LIT> ; if ( cfun -> machine -> callee_saved_last_gpr_regno <= <NUM_LIT> ) { cfun -> machine -> callee_saved_last_gpr_regno = <NUM_LIT> ; } else if ( cfun -> machine -> callee_saved_last_gpr_regno <= <NUM_LIT> ) { cfun -> machine -> callee_saved_last_gpr_regno = <NUM_LIT> ; } else if ( cfun -> machine -> callee_saved_last_gpr_regno <= <NUM_LIT> ) { cfun -> machine -> callee_saved_last_gpr_regno = <NUM_LIT> ; } else if ( cfun -> machine -> callee_saved_last_gpr_regno <= <NUM_LIT> ) { cfun -> machine -> callee_saved_last_gpr_regno = <NUM_LIT> ; } else if ( cfun -> machine -> callee_saved_last_gpr_regno == SP_REGNUM ) { cfun -> machine -> callee_saved_last_gpr_regno = <NUM_LIT> ; } else { gcc_unreachable ( ) ; } } if ( cfun -> machine -> callee_saved_last_gpr_regno != SP_REGNUM ) { cfun -> machine -> callee_saved_gpr_regs_size = <NUM_LIT> * ( cfun -> machine -> callee_saved_last_gpr_regno - cfun -> machine -> callee_saved_first_gpr_regno + <NUM_LIT> ) ; } block_size = cfun -> machine -> fp_size + cfun -> machine -> gp_size + cfun -> machine -> lp_size + cfun -> machine -> callee_saved_gpr_regs_size ; if ( ! NDS32_DOUBLE_WORD_ALIGN_P ( block_size ) ) {

cfun -> machine -> callee_saved_area_gpr_padding_bytes = NDS32_ROUND_UP_DOUBLE_WORD ( block_size ) - block_size ;


<s> else fputs ( <STR_LIT> , file ) ; output_addr_const ( file , x ) ; fputs ( <STR_LIT> , file ) ;


<s> bool <ISA_LIT>AbstractMemberAccess :: transformGEPChain ( Module & M , CallInst * Call , uint32_t Kind ) { std :: string AccessStr , AccessKey ; MDNode * TypeMeta = nullptr ; Value * Base = computeBaseAndAccessStr ( Call , AccessStr , AccessKey , Kind , TypeMeta ) ; if ( ! Base ) return false ; BasicBlock * BB = Call -> getParent ( ) ; GlobalVariable * GV ; if ( GEPGlobals . find ( AccessKey ) == GEPGlobals . end ( ) ) { GV = new GlobalVariable ( M , Type :: getInt64Ty ( BB -> getContext ( ) ) , false , GlobalVariable :: ExternalLinkage , NULL , AccessStr ) ; GV -> addAttribute ( <STR_LIT> ) ; if ( TypeMeta ) GV -> setMetadata ( LLVMContext :: MD_preserve_access_index , TypeMeta ) ; GEPGlobals [ AccessKey ] = GV ; } else { GV = GEPGlobals [ AccessKey ] ; } auto * LDInst = new LoadInst ( Type :: getInt64Ty ( BB -> getContext ( ) ) , GV ) ; BB -> getInstList ( ) . insert ( Call -> getIterator ( ) , LDInst ) ; auto * BCInst = new BitCastInst ( Base , Type :: getInt8PtrTy ( BB -> getContext ( ) ) ) ; BB -> getInstList ( ) . insert ( Call -> getIterator ( ) , BCInst ) ; auto * GEP = GetElementPtrInst :: Create ( Type :: getInt8Ty ( BB -> getContext ( ) ) , BCInst , LDInst ) ; BB -> getInstList ( ) . insert ( Call -> getIterator ( ) , GEP ) ; auto * BCInst2 = new BitCastInst ( GEP , Call -> getType ( ) ) ; BB -> getInstList ( ) . insert ( Call -> getIterator ( ) , BCInst2 ) ;

Call -> replaceAllUsesWith ( BCInst2 ) ;


<s> if ( ScratchWaveOffsetReg == TRI -> reservedPrivateSegmentWaveByteOffsetReg ( MF ) ) { MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned NumPreloaded = MFI -> getNumPreloadedSGPRs ( ) ; for ( MCPhysReg Reg : getAllSGPRs ( ) . drop_back ( <NUM_LIT> ) . slice ( NumPreloaded ) ) { if ( ! MRI . isPhysRegUsed ( Reg ) ) { if ( ! MRI . isAllocatable ( Reg ) || TRI -> isSubRegisterEq ( ScratchRsrcReg , Reg ) ) continue ; MRI . replaceRegWith ( ScratchWaveOffsetReg , Reg ) ; ScratchWaveOffsetReg = Reg ; MFI -> setScratchWaveOffsetReg ( ScratchWaveOffsetReg ) ; break ; } } } } assert ( ! TRI -> isSubRegister ( ScratchRsrcReg , ScratchWaveOffsetReg ) ) ; const MCInstrDesc & SMovB32 = TII -> get ( <STR_LIT> ) ; DebugLoc DL ; if ( PreloadedScratchWaveOffsetReg != ScratchWaveOffsetReg ) { BuildMI ( MBB , I , DL , SMovB32 , ScratchWaveOffsetReg ) . addReg ( PreloadedScratchWaveOffsetReg , RegState :: Kill ) ; } if ( ST . isAmdHsaOS ( ) ) { assert ( ! TRI -> isSubRegisterEq ( PreloadedPrivateBufferReg , ScratchRsrcReg ) && ! TRI -> isSubRegisterEq ( PreloadedPrivateBufferReg , ScratchWaveOffsetReg ) ) ; unsigned Rsrc01 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; unsigned Rsrc23 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; unsigned Lo = TRI -> getSubReg ( PreloadedPrivateBufferReg , <STR_LIT> ) ; unsigned Hi = TRI -> getSubReg ( PreloadedPrivateBufferReg , <STR_LIT> ) ; const MCInstrDesc & SMovB64 = TII -> get ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , SMovB64 , Rsrc01 ) . addReg ( Lo , RegState :: Kill ) ; BuildMI ( MBB , I , DL , SMovB64 , Rsrc23 ) . addReg ( Hi , RegState :: Kill ) ; } else { unsigned Rsrc0 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; unsigned Rsrc1 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; unsigned Rsrc2 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; unsigned Rsrc3 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; uint64_t Rsrc23 = TII -> getScratchRsrcWords23 ( ) ; BuildMI ( MBB , I , DL , SMovB32 , Rsrc0 ) . addExternalSymbol ( <STR_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; BuildMI ( MBB , I , DL , SMovB32 , Rsrc1 ) . addExternalSymbol ( <STR_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ;

BuildMI ( MBB , I , DL , SMovB32 , Rsrc2 ) . addImm ( Rsrc23 & <NUM_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ;


<s> inline bool is_so_imm_not ( unsigned Imm ) const {

return <STR_LIT> ( ~ Imm ) != - <NUM_LIT> ;


<s> switch ( DefMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : if ( DefMI -> findRegisterDefOperandIdx ( <STR_LIT> , true ) == - <NUM_LIT> ) return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : if ( ! DefMI -> getOperand ( <NUM_LIT> ) . isImm ( ) || DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> || DefMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; SrcOpNum = <NUM_LIT> ; Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : { unsigned ZReg = removeCopies ( MRI , DefMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ZReg != <STR_LIT> && ZReg != <STR_LIT> ) return <NUM_LIT> ; SrcOpNum = <NUM_LIT> ; Opc = Is64Bit ? <STR_LIT> : <STR_LIT> ;


<s> uint32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> case LT : case UNLT : if ( code == LT && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , const1_rtx ) ) ; intcmp_mode = CCmode ; code = EQ ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , const1_rtx ) ) ; code = NE ; } break ; case GE : case UNGE : if ( code == GE || ! TARGET_IEEE_FP ) { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = EQ ; } else { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_xorqi_cc_ext_1 ( scratch , scratch , const1_rtx ) ) ; code = NE ; } break ; case LE : case UNLE : if ( code == LE && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_addqi_ext_1 ( scratch , scratch , constm1_rtx ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; intcmp_mode = CCmode ; code = LTU ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = NE ; } break ; case EQ : case UNEQ : if ( code == EQ && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_cmpqi_ext_3 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; intcmp_mode = CCmode ; code = EQ ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = NE ; } break ; case NE : case LTGT : if ( code == NE && TARGET_IEEE_FP ) { emit_insn ( gen_andqi_ext_0 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_xorqi_cc_ext_1 ( scratch , scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = NE ; } else { emit_insn ( gen_testqi_ext_ccno_0 ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; code = EQ ; } break ; case UNORDERED :


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X ;


<s> return true ; } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } if ( Reg == <STR_LIT> && Reg1 == <STR_LIT> ) { Reg = <STR_LIT> ; RegWidth = <NUM_LIT> ; return true ; } return false ; case IS_VGPR : case IS_SGPR : case IS_TTMP : if ( Reg1 != Reg + RegWidth ) { return false ; } RegWidth ++ ; return true ; default :


<s> if ( ! Section ) { getStreamer ( ) . InitSections ( false ) ; Section = getStreamer ( ) . getCurrentSection ( ) . first ; } if ( Section -> UseCodeAlign ( ) ) getStreamer ( ) . EmitCodeAlignment ( <NUM_LIT> , <NUM_LIT> ) ; else getStreamer ( ) . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ;


<s> case <STR_LIT> : switch ( * RelocPos >> <NUM_LIT> ) { case <NUM_LIT> : idx = & GOTBase [ GOToffset * <NUM_LIT> ] - ( unsigned char * ) RelocPos ; idx = getUpper16 ( idx ) ; DOUT << <STR_LIT> << idx << <STR_LIT> ; gpdistmap [ std :: make_pair ( Function , MR -> getConstantVal ( ) ) ] = RelocPos ; break ; case <NUM_LIT> : assert ( gpdistmap [ std :: make_pair ( Function , MR -> getConstantVal ( ) ) ] && <STR_LIT> ) ; idx = & GOTBase [ GOToffset * <NUM_LIT> ] - ( unsigned char * ) gpdistmap [ std :: make_pair ( Function , MR -> getConstantVal ( ) ) ] ; idx = getLower16 ( idx ) ; DOUT << <STR_LIT> << idx << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } break ; case <STR_LIT> : { idx = ( ( ( unsigned char * ) MR -> getResultPointer ( ) - ( unsigned char * ) RelocPos ) >> <NUM_LIT> ) + <NUM_LIT> ; * RelocPos |= ( idx & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ) ; doCommon = false ; break ; } } if ( doCommon ) { short x = ( short ) idx ; assert ( x == idx ) ; * ( short * ) RelocPos = x ; } }


<s> SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; SDValue M = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; M = DAG . getNode ( <STR_LIT> , dl , VT , R , M ) ; M = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , M , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; R = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , R , M , Op ) ; Op = DAG . getNode ( <STR_LIT> , dl , VT , Op , Op ) ; C = ConstantVector :: get ( CVM2 ) ; CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) , <NUM_LIT> ) ; M = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ; M = DAG . getNode ( <STR_LIT> , dl , VT , R , M ) ;


<s> if ( count == <NUM_LIT> || ( count * ix86_cost -> add <= ix86_cost -> shift_const && ! optimize_insn_for_size_p ( ) ) ) { insn = mode == DImode ? gen_addsi3 : gen_adddi3 ; while ( count -- > <NUM_LIT> ) emit_insn ( insn ( operand , operand , operand ) ) ; } else { insn = mode == DImode ? gen_ashlsi3 : gen_ashldi3 ;

emit_insn ( insn ( operand , operand , GEN_INT ( count ) ) ) ;


<s> bool <ISA_LIT>FrameLowering :: shouldInlineCSR ( const MachineFunction & MF , const CSIVect & CSI ) const { if ( MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> hasEHReturn ( ) ) return true ; if ( ! hasFP ( MF ) ) return true ; if ( ! isOptSize ( MF ) && ! isMinSize ( MF ) ) if ( MF . getTarget ( ) . getOptLevel ( ) > CodeGenOpt :: Default ) return true ; BitVector Regs ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , n = CSI . size ( ) ; i < n ; ++ i ) { unsigned R = CSI [ i ] . getReg ( ) ; if ( ! <STR_LIT> . contains ( R ) ) return true ; Regs [ R ] = true ;


<s> if ( type == error_mark_node ) return NULL_TREE ;

return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) ;


<s> MachineIRBuilder & Builder = Helper . MIRBuilder ; const MachineInstr * Base = getOpcodeDef ( G_JUMP_TABLE , MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; assert ( Base && <STR_LIT> ) ; assert ( MI . getOperand ( <NUM_LIT> ) . isJTI ( ) ) ; assert ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) == Base -> getOperand ( <NUM_LIT> ) . getIndex ( ) && <STR_LIT> ) ; Register Offset = Builder . buildTrunc ( S8 , MI . getOperand ( <NUM_LIT> ) ) . getReg ( <NUM_LIT> ) ; Register LoAddr = MRI . createGenericVirtualRegister ( S8 ) ; Builder . buildInstr ( <STR_LIT> ) . addDef ( LoAddr ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addUse ( Offset ) ; Register HiAddr = MRI . createGenericVirtualRegister ( S8 ) ;

Builder . buildInstr ( <STR_LIT> ) . addDef ( HiAddr ) . addJumpTableIndex ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) , <STR_LIT> ) . addUse ( Offset ) ;


<s> MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; EVT ValTy = Op -> getValueType ( <NUM_LIT> ) ; int FI = MFI -> CreateFixedObject ( Op . getValueSizeInBits ( ) / <NUM_LIT> , <NUM_LIT> , false ) ; SDValue InArgsAddr = DAG . getFrameIndex ( FI , ValTy ) ;

return DAG . getNode ( <STR_LIT> , Op -> getDebugLoc ( ) , ValTy , InArgsAddr , DAG . getConstant ( <NUM_LIT> , ValTy ) ) ;


<s> case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : case Instruction :: And : case Instruction :: Or : case Instruction :: Xor : case Instruction :: ICmp : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr :


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Scale < <NUM_LIT> ) Scale = - Scale ; if ( Scale == <NUM_LIT> ) return true ; return isPowerOf2_32 ( Scale & ~ <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= <NUM_LIT> ) return true ; return false ; case <STR_LIT> : if ( Scale & <NUM_LIT> ) return false ;


<s> void <ISA_LIT>InstPrinter :: printZPRasFPR32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) {

unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ;


<s> const TargetFrameLowering * TFL = Subtarget . getFrameLowering ( ) ; assert ( Size && <STR_LIT> ) ; Alignment = std :: min ( Alignment , TFL -> getStackAlign ( ) ) ; unsigned FirstReg = <NUM_LIT> ; unsigned NumRegs = <NUM_LIT> ; if ( State -> getCallingConv ( ) != CallingConv :: Fast ) { unsigned RegSizeInBytes = Subtarget . getGPRSizeInBytes ( ) ; ArrayRef < MCPhysReg > IntArgRegs = ABI . GetByValArgRegs ( ) ; const MCPhysReg * ShadowRegs = ABI . IsO32 ( ) ? IntArgRegs . data ( ) : <ISA_LIT>64DPRegs ; assert ( Alignment >= Align ( RegSizeInBytes ) && <STR_LIT> ) ; FirstReg = State -> getFirstUnallocated ( IntArgRegs ) ; if ( ( Alignment > RegSizeInBytes ) && ( FirstReg % <NUM_LIT> ) ) { State -> AllocateReg ( IntArgRegs [ FirstReg ] , ShadowRegs [ FirstReg ] ) ; ++ FirstReg ; } Size = alignTo ( Size , RegSizeInBytes ) ; for ( unsigned I = FirstReg ; Size > <NUM_LIT> && ( I < IntArgRegs . size ( ) ) ; Size -= RegSizeInBytes , ++ I , ++ NumRegs ) State -> AllocateReg ( IntArgRegs [ I ] , ShadowRegs [ I ] ) ; } State -> addInRegsParamInfo ( FirstReg , FirstReg + NumRegs ) ;


<s> else { assert ( LdSt -> mayStore ( ) ) ; int Data0Idx = <STR_LIT> ( Opc , <STR_LIT> :: data0 ) ; EltSize = getOpRegClass ( * LdSt , Data0Idx ) -> getSize ( ) ; } if ( isStride64 ( Opc ) ) EltSize *= <NUM_LIT> ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: addr ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = EltSize * Offset0 ; return true ; } return false ; } if ( isMUBUF ( Opc ) || isMTBUF ( Opc ) ) { if ( <STR_LIT> ( Opc , <STR_LIT> :: soffset ) != - <NUM_LIT> ) return false ; const MachineOperand * AddrReg = getNamedOperand ( * LdSt , <STR_LIT> :: vaddr ) ; if ( ! AddrReg ) return false ; const MachineOperand * OffsetImm = getNamedOperand ( * LdSt , <STR_LIT> :: offset ) ; BaseReg = AddrReg -> getReg ( ) ; Offset = OffsetImm -> getImm ( ) ; return true ; } if ( isSMRD ( Opc ) ) {


<s> Register VOffset = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SOffset = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CachePolicy = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned ImmOffset ; std :: tie ( VOffset , ImmOffset ) = splitBufferOffsets ( B , VOffset ) ; const bool Offen = ! isZero ( VOffset , MRI ) ; unsigned Opc = <STR_LIT> ; switch ( <NUM_LIT> * MemSize ) { case <NUM_LIT> : Opc = Offen ? <STR_LIT> : <STR_LIT> ; break ; case <NUM_LIT> : Opc = Offen ? <STR_LIT> : <STR_LIT> ; break ; default : Opc = Offen ? <STR_LIT> : <STR_LIT> ;

if ( Size > <NUM_LIT> ) Opc = <STR_LIT> ( Opc , Size / <NUM_LIT> ) ;


<s> static MachineOperand makeImplicit ( const MachineOperand & MO ) { MachineOperand NewMO = MO ; NewMO . setImplicit ( ) ;


<s> StringRef getExecutionModelName ( ExecutionModel e ) { switch ( e ) {

CASE ( ExecutionModel , Vertex ) CASE ( ExecutionModel , TessellationControl ) CASE ( ExecutionModel , TessellationEvaluation ) CASE ( ExecutionModel , Geometry ) CASE ( ExecutionModel , Fragment ) CASE ( ExecutionModel , GLCompute ) CASE ( ExecutionModel , Kernel ) CASE ( ExecutionModel , TaskNV ) CASE ( ExecutionModel , MeshNV ) CASE ( ExecutionModel , RayGenerationNV ) CASE ( ExecutionModel , IntersectionNV ) CASE ( ExecutionModel , AnyHitNV ) CASE ( ExecutionModel , ClosestHitNV ) CASE ( ExecutionModel , MissNV ) CASE ( ExecutionModel , CallableNV ) break ;


<s> disablePass ( & PatchableFunctionID ) ; disablePass ( & ShrinkWrapID ) ; const <ISA_LIT>Subtarget & ST = * getTM < <ISA_LIT>TargetMachine > ( ) . getSubtargetImpl ( ) ; addPass ( createNVVMReflectPass ( ST . getSmVersion ( ) ) ) ; if ( getTM < <ISA_LIT>TargetMachine > ( ) . getTargetTriple ( ) . getOS ( ) == Triple :: CUDA && getTM < <ISA_LIT>TargetMachine > ( ) . getTargetTriple ( ) . getEnvironment ( ) == Triple :: SYCLDevice ) {

addPass ( createLocalAccessorToSharedMemoryPass ( ) ) ;


<s> if ( ! N -> readMem ( ) ) return false ; const Value * MemVal = N -> getMemOperand ( ) -> getValue ( ) ;

if ( CbId == - <NUM_LIT> ) return checkType ( MemVal , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( ! Subtarget . hasE2 ( ) ) { setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( ! Subtarget . has2E3 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( ! Subtarget . has3r2E3r3 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; <STR_LIT> FPOpToExpand [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( STI . useHardFloat ( ) ) { MVT AllVTy [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : AllVTy ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , VT , Expand ) ; for ( auto Op : FPOpToExpand ) setOperationAction ( Op , VT , Expand ) ; }

if ( STI . hasFPUv2SingleFloat ( ) || STI . hasFPUv3SingleFloat ( ) ) {


<s> SDLoc dl ( GA ) ; SDValue Offset ; SDValue Chain = DAG . getEntryNode ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , dl , PtrVT ) ; if ( model == TLSModel :: InitialExec ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; unsigned char PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GA -> getGlobal ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj , <STR_LIT> , true ) ; Offset = DAG . getTargetConstantPool ( CPV , PtrVT , Align ( <NUM_LIT> ) ) ; Offset = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Offset ) ; Offset = DAG . getLoad ( PtrVT , dl , Chain , Offset , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ; Chain = Offset . getValue ( <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , dl , <STR_LIT> ) ;

Offset = DAG . getNode ( <STR_LIT> , dl , PtrVT , Offset , PICLabel ) ;


<s> if ( reload_completed && ( LABEL_REF_P ( ind ) || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , <NUM_LIT> ) ;

if ( GET_CODE ( ind ) == POST_INC || GET_CODE ( ind ) == PRE_DEC ) return arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ;


<s> return ( ( ! TARGET_SSE2 || npush < ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ) && TARGET_PUSH_ARGS && ! ACCUMULATE_OUTGOING_ARGS ) ;


<s> Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; return <STR_LIT> . contains ( DstReg ) || <STR_LIT> . contains ( SrcReg ) ;


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;

assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;


<s> return ( ( qword ) ( vec_cmpgt ( ( vec_char16 ) ( a ) , ( vec_char16 ) ( b ) ) ) ) ;


<s> inline static unsigned encodeSEW ( unsigned SEW ) {

assert ( isValidSEW ( SEW ) && <STR_LIT> ) ;


<s> auto * C2 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( C1 && C2 ) { const APInt & C1Int = C1 -> getAPIntValue ( ) ; APInt ShiftedC1Int = C1Int << C2 -> getAPIntValue ( ) ; if ( ShiftedC1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( ShiftedC1Int . getSExtValue ( ) ) ) return true ;

if ( C1Int . getMinSignedBits ( ) <= <NUM_LIT> && isLegalAddImmediate ( C1Int . getSExtValue ( ) ) ) return false ;


<s> BW = <NUM_LIT> ; return true ; } if ( RC == & <STR_LIT> ) { BW = ( RR . Sub != <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return true ;


<s> if ( auto * ConstNode = dyn_cast < ConstantSDNode > ( C . getNode ( ) ) ) { const APInt & Imm = ConstNode -> getAPIntValue ( ) ; if ( ( Imm + <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - Imm ) . isPowerOf2 ( ) || ( - <NUM_LIT> - Imm ) . isPowerOf2 ( ) ) return true ; if ( Subtarget . hasStdExtZba ( ) && ! Imm . isSignedIntN ( <NUM_LIT> ) && ( ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ; if ( ! Imm . isSignedIntN ( <NUM_LIT> ) && Imm . countTrailingZeros ( ) < <NUM_LIT> ) { APInt ImmS = Imm . ashr ( Imm . countTrailingZeros ( ) ) ; if ( ( ImmS + <NUM_LIT> ) . isPowerOf2 ( ) || ( ImmS - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - ImmS ) . isPowerOf2 ( ) ) return true ; } } } return false ;


<s> SDValue Elt = DAG . getNode ( <STR_LIT> , SL , EltVT , Vec . getOperand ( <NUM_LIT> ) , Idx ) ; return DAG . getNode ( Vec . getOpcode ( ) , SL , EltVT , Elt ) ; } if ( Vec . hasOneUse ( ) && DCI . isBeforeLegalize ( ) ) { SDLoc SL ( N ) ; EVT EltVT = N -> getValueType ( <NUM_LIT> ) ; SDValue Idx = N -> getOperand ( <NUM_LIT> ) ; unsigned Opc = Vec . getOpcode ( ) ; switch ( Opc ) { default :


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) {

return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> return ( __m512i ) __builtin_ia32_permvardi512_mask ( ( __v8di ) __Y , ( __v8di ) __X , ( __v8di ) _mm512_undefined_epi32 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> RC = updatedRC ( RC ) ; storeRegToStackSlotNoUpd ( MBB , MI , SrcReg , isKill , FrameIdx , RC , TRI ) ;


<s> return Waitcnt ( std :: min ( VmCnt , Other . VmCnt ) , std :: min ( ExpCnt , Other . ExpCnt ) , std :: min ( LgkmCnt , Other . LgkmCnt ) , std :: min ( VsCnt , Other . VsCnt ) ) ;


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; if ( ! getHasJmpExt ( ) ) NegateCC ( LHS , RHS , CC ) ;

return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , LHS , RHS , DAG . getConstant ( CC , DL , LHS . getValueType ( ) ) , Dest ) ;


<s> SchedCandidate ( ) : SU ( nullptr ) , SCost ( <NUM_LIT> ) {


<s> Src1 -> ChangeToImmediate ( Imm ) ; removeModOperands ( UseMI ) ; UseMI . setDesc ( get ( <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ; if ( DeleteDef ) DefMI . eraseFromParent ( ) ; return true ; } if ( Src2 -> isReg ( ) && Src2 -> getReg ( ) == Reg ) { if ( ! Src0 -> isImm ( ) && ( Src0 -> isReg ( ) && RI . isSGPRClass ( MRI -> getRegClass ( Src0 -> getReg ( ) ) ) ) ) return false ; if ( ! Src1 -> isReg ( ) || RI . isSGPRClass ( MRI -> getRegClass ( Src1 -> getReg ( ) ) ) ) return false ; const int64_t Imm = DefMI . getOperand ( <NUM_LIT> ) . getImm ( ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) ) ; UseMI . RemoveOperand ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ) ; if ( Opc == <STR_LIT> ) { UseMI . untieRegOperand ( <STR_LIT> ( Opc , <STR_LIT> :: src2 ) ) ; } Src2 -> ChangeToImmediate ( Imm ) ; removeModOperands ( UseMI ) ; UseMI . setDesc ( get ( <STR_LIT> ) ) ; bool DeleteDef = MRI -> hasOneNonDBGUse ( Reg ) ;


<s> bool useAVX512Regs ( ) const { return hasAVX512 ( ) && ( canExtendTo512DQ ( ) || RequiredVectorWidth > <NUM_LIT> ) ;


<s> static int csky_sched_adjust_cost ( rtx_insn * insn , int dep_type , rtx_insn * dep , int cost , unsigned int dw ATTRIBUTE_UNUSED ) { if ( dep_type == REG_DEP_ANTI || dep_type == REG_DEP_OUTPUT ) return <NUM_LIT> ; else if ( recog_memoized ( insn ) >= <NUM_LIT> && recog_memoized ( dep ) >= <NUM_LIT> ) { enum attr_type insn_type = get_attr_type ( insn ) ; if ( CSKY_TARGET_ARCH ( CK803 ) ) { if ( insn_type == TYPE_LOAD || insn_type == TYPE_STORE ) { rtx pattern = PATTERN ( insn ) ; gcc_assert ( GET_CODE ( pattern ) == SET ) ; rtx addr = ( insn_type == TYPE_LOAD ? SET_SRC ( pattern ) : SET_DEST ( pattern ) ) ; enum rtx_code code = GET_CODE ( addr ) ; if ( code == ZERO_EXTEND || code == SIGN_EXTEND ) addr = XEXP ( addr , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( addr ) == MEM ) ;


<s> case <STR_LIT> : case <STR_LIT> : Info . opc = <STR_LIT> ; Info . memVT = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad | MachineMemOperand :: MOStore | MachineMemOperand :: MOVolatile ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . memVT = getValueType ( DL , I . getType ( ) -> getScalarType ( ) ) ; Info . align = Align ( DL . getTypeSizeInBits ( I . getType ( ) -> getScalarType ( ) ) / <NUM_LIT> ) ; Info . size = MemoryLocation :: UnknownSize ; Info . flags |= MachineMemOperand :: MOLoad ; return true ; case <STR_LIT> : Info . opc = <STR_LIT> ;


<s> if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode1 ) ) op2 = copy_to_mode_reg ( mode0 , op2 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op3 , mode1 ) ) op3 = copy_to_mode_reg ( mode0 , op3 ) ; scratch = gen_reg_rtx ( CCmode ) ; pat = GEN_FCN ( icode ) ( scratch , op0 , op1 ) ; if ( ! pat ) return const0_rtx ; emit_insn ( pat ) ; if ( mode0 == V2SImode ) emit_insn ( gen_spe_evsel ( target , op2 , op3 , scratch ) ) ; else emit_insn ( gen_spe_evsel_fs ( target , op2 , op3 , scratch ) ) ; return target ;


<s> bool loadStoreOptEnabled ( ) const { return EnableLoadStoreOpt ;


<s> DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; ZeroReg = <STR_LIT> ; } else if ( ( MI . getOpcode ( ) == <STR_LIT> ) && ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; ZeroReg = <STR_LIT> ;


<s> if ( MinAlign == <NUM_LIT> ) return Type :: getInt16Ty ( Context ) ;

if ( SrcAddrSpace == <ISA_LIT>AS :: LOCAL_ADDRESS || SrcAddrSpace == <ISA_LIT>AS :: REGION_ADDRESS || DestAddrSpace == <ISA_LIT>AS :: LOCAL_ADDRESS || DestAddrSpace == <ISA_LIT>AS :: REGION_ADDRESS ) {


<s> MRI . setRegAllocationHint ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> , <STR_LIT> ) ; continue ; } if ( DstReg != <STR_LIT> ) continue ; } if ( Op32 == <STR_LIT> ) { const MachineOperand * Src2 = TII -> getNamedOperand ( MI , <STR_LIT> :: src2 ) ; if ( ! Src2 -> isReg ( ) ) continue ; unsigned SReg = Src2 -> getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( SReg ) ) { MRI . setRegAllocationHint ( SReg , <NUM_LIT> , <STR_LIT> ) ; continue ; } if ( SReg != <STR_LIT> ) continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << '\n' ; ) ; MachineInstrBuilder Inst32 = BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII -> get ( Op32 ) ) ; Inst32 . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Inst32 . addOperand ( * TII -> getNamedOperand ( MI , <STR_LIT> :: src0 ) ) ; const MachineOperand * Src1 = TII -> getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 ) Inst32 . addOperand ( * Src1 ) ;


<s> if ( IDVal == <STR_LIT> ) return ParseDirective<ISA_LIT>HsaKernel ( ) ; if ( IDVal == <STR_LIT> ) return ParseDirectiveISAVersion ( ) ;

if ( IDVal == <STR_LIT> :: AssemblerDirectiveBegin ) return ParseDirectiveHSAMetadata ( ) ;


<s> static void m68hc11_asm_out_destructor ( rtx symbol , int priority ) {

default_dtor_section_asm_out_destructor ( symbol , priority ) ;


<s> static bool IsSpilledAfterDef ( MachineInstr * start , unsigned reg ) { bool canBeSpilled = false ; if ( ! CheckSpillAfterDef ( start , reg , canBeSpilled ) ) { std :: queue < MachineBasicBlock * > Q ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > Visited ; MachineBasicBlock * MBB = start -> getParent ( ) ; Q . push ( MBB ) ;

while ( ! Q . empty ( ) && ! canBeSpilled ) {


<s> static bool is16BitMemOperand ( const MCInst & MI , unsigned Op , const MCSubtargetInfo & STI ) { const MCOperand & BaseReg = MI . getOperand ( Op + <STR_LIT> ) ; const MCOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ;

const MCOperand & Disp = MI . getOperand ( Op + <STR_LIT> ) ;


<s> if ( TARGET_ARCH64 ) { cpp_assert ( parse_in , <STR_LIT> ) ; cpp_assert ( parse_in , <STR_LIT> ) ; } else { cpp_assert ( parse_in , <STR_LIT> ) ; cpp_assert ( parse_in , <STR_LIT> ) ; } if ( TARGET_VIS4 ) { cpp_define ( parse_in , <STR_LIT> ) ; cpp_define ( parse_in , <STR_LIT> ) ; } else if ( TARGET_VIS3 ) {


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;

return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FI , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> SDValue Sub1 = CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ; SDNode * N0Lo = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , N0 , Sub0 ) ; SDNode * N0Hi = CurDAG -> getMachineNode ( TargetOpcode :: EXTRACT_SUBREG , DL , <STR_LIT> , N0 , Sub1 ) ; SDValue AddOffsetLo = getMaterializedScalarImm32 ( Lo_32 ( RemainderOffset ) , DL ) ; SDValue AddOffsetHi = getMaterializedScalarImm32 ( Hi_32 ( RemainderOffset ) , DL ) ; SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDNode * Add = CurDAG -> getMachineNode ( <STR_LIT> , DL , VTs , { AddOffsetLo , SDValue ( N0Lo , <NUM_LIT> ) , Clamp } ) ; SDNode * Addc = CurDAG -> getMachineNode ( <STR_LIT> , DL , VTs , { AddOffsetHi , SDValue ( N0Hi , <NUM_LIT> ) , SDValue ( Add , <NUM_LIT> ) , Clamp } ) ; SDValue RegSequenceArgs [ ] = { CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , SDValue ( Add , <NUM_LIT> ) , Sub0 , SDValue ( Addc , <NUM_LIT> ) , Sub1 } ; Addr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , RegSequenceArgs ) , <NUM_LIT> ) ; } }


<s> MCSymbol * Sym = Printer . createTempSymbol ( <STR_LIT> ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Returns ; SmallVector < <STR_LIT> , <NUM_LIT> > Params ; const MachineRegisterInfo & MRI = MI -> getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; for ( const MachineOperand & MO : MI -> defs ( ) ) Returns . push_back ( getType ( MRI . getRegClass ( MO . getReg ( ) ) ) ) ; for ( const MachineOperand & MO : MI -> explicit_uses ( ) ) if ( MO . isReg ( ) ) Params . push_back ( getType ( MRI . getRegClass ( MO . getReg ( ) ) ) ) ; if ( <STR_LIT> ( * MI ) ) Params . pop_back ( ) ; MCSymbolWasm * WasmSym = cast < MCSymbolWasm > ( Sym ) ; auto Signature = make_unique < <STR_LIT> > ( std :: move ( Returns ) , std :: move ( Params ) ) ; WasmSym -> setSignature ( Signature . get ( ) ) ; Printer . addSignature ( std :: move ( Signature ) ) ; WasmSym -> setType ( <STR_LIT> ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( WasmSym , MCSymbolRefExpr :: VK_<ISA_LIT>_TYPEINDEX , Ctx ) ; MCOp = MCOperand :: createExpr ( Expr ) ; break ; } } MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ; break ; case MachineOperand :: MO_FPImmediate : { const ConstantFP * Imm = MO . getFPImm ( ) ;

if ( Imm -> getType ( ) -> isFloatTy ( ) ) MCOp = MCOperand :: createFPImm ( Imm -> getValueAPF ( ) . convertToFloat ( ) ) ;


<s> Value * NewOperand = Operand ; if ( Operand ) { if ( isa < GlobalVariable > ( Operand ) ) { GVMapTy :: iterator I = GVMap . find ( cast < GlobalVariable > ( Operand ) ) ; if ( I != GVMap . end ( ) ) { NewOperand = I -> second ; if ( ++ i < NumOperands ) { NewOperands . push_back ( NewOperand ) ; NewOperand = ConstantInt :: get ( Type :: getInt32Ty ( M -> getContext ( ) ) , I -> second -> getType ( ) -> getAddressSpace ( ) ) ; } } } else if ( isa < MDNode > ( Operand ) ) { NewOperand = remapMDNode ( M , cast < MDNode > ( Operand ) ) ; } } OperandChanged |= Operand != NewOperand ; NewOperands . push_back ( NewOperand ) ; } if ( ! OperandChanged ) { return N ;


<s> const APInt Mask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; return Helper . getKnownBits ( ) -> maskedValueIsZero ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Mask ) ; } return false ;


<s> IsFlatOutstanding = false ; ReturnsVoid = MFI -> returnsVoid ( ) ; memset ( & UsedRegs , <NUM_LIT> , sizeof ( UsedRegs ) ) ; memset ( & DefinedRegs , <NUM_LIT> , sizeof ( DefinedRegs ) ) ; SmallVector < MachineInstr * , <NUM_LIT> > RemoveMI ; SmallVector < MachineBasicBlock * , <NUM_LIT> > EndPgmBlocks ; bool HaveScalarStores = false ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { if ( ! HaveScalarStores && TII -> isScalarStore ( * I ) ) HaveScalarStores = true ; if ( ST -> getGeneration ( ) <= <ISA_LIT>Subtarget :: SEA_ISLANDS ) { if ( TII -> isSMRD ( I -> getOpcode ( ) ) ) { VCCZCorrupt = true ; } else if ( ! hasOutstandingLGKM ( ) && I -> modifiesRegister ( <STR_LIT> , TRI ) ) { VCCZCorrupt = false ; } if ( VCCZCorrupt && readsVCCZ ( * I ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; insertWait ( MBB , I , LastIssued ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } } if ( I -> getOpcode ( ) == <STR_LIT> ) { handleExistingWait ( * I ) ; RemoveMI . push_back ( & * I ) ; continue ; } Counters Required ;

if ( ( I -> getOpcode ( ) == <STR_LIT> && ST -> needWaitcntBeforeBarrier ( ) ) || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) Required = LastIssued ;


<s> Out . EmitBundleLock ( false ) ; EmitBICMask ( Out , <STR_LIT> , Pred , <NUM_LIT> ) ; Out . EmitInstruction ( Saved [ <NUM_LIT> ] ) ; Out . EmitBundleUnlock ( ) ;


set_mem_alias_set ( gp_regs , get_varargs_alias_set ( ) ) ;


<s> VectorElementize ( <ISA_LIT>TargetMachine & tm ) : MachineFunctionPass ( ID ) , TM ( tm ) {


<s> Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: String ) ) return TokError ( <STR_LIT> ) ; VendorName = getLexer ( ) . getTok ( ) . getStringContents ( ) ; Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: String ) ) return TokError ( <STR_LIT> ) ; ArchName = getLexer ( ) . getTok ( ) . getStringContents ( ) ; Lex ( ) ; getTargetStreamer ( ) . EmitDirectiveHSACodeObjectISA ( Major , Minor , Stepping , VendorName , ArchName ) ; return false ;


<s> NewOpc = AMDGPU :: getCommuteRev ( Opcode ) ;

if ( NewOpc != - <NUM_LIT> && pseudoToMCOpcode ( NewOpc ) != - <NUM_LIT> ) return NewOpc ;


<s> ZDC ( ) : MachineFunctionPass ( ID ) {


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;

else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> return ; } if ( FrameSize <= <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addImm ( FrameSize ) ; return ; } BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ;

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( RHS ) ) { int32_t imm = C -> getSExtValue ( ) ; if ( imm < <NUM_LIT> && imm > std :: numeric_limits < int > :: min ( ) ) { SDLoc DL ( N ) ; RHS = DAG . getConstant ( - imm , DL , <STR_LIT> ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , DL , N -> getVTList ( ) , N -> getOperand ( <NUM_LIT> ) , RHS ) ; }


<s> MIs . erase ( std :: find ( MIs . begin ( ) , MIs . end ( ) , MI ) , MIs . end ( ) ) ; }

for ( InstructionSetMap :: iterator It = PreviousRegSeqByUndefCount . begin ( ) , E = PreviousRegSeqByUndefCount . end ( ) ; It != E ; ++ It ) {


<s> if ( Flags != <STR_LIT> && Flags != <STR_LIT> ) return true ; assert ( DefMI -> hasOneMemOperand ( ) ) ; Val = ( * DefMI -> memoperands_begin ( ) ) -> getValue ( ) ; if ( ! Val ) Val = ( * DefMI -> memoperands_begin ( ) ) -> getPseudoValue ( ) ; return true ;


bool IsBlendSupported = Subtarget . hasSSE41 ( ) ;


<s> if ( GET_CODE ( addr ) == PLUS ) { if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == SYMBOL_REF ) return false ; if ( GET_CODE ( XEXP ( addr , <NUM_LIT> ) ) == CONST_INT ) { if ( ( mode == SImode || mode == SFmode ) && NDS32_SINGLE_WORD_ALIGN_P ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) ) && ! satisfies_constraint_Is14 ( XEXP ( addr , <NUM_LIT> ) ) ) return false ; if ( ( mode == DImode || mode == DFmode ) && NDS32_DOUBLE_WORD_ALIGN_P ( INTVAL ( XEXP ( addr , <NUM_LIT> ) ) ) && ! satisfies_constraint_Is14 ( XEXP ( addr , <NUM_LIT> ) ) ) return false ;


<s> return IN_RANGE ( v , <NUM_LIT> , <NUM_LIT> ) ;


<s> return ( poly8x8_t ) __builtin_neon_vmvnv8qi ( ( int8x8_t ) __a ) ;


<ISA_LIT>HazardRecognizer ( const MachineSchedContext * C ) : DAG ( nullptr ) , SchedModel ( nullptr ) {


<s> uint64_t EncVal = Imm ; return ( EncVal << <NUM_LIT> ) | ( EncVal << <NUM_LIT> ) | ( EncVal << <NUM_LIT> ) | EncVal ;


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; assert ( ! Subtarget -> has<ISA_LIT>32r6 ( ) && ! Subtarget -> has<ISA_LIT>64r6 ( ) ) ; SDValue CondRes = createFPCmp ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; if ( CondRes . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue CCNode = CondRes . getOperand ( <NUM_LIT> ) ;

<STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( CCNode ) -> getZExtValue ( ) ;


<s> unsigned getRotImmOpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT> ;


<s> bool isALU ( const MachineInstr & MI ) const { if ( TII -> isALUInstr ( MI . getOpcode ( ) ) ) return true ;

if ( TII -> isVector ( MI ) || TII -> isCubeOp ( MI . getOpcode ( ) ) ) return true ;


<s> if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ;

if ( EnableGenMux ) addPass ( create<ISA_LIT>GenMux ( ) , false ) ;


<s> case NVPTX_BUILTIN_SHUFFLE : case NVPTX_BUILTIN_SHUFFLELL : return nvptx_expand_shuffle ( exp , target , mode , ignore ) ; case NVPTX_BUILTIN_WORKER_ADDR : return nvptx_expand_shared_addr ( exp , target , mode , ignore , false ) ; case NVPTX_BUILTIN_VECTOR_ADDR : return nvptx_expand_shared_addr ( exp , target , mode , ignore , true ) ; case NVPTX_BUILTIN_CMP_SWAP : case NVPTX_BUILTIN_CMP_SWAPLL : return nvptx_expand_cmp_swap ( exp , target , mode , ignore ) ; default : gcc_unreachable ( ) ; }


<s> x . v = vec_splat ( ( vec_uchar16 ) ( count ) , <NUM_LIT> ) ; cnt = x . i [ <NUM_LIT> ] ; mask = ( cnt & <NUM_LIT> ) ? vec_splat_u8 ( <NUM_LIT> ) : vec_splat_u8 ( - <NUM_LIT> ) ;

return ( ( qword ) ( vec_and ( vec_slo ( ( vec_uchar16 ) ( a ) , x . v ) , mask ) ) ) ;


<s> bool isLegal = false ; if ( VT . isVector ( ) ) isLegal = Subtarget -> hasMVEIntegerOps ( ) && getMVEIndexedAddressParts ( Ptr . getNode ( ) , VT , Align , isSEXTLoad , Subtarget -> isLittle ( ) , Base , Offset , isInc , DAG ) ; else { if ( Subtarget -> isThumb2 ( ) ) isLegal = getT2IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; else isLegal = get<ISA_LIT>IndexedAddressParts ( Ptr . getNode ( ) , VT , isSEXTLoad , Base , Offset , isInc , DAG ) ; } if ( ! isLegal ) return false ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT ) {

MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ;


<s> MachineInstr * SecondLastInst = nullptr ; for ( ; ; ) { if ( & * I != LastInst && ! I -> isBundle ( ) && isUnpredicatedTerminator ( & * I ) ) { if ( ! SecondLastInst ) SecondLastInst = & * I ; else return true ; } if ( I == MBB . instr_begin ( ) ) break ; -- I ; } int LastOpcode = LastInst -> getOpcode ( ) ; int SecLastOpcode = SecondLastInst ? SecondLastInst -> getOpcode ( ) : <NUM_LIT> ; if ( LastOpcode == <STR_LIT> && ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( SecLastOpcode == <STR_LIT> && ! SecondLastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c ( LastOpcode ) ; bool LastOpcodeHasNVJump = isNewValueJump ( LastInst ) ; if ( LastOpcodeHasJMP_c && ! LastInst -> getOperand ( <NUM_LIT> ) . isMBB ( ) ) return true ; if ( LastInst && ! SecondLastInst ) { if ( LastOpcode == <STR_LIT> ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isEndLoopN ( LastOpcode ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ; } if ( LastOpcodeHasJMP_c ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst -> getOpcode ( ) ) ) ; Cond . push_back ( LastInst -> getOperand ( <NUM_LIT> ) ) ; return false ;


<s> Value * NewFDiv = nullptr ; if ( VectorType * VT = dyn_cast < VectorType > ( FDiv . getType ( ) ) ) { NewFDiv = UndefValue :: get ( VT ) ; for ( unsigned I = <NUM_LIT> , E = VT -> getNumElements ( ) ; I != E ; ++ I ) { Value * NumEltI = Builder . CreateExtractElement ( Num , I ) ; Value * DenEltI = Builder . CreateExtractElement ( Den , I ) ; Value * NewElt = nullptr ; if ( UseFDivFast && ! shouldKeepFDivF32 ( NumEltI , FastUnsafeRcpLegal , HasFP32Denormals ) ) { Function * Decl = <STR_LIT> ( Mod , <STR_LIT> ) ; NewElt = Builder . CreateCall ( Decl , { NumEltI , DenEltI } , <STR_LIT> , FPMath ) ; } if ( ! NewElt ) NewElt = performRCPOpt ( NumEltI , DenEltI , FastUnsafeRcpLegal , Builder , FPMath , Mod , HasFP32Denormals , NeedHighAccuracy ) ; if ( ! NewElt ) NewElt = Builder . CreateFDiv ( NumEltI , DenEltI , <STR_LIT> , FPMath ) ; NewFDiv = Builder . CreateInsertElement ( NewFDiv , NewElt , I ) ; } } else { if ( UseFDivFast && ! shouldKeepFDivF32 ( Num , FastUnsafeRcpLegal , HasFP32Denormals ) ) { Function * Decl = <STR_LIT> ( Mod , <STR_LIT> ) ; NewFDiv = Builder . CreateCall ( Decl , { Num , Den } , <STR_LIT> , FPMath ) ; }


<s> addPass ( create<ISA_LIT>RelaxMemPass ( ) ) ;

addPass ( create<ISA_LIT>ExpandPseudoPass ( ) ) ;


<s> if ( TARGET_8ALIGN && GET_MODE_SIZE ( mode ) > UNITS_PER_WORD ) return ( regno & <NUM_LIT> ) == <NUM_LIT> ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> bool mips_cannot_change_mode_class ( enum machine_mode from , enum machine_mode to , enum reg_class class ) { if ( MIN ( GET_MODE_SIZE ( from ) , GET_MODE_SIZE ( to ) ) <= UNITS_PER_WORD && MAX ( GET_MODE_SIZE ( from ) , GET_MODE_SIZE ( to ) ) > UNITS_PER_WORD ) { if ( TARGET_BIG_ENDIAN ) { if ( FP_INC > <NUM_LIT> && reg_classes_intersect_p ( FP_REGS , class ) ) return true ; } else {

if ( reg_classes_intersect_p ( ACC_REGS , class ) ) return true ;


<s> static int tilegx_pic_address_needs_scratch ( rtx x ) { if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF || GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF ) && ( CONST_INT_P ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) return true ; return false ;


<s> static const char * const suffix [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( flags & SECTION_EXCLUDE ) smclass = <NUM_LIT> ; else if ( flags & SECTION_DEBUG ) { fprintf ( asm_out_file , <STR_LIT> , name ) ; return ; } else if ( flags & SECTION_CODE ) smclass = <NUM_LIT> ; else if ( flags & SECTION_TLS ) { if ( flags & SECTION_BSS ) smclass = <NUM_LIT> ; else smclass = <NUM_LIT> ; }


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; if ( ! Memory . OffsetImm ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;

else if ( const auto * CE = dyn_cast < MCConstantExpr > ( Memory . OffsetImm ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) / <NUM_LIT> ) ) ;


<s> return new <ISA_LIT>MCCodeEmitter ( Ctx , MCII ) ;


<s> rtvec vec ; vec = gen_rtvec ( <NUM_LIT> , reg , symbol , gen_rtx_REG ( SImode , GOT_VERSION_REGNUM ) ) ; return gen_rtx_UNSPEC ( Pmode , vec , UNSPEC_LOAD_CALL ) ;