<s> SwitchToEHSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_EXIDX , ELF :: SHF_ALLOC | ELF :: SHF_LINK_ORDER , SectionKind :: getDataRel ( ) , FnStart ) ;


<s> if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> && Op0 . getOperand ( <NUM_LIT> ) == Op1 . getOperand ( <NUM_LIT> ) && CC == <STR_LIT> && isa < ConstantSDNode > ( Op0 . getOperand ( <NUM_LIT> ) ) ) { unsigned Bits = Op0 . getValueSizeInBits ( ) ; if ( b != Bits / <NUM_LIT> - <NUM_LIT> ) return false ; if ( Op0 . getConstantOperandVal ( <NUM_LIT> ) != Bits - <NUM_LIT> ) return false ; LHS = Op0 . getOperand ( <NUM_LIT> ) ; RHS = Op1 . getOperand ( <NUM_LIT> ) ; return true ; } if ( Op0 . getOpcode ( ) == <STR_LIT> && CC == <STR_LIT> && isa < ConstantSDNode > ( O . getOperand ( <NUM_LIT> ) ) ) { uint64_t ULim = O . getConstantOperandVal ( <NUM_LIT> ) ; if ( ULim != ( UINT64_C ( <NUM_LIT> ) << b * <NUM_LIT> ) ) return false ; unsigned Bits = Op0 . getValueSizeInBits ( ) ; if ( ! CurDAG -> MaskedValueIsZero ( Op0 , APInt :: getHighBitsSet ( Bits , Bits - ( b + <NUM_LIT> ) * <NUM_LIT> ) ) ) return false ; LHS = Op0 . getOperand ( <NUM_LIT> ) ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; return true ; } return false ; } if ( CC != <STR_LIT> ) return false ; SDValue Op = O . getOperand ( <NUM_LIT> ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) { if ( ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return false ; if ( Op . getConstantOperandVal ( <NUM_LIT> ) != ( UINT64_C ( <NUM_LIT> ) << ( <NUM_LIT> * b ) ) ) return false ; SDValue XOR = Op . getOperand ( <NUM_LIT> ) ; if ( XOR . getOpcode ( ) == <STR_LIT> ) XOR = XOR . getOperand ( <NUM_LIT> ) ; if ( XOR . getOpcode ( ) != <STR_LIT> ) return false ; LHS = XOR . getOperand ( <NUM_LIT> ) ; RHS = XOR . getOperand ( <NUM_LIT> ) ; return true ; } else if ( Op . getOpcode ( ) == <STR_LIT> ) { if ( ! isa < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ) return false ; unsigned Bits = Op . getValueSizeInBits ( ) ; if ( b != Bits / <NUM_LIT> - <NUM_LIT> ) return false ;

if ( Op . getConstantOperandVal ( <NUM_LIT> ) != Bits - <NUM_LIT> ) return false ;


<s> unsigned StackAlignment = TFL -> getStackAlignment ( ) ; NextStackOffset = alignTo ( NextStackOffset , StackAlignment ) ; SDValue NextStackOffsetVal = DAG . getIntPtrConstant ( NextStackOffset , DL , true ) ; if ( ! IsTailCall ) Chain = DAG . getCALLSEQ_START ( Chain , NextStackOffsetVal , DL ) ; SDValue StackPtr = DAG . getCopyFromReg ( Chain , DL , ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; std :: deque < std :: pair < unsigned , SDValue > > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; CCInfo . rewindByValRegsInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { SDValue Arg = OutVals [ i ] ; CCValAssign & VA = ArgLocs [ i ] ; MVT ValVT = VA . getValVT ( ) , LocVT = VA . getLocVT ( ) ; <STR_LIT> Flags = Outs [ i ] . Flags ; bool UseUpperBits = false ; if ( Flags . isByVal ( ) ) { unsigned FirstByValReg , LastByValReg ; unsigned ByValIdx = CCInfo . getInRegsParamsProcessed ( ) ; CCInfo . getInRegsParamInfo ( ByValIdx , FirstByValReg , LastByValReg ) ; assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValIdx < CCInfo . getInRegsParamsCount ( ) ) ; assert ( ! IsTailCall && <STR_LIT> ) ; passByValArg ( Chain , DL , RegsToPass , MemOpChains , StackPtr , MFI , DAG , Arg , FirstByValReg , LastByValReg , Flags , Subtarget . isLittle ( ) , VA ) ; CCInfo . nextInRegsParam ( ) ; continue ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : if ( VA . isRegLoc ( ) ) { if ( ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) || ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) || ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) ) Arg = DAG . getNode ( <STR_LIT> , DL , LocVT , Arg ) ; else if ( ValVT == <STR_LIT> && LocVT == <STR_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; if ( ! Subtarget . isLittle ( ) ) std :: swap ( Lo , Hi ) ; unsigned LocRegLo = VA . getLocReg ( ) ; unsigned LocRegHigh = getNextIntArgReg ( LocRegLo ) ; RegsToPass . push_back ( std :: make_pair ( LocRegLo , Lo ) ) ; RegsToPass . push_back ( std :: make_pair ( LocRegHigh , Hi ) ) ;


<s> if ( GET_MODE ( x ) == VOIDmode ) x = convert_to_mode ( mode , x , <NUM_LIT> ) ;


<s> if ( LHS -> getType ( ) -> getPointerAddressSpace ( ) != <NUM_LIT> || RHS -> getType ( ) -> getPointerAddressSpace ( ) != <NUM_LIT> ) return nullptr ; if ( ! isa < GlobalObject > ( LHS ) || ! isa < GlobalVariable > ( RHS ) || LHS -> isThreadLocal ( ) || RHS -> isThreadLocal ( ) || RHS -> getName ( ) != <STR_LIT> || ! RHS -> hasExternalLinkage ( ) || cast < GlobalVariable > ( RHS ) -> hasInitializer ( ) || RHS -> hasSection ( ) ) return nullptr ;

return MCSymbolRefExpr :: create ( TM . getSymbol ( LHS ) , MCSymbolRefExpr :: VK_COFF_IMGREL32 , getContext ( ) ) ;


<s> UseSet & Us = UF -> second ; UseSet LSs ; for ( Use * U : Us ) { User * R = U -> getUser ( ) ; if ( LoadInst * Ld = dyn_cast < LoadInst > ( R ) ) { unsigned PtrX = LoadInst :: getPointerOperandIndex ( ) ; if ( & Ld -> getOperandUse ( PtrX ) == U ) LSs . insert ( U ) ;

} else if ( StoreInst * St = dyn_cast < StoreInst > ( R ) ) {


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM , CM ) ;


<s> ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT LocVT = VA . getLocVT ( ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DL ) ) ; InVals . push_back ( DAG . getLoad ( LocVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) , <NUM_LIT> ) ) ; } } if ( isVarArg ) { unsigned StackSize = CCInfo . getNextStackOffset ( ) ;

<ISA_LIT>Z80MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ;


<s> case <STR_LIT> : return performAddCarrySubCarryCombine ( N , DCI ) ; case <STR_LIT> : return performFAddCombine ( N , DCI ) ; case <STR_LIT> : return performFSubCombine ( N , DCI ) ; case <STR_LIT> : return performSetCCCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performMinMaxCombine ( N , DCI ) ; case <STR_LIT> : return performFMACombine ( N , DCI ) ; case <STR_LIT> : return performAndCombine ( N , DCI ) ; case <STR_LIT> : return performOrCombine ( N , DCI ) ; case <STR_LIT> : return performXorCombine ( N , DCI ) ; case <STR_LIT> : return performZeroExtendCombine ( N , DCI ) ; case <STR_LIT> : return performSignExtendInRegCombine ( N , DCI ) ; case <STR_LIT> : return performClassCombine ( N , DCI ) ; case <STR_LIT> : return performFCanonicalizeCombine ( N , DCI ) ; case <STR_LIT> : return performRcpCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case <STR_LIT> : case <STR_LIT> : return performUCharToFloatCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performCvtF32UByteNCombine ( N , DCI ) ; case <STR_LIT> : return performFMed3Combine ( N , DCI ) ; case <STR_LIT> : return performCvtPkRTZCombine ( N , DCI ) ; case <STR_LIT> : return performClampCombine ( N , DCI ) ; case <STR_LIT> : { SelectionDAG & DAG = DCI . DAG ;

EVT VT = N -> getValueType ( <NUM_LIT> ) ;


<s> bool hasAES ( ) const { return HasAES ;


<s> if ( Known . isNegative ( ) ) return Constant :: getAllOnesValue ( V -> getType ( ) ) ; if ( Known . isNonNegative ( ) ) return Constant :: getNullValue ( V -> getType ( ) ) ; return Builder . CreateAShr ( V , Builder . getInt32 ( <NUM_LIT> ) ) ;


return new <ISA_LIT>GatherScatterLowering ( ) ;


<s> Top . init ( DAG , SchedModel ) ; Bot . init ( DAG , SchedModel ) ; const InstrItineraryData * Itin = DAG -> getSchedModel ( ) -> getInstrItineraries ( ) ; const TargetSubtargetInfo & STI = DAG -> MF . getSubtarget ( ) ; const TargetInstrInfo * TII = STI . getInstrInfo ( ) ; delete Top . HazardRec ; delete Bot . HazardRec ; Top . HazardRec = TII -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; Bot . HazardRec = TII -> CreateTargetMIHazardRecognizer ( Itin , DAG ) ; delete Top . ResourceModel ; delete Bot . ResourceModel ; Top . ResourceModel = new VLIWResourceModel ( STI , DAG -> getSchedModel ( ) ) ; Bot . ResourceModel = new VLIWResourceModel ( STI , DAG -> getSchedModel ( ) ) ; const std :: vector < unsigned > & MaxPressure = DAG -> getRegPressure ( ) . MaxSetPressure ; HighPressureSets . assign ( MaxPressure . size ( ) , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = MaxPressure . size ( ) ; i < e ; ++ i ) { unsigned Limit = DAG -> getRegClassInfo ( ) -> getRegPressureSetLimit ( i ) ; HighPressureSets [ i ] = ( ( float ) MaxPressure [ i ] > ( ( float ) Limit * RPThreshold ) ) ; } assert ( ( ! ForceTopDown || ! ForceBottomUp ) && <STR_LIT> ) ;


<s> assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; assert ( VT . getVectorNumElements ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; assert ( ( VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> || VT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> || InVT . getVectorElementType ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned ExtendInVecOpc = getOpcode_EXTEND_VECTOR_INREG ( Opc ) ; if ( InVT == <STR_LIT> ) { if ( VT != <STR_LIT> ) return SDValue ( ) ;

In = DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , In , DAG . getUNDEF ( <STR_LIT> ) ) ;


<s> VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; default : VT = <STR_LIT> ; break ; } Info . opc = <STR_LIT> ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . size = VT . getStoreSize ( ) ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOLoad ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT ; switch ( Intrinsic ) { case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; default : VT = <STR_LIT> ; break ; } Info . opc = <STR_LIT> ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = - VT . getStoreSize ( ) + <NUM_LIT> ; Info . size = <NUM_LIT> * VT . getStoreSize ( ) - <NUM_LIT> ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOStore ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT ; switch ( Intrinsic ) { case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; default : VT = <STR_LIT> ; break ; } Info . opc = <STR_LIT> ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . size = VT . getStoreSize ( ) ; Info . align = Align ( <NUM_LIT> ) ; Info . flags = MachineMemOperand :: MOStore ; return true ;


<s> int Cost = BaseT :: getVectorInstrCost ( Opcode , Val , Index ) ; Cost = vectorCostAdjustment ( Cost , Opcode , Val , nullptr ) ; if ( ST -> hasVSX ( ) && Val -> getScalarType ( ) -> isDoubleTy ( ) ) { if ( ISD == <STR_LIT> && Index == ( ST -> isLittleEndian ( ) ? <NUM_LIT> : <NUM_LIT> ) ) return <NUM_LIT> ; return Cost ; } else if ( Val -> getScalarType ( ) -> isIntegerTy ( ) && Index != - <NUM_LIT> ) {


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > A ( getThe<ISA_LIT>32Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > B ( getThe<ISA_LIT>64Target ( ) ) ; RegisterTargetMachine < <ISA_LIT>TargetMachine > C ( getThe<ISA_LIT>64LETarget ( ) ) ;

PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ;


<s> return Kind == k_Register && Reg . Kind == Kind_MSA128BRegs ;


<s> MIB . addImm ( <NUM_LIT> ) ; MIB -> addOperand ( BranchCond [ <NUM_LIT> ] ) ; MIB . copyImplicitOps ( TailCall ) ; LivePhysRegs LiveRegs ( getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; SmallVector < std :: pair < unsigned , const MachineOperand * > , <NUM_LIT> > Clobbers ; LiveRegs . stepForward ( * MIB , Clobbers ) ; for ( const auto & C : Clobbers ) { MIB . addReg ( C . first , RegState :: Implicit ) ; MIB . addReg ( C . first , RegState :: Implicit | RegState :: Define ) ;


<s> MachineInstr * RHSDef = getDefIgnoringCopies ( RHS . getReg ( ) , MRI ) ; auto P = static_cast < CmpInst :: Predicate > ( Predicate . getPredicate ( ) ) ; if ( isCMN ( LHSDef , P , MRI ) ) return emitCMN ( LHSDef -> getOperand ( <NUM_LIT> ) , RHS , MIRBuilder ) ; if ( isCMN ( RHSDef , P , MRI ) ) return emitCMN ( LHS , RHSDef -> getOperand ( <NUM_LIT> ) , MIRBuilder ) ; if ( ! CmpInst :: isUnsigned ( P ) && LHSDef && LHSDef -> getOpcode ( ) == TargetOpcode :: G_AND ) { auto ValAndVReg = getIConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI ) ; if ( ! ValAndVReg || ValAndVReg -> Value != <NUM_LIT> ) return nullptr ; return emitTST ( LHSDef -> getOperand ( <NUM_LIT> ) , LHSDef -> getOperand ( <NUM_LIT> ) , MIRBuilder ) ; }


<s> case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , true , false , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , false , true , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , true , false , true , <STR_LIT> ) ; case <STR_LIT> : return LowerFPToInt ( MI , DL , BB , TII , false , true , true , <STR_LIT> ) ; case <STR_LIT> :

return LowerFPToInt ( MI , DL , BB , TII , true , true , true , <STR_LIT> ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > create<ISA_LIT>WinCOFFObjectWriter ( bool Is64Bit ) { return llvm :: make_unique < <ISA_LIT>WinCOFFObjectWriter > ( Is64Bit ) ;


<s> void dump ( const GCNRegBankReassign * P ) const { MI -> dump ( ) ;

dbgs ( ) << P -> printReg ( Reg ) << <STR_LIT> ;


<s> return ( __m256i ) __builtin_ia32_pmovsqd512_mask ( ( __v8di ) __A , ( __v8si ) _mm256_undefined_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return <ISA_LIT>SelectExtractValue ( I ) ; case Instruction :: IntToPtr : case Instruction :: PtrToInt : { MVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; MVT DstVT = TLI . getValueType ( I -> getType ( ) ) ; if ( DstVT . bitsGT ( SrcVT ) ) return <ISA_LIT>SelectZExt ( I ) ; if ( DstVT . bitsLT ( SrcVT ) ) return <ISA_LIT>SelectTrunc ( I ) ;

unsigned Reg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( ! isNonZeroElementsInOrder ( Zeroable , Mask , V1 . getValueType ( ) , IsLeftZeroSide ) ) return SDValue ( ) ; unsigned VEXPANDMask = ( ~ Zeroable ) . getZExtValue ( ) ; MVT IntegerType = <STR_LIT> ( std :: max ( ( int ) VT . getVectorNumElements ( ) , <NUM_LIT> ) ) ; SDValue MaskNode = DAG . getConstant ( VEXPANDMask , DL , IntegerType ) ; unsigned NumElts = VT . getVectorNumElements ( ) ;

assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ;


<s> uint64_t encoding = <STR_LIT> ( MCE -> getValue ( ) & <NUM_LIT> , <NUM_LIT> ) ;

Inst . addOperand ( MCOperand :: createImm ( encoding ) ) ;


<s> if ( opCode == <STR_LIT> ) return <STR_LIT> ; if ( opCode == <STR_LIT> ) return <STR_LIT> ; if ( opCode == <STR_LIT> ) return <STR_LIT> ;


<s> continue ; } if ( ! MI -> hasDelaySlot ( ) ) continue ; MachineBasicBlock :: iterator D = MBB . end ( ) ; if ( ! DisableDelaySlotFiller ) D = findDelayInstr ( MBB , MI ) ; ++ FilledSlots ; Changed = true ; if ( D == MBB . end ( ) ) BuildMI ( MBB , I , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; else MBB . splice ( I , & MBB , D ) ; unsigned structSize = <NUM_LIT> ; if ( needsUnimp ( MI , structSize ) ) { MachineBasicBlock :: iterator J = MI ; ++ J ; assert ( J != MBB . end ( ) && <STR_LIT> ) ; BuildMI ( MBB , ++ J , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( structSize ) ; MIBundleBuilder ( MBB , MachineBasicBlock :: iterator ( MI ) , J ) ; } else {

MIBundleBuilder ( MBB , MachineBasicBlock :: iterator ( MI ) , I ) ;


<s> SDLoc SL ( Op ) ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) { SDValue Val = DAG . getNode ( <STR_LIT> , SL , EltVT , Store -> getValue ( ) , DAG . getConstant ( i , <STR_LIT> ) ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , PtrVT , Store -> getBasePtr ( ) , DAG . getConstant ( i * ( MemEltVT . getSizeInBits ( ) / <NUM_LIT> ) , PtrVT ) ) ; Chains . push_back ( DAG . getTruncStore ( Store -> getChain ( ) , SL , Val , Ptr , MachinePointerInfo ( Store -> getMemOperand ( ) -> getValue ( ) ) , MemEltVT , Store -> isVolatile ( ) , Store -> isNonTemporal ( ) , Store -> getAlignment ( ) ) ) ; }

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , & Chains [ <NUM_LIT> ] , NumElts ) ;


<s> int64_t EncodedOffset = getSMRDEncodedOffset ( ST , ByteOffset ) ; return ( hasSMEMByteOffset ( ST ) ) ? isUInt < <NUM_LIT> > ( EncodedOffset ) : isUInt < <NUM_LIT> > ( EncodedOffset ) ;


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> static rtx loongarch_add_offset ( rtx temp , rtx reg , HOST_WIDE_INT offset ) { if ( ! IMM12_OPERAND ( offset ) ) { rtx high ; high = gen_int_mode ( CONST_HIGH_PART ( offset ) , Pmode ) ; offset = CONST_LOW_PART ( offset ) ;

high = loongarch_force_temporary ( temp , high ) ;


<s> TargetPassConfig :: addMachineSSAOptimization ( ) ; addPass ( & <ISA_LIT>FoldOperandsID ) ; addPass ( & DeadMachineInstructionElimID ) ; addPass ( & <ISA_LIT>LoadStoreOptimizerID ) ;


<s> Register SrcReg , DstReg , IndReg ; for ( auto phi : FPPhis ) { DstReg = phi -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) == FrepBlock ) { SrcReg = phi -> getOperand ( <NUM_LIT> ) . getReg ( ) ; IndReg = phi -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else if ( phi -> getOperand ( <NUM_LIT> ) . getMBB ( ) == FrepBlock ) { SrcReg = phi -> getOperand ( <NUM_LIT> ) . getReg ( ) ; IndReg = phi -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( phi -> dump ( ) ; ) ; continue ;


<s> continue ; case MachineOperand :: MO_GlobalAddress : MCOp = LowerSymbolOperand ( MO , GetGlobalAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = LowerSymbolOperand ( MO , GetBlockAddressSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = LowerSymbolOperand ( MO , GetExternalSymbolSymbol ( MO ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = LowerSymbolOperand ( MO , GetJumpTableSymbol ( MO ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = LowerSymbolOperand ( MO , GetConstantPoolIndexSymbol ( MO ) ) ;


<s> CPEntry ( MachineInstr * cpemi , unsigned cpi , unsigned rc = <NUM_LIT> ) : CPEMI ( cpemi ) , CPI ( cpi ) , RefCount ( rc ) {


<s> unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ;

return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ;


<s> x = gen_reg_rtx ( SImode ) ; emit_insn ( gen_movsi ( x , CONST0_RTX ( SImode ) ) ) ;


<s> unsigned LMul = <NUM_LIT> << ( <NUM_LIT> - static_cast < unsigned > ( VLMUL ) ) ; OS << <STR_LIT> << LMul ; break ; } } if ( isTailAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ; if ( isMaskAgnostic ( VType ) ) OS << <STR_LIT> ; else OS << <STR_LIT> ;


<s> for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) clobbered_regs [ i ] = clobbered_regs [ i ] && ! global_regs [ i ] ; clobbered_regs [ RETURN_REGNUM ] |= ( TARGET_TPF_PROFILING || cfun_frame_layout . save_return_addr_p || crtl -> calls_eh_return ) ;


<s> SMLoc <ISA_LIT>Operand :: getStartLoc ( ) const { return this -> StartLoc ;


<s> static tree avr_fold_absfx ( tree tval ) { if ( FIXED_CST != TREE_CODE ( tval ) ) return NULL_TREE ; FIXED_VALUE_TYPE fval = TREE_FIXED_CST ( tval ) ;

unsigned int bits = GET_MODE_BITSIZE ( fval . mode ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) {

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


addPass ( create<ISA_LIT>AnnotateControlFlowPass ( ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : { int32_t Trunc = static_cast < int32_t > ( Imm ) ; return Trunc == Imm && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { return <STR_LIT> ( MO . getImm ( ) , ST . hasInv2PiInlineImm ( ) ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( isInt < <NUM_LIT> > ( Imm ) || isUInt < <NUM_LIT> > ( Imm ) ) { int16_t Trunc = static_cast < int16_t > ( Imm ) ; return ST . has16BitInsts ( ) && <STR_LIT> ( Trunc , ST . hasInv2PiInlineImm ( ) ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : {

uint32_t Trunc = static_cast < uint32_t > ( Imm ) ;


<s> static bool isUnscaledLdSt ( MachineInstr * MI ) { return isUnscaledLdSt ( MI -> getOpcode ( ) ) ;


<s> case 'w' : return C_RegisterClass ; case 'Q' : return C_Memory ; } } else if ( Constraint . size ( ) == <NUM_LIT> && Constraint [ <NUM_LIT> ] == 'U' && Constraint [ <NUM_LIT> ] == 'p' && ( Constraint [ <NUM_LIT> ] == 'l' || Constraint [ <NUM_LIT> ] == 'a' ) ) {


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : ReturnStackOffsetSet ( false ) , VarArgsFrameIndex ( <NUM_LIT> ) , ReturnStackOffset ( - <NUM_LIT> ) , MaxCallStackReq ( <NUM_LIT> ) {


<s> MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = MBBb ; SExtMap . clear ( ) ; for ( MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MII != MBB -> end ( ) ; ++ MII ) { MachineInstr * MI = MII ; if ( MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { SExtMap [ DstReg ] = SrcReg ; } } if ( MI -> isCopy ( ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { if ( unsigned SextSrc = SExtMap . lookup ( SrcReg ) ) { MI -> RemoveOperand ( <NUM_LIT> ) ; MI -> addOperand ( MachineOperand :: CreateReg ( SextSrc , false ) ) ; } } } } } return true ;


<s> auto IsExpiredFn = [ ] ( MachineInstr * MI , int ) { if ( ! MI ) return false ; unsigned Opc = MI -> getOpcode ( ) ; return <ISA_LIT>InstrInfo :: isVALU ( * MI ) && Opc != <STR_LIT> && Opc != <STR_LIT> && Opc != <STR_LIT> ; } ; if ( :: getWaitStatesSince ( IsHazardFn , MI , IsExpiredFn ) == std :: numeric_limits < int > :: max ( ) ) return false ; auto * Src0 = TII -> getNamedOperand ( * MI , <STR_LIT> :: src0 ) ; Register Reg = Src0 -> getReg ( ) ;


<s> if ( GET_MODE_SIZE ( mode ) <= UNITS_PER_WORD ) return <NUM_LIT> ; else return <NUM_LIT> ; }


<s> auto & MFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; auto & MRI = MF . getRegInfo ( ) ; for ( auto & MI : Split ) { for ( auto & MO : MI . explicit_uses ( ) ) { if ( ! MO . isReg ( ) || Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ; if ( MachineInstr * Def = MRI . getUniqueVRegDef ( MO . getReg ( ) ) ) if ( Def -> getParent ( ) == & MBB ) MFI . unstackifyVReg ( MO . getReg ( ) ) ; } } for ( MachineInstr & MI : llvm :: make_early_inc_range ( MBB ) ) { if ( ! <STR_LIT> ( MI . getOpcode ( ) ) ) continue ;

Register TeeReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> void <ISA_LIT>TargetStreamer :: emitMovSP ( unsigned Reg , int64_t Offset ) {


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : if ( Size < <NUM_LIT> ) return <STR_LIT> ; if ( Size > <NUM_LIT> ) return - <NUM_LIT> ; return sizeToSubRegIndex ( PowerOf2Ceil ( Size ) ) ;


<s> <ISA_LIT>WinCOFFObjectWriter :: <ISA_LIT>WinCOFFObjectWriter ( bool Is64Bit ) : MCWinCOFFObjectTargetWriter ( Is64Bit ? COFF :: IMAGE_FILE_MACHINE_AMD64 : COFF :: IMAGE_FILE_MACHINE_I386 ) {


<s> default : return TargetLowering :: findRepresentativeClass ( VT ) ; case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ; break ; case <STR_LIT> : RRC = & <STR_LIT> ; Cost = <NUM_LIT> ;


<s> const VOPInfo * Info = getVOP3OpcodeHelper ( Opc ) ; return Info ? Info -> IsSingle : false ;


<s> int direct_return ( ) { if ( ! reload_completed ) return FALSE ; if ( ! current_frame_info . initialized ) m32r_compute_frame_size ( get_frame_size ( ) ) ; return current_frame_info . total_size == <NUM_LIT> ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , CPUString ( CPU ) , TargetTriple ( TT ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( ) , TLInfo ( TM , * this ) {


<s> static const unsigned Idxs [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , } ; assert ( CI . Width >= <NUM_LIT> && CI . Width <= <NUM_LIT> ) ; assert ( Paired . Width >= <NUM_LIT> && Paired . Width <= <NUM_LIT> ) ; if ( ReverseOrder ) { Idx1 = Idxs [ <NUM_LIT> ] [ Paired . Width - <NUM_LIT> ] ; Idx0 = Idxs [ Paired . Width ] [ CI . Width - <NUM_LIT> ] ; } else {

Idx0 = Idxs [ <NUM_LIT> ] [ CI . Width - <NUM_LIT> ] ;


<s> TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; InitializeELF ( TM . Options . UseInitArray ) ;


return __builtin_mve_vctp16qhi ( __a ) ;


<s> for ( MutationList :: iterator it = Mutations . begin ( ) , ie = Mutations . end ( ) ;


<s> assert ( Kind == Memory && <STR_LIT> ) ; return Mem . FrontendSize ;


<s> if ( HAS_VLINDEX ( MCID . TSFlags ) ) return GET_VLINDEX ( MCID . TSFlags ) ;


return ( isReg ( ) && isRegClass ( <STR_LIT> ) ) || isInlineImm ( ) ;


<s> return FI <= InArgFIRange . first && FI >= InArgFIRange . second ;


Branch . addOperand ( MCOperand :: CreateExpr ( BranchTarget ) ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; if ( Op -> getOpcode ( ) == <STR_LIT> && isNullConstant ( LHS ) && isNullConstant ( RHS ) ) { Known . Zero |= APInt :: getHighBitsSet ( BitWidth , BitWidth - <NUM_LIT> ) ; return ; } } break ; case <STR_LIT> : { Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; if ( Known . isUnknown ( ) ) return ; KnownBits KnownRHS = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known . Zero &= KnownRHS . Zero ; Known . One &= KnownRHS . One ; return ; } case <STR_LIT> : { ConstantSDNode * CN = cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> IntID = static_cast < <STR_LIT> > ( CN -> getZExtValue ( ) ) ; switch ( IntID ) { default : return ;


<s> return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR16List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR16List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR32List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR32List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> ) { static const MCPhysReg FPR64List [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( FPR64List ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset4 = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset4 , LocVT , LocInfo ) ) ; return false ; } if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { unsigned Offset5 = State . AllocateStack ( <NUM_LIT> , Align ( <NUM_LIT> ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset5 , LocVT , LocInfo ) ) ; return false ; }


<s> int Op32DstIdx = <STR_LIT> ( Op32 , <STR_LIT> :: vdst ) ; if ( Op32DstIdx != - <NUM_LIT> ) { Inst32 . add ( MI . getOperand ( <NUM_LIT> ) ) ; } else { assert ( ( ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; } Inst32 . add ( * getNamedOperand ( MI , <STR_LIT> :: src0 ) ) ; const MachineOperand * Src1 = getNamedOperand ( MI , <STR_LIT> :: src1 ) ; if ( Src1 ) Inst32 . add ( * Src1 ) ; const MachineOperand * Src2 = getNamedOperand ( MI , <STR_LIT> :: src2 ) ; if ( Src2 ) { int Op32Src2Idx = <STR_LIT> ( Op32 , <STR_LIT> :: src2 ) ; if ( Op32Src2Idx != - <NUM_LIT> ) { Inst32 . add ( * Src2 ) ; } else { copyFlagsToImplicitVCC ( * Inst32 , * Src2 ) ; } }


<s> Dst = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( Size1 , DL , PtrVT ) ) ; DstPtrInfo = DstPtrInfo . getWithOffset ( Size1 ) ; SDValue Chain2 = memsetStore ( DAG , DL , Chain , Dst , ByteVal , Size2 , std :: min ( Align , Size1 ) , DstPtrInfo ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } else { if ( Bytes <= <NUM_LIT> ) { SDValue Chain1 = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , Align ) ; if ( Bytes == <NUM_LIT> ) return Chain1 ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , PtrVT , Dst , DAG . getConstant ( <NUM_LIT> , DL , PtrVT ) ) ; SDValue Chain2 = DAG . getStore ( Chain , DL , Byte , Dst2 , DstPtrInfo . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } assert ( Bytes >= <NUM_LIT> && <STR_LIT> ) ;

auto * CByte = dyn_cast < ConstantSDNode > ( Byte ) ;


<s> if ( Src . first -> getReg ( ) == AMDGPU :: ALU_LITERAL_X ) Literals . insert ( Src . second ) ; if ( Literals . size ( ) > <NUM_LIT> ) return false ; if ( Src . first -> getReg ( ) == AMDGPU :: ALU_CONST ) Consts . push_back ( Src . second ) ; if ( AMDGPU :: R600_KC0RegClass . contains ( Src . first -> getReg ( ) ) || AMDGPU :: R600_KC1RegClass . contains ( Src . first -> getReg ( ) ) ) { unsigned Index = RI . getEncodingValue ( Src . first -> getReg ( ) ) & <NUM_LIT> ; unsigned Chan = RI . getHWRegChan ( Src . first -> getReg ( ) ) ; Consts . push_back ( ( Index << <NUM_LIT> ) | Chan ) ; }


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateIndReg ( unsigned RegNum , SMLoc S , SMLoc E ) {

return std :: make_unique < <ISA_LIT>Operand > ( k_IndReg , RegNum , S , E ) ;


<s> void addCondCodeOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( CondCode ) ) ;


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ && Subtarget . isPICStyleGOT ( ) ) return MachineJumpTableInfo :: EK_Custom32 ; return TargetLowering :: getJumpTableEncoding ( ) ;


<s> return new <ISA_LIT>SetWavePriority ( ) ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( getMemBaseReg ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( getMemScale ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemIndexReg ( ) ) ) ; addExpr ( Inst , getMemDisp ( ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemSegReg ( ) ) ) ;


<s> TargetTransformInfo <ISA_LIT>TargetMachine :: getTargetTransformInfo ( const Function & F ) {

return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;


<s> return __builtin_mve_vdupq_m_n_uv4si ( __arm_vuninitializedq_u32 ( ) , __a , __p ) ;


<s> fprintf ( FILE , <STR_LIT> , XSTR ( SYMREF , <NUM_LIT> ) , XSTR ( SYMREF , <NUM_LIT> ) , arc_mangle_suffix ) ;


<s> if ( ! isImm ( ) ) return false ; if ( const auto * ConstExpr = dyn_cast < MCConstantExpr > ( Imm . Val ) ) { int64_t Value = ConstExpr -> getValue ( ) ;


<s> static rtx_insn * next_insn_to_bundle ( rtx_insn * r , rtx_insn * end ) { for ( ; r != end ; r = NEXT_INSN ( r ) ) { if ( NONDEBUG_INSN_P ( r ) && GET_CODE ( PATTERN ( r ) ) != USE && GET_CODE ( PATTERN ( r ) ) != CLOBBER ) return r ; } return NULL ;


<s> doubleword_aligned_p = tilegx_function_arg_boundary ( arg . mode , arg . type ) > BITS_PER_WORD ; if ( doubleword_aligned_p ) * cum += * cum & <NUM_LIT> ; if ( * cum < TILEGX_NUM_ARG_REGS && * cum + word_size > TILEGX_NUM_ARG_REGS ) * cum = TILEGX_NUM_ARG_REGS ;


<s> ConstantSDNode * ConstVal = cast < ConstantSDNode > ( N ) ; uint64_t ImmVal = ConstVal -> getZExtValue ( ) ; uint64_t SupportedMask = <NUM_LIT> ; if ( ( ImmVal & SupportedMask ) != ImmVal ) { return SelectCode ( N ) ; } uint64_t LoMask = <NUM_LIT> ; uint64_t HiMask = <NUM_LIT> ; uint64_t ImmLo = ( ImmVal & LoMask ) ; uint64_t ImmHi = ( ImmVal & HiMask ) ; SDValue ConstLo = CurDAG -> getTargetConstant ( ImmLo , N , <STR_LIT> ) ;

MachineSDNode * Move = CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , ConstLo ) ;


<s> unsigned TruncBits = <NUM_LIT> ; unsigned SExtBits = <NUM_LIT> ; unsigned ZExtBits = <NUM_LIT> ; if ( UserI -> hasOneUse ( ) ) { unsigned UserBits = UserI -> getType ( ) -> getScalarSizeInBits ( ) ; if ( isa < TruncInst > ( UserI ) ) TruncBits = UserBits ; else if ( isa < SExtInst > ( UserI ) ) SExtBits = UserBits ; else if ( isa < ZExtInst > ( UserI ) ) ZExtBits = UserBits ; } if ( TruncBits || SExtBits || ZExtBits ) { FoldedValue = UserI ; UserI = cast < Instruction > ( * UserI -> user_begin ( ) ) ; } if ( ( UserI -> getOpcode ( ) == Instruction :: Sub || UserI -> getOpcode ( ) == Instruction :: SDiv || UserI -> getOpcode ( ) == Instruction :: UDiv ) && UserI -> getOperand ( <NUM_LIT> ) != FoldedValue ) return false ; unsigned LoadOrTruncBits = ( ( SExtBits || ZExtBits ) ? <NUM_LIT> : ( TruncBits ? TruncBits : LoadedBits ) ) ; switch ( UserI -> getOpcode ( ) ) { case Instruction :: Add :


<s> case <STR_LIT> : return Value ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : return Value & <NUM_LIT> ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> void <ISA_LIT>InstPrinter :: printVectorIndex ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm ( ) << <STR_LIT> ;


<s> const Triple & TT = TM -> getTargetTriple ( ) ; IsAMDGCN = TT . getArch ( ) == Triple :: amdgcn ; IsAMDHSA = TT . getOS ( ) == Triple :: AMDHSA ; return false ;


<s> } SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; if ( VA . needsCustom ( ) ) { assert ( VA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; Passv64i1ArgInRegs ( dl , DAG , Chain , ValToCopy , RegsToPass , VA , RVLocs [ ++ I ] , Subtarget ) ; assert ( <NUM_LIT> == RegsToPass . size ( ) && <STR_LIT> ) ; if ( ShouldDisableCalleeSavedRegister ) MF . getRegInfo ( ) . disableCalleeSavedRegister ( RVLocs [ I ] . getLocReg ( ) ) ; } else { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , ValToCopy ) ) ; } for ( auto & Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , dl , Reg . first , Reg . second , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ; } } if ( unsigned SRetReg = FuncInfo -> getSRetReturnReg ( ) ) { SDValue Val = DAG . getCopyFromReg ( RetOps [ <NUM_LIT> ] , dl , SRetReg , getPointerTy ( MF . getDataLayout ( ) ) ) ; unsigned RetValReg = ( Subtarget . is64Bit ( ) && ! Subtarget . isTarget64BitILP32 ( ) ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , RetValReg , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetValReg , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; if ( ShouldDisableCalleeSavedRegister ) MF . getRegInfo ( ) . disableCalleeSavedRegister ( RetValReg ) ; } const <ISA_LIT>RegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; const MCPhysReg * I = TRI -> getCalleeSavedRegsViaCopy ( & DAG . getMachineFunction ( ) ) ; if ( I ) { for ( ; * I ; ++ I ) { if ( <STR_LIT> . contains ( * I ) ) RetOps . push_back ( DAG . getRegister ( * I , <STR_LIT> ) ) ; else llvm_unreachable ( <STR_LIT> ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ;


<s> MachineBasicBlock :: iterator MBBI ( MI ) ; unsigned Dest = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( hasCalls ) { TRI -> addOffset ( MBB , MBBI , DL , Dest , Src , Offset ) ; } else { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Src ) ; } ++ II ; MI -> eraseFromParent ( ) ;


<s> auto IsAtomic = InstName . contains ( <STR_LIT> ) ; if ( IsLoadStore || IsAtomic ) { if ( IsLoadStore && isNext ( AsmToken :: Colon ) ) { auto Id = expectIdent ( ) ; if ( Id != <STR_LIT> ) return error ( <STR_LIT> + Id ) ; if ( expect ( AsmToken :: Equal , <STR_LIT> ) ) return true ; if ( ! Lexer . is ( AsmToken :: Integer ) ) return error ( <STR_LIT> ) ; parseSingleInteger ( false , Operands ) ; } else { auto IsLoadStoreLane = InstName . contains ( <STR_LIT> ) ; if ( IsLoadStoreLane && Operands . size ( ) == <NUM_LIT> ) return false ; auto Tok = Lexer . getTok ( ) ; Operands . push_back ( std :: make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Tok . getLoc ( ) , Tok . getEndLoc ( ) , <STR_LIT> { - <NUM_LIT> } ) ) ;


<s> const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > DefsA ; SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( Register :: isPhysicalRegister ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ;

if ( Register :: isPhysicalRegister ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegA == * SubRegs ) return true ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * TRI = STI . getRegisterInfo ( ) ; return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || TRI -> hasStackRealignment ( MF ) ;


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> Register SaveExecDest = SaveExec . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! TRI -> isSGPRReg ( MRI , SaveExecDest ) ) return nullptr ; MachineOperand * SaveExecSrc0 = TII -> getNamedOperand ( SaveExec , <STR_LIT> :: src0 ) ; if ( ! SaveExecSrc0 -> isReg ( ) ) return nullptr ; VCmp = findInstrBackwards ( SaveExec , [ & ] ( MachineInstr * Check ) { return <STR_LIT> ( Check -> getOpcode ( ) ) != - <NUM_LIT> && Check -> modifiesRegister ( SaveExecSrc0 -> getReg ( ) , TRI ) ; } , { Exec , SaveExecSrc0 -> getReg ( ) } , TRI ) ; if ( ! VCmp ) return nullptr ; MachineOperand * VCmpDest = TII -> getNamedOperand ( * VCmp , <STR_LIT> :: sdst ) ; assert ( VCmpDest && <STR_LIT> ) ; MachineOperand * Src0 = TII -> getNamedOperand ( * VCmp , <STR_LIT> :: src0 ) ;

if ( Src0 -> isReg ( ) && TRI -> isSGPRReg ( MRI , Src0 -> getReg ( ) ) && SaveExec . modifiesRegister ( Src0 -> getReg ( ) , TRI ) ) return nullptr ;


<s> return Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , * this ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI ) : MCDisassembler ( STI ) {


<s> if ( ! PSB ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreatePSBHint ( PSB -> Encoding , Tok . getString ( ) , S , getContext ( ) ) ) ;


<s> unsigned int __i = ( unsigned short ) __w << <NUM_LIT> | ( unsigned short ) __w ;


<s> static bool ix86_hard_regno_scratch_ok ( unsigned int regno ) { return ( ! cfun -> machine -> no_caller_saved_registers || ( ! epilogue_completed && df_regs_ever_live_p ( regno ) ) ) ;


<s> unsigned SGPRReg = AMDGPU :: NoRegister ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { int Idx = VOP3Idx [ i ] ; if ( Idx == - <NUM_LIT> ) continue ; MachineOperand & MO = MI -> getOperand ( Idx ) ; if ( MO . isReg ( ) ) { if ( ! RI . isSGPRClass ( MRI . getRegClass ( MO . getReg ( ) ) ) ) continue ; assert ( MO . getReg ( ) != AMDGPU :: SCC && <STR_LIT> ) ; if ( SGPRReg == AMDGPU :: NoRegister || SGPRReg == MO . getReg ( ) ) { SGPRReg = MO . getReg ( ) ; continue ; } } else if ( ! isLiteralConstant ( MO ) ) { continue ; } legalizeOpWithMove ( MI , Idx ) ; } } if ( MI -> getOpcode ( ) == AMDGPU :: REG_SEQUENCE ) { const TargetRegisterClass * RC = NULL , * SRC = NULL , * VRC = NULL ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; i += <NUM_LIT> ) { if ( ! MI -> getOperand ( i ) . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MI -> getOperand ( i ) . getReg ( ) ) ) continue ; const TargetRegisterClass * OpRC = MRI . getRegClass ( MI -> getOperand ( i ) . getReg ( ) ) ; if ( RI . hasVGPRs ( OpRC ) ) { VRC = OpRC ; } else { SRC = OpRC ; } } if ( VRC || ! RI . isSGPRClass ( getOpRegClass ( * MI , <NUM_LIT> ) ) ) { if ( ! VRC ) { assert ( SRC ) ; VRC = RI . getEquivalentVGPRClass ( SRC ) ; } RC = VRC ; } else { RC = SRC ; } for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; i += <NUM_LIT> ) { if ( ! MI -> getOperand ( i ) . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MI -> getOperand ( i ) . getReg ( ) ) ) continue ; unsigned DstReg = MRI . createVirtualRegister ( RC ) ; BuildMI ( * MI -> getParent ( ) , MI , MI -> getDebugLoc ( ) , get ( AMDGPU :: COPY ) , DstReg ) . addOperand ( MI -> getOperand ( i ) ) ; MI -> getOperand ( i ) . setReg ( DstReg ) ; }


<s> static void rs6000_xcoff_asm_output_anchor ( rtx symbol ) { char buffer [ <NUM_LIT> ] ; sprintf ( buffer , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , SYMBOL_REF_BLOCK_OFFSET ( symbol ) ) ; fprintf ( asm_out_file , <STR_LIT> , SET_ASM_OP ) ; RS6000_OUTPUT_BASENAME ( asm_out_file , XSTR ( symbol , <NUM_LIT> ) ) ; fprintf ( asm_out_file , <STR_LIT> ) ;

RS6000_OUTPUT_BASENAME ( asm_out_file , buffer ) ;


<s> continue ; } case AsmToken :: Hash : { bool MustNotExtend = false ; bool ImplicitExpression = implicitExpressionLocation ( Operands ) ; SMLoc ExprLoc = Lexer . getLoc ( ) ; if ( ! ImplicitExpression ) Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( Token . getString ( ) , Token . getLoc ( ) ) ) ; Lexer . Lex ( ) ; bool MustExtend = false ; bool HiOnly = false ; bool LoOnly = false ; if ( Lexer . is ( AsmToken :: Hash ) ) { Lexer . Lex ( ) ; MustExtend = true ; } else if ( ImplicitExpression ) MustNotExtend = true ; AsmToken const & Token = Parser . getTok ( ) ; if ( Token . is ( AsmToken :: Identifier ) ) { StringRef String = Token . getString ( ) ; AsmToken IDToken = Token ; if ( String . lower ( ) == <STR_LIT> ) { HiOnly = true ; } else if ( String . lower ( ) == <STR_LIT> ) { LoOnly = true ; } if ( HiOnly || LoOnly ) { AsmToken LParen = Lexer . peekTok ( ) ; if ( ! LParen . is ( AsmToken :: LParen ) ) { HiOnly = false ; LoOnly = false ; } else { Lexer . Lex ( ) ; } } } MCExpr const * Expr = nullptr ; if ( parseExpression ( Expr ) ) return true ; int64_t Value ; MCContext & Context = Parser . getContext ( ) ; assert ( Expr != nullptr ) ; if ( Expr -> evaluateAsAbsolute ( Value ) ) { if ( HiOnly ) Expr = MCBinaryExpr :: createLShr ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Context ) , Context ) ; if ( HiOnly || LoOnly ) Expr = MCBinaryExpr :: createAnd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , Context ) , Context ) ; } else { MCValue Value ; if ( Expr -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ) { if ( ! Value . isAbsolute ( ) ) { switch ( Value . getAccessVariant ( ) ) { case MCSymbolRefExpr :: VariantKind :: VK_TPREL : case MCSymbolRefExpr :: VariantKind :: VK_DTPREL : MustNotExtend = ! MustExtend ; break ; default : break ; } } } } Expr = <ISA_LIT>MCExpr :: create ( Expr , Context ) ;

<ISA_LIT>MCInstrInfo :: setMustNotExtend ( * Expr , MustNotExtend ) ;


<s> return <STR_LIT> :: I64 ; case <STR_LIT> : return <STR_LIT> :: F32 ; case <STR_LIT> : return <STR_LIT> :: F64 ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> :: V128 ; case <STR_LIT> : return <STR_LIT> :: FUNCREF ; case <STR_LIT> : return <STR_LIT> :: EXTERNREF ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> if ( val & <NUM_LIT> ) val = ~ val ; first_one = val & - val ; tmp = val & ( val + first_one ) ; if ( tmp == <NUM_LIT> ) return true ; next_one = tmp & - tmp ; bits = clz_hwi ( first_one ) - clz_hwi ( next_one ) ; mask = val ^ tmp ; if ( ( mask >> bits ) != <NUM_LIT> || bits != ( bits & - bits ) ) return false ;

return val == mask * bitmask_imm_mul [ __builtin_clz ( bits ) - <NUM_LIT> ] ;


<s> int NumElts = VT . getVectorNumElements ( ) ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ NumElts ] ( int M ) { return M >= NumElts ; } ) ; if ( NumV2Elements == <NUM_LIT> && Mask [ <NUM_LIT> ] >= NumElts ) if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( DL , VT , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; if ( VT . isInteger ( ) && ! Subtarget -> hasAVX2 ( ) ) { int ElementBits = VT . getScalarSizeInBits ( ) ; if ( ElementBits < <NUM_LIT> ) return splitAndLowerVectorShuffle ( DL , VT , V1 , V2 , Mask , DAG ) ; MVT FpVT = <STR_LIT> ( <STR_LIT> ( ElementBits ) , VT . getVectorNumElements ( ) ) ; V1 = DAG . getNode ( <STR_LIT> , DL , FpVT , V1 ) ; V2 = DAG . getNode ( <STR_LIT> , DL , FpVT , V2 ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getVectorShuffle ( FpVT , DL , V1 , V2 , Mask ) ) ; } switch ( VT . SimpleTy ) { case <STR_LIT> : return lowerV4F64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV4I64VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8F32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV8I32VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV16I16VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; case <STR_LIT> : return lowerV32I8VectorShuffle ( Op , V1 , V2 , Subtarget , DAG ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> int br = <NUM_LIT> ; if ( crtl -> is_leaf ) for ( br = <NUM_LIT> ; br >= <NUM_LIT> && df_regs_ever_live_p ( br ) ; br -- ) ;

cfun -> machine -> base_reg = gen_rtx_REG ( Pmode , ( br >= <NUM_LIT> ) ? br : BASE_REGNUM ) ;


<s> using ValueEntry = std :: pair < SDValue , size_t > ; SmallVector < ValueEntry , <NUM_LIT> > SplatValueCounts ; using SwizzleEntry = std :: pair < std :: pair < SDValue , SDValue > , size_t > ; SmallVector < SwizzleEntry , <NUM_LIT> > SwizzleCounts ; auto AddCount = [ ] ( auto & Counts , const auto & Val ) { auto CountIt = std :: find_if ( Counts . begin ( ) , Counts . end ( ) , [ & Val ] ( auto E ) { return E . first == Val ; } ) ; if ( CountIt == Counts . end ( ) ) { Counts . emplace_back ( Val , <NUM_LIT> ) ; } else { CountIt -> second ++ ; } } ; auto GetMostCommon = [ ] ( auto & Counts ) { auto CommonIt = std :: max_element ( Counts . begin ( ) , Counts . end ( ) , [ ] ( auto A , auto B ) { return A . second < B . second ; } ) ; assert ( CommonIt != Counts . end ( ) && <STR_LIT> ) ; return * CommonIt ; } ; size_t NumConstantLanes = <NUM_LIT> ; for ( size_t I = <NUM_LIT> ; I < Lanes ; ++ I ) { const SDValue & Lane = Op -> getOperand ( I ) ; if ( Lane . isUndef ( ) ) continue ; AddCount ( SplatValueCounts , Lane ) ; if ( IsConstant ( Lane ) ) { NumConstantLanes ++ ; } else if ( CanSwizzle ) { auto SwizzleSrcs = GetSwizzleSrcs ( I , Lane ) ; if ( SwizzleSrcs . first ) AddCount ( SwizzleCounts , SwizzleSrcs ) ; } } SDValue SplatValue ; size_t NumSplatLanes ; std :: tie ( SplatValue , NumSplatLanes ) = GetMostCommon ( SplatValueCounts ) ; SDValue SwizzleSrc ; SDValue SwizzleIndices ; size_t NumSwizzleLanes = <NUM_LIT> ; if ( SwizzleCounts . size ( ) ) std :: forward_as_tuple ( std :: tie ( SwizzleSrc , SwizzleIndices ) , NumSwizzleLanes ) = GetMostCommon ( SwizzleCounts ) ; std :: function < bool ( size_t , const SDValue & ) > IsLaneConstructed ; SDValue Result ; if ( NumSwizzleLanes >= NumSplatLanes && ( ! Subtarget -> hasUnimplementedSIMD128 ( ) || NumSwizzleLanes >= NumConstantLanes ) ) { Result = DAG . getNode ( <STR_LIT> , DL , VecT , SwizzleSrc , SwizzleIndices ) ; auto Swizzled = std :: make_pair ( SwizzleSrc , SwizzleIndices ) ; IsLaneConstructed = [ & , Swizzled ] ( size_t I , const SDValue & Lane ) { return Swizzled == GetSwizzleSrcs ( I , Lane ) ; } ; } else if ( NumConstantLanes >= NumSplatLanes && Subtarget -> hasUnimplementedSIMD128 ( ) ) { SmallVector < SDValue , <NUM_LIT> > ConstLanes ;

for ( const SDValue & Lane : Op -> op_values ( ) ) {


<s> if ( ! LHSReg ) return <NUM_LIT> ; unsigned ResultReg = <NUM_LIT> ; if ( const auto * C = dyn_cast < ConstantInt > ( RHS ) ) { uint64_t Imm = C -> getZExtValue ( ) ; ResultReg = emitLogicalOp_ri ( ISDOpc , RetVT , LHSReg , Imm ) ; } if ( ResultReg ) return ResultReg ; if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) { if ( isMulPowOf2 ( RHS ) ) { const Value * MulLHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; const Value * MulRHS = cast < MulOperator > ( RHS ) -> getOperand ( <NUM_LIT> ) ; if ( const auto * C = dyn_cast < ConstantInt > ( MulLHS ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) std :: swap ( MulLHS , MulRHS ) ; assert ( isa < ConstantInt > ( MulRHS ) && <STR_LIT> ) ; uint64_t ShiftVal = cast < ConstantInt > ( MulRHS ) -> getValue ( ) . logBase2 ( ) ; unsigned RHSReg = getRegForValue ( MulLHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; ResultReg = emitLogicalOp_rs ( ISDOpc , RetVT , LHSReg , RHSReg , ShiftVal ) ; if ( ResultReg ) return ResultReg ; } } if ( RHS -> hasOneUse ( ) && isValueAvailable ( RHS ) ) { if ( const auto * SI = dyn_cast < ShlOperator > ( RHS ) ) if ( const auto * C = dyn_cast < ConstantInt > ( SI -> getOperand ( <NUM_LIT> ) ) ) { uint64_t ShiftVal = C -> getZExtValue ( ) ; unsigned RHSReg = getRegForValue ( SI -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHSReg ) return <NUM_LIT> ; ResultReg = emitLogicalOp_rs ( ISDOpc , RetVT , LHSReg , RHSReg , ShiftVal ) ; if ( ResultReg ) return ResultReg ; } } unsigned RHSReg = getRegForValue ( RHS ) ; if ( ! RHSReg ) return <NUM_LIT> ; MVT VT = std :: max ( <STR_LIT> , RetVT . SimpleTy ) ; ResultReg = fastEmit_rr ( VT , VT , ISDOpc , LHSReg , RHSReg ) ; if ( RetVT >= <STR_LIT> && RetVT <= <STR_LIT> ) { uint64_t Mask = ( RetVT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; ResultReg = emitAnd_ri ( <STR_LIT> , ResultReg , Mask ) ; }


<s> <ISA_LIT>Operand ( KindTy K , SMLoc Start , SMLoc End ) : Kind ( K ) , StartLoc ( Start ) , EndLoc ( End ) , OpDecl ( nullptr ) , AddressOf ( false ) , CallOperand ( false ) {


<s> CFStack ( const <ISA_LIT>Subtarget * st , CallingConv :: ID cc ) : ST ( st ) , MaxStackSize ( cc == CallingConv :: <ISA_LIT>_VS ? <NUM_LIT> : <NUM_LIT> ) {


<s> if ( GET_CODE ( op ) != CONST_INT ) return H8SX_SHIFT_BINARY ; if ( INTVAL ( op ) <= <NUM_LIT> || INTVAL ( op ) >= GET_MODE_BITSIZE ( mode ) ) return H8SX_SHIFT_NONE ; if ( exact_log2 ( INTVAL ( op ) ) >= <NUM_LIT> ) return H8SX_SHIFT_UNARY ; return H8SX_SHIFT_BINARY ; case ASHIFTRT : if ( op == const1_rtx || op == const2_rtx ) return H8SX_SHIFT_UNARY ; return H8SX_SHIFT_NONE ;


<s> if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ; return ( Cnt >= <NUM_LIT> && ( isLong ? Cnt - <NUM_LIT> : Cnt ) < ElementBits ) ;


<s> LowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! IsN64 ) return getAddrNonPIC ( Op , DAG ) ;

return getAddrLocal ( Op , DAG , Has<ISA_LIT>64 ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default :


<s> MBBb != MBBe ; ++ MBBb ) { MachineBasicBlock * MBB = MBBb ; PeepholeMap . clear ( ) ; PeepholeDoubleRegsMap . clear ( ) ; for ( MachineBasicBlock :: iterator MII = MBB -> begin ( ) ; MII != MBB -> end ( ) ; ++ MII ) { MachineInstr * MI = MII ; if ( ! DisableOptSZExt && MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { PeepholeMap [ DstReg ] = SrcReg ; } } if ( ! DisableOptExtTo64 && MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src2 = MI -> getOperand ( <NUM_LIT> ) ; if ( Src1 . getImm ( ) != <NUM_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src2 . getReg ( ) ; PeepholeMap [ DstReg ] = SrcReg ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src1 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src2 = MI -> getOperand ( <NUM_LIT> ) ; if ( Src2 . getImm ( ) != <NUM_LIT> ) continue ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src1 . getReg ( ) ; PeepholeDoubleRegsMap [ DstReg ] = std :: make_pair ( * & SrcReg , <NUM_LIT> ) ; } if ( ! DisablePNotP && ( MI -> getOpcode ( ) == <STR_LIT> ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; unsigned DstReg = Dst . getReg ( ) ; unsigned SrcReg = Src . getReg ( ) ; if ( TargetRegisterInfo :: isVirtualRegister ( DstReg ) && TargetRegisterInfo :: isVirtualRegister ( SrcReg ) ) { PeepholeMap [ DstReg ] = SrcReg ; } } if ( ! DisableOptSZExt && MI -> isCopy ( ) ) { assert ( MI -> getNumOperands ( ) == <NUM_LIT> ) ; MachineOperand & Dst = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; if ( Src . getSubReg ( ) != <STR_LIT> ) continue ;


<s> bool <ISA_LIT>AsmParser :: validateCoherencyBits ( const MCInst & Inst , const OperandVector & Operands , const SMLoc & IDLoc ) { int GLCPos = <STR_LIT> ( Inst . getOpcode ( ) , <STR_LIT> :: glc1 ) ; if ( GLCPos != - <NUM_LIT> ) { if ( Inst . getOperand ( GLCPos ) . getImm ( ) == - <NUM_LIT> ) { Error ( IDLoc , <STR_LIT> ) ;


<s> WorkList . push_back ( User ) ; continue ; } Instruction * UseInst = dyn_cast < Instruction > ( User ) ; if ( UseInst && UseInst -> getOpcode ( ) == Instruction :: PtrToInt ) return false ; if ( StoreInst * <ISA_LIT> = dyn_cast_or_null < StoreInst > ( UseInst ) ) { if ( <ISA_LIT> -> isVolatile ( ) ) return false ; if ( <ISA_LIT> -> getPointerOperand ( ) != Val ) return false ; } else if ( LoadInst * LI = dyn_cast_or_null < LoadInst > ( UseInst ) ) { if ( LI -> isVolatile ( ) ) return false ; } else if ( AtomicRMWInst * RMW = dyn_cast_or_null < AtomicRMWInst > ( UseInst ) ) { if ( RMW -> isVolatile ( ) ) return false ; } else if ( AtomicCmpXchgInst * CAS = dyn_cast_or_null < AtomicCmpXchgInst > ( UseInst ) ) { if ( CAS -> isVolatile ( ) ) return false ; } if ( ! User -> getType ( ) -> isPointerTy ( ) ) continue ; WorkList . push_back ( User ) ; if ( ! collectUsesWithPtrTypes ( User , WorkList ) ) return false ; } return true ;


<s> enum rtx_code cmp_code = GET_CODE ( operands [ <NUM_LIT> ] ) ; enum machine_mode mode = GET_MODE ( cmp_operands [ <NUM_LIT> ] ) ; switch ( cmp_code ) { case GT : cmp_code = LT ; break ; case LE : cmp_code = GE ; break ; case GTU : cmp_code = LTU ; break ; case LEU : cmp_code = GEU ; break ; default : break ; } if ( cmp_code == GET_CODE ( operands [ <NUM_LIT> ] ) ) { op0 = cmp_operands [ <NUM_LIT> ] ; op1 = cmp_operands [ <NUM_LIT> ] ; } else {


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ;


<s> MCSymbolData & SD = Asm . getSymbolData ( R . Sym -> AliasedSymbol ( ) ) ;

return ( ( R . Reloc . Type == ELF :: R_MIPS_GOT16 ) && ! SD . isExternal ( ) ) || ( R . Reloc . Type == ELF :: R_MIPS_HI16 ) ;


<s> if ( FirstSPAdjustAmount ) { uint64_t SecondSPAdjustAmount = MFI . getStackSize ( ) - FirstSPAdjustAmount ; assert ( SecondSPAdjustAmount > <NUM_LIT> && <STR_LIT> ) ; adjustReg ( MBB , MBBI , DL , SPReg , SPReg , - SecondSPAdjustAmount , MachineInstr :: FrameSetup ) ; if ( ! hasFP ( MF ) ) { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: cfiDefCfaOffset ( nullptr , MFI . getStackSize ( ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } } if ( RVVStackSize ) adjustStackForRVV ( MF , MBB , MBBI , DL , - RVVStackSize , MachineInstr :: FrameSetup ) ; if ( hasFP ( MF ) ) { const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; if ( RI -> hasStackRealignment ( MF ) ) { Align MaxAlignment = MFI . getMaxAlign ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; if ( isInt < <NUM_LIT> > ( - ( int ) MaxAlignment . value ( ) ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( SPReg ) . addImm ( - ( int ) MaxAlignment . value ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { unsigned ShiftAmount = Log2 ( MaxAlignment ) ; Register VR = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( SPReg ) . addImm ( ShiftAmount ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , SPReg ) . addReg ( VR ) . addImm ( ShiftAmount ) . setMIFlag ( MachineInstr :: FrameSetup ) ; }


<s> if ( Pairs [ i ] . Name == LowerCaseName ) { Valid = true ; return Pairs [ i ] . Value ;


<s> else reg [ <NUM_LIT> ] = operands [ <NUM_LIT> ] ; } for ( num_reg = ( mode == DImode ) ? <NUM_LIT> : <NUM_LIT> ; num_reg > <NUM_LIT> ; num_reg -- ) { sub_reg = gen_lowpart ( QImode , reg [ <NUM_LIT> ] ) ; mem [ <NUM_LIT> ] = gen_rtx_MEM ( QImode , plus_constant ( Pmode , operands [ <NUM_LIT> ] , offset ) ) ; emit_move_insn ( sub_reg , mem [ <NUM_LIT> ] ) ; emit_insn ( gen_zero_extendqisi2 ( reg [ <NUM_LIT> ] , sub_reg ) ) ; while ( width > <NUM_LIT> ) { offset = offset + offset_adj ; shift ++ ; width -- ; mem [ <NUM_LIT> ] = gen_rtx_MEM ( QImode , plus_constant ( Pmode , operands [ <NUM_LIT> ] , offset ) ) ; emit_move_insn ( temp_sub_reg , mem [ <NUM_LIT> ] ) ; emit_insn ( gen_ashlsi3 ( temp_reg , temp_reg , GEN_INT ( shift * <NUM_LIT> ) ) ) ; emit_insn ( gen_iorsi3 ( reg [ <NUM_LIT> ] , reg [ <NUM_LIT> ] , temp_reg ) ) ; } if ( mode == DImode ) { reg [ <NUM_LIT> ] = reg [ <NUM_LIT> ] ; shift = <NUM_LIT> ;

width = GET_MODE_SIZE ( SImode ) - <NUM_LIT> ;


<s> void setSRetReturnReg ( unsigned Reg ) {


<s> ShiftVT = ByteShift ? <STR_LIT> ( <STR_LIT> , SizeInBits / <NUM_LIT> ) : <STR_LIT> ( ShiftSVT , Size / Scale ) ; return ( int ) ShiftAmt ; } ; unsigned MaxWidth = ( ( SizeInBits == <NUM_LIT> ) && ! Subtarget . hasBWI ( ) ? <NUM_LIT> : <NUM_LIT> ) ; for ( int Scale = <NUM_LIT> ; Scale * ScalarSizeInBits <= MaxWidth ; Scale *= <NUM_LIT> ) for ( int Shift = <NUM_LIT> ; Shift != Scale ; ++ Shift ) for ( bool Left : { true , false } ) if ( CheckZeros ( Shift , Scale , Left ) ) { int ShiftAmt = MatchShift ( Shift , Scale , Left ) ; if ( <NUM_LIT> < ShiftAmt ) return ShiftAmt ; }


<s> const LLT v16s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v64s8 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v32s16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v16s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v4s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v8s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v8s32 , v4s64 } ) setAction ( { MemOp , Ty } , Legal ) ; for ( auto Ty : { v32s8 , v16s16 , v8s32 , v4s64 } ) { setAction ( { G_INSERT , Ty } , Legal ) ; setAction ( { G_EXTRACT , <NUM_LIT> , Ty } , Legal ) ; } for ( auto Ty : { v16s8 , v8s16 , v4s32 , v2s64 } ) { setAction ( { G_INSERT , <NUM_LIT> , Ty } , Legal ) ; setAction ( { G_EXTRACT , Ty } , Legal ) ; } for ( const auto & Ty : { v32s8 , v64s8 , v16s16 , v32s16 , v8s32 , v16s32 , v4s64 , v8s64 } ) {

setAction ( { G_MERGE_VALUES , Ty } , Legal ) ;


<s> Error ( StartLoc , <STR_LIT> , SMRange ( StartLoc , EndLoc ) ) ; return <NUM_LIT> ; } } if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; IndexLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Percent ) ) { SMLoc L ; if ( ParseRegister ( IndexReg , L , L ) ) return <NUM_LIT> ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t ScaleVal ; if ( getParser ( ) . ParseAbsoluteExpression ( ScaleVal ) ) { Error ( Loc , <STR_LIT> ) ; return <NUM_LIT> ; } if ( ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> && ScaleVal != <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return <NUM_LIT> ; } Scale = ( unsigned ) ScaleVal ; } } } else if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { SMLoc Loc = Parser . getTok ( ) . getLoc ( ) ; int64_t Value ; if ( getParser ( ) . ParseAbsoluteExpression ( Value ) ) return <NUM_LIT> ; if ( Value != <NUM_LIT> ) Warning ( Loc , <STR_LIT> ) ; Scale = <NUM_LIT> ; } } if ( getLexer ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } SMLoc MemEnd = Parser . getTok ( ) . getLoc ( ) ;


<s> return __builtin_mve_vshlq_sv16qi ( __a , __b ) ;


<s> static const uint16_t DoubleRegDecoderTable [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; return ( DecodeRegisterClass ( Inst , RegNo >> <NUM_LIT> , DoubleRegDecoderTable , sizeof ( DoubleRegDecoderTable ) ) ) ;


<s> unsigned Directive = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getCPUDirective ( ) ;


<s> MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( MRI . getRegClass ( MI . getOperand ( OpIdx2 ) . getReg ( ) ) -> hasSuperClassEq ( & <STR_LIT> ) ) { if ( ! safeToCommute ( MI , OpIdx1 , OpIdx2 ) ) return nullptr ; }

return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ;


<s> else if ( IsReturn ) DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getNumber ( ) << <STR_LIT> ; ) ; return IsReturn ;


<s> virtual void emitMachine ( StringRef CPU ) {


<s> if ( ! ST . isVGPRSpillingEnabled ( * MF -> getFunction ( ) ) ) { LLVMContext & Ctx = MF -> getFunction ( ) -> getContext ( ) ; Ctx . emitError ( <STR_LIT> <STR_LIT> ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) ; return ; } assert ( RI . hasVGPRs ( RC ) && <STR_LIT> ) ; unsigned Opcode = getVGPRSpillRestoreOpcode ( RC -> getSize ( ) ) ; BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addReg ( MFI -> getScratchRSrcReg ( ) ) . addReg ( MFI -> getScratchWaveOffsetReg ( ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> if ( Worklist . empty ( ) ) return false ;

const RangeTy & Range = Worklist . back ( ) ;


<s> unsigned <ISA_LIT>TTI :: getMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace ) const { if ( VectorType * VTy = dyn_cast < VectorType > ( Src ) ) { unsigned NumElem = VTy -> getVectorNumElements ( ) ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { unsigned Cost = TargetTransformInfo :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace ) ;

unsigned SplitCost = getScalarizationOverhead ( Src , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ;


insertPass ( & MachineSchedulerID , & RegisterCoalescerID ) ;


<s> MachineJumpTableInfo * JTI = MF -> getOrCreateJumpTableInfo ( getJumpTableEncoding ( ) ) ; unsigned MJTI = JTI -> createJumpTableIndex ( LPadList ) ; const <ISA_LIT>InstrInfo * XII = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) ; const <ISA_LIT>RegisterInfo & RI = XII -> getRegisterInfo ( ) ; if ( RI . hasBasePointer ( * MF ) ) { const bool FPIs64Bit = Subtarget . isTarget64BitLP64 ( ) || Subtarget . isTargetNaCl64 ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MFI -> setRestoreBasePointer ( MF ) ; unsigned FP = RI . getFrameRegister ( * MF ) ; unsigned BP = RI . getBaseRegister ( ) ; unsigned Op = FPIs64Bit ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( DispatchBB , DL , TII -> get ( Op ) , BP ) , FP , true , MFI -> getRestoreBasePointerOffset ( ) ) . addRegMask ( RI . getNoPreservedMask ( ) ) ; } else { BuildMI ( DispatchBB , DL , TII -> get ( <STR_LIT> ) ) . addRegMask ( RI . getNoPreservedMask ( ) ) ; } unsigned IReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; addFrameReference ( BuildMI ( DispatchBB , DL , TII -> get ( <STR_LIT> ) , IReg ) , FI , <NUM_LIT> ) ; BuildMI ( DispatchBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IReg ) . addImm ( LPadList . size ( ) ) ; BuildMI ( DispatchBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( TrapBB ) ; unsigned JReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( DispContBB , DL , TII -> get ( <STR_LIT> ) , JReg ) . addReg ( IReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( DispContBB , DL , TII -> get ( Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( <NUM_LIT> ) . addImm ( Subtarget . is64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ) . addReg ( JReg ) . addJumpTableIndex ( MJTI ) . addReg ( <NUM_LIT> ) ; SmallPtrSet < MachineBasicBlock * , <NUM_LIT> > SeenMBBs ; for ( auto & LP : LPadList ) if ( SeenMBBs . insert ( LP ) . second ) DispContBB -> addSuccessor ( LP ) ; SmallVector < MachineBasicBlock * , <NUM_LIT> > MBBLPads ; const MCPhysReg * SavedRegs = Subtarget . getRegisterInfo ( ) -> getCalleeSavedRegs ( MF ) ; for ( MachineBasicBlock * MBB : InvokeBBs ) {

SmallVector < MachineBasicBlock * , <NUM_LIT> > Successors ( MBB -> succ_rbegin ( ) , MBB -> succ_rend ( ) ) ;


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override { llvm_unreachable ( <STR_LIT> ) ; } bool writeNopData ( raw_ostream & OS , uint64_t Count ) const override ; std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override { return create<ISA_LIT>ObjectWriter ( OSABI ) ; } } ; } const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { const static MCFixupKindInfo Infos [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ; } void <ISA_LIT>MCAsmBackend :: applyFixup ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target , MutableArrayRef < char > Data , uint64_t Value , bool IsResolved , const MCSubtargetInfo * STI ) const {

MCFixupKind Kind = Fixup . getKind ( ) ;


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( FIST . getNode ( ) == <NUM_LIT> ) return Op ; return DAG . getLoad ( Op . getValueType ( ) , Op . getDebugLoc ( ) , FIST , StackSlot , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> unsigned RegIdx = MRI . getEncodingValue ( RegNo ) & ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; unsigned NumRegs ; if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 'v' ; NumRegs = <NUM_LIT> ; } else if ( MRI . getRegClass ( <STR_LIT> ) . contains ( RegNo ) ) { O << 's' ; NumRegs = <NUM_LIT> ; } else { O << getRegisterName ( RegNo ) ;


<s> static bool regJustKilledBefore ( const LiveIntervals & LIs , unsigned reg , const MachineInstr & MI ) { const LiveInterval & LI = LIs . getInterval ( reg ) ; SlotIndex SI = LIs . getInstructionIndex ( MI ) ;


<s> return getTM < GCNTargetMachine > ( ) ;


<s> <ISA_LIT>SplitConst32AndConst64 ( const <ISA_LIT>TargetMachine & TM ) : MachineFunctionPass ( ID ) , QTM ( TM ) {


<s> inline vector signed int vec_vcmpgtfp ( vector float a1 , vector float a2 ) { return ( vector signed int ) __builtin_altivec_vcmpgtfp ( ( vector float ) a1 , ( vector float ) a2 ) ;


<s> const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const int DivFMasWaitStates = <NUM_LIT> ; auto IsHazardDefFn = [ TII ] ( MachineInstr * MI ) { return TII -> isVALU ( * MI ) ; } ; int WaitStatesNeeded = getWaitStatesSinceDef ( <STR_LIT> , IsHazardDefFn ) ;

return DivFMasWaitStates - WaitStatesNeeded ;


<s> HOST_WIDE_INT size = sparc_frame_size ; if ( sparc_n_global_fp_regs > <NUM_LIT> ) emit_save_or_restore_global_fp_regs ( sparc_frame_base_reg , sparc_frame_base_offset - sparc_apparent_frame_size , SORR_RESTORE ) ; if ( size == <NUM_LIT> || for_eh ) ; else if ( sparc_leaf_function_p ) { if ( size <= <NUM_LIT> ) emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size ) ) ) ; else if ( size <= <NUM_LIT> ) { emit_insn ( gen_stack_pointer_inc ( GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_stack_pointer_inc ( GEN_INT ( size - <NUM_LIT> ) ) ) ; } else {

rtx reg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ;


<s> static SDValue convertLocVTToValVT ( SelectionDAG & DAG , SDValue Val , const CCValAssign & VA , const SDLoc & DL ) { switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ;


<s> InVals . push_back ( ThisVal ) ; continue ; } SDValue Val ; if ( VA . needsCustom ( ) ) { SDValue Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; SDValue Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; } switch ( VA . getLocInfo ( ) ) {

default : llvm_unreachable ( <STR_LIT> ) ;


return __builtin_aarch64_reduc_plus_scal_v2df ( __a ) ;


<s> for ( auto & B : MF ) { for ( auto & MI : B ) { if ( ! MI . isBranch ( ) || ! isJumpOutOfRange ( MI , BlockToInstOffset ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << HII -> isExtendable ( MI ) << <STR_LIT> << HII -> isConstExtended ( MI ) << <STR_LIT> << MI ) ; if ( ! HII -> isExtendable ( MI ) && ! HII -> isExtended ( MI ) ) {


<s> std :: string LowerCaseName = Name . lower ( ) ;

for ( unsigned i = <NUM_LIT> ; i < NumMappings ; ++ i ) {


<s> return emitGlobalConstant ( DL , ACPC -> getPromotedGlobalInit ( ) ) ; } MCSymbol * MCSym ; if ( ACPV -> isLSDA ( ) ) { MCSym = getCurExceptionSym ( ) ; } else if ( ACPV -> isBlockAddress ( ) ) { const BlockAddress * BA = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getBlockAddress ( ) ; MCSym = GetBlockAddressSymbol ( BA ) ; } else if ( ACPV -> isGlobalValue ( ) ) { const GlobalValue * GV = cast < <ISA_LIT>ConstantPoolConstant > ( ACPV ) -> getGV ( ) ; unsigned char TF = Subtarget -> isTargetMachO ( ) ? <STR_LIT> : <NUM_LIT> ; MCSym = Get<ISA_LIT>GVSymbol ( GV , TF ) ; } else if ( ACPV -> isMachineBasicBlock ( ) ) { const MachineBasicBlock * MBB = cast < <ISA_LIT>ConstantPoolMBB > ( ACPV ) -> getMBB ( ) ; MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; auto Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL . getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: createAdd ( PCRelExpr , MCConstantExpr :: create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ;


<s> gcc_assert ( GET_CODE ( address ) == MEM ) ; m32c_print_operand ( stream , XEXP ( address , <NUM_LIT> ) , <NUM_LIT> ) ;


<s> if ( INTVAL ( startop ) > <NUM_LIT> && INTVAL ( startop ) < <NUM_LIT> && INTVAL ( sizeop ) > <NUM_LIT> && INTVAL ( sizeop ) + INTVAL ( startop ) < <NUM_LIT> && INTVAL ( shiftop ) > <NUM_LIT> && INTVAL ( sizeop ) + INTVAL ( shiftop ) < <NUM_LIT> && ( <NUM_LIT> - ( INTVAL ( shiftop ) & <NUM_LIT> ) ) >= INTVAL ( sizeop ) ) return <NUM_LIT> ;


<s> void <ISA_LIT>TargetStreamer :: emitPersonality ( const MCSymbol * Personality ) {


<s> size_t getSize ( ) const { return sizeof ( * this ) + alignTo ( namesz , ALIGN ) + alignTo ( descsz , ALIGN ) ;


<s>
LLVM_DEBUG
(
dbgs
(
)
<<
<STR_LIT>
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
<ISA_LIT>ScheduleBlock
*
Block
:
ReadyBlocks
)
dbgs
(
)
<<
Block
->
getID
(
)
<<
' '
;
dbgs
(
)
<<
<STR_LIT>
;
for
(
unsigned
Reg
:
LiveRegs
)
dbgs
(
)
<<
printVRegOrUnit
(
Reg
,
DAG
->
getTRI
(
)
)
<<
' '
;
dbgs
(
)
<<
'\n'
;
dbgs
(
)
<<
<STR_LIT>
<<
VregCurrentUsage
<<
'\n'
;
dbgs
(
)
<<
<STR_LIT>
<<
SregCurrentUsage
<<
'\n'
;
)
;
Cand
.
Block
=
nullptr
;
for
(
std
::
vector
<
<ISA_LIT>ScheduleBlock
*
>
::
iterator
I
=
ReadyBlocks
.
begin
(
)
,
E
=
ReadyBlocks
.
end
(
)
;
I
!=
E
;
++
I
)
{
<ISA_LIT>BlockSchedCandidate
TryCand
;
TryCand
.
Block
=
*
I
;
TryCand
.
IsHighLatency
=
TryCand
.
Block
->
isHighLatencyBlock
(
)
;
TryCand
.
VGPRUsageDiff
=
checkRegUsageImpact
(
TryCand
.
Block
->
getInRegs
(
)
,
TryCand
.
Block
->
getOutRegs
(
)
)
[
DAG
->
getVGPRSetID
(
)
]
;
TryCand
.
NumSuccessors
=
TryCand
.
Block
->
getSuccs
(
)
.
size
(
)
;
TryCand
.
NumHighLatencySuccessors
=
TryCand
.
Block
->
getNumHighLatencySuccessors
(
)
;
TryCand
.
LastPosHighLatParentScheduled
=
(
unsigned
int
)
std
::
max
<
int
>
(
<NUM_LIT>
,
LastPosHighLatencyParentScheduled
[
TryCand
.
Block
->
getID
(
)
]
LastPosWaitedHighLatency
)
;
TryCand
.
Height
=
TryCand
.
Block
->
Height
;
if
(
VregCurrentUsage
>
<NUM_LIT>
||
Variant
!=
<STR_LIT>
)
{
if
(
!
tryCandidateRegUsage
(
Cand
,
TryCand
)
&&
Variant
!=
<STR_LIT>
)
tryCandidateLatency
(
Cand
,
TryCand
)
;
}
else
{
if
(
!
tryCandidateLatency
(
Cand
,
TryCand
)
)
tryCandidateRegUsage
(
Cand
,
TryCand
)
;
}


<s> CallingConv :: ID CallerCC = CallerF -> getCallingConv ( ) ; bool CCMatch = CallerCC == CalleeCC ; if ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) { return false ; } if ( ! CCMatch ) { bool R = ( CallerCC == CallingConv :: C || CallerCC == CallingConv :: Fast ) ; bool E = ( CalleeCC == CallingConv :: C || CalleeCC == CallingConv :: Fast ) ; if ( ! R || ! E ) return false ; } if ( isVarArg ) return false ; if ( isCalleeStructRet || isCallerStructRet ) return false ; return true ;


<s> virtual const DataLayout * getDataLayout ( ) const { return & DL ;


<s> MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( LO10 ( Offset ) ) ; return ; } BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( HIX22 ( Offset ) ) ; BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( LOX10 ( Offset ) ) ;

BuildMI ( * MI . getParent ( ) , II , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( FramePtr ) ;


<s> emit_library_call ( byt_memcpy_libfunc , LCT_NORMAL , VOIDmode , <NUM_LIT> , dst_reg , Pmode , src_reg , Pmode , convert_to_mode ( TYPE_MODE ( sizetype ) , bytes_rtx , TYPE_UNSIGNED ( sizetype ) ) , TYPE_MODE ( sizetype ) ) ;


<s> Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } if ( cmode == <NUM_LIT> ) { if ( op == <NUM_LIT> ) { Inst . setOpcode ( <STR_LIT> ) ; } else { Inst . setOpcode ( <STR_LIT> ) ; } } } return DecodeVMOVModImmInstruction ( Inst , Insn , Address , Decoder ) ; } if ( ! ( imm & <NUM_LIT> ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Vm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - imm ) ) ;


<s> static SDValue lowerShuffleWithUNPCK256 ( const SDLoc & DL , MVT VT , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , SelectionDAG & DAG ) { SmallVector < int , <NUM_LIT> > Unpckl , Unpckh ; createSplat2ShuffleMask ( VT , Unpckl , true ) ; createSplat2ShuffleMask ( VT , Unpckh , false ) ; unsigned UnpackOpcode ;

if ( isShuffleEquivalent ( Mask , Unpckl , V1 , V2 ) ) UnpackOpcode = <STR_LIT> ;


<s> return APIntToHexString ( CI -> getValue ( ) ) ; } else { unsigned NumElements ; if ( isa < VectorType > ( Ty ) ) NumElements = Ty -> getVectorNumElements ( ) ; else NumElements = Ty -> getArrayNumElements ( ) ; std :: string HexString ; for ( int I = NumElements - <NUM_LIT> , E = - <NUM_LIT> ; I != E ; -- I ) HexString += scalarConstantToHexString ( C -> getAggregateElement ( I ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) { return new <ISA_LIT>DAGToDAGISel ( TM ) ;


<s> bool case2 = JumpAroundTarget -> isSuccessor ( UncondTarget ) && JumpAroundTarget -> size ( ) >= <NUM_LIT> && IsUnconditionalJump ( JumpAroundTarget -> back ( ) . getOpcode ( ) ) && JumpAroundTarget -> pred_size ( ) == <NUM_LIT> && JumpAroundTarget -> succ_size ( ) == <NUM_LIT> ; if ( case1 || case2 ) { InvertAndChangeJumpTarget ( MI , UncondTarget ) ; MBB -> replaceSuccessor ( JumpAroundTarget , UncondTarget ) ; LayoutSucc -> erase ( LayoutSucc -> begin ( ) ) ; LayoutSucc -> replaceSuccessor ( UncondTarget , JumpAroundTarget ) ; if ( case2 && ! case1 ) { JumpAroundTarget -> moveAfter ( LayoutSucc ) ; if ( ! UncondTarget -> canFallThrough ( ) ) { UncondTarget -> moveAfter ( JumpAroundTarget ) ; } } std :: vector < MachineBasicBlock :: RegisterMaskPair > OrigLiveIn ( LayoutSucc -> livein_begin ( ) , LayoutSucc -> livein_end ( ) ) ; std :: vector < MachineBasicBlock :: RegisterMaskPair > NewLiveIn ( JumpAroundTarget -> livein_begin ( ) , JumpAroundTarget -> livein_end ( ) ) ;

for ( const auto & OrigLI : OrigLiveIn ) LayoutSucc -> removeLiveIn ( OrigLI . PhysReg ) ;


<s> auto & DL = F . getParent ( ) -> getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo * TRI = STI . getRegisterInfo ( ) ; SmallVector < ArgInfo , <NUM_LIT> > OutArgs ; for ( auto & OrigArg : Info . OrigArgs ) splitToValueTypes ( OrigArg , OutArgs , DL , Info . CallConv ) ; SmallVector < ArgInfo , <NUM_LIT> > InArgs ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) splitToValueTypes ( Info . OrigRet , InArgs , DL , Info . CallConv ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; auto CallSeqStart = MIRBuilder . buildInstr ( AdjStackDown ) ; unsigned Opc = TLI . getTargetMachine ( ) . isPositionIndependent ( ) ? <STR_LIT> : Info . Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) . add ( Info . Callee ) . addRegMask ( TRI -> getCallPreservedMask ( MF , Info . CallConv ) ) ; CCAssignFn * AssignFn = TLI . getCCAssignFn ( Info . CallConv , false , Info . IsVarArg ) ; OutgoingValueAssigner Assigner ( AssignFn ) ; <ISA_LIT>OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , OutArgs , MIRBuilder , Info . CallConv , Info . IsVarArg ) ) return false ; if ( Info . Callee . isReg ( ) ) constrainOperandRegClass ( MF , * TRI , MRI , * STI . getInstrInfo ( ) , * STI . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Info . Callee , <NUM_LIT> ) ; MIRBuilder . insertInstr ( MIB ) ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { CCAssignFn * RetAssignFn = TLI . getCCAssignFn ( Info . CallConv , true , Info . IsVarArg ) ; OutgoingValueAssigner Assigner ( RetAssignFn , RetAssignFn ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB ) ; if ( ! determineAndHandleAssignments ( Handler , Assigner , InArgs , MIRBuilder , Info . CallConv , Info . IsVarArg ) ) return false ; } CallSeqStart . addImm ( Assigner . StackOffset ) . addImm ( <NUM_LIT> ) ; unsigned AdjStackUp = TII . getCallFrameDestroyOpcode ( ) ; MIRBuilder . buildInstr ( AdjStackUp ) . addImm ( Assigner . StackOffset ) . addImm ( <NUM_LIT> ) ;


<s> rs6000_isa_flags &= ~ OPTION_MASK_RELOCATABLE ; error ( INVALID_64BIT , <STR_LIT> ) ; } if ( rs6000_isa_flags & OPTION_MASK_EABI ) { rs6000_isa_flags &= ~ OPTION_MASK_EABI ; error ( INVALID_64BIT , <STR_LIT> ) ; } if ( TARGET_PROTOTYPE ) { target_prototype = <NUM_LIT> ; error ( INVALID_64BIT , <STR_LIT> ) ; } if ( ( rs6000_isa_flags & OPTION_MASK_POWERPC64 ) == <NUM_LIT> ) { rs6000_isa_flags |= OPTION_MASK_POWERPC64 ; error ( <STR_LIT> ) ; } if ( ! OPTION_SET_P ( rs6000_current_cmodel ) ) SET_CMODEL ( CMODEL_MEDIUM ) ; if ( ( rs6000_isa_flags_explicit & OPTION_MASK_MINIMAL_TOC ) != <NUM_LIT> ) { if ( OPTION_SET_P ( rs6000_current_cmodel ) && rs6000_current_cmodel != CMODEL_SMALL ) error ( <STR_LIT> ) ; if ( TARGET_MINIMAL_TOC ) SET_CMODEL ( CMODEL_SMALL ) ; else if ( TARGET_PCREL || ( PCREL_SUPPORTED_BY_OS && ( rs6000_isa_flags_explicit & OPTION_MASK_PCREL ) == <NUM_LIT> ) ) ; else SET_CMODEL ( CMODEL_SMALL ) ; } if ( rs6000_current_cmodel != CMODEL_SMALL ) { if ( ! OPTION_SET_P ( TARGET_NO_FP_IN_TOC ) ) TARGET_NO_FP_IN_TOC = rs6000_current_cmodel == CMODEL_MEDIUM ; if ( ! OPTION_SET_P ( TARGET_NO_SUM_IN_TOC ) ) TARGET_NO_SUM_IN_TOC = <NUM_LIT> ; } if ( TARGET_PLTSEQ && DEFAULT_ABI != ABI_ELFv2 ) { if ( OPTION_SET_P ( rs6000_pltseq ) ) warning ( <NUM_LIT> , <STR_LIT> , <STR_LIT> ) ; rs6000_pltseq = false ; } } else if ( TARGET_64BIT ) error ( INVALID_32BIT , <STR_LIT> ) ; else { if ( TARGET_PROFILE_KERNEL ) {


<s> unsigned Factor = VT . getSizeInBits ( ) / vectorWidth ; EVT ResultVT = EVT :: getVectorVT ( * DAG . getContext ( ) , ElVT , VT . getVectorNumElements ( ) / Factor ) ; if ( Vec . isUndef ( ) ) return DAG . getUNDEF ( ResultVT ) ; unsigned ElemsPerChunk = vectorWidth / ElVT . getSizeInBits ( ) ; assert ( isPowerOf2_32 ( ElemsPerChunk ) && <STR_LIT> ) ; IdxVal &= ~ ( ElemsPerChunk - <NUM_LIT> ) ;

if ( Vec . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , ResultVT , makeArrayRef ( Vec -> op_begin ( ) + IdxVal , ElemsPerChunk ) ) ;


<s> AU . addRequired < LoopInfoWrapperPass > ( ) ; AU . addPreserved < LoopInfoWrapperPass > ( ) ; AU . addRequired < ScalarEvolution > ( ) ;

AU . addRequired < TargetTransformInfoWrapperPass > ( ) ;


<s> machine_mode move_mode ; int piece_size , i ; piece_size = <NUM_LIT> << floor_log2 ( size_to_move ) ; while ( ! int_mode_for_size ( piece_size * BITS_PER_UNIT , <NUM_LIT> ) . exists ( & move_mode ) || ( code = optab_handler ( mov_optab , move_mode ) ) == CODE_FOR_nothing ) { gcc_assert ( piece_size > <NUM_LIT> ) ; piece_size >>= <NUM_LIT> ; } if ( GET_MODE_SIZE ( move_mode ) > GET_MODE_SIZE ( word_mode ) ) { int nunits = GET_MODE_SIZE ( move_mode ) / GET_MODE_SIZE ( word_mode ) ; if ( ! mode_for_vector ( word_mode , nunits ) . exists ( & move_mode ) || ( code = optab_handler ( mov_optab , move_mode ) ) == CODE_FOR_nothing ) { move_mode = word_mode ; piece_size = GET_MODE_SIZE ( move_mode ) ; code = optab_handler ( mov_optab , move_mode ) ; } } gcc_assert ( code != CODE_FOR_nothing ) ; dst = adjust_automodify_address_nv ( dst , move_mode , destptr , <NUM_LIT> ) ; src = adjust_automodify_address_nv ( src , move_mode , srcptr , <NUM_LIT> ) ; gcc_assert ( size_to_move % piece_size == <NUM_LIT> ) ;

for ( i = <NUM_LIT> ; i < size_to_move ; i += piece_size ) {


<s> bool <ISA_LIT>TTIImpl :: canMacroFuseCmp ( ) {

return ST -> hasMacroFusion ( ) || ST -> hasBranchFusion ( ) ;


<s> if ( STI -> getFeatureBits ( ) . test ( FeatureLocalMemorySize32768 ) ) return <NUM_LIT> ; if ( STI -> getFeatureBits ( ) . test ( FeatureLocalMemorySize65536 ) ) return <NUM_LIT> ;


<s> int Offset = RemainingAdj - OffsetFromTop ; int Opcode = isImmU6 ( Offset ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opcode ) , SpillList [ i ] . Reg ) . addImm ( Offset ) . addMemOperand ( getFrameIndexMMO ( MBB , SpillList [ i ] . FI , MachineMemOperand :: MOLoad ) ) ;


<s> CallReturnHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , MachineInstrBuilder & MIB ) : <ISA_LIT>IncomingValueHandler ( MIRBuilder , MRI ) , MIB ( MIB ) {


<s> static bool parseLEBImmediate ( MCInst & MI , uint64_t & Size , ArrayRef < uint8_t > Bytes , bool Signed ) {


<s> const GlobalValue * GV = N -> getGlobal ( ) ; const GlobalObject * GO = GV -> getBaseObject ( ) ; if ( ! isPositionIndependent ( ) ) { if ( GO && TLOF -> IsGlobalInSmallSection ( GO , getTargetMachine ( ) ) ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> ) ; SDValue GPRelNode = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> ) , GA ) ; SDValue GPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , GPReg , GPRelNode ) ;


<s> const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MI -> isCall ( ) && MO . isRegMask ( ) && ! clobbersAllYmmRegs ( MO ) ) return true ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isDebug ( ) ) continue ; if ( isYmmReg ( MO . getReg ( ) ) ) return true ; }


<s> Inst . addOperand ( MCOperand :: createImm ( getVectorIndex ( ) ) ) ;


<s> unsigned Lane1 = Ins1 . getConstantOperandVal ( <NUM_LIT> ) ; unsigned Lane2 = Ins2 . getConstantOperandVal ( <NUM_LIT> ) ; if ( Lane2 % <NUM_LIT> != <NUM_LIT> || Lane1 != Lane2 + <NUM_LIT> ) return false ; SDValue Val1 = Ins1 . getOperand ( <NUM_LIT> ) ; SDValue Val2 = Ins2 . getOperand ( <NUM_LIT> ) ; if ( Val1 . getOpcode ( ) == <STR_LIT> || Val2 . getOpcode ( ) == <STR_LIT> ) return false ; if ( ( Val1 . getOpcode ( ) == <STR_LIT> || Val1 . getOpcode ( ) == <STR_LIT> ) && ( Val2 . getOpcode ( ) == <STR_LIT> || Val2 . getOpcode ( ) == <STR_LIT> ) && isa < ConstantSDNode > ( Val1 . getOperand ( <NUM_LIT> ) ) && isa < ConstantSDNode > ( Val2 . getOperand ( <NUM_LIT> ) ) && ( Val1 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> || Val1 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) && ( Val2 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> || Val2 . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) ) { unsigned ExtractLane1 = Val1 . getConstantOperandVal ( <NUM_LIT> ) ; unsigned ExtractLane2 = Val2 . getConstantOperandVal ( <NUM_LIT> ) ; if ( Val1 . getOperand ( <NUM_LIT> ) == Val2 . getOperand ( <NUM_LIT> ) && ExtractLane2 % <NUM_LIT> == <NUM_LIT> && ExtractLane1 == ExtractLane2 + <NUM_LIT> ) { SDValue NewExt = CurDAG -> getTargetExtractSubreg ( <STR_LIT> + ExtractLane2 / <NUM_LIT> , dl , <STR_LIT> , Val1 . getOperand ( <NUM_LIT> ) ) ; SDValue NewIns = CurDAG -> getTargetInsertSubreg ( <STR_LIT> + Lane2 / <NUM_LIT> , dl , VT , Ins2 . getOperand ( <NUM_LIT> ) , NewExt ) ; ReplaceUses ( Ins1 , NewIns ) ; return true ; } if ( VT == <STR_LIT> ) { SDValue Inp1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> + ExtractLane1 / <NUM_LIT> , dl , <STR_LIT> , Val1 . getOperand ( <NUM_LIT> ) ) ; SDValue Inp2 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> + ExtractLane2 / <NUM_LIT> , dl , <STR_LIT> , Val2 . getOperand ( <NUM_LIT> ) ) ; if ( ExtractLane1 % <NUM_LIT> != <NUM_LIT> ) Inp1 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Inp1 ) , <NUM_LIT> ) ; if ( ExtractLane2 % <NUM_LIT> != <NUM_LIT> ) Inp2 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Inp2 ) , <NUM_LIT> ) ; SDNode * VINS = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Inp2 , Inp1 ) ; SDValue NewIns = CurDAG -> getTargetInsertSubreg ( <STR_LIT> + Lane2 / <NUM_LIT> , dl , <STR_LIT> , Ins2 . getOperand ( <NUM_LIT> ) , SDValue ( VINS , <NUM_LIT> ) ) ;


<s> return std :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI , IsILP32 ) ;


<s> unsigned getLibCallStackSize ( ) const { return LibCallStackSize ;


<s> if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( EFLAGS , DAG ) ) return Flags ; if ( SDValue R = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) return R ; if ( SDValue R = combinePTESTCC ( EFLAGS , CC , DAG , Subtarget ) ) return R ; return combineSetCCAtomicArith ( EFLAGS , CC , DAG , Subtarget ) ;


<s> if ( SU -> NodeNum < DAGSize && ! -- TopDownSU2Index [ SU -> NodeNum ] ) WorkList . push_back ( SU ) ; } } BottomUpIndex2SU = std :: vector < int > ( TopDownIndex2SU . rbegin ( ) , TopDownIndex2SU . rend ( ) ) ; for ( unsigned i = <NUM_LIT> , e = DAGSize ; i != e ; ++ i ) { SUnit * SU = & SUnits [ i ] ; for ( SDep & Pred : SU -> Preds ) { if ( Pred . getSUnit ( ) -> NodeNum >= DAGSize ) continue ; assert ( TopDownSU2Index [ SU -> NodeNum ] > TopDownSU2Index [ Pred . getSUnit ( ) -> NodeNum ] && <STR_LIT> ) ; } } for ( unsigned i = <NUM_LIT> , e = DAGSize ; i != e ; ++ i ) { SUnit * SU = & SUnits [ i ] ; for ( SDep & Succ : SU -> Succs ) { if ( Succ . getSUnit ( ) -> NodeNum >= DAGSize ) continue ;

assert ( TopDownSU2Index [ SU -> NodeNum ] < TopDownSU2Index [ Succ . getSUnit ( ) -> NodeNum ] && <STR_LIT> ) ;


<s> return AS == <ISA_LIT>AS :: GLOBAL_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS || AS == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ;