<s> Register EhStackReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register EhHandlerReg = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( EhStackReg ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( EhHandlerReg ) ; MBB . erase ( MBBI ) ; return ; } bool restoreLR = XFI -> hasLRSpillSlot ( ) ; bool UseRETSP = restoreLR && RemainingAdj && ( MFI . getObjectOffset ( XFI -> getLRSpillSlot ( ) ) == <NUM_LIT> ) ; if ( UseRETSP ) restoreLR = false ; bool FP = hasFP ( MF ) ; if ( FP ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( FramePtr ) ; SmallVector < StackSlotInfo , <NUM_LIT> > SpillList ; GetSpillList ( SpillList , MFI , XFI , restoreLR , FP ) ; RestoreSpillList ( MBB , MBBI , dl , TII , RemainingAdj , SpillList ) ; if ( RemainingAdj ) { IfNeededLDAWSP ( MBB , MBBI , dl , TII , <NUM_LIT> , RemainingAdj ) ; if ( UseRETSP ) { assert ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; int Opcode = isImmU6 ( RemainingAdj ) ? <STR_LIT> : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opcode ) ) . addImm ( RemainingAdj ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i < e ; ++ i ) MIB -> addOperand ( MBBI -> getOperand ( i ) ) ; MBB . erase ( MBBI ) ; } else { int Opcode = isImmU6 ( RemainingAdj ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII . get ( Opcode ) , <STR_LIT> ) . addImm ( RemainingAdj ) ;


<s> break ; case <STR_LIT> : args_float [ ArgNo ] = AddLiveIn ( MF , args_float [ ArgNo ] , & <STR_LIT> ) ; ArgVal = DAG . getCopyFromReg ( Root , dl , args_float [ ArgNo ] , ObjectVT ) ; break ; case <STR_LIT> : args_int [ ArgNo ] = AddLiveIn ( MF , args_int [ ArgNo ] , & <STR_LIT> ) ; ArgVal = DAG . getCopyFromReg ( Root , dl , args_int [ ArgNo ] , <STR_LIT> ) ; break ; } } else { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , <NUM_LIT> * ( ArgNo - <NUM_LIT> ) ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Root , FIN , NULL , <NUM_LIT> ) ; } ArgValues . push_back ( ArgVal ) ; } bool isVarArg = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) != <NUM_LIT> ; if ( isVarArg ) { VarArgsOffset = ( Op . getNode ( ) -> getNumValues ( ) - <NUM_LIT> ) * <NUM_LIT> ; std :: vector < SDValue > LS ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( TargetRegisterInfo :: isPhysicalRegister ( args_int [ i ] ) ) args_int [ i ] = AddLiveIn ( MF , args_int [ i ] , & <STR_LIT> ) ; SDValue argt = DAG . getCopyFromReg ( Root , dl , args_int [ i ] , <STR_LIT> ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , - <NUM_LIT> * ( <NUM_LIT> - i ) ) ; if ( i == <NUM_LIT> ) VarArgsBase = FI ; SDValue SDFI = DAG . getFrameIndex ( FI , <STR_LIT> ) ; LS . push_back ( DAG . getStore ( Root , dl , argt , SDFI , NULL , <NUM_LIT> ) ) ;

if ( TargetRegisterInfo :: isPhysicalRegister ( args_float [ i ] ) ) args_float [ i ] = AddLiveIn ( MF , args_float [ i ] , & <STR_LIT> ) ;


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo MFI = MF . getFrameInfo ( ) ; MachineOperand & FIOp = MI . getOperand ( FIOperandNum ) ; unsigned FI = FIOp . getIndex ( ) ; unsigned ImmOpIdx = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default :


<s> const GlobalVariable * getPromotedGlobal ( ) const {

return dyn_cast_or_null < GlobalVariable > ( GVar ) ;


<s> return <STR_LIT> . contains ( Reg ) ;


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ;


<s> void setVarArgsFrameIndex ( int Idx ) { VarArgsFrameIndex = Idx ;


<s> if ( isFP64 ( ) ) return MatchOperand_NoMatch ;

return parseRegs ( Operands , ( int ) <STR_LIT> ) ;


<s> void <ISA_LIT>IntelAsmPrinter :: printPICLabel ( const MachineInstr * MI , unsigned Op ) { O << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> ; O << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> ;


<s>
void
FPOStateMachine
::
emitFrameDataRecord
(
MCStreamer
&
OS
,
MCSymbol
*
Label
)
{
unsigned
CurFlags
=
Flags
;
if
(
Label
==
FPO
->
Begin
)
CurFlags
|=
FrameData
::
IsFunctionStart
;
FrameFunc
.
clear
(
)
;
raw_svector_ostream
FuncOS
(
FrameFunc
)
;
const
MCRegisterInfo
*
MRI
=
OS
.
getContext
(
)
.
getRegisterInfo
(
)
;
assert
(
(
StackAlign
==
<NUM_LIT>
||
FrameReg
!=
<NUM_LIT>
)
&&
<STR_LIT>
)
;
StringRef
CFAVar
=
StackAlign
==
<NUM_LIT>
<STR_LIT>
:
<STR_LIT>
;
if
(
FrameReg
)
{
FuncOS
<<
CFAVar
<<
' '
<<
printFPOReg
(
MRI
,
FrameReg
)
<<
' '
<<
FrameRegOff
<<
<STR_LIT>
;
if
(
StackAlign
)
{
FuncOS
<<
<STR_LIT>
<<
CFAVar
<<
' '
<<
StackOffsetBeforeAlign
<<
<STR_LIT>
<<
StackAlign
<<
<STR_LIT>
;
}
}
else
{
FuncOS
<<
CFAVar
<<
<STR_LIT>
;
}
FuncOS
<<
<STR_LIT>
<<
CFAVar
<<
<STR_LIT>
;
FuncOS
<<
<STR_LIT>
<<
CFAVar
<<
<STR_LIT>
;
for
(
RegSaveOffset
RO
:
RegSaveOffsets
)
FuncOS
<<
printFPOReg
(
MRI
,
RO
.
Reg
)
<<
' '
<<
CFAVar
<<
' '
<<
RO
.
Offset
<<
<STR_LIT>
;
CodeViewContext
&
CVCtx
=
OS
.
getContext
(
)
.
getCVContext
(
)
;
unsigned
FrameFuncStrTabOff
=
CVCtx
.
addToStringTable
(
FuncOS
.
str
(
)
)
.
second
;
unsigned
MaxStackSize
=
<NUM_LIT>
;
OS
.
emitAbsoluteSymbolDiff
(
Label
,
FPO
->
Begin
,
<NUM_LIT>
)
;
OS
.
emitAbsoluteSymbolDiff
(
FPO
->
End
,
Label
,
<NUM_LIT>
)
;
OS
.
emitInt32
(
LocalSize
)
;
OS
.
emitInt32
(
FPO
->
ParamsSize
)
;


<s> if ( SUJ -> isSucc ( SUI ) ) { for ( unsigned i = <NUM_LIT> , e = SUJ -> Succs . size ( ) ; i < e ; ++ i ) { const SDep & Dep = SUJ -> Succs [ i ] ; if ( Dep . getSUnit ( ) != SUI ) continue ; if ( Dep . getKind ( ) == SDep :: Anti ) continue ; if ( Dep . getKind ( ) == SDep :: Output ) if ( MII -> getOperand ( <NUM_LIT> ) . getReg ( ) != MIJ -> getOperand ( <NUM_LIT> ) . getReg ( ) ) continue ; return false ; } } bool ARDef = TII -> definesAddressRegister ( * MII ) || TII -> definesAddressRegister ( * MIJ ) ; bool ARUse = TII -> usesAddressRegister ( * MII ) || TII -> usesAddressRegister ( * MIJ ) ; return ! ARDef || ! ARUse ;


<s> case Type :: HalfTyID : return <STR_LIT> ; case Type :: FloatTyID : return <STR_LIT> ; case Type :: DoubleTyID : return <STR_LIT> ; case Type :: PointerTyID :

if ( static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . is64Bit ( ) ) if ( useB4PTR ) return <STR_LIT> ;


<s> BlockPosition ( unsigned InitialAlignment ) : Address ( <NUM_LIT> ) , KnownBits ( InitialAlignment ) {


<s> const <ISA_LIT>Subtarget * <ISA_LIT>TargetLowering :: getSubtarget ( ) const { return Subtarget ;


<s> unsigned NumZeros = getNumOfConsecutiveZeros ( SVOp , NumElems , true , DAG ) ; unsigned OpSrc ; if ( ! NumZeros ) return false ; if ( ! isShuffleMaskConsecutive ( SVOp , NumZeros , NumElems - <NUM_LIT> , <NUM_LIT> , NumElems , OpSrc ) ) return false ; isLeft = true ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; int64_t FPOffset = Offset - <NUM_LIT> ; if ( ! AFI -> isThumbFunction ( ) || ! AFI -> isThumb1OnlyFunction ( ) ) FPOffset -= <NUM_LIT> ; Offset = - Offset ; Offset += MFI -> getLocalFrameSize ( ) ; Offset += <NUM_LIT> ; unsigned StackAlign = TFI -> getStackAlignment ( ) ; if ( TFI -> hasFP ( MF ) && ! ( ( MFI -> getLocalFrameMaxAlign ( ) > StackAlign ) && canRealignStack ( MF ) ) ) {

if ( isFrameOffsetLegal ( MI , FPOffset ) ) return false ;


<s> static void count_unit_reqs ( unit_req_table reqs , rtx_insn * head , rtx_insn * tail ) { rtx_insn * insn ; memset ( reqs , <NUM_LIT> , sizeof ( unit_req_table ) ) ; for ( insn = head ; insn != NEXT_INSN ( tail ) ; insn = NEXT_INSN ( insn ) ) { int side1 , side2 , req1 , req2 ; switch ( get_unit_reqs ( insn , & req1 , & side1 , & req2 , & side2 ) ) { case <NUM_LIT> : reqs [ side2 ] [ req2 ] ++ ;


<s> ++ FilledSlots ; Changed = true ; MachineBasicBlock :: iterator D ; if ( EnableDelaySlotFiller && findDelayInstr ( MBB , I , D ) ) { MBB . splice ( llvm :: next ( I ) , & MBB , D ) ; ++ UsefulSlots ; } else BuildMI ( MBB , llvm :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ;


<s> void <ISA_LIT>InstPrinter :: printPredicateOperand ( MCInst const * MI , unsigned OpNo , raw_ostream & O ) const {


<s> SDLoc DL ( N ) ; RegisterSDNode * RN = dyn_cast < RegisterSDNode > ( Base ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Base = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else if ( Base . getValueType ( ) == <STR_LIT> && ! dyn_cast < FrameIndexSDNode > ( Base ) ) { Base = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Base , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; } RN = dyn_cast < RegisterSDNode > ( Index ) ; if ( RN && RN -> getReg ( ) == <NUM_LIT> ) Index = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; else { assert ( Index . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ;

Index = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: SUBREG_TO_REG , DL , <STR_LIT> , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , Index , CurDAG -> getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) ) , <NUM_LIT> ) ;


<s> return __builtin_neon_vrndihf ( __a ) ;


<s> const Function * <ISA_LIT>SPMark :: getCallTarget ( const MachineInstr * MI ) const { const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; const Function * Target = NULL ; if ( MO . isGlobal ( ) ) {

Target = dyn_cast < Function > ( MO . getGlobal ( ) ) ;


<s> bool HasFP = hasFP ( MF ) ; if ( ( STI . isTargetDarwin ( ) && NumBytes ) || HasFP ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( HasFP || AFI -> getGPRCalleeSavedArea2Size ( ) || AFI -> getDPRCalleeSavedAreaSize ( ) || AFI -> getDPRCalleeSavedAreaOffset ( ) ) { if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ; } } } else if ( NumBytes ) emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , NumBytes ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , STI ) ; emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getDPRCalleeSavedAreaSize ( ) ) ; movePastCSLoadStoreOps ( MBB , MBBI , <STR_LIT> , <STR_LIT> , <NUM_LIT> , STI ) ;

emitSPUpdate ( is<ISA_LIT> , MBB , MBBI , dl , TII , AFI -> getGPRCalleeSavedArea2Size ( ) ) ;


<s> SelectionDAG & DAG = CLI . DAG ; DebugLoc & dl = CLI . DL ; SmallVector < <STR_LIT> , <NUM_LIT> > & Outs = CLI . Outs ; SmallVector < SDValue , <NUM_LIT> > & OutVals = CLI . OutVals ; SmallVector < <STR_LIT> , <NUM_LIT> > & Ins = CLI . Ins ;


<s> else if ( Addr . getOpcode ( ) == <STR_LIT> && expandAdjDynAlloc ( AM , true , SDValue ( ) ) ) ; else while ( expandAddress ( AM , true ) || ( AM . Index . getNode ( ) && expandAddress ( AM , false ) ) ) continue ; if ( AM . Form == <STR_LIT> && ! shouldUseLA ( AM . Base . getNode ( ) , AM . Disp , AM . Index . getNode ( ) ) ) return false ; if ( ! isValidDisp ( AM . DR , AM . Disp ) ) return false ;

if ( AM . isDynAlloc ( ) && ! AM . IncludesDynAlloc ) return false ;


<s> } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasLZCNT = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasPRFCHW = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsAMD ) { if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasSSE4A = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasXOP = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( ECX >> <NUM_LIT> ) & <NUM_LIT> ) { HasFMA4 = true ; ToggleFeature ( <STR_LIT> ) ; } } } } if ( MaxLevel >= <NUM_LIT> ) { if ( ! <ISA_LIT>_MC :: GetCpuIDAndInfoEx ( <NUM_LIT> , <NUM_LIT> , & EAX , & EBX , & ECX , & EDX ) ) { if ( IsIntel && ( EBX & <NUM_LIT> ) ) { HasFSGSBase = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( EBX >> <NUM_LIT> ) & <NUM_LIT> ) { HasBMI = true ; ToggleFeature ( <STR_LIT> ) ; } if ( ( EBX >> <NUM_LIT> ) & <NUM_LIT> ) { HasHLE = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( EBX >> <NUM_LIT> ) & <NUM_LIT> ) ) { <ISA_LIT>SSELevel = AVX2 ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( EBX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasBMI2 = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( EBX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasRTM = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( EBX >> <NUM_LIT> ) & <NUM_LIT> ) ) { <ISA_LIT>SSELevel = AVX512F ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( EBX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasRDSEED = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( EBX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasADX = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( EBX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasPFI = true ; ToggleFeature ( <STR_LIT> ) ; } if ( IsIntel && ( ( EBX >> <NUM_LIT> ) & <NUM_LIT> ) ) { HasERI = true ;


<s> static inline bool isOptNone ( const MachineFunction & MF ) {

return MF . getFunction ( ) . hasFnAttribute ( Attribute :: OptimizeNone ) || MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ;


<s> static bool isALUArithLoOpcode ( unsigned Opcode ) {


<s> bool useOddSPReg ( ) const { return ! ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) ;


raw_svector_ostream ( Name ) << DL -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << uid << '_' << uid2 ;


<s> return MachineOperand :: CreateReg ( CCReg , <NUM_LIT> ) ;


<s> MBBI ++ ; while ( MBBI -> getOpcode ( ) == <STR_LIT> ) MBBI ++ ; } if ( AFI -> getGPRCalleeSavedArea2Size ( ) ) MBBI ++ ; if ( AFI -> getGPRCalleeSavedArea1Size ( ) ) MBBI ++ ; } if ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) { MBBI = MBB . getLastNonDebugInstr ( ) ; MachineOperand & JumpTarget = MBBI -> getOperand ( <NUM_LIT> ) ; if ( RetOpcode == <STR_LIT> ) { unsigned TCOpcode = STI . isThumb ( ) ? ( STI . isTargetMachO ( ) ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( TCOpcode ) ) ; if ( JumpTarget . isGlobal ( ) ) MIB . addGlobalAddress ( JumpTarget . getGlobal ( ) , JumpTarget . getOffset ( ) , JumpTarget . getTargetFlags ( ) ) ; else { assert ( JumpTarget . isSymbol ( ) ) ; MIB . addExternalSymbol ( JumpTarget . getSymbolName ( ) , JumpTarget . getTargetFlags ( ) ) ; } if ( STI . isThumb ( ) ) MIB . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; } else if ( RetOpcode == <STR_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ) ) . addReg ( JumpTarget . getReg ( ) , RegState :: Kill ) ; } MachineInstr * NewMI = std :: prev ( MBBI ) ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) NewMI -> addOperand ( MBBI -> getOperand ( i ) ) ;


<s> NumHex = <NUM_LIT> ; APF . convert ( APFloat :: IEEEsingle , APFloat :: rmNearestTiesToEven , & Ignored ) ; break ; case VK_<ISA_LIT>_DOUBLE_PREC_FLOAT : OS << <STR_LIT> ; NumHex = <NUM_LIT> ; APF . convert ( APFloat :: IEEEdouble , APFloat :: rmNearestTiesToEven , & Ignored ) ; break ; } APInt API = APF . bitcastToAPInt ( ) ;

std :: string HexStr ( utohexstr ( API . getZExtValue ( ) ) ) ;


<s> AsmPrinter :: EmitBasicBlockEnd ( MBB ) ; <ISA_LIT>TargetStreamer & TS = getTargetStreamer ( ) ;

if ( MBB . empty ( ) ) TS . emitDirectiveInsn ( ) ;


<s> if ( ! SelectMUBUF ( Addr , Ptr , VAddr , SOffset , Offset , Offen , Idxen , Addr64 ) ) return false ; if ( ! cast < ConstantSDNode > ( Offen ) -> getSExtValue ( ) && ! cast < ConstantSDNode > ( Idxen ) -> getSExtValue ( ) && ! cast < ConstantSDNode > ( Addr64 ) -> getSExtValue ( ) ) { uint64_t Rsrc = TII -> getDefaultRsrcDataFormat ( ) | APInt :: getAllOnes ( <NUM_LIT> ) . getZExtValue ( ) ; SDLoc DL ( Addr ) ; const <ISA_LIT>TargetLowering & Lowering = * static_cast < const <ISA_LIT>TargetLowering * > ( getTargetLowering ( ) ) ; SRsrc = SDValue ( Lowering . buildRSRC ( * CurDAG , DL , Ptr , <NUM_LIT> , Rsrc ) , <NUM_LIT> ) ; return true ; }


<s> regno = reg_renumber [ regno ] ; if ( regno == INVALID_REGNUM ) return false ; } return TEST_HARD_REG_BIT ( reg_class_contents [ rclass ] , regno ) ;


for ( Loop * I : LI ) for ( auto L = df_begin ( I ) , LE = df_end ( I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> SDLoc DL ( N ) ; return DAG . getNode ( <STR_LIT> , DL , ValTy , Shl . getOperand ( <NUM_LIT> ) , DAG . getConstant ( SMPos0 , DL , <STR_LIT> ) , DAG . getConstant ( SMSize0 , DL , <STR_LIT> ) , And0 . getOperand ( <NUM_LIT> ) ) ; } else { if ( ~ CN -> getSExtValue ( ) == ( ( ( ( int64_t ) <NUM_LIT> << SMSize0 ) - <NUM_LIT> ) << SMPos0 ) && ( ( SMSize0 + SMPos0 <= <NUM_LIT> && Subtarget . has<ISA_LIT>64r2 ( ) ) || ( SMSize0 + SMPos0 <= <NUM_LIT> ) ) ) { bool isConstCase = And1 . getOpcode ( ) != <STR_LIT> ; if ( And1 . getOpcode ( ) == <STR_LIT> ) { if ( ! ( CN1 = dyn_cast < ConstantSDNode > ( And1 -> getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; } else { if ( ! ( CN1 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) ) return SDValue ( ) ; } if ( CN -> getSExtValue ( ) & CN1 -> getSExtValue ( ) ) return SDValue ( ) ; SDLoc DL ( N ) ; EVT ValTy = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; SDValue Const1 ; SDValue SrlX ; if ( ! isConstCase ) { Const1 = DAG . getConstant ( SMPos0 , DL , <STR_LIT> ) ;

SrlX = DAG . getNode ( <STR_LIT> , DL , And1 -> getValueType ( <NUM_LIT> ) , And1 , Const1 ) ;


<s> for ( const MCOperandInfo & opInfo : MCID . operands ( ) ) if ( opInfo . isPredicate ( ) ) return true ; return false ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MCAsmLexer & getLexer ( ) const { return Parser . getLexer ( ) ;


<s> bool IsWin64 = Subtarget . isCallingConvWin64 ( MF . getFunction ( ) . getCallingConv ( ) ) ; unsigned FixedObject = getFixedObjectSize ( MF , AFI , IsWin64 , false ) ;

unsigned FPAdjust = isTargetDarwin ( MF ) ? <NUM_LIT> : AFI -> getCalleeSavedStackSize ( MF . getFrameInfo ( ) ) ;


<s> if ( ! arm_macro_fusion_p ( ) ) return false ; if ( current_tune -> fusible_ops & tune_params :: FUSE_AES_AESMC && aarch_crypto_can_dual_issue ( prev , curr ) ) return true ; if ( current_tune -> fusible_ops & tune_params :: FUSE_MOVW_MOVT && arm_sets_movw_movt_fusible_p ( prev_set , curr_set ) ) return true ;


<s> if ( Triple . getArch ( ) == Triple :: x86_64 ) { PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ;


<s> virtual std :: string getLabelEndName ( ) const { return <STR_LIT> ;


<s> for ( unsigned i = <NUM_LIT> , e = array_lengthof ( ReduceTable ) ; i != e ; ++ i ) { unsigned FromOpc = ReduceTable [ i ] . WideOpc ;

if ( ! ReduceOpcodeMap . insert ( std :: make_pair ( FromOpc , i ) ) . second ) assert ( false && <STR_LIT> ) ;


<s> <ISA_LIT>TargetStreamer :: ~ <ISA_LIT>TargetStreamer ( ) {


<s> if ( cast < ConstantInt > ( RHS ) -> getValue ( ) != - <NUM_LIT> ) return false ; TestBit = BW - <NUM_LIT> ; IsCmpNE = false ; } else return false ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool IsBitTest = TestBit != - <NUM_LIT> ; bool Is64Bit = BW == <NUM_LIT> ; if ( TestBit < <NUM_LIT> && TestBit >= <NUM_LIT> ) Is64Bit = false ; unsigned Opc = OpcTable [ IsBitTest ] [ IsCmpNE ] [ Is64Bit ] ; const MCInstrDesc & II = TII . get ( Opc ) ; unsigned SrcReg = getRegForValue ( LHS ) ; if ( ! SrcReg ) return false ; bool SrcIsKill = hasTrivialKill ( LHS ) ; if ( BW == <NUM_LIT> && ! Is64Bit ) SrcReg = fastEmitInst_extractsubreg ( <STR_LIT> , SrcReg , SrcIsKill , <STR_LIT> ) ; SrcReg = constrainOperandRegClass ( II , SrcReg , II . getNumDefs ( ) ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( SrcIsKill ) ) ; if ( IsBitTest ) MIB . addImm ( TestBit ) ; MIB . addMBB ( TBB ) ; uint32_t BranchWeight = <NUM_LIT> ;

if ( FuncInfo . BPI ) BranchWeight = FuncInfo . BPI -> getEdgeWeight ( BI -> getParent ( ) , TBB -> getBasicBlock ( ) ) ;


<s> if ( IsValidLdStrOpc ) * IsValidLdStrOpc = true ; switch ( Opc ) { default : if ( IsValidLdStrOpc ) * IsValidLdStrOpc = false ; return UINT_MAX ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> <ISA_LIT>16HardFloat ( ) : ModulePass ( ID ) {


<s> if ( getLexer ( ) . isNot ( AsmToken :: LParen ) ) return true ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Integer ) ) return true ; SMLoc ValLoc = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseAbsoluteExpression ( CntVal ) ) return true ; <STR_LIT> :: IsaVersion ISA = <STR_LIT> :: getIsaVersion ( getFeatureBits ( ) ) ; bool Failed = true ; bool Sat = CntName . endswith ( <STR_LIT> ) ; if ( CntName == <STR_LIT> || CntName == <STR_LIT> ) { Failed = encodeCnt ( ISA , IntVal , CntVal , Sat , encodeVmcnt , decodeVmcnt ) ; } else if ( CntName == <STR_LIT> || CntName == <STR_LIT> ) {

Failed = encodeCnt ( ISA , IntVal , CntVal , Sat , encodeExpcnt , decodeExpcnt ) ;


<s> unsigned getVariadicGPRSize ( ) const {


<s> return true ; default : return false ; } } if ( VT == <STR_LIT> && Op == <STR_LIT> ) return false ;

return TargetLowering :: isTypeDesirableForOp ( Op , VT ) ;


<s> Advantage -= <NUM_LIT> ; } else { Advantage -= <NUM_LIT> ; if ( CC . ExpectedDist % StackAlign ) Advantage -= <NUM_LIT> ; Advantage += ( CC . ExpectedDist >> Log2SlotSize ) * <NUM_LIT> ; }


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( <STR_LIT> ( N0 . getNode ( ) ) && N0 . hasOneUse ( ) && ! cast < LoadSDNode > ( N0 ) -> isVolatile ( ) ) { LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DAG . getLoad ( VT , SDLoc ( N ) , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , LN0 -> getPointerInfo ( ) , LN0 -> isVolatile ( ) , LN0 -> isNonTemporal ( ) , LN0 -> isInvariant ( ) , LN0 -> getAlignment ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN0 , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , SDLoc ( N ) , VT , Load ) ; }


<s> assert ( Subtarget . hasStdExtZbp ( ) && <STR_LIT> ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc DL ( Op ) ; unsigned Imm = VT . getSizeInBits ( ) - <NUM_LIT> ; if ( Op . getOpcode ( ) == <STR_LIT> ) Imm &= ~ <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( Imm , DL , Subtarget . getXLenVT ( ) ) ) ; } case <STR_LIT> : { SDLoc DL ( Op ) ; EVT VT = Op . getValueType ( ) ; if ( ! VT . isVector ( ) ) return Op ; if ( VT . getVectorElementType ( ) == <STR_LIT> ) return lowerVectorMaskTrunc ( Op , DAG ) ; EVT DstEltVT = VT . getVectorElementType ( ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; EVT SrcEltVT = SrcVT . getVectorElementType ( ) ; assert ( DstEltVT . bitsLT ( SrcEltVT ) && isPowerOf2_64 ( DstEltVT . getSizeInBits ( ) ) && isPowerOf2_64 ( SrcEltVT . getSizeInBits ( ) ) && <STR_LIT> ) ; SDValue Result = Src ; LLVMContext & Context = * DAG . getContext ( ) ; const ElementCount Count = SrcVT . getVectorElementCount ( ) ; do { SrcEltVT = EVT :: getIntegerVT ( Context , SrcEltVT . getSizeInBits ( ) / <NUM_LIT> ) ; EVT ResultVT = EVT :: getVectorVT ( Context , SrcEltVT , Count ) ; Result = DAG . getNode ( <STR_LIT> , DL , ResultVT , Result ) ; } while ( SrcEltVT != DstEltVT ) ; return Result ; } case <STR_LIT> : case <STR_LIT> : return lowerVectorMaskExt ( Op , DAG , <NUM_LIT> ) ;


<s> if ( getGeneration ( ) == <ISA_LIT>Subtarget :: SEA_ISLANDS ) return <NUM_LIT> ; } if ( isXNACKEnabled ( ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> t2 = gen_rtx_EXPR_LIST ( VOIDmode , t2 , const0_rtx ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , t1 , t2 ) ) ; } } if ( orig_mode == BLKmode ) { if ( bytes > <NUM_LIT> && bytes <= <NUM_LIT> ) mode = ( bytes > <NUM_LIT> ? DImode : SImode ) ; if ( mode == BLKmode ) mode = DImode ; }

return gen_reg_or_parallel ( mode , orig_mode , regno ) ;


<s> if ( MO . isReg ( ) ) { if ( Register MOReg = MO . getReg ( ) ) { if ( TRI -> regsOverlap ( MOReg , Reg ) ) { if ( MO . isUse ( ) ) Ref . Use = true ; else if ( MO . isDef ( ) ) Ref . Def = true ; } } } } return Ref ;


<s> FunctionPass * llvm :: create<ISA_LIT>PrepareForLiveIntervals ( ) { return new <ISA_LIT>PrepareForLiveIntervals ( ) ;


<s> NextI = std :: next ( I ) ; unsigned Opc = I -> getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { bool Done = predicate ( * I , ( Opc == <STR_LIT> ) , UpdRegs ) ; if ( ! Done ) { if ( RegisterRef ( I -> getOperand ( <NUM_LIT> ) ) == RegisterRef ( I -> getOperand ( <NUM_LIT> ) ) ) { for ( auto & Op : I -> operands ( ) ) if ( Op . isReg ( ) ) UpdRegs . insert ( Op . getReg ( ) ) ; removeInstr ( * I ) ; } } Changed |= Done ; }


<s> static DecodeStatus DecodeSORegImmOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Rm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned type = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned imm = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; <STR_LIT> Shift = <STR_LIT> ; switch ( type ) { case <NUM_LIT> : Shift = <STR_LIT> ; break ; case <NUM_LIT> :


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ;

MCRegister SP = MRI . getDwarfRegNum ( <STR_LIT> , true ) ;


<s> SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue ConstTrue = CurDAG -> getConstant ( N -> getOpcode ( ) == <STR_LIT> ? - <NUM_LIT> : <NUM_LIT> , dl , VT ) ; SDValue ConstFalse = CurDAG -> getConstant ( <NUM_LIT> , dl , VT ) ; do { SDNode * User = * N -> use_begin ( ) ; if ( User -> getNumOperands ( ) != <NUM_LIT> ) break ; auto TryFold = [ this , N , User , dl ] ( SDValue Val ) { SDValue UserO0 = User -> getOperand ( <NUM_LIT> ) , UserO1 = User -> getOperand ( <NUM_LIT> ) ; SDValue O0 = UserO0 . getNode ( ) == N ? Val : UserO0 ; SDValue O1 = UserO1 . getNode ( ) == N ? Val : UserO1 ; return CurDAG -> FoldConstantArithmetic ( User -> getOpcode ( ) , dl , User -> getValueType ( <NUM_LIT> ) , { O0 , O1 } ) ; } ; SDValue TrueRes = TryFold ( ConstTrue ) ; if ( ! TrueRes || TrueRes . isUndef ( ) ) break ; SDValue FalseRes = TryFold ( ConstFalse ) ; if ( ! FalseRes || FalseRes . isUndef ( ) ) break ; uint64_t True = cast < ConstantSDNode > ( TrueRes ) -> getZExtValue ( ) , False = cast < ConstantSDNode > ( FalseRes ) -> getZExtValue ( ) ; if ( ! isInt < <NUM_LIT> > ( True ) || ! isInt < <NUM_LIT> > ( False ) ) break ; Res = CurDAG -> getSelect ( dl , User -> getValueType ( <NUM_LIT> ) , Cond , TrueRes , FalseRes ) ; N = User ;


<s> return enableNamedBit ( MI , <STR_LIT> :: SC0 ) ;


<s> if ( const uint16_t * R = D . ImplicitDefs ) while ( * R ) expandReg ( * R ++ , Defs ) ; if ( const uint16_t * R = D . ImplicitUses ) while ( * R ) expandReg ( * R ++ , Uses ) ; for ( ConstMIOperands Mo ( MI ) ; Mo . isValid ( ) ; ++ Mo ) { if ( ! Mo -> isReg ( ) || Mo -> isImplicit ( ) ) continue ; unsigned R = Mo -> getReg ( ) ;

BitVector & Set = Mo -> isDef ( ) ? Defs : Uses ;


<s> void llvm :: addUnpredicatedMveVpredNOp ( MachineInstrBuilder & MIB ) { MIB . addImm ( <STR_LIT> ) ;


<s> if ( ! VF . isScalable ( ) ) return VF . getFixedValue ( ) ;

return VF . getKnownMinValue ( ) * ST -> getVScaleForTuning ( ) ;


<s> if ( ! Ty . isVector ( ) ) return Ty ;

return <STR_LIT> ( Ty . getSizeInBits ( ) ) ;


<s> union { vector signed int v ; signed int i [ <NUM_LIT> ] ; } aa , bb ; aa . v = ( vector signed int ) ( a ) ; bb . v = ( vector signed int ) ( b ) ; if ( aa . i [ <NUM_LIT> ] > bb . i [ <NUM_LIT> ] ) { SPU_HALT_ACTION ; } ;


<s> SDValue ib = sign ? DAG . getSExtOrTrunc ( RHS , DL , IntVT ) : DAG . getZExtOrTrunc ( RHS , DL , IntVT ) ; SDValue fa = DAG . getNode ( ToFp , DL , FltVT , ia ) ; SDValue fb = DAG . getNode ( ToFp , DL , FltVT , ib ) ; SDValue fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fa , DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ) ; fq = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fqneg = DAG . getNode ( <STR_LIT> , DL , FltVT , fq ) ; SDValue fr = DAG . getNode ( <STR_LIT> , DL , FltVT , DAG . getNode ( <STR_LIT> , DL , FltVT , fqneg , fb ) , fa ) ; SDValue iq = DAG . getNode ( ToInt , DL , IntVT , fq ) ; fr = DAG . getNode ( <STR_LIT> , DL , FltVT , fr ) ; fb = DAG . getNode ( <STR_LIT> , DL , FltVT , fb ) ; EVT SetCCVT = getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , VT ) ; SDValue cv = DAG . getSetCC ( DL , SetCCVT , fr , fb , <STR_LIT> ) ;

jq = DAG . getNode ( <STR_LIT> , DL , VT , cv , jq , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ;


<s> EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue VAList = DAG . getLoad ( getPointerTy ( ) , dl , Node -> getOperand ( <NUM_LIT> ) , Node -> getOperand ( <NUM_LIT> ) , V , <NUM_LIT> , false , false , <NUM_LIT> ) ;

SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , VAList , DAG . getConstant ( VT . getSizeInBits ( ) , getPointerTy ( ) ) ) ;


<s> void <ISA_LIT>InstPrinter :: printSignedImmOperand ( const MCInst * MI , int OpNo , raw_ostream & O ) { unsigned int Value = MI -> getOperand ( OpNo ) . getImm ( ) ; O << ( int ) Value ;


<s> Loops = getAnalysisIfAvailable < MachineLoopInfo > ( ) ; MBPI = & getAnalysis < MachineBranchProbabilityInfo > ( ) ; Traces = & getAnalysis < MachineTraceMetrics > ( ) ; MinInstr = nullptr ; MinSize = MF . getFunction ( ) . hasMinSize ( ) ; bool Changed = false ;

CmpConv . runOnMachineFunction ( MF , MBPI ) ;


<s> virtual ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> BuildMI ( LoopMBB , DL , TII -> get ( getLRForRMW ( Ordering , Width ) ) , DestReg ) . addReg ( AddrReg ) ; switch ( BinOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case AtomicRMWInst :: Nand : BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( DestReg ) . addReg ( IncrReg ) ;

BuildMI ( LoopMBB , DL , TII -> get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( - <NUM_LIT> ) ;


<s> <ISA_LIT>MCAsmInfoGNUCOFF :: <ISA_LIT>MCAsmInfoGNUCOFF ( ) { CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> return is64Bit ( ) && ! isTargetNaCl ( ) ;


<s> if ( ( val > - <NUM_LIT> ) && ( val < <NUM_LIT> ) ) fprintf ( file , <STR_LIT> , val ) ; else if ( val < <NUM_LIT> ) fprintf ( file , <STR_LIT> , - val ) ; else fprintf ( file , <STR_LIT> , val ) ;


<s> const uint64_t F = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . TSFlags ; return ( ( F >> <STR_LIT> ) & <STR_LIT> ) ;


<s> Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ; Parser . addAliasForDirective ( <STR_LIT> , <STR_LIT> ) ;

setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> extern __inline int __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_cvtsd_si32 ( __m128d __A ) { __v2df rounded = vec_rint ( ( __v2df ) __A ) ; int result = ( ( __v2df ) rounded ) [ <NUM_LIT> ] ; return result ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {


<s> AddDefaultPred ( BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , PRTmp ) ) . addReg ( guard ) . addImm ( <NUM_LIT> ) . addOperand ( Cond [ <NUM_LIT> ] ) . addOperand ( Cond [ <NUM_LIT> ] ) ; unsigned or_opcode = ( isUInt < <NUM_LIT> > ( or_bitmask ) ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , MI , DL , TII -> get ( or_opcode ) , tmpReg ) . addReg ( PRTmp ) . addImm ( <NUM_LIT> ) . addReg ( tmpReg ) . addImm ( or_bitmask ) ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( createThumb2SizeReductionPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) addPass ( & UnpackMachineBundlesID ) ; addPass ( create<ISA_LIT>OptimizeBarriersPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . useConstIslands ( ) ) addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isTargetNaCl ( ) ) {

addPass ( create<ISA_LIT>NaClRewritePass ( ) ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> x ^= x >> <NUM_LIT> ; x ^= x >> <NUM_LIT> ; x &= <NUM_LIT> ;


<s> <ISA_LIT>Cloner ( ) : ModulePass ( ID ) {


<s> bool MachineConstEvaluator :: evaluateORrr ( const RegisterSubReg & R1 , const RegisterSubReg & R2 , const CellMap & Inputs , LatticeCell & Result ) { assert ( Inputs . has ( R1 . Reg ) && Inputs . has ( R2 . Reg ) ) ; const LatticeCell & L1 = Inputs . get ( R2 . Reg ) ; const LatticeCell & L2 = Inputs . get ( R2 . Reg ) ; if ( L2 . isBottom ( ) ) { if ( L1 . isBottom ( ) ) return false ;

return evaluateORrr ( R2 , R1 , Inputs , Result ) ;


<s> if ( fncode == MMA_BUILTIN_DISASSEMBLE_ACC ) { new_decl = rs6000_builtin_decls [ MMA_BUILTIN_XXMFACC_INTERNAL ] ; new_call = gimple_build_call ( new_decl , <NUM_LIT> , src ) ; src = make_ssa_name ( vector_quad_type_node ) ; gimple_call_set_lhs ( new_call , src ) ; gimple_seq_add_stmt ( & new_seq , new_call ) ; } new_decl = rs6000_builtin_decls [ fncode + <NUM_LIT> ] ; tree dst_type = build_pointer_type_for_mode ( unsigned_V16QI_type_node , ptr_mode , true ) ; tree dst_base = build1 ( VIEW_CONVERT_EXPR , dst_type , dst_ptr ) ; for ( unsigned i = <NUM_LIT> ; i < nvec ; i ++ ) { unsigned index = WORDS_BIG_ENDIAN ? i : nvec - <NUM_LIT> - i ; tree dst = build2 ( MEM_REF , unsigned_V16QI_type_node , dst_base , build_int_cst ( dst_type , index * <NUM_LIT> ) ) ; tree dstssa = make_ssa_name ( unsigned_V16QI_type_node ) ; new_call = gimple_build_call ( new_decl , <NUM_LIT> , src , build_int_cstu ( uint16_type_node , i ) ) ; gimple_call_set_lhs ( new_call , dstssa ) ; gimple_seq_add_stmt ( & new_seq , new_call ) ; gimplify_assign ( dst , dstssa , & new_seq ) ; } pop_gimplify_context ( NULL ) ; gsi_replace_with_seq ( gsi , new_seq , true ) ; return true ; } new_decl = rs6000_builtin_decls [ fncode + <NUM_LIT> ] ; tree lhs , op [ MAX_MMA_OPERANDS ] ; tree acc = gimple_call_arg ( stmt , <NUM_LIT> ) ; push_gimplify_context ( true ) ; if ( ( attr & RS6000_BTC_QUAD ) != <NUM_LIT> ) { op [ <NUM_LIT> ] = make_ssa_name ( vector_quad_type_node ) ; for ( unsigned i = <NUM_LIT> ; i < nopnds ; i ++ ) op [ i ] = gimple_call_arg ( stmt , i ) ;

gimplify_assign ( op [ <NUM_LIT> ] , build_simple_mem_ref ( acc ) , & new_seq ) ;


<s> return __builtin_mve_vbrsrq_n_fv4sf ( __a , __b ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> case <STR_LIT> : return PerformCMOVCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAddCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSubCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformADCCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformMulCombine ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShiftCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformAndCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformOrCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformLOADCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSTORECombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSINT_TO_FPCombine ( N , DAG , this ) ; case <STR_LIT> : return PerformFADDCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformFSUBCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return PerformFORCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformFMinFMaxCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDCombine ( N , DAG ) ; case <STR_LIT> : return PerformFANDNCombine ( N , DAG ) ; case <STR_LIT> : return PerformBTCombine ( N , DAG , DCI ) ; case <STR_LIT> : return PerformVZEXT_MOVLCombine ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return PerformZExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSExtCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformSIGN_EXTEND_INREGCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformTruncateCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformISDSETCCCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : return PerformSETCCCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformBrCondCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performVZEXTCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return PerformShuffleCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return PerformFMACombine ( N , DAG , Subtarget ) ;


<s> DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( A ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { AM . BaseType = <STR_LIT> ; AM . Base . FrameIndex = SI -> second ; return true ; } break ; } case Instruction :: Add : { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( U -> getOperand ( <NUM_LIT> ) ) ) { uint64_t Disp = ( int32_t ) AM . Disp + ( uint64_t ) CI -> getSExtValue ( ) ; if ( isInt < <NUM_LIT> > ( Disp ) ) { AM . Disp = ( uint32_t ) Disp ; return <ISA_LIT>SelectAddress ( U -> getOperand ( <NUM_LIT> ) , AM ) ; } } break ; } case Instruction :: GetElementPtr : { <ISA_LIT>AddressMode SavedAM = AM ; uint64_t Disp = ( int32_t ) AM . Disp ; unsigned IndexReg = AM . IndexReg ; unsigned Scale = AM . Scale ; gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = GTI . getStructTypeOrNull ( ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; Disp += SL -> getElementOffset ( cast < ConstantInt > ( Op ) -> getZExtValue ( ) ) ; continue ; } uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { Disp += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; Disp += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } if ( IndexReg == <NUM_LIT> && ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) && ( S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> || S == <NUM_LIT> ) ) { Scale = S ; IndexReg = getRegForGEPIndex ( Op ) ; if ( IndexReg == <NUM_LIT> ) return false ; break ; } goto unsupported_gep ; } }

if ( ! isInt < <NUM_LIT> > ( Disp ) ) break ;


<s> static DecodeStatus decodeSimm19Value ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: createImm ( Insn ) ) ;


<s> unsigned NumElems = Mask . getNumOperands ( ) ; SmallVector < SDValue , <NUM_LIT> > MaskVec ; DebugLoc dl = Op . getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { SDValue Arg = Mask . getOperand ( i ) ; if ( Arg . getOpcode ( ) == <STR_LIT> ) { MaskVec . push_back ( DAG . getUNDEF ( EltVT ) ) ; continue ; } assert ( isa < ConstantSDNode > ( Arg ) && <STR_LIT> ) ; unsigned Val = cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) ; if ( Val < NumElems ) MaskVec . push_back ( DAG . getConstant ( Val + NumElems , EltVT ) ) ; else MaskVec . push_back ( DAG . getConstant ( Val - NumElems , EltVT ) ) ;


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { SetupMachineFunction ( MF ) ; EmitConstantPool ( ) ; emitFunctionStart ( MF ) ; DW -> BeginFunction ( & MF ) ; EmitFunctionBody ( ) ;


<s> unsigned <ISA_LIT>InstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond , DebugLoc DL ) const { assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( FBB == <NUM_LIT> ) { if ( Cond . empty ( ) ) BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; else BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addMBB ( TBB ) ;


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const {


<s> else { pic = NULL ; type = UNSPEC_INDNTPOFF ; } off = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x ) , type ) ; off = gen_rtx_CONST ( Pmode , off ) ; if ( pic ) off = gen_rtx_PLUS ( Pmode , pic , off ) ; off = gen_const_mem ( Pmode , off ) ; set_mem_alias_set ( off , ix86_GOT_alias_set ( ) ) ; if ( TARGET_64BIT || TARGET_GNU_TLS ) { base = get_thread_pointer ( for_mov || ! TARGET_TLS_DIRECT_SEG_REFS ) ; off = force_reg ( Pmode , off ) ; return gen_rtx_PLUS ( Pmode , base , off ) ; } else { base = get_thread_pointer ( true ) ; dest = gen_reg_rtx ( Pmode ) ; emit_insn ( gen_subsi3 ( dest , base , off ) ) ; } break ; case TLS_MODEL_LOCAL_EXEC : off = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , x ) , ( TARGET_64BIT || TARGET_GNU_TLS ) ? UNSPEC_NTPOFF : UNSPEC_TPOFF ) ; off = gen_rtx_CONST ( Pmode , off ) ; if ( TARGET_64BIT || TARGET_GNU_TLS ) { base = get_thread_pointer ( for_mov || ! TARGET_TLS_DIRECT_SEG_REFS ) ; return gen_rtx_PLUS ( Pmode , base , off ) ; }


<s> bool supportsRMW ( ) const { return m_supportsRMW ;


<s> return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; case <NUM_LIT> : return getCommonSubClass ( & <STR_LIT> , RC ) != nullptr ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> return new MCInstrAnalysis ( Info ) ;


<s> return false ; } if ( I . isPHI ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I ) ; return false ; } if ( I . mayLoad ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I ) ; return false ; } bool DontMoveAcrossStore = true ; if ( ! I . isSafeToMove ( nullptr , DontMoveAcrossStore ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I ) ; return false ; } if ( & I != CmpMI && I . modifiesRegister ( <STR_LIT> , TRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << I ) ; return false ;


<s> return create<ISA_LIT>MachObjectWriter ( false , MachO :: CPU_TYPE_<ISA_LIT> , Subtype ) ;


<s> printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ;


<s> SDValue TrueOpnd = N -> getOperand ( <NUM_LIT> ) ; SDValue FalseOpnd = N -> getOperand ( <NUM_LIT> ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( Cond . getOpcode ( ) != <STR_LIT> || TrueOpnd . getOpcode ( ) != <STR_LIT> || FalseOpnd . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( ! ( Cond . hasOneUse ( ) || TrueOpnd . hasOneUse ( ) || FalseOpnd . hasOneUse ( ) ) ) return SDValue ( ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Cond . getOperand ( <NUM_LIT> ) ) -> get ( ) ; switch ( CC ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TrueOpnd , FalseOpnd ) ; break ; } SDValue CmpOpnd1 = Cond . getOperand ( <NUM_LIT> ) ; SDValue CmpOpnd2 = Cond . getOperand ( <NUM_LIT> ) ; if ( TrueOpnd . getOperand ( <NUM_LIT> ) == CmpOpnd1 && TrueOpnd . getOperand ( <NUM_LIT> ) == CmpOpnd2 && FalseOpnd . getOperand ( <NUM_LIT> ) == CmpOpnd2 && FalseOpnd . getOperand ( <NUM_LIT> ) == CmpOpnd1 ) {

return DAG . getNode ( <STR_LIT> , dl , N -> getOperand ( <NUM_LIT> ) . getValueType ( ) , CmpOpnd1 , CmpOpnd2 , DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ;


<s> unsigned CondReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII -> get ( TargetOpcode :: PHI ) , PhiReg ) . addReg ( InitReg ) . addMBB ( & OrigBB ) . addReg ( ResultReg ) . addMBB ( & LoopBB ) ; BuildMI ( LoopBB , I , DL , TII -> get ( TargetOpcode :: PHI ) , PhiExec ) . addReg ( InitSaveExecReg ) . addMBB ( & OrigBB ) . addReg ( NewExec ) . addMBB ( & LoopBB ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , getUndefRegState ( IdxReg . isUndef ( ) ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , CondReg ) . addReg ( CurrentIdxReg ) . addReg ( IdxReg . getReg ( ) , <NUM_LIT> , IdxReg . getSubReg ( ) ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , NewExec ) . addReg ( CondReg , RegState :: Kill ) ; MRI . setSimpleHint ( NewExec , CondReg ) ; if ( UseGPRIdxMode ) { unsigned IdxReg ; if ( Offset == <NUM_LIT> ) { IdxReg = CurrentIdxReg ; } else { IdxReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , IdxReg ) . addReg ( CurrentIdxReg , RegState :: Kill ) . addImm ( Offset ) ; } unsigned IdxMode = IsIndirectSrc ? VGPRIndexMode :: SRC0_ENABLE : VGPRIndexMode :: DST_ENABLE ; MachineInstr * SetOn = BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) ) . addReg ( IdxReg , RegState :: Kill ) . addImm ( IdxMode ) ; SetOn -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ; } else { if ( Offset == <NUM_LIT> ) { BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CurrentIdxReg , RegState :: Kill ) ; } else { BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( CurrentIdxReg , RegState :: Kill ) . addImm ( Offset ) ; } } MachineInstr * InsertPt = BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( NewExec ) ; BuildMI ( LoopBB , I , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( & LoopBB ) ;


<s> if ( needIndirectCall ) { SDValue MTCTROps [ ] = { Chain , Callee , InFlag } ; if ( isSVR4ABI && is<ISA_LIT>64 && ! isELFv2ABI ) { SDValue LDChain = CallSeqStart . getValue ( CallSeqStart -> getNumValues ( ) - <NUM_LIT> ) ; if ( LDChain . getValueType ( ) == <STR_LIT> ) LDChain = CallSeqStart . getValue ( CallSeqStart -> getNumValues ( ) - <NUM_LIT> ) ; auto MMOFlags = Subtarget . hasInvariantFunctionDescriptors ( ) ? ( MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) : MachineMemOperand :: MONone ; MachinePointerInfo MPI ( CS ? CS . getCalledValue ( ) : nullptr ) ; SDValue LoadFuncPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , Callee , MPI , <NUM_LIT> , MMOFlags ) ; SDValue PtrOff = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue AddPtr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , PtrOff ) ; SDValue LoadEnvPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , AddPtr , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> , MMOFlags ) ; SDValue TOCOff = DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ; SDValue AddTOC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Callee , TOCOff ) ; SDValue TOCPtr = DAG . getLoad ( <STR_LIT> , dl , LDChain , AddTOC , MPI . getWithOffset ( <NUM_LIT> ) , <NUM_LIT> , MMOFlags ) ; setUsesTOCBasePtr ( DAG ) ; SDValue TOCVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , TOCPtr , InFlag ) ; Chain = TOCVal . getValue ( <NUM_LIT> ) ; InFlag = TOCVal . getValue ( <NUM_LIT> ) ; if ( ! hasNest ) { SDValue EnvVal = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , LoadEnvPtr , InFlag ) ; Chain = EnvVal . getValue ( <NUM_LIT> ) ; InFlag = EnvVal . getValue ( <NUM_LIT> ) ;


<s> unsigned getNumFixupKinds ( ) const {


<s> } } else if ( GET_CODE ( op [ <NUM_LIT> ] ) == ASHIFT || GET_CODE ( op [ <NUM_LIT> ] ) == ASHIFTRT || GET_CODE ( op [ <NUM_LIT> ] ) == LSHIFTRT ) { rtx ops [ <NUM_LIT> ] ; ops [ <NUM_LIT> ] = op [ <NUM_LIT> ] ; ops [ <NUM_LIT> ] = XEXP ( op [ <NUM_LIT> ] , <NUM_LIT> ) ; ops [ <NUM_LIT> ] = XEXP ( op [ <NUM_LIT> ] , <NUM_LIT> ) ; switch ( GET_CODE ( op [ <NUM_LIT> ] ) ) { case ASHIFT : switch ( GET_MODE ( op [ <NUM_LIT> ] ) ) { case QImode : ashlqi3_out ( insn , ops , & len ) ; break ; case HImode : ashlhi3_out ( insn , ops , & len ) ; break ; case SImode : ashlsi3_out ( insn , ops , & len ) ; break ; default : break ; } break ; case ASHIFTRT : switch ( GET_MODE ( op [ <NUM_LIT> ] ) ) { case QImode : ashrqi3_out ( insn , ops , & len ) ; break ; case HImode : ashrhi3_out ( insn , ops , & len ) ; break ; case SImode : ashrsi3_out ( insn , ops , & len ) ; break ; default : break ; } break ; case LSHIFTRT : switch ( GET_MODE ( op [ <NUM_LIT> ] ) ) { case QImode : lshrqi3_out ( insn , ops , & len ) ; break ; case HImode : lshrhi3_out ( insn , ops , & len ) ; break ; case SImode : lshrsi3_out ( insn , ops , & len ) ; break ; default : break ; } break ; default : break ; }


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> unsigned asA = LocA . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ;

unsigned asB = LocB . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ;


<s> if ( sh_pass_in_reg_p ( * cum , arg . mode , arg . type ) && ! TARGET_FPU_DOUBLE && ( sh_round_reg ( * cum , arg . mode ) + CEIL ( arg . promoted_size_in_bytes ( ) , UNITS_PER_WORD ) > NPARM_REGS ( arg . mode ) ) ) words = NPARM_REGS ( arg . mode ) - sh_round_reg ( * cum , arg . mode ) ;


<s> static bool required_extensions_p ( enum rvv_base_type type ) { return type == RVV_BASE_eew8_index || type == RVV_BASE_eew16_index || type == RVV_BASE_eew32_index || type == RVV_BASE_eew64_index || type == RVV_BASE_float_vector || type == RVV_BASE_double_trunc_float_vector || type == RVV_BASE_double_trunc_vector || type == RVV_BASE_widen_lmul1_vector || type == RVV_BASE_eew8_interpret || type == RVV_BASE_eew16_interpret || type == RVV_BASE_eew32_interpret || type == RVV_BASE_eew64_interpret || type == RVV_BASE_vlmul_ext_x2 || type == RVV_BASE_vlmul_ext_x4 || type == RVV_BASE_vlmul_ext_x8 || type == RVV_BASE_vlmul_ext_x16 || type == RVV_BASE_vlmul_ext_x32 || type == RVV_BASE_vlmul_ext_x64 ;


<s> EltVT = <STR_LIT> ; VecVT = <STR_LIT> ; EltMask = <NUM_LIT> ; if ( ! VT . isVector ( ) ) { VecVal1 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In1 ) ; VecVal2 = DAG . getTargetInsertSubreg ( <STR_LIT> , DL , VecVT , DAG . getUNDEF ( VecVT ) , In2 ) ; } else { VecVal1 = DAG . getNode ( <STR_LIT> , DL , VecVT , In1 ) ; VecVal2 = DAG . getNode ( <STR_LIT> , DL , VecVT , In2 ) ; } } else { llvm_unreachable ( <STR_LIT> ) ; } SDValue BuildVec = DAG . getConstant ( EltMask , VecVT ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { BuildVec = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BuildVec ) ; BuildVec = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BuildVec ) ; BuildVec = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BuildVec ) ; } SDValue Sel = DAG . getNode ( <STR_LIT> , DL , VecVT , VecVal1 , VecVal2 , BuildVec ) ; if ( VT == <STR_LIT> ) return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , VT , Sel ) ; else if ( VT == <STR_LIT> ) return DAG . getTargetExtractSubreg ( <STR_LIT> , DL , VT , Sel ) ;

else return DAG . getNode ( <STR_LIT> , DL , VT , Sel ) ;


<s> if ( MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && MI -> getOperand ( <NUM_LIT> ) . isSymbol ( ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } return <NUM_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printBranchOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) const { assert ( <STR_LIT> ) ;


<s> unsigned imm = Val << <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( imm ) ) ; tryAddingPcLoadReferenceComment ( Address , ( Address & ~ <NUM_LIT> ) + imm + <NUM_LIT> , Decoder ) ;


<s> bool <ISA_LIT>InstrInfo :: isProfitableToIfCvt ( MachineBasicBlock & MBB , unsigned NumCycles , unsigned ExtraPredCycles , BranchProbability Probability ) const {


<s> unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit3_1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit5 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Bit11 << <NUM_LIT> ) | ( Bit4 << <NUM_LIT> ) | ( Bit9_8 << <NUM_LIT> ) | ( Bit10 << <NUM_LIT> ) | ( Bit6 << <NUM_LIT> ) | ( Bit7 << <NUM_LIT> ) | ( Bit3_1 << <NUM_LIT> ) | Bit5 ; return Value ; } case <STR_LIT> : {

unsigned Bit8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;


<s> return TargetLowering :: getMinimumJumpTableEntries ( ) ;


<s> if ( ! Is64Bit && Idx == <STR_LIT> ) Idx = <STR_LIT> ;

return <ISA_LIT>GenRegisterInfo :: getSubClassWithSubReg ( RC , Idx ) ;


<s> if ( NewPt == IPI . first || DT . dominates ( IPI . first , NewPt ) || ( IPI . first -> getParent ( ) != NewPt -> getParent ( ) && DT . dominates ( IPI . first -> getParent ( ) , NewPt -> getParent ( ) ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( IPI . first -> print ( dbgs ( ) ) ) ; LLVM_DEBUG ( dbgs ( ) << '\n' ) ;

IPI . second . emplace_back ( User , OpNo ) ;


<s> switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: createExpr ( Expr ) ;


<s> if ( res != MatchOperand_Success ) { return res ; } int64_t Int ; Int = StringSwitch < int64_t > ( Value ) . Case ( <STR_LIT> , DstUnused :: UNUSED_PAD ) . Case ( <STR_LIT> , DstUnused :: UNUSED_SEXT ) . Case ( <STR_LIT> , DstUnused :: UNUSED_PRESERVE ) . Default ( <NUM_LIT> ) ; if ( Int == <NUM_LIT> ) { Error ( StringLoc , <STR_LIT> ) ; return MatchOperand_ParseFail ; }

Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , Int , S , <ISA_LIT>Operand :: ImmTySdwaDstUnused ) ) ;


<s> if ( ! Cand . isValid ( ) ) { TryCand . Reason = NodeOrder ; return true ; } if ( tryLess ( TryCand . VGPRUsageDiff > <NUM_LIT> , Cand . VGPRUsageDiff > <NUM_LIT> , TryCand , Cand , RegUsage ) ) return true ; if ( tryGreater ( TryCand . NumSuccessors > <NUM_LIT> , Cand . NumSuccessors > <NUM_LIT> , TryCand , Cand , Successor ) ) return true ; if ( tryGreater ( TryCand . Height , Cand . Height , TryCand , Cand , Depth ) ) return true ; if ( tryLess ( TryCand . VGPRUsageDiff , Cand . VGPRUsageDiff , TryCand , Cand , RegUsage ) ) return true ; return false ;


<s> return new <ISA_LIT>AbstractMemberAccessLegacyPass ( TM ) ;


<s> if ( ExVT . getSizeInBits ( ) == <NUM_LIT> ) { SDNode * And = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Mask , <NUM_LIT> ) , SDValue ( OnesReg , <NUM_LIT> ) ) ; SDValue SubR = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , dl , ExVT , SDValue ( And , <NUM_LIT> ) , SubR ) ) ; return ; } ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , dl , ExVT , SDValue ( Mask , <NUM_LIT> ) , SDValue ( OnesReg , <NUM_LIT> ) ) ) ; return ; } SDNode * Int = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ( Int -> getOpcode ( ) == <STR_LIT> ) ) { unsigned ID = cast < ConstantSDNode > ( Int -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( doesIntrinsicReturnPredicate ( ID ) ) { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Int , <NUM_LIT> ) ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) ) ; ReplaceNode ( N , Result_3 ) ; return ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDNode * RsPd = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Int , <NUM_LIT> ) ) ; ReplaceNode ( N , RsPd ) ; return ; } llvm_unreachable ( <STR_LIT> ) ; }


<s> TargetLowering :: ConstraintWeight <ISA_LIT>TargetLowering :: getSingleConstraintMatchWeight ( AsmOperandInfo & info , const char * constraint ) const { ConstraintWeight weight = CW_Invalid ; Value * CallOperandVal = info . CallOperandVal ; if ( ! CallOperandVal ) return CW_Default ; switch ( * constraint ) { default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'I' : if ( ConstantInt * C = dyn_cast < ConstantInt > ( info . CallOperandVal ) ) { if ( isInt < <NUM_LIT> > ( C -> getSExtValue ( ) ) ) weight = CW_Constant ; } break ; } return weight ;


<s> } } for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) { if ( df_regs_ever_live_p ( i ) && ! call_used_or_fixed_reg_p ( i ) ) { if ( merge_sp_adjust_with_load == <NUM_LIT> && local_fsize == <NUM_LIT> && VAL_14_BITS_P ( - actual_fsize ) ) merge_sp_adjust_with_load = i ; else load_reg ( i , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; } } } offset = ( offset + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( save_fregs ) { if ( frame_pointer_needed ) set_reg_plus_d ( <NUM_LIT> , HARD_FRAME_POINTER_REGNUM , offset , <NUM_LIT> ) ; else set_reg_plus_d ( <NUM_LIT> , STACK_POINTER_REGNUM , offset , <NUM_LIT> ) ; for ( i = FP_SAVED_REG_LAST ; i >= FP_SAVED_REG_FIRST ; i -= FP_REG_STEP ) if ( df_regs_ever_live_p ( i ) || ( ! TARGET_64BIT && df_regs_ever_live_p ( i + <NUM_LIT> ) ) ) { rtx src = gen_rtx_MEM ( DFmode , gen_rtx_POST_INC ( word_mode , tmpreg ) ) ; rtx dest = gen_rtx_REG ( DFmode , i ) ; emit_move_insn ( dest , src ) ; } } emit_insn ( gen_blockage ( ) ) ; if ( frame_pointer_needed ) {


<s> case <STR_LIT> : case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , <STR_LIT> ) ; } break ; } } std :: pair < unsigned , const TargetRegisterClass * > Res ; Res = TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; if ( Res . second == <NUM_LIT> ) { if ( StringsEqualNoCase ( <STR_LIT> , Constraint ) ) { Res . first = <STR_LIT> ; Res . second = <STR_LIT> ; } if ( Constraint == <STR_LIT> ) { Res . first = <STR_LIT> ; Res . second = <STR_LIT> ; } return Res ; } if ( Res . second -> hasType ( VT ) ) return Res ; if ( Res . second == <STR_LIT> ) { if ( VT == <STR_LIT> ) { unsigned DestReg = <NUM_LIT> ; switch ( Res . first ) { default : break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; } if ( DestReg ) { Res . first = DestReg ; Res . second = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { unsigned DestReg = <NUM_LIT> ; switch ( Res . first ) { default : break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; } if ( DestReg ) { Res . first = DestReg ; Res . second = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { unsigned DestReg = <NUM_LIT> ; switch ( Res . first ) { default : break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; case <STR_LIT> : DestReg = <STR_LIT> ; break ; } if ( DestReg ) { Res . first = DestReg ; Res . second = <STR_LIT> ; } }

} else if ( Res . second == <STR_LIT> || Res . second == <STR_LIT> || Res . second == <STR_LIT> ) {


<s> static bool vsetvl_discard_result_insn_p ( rtx_insn * rinsn ) { if ( ! vector_config_insn_p ( rinsn ) ) return false ; return ( INSN_CODE ( rinsn ) == CODE_FOR_vsetvl_discard_resultdi || INSN_CODE ( rinsn ) == CODE_FOR_vsetvl_discard_resultsi ) ;


<s> if ( X . getOpcode ( ) == <STR_LIT> ) return isOrXorXorTree ( X . getOperand ( <NUM_LIT> ) , false ) && isOrXorXorTree ( X . getOperand ( <NUM_LIT> ) , false ) ; if ( Root ) return false ; return X . getOpcode ( ) == <STR_LIT> ;


<s> <ISA_LIT>EB_AsmBackend ( const Target & T , Triple :: OSType _OSType ) : <ISA_LIT>AsmBackend ( T ) , OSType ( _OSType ) {


<s> if ( isa < IntrinsicInst > ( I ) ) if ( auto * Memset = dyn_cast < MemSetInst > ( & I ) ) if ( ! isa < Constant > ( Memset -> getLength ( ) ) ) return true ;


<s> bool <ISA_LIT>MachineFunctionInfo :: hasScheduledCycles ( const MachineBasicBlock * BB ) const {

return ScheduledCycles . find ( BB ) != ScheduledCycles . end ( ) ;


<s> if ( x == const0_rtx ) x = CONST0_RTX ( mode ) ; return x ;


<s> Instruction * lastAddLoadBB1 = incInstruction ( BB1 , BB1 , LoadId , lastAddLoadBB0 , nullptr , after ) ; Instruction * lastAddStoreBB1 = incInstruction ( BB1 , BB1 , StoreId , dyn_cast < Instruction > ( StorePtrList [ <NUM_LIT> ] -> getOperand ( <NUM_LIT> ) ) , nullptr , lastAddLoadBB1 ) ; BasicBlock * preHeader = WorkingLoop -> getLoopPreheader ( ) ; SmallVector < Instruction * , <NUM_LIT> > phiInst = phiFromTwoBasicBlock ( LoadId , ( & * ( * WorkingLoop -> block_begin ( ) ) -> begin ( ) ) , BB0 , BB1 , preHeader , BB1 ) ; IRBuilder < > builder ( BB1 ) ; PHINode * phiLoad = insetPhiInst ( lastAddLoadBB0 , lastAddLoadBB1 , preHeader , lastAddLoadBB1 -> getParent ( ) , builder , Type :: getInt32Ty ( lastAddLoadBB1 -> getContext ( ) ) , <NUM_LIT> , phiInst . back ( ) ) ; SmallVector < IntrinsicInst * , <NUM_LIT> > intrinList = get_list_of < IntrinsicInst , <NUM_LIT> > ( & BB1 ) ; LoadPtrList = extractIntrinFromList ( intrinList , LoadId ) ; LoadPtrList [ <NUM_LIT> ] -> setOperand ( <NUM_LIT> , phiLoad ) ;

LoadPtrList [ <NUM_LIT> ] -> getNextNode ( ) -> setOperand ( <NUM_LIT> , phiLoad ) ;


<s> MI . getOperand ( <NUM_LIT> ) . setReg ( Not ) ; MI . getOperand ( <NUM_LIT> ) . setPredicate ( CmpInst :: getInversePredicate ( Pred ) ) ; Helper . Observer . changedInstr ( MI ) ; Builder . setInsertPt ( Builder . getMBB ( ) , std :: next ( Builder . getInsertPt ( ) ) ) ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( k_MemBarrierOpt ) ; Op -> MBOpt . Val = Opt ; Op -> StartLoc = S ; Op -> EndLoc = S ;


<s> Micro<ISA_LIT>SizeReduce :: Micro<ISA_LIT>SizeReduce ( ) : MachineFunctionPass ( ID ) {


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; if ( isVarArg ) report_fatal_error ( <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { SDValue ArgValue ; CCValAssign & VA = ArgLocs [ i ] ; EVT LocVT = VA . getLocVT ( ) ; if ( VA . isRegLoc ( ) ) { TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : errs ( ) << <STR_LIT> << LocVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ;


<s> const MCConstantExpr * MCE = cast < MCConstantExpr > ( getImm ( ) ) ;

Inst . addOperand ( MCOperand :: createImm ( MCE -> getValue ( ) ) ) ;


<s> split_const ( op , & base , & offset ) ; if ( UNSPEC_ADDRESS_P ( base ) ) op = plus_constant ( Pmode , UNSPEC_ADDRESS ( base ) , INTVAL ( offset ) ) ;


<s> bool LookedThroughZExt = false ; if ( OffsetOpc != TargetOpcode :: G_SHL && OffsetOpc != TargetOpcode :: G_MUL ) { if ( OffsetOpc != TargetOpcode :: G_ZEXT || ! WantsExt ) return None ; OffsetInst = MRI . getVRegDef ( OffsetInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; OffsetOpc = OffsetInst -> getOpcode ( ) ; LookedThroughZExt = true ; if ( OffsetOpc != TargetOpcode :: G_SHL && OffsetOpc != TargetOpcode :: G_MUL ) return None ; } int64_t LegalShiftVal = Log2_32 ( SizeInBytes ) ; if ( LegalShiftVal == <NUM_LIT> ) return None ; if ( ! isWorthFoldingIntoExtendedReg ( * OffsetInst , MRI ) ) return None ; Register OffsetReg = OffsetInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ConstantReg = OffsetInst -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg ) { if ( OffsetOpc == TargetOpcode :: G_SHL ) return None ; std :: swap ( OffsetReg , ConstantReg ) ; ValAndVReg = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! ValAndVReg ) return None ; } int64_t ImmVal = ValAndVReg -> Value . getSExtValue ( ) ; if ( OffsetOpc == TargetOpcode :: G_MUL ) {

if ( ! isPowerOf2_32 ( ImmVal ) ) return None ;


<s> exitMBB -> splice ( exitMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; exitMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( loopMBB ) ; loopMBB -> addSuccessor ( exitMBB ) ; BB = loopMBB ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , OldVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; if ( Nand ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AndRes ) . addReg ( OldVal ) . addReg ( Incr ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , AllOnes ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , StoreVal ) . addReg ( AllOnes ) . addReg ( AndRes ) ; } else if ( BinOpcode ) { BuildMI ( BB , DL , TII -> get ( BinOpcode ) , StoreVal ) . addReg ( OldVal ) . addReg ( Incr ) ; } else { StoreVal = Incr ; }

BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( StoreVal ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ;


<s> if ( ( Op . isMemcpy ( ) || Op . isZeroMemset ( ) ) && Subtarget -> hasNEON ( ) && ! FuncAttributes . hasFnAttribute ( Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT> ; } else if ( Op . size ( ) >= <NUM_LIT> && ( Op . isAligned ( Align ( <NUM_LIT> ) ) || ( allowsMisalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MachineMemOperand :: MONone , & Fast ) && Fast ) ) ) { return <STR_LIT> ; }


<s> static SDValue simplifyI24 ( SDNode * Node24 , TargetLowering :: DAGCombinerInfo & DCI ) { SelectionDAG & DAG = DCI . DAG ; SDValue LHS = Node24 -> getOperand ( <NUM_LIT> ) ; SDValue RHS = Node24 -> getOperand ( <NUM_LIT> ) ;

APInt Demanded = APInt :: getLowBitsSet ( LHS . getValueSizeInBits ( ) , <NUM_LIT> ) ;


<s> if ( ! SllMI || SllMI -> isPHI ( ) || SllMI -> getOpcode ( ) != <STR_LIT> || SllMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SllMI -> dump ( ) ) ; MachineInstr * MovMI = MRI -> getVRegDef ( SllMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( ! MovMI || MovMI -> isPHI ( ) || MovMI -> getOpcode ( ) != <STR_LIT> ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( MovMI -> dump ( ) ) ; unsigned SubReg = MovMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! isMovFrom32Def ( MovMI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; continue ; } BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addReg ( SubReg ) . addImm ( <STR_LIT> ) ; SllMI -> eraseFromParent ( ) ;


<s> if ( auto * II = dyn_cast < InvokeInst > ( & Call ) ) {

assert ( FuncInfo . InvokeStateMap . count ( II ) && <STR_LIT> ) ;


<s> llvm_unreachable ( nullptr ) ; } TopReadySUs . erase ( I ) ; releaseSuccessors ( SU , true ) ; if ( HasLowLatencyNonWaitedParent [ NodeNum2Index [ SU -> NodeNum ] ] ) HasLowLatencyNonWaitedParent . assign ( SUnits . size ( ) , <NUM_LIT> ) ; if ( DAG -> IsLowLatencySU [ SU -> NodeNum ] ) { for ( SDep & Succ : SU -> Succs ) {

std :: map < unsigned , unsigned > :: iterator I = NodeNum2Index . find ( Succ . getSUnit ( ) -> NodeNum ) ;


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; EHSpillSlot [ <NUM_LIT> ] = MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , true ) ;


<s> return ( ! ( CSKY_TARGET_ARCH ( CK802 ) || CSKY_TARGET_ARCH ( CK801 ) ) && try_csky_constant_tricks ( value , & x , & y ) ) ;


<s> mode1 = insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . mode ; if ( arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node ) return const0_rtx ; * expandedp = true ; STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || TREE_INT_CST_LOW ( arg2 ) & ~ <NUM_LIT> ) { error ( <STR_LIT> , d -> name ) ; return const0_rtx ; } if ( ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( Pmode , op0 ) ; if ( ! ( * insn_data [ d -> icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; pat = GEN_FCN ( d -> icode ) ( op0 , op1 , op2 ) ; if ( pat != <NUM_LIT> ) emit_insn ( pat ) ; return NULL_RTX ;


<s> if ( Desc . getOpcode ( ) == <STR_LIT> ) { Size += GetInstSizeWithDesc ( * MI , & get ( <STR_LIT> ) , IsPIC , Is64BitMode ) ; }


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator MI , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const {


<s> static bool pa_pass_by_reference ( cumulative_args_t ca ATTRIBUTE_UNUSED , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { HOST_WIDE_INT size ; if ( type ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ;

if ( TARGET_64BIT ) return size <= <NUM_LIT> ;


<s> getAssembler ( ) . setIsThumbFunc ( Func ) ; EmitSymbolAttribute ( Func , MCSA_ELF_TypeFunction ) ;


<s> case 'h' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> , true ) ; break ; case 'w' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ; case 'k' : Reg = get<ISA_LIT>SubSuperRegister ( Reg , <STR_LIT> ) ; break ;


<s> MVT SrcVT = N0 . getValueType ( ) ; if ( SrcVT == <STR_LIT> ) { if ( Op . getValueType ( ) != <STR_LIT> || ! <ISA_LIT>ScalarSSEf64 ) return SDValue ( ) ; return LowerUINT_TO_FP_i64 ( Op , DAG ) ; } else if ( SrcVT == <STR_LIT> ) { return LowerUINT_TO_FP_i32 ( Op , DAG ) ; }


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectBRCOND ( SDNode * Node ) { assert ( Node -> getNumOperands ( ) >= <NUM_LIT> ) ; SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue Pred = Node -> getOperand ( <NUM_LIT> ) ; SDValue Target = Node -> getOperand ( <NUM_LIT> ) ; SDValue PredOp = CurDAG -> getTargetConstant ( <ISA_LIT>Predicate :: Normal , <STR_LIT> ) ; DebugLoc dl = Node -> getDebugLoc ( ) ; assert ( Target . getOpcode ( ) == <STR_LIT> ) ; assert ( Pred . getValueType ( ) == <STR_LIT> ) ;

SDValue Ops [ ] = { Target , Pred , PredOp , Chain } ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & ST ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , ST . is64Bit ( ) ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) , <NUM_LIT> , ST . is64Bit ( ) ? Align ( <NUM_LIT> ) : Align ( <NUM_LIT> ) ) {


<s> for ( int I = MFFrame . getObjectIndexBegin ( ) ; I != <NUM_LIT> ; ++ I ) if ( MFFrame . getObjectOffset ( I ) >= <NUM_LIT> ) { int64_t ArgOffset = MFFrame . getObjectOffset ( I ) + MFFrame . getObjectSize ( I ) ; MaxArgOffset = std :: max ( MaxArgOffset , ArgOffset ) ; } uint64_t MaxReach = StackSize + MaxArgOffset ; if ( ! isUInt < <NUM_LIT> > ( MaxReach ) ) {

RS -> addScavengingFrameIndex ( MFFrame . CreateStackObject ( <NUM_LIT> , Align ( <NUM_LIT> ) , false ) ) ;


<s> bool hasArithmeticCbzFusion ( ) const { return HasArithmeticCbzFusion ;


return Kind == Memory && ! getMemSegReg ( ) && ! getMemBaseReg ( ) && ! getMemIndexReg ( ) && getMemScale ( ) == <NUM_LIT> && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) ;


<s> <ISA_LIT>Operand & TyOp = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; bool isVmovf = TyOp . isToken ( ) && ( TyOp . getToken ( ) == <STR_LIT> || TyOp . getToken ( ) == <STR_LIT> ) ; <ISA_LIT>Operand & Mnemonic = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; bool isFconst = Mnemonic . isToken ( ) && ( Mnemonic . getToken ( ) == <STR_LIT> || Mnemonic . getToken ( ) == <STR_LIT> ) ; if ( ! ( isVmovf || isFconst ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; SMLoc Loc = Tok . getLoc ( ) ; if ( Tok . is ( AsmToken :: Real ) && isVmovf ) { APFloat RealVal ( APFloat :: IEEEsingle , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( IntVal , getContext ( ) ) , S , Parser . getTok ( ) . getLoc ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: Integer ) && isFconst ) { int64_t Val = Tok . getIntVal ( ) ; Parser . Lex ( ) ; if ( Val > <NUM_LIT> || Val < <NUM_LIT> ) { Error ( Loc , <STR_LIT> ) ; return MatchOperand_ParseFail ; } float RealVal = <STR_LIT> ( Val ) ; Val = APFloat ( RealVal ) . bitcastToAPInt ( ) . getZExtValue ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( Val , getContext ( ) ) , S , Parser . getTok ( ) . getLoc ( ) ) ) ; return MatchOperand_Success ; } Error ( Loc , <STR_LIT> ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCT ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ;

setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ;


<s> else if ( MO . isGlobal ( ) ) emitGlobalAddress ( MO . getGlobal ( ) , <STR_LIT> , true , false ) ; else if ( MO . isSymbol ( ) ) emitExternalSymbolAddress ( MO . getSymbolName ( ) , <STR_LIT> ) ; else if ( MO . isCPI ( ) ) { const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Reloc = ( ( TID . TSFlags & <STR_LIT> ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; emitConstPoolAddress ( MO . getIndex ( ) , Reloc ) ; } else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , <STR_LIT> ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , <STR_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override {


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MFI -> setFrameAddressIsTaken ( true ) ; bool is31 = ( DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ) && MFI -> getStackSize ( ) && ! MF . getFunction ( ) -> hasFnAttr ( Attribute :: Naked ) ; unsigned FrameReg = is<ISA_LIT>64 ? ( is31 ? <STR_LIT> : <STR_LIT> ) :


<s> if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . in<ISA_LIT>16Mode ( ) ) return false ; if ( ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) && TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isABI_O32 ( ) && F . getInfo < <ISA_LIT>FunctionInfo > ( ) -> globalBaseRegSet ( ) ) emitGPDisp ( F , TII ) ; if ( SkipLongBranch ) return true ; MF = & F ; initMBBInfo ( ) ; SmallVectorImpl < MBBInfo > :: iterator I , E = MBBInfos . end ( ) ; bool EverMadeChange = false , MadeChange = true ; while ( MadeChange ) { MadeChange = false ; for ( I = MBBInfos . begin ( ) ; I != E ; ++ I ) { if ( ! I -> Br || I -> HasLongBranch ) continue ; if ( ! ForceLongBranch && isInt < <NUM_LIT> > ( computeOffset ( I -> Br ) / <NUM_LIT> ) ) continue ; I -> HasLongBranch = true ; I -> Size += LongBranchSeqSize * <NUM_LIT> ; ++ LongBranches ; EverMadeChange = MadeChange = true ; } } if ( ! EverMadeChange ) return true ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { uint64_t Address = <NUM_LIT> ;

for ( I = MBBInfos . begin ( ) ; I != E ; Address += I -> Size , ++ I ) I -> Address = Address ;


<s> AFI = Fn . getInfo < <ISA_LIT>FunctionInfo > ( ) ; isThumb = AFI -> isThumbFunction ( ) ; HasFarJump = false ; Fn . RenumberBlocks ( ) ; AFI -> setAlign ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; std :: vector < MachineInstr * > CPEMIs ; if ( ! MCP . isEmpty ( ) ) { DoInitialPlacement ( Fn , CPEMIs ) ; if ( isThumb ) AFI -> setAlign ( <NUM_LIT> ) ; } AFI -> initConstPoolEntryUId ( CPEMIs . size ( ) ) ; InitialFunctionScan ( Fn , CPEMIs ) ; CPEMIs . clear ( ) ; RemoveUnusedCPEntries ( ) ; bool MadeChange = false ; while ( true ) { bool Change = false ; for ( unsigned i = <NUM_LIT> , e = CPUsers . size ( ) ; i != e ; ++ i ) Change |= HandleConstantPoolUser ( Fn , i ) ; DEBUG ( dumpBBs ( ) ) ; for ( unsigned i = <NUM_LIT> , e = ImmBranches . size ( ) ; i != e ; ++ i ) Change |= FixUpImmediateBr ( Fn , ImmBranches [ i ] ) ; DEBUG ( dumpBBs ( ) ) ; if ( ! Change ) break ; MadeChange = true ; } verify ( Fn ) ; if ( ! HasFarJump && AFI -> isLRSpilledForFarJump ( ) && isThumb ) MadeChange |= UndoLRSpillRestore ( ) ; BBSizes . clear ( ) ; BBOffsets . clear ( ) ; WaterList . clear ( ) ; CPUsers . clear ( ) ;


<s> case AMDGPU :: R600_ExportSwz : case AMDGPU :: EG_ExportSwz : return true ; default : return false ; }


<s> assert ( isMem ( MI , Op ) && <STR_LIT> ) ; const MachineOperand & Segment = MI -> getOperand ( Op + <NUM_LIT> ) ;


<s> } else { MachineOperand & FlagOp = getFlagOp ( MI ) ; unsigned InstFlags = FlagOp . getImm ( ) ; InstFlags &= ~ ( Flag << ( NUM_MO_FLAGS * Operand ) ) ; FlagOp . setImm ( InstFlags ) ;


<s> bool <ISA_LIT>RegisterInfo :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

return NoFramePointerElim || MFI -> hasVarSizedObjects ( ) ;


<s> bool useAA ( ) const override { return true ;


<s> for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( JUMP_P ( insn ) || CALL_P ( insn ) ) split_delayed_branch ( insn ) ;


<s> Register DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ;

bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ;


union { __v2sf v ; float a [ <NUM_LIT> ] ; } __tmp = { ( __v2sf ) __A } ;


<s> Inst . addOperand ( MCOperand :: CreateReg ( getReg ( ) ) ) ;


<s> Result = CC_<ISA_LIT>32_SVR4_VarArg ( i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo ) ; } if ( Result ) { errs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ; llvm_unreachable ( nullptr ) ; } } } else { CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>32_SVR4 ) ; } CCInfo . clearWas<ISA_LIT>F128 ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ByValArgLocs ; CCState CCByValInfo ( CallConv , IsVarArg , MF , ByValArgLocs , * DAG . getContext ( ) ) ; CCByValInfo . AllocateStack ( CCInfo . getNextStackOffset ( ) , PtrByteSize ) ; CCByValInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT>32_SVR4_ByVal ) ; unsigned NumBytes = CCByValInfo . getNextStackOffset ( ) ; int SPDiff = CalculateTailCallSPDiff ( DAG , IsTailCall , NumBytes ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , dl ) ; SDValue CallSeqStart = Chain ; SDValue LROp , FPOp ; Chain = EmitTailCallLoadFPAndRetAddr ( DAG , SPDiff , Chain , LROp , FPOp , dl ) ; SDValue StackPtr = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < TailCallArgumentInfo , <NUM_LIT> > TailCallArguments ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; bool seenFloatArg = false ; for ( unsigned i = <NUM_LIT> , RealArgIdx = <NUM_LIT> , j = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i , ++ RealArgIdx ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ RealArgIdx ] ; <STR_LIT> Flags = Outs [ RealArgIdx ] . Flags ; if ( Flags . isByVal ( ) ) { assert ( ( j < ByValArgLocs . size ( ) ) && <STR_LIT> ) ; CCValAssign & ByValVA = ByValArgLocs [ j ++ ] ; assert ( ( VA . getValNo ( ) == ByValVA . getValNo ( ) ) && <STR_LIT> ) ; unsigned LocMemOffset = ByValVA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , dl ) ; PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( MF . getDataLayout ( ) ) , StackPtr , PtrOff ) ;

SDValue MemcpyCall = CreateCopyOfByValArgument ( Arg , PtrOff , CallSeqStart . getNode ( ) -> getOperand ( <NUM_LIT> ) , Flags , DAG , dl ) ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT ) const { if ( ! VT . isVector ( ) ) return getPointerTy ( ) ;

return VT . changeVectorElementTypeToInteger ( ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( getVectorIndex ( ) ) ) ;


<s> CPU = <STR_LIT> ; } return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ;


<s> unsigned getMemOp ( ) const { assert ( isMem ( ) && <STR_LIT> ) ;


<s> if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; Node -> setNodeId ( - <NUM_LIT> ) ; return ; } if ( trySelect ( Node ) ) return ;


<s> void EmitBytes ( StringRef Data ) override {


<s> break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPairSpacedRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; } if ( Rm != <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> && Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


return UseHVXIEEEFPOps && useHVXOps ( ) ;


<s> createEntryPHIs ( CurrentRegion ) ; removeExternalCFGSuccessors ( CodeBB ) ; CodeBB -> addSuccessor ( MergeBB ) ; CurrentRegion -> addMBB ( CodeBB ) ; return nullptr ; } else { const TargetRegisterClass * RegClass = MRI -> getRegClass ( BBSelectRegIn ) ; Register CodeBBSelectReg = MRI -> createVirtualRegister ( RegClass ) ; rewriteCodeBBTerminator ( CodeBB , MergeBB , CodeBBSelectReg ) ; bool IsRegionEntryBB = CurrentRegion -> getEntry ( ) == CodeBB ; MachineBasicBlock * IfBB = createIfBlock ( MergeBB , CodeBB , CodeBB , CodeBB , BBSelectRegIn , IsRegionEntryBB ) ; CurrentRegion -> addMBB ( IfBB ) ; if ( IsRegionEntryBB ) { CurrentRegion -> setEntry ( IfBB ) ; if ( CurrentRegion -> getHasLoop ( ) ) { MachineBasicBlock * RegionExit = CurrentRegion -> getExit ( ) ; MachineBasicBlock * ETrueBB = nullptr ; MachineBasicBlock * EFalseBB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > ECond ; const DebugLoc & DL = DebugLoc ( ) ; TII -> analyzeBranch ( * RegionExit , ETrueBB , EFalseBB , ECond ) ;


<s> case FK_Data_2 : case FK_GPRel_4 : case FK_Data_4 : case FK_Data_8 : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isIntN ( <NUM_LIT> , Value ) && Ctx ) Ctx -> FatalError ( Fixup . getLoc ( ) , <STR_LIT> ) ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ;


<s> unsigned size ( ) const { return Size ;


<s> if ( miI == BB -> end ( ) ) { for ( MachineBasicBlock :: succ_iterator sItr = BB -> succ_begin ( ) , sEnd = BB -> succ_end ( ) ; sItr != sEnd ; ++ sItr ) { MachineBasicBlock * succ = * sItr ; if ( succ -> isLiveIn ( <STR_LIT> ) ) return false ; }


<s> InsertInfo ( MachineInstrBuilder & MIB ) : MBB ( * MIB -> getParent ( ) ) , InsertBefore ( std :: next ( MIB -> getIterator ( ) ) ) , DbgLoc ( MIB -> getDebugLoc ( ) ) {


<s> rtx reg ; slotno = mt_function_arg_slotno ( cum , mode , type , named , incoming_p , & regno ) ; if ( slotno == - <NUM_LIT> ) reg = NULL_RTX ; else reg = gen_rtx_REG ( mode , regno ) ;


<s> if ( j == <NUM_LIT> ) break ; if ( ! BucketChain . Elements [ j ] . Offset || cast < SCEVConstant > ( BucketChain . Elements [ j ] . Offset ) -> isZero ( ) ) break ; const SCEV * Offset = BucketChain . Elements [ j ] . Offset ; BucketChain . BaseSCEV = SE -> getAddExpr ( BucketChain . BaseSCEV , Offset ) ;

for ( auto & E : BucketChain . Elements ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MVT NVT = <STR_LIT> ( <STR_LIT> , SrcVT . getVectorNumElements ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , NVT , N0 ) ) ; } case <STR_LIT> : return lowerUINT_TO_FP_v2i32 ( Op , DAG , Subtarget , dl ) ; case <STR_LIT> : case <STR_LIT> : return lowerUINT_TO_FP_vXi32 ( Op , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget . hasAVX512 ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N0 ) ) ;


<s> if ( ! parseLEBImmediate ( MI , Size , Bytes , false ) ) return MCDisassembler :: Fail ; break ; } case <STR_LIT> : case <STR_LIT> : { if ( ! parseLEBImmediate ( MI , Size , Bytes , true ) ) return MCDisassembler :: Fail ; break ; } case <STR_LIT> : { int64_t Val ; uint64_t PrevSize = Size ; if ( ! nextLEB ( Val , Bytes , Size , true ) ) return MCDisassembler :: Fail ; if ( Val < <NUM_LIT> ) { if ( Size != PrevSize + <NUM_LIT> ) { MI . addOperand ( MCOperand :: createImm ( int64_t ( <STR_LIT> :: Invalid ) ) ) ; } else { MI . addOperand ( MCOperand :: createImm ( Val & <NUM_LIT> ) ) ; } } else { MCSymbol * Sym = getContext ( ) . createTempSymbol ( <STR_LIT> , true ) ; auto * WasmSym = cast < MCSymbolWasm > ( Sym ) ; WasmSym -> setType ( <STR_LIT> ) ; const MCExpr * Expr = MCSymbolRefExpr :: create ( WasmSym , MCSymbolRefExpr :: VK_WASM_TYPEINDEX , getContext ( ) ) ; MI . addOperand ( MCOperand :: createExpr ( Expr ) ) ; } break ; } case <STR_LIT> : { if ( ! parseImmediate < float > ( MI , Size , Bytes ) ) return MCDisassembler :: Fail ; break ; } case <STR_LIT> : { if ( ! parseImmediate < double > ( MI , Size , Bytes ) ) return MCDisassembler :: Fail ; break ; } case <STR_LIT> : { if ( ! parseImmediate < uint8_t > ( MI , Size , Bytes ) ) return MCDisassembler :: Fail ; break ; } case <STR_LIT> : { if ( ! parseImmediate < uint16_t > ( MI , Size , Bytes ) ) return MCDisassembler :: Fail ; break ; } case <STR_LIT> : { if ( ! parseImmediate < uint32_t > ( MI , Size , Bytes ) ) return MCDisassembler :: Fail ; break ;


<s> if ( ! IsResolved && Fixup . getValue ( ) -> evaluateAsValue ( Res , Layout ) && Res . isAbsolute ( ) ) { Value = Res . getConstant ( ) ;


<s> not_to_clear_mask = comp_not_to_clear_mask_str_un ( arg_type , & regno , padding_bits_to_clear , <NUM_LIT> , & last_used_bit ) ; if ( last_used_bit != <NUM_LIT> ) padding_bits_to_clear [ regno ] |= ( ( uint32_t ) - <NUM_LIT> ) - ( ( uint32_t ) <NUM_LIT> << last_used_bit ) + <NUM_LIT> ; else not_to_clear_mask &= ~ ( HOST_WIDE_INT_1U << regno ) ; } else { not_to_clear_mask = <NUM_LIT> ; if ( GET_MODE ( arg_rtx ) == BLKmode ) { int i , arg_regs ; rtx reg ; gcc_assert ( TARGET_HARD_FLOAT_ABI ) ; for ( i = <NUM_LIT> ; i < XVECLEN ( arg_rtx , <NUM_LIT> ) ; i ++ ) { reg = XEXP ( XVECEXP ( arg_rtx , <NUM_LIT> , i ) , <NUM_LIT> ) ; gcc_assert ( REG_P ( reg ) ) ; not_to_clear_mask |= HOST_WIDE_INT_1U << REGNO ( reg ) ; arg_regs = ARM_NUM_REGS ( GET_MODE ( reg ) ) ; if ( arg_regs > <NUM_LIT> ) { unsigned HOST_WIDE_INT mask ; mask = HOST_WIDE_INT_1U << ( REGNO ( reg ) + arg_regs ) ; mask -= HOST_WIDE_INT_1U << REGNO ( reg ) ; not_to_clear_mask |= mask ; } } } else { int arg_regs = ARM_NUM_REGS ( GET_MODE ( arg_rtx ) ) ;

not_to_clear_mask |= HOST_WIDE_INT_1U << REGNO ( arg_rtx ) ;


<s> i386_pe_declare_function_type ( f , name , TREE_PUBLIC ( decl ) ) ; if ( decl != NULL_TREE ) switch_to_section ( function_section ( decl ) ) ;

ASM_OUTPUT_FUNCTION_LABEL ( f , name , decl ) ;


<s> if ( scalar ) { fc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Rm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRwithZRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else { fc = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned Qm = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeMQPRRegisterClass ( Inst , Qm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , predicate_decoder ( Inst , fc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ;

Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;


SecondHalfOfMandatoryField |= TracebackTable :: IsBackChainStoredMask ;


<s> FOR_EACH_MODE_IN_CLASS ( mode , mclass ) if ( inner_mode == GET_MODE_INNER ( mode ) && known_eq ( nunits , GET_MODE_NUNITS ( mode ) ) && aarch64_sve_data_mode_p ( mode ) ) return mode ; return opt_machine_mode ( ) ;


<s> return E -> getKind ( ) == MCExpr :: Target ;


<s> assert ( isSimilarDispOp ( Op1 , Op2 ) && <STR_LIT> ) ; if ( Op1 . isJTI ( ) ) return <NUM_LIT> ;

return Op1 . isImm ( ) ? Op1 . getImm ( ) - Op2 . getImm ( ) : Op1 . getOffset ( ) - Op2 . getOffset ( ) ;


<s> PointerType * PtrType = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <STR_LIT> ) ; assert ( isInt < <NUM_LIT> > ( ByteOffset ) ) ;

return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getConstant ( ByteOffset , <STR_LIT> ) , MachinePointerInfo ( ConstantPointerNull :: get ( PtrType ) ) , false , false , false , <NUM_LIT> ) ;


<s> ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } bool Done = rewriteFrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> ) ;


<s> assert ( insn . mode == MODE_16BIT ) ; baseRegNo = insn . hasAdSize ? <STR_LIT> : <STR_LIT> ; } MCOperand baseReg = MCOperand :: createReg ( baseRegNo ) ; mcInst . addOperand ( baseReg ) ; return false ;


<s> bool aarch64_move_imm ( HOST_WIDE_INT val , machine_mode mode ) {

if ( aarch64_movw_imm ( val , mode ) || aarch64_movw_imm ( ~ val , mode ) ) return <NUM_LIT> ;


<s> enum { N = <NUM_LIT> , Z = <NUM_LIT> , C = <NUM_LIT> , V = <NUM_LIT> } ; switch ( Code ) { default : llvm_unreachable ( <STR_LIT> ) ; case EQ : return Z ; case NE : return <NUM_LIT> ; case HS : return C ; case LO : return <NUM_LIT> ;


<s> SDValue StVal = S -> getValue ( ) ; EVT VT = StVal . getValueType ( ) ; if ( ! VT . isVector ( ) || VT . getVectorNumElements ( ) < <NUM_LIT> || VT == <STR_LIT> ) return SDValue ( ) ; if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , S ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , DL , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> isVolatile ( ) , S -> isNonTemporal ( ) , S -> getAlignment ( ) ) ;

SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


return ( TARGET_ARCH64 ? DImode : SImode ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( The<ISA_LIT>Target ) ;


<s> int param_size = csky_num_arg_regs ( arg . mode , arg . type , pcum -> is_stdarg ) ; int reg = pcum -> reg ;

if ( FUNCTION_VARG_MODE_P ( arg . mode ) && ! pcum -> is_stdarg ) return <NUM_LIT> ;