<s> const MCOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <STR_LIT> . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <STR_LIT> . contains ( IndexReg . getReg ( ) ) ) ) return true ; return false ;


<s> SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GA ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; SDValue GlobalBase = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) ) ; SDValue RelAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ;

SDValue AbsAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , GlobalBase , RelAddr ) ;


<s> <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler & mang , AsmPrinter & printer ) : Ctx ( ctx ) , Mang ( mang ) , Printer ( printer ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ;

MCSymbol * GetJumpTableSymbol ( const MachineOperand & MO ) const ;


<s> void <ISA_LIT>LateBranchLowering :: earlyTerm ( MachineInstr & MI , MachineBasicBlock * EarlyExitBlock ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; const DebugLoc DL = MI . getDebugLoc ( ) ; auto BranchMI = BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EarlyExitBlock ) ; auto Next = std :: next ( MI . getIterator ( ) ) ; if ( Next != MBB . end ( ) && ! Next -> isTerminator ( ) ) splitBlock ( MBB , * BranchMI , MDT ) ;


<s> assert ( Kind == KindTy :: Register && <STR_LIT> ) ;


<s> Value * Load = M -> getOrInsertFunction ( <STR_LIT> , Type :: getByteTy ( Context ) , Type :: getIntBytePtrTy ( Context ) ) ; Value * Store = M -> getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( Context ) , Type :: getIntBytePtrTy ( Context ) , Type :: getByteTy ( Context ) ) ; for ( auto II = BB . begin ( ) , IE = BB . end ( ) ; II != IE ; ) { Instruction * I = & * II ++ ; if ( LoadInst * LI = dyn_cast < LoadInst > ( I ) ) { CallInst * C = CallInst :: Create ( Load , { LI -> getPointerOperand ( ) } , <STR_LIT> , LI ) ; BasicBlock :: iterator It ( LI ) ; ReplaceInstWithValue ( LI -> getParent ( ) -> getInstList ( ) , It , C ) ; Changed = true ; } else if ( StoreInst * SI = dyn_cast < StoreInst > ( I ) ) { Value * Args [ ] = { SI -> getPointerOperand ( ) , SI -> getValueOperand ( ) } ; CallInst * C = CallInst :: Create ( Store , Args ) ; ReplaceInstWithInst ( I , C ) ; Changed = true ; } } return Changed ;


<s> <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = <NUM_LIT> ; DebugLoc DL = Op . getDebugLoc ( ) ; EVT PtrVT = getPointerTy ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; if ( RelocM == Reloc :: Static ) { CPAddr = DAG . getTargetConstantPool ( BA , PtrVT , <NUM_LIT> ) ; } else { unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( BA , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; } CPAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , CPAddr ) ;

SDValue Result = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , <NUM_LIT> ) ;


<s> const auto & DL = DAG . getDataLayout ( ) ; const auto & TLI = DAG . getTargetLoweringInfo ( ) ; const char * Name = nullptr ; if ( Signed ) Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Name = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue ES = DAG . getExternalSymbol ( Name , TLI . getPointerTy ( DL ) ) ; <ISA_LIT>TargetLowering :: ArgListTy Args ; for ( auto AI : { <NUM_LIT> , <NUM_LIT> } ) { ArgListEntry Arg ; Arg . Node = Op . getOperand ( AI ) ; Arg . Ty = Arg . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Args . push_back ( Arg ) ;


<s> return ParseMemory ( Operands ) ; case AsmToken :: LCurly : return ParseRegisterList ( Operands ) ; case AsmToken :: Hash : S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ; return false ; case AsmToken :: Colon : { <ISA_LIT>MCExpr :: VariantKind RefKind ; if ( ParsePrefix ( RefKind ) ) return true ; const MCExpr * SubExprVal ; if ( getParser ( ) . ParseExpression ( SubExprVal ) ) return true ; const MCExpr * ExprVal = <ISA_LIT>MCExpr :: Create ( RefKind , SubExprVal , getContext ( ) ) ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ExprVal , S , E ) ) ; return false ; }


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS64Bit4ByteAligned ( MachineOperand & Root ) const { return selectDSReadWrite2 ( Root , <NUM_LIT> ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HI : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; } OS << '(' ; Expr -> print ( OS ) ; OS << ')' ;


<s> if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getFPTOSINT ( SrcVal . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getFPTOUINT ( SrcVal . getValueType ( ) , Op . getValueType ( ) ) ;

return LowerF128Call ( Op , DAG , LC ) ;


<s> const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; MCPhysReg Reg = MFI -> getVGPRToAGPRSpill ( Index , Lane ) ; if ( Reg == <STR_LIT> ) return MachineInstrBuilder ( ) ; bool IsStore = MI -> mayStore ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; auto * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; unsigned Dst = IsStore ? Reg : ValueReg ; unsigned Src = IsStore ? ValueReg : Reg ; bool IsVGPR = TRI -> isVGPR ( MRI , Reg ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; if ( IsVGPR == TRI -> isVGPR ( MRI , ValueReg ) ) { auto CopyMIB = BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Src , getKillRegState ( IsKill ) ) ; CopyMIB -> setAsmPrinterFlag ( MachineInstr :: ReloadReuse ) ; return CopyMIB ; }

unsigned Opc = ( IsStore ^ IsVGPR ) ? <STR_LIT> : <STR_LIT> ;


<s> void h8300_swap_into_er6 ( rtx addr ) { rtx insn = push ( HARD_FRAME_POINTER_REGNUM , false ) ; if ( frame_pointer_needed ) add_reg_note ( insn , REG_CFA_DEF_CFA , plus_constant ( Pmode , gen_rtx_MEM ( Pmode , stack_pointer_rtx ) , <NUM_LIT> * UNITS_PER_WORD ) ) ; else add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , <NUM_LIT> ) ) ) ;

emit_move_insn ( hard_frame_pointer_rtx , addr ) ;


<s> static DecodeStatus DecodeLSAImm ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( Insn + <NUM_LIT> ) ) ;


<s> void <ISA_LIT>COFFMCAsmInfoGNU :: anchor ( ) {


<s> <ISA_LIT>MachineFunctionInfo * MFI = const_cast < <ISA_LIT>MachineFunctionInfo * > ( MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ) ; unsigned NumSlotsTotal = <STR_LIT> . getNumRegs ( ) ; unsigned RegSlots = NumSlotsTotal / <NUM_LIT> ; if ( MFI -> getRegisterPartitioning ( ) == <NUM_LIT> ) { const MachineRegisterInfo & RI = MF . getRegInfo ( ) ; unsigned rc32 = <NUM_LIT> , rc64 = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = RI . getNumVirtRegs ( ) ; i != e ; ++ i ) { switch ( RI . getRegClass ( index2VirtReg ( i ) ) -> getSize ( ) ) { case <NUM_LIT> : rc32 ++ ; break ; case <NUM_LIT> : rc64 ++ ; break ; } } if ( <ISA_LIT>RegSlots > <NUM_LIT> ) { RegSlots = <ISA_LIT>RegSlots ; } else { if ( rc64 < ( NumSlotsTotal - RegSlots ) && rc32 > ( RegSlots * <NUM_LIT> ) ) { RegSlots = NumSlotsTotal - rc64 ; } else if ( rc32 < ( RegSlots * <NUM_LIT> ) && rc64 > ( NumSlotsTotal - RegSlots ) ) { RegSlots = ( rc32 + <NUM_LIT> ) / <NUM_LIT> ; } } if ( RegSlots < <NUM_LIT> ) RegSlots = <NUM_LIT> ;

else if ( RegSlots > ( NumSlotsTotal - <NUM_LIT> ) ) RegSlots = NumSlotsTotal - <NUM_LIT> ;


<s> } else { unsigned RegSize = RegVT . getSizeInBits ( ) ; assert ( RegSize == <NUM_LIT> || RegSize == <NUM_LIT> || Subtarget . isHVXVectorType ( RegVT ) ) ; } InVals . push_back ( Copy ) ; MRI . addLiveIn ( VA . getLocReg ( ) , VReg ) ; HFL . FirstVarArgSavedReg = NextSingleReg ( * RC , VA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = Flags . isByVal ( ) ? Flags . getByValSize ( ) : VA . getLocVT ( ) . getStoreSizeInBits ( ) / <NUM_LIT> ; int Offset = HEXAGON_LRFP_SIZE + VA . getLocMemOffset ( ) ; int FI = MFI . CreateFixedObject ( ObjSize , Offset , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; if ( Flags . isByVal ( ) ) { InVals . push_back ( FIN ) ; } else { SDValue L = DAG . getLoad ( VA . getValVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI , <NUM_LIT> ) ) ; InVals . push_back ( L ) ; } } } if ( IsVarArg && Subtarget . isEnvironmentMusl ( ) ) { for ( int i = HFL . FirstVarArgSavedReg ; i < <NUM_LIT> ; i ++ ) MRI . addLiveIn ( <STR_LIT> + i ) ; } if ( IsVarArg && Subtarget . isEnvironmentMusl ( ) ) { HMFI . setFirstNamedArgFrameIndex ( HMFI . getFirstNamedArgFrameIndex ( ) - <NUM_LIT> ) ; HMFI . setLastNamedArgFrameIndex ( - int ( MFI . getNumFixedObjects ( ) ) ) ; int NumVarArgRegs = <NUM_LIT> - HFL . FirstVarArgSavedReg ; bool RequiresPadding = ( NumVarArgRegs & <NUM_LIT> ) ; int RegSaveAreaSizePlusPadding = RequiresPadding ? ( NumVarArgRegs + <NUM_LIT> ) * <NUM_LIT> : NumVarArgRegs * <NUM_LIT> ; if ( RegSaveAreaSizePlusPadding > <NUM_LIT> ) { int RegAreaStart = HEXAGON_LRFP_SIZE + CCInfo . getNextStackOffset ( ) ; if ( ! ( RegAreaStart % <NUM_LIT> ) ) RegAreaStart = ( RegAreaStart + <NUM_LIT> ) & - <NUM_LIT> ; int RegSaveAreaFrameIndex = MFI . CreateFixedObject ( RegSaveAreaSizePlusPadding , RegAreaStart , true ) ; HMFI . setRegSavedAreaStartFrameIndex ( RegSaveAreaFrameIndex ) ;

int Offset = RegAreaStart + RegSaveAreaSizePlusPadding ;


<s> static bool ContainsReg ( const ArrayRef < std :: pair < unsigned , bool >> & Regs , unsigned Reg ) {

for ( const std :: pair < unsigned , bool > & R : Regs ) if ( R . first == Reg ) return true ;


<s> inline vector signed int vec_vmulesh ( vector signed short a1 , vector signed short a2 ) { return ( vector signed int ) __builtin_altivec_vmulesh ( ( vector signed short ) a1 , ( vector signed short ) a2 ) ;


<s> SmallVector < Type * , <NUM_LIT> > Types = { I . getInsertedValueOperand ( ) -> getType ( ) } ; SmallVector < Value * > Args ; for ( auto & Op : I . operands ( ) ) if ( isa < UndefValue > ( Op ) ) Args . push_back ( UndefValue :: get ( IRB -> getInt32Ty ( ) ) ) ;


<s> const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & ImmOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( ( ImmOp . isImm ( ) || ImmOp . isExpr ( ) ) && <STR_LIT> ) ; if ( ! ImmOp . isImm ( ) ) { expandLoadAddressSym ( DstRegOp , ImmOp , Is32BitImm , IDLoc , Instructions ) ; return false ; } if ( loadImmediate ( ImmOp . getImm ( ) , DstRegOp . getReg ( ) , <STR_LIT> , Is32BitImm , IDLoc , Instructions ) ) return true ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , Subtarget ( STI ) {


<s> void <ISA_LIT>InstPrinter :: printAbsAddrOperand ( MCInst const * MI , unsigned OpNo , raw_ostream & O ) const {


<s> machine_mode dst_inner = ( GET_CODE ( dst ) == SUBREG ? GET_MODE ( XEXP ( dst , <NUM_LIT> ) ) : dst_mode ) ; machine_mode src_inner = ( GET_CODE ( src ) == SUBREG ? GET_MODE ( XEXP ( src , <NUM_LIT> ) ) : dst_mode ) ; rtx sym = src ; if ( GET_CODE ( sym ) == CONST ) sym = XEXP ( XEXP ( sym , <NUM_LIT> ) , <NUM_LIT> ) ; if ( SYMBOL_REF_P ( sym ) ) { if ( SYMBOL_DATA_AREA ( sym ) != DATA_AREA_GENERIC ) return <STR_LIT> ; nvptx_maybe_record_fnsym ( sym ) ; } if ( src_inner == dst_inner ) return <STR_LIT> ; if ( CONSTANT_P ( src ) ) return ( GET_MODE_CLASS ( dst_inner ) == MODE_INT && GET_MODE_CLASS ( src_inner ) != MODE_FLOAT ? <STR_LIT> : <STR_LIT> ) ; if ( GET_MODE_SIZE ( dst_inner ) == GET_MODE_SIZE ( src_inner ) ) return <STR_LIT> ;


<s> else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; }


<s> void <ISA_LIT>TargetStreamer :: emitCantUnwind ( ) {


<s> return __builtin_mve_vmaxq_m_uv4si ( __arm_vuninitializedq_u32 ( ) , __a , __b , __p ) ;


<s> SDValue getNode ( unsigned MachineOpc , const SDLoc & dl , MVT Ty , ArrayRef < SDValue > Ops , SelectionDAG & DAG ) const { SDNode * N = DAG . getMachineNode ( MachineOpc , dl , Ty , Ops ) ; return SDValue ( N , <NUM_LIT> ) ;


<s> int32_t <ISA_LIT>CallingConvHook :: findInRegLastRecord ( StringRef funString ) { uint32_t index = regRecord . size ( ) ; for ( int32_t i = index - <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) {

if ( regRecord [ i ] . fName . compare ( funString ) == <NUM_LIT> ) return i ;


<s> if ( Subtarget -> isThumb1Only ( ) ) return false ; EVT VT ; SDValue Ptr ; bool isSEXTLoad = false ; if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; isSEXTLoad = LD -> getExtensionType ( ) == <STR_LIT> ;

} else if ( StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) {


<s> if ( SVT . getVectorElementType ( ) == <STR_LIT> ) return LowerZERO_EXTEND_Mask ( Op , Subtarget , DAG ) ; if ( Subtarget . hasFp256 ( ) ) if ( SDValue Res = LowerAVXExtend ( Op , DAG , Subtarget ) ) return Res ;

assert ( ! Op . getSimpleValueType ( ) . is256BitVector ( ) || ! SVT . is128BitVector ( ) || Op . getSimpleValueType ( ) . getVectorNumElements ( ) != SVT . getVectorNumElements ( ) ) ;


<s> if ( PHINode * PhiInst = dyn_cast < PHINode > ( & User ) ) return PhiInst -> getIncomingBlock ( OpNo ) -> getTerminator ( ) ; return & User ;


<s> MI -> dump ( ) ; ) ; RegSeqInfo CandidateR<ISA_LIT> ; std :: vector < std :: pair < unsigned , unsigned > > RemapChan ; DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; if ( tryMergeUsingCommonSlot ( R<ISA_LIT> , CandidateR<ISA_LIT> , RemapChan ) ) { RemoveMI ( CandidateR<ISA_LIT> . Instr ) ; MII = RebuildVector ( & R<ISA_LIT> , & CandidateR<ISA_LIT> , RemapChan ) ; trackR<ISA_LIT> ( R<ISA_LIT> ) ; continue ; } DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; RemapChan . clear ( ) ; if ( tryMergeUsingFreeSlot ( R<ISA_LIT> , CandidateR<ISA_LIT> , RemapChan ) ) { RemoveMI ( CandidateR<ISA_LIT> . Instr ) ; MII = RebuildVector ( & R<ISA_LIT> , & CandidateR<ISA_LIT> , RemapChan ) ; trackR<ISA_LIT> ( R<ISA_LIT> ) ;


<s> if ( Base != NewBase && Offset >= <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) ; Base = NewBase ; BaseKill = false ; } AddDefaultT1CC ( BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ; } else { BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ; } Base = NewBase ; BaseKill = true ; } bool isDef = ( isi32Load ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; Opcode = getLoadStoreMultipleOpcode ( Opcode , Mode ) ; if ( ! Opcode ) return false ; bool Writeback = isThumb1 ; if ( Opcode == <STR_LIT> && isThumb1 ) for ( unsigned I = <NUM_LIT> ; I < NumRegs ; ++ I ) if ( Base == Regs [ I ] . first ) { Writeback = false ; break ; } if ( isThumb1 && Writeback && ! BaseKill ) return false ; MachineInstrBuilder MIB ; if ( Writeback ) { if ( Opcode == <STR_LIT> ) Opcode = <STR_LIT> ; MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode ) ) ; MIB . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( BaseKill ) ) ; } else { MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( Opcode ) ) ; MIB . addReg ( Base , getKillRegState ( BaseKill ) ) ; } MIB . addImm ( Pred ) . addReg ( PredReg ) ; for ( unsigned i = <NUM_LIT> ; i != NumRegs ; ++ i ) MIB = MIB . addReg ( Regs [ i ] . first , getDefRegState ( isDef ) | getKillRegState ( Regs [ i ] . second ) ) ; for ( unsigned i = <NUM_LIT> , e = ImpDefs . size ( ) ; i != e ; ++ i ) MIB . addReg ( ImpDefs [ i ] , RegState :: ImplicitDefine ) ;


<s> void <ISA_LIT>AsmPrinter :: LowerPATCHABLE_EVENT_CALL ( const MachineInstr & MI , <ISA_LIT>MCInstLower & MCIL ) { assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; NoAutoPaddingScope NoPadScope ( * OutStreamer ) ; auto CurSled = OutContext . createTempSymbol ( <STR_LIT> , true ) ; OutStreamer -> AddComment ( <STR_LIT> ) ; OutStreamer -> emitCodeAlignment ( <NUM_LIT> , & getSubtargetInfo ( ) ) ; OutStreamer -> emitLabel ( CurSled ) ; OutStreamer -> emitBinaryData ( <STR_LIT> ) ; const Register DestRegs [ ] = { <STR_LIT> , <STR_LIT> } ; bool UsedMask [ ] = { false , false } ; Register SrcRegs [ ] = { <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( auto Op = MCIL . LowerMachineOperand ( & MI , MI . getOperand ( I ) ) ) { assert ( Op -> isReg ( ) && <STR_LIT> ) ; SrcRegs [ I ] = get<ISA_LIT>SubSuperRegister ( Op -> getReg ( ) , <NUM_LIT> ) ; if ( SrcRegs [ I ] != DestRegs [ I ] ) { UsedMask [ I ] = true ; EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) ) ; } else { emit<ISA_LIT>Nops ( * OutStreamer , <NUM_LIT> , Subtarget ) ; } } for ( unsigned I = <NUM_LIT> ; I < MI . getNumOperands ( ) ; ++ I ) if ( SrcRegs [ I ] != DestRegs [ I ] ) EmitAndCountInstruction ( MCInstBuilder ( <STR_LIT> ) . addReg ( DestRegs [ I ] ) . addReg ( SrcRegs [ I ] ) ) ; auto TSym = OutContext . getOrCreateSymbol ( <STR_LIT> ) ; MachineOperand TOp = MachineOperand :: CreateMCSymbol ( TSym ) ;

if ( isPositionIndependent ( ) ) TOp . setTargetFlags ( <STR_LIT> ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createHWRegsReg ( unsigned Index , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser ) { return CreateReg ( Index , RegKind_HWRegs , RegInfo , S , E , Parser ) ;


<s> shouldReplaceInst ( MachineFunction * MF , const MCInstrDesc * InstDesc , SmallVectorImpl < const MCInstrDesc * > & InstDescRepl ) { std :: string Subtarget = std :: string ( SchedModel . getSubtargetInfo ( ) -> getCPU ( ) ) ; auto InstID = std :: make_pair ( InstDesc -> getOpcode ( ) , Subtarget ) ; if ( SIMDInstrTable . find ( InstID ) != SIMDInstrTable . end ( ) ) return SIMDInstrTable [ InstID ] ; unsigned SCIdx = InstDesc -> getSchedClass ( ) ; const MCSchedClassDesc * SCDesc = SchedModel . getMCSchedModel ( ) -> getSchedClassDesc ( SCIdx ) ; const MCSchedClassDesc * SCDescRepl ; if ( ! SCDesc -> isValid ( ) || SCDesc -> isVariant ( ) ) { SIMDInstrTable [ InstID ] = false ; return false ; } for ( auto IDesc : InstDescRepl ) { SCDescRepl = SchedModel . getMCSchedModel ( ) -> getSchedClassDesc ( IDesc -> getSchedClass ( ) ) ; if ( ! SCDescRepl -> isValid ( ) || SCDescRepl -> isVariant ( ) ) { SIMDInstrTable [ InstID ] = false ; return false ; } } unsigned ReplCost = <NUM_LIT> ; for ( auto IDesc : InstDescRepl ) ReplCost += SchedModel . computeInstrLatency ( IDesc -> getOpcode ( ) ) ; if ( SchedModel . computeInstrLatency ( InstDesc -> getOpcode ( ) ) > ReplCost ) { SIMDInstrTable [ InstID ] = true ; return true ;


<s> } } Register PHIRes = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC0 = MRI -> getRegClass ( PHIRes ) ; if ( AllAGPRUses && numVGPRUses && ! TRI -> isAGPRClass ( RC0 ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MRI -> setRegClass ( PHIRes , TRI -> getEquivalentAGPRClass ( RC0 ) ) ; for ( unsigned I = <NUM_LIT> , N = MI . getNumOperands ( ) ; I != N ; I += <NUM_LIT> ) { MachineInstr * DefMI = MRI -> getVRegDef ( MI . getOperand ( I ) . getReg ( ) ) ; if ( DefMI && DefMI -> isPHI ( ) ) PHIOperands . insert ( DefMI ) ; } } bool hasVGPRInput = false ; for ( unsigned i = <NUM_LIT> ; i < MI . getNumOperands ( ) ; i += <NUM_LIT> ) { Register InputReg = MI . getOperand ( i ) . getReg ( ) ; MachineInstr * Def = MRI -> getVRegDef ( InputReg ) ; if ( TRI -> isVectorRegister ( * MRI , InputReg ) ) { if ( Def -> isCopy ( ) ) { Register SrcReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getRegClassForReg ( * MRI , SrcReg ) ; if ( TRI -> isSGPRClass ( RC ) ) continue ; } hasVGPRInput = true ; break ; } else if ( Def -> isCopy ( ) && TRI -> isVectorRegister ( * MRI , Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { Register SrcReg = Def -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * SrcDef = MRI -> getVRegDef ( SrcReg ) ; unsigned SMovOp ; int64_t Imm ; if ( ! isSafeToFoldImmIntoCopy ( Def , SrcDef , TII , SMovOp , Imm ) ) { hasVGPRInput = true ; break ; } else { MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; Def -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( Imm ) ; Def -> addImplicitDefUseOperands ( * MF ) ; Def -> setDesc ( TII -> get ( SMovOp ) ) ; } } } if ( ( ! TRI -> isVectorRegister ( * MRI , PHIRes ) && RC0 != & <STR_LIT> ) && ( hasVGPRInput || numVGPRUses > <NUM_LIT> ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; CreatedBB = TII -> moveToVALU ( MI ) ; }


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Subtarget . hasBWI ( ) && <STR_LIT> ) ; if ( SDValue ZExt = lowerShuffleAsZeroOrAnyExtend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return ZExt ; if ( SDValue V = lowerShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ;

if ( SDValue Shift = lowerShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ;


<s> SDValue Ops [ ] = { Op , DAG . getConstant ( NumBits , dl , VT ) , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Op . getValue ( <NUM_LIT> ) } ; return DAG . getNode ( <STR_LIT> , dl , VT , Ops ) ;


<s> int long_jump = ( get_attr_length ( insn ) >= <NUM_LIT> ) ; int reverse = long_jump || jump_over_one_insn_p ( insn , operands [ <NUM_LIT> ] ) ; if ( comp == GE ) comp = EQ ; else if ( comp == LT ) comp = NE ; if ( reverse ) comp = reverse_condition ( comp ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) { if ( INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> ) { if ( comp == EQ ) output_asm_insn ( AS2 ( sbis , % <NUM_LIT> - <NUM_LIT> , % <NUM_LIT> ) , operands ) ;

else output_asm_insn ( AS2 ( sbic , % <NUM_LIT> - <NUM_LIT> , % <NUM_LIT> ) , operands ) ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & T ) { CodePointerSize = CalleeSaveStackSlotSize = T . isArch64Bit ( ) ? <NUM_LIT> : <NUM_LIT> ; UseDataRegionDirectives = true ; ZeroDirective = <STR_LIT> ; Data8bitsDirective = <STR_LIT> ;


<s> StringRef getPassName ( ) const override {


<s> if ( Offset . getScalable ( ) ) return createDefCFAExpression ( TRI , Reg , Offset ) ; if ( FrameReg == Reg && ! LastAdjustmentWasScalable ) return MCCFIInstruction :: cfiDefCfaOffset ( nullptr , int ( Offset . getFixed ( ) ) ) ; unsigned DwarfReg = TRI . getDwarfRegNum ( Reg , true ) ; return MCCFIInstruction :: cfiDefCfa ( nullptr , DwarfReg , ( int ) Offset . getFixed ( ) ) ;


<s> return ( __m256i ) __builtin_ia32_vpconflictdi_256_mask ( ( __v4di ) __A , ( __v4di ) _mm256_setzero_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> snprintf ( buf , sizeof buf , <STR_LIT> , src -> mode , src -> predicate , src -> constraint ) ; printf ( src -> rtl , buf ) ; fputs ( <STR_LIT> , stdout ) ;


<s> const TargetRegisterClass * UAS :: getChangedRegRC ( unsigned reg , unsigned side ) const { const TargetRegisterClass * RC = MRI . getRegClass ( reg ) ;

if ( RC -> hasSuperClass ( PredRegsRegisterClass ) ) return side ? BPredRegsRegisterClass : APredRegsRegisterClass ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: systemz , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> ) ;


<s> void EmitValueImpl ( const MCExpr * Value , unsigned Size , const SMLoc & Loc ) override { EmitDataMappingSymbol ( ) ; MCELFStreamer :: EmitValueImpl ( Value , Size , Loc ) ;


<s> return STI . getFeatureBits ( ) & <STR_LIT> ;


<s> void initializePass ( ) override { pushTTIStack ( this ) ;


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; if ( ! DisableCTRLoops && getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>CTRLoopsVerify ( ) ) ;

addPass ( create<ISA_LIT>VSXCopyPass ( ) ) ;


<s> else if ( IDVal == <STR_LIT> ) return parseDirectiveAttribute ( ) ; return true ;


<s> if ( is_naked_func ( ) ) { emit_insn ( gen_rtx_CLOBBER ( VOIDmode , GEN_INT ( <NUM_LIT> ) ) ) ; return ; } emit_insn ( gen_prologue_start_marker ( ) ) ; if ( is_critical_func ( ) ) { emit_insn ( gen_push_intr_state ( ) ) ; emit_insn ( gen_disable_interrupts ( ) ) ; } else if ( is_reentrant_func ( ) ) emit_insn ( gen_disable_interrupts ( ) ) ; if ( ! cfun -> machine -> computed ) msp430_compute_frame_info ( ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = cfun -> machine -> framesize ; if ( crtl -> args . pretend_args_size ) { rtx note ; gcc_assert ( crtl -> args . pretend_args_size == <NUM_LIT> ) ; p = emit_insn ( gen_grow_and_swap ( ) ) ; note = F ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_MINUS ( Pmode , stack_pointer_rtx , GEN_INT ( <NUM_LIT> ) ) ) ) ; add_reg_note ( p , REG_FRAME_RELATED_EXPR , note ) ; note = F ( gen_rtx_SET ( gen_rtx_MEM ( Pmode , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> ) ) ) , pc_rtx ) ) ; add_reg_note ( p , REG_CFA_OFFSET , note ) ; F ( p ) ; } for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( cfun -> machine -> need_to_save [ i ] ) { int seq , count ; rtx note ; for ( seq = i - <NUM_LIT> ; seq >= <NUM_LIT> && cfun -> machine -> need_to_save [ seq ] ; seq -- ) ; count = i - seq ; if ( msp430x ) { p = F ( emit_insn ( gen_pushm ( gen_rtx_REG ( Pmode , i ) , GEN_INT ( count ) ) ) ) ; note = gen_rtx_SEQUENCE ( VOIDmode , rtvec_alloc ( count + <NUM_LIT> ) ) ; XVECEXP ( note , <NUM_LIT> , <NUM_LIT> ) = F ( gen_rtx_SET ( stack_pointer_rtx , gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( count * ( TARGET_LARGE ? - <NUM_LIT> : - <NUM_LIT> ) ) ) ) ) ; for ( j = <NUM_LIT> ; j < count ; j ++ ) { rtx addr ; int ofs = ( count - j - <NUM_LIT> ) * ( TARGET_LARGE ? <NUM_LIT> : <NUM_LIT> ) ; if ( ofs ) addr = gen_rtx_PLUS ( Pmode , sp , GEN_INT ( ofs ) ) ; else addr = stack_pointer_rtx ; XVECEXP ( note , <NUM_LIT> , j + <NUM_LIT> ) = F ( gen_rtx_SET ( gen_rtx_MEM ( Pmode , addr ) , gen_rtx_REG ( Pmode , i - j ) ) ) ; } add_reg_note ( p , REG_FRAME_RELATED_EXPR , note ) ; i -= count - <NUM_LIT> ; } else F ( emit_insn ( gen_push ( gen_rtx_REG ( Pmode , i ) ) ) ) ; }

if ( frame_pointer_needed ) F ( emit_move_insn ( gen_rtx_REG ( Pmode , FRAME_POINTER_REGNUM ) , sp ) ) ;


<s> static void concatenateMemOperands ( MachineInstr * MI , MachineInstr * Op0 , MachineInstr * Op1 ) { assert ( MI -> memoperands_empty ( ) && <STR_LIT> ) ;

size_t numMemRefs = ( Op0 -> memoperands_end ( ) - Op0 -> memoperands_begin ( ) ) + ( Op1 -> memoperands_end ( ) - Op1 -> memoperands_begin ( ) ) ;


<s> bool <ISA_LIT>RegisterInfo :: isConstantPhysReg ( unsigned PhysReg ) const { return PhysReg == <STR_LIT> ;


<s> bool hasArchitectedFlatScratch ( ) const { return getFeatureBits ( ) [ <STR_LIT> ] ;


<s> if ( GET_CODE ( op ) == REG ) regnum = REGNO ( op ) ;

else if ( GET_CODE ( op ) == PLUS && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) regnum = REGNO ( XEXP ( op , <NUM_LIT> ) ) ;


<s> getMnemonicAcceptInfo ( StringRef Mnemonic , StringRef FullInst , bool & CanAcceptCarrySet , bool & CanAcceptPredicationCode ) { if ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || ( ! isThumb ( ) && ( Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> || Mnemonic == <STR_LIT> ) ) ) { CanAcceptCarrySet = true ;


<s> } ) ; if ( RepeatedSequenceLocs [ <NUM_LIT> ] . back ( ) -> isTerminator ( ) ) return outliner :: TargetCostInfo ( SequenceSize , <NUM_LIT> , <NUM_LIT> , MachineOutlinerTailCall , MachineOutlinerTailCall ) ; return outliner :: TargetCostInfo ( SequenceSize , <NUM_LIT> , <NUM_LIT> , MachineOutlinerDefault , MachineOutlinerDefault ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectVSplat ( SDValue N , SDValue & SplatVal ) { if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> ) return false ; SplatVal = N . getOperand ( <NUM_LIT> ) ; return true ;


<s> if ( SrcVT == <STR_LIT> && UseSSEReg && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; if ( SrcVT == <STR_LIT> && ( UseSSEReg || VT == <STR_LIT> ) ) { SDValue Ext = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Ext ) ; } if ( VT == <STR_LIT> ) return LowerF128Call ( Op , DAG , RTLIB :: getSINTTOFP ( SrcVT , VT ) ) ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && UseSSEReg && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ;

unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ;


<s> <ISA_LIT>SEInstrInfo :: <ISA_LIT>SEInstrInfo ( const <ISA_LIT>Subtarget & STI ) : <ISA_LIT>InstrInfo ( STI , STI . getRelocationModel ( ) == Reloc :: PIC_ ? <STR_LIT> : <STR_LIT> ) , RI ( STI ) , IsN64 ( STI . isABI_N64 ( ) ) {


<s> else if ( ( from ) == ARG_POINTER_REGNUM ) ( offset ) = ( cfun -> machine -> total_size ) ; else if ( ( from ) == RETURN_ADDRESS_POINTER_REGNUM ) {

if ( leaf_function_p ( ) ) ( offset ) = <NUM_LIT> ;


<s> const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printUnsignedImm8 ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ; void printMemOperandEA ( const MachineInstr * MI , int opNum , raw_ostream & O ) ;

void printFCCOperand ( const MachineInstr * MI , int opNum , raw_ostream & O , const char * Modifier = nullptr ) ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> unsigned Offset = <NUM_LIT> ; for ( MachineBasicBlock & MBB : * MF ) { const Align Alignment = MBB . getAlignment ( ) ; unsigned AlignedOffset ; if ( Alignment == Align ( <NUM_LIT> ) ) AlignedOffset = Offset ;

else AlignedOffset = alignTo ( Offset , Alignment ) ;


<s> if ( Cst && ! isa < GlobalValue > ( Cst ) && ! isa < ConstantExpr > ( Cst ) && AlreadyChecked . insert ( Cst ) . second ) LocalChange |= promoteConstant ( Cst ) ; } } return LocalChange ;


<s> void <ISA_LIT>ParamManager :: addParamName ( std :: string Name , unsigned Index ) {

char * name = ( char * ) malloc ( Name . length ( ) + <NUM_LIT> ) ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const GCNSubtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI , const <ISA_LIT>TargetMachine & TM ) : InstructionSelector ( ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , TM ( TM ) , STI ( STI ) , EnableLateStructurizeCFG ( <ISA_LIT>TargetMachine :: EnableLateStructurizeCFG ) , {


<s> Map . insert ( std :: make_pair ( N , ++ LastNum ) ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {


<s> case <NUM_LIT> : code = <NUM_LIT> ; break ; case <NUM_LIT> : code = <NUM_LIT> ; break ; case <NUM_LIT> : code = <NUM_LIT> ; break ; default : return <NUM_LIT> ; } return __builtin_s390_lcbb ( ptr , code ) ;


<s> return Type :: getIntNPtrTy ( M -> getContext ( ) , M -> getDataLayout ( ) . getPointerSizeInBits ( ) ) ;


<s> unsigned ShiftAmt = SVOp -> getMaskElt ( i ) ; if ( ShiftAmt < i ) return - <NUM_LIT> ; ShiftAmt -= i ; if ( ! isUnary ) { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ShiftAmt + i ) ) return - <NUM_LIT> ; } else { for ( ++ i ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( SVOp -> getMaskElt ( i ) , ( ShiftAmt + i ) & <NUM_LIT> ) ) return - <NUM_LIT> ; }


<s> SDValue <ISA_LIT>TargetLowering :: EmitTailCallLoadRetAddr ( SelectionDAG & DAG , SDValue & OutRetAddr , SDValue Chain , bool IsTailCall , bool Is64Bit , int FPDiff , DebugLoc dl ) { if ( ! IsTailCall || FPDiff == <NUM_LIT> ) return Chain ;


<s> Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Res . setOpcode ( Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : unsigned opcode ; if ( STI . getFeatureBits ( ) [ <STR_LIT> ] ) opcode = Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else opcode = Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Res . setOpcode ( opcode ) ;


if ( GET_MODE_SIZE ( mode ) == <NUM_LIT> && reg_classes_intersect_p ( rclass , ADDR_REGS ) && ! ( INT_REGNO_P ( regno ) || CONSTANT_P ( x ) ) ) return DATA_REGS ;


<s> int64_t ImmVal ; if ( SignedCmp ) ImmVal = ( short ) MO . getImm ( ) ; else ImmVal = MO . getImm ( ) ; const MachineInstr * IV_DefInstr = MRI -> getVRegDef ( IV_Opnd -> getReg ( ) ) ; assert ( L -> contains ( IV_DefInstr -> getParent ( ) ) && <STR_LIT> ) ; int64_t iv_value = ( short ) IV_DefInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( InitialValue -> isReg ( ) && <STR_LIT> ) ; unsigned InitialValueReg = InitialValue -> getReg ( ) ; MachineInstr * DefInstr = MRI -> getVRegDef ( InitialValueReg ) ; if ( DefInstr && ( DefInstr -> getOpcode ( ) == <STR_LIT> || DefInstr -> getOpcode ( ) == <STR_LIT> ) ) { int64_t start = ( short ) DefInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineInstr * DefInstr2 = MRI -> getVRegDef ( DefInstr -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( DefInstr2 && ( DefInstr2 -> getOpcode ( ) == <STR_LIT> || DefInstr2 -> getOpcode ( ) == <STR_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * DefInstr ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * DefInstr2 ) ; start |= int64_t ( short ( DefInstr2 -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) << <NUM_LIT> ; int64_t count = ImmVal - start ; if ( ( count % iv_value ) != <NUM_LIT> ) { return <NUM_LIT> ; } OldInsts . push_back ( DefInstr ) ; OldInsts . push_back ( DefInstr2 ) ; if ( Int64Cmp ) return new CountValue ( count / iv_value ) ; else return new CountValue ( uint32_t ( count / iv_value ) ) ; } } else if ( DefInstr && ( DefInstr -> getOpcode ( ) == <STR_LIT> || DefInstr -> getOpcode ( ) == <STR_LIT> ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * DefInstr ) ; int64_t count = ImmVal - int64_t ( short ( DefInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ;


<s> unsigned decode ( unsigned Code ) const {


<s> return new GCNPassConfig ( this , PM ) ;


<s> <ISA_LIT>TargetMachine & get<ISA_LIT>TargetMachine ( ) const {

return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> case 'H' : mode = HImode ; break ; case 'S' : mode = SImode ; break ; case 'D' : mode = DImode ; break ; default : return <NUM_LIT> ; } switch ( str [ <NUM_LIT> ] ) { case '0' : def = <NUM_LIT> ; break ; case 'F' : def = - <NUM_LIT> ; break ; default : return <NUM_LIT> ; } if ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( part_mode ) ) return <NUM_LIT> ; part = s390_single_part ( GEN_INT ( value ) , mode , part_mode , def ) ; if ( part < <NUM_LIT> ) return <NUM_LIT> ; if ( part_goal != - <NUM_LIT> && part_goal != part ) return <NUM_LIT> ; break ; case 'O' : if ( ! TARGET_EXTIMM ) return <NUM_LIT> ; switch ( str [ <NUM_LIT> ] ) { case 's' : return trunc_int_for_mode ( value , SImode ) == value ; case 'p' : return value == <NUM_LIT> || s390_single_part ( GEN_INT ( value ) , DImode , SImode , <NUM_LIT> ) == <NUM_LIT> ; case 'n' : return value == - <NUM_LIT> || s390_single_part ( GEN_INT ( value ) , DImode , SImode , - <NUM_LIT> ) == <NUM_LIT> ; default : gcc_unreachable ( ) ; } break ;


<s> if ( ! Subtarget -> hasVFP3 ( ) ) return false ; if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ; if ( VT == <STR_LIT> && ! Subtarget -> isFPOnlySP ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ;


<s> return ( to == FRAME_POINTER_REGNUM ) || ! ft32_frame_pointer_required ( ) ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( parseOperand ( Operands , Name ) ) { return true ; } while ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; if ( parseOperand ( Operands , Name ) ) { return true ; } } if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { SMLoc Loc = getLexer ( ) . getLoc ( ) ; return Error ( Loc , <STR_LIT> ) ;


<s> OS . emitIntValue ( <STR_LIT> , <NUM_LIT> ) ; OS . emitInt8 ( <STR_LIT> ) ; OS . emitInt8 ( <NUM_LIT> ) ;


<s> static SDValue PerformXorCombine ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget * Subtarget ) { if ( DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ; if ( Subtarget -> hasCMov ( ) ) { SDValue RV = performIntegerAbsCombine ( N , DAG ) ; if ( RV . getNode ( ) ) return RV ; } if ( ! Subtarget -> hasBMI ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; assert ( Subtarget -> hasBMI ( ) && <STR_LIT> ) ;

SDValue N0 = N -> getOperand ( <NUM_LIT> ) ;


<s> static SDValue performExtendCombine ( SDNode * N , TargetLowering :: DAGCombinerInfo & DCI , SelectionDAG & DAG ) { if ( ! DCI . isBeforeLegalizeOps ( ) && N -> getOpcode ( ) == <STR_LIT> && ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) {

SDNode * ABDNode = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ;


<s> SDLoc DL ( Op ) ; EVT DstTy = Op . getValueType ( ) ; if ( ! IsSigned && ! isIntegerTypeFTOL ( DstTy ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; DstTy = <STR_LIT> ; } assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; if ( Subtarget -> is64Bit ( ) && DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; unsigned Opc ; if ( ! IsSigned && isIntegerTypeFTOL ( DstTy ) ) Opc = <STR_LIT> ; else switch ( DstTy . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> else if ( ( fn_type & ARC_FUNCTION_ILINK2 ) != <NUM_LIT> ) regno = ILINK2_REG ; else gcc_unreachable ( ) ; } else if ( ARC_NORMAL_P ( fn_type ) || ARC_NAKED_P ( fn_type ) ) regno = RETURN_ADDR_REGNUM ; gcc_assert ( regno != <NUM_LIT> ) ;


<s> assert ( PairedRegOp < <NUM_LIT> && <STR_LIT> ) ; unsigned Idx = isPairedLdSt ( MI ) ? PairedRegOp : <NUM_LIT> ;


<s> if ( OpToFold . isImm ( ) && tryConstantFoldOp ( * MRI , TII , UseMI , & OpToFold ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * UseMI << '\n' ) ; NextUse = MRI -> use_begin ( Dst . getReg ( ) ) ; FoldList . clear ( ) ; continue ; } if ( isInlineConstantIfFolded ( TII , * UseMI , OpNo , OpToFold ) ) { foldOperand ( OpToFold , UseMI , OpNo , FoldList , CopiesToReplace ) ; } else { if ( ++ NumLiteralUses == <NUM_LIT> ) { NonInlineUse = & * Use ; NonInlineUseOpNo = OpNo ; } } } if ( NumLiteralUses == <NUM_LIT> ) { MachineInstr * UseMI = NonInlineUse -> getParent ( ) ; foldOperand ( OpToFold , UseMI , NonInlineUseOpNo , FoldList , CopiesToReplace ) ; } } else { for ( MachineRegisterInfo :: use_iterator Use = MRI -> use_begin ( Dst . getReg ( ) ) , E = MRI -> use_end ( ) ; Use != E ; ++ Use ) { MachineInstr * UseMI = Use -> getParent ( ) ; foldOperand ( OpToFold , UseMI , Use . getOperandNo ( ) , FoldList , CopiesToReplace ) ; } } MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; for ( MachineInstr * Copy : CopiesToReplace ) Copy -> addImplicitDefUseOperands ( * MF ) ; for ( FoldCandidate & Fold : FoldList ) { if ( updateOperand ( Fold , * TRI ) ) {


<s> case <STR_LIT> : case <STR_LIT> : return DAG . getNode ( Opc , dl , VT , SrcOp , ShAmt ) ; } } switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue ShOps [ <NUM_LIT> ] ; ShOps [ <NUM_LIT> ] = ShAmt ; ShOps [ <NUM_LIT> ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; ShOps [ <NUM_LIT> ] = DAG . getUNDEF ( <STR_LIT> ) ; ShOps [ <NUM_LIT> ] = DAG . getUNDEF ( <STR_LIT> ) ; ShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & ShOps [ <NUM_LIT> ] , <NUM_LIT> ) ; ShAmt = DAG . getNode ( <STR_LIT> , dl , VT , ShAmt ) ;


<s> RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> if ( ! isPositionIndependent ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( is64Bit ( ) ) setPICStyle ( PICStyles :: RIPRel ) ; else if ( isTargetCOFF ( ) ) setPICStyle ( PICStyles :: None ) ; else if ( isTargetDarwin ( ) ) setPICStyle ( PICStyles :: StubPIC ) ; else if ( isTargetELF ( ) ) setPICStyle ( PICStyles :: GOT ) ; CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ;

auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ;


static unsigned SubRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ;


<s> static inline __ev64_opaque__ __ev_set_ufix32_fs_internal ( __ev64_opaque__ a , float b , uint32_t pos ) { __ev64_opaque__ v ; float other ; other = __ev_get_fs_internal ( a , pos ^ <NUM_LIT> ) ;


<s> MachineInstr * MI = Root . getParent ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; SmallVector < GEPInfo , <NUM_LIT> > AddrInfo ; getAddrModeInfo ( * MI , MRI , AddrInfo ) ; if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ;

const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ;


<s> assert ( Res . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; Results . push_back ( Res . getValue ( <NUM_LIT> ) ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Res = LowerADDSUBSAT ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ; break ; case <STR_LIT> : ReplaceREADCYCLECOUNTER ( N , Results , DAG , Subtarget ) ; return ; case <STR_LIT> : case <STR_LIT> : assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; return ExpandDIV_Windows ( SDValue ( N , <NUM_LIT> ) , DAG , N -> getOpcode ( ) == <STR_LIT> , Results ) ; case <STR_LIT> : ReplaceCMP_SWAP_64Results ( N , Results , DAG ) ; return ; case <STR_LIT> : return ReplaceLongIntrinsic ( N , Results , DAG ) ; case <STR_LIT> : lowerABS ( N , Results , DAG ) ; return ; case <STR_LIT> :


<s> static inline long long load_byte ( void * skb __attribute__ ( ( unused ) ) , unsigned long long off ) { return __builtin_bpf_load_byte ( off ) ;


<s> static __inline unsigned long long sh_media_MPERM_W ( unsigned long long mm , unsigned int mn ) {

typedef float v4hi __attribute__ ( ( mode ( V4HI ) ) ) ;


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ;

if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups ) ;


<s> inline static unsigned makePostOp ( unsigned AluOp ) {

assert ( ! isPreOp ( AluOp ) && <STR_LIT> ) ;


<s> const RegInfo & RI = RegInfos [ R ] ; LaneBitmask RCM = RI . RegClass ? RI . RegClass -> LaneMask : LaneBitmask :: getAll ( ) ; LaneBitmask M = TRI . reverseComposeSubRegIndexLaneMask ( Idx , RR . Mask ) ; return RegisterRef ( R , M & RCM ) ; }


<s> if ( ! DisableLeafProc && isLeafProc ( MF ) ) { SparcMachineFunctionInfo * MFI = MF . getInfo < SparcMachineFunctionInfo > ( ) ; MFI -> setLeafProc ( true ) ;


<s> bool invert = invertFPCondCodeUser ( ( <STR_LIT> ) CC -> getSExtValue ( ) ) ;

return DAG . getNode ( ( invert ? <STR_LIT> : <STR_LIT> ) , DL , True . getValueType ( ) , True , False , Cond ) ;


<s> AssemblerDialect = AsmWriterFlavor ; TextAlignFillValue = <NUM_LIT> ; HasLEB128 = true ; SupportsDebugInformation = true ; ExceptionsType = ExceptionHandling :: DwarfCFI ;

if ( ( T . getOS ( ) == Triple :: OpenBSD || T . getOS ( ) == Triple :: Bitrig ) && T . getArch ( ) == Triple :: x86 ) Data64bitsDirective = <NUM_LIT> ;


<s> switch ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) { case <NUM_LIT> : align = <NUM_LIT> ; break ; case <NUM_LIT> : return MCDisassembler :: Fail ; default : align = <NUM_LIT> << fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; } index = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) inc = <NUM_LIT> ; break ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( align ) ) ; if ( Rm != <NUM_LIT> ) { if ( Rm != <NUM_LIT> ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else Inst . addOperand ( MCOperand :: createReg ( <NUM_LIT> ) ) ; } if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd + <NUM_LIT> * inc , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> unsigned MaxOps ; if ( PartialUnrollingThreshold . getNumOccurrences ( ) > <NUM_LIT> ) { MaxOps = PartialUnrollingThreshold ; } else if ( ST -> isAtom ( ) ) { MaxOps = <NUM_LIT> ; } else if ( ST -> hasFSGSBase ( ) && ST -> hasXOP ( ) ) { MaxOps = <NUM_LIT> ; } else if ( ST -> hasFMA4 ( ) ) { return ; } else if ( ST -> hasAVX ( ) || ST -> hasSSE42 ( ) ) { MaxOps = <NUM_LIT> ; } else if ( ST -> hasSSSE3 ( ) ) { MaxOps = <NUM_LIT> ; } else { return ; } for ( Loop :: block_iterator I = L -> block_begin ( ) , E = L -> block_end ( ) ; I != E ; ++ I ) { BasicBlock * BB = * I ; for ( BasicBlock :: iterator J = BB -> begin ( ) , JE = BB -> end ( ) ; J != JE ; ++ J ) if ( isa < CallInst > ( J ) || isa < InvokeInst > ( J ) ) {


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateCondCode ( <STR_LIT> Code , SMLoc S , SMLoc E , MCContext & Ctx ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_CondCode , Ctx ) ; Op -> CondCode . Code = Code ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> bool isMemOffset ( ) const { return isMem ( ) && Mem . Update == None ;


<s> SDValue SDImm = CurDAG -> getTargetConstant ( Inst . Imm , DL , XLenVT ) ; if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ; else Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ; SrcReg = SDValue ( Result , <NUM_LIT> ) ; } return Result ;


<s> AddMI -> setDesc ( TII -> get ( ( AddMI -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ; AddMI -> getOperand ( <NUM_LIT> ) . setReg ( reg - <STR_LIT> + <STR_LIT> ) ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MachineBasicBlock * getHeader ( ) const override { return Unit -> getHeader ( ) ;


<s> for ( auto U : V . users ( ) ) if ( auto * I = dyn_cast < Instruction > ( U ) ) if ( hasVolatileAccess ( I ) ) return true ;


<s> MCSubtargetInfo * <ISA_LIT>_MC :: create<ISA_LIT>MCSubtargetInfo ( StringRef TT , StringRef CPU , StringRef FS ) { MCSubtargetInfo * X = new MCSubtargetInfo ( ) ; Init<ISA_LIT>MCSubtargetInfo ( X , TT , CPU , FS ) ; return X ;


<s> if ( ( TARGET_SSE && mode == TFmode ) || ( TARGET_80387 && mode == XFmode ) || ( ( TARGET_80387 || TARGET_SSE2 ) && mode == DFmode ) || ( ( TARGET_80387 || TARGET_SSE ) && mode == SFmode ) ) units = GET_MODE_SIZE ( mode ) ; break ; case MODE_COMPLEX_FLOAT : if ( ( TARGET_SSE && mode == TCmode ) || ( TARGET_80387 && mode == XCmode ) || ( ( TARGET_80387 || TARGET_SSE2 ) && mode == DCmode ) || ( ( TARGET_80387 || TARGET_SSE ) && mode == SCmode ) ) units = GET_MODE_SIZE ( mode ) ;


<s> case <NUM_LIT> : { switch ( Cond [ <NUM_LIT> ] . getImm ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : CC = <STR_LIT> ; break ; } if ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; else BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( Cond [ <NUM_LIT> ] . getReg ( ) ) . addImm ( <STR_LIT> ( <NUM_LIT> << Cond [ <NUM_LIT> ] . getImm ( ) , <NUM_LIT> ) ) ; break ; } } unsigned Opc = <NUM_LIT> ; const TargetRegisterClass * RC = nullptr ; bool TryFold = false ; if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; TryFold = true ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; } else if ( MRI . constrainRegClass ( DstReg , & <STR_LIT> ) ) { RC = & <STR_LIT> ; Opc = <STR_LIT> ; } assert ( RC && <STR_LIT> ) ; if ( TryFold ) { unsigned NewVReg = <NUM_LIT> ; unsigned FoldedOpc = canFoldIntoCSel ( MRI , TrueReg , & NewVReg ) ; if ( FoldedOpc ) { CC = <STR_LIT> ( CC ) ; TrueReg = FalseReg ; } else FoldedOpc = canFoldIntoCSel ( MRI , FalseReg , & NewVReg ) ; if ( FoldedOpc ) { FalseReg = NewVReg ; Opc = FoldedOpc ; MRI . clearKillFlags ( NewVReg ) ; }


<s> case 'L' : case 'H' : { const MachineOperand & MO = MI -> getOperand ( OpNo ) ; const MachineFunction & MF = * MI -> getParent ( ) -> getParent ( ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( ! MO . isReg ( ) ) return true ; Register RegNumber = MO . getReg ( ) ; if ( <STR_LIT> . contains ( RegNumber ) ) RegNumber = TRI -> getSubReg ( RegNumber , ExtraCode [ <NUM_LIT> ] == 'L' ? <STR_LIT> : <STR_LIT> ) ; OS << <ISA_LIT>InstPrinter :: getRegisterName ( RegNumber ) ; return false ; } case 'I' : if ( MI -> getOperand ( OpNo ) . isImm ( ) ) OS << <STR_LIT> ; return false ; } } printOperand ( MI , OpNo , OS ) ;


<s> unsigned Opcode = <STR_LIT> ; assert ( MI -> getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; if ( MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) == <STR_LIT> ) { Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_NOTOC ; Opcode = <STR_LIT> ; } const Module * M = MF -> getFunction ( ) . getParent ( ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && ( ( Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! Subtarget -> is<ISA_LIT>64 ( ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ) && <STR_LIT> ) ; if ( Subtarget -> is32BitELFABI ( ) && isPositionIndependent ( ) ) Kind = MCSymbolRefExpr :: VK_PLT ; const MCExpr * TlsRef = MCSymbolRefExpr :: create ( TlsGetAddr , Kind , OutContext ) ; if ( Kind == MCSymbolRefExpr :: VK_PLT && Subtarget -> isSecurePlt ( ) && M -> getPICLevel ( ) == PICLevel :: BigPIC ) TlsRef = MCBinaryExpr :: createAdd ( TlsRef , MCConstantExpr :: create ( <NUM_LIT> , OutContext ) , OutContext ) ; const MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; const GlobalValue * GValue = MO . getGlobal ( ) ; MCSymbol * MOSymbol = getSymbol ( GValue ) ; const MCExpr * SymVar = MCSymbolRefExpr :: create ( MOSymbol , VK , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( Subtarget -> is<ISA_LIT>64 ( ) ? Opcode : ( unsigned ) <STR_LIT> ) . addExpr ( TlsRef ) . addExpr ( SymVar ) ) ;


<s> std :: unique_ptr < ScheduleDAGMutation > createPowerPCMacroFusionDAGMutation ( ) {

return createMacroFusionDAGMutation ( shouldScheduleAdjacent ) ;


<s> rtx mov = gen_movdi ( mem , reg ) ; rtx reg_note = gen_rtx_REG ( DImode , regno_note ) ; rtx cfa_relative_addr = gen_rtx_PLUS ( Pmode , cfa , GEN_INT ( cfa_offset ) ) ; rtx cfa_relative_mem = gen_frame_mem ( DImode , cfa_relative_addr ) ; rtx real = gen_rtx_SET ( cfa_relative_mem , reg_note ) ;

add_reg_note ( mov , REG_CFA_OFFSET , real ) ;


<s> case GE : output_asm_insn ( <STR_LIT> , operands ) ; break ; case GEU : output_asm_insn ( <STR_LIT> , operands ) ; break ; case LE : output_asm_insn ( <STR_LIT> , operands ) ; break ; case LEU : output_asm_insn ( <STR_LIT> , operands ) ; break ; case PLUS : output_asm_insn ( <STR_LIT> , operands ) ; break ; case MINUS : output_asm_insn ( <STR_LIT> , operands ) ; break ; default : gcc_unreachable ( ) ; }

switch ( GET_MODE ( operands [ <NUM_LIT> ] ) ) {


<s> const InstrItineraryData * II = TM -> getInstrItineraryData ( ) ; return new ScoreboardHazardRecognizer ( II , DAG , <STR_LIT> ) ;


<s> static SDValue canonicalizeBitSelect ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( ! VT . isVector ( ) ) return SDValue ( ) ; SDValue N0 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; SDValue N1 = peekThroughBitcasts ( N -> getOperand ( <NUM_LIT> ) ) ; if ( N0 . getOpcode ( ) != <STR_LIT> || N1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; if ( ! ( Subtarget . hasXOP ( ) || ! N0 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) || ! N1 . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) return SDValue ( ) ; APInt UndefElts0 , UndefElts1 ; SmallVector < APInt , <NUM_LIT> > EltBits0 , EltBits1 ; if ( ! getTargetConstantBitsFromNode ( N0 . getOperand ( <NUM_LIT> ) , <NUM_LIT> , UndefElts0 , EltBits0 , false , false ) ) return SDValue ( ) ; if ( ! getTargetConstantBitsFromNode ( N1 . getOperand ( <NUM_LIT> ) , <NUM_LIT> , UndefElts1 , EltBits1 , false , false ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> , e = EltBits0 . size ( ) ; i != e ; ++ i ) {

if ( UndefElts0 [ i ] || UndefElts1 [ i ] ) return SDValue ( ) ;


<s> <ISA_LIT>TargetMachine32 :: <ISA_LIT>TargetMachine32 ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( Chain ) ; std :: vector < EVT > ResTys ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; ResTys . push_back ( <STR_LIT> ) ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; if ( NumVecs == <NUM_LIT> ) ReplaceUses ( SDValue ( N , <NUM_LIT> ) , SuperReg ) ; else for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs + <NUM_LIT> ) , SDValue ( Ld , <NUM_LIT> ) ) ;


<s> SubRegs = <NUM_LIT> ; Spacing = <NUM_LIT> ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) && Subtarget . isFPOnlySP ( ) ) { Opc = <STR_LIT> ; BeginIdx = <STR_LIT> ; SubRegs = <NUM_LIT> ; } else if ( SrcReg == <STR_LIT> ) { copyFromCPSR ( MBB , I , DestReg , KillSrc , Subtarget ) ; return ; } else if ( DestReg == <STR_LIT> ) { copyToCPSR ( MBB , I , SrcReg , KillSrc , Subtarget ) ; return ; } assert ( Opc && <STR_LIT> ) ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; MachineInstrBuilder Mov ; if ( TRI -> regsOverlap ( SrcReg , TRI -> getSubReg ( DestReg , BeginIdx ) ) ) { BeginIdx = BeginIdx + ( ( SubRegs - <NUM_LIT> ) * Spacing ) ; Spacing = - Spacing ; } SmallSet < unsigned , <NUM_LIT> > DstRegs ; for ( unsigned i = <NUM_LIT> ; i != SubRegs ; ++ i ) { unsigned Dst = TRI -> getSubReg ( DestReg , BeginIdx + i * Spacing ) ; unsigned Src = TRI -> getSubReg ( SrcReg , BeginIdx + i * Spacing ) ; assert ( Dst && Src && <STR_LIT> ) ; assert ( ! DstRegs . count ( Src ) && <STR_LIT> ) ; DstRegs . insert ( Dst ) ; Mov = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) , Dst ) . addReg ( Src ) ; if ( Opc == <STR_LIT> ) Mov . addReg ( Src ) ; Mov = AddDefaultPred ( Mov ) ; if ( Opc == <STR_LIT> ) Mov = AddDefaultCC ( Mov ) ;


<s> static int need_to_save ( int regno ) { if ( fixed_regs [ regno ] ) return <NUM_LIT> ; if ( crtl -> calls_eh_return ) return <NUM_LIT> ; if ( regno == FP_REGNO ) return <NUM_LIT> ; if ( cfun -> machine -> is_interrupt && ( ! cfun -> machine -> is_leaf || ( regno == A0_REGNO && m32c_function_needs_enter ( ) ) ) ) return <NUM_LIT> ; if ( df_regs_ever_live_p ( regno ) && ( ! call_used_or_fixed_reg_p ( regno ) || cfun -> machine -> is_interrupt ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> void <ISA_LIT>AsmPrinter :: PrintMemReference ( const MachineInstr * MI , unsigned OpNo , raw_ostream & O , const char * Modifier ) { assert ( isMem ( * MI , OpNo ) && <STR_LIT> ) ; const MachineOperand & Segment = MI -> getOperand ( OpNo + <STR_LIT> ) ; if ( Segment . getReg ( ) ) {

PrintModifiedOperand ( MI , OpNo + <STR_LIT> , O , Modifier ) ;


<s> if ( AddrInfo . empty ( ) || AddrInfo [ <NUM_LIT> ] . SgprParts . size ( ) != <NUM_LIT> ) return None ; const GEPInfo & GEPInfo = AddrInfo [ <NUM_LIT> ] ; unsigned PtrReg = GEPInfo . SgprParts [ <NUM_LIT> ] ; Optional < int64_t > EncodedImm = <STR_LIT> ( STI , GEPInfo . Imm ) ; if ( ! EncodedImm ) return None ; return { {

[ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( PtrReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {


<s> Address = DAG . getNode ( <STR_LIT> , DL , PtrTy , Address , Offset ) ; return DAG . getStore ( ChainIn , DL , Value , Address , MachinePointerInfo ( ) , <NUM_LIT> ) ;


<s> IncomingArgHandler ( MachineIRBuilder & B , MachineRegisterInfo & MRI , CCAssignFn * AssignFn ) : ValueHandler ( B , MRI , AssignFn ) {


<s> getJumpTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ; return <NUM_LIT> ;


<s> O << <STR_LIT> ; printOperand ( MI , OpNo + <NUM_LIT> , O ) ;


<s> } SDValue Load = DAG . getLoad ( MemVT , dl , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getMemOperand ( ) ) ; assert ( Load -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( ExtOpcode , dl , Op . getValueType ( ) , Load ) ; } if ( NumElts <= <NUM_LIT> ) { unsigned NumBitsToLoad = <NUM_LIT> ; MVT TypeToLoad = <STR_LIT> ( NumBitsToLoad ) ; SDValue Load = DAG . getLoad ( TypeToLoad , dl , Ld -> getChain ( ) , Ld -> getBasePtr ( ) , Ld -> getMemOperand ( ) ) ; assert ( Load -> getNumValues ( ) == <NUM_LIT> && <STR_LIT> ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumBitsToLoad ) ; SDValue BitVec = DAG . getBitcast ( MaskVT , Load ) ; if ( NumElts == <NUM_LIT> ) return DAG . getNode ( ExtOpcode , dl , VT , BitVec ) ; MVT ExtVT = <STR_LIT> ( VT . getScalarType ( ) , <NUM_LIT> ) ; SDValue ExtVec = DAG . getNode ( ExtOpcode , dl , ExtVT , BitVec ) ; return DAG . getNode ( <STR_LIT> , dl , VT , ExtVec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( VT == <STR_LIT> && <STR_LIT> ) ;

SmallVector < SDValue , <NUM_LIT> > Chains ;


<s> if ( ! UseGP && GAOpc != <STR_LIT> ) return false ; if ( ConstantSDNode * Const = dyn_cast < ConstantSDNode > ( N1 ) ) { SDValue Addr = N0 . getOperand ( <NUM_LIT> ) ; if ( GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( Addr ) ) { if ( GA -> getOpcode ( ) == <STR_LIT> ) { uint64_t NewOff = GA -> getOffset ( ) + ( uint64_t ) Const -> getSExtValue ( ) ; R = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , SDLoc ( Const ) , N . getValueType ( ) , NewOff ) ; return true ; } } } break ; } case <STR_LIT> :

if ( ! UseGP ) R = N . getOperand ( <NUM_LIT> ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) {

return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> TrackDefUses ( MI , Defs , Uses , TRI ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addImm ( CC ) ; MI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; MachineInstr * LastITMI = MI ; MachineBasicBlock :: iterator InsertPos = MIB . getInstr ( ) ; ++ MBBI ; <STR_LIT> OCC = <STR_LIT> ( CC ) ; unsigned Mask = <NUM_LIT> , Pos = <NUM_LIT> ; if ( ! restrictIT ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; for ( ; MBBI != E && Pos && ( ! MI -> isBranch ( ) && ! MI -> isReturn ( ) ) ; ++ MBBI ) { if ( MBBI -> isDebugInstr ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; Register NPredReg ; <STR_LIT> NCC = getITInstrPredicate ( * NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( ( NCC ^ CC ) & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ClearKillFlags ( MI , Uses ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ;


<s> Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register CarryOut = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register CarryIn = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT Ty = MRI . getType ( Dst ) ; if ( Ty == S8 ) return true ; auto Unmerge = Builder . buildUnmerge ( S8 , Src ) ; SmallVector < Register > Parts ; SmallVector < Register > Defs ; for ( MachineOperand & SrcPart : unmergeDefs ( Unmerge ) ) Defs . push_back ( SrcPart . getReg ( ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) std :: reverse ( Defs . begin ( ) , Defs . end ( ) ) ; Register Carry = CarryIn ; for ( const auto & I : enumerate ( Defs ) ) { Parts . push_back ( MRI . createGenericVirtualRegister ( S8 ) ) ; Register NewCarry = I . index ( ) == Defs . size ( ) - <NUM_LIT> ? CarryOut : MRI . createGenericVirtualRegister ( S1 ) ; Builder . buildInstr ( MI . getOpcode ( ) , { Parts . back ( ) , NewCarry } , { I . value ( ) , Carry } ) ; Carry = NewCarry ; }

if ( MI . getOpcode ( ) == <STR_LIT> ) std :: reverse ( Parts . begin ( ) , Parts . end ( ) ) ;


<s> case <STR_LIT> : ret = <NUM_LIT> ; break ; case <STR_LIT> : ret = <NUM_LIT> ; break ; case <STR_LIT> : ret = <NUM_LIT> ; break ; case <STR_LIT> : ret = <NUM_LIT> ; break ; case <STR_LIT> : ret = <NUM_LIT> ; break ; case <STR_LIT> : ret = <NUM_LIT> ; break ; case <STR_LIT> : ret = <NUM_LIT> ; break ;


<s> bool isSystemPStateFieldWithImm0_1 ( ) const {


<s> bool <ISA_LIT>AIXAsmPrinter :: doFinalization ( Module & M ) { if ( ! MAI -> usesDwarfFileAndLocDirectives ( ) && MMI -> hasDebugInfo ( ) ) OutStreamer -> doFinalizationAtSectionEnd ( OutStreamer -> getContext ( ) . getObjectFileInfo ( ) -> getTextSection ( ) ) ; for ( MCSymbol * Sym : ExtSymSDNodeSymbols ) OutStreamer -> emitSymbolAttribute ( Sym , MCSA_Extern ) ; return <ISA_LIT>AsmPrinter :: doFinalization ( M ) ;


<s> const DataLayout * getDataLayout ( ) const { return & DL ;


<s> SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( Idx ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; EVT VVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( VVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; EVT VVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; SDValue Vec = DAG . getVectorShuffle ( VVT , dl , Op . getOperand ( <NUM_LIT> ) , DAG . getUNDEF ( VVT ) , Mask ) ;


<s> if ( VY != <NUM_LIT> ) return SDValue ( ) ; if ( Opc == <STR_LIT> ) { SDValue Op = DAG . getNode ( <STR_LIT> , dl , VTs . VTs [ <NUM_LIT> ] , { X , Y } ) ; SDValue Ov = DAG . getSetCC ( dl , <STR_LIT> , Op , getZero ( dl , ty ( Op ) , DAG ) , <STR_LIT> ) ; return DAG . getMergeValues ( { Op , Ov } , dl ) ; } if ( Opc == <STR_LIT> ) { SDValue Op = DAG . getNode ( <STR_LIT> , dl , VTs . VTs [ <NUM_LIT> ] , { X , Y } ) ; SDValue Ov = DAG . getSetCC ( dl , <STR_LIT> , Op , DAG . getConstant ( - <NUM_LIT> , dl , ty ( Op ) ) , <STR_LIT> ) ; return DAG . getMergeValues ( { Op , Ov } , dl ) ; }


<s> bool <ISA_LIT>RegisterInfo :: hasBasePointer ( const MachineFunction & MF ) const { return false ;


<s> if ( isFloat && ! Subtarget -> hasVFP2 ( ) ) return false ; unsigned Opc ; bool is64bit = VT == <STR_LIT> || VT == <STR_LIT> ; switch ( ISDOpcode ) { default : return false ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; case <STR_LIT> : Opc = is64bit ? <STR_LIT> : <STR_LIT> ; break ; } unsigned Op1 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op1 == <NUM_LIT> ) return false ; unsigned Op2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( Op2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( Op1 ) . addReg ( Op2 ) ) ;


<s> assert ( QII -> isPostIncrement ( MI ) && <STR_LIT> ) ; DenseMap < unsigned , unsigned > DefRegsSet ; for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) if ( MI -> getOperand ( opNum ) . isReg ( ) && MI -> getOperand ( opNum ) . isDef ( ) ) { DefRegsSet [ MI -> getOperand ( opNum ) . getReg ( ) ] = <NUM_LIT> ; } for ( unsigned opNum = <NUM_LIT> ; opNum < MI -> getNumOperands ( ) ; opNum ++ ) if ( MI -> getOperand ( opNum ) . isReg ( ) && MI -> getOperand ( opNum ) . isUse ( ) ) { if ( DefRegsSet [ MI -> getOperand ( opNum ) . getReg ( ) ] ) { return MI -> getOperand ( opNum ) ; } } if ( MI -> getDesc ( ) . mayLoad ( ) ) { assert ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; return ( MI -> getOperand ( <NUM_LIT> ) ) ; } if ( MI -> getDesc ( ) . mayStore ( ) ) {


<s> if ( TLI -> shouldEmitPCReloc ( GV ) ) { buildPCRelGlobalAddress ( DstReg , Ty , B , GV , <NUM_LIT> , <ISA_LIT>InstrInfo :: MO_REL32 ) ; MI . eraseFromParent ( ) ; return true ; } LLT PtrTy = LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ; Register GOTAddr = MRI . createGenericVirtualRegister ( PtrTy ) ; MachineMemOperand * GOTMMO = MF . getMachineMemOperand ( MachinePointerInfo :: getGOT ( MF ) , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , <NUM_LIT> , <NUM_LIT> ) ; buildPCRelGlobalAddress ( GOTAddr , PtrTy , B , GV , <NUM_LIT> , <ISA_LIT>InstrInfo :: MO_GOTPCREL32 ) ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) { auto Load = B . buildLoad ( PtrTy , GOTAddr , * GOTMMO ) ; B . buildExtract ( DstReg , Load , <NUM_LIT> ) ; } else B . buildLoad ( DstReg , GOTAddr , * GOTMMO ) ;


<s> { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } } ; std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( Tp ) ; int Idx = CostTableLookup < MVT > ( NEONShuffleTbl , array_lengthof ( NEONShuffleTbl ) , <STR_LIT> , LT . second ) ; if ( Idx == - <NUM_LIT> ) return TargetTransformInfo :: getShuffleCost ( Kind , Tp , Index , SubTp ) ;

return LT . first * NEONShuffleTbl [ Idx ] . Cost ;


<s> if ( regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed ) return true ; if ( regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p ( leaf_function ) ) return true ; if ( got_register_rtx && regno == REGNO ( got_register_rtx ) ) return true ;

if ( crtl -> accesses_prior_frames && ( regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM ) ) return true ;


<s> bool <ISA_LIT>PreserveDIType :: runOnFunction ( Function & F ) {

return <ISA_LIT>PreserveDITypeImpl ( F ) ;


<s> assert ( LHSReg && RHSReg && <STR_LIT> ) ; assert ( LHSReg != <STR_LIT> && LHSReg != <STR_LIT> && RHSReg != <STR_LIT> && RHSReg != <STR_LIT> ) ; if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return <NUM_LIT> ; if ( ShiftImm >= <NUM_LIT> ) return <NUM_LIT> ; static const unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Is64Bit = RetVT == <STR_LIT> ; unsigned Opc = OpcTable [ SetFlags ] [ UseAdd ] [ Is64Bit ] ; const TargetRegisterClass * RC = nullptr ; if ( SetFlags ) RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; else RC = Is64Bit ? & <STR_LIT> : & <STR_LIT> ; unsigned ResultReg ; if ( WantResult ) ResultReg = createResultReg ( RC ) ; else ResultReg = Is64Bit ? <STR_LIT> : <STR_LIT> ; const MCInstrDesc & II = TII . get ( Opc ) ;

LHSReg = constrainOperandRegClass ( II , LHSReg , II . getNumDefs ( ) ) ;


<s> Result . setOpcode ( <STR_LIT> ) ; Result . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;


<s> unsigned LOOPi = ( Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ) ;

for ( auto & I : PreHeader . instrs ( ) ) if ( I . getOpcode ( ) == LOOPi ) return & I ;


<s> return __builtin_ia32_cvttss2si64 ( ( __v4sf ) __A ) ;


<s> bool isValidMsgStream ( int64_t MsgId , int64_t OpId , int64_t StreamId , const MCSubtargetInfo & STI , bool Strict ) { assert ( isValidMsgOp ( MsgId , OpId , STI , Strict ) ) ; if ( ! Strict ) return <NUM_LIT> <= StreamId && isUInt < STREAM_ID_WIDTH_ > ( StreamId ) ; if ( ! isGFX11Plus ( STI ) ) { switch ( MsgId ) { case ID_GS_PreGFX11 : return STREAM_ID_FIRST_ <= StreamId && StreamId < STREAM_ID_LAST_ ;


<s> if ( LABEL_P ( insn ) && ( LABEL_PRESERVE_P ( insn ) || bb -> flags & BB_NON_LOCAL_GOTO_TARGET ) ) { bti_insn = aarch_gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { label = as_a < rtx_insn * > ( XEXP ( RTVEC_ELT ( vec , j ) , <NUM_LIT> ) ) ; rtx_insn * next = next_nonnote_nondebug_insn ( label ) ; if ( aarch_bti_j_insn_p ( next ) ) continue ; bti_insn = aarch_gen_bti_j ( ) ; emit_insn_after ( bti_insn , label ) ; } } } if ( CALL_P ( insn ) && ( find_reg_note ( insn , REG_SETJMP , NULL ) ) ) { bti_insn = aarch_gen_bti_j ( ) ; emit_insn_after ( bti_insn , insn ) ; continue ; } } } if ( ! cgraph_node :: get ( cfun -> decl ) -> only_called_directly_p ( ) ) { bb = ENTRY_BLOCK_PTR_FOR_FN ( cfun ) -> next_bb ; insn = BB_HEAD ( bb ) ; if ( ! aarch_pac_insn_p ( get_first_nonnote_insn ( ) ) ) {


<s> initialize<ISA_LIT>TLSDynamicCallPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> if ( MO . isRegMask ( ) ) { const uint32_t * RegMask = MO . getRegMask ( ) ; for ( MCPhysReg Reg : <STR_LIT> ) handleRegMaskClobber ( RegMask , Reg , LOHInfos ) ; for ( MCPhysReg Reg : <STR_LIT> ) handleRegMaskClobber ( RegMask , Reg , LOHInfos ) ; continue ; } if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; int Idx = mapRegToGPRIndex ( MO . getReg ( ) ) ; if ( Idx < <NUM_LIT> ) continue ; handleClobber ( LOHInfos [ Idx ] ) ; } SmallSet < int , <NUM_LIT> > UsesSeen ; for ( const MachineOperand & MO : MI . uses ( ) ) { if ( ! MO . isReg ( ) || ! MO . readsReg ( ) ) continue ; int Idx = mapRegToGPRIndex ( MO . getReg ( ) ) ; if ( Idx < <NUM_LIT> ) continue ; if ( ! UsesSeen . count ( Idx ) ) {

handleUse ( MI , MO , LOHInfos [ Idx ] ) ;


<s> if ( v9_form ) rval = <STR_LIT> ; else rval = <STR_LIT> ; } else { if ( emit_nop ) rval = <STR_LIT> ; else rval = <STR_LIT> ; } return rval ; } if ( v9_form ) strcpy ( string , <STR_LIT> ) ; else strcpy ( string , <STR_LIT> ) ; p = strchr ( string , '\0' ) ; * p ++ = '%' ; * p ++ = 'l' ; * p ++ = '0' ; * p ++ = '%' ; * p ++ = '(' ; * p = '\0' ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) :

<ISA_LIT>Subtarget ( TT , GPU , FS , TM ) , InstrInfo ( * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) , TLInfo ( TM , * this ) {


<s> if ( saved_size > <NUM_LIT> ) { floats_offset += saved_size ; asm_fprintf ( f , <STR_LIT> , IP_REGNUM , FP_REGNUM , floats_offset - vfp_offset ) ; } start_reg = FIRST_VFP_REGNUM ; for ( reg = FIRST_VFP_REGNUM ; reg < LAST_VFP_REGNUM ; reg += <NUM_LIT> ) { if ( ( ! regs_ever_live [ reg ] || call_used_regs [ reg ] ) && ( ! regs_ever_live [ reg + <NUM_LIT> ] || call_used_regs [ reg + <NUM_LIT> ] ) ) { if ( start_reg != reg ) arm_output_fldmx ( f , IP_REGNUM , ( start_reg - FIRST_VFP_REGNUM ) / <NUM_LIT> , ( reg - start_reg ) / <NUM_LIT> ) ; start_reg = reg + <NUM_LIT> ; } } if ( start_reg != reg ) arm_output_fldmx ( f , IP_REGNUM , ( start_reg - FIRST_VFP_REGNUM ) / <NUM_LIT> , ( reg - start_reg ) / <NUM_LIT> ) ; } if ( TARGET_IWMMXT ) { lrm_count += ( lrm_count % <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; for ( reg = LAST_IWMMXT_REGNUM ; reg >= FIRST_IWMMXT_REGNUM ; reg -- ) if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) { asm_fprintf ( f , <STR_LIT> , reg , FP_REGNUM , lrm_count * <NUM_LIT> ) ; lrm_count += <NUM_LIT> ; } } gcc_assert ( saved_regs_mask & ( <NUM_LIT> << IP_REGNUM ) ) ; saved_regs_mask &= ~ ( <NUM_LIT> << IP_REGNUM ) ; saved_regs_mask |= ( <NUM_LIT> << SP_REGNUM ) ; if ( really_return && ARM_FUNC_TYPE ( func_type ) == ARM_FT_NORMAL && ! current_function_calls_eh_return ) saved_regs_mask &= ~ ( <NUM_LIT> << LR_REGNUM ) ; else saved_regs_mask &= ~ ( <NUM_LIT> << PC_REGNUM ) ; if ( offsets -> outgoing_args != ( <NUM_LIT> + ( int ) bit_count ( saved_regs_mask ) ) || current_function_calls_alloca ) asm_fprintf ( f , <STR_LIT> , SP_REGNUM , FP_REGNUM , <NUM_LIT> * bit_count ( saved_regs_mask ) ) ; print_multi_reg ( f , <STR_LIT> , SP_REGNUM , saved_regs_mask ) ; if ( IS_INTERRUPT ( func_type ) ) print_multi_reg ( f , <STR_LIT> , SP_REGNUM , <NUM_LIT> << IP_REGNUM ) ; } else { if ( offsets -> outgoing_args != offsets -> saved_regs ) { operands [ <NUM_LIT> ] = operands [ <NUM_LIT> ] = stack_pointer_rtx ; operands [ <NUM_LIT> ] = GEN_INT ( offsets -> outgoing_args - offsets -> saved_regs ) ; output_add_immediate ( operands ) ; } if ( arm_fpu_arch == FPUTYPE_FPA_EMU2 ) { for ( reg = FIRST_FPA_REGNUM ; reg <= LAST_FPA_REGNUM ; reg ++ ) if ( regs_ever_live [ reg ] && ! call_used_regs [ reg ] ) asm_fprintf ( f , <STR_LIT> , reg , SP_REGNUM ) ;


<s> if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MFI -> CreateFixedObject ( - TailCallReturnAddrDelta , ( - <NUM_LIT> * SlotSize ) + TailCallReturnAddrDelta , true ) ; } if ( hasFP ( MF ) ) { assert ( ( TailCallReturnAddrDelta <= <NUM_LIT> ) && <STR_LIT> ) ;

const TargetFrameInfo & TFI = * MF . getTarget ( ) . getFrameInfo ( ) ;


<s> const MCInstrDesc & InstDesc = get ( MI -> getOpcode ( ) ) ; const MCOperandInfo & OpInfo = InstDesc . OpInfo [ OpIdx ] ; const TargetRegisterClass * DefinedRC = OpInfo . RegClass != - <NUM_LIT> ? RI . getRegClass ( OpInfo . RegClass ) : nullptr ; if ( ! MO ) MO = & MI -> getOperand ( OpIdx ) ; if ( isVALU ( * MI ) && usesConstantBus ( MRI , * MO , DefinedRC -> getSize ( ) ) ) { unsigned SGPRUsed = MO -> isReg ( ) ? MO -> getReg ( ) : ( unsigned ) <STR_LIT> ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i == OpIdx ) continue ; const MachineOperand & Op = MI -> getOperand ( i ) ; if ( Op . isReg ( ) && Op . getReg ( ) != SGPRUsed && usesConstantBus ( MRI , Op , getOpSize ( * MI , i ) ) ) { return false ; } } }


<s> if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Subtarget -> hasMVEIntegerOps ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ) return PerformORCombine_i1 ( N , DCI , Subtarget ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && ( Subtarget -> hasNEON ( ) || Subtarget -> hasMVEIntegerOps ( ) ) && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> || SplatBitSize == <NUM_LIT> ) { EVT VorrVT ; SDValue Val = isVMOVModifiedImm ( SplatBits . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , dl , VorrVT , VT , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VorrVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vorr = DAG . getNode ( <STR_LIT> , dl , VorrVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vorr ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , false , DCI ) ) return Result ; if ( SDValue Result = PerformORCombineToSMULWBT ( N , DCI , Subtarget ) ) return Result ; } SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && N1 . getOpcode ( ) == <STR_LIT> && VT . isVector ( ) && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) { if ( N0 . getOpcode ( ) != <STR_LIT> || ! N0 . hasOneUse ( ) ) return SDValue ( ) ; APInt SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; APInt SplatBits0 , SplatBits1 ; BuildVectorSDNode * BVN0 = dyn_cast < BuildVectorSDNode > ( N0 -> getOperand ( <NUM_LIT> ) ) ; BuildVectorSDNode * BVN1 = dyn_cast < BuildVectorSDNode > ( N1 -> getOperand ( <NUM_LIT> ) ) ; if ( BVN0 && BVN0 -> isConstantSplat ( SplatBits0 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( BVN1 && BVN1 -> isConstantSplat ( SplatBits1 , SplatUndef , SplatBitSize , HasAnyUndefs ) && ! HasAnyUndefs ) { if ( SplatBits0 . getBitWidth ( ) == SplatBits1 . getBitWidth ( ) && SplatBits0 == ~ SplatBits1 ) { EVT CanonicalVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , CanonicalVT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) , N1 -> getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ;

CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ;


<s> if ( Use . getParent ( ) == SourceRegion . BranchBlock ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> <STR_LIT> ) ; SourceRegion . MustMoveDown = true ; } } } for ( MachineBasicBlock :: iterator I = SourceRegion . BranchBlock -> getFirstNonPHI ( ) , E = SourceRegion . BranchBlock -> end ( ) ; I != E ; ++ I ) { if ( ! canMoveToBeginning ( * I , * SourceRegion . BranchTargetBlock ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; SourceRegion . MustMoveUp = true ; } if ( ! canMoveToEnd ( * I , * TargetRegion . BranchBlock ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; SourceRegion . MustMoveDown = true ;


<s> LastMappingSymbols [ getPreviousSection ( ) . first ] = LastEMS ; LastEMS = LastMappingSymbols . lookup ( Section ) ;

MCELFStreamer :: ChangeSection ( Section , Subsection ) ;


<s> SDValue ResNode ; SDValue HiPart ; DebugLoc dl = Op . getDebugLoc ( ) ; bool IsPIC = getTargetMachine ( ) . getRelocationModel ( ) == Reloc :: PIC_ ; unsigned char OpFlag = IsPIC ? <STR_LIT> : <STR_LIT> ; EVT PtrVT = Op . getValueType ( ) ; JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; SDValue JTI = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlag ) ; if ( ! IsPIC ) { SDValue Ops [ ] = { JTI } ; HiPart = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> ) , Ops , <NUM_LIT> ) ; } else HiPart = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , JTI , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; return ResNode ;


<s> uint8_t OpFlagHi = <STR_LIT> ; uint8_t OpFlagLo = <STR_LIT> ; SDValue Hi = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , OpFlagHi ) ; SDValue Lo = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) , Offset , OpFlagLo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi , Lo ) ;


if ( AsmOp -> isImm ( ) ) return Match_ImmediateTooLarge ;


<s> if ( Subtarget . hasStdExtD ( ) ) return Subtarget . hasCheri ( ) ? CSR_XLEN_CLEN_F64_Interrupt_SaveList : CSR_XLEN_F64_Interrupt_SaveList ; if ( Subtarget . hasStdExtF ( ) ) return Subtarget . hasCheri ( ) ? CSR_XLEN_CLEN_F32_Interrupt_SaveList : CSR_XLEN_F32_Interrupt_SaveList ; return Subtarget . hasCheri ( ) ? CSR_XLEN_CLEN_Interrupt_SaveList : CSR_Interrupt_SaveList ; } switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_SaveList ; case <STR_LIT> : case <STR_LIT> :


<s> bool GCNTTIImpl :: isAlwaysUniform ( const Value * V ) const { if ( const IntrinsicInst * Intrinsic = dyn_cast < IntrinsicInst > ( V ) ) { switch ( Intrinsic -> getIntrinsicID ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : return true ; }


return ( __m128i ) __builtin_ia32_cvttps2uqq128_mask ( ( __v4sf ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> return estimated_poly_value ( BITS_PER_SVE_VECTOR ) / <NUM_LIT> ;


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> if ( ! G . hasInitializer ( ) && G . hasExternalLinkage ( ) ) { if ( G . getValueType ( ) -> isSized ( ) ) { uint16_t Size = M . getDataLayout ( ) . getTypeAllocSize ( G . getValueType ( ) ) ; OutStreamer -> emitELFSize ( getSymbol ( & G ) , MCConstantExpr :: create ( Size , OutContext ) ) ; } } } if ( const NamedMDNode * Named = M . getNamedMetadata ( <STR_LIT> ) ) { for ( const Metadata * MD : Named -> operands ( ) ) { const MDTuple * Tuple = dyn_cast < MDTuple > ( MD ) ; if ( ! Tuple || Tuple -> getNumOperands ( ) != <NUM_LIT> ) continue ; const MDString * Name = dyn_cast < MDString > ( Tuple -> getOperand ( <NUM_LIT> ) ) ; const MDString * Contents = dyn_cast < MDString > ( Tuple -> getOperand ( <NUM_LIT> ) ) ; if ( ! Name || ! Contents ) continue ; OutStreamer -> PushSection ( ) ; std :: string SectionName = ( <STR_LIT> + Name -> getString ( ) ) . str ( ) ; MCSectionWasm * mySection = OutContext . getWasmSection ( SectionName , SectionKind :: getMetadata ( ) ) ;

OutStreamer -> SwitchSection ( mySection ) ;


<s> void <ISA_LIT>ModuleInfo :: processModule ( const Module * M , const <ISA_LIT>TargetMachine * mTM ) {


<s> unsigned <ISA_LIT>Subtarget :: getImplicitArgNumBytes ( const Function & F ) const { assert ( <STR_LIT> ( F . getCallingConv ( ) ) ) ; if ( F . hasFnAttribute ( <STR_LIT> ) ) return <NUM_LIT> ; if ( isMesaKernel ( F ) ) return <NUM_LIT> ; unsigned NBytes = ( <STR_LIT> ( ) >= <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;

return <STR_LIT> ( F , <STR_LIT> , NBytes ) ;


<s> BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , getPairHigh ( DestReg ) ) . addReg ( getPairHigh ( SrcReg ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , getPairLow ( DestReg ) ) . addReg ( getPairLow ( SrcReg ) ) ; } else { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , getPairHigh ( DestReg ) ) . addImm ( <NUM_LIT> ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , getPairLow ( DestReg ) ) . addReg ( SrcReg ) ;


<s> vabal_u32 ( uint64x2_t a , uint32x2_t b , uint32x2_t c ) { uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result ;


<s> else if ( Offset == - <NUM_LIT> * ( int ) NumRegs + <NUM_LIT> && haveIBAndDA ) Mode = <STR_LIT> ; else if ( Offset == - <NUM_LIT> * ( int ) NumRegs && isNotVFP ) Mode = <STR_LIT> ; else if ( Offset != <NUM_LIT> ) { if ( ! getLoadStoreMultipleOpcode ( Opcode , Mode ) ) return false ; if ( NumRegs <= <NUM_LIT> ) return false ; unsigned NewBase ; if ( isi32Load ( Opcode ) ) NewBase = Regs [ NumRegs - <NUM_LIT> ] . first ; else { NewBase = Scratch ; if ( NewBase == <NUM_LIT> ) return false ; } int BaseOpc = ! isThumb2 ? <STR_LIT> : <STR_LIT> ; if ( Offset < <NUM_LIT> ) { BaseOpc = ! isThumb2 ? <STR_LIT> : <STR_LIT> ; Offset = - Offset ; } int ImmedOffset = isThumb2 ? <STR_LIT> ( Offset ) : <STR_LIT> ( Offset ) ; if ( ImmedOffset == - <NUM_LIT> ) return false ;

BuildMI ( MBB , MBBI , dl , TII -> get ( BaseOpc ) , NewBase ) . addReg ( Base , getKillRegState ( BaseKill ) ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( <NUM_LIT> ) ;


<s> if ( Shuffle ) { Op = Op . getOperand ( <NUM_LIT> ) ; } else { Shuffle = dyn_cast < ShuffleVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ; Op = Op . getOperand ( <NUM_LIT> ) ; } if ( ! Shuffle || ( Shuffle -> getOperand ( <NUM_LIT> ) != Op ) ) return SDValue ( ) ; for ( int Index = <NUM_LIT> , MaskEnd = <NUM_LIT> << i ; Index < MaskEnd ; ++ Index ) if ( Shuffle -> getMaskElt ( Index ) != MaskEnd + Index ) return SDValue ( ) ; } return Op ;


<s> const auto & TrackedLR = LiveRegs ; if ( ! isEqual ( LISLR , TrackedLR ) ) { dbgs ( ) << <STR_LIT> <STR_LIT> ; printLivesAt ( <ISA_LIT> , LIS , * MRI ) ;

reportMismatch ( LISLR , TrackedLR , MRI -> getTargetRegisterInfo ( ) ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ;


<s> return ( __m128i ) __builtin_ia32_cvtps2qq128_mask ( ( __v4sf ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> getParser ( ) . getStreamer ( ) . EmitGPRel32Value ( Value ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ; return false ;


<s> int Offset = MF . getFrameInfo ( ) -> getObjectOffset ( FrameIndex ) + MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ;

MI . getOperand ( FIOperandNum ) . ChangeToRegister ( <STR_LIT> , false ) ;


<s> return getMatchingLoType ( Asm , First ) != ELF :: R_MIPS_NONE && getMatchingLoType ( Asm , First ) == Second . Type && First . Symbol && First . Symbol == Second . Symbol ;


<s> rtx ind ; if ( strict && ! ( reload_in_progress || reload_completed ) && ( reg_mentioned_p ( frame_pointer_rtx , op ) || reg_mentioned_p ( arg_pointer_rtx , op ) || reg_mentioned_p ( virtual_incoming_args_rtx , op ) || reg_mentioned_p ( virtual_outgoing_args_rtx , op ) || reg_mentioned_p ( virtual_stack_dynamic_rtx , op ) || reg_mentioned_p ( virtual_stack_vars_rtx , op ) ) ) return FALSE ; if ( ! MEM_P ( op ) ) return FALSE ; ind = XEXP ( op , <NUM_LIT> ) ; if ( reload_completed && ( GET_CODE ( ind ) == LABEL_REF || ( GET_CODE ( ind ) == CONST && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) == LABEL_REF && CONST_INT_P ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) ) return TRUE ; if ( REG_P ( ind ) ) return arm_address_register_rtx_p ( ind , <NUM_LIT> ) ; if ( ( type != <NUM_LIT> && GET_CODE ( ind ) == POST_INC ) || ( type == <NUM_LIT> && GET_CODE ( ind ) == PRE_DEC ) ) return arm_address_register_rtx_p ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ; if ( type == <NUM_LIT> && GET_CODE ( ind ) == POST_MODIFY && GET_CODE ( XEXP ( ind , <NUM_LIT> ) ) == PLUS && REG_P ( XEXP ( XEXP ( ind , <NUM_LIT> ) , <NUM_LIT> ) ) ) return true ; if ( type == <NUM_LIT> && GET_CODE ( ind ) == PLUS && REG_P ( XEXP ( ind , <NUM_LIT> ) ) && REG_MODE_OK_FOR_BASE_P ( XEXP ( ind , <NUM_LIT> ) , VOIDmode ) && CONST_INT_P ( XEXP ( ind , <NUM_LIT> ) ) && INTVAL ( XEXP ( ind , <NUM_LIT> ) ) > - <NUM_LIT> && ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) < ( VALID_NEON_QREG_MODE ( GET_MODE ( op ) ) ? <NUM_LIT> : <NUM_LIT> ) ) && ( INTVAL ( XEXP ( ind , <NUM_LIT> ) ) & <NUM_LIT> ) == <NUM_LIT> ) return TRUE ; return FALSE ;


<s> if ( count != <NUM_LIT> ) return const0_rtx ; return get_hard_reg_initial_val ( Pmode , LINK_POINTER_REGNUM ) ;


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc S ; bool Result = true ; while ( getLexer ( ) . getKind ( ) == AsmToken :: LParen ) Parser . Lex ( ) ; switch ( getLexer ( ) . getKind ( ) ) {


<s> static inline const char * getAMSubModeAltStr ( AMSubMode Mode , bool isLD ) { switch ( Mode ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : return isLD ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return isLD ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return isLD ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return isLD ? <STR_LIT> : <STR_LIT> ;


<s> return slice ( insn , <NUM_LIT> , <NUM_LIT> ) ? Offset : - Offset ;


<s> if ( MFI . isLRStoreRequired ( ) ) return Op ; unsigned NumOps = Op . getNumOperands ( ) ; if ( Op . getOperand ( NumOps - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) -- NumOps ; for ( unsigned i = InlineAsm :: Op_FirstOperand ; i != NumOps ; ) { unsigned Flags = cast < ConstantSDNode > ( Op . getOperand ( i ) ) -> getZExtValue ( ) ; unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ; ++ i ; switch ( InlineAsm :: getKind ( Flags ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Kind_RegUse : case InlineAsm :: Kind_Imm : case InlineAsm :: Kind_Mem : i += NumVals ; break ; case InlineAsm :: Kind_Clobber : case InlineAsm :: Kind_RegDef : case InlineAsm :: Kind_RegDefEarlyClobber : { for ( ; NumVals ; -- NumVals , ++ i ) {

Register Reg = cast < RegisterSDNode > ( Op . getOperand ( i ) ) -> getReg ( ) ;


<s> EmitNote ( ElfNote :: NoteNameV2 , DescSZ , ELF :: NT_AMD_<ISA_LIT>_ISA , [ & ] ( MCELFStreamer & OS ) { OS . EmitLabel ( DescBegin ) ; OS . EmitBytes ( IsaVersionString ) ;


<s> Module * M = GV -> getParent ( ) ; LLVMContext & Ctx = M -> getContext ( ) ; if ( ! GV -> isThreadLocal ( ) ) return false ; if ( hasNonInstructionUse ( GV ) || ! GV -> getType ( ) -> isSized ( ) || isZeroLengthArray ( GV -> getType ( ) ) ) return false ; ArrayType * NewType = createLoweredType ( GV -> getType ( ) -> getElementType ( ) ) ; Constant * NewInitializer = createLoweredInitializer ( NewType , GV -> getInitializer ( ) ) ; GlobalVariable * NewGV = new GlobalVariable ( * M , NewType , GV -> isConstant ( ) , GV -> getLinkage ( ) , NewInitializer , <STR_LIT> , <NUM_LIT> , GlobalVariable :: NotThreadLocal , GV -> getType ( ) -> getAddressSpace ( ) , GV -> isExternallyInitialized ( ) ) ; SmallVector < User * , <NUM_LIT> > Users ( GV -> use_begin ( ) , GV -> use_end ( ) ) ; for ( unsigned I = <NUM_LIT> , E = Users . size ( ) ; I != E ; ++ I ) { User * U = Users [ I ] ; Instruction * Inst = cast < Instruction > ( U ) ; IRBuilder < > Builder ( Inst ) ; Function * GetID = <STR_LIT> ( GV -> getParent ( ) , <STR_LIT> ) ;

Value * ThreadID = Builder . CreateCall ( GetID ) ;


<s> return true ; } ; auto FindStartInsertionPoint = [ ] ( MachineInstr * Start , MachineInstr * Dec , MachineBasicBlock :: iterator & InsertPt , MachineBasicBlock * & InsertBB , ReachingDefAnalysis & RDA , InstSet & ToRemove ) { if ( Start -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) { InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } unsigned CountReg = Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto IsMoveLR = [ & CountReg ] ( MachineInstr * MI ) { return MI -> getOpcode ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == CountReg && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <STR_LIT> ; } ; if ( auto * LRDef = RDA . getUniqueReachingMIDef ( Start , <STR_LIT> ) ) { if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { Dec } ; if ( ! TryRemove ( LRDef , RDA , ToRemove , Ignore ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } } MachineBasicBlock * MBB = Start -> getParent ( ) ; if ( auto * LRDef = RDA . getLocalLiveOutMIDef ( MBB , <STR_LIT> ) ) { if ( IsMoveLR ( LRDef ) && RDA . hasSameReachingDef ( Start , LRDef , CountReg ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { Start , Dec } ; if ( ! TryRemove ( LRDef , RDA , ToRemove , Ignore ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( LRDef ) ; InsertBB = LRDef -> getParent ( ) ; return true ; } } if ( ! RDA . isSafeToDefRegAt ( Start , <STR_LIT> ) ) return false ; InsertPt = MachineBasicBlock :: iterator ( Start ) ; InsertBB = Start -> getParent ( ) ; return true ; } ; auto TryAdjustInsertionPoint = [ ] ( MachineBasicBlock :: iterator & InsertPt , MachineInstr * Start , ReachingDefAnalysis & RDA ) { MachineBasicBlock * MBB = InsertPt -> getParent ( ) ; MachineBasicBlock :: iterator FirstNonTerminator = MBB -> getFirstTerminator ( ) ; unsigned CountReg = Start -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( FirstNonTerminator == MBB -> end ( ) ) {

if ( RDA . isReachingDefLiveOut ( Start , CountReg ) && RDA . isReachingDefLiveOut ( Start , <STR_LIT> ) ) InsertPt = FirstNonTerminator ;


<s> const uint8_t ABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;

return new ELF<ISA_LIT>AsmBackend ( T , TT . getTriple ( ) , ABI ) ;


<s> assert ( ContainerVT . isScalableVector ( ) && <STR_LIT> ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ;

SDValue VL = VecVT . isFixedLengthVector ( ) ? DAG . getConstant ( VecVT . getVectorNumElements ( ) , DL , XLenVT ) : DAG . getTargetConstant ( <STR_LIT> , DL , XLenVT ) ;