<s> assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Read2Desc = TII -> get ( Opc ) ; const TargetRegisterClass * SuperRC = ( CI . EltSize == <NUM_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; Register DestReg = MRI -> createVirtualRegister ( SuperRC ) ; DebugLoc DL = CI . I -> getDebugLoc ( ) ; Register BaseReg = AddrReg -> getReg ( ) ; unsigned BaseSubReg = AddrReg -> getSubReg ( ) ; unsigned BaseRegFlags = <NUM_LIT> ; if ( CI . BaseOff ) { Register ImmReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , Paired . I , DL , TII -> get ( <STR_LIT> ) , ImmReg ) . addImm ( CI . BaseOff ) ; BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BaseRegFlags = RegState :: Kill ; TII -> getAddNoCarry ( * MBB , Paired . I , DL , BaseReg ) . addReg ( ImmReg ) . addReg ( AddrReg -> getReg ( ) , <NUM_LIT> , BaseSubReg ) . addImm ( <NUM_LIT> ) ; BaseSubReg = <NUM_LIT> ; } MachineInstrBuilder Read2 = BuildMI ( * MBB , Paired . I , DL , Read2Desc , DestReg ) . addReg ( BaseReg , BaseRegFlags , BaseSubReg ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addImm ( <NUM_LIT> ) . cloneMergedMemRefs ( { & * CI . I , & * Paired . I } ) ; ( void ) Read2 ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1 , CI . InstsToMove ) ; CI . I -> eraseFromParent ( ) ; Paired . I -> eraseFromParent ( ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * Read2 << '\n' ) ;


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ; c = ( __v4sf ) vec_cmplt ( a , b ) ;

return ( ( __m128 ) vec_sel ( ( __v4sf ) __A , c , mask ) ) ;


<s> return __builtin_ia32_rsqrtsh_mask ( __B , __A , _mm_setzero_ph ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> unsigned CPELogAlign = getCPELogAlign ( U . CPEMI ) ; unsigned CPEOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( CPELogAlign ) ; unsigned NextBlockOffset , NextBlockLogAlignment ; MachineFunction :: const_iterator NextBlock = Water -> getIterator ( ) ; if ( ++ NextBlock == MF -> end ( ) ) { NextBlockOffset = BBInfo [ Water -> getNumber ( ) ] . postOffset ( ) ; NextBlockLogAlignment = <NUM_LIT> ; } else { NextBlockOffset = BBInfo [ NextBlock -> getNumber ( ) ] . Offset ; NextBlockLogAlignment = NextBlock -> getLogAlignment ( ) ; } unsigned Size = U . CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPEEnd = CPEOffset + Size ;


<s> uint64_t AvailableFeatures = getAvailableFeatures ( ) ; setAvailableFeatures ( ~ ( uint64_t ) <NUM_LIT> ) ; OperandMatchResultTy ResTy = MatchOperandParserImpl ( Operands , Mnemonic ) ; setAvailableFeatures ( AvailableFeatures ) ; if ( ResTy == MatchOperand_Success ) return false ; if ( ResTy == MatchOperand_ParseFail ) return true ; if ( Parser . getTok ( ) . is ( AsmToken :: Percent ) ) { Register Reg ; if ( parseRegister ( Reg ) ) return true ; Operands . push_back ( <ISA_LIT>Operand :: createInvalid ( Reg . StartLoc , Reg . EndLoc ) ) ; return false ; } SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; Register Reg1 , Reg2 ; bool HaveReg1 , HaveReg2 ; const MCExpr * Expr ;


<s> static bool ShouldRematerialize ( const MachineInstr & Def , AliasAnalysis & AA , const <ISA_LIT>InstrInfo * TII ) { if ( Def . getOpcode ( ) == <STR_LIT> ) return true ; return Def . isAsCheapAsAMove ( ) && TII -> isTriviallyReMaterializable ( Def , & AA ) ;


<s> state = alloca ( state_size ( ) ) ; state_reset ( state ) ; state_transition ( state , insn ) ; for ( unit = <NUM_LIT> ; unit < ARRAY_SIZE ( frv_unit_codes ) ; unit ++ ) if ( cpu_unit_reservation_p ( state , frv_unit_codes [ unit ] ) ) break ; gcc_assert ( unit != ARRAY_SIZE ( frv_unit_codes ) ) ;


<s> static DecodeStatus DecodeThumbBLXOffset ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) {

if ( ! tryAddingSymbolicOperand ( Address , ( Address & ~ <NUM_LIT> ) + SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val << <NUM_LIT> ) ) ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool HasSSE = Subtarget . hasSSE1 ( ) ; bool HasAVX = Subtarget . hasAVX ( ) ; bool HasAVX512 = Subtarget . hasAVX512 ( ) ; bool CallsEHReturn = MF -> getMMI ( ) . callsEHReturn ( ) ; assert ( MF && <STR_LIT> ) ; switch ( MF -> getFunction ( ) -> getCallingConv ( ) ) { case CallingConv :: GHC : case CallingConv :: HiPE : return CSR_NoRegs_SaveList ; case CallingConv :: AnyReg : if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; return CSR_64_AllRegs_SaveList ; case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: <ISA_LIT>_64_Win64 : return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; else return CSR_64_AllRegs_SaveList ; } else { if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ;


<s> default : return NULL ; case <STR_LIT> : return <STR_LIT> ;


<s> return emitConjunctionDisjunctionTreeRec ( DAG , Val , OutCC , false , SDValue ( ) , <STR_LIT> ) ;


<s> unsigned encodeWaitcnt ( const IsaVersion & Version , const Waitcnt & Decoded ) {

return encodeWaitcnt ( Version , Decoded . VmCnt , Decoded . ExpCnt , Decoded . LgkmCnt ) ;


<s> * total = <NUM_LIT> ; return true ; } case CONST : case LABEL_REF : case SYMBOL_REF : if ( TARGET_H8300SX ) { * total = <NUM_LIT> ; return true ; } * total = <NUM_LIT> ; return true ; case CONST_DOUBLE : * total = <NUM_LIT> ; return true ; case COMPARE : if ( XEXP ( x , <NUM_LIT> ) == const0_rtx ) * total = <NUM_LIT> ; return false ; case AND : if ( ! h8300_dst_operand ( XEXP ( x , <NUM_LIT> ) , VOIDmode ) || ! h8300_src_operand ( XEXP ( x , <NUM_LIT> ) , VOIDmode ) ) return false ; * total = COSTS_N_INSNS ( h8300_and_costs ( x ) ) ; return true ; case MOD : case DIV : case UMOD : case UDIV : if ( TARGET_H8300SX ) switch ( GET_MODE ( x ) ) { case QImode : case HImode : * total = COSTS_N_INSNS ( ! speed ? <NUM_LIT> : <NUM_LIT> ) ; return false ; case SImode : * total = COSTS_N_INSNS ( ! speed ? <NUM_LIT> : <NUM_LIT> ) ; return false ; default : break ; } * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT :


<s> Cond [ <NUM_LIT> ] . setImm ( Cond [ <NUM_LIT> ] . getImm ( ) ^ <STR_LIT> ) ;


<s> <STR_LIT> MIbG = getDuplexCandidateGroup ( MIb ) ;

return ( isDuplexPairMatch ( MIaG , MIbG ) || isDuplexPairMatch ( MIbG , MIaG ) ) ;


<s> if ( dest_op_info -> heads [ i ] -> regno != dest_regno ) continue ; head = dest_op_info -> heads [ i ] ; if ( ! head -> first ) head = regrename_chain_from_id ( head -> id ) ; for ( chain = head -> first ; chain ; chain = chain -> next_use ) if ( chain -> insn == insn ) return rename_chain ( insn_info , tag_map , head ) ; } return - <NUM_LIT> ;


<s> static MCInstrAnalysis * create<ISA_LIT>InstrAnalysis ( const MCInstrInfo * Info ) { return new <ISA_LIT>MCInstrAnalysis ( Info ) ;


<s> unsigned NumElems = RegisterWidth / FieldWidth ; MVT ToVT = <STR_LIT> ( <STR_LIT> ( FieldWidth * <NUM_LIT> ) , NumElems / <NUM_LIT> ) ; return ToVT ;


<s> IndexType Index = IndexMap . getIndex ( & In ) ; for ( auto & Op : In . operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isUse ( ) || Op . isUndef ( ) ) continue ; RegisterRef R = { Op . getReg ( ) , Op . getSubReg ( ) } ; if ( TargetRegisterInfo :: isPhysicalRegister ( R . Reg ) && Reserved [ R . Reg ] ) continue ; bool IsKill = Op . isKill ( ) ; for ( auto S : expandToSubRegs ( R , MRI , TRI ) ) { LastUse [ S ] = Index ; if ( IsKill ) closeRange ( S ) ; } } for ( auto & Op : In . operands ( ) ) { if ( ! Op . isReg ( ) || ! Op . isDef ( ) || Op . isUndef ( ) ) continue ; RegisterRef R = { Op . getReg ( ) , Op . getSubReg ( ) } ; if ( TargetRegisterInfo :: isPhysicalRegister ( R . Reg ) && Reserved [ R . Reg ] ) continue ; for ( auto S : expandToSubRegs ( R , MRI , TRI ) ) { if ( LastDef [ S ] != IndexType :: None || LastUse [ S ] != IndexType :: None ) closeRange ( S ) ; LastDef [ S ] = Index ; } } } RegisterSet LiveOnExit ; for ( auto * SB : B . successors ( ) ) for ( auto R : getLiveIns ( * SB ) ) for ( auto S : expandToSubRegs ( R , MRI , TRI ) ) LiveOnExit . insert ( S ) ; for ( auto R : LiveOnExit ) LastUse [ R ] = IndexType :: Exit ; RegisterSet Left ; for ( auto & I : LastUse ) if ( I . second != IndexType :: None ) Left . insert ( I . first ) ;

for ( auto & I : LastDef ) if ( I . second != IndexType :: None ) Left . insert ( I . first ) ;


<s> <ISA_LIT>AsmParser ( const MCSubtargetInfo & _STI , MCAsmParser & _Parser , const MCInstrInfo & MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( Options , _STI ) , Parser ( _Parser ) , MCII ( MII ) , MCB ( <ISA_LIT>MCInstrInfo :: createBundle ( ) ) , InBrackets ( false ) { setAvailableFeatures ( ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ) ; MCAsmParserExtension :: Initialize ( _Parser ) ; Assembler = nullptr ; if ( ! Parser . getStreamer ( ) . hasRawTextSupport ( ) ) { MCELFStreamer * MES = static_cast < MCELFStreamer * > ( & Parser . getStreamer ( ) ) ; Assembler = & MES -> getAssembler ( ) ;


<s> static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , DL , OpLo , OpHi , ShufMask ) ; } if ( ( VT == <STR_LIT> ) && ( InVT == <STR_LIT> ) ) { if ( Subtarget . hasInt256 ( ) ) { In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask1 ) ; In = DAG . getBitcast ( <STR_LIT> , In ) ; static const int ShufMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; In = DAG . getVectorShuffle ( <STR_LIT> , DL , In , In , ShufMask2 ) ; In = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getBitcast ( VT , In ) ; } SDValue OpLo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue OpHi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask1 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; OpLo = DAG . getVectorShuffle ( <STR_LIT> , DL , OpLo , OpLo , ShufMask1 ) ; OpHi = DAG . getVectorShuffle ( <STR_LIT> , DL , OpHi , OpHi , ShufMask1 ) ; OpLo = DAG . getBitcast ( <STR_LIT> , OpLo ) ; OpHi = DAG . getBitcast ( <STR_LIT> , OpHi ) ; static const int ShufMask2 [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; SDValue res = DAG . getVectorShuffle ( <STR_LIT> , DL , OpLo , OpHi , ShufMask2 ) ; return DAG . getBitcast ( <STR_LIT> , res ) ; }

if ( VT == <STR_LIT> && InVT == <STR_LIT> ) {


<s> if ( ! TheTriple . isOSBinFormatELF ( ) ) llvm_unreachable ( <STR_LIT> ) ; return new <ISA_LIT>AsmBackend ( T , TheTriple . getOS ( ) ) ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( <ISA_LIT>32 ) , <ISA_LIT>ABI ( UnknownABI ) , IsLittle ( little ) , IsSingleFloat ( false ) , IsFP64bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , IsLinux ( true ) , HasSEInReg ( false ) , HasCondMov ( false ) , HasSwap ( false ) , HasBitCount ( false ) , HasFPIdx ( false ) , In<ISA_LIT>16Mode ( false ) , In<ISA_LIT>16HardFloat ( <ISA_LIT>16HardFloat ) , InMicro<ISA_LIT>Mode ( false ) , HasDSP ( false ) , HasDSPR2 ( false ) , AllowMixed16_32 ( Mixed16_32 | <ISA_LIT>_Os16 ) , Os16 ( <ISA_LIT>_Os16 ) , RM ( _RM ) , OverrideMode ( NoOverride ) , TM ( _TM ) {


<s> bool hasF16C ( ) const { return HasF16C ;


<s> while ( MI != End ) { if ( MI -> isKill ( ) || MI -> getOpcode ( ) == <STR_LIT> || ( MI -> getOpcode ( ) == <STR_LIT> && ! MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) { MachineBasicBlock :: iterator DeleteMI = MI ; ++ MI ; MBB -> erase ( DeleteMI ) ; End = MBB -> end ( ) ; continue ; } ++ MI ; } } for ( MachineFunction :: iterator MBB = Fn . begin ( ) , MBBe = Fn . end ( ) ; MBB != MBBe ; ++ MBB ) { unsigned RemainingCount = MBB -> size ( ) ; for ( MachineBasicBlock :: iterator RegionEnd = MBB -> end ( ) ; RegionEnd != MBB -> begin ( ) ; ) { MachineBasicBlock :: iterator I = RegionEnd ;

for ( ; I != MBB -> begin ( ) ; -- I , -- RemainingCount ) {


<s> } if ( VCCZCorrupt && readsVCCZ ( * I ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * I << '\n' ) ; insertWait ( MBB , I , LastIssued ) ; BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; } } if ( I -> getOpcode ( ) == <STR_LIT> ) { handleExistingWait ( * I ) ; RemoveMI . push_back ( & * I ) ; continue ; } Counters Required ; if ( ( I -> getOpcode ( ) == <STR_LIT> && ST -> needWaitcntBeforeBarrier ( ) ) || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) Required = LastIssued ; else Required = handleOperands ( * I ) ; Counters Increment = getHwCounts ( * I ) ; if ( countersNonZero ( Required ) || countersNonZero ( Increment ) ) increaseCounters ( Required , DelayedWaitOn ) ; Changes |= insertWait ( MBB , I , Required ) ; pushInstruction ( MBB , I , Increment ) ; handleSendMsg ( MBB , I ) ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) EndPgmBlocks . push_back ( & MBB ) ; } if ( ! hasTrivialSuccessor ( MBB ) ) Changes |= insertWait ( MBB , MBB . getFirstTerminator ( ) , LastIssued ) ; } if ( HaveScalarStores ) { for ( MachineBasicBlock * MBB : EndPgmBlocks ) { bool SeenDCacheWB = false ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ;


<s> if ( IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { if ( ! IsLE ) return false ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> ) ) return false ; } else if ( ShuffleKind == <NUM_LIT> ) { unsigned j = IsLE ? <NUM_LIT> : <NUM_LIT> ;

for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) if ( ! isConstantOrUndef ( N -> getMaskElt ( i ) , i * <NUM_LIT> + j ) || ! isConstantOrUndef ( N -> getMaskElt ( i + <NUM_LIT> ) , i * <NUM_LIT> + j ) ) return false ;


<s> static MachineMemOperand * getFrameIndexMMO ( MachineBasicBlock & MBB , int FrameIndex , MachineMemOperand :: Flags flags ) { MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = * MF -> getFrameInfo ( ) ;

MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , flags , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ;


<s> if ( nready == <NUM_LIT> ) swap_reorder ( ready , nready ) ; else if ( nready > <NUM_LIT> ) qsort ( ready , nready , sizeof ( rtx_insn * ) , rank_for_reorder ) ;


<s> return findOneNVVMAnnotation ( & F , <STR_LIT> , x ) ;


<s> explicit <ISA_LIT>DefineUndef ( ) : BasicBlockPass ( ID ) {


<s> case MachineOperand :: MO_Immediate : return MCOperand :: CreateImm ( MO . getImm ( ) + Offset ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress :

return LowerSymbolOperand ( MO , Offset ) ;


<s> const char * getIdAddr ( ) const override { return & ID ;


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ;


<s> VRI . NumGroups += <NUM_LIT> ; VRI . FirstGroupStartIdx = std :: min ( VRI . FirstGroupStartIdx , BG . StartIdx ) ; } ValueRotsVec . clear ( ) ; for ( auto & I : ValueRots ) { ValueRotsVec . push_back ( I . second ) ; }

llvm :: sort ( ValueRotsVec . begin ( ) , ValueRotsVec . end ( ) ) ;


<s> SDValue Magnitude = DAG . getNode ( <STR_LIT> , DL , IntVT , InvSignMask , getSVESafeBitCast ( IntVT , In1 , DAG ) ) ; SDValue IntResult = DAG . getNode ( <STR_LIT> , DL , IntVT , Sign , Magnitude ) ; return getSVESafeBitCast ( VT , IntResult , DAG ) ; } if ( ! Subtarget -> hasNEON ( ) ) return SDValue ( ) ; if ( SrcVT . bitsLT ( VT ) ) In2 = DAG . getNode ( <STR_LIT> , DL , VT , In2 ) ; else if ( SrcVT . bitsGT ( VT ) ) In2 = DAG . getNode ( <STR_LIT> , DL , VT , In2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; EVT VecVT ; uint64_t EltMask ; SDValue VecVal1 , VecVal2 ; auto setVecVal = [ & ] ( int Idx ) { if ( ! VT . isVector ( ) ) { VecVal1 = DAG . getTargetInsertSubreg ( Idx , DL , VecVT , DAG . getUNDEF ( VecVT ) , In1 ) ; VecVal2 = DAG . getTargetInsertSubreg ( Idx , DL , VecVT , DAG . getUNDEF ( VecVT ) , In2 ) ; } else { VecVal1 = DAG . getNode ( <STR_LIT> , DL , VecVT , In1 ) ; VecVal2 = DAG . getNode ( <STR_LIT> , DL , VecVT , In2 ) ; } } ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EltMask = <NUM_LIT> ; setVecVal ( <STR_LIT> ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = <STR_LIT> ; EltMask = <NUM_LIT> ; setVecVal ( <STR_LIT> ) ; } else if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) { VecVT = ( VT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; EltMask = <NUM_LIT> ;


<s> SDValue RHS = Cmp . getOperand ( <NUM_LIT> ) ; assert ( LHS . getValueType ( ) == RHS . getValueType ( ) && <STR_LIT> ) ; if ( LHS . getValueType ( ) != <STR_LIT> && LHS . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( isNullConstant ( LHS ) ) std :: swap ( LHS , RHS ) ; if ( ! isNullConstant ( RHS ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> || LHS . getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; SDValue BR ; if ( CC == <STR_LIT> ) BR = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Chain , LHS , Dest ) ; else BR = DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> , Chain , LHS , Dest ) ; DCI . CombineTo ( N , BR , false ) ;


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableAtomicTidy ) addPass ( createCFGSimplificationPass ( ) ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) { if ( EnableLoopDataPrefetch ) addPass ( createLoopDataPrefetchPass ( ) ) ; if ( EnableFalkorHWPFFix ) addPass ( createFalkorMarkStridedAccessesPass ( ) ) ; } TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> default : return SDValue ( ) ; } SDValue fence = atomic . getOperand ( <NUM_LIT> ) ; if ( fence . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; switch ( atomic . getOpcode ( ) ) { case <STR_LIT> : return DAG . UpdateNodeOperands ( atomic , fence . getOperand ( <NUM_LIT> ) , atomic . getOperand ( <NUM_LIT> ) , atomic . getOperand ( <NUM_LIT> ) , atomic . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

return DAG . UpdateNodeOperands ( atomic , fence . getOperand ( <NUM_LIT> ) , atomic . getOperand ( <NUM_LIT> ) , atomic . getOperand ( <NUM_LIT> ) ) ;


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( bool is64Bit , const Triple & T ) { NeedsLocalForSize = true ; if ( is64Bit ) { CodePointerSize = CalleeSaveStackSlotSize = <NUM_LIT> ; } IsLittleEndian = T . getArch ( ) == Triple :: ppc64le || T . getArch ( ) == Triple :: ppcle ;


<s> } if ( src_aligned ) emit_move_insn ( reg0 , src ) ; else { emit_insn ( gen_unaligned_loadsi ( low_reg , src ) ) ; src = next_consecutive_mem ( src ) ; emit_insn ( gen_unaligned_loadsi ( hi_reg , src ) ) ; } if ( dst_aligned ) emit_move_insn ( dst , reg0 ) ; else { emit_insn ( gen_unaligned_storesi ( dst , low_reg ) ) ; dst = next_consecutive_mem ( dst ) ; emit_insn ( gen_unaligned_storesi ( dst , hi_reg ) ) ; } src = next_consecutive_mem ( src ) ; dst = next_consecutive_mem ( dst ) ; } gcc_assert ( len < <NUM_LIT> ) ; if ( len >= <NUM_LIT> ) { reg0 = gen_reg_rtx ( SImode ) ; src = adjust_address ( src , SImode , <NUM_LIT> ) ; dst = adjust_address ( dst , SImode , <NUM_LIT> ) ; if ( src_aligned ) emit_move_insn ( reg0 , src ) ; else emit_insn ( gen_unaligned_loadsi ( reg0 , src ) ) ; if ( dst_aligned ) emit_move_insn ( dst , reg0 ) ; else emit_insn ( gen_unaligned_storesi ( dst , reg0 ) ) ; src = next_consecutive_mem ( src ) ; dst = next_consecutive_mem ( dst ) ; len -= <NUM_LIT> ; } if ( len == <NUM_LIT> ) return true ; if ( len >= <NUM_LIT> ) { dst = adjust_address ( dst , HImode , <NUM_LIT> ) ; src = adjust_address ( src , HImode , <NUM_LIT> ) ; reg0 = gen_reg_rtx ( SImode ) ; if ( src_aligned ) emit_insn ( gen_zero_extendhisi2 ( reg0 , src ) ) ; else emit_insn ( gen_unaligned_loadhiu ( reg0 , src ) ) ; if ( dst_aligned ) emit_insn ( gen_movhi ( dst , gen_lowpart ( HImode , reg0 ) ) ) ; else emit_insn ( gen_unaligned_storehi ( dst , gen_lowpart ( HImode , reg0 ) ) ) ; src = next_consecutive_mem ( src ) ; dst = next_consecutive_mem ( dst ) ; if ( len == <NUM_LIT> ) return true ; } dst = adjust_address ( dst , QImode , <NUM_LIT> ) ;

src = adjust_address ( src , QImode , <NUM_LIT> ) ;


<s> if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == <NUM_LIT> ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; if ( ST -> isThumb ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return <NUM_LIT> ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= <NUM_LIT> ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( ) ) , Imm ) ) ) return <NUM_LIT> ; } return getIntImmCost ( Imm , Ty , CostKind ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createQPairNode ( SDValue V0 , SDValue V1 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;

SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;


<s> rtx_code_label * loop_start_label = gen_label_rtx ( ) ; rtx_code_label * loop_end_label = gen_label_rtx ( ) ; rtx_code_label * end_label = gen_label_rtx ( ) ; machine_mode mode ; mode = GET_MODE ( len ) ; if ( mode == VOIDmode ) mode = Pmode ; dst_addr = gen_reg_rtx ( Pmode ) ; src_addr = gen_reg_rtx ( Pmode ) ; count = gen_reg_rtx ( mode ) ; blocks = gen_reg_rtx ( mode ) ; convert_move ( count , len , <NUM_LIT> ) ; emit_cmp_and_jump_insns ( count , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , end_label ) ; emit_move_insn ( dst_addr , force_operand ( XEXP ( dst , <NUM_LIT> ) , NULL_RTX ) ) ; emit_move_insn ( src_addr , force_operand ( XEXP ( src , <NUM_LIT> ) , NULL_RTX ) ) ; dst = change_address ( dst , VOIDmode , dst_addr ) ; src = change_address ( src , VOIDmode , src_addr ) ; temp = expand_binop ( mode , add_optab , count , constm1_rtx , count , <NUM_LIT> , OPTAB_DIRECT ) ; if ( temp != count ) emit_move_insn ( count , temp ) ; temp = expand_binop ( mode , lshr_optab , count , GEN_INT ( <NUM_LIT> ) , blocks , <NUM_LIT> , OPTAB_DIRECT ) ; if ( temp != blocks ) emit_move_insn ( blocks , temp ) ; emit_cmp_and_jump_insns ( blocks , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , loop_end_label ) ; emit_label ( loop_start_label ) ; if ( TARGET_Z10 && ( GET_CODE ( len ) != CONST_INT || INTVAL ( len ) > <NUM_LIT> ) ) { rtx prefetch ; prefetch = gen_prefetch ( gen_rtx_PLUS ( Pmode , src_addr , GEN_INT ( <NUM_LIT> ) ) , const0_rtx , const0_rtx ) ; PREFETCH_SCHEDULE_BARRIER_P ( prefetch ) = true ; emit_insn ( prefetch ) ; prefetch = gen_prefetch ( gen_rtx_PLUS ( Pmode , dst_addr , GEN_INT ( <NUM_LIT> ) ) , const1_rtx , const0_rtx ) ; PREFETCH_SCHEDULE_BARRIER_P ( prefetch ) = true ; emit_insn ( prefetch ) ; } emit_insn ( gen_cpymem_short ( dst , src , GEN_INT ( <NUM_LIT> ) ) ) ; s390_load_address ( dst_addr , gen_rtx_PLUS ( Pmode , dst_addr , GEN_INT ( <NUM_LIT> ) ) ) ; s390_load_address ( src_addr , gen_rtx_PLUS ( Pmode , src_addr , GEN_INT ( <NUM_LIT> ) ) ) ; temp = expand_binop ( mode , add_optab , blocks , constm1_rtx , blocks , <NUM_LIT> , OPTAB_DIRECT ) ; if ( temp != blocks ) emit_move_insn ( blocks , temp ) ; emit_cmp_and_jump_insns ( blocks , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , loop_end_label ) ; emit_jump ( loop_start_label ) ; emit_label ( loop_end_label ) ; emit_insn ( gen_cpymem_short ( dst , src , convert_to_mode ( Pmode , count , <NUM_LIT> ) ) ) ; emit_label ( end_label ) ; } return true ;


return AsmFlavor != Unset ? unsigned ( AsmFlavor ) : <NUM_LIT> ;


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & MF ) const { return true ;


<s> if ( isFullNopInstr ( MI ) ) return false ; if ( MI . isBundle ( ) ) { const MachineBasicBlock * MBB = MI . getParent ( ) ; auto MII = MI . getIterator ( ) ;

for ( ++ MII ; MII != MBB -> instr_end ( ) && MII -> isInsideBundle ( ) ; ++ MII ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , DataLayout ( <STR_LIT> ) , FrameLowering ( Subtarget ) , Subtarget ( TT , CPU , FS ) , TLInfo ( * this ) , TSInfo ( * this ) {


if ( NoCalleeSaveRestore ) StackRestoreBytes += ArgumentPopSize ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; AtomicOrdering FenceOrdering = static_cast < AtomicOrdering > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; SynchronizationScope FenceScope = static_cast < SynchronizationScope > ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; if ( FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread ) { if ( Subtarget -> hasXMMInt ( ) || Subtarget -> is64Bit ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;

SDValue Chain = Op . getOperand ( <NUM_LIT> ) ;


<s> if ( REGNO ( base ) == REGNO ( operands [ <NUM_LIT> ] ) ) reversed = true ; dead = true ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == REG && GET_CODE ( operands [ <NUM_LIT> ] ) == REG && REGNO ( operands [ <NUM_LIT> ] ) == REGNO ( operands [ <NUM_LIT> ] ) + <NUM_LIT> ) reversed = true ; fixup [ <NUM_LIT> ] = ia64_split_tmode ( in , operands [ <NUM_LIT> ] , reversed , dead ) ; fixup [ <NUM_LIT> ] = ia64_split_tmode ( out , operands [ <NUM_LIT> ] , reversed , dead ) ; if ( GET_CODE ( EXP ) == MEM \ && ( GET_CODE ( XEXP ( EXP , <NUM_LIT> ) ) == POST_MODIFY \ || GET_CODE ( XEXP ( EXP , <NUM_LIT> ) ) == POST_INC \ || GET_CODE ( XEXP ( EXP , <NUM_LIT> ) ) == POST_DEC ) ) \ REG_NOTES ( INSN ) = gen_rtx_EXPR_LIST ( REG_INC , \ XEXP ( XEXP ( EXP , <NUM_LIT> ) , <NUM_LIT> ) , \ REG_NOTES ( INSN ) ) insn = emit_insn ( gen_rtx_SET ( VOIDmode , out [ <NUM_LIT> ] , in [ <NUM_LIT> ] ) ) ;

MAYBE_ADD_REG_INC_NOTE ( insn , in [ <NUM_LIT> ] ) ;


<s> static DecodeStatus DecodeMSA128Mem ( MCInst & Inst , unsigned Insn , uint64_t Address , const MCDisassembler * Decoder ) { int Offset = SignExtend32 < <NUM_LIT> > ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ) ; unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; switch ( Inst . getOpcode ( ) ) { default : assert ( false && <STR_LIT> ) ; return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createImm ( Offset * <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createImm ( Offset * <NUM_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : Inst . addOperand ( MCOperand :: createImm ( Offset * <NUM_LIT> ) ) ; break ; }


<s> bool <ISA_LIT>InstrInfo :: isFloat ( const MachineInstr * MI ) const { unsigned Opcode = MI -> getOpcode ( ) ;

const uint64_t F = get ( Opcode ) . TSFlags ;


<s> bool HasAlloca = MFI . hasVarSizedObjects ( ) ; bool NeedsAlign = ( MFI . getMaxAlign ( ) > getStackAlign ( ) ) ; if ( ! HasAlloca || ! NeedsAlign ) return ; SmallSet < int , <NUM_LIT> > DealignSlots ; unsigned LFS = MFI . getLocalFrameSize ( ) ; for ( int i = <NUM_LIT> , e = MFI . getObjectIndexEnd ( ) ; i != e ; ++ i ) { if ( ! MFI . isSpillSlotObjectIndex ( i ) || MFI . isDeadObjectIndex ( i ) ) continue ; unsigned S = MFI . getObjectSize ( i ) ; unsigned A = std :: max ( MFI . getObjectAlignment ( i ) , <NUM_LIT> ) ; MFI . setObjectAlignment ( i , <NUM_LIT> ) ; LFS = alignTo ( LFS + S , A ) ; MFI . mapLocalFrameObject ( i , - static_cast < int64_t > ( LFS ) ) ; DealignSlots . insert ( i ) ; } MFI . setLocalFrameSize ( LFS ) ; Align A = MFI . getLocalFrameMaxAlign ( ) ; assert ( A <= <NUM_LIT> && <STR_LIT> ) ; if ( A == <NUM_LIT> ) MFI . setLocalFrameMaxAlign ( Align ( <NUM_LIT> ) ) ; MFI . setUseLocalStackAllocationBlock ( true ) ; if ( ! DealignSlots . empty ( ) ) { for ( MachineBasicBlock & BB : MF ) { for ( MachineInstr & MI : BB ) { bool KeepOld = true ; ArrayRef < MachineMemOperand * > memops = MI . memoperands ( ) ; SmallVector < MachineMemOperand * , <NUM_LIT> > new_memops ; for ( MachineMemOperand * MMO : memops ) { auto * PV = MMO -> getPseudoValue ( ) ; if ( auto * FS = dyn_cast_or_null < FixedStackPseudoSourceValue > ( PV ) ) { int FI = FS -> getFrameIndex ( ) ; if ( DealignSlots . count ( FI ) ) { unsigned A = MFI . getObjectAlignment ( FI ) ; auto * NewMMO = MF . getMachineMemOperand ( MMO -> getPointerInfo ( ) , MMO -> getFlags ( ) , MMO -> getSize ( ) , A , MMO -> getAAInfo ( ) , MMO -> getRanges ( ) , MMO -> getSyncScopeID ( ) , MMO -> getOrdering ( ) , MMO -> getFailureOrdering ( ) ) ; new_memops . push_back ( NewMMO ) ; KeepOld = false ; continue ; } } new_memops . push_back ( MMO ) ; } if ( ! KeepOld ) MI . setMemRefs ( MF , new_memops ) ; } } } unsigned AP = <NUM_LIT> ; if ( const MachineInstr * AI = getAlignaInstr ( MF ) ) AP = AI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto & HMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; HMFI . setStackAlignBasePhysReg ( AP ) ;


<s> remove ( header_path ) ; remove ( init_path ) ; remove ( defines_path ) ;


Out . wavefront_sgpr_count = CurrentProgramInfo . NumSGPR ;


<s> static unsigned char * unw_decode_p1 ( unsigned char * dp , unsigned char code , void * arg ) { unsigned char brmask = ( code & <NUM_LIT> ) ; UNW_DEC_BR_MEM ( P1 , brmask , arg ) ; return dp ;


if ( ! DisableLoadStoreVectorizer ) addPass ( createLoadStoreVectorizerPass ( ) ) ;


<s> DECL_USER_ALIGN ( f_args ) = <NUM_LIT> ; DECL_FIELD_CONTEXT ( f_skip ) = record ; SET_DECL_ALIGN ( f_skip , <NUM_LIT> ) ; DECL_USER_ALIGN ( f_skip ) = <NUM_LIT> ; TYPE_STUB_DECL ( record ) = type_decl ; TYPE_NAME ( record ) = type_decl ; TYPE_FIELDS ( record ) = f_args ; DECL_CHAIN ( f_args ) = f_skip ; owp = warn_padded ; warn_padded = false ; layout_type ( record ) ;


<s> return Mod . Spelling == Name ; } ) ; if ( Modifier != std :: end ( ModifierNames ) ) { return Modifier -> VariantKind ; }


<s> Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> tree ftype = NULL ; tree fndecl = NULL ; d -> fcode = fcode ; int op_num = insn_data [ d -> code ] . n_operands - <NUM_LIT> ; int arg_num = d -> qualifiers [ <NUM_LIT> ] & qualifier_void ? op_num + <NUM_LIT> : op_num ; tree return_type = void_type_node , args = void_list_node ; tree eltype ; for ( ; op_num >= <NUM_LIT> ; arg_num -- , op_num -- ) { machine_mode op_mode = insn_data [ d -> code ] . operand [ op_num ] . mode ; enum aarch64_type_qualifiers qualifiers = d -> qualifiers [ arg_num ] ; if ( qualifiers & qualifier_unsigned ) { type_signature [ op_num ] = 'u' ; print_type_signature_p = true ; } else if ( qualifiers & qualifier_poly ) { type_signature [ op_num ] = 'p' ; print_type_signature_p = true ; } else type_signature [ op_num ] = 's' ; if ( qualifiers & qualifier_internal ) continue ; if ( qualifiers & qualifier_map_mode ) op_mode = d -> mode ; if ( qualifiers & qualifier_pointer && VECTOR_MODE_P ( op_mode ) ) op_mode = GET_MODE_INNER ( op_mode ) ; eltype = aarch64_simd_builtin_type ( op_mode , ( qualifiers & qualifier_unsigned ) != <NUM_LIT> , ( qualifiers & qualifier_poly ) != <NUM_LIT> ) ; gcc_assert ( eltype != NULL ) ; if ( qualifiers & qualifier_const ) eltype = build_qualified_type ( eltype , TYPE_QUAL_CONST ) ; if ( qualifiers & qualifier_pointer ) eltype = build_pointer_type ( eltype ) ; if ( arg_num == <NUM_LIT> ) return_type = eltype ; else args = tree_cons ( NULL_TREE , eltype , args ) ;


<s> const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned Reg = MO1 . getReg ( ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) ; O << TRI -> getAsmName ( Reg ) ; O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO2 . getImm ( ) ) ) << <STR_LIT> ; assert ( MO2 . isImm ( ) && <STR_LIT> ) ; O << <STR_LIT> << <STR_LIT> ( MO2 . getImm ( ) ) ;


<s> <STR_LIT> :: OFFSET_SRC_PRIVATE_BASE ; unsigned WidthM1 = AS == <ISA_LIT>AS :: LOCAL_ADDRESS ? <STR_LIT> :: WIDTH_M1_SRC_SHARED_BASE : <STR_LIT> :: WIDTH_M1_SRC_PRIVATE_BASE ; unsigned Encoding = <STR_LIT> :: ID_MEM_BASES << <STR_LIT> :: ID_SHIFT_ | Offset << <STR_LIT> :: OFFSET_SHIFT_ | WidthM1 << <STR_LIT> :: WIDTH_M1_SHIFT_ ; SDValue EncodingImm = DAG . getTargetConstant ( Encoding , DL , <STR_LIT> ) ; SDValue ApertureReg = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , <STR_LIT> , EncodingImm ) , <NUM_LIT> ) ; SDValue ShiftAmount = DAG . getTargetConstant ( WidthM1 + <NUM_LIT> , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ApertureReg , ShiftAmount ) ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * Info = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; Register UserSGPR = Info -> getQueuePtrUserSGPR ( ) ; assert ( UserSGPR != <STR_LIT> ) ; SDValue QueuePtr = CreateLiveInRegister ( DAG , & <STR_LIT> , UserSGPR , <STR_LIT> ) ; uint32_t StructOffset = ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Ptr = DAG . getObjectPtrOffset ( DL , QueuePtr , TypeSize :: Fixed ( StructOffset ) ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: CONSTANT_ADDRESS ) ;

return DAG . getLoad ( <STR_LIT> , DL , QueuePtr . getValue ( <NUM_LIT> ) , Ptr , PtrInfo , commonAlignment ( Align ( <NUM_LIT> ) , StructOffset ) , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = QFPRegDecoderTable [ RegNo ] ;

if ( Reg == ~ <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> for ( int M : Mask ) if ( ! isUndefOrInRange ( M , Low , Hi ) ) return false ; return true ;


<s> if ( Idx == <NUM_LIT> ) return <NUM_LIT> * TTI :: TCC_Basic ; return TTI :: TCC_Free ; case Instruction :: Store : ImmIdx = <NUM_LIT> ; break ; case Instruction :: ICmp : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> ) { uint64_t ImmVal = Imm . getZExtValue ( ) ; if ( ImmVal == <NUM_LIT> || ImmVal == <NUM_LIT> ) return TTI :: TCC_Free ; } ImmIdx = <NUM_LIT> ; break ; case Instruction :: And : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> && isUInt < <NUM_LIT> > ( Imm . getZExtValue ( ) ) ) return TTI :: TCC_Free ; ImmIdx = <NUM_LIT> ; break ; case Instruction :: Add : case Instruction :: Sub : if ( Idx == <NUM_LIT> && Imm . getBitWidth ( ) == <NUM_LIT> && Imm . getZExtValue ( ) == <NUM_LIT> ) return TTI :: TCC_Free ; ImmIdx = <NUM_LIT> ; break ; case Instruction :: UDiv : case Instruction :: SDiv : case Instruction :: URem : case Instruction :: SRem : return TTI :: TCC_Free ; case Instruction :: Mul : case Instruction :: Or : case Instruction :: Xor : ImmIdx = <NUM_LIT> ; break ; case Instruction :: Shl : case Instruction :: LShr : case Instruction :: AShr : if ( Idx == <NUM_LIT> ) return TTI :: TCC_Free ; break ; case Instruction :: Trunc : case Instruction :: ZExt : case Instruction :: SExt : case Instruction :: IntToPtr : case Instruction :: PtrToInt : case Instruction :: BitCast :


<s> rtx sp = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; rtx limit = gen_reg_rtx ( Pmode ) ; rtx requested = gen_reg_rtx ( Pmode ) ; rtx cmp = gen_reg_rtx ( CCUNSmode ) ; rtx jump ; emit_insn ( gen_load_split_stack_limit ( limit ) ) ; if ( CONST_INT_P ( size ) ) emit_insn ( gen_add3_insn ( requested , sp , GEN_INT ( - INTVAL ( size ) ) ) ) ; else { size = force_reg ( Pmode , size ) ; emit_move_insn ( requested , gen_rtx_MINUS ( Pmode , sp , size ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ShrinkInstructionsPass ( ) {

return new <ISA_LIT>ShrinkInstructions ( ) ;


<s> static bool isLD ( InsnType insn ) { return ( getBit ( insn , <NUM_LIT> ) == <NUM_LIT> ) ;


<s> if ( ! TYPE_NO_NAMED_ARGS_STDARG_P ( TREE_TYPE ( current_function_decl ) ) ) named_parm_regs = ( sh_round_reg ( * get_cumulative_args ( ca ) , arg . mode ) + CEIL ( arg . promoted_size_in_bytes ( ) , UNITS_PER_WORD ) ) ; anon_parm_regs = NPARM_REGS ( SImode ) - named_parm_regs ; if ( anon_parm_regs > <NUM_LIT> ) * pretend_arg_size = anon_parm_regs * <NUM_LIT> ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , OptForSize ( false ) {


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {


return ( __m512i ) __builtin_ia32_vpopcountb_v64qi_mask ( ( __v64qi ) __A , ( __v64qi ) _mm512_setzero_si512 ( ) , ( __mmask64 ) __U ) ;


<s> if ( Match [ I ] == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfoIgnore ; } Op . setTokenValue ( Base ) ; unsigned NumSuccessfulMatches = std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Success ) ; if ( NumSuccessfulMatches == <NUM_LIT> ) { Inst . setLoc ( IDLoc ) ; if ( ! MatchingInlineAsm ) EmitInstruction ( Inst , Operands , Out ) ; Opcode = Inst . getOpcode ( ) ; return false ; } if ( NumSuccessfulMatches > <NUM_LIT> ) { char MatchChars [ <NUM_LIT> ] ; unsigned NumMatches = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( Match ) ; I != E ; ++ I ) if ( Match [ I ] == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ I ] ; SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumMatches ; ++ i ) { if ( i != <NUM_LIT> ) OS << <STR_LIT> ; if ( i + <NUM_LIT> == NumMatches ) OS << <STR_LIT> ; OS << <STR_LIT> << Base << MatchChars [ i ] << <STR_LIT> ; } OS << <STR_LIT> ; Error ( IDLoc , OS . str ( ) , EmptyRanges , MatchingInlineAsm ) ; return true ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MnemonicFail ) == <NUM_LIT> ) { if ( ! WasOriginallyInvalidOperand ) {

ArrayRef < SMRange > Ranges = MatchingInlineAsm ? EmptyRanges : Op . getLocRange ( ) ;


<s> IntegerType * ByteTy = Type :: getInt8Ty ( F . getContext ( ) ) ; if ( ElemCount == <NUM_LIT> ) return ByteTy ;

return VectorType :: get ( ByteTy , ElemCount , false ) ;


<s> if ( Signed && isPow2Splat ( Op . getOperand ( <NUM_LIT> ) , SplatVal , Negated ) ) { SDValue Pg = getPredicateForScalableVector ( DAG , dl , VT ) ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , VT , Pg , Op -> getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( Log2_64 ( SplatVal ) , dl , <STR_LIT> ) ) ; if ( Negated ) Res = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getConstant ( <NUM_LIT> , dl , VT ) , Res ) ; return Res ; } if ( VT == <STR_LIT> || VT == <STR_LIT> ) return LowerToPredicatedOp ( Op , DAG , PredOpcode ) ; EVT WidenedVT ; if ( VT == <STR_LIT> ) WidenedVT = <STR_LIT> ; else if ( VT == <STR_LIT> ) WidenedVT = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned UnpkLo = Signed ? <STR_LIT> : <STR_LIT> ; unsigned UnpkHi = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Op0Lo = DAG . getNode ( UnpkLo , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1Lo = DAG . getNode ( UnpkLo , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op0Hi = DAG . getNode ( UnpkHi , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Op1Hi = DAG . getNode ( UnpkHi , dl , WidenedVT , Op . getOperand ( <NUM_LIT> ) ) ;

SDValue ResultLo = DAG . getNode ( Op . getOpcode ( ) , dl , WidenedVT , Op0Lo , Op1Lo ) ;


<s> unsigned getWAReg ( unsigned VReg ) const {

auto I = TargetRegisterInfo :: virtReg2Index ( VReg ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) , Subtarget ( TT , CPU , FS , * this ) { initAsmInfo ( ) ;


<s> return sparc_function_arg_1 ( cum , mode , type , named , false ) ;


<s> void <ISA_LIT>Section :: anchor ( ) {


<s> * len = <NUM_LIT> ; return ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> ) ; case <NUM_LIT> : * len = <NUM_LIT> ; return ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> ) ; default : if ( INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> ) break ; case <NUM_LIT> : * len = <NUM_LIT> ; return ( <STR_LIT> CR_TAB <STR_LIT> ) ; } } else if ( CONSTANT_P ( operands [ <NUM_LIT> ] ) ) fatal_insn ( <STR_LIT> , insn ) ; out_shift_with_cnt ( <STR_LIT> , insn , operands , len , <NUM_LIT> ) ;


<s> assert ( Op . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( isSingleInputShuffleMask ( Mask ) ) { if ( SDValue Broadcast = lowerVectorShuffleAsBroadcast ( <STR_LIT> , DL , V1 , Mask , Subtarget , DAG ) ) return Broadcast ; V1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; int WidenedMask [ <NUM_LIT> ] = { std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> , std :: max ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) * <NUM_LIT> + <NUM_LIT> } ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( WidenedMask , DAG ) ) ) ; } if ( SDValue Shift = lowerVectorShuffleAsByteShift ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Shift ; if ( ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) + ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ) == <NUM_LIT> ) { if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V1 , V2 , Mask , Subtarget , DAG ) ) return Insertion ; int InverseMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) , Mask [ <NUM_LIT> ] < <NUM_LIT> ? - <NUM_LIT> : ( Mask [ <NUM_LIT> ] ^ <NUM_LIT> ) } ; if ( SDValue Insertion = lowerVectorShuffleAsElementInsertion ( <STR_LIT> , DL , V2 , V1 , InverseMask , Subtarget , DAG ) ) return Insertion ; } if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ;


<s> static SDValue LowerBuildVectorv8i16 ( SDValue Op , unsigned NonZeros , unsigned NumNonZero , unsigned NumZero , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( NumNonZero > <NUM_LIT> && ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ;

return LowerBuildVectorAsInsert ( Op , NonZeros , NumNonZero , NumZero , DAG , Subtarget ) ;


<s> UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; case <STR_LIT> : UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; case <STR_LIT> : UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; case <STR_LIT> : UpperOpcode = <STR_LIT> ; LowerOpcode = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } Register TargetReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Opcode ; if ( ( TargetReg >= <STR_LIT> && TargetReg <= <STR_LIT> ) || ( TargetReg >= <STR_LIT> && TargetReg <= <STR_LIT> ) ) Opcode = LowerOpcode ; else Opcode = UpperOpcode ; MI . setDesc ( get ( Opcode ) ) ; return true ;


<s> void <ISA_LIT>AsmParser :: expandMem9Inst ( MCInst & Inst , SMLoc IDLoc , MCStreamer & Out , const MCSubtargetInfo * STI , bool IsLoad ) { unsigned NumOp = Inst . getNumOperands ( ) ; assert ( ( NumOp == <NUM_LIT> || NumOp == <NUM_LIT> ) && <STR_LIT> ) ; unsigned StartOp = NumOp == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; const MCOperand & DstRegOp = Inst . getOperand ( StartOp ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & BaseRegOp = Inst . getOperand ( StartOp + <NUM_LIT> ) ; assert ( BaseRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetOp = Inst . getOperand ( StartOp + <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned OpCode = Inst . getOpcode ( ) ; unsigned DstReg = DstRegOp . getReg ( ) ; unsigned BaseReg = BaseRegOp . getReg ( ) ; unsigned TmpReg = DstReg ; const MCInstrDesc & Desc = getInstDesc ( OpCode ) ; int16_t DstRegClass = Desc . OpInfo [ StartOp ] . RegClass ; unsigned DstRegClassID = getContext ( ) . getRegisterInfo ( ) -> getRegClass ( DstRegClass ) . getID ( ) ; bool IsGPR = ( DstRegClassID == <STR_LIT> ) || ( DstRegClassID == <STR_LIT> ) ; if ( ! IsLoad || ! IsGPR || ( BaseReg == DstReg ) ) { TmpReg = getATReg ( IDLoc ) ; if ( ! TmpReg ) return ; } auto emitInst = [ & ] ( ) { if ( NumOp == <NUM_LIT> ) TOut . emitRRX ( OpCode , DstReg , TmpReg , MCOperand :: createImm ( <NUM_LIT> ) , IDLoc , STI ) ; else TOut . emitRRRX ( OpCode , DstReg , DstReg , TmpReg , MCOperand :: createImm ( <NUM_LIT> ) , IDLoc , STI ) ; } ;


<s> } else if ( isa < MCBinaryExpr > ( getImm ( ) ) ) { const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm ( ) ) ; assert ( isa < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) && cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ;


<s> auto Imm = static_cast < unsigned > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; if ( Imm != <STR_LIT> ) O << <STR_LIT> ( Imm ) ;


<s> static __inline unsigned int _MM_GET_FLUSH_ZERO_MODE ( void ) { return _mm_getcsr ( ) & _MM_FLUSH_ZERO_MASK ;


<s> bool Is64Bit = Subtarget -> is64Bit ( ) ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getValVT ( ) ; if ( ( CopyVT == <STR_LIT> || CopyVT == <STR_LIT> ) && ( ( Is64Bit || Ins [ i ] . Flags . isInReg ( ) ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ;


<s> unsigned <ISA_LIT>FrameLowering :: determineFrameLayout ( MachineFunction & MF , bool UpdateMF , bool UseEstimate ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = UseEstimate ? MFI . estimateStackSize ( MF ) : MFI . getStackSize ( ) ; unsigned TargetAlign = getStackAlignment ( ) ; unsigned MaxAlign = MFI . getMaxAlignment ( ) ; unsigned AlignMask = std :: max ( MaxAlign , TargetAlign ) - <NUM_LIT> ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned LR = RegInfo -> getRARegister ( ) ; bool DisableRedZone = MF . getFunction ( ) . hasFnAttribute ( Attribute :: NoRedZone ) ; bool CanUseRedZone = ! MFI . hasVarSizedObjects ( ) && ! MFI . adjustsStack ( ) && ! MustSaveLR ( MF , LR ) && ! RegInfo -> hasBasePointer ( MF ) ; bool FitsInRedZone = FrameSize <= Subtarget . getRedZoneSize ( ) ; if ( ! DisableRedZone && CanUseRedZone && FitsInRedZone ) { NumNoNeedForFrame ++ ; if ( UpdateMF ) MFI . setStackSize ( <NUM_LIT> ) ; return <NUM_LIT> ; } unsigned maxCallFrameSize = MFI . getMaxCallFrameSize ( ) ; unsigned minCallFrameSize = getLinkageSize ( ) ; maxCallFrameSize = std :: max ( maxCallFrameSize , minCallFrameSize ) ; if ( MFI . hasVarSizedObjects ( ) ) maxCallFrameSize = ( maxCallFrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setMaxCallFrameSize ( maxCallFrameSize ) ; FrameSize += maxCallFrameSize ; FrameSize = ( FrameSize + AlignMask ) & ~ AlignMask ; if ( UpdateMF ) MFI . setStackSize ( FrameSize ) ; return FrameSize ;


<s> reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; reserveRegisterTuples ( Reserved , <STR_LIT> ) ; if ( isWave32 ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; unsigned MaxNumSGPRs = ST . getMaxNumSGPRs ( MF ) ; unsigned TotalNumSGPRs = <STR_LIT> . getNumRegs ( ) ; for ( unsigned i = MaxNumSGPRs ; i < TotalNumSGPRs ; ++ i ) { unsigned Reg = <STR_LIT> . getRegister ( i ) ; reserveRegisterTuples ( Reserved , Reg ) ; } unsigned MaxNumVGPRs = ST . getMaxNumVGPRs ( MF ) ; unsigned TotalNumVGPRs = <STR_LIT> . getNumRegs ( ) ;

for ( unsigned i = MaxNumVGPRs ; i < TotalNumVGPRs ; ++ i ) {


<s> return ( uint32x4_t ) __builtin_aarch64_ld1v4si ( ( const __builtin_aarch64_simd_si * ) a ) ;


<s> bool <ISA_LIT>TargetLowering :: needsCmpXchgNb ( const Type * MemType ) const {

const <ISA_LIT>Subtarget & Subtarget = getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> switch ( RC -> getID ( ) ) { case <STR_LIT> : case <STR_LIT> :


<s> bool hasCCPP ( ) const { return HasCCPP ;


<s> void pdp11_gen_int_label ( char * label , const char * prefix , int num ) { if ( TARGET_DEC_ASM ) sprintf ( label , <STR_LIT> , num + <NUM_LIT> ) ;

else sprintf ( label , <STR_LIT> , prefix , num ) ;


<s> constexpr sve_vec_cost ( const simd_vec_cost & base , unsigned int clast_cost , unsigned int fadda_f16_cost , unsigned int fadda_f32_cost , unsigned int fadda_f64_cost , unsigned int gather_load_x32_cost , unsigned int gather_load_x64_cost , unsigned int scatter_store_elt_cost ) : simd_vec_cost ( base ) , clast_cost ( clast_cost ) , fadda_f16_cost ( fadda_f16_cost ) , fadda_f32_cost ( fadda_f32_cost ) , fadda_f64_cost ( fadda_f64_cost ) , gather_load_x32_cost ( gather_load_x32_cost ) , gather_load_x64_cost ( gather_load_x64_cost ) , scatter_store_elt_cost ( scatter_store_elt_cost ) {


<s> addr_rtx = ( XEXP ( mem , <NUM_LIT> ) ) ; if ( GET_CODE ( addr_rtx ) == PRE_MODIFY ) addr_rtx = XEXP ( addr_rtx , <NUM_LIT> ) ; * offset = <NUM_LIT> ; while ( GET_CODE ( addr_rtx ) == PLUS && CONST_INT_P ( XEXP ( addr_rtx , <NUM_LIT> ) ) ) { * offset += INTVAL ( XEXP ( addr_rtx , <NUM_LIT> ) ) ; addr_rtx = XEXP ( addr_rtx , <NUM_LIT> ) ; } if ( ! REG_P ( addr_rtx ) ) return false ;


<s> case AsmToken :: Identifier : Operands . push_back ( <ISA_LIT>Operand :: CreateExpr ( MCSymbolRefExpr :: create ( getContext ( ) . getOrCreateSymbol ( Parser . getTok ( ) . getString ( ) ) , getContext ( ) ) , S ) ) ; Parser . Lex ( ) ;


<s> if ( ! type ) return GET_MODE_ALIGNMENT ( mode ) > PARM_BOUNDARY ; if ( ! AGGREGATE_TYPE_P ( type ) ) return TYPE_ALIGN ( TYPE_MAIN_VARIANT ( type ) ) > PARM_BOUNDARY ; if ( TREE_CODE ( type ) == ARRAY_TYPE ) return TYPE_ALIGN ( TREE_TYPE ( type ) ) > PARM_BOUNDARY ; int ret = <NUM_LIT> ; int ret2 = <NUM_LIT> ; for ( tree field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) if ( DECL_ALIGN ( field ) > PARM_BOUNDARY ) { if ( TREE_CODE ( field ) == FIELD_DECL ) return <NUM_LIT> ; else ret = - <NUM_LIT> ; } else if ( TREE_CODE ( field ) == FIELD_DECL && DECL_BIT_FIELD_TYPE ( field ) && TYPE_ALIGN ( DECL_BIT_FIELD_TYPE ( field ) ) > PARM_BOUNDARY ) ret2 = <NUM_LIT> ; if ( ret2 ) return <NUM_LIT> ; return ret ;


<s> return BaseT :: getVectorInstrCost ( Opcode , Val , Index ) ; } else if ( ST -> hasQPX ( ) && Val -> getScalarType ( ) -> isFloatingPointTy ( ) ) { if ( Index == <NUM_LIT> ) return <NUM_LIT> ; return BaseT :: getVectorInstrCost ( Opcode , Val , Index ) ; } unsigned LHSPenalty = <NUM_LIT> ;

if ( ISD == <STR_LIT> ) LHSPenalty += <NUM_LIT> ;


<s> assert ( Ty . isVector ( ) && <STR_LIT> ) ; MachineInstr * MI = MRI . getVRegDef ( Reg ) ;

auto Cst = get<ISA_LIT>VectorSplatScalar ( * MI , MRI ) ;


<s> if ( MEM_P ( dest ) && ( REG_P ( src ) || src == CONST0_RTX ( GET_MODE ( dest ) ) ) ) { return CONSTANT_ADDRESS_P ( XEXP ( dest , <NUM_LIT> ) ) ; } else if ( REG_P ( dest ) && MEM_P ( src ) ) {

return CONSTANT_ADDRESS_P ( XEXP ( src , <NUM_LIT> ) ) ;


<s> if ( Op -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarSizeInBits ( ) == <NUM_LIT> ) return Op ; if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Cond = Op . getOperand ( <NUM_LIT> ) ; assert ( Cond . getValueType ( ) . getScalarSizeInBits ( ) == VT . getScalarSizeInBits ( ) && <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , VT . getVectorNumElements ( ) ) ; SDValue Mask = DAG . getNode ( <STR_LIT> , dl , MaskVT , Cond , getZeroVector ( VT , Subtarget , DAG , dl ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; return DAG . getSelect ( dl , VT , Mask , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( llvm :: AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal . lower ( ) == <STR_LIT> ) { parseLiteralValues ( SIZE_LONG , DirectiveID . getLoc ( ) ) ;

} else if ( IDVal . lower ( ) == <STR_LIT> || IDVal . lower ( ) == <STR_LIT> ) {


<s> loongarch_block_move_straight ( dest , src , INTVAL ( length ) ) ; return true ; } else if ( optimize ) { loongarch_block_move_loop ( dest , src , INTVAL ( length ) , LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER ) ; return true ; } }


<s> void setVarArgsFirstFPR ( unsigned FPR ) {


<s> unsigned AndOp = <STR_LIT> ; unsigned MovOp = <STR_LIT> ; unsigned Tmp = <STR_LIT> ; BuildMI ( MBB , MBBI , DL , TII . get ( MovOp ) , Tmp ) . addReg ( Reg ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( AndOp ) , Tmp ) . addReg ( Tmp ) . addImm ( Val ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>PMLProfileImport ( const <ISA_LIT>TargetMachine & tm ) { return new <ISA_LIT>PMLProfileImport ( tm ) ;


<s> if ( MI -> getOperand ( OpNo ) . getImm ( ) ) {


<s> if ( DWordIdx == <NUM_LIT> ) { SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( DWordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } int WordIdx = IdxVal / <NUM_LIT> ; SDValue Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Vec ) , DAG . getIntPtrConstant ( WordIdx , dl ) ) ; int ShiftVal = ( IdxVal % <NUM_LIT> ) * <NUM_LIT> ; if ( ShiftVal != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Res , DAG . getConstant ( ShiftVal , dl , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Res ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { static_cast < int > ( IdxVal ) , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { if ( IdxVal == <NUM_LIT> ) return Op ; int Mask [ <NUM_LIT> ] = { <NUM_LIT> , - <NUM_LIT> } ; Vec = DAG . getVectorShuffle ( VecVT , dl , Vec , DAG . getUNDEF ( VecVT ) , Mask ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } return SDValue ( ) ;


<s> static bool expectAbsExpression ( MCAsmParser & MCParser , int64_t & Value , raw_ostream & Err ) { if ( MCParser . getLexer ( ) . isNot ( AsmToken :: Equal ) ) { Err << <STR_LIT> ; return false ; }


<s> Mask = ExtendToType ( Mask , MaskVT , DAG , true ) ; } SDValue Ops [ ] = { N -> getChain ( ) , PassThru , Mask , N -> getBasePtr ( ) , Index , N -> getScale ( ) } ; SDValue NewGather = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , Ops , N -> getMemoryVT ( ) , N -> getMemOperand ( ) ) ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , OrigVT , NewGather , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ;

return DAG . getMergeValues ( { Extract , NewGather . getValue ( <NUM_LIT> ) } , dl ) ;


<s> TargetLowering :: ArgListTy Args ; Args . reserve ( NumOps ) ; TargetLowering :: ArgListEntry Entry ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { Entry . Node = Ops [ i ] ;

Entry . Ty = Entry . Node . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ;


<s> case E_QImode : case E_HImode : case E_SImode : case E_DImode : return true ; case E_SFmode :


<s> MachineBasicBlock * ExitMBB = & MFI ; if ( ExitMBB -> succ_size ( ) == <NUM_LIT> ) { return ExitMBB ; }


<s> unsigned <ISA_LIT>AsmParser :: IdentifyIntelInlineAsmOperator ( StringRef Name ) {

return StringSwitch < unsigned > ( Name ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_TYPE ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_SIZE ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_LENGTH ) . Cases ( <STR_LIT> , <STR_LIT> , IOK_OFFSET ) . Default ( IOK_INVALID ) ;


<s> const BlockData & PBBInfo = BlockInfo [ PBB -> getNumber ( ) ] ; if ( PBBInfo . Exit . isUnknown ( ) || ! PBBInfo . Exit . hasCompatibleVTYPE ( Require ) ) return true ; MachineInstr * DefMI = MRI -> getVRegDef ( InReg ) ; if ( ! DefMI || ! isVectorConfigInstr ( * DefMI ) ) return true ; VSETVLIInfo DefInfo = getInfoForVSETVLI ( * DefMI ) ; if ( ! DefInfo . hasSameAVL ( PBBInfo . Exit ) || ! DefInfo . hasSameVTYPE ( PBBInfo . Exit ) ) return true ;


<s> case R8 : case D8 : case Q8 : return <NUM_LIT> ; case R9 : case D9 : case Q9 : return <NUM_LIT> ; case R10 : case D10 : case Q10 : return <NUM_LIT> ; case R11 : case D11 : case Q11 : return <NUM_LIT> ; case R12 : case D12 : case Q12 : return <NUM_LIT> ; case SP : case D13 : case Q13 : return <NUM_LIT> ; case LR : case D14 : case Q14 : return <NUM_LIT> ; case PC : case D15 : case Q15 : return <NUM_LIT> ; case D16 : return <NUM_LIT> ; case D17 : return <NUM_LIT> ; case D18 : return <NUM_LIT> ; case D19 : return <NUM_LIT> ; case D20 : return <NUM_LIT> ; case D21 : return <NUM_LIT> ; case D22 : return <NUM_LIT> ; case D23 : return <NUM_LIT> ; case D24 : return <NUM_LIT> ; case D25 : return <NUM_LIT> ; case D26 : return <NUM_LIT> ; case D27 : return <NUM_LIT> ; case D28 : return <NUM_LIT> ; case D29 : return <NUM_LIT> ; case D30 : return <NUM_LIT> ; case D31 : return <NUM_LIT> ; case S0 : case S1 : case S2 : case S3 : case S4 : case S5 : case S6 : case S7 : case S8 : case S9 : case S10 : case S11 : case S12 : case S13 : case S14 : case S15 : case S16 : case S17 : case S18 : case S19 : case S20 : case S21 : case S22 : case S23 : case S24 : case S25 : case S26 : case S27 : case S28 : case S29 : case S30 : case S31 : { if ( isSPVFP ) * isSPVFP = true ; switch ( RegEnum ) { default : return <NUM_LIT> ;


<s> } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDirectiveGpWord ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDirectiveWord ( <NUM_LIT> , DirectiveID . getLoc ( ) ) ; return false ;


<s> if ( riscv_use_save_libcall ( frame ) ) { rtx dwarf = NULL_RTX ; dwarf = riscv_adjust_libcall_cfi_prologue ( ) ; frame -> mask = <NUM_LIT> ; size -= frame -> save_libcall_adjustment ; insn = emit_insn ( gen_gpr_save ( GEN_INT ( mask ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; REG_NOTES ( insn ) = dwarf ; } if ( ( frame -> mask | frame -> fmask ) != <NUM_LIT> ) { HOST_WIDE_INT step1 = MIN ( size , riscv_first_stack_step ( frame ) ) ; insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - step1 ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; size -= step1 ; riscv_for_each_saved_reg ( size , riscv_save_reg ) ; } frame -> mask = mask ; if ( frame_pointer_needed ) { insn = gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , GEN_INT ( frame -> hard_frame_pointer_offset - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; riscv_emit_stack_tie ( ) ; } if ( size > <NUM_LIT> ) { if ( SMALL_OPERAND ( - size ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - size ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; } else { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - size ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , RISCV_PROLOGUE_TEMP ( Pmode ) ) ) ;

insn = plus_constant ( Pmode , stack_pointer_rtx , - size ) ;


<s> static VectorType * getVectorType ( IntrinsicInst * I ) { unsigned TypeOp = I -> getIntrinsicID ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ;

auto * PtrTy = cast < PointerType > ( I -> getOperand ( TypeOp ) -> getType ( ) ) ;


<s> return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: ADD_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: SUB_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: MUL_F128 ) ; case <STR_LIT> : return LowerF128Call ( Op , DAG , RTLIB :: DIV_F128 ) ; case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_SUBVECTOR ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerVectorSRA_SRL_SHL ( Op , DAG ) ; case <STR_LIT> :

return LowerShiftLeftParts ( Op , DAG ) ;


<s> Type * ArgTy = Arg . getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) ) return false ; if ( ! Subtarget -> hasSIMD128 ( ) && ArgTy -> isVectorTy ( ) ) return false ; unsigned Opc ; const TargetRegisterClass * RC ; switch ( getSimpleType ( ArgTy ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; RC = & <STR_LIT> ; break ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>beAsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , const MCTargetOptions & ) { return new <ISA_LIT>AsmBackend ( false ) ;


<s> static bool MaskRegClassContains ( unsigned Reg ) { return <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ;


<s> size_t func_name_end = Sym . find ( '.' ) ; return Sym . substr ( <NUM_LIT> , func_name_end ) ;


<s> MCSection * Cur = OutStreamer -> getCurrentSectionOnly ( ) ; MCSection * Nt = MMI -> getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ; OutStreamer -> SwitchSection ( Nt ) ; EmitAlignment ( Align ( <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> * <NUM_LIT> , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( ELF :: NT_GNU_PROPERTY_TYPE_0 , <NUM_LIT> ) ; OutStreamer -> EmitBytes ( StringRef ( <STR_LIT> , <NUM_LIT> ) ) ; OutStreamer -> EmitIntValue ( ELF :: GNU_PROPERTY_AARCH64_FEATURE_1_AND , <NUM_LIT> ) ; OutStreamer -> EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ;

OutStreamer -> EmitIntValue ( Flags , <NUM_LIT> ) ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & ctx , <ISA_LIT>AsmPrinter & asmprinter ) : Ctx ( ctx ) , AsmPrinter ( asmprinter ) {


<s> LC = RTLIB :: getFPROUND ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; SDValue SrcVal = Op . getOperand ( <NUM_LIT> ) ; return makeLibCall ( DAG , LC , Op . getValueType ( ) , SrcVal , false , SDLoc ( Op ) ) . first ;


<s> return __builtin_mve_vabsq_m_fv4sf ( __arm_vuninitializedq_f32 ( ) , __a , __p ) ;


<s> SDValue Mul1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opcode , dl , MulVT , Op0 , Op1 ) ) ; SDValue Mul2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Opcode , dl , MulVT , Odd0 , Odd1 ) ) ; SDValue Highs , Lows ; if ( VT == <STR_LIT> ) { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } else { const int HighMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Highs = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , HighMask ) ; const int LowMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; Lows = DAG . getVectorShuffle ( VT , dl , Mul1 , Mul2 , LowMask ) ; } if ( IsSigned && ! Subtarget -> hasSSE41 ( ) ) { SDValue ShAmt = DAG . getConstant ( <NUM_LIT> , DAG . getTargetLoweringInfo ( ) . getShiftAmountTy ( VT ) ) ; SDValue T1 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op0 , ShAmt ) , Op1 ) ; SDValue T2 = DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , VT , Op1 , ShAmt ) , Op0 ) ;

SDValue Fixup = DAG . getNode ( <STR_LIT> , dl , VT , T1 , T2 ) ;


<s> return __aarch64_vset_lane_any ( * __src , __vec , __lane ) ;


<s> bool mmix_frame_pointer_required ( void ) {


<s> __builtin_aarch64_simd_ci __o ; uint8x16x3_t temp ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_u8 ( val . val [ <NUM_LIT> ] , vcreate_u8 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> Optional < int64_t > Const ; if ( ( Const = getIfConst ( Add -> getOperand ( <NUM_LIT> ) ) ) ) Summand = Add -> getOperand ( <NUM_LIT> ) ; else if ( ( Const = getIfConst ( Add -> getOperand ( <NUM_LIT> ) ) ) ) Summand = Add -> getOperand ( <NUM_LIT> ) ; else return ReturnFalse ;

int64_t Immediate = Const . getValue ( ) << TypeScale ;


<s> return getFeatureBits ( ) [ <STR_LIT> ] ;


<s> if ( ! NextOp ) return ; MachineInstr & MISucc = * NextOp -> getParent ( ) ; if ( ! TII -> canShrink ( MISucc , * MRI ) ) return ; int SuccOpc = <STR_LIT> ( MISucc . getOpcode ( ) ) ; MachineOperand * CarryIn = TII -> getNamedOperand ( MISucc , <STR_LIT> :: src2 ) ; if ( ! CarryIn ) return ; MachineOperand * CarryOut = TII -> getNamedOperand ( MISucc , <STR_LIT> :: sdst ) ; if ( ! CarryOut ) return ; if ( ! MRI -> hasOneUse ( CarryIn -> getReg ( ) ) || ! MRI -> use_empty ( CarryOut -> getReg ( ) ) ) return ; MachineBasicBlock & MBB = * MI . getParent ( ) ; auto Liveness = MBB . computeRegisterLiveness ( TRI , <STR_LIT> , MI , <NUM_LIT> ) ; if ( Liveness != MachineBasicBlock :: LQR_Dead ) return ; for ( auto I = std :: next ( MI . getIterator ( ) ) , E = MISucc . getIterator ( ) ; I != E ; ++ I ) { if ( I -> modifiesRegister ( <STR_LIT> , TRI ) ) return ; } BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( Opc ) ) . add ( * TII -> getNamedOperand ( MI , <STR_LIT> :: vdst ) ) . add ( * TII -> getNamedOperand ( MI , <STR_LIT> :: src0 ) ) . add ( * TII -> getNamedOperand ( MI , <STR_LIT> :: src1 ) ) . setMIFlags ( MI . getFlags ( ) ) ; MI . eraseFromParent ( ) ; BuildMI ( MBB , MISucc , MISucc . getDebugLoc ( ) , TII -> get ( SuccOpc ) ) . add ( * TII -> getNamedOperand ( MISucc , <STR_LIT> :: vdst ) ) . add ( * TII -> getNamedOperand ( MISucc , <STR_LIT> :: src0 ) ) . add ( * TII -> getNamedOperand ( MISucc , <STR_LIT> :: src1 ) ) . setMIFlags ( MISucc . getFlags ( ) ) ;


<s> int frv_legitimate_constant_p ( rtx x ) { enum machine_mode mode = GET_MODE ( x ) ; if ( TARGET_FDPIC ) return LEGITIMATE_PIC_OPERAND_P ( x ) ; if ( GET_CODE ( x ) != CONST_DOUBLE ) return TRUE ; if ( mode == VOIDmode || mode == DImode ) return TRUE ; if ( x == CONST0_RTX ( mode ) ) return TRUE ;


<s> bool unifyMetadataImpl ( Module & M ) { const char * Vers [ ] = { kOCLMD :: SpirVer , kOCLMD :: OCLVer } ; const char * Exts [ ] = { kOCLMD :: UsedExt , kOCLMD :: UsedOptCoreFeat , kOCLMD :: CompilerOptions , kOCLMD :: LLVMIdent } ;


<s> if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . in<ISA_LIT>16Mode ( ) ) addPass ( create<ISA_LIT>ConstantIslandPass ( TM ) ) ; if ( get<ISA_LIT>Subtarget ( ) . isTargetNaCl ( ) ) { addPass ( create<ISA_LIT>NaClRewritePass ( ) ) ; } return true ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isMov ( unsigned Opcode ) const { switch ( Opcode ) {


<s> unsigned Reg = Op . getReg ( ) ; O << getRegisterName ( Reg ) ; } else if ( Op . isImm ( ) ) { O << '#' << Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; const MCConstantExpr * BranchTarget = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ; int64_t Address ; if ( BranchTarget && BranchTarget -> EvaluateAsAbsolute ( Address ) ) { O << <STR_LIT> ; O . write_hex ( Address ) ; }


<s> if ( addr . pointer ) return true ; if ( ( addr . base && REG_P ( addr . base ) && REG_POINTER ( addr . base ) ) || ( addr . indx && REG_P ( addr . indx ) && REG_POINTER ( addr . indx ) ) ) return true ; return false ;


<s> case Token : OS << <STR_LIT> << getToken ( ) << <STR_LIT> ; break ; case SystemRegister : OS << <STR_LIT> << getSysReg ( ) << '>' ; break ; }


<s> bool HasStdExtC = STI . getFeatureBits ( ) [ <STR_LIT> ] ; unsigned MinNopLen = HasStdExtC ? <NUM_LIT> : <NUM_LIT> ; if ( ( Count % MinNopLen ) != <NUM_LIT> ) return false ;


<s> if ( MBBI -> isDebugValue ( ) ) continue ; MachineInstr * NMI = & * MBBI ; MI = NMI ; unsigned NPredReg = <NUM_LIT> ; <STR_LIT> NCC = getITInstrPredicate ( NMI , NPredReg ) ; if ( NCC == CC || NCC == OCC ) { Mask |= ( NCC & <NUM_LIT> ) << Pos ; NMI -> addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true , false ) ) ; LastITMI = NMI ; } else { if ( NCC == <STR_LIT> && MoveCopyOutOfITBlock ( NMI , CC , OCC , Defs , Uses ) ) { -- MBBI ; MBB . remove ( NMI ) ; MBB . insert ( InsertPos , NMI ) ; ++ NumMovedInsts ; continue ; } break ; } TrackDefUses ( NMI , Defs , Uses , TRI ) ; -- Pos ; } }


<s> OperandMatchResultTy parsePCRel12 ( OperandVector & Operands ) {

return parsePCRel ( Operands , - ( <NUM_LIT> << <NUM_LIT> ) , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> , false ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue CmpOp0 = Op . getOperand ( <NUM_LIT> ) ; SDValue CmpOp1 = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc DL ( Op ) ; unsigned CCValid , CCMask ; SDValue Flags = emitCmp ( DAG , CmpOp0 , CmpOp1 , CC , CCValid , CCMask ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , DAG . getConstant ( CCValid , <STR_LIT> ) , DAG . getConstant ( CCMask , <STR_LIT> ) , Dest , Flags ) ;


<s> unsigned getCalleeSavedFrameSize ( ) const {


<s> const LLT s64 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s128 = LLT :: scalar ( <NUM_LIT> ) ; for ( auto Ty : { p0 , s1 , s8 , s16 , s32 } ) setAction ( { G_IMPLICIT_DEF , Ty } , Legal ) ; for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { G_PHI , Ty } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) for ( auto Ty : { s8 , s16 , s32 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned Op : { G_UADDE } ) { setAction ( { Op , s32 } , Legal ) ; setAction ( { Op , <NUM_LIT> , s1 } , Legal ) ; } for ( unsigned MemOp : { G_LOAD , G_STORE } ) { for ( auto Ty : { s8 , s16 , s32 , p0 } ) setAction ( { MemOp , Ty } , Legal ) ; setAction ( { MemOp , <NUM_LIT> , p0 } , Legal ) ; } setAction ( { G_FRAME_INDEX , p0 } , Legal ) ; setAction ( { G_GLOBAL_VALUE , p0 } , Legal ) ; setAction ( { G_PTR_ADD , p0 } , Legal ) ; setAction ( { G_PTR_ADD , <NUM_LIT> , s32 } , Legal ) ; if ( ! Subtarget . is64Bit ( ) ) { getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 } , { p0 } ) . maxScalar ( <NUM_LIT> , s32 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s32 } } ) ; getActionDefinitionsBuilder ( { G_SDIV , G_SREM , G_UDIV , G_UREM } ) . legalFor ( { s8 , s16 , s32 } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) ;

getActionDefinitionsBuilder ( { G_SHL , G_LSHR , G_ASHR } ) . legalFor ( { { s8 , s8 } , { s16 , s8 } , { s32 , s8 } } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) . clampScalar ( <NUM_LIT> , s8 , s8 ) ;


<s> if ( EnableCondOpt ) addPass ( create<ISA_LIT>ConditionOptimizerPass ( ) ) ; if ( EnableCCMP ) addPass ( create<ISA_LIT>ConditionalCompares ( ) ) ; if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableCondBrTuning ) addPass ( create<ISA_LIT>CondBrTuning ( ) ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ;

if ( EnableStPairSuppress ) addPass ( create<ISA_LIT>StorePairSuppressPass ( ) ) ;


<s> __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ;

return ( uint8x16_t ) __builtin_aarch64_qtbl3v16qi ( __o , ( int8x16_t ) idx ) ;


<s> int sp_adjust ; if ( ! reload_completed ) return <NUM_LIT> ; if ( cfun -> machine -> attr_naked_p && ! flag_ret_in_naked_func ) return <NUM_LIT> ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ;

if ( ! cfun -> machine -> fp_as_gp_p && satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca && NDS32_V3PUSH_AVAILABLE_P && ! ( TARGET_HARD_FLOAT && ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) ) ) return <NUM_LIT> ;


<s> unsigned Size = Ty . getSizeInBits ( ) ; unsigned Pieces = ( Size + <NUM_LIT> ) / <NUM_LIT> ; unsigned NewNumElts = ( Ty . getNumElements ( ) + <NUM_LIT> ) / Pieces ;

return std :: make_pair ( TypeIdx , LLT :: scalarOrVector ( NewNumElts , EltTy ) ) ;


for ( regno = P0_REGNUM ; regno < R0_REGNUM ; regno ++ ) call_used_regs [ regno ] = <NUM_LIT> ;


<s> if ( TT . getObjectFormat ( ) == Triple :: ELF ) return new <ISA_LIT>TargetELFStreamer ( S ) ; return nullptr ;


<s> inline static int number_of_first_bit_set ( unsigned mask ) { return ctz_hwi ( mask ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS ) , DataLayout ( Subtarget . getTargetDataString ( ) ) , InstrInfo ( * this ) , FrameLowering ( Subtarget ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrItins ( Subtarget . getInstrItineraryData ( ) ) {


<s> EmitSled ( MI , SledKind :: TAIL_CALL ) ;


<s> Type * ArgTy = ArgVT . getTypeForEVT ( * DAG . getContext ( ) ) ; uint32_t ArgSize = getTargetData ( ) -> getTypeAllocSize ( ArgTy ) ; uint8_t ArgMode ; if ( ArgVT == <STR_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } else if ( ArgVT . isFloatingPoint ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else if ( ArgVT . isInteger ( ) && ArgSize <= <NUM_LIT> ) { ArgMode = <NUM_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } if ( ArgMode == <NUM_LIT> ) { assert ( ! getTargetMachine ( ) . Options . UseSoftFloat && ! ( DAG . getMachineFunction ( ) . getFunction ( ) -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) && Subtarget -> hasSSE1 ( ) ) ; } SmallVector < SDValue , <NUM_LIT> > InstOps ; InstOps . push_back ( Chain ) ;


return isRegOrInlineNoMods ( <STR_LIT> , <STR_LIT> ) ;


<s> rtx frv_dynamic_chain_address ( rtx frame ) { cfun -> machine -> frame_needed = <NUM_LIT> ;


<s> <ISA_LIT>OptimizeSZExtends ( ) : MachineFunctionPass ( ID ) {


<s> if ( ! Elt . getNode ( ) || ( Elt . getOpcode ( ) != <STR_LIT> && ! <STR_LIT> ( Elt . getNode ( ) ) ) ) return SDValue ( ) ; if ( ! LDBase ) { if ( Elt . getNode ( ) -> getOpcode ( ) == <STR_LIT> ) return SDValue ( ) ; LDBase = cast < LoadSDNode > ( Elt . getNode ( ) ) ; LastLoadedElt = i ; continue ; } if ( Elt . getOpcode ( ) == <STR_LIT> ) continue ; LoadSDNode * LD = cast < LoadSDNode > ( Elt ) ; if ( ! DAG . isConsecutiveLoad ( LD , LDBase , EltVT . getSizeInBits ( ) / <NUM_LIT> , i ) ) return SDValue ( ) ; LastLoadedElt = i ; } if ( LastLoadedElt == NumElems - <NUM_LIT> ) { SDValue NewLd = SDValue ( ) ; if ( DAG . InferPtrAlignment ( LDBase -> getBasePtr ( ) ) >= <NUM_LIT> ) NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , <NUM_LIT> ) ; NewLd = DAG . getLoad ( VT , DL , LDBase -> getChain ( ) , LDBase -> getBasePtr ( ) , LDBase -> getPointerInfo ( ) , LDBase -> isVolatile ( ) , LDBase -> isNonTemporal ( ) , LDBase -> isInvariant ( ) , LDBase -> getAlignment ( ) ) ; if ( LDBase -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SDValue ( LDBase , <NUM_LIT> ) , SDValue ( NewLd . getNode ( ) , <NUM_LIT> ) ) ;

DAG . ReplaceAllUsesOfValueWith ( SDValue ( LDBase , <NUM_LIT> ) , NewChain ) ;


<s> Opc = ( EltSize == <NUM_LIT> ) ? AMDGPU :: DS_READ2ST64_B32 : AMDGPU :: DS_READ2ST64_B64 ; } assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Read2Desc = TII -> get ( Opc ) ; const TargetRegisterClass * SuperRC = ( EltSize == <NUM_LIT> ) ? & AMDGPU :: VReg_64RegClass : & AMDGPU :: VReg_128RegClass ; unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; DebugLoc DL = I -> getDebugLoc ( ) ; MachineInstrBuilder Read2 = BuildMI ( * MBB , I , DL , Read2Desc , DestReg ) . addImm ( <NUM_LIT> ) . addOperand ( * AddrReg ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addOperand ( * M0Reg ) . addMemOperand ( * I -> memoperands_begin ( ) ) . addMemOperand ( * Paired -> memoperands_begin ( ) ) ; LIS -> InsertMachineInstrInMaps ( Read2 ) ; unsigned SubRegIdx0 = ( EltSize == <NUM_LIT> ) ? AMDGPU :: sub0 : AMDGPU :: sub0_sub1 ; unsigned SubRegIdx1 = ( EltSize == <NUM_LIT> ) ? AMDGPU :: sub1 : AMDGPU :: sub2_sub3 ; updateRegDefsUses ( DestReg0 , DestReg , SubRegIdx0 ) ; updateRegDefsUses ( DestReg1 , DestReg , SubRegIdx1 ) ; LIS -> RemoveMachineInstrFromMaps ( I ) ;

LIS -> RemoveMachineInstrFromMaps ( Paired ) ;


<s> MachineInstr * MI = & * MII ++ ; if ( MI -> getOpcode ( ) != <STR_LIT> ) continue ; unsigned Cond = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool Inverted = false ; if ( MFI . isVRegStackified ( Cond ) ) { assert ( MRI . hasOneDef ( Cond ) ) ; MachineInstr * Def = MRI . getVRegDef ( Cond ) ; switch ( Def -> getOpcode ( ) ) { using namespace <ISA_LIT> ; case EQ_I32 : Def -> setDesc ( TII . get ( NE_I32 ) ) ; Inverted = true ; break ; case NE_I32 : Def -> setDesc ( TII . get ( EQ_I32 ) ) ; Inverted = true ; break ; case GT_S_I32 : Def -> setDesc ( TII . get ( LE_S_I32 ) ) ; Inverted = true ; break ; case GE_S_I32 : Def -> setDesc ( TII . get ( LT_S_I32 ) ) ; Inverted = true ; break ; case LT_S_I32 : Def -> setDesc ( TII . get ( GE_S_I32 ) ) ; Inverted = true ; break ; case LE_S_I32 : Def -> setDesc ( TII . get ( GT_S_I32 ) ) ; Inverted = true ; break ; case GT_U_I32 : Def -> setDesc ( TII . get ( LE_U_I32 ) ) ; Inverted = true ; break ; case GE_U_I32 : Def -> setDesc ( TII . get ( LT_U_I32 ) ) ; Inverted = true ; break ; case LT_U_I32 : Def -> setDesc ( TII . get ( GE_U_I32 ) ) ; Inverted = true ;


<s> case CmpInst :: FCMP_OLE : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ONE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ORD : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UNO : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UEQ : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UGT : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_UGE : SwapArgs = true ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ULT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: FCMP_ULE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_EQ : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_NE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_UGT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_UGE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_ULT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_ULE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_SGT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_SGE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_SLT : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; case CmpInst :: ICMP_SLE : SwapArgs = false ; SetCCOpc = <STR_LIT> ; break ; default : return false ; } const Value * Op0 = CI -> getOperand ( <NUM_LIT> ) , * Op1 = CI -> getOperand ( <NUM_LIT> ) ; if ( SwapArgs ) std :: swap ( Op0 , Op1 ) ; if ( ! <ISA_LIT>FastEmitCompare ( Op0 , Op1 , VT ) ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( SetCCOpc ) , ResultReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ;


<s> bool <ISA_LIT>InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( * I ) ) break ; SmallVector < MachineOperand , <NUM_LIT> > ThisCond ; ThisCond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; const MachineOperand * ThisTarget ; if ( ! isBranch ( I , ThisCond , ThisTarget ) ) return true ; if ( ! ThisTarget -> isMBB ( ) ) return true ; if ( ThisCond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = ThisTarget -> getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) std :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; TBB = ThisTarget -> getMBB ( ) ; continue ; } if ( Cond . empty ( ) ) { FBB = TBB ; TBB = ThisTarget -> getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( ThisCond [ <NUM_LIT> ] . getImm ( ) ) ) ;

for ( unsigned int i = <NUM_LIT> ; i < ( I -> getNumExplicitOperands ( ) ) ; i ++ ) Cond . push_back ( I -> getOperand ( i ) ) ;


<s> StringRef <ISA_LIT>Operand :: getToken ( ) const { assert ( isToken ( ) ) ; return Token ;


<s> bool <ISA_LIT>SinglePathInfo :: doInitialization ( Module & M ) { return false ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> ret = alpha_sa_size ( ) ; ret += ALPHA_ROUND ( crtl -> outgoing_args_size ) ; switch ( from ) { case FRAME_POINTER_REGNUM : break ; case ARG_POINTER_REGNUM : ret += ( ALPHA_ROUND ( get_frame_size ( ) + crtl -> args . pretend_args_size ) - crtl -> args . pretend_args_size ) ; break ; default : gcc_unreachable ( ) ; }


<s> static SDNode * selectI64Imm ( SelectionDAG * CurDAG , SDNode * N ) { SDLoc dl ( N ) ; int64_t Imm = cast < ConstantSDNode > ( N ) -> getZExtValue ( ) ; if ( unsigned MinSize = allUsesTruncate ( CurDAG , N ) ) { uint64_t SextImm = SignExtend64 ( Imm , MinSize ) ; SDValue SDImm = CurDAG -> getTargetConstant ( SextImm , dl , <STR_LIT> ) ; if ( isInt < <NUM_LIT> > ( SextImm ) ) return CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDImm ) ;


<s> case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; default : return false ; } unsigned Reg ; if ( FuncInfo . Fn -> getAttributes ( ) . hasAttribute ( <NUM_LIT> , Attribute :: SExt ) ) Reg = getRegForSignedValue ( RV ) ; else if ( FuncInfo . Fn -> getAttributes ( ) . hasAttribute ( <NUM_LIT> , Attribute :: ZExt ) ) Reg = getRegForUnsignedValue ( RV ) ; else Reg = getRegForValue ( RV ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( Reg ) ;


<s> return <ISA_LIT>InstrInfo :: getSide ( SU -> getInstr ( ) ) ;


<s> Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned AssignedReg = FuncInfo . ValueMap [ I ] ; const TargetRegisterClass * RC = AssignedReg ? MRI . getRegClass ( AssignedReg ) : nullptr ; unsigned ResultReg = <NUM_LIT> ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , RC ) ) return false ; updateValueMap ( I , ResultReg ) ;


return ( poly128_t ) __builtin_neon_vreinterprettiv4si ( __a ) ;


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override { return & InstrInfo . getRegisterInfo ( ) ;


<s> if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else if ( FBS [ <STR_LIT> ] ) Str += <STR_LIT> ; else { auto ext = std :: find_if ( std :: begin ( ExtensionMap ) , std :: end ( ExtensionMap ) , [ & ] ( const Extension & e ) {

return ( FBS & e . Features ) != FeatureBitset ( ) ;


<s> return ScalableBytes % <NUM_LIT> == <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI -> getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } } return <NUM_LIT> ;


<s> SDValue LowAddr , HighAddr ; if ( GlobalAddressSDNode * GASD = dyn_cast < GlobalAddressSDNode > ( Base . getNode ( ) ) ) { LowAddr = DAG . getGlobalAddress ( GASD -> getGlobal ( ) , DL , Base . getValueType ( ) , LowOffset ) ; HighAddr = DAG . getGlobalAddress ( GASD -> getGlobal ( ) , DL , Base . getValueType ( ) , HighOffset ) ; } else { LowAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Base , DAG . getConstant ( LowOffset , DL , <STR_LIT> ) ) ; HighAddr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Base , DAG . getConstant ( HighOffset , DL , <STR_LIT> ) ) ; } SDValue LowShift = DAG . getConstant ( ( Offset - LowOffset ) * <NUM_LIT> , DL , <STR_LIT> ) ; SDValue HighShift = DAG . getConstant ( ( HighOffset - Offset ) * <NUM_LIT> , DL , <STR_LIT> ) ;

SDValue Low = DAG . getLoad ( PtrVT , DL , Chain , LowAddr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> <ISA_LIT>IRDecorator ( ) : FunctionPass ( ID ) {


<s> void <ISA_LIT>LoadStoreOptimizer :: addInstToMergeableList ( const CombineInfo & CI , std :: list < std :: list < CombineInfo > > & MergeableInsts ) const {

for ( std :: list < CombineInfo > & AddrList : MergeableInsts ) {


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override {


<s> Forward ( unsigned VReg , MCPhysReg PReg , MVT VT ) : VReg ( VReg ) , PReg ( PReg ) , VT ( VT ) {


<s> if ( ArgVT . isScalableVector ( ) && ArgVT . getVectorElementType ( ) . SimpleTy == <STR_LIT> ) return ArgIdx . index ( ) ; }


<s> return CC_FPU_LTmode ; case GT : return CC_FPU_GTmode ; case EQ : return CC_FPU_EQmode ; case NE : return CC_FPU_NEmode ; default : gcc_unreachable ( ) ; } }


<s> if ( MF -> getFunction ( ) . hasFnAttribute ( Attribute :: OptimizeForSize ) ) -- Latency ; } return Latency ; } if ( DefMO . isImplicit ( ) || UseMI . getOperand ( UseIdx ) . isImplicit ( ) ) return - <NUM_LIT> ; unsigned DefAlign = DefMI . hasOneMemOperand ( ) ? ( * DefMI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; unsigned UseAlign = UseMI . hasOneMemOperand ( ) ? ( * UseMI . memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefMCID , DefIdx , DefAlign , UseMCID , UseIdx , UseAlign ) ; if ( Latency < <NUM_LIT> ) return Latency ;


<s> return isInt < <NUM_LIT> > ( Amount ) ;


<s> HOST_WIDE_INT total , max ; unsigned try_align = FASTEST_ALIGNMENT ; if ( maximum_field_alignment && try_align > maximum_field_alignment ) try_align = maximum_field_alignment ; if ( align >= try_align ) return align ; for ( max = <NUM_LIT> , field = TYPE_FIELDS ( type ) ; field ; field = DECL_CHAIN ( field ) ) { tree offset , size ; if ( TREE_CODE ( field ) != FIELD_DECL || TREE_TYPE ( field ) == error_mark_node ) continue ; offset = bit_position ( field ) ; size = DECL_SIZE ( field ) ; if ( ! tree_fits_uhwi_p ( offset ) || ! tree_fits_uhwi_p ( size ) || tree_to_uhwi ( offset ) >= try_align || tree_to_uhwi ( size ) >= try_align ) return try_align ; total = tree_to_uhwi ( offset ) + tree_to_uhwi ( size ) ; if ( total > max ) max = total ; } if ( max >= ( HOST_WIDE_INT ) try_align ) align = try_align ; else if ( try_align > <NUM_LIT> && max >= <NUM_LIT> ) align = max > <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; return align ;


<s> SDValue Elt = getShuffleScalarElt ( SVOp , Index , DAG , <NUM_LIT> ) ; if ( ! ( Elt . getNode ( ) && ( Elt . getOpcode ( ) == <STR_LIT> || <STR_LIT> ( Elt ) ) ) ) break ; } return i ;


<s> case <STR_LIT> : case <STR_LIT> : if ( VT != <STR_LIT> ) return false ; break ; } Address Addr ; if ( ! <ISA_LIT>ComputeAddress ( LI -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <ISA_LIT>EmitLoad ( VT , ResultReg , Addr , isZExt , false ) ) return false ;


<s> MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else if ( F -> getTarget ( ) . getRelocationModel ( ) != Reloc :: PIC_ ) { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } else { MachineInstrBuilder MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( TII -> getGlobalBaseReg ( F ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addGlobalAddress ( MI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) , <NUM_LIT> , MI -> getOperand ( <NUM_LIT> ) . getTargetFlags ( ) ) . addReg ( <NUM_LIT> ) ; MIB = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ; addDirectMem ( MIB , <STR_LIT> ) ; MIB . addReg ( <STR_LIT> , RegState :: ImplicitDefine ) . addRegMask ( RegMask ) ; } MI -> eraseFromParent ( ) ; return BB ;


<s> static bool ck807_ck810_rtx_costs ( rtx x , int code , int outer_code ATTRIBUTE_UNUSED , int * total , bool speed ATTRIBUTE_UNUSED ) { switch ( code ) { case MULT : if ( REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) { HOST_WIDE_INT val = INTVAL ( XEXP ( x , <NUM_LIT> ) ) ; if ( val % <NUM_LIT> == <NUM_LIT> && val < <NUM_LIT> && val > <NUM_LIT> ) { * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ;


<s> bool handled_one = false ; struct seh_frame_state * seh ; if ( ! TARGET_SEH ) return ; seh = cfun -> machine -> seh ; if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS ) { rtx_insn * prev = prev_active_insn ( insn ) ; if ( prev && ! insn_nothrow_p ( prev ) ) fputs ( <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; seh -> in_cold_section = true ; return ; } if ( NOTE_P ( insn ) || ! RTX_FRAME_RELATED_P ( insn ) ) return ; if ( seh -> after_prologue ) return ; for ( note = REG_NOTES ( insn ) ; note ; note = XEXP ( note , <NUM_LIT> ) ) { switch ( REG_NOTE_KIND ( note ) ) { case REG_FRAME_RELATED_EXPR : pat = XEXP ( note , <NUM_LIT> ) ; goto found ;


<s> fixVcmpxPermlaneHazards ( MI ) ; fixSMEMtoVectorWriteHazards ( MI ) ; fixVcmpxExecWARHazard ( MI ) ;