<s> unsigned LaneStart = l * NumLaneElts ; for ( unsigned i = <NUM_LIT> ; i != NumLaneElts ; ++ i ) { unsigned Idx = NumLaneElts == <NUM_LIT> ? ( Imm >> ( i * <NUM_LIT> ) ) & <NUM_LIT> : ( Imm >> ( i + LaneStart ) ) & <NUM_LIT> ; ShuffleMask . push_back ( Idx + LaneStart ) ; }


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {


<s> if ( VT . getSizeInBits ( ) != <NUM_LIT> || S -> getAlignment ( ) >= <NUM_LIT> || S -> getAlignment ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( SDValue ReplacedSplat = replaceSplatVectorStore ( DAG , * S ) ) return ReplacedSplat ; SDLoc DL ( S ) ; unsigned NumElts = VT . getVectorNumElements ( ) / <NUM_LIT> ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , VT . getVectorElementType ( ) , NumElts ) ; SDValue SubVector0 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue SubVector1 = DAG . getNode ( <STR_LIT> , DL , HalfVT , StVal , DAG . getConstant ( NumElts , DL , <STR_LIT> ) ) ; SDValue BasePtr = S -> getBasePtr ( ) ; SDValue NewST1 = DAG . getStore ( S -> getChain ( ) , DL , SubVector0 , BasePtr , S -> getPointerInfo ( ) , S -> getAlignment ( ) , S -> getMemOperand ( ) -> getFlags ( ) ) ;

SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getInstrBits ( const MCInst & MI , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { uint64_t inst = getBinaryCodeForInstr ( MI , Fixups , STI ) ;


<s> if ( __align < <NUM_LIT> * sizeof ( void * ) ) __align = <NUM_LIT> * sizeof ( void * ) ; __malloc_ptr = malloc ( __size + __align ) ; if ( ! __malloc_ptr ) return ( ( void * ) <NUM_LIT> ) ; __aligned_ptr = ( void * ) ( ( ( size_t ) __malloc_ptr + __align ) & ~ ( ( size_t ) ( __align ) - <NUM_LIT> ) ) ; ( ( void * * ) __aligned_ptr ) [ - <NUM_LIT> ] = __malloc_ptr ;


<s> if ( TLI . SimplifyDemandedBits ( Mask , DemandedMask , DCI ) ) { DCI . AddToWorklist ( N ) ; return SDValue ( N , <NUM_LIT> ) ; } } return SDValue ( ) ;


<s> if ( ! MO . isImm ( ) ) return false ;

return MO . getImm ( ) == Start . ImmVal ;


<s> void setEndPacket ( bool yes ) { endPacket = yes ;


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; StackPtr = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; <ISA_LIT>ScalarSSEf64 = Subtarget -> hasSSE2 ( ) || Subtarget -> hasAVX ( ) ;

<ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 ( ) || Subtarget -> hasAVX ( ) ;


<s> SDLoc DL ( ExtElt ) ; SDValue Ext0 = DAG . getNode ( <STR_LIT> , DL , OpVT , Vec . getOperand ( <NUM_LIT> ) , Index ) ; SDValue Ext1 = DAG . getNode ( <STR_LIT> , DL , OpVT , Vec . getOperand ( <NUM_LIT> ) , Index ) ; return DAG . getNode ( Vec . getOpcode ( ) , DL , VT , Ext0 , Ext1 , Vec . getOperand ( <NUM_LIT> ) ) ; } if ( ! ( VT == <STR_LIT> && Subtarget . hasFP16 ( ) ) && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( Vec . getOpcode ( ) == <STR_LIT> && Vec . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Vec . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> && Vec . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) == VecVT ) { SDLoc DL ( ExtElt ) ; SDValue Ext0 = DAG . getNode ( <STR_LIT> , DL , Vec . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) , Vec . getOperand ( <NUM_LIT> ) , Index ) ; SDValue Ext1 = DAG . getNode ( <STR_LIT> , DL , VT , Vec . getOperand ( <NUM_LIT> ) , Index ) ; SDValue Ext2 = DAG . getNode ( <STR_LIT> , DL , VT , Vec . getOperand ( <NUM_LIT> ) , Index ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ext0 , Ext1 , Ext2 ) ; } switch ( Vec . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> unsigned long type = ARM_FT_UNKNOWN ; tree a ; tree attr ; gcc_assert ( TREE_CODE ( current_function_decl ) == FUNCTION_DECL ) ; if ( optimize > <NUM_LIT> && ( TREE_NOTHROW ( current_function_decl ) || ! ( flag_unwind_tables || ( flag_exceptions && arm_except_unwind_info ( & global_options ) != UI_SJLJ ) ) ) && TREE_THIS_VOLATILE ( current_function_decl ) ) type |= ARM_FT_VOLATILE ; if ( cfun -> static_chain_decl != NULL ) type |= ARM_FT_NESTED ; attr = DECL_ATTRIBUTES ( current_function_decl ) ; a = lookup_attribute ( <STR_LIT> , attr ) ; if ( a != NULL_TREE ) type |= ARM_FT_NAKED ; a = lookup_attribute ( <STR_LIT> , attr ) ;

if ( a == NULL_TREE ) a = lookup_attribute ( <STR_LIT> , attr ) ;


<s> return true ; } } } else if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { if ( ( CN -> getZExtValue ( ) & <NUM_LIT> ) == <NUM_LIT> ) { short Imm ; if ( isIntS16Immediate ( CN , Imm ) ) { Disp = DAG . getTargetConstant ( ( unsigned short ) Imm >> <NUM_LIT> , getPointerTy ( ) ) ; Base = DAG . getRegister ( <STR_LIT> , CN -> getValueType ( <NUM_LIT> ) ) ; return true ; } if ( CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> || ( int64_t ) CN -> getZExtValue ( ) == ( int ) CN -> getZExtValue ( ) ) { int Addr = ( int ) CN -> getZExtValue ( ) ; Disp = DAG . getTargetConstant ( ( short ) Addr >> <NUM_LIT> , <STR_LIT> ) ; Base = DAG . getTargetConstant ( ( Addr - ( signed short ) Addr ) >> <NUM_LIT> , <STR_LIT> ) ; unsigned Opc = CN -> getValueType ( <NUM_LIT> ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; Base = SDValue ( DAG . getMachineNode ( Opc , dl , CN -> getValueType ( <NUM_LIT> ) , Base ) , <NUM_LIT> ) ; return true ; } } } Disp = DAG . getTargetConstant ( <NUM_LIT> , getPointerTy ( ) ) ; if ( FrameIndexSDNode * FI = dyn_cast < FrameIndexSDNode > ( N ) ) Base = DAG . getTargetFrameIndex ( FI -> getIndex ( ) , N . getValueType ( ) ) ; else Base = N ; return true ;


<s> void <ISA_LIT>InstPrinter :: printVectorRegister ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNo ) . getReg ( ) ; printRegName ( O , Reg ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> for ( <STR_LIT> & Inst : Seq ) { if ( ++ Num == Seq . size ( ) ) Result = DstReg ; if ( Inst . Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , Result ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } else { BuildMI ( MBB , MBBI , DL , get ( Inst . Opc ) , Result ) . addReg ( SrcReg , RegState :: Kill ) . addImm ( Inst . Imm ) . setMIFlag ( Flag ) ; } SrcReg = Result ; }


<s> if ( val == <NUM_LIT> || val == <NUM_LIT> || val == <NUM_LIT> ) return <NUM_LIT> ;


<s> int cur_pos ; cur_pos = <NUM_LIT> ; fprintf ( stream , <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < len ; i ++ ) { int c ; c = ( unsigned char ) string [ i ] ; if ( ISPRINT ( c ) ) { if ( c == '\\' || c == '\"' ) { putc ( '\\' , stream ) ; cur_pos ++ ; }


<s> assert ( II -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( ! TrackedWaitcntSet . count ( & * II ) ) { unsigned OldVSCnt = TII -> getNamedOperand ( * II , <STR_LIT> :: simm16 ) -> getImm ( ) ; Wait . VsCnt = std :: min ( Wait . VsCnt , OldVSCnt ) ; } if ( ! WaitcntVsCntInstr ) { WaitcntVsCntInstr = & * II ; } else { II -> eraseFromParent ( ) ; Modified = true ; } } } if ( WaitcntInstr ) { if ( Wait . hasWaitExceptVsCnt ( ) ) { unsigned NewEnc = <STR_LIT> ( IV , Wait ) ; unsigned OldEnc = WaitcntInstr -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( OldEnc != NewEnc ) { WaitcntInstr -> getOperand ( <NUM_LIT> ) . setImm ( NewEnc ) ; Modified = true ; } ScoreBrackets . applyWaitcnt ( Wait ) ; Wait . VmCnt = ~ <NUM_LIT> ; Wait . LgkmCnt = ~ <NUM_LIT> ; Wait . ExpCnt = ~ <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << * MI << <STR_LIT> << * WaitcntInstr << '\n' ) ; } else { WaitcntInstr -> eraseFromParent ( ) ; Modified = true ; } } if ( WaitcntVsCntInstr ) { if ( Wait . hasWaitVsCnt ( ) ) { assert ( ST -> hasVscnt ( ) ) ; unsigned OldVSCnt = TII -> getNamedOperand ( * WaitcntVsCntInstr , <STR_LIT> :: simm16 ) -> getImm ( ) ; if ( Wait . VsCnt != OldVSCnt ) { TII -> getNamedOperand ( * WaitcntVsCntInstr , <STR_LIT> :: simm16 ) -> setImm ( Wait . VsCnt ) ; Modified = true ; } ScoreBrackets . applyWaitcnt ( Wait ) ; Wait . VsCnt = ~ <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << * MI << <STR_LIT> << * WaitcntVsCntInstr << '\n' ) ; } else { WaitcntVsCntInstr -> eraseFromParent ( ) ; Modified = true ; } } return Modified ;


<s> return isUImm < <NUM_LIT> , <NUM_LIT> > ( ) ;


<s> <ISA_LIT>PreLegalizerCombinerInfo ( bool EnableOpt , bool OptSize , bool MinSize ) : CombinerInfo ( true , false , nullptr , EnableOpt , OptSize , MinSize ) {


<s> collectRedundancyVSETVLIInMF ( MachineFunction & MF ) { for ( auto & MBB : MF ) {


<s> if ( Offset >= ( <NUM_LIT> << <NUM_LIT> ) ) return SDValue ( ) ; const GlobalValue * GV = GN -> getGlobal ( ) ; Type * T = GV -> getValueType ( ) ; if ( ! T -> isSized ( ) || Offset > GV -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( T ) ) return SDValue ( ) ; SDLoc DL ( GN ) ; SDValue Result = DAG . getGlobalAddress ( GV , DL , <STR_LIT> , Offset ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( MinOffset , DL , <STR_LIT> ) ) ;


<s> bool OptSize = Attr . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: MinSize ) ;


<s> if ( ConstantSDNode * RHSC = dyn_cast < ConstantSDNode > ( RHS ) ) { if ( SetCCOpcode == <STR_LIT> && RHSC -> isAllOnesValue ( ) ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return <STR_LIT> ; } if ( SetCCOpcode == <STR_LIT> && RHSC -> isNullValue ( ) ) { return <STR_LIT> ; } if ( SetCCOpcode == <STR_LIT> && RHSC -> isNullValue ( ) ) { return <STR_LIT> ; } if ( SetCCOpcode == <STR_LIT> && RHSC -> getAPIntValue ( ) == <NUM_LIT> ) { RHS = DAG . getConstant ( <NUM_LIT> , DL , RHS . getValueType ( ) ) ; return <STR_LIT> ; } } return TranslateInteger<ISA_LIT>CC ( SetCCOpcode ) ; } if ( <STR_LIT> ( LHS . getNode ( ) ) && ! <STR_LIT> ( RHS . getNode ( ) ) ) { SetCCOpcode = getSetCCSwappedOperands ( SetCCOpcode ) ; std :: swap ( LHS , RHS ) ; } switch ( SetCCOpcode ) { default : break ; case <STR_LIT> : case <STR_LIT> :


<s> auto Status = createLibcall ( MIRBuilder , Libcall . LibcallID , { LibcallResult , RetTy , <NUM_LIT> } , { { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy , <NUM_LIT> } , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , ArgTy , <NUM_LIT> } } ) ; if ( Status != LegalizerHelper :: Legalized ) return false ; auto ProcessedResult = Libcalls . size ( ) == <NUM_LIT> ? OriginalResult : MRI . createGenericVirtualRegister ( MRI . getType ( OriginalResult ) ) ; CmpInst :: Predicate ResultPred = Libcall . Predicate ; if ( ResultPred == CmpInst :: BAD_ICMP_PREDICATE ) { MIRBuilder . buildTrunc ( ProcessedResult , LibcallResult ) ; } else { assert ( CmpInst :: isIntPredicate ( ResultPred ) && <STR_LIT> ) ; auto Zero = MIRBuilder . buildConstant ( LLT :: scalar ( <NUM_LIT> ) , <NUM_LIT> ) ; MIRBuilder . buildICmp ( ResultPred , ProcessedResult , LibcallResult , Zero ) ; } Results . push_back ( ProcessedResult ) ; } if ( Results . size ( ) != <NUM_LIT> ) { assert ( Results . size ( ) == <NUM_LIT> && <STR_LIT> ) ; MIRBuilder . buildOr ( OriginalResult , Results [ <NUM_LIT> ] , Results [ <NUM_LIT> ] ) ; } break ; } case G_FCONSTANT : { auto AsInteger = MI . getOperand ( <NUM_LIT> ) . getFPImm ( ) -> getValueAPF ( ) . bitcastToAPInt ( ) ; MIRBuilder . buildConstant ( MI . getOperand ( <NUM_LIT> ) , * ConstantInt :: get ( Ctx , AsInteger ) ) ; break ;


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( & IfConverterID ) ;


<s> return isUInt < <NUM_LIT> > ( OffsetSize ) ; } case <ISA_LIT>AS :: CONSTANT_ADDRESS : { if ( STI . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) return isUInt < <NUM_LIT> > ( OffsetSize ) ; else return ( OffsetSize % <NUM_LIT> == <NUM_LIT> ) && isUInt < <NUM_LIT> > ( OffsetSize / <NUM_LIT> ) ; } case <ISA_LIT>AS :: LOCAL_ADDRESS : case <ISA_LIT>AS :: REGION_ADDRESS : { return isUInt < <NUM_LIT> > ( OffsetSize ) ; } case <ISA_LIT>AS :: PRIVATE_ADDRESS : default : return <NUM_LIT> ;


<s> static int labelno ; bool needs_tgt = register_operand ( callee , Pmode ) ; rtx pat = PATTERN ( insn ) ; int arg_end = XVECLEN ( pat , <NUM_LIT> ) ; tree decl = NULL_TREE ; fprintf ( asm_out_file , <STR_LIT> ) ; if ( result != NULL ) fprintf ( asm_out_file , <STR_LIT> , nvptx_ptx_type_from_mode ( GET_MODE ( result ) , false ) , reg_names [ NVPTX_RETURN_REGNUM ] ) ; if ( GET_CODE ( callee ) == SYMBOL_REF ) { decl = SYMBOL_REF_DECL ( callee ) ; if ( ! decl || ( DECL_EXTERNAL ( decl ) && ! TYPE_ARG_TYPES ( TREE_TYPE ( decl ) ) ) ) nvptx_record_libfunc ( callee , result , pat ) ; else if ( DECL_EXTERNAL ( decl ) ) nvptx_record_fndecl ( decl ) ; } if ( needs_tgt ) { ASM_GENERATE_INTERNAL_LABEL ( buf , <STR_LIT> , labelno ) ; labelno ++ ; ASM_OUTPUT_LABEL ( asm_out_file , buf ) ; std :: stringstream s ; write_fn_proto_from_insn ( s , NULL , result , pat ) ; fputs ( s . str ( ) . c_str ( ) , asm_out_file ) ; } for ( int argno = <NUM_LIT> ; argno < arg_end ; argno ++ ) { rtx t = XEXP ( XVECEXP ( pat , <NUM_LIT> , argno ) , <NUM_LIT> ) ; machine_mode mode = GET_MODE ( t ) ; const char * ptx_type = nvptx_ptx_type_from_mode ( mode , false ) ; fprintf ( asm_out_file , <STR_LIT> <STR_LIT> , ptx_type , argno , ptx_type , argno ) ; output_reg ( asm_out_file , REGNO ( t ) , VOIDmode ) ; fprintf ( asm_out_file , <STR_LIT> ) ; } fprintf ( asm_out_file , <STR_LIT> ) ; if ( result != NULL_RTX ) fprintf ( asm_out_file , <STR_LIT> , reg_names [ NVPTX_RETURN_REGNUM ] ) ; if ( decl ) { const char * name = get_fnname_from_decl ( decl ) ; name = nvptx_name_replacement ( name ) ; assemble_name ( asm_out_file , name ) ; } else output_address ( VOIDmode , callee ) ; const char * open = <STR_LIT> ; for ( int argno = <NUM_LIT> ; argno < arg_end ; argno ++ ) { fprintf ( asm_out_file , <STR_LIT> , open , argno ) ; open = <STR_LIT> ; } if ( decl && DECL_STATIC_CHAIN ( decl ) ) { fprintf ( asm_out_file , <STR_LIT> , open , reg_names [ STATIC_CHAIN_REGNUM ] ) ; open = <STR_LIT> ; }

if ( ! open [ <NUM_LIT> ] ) fprintf ( asm_out_file , <STR_LIT> ) ;


<s> if ( GET_CODE ( src ) == SIGN_EXTEND ) { fusion = SCHED_FUSION_LD_SIGN_EXTEND ; src = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } else if ( GET_CODE ( src ) == ZERO_EXTEND ) { fusion = SCHED_FUSION_LD_ZERO_EXTEND ; src = XEXP ( src , <NUM_LIT> ) ; if ( GET_CODE ( src ) != MEM || GET_MODE ( src ) != SImode ) return SCHED_FUSION_NONE ; } if ( GET_CODE ( src ) == MEM && REG_P ( dest ) ) extract_base_offset_in_addr ( src , base , offset ) ; else if ( GET_CODE ( dest ) == MEM && ( REG_P ( src ) || src == const0_rtx ) ) { fusion = SCHED_FUSION_ST ; extract_base_offset_in_addr ( dest , base , offset ) ; } else return SCHED_FUSION_NONE ; if ( * base == NULL_RTX || * offset == NULL_RTX ) fusion = SCHED_FUSION_NONE ; return fusion ;


<s> case UNSPEC_GOT : case UNSPEC_GOTOFF : case UNSPEC_PLT : case UNSPEC_TLSGD : case UNSPEC_TLSLD : case UNSPEC_TLSIE : case UNSPEC_TLSLE : case UNSPEC_ICT : x = XVECEXP ( inner , <NUM_LIT> , <NUM_LIT> ) ; break ; default : break ; } } } return x ;


<s> return sh_movt_set_dest ( i ) != NULL ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSet<ISA_LIT>32R2 ( ) {


<s> return static_cast < MCELFStreamer & > ( Streamer ) ;


<s> StringRef getPassName ( ) const override { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return <STR_LIT> ;


<s> getParser ( ) . getStreamer ( ) . EmitThumbFunc ( Symbol ) ; NextSymbolIsThumb = false ; }


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : FPStackOffset ( <NUM_LIT> ) , RAStackOffset ( <NUM_LIT> ) , CPUTopSavedRegOff ( <NUM_LIT> ) , GPHolder ( - <NUM_LIT> , - <NUM_LIT> ) , HasLoadArgs ( false ) , HasStoreVarArgs ( false ) , SRetReturnReg ( <NUM_LIT> ) , GlobalBaseReg ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) {


<s> static EVT getVectorTyFromPredicateVector ( EVT VT ) {

switch ( VT . getSimpleVT ( ) . SimpleTy ) {


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ;

Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant ( ) , getKind ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerSINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { SDValue Src = Op . getOperand ( <NUM_LIT> ) ; MVT SrcVT = Src . getSimpleValueType ( ) ; MVT VT = Op . getSimpleValueType ( ) ; SDLoc dl ( Op ) ; if ( SDValue Extract = vectorizeExtractedCast ( Op , DAG , Subtarget ) ) return Extract ; if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && VT == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getUNDEF ( SrcVT ) ) ) ; } return SDValue ( ) ; } assert ( SrcVT <= <STR_LIT> && SrcVT >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( VT ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( VT ) && Subtarget . is64Bit ( ) ) return Op ; if ( SDValue V = LowerI64IntToFP_AVX512DQ ( Op , DAG , Subtarget ) ) return V ; SDValue ValueToStore = Op . getOperand ( <NUM_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( VT ) && ! Subtarget . is64Bit ( ) ) ValueToStore = DAG . getBitcast ( <STR_LIT> , ValueToStore ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; int SSFI = MF . getFrameInfo ( ) . CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , ValueToStore , StackSlot , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , SSFI ) ) ;

return BuildFILD ( Op , SrcVT , Chain , StackSlot , DAG ) ;


<s> unsigned Imm , WhichResult ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; return ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTBLMask ( M , VT ) || isNEONTwoResultShuffleMask ( M , VT , WhichResult , isV_UNDEF ) || ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && isReverseMask ( M , VT ) ) ) ;


<s> const MachineOperand & Src = MI -> getOperand ( <NUM_LIT> ) ; const MachineOperand & Dest = MI -> getOperand ( <NUM_LIT> ) ; NewMI = BuildMI ( * MF , MI -> getDebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ) . addOperand ( Dest ) . addOperand ( Src ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; MFI -> insert ( MBBI , NewMI ) ; return NewMI ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>ExpandCondsets :: isRefInMap ( RegisterRef RR , ReferenceMap & Map , unsigned Exec ) { ReferenceMap :: iterator F = Map . find ( RR . Reg ) ;

if ( F == Map . end ( ) ) return false ;


<s> case SFmode : return <NUM_LIT> ; case DFmode : return <NUM_LIT> ; case XFmode : return <NUM_LIT> ; case TImode : return SPEC_MODE_INVALID ; default : return SPEC_MODE_INVALID ; }


<s> if ( ! <STR_LIT> . contains ( DestReg , SrcReg ) ) return <ISA_LIT>BaseInstrInfo :: copyPhysReg ( MBB , I , DL , DestReg , SrcReg , KillSrc ) ;

AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ) ;


<s> emitFPU = true ; } else { MCObjectStreamer & O = static_cast < MCObjectStreamer & > ( OutStreamer ) ; AttrEmitter = new ObjectAttributeEmitter ( O ) ; } AttrEmitter -> MaybeSwitchVendor ( <STR_LIT> ) ; std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString == <STR_LIT> || Subtarget -> isCortexA8 ( ) ) { AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( CPUString == <STR_LIT> ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; } if ( Subtarget -> hasNEON ( ) && emitFPU ) { if ( Subtarget -> hasNEON2 ( ) ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; else AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; emitFPU = false ; } if ( Subtarget -> hasVFP4 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP3 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; } else if ( Subtarget -> hasVFP2 ( ) ) { AttrEmitter -> EmitAttribute ( <STR_LIT> , <STR_LIT> ) ; if ( emitFPU ) AttrEmitter -> EmitTextAttribute ( <STR_LIT> , <STR_LIT> ) ; }


<s> return D ( <STR_LIT> , R ( a ) , R ( b ) , <STR_LIT> ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> void <ISA_LIT>InstPrinter :: printThumbAddrModeS1Operand ( const MCInst * MI , unsigned Op , raw_ostream & O ) { printThumbAddrModeRI5Operand ( MI , Op , O , <NUM_LIT> ) ;


<s> if ( MinAlign == <NUM_LIT> ) return Type :: getInt16Ty ( Context ) ;

if ( SrcAddrSpace == <ISA_LIT>AS :: LOCAL_ADDRESS || SrcAddrSpace == <ISA_LIT>AS :: REGION_ADDRESS || DestAddrSpace == <ISA_LIT>AS :: LOCAL_ADDRESS || DestAddrSpace == <ISA_LIT>AS :: REGION_ADDRESS ) {


<s> return gen_symGOT2reg ( dest , gp_sym , src , GEN_INT ( R_FRV_GOT12 ) ) ;


<s> <ISA_LIT>SelectionDAGInfo :: <ISA_LIT>SelectionDAGInfo ( const <ISA_LIT>TargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) {


<s> if ( mode == DFmode ) gregno += ( <NUM_LIT> - gregno ) & <NUM_LIT> ; if ( gregno + n_words - <NUM_LIT> > GP_ARG_MAX_REG ) return NULL_RTX ; return spe_build_register_parallel ( mode , gregno ) ; } if ( cum -> stdarg ) { int n_words = rs6000_arg_size ( mode , type ) ; if ( n_words == <NUM_LIT> && ( gregno & <NUM_LIT> ) == <NUM_LIT> ) gregno += <NUM_LIT> ; if ( gregno + n_words - <NUM_LIT> <= GP_ARG_MAX_REG ) { rtx r1 , r2 ; machine_mode m = SImode ; r1 = gen_rtx_REG ( m , gregno ) ; r1 = gen_rtx_EXPR_LIST ( m , r1 , const0_rtx ) ; r2 = gen_rtx_REG ( m , gregno + <NUM_LIT> ) ; r2 = gen_rtx_EXPR_LIST ( m , r2 , GEN_INT ( <NUM_LIT> ) ) ; return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , r1 , r2 ) ) ;


<s> if ( flag_modulo_sched ) flag_resched_modulo_sched = <NUM_LIT> ;


<s> unsigned Size = Ty . getSizeInBits ( ) ; assert ( ( Size == <NUM_LIT> || Size == <NUM_LIT> ) && <STR_LIT> ) ; bool Is32Bit = Size == <NUM_LIT> ; if ( auto Fns = selectArithImmed ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ; if ( auto Fns = selectShiftedRegister ( RHS ) ) return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS } , MIRBuilder , Fns ) ;

return emitInstr ( AddrModeAndSizeToOpcode [ <NUM_LIT> ] [ Is32Bit ] , { Dst } , { LHS , RHS } , MIRBuilder ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { unsigned char OpFlags = Subtarget -> ClassifyBlockAddressReference ( ) ; CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; int64_t Offset = cast < BlockAddressSDNode > ( Op ) -> getOffset ( ) ; SDLoc dl ( Op ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( ) , Offset , OpFlags ) ;

if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> if ( Rn == <NUM_LIT> ) S = MCDisassembler :: SoftFail ; if ( ! Check ( S , DecodeGPRPairRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecodePredicateOperand ( Inst , pred , Address , Decoder ) ) ) return MCDisassembler :: Fail ; return S ;


<s> return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ;


<s> if ( ! compute_offset_order ( nops , unsorted_offsets , order , check_regs ? unsorted_regs : NULL ) ) return <NUM_LIT> ; if ( saved_order ) memcpy ( saved_order , order , sizeof order ) ; if ( base ) { * base = base_reg ; for ( i = <NUM_LIT> ; i < nops ; i ++ ) { regs [ i ] = unsorted_regs [ check_regs ? order [ i ] : i ] ; if ( reg_rtxs ) reg_rtxs [ i ] = unsorted_reg_rtxs [ check_regs ? order [ i ] : i ] ; } * load_offset = unsorted_offsets [ order [ <NUM_LIT> ] ] ; } if ( TARGET_THUMB1 && ! peep2_reg_dead_p ( nops_total , base_reg_rtx ) ) return <NUM_LIT> ; if ( unsorted_offsets [ order [ <NUM_LIT> ] ] == <NUM_LIT> ) stm_case = <NUM_LIT> ; else if ( TARGET_ARM && unsorted_offsets [ order [ <NUM_LIT> ] ] == <NUM_LIT> ) stm_case = <NUM_LIT> ; else if ( TARGET_ARM && unsorted_offsets [ order [ nops - <NUM_LIT> ] ] == <NUM_LIT> ) stm_case = <NUM_LIT> ; else if ( TARGET_32BIT && unsorted_offsets [ order [ nops - <NUM_LIT> ] ] == - <NUM_LIT> ) stm_case = <NUM_LIT> ; else return <NUM_LIT> ; if ( ! multiple_operation_profitable_p ( false , nops , <NUM_LIT> ) ) return <NUM_LIT> ; return stm_case ;


<s> if ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) >= <NUM_LIT> ) fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; } else gcc_unreachable ( ) ; break ; case MINUS : x = simplify_subtraction ( x ) ; if ( GET_CODE ( x ) != MINUS ) goto restart ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; if ( GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST_INT && INTVAL ( XEXP ( x , <NUM_LIT> ) ) < <NUM_LIT> ) { fprintf ( file , <STR_LIT> ) ; arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; fprintf ( file , <STR_LIT> ) ; } else arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; break ; case ZERO_EXTEND : case SIGN_EXTEND : arc_output_pic_addr_const ( file , XEXP ( x , <NUM_LIT> ) , code ) ; break ; case UNSPEC : const char * suffix ; bool pcrel ; pcrel = false ; rtx base ; base = NULL ; gcc_assert ( XVECLEN ( x , <NUM_LIT> ) >= <NUM_LIT> ) ; switch ( XINT ( x , <NUM_LIT> ) ) { case ARC_UNSPEC_GOT : suffix = <STR_LIT> , pcrel = true ; break ; case ARC_UNSPEC_GOTOFF : suffix = <STR_LIT> ; break ; case ARC_UNSPEC_GOTOFFPC : suffix = <STR_LIT> , pcrel = true ; break ; case ARC_UNSPEC_PLT : suffix = <STR_LIT> ; break ; case UNSPEC_TLS_GD : suffix = <STR_LIT> , pcrel = true ; break ; case UNSPEC_TLS_IE : suffix = <STR_LIT> , pcrel = true ; break ; case UNSPEC_TLS_OFF : if ( XVECLEN ( x , <NUM_LIT> ) == <NUM_LIT> ) base = XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ; if ( SYMBOL_REF_TLS_MODEL ( XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) == TLS_MODEL_LOCAL_EXEC || ( ! flag_pic && ! base ) ) suffix = <STR_LIT> ; else suffix = <STR_LIT> ; break ; default : suffix = <STR_LIT> ; output_operand_lossage ( <STR_LIT> , XINT ( x , <NUM_LIT> ) ) ;


<s> MachineBasicBlock * <ISA_LIT>InstrInfo :: getBranchDestBlock ( const MachineInstr & MI ) const { assert ( MI . getDesc ( ) . isBranch ( ) && <STR_LIT> ) ;

return MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> assert ( ! STI . getFeatureBits ( ) [ llvm :: <STR_LIT> ] && <STR_LIT> ) ; assert ( MI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; bool ListContainsPC = false , ListContainsLR = false ; for ( unsigned OI = <NUM_LIT> , OE = MI . getNumOperands ( ) ; OI < OE ; ++ OI ) {

assert ( MI . getOperand ( OI ) . isReg ( ) && <STR_LIT> ) ;


<s> BitGroup ( SDValue V , unsigned R , unsigned S , unsigned E ) : V ( V ) , RLAmt ( R ) , StartIdx ( S ) , EndIdx ( E ) , Repl32 ( false ) , Repl32CR ( false ) , Repl32Coalesced ( false ) {

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << V . getNode ( ) << <STR_LIT> << R << <STR_LIT> << S << <STR_LIT> << E << <STR_LIT> ) ;


<s> bool shouldExpandReduction ( const IntrinsicInst * II ) const { return false ;


<s> if ( isThumb2 ( STI ) ) { EncodedValue |= <NUM_LIT> ; }


<s> size = ( <NUM_LIT> + h8300_constant_length ( offset ) + h8300_classify_operand ( src , GET_MODE_SIZE ( GET_MODE ( src ) ) , <NUM_LIT> ) ) ; if ( ! REG_P ( dest ) || ! REG_P ( src ) || REGNO ( src ) != REGNO ( dest ) ) size += <NUM_LIT> ;


<s> unsigned Idx = WhichResult ; for ( unsigned k = <NUM_LIT> ; k < Half ; ++ k ) { int MIdx = M [ i + j + k ] ; if ( MIdx >= <NUM_LIT> && ( unsigned ) MIdx != Idx ) return false ; Idx += <NUM_LIT> ; } } } if ( M . size ( ) == NumElts * <NUM_LIT> ) WhichResult = <NUM_LIT> ; if ( VT . is64BitVector ( ) && EltSz == <NUM_LIT> ) return false ; return true ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ;

Init<ISA_LIT>MCRegisterInfo ( X , <NUM_LIT> ) ;


<s> if ( crtl -> args . size <= <NUM_LIT> && crtl -> args . size != - <NUM_LIT> ) { if ( layout . frame_size - INCOMING_FRAME_SP_OFFSET + crtl -> args . size <= <NUM_LIT> ) layout . fp_minus_ap = layout . frame_size - INCOMING_FRAME_SP_OFFSET ; else layout . fp_minus_ap = <NUM_LIT> - crtl -> args . size ; } else layout . fp_minus_ap = ( layout . stdarg_save_size + layout . register_save_size - INCOMING_FRAME_SP_OFFSET ) ; layout . sp_minus_fp = ( layout . frame_size - INCOMING_FRAME_SP_OFFSET - layout . fp_minus_ap ) ;

layout . first_local_minus_ap = layout . sp_minus_fp - layout . locals_size ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm ) : SelectionDAGISel ( tm ) , TM ( tm ) {


<s> const TargetRegisterClass * CopyRC = ( SrcVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( MBB , DL , TII . get ( CopyOpc ) , CopyReg ) . addReg ( InputReg ) ; unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , CopyReg , <STR_LIT> ) ; if ( ! ResultReg ) return false ; UpdateValueMap ( I , ResultReg ) ;


<s> if ( Cond . size ( ) != <NUM_LIT> ) return false ; if ( Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getReg ( ) == <STR_LIT> ) return false ; const MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; const TargetRegisterClass * RC = RI . getCommonSubClass ( MRI . getRegClass ( TrueReg ) , MRI . getRegClass ( FalseReg ) ) ; if ( ! RC ) return false ; if ( ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) && ! <STR_LIT> . hasSubClassEq ( RC ) ) return false ; CondCycles = <NUM_LIT> ;


<s> for ( const auto & Function : M ) TLOF . emitLinkerFlagsForGlobal ( OS , & Function ) ; for ( const auto & Global : M . globals ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Global ) ; for ( const auto & Alias : M . aliases ( ) ) TLOF . emitLinkerFlagsForGlobal ( OS , & Alias ) ; OS . flush ( ) ;


<s> void <ISA_LIT>Subtarget :: initSubtargetFeatures ( StringRef CPU , StringRef FS ) { std :: string <ISA_LIT>Name = CPU ; if ( <ISA_LIT>Name . empty ( ) ) <ISA_LIT>Name = <STR_LIT> ; std :: string FullFS = FS ;

ParseSubtargetFeatures ( <ISA_LIT>Name , FullFS ) ;


<s> range ++ ; uses = BitVector ( range ) ;


<s> return ( int8x8_t ) __builtin_aarch64_srshr_nv8qi ( __a , __b ) ;


<s> default : if ( ST -> getGeneration ( ) <= <ISA_LIT>Subtarget :: NORTHERN_ISLANDS && ( AddrSpace == <ISA_LIT>AS :: PARAM_D_ADDRESS || AddrSpace == <ISA_LIT>AS :: PARAM_I_ADDRESS || ( AddrSpace >= <ISA_LIT>AS :: CONSTANT_BUFFER_0 && AddrSpace <= <ISA_LIT>AS :: CONSTANT_BUFFER_15 ) ) ) return <NUM_LIT> ;


<s> if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( Subtarget . hasSSE4A ( ) ) if ( SDValue V = lowerVectorShuffleWithSSE4A ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return V ; if ( NumV2Inputs == <NUM_LIT> ) if ( SDValue V = lowerVectorShuffleAsElementInsertion ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return V ; bool IsBlendSupported = Subtarget . hasSSE41 ( ) ; if ( IsBlendSupported ) if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ; if ( SDValue Masked = lowerVectorShuffleAsBitMask ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , DAG ) ) return Masked ; if ( SDValue V = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return V ; if ( SDValue V = lowerVectorShuffleWithPACK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG , Subtarget ) ) return V ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ;

if ( SDValue BitBlend = lowerVectorShuffleAsBitBlend ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return BitBlend ;


<s> int <ISA_LIT>TTIImpl :: getCastInstrCost ( unsigned Opcode , Type * Dst , Type * Src , const Instruction * I ) {

assert ( TLI -> InstructionOpcodeToISD ( Opcode ) && <STR_LIT> ) ;


<s> return <NUM_LIT> ; } mreg = force_reg ( SImode , GEN_INT ( ~ ( ( ( <NUM_LIT> << width ) - <NUM_LIT> ) << posn ) ) ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , gen_rtx_AND ( SImode , operands [ <NUM_LIT> ] , mreg ) ) ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) return <NUM_LIT> ; sreg = copy_to_mode_reg ( SImode , operands [ <NUM_LIT> ] ) ; if ( width + posn != ( int ) GET_MODE_SIZE ( SImode ) ) { ereg = force_reg ( SImode , GEN_INT ( ( <NUM_LIT> << width ) - <NUM_LIT> ) ) ; emit_insn ( gen_rtx_SET ( sreg , gen_rtx_AND ( SImode , sreg , ereg ) ) ) ; }

if ( posn != <NUM_LIT> ) emit_insn ( gen_rtx_SET ( sreg , gen_rtx_ASHIFT ( SImode , sreg , GEN_INT ( posn ) ) ) ) ;


<s> static <ISA_LIT>MCExpr :: VariantKind Variants [ ] = { <ISA_LIT>MCExpr :: VK_ABS_G0_NC , <ISA_LIT>MCExpr :: VK_GOTTPREL_G0_NC , <ISA_LIT>MCExpr :: VK_TPREL_G0_NC , <ISA_LIT>MCExpr :: VK_DTPREL_G0_NC } ;


<s> return CSR_Interrupt_RegMask ; } switch ( Subtarget . getTargetABI ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32_LP64_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32F_LP64F_RegMask ; case <STR_LIT> : case <STR_LIT> : return CSR_ILP32D_LP64D_RegMask ;


<s> DebugLoc DL ; unsigned V0 , V1 ; const TargetRegisterClass * RC ; const <ISA_LIT>ABIInfo & ABI = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) ; RC = ( ABI . IsN64 ( ) ) ? & <STR_LIT> : & <STR_LIT> ; V0 = RegInfo . createVirtualRegister ( RC ) ; V1 = RegInfo . createVirtualRegister ( RC ) ; if ( ABI . IsN64 ( ) ) { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; const GlobalValue * FName = & MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; return ; } if ( ! MF . getTarget ( ) . isPositionIndependent ( ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V0 ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ; return ; } MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; if ( ABI . IsN32 ( ) ) { const GlobalValue * FName = & MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; return ; } assert ( ABI . IsO32 ( ) ) ; MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> if ( XFI -> isLargeFrame ( MF ) || hasFP ( MF ) ) RS -> addScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ; if ( XFI -> isLargeFrame ( MF ) && ! hasFP ( MF ) ) RS -> addScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ;


<s> <STR_LIT> NewExtType = N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; if ( LD -> getExtensionType ( ) != <STR_LIT> && LD -> getExtensionType ( ) != <STR_LIT> && LD -> getExtensionType ( ) != NewExtType ) return SDValue ( ) ; LLVMContext & C = * DAG . getContext ( ) ; SDLoc DL ( LD ) ; SDValue Ch = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; Align Alignment = LD -> getOriginalAlign ( ) ; MachineMemOperand :: Flags MMOFlags = LD -> getMemOperand ( ) -> getFlags ( ) ; AAMDNodes AAInfo = LD -> getAAInfo ( ) ; SDValue Offset = DAG . getUNDEF ( BasePtr . getValueType ( ) ) ; EVT NewFromVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , FromEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; EVT NewToVT = EVT :: getVectorVT ( C , EVT :: getIntegerVT ( C , ToEltVT . getScalarSizeInBits ( ) ) , NumElements ) ; SmallVector < SDValue , <NUM_LIT> > Loads ; SmallVector < SDValue , <NUM_LIT> > Chains ; for ( unsigned i = <NUM_LIT> ; i < FromVT . getVectorNumElements ( ) / NumElements ; i ++ ) { unsigned NewOffset = ( i * NewFromVT . getSizeInBits ( ) ) / <NUM_LIT> ; SDValue NewPtr = DAG . getObjectPtrOffset ( DL , BasePtr , TypeSize :: Fixed ( NewOffset ) ) ; SDValue NewLoad = DAG . getLoad ( <STR_LIT> , NewExtType , NewToVT , DL , Ch , NewPtr , Offset , LD -> getPointerInfo ( ) . getWithOffset ( NewOffset ) , NewFromVT , Alignment , MMOFlags , AAInfo ) ; Loads . push_back ( NewLoad ) ; Chains . push_back ( SDValue ( NewLoad . getNode ( ) , <NUM_LIT> ) ) ; }

SDValue NewChain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chains ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>leTarget ( ) ) ; RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Y ( getThe<ISA_LIT>beTarget ( ) ) ;

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > Z ( getTheARM64Target ( ) ) ;


<s> Header . amd_kernel_code_version_minor = <NUM_LIT> ; Header . amd_machine_kind = <NUM_LIT> ; Header . amd_machine_version_major = Version . Major ; Header . amd_machine_version_minor = Version . Minor ; Header . amd_machine_version_stepping = Version . Stepping ; Header . kernel_code_entry_byte_offset = sizeof ( Header ) ; Header . wavefront_size = <NUM_LIT> ; Header . call_convention = - <NUM_LIT> ;

Header . kernarg_segment_alignment = <NUM_LIT> ;


<s> case REG_X : return <STR_LIT> ; case REG_Y : return <STR_LIT> ; case REG_Z : return <STR_LIT> ; default : gcc_unreachable ( ) ; } return NULL ;


<s> void <ISA_LIT>InstPrinter :: printFBits32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) {

O << markup ( <STR_LIT> ) << <STR_LIT> << <NUM_LIT> - MI -> getOperand ( OpNum ) . getImm ( ) << markup ( <STR_LIT> ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> pConfig . attribute ( ) . predefined ( ) . unsetWholeArchive ( ) ; pConfig . attribute ( ) . predefined ( ) . unsetAsNeeded ( ) ; pConfig . attribute ( ) . predefined ( ) . setDynamic ( ) ; return true ;


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return DstVT != <STR_LIT> || Subtarget . is16Bit ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> unsigned STmp0 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; unsigned STmp1 = RS -> scavengeRegister ( & <STR_LIT> , <NUM_LIT> ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp0 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Z ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( InputPtrReg ) . addImm ( <STR_LIT> :: NGROUPS_Y ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , STmp1 ) . addReg ( STmp1 ) . addReg ( STmp0 ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp1 ) . addReg ( TIDIGXReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( STmp0 ) . addReg ( TIDIGYReg ) . addReg ( TIDReg ) ; BuildMI ( Entry , Insert , DL , get ( <STR_LIT> ) , TIDReg ) . addReg ( TIDReg ) . addReg ( TIDIGZReg ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> CCValAssign & VA = ArgLocs [ i ] ; const Value * ArgVal = Args [ VA . getValNo ( ) ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: BCvt : { unsigned BC = fastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { assert ( VA . getLocVT ( ) == <STR_LIT> && <STR_LIT> ) ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; assert ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) && <STR_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , VA . getLocReg ( ) ) . addReg ( NextVA . getLocReg ( ) , RegState :: Define ) . addReg ( Arg ) ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; RegArgs . push_back ( NextVA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; Address Addr ; Addr . BaseType = Address :: RegBase ; Addr . Base . Reg = <STR_LIT> ; Addr . Offset = VA . getLocMemOffset ( ) ; bool EmitRet = <ISA_LIT>EmitStore ( ArgVT , Arg , Addr ) ; ( void ) EmitRet ; assert ( EmitRet && <STR_LIT> ) ; }


<s> static DecodeStatus DecodePRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( PRegsTable [ RegNo ] ) ) ; return MCDisassembler :: Success ;


<s> return static_cast < MCELFStreamer & > ( Streamer ) ;


<s> const MCOperand MO = MI -> getOperand ( OpNum ) ; if ( MO . isImm ( ) ) {

O << <STR_LIT> << formatImm ( MO . getImm ( ) * Scale ) ;


<s> if ( ! CostFactor . isValid ( ) ) return InstructionCost :: getMax ( ) ;

if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo , Args , CxtI ) ;


<s> void <ISA_LIT>LowerControlFlow :: findMaskOperands ( MachineInstr & MI , unsigned OpNo , SmallVectorImpl < MachineOperand > & Src ) const { MachineOperand & Op = MI . getOperand ( OpNo ) ; if ( ! Op . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( Op . getReg ( ) ) ) { Src . push_back ( Op ) ; return ; } MachineInstr * Def = MRI -> getUniqueVRegDef ( Op . getReg ( ) ) ; if ( ! Def || Def -> getParent ( ) != MI . getParent ( ) || ! ( Def -> isFullCopy ( ) || ( Def -> getOpcode ( ) == MI . getOpcode ( ) ) ) ) return ; for ( auto I = Def -> getIterator ( ) ; I != MI . getIterator ( ) ; ++ I ) if ( I -> modifiesRegister ( <STR_LIT> , TRI ) && ! ( I -> isCopy ( ) && I -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) ) return ;

for ( const auto & SrcOp : Def -> explicit_operands ( ) ) if ( SrcOp . isUse ( ) && ( ! SrcOp . isReg ( ) || TargetRegisterInfo :: isVirtualRegister ( SrcOp . getReg ( ) ) || SrcOp . getReg ( ) == <STR_LIT> ) ) Src . push_back ( SrcOp ) ;


<s> if ( Subtarget . hasAVX2 ( ) && V2 . isUndef ( ) ) return SDValue ( ) ; MVT SubVT = <STR_LIT> ( VT . getVectorElementType ( ) , VT . getVectorNumElements ( ) / <NUM_LIT> ) ; SDValue LoV = DAG . getNode ( <STR_LIT> , DL , SubVT , V1 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; SDValue HiV = DAG . getNode ( <STR_LIT> , DL , SubVT , OnlyUsesV1 ? V1 : V2 , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LoV , HiV ) ; } } int MaskLO = Mask [ <NUM_LIT> ] ; if ( MaskLO == SM_SentinelUndef ) MaskLO = Mask [ <NUM_LIT> ] == SM_SentinelUndef ? <NUM_LIT> : Mask [ <NUM_LIT> ] ; int MaskHI = Mask [ <NUM_LIT> ] ; if ( MaskHI == SM_SentinelUndef ) MaskHI = Mask [ <NUM_LIT> ] == SM_SentinelUndef ? <NUM_LIT> : Mask [ <NUM_LIT> ] ; unsigned PermMask = MaskLO / <NUM_LIT> | ( MaskHI / <NUM_LIT> ) << <NUM_LIT> ; if ( IsV1Zero ) { V1 = DAG . getUNDEF ( VT ) ; if ( MaskLO < <NUM_LIT> ) PermMask = ( PermMask & <NUM_LIT> ) | <NUM_LIT> ;

if ( MaskHI < <NUM_LIT> ) PermMask = ( PermMask & <NUM_LIT> ) | <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerVACOPY ( SDValue Op , SelectionDAG & DAG ) const { const Value * DestSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getMemcpy ( Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <NUM_LIT> , false , false , MachinePointerInfo ( DestSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> void emitBundleLock ( bool AlignToEnd ) override {


<s> bool <ISA_LIT>InstrInfo :: isReallyTriviallyReMaterializable ( const MachineInstr & MI , AAResults * AA ) const { switch ( MI . getOpcode ( ) ) {


<s> FastISel * <STR_LIT> ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) { return new <ISA_LIT>FastISel ( FuncInfo , LibInfo ) ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getGatherScatterOpCost ( unsigned Opcode , Type * DataTy , const Value * Ptr , bool VariableMask , Align Alignment , TTI :: TargetCostKind CostKind , const Instruction * I ) { if ( useNeonVector ( DataTy ) ) return BaseT :: getGatherScatterOpCost ( Opcode , DataTy , Ptr , VariableMask , Alignment , CostKind , I ) ; auto * VT = cast < VectorType > ( DataTy ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , DataTy ) ; if ( ! LT . first . isValid ( ) ) return InstructionCost :: getInvalid ( ) ; if ( cast < VectorType > ( DataTy ) -> getElementCount ( ) == ElementCount :: getScalable ( <NUM_LIT> ) ) return InstructionCost :: getInvalid ( ) ; ElementCount LegalVF = LT . second . getVectorElementCount ( ) ; InstructionCost MemOpCost = getMemoryOpCost ( Opcode , VT -> getElementType ( ) , Alignment , <NUM_LIT> , CostKind , I ) ; MemOpCost *= getSVEGatherScatterOverhead ( Opcode ) ;

return LT . first * MemOpCost * getMaxNumElements ( LegalVF ) ;


<s> ItaniumMangler ( bool useAddrSpace ) : UseAddrSpace ( useAddrSpace ) {


<s> void resetUnwindDirectiveParserState ( ) { FnStartLoc = SMLoc ( ) ; CantUnwindLoc = SMLoc ( ) ; PersonalityLoc = SMLoc ( ) ; HandlerDataLoc = SMLoc ( ) ;


<s> LiveRegs . addReg ( SpillReg ) ; MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister ( MF -> getRegInfo ( ) , LiveRegs , <STR_LIT> ) ; BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( Offset ) ;

BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( SpillReg , RegState :: Kill ) . addReg ( OffsetReg , RegState :: Kill ) . addReg ( ScratchRsrcReg ) . addReg ( SPReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> void expand_cbranchsi4 ( rtx * operands , enum rtx_code comparison , int probability ) { rtx ( * branch_expander ) ( rtx ) = gen_branch_true ; comparison = prepare_cbranch_operands ( operands , SImode , comparison ) ; switch ( comparison ) { case NE : case LT : case LE : case LTU : case LEU : comparison = reverse_condition ( comparison ) ; branch_expander = gen_branch_false ; default : ;


<s> break ; case E_HImode : shift_mode = HIshift ; break ; case E_SImode : shift_mode = SIshift ; break ; default : gcc_unreachable ( ) ; } switch ( code ) { case ASHIFTRT : shift_type = SHIFT_ASHIFTRT ; break ; case LSHIFTRT : shift_type = SHIFT_LSHIFTRT ; break ; case ASHIFT : shift_type = SHIFT_ASHIFT ; break ; default : gcc_unreachable ( ) ; } gcc_assert ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT ) ; n = INTVAL ( operands [ <NUM_LIT> ] ) ; if ( n < <NUM_LIT> ) n = <NUM_LIT> ; else if ( ( unsigned int ) n > GET_MODE_BITSIZE ( mode ) ) n = GET_MODE_BITSIZE ( mode ) ; get_shift_alg ( shift_type , shift_mode , n , & info ) ; switch ( info . alg ) { case SHIFT_SPECIAL : if ( info . remainder == <NUM_LIT> ) return ( info . cc_special == OLD_CC_SET_ZN || info . cc_special == OLD_CC_SET_ZNV ) ; case SHIFT_INLINE : return ( info . cc_inline == OLD_CC_SET_ZN || info . cc_inline == OLD_CC_SET_ZNV ) ; case SHIFT_ROT_AND :


<s> if ( it == m_ExIdxToTuple . end ( ) ) {


<s> if ( ! Subtarget -> in<ISA_LIT>16Mode ( ) ) return false ;

return <ISA_LIT>DAGToDAGISel :: runOnMachineFunction ( MF ) ;


return ( uint32x4_t ) __builtin_neon_vdup_nv4si ( ( __builtin_neon_si ) __a ) ;


<s> for ( auto & C : BaseAICalls ) Transformed = transformGEPChain ( M , C . first , C . second ) || Transformed ; } return removePreserveAccessIndexIntrinsic ( M ) || Transformed ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumEntries - <NUM_LIT> ; ++ i ) assert ( NEONLdStTable [ i ] < NEONLdStTable [ i + <NUM_LIT> ] && <STR_LIT> ) ; TableChecked = true ; } const NEONLdStTableEntry * I = std :: lower_bound ( NEONLdStTable , NEONLdStTable + NumEntries , Opcode ) ; if ( I != NEONLdStTable + NumEntries && I -> PseudoOpc == Opcode ) return I ; return nullptr ;


<s> MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , AMDGPU :: MOV , AddrReg , ValueReg ) . addReg ( AMDGPU :: AR_X , RegState :: Implicit | RegState :: Kill ) ; setImmOperand ( Mov , AMDGPU :: OpName :: dst_rel , <NUM_LIT> ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const override { return getSubtargetImpl ( ) -> getInstrInfo ( ) ;


<s> bool <ISA_LIT>PassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ;


<s> static machine_mode s390_unwind_word_mode ( void ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> emit_insn ( gen_rtx_SET ( VOIDmode , new_out , x ) ) ; x = gen_rtx_NOT ( wmode , new_out ) ; emit_insn ( gen_rtx_SET ( VOIDmode , new_out , x ) ) ; break ; case MINUS : if ( CONST_INT_P ( value ) ) { value = GEN_INT ( - INTVAL ( value ) ) ; code = PLUS ; } default : x = gen_rtx_fmt_ee ( code , wmode , old_out , value ) ; emit_insn ( gen_rtx_SET ( VOIDmode , new_out , x ) ) ;


<s> continue ; } if ( Vector [ Src . second ] [ j ] < <NUM_LIT> ) Vector [ Src . second ] [ j ] = Src . first ; if ( Vector [ Src . second ] [ j ] != Src . first ) return i ; } } for ( unsigned i = <NUM_LIT> , e = TransSrcs . size ( ) ; i < e ; ++ i ) { const std :: pair < int , unsigned > & Src = TransSrcs [ i ] ; unsigned Cycle = getTransSwizzle ( TransSwz , i ) ; if ( Src . first < <NUM_LIT> ) continue ; if ( Src . first == <NUM_LIT> ) continue ;

if ( Vector [ Src . second ] [ Cycle ] < <NUM_LIT> ) Vector [ Src . second ] [ Cycle ] = Src . first ;


<s> const char * name = rs6000_builtin_info [ uns_fncode ] . name ; HOST_WIDE_INT fnmask = rs6000_builtin_info [ uns_fncode ] . mask ; gcc_assert ( name != NULL ) ; if ( ( fnmask & RS6000_BTM_CELL ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_VSX ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_HTM ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_ALTIVEC ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_PAIRED ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_SPE ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) == ( RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR ) ) error ( <STR_LIT> <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_DFP ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_P8_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT ) ) error ( <STR_LIT> <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_P9_VECTOR ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) == ( RS6000_BTM_P9_MISC | RS6000_BTM_64BIT ) ) error ( <STR_LIT> <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_P9_MISC ) == RS6000_BTM_P9_MISC ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & ( RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128 ) ) == ( RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128 ) ) error ( <STR_LIT> <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_HARD_FLOAT ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else if ( ( fnmask & RS6000_BTM_FLOAT128 ) != <NUM_LIT> ) error ( <STR_LIT> , name ) ; else error ( <STR_LIT> , name ) ;


<s> void <ISA_LIT>DAGToDAGISel :: SelectLoad ( SDNode * N , unsigned NumVecs , unsigned Opc , unsigned SubRegIdx ) { SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Chain } ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( Ld ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ; CurDAG -> RemoveDeadNode ( N ) ;


<s> if ( ! aarch64_sve_cmp_operand_p ( code , op1 ) ) op1 = force_reg ( data_mode , op1 ) ; rtx ptrue = force_reg ( pred_mode , CONSTM1_RTX ( pred_mode ) ) ; rtx cond = gen_rtx_fmt_ee ( code , pred_mode , op0 , op1 ) ; aarch64_emit_sve_ptrue_op_cc ( target , ptrue , cond ) ;


<s> break ; } unsigned IndexReg = <NUM_LIT> ; <ISA_LIT>SimplifyAddress ( Addr , UseOffset , IndexReg ) ; bool IsVSSRC = isVSSRCRegClass ( RC ) ; bool IsVSFRC = isVSFRCRegClass ( RC ) ; bool Is32VSXStore = IsVSSRC && Opc == <STR_LIT> ; bool Is64VSXStore = IsVSFRC && Opc == <STR_LIT> ; if ( ( Is32VSXStore || Is64VSXStore ) && ( Addr . BaseType != Address :: FrameIndexBase ) && UseOffset && ( Addr . Offset == <NUM_LIT> ) ) { UseOffset = false ; } if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( Is32VSXStore || Is64VSXStore ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * FuncInfo . MF , Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlign ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( Is32VSXStore || Is64VSXStore ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( SrcReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ;


<s> } unsigned Count = <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; ++ Count ; if ( FBB ) {

BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> __rv . __o = __builtin_neon_vld3_dupv8qi ( ( const __builtin_neon_qi * ) __a ) ;


<s> void Init ( const std :: string & GV , Mangler * Mang ) { if ( ! Stub . empty ( ) ) return ; Stub = Mang -> makeNameProper ( GV + <STR_LIT> , Mangler :: Private ) ; LazyPtr = Mang -> makeNameProper ( GV + <STR_LIT> , Mangler :: Private ) ;

AnonSymbol = Mang -> makeNameProper ( GV + <STR_LIT> , Mangler :: Private ) ;


<s> static DecodeStatus DecodeGR32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {

return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCall ( TargetLowering :: CallLoweringInfo & CLI , SmallVectorImpl < SDValue > & InVals ) const { SelectionDAG & DAG = CLI . DAG ; DebugLoc & dl = CLI . DL ; SmallVector < <STR_LIT> , <NUM_LIT> > & Outs = CLI . Outs ; SmallVector < SDValue , <NUM_LIT> > & OutVals = CLI . OutVals ; SmallVector < <STR_LIT> , <NUM_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; isTailCall = false ;


<s> int32_t <ISA_LIT>TargetLowering :: analyzeImmediate ( const SDNode * N ) const { union { int32_t I ; float F ; } Imm ; if ( const ConstantSDNode * Node = dyn_cast < ConstantSDNode > ( N ) ) Imm . I = Node -> getSExtValue ( ) ; else if ( const ConstantFPSDNode * Node = dyn_cast < ConstantFPSDNode > ( N ) ) Imm . F = Node -> getValueAPF ( ) . convertToFloat ( ) ; else return - <NUM_LIT> ; if ( ( Imm . I >= - <NUM_LIT> && Imm . I <= <NUM_LIT> ) || Imm . F == <NUM_LIT> || Imm . F == - <NUM_LIT> || Imm . F == <NUM_LIT> || Imm . F == - <NUM_LIT> || Imm . F == <NUM_LIT> || Imm . F == - <NUM_LIT> || Imm . F == <NUM_LIT> || Imm . F == - <NUM_LIT> ) return <NUM_LIT> ; return Imm . I ;


<s> if ( OpReg == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( OpReg ) ; UpdateValueMap ( I , ResultReg ) ; return true ;


<s> MaxAlign = Align ( <NUM_LIT> ) ; for ( const Argument & Arg : F . args ( ) ) { Type * ArgTy = Arg . getType ( ) ;

const Align Alignment ( DL . getABITypeAlignment ( ArgTy ) ) ;


<s> int extra ; rtx addr = XEXP ( op , <NUM_LIT> ) ; if ( TARGET_UPDATE && ( GET_CODE ( addr ) == PRE_INC || GET_CODE ( addr ) == PRE_DEC ) && mode_supports_pre_incdec_p ( mode ) && legitimate_indirect_address_p ( XEXP ( addr , <NUM_LIT> ) , false ) ) return true ; if ( ! rs6000_offsettable_memref_p ( op , mode , false ) ) return false ; op = address_offset ( addr ) ;


<s> ClassDef += <STR_LIT> ; for ( auto & TyFIDPair : CompFields ) EmitFieldAllocation ( ClassDef , TyFIDPair . first , ClassName , TyFIDPair . second ) ; ClassDef += <STR_LIT> ;


<s> bool isMemoryRegisterOffset64 ( ) const {

return isMem ( ) && Mem . Mode == RegisterOffset && ( Mem . ShiftVal == <NUM_LIT> || Mem . ShiftVal == <NUM_LIT> ) ;


<s> } case <STR_LIT> : { bool HasFP = MF . getFrameInfo ( ) . isMaxCallFrameSizeComputed ( ) ? TFI -> hasFP ( MF ) : true ; bool IsPagerando = MF . getFunction ( ) . isPagerando ( ) ; return <NUM_LIT> - HasFP - ( STI . isR9Reserved ( ) || IsPagerando ? <NUM_LIT> : <NUM_LIT> ) ; } case <STR_LIT> :


<s> if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ;

} else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ;


<s> if ( ! TARGET_BOOLEANS && TARGET_HARD_FLOAT ) error ( <STR_LIT> ) ; for ( mode = VOIDmode ; mode != MAX_MACHINE_MODE ; mode = ( machine_mode ) ( ( int ) mode + <NUM_LIT> ) ) { int size = GET_MODE_SIZE ( mode ) ; enum mode_class mclass = GET_MODE_CLASS ( mode ) ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { int temp ; if ( ACC_REG_P ( regno ) ) temp = ( TARGET_MAC16 && ( mclass == MODE_INT ) && ( size <= UNITS_PER_WORD ) ) ; else if ( GP_REG_P ( regno ) ) temp = ( ( regno & <NUM_LIT> ) == <NUM_LIT> || ( size <= UNITS_PER_WORD ) ) ; else if ( FP_REG_P ( regno ) ) temp = ( TARGET_HARD_FLOAT && ( mode == SFmode ) ) ; else if ( BR_REG_P ( regno ) ) temp = ( TARGET_BOOLEANS && ( mode == CCmode ) ) ; else temp = FALSE ; xtensa_hard_regno_mode_ok_p [ ( int ) mode ] [ regno ] = temp ; } }


<s> return resolveFrameIndexReference ( MF , FI , FrameReg , MF . getFunction ( ) . hasFnAttribute ( Attribute :: SanitizeHWAddress ) , false ) ;


<s> if ( ARM_DOUBLEWORD_ALIGN ) for ( mp = minipool_vector_head ; mp != NULL ; mp = mp -> next ) if ( mp -> refcount > <NUM_LIT> && mp -> fix_size >= <NUM_LIT> ) { align64 = <NUM_LIT> ; break ; } if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( scan ) , ( unsigned long ) minipool_barrier -> address , align64 ? <NUM_LIT> : <NUM_LIT> ) ; scan = emit_label_after ( gen_label_rtx ( ) , scan ) ; scan = emit_insn_after ( align64 ? gen_align_8 ( ) : gen_align_4 ( ) , scan ) ; scan = emit_label_after ( minipool_vector_label , scan ) ; for ( mp = minipool_vector_head ; mp != NULL ; mp = nmp ) { if ( mp -> refcount > <NUM_LIT> ) { if ( dump_file ) { fprintf ( dump_file , <STR_LIT> , ( unsigned ) mp -> offset , ( unsigned long ) mp -> min_address , ( unsigned long ) mp -> max_address ) ; arm_print_value ( dump_file , mp -> value ) ; fputc ( '\n' , dump_file ) ; } rtx val = copy_rtx ( mp -> value ) ; switch ( GET_MODE_SIZE ( mp -> mode ) ) { case <NUM_LIT> : scan = emit_insn_after ( gen_consttable_1 ( val ) , scan ) ; break ; case <NUM_LIT> : scan = emit_insn_after ( gen_consttable_2 ( val ) , scan ) ; break ; case <NUM_LIT> :

scan = emit_insn_after ( gen_consttable_4 ( val ) , scan ) ;


<s> tree a ; if ( TREE_CODE ( decl ) != VAR_DECL ) return <NUM_LIT> ; if ( avr_decl_memx_p ( decl ) ) return <NUM_LIT> ; if ( avr_decl_flash_p ( decl ) ) return <NUM_LIT> ; if ( NULL_TREE != lookup_attribute ( <STR_LIT> , attributes ) ) return - <NUM_LIT> ; a = decl ; do a = TREE_TYPE ( a ) ; while ( TREE_CODE ( a ) == ARRAY_TYPE ) ; if ( a == error_mark_node ) return <NUM_LIT> ; if ( NULL_TREE != lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( a ) ) ) return - <NUM_LIT> ;


<s> static bool readInstruction32 ( ArrayRef < uint8_t > Bytes , uint64_t Address , uint64_t & Size , uint32_t & Insn ) { Size = <NUM_LIT> ;

Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> extern __inline __m64 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_subs_pi16 ( __m64 __m1 , __m64 __m2 ) { __vector signed short a , b , c ; a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ;


<s> emitFunctionEnd ( MachineFunction & MF ) { O << <STR_LIT> ; O << <STR_LIT> ;

O << <STR_LIT> << CurrentFnName << '\n' ;


<s> assert ( N == <NUM_LIT> || N == <NUM_LIT> ) ; uint64_t Result ; unsigned bit6 = slice ( byte , <NUM_LIT> , <NUM_LIT> ) ; if ( N == <NUM_LIT> ) { Result = slice ( byte , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | slice ( byte , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( bit6 ) Result |= <NUM_LIT> << <NUM_LIT> ; else Result |= <NUM_LIT> << <NUM_LIT> ;


<s> unsigned <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( unsigned Channel , unsigned NumRegs ) { assert ( NumRegs < SubRegFromChannelTableWidthMap . size ( ) ) ; unsigned NumRegIndex = SubRegFromChannelTableWidthMap [ NumRegs ] ; assert ( NumRegIndex && <STR_LIT> ) ;

assert ( Channel < SubRegFromChannelTable [ NumRegIndex - <NUM_LIT> ] . size ( ) ) ;


<s> if ( ! MEM_P ( mem ) ) return false ; if ( ! fusion_gpr_mem_load ( mem , GET_MODE ( mem ) ) ) return false ; addr = XEXP ( mem , <NUM_LIT> ) ; if ( GET_CODE ( addr ) != PLUS && GET_CODE ( addr ) != LO_SUM ) return false ; if ( REGNO ( addis_reg ) != REGNO ( target ) ) { if ( reg_mentioned_p ( target , mem ) ) return false ; if ( ! peep2_reg_dead_p ( <NUM_LIT> , addis_reg ) ) return false ; if ( REG_P ( target ) && REGNO ( target ) == STACK_POINTER_REGNUM ) return false ; } base_reg = XEXP ( addr , <NUM_LIT> ) ;

return REGNO ( addis_reg ) == REGNO ( base_reg ) ;


<s> void setGlobalBaseReg ( unsigned Reg ) { <ISA_LIT>_LOG ( <STR_LIT> << Reg ) ;


<s> return Kind == OpKind :: MovDGUnpack ;


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ;


<s> TargetRegistry :: RegisterMCInstrInfo ( * T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( * T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( * T , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( * T , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( * T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , create<ISA_LIT>AsmTargetStreamer ) ; }


<s> SelectionDAG & DAG = DCI . DAG ; unsigned Opc = N -> getOpcode ( ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == Opc && Op0 . hasOneUse ( ) ) { SDLoc DL ( N ) ; return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) , Op1 ) ; } if ( Op1 . getOpcode ( ) == Opc && Op1 . hasOneUse ( ) ) { SDLoc DL ( N ) ; return DAG . getNode ( minMaxOpcToMin3Max3Opc ( Opc ) , DL , N -> getValueType ( <NUM_LIT> ) , Op0 , Op1 . getOperand ( <NUM_LIT> ) , Op1 . getOperand ( <NUM_LIT> ) ) ; } return SDValue ( ) ;


<s> rtx not_value = GEN_INT ( ~ mask ) ; int i ; if ( mask == <NUM_LIT> ) { emit_move_insn ( operands [ <NUM_LIT> ] , const0_rtx ) ; return true ; } if ( mask == - <NUM_LIT> ) { emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; return true ; } if ( CSKY_ISA_FEATURE ( E2 ) && csky_arith_O_operand ( operands [ <NUM_LIT> ] , SImode ) ) return false ; if ( CSKY_ISA_FEATURE ( E2 ) && csky_arith_O_operand ( not_value , SImode ) ) { emit_insn ( gen_cskyv2_andnsi3 ( operands [ <NUM_LIT> ] , not_value , operands [ <NUM_LIT> ] ) ) ; return true ; } if ( popcount_hwi ( ~ mask & <NUM_LIT> ) <= ( reload_completed && ! CSKY_ISA_FEATURE ( E2 ) ? <NUM_LIT> : <NUM_LIT> ) ) { rtx input = operands [ <NUM_LIT> ] ; if ( ! CSKY_ISA_FEATURE ( E2 ) ) { emit_move_insn ( operands [ <NUM_LIT> ] , input ) ; input = operands [ <NUM_LIT> ] ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ( mask & ( <NUM_LIT> << i ) ) == <NUM_LIT> ) { emit_insn ( gen_bclri ( operands [ <NUM_LIT> ] , input , GEN_INT ( i ) ) ) ; input = operands [ <NUM_LIT> ] ; } return true ; } for ( i = ( CSKY_ISA_FEATURE ( E2 ) ? <NUM_LIT> : <NUM_LIT> ) ; i < <NUM_LIT> ; i ++ ) { if ( ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << i ) - <NUM_LIT> == mask ) { if ( CSKY_ISA_FEATURE ( <NUM_LIT> ) ) emit_insn ( gen_cskyv2_extzv ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , GEN_INT ( i ) , const0_rtx ) ) ; else { rtx shift = GEN_INT ( <NUM_LIT> - i ) ; rtx reg = ( reload_completed ? operands [ <NUM_LIT> ] : gen_reg_rtx ( SImode ) ) ; emit_insn ( gen_ashlsi3 ( reg , operands [ <NUM_LIT> ] , shift ) ) ; emit_insn ( gen_lshrsi3 ( operands [ <NUM_LIT> ] , reg , shift ) ) ; } return true ; } else if ( ( ( ( HOST_WIDE_INT ) <NUM_LIT> ) << i ) - <NUM_LIT> == ~ mask ) { rtx shift = GEN_INT ( i ) ; rtx reg = ( reload_completed ? operands [ <NUM_LIT> ] : gen_reg_rtx ( SImode ) ) ; emit_insn ( gen_lshrsi3 ( reg , operands [ <NUM_LIT> ] , shift ) ) ; emit_insn ( gen_ashlsi3 ( operands [ <NUM_LIT> ] , reg , shift ) ) ; return true ; } } if ( ! reload_completed && INTVAL ( operands [ <NUM_LIT> ] ) < <NUM_LIT> ) { rtx reg = copy_to_mode_reg ( SImode , not_value ) ; if ( CSKY_ISA_FEATURE ( E2 ) ) emit_insn ( gen_cskyv2_andnsi3 ( operands [ <NUM_LIT> ] , reg , operands [ <NUM_LIT> ] ) ) ;


<s> case <STR_LIT> : default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return false ; }


<s> static SDValue combineFP_EXTEND ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { if ( ! Subtarget . hasF16C ( ) || Subtarget . useSoftFloat ( ) ) return SDValue ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = Src . getValueType ( ) ; if ( ! SrcVT . isVector ( ) || SrcVT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; if ( VT . getVectorElementType ( ) != <STR_LIT> && VT . getVectorElementType ( ) != <STR_LIT> ) return SDValue ( ) ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> || ! isPowerOf2_32 ( NumElts ) ) return SDValue ( ) ; SDLoc dl ( N ) ; EVT IntVT = SrcVT . changeVectorElementTypeToInteger ( ) ; Src = DAG . getBitcast ( IntVT , Src ) ;


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; }


<s> void <ISA_LIT>CCState :: PreAnalyzeCallOperand ( const Type * ArgTy , bool IsFixed , const char * Func ) {

OriginalArgWasF128 . push_back ( originalTypeIsF128 ( ArgTy , Func ) ) ;


<s> if ( <STR_LIT> ( InVec . getNode ( ) ) ) return getZeroVector ( OpVT , Subtarget , DAG , SDLoc ( N ) ) ; if ( <STR_LIT> ( InVec . getNode ( ) ) ) { if ( OpVT . getScalarType ( ) == <STR_LIT> ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , OpVT ) ; return getOnesVector ( OpVT , DAG , SDLoc ( N ) ) ; } if ( InVec . getOpcode ( ) == <STR_LIT> ) return DAG . getBuildVector ( OpVT , SDLoc ( N ) , InVec . getNode ( ) -> ops ( ) . slice ( IdxVal , OpVT . getVectorNumElements ( ) ) ) ;


<s> if ( rtx_equal_p ( op0 , op1 ) ) { perm0 = perm0 & <NUM_LIT> ; perm1 = ( perm1 & <NUM_LIT> ) + <NUM_LIT> ; } else if ( perm0 & <NUM_LIT> ) { if ( perm1 & <NUM_LIT> ) return false ; perm0 -= <NUM_LIT> ; perm1 += <NUM_LIT> ; std :: swap ( op0 , op1 ) ; } else if ( ( perm1 & <NUM_LIT> ) == <NUM_LIT> ) return false ; if ( target != NULL ) { machine_mode vmode , dmode ;


<s> } else { const MCPhysReg * CSRegs = RegInfo -> getCalleeSavedRegs ( & MF ) ; if ( MBBI != MBB . begin ( ) ) { do { -- MBBI ; } while ( MBBI != MBB . begin ( ) && isCSRestore ( MBBI , TII , CSRegs ) ) ; if ( ! isCSRestore ( MBBI , TII , CSRegs ) ) ++ MBBI ; } NumBytes -= ( ArgRegsSaveSize + AFI -> getGPRCalleeSavedArea1Size ( ) + AFI -> getGPRCalleeSavedArea2Size ( ) + AFI -> getDPRCalleeSavedGapSize ( ) + AFI -> getDPRCalleeSavedAreaSize ( ) ) ; if ( AFI -> shouldRestoreSPFromFP ( ) ) { NumBytes = AFI -> getFramePtrSpillOffset ( ) - NumBytes ; if ( NumBytes ) { if ( is<ISA_LIT> ) emit<ISA_LIT>RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; else { assert ( MF . getRegInfo ( ) . isPhysRegUsed ( <STR_LIT> ) && <STR_LIT> ) ; emitT2RegPlusImmediate ( MBB , MBBI , dl , <STR_LIT> , FramePtr , - NumBytes , <STR_LIT> , <NUM_LIT> , TII ) ; AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ) ; } } else { if ( is<ISA_LIT> ) BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) . addImm ( ( unsigned ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; else AddDefaultPred ( BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( FramePtr ) ) ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ;


<s> if ( MO . isExpr ( ) ) { return :: getBranchTargetOpValue ( MI , OpIdx , <STR_LIT> , Fixups , STI ) ; }


<s> case AddrModeT2_i8neg : return <STR_LIT> ; case AddrModeT2_so : return <STR_LIT> ; case AddrModeT2_pc : return <STR_LIT> ; case AddrModeT2_i8s4 : return <STR_LIT> ; case AddrMode_i12 : return <STR_LIT> ; case AddrModeT2_ldrex : return <STR_LIT> ; case AddrModeT2_i7s4 : return <STR_LIT> ; case AddrModeT2_i7s2 : return <STR_LIT> ; case AddrModeT2_i7 : return <STR_LIT> ; }


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> if ( this -> <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) { return <STR_LIT> ; } else { return <STR_LIT> ; }


<s> const int predIndex = MI . findFirstPredOperandIdx ( ) ; if ( predIndex == - <NUM_LIT> ) return false ; if ( MI . getOperand ( predIndex ) . getImm ( ) != - <NUM_LIT> ) return true ; return false ;


<s> inline SDValue getI32Imm ( int64_t Imm , const SDLoc & DL ) { return CurDAG -> getTargetConstant ( Imm , DL , <STR_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : return NULL ;


<s> BasicBlock * Exit = L -> getUniqueExitBlock ( ) ; if ( ! Exit ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return ; } SmallPtrSet < Instruction * , <NUM_LIT> > Dead ; while ( ! MaybeDead . empty ( ) ) { auto * I = MaybeDead . front ( ) ; MaybeDead . remove ( I ) ; if ( I -> hasNUsesOrMore ( <NUM_LIT> ) ) continue ; for ( auto & U : I -> operands ( ) ) if ( auto * OpI = dyn_cast < Instruction > ( U ) ) MaybeDead . insert ( OpI ) ; Dead . insert ( I ) ;


return DAG . getBitcast ( <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , V1 ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , PSHUFBMask ) ) ) ;


<s> } else if ( GET_CODE ( x ) == PLUS && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) ) fprintf ( file , HOST_WIDE_INT_PRINT_DEC <STR_LIT> , INTVAL ( XEXP ( x , <NUM_LIT> ) ) , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { fprintf ( file , <STR_LIT> ) ; output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , <NUM_LIT> ) ) && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) ) { output_addr_const ( file , XEXP ( x , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; } else if ( toc_relative_expr_p ( x , false , & tocrel_base_oac , & tocrel_offset_oac ) ) { output_addr_const ( file , CONST_CAST_RTX ( tocrel_base_oac ) ) ; if ( GET_CODE ( x ) == LO_SUM ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ;

else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XVECEXP ( tocrel_base_oac , <NUM_LIT> , <NUM_LIT> ) ) ] ) ;


<s> void <ISA_LIT>FrameLowering :: emitPushInst ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , unsigned StmOpc , unsigned StrOpc , bool NoGap , bool ( * Func ) ( unsigned , bool ) , unsigned NumAlignedDPRCS2Regs , unsigned MIFlags ) const { MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const TargetRegisterInfo & TRI = * STI . getRegisterInfo ( ) ; DebugLoc DL ; typedef std :: pair < unsigned , bool > RegAndKill ; SmallVector < RegAndKill , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . splitFramePushPop ( MF ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; bool isLiveIn = MF . getRegInfo ( ) . isLiveIn ( Reg ) ; if ( ! isLiveIn ) MBB . addLiveIn ( Reg ) ; if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ; LastReg = Reg ; Regs . push_back ( std :: make_pair ( Reg , ! isLiveIn ) ) ; } if ( Regs . empty ( ) ) continue ; std :: sort ( Regs . begin ( ) , Regs . end ( ) , [ & ] ( const RegAndKill & LHS , const RegAndKill & RHS ) { return TRI . getEncodingValue ( LHS . first ) < TRI . getEncodingValue ( RHS . first ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> || StrOpc == <NUM_LIT> ) { MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( StmOpc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . add ( predOps ( <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) ; i < e ; ++ i ) MIB . addReg ( Regs [ i ] . first , getKillRegState ( Regs [ i ] . second ) ) ; } else if ( Regs . size ( ) == <NUM_LIT> ) { BuildMI ( MBB , MI , DL , TII . get ( StrOpc ) , <STR_LIT> ) . addReg ( Regs [ <NUM_LIT> ] . first , getKillRegState ( Regs [ <NUM_LIT> ] . second ) ) . addReg ( <STR_LIT> ) . setMIFlags ( MIFlags ) . addImm ( - <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ; } Regs . clear ( ) ; if ( MI != MBB . begin ( ) ) -- MI ; }


<s> static std :: string GetArgumentSymbolName ( Argument & Arg ) { return ( symbols :: PREFIX + <STR_LIT> + GetTypeName ( * Arg . getType ( ) ) ) . str ( ) ;


if ( GENERATE_DIVIDE_TRAPS && ! MSA_SUPPORTED_MODE_P ( mode ) ) count ++ ;


<s> if ( L && L -> empty ( ) && canPeel ( L ) && SE . getSmallConstantTripCount ( L ) == <NUM_LIT> && SE . getSmallConstantMaxTripCount ( L ) > <NUM_LIT> && SE . getSmallConstantMaxTripCount ( L ) <= <NUM_LIT> ) {


return ( __m512d ) __builtin_ia32_cvtdq2pd512_mask ( ( __v8si ) __A , ( __v8df ) _mm512_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> StringRef IDVal = DirectiveID . getIdentifier ( ) ; SMLoc Loc = DirectiveID . getLoc ( ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveArch ( Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveCPU ( Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveWord ( <NUM_LIT> , Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveTLSDescCall ( Loc ) ; if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) return parseDirectiveLtorg ( Loc ) ; if ( IDVal == <STR_LIT> ) return parseDirectiveUnreq ( Loc ) ; if ( ! IsMachO && ! IsCOFF ) { if ( IDVal == <STR_LIT> ) return parseDirectiveInst ( Loc ) ;


<s> <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) {


<s> typedef enum { none , zpreg } TCopyKind ; for ( MachineFunction :: iterator MBBI = MF -> begin ( ) , MBBE = MF -> end ( ) ; MBBI != MBBE ; ++ MBBI ) { MBB = & * MBBI ; for ( MachineBasicBlock :: iterator mi = MBB -> begin ( ) , me = MBB -> end ( ) ; mi != me ; ) { MachineBasicBlock :: iterator nmi = std :: next ( mi ) ; MachineInstr * MI = & * mi ; auto opc = MI -> getOpcode ( ) ; if ( opc == TargetOpcode :: COPY ) { MachineOperand des = MI -> getOperand ( <NUM_LIT> ) ;


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , EFLAGS ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> return ST -> hasHalfRate64Ops ( ) ? getHalfRateInstrCost ( CostKind ) : getQuarterRateInstrCost ( CostKind ) ;


<s> default_file_start ( ) ; if ( TARGET_H8300SX ) fputs ( TARGET_NORMAL_MODE ? <STR_LIT> : <STR_LIT> , asm_out_file ) ;

else if ( TARGET_H8300S ) fputs ( TARGET_NORMAL_MODE ? <STR_LIT> : <STR_LIT> , asm_out_file ) ;


<s> SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue Chain = Result . getValue ( <NUM_LIT> ) ; SDValue GOT = DAG . getGLOBAL_OFFSET_TABLE ( PtrVT ) ; Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , GOT ) ; if ( ! UseGOTOFF ) Result = DAG . getLoad ( PtrVT , dl , Chain , Result , MachinePointerInfo :: getGOT ( ) , false , false , false , <NUM_LIT> ) ;


<s> Candidate ( MachineInstr * mi , unsigned reg , unsigned subreg , unsigned freebanks , unsigned weight ) : MI ( mi ) , Reg ( reg ) , SubReg ( subreg ) , FreeBanks ( freebanks ) , Weight ( weight ) {


<s> } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { LoadOpCode = <STR_LIT> ; StackID = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { LoadOpCode = <STR_LIT> ; StackID = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { LoadOpCode = <STR_LIT> ; StackID = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { LoadOpCode = <STR_LIT> ; StackID = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Subtarget . getTargetLowering ( ) -> getTargetMachine ( ) . Options . LongIRF ) report_fatal_error ( <STR_LIT> ) ; LoadOpCode = <STR_LIT> ; StackID = <STR_LIT> ; } else { report_fatal_error ( <STR_LIT> ) ; } FrameInfo . setStackID ( FrameIndex , StackID ) ;

BuildMI ( MBB , I , DL , get ( LoadOpCode ) , DestReg ) . addFrameIndex ( FrameIndex ) ;


<s> if ( const auto * C = dyn_cast < ConstantInt > ( Src1 ) ) if ( C -> getValue ( ) . isPowerOf2 ( ) ) { uint64_t ShiftVal = C -> getValue ( ) . logBase2 ( ) ; MVT SrcVT = VT ; bool IsZExt = true ; if ( const auto * ZExt = dyn_cast < ZExtInst > ( Src0 ) ) { if ( ! isIntExtFree ( ZExt ) ) { MVT VT ; if ( isValueAvailable ( ZExt ) && isTypeSupported ( ZExt -> getSrcTy ( ) , VT ) ) { SrcVT = VT ; IsZExt = true ; Src0 = ZExt -> getOperand ( <NUM_LIT> ) ; } } } else if ( const auto * SExt = dyn_cast < SExtInst > ( Src0 ) ) { if ( ! isIntExtFree ( SExt ) ) { MVT VT ; if ( isValueAvailable ( SExt ) && isTypeSupported ( SExt -> getSrcTy ( ) , VT ) ) { SrcVT = VT ; IsZExt = false ; Src0 = SExt -> getOperand ( <NUM_LIT> ) ; } }


<s> <ISA_LIT>MCInstLower MCInstLowering ; explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCP ( nullptr ) , InConstantPool ( false ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; } const char * getPassName ( ) const override { return <STR_LIT> ; } bool runOnMachineFunction ( MachineFunction & MF ) override ; void EmitConstantPool ( ) override { bool UsingConstantPools = ( Subtarget -> in<ISA_LIT>16Mode ( ) && Subtarget -> useConstantIslands ( ) ) ; if ( ! UsingConstantPools ) AsmPrinter :: EmitConstantPool ( ) ; } void EmitInstruction ( const MachineInstr * MI ) override ; void printSavedRegsBitmask ( ) ; void emitFrameDirective ( ) ; const char * getCurrentABIString ( ) const ; void EmitFunctionEntryLabel ( ) override ; void EmitFunctionBodyStart ( ) override ; void EmitFunctionBodyEnd ( ) override ; bool isBlockOnlyReachableByFallthrough ( const MachineBasicBlock * MBB ) const override ; bool PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; bool PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) override ; void printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) ;

void printUnsignedImm ( const MachineInstr * MI , int opNum , raw_ostream & O ) ;


<s> } ; if ( ! isTailCallableCC ( CallerCC ) || ! isTailCallableCC ( CalleeCC ) ) return false ; return CallerCC == CallingConv :: C || CallerCC == CalleeCC ;


<s> Status merge ( const Status & S ) const { return Status ( ( Mask | S . Mask ) , ( ( Mode & ~ S . Mask ) | ( S . Mode & S . Mask ) ) ) ;


<s> bool hasAVLImm ( ) const { return State == AVLIsImm ;


<s> HII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; HRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; Dependence = false ; PacketNum = <NUM_LIT> ;

addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: <ISA_LIT>DAGMutation > ( ) ) ;


<s> } OptionalImmIndexMap OptionalIdx ; for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( Op . isRegOrImm ( ) ) { Op . addRegOrImmOperands ( Inst , <NUM_LIT> ) ; continue ; } else if ( Op . isImmModifier ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else {


<s>
const
MCSectionELF
*
CommentSection
=
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_PROGBITS
,
<NUM_LIT>
,
SectionKind
::
getReadOnly
(
)
)
;
OutStreamer
.
SwitchSection
(
CommentSection
)
;
if
(
STM
.
getGeneration
(
)
>=
AMDGPUSubtarget
::
SOUTHERN_ISLANDS
)
{
OutStreamer
.
emitRawComment
(
<STR_LIT>
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
CodeLen
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
NumSGPR
)
,
false
)
;
OutStreamer
.
emitRawComment
(
<STR_LIT>
+
Twine
(
KernelInfo
.
NumVGPR
)
,
false
)
;
}
else
{
R600MachineFunctionInfo
*
MFI
=
MF
.
getInfo
<
R600MachineFunctionInfo
>
(
)
;
OutStreamer
.
emitRawComment
(
Twine
(
<STR_LIT>
+
Twine
(
MFI
->
StackSize
)
)
)
;
}
}
if
(
STM
.
dumpCode
(
)
)
{
MF
.
dump
(
)
;
if
(
DisasmEnabled
)
{
OutStreamer
.
SwitchSection
(
Context
.
getELFSection
(
<STR_LIT>
,
ELF
::
SHT_NOTE
,
<NUM_LIT>
,
SectionKind
::
getReadOnly
(
)
)
)
;
for
(
size_t
i
=
<NUM_LIT>
;
i
<
DisasmLines
.
size
(
)
;
++
i
)
{
std
::
string
Comment
(
DisasmLineMaxLen
DisasmLines
[
i
]
.
size
(
)
,
' '
)
;

Comment += <STR_LIT> + HexLines [ i ] + <STR_LIT> ;


<s> ReplaceTXF ( I ) ; return ; } if ( Name == <STR_LIT> ) { ReplaceTexIntrinsic ( I , false , TexQSign , <STR_LIT> , <STR_LIT> ) ; return ; } if ( Name == <STR_LIT> ) { ReplaceTexIntrinsic ( I , false , TexSign , <STR_LIT> , <STR_LIT> ) ; return ; } if ( Name == <STR_LIT> ) { ReplaceTexIntrinsic ( I , false , TexSign , <STR_LIT> , <STR_LIT> ) ;


<s> unsigned Opc = <STR_LIT> ( ( <STR_LIT> ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( BB , DL , TII -> get ( Opc ) ) . addMBB ( sinkMBB ) ; copy0MBB -> addSuccessor ( sinkMBB ) ; BuildMI ( * sinkMBB , sinkMBB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; MI -> eraseFromParent ( ) ; return sinkMBB ;


<s> return new <ISA_LIT>RegisterAllocator ( ) ;


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> :


<s> HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; IsBTMemSlow = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMorZMMWrite = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasFastLZCNT = false ; HasFastSHLDRotate = false ; HasERMSB = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; CallRegIndirect = false ;


<s> } r0 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; r1 = gen_rtx_REG ( Pmode , STACK_POINTER_REGNUM ) ; r12 = gen_rtx_REG ( Pmode , <NUM_LIT> ) ; emit_insn ( gen_load_split_stack_limit ( r0 ) ) ; alloc_hi = ( - allocate + <NUM_LIT> ) & ~ <NUM_LIT> ; alloc_lo = - allocate - alloc_hi ; if ( alloc_hi != <NUM_LIT> ) { emit_insn ( gen_add3_const ( r12 , r1 , alloc_hi ) ) ; if ( alloc_lo != <NUM_LIT> ) emit_insn ( gen_add3_const ( r12 , r12 , alloc_lo ) ) ; else emit_insn ( gen_nop ( ) ) ; } else { emit_insn ( gen_add3_const ( r12 , r1 , alloc_lo ) ) ; emit_insn ( gen_nop ( ) ) ; } compare = gen_rtx_REG ( CCUNSmode , CR7_REGNO ) ; emit_insn ( gen_rtx_SET ( compare , gen_rtx_COMPARE ( CCUNSmode , r12 , r0 ) ) ) ; ok_label = gen_label_rtx ( ) ; jump = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_GEU ( VOIDmode , compare , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , ok_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , jump ) ) ; JUMP_LABEL ( insn ) = ok_label ; add_reg_br_prob_note ( insn , profile_probability :: very_likely ( ) ) ; lr = gen_rtx_REG ( Pmode , LR_REGNO ) ; insn = emit_move_insn ( r0 , lr ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_insn ( gen_frame_store ( r0 , r1 , info -> lr_save_offset ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_call_insn ( gen_call ( gen_rtx_MEM ( SImode , morestack_ref ) , const0_rtx , const0_rtx ) ) ; call_fusage = NULL_RTX ; use_reg ( & call_fusage , r12 ) ; use_reg ( & call_fusage , r0 ) ;

add_function_usage_to ( insn , call_fusage ) ;


<s> virtual unsigned int execute ( function * ) { return rest_of_insert_bti ( ) ;


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ;

const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ;


<s> pad_direction nios2_block_reg_padding ( machine_mode mode , tree type , int first ATTRIBUTE_UNUSED ) { return nios2_function_arg_padding ( mode , type ) ;


<s> if ( TARGET_SHMEDIA_FPU && ( ( mode == V2SFmode ) || ( mode == V4SFmode ) || ( mode == V16SFmode ) ) ) return true ; else if ( TARGET_SHMEDIA && ( ( mode == V8QImode ) || ( mode == V2HImode ) || ( mode == V4HImode ) || ( mode == V2SImode ) ) ) return true ; return false ;


<s> return ! isDarwinABI ( ) && ! isAIXABI ( ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; return MCDisassembler :: Success ;


<s> GTI != E ; ++ GTI ) { NumIndices -- ; const Value * Idx = GTI . getOperand ( ) ; Type * IdxTy = GTI . getIndexedType ( ) ; if ( NextIndex == ARRAY_REF || NextIndex == STRUCT_REF ) { unsigned NodeOpcode = NextIndex == STRUCT_REF ? <STR_LIT> : <STR_LIT> ; IsInChain |= <NUM_LIT> << <NUM_LIT> ; IsInChain |= ( <NUM_LIT> == NumIndices ) << <NUM_LIT> ; SDValue InChainUse = DAG . getConstant ( IsInChain , dl , <STR_LIT> ) ; IsInChain &= ~ <NUM_LIT> ; SDValue Ops [ ] = { SDB -> getRoot ( ) , N , SDB -> getValue ( Idx ) , InChainUse } ; if ( isa < CompositeType > ( IdxTy ) ) { EVT VTs [ ] = { <STR_LIT> , <STR_LIT> } ; N = DAG . getNode ( NodeOpcode , dl , VTs , Ops ) ; SDNodeFlags Flags = N . getNode ( ) -> getFlags ( ) ; Flags . setIsComposite ( true ) ; N . getNode ( ) -> setFlags ( Flags ) ; } else { EVT IdxVT = getValueType ( DL , IdxTy ) ;


<s> <ISA_LIT>EL_AsmBackend ( const Target & T , Triple :: OSType _OSType ) : <ISA_LIT>AsmBackend ( T ) , OSType ( _OSType ) {


<s> return SrcVT . getSizeInBits ( ) > <NUM_LIT> && DestVT . getSizeInBits ( ) == <NUM_LIT> ;


<s> bool <ISA_LIT>MCAsmBackend :: shouldForceRelocation ( const MCAssembler & , const MCFixup & Fixup , const MCValue & ) {

return Fixup . getKind ( ) >= FirstLiteralRelocationKind ;


<s> EVT MemVT = MSC -> getMemoryVT ( ) ; SDValue InputVT = DAG . getValueType ( MemVT ) ; if ( IsFixedLength ) { assert ( Subtarget -> useSVEForFixedLengthVectors ( ) && <STR_LIT> ) ; if ( MemVT . getScalarSizeInBits ( ) <= IndexVT . getScalarSizeInBits ( ) ) { IndexVT = getContainerForFixedLengthVector ( DAG , IndexVT ) ; MemVT = IndexVT . changeVectorElementType ( MemVT . getVectorElementType ( ) ) ; } else { MemVT = getContainerForFixedLengthVector ( DAG , MemVT ) ; IndexVT = MemVT . changeTypeToInteger ( ) ; } InputVT = DAG . getValueType ( MemVT . changeTypeToInteger ( ) ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeTypeToInteger ( ) , StoreVal ) ; StoreVal = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , StoreVal ) ; StoreVal = convertToScalableVector ( DAG , IndexVT , StoreVal ) ; Mask = DAG . getNode ( <STR_LIT> , DL , VT . changeVectorElementType ( IndexVT . getVectorElementType ( ) ) , Mask ) ; } else if ( VT . isFloatingPoint ( ) ) { EVT StoreValVT = getPackedSVEVectorVT ( VT . getVectorElementCount ( ) ) ; StoreVal = getSVESafeBitCast ( StoreValVT , StoreVal , DAG ) ; InputVT = DAG . getValueType ( MemVT . changeVectorElementTypeToInteger ( ) ) ; }

if ( getGatherScatterIndexIsExtended ( Index ) ) Index = Index . getOperand ( <NUM_LIT> ) ;


<s> cvtSDWA ( Inst , Operands , <STR_LIT> , false , true ) ;


<s> static size_t cygwin_gt_pch_alloc_granularity ( void ) { return va_granularity ;


<s> bool NoFloat = DAG . getMachineFunction ( ) . getFunction ( ) . hasFnAttribute ( Attribute :: NoImplicitFloat ) ; if ( NoFloat ) return ( MemVT . getSizeInBits ( ) <= <NUM_LIT> ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>RegisterInfo ( ) {


<s> static Value * UseTlsOffset ( IRBuilder < > & IRB , unsigned Offset ) { Module * M = IRB . GetInsertBlock ( ) -> getParent ( ) -> getParent ( ) ;

Function * ThreadPointerFunc = <STR_LIT> ( M , <STR_LIT> ) ;


<s> return ( __m128i ) __builtin_ia32_vpcomtrued ( ( __v4si ) __A , ( __v4si ) __B ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const Triple & TT ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TT ( TT ) { <ISA_LIT>_MC :: initLLVMToCVRegMapping ( this ) ;


<s> void <ISA_LIT>InstrInfo :: AnalyzeCondBr ( const MachineInstr * Inst , unsigned Opc , MachineBasicBlock * & BB , SmallVectorImpl < MachineOperand > & Cond ) const { assert ( getAnalyzableBrOpc ( Opc ) && <STR_LIT> ) ;

int NumOp = Inst -> getNumExplicitOperands ( ) ;


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx , T . createMCInstrInfo ( ) ) ;


<s> switch ( Node -> getOpcode ( ) ) { default : break ; } SelectCode ( Node ) ;


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; int DppVgprWaitStates = <NUM_LIT> ; int DppExecWaitStates = <NUM_LIT> ; int WaitStatesNeeded = <NUM_LIT> ; auto IsHazardDefFn = [ TII ] ( const MachineInstr & MI ) { return TII -> isVALU ( MI ) ; } ; for ( const MachineOperand & Use : DPP -> uses ( ) ) { if ( ! Use . isReg ( ) || ! TRI -> isVGPR ( MF . getRegInfo ( ) , Use . getReg ( ) ) ) continue ; int WaitStatesNeededForUse = DppVgprWaitStates - getWaitStatesSinceDef ( Use . getReg ( ) , [ ] ( const MachineInstr & ) { return true ; } , DppVgprWaitStates ) ;

WaitStatesNeeded = std :: max ( WaitStatesNeeded , WaitStatesNeededForUse ) ;