<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && MI . isInvariantLoad ( AA ) ) { unsigned BaseReg = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> || BaseReg == <STR_LIT> ) return true ; if ( ! ReMatPICStubLoad && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isGlobal ( ) ) return false ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) == <NUM_LIT> && ! MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) ) { if ( ! MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . isReg ( ) ) return true ; unsigned BaseReg = MI . getOperand ( <NUM_LIT> + <STR_LIT> ) . getReg ( ) ; if ( BaseReg == <NUM_LIT> ) return true ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; return regIsPICBase ( BaseReg , MRI ) ; } return false ; }


<s> unsigned <ISA_LIT>MCCodeEmitter :: getMachineOpValue ( const MCInst & MI , const MCOperand & MO , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MO . isReg ( ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; assert ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: SymbolRef ) ;


<s> if ( GV -> hasDLLImportStorageClass ( ) ) return <STR_LIT> ; return <STR_LIT> ; } const Function * F = dyn_cast_or_null < Function > ( GV ) ; if ( isTargetELF ( ) ) { if ( is64Bit ( ) && F && ( CallingConv :: <ISA_LIT>_RegCall == F -> getCallingConv ( ) ) ) return <STR_LIT> ;

if ( ( ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) || ( ! F && M . getRtLibUseGOT ( ) ) ) && is64Bit ( ) ) return <STR_LIT> ;


<s> unsigned i = <NUM_LIT> ; MachineInstr & MI = * II ; MachineBasicBlock & MBB = * MI . getParent ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; DebugLoc dl = II -> getDebugLoc ( ) ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } MachineOperand & SPOp = MI . getOperand ( i ) ; int FrameIndex = SPOp . getIndex ( ) ; int Offset = MFI -> getObjectOffset ( FrameIndex ) ; unsigned OpNo = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) OpNo = <NUM_LIT> ; MachineOperand & MO = MI . getOperand ( OpNo ) ; Offset += MO . getImm ( ) + MFI -> getStackSize ( ) + <ISA_LIT>FrameInfo :: minStackSize ( ) ; assert ( ( Offset & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; SPOp . ChangeToRegister ( <STR_LIT> , false ) ; if ( ( MI . getOpcode ( ) == <STR_LIT> && ! isInt < <NUM_LIT> > ( Offset ) ) || ! isInt < <NUM_LIT> > ( Offset ) ) { int newOpcode = convertDFormToXForm ( MI . getOpcode ( ) ) ; unsigned tmpReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; BuildMI ( MBB , II , dl , TII . get ( <STR_LIT> ) , tmpReg ) . addImm ( Offset ) ; BuildMI ( MBB , II , dl , TII . get ( newOpcode ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( tmpReg , RegState :: Kill ) . addReg ( <STR_LIT> ) ; MBB . erase ( II ) ; } else { MO . ChangeToImmediate ( Offset ) ;


<s> static SDValue combineFneg ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT SVT = VT . getScalarType ( ) ; SDValue Arg = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; if ( Arg . getOpcode ( ) == <STR_LIT> && ( SVT == <STR_LIT> || SVT == <STR_LIT> ) && Arg -> getFlags ( ) -> hasNoSignedZeros ( ) && Subtarget . hasAnyFMA ( ) ) { SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , DL , VT ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Zero ) ; } if ( Arg . hasOneUse ( ) ) { switch ( Arg . getOpcode ( ) ) { case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) , Arg . getOperand ( <NUM_LIT> ) ) ; } }


<s> SDValue <ISA_LIT>TargetLowering :: LowerFRAMEADDR ( SDValue Op , SelectionDAG & DAG ) const { MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ;

while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> RemBB -> splice ( RemBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; RemBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( LoopBB ) ; BB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( RemBB ) ; LoopBB -> addSuccessor ( LoopBB ) ; unsigned ShiftAmtReg = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftAmtReg2 = RI . createVirtualRegister ( & <STR_LIT> ) ; unsigned ShiftReg = RI . createVirtualRegister ( RC ) ; unsigned ShiftReg2 = RI . createVirtualRegister ( RC ) ; unsigned ShiftAmtSrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addReg ( ShiftAmtSrcReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( RemBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg ) . addReg ( ShiftAmtSrcReg ) . addMBB ( BB ) . addReg ( ShiftAmtReg2 ) . addMBB ( LoopBB ) ; BuildMI ( LoopBB , dl , TII . get ( Opc ) , ShiftReg2 ) . addReg ( ShiftReg ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) , ShiftAmtReg2 ) . addReg ( ShiftAmtReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( LoopBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( LoopBB ) ;

BuildMI ( * RemBB , RemBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addMBB ( BB ) . addReg ( ShiftReg2 ) . addMBB ( LoopBB ) ;


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> } if ( ! NewOpc ) continue ; unsigned UserOffset = GetUserOffset ( U ) ; unsigned MaxOffs = ( ( <NUM_LIT> << Bits ) - <NUM_LIT> ) * Scale ; if ( ! U . KnownAlignment ) MaxOffs -= <NUM_LIT> ; if ( CPEIsInRange ( U . MI , UserOffset , U . CPEMI , MaxOffs , false , true ) ) { U . MI -> setDesc ( TII -> get ( NewOpc ) ) ; MachineBasicBlock * MBB = U . MI -> getParent ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size -= <NUM_LIT> ; AdjustBBOffsetsAfter ( MBB ) ; ++ NumT2CPShrunk ; MadeChange = true ; } }

MadeChange |= OptimizeThumb2Branches ( ) ;


<s> return PosOpt ? Op -> getOperand ( * PosOpt ) : SDValue ( ) ;


<s> uint32_t ProtoTypeId ; const std :: unordered_map < uint32_t , StringRef > FuncArgNames ; visitSubroutineType ( SP -> getType ( ) , false , FuncArgNames , ProtoTypeId ) ; uint8_t Scope = <STR_LIT> ; auto FuncTypeEntry = std :: make_unique < BTFTypeFunc > ( SP -> getName ( ) , ProtoTypeId , Scope ) ; uint32_t FuncId = addType ( std :: move ( FuncTypeEntry ) ) ; if ( F -> hasSection ( ) ) { StringRef SecName = F -> getSection ( ) ; if ( DataSecEntries . find ( std :: string ( SecName ) ) == DataSecEntries . end ( ) ) { DataSecEntries [ std :: string ( SecName ) ] = std :: make_unique < BTFKindDataSec > ( Asm , std :: string ( SecName ) ) ; }

DataSecEntries [ std :: string ( SecName ) ] -> addDataSecEntry ( FuncId , Asm -> getSymbol ( F ) , <NUM_LIT> ) ;


<s> return ( int16x4_t ) __builtin_neon_vraddhnv4si ( __a , __b ) ;


<s> const APInt & Imm = ConstNode -> getAPIntValue ( ) ; if ( ( Imm + <NUM_LIT> ) . isPowerOf2 ( ) || ( Imm - <NUM_LIT> ) . isPowerOf2 ( ) || ( <NUM_LIT> - Imm ) . isPowerOf2 ( ) || ( - <NUM_LIT> - Imm ) . isPowerOf2 ( ) ) return true ; if ( Subtarget . hasStdExtM ( ) && VT . getSizeInBits ( ) >= Subtarget . getXLen ( ) ) return false ; if ( ! Imm . isSignedIntN ( <NUM_LIT> ) && Imm . countTrailingZeros ( ) < <NUM_LIT> ) {

APInt ImmS = Imm . ashr ( Imm . countTrailingZeros ( ) ) ;


<s> dbgs ( ) << <STR_LIT> ; for ( auto DI : ReachingDefs ) { NodeAddr < UseNode * > DA = DFG -> addr < UseNode * > ( DI ) ; NodeAddr < StmtNode * > TempIA = DA . Addr -> getOwner ( * DFG ) ; dbgs ( ) << <STR_LIT> << Print < NodeAddr < InstrNode * >> ( TempIA , * DFG ) << <STR_LIT> ; } } ) ; return false ;


<s> if ( ! GV . hasInitializer ( ) ) { continue ; } if ( ! isa < UndefValue > ( GV . getInitializer ( ) ) ) { continue ; } if ( GV . isConstant ( ) ) { continue ; } if ( ! shouldLowerLDSToStruct ( UsedList , GV , F ) ) { continue ; }


<s> bool mayNeedRelaxation ( const MCInst & Inst ) const {


<s> const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ; const <ISA_LIT>InstrInfo * TII = TM -> getSubtargetImpl ( ) -> getInstrInfo ( ) ; MachineInstr * Copy = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , <STR_LIT> ) . addReg ( TLSBaseAddrReg ) ;


<s> MF . getRegInfo ( ) . addLiveIn ( PReg , VReg ) ;


<s> auto Pred = static_cast < CmpInst :: Predicate > ( PredNum ) ; switch ( Pred ) { case CmpInst :: ICMP_EQ : return <STR_LIT> ; case CmpInst :: ICMP_NE : return <STR_LIT> ; default :


<s> int64_t FullOffset = Offset + getScratchInstrOffset ( MI ) ; if ( <ISA_LIT>InstrInfo :: isMUBUF ( * MI ) ) return ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( FullOffset ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; return TII -> isLegalFLATOffset ( FullOffset , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ;


<s> auto & TD = DAG . getDataLayout ( ) ; unsigned PrefAlign = TD . getPrefTypeAlignment ( ResVT . getTypeForEVT ( * DAG . getContext ( ) ) ) ; if ( Align < PrefAlign ) { return ; } EVT EltVT = ResVT . getVectorElementType ( ) ; unsigned NumElts = ResVT . getVectorNumElements ( ) ; bool NeedTrunc = false ; if ( EltVT . getSizeInBits ( ) < <NUM_LIT> ) { EltVT = <STR_LIT> ; NeedTrunc = true ; } unsigned Opcode = <NUM_LIT> ; SDVTList LdResVTs ; switch ( NumElts ) { default : return ; case <NUM_LIT> : Opcode = <STR_LIT> ; LdResVTs = DAG . getVTList ( EltVT , EltVT , <STR_LIT> ) ; break ; case <NUM_LIT> : { Opcode = <STR_LIT> ; EVT ListVTs [ ] = { EltVT , EltVT , EltVT , EltVT , <STR_LIT> } ; LdResVTs = DAG . getVTList ( ListVTs ) ; break ; } } SmallVector < SDValue , <NUM_LIT> > OtherOps ( N -> op_begin ( ) , N -> op_end ( ) ) ; OtherOps . push_back ( DAG . getIntPtrConstant ( LD -> getExtensionType ( ) , DL ) ) ; SDValue NewLD = DAG . getMemIntrinsicNode ( Opcode , DL , LdResVTs , OtherOps , LD -> getMemoryVT ( ) , LD -> getMemOperand ( ) ) ; SmallVector < SDValue , <NUM_LIT> > ScalarRes ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue Res = NewLD . getValue ( i ) ; if ( NeedTrunc ) Res = DAG . getNode ( <STR_LIT> , DL , ResVT . getVectorElementType ( ) , Res ) ; ScalarRes . push_back ( Res ) ; }

SDValue LoadChain = NewLD . getValue ( NumElts ) ;


<s> static DecodeStatus DecodeShiftRight32Imm ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ;


<s> if ( ! Subtarget -> hasSSE3orAVX ( ) ) return false ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) || ( VT . getSizeInBits ( ) == <NUM_LIT> && NumElems != <NUM_LIT> ) ) return false ;

for ( unsigned i = <NUM_LIT> ; i < NumElems ; i += <NUM_LIT> ) if ( ! isUndefOrEqual ( N -> getMaskElt ( i ) , i ) || ! isUndefOrEqual ( N -> getMaskElt ( i + <NUM_LIT> ) , i ) ) return false ;


<s> return __builtin_mve_vrmulhq_uv4si ( __a , __b ) ;


<s> const Register VirtReg = MO . getReg ( ) ; if ( VirtReg . isPhysical ( ) ) continue ; if ( ! VRM -> hasPhys ( VirtReg ) ) continue ; Register PhysReg = VRM -> getPhys ( VirtReg ) ; const unsigned SubReg = MO . getSubReg ( ) ; if ( SubReg != <NUM_LIT> ) { PhysReg = TRI -> getSubReg ( PhysReg , SubReg ) ; MO . setSubReg ( <NUM_LIT> ) ; } MO . setReg ( PhysReg ) ; MO . setIsRenamable ( false ) ; } } } <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned Reg : RegsToRewrite ) { LIS -> removeInterval ( Reg ) ; const Register PhysReg = VRM -> getPhys ( Reg ) ; assert ( PhysReg != <NUM_LIT> ) ; MFI -> reserveWWMRegister ( PhysReg ) ;


<s> SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ;

SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ;


<s> int64_t Value = CE -> getValue ( ) ;

return Value > <NUM_LIT> && Value <= <NUM_LIT> ;


<s> <ISA_LIT>FrameLowering ( StackDirection D , Align StackAl , int LAO , Align TransAl = Align :: None ( ) ) : <ISA_LIT>FrameLowering ( D , StackAl , LAO , TransAl ) {


<s> else gen_divmod4_1 = unsigned_p ? gen_udivmodsi4_zext_2 : gen_divmodsi4_zext_2 ; } else gen_divmod4_1 = unsigned_p ? gen_udivmodsi4_zext_1 : gen_divmodsi4_zext_1 ; break ; case E_DImode : gen_divmod4_1 = unsigned_p ? gen_udivmoddi4_1 : gen_divmoddi4_1 ; break ; default : gcc_unreachable ( ) ; } end_label = gen_label_rtx ( ) ; qimode_label = gen_label_rtx ( ) ; scratch = gen_reg_rtx ( mode ) ; emit_move_insn ( scratch , operands [ <NUM_LIT> ] ) ; scratch = expand_simple_binop ( mode , IOR , scratch , operands [ <NUM_LIT> ] , scratch , <NUM_LIT> , OPTAB_DIRECT ) ; emit_insn ( gen_test_ccno_1 ( mode , scratch , GEN_INT ( - <NUM_LIT> ) ) ) ; tmp0 = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; tmp0 = gen_rtx_EQ ( VOIDmode , tmp0 , const0_rtx ) ; tmp0 = gen_rtx_IF_THEN_ELSE ( VOIDmode , tmp0 , gen_rtx_LABEL_REF ( VOIDmode , qimode_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp0 ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = qimode_label ; emit_insn ( gen_divmod4_1 ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) ; emit_jump_insn ( gen_jump ( end_label ) ) ; emit_barrier ( ) ;


<s> const auto Arch = TT . getArch ( ) ; assert ( TT . is<ISA_LIT> ( ) ) ; return Arch == Triple :: spirv32 ? <NUM_LIT> : Arch == Triple :: spirv64 ? <NUM_LIT> : <NUM_LIT> ;


<s> clear_content_memory ( ) ; for ( insn = get_insns ( ) ; insn ; insn = curr ) { rtx pattern ; curr = insn ? next_nonnote_nondebug_insn ( insn ) : NULL ; if ( ! INSN_P ( insn ) ) { if ( LABEL_P ( insn ) ) clear_content_memory ( ) ; continue ; } if ( dump_file ) fprintf ( dump_file , <STR_LIT> , INSN_UID ( insn ) ) ; pattern = PATTERN ( insn ) ; if ( GET_CODE ( pattern ) == PARALLEL ) pattern = XVECEXP ( pattern , <NUM_LIT> , <NUM_LIT> ) ; if ( JUMP_P ( insn ) || CALL_P ( insn ) || GET_CODE ( pattern ) == CALL ) clear_content_memory ( ) ; if ( GET_CODE ( pattern ) != SET && GET_CODE ( pattern ) != CALL ) continue ; if ( GET_CODE ( pattern ) == SET && GET_CODE ( SET_SRC ( pattern ) ) == ASM_OPERANDS ) continue ; valloc_method = get_attr_valloc ( insn ) ; PATTERN ( insn ) = copy_rtx_if_shared ( PATTERN ( insn ) ) ; if ( valloc_method == VALLOC_MACAX ) { record_content ( AX , NULL_RTX ) ; record_content ( BC , NULL_RTX ) ; record_content ( DE , NULL_RTX ) ; } if ( insn_ok_now ( insn ) ) continue ; INSN_CODE ( insn ) = - <NUM_LIT> ; if ( RTX_FRAME_RELATED_P ( insn ) ) virt_insn_was_frame = <NUM_LIT> ; else virt_insn_was_frame = <NUM_LIT> ; switch ( valloc_method ) { case VALLOC_OP1 : rl78_alloc_physical_registers_op1 ( insn ) ; break ; case VALLOC_OP2 : rl78_alloc_physical_registers_op2 ( insn ) ; break ; case VALLOC_RO1 : rl78_alloc_physical_registers_ro1 ( insn ) ; break ; case VALLOC_CMP : rl78_alloc_physical_registers_cmp ( insn ) ; break ; case VALLOC_UMUL : rl78_alloc_physical_registers_umul ( insn ) ; break ;


<s> if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ;

return Value >= MinValue && Value <= MaxValue ;


<s> if ( ! matchShuffleWithSHUFPD ( VT , V1 , V2 , Immediate , Mask ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , DAG . getConstant ( Immediate , DL , <STR_LIT> ) ) ;


<s> gcc_assert ( srcp != NULL ) ; src = * srcp ; orig_src = src ; } for ( piece_size = <NUM_LIT> ; piece_size <= desired_align && copied_bytes < align_bytes ; piece_size <<= <NUM_LIT> ) { if ( align_bytes & piece_size ) { if ( issetmem ) { if ( vec_value && piece_size > GET_MODE_SIZE ( GET_MODE ( value ) ) ) dst = emit_memset ( dst , destreg , vec_value , piece_size ) ; else dst = emit_memset ( dst , destreg , value , piece_size ) ; } else dst = emit_memmov ( dst , & src , destreg , srcreg , piece_size ) ; copied_bytes += piece_size ; } } if ( MEM_ALIGN ( dst ) < ( unsigned int ) desired_align * BITS_PER_UNIT ) set_mem_align ( dst , desired_align * BITS_PER_UNIT ) ; if ( MEM_SIZE_KNOWN_P ( orig_dst ) ) set_mem_size ( dst , MEM_SIZE ( orig_dst ) - align_bytes ) ; if ( ! issetmem ) { int src_align_bytes = get_mem_align_offset ( src , desired_align * BITS_PER_UNIT ) ; if ( src_align_bytes >= <NUM_LIT> ) src_align_bytes = desired_align - src_align_bytes ; if ( src_align_bytes >= <NUM_LIT> ) { unsigned int src_align ; for ( src_align = desired_align ; src_align >= <NUM_LIT> ; src_align >>= <NUM_LIT> ) { if ( ( src_align_bytes & ( src_align - <NUM_LIT> ) ) == ( align_bytes & ( src_align - <NUM_LIT> ) ) ) break ;


<s> unsigned Reg = addLiveIn ( DAG . getMachineFunction ( ) , ArgReg , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) { unsigned Opcode = <NUM_LIT> ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) Opcode = <STR_LIT> ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) Opcode = <STR_LIT> ; if ( Opcode ) ArgValue = DAG . getNode ( Opcode , DL , RegVT , ArgValue , DAG . getValueType ( ValVT ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; } if ( ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) || ( RegVT == <STR_LIT> && ValVT == <STR_LIT> ) ) ArgValue = DAG . getNode ( <STR_LIT> , DL , ValVT , ArgValue ) ; InVals . push_back ( ArgValue ) ; } else { MVT LocVT = VA . getLocVT ( ) ; assert ( VA . isMemLoc ( ) ) ; int FI = MFI . CreateFixedObject ( ValVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Load = DAG . getLoad ( LocVT , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; InVals . push_back ( Load ) ; OutChains . push_back ( Load . getValue ( <NUM_LIT> ) ) ;


<s> return create<ISA_LIT>ELFStreamer ( Ctx , TAB , OS , Emitter , RelaxAll ) ;


<s> ScalarAlloc = - ScalarAlloc ; } generateStackAdjustment ( MBB , MBBI , * ST . getInstrInfo ( ) , DebugLoc ( ) , ScalarAlloc , <STR_LIT> ) ;


<s> switch ( Type ) { case ImmTyNone : OS << <STR_LIT> ; break ; case ImmTyGDS : OS << <STR_LIT> ; break ; case ImmTyOffen : OS << <STR_LIT> ; break ; case ImmTyIdxen : OS << <STR_LIT> ; break ; case ImmTyAddr64 : OS << <STR_LIT> ; break ; case ImmTyOffset : OS << <STR_LIT> ; break ; case ImmTyOffset0 : OS << <STR_LIT> ; break ; case ImmTyOffset1 : OS << <STR_LIT> ; break ; case ImmTyGLC : OS << <STR_LIT> ; break ; case ImmTySLC : OS << <STR_LIT> ; break ; case ImmTyTFE : OS << <STR_LIT> ; break ; case ImmTyClamp<ISA_LIT> : OS << <STR_LIT> ; break ; case ImmTyOMod<ISA_LIT> : OS << <STR_LIT> ; break ; case ImmTyDppCtrl : OS << <STR_LIT> ; break ; case ImmTyDppRowMask : OS << <STR_LIT> ; break ; case ImmTyDppBankMask : OS << <STR_LIT> ; break ; case ImmTyDppBoundCtrl : OS << <STR_LIT> ; break ; case ImmTySdwaDstSel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc0Sel : OS << <STR_LIT> ; break ; case ImmTySdwaSrc1Sel : OS << <STR_LIT> ; break ; case ImmTySdwaDstUnused : OS << <STR_LIT> ; break ; case ImmTyDMask : OS << <STR_LIT> ; break ; case ImmTyUNorm : OS << <STR_LIT> ; break ; case ImmTyDA : OS << <STR_LIT> ; break ; case ImmTyR128 : OS << <STR_LIT> ; break ; case ImmTyLWE : OS << <STR_LIT> ; break ; case ImmTyOff : OS << <STR_LIT> ; break ; case ImmTyExpTgt : OS << <STR_LIT> ; break ; case ImmTyExpCompr : OS << <STR_LIT> ; break ; case ImmTyExpVM : OS << <STR_LIT> ; break ; case ImmTyHwreg : OS << <STR_LIT> ; break ; case ImmTySendMsg : OS << <STR_LIT> ; break ; case ImmTyInterpSlot : OS << <STR_LIT> ; break ; case ImmTyInterpAttr : OS << <STR_LIT> ; break ; case ImmTyAttrChan : OS << <STR_LIT> ; break ;

case ImmTyOpSel : OS << <STR_LIT> ; break ;


<s> static unsigned PromoteRegTo64 ( unsigned RegIn ) { if ( RegIn == <NUM_LIT> ) return <NUM_LIT> ; unsigned RegOut = get<ISA_LIT>SubSuperRegister ( RegIn , <STR_LIT> , false ) ; assert ( RegOut != <NUM_LIT> ) ;


<s> return MCDisassembler :: Fail ; } tmp = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( DecodeVRFRegisterClass ( Inst , tmp , Address , Decoder ) == MCDisassembler :: Fail ) { return MCDisassembler :: Fail ; } auto * Disasm = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; Inst . addOperand ( MCOperand :: createImm ( Disasm -> getImmediate ( ) ) ) ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( tmp ) ) ; tmp = fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) ; if ( DecodeVRFRegisterClass ( Inst , tmp , Address , Decoder ) == MCDisassembler :: Fail ) { return MCDisassembler :: Fail ; } tmp = <NUM_LIT> ;

tmp |= fieldFromInstruction ( insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ;


<s> return new pass_analyze_swaps ( ctxt ) ;


<s> unsigned FRINTXOpcs [ ] = { <STR_LIT> , <STR_LIT> } ; if ( VT == <STR_LIT> ) { Variant = <NUM_LIT> ; } else if ( VT == <STR_LIT> ) { Variant = <NUM_LIT> ; } else return nullptr ; unsigned FRINTXOpc = FRINTXOpcs [ Variant ] ; switch ( N -> getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : { unsigned FRINTPOpcs [ ] = { <STR_LIT> , <STR_LIT> } ; Opc = FRINTPOpcs [ Variant ] ; break ; } case <STR_LIT> : { unsigned FRINTMOpcs [ ] = { <STR_LIT> , <STR_LIT> } ; Opc = FRINTMOpcs [ Variant ] ; break ; } case <STR_LIT> : { unsigned FRINTZOpcs [ ] = { <STR_LIT> , <STR_LIT> } ; Opc = FRINTZOpcs [ Variant ] ; break ; } case <STR_LIT> : { unsigned FRINTAOpcs [ ] = { <STR_LIT> , <STR_LIT> } ;


<s> SDLoc dl ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , PtrVT ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ;


<s> static bool aarch64_hard_regno_mode_ok ( unsigned regno , machine_mode mode ) { if ( GET_MODE_CLASS ( mode ) == MODE_CC ) return regno == CC_REGNUM ; if ( regno == VG_REGNUM ) return mode == DImode ; unsigned int vec_flags = aarch64_classify_vector_mode ( mode ) ; if ( vec_flags & VEC_SVE_PRED ) return PR_REGNUM_P ( regno ) ; if ( PR_REGNUM_P ( regno ) ) return <NUM_LIT> ; if ( regno == SP_REGNUM ) return mode == Pmode || mode == ptr_mode ; if ( regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM ) return mode == Pmode ;


<s> bool <ISA_LIT>LinuxAsmPrinter :: doFinalization ( Module & M ) { const DataLayout * TD = TM . getSubtargetImpl ( ) -> getDataLayout ( ) ; bool is<ISA_LIT>64 = TD -> getPointerSizeInBits ( ) == <NUM_LIT> ; <ISA_LIT>TargetStreamer & TS = static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer . getTargetStreamer ( ) ) ; if ( ! TOC . empty ( ) ) { const MCSectionELF * Section ; if ( is<ISA_LIT>64 ) Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; else Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = OutContext . GetOrCreateSymbol ( I -> first -> getName ( ) ) ; if ( is<ISA_LIT>64 ) TS . emitTCEntry ( * S ) ;

else OutStreamer . EmitSymbolValue ( S , <NUM_LIT> ) ;


<s> for ( auto & Op : MI -> operands ( ) ) { if ( ! Op . isReg ( ) ) { NewI -> addOperand ( Op ) ; continue ; } Register R = Op . getReg ( ) ; unsigned SR = Op . getSubReg ( ) ; bool isVirtReg = R . isVirtual ( ) ; bool isKill = Op . isKill ( ) ; if ( isVirtReg && MRI -> getRegClass ( R ) == DoubleRC ) { isKill = false ; UUPairMap :: const_iterator F = PairMap . find ( R ) ; if ( F == PairMap . end ( ) ) { SR = SubR ; } else { const UUPair & P = F -> second ; R = ( SubR == <STR_LIT> ) ? P . first : P . second ; SR = <NUM_LIT> ; } } auto CO = MachineOperand :: CreateReg ( R , Op . isDef ( ) , Op . isImplicit ( ) , isKill , Op . isDead ( ) , Op . isUndef ( ) , Op . isEarlyClobber ( ) , SR , Op . isDebug ( ) , Op . isInternalRead ( ) ) ; NewI -> addOperand ( CO ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T , Triple :: OSType _OSType ) : MCAsmBackend ( ) , OSType ( _OSType ) {


<s> const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind ; const <ISA_LIT>Subtarget & Subtarget = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isThumb2 ( ) ) Kind = MCFixupKind ( <STR_LIT> ) ; else Kind = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , Kind ) ) ; ++ MCNumCPRelocations ;


<s> void <ISA_LIT>TargetELFStreamer :: emitFrame ( unsigned StackReg , unsigned StackSize , unsigned ReturnReg ) {


<s> return isRegClass ( <STR_LIT> ) || isRegClass ( <STR_LIT> ) || isRegClass ( <STR_LIT> ) || isRegClass ( <STR_LIT> ) || isRegClass ( <STR_LIT> ) || isRegClass ( <STR_LIT> ) || isRegClass ( <STR_LIT> ) || isRegClass ( <STR_LIT> ) ;


<s> UHItype carries = ( UHItype ) uu . s . low >> bm ; w . s . low = ( UHItype ) uu . s . low << b ; w . s . high = ( ( UHItype ) uu . s . high << b ) | carries ; } return w . ll ;


<s> for ( MachineBasicBlock & BB : MF ) { bool InsideFrameSequence = false ; for ( MachineInstr & MI : BB ) { if ( MI . getOpcode ( ) == FrameSetupOpcode ) { if ( TII -> getFrameSize ( MI ) >= StackProbeSize && EmitStackProbeCall ) return false ; if ( InsideFrameSequence ) return false ; InsideFrameSequence = true ; } else if ( MI . getOpcode ( ) == FrameDestroyOpcode ) { if ( ! InsideFrameSequence ) return false ; InsideFrameSequence = false ;


<s> MCAsmParserExtension :: Initialize ( Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( AddBuildAttributes ) getTargetStreamer ( ) . emitTargetAttributes ( STI ) ; ITState . CurPosition = ~ <NUM_LIT> ; VPTState . CurPosition = ~ <NUM_LIT> ;


<s> rtx base , offset ; if ( splittable_const_int_operand ( src , mode ) ) { riscv_move_integer ( dest , dest , INTVAL ( src ) ) ; return ; } if ( riscv_split_symbol ( dest , src , MAX_MACHINE_MODE , & src ) ) { riscv_emit_set ( dest , src ) ; return ; } if ( riscv_tls_symbol_p ( src ) ) { riscv_emit_move ( dest , riscv_legitimize_tls_address ( src ) ) ; return ; } split_const ( src , & base , & offset ) ; if ( offset != const0_rtx && ( targetm . cannot_force_const_mem ( mode , src ) || can_create_pseudo_p ( ) ) ) {

base = riscv_force_temporary ( dest , base ) ;


<s> if ( Tok . is ( AsmToken :: Identifier ) ) { std :: string lowerCase = Tok . getString ( ) . lower ( ) ; RegNum = matchRegisterName ( lowerCase ) ;

} else if ( Tok . is ( AsmToken :: Integer ) ) RegNum = matchRegisterByNumber ( static_cast < unsigned > ( Tok . getIntVal ( ) ) , Mnemonic . lower ( ) ) ;


<s> if ( Val == DoubleToBits ( - <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( - <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( <NUM_LIT> ) ) return <NUM_LIT> ;


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> <ISA_LIT>MCAsmInfo :: ~ <ISA_LIT>MCAsmInfo ( ) {


<s> MBB . splice ( std :: next ( I ) , & MBB , FI , I ) ; FilledSlots += <NUM_LIT> ; } else { if ( ! NopDelaySlotFiller && findDelayInstr ( MBB , I , J ) ) { MBB . splice ( std :: next ( I ) , & MBB , J ) ; } else { BuildMI ( MBB , std :: next ( I ) , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; } ++ FilledSlots ; } Changed = true ; LastFiller = ++ I ; MIBundleBuilder ( MBB , InstrWithSlot , std :: next ( LastFiller ) ) ; } } return Changed ;


<s> bool isFGR64Asm ( ) const { return Kind == k_Register && Reg . Kind == Kind_FGR64Regs ;


<s> if ( ! getBranchInfo ( * I ) . hasMBBTarget ( ) ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; }


<s> printThumbAddrModeImm5SOperand ( MI , Op , O , <NUM_LIT> ) ;


<s> static int loongarch_address_cost ( rtx addr , machine_mode mode , addr_space_t as ATTRIBUTE_UNUSED , bool speed ATTRIBUTE_UNUSED ) {

return loongarch_address_insns ( addr , mode , false ) ;


<s> gcc_unreachable ( ) ; } } gcc_assert ( TARGET_SPE ) ; cst = INTVAL ( CONST_VECTOR_ELT ( vec , <NUM_LIT> ) ) ; cst2 = INTVAL ( CONST_VECTOR_ELT ( vec , <NUM_LIT> ) ) ; operands [ <NUM_LIT> ] = CONST_VECTOR_ELT ( vec , <NUM_LIT> ) ; operands [ <NUM_LIT> ] = CONST_VECTOR_ELT ( vec , <NUM_LIT> ) ; if ( cst == cst2 ) return <STR_LIT> ; else return <STR_LIT> ;


<s> Metadata * LowAndHigh [ ] = { ConstantAsMetadata :: get ( ConstantInt :: get ( I32Ty , Lower -> getValue ( ) . zext ( <NUM_LIT> ) ) ) , ConstantAsMetadata :: get ( ConstantInt :: get ( I32Ty , <NUM_LIT> ) ) } ; WidenLoad -> setMetadata ( LLVMContext :: MD_range , MDNode :: get ( Mod -> getContext ( ) , LowAndHigh ) ) ; } } int TySize = Mod -> getDataLayout ( ) . getTypeSizeInBits ( I . getType ( ) ) ; Type * IntNTy = Builder . getIntNTy ( TySize ) ; Value * ValTrunc = Builder . CreateTrunc ( WidenLoad , IntNTy ) ;

Value * ValOrig = Builder . CreateBitCast ( ValTrunc , I . getType ( ) ) ;


<s> return aarch64_classify_address ( & addr , x , mode , outer_code , strict_p ) ;


<s> if ( ! TPC ) return false ; auto & TM = TPC -> getTM < <ISA_LIT>TargetMachine > ( ) ; ST = TM . getSubtargetImpl ( F ) ; DL = & F . getParent ( ) -> getDataLayout ( ) ; bool MadeChange = false ; for ( auto & BB : F ) {


<s> bool <ISA_LIT>RegisterInfo :: isSGPRReg ( const MachineRegisterInfo & MRI , Register Reg ) const {


<s> } addPass ( createSinkingPass ( ) ) ; addPass ( create<ISA_LIT>AnnotateUniformValues ( ) ) ; if ( ! LateCFGStructurize ) { addPass ( create<ISA_LIT>AnnotateControlFlowPass ( ) ) ; }


<s> explicit value ( Value * Val , const value_var & v ) { * static_cast < value_var * > ( this ) = v ;


<s> for ( auto J : CurrentPacketMIs ) { noSlot1Store |= HII -> isRestrictNoSlot1Store ( * J ) ; isSlot0Only |= HII -> isPureSlot0 ( * J ) ;


<s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : SRetReturnReg ( <NUM_LIT> ) , HasClobberLR ( <NUM_LIT> ) , HasEHReturn ( false ) {


<s> if ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) return <STR_LIT> ; return <STR_LIT> ; } if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST_INT && ( logval = exact_log2 ( INTVAL ( operands [ <NUM_LIT> ] ) & <NUM_LIT> ) ) >= <NUM_LIT> && ( DATA_REG_P ( operands [ <NUM_LIT> ] ) || offsettable_memref_p ( operands [ <NUM_LIT> ] ) ) ) { if ( DATA_REG_P ( operands [ <NUM_LIT> ] ) ) operands [ <NUM_LIT> ] = GEN_INT ( logval ) ; else { operands [ <NUM_LIT> ] = adjust_address ( operands [ <NUM_LIT> ] , SImode , <NUM_LIT> - ( logval / <NUM_LIT> ) ) ; operands [ <NUM_LIT> ] = GEN_INT ( logval % <NUM_LIT> ) ; } return <STR_LIT> ; } if ( ! side_effects_p ( operands [ <NUM_LIT> ] ) ) flags_operand1 = operands [ <NUM_LIT> ] ; flags_valid = FLAGS_VALID_YES ;


<s> return new <ISA_LIT>CFGStructurizer ( ) ;


<s> const TargetInstrDesc & TID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( TID . getNumDefs ( ) == <NUM_LIT> ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( TID . getSchedClass ( ) , <NUM_LIT> ) > <NUM_LIT> ) return Sched :: Latency ;


<s> const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; BitVector Reserved ( getNumRegs ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) || TT . isOSDarwin ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < <STR_LIT> . getNumRegs ( ) ; ++ i ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isXRegisterReserved ( i ) ) markSuperRegs ( Reserved , <STR_LIT> . getRegister ( i ) ) ;


<s> Other = N -> getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } DebugLoc dl = N -> getDebugLoc ( ) ; SDValue LL , RL , AddendL , AddendH ; LL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mul . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; RL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Mul . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; AddendL = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Other , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; AddendH = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Other , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; APInt HighMask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; unsigned LHSSB = DAG . ComputeNumSignBits ( Mul . getOperand ( <NUM_LIT> ) ) ; unsigned RHSSB = DAG . ComputeNumSignBits ( Mul . getOperand ( <NUM_LIT> ) ) ; if ( DAG . MaskedValueIsZero ( Mul . getOperand ( <NUM_LIT> ) , HighMask ) && DAG . MaskedValueIsZero ( Mul . getOperand ( <NUM_LIT> ) , HighMask ) ) { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , AddendH , AddendL , LL , RL ) ; SDValue Lo ( Hi . getNode ( ) , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } if ( LHSSB > <NUM_LIT> && RHSSB > <NUM_LIT> ) { SDValue Hi = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , AddendH , AddendL , LL , RL ) ;


<s> return new <ISA_LIT>TargetELFStreamer ( S , STI ) ;


<s> param_iterator ret_begin ( ) const { return ReturnParams . begin ( ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getJumpTableEncoding ( ) const {

if ( isPositionIndependent ( ) ) return MachineJumpTableInfo :: EK_Custom32 ;


<s> if ( isVShiftLImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , Cnt ) ) return DAG . getNode ( <STR_LIT> , N -> getDebugLoc ( ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , <STR_LIT> ) ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( isVShiftRImm ( N -> getOperand ( <NUM_LIT> ) , VT , false , false , Cnt ) ) { unsigned VShiftOpc = ( N -> getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return DAG . getNode ( VShiftOpc , N -> getDebugLoc ( ) , VT , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Cnt , <STR_LIT> ) ) ; } }


<s> const Constant * C = dyn_cast < Constant > ( V ) ; if ( C && C -> getSplatValue ( ) ) return Optional < int64_t > { C -> getUniqueInteger ( ) . getSExtValue ( ) } ; if ( ! isa < Instruction > ( V ) ) return Optional < int64_t > { } ; const Instruction * I = cast < Instruction > ( V ) ; if ( I -> getOpcode ( ) == Instruction :: Add || I -> getOpcode ( ) == Instruction :: Or || I -> getOpcode ( ) == Instruction :: Mul || I -> getOpcode ( ) == Instruction :: Shl ) { Optional < int64_t > Op0 = getIfConst ( I -> getOperand ( <NUM_LIT> ) ) ; Optional < int64_t > Op1 = getIfConst ( I -> getOperand ( <NUM_LIT> ) ) ; if ( ! Op0 || ! Op1 ) return Optional < int64_t > { } ; if ( I -> getOpcode ( ) == Instruction :: Add ) return Optional < int64_t > { Op0 . getValue ( ) + Op1 . getValue ( ) } ;

if ( I -> getOpcode ( ) == Instruction :: Mul ) return Optional < int64_t > { Op0 . getValue ( ) * Op1 . getValue ( ) } ;


<s> if ( Subtarget . is<ISA_LIT>64 ( ) && Directive < <STR_LIT> ) Directive = <STR_LIT> ; assert ( Directive <= <STR_LIT> && <STR_LIT> ) ; if ( OutStreamer . hasRawTextSupport ( ) ) OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CPUDirectives [ Directive ] ) ) ; const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; }

OutStreamer . SwitchSection ( getObjFileLowering ( ) . getTextSection ( ) ) ;


<s> void <ISA_LIT>TargetLowering :: addAllExtLoads ( const MVT From , const MVT To , LegalizeAction Action ) { setLoadExtAction ( <STR_LIT> , From , To , Action ) ; setLoadExtAction ( <STR_LIT> , From , To , Action ) ; setLoadExtAction ( <STR_LIT> , From , To , Action ) ;


<s> LoadReg = createResultReg ( RC ) ; MachineInstrBuilder LoadMI = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , LoadReg ) ; addFullAddress ( LoadMI , StubAM ) ; leaveLocalValueArea ( SaveInsertPt ) ; LocalValueMap [ V ] = LoadReg ; } AM . Base . Reg = LoadReg ; AM . GV = nullptr ; return true ; } } if ( ! AM . GV || ! Subtarget -> isPICStyleRIPRel ( ) ) { if ( AM . Base . Reg == <NUM_LIT> ) { AM . Base . Reg = getRegForValue ( V ) ; return AM . Base . Reg != <NUM_LIT> ; } if ( AM . IndexReg == <NUM_LIT> ) { assert ( AM . Scale == <NUM_LIT> && <STR_LIT> ) ; AM . IndexReg = getRegForValue ( V ) ; return AM . IndexReg != <NUM_LIT> ; } }


<s> rtx src = op [ <NUM_LIT> ] ; rtx base = XEXP ( dest , <NUM_LIT> ) ; int reg_base = REGNO ( XEXP ( base , <NUM_LIT> ) ) ; int reg_src = true_regnum ( src ) ; if ( reg_src == reg_base ) { return avr_asm_len ( <STR_LIT> CR_TAB <STR_LIT> CR_TAB TINY_ADIW ( % I0 , % J0 , % o0 ) CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB <STR_LIT> CR_TAB TINY_SBIW ( % I0 , % J0 , % o0 + <NUM_LIT> ) , op , plen , - <NUM_LIT> ) ; }

else if ( reg_src == reg_base - <NUM_LIT> ) {


<s> return true ; } if ( RegNo == <NUM_LIT> ) { return ! EmitError || Error ( S , <STR_LIT> ) ; } SMLoc E = Lexer . getLoc ( ) ; Lexer . Lex ( ) ; Operands . push_back ( std :: unique_ptr < MCParsedAsmOperand > ( <ISA_LIT>Operand :: CreateReg ( RegNo , S , E ) ) ) ;


<s> return __builtin_mve_vbrsrq_m_n_sv4si ( __arm_vuninitializedq_s32 ( ) , __a , __b , __p ) ;


<s> bool <ISA_LIT>TargetLowering :: shouldConvertConstantLoadToIntImm ( const APInt & Imm , Type * Ty ) const { assert ( Ty -> isIntegerTy ( ) ) ; unsigned BitSize = Ty -> getPrimitiveSizeInBits ( ) ; return ! ( BitSize == <NUM_LIT> || BitSize > <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; }


<s> uint32_t <ISA_LIT>CallingConvHook :: getNumOfArgs ( StringRef fName ) { uint32_t count = <NUM_LIT> ; for ( auto & rec : regRecord ) { if ( rec . fName . compare ( fName ) == <NUM_LIT> ) count ++ ; } return count ;


<s> return ( h8300_interrupt_function_p ( current_function_decl ) || h8300_monitor_function_p ( current_function_decl ) ) ;


<s> HII = ST . getInstrInfo ( ) ; HRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; Changed = removeDeadCode ( MDT -> getRootNode ( ) ) ; const <ISA_LIT>Evaluator HE ( * HRI , * MRI , * HII , MF ) ; BitTracker BTLoc ( HE , MF ) ; BTLoc . trace ( isDebug ( ) ) ; BTLoc . run ( ) ; CellMapShadow MS ( BTLoc ) ; CMS = & MS ; buildOrderingMF ( BaseOrd ) ; buildOrderingBT ( BaseOrd , CellOrd ) ; if ( isDebug ( ) ) { dbgs ( ) << <STR_LIT> ; for ( RegisterOrdering :: iterator I = CellOrd . begin ( ) , E = CellOrd . end ( ) ; I != E ; ++ I ) { unsigned VR = I -> first , Pos = I -> second ; dbgs ( ) << PrintReg ( VR , HRI ) << <STR_LIT> << Pos << <STR_LIT> ; } } MachineBasicBlock * RootB = MDT -> getRoot ( ) ; OrderedRegisterList AvailR ( CellOrd ) ; { NamedRegionTimer _T ( <STR_LIT> , <STR_LIT> , TimingDetail ) ; collectInBlock ( RootB , AvailR ) ; computeRemovableRegisters ( ) ; } if ( isDebug ( ) ) { dbgs ( ) << <STR_LIT> ; dump_map ( ) ; } if ( IFMap . empty ( ) ) return Changed ; {


<s> return D ( <STR_LIT> , R ( a ) , <STR_LIT> ) ;


<s> if ( T -> isFloatingPointTy ( ) ) return true ;


<s> fputs ( <STR_LIT> , file ) ; output_addr_const ( file , plus_constant ( x , TLS_BIAS ) ) ;


<s> if ( ! hasV60Ops ( ) ) return ; auto & QII = static_cast < const <ISA_LIT>InstrInfo & > ( * getInstrInfo ( ) ) ; if ( QII . isHVXVec ( SrcInst ) || useBSBScheduling ( ) ) Dep . setLatency ( ( Dep . getLatency ( ) + <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> void notice_update_cc ( rtx exp ) { if ( GET_CODE ( exp ) == SET ) { if ( SET_DEST ( exp ) == pc_rtx ) return ; if ( REG_P ( SET_DEST ( exp ) ) && ( REG_P ( SET_SRC ( exp ) ) || GET_CODE ( SET_SRC ( exp ) ) == MEM ) ) {


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( <ISA_LIT>Subtarget & st , const <ISA_LIT>InstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , Subtarget ( st ) , TII ( tii ) {


<s> SDLoc DL ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ;

auto * TFL = static_cast < const <ISA_LIT>FrameLowering * > ( Subtarget . getFrameLowering ( ) ) ;


<s> Expr = <ISA_LIT>MCExpr :: create ( Expr , <ISA_LIT>MCExpr :: VK_TLSDESC , getContext ( ) ) ; MCInst Inst ; Inst . setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ; getParser ( ) . getStreamer ( ) . EmitInstruction ( Inst , STI ) ; return false ;


<s> MCOperand MCOp ; switch ( MO . getType ( ) ) { default : MI . print ( errs ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) continue ; MCOp = MCOperand :: createReg ( MO . getReg ( ) ) ; break ; case MachineOperand :: MO_Immediate : MCOp = MCOperand :: createImm ( MO . getImm ( ) ) ;


<s> bool HasStackObject = false ; for ( unsigned i = <NUM_LIT> , e = MFFrame . getObjectIndexEnd ( ) ; i != e ; ++ i ) if ( ! MFFrame . isDeadObjectIndex ( i ) ) { HasStackObject = true ; break ; } if ( HasStackObject || MFFrame . hasCalls ( ) ) StackSize += <STR_LIT> ; StackSize = StackSize > <STR_LIT> ? StackSize - <STR_LIT> : <NUM_LIT> ; MFFrame . setStackSize ( StackSize ) ; if ( StackSize ) { bool StoreBackchain = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) ; int64_t Delta = - int64_t ( StackSize ) ; emitIncrement ( MBB , MBBI , DL , <STR_LIT> , Delta , ZII ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , SPOffsetFromCFA + Delta ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; SPOffsetFromCFA += Delta ; if ( StoreBackchain ) BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) ; } if ( HasFP ) { BuildMI ( MBB , MBBI , DL , ZII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; unsigned HardFP = MRI -> getDwarfRegNum ( <STR_LIT> , true ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaRegister ( nullptr , HardFP ) ) ; BuildMI ( MBB , MBBI , DL , ZII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; for ( auto I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( <STR_LIT> ) ; } SmallVector < unsigned , <NUM_LIT> > CFIIndexes ; for ( auto & Save : CSI ) { unsigned Reg = Save . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( <STR_LIT> . contains ( Reg ) ) { if ( MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ++ MBBI ; else llvm_unreachable ( <STR_LIT> ) ; } else continue ; unsigned DwarfReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned IgnoredFrameReg ;

int64_t Offset = getFrameIndexReference ( MF , Save . getFrameIdx ( ) , IgnoredFrameReg ) ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_ProcIFlags ) ;


<s> if ( auto * Branch = dyn_cast < BranchInst > ( Terminator ) ) { if ( Branch -> getSuccessor ( <NUM_LIT> ) == OriginalBB ) { Branch -> setSuccessor ( <NUM_LIT> , NewBB ) ; return ; } assert ( Branch -> isConditional ( ) && <STR_LIT> ) ; assert ( Branch -> getSuccessor ( <NUM_LIT> ) == OriginalBB && <STR_LIT> ) ; Branch -> setSuccessor ( <NUM_LIT> , NewBB ) ; return ; }


<s> getTargetStreamer ( ) . emitARM64WinCFISaveNext ( ) ;


<s> vs8 = ( __vector signed short ) ( __vector unsigned long long ) { __A , __A } ; vi4 = vec_vupklsh ( vs8 ) ; vf1 = ( __vector float ) vec_ctf ( vi4 , <NUM_LIT> ) ; return ( __m128 ) vf1 ;


<s> rtx pattern = PATTERN ( insn ) ; rtx unspec ; if ( GET_CODE ( pattern ) != SET ) return false ; if ( GET_CODE ( SET_SRC ( pattern ) ) != LO_SUM ) return false ; if ( GET_CODE ( XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) ) != CONST ) return false ; unspec = XEXP ( XEXP ( SET_SRC ( pattern ) , <NUM_LIT> ) , <NUM_LIT> ) ;

return ( GET_CODE ( unspec ) == UNSPEC && XINT ( unspec , <NUM_LIT> ) == UNSPEC_PCREL_SYM ) ;


<s> if ( TruncInst * Trunc = dyn_cast < TruncInst > ( Input ) ) { Value * PreTrunc = Trunc -> getOperand ( <NUM_LIT> ) ; Type * PreTruncTy = PreTrunc -> getType ( ) ; if ( PreTruncTy -> getPrimitiveSizeInBits ( ) == <NUM_LIT> ) { Input = PreTrunc ; InputTy = PreTruncTy ; } } if ( InputTy -> getPrimitiveSizeInBits ( ) != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> ) ; return nullptr ; } GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ; Value * Offsets ; Value * BasePtr = checkGEP ( Offsets , InputTy , GEP , Builder ) ; if ( ! BasePtr ) return nullptr ; Value * Store = tryCreateIncrementingGatScat ( I , BasePtr , Offsets , GEP , Builder ) ; if ( Store ) return Store ; int Scale = computeScale ( BasePtr -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) , MemoryTy -> getScalarSizeInBits ( ) ) ; if ( Scale == - <NUM_LIT> ) return nullptr ; if ( ! match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { BasePtr -> getType ( ) , Offsets -> getType ( ) , Input -> getType ( ) , Mask -> getType ( ) } , { BasePtr , Offsets , Input , Builder . getInt32 ( MemoryTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Mask } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { BasePtr -> getType ( ) , Offsets -> getType ( ) , Input -> getType ( ) } , { BasePtr , Offsets , Input , Builder . getInt32 ( MemoryTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) } ) ;


<s> SDLoc dl ( Op ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; const <ISA_LIT>BaseRegisterInfo * ARI = Subtarget -> getRegisterInfo ( ) ; const uint32_t * Mask = ARI -> getCallPreservedMask ( DAG . getMachineFunction ( ) , CallingConv :: C ) ; assert ( Mask && <STR_LIT> ) ; Register Reg = MF . addLiveIn ( <STR_LIT> , getRegClassFor ( <STR_LIT> ) ) ; SDValue ReturnAddress = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Reg , PtrVT ) ;

constexpr EVT ResultTys [ ] = { <STR_LIT> , <STR_LIT> } ;


<s> for ( auto & Frontier : MDF . find ( SubE -> getEHPad ( ) ) -> second ) if ( MDT . dominates ( EHPad , Frontier ) ) WL . push_back ( Frontier ) ; } continue ; } changeExceptionFor ( MBB , WE ) ; ++ NumBlocks ; for ( auto * Succ : MBB -> successors ( ) ) if ( MDT . dominates ( EHPad , Succ ) ) WL . push_back ( Succ ) ; } WE -> getSubExceptions ( ) . reserve ( NumSubExceptions ) ; WE -> reserveBlocks ( NumBlocks ) ;


<s> void <ISA_LIT>SEInstrInfo :: ExpandRetRA ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned Opc ) const {

BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) ) . addReg ( <STR_LIT> ) ;


<s> unsigned <ISA_LIT>ELFObjectWriter :: getRelocType ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_SecRel_8 :


<s> HII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ;

HRI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ;


<s> static unsigned int aarch64_call_properties ( aarch64_simd_builtin_datum * d ) { unsigned int flags = d -> flags ; if ( ! ( flags & FLAG_AUTO_FP ) && FLOAT_MODE_P ( d -> mode ) ) flags |= FLAG_FP ; if ( ! flag_trapping_math ) flags &= ~ FLAG_RAISE_FP_EXCEPTIONS ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {

AU . addRequired < MemoryDependenceWrapperPass > ( ) ;


<s> SDValue RegCopy = CurDAG -> getCopyFromReg ( Chain , dl , GPVR , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue Sub0 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue Sub1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue T0 = CurDAG -> getCopyToReg ( Sub0 , dl , Reg0 , Sub0 , RegCopy . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , Ops ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( createGPRPairNode ( <STR_LIT> , T0 , T1 ) , <NUM_LIT> ) ; Register GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; Chain = CurDAG -> getCopyToReg ( T1 , dl , GPVR , Pair , T1 . getValue ( <NUM_LIT> ) ) ; AsmNodeOperands [ InlineAsm :: Op_InputChain ] = Chain ; Glue = Chain . getValue ( <NUM_LIT> ) ; } Changed = true ; if ( PairedReg . getNode ( ) ) { OpChanged [ OpChanged . size ( ) - <NUM_LIT> ] = true ; Flag = InlineAsm :: getFlagWord ( Kind , <NUM_LIT> ) ; if ( IsTiedToChangedOp ) Flag = InlineAsm :: getFlagWordForMatchingOp ( Flag , DefIdx ) ; else Flag = InlineAsm :: getFlagWordForRegClass ( Flag , <STR_LIT> ) ; AsmNodeOperands [ AsmNodeOperands . size ( ) - <NUM_LIT> ] = CurDAG -> getTargetConstant ( Flag , dl , <STR_LIT> ) ;

AsmNodeOperands . push_back ( PairedReg ) ;


<s> uint64_t SplatBits = APSplatBits . getZExtValue ( ) ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : report_fatal_error ( <STR_LIT> + Twine ( VT . getEVTString ( ) ) ) ; case <STR_LIT> : { uint32_t Value32 = uint32_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( Value32 , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T , T , T ) ) ; } case <STR_LIT> : { uint64_t f64val = uint64_t ( SplatBits ) ; assert ( SplatBitSize == <NUM_LIT> && <STR_LIT> ) ; SDValue T = DAG . getConstant ( f64val , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , T , T ) ) ; }


<s> OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOC , OutContext ) , <NUM_LIT> ) ; OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer . SwitchSection ( Current ) ; MCSymbol * RealFnSym = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitLabel ( RealFnSym ) ; CurrentFnSymForSize = RealFnSym ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; }


<s> StringRef getPassName ( ) const override {


<s> return IREmitter :: visitSUB ( N ) ;


<s> case FRAME_POINTER_REGNUM : switch ( to ) { case HARD_FRAME_POINTER_REGNUM : if ( current_function_is_leaf ) offset = - current_frame_info . total_size ; else offset = - ( current_frame_info . total_size - current_function_outgoing_args_size - <NUM_LIT> ) ; break ; case STACK_POINTER_REGNUM : if ( current_function_is_leaf ) offset = <NUM_LIT> ; else offset = <NUM_LIT> + current_function_outgoing_args_size ; break ; default :


<s> uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; FrameSize = alignTo ( FrameSize , StackAlign ) ; MFI . setStackSize ( FrameSize ) ;


<s> MachineFunction * MF = MBB . getParent ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( Subtarget . getInstrInfo ( ) ) ; DebugLoc DL ; bool CRSpilled = false ; MachineInstrBuilder CRMIB ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == <STR_LIT> && ! Subtarget . isDarwinABI ( ) ) continue ; bool IsCRField = <STR_LIT> <= Reg && Reg <= <STR_LIT> ; MBB . addLiveIn ( Reg ) ; if ( CRSpilled && IsCRField ) { CRMIB . addReg ( Reg , RegState :: ImplicitKill ) ;


<s> const Twine bb_ir_label = <STR_LIT> + MBB -> getParent ( ) -> getFunction ( ) -> getName ( ) + <STR_LIT> + bbname + <STR_LIT> + Twine ( MBB -> getNumber ( ) ) ; bb_ir_label . toVector ( result ) ;


<s> case <STR_LIT> : case <STR_LIT> : return LowerXALUO ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ;


<s> if ( samplerInstr -> getOperand ( <NUM_LIT> ) . isCImm ( ) ) { auto sampMask = getIConstVal ( OrigArgs [ <NUM_LIT> ] , MRI ) ; Register res ; sampler = buildSamplerLiteral ( sampMask , res , GR -> get<ISA_LIT>TypeForVReg ( sampler ) , MIRBuilder , GR ) ; } } Register reg ; Register sampledImage = buildOpSampledImage ( reg , image , sampler , MIRBuilder , GR ) ; Register coord = OrigArgs [ <NUM_LIT> ] ; Register lod = GR -> buildConstantFP ( APFloat :: getZero ( APFloat :: IEEEsingle ( ) ) , MIRBuilder ) ; <ISA_LIT>Type * tmpType = retType ; bool NeedExtract = false ;

if ( tmpType -> getOpcode ( ) != <STR_LIT> ) {


<s> assert ( <NUM_LIT> ) ; } else if ( Modifier && strcmp ( Modifier , <STR_LIT> ) == <NUM_LIT> ) { assert ( <NUM_LIT> ) ; } else { O << getRegisterName ( Reg ) ; } } else if ( Op . isImm ( ) ) { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; O << '#' << Op . getImm ( ) ;


<s> CallingConv :: ID CC = CS . getCallingConv ( ) ; if ( CC == CallingConv :: Fast || CC == CallingConv :: GHC ) return <NUM_LIT> ;

if ( ! CS . paramHasAttr ( <NUM_LIT> , Attribute :: StructRet ) ) return <NUM_LIT> ;


<s> bool <ISA_LIT>PromoteAlloca :: doInitialization ( Module & M ) { if ( ! TM ) return false ; Mod = & M ; DL = & Mod -> getDataLayout ( ) ; MDBuilder MDB ( Mod -> getContext ( ) ) ; MaxWorkGroupSizeRange = MDB . createRange ( APInt ( <NUM_LIT> , <NUM_LIT> ) , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; const Triple & TT = TM -> getTargetTriple ( ) ; IsAMDGCN = TT . getArch ( ) == Triple :: amdgcn ; IsAMDHSA = TT . getOS ( ) == Triple :: AMDHSA ;


<s> static Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) { if ( ! RM . hasValue ( ) ) return Reloc :: Static ;


<s> return isMemOffs ( ) && Mem . ModeSize == <NUM_LIT> && ( ! Mem . Size || Mem . Size == <NUM_LIT> ) ;


<s> if ( align < <NUM_LIT> ) align = <NUM_LIT> ; } } if ( how != align_abi ) { if ( TREE_CODE ( type ) == ARRAY_TYPE && TYPE_MODE ( TREE_TYPE ( type ) ) == QImode ) { if ( align < BITS_PER_WORD ) align = BITS_PER_WORD ; }


<s> return DAG . getConstant ( getV4<ISA_LIT>ShuffleImm ( Mask ) , DL , <STR_LIT> ) ;


<s> default : return UNSUPPORTED ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; }


<s> state_reset ( curr_state ) ; targetm . sched . init ( <NUM_LIT> , false , <NUM_LIT> ) ;


<s> bool <ISA_LIT>InstrInfo :: isZeroImm ( const MachineOperand & op ) const {

return op . isImm ( ) && op . getImm ( ) == <NUM_LIT> ;


<s> if ( isa < FPExtInst > ( Ext ) ) return false ; if ( Ext -> getType ( ) -> isVectorTy ( ) ) return false ; for ( const Use & U : Ext -> uses ( ) ) { const Instruction * Instr = cast < Instruction > ( U . getUser ( ) ) ; switch ( Instr -> getOpcode ( ) ) { case Instruction :: Shl : if ( ! isa < ConstantInt > ( Instr -> getOperand ( <NUM_LIT> ) ) ) return false ; break ; case Instruction :: GetElementPtr : { gep_type_iterator GTI = gep_type_begin ( Instr ) ; auto & DL = Ext -> getModule ( ) -> getDataLayout ( ) ; std :: advance ( GTI , U . getOperandNo ( ) - <NUM_LIT> ) ; Type * IdxTy = GTI . getIndexedType ( ) ; uint64_t ShiftAmt = countTrailingZeros ( DL . getTypeStoreSizeInBits ( IdxTy ) . getFixedSize ( ) ) - <NUM_LIT> ; if ( ShiftAmt == <NUM_LIT> || ShiftAmt > <NUM_LIT> ) return false ; break ; } case Instruction :: Trunc : if ( Instr -> getType ( ) == Ext -> getOperand ( <NUM_LIT> ) -> getType ( ) ) continue ; LLVM_FALLTHROUGH ; default : return false ; }


<s> high = expand_simple_binop ( SImode , PLUS , end_addr , GEN_INT ( <NUM_LIT> ) , NULL , false , OPTAB_WIDEN ) ; high = expand_simple_binop ( SImode , LSHIFTRT , high , GEN_INT ( <NUM_LIT> ) , NULL , false , OPTAB_WIDEN ) ; low = convert_to_mode ( SImode , gen_lowpart ( HImode , end_addr ) , true ) ; opcode = OP ( MIPS_LUI ( AT_REGNUM , <NUM_LIT> ) ) ; trampoline [ i ++ ] = expand_simple_binop ( SImode , IOR , opcode , high , NULL , false , OPTAB_WIDEN ) ; opcode = OP ( MIPS_LOAD_PTR ( PIC_FUNCTION_ADDR_REGNUM , target_function_offset - end_addr_offset , AT_REGNUM ) ) ; trampoline [ i ++ ] = expand_simple_binop ( SImode , IOR , opcode , low , NULL , false , OPTAB_WIDEN ) ; if ( ! ISA_HAS_LOAD_DELAY ) trampoline [ i ++ ] = OP ( MIPS_JR ( PIC_FUNCTION_ADDR_REGNUM ) ) ; opcode = OP ( MIPS_LOAD_PTR ( STATIC_CHAIN_REGNUM , static_chain_offset - end_addr_offset , AT_REGNUM ) ) ; trampoline [ i ++ ] = expand_simple_binop ( SImode , IOR , opcode , low , NULL , false , OPTAB_WIDEN ) ; if ( ISA_HAS_LOAD_DELAY ) { trampoline [ i ++ ] = OP ( MIPS_JR ( PIC_FUNCTION_ADDR_REGNUM ) ) ; trampoline [ i ++ ] = OP ( MIPS_NOP ) ; } } if ( TARGET_CB_ALWAYS ) { rtx temp ; temp = trampoline [ i - <NUM_LIT> ] ; trampoline [ i - <NUM_LIT> ] = trampoline [ i - <NUM_LIT> ] ; trampoline [ i - <NUM_LIT> ] = temp ; } for ( j = <NUM_LIT> ; j < i ; j ++ ) { mem = adjust_address ( m_tramp , SImode , j * GET_MODE_SIZE ( SImode ) ) ; mips_emit_move ( mem , trampoline [ j ] ) ;


<s> perm1 += <NUM_LIT> ; std :: swap ( op0 , op1 ) ; } else if ( ( perm1 & <NUM_LIT> ) == <NUM_LIT> ) return false ; if ( target != NULL ) { machine_mode vmode , dmode ; rtvec v ; vmode = GET_MODE ( target ) ; gcc_assert ( GET_MODE_NUNITS ( vmode ) == <NUM_LIT> ) ; dmode = mode_for_vector ( GET_MODE_INNER ( vmode ) , <NUM_LIT> ) ; x = gen_rtx_VEC_CONCAT ( dmode , op0 , op1 ) ; v = gen_rtvec ( <NUM_LIT> , GEN_INT ( perm0 ) , GEN_INT ( perm1 ) ) ; x = gen_rtx_VEC_SELECT ( vmode , x , gen_rtx_PARALLEL ( VOIDmode , v ) ) ; emit_insn ( gen_rtx_SET ( VOIDmode , target , x ) ) ; }


<s> if ( DAG . ComputeNumSignBits ( In ) < InVT . getScalarSizeInBits ( ) ) { MVT ExtVT = <STR_LIT> ( <STR_LIT> , InVT . getSizeInBits ( ) / <NUM_LIT> ) ; In = DAG . getNode ( <STR_LIT> , DL , ExtVT , DAG . getBitcast ( ExtVT , In ) , DAG . getConstant ( ShiftInx , DL , ExtVT ) ) ; In = DAG . getBitcast ( InVT , In ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , DL , InVT ) , In , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; } assert ( ( InVT . is256BitVector ( ) || InVT . is128BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = InVT . getVectorNumElements ( ) ; assert ( ( NumElts == <NUM_LIT> || NumElts == <NUM_LIT> ) && <STR_LIT> ) ; if ( NumElts == <NUM_LIT> && ! Subtarget . canExtendTo512DQ ( ) ) { if ( InVT == <STR_LIT> ) { InVT = <STR_LIT> ; In = DAG . getNode ( <STR_LIT> , DL , InVT , In ) ; } SDValue Lo = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; SDValue Hi = extract128BitVector ( In , <NUM_LIT> , DAG , DL ) ; Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Lo , Hi ) ; } MVT EltVT = Subtarget . hasVLX ( ) ? <STR_LIT> : <STR_LIT> ( <NUM_LIT> / NumElts ) ; MVT ExtVT = <STR_LIT> ( EltVT , NumElts ) ;

In = DAG . getNode ( <STR_LIT> , DL , ExtVT , In ) ;


<s> bool HasFP = TFI -> hasFP ( MF ) ; uint64_t Offset = HasFP ? <NUM_LIT> : <NUM_LIT> ; Offset = Pred -> layoutRegion ( MF , Offset , <NUM_LIT> ) ; if ( HasFP && ( Pred -> getRegionSize ( ) > <NUM_LIT> ) ) {

Pred -> setRegionSize ( Pred -> getRegionSize ( ) + <NUM_LIT> ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned VirtualRegister ; if ( ! MRI . isLiveIn ( Reg ) ) { VirtualRegister = MRI . createVirtualRegister ( RC ) ; MRI . addLiveIn ( Reg , VirtualRegister ) ; } else {

VirtualRegister = MRI . getLiveInVirtReg ( Reg ) ;


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> Value * <ISA_LIT>IREmitter :: visitFOR ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Subtarget ( nullptr ) {


<s> MachineBasicBlock * TBB , * FBB ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; TII -> AnalyzeBranch ( * MBB , TBB , FBB , Cond , false ) ; MachineBasicBlock * NewBB = splitBlockBeforeInstr ( MI ) ; int delta = TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; MBB -> replaceSuccessor ( FBB , NewBB ) ; NewBB -> addSuccessor ( FBB ) ; } MachineBasicBlock * NextBB = & * std :: next ( MachineFunction :: iterator ( MBB ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DestBB -> getNumber ( ) << <STR_LIT> << NextBB -> getNumber ( ) << <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , DebugLoc ( ) , TII -> get ( getOppositeConditionOpcode ( MI -> getOpcode ( ) ) ) ) . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( MI -> getOpcode ( ) == <STR_LIT> ) invertBccCondition ( MIB ) ; MIB . addMBB ( NextBB ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( DestBB ) ; BlockInfo [ MBB -> getNumber ( ) ] . Size += TII -> GetInstSizeInBytes ( & MBB -> back ( ) ) ; BlockInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> GetInstSizeInBytes ( MI ) ; MI -> eraseFromParent ( ) ; adjustBlockOffsets ( * MBB ) ; return true ;


<s> void <ISA_LIT>InstPrinter :: printThumbS4ImmOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << markup ( <STR_LIT> ) << <STR_LIT> << formatImm ( MI -> getOperand ( OpNum ) . getImm ( ) * <NUM_LIT> ) << markup ( <STR_LIT> ) ;


<s> for ( res_set_t :: const_iterator I = set . begin ( ) , E = set . end ( ) ; I != E ; ++ I ) if ( ( * I & <NUM_LIT> ) == side ) return * I ;


<s> unsigned constant_generates_xxspltiw ( vec_const_128bit_type * vsx_const ) { if ( ! TARGET_SPLAT_WORD_CONSTANT || ! TARGET_PREFIXED || ! TARGET_VSX ) return <NUM_LIT> ; if ( ! vsx_const -> all_words_same ) return <NUM_LIT> ; if ( vsx_const -> all_bytes_same ) return <NUM_LIT> ; if ( vsx_const -> all_half_words_same ) { short sign_h_word = vsx_const -> half_words [ <NUM_LIT> ] ;

if ( EASY_VECTOR_15 ( sign_h_word ) ) return <NUM_LIT> ;


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , const Triple & TT ) : <ISA_LIT>AsmBackend ( T , TT ) {


<s> static DecodeStatus DecodeFP32BitRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const MCDisassembler * Decoder ) {

return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , <NUM_LIT> ) ;


<s> if ( forceFixedWidth ) return false ;


<s> auto_vec < rtx_insn * > control_flow_insns ; df_set_flags ( DF_DEFER_INSN_RESCAN ) ; FOR_EACH_BB_FN ( bb , cfun ) { FOR_BB_INSNS ( bb , insn ) { if ( ! NONDEBUG_INSN_P ( insn ) ) continue ; if ( TARGET_AVX512F ) replace_constant_pool_with_broadcast ( insn ) ; set = single_set ( insn ) ; if ( ! set ) continue ; if ( get_attr_avx_partial_xmm_update ( insn ) != AVX_PARTIAL_XMM_UPDATE_TRUE ) continue ; if ( ! v4sf_const0 ) v4sf_const0 = gen_reg_rtx ( V4SFmode ) ; rtx src = SET_SRC ( set ) ; rtx dest = SET_DEST ( set ) ; machine_mode dest_mode = GET_MODE ( dest ) ; rtx zero ; machine_mode dest_vecmode ; if ( dest_mode == E_SFmode ) { dest_vecmode = V4SFmode ; zero = v4sf_const0 ; } else { dest_vecmode = V2DFmode ; zero = gen_rtx_SUBREG ( V2DFmode , v4sf_const0 , <NUM_LIT> ) ; } src = gen_rtx_VEC_DUPLICATE ( dest_vecmode , src ) ; src = gen_rtx_VEC_MERGE ( dest_vecmode , src , zero , GEN_INT ( HOST_WIDE_INT_1U ) ) ; rtx vec = gen_reg_rtx ( dest_vecmode ) ; set = gen_rtx_SET ( vec , src ) ; set_insn = emit_insn_before ( set , insn ) ; df_insn_rescan ( set_insn ) ; if ( cfun -> can_throw_non_call_exceptions ) { rtx note = find_reg_note ( insn , REG_EH_REGION , NULL_RTX ) ; if ( note ) { control_flow_insns . safe_push ( set_insn ) ; add_reg_note ( set_insn , REG_EH_REGION , XEXP ( note , <NUM_LIT> ) ) ; } } src = gen_rtx_SUBREG ( dest_mode , vec , <NUM_LIT> ) ; set = gen_rtx_SET ( dest , src ) ; PATTERN ( insn ) = set ; INSN_CODE ( insn ) = - <NUM_LIT> ; recog_memoized ( insn ) ; df_insn_rescan ( insn ) ; bitmap_set_bit ( convert_bbs , bb -> index ) ; } } if ( v4sf_const0 ) { calculate_dominance_info ( CDI_DOMINATORS ) ; loop_optimizer_init ( AVOID_CFG_MODIFICATIONS ) ; bb = nearest_common_dominator_for_set ( CDI_DOMINATORS , convert_bbs ) ; while ( bb -> loop_father -> latch != EXIT_BLOCK_PTR_FOR_FN ( cfun ) ) bb = get_immediate_dominator ( CDI_DOMINATORS , bb -> loop_father -> header ) ; set = gen_rtx_SET ( v4sf_const0 , CONST0_RTX ( V4SFmode ) ) ; insn = BB_HEAD ( bb ) ; while ( insn && ! NONDEBUG_INSN_P ( insn ) ) { if ( insn == BB_END ( bb ) ) { insn = NULL ; break ; } insn = NEXT_INSN ( insn ) ; } if ( insn == BB_HEAD ( bb ) ) set_insn = emit_insn_before ( set , insn ) ; else set_insn = emit_insn_after ( set , insn ? PREV_INSN ( insn ) : BB_END ( bb ) ) ; df_insn_rescan ( set_insn ) ; loop_optimizer_finalize ( ) ; if ( ! control_flow_insns . is_empty ( ) ) { free_dominance_info ( CDI_DOMINATORS ) ; unsigned int i ; FOR_EACH_VEC_ELT ( control_flow_insns , i , insn ) if ( control_flow_insn_p ( insn ) ) { bb = BLOCK_FOR_INSN ( insn ) ;


<s> getBranchTarget ( const MachineInstr * MI ) const { assert ( MI -> isBranch ( ) && ! MI -> isIndirectBranch ( ) && <STR_LIT> ) ;

return MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ;


return GISel -> getMachineLegalizer ( ) ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _tzcnt_u64 ( unsigned long long __X ) {


<s> unsigned postOffset ( Align Alignment = Align :: None ( ) ) const { unsigned PO = Offset + Size ;

const Align PA = std :: max ( PostAlign , Alignment ) ;


<s> rtx aarch64_ptrue_reg ( machine_mode mode ) { gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL ) ; rtx reg = force_reg ( VNx16BImode , CONSTM1_RTX ( VNx16BImode ) ) ; return gen_lowpart ( mode , reg ) ;


<s> for ( unsigned i = <NUM_LIT> , e = MRI -> getNumVirtRegs ( ) ; i != e ; ++ i ) { unsigned Reg = TargetRegisterInfo :: index2VirtReg ( i ) ; if ( LIS -> hasInterval ( Reg ) ) { if ( LIS -> isLiveInToMBB ( LIS -> getInterval ( Reg ) , & MBB ) ) { vregs . insert ( Reg ) ; } } }


<s> if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> if ( def_p ) cpp_define ( pfile , name ) ;


<s> if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> <ISA_LIT>Peephole ( ) : MachineFunctionPass ( ID ) {


<s> rtx op1 = operands [ <NUM_LIT> ] ; if ( TARGET_A24 ) return true ; fprintf ( stderr , <STR_LIT> , mode_name [ mode ] ) ; debug_rtx ( op0 ) ; debug_rtx ( op1 ) ;

if ( GET_CODE ( op0 ) == SUBREG ) op0 = XEXP ( op0 , <NUM_LIT> ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CC_Save_SaveList ;


<s> EVT SrcVT = TLI . getValueType ( Src -> getType ( ) , true ) ; EVT DestVT = TLI . getValueType ( I -> getType ( ) , true ) ; if ( SrcVT != <STR_LIT> || DestVT != <STR_LIT> ) return false ;

unsigned SrcReg = getRegForValue ( Src ) ;


<s> bool moveAllToNextBlock = false ; for ( MachineBasicBlock :: iterator I = MBB -> begin ( ) , E = MBB -> end ( ) ; I != E ; ++ I ) { if ( I == MBB -> begin ( ) && ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) ) { continue ; } if ( std :: next ( I ) == E || ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) { if ( ! ( I -> isBranch ( ) ) && ! ( I -> isCall ( ) ) && ! ( I -> isReturn ( ) ) && ! ( I -> isCompare ( ) ) && ! ( I -> getOpcode ( ) == <STR_LIT> ) && ! ( I -> getOpcode ( ) > <NUM_LIT> && I -> getOpcode ( ) < <NUM_LIT> ) ) interleavingQueue . push ( I ) ; while ( interleavingQueue . size ( ) != <NUM_LIT> ) { MachineBasicBlock :: iterator interleavedI = interleavingQueue . front ( ) ; MachineInstr * slaveinst = MF . CloneMachineInstr ( & * interleavedI ) ; slaveinst -> setFlags ( <NUM_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < interleavedI -> getNumOperands ( ) ; opcount ++ ) { if ( interleavedI -> getOperand ( opcount ) . isReg ( ) ) { slaveinst -> getOperand ( opcount ) . setReg ( getSlaveReg ( interleavedI -> getOperand ( opcount ) . getReg ( ) ) ) ; } else if ( interleavedI -> getOperand ( opcount ) . isImm ( ) && ( interleavedI -> mayStore ( ) || interleavedI -> mayLoad ( ) ) ) { slaveinst -> getOperand ( opcount ) . setImm ( interleavedI -> getOperand ( opcount ) . getImm ( ) - MEMZDC_OFFSET ) ; } } MBB -> insert ( I , slaveinst ) ; interleavingQueue . pop ( ) ; } } else if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { while ( interleavingQueue . size ( ) != <NUM_LIT> ) { MachineBasicBlock :: iterator interleavedI = interleavingQueue . front ( ) ; MachineInstr * slaveinst = MF . CloneMachineInstr ( & * interleavedI ) ; slaveinst -> setFlags ( <NUM_LIT> ) ; for ( unsigned int opcount = <NUM_LIT> ; opcount < interleavedI -> getNumOperands ( ) ; opcount ++ ) { if ( interleavedI -> getOperand ( opcount ) . isReg ( ) ) {


<s> bool <ISA_LIT>CodeGenPrepare :: isSupportedValue ( Value * V ) { if ( auto * I = dyn_cast < ICmpInst > ( V ) ) { if ( isa < PointerType > ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ) return true ; return EqualTypeSize ( I -> getOperand ( <NUM_LIT> ) ) ; } if ( isa < StoreInst > ( V ) || isa < GetElementPtrInst > ( V ) ) return true ; if ( isa < BranchInst > ( V ) || isa < SwitchInst > ( V ) || isa < BasicBlock > ( V ) ) return true ; if ( ( isa < Constant > ( V ) && ! isa < ConstantExpr > ( V ) ) || isa < Argument > ( V ) ) return isSupportedType ( V ) ; if ( isa < PHINode > ( V ) || isa < SelectInst > ( V ) || isa < ReturnInst > ( V ) || isa < LoadInst > ( V ) ) return isSupportedType ( V ) ; if ( isa < SExtInst > ( V ) ) return false ; if ( auto * Cast = dyn_cast < CastInst > ( V ) ) return isSupportedType ( Cast ) || isSupportedType ( Cast -> getOperand ( <NUM_LIT> ) ) ; if ( auto * Call = dyn_cast < CallInst > ( V ) ) return isSupportedType ( Call ) && Call -> hasRetAttr ( Attribute :: AttrKind :: ZExt ) ; if ( ! isa < BinaryOperator > ( V ) ) return false ; if ( ! isSupportedType ( V ) ) return false ; if ( generateSignBits ( V ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; }


<s> bool is<ISA_LIT>SrcOperand ( const MCInstrDesc & Desc , unsigned OpNo ) { unsigned OpType = Desc . OpInfo [ OpNo ] . OperandType ;

return OpType >= <STR_LIT> && OpType <= <STR_LIT> ;


<s> rtx label1 , label2 , x , mask , shift ; machine_mode mode , orig_mode ; enum memmodel mod_s , mod_f ; bool is_weak ; boolval = operands [ <NUM_LIT> ] ; retval = operands [ <NUM_LIT> ] ; mem = operands [ <NUM_LIT> ] ; oldval = operands [ <NUM_LIT> ] ; newval = operands [ <NUM_LIT> ] ; is_weak = ( INTVAL ( operands [ <NUM_LIT> ] ) != <NUM_LIT> ) ; mod_s = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; mod_f = ( enum memmodel ) INTVAL ( operands [ <NUM_LIT> ] ) ; orig_mode = mode = GET_MODE ( mem ) ; mask = shift = NULL_RTX ; if ( mode == QImode || mode == HImode ) { oldval = convert_modes ( SImode , mode , oldval , <NUM_LIT> ) ; if ( ! TARGET_SYNC_HI_QI ) { mem = rs6000_adjust_atomic_subword ( mem , & shift , & mask ) ; oldval = expand_simple_binop ( SImode , ASHIFT , oldval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; newval = convert_modes ( SImode , mode , newval , <NUM_LIT> ) ; newval = expand_simple_binop ( SImode , ASHIFT , newval , shift , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } retval = gen_reg_rtx ( SImode ) ; mode = SImode ; } else if ( reg_overlap_mentioned_p ( retval , oldval ) ) oldval = copy_to_reg ( oldval ) ; mem = rs6000_pre_atomic_barrier ( mem , mod_s ) ; label1 = NULL_RTX ; if ( ! is_weak ) { label1 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_label ( XEXP ( label1 , <NUM_LIT> ) ) ; } label2 = gen_rtx_LABEL_REF ( VOIDmode , gen_label_rtx ( ) ) ; emit_load_locked ( mode , retval , mem ) ; x = retval ; if ( mask ) { x = expand_simple_binop ( SImode , AND , retval , mask , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } cond = gen_reg_rtx ( CCmode ) ; if ( mode != TImode ) x = gen_rtx_COMPARE ( CCmode , x , oldval ) ; else { rtx xor1_result = gen_reg_rtx ( DImode ) ; rtx xor2_result = gen_reg_rtx ( DImode ) ; rtx or_result = gen_reg_rtx ( DImode ) ; rtx new_word0 = simplify_gen_subreg ( DImode , x , TImode , <NUM_LIT> ) ; rtx new_word1 = simplify_gen_subreg ( DImode , x , TImode , <NUM_LIT> ) ; rtx old_word0 = simplify_gen_subreg ( DImode , oldval , TImode , <NUM_LIT> ) ; rtx old_word1 = simplify_gen_subreg ( DImode , oldval , TImode , <NUM_LIT> ) ; emit_insn ( gen_xordi3 ( xor1_result , new_word0 , old_word0 ) ) ; emit_insn ( gen_xordi3 ( xor2_result , new_word1 , old_word1 ) ) ;


<s> OperandMatchResultTy parseBDAddr64 ( OperandVector & Operands ) { return parseAddress ( Operands , BDMem , <STR_LIT> , GR64Reg ) ;


<s> F = Function :: Create ( FunctionType :: get ( Type :: getVoidTy ( C ) , false ) , Function :: ExternalLinkage , Name , M ) ; assert ( F && <STR_LIT> ) ; F -> setLinkage ( GlobalValue :: LinkOnceODRLinkage ) ; F -> setUnnamedAddr ( GlobalValue :: UnnamedAddr :: Global ) ; F -> addFnAttr ( Attribute :: OptimizeNone ) ; F -> addFnAttr ( Attribute :: NoInline ) ; F -> addFnAttr ( Attribute :: MinSize ) ;


SSThreshold = mdconst :: extract < ConstantInt > ( MFE . Val ) -> getZExtValue ( ) ;


<s> CCInfo . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState RetCCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; RetCCInfo . AllocateStack ( CCInfo . getNextStackOffset ( ) , <NUM_LIT> ) ; RetCCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; unsigned NumBytes = RetCCInfo . getNextStackOffset ( ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , getPointerTy ( ) , true ) , dl ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createImm ( const MCExpr * Val , SMLoc S , SMLoc E ) {

auto Op = make_unique < <ISA_LIT>Operand > ( k_Immediate ) ;


<s> int fp_high_losum_p ( rtx op ) { if ( GET_CODE ( op ) == CONST_DOUBLE ) { long i ; REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( op ) , i ) ; return ! SPARC_SIMM13_P ( i ) && ! SPARC_SETHI_P ( i ) ;


<s> assert ( Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , dl , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , RevShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , dl , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , ShAmt ) ;

SDValue Tmp3 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ExtraShAmt ) ;


<s> if ( DstVT != <STR_LIT> ) return SDValue ( ) ; SDValue InVec = Op -> getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; unsigned NumElts = SrcVT . getVectorNumElements ( ) ; EVT SVT = SrcVT . getVectorElementType ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , SVT , InVec , DAG . getIntPtrConstant ( i ) ) ) ; SDValue Undef = DAG . getUNDEF ( SVT ) ; for ( unsigned i = NumElts , e = NumElts * <NUM_LIT> ; i != e ; ++ i ) Elts . push_back ( Undef ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumElts * <NUM_LIT> ) ; SDValue BV = DAG . getNode ( <STR_LIT> , dl , NewVT , Elts ) ; SDValue ToV2F64 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BV ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ToV2F64 , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } assert ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) && Subtarget -> hasMMX ( ) && <STR_LIT> ) ;

assert ( ( DstVT == <STR_LIT> || ( DstVT . isVector ( ) && DstVT . getSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ;


<s> if ( TM . getTargetTriple ( ) . isOSBinFormatELF ( ) ) emitAttributes ( ) ;


<s> if ( TT . isOSBinFormatMachO ( ) ) { if ( TT . getArch ( ) == Triple :: x86_64 ) return llvm :: make_unique < <ISA_LIT>_64MachoTargetObjectFile > ( ) ; return llvm :: make_unique < TargetLoweringObjectFileMachO > ( ) ; } if ( TT . isOSBinFormatRepo ( ) ) return make_unique < TargetLoweringObjectFileRepo > ( ) ; if ( TT . isOSFreeBSD ( ) ) return llvm :: make_unique < <ISA_LIT>FreeBSDTargetObjectFile > ( ) ; if ( TT . isOSLinux ( ) || TT . isOSNaCl ( ) || TT . isOSIAMCU ( ) ) return llvm :: make_unique < <ISA_LIT>LinuxNaClTargetObjectFile > ( ) ;

if ( TT . isOSSolaris ( ) ) return llvm :: make_unique < <ISA_LIT>SolarisTargetObjectFile > ( ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC ) const { unsigned opc ; bool isValidFrameIdx = ( FrameIdx < <ISA_LIT>FrameInfo :: maxFrameOffset ( ) ) ; if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) { opc = ( isValidFrameIdx ? <STR_LIT> : <STR_LIT> ) ; } else if ( RC == <STR_LIT> ) {

opc = ( isValidFrameIdx ) ? <STR_LIT> : <STR_LIT> ;


<s> case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; assert ( VA . getValVT ( ) != <STR_LIT> && <STR_LIT> ) ; int index = ArgLocs [ i ] . getValNo ( ) ; if ( index != lastInsIndex ) { <STR_LIT> Flags = Ins [ index ] . Flags ; if ( Flags . isByVal ( ) ) { unsigned VARegSize , VARegSaveSize ; computeRegArea ( CCInfo , MF , VARegSize , VARegSaveSize ) ; VarArgStyleRegisters ( CCInfo , DAG , dl , Chain , <NUM_LIT> ) ; unsigned Bytes = Flags . getByValSize ( ) - VARegSize ; if ( Bytes == <NUM_LIT> ) Bytes = <NUM_LIT> ; int FI = MFI -> CreateFixedObject ( Bytes , VA . getLocMemOffset ( ) , false ) ; InVals . push_back ( DAG . getFrameIndex ( FI , getPointerTy ( ) ) ) ; } else { int FI = MFI -> CreateFixedObject ( VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ;

SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Info . SwiftErrorVReg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! mayTailCallThisCC ( CalleeCC ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( Info . IsVarArg ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( any_of ( CallerF . args ( ) , [ ] ( const Argument & A ) {

return A . hasByValAttr ( ) || A . hasInRegAttr ( ) ;


<s> type = TYPE_MOFFS16 ; break ; case <NUM_LIT> : type = TYPE_MOFFS32 ; break ; case <NUM_LIT> : type = TYPE_MOFFS64 ; break ; } } else if ( type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || type == TYPE_IMM64 ) { uint32_t Opcode = mcInst . getOpcode ( ) ; switch ( operand . encoding ) { default : break ; case ENCODING_IB : if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) type = TYPE_MOFFS8 ; break ; case ENCODING_IW : type = TYPE_MOFFS16 ; break ; case ENCODING_ID :


<s> void addImmOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> RS6000_OUTPUT_BASENAME ( stream , name ) ;


<s> const <ISA_LIT>_64GOT & <ISA_LIT>_64GNULDBackend :: getGOT ( ) const { assert ( m_pGOT != NULL ) ;


<s> if ( regno == CC_REGNUM && GET_MODE_CLASS ( mode ) != MODE_CC ) return false ; if ( IS_VPR_REGNUM ( regno ) ) return mode == HImode || mode == V16BImode || mode == V8BImode || mode == V4BImode ; if ( TARGET_THUMB1 ) return ( ARM_NUM_REGS ( mode ) < <NUM_LIT> ) || ( regno < LAST_LO_REGNUM ) ; if ( TARGET_VFP_BASE && IS_VFP_REGNUM ( regno ) ) { if ( mode == DFmode || mode == DImode ) return VFP_REGNO_OK_FOR_DOUBLE ( regno ) ; if ( mode == HFmode || mode == BFmode || mode == HImode || mode == SFmode || mode == SImode ) return VFP_REGNO_OK_FOR_SINGLE ( regno ) ; if ( TARGET_NEON ) return ( VALID_NEON_DREG_MODE ( mode ) && VFP_REGNO_OK_FOR_DOUBLE ( regno ) ) || ( VALID_NEON_QREG_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == TImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == EImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == CImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) ; if ( TARGET_HAVE_MVE ) return ( ( VALID_MVE_MODE ( mode ) && NEON_REGNO_OK_FOR_QUAD ( regno ) ) || ( mode == OImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) || ( mode == XImode && NEON_REGNO_OK_FOR_NREGS ( regno , <NUM_LIT> ) ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> MachineMemOperand * MMOa = * MIa . memoperands_begin ( ) ; MachineMemOperand * MMOb = * MIb . memoperands_begin ( ) ; const Value * VALa = MMOa -> getValue ( ) ; const Value * VALb = MMOb -> getValue ( ) ; bool SameVal = ( VALa && VALb && ( VALa == VALb ) ) ; if ( ! SameVal ) { const PseudoSourceValue * PSVa = MMOa -> getPseudoValue ( ) ; const PseudoSourceValue * PSVb = MMOb -> getPseudoValue ( ) ; if ( PSVa && PSVb && ( PSVa == PSVb ) ) SameVal = true ; } if ( SameVal ) { int OffsetA = MMOa -> getOffset ( ) , OffsetB = MMOb -> getOffset ( ) ;

int WidthA = MMOa -> getSize ( ) , WidthB = MMOb -> getSize ( ) ;


<s> break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionAlignment = <NUM_LIT> ; PrefLoopAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 :


<s> diff = d -> perm [ <NUM_LIT> ] ; switch ( diff ) { case <NUM_LIT> : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev64v16qi ; break ; case V8QImode : gen = gen_neon_vrev64v8qi ; break ; default : return false ; } break ; case <NUM_LIT> : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev32v16qi ; break ; case V8QImode : gen = gen_neon_vrev32v8qi ; break ; case V8HImode : gen = gen_neon_vrev64v8hi ; break ; case V4HImode : gen = gen_neon_vrev64v4hi ; break ; case V8HFmode : gen = gen_neon_vrev64v8hf ; break ; case V4HFmode : gen = gen_neon_vrev64v4hf ; break ; default : return false ; } break ; case <NUM_LIT> : switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vrev16v16qi ; break ; case V8QImode : gen = gen_neon_vrev16v8qi ; break ; case V8HImode : gen = gen_neon_vrev32v8hi ; break ; case V4HImode : gen = gen_neon_vrev32v4hi ; break ; case V4SImode : gen = gen_neon_vrev64v4si ; break ; case V2SImode : gen = gen_neon_vrev64v2si ; break ;

case V4SFmode : gen = gen_neon_vrev64v4sf ; break ;


<s> TargetRegistry :: RegisterELFStreamer ( * T , create<ISA_LIT>ELFStreamer ) ; TargetRegistry :: RegisterXCOFFStreamer ( * T , create<ISA_LIT>XCOFFStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( * T , createObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( * T , createAsmTargetStreamer ) ; TargetRegistry :: RegisterMCInstPrinter ( * T , create<ISA_LIT>MCInstPrinter ) ;


<s> printInlineJT ( MI , opNum , <STR_LIT> ) ;


<s> return __builtin_aarch64_lceilhfdi ( __a ) ;


<s> return __builtin_tbegin_nofloat ( tdb ) ;


<s> bool SelectAddrIdx ( SDValue N , SDValue & Base , SDValue & Index ) { return <ISA_LIT>Lowering . SelectAddressRegReg ( N , Base , Index , * CurDAG ) ;


<s> SDValue N10 = N1 . getOperand ( <NUM_LIT> ) ; EVT N00Type = N00 . getValueType ( ) ; EVT N10Type = N10 . getValueType ( ) ; if ( N00Type != N10Type || ! ( ( Subtarget . hasSSE1 ( ) && N00Type == <STR_LIT> ) || ( Subtarget . hasSSE2 ( ) && N00Type == <STR_LIT> ) ) ) return SDValue ( ) ; unsigned FPOpcode = convertIntLogicToFPLogicOpcode ( N -> getOpcode ( ) ) ;

SDValue FPLogic = DAG . getNode ( FPOpcode , DL , N00Type , N00 , N10 ) ;


<s> if ( STI . hasV5TOps ( ) ) return <STR_LIT> ; if ( STI . hasV4TOps ( ) ) return <STR_LIT> ;


<s> case <STR_LIT> : return LowerUDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerSDIVREM ( Op , DAG ) ; case <STR_LIT> : return LowerFREM ( Op , DAG ) ; case <STR_LIT> : return LowerFCEIL ( Op , DAG ) ; case <STR_LIT> : return LowerFTRUNC ( Op , DAG ) ; case <STR_LIT> : return LowerFRINT ( Op , DAG ) ; case <STR_LIT> : return LowerFNEARBYINT ( Op , DAG ) ; case <STR_LIT> : return LowerFROUND ( Op , DAG ) ; case <STR_LIT> : return LowerFFLOOR ( Op , DAG ) ; case <STR_LIT> : return Lower<ISA_LIT>NT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerUINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFP_TO_FP16 ( Op , DAG ) ;

case <STR_LIT> : return LowerFP_TO_<ISA_LIT>NT ( Op , DAG ) ;


<s> return ( int16x8_t ) __builtin_neon_vqaddsv8hi ( __a , __b ) ;


<s> static unsigned CalculateStackSlotSize ( EVT ArgVT , <STR_LIT> Flags , unsigned PtrByteSize ) { unsigned ArgSize = ArgVT . getSizeInBits ( ) / <NUM_LIT> ; if ( Flags . isByVal ( ) ) ArgSize = Flags . getByValSize ( ) ; ArgSize = ( ( ArgSize + PtrByteSize - <NUM_LIT> ) / PtrByteSize ) * PtrByteSize ;


<s> if ( Model == TLSModel :: LocalExec ) { SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , HiVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , TPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; } else if ( Model == TLSModel :: InitialExec ) { TPOff = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPOff ) ; } else if ( Model == TLSModel :: LocalDynamic ) { <ISA_LIT>FunctionInfo * MFI = DAG . getMachineFunction ( ) . getInfo < <ISA_LIT>FunctionInfo > ( ) ; MFI -> incNumLocalDynamicTLSAccesses ( ) ; SDValue HiDesc = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> | <STR_LIT> ) ; SDValue LoDesc = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiDesc ) ; DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DescAddr , LoDesc ) ; SDValue SymAddr = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TPOff = LowerELFTLSDescCall ( SymAddr , DescAddr , DL , DAG ) ; SDValue HiVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoVar = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue DTPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , HiVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; DTPOff = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , PtrVT , DTPOff , LoVar , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) , <NUM_LIT> ) ; TPOff = DAG . getNode ( <STR_LIT> , DL , PtrVT , TPOff , DTPOff ) ; } else if ( Model == TLSModel :: GeneralDynamic ) { SDValue HiDesc = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> ) ; SDValue LoDesc = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , HiDesc ) ;


<s> const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; return DAG . getIntPtrConstant ( <NUM_LIT> * RegInfo -> getSlotSize ( ) , SDLoc ( Op ) ) ;


<s> if ( Fractional ) { Lmul = <NUM_LIT> - Lmul ; Lmul = <NUM_LIT> << Lmul ; O << <STR_LIT> << Lmul ; } else { Lmul = <NUM_LIT> << Lmul ; O << <STR_LIT> << Lmul ; } bool TailAgnostic = Imm & <NUM_LIT> ; bool MaskedoffAgnostic = Imm & <NUM_LIT> ; if ( TailAgnostic ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( MaskedoffAgnostic ) O << <STR_LIT> ;


<s> vst1_s8 ( int8_t * a , int8x8_t b ) { __builtin_aarch64_st1v8qi ( ( __builtin_aarch64_simd_qi * ) a , b ) ;


<s> if ( GET_MODE_SIZE ( inner_mode ) == GET_MODE_SIZE ( mode ) ) { if ( GET_MODE_SIZE ( inner_mode ) == <NUM_LIT> ) { emit_move_insn ( gen_lowpart ( SImode , target ) , gen_lowpart ( SImode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) ; return ; } else if ( GET_MODE_SIZE ( inner_mode ) == <NUM_LIT> ) { emit_move_insn ( gen_lowpart ( DImode , target ) , gen_lowpart ( DImode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) ; return ; } } else if ( GET_MODE_SIZE ( inner_mode ) == GET_MODE_SIZE ( word_mode ) && GET_MODE_SIZE ( mode ) == <NUM_LIT> * GET_MODE_SIZE ( word_mode ) ) { emit_move_insn ( gen_highpart ( word_mode , target ) , gen_lowpart ( word_mode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) ; emit_move_insn ( gen_lowpart ( word_mode , target ) , gen_lowpart ( word_mode , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) ; return ; }

if ( all_same && GET_MODE_SIZE ( mode ) == <NUM_LIT> ) {


<s> assert ( MIb && ( MIb -> mayLoad ( ) || MIb -> mayStore ( ) ) && <STR_LIT> ) ; if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) ) return false ; if ( MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( Opc0 ) ) { if ( isDS ( Opc1 ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( Opc1 ) ; } if ( isMUBUF ( Opc0 ) || isMTBUF ( Opc0 ) ) { if ( isMUBUF ( Opc1 ) || isMTBUF ( Opc1 ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ;

return ! isFLAT ( Opc1 ) && ! isSMRD ( Opc1 ) ;