<s> ShuffleSourceInfo ( SDValue Vec ) : Vec ( Vec ) , MinElt ( UINT_MAX ) , MaxElt ( <NUM_LIT> ) , ShuffleVec ( Vec ) , WindowBase ( <NUM_LIT> ) , WindowScale ( <NUM_LIT> ) {


<s> int Indexes [ <NUM_LIT> ] ; for ( unsigned I = <NUM_LIT> ; I < NumElts ; ++ I ) { Constant * COp = V -> getAggregateElement ( I ) ; if ( ! COp || ( ! isa < UndefValue > ( COp ) && ! isa < ConstantInt > ( COp ) ) ) return nullptr ; if ( isa < UndefValue > ( COp ) ) { Indexes [ I ] = - <NUM_LIT> ; continue ; } APInt Index = cast < ConstantInt > ( COp ) -> getValue ( ) ; Index = Index . zextOrTrunc ( <NUM_LIT> ) . getLoBits ( <NUM_LIT> ) ; if ( IsPD ) Index . lshrInPlace ( <NUM_LIT> ) ; Index += APInt ( <NUM_LIT> , ( I / NumLaneElts ) * NumLaneElts ) ; Indexes [ I ] = Index . getZExtValue ( ) ; }

auto V1 = II . getArgOperand ( <NUM_LIT> ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Target & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI ) { if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI , STI ) ;


<s> { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } } ; if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ;

assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ;


<s> SUnit * SU = CurrentPacket [ i ] ; ( void ) SU ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << * ( SU -> getInstr ( ) ) ) ; }


<s> <STR_LIT> getCondCode ( ) const { assert ( Kind == k_CondCode && <STR_LIT> ) ; return CC . Val ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ;


<s> if ( Load -> isInvariant ( ) && Load -> isDereferenceable ( ) ) return true ; const Value * V1 = Load -> getMemOperand ( ) -> getValue ( ) ; const Value * V2 = Store -> getMemOperand ( ) -> getValue ( ) ; if ( ! V1 || ! V2 ) return false ; uint64_t Size = Load -> getMemoryVT ( ) . getStoreSize ( ) ; int64_t End1 = Load -> getSrcValueOffset ( ) + Size ; int64_t End2 = Store -> getSrcValueOffset ( ) + Size ;

if ( V1 == V2 && End1 == End2 ) return false ;


<s> explicit <ISA_LIT>AAResult ( const DataLayout & DL , Triple T ) : AAResultBase ( ) , DL ( DL ) {


<s> static SDValue createPSADBW ( SelectionDAG & DAG , const SDValue & Zext0 , const SDValue & Zext1 , const SDLoc & DL , const <ISA_LIT>Subtarget & Subtarget ) { EVT InVT = Zext0 . getOperand ( <NUM_LIT> ) . getValueType ( ) ; unsigned RegSize = std :: max ( <NUM_LIT> , ( unsigned ) InVT . getSizeInBits ( ) ) ; unsigned NumConcat = RegSize / InVT . getSizeInBits ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( NumConcat , DAG . getConstant ( <NUM_LIT> , DL , InVT ) ) ; Ops [ <NUM_LIT> ] = Zext0 . getOperand ( <NUM_LIT> ) ; MVT ExtendedVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue SadOp0 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ; Ops [ <NUM_LIT> ] = Zext1 . getOperand ( <NUM_LIT> ) ; SDValue SadOp1 = DAG . getNode ( <STR_LIT> , DL , ExtendedVT , Ops ) ;

auto PSADBWBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) {


<s> bool <ISA_LIT>TargetLowering :: shouldExpandAtomicLoadInIR ( LoadInst * LI ) const {

return LI -> getType ( ) -> getPrimitiveSizeInBits ( ) > <NUM_LIT> ;


<s> TargetRegistry :: RegisterMCDisassembler ( The<ISA_LIT>Target64 , create<ISA_LIT>Disassembler ) ;


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & _STI , MCAsmParser & _Parser , const MCInstrInfo & _MII , const MCTargetOptions & Options ) : MCTargetAsmParser ( ) , STI ( _STI ) , Parser ( _Parser ) , MII ( _MII ) { Triple TheTriple ( STI . getTargetTriple ( ) ) ; Is<ISA_LIT>64 = ( TheTriple . getArch ( ) == Triple :: ppc64 || TheTriple . getArch ( ) == Triple :: ppc64le ) ; IsDarwin = TheTriple . isMacOSX ( ) ;

setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> SDValue In = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ; EVT InVT = In . getValueType ( ) ; unsigned Opc = Op . getOpcode ( ) ; bool IsSigned = Opc == <STR_LIT> || Opc == <STR_LIT> ; if ( VT . isScalableVector ( ) ) { if ( InVT . getVectorElementType ( ) == <STR_LIT> ) { unsigned CastOpc = IsSigned ? <STR_LIT> : <STR_LIT> ; EVT CastVT = getPromotedVTForPredicate ( InVT ) ; In = DAG . getNode ( CastOpc , dl , CastVT , In ) ; return DAG . getNode ( Opc , dl , VT , In ) ; } unsigned Opcode = IsSigned ? <STR_LIT> : <STR_LIT> ; return LowerToPredicatedOp ( Op , DAG , Opcode ) ; } if ( useSVEForFixedLengthVectorVT ( VT ) || useSVEForFixedLengthVectorVT ( InVT ) ) return LowerFixedLengthIntToFPToSVE ( Op , DAG ) ; uint64_t VTSize = VT . getFixedSizeInBits ( ) ; uint64_t InVTSize = InVT . getFixedSizeInBits ( ) ; if ( VTSize < InVTSize ) {

MVT CastVT = <STR_LIT> ( <STR_LIT> ( InVT . getScalarSizeInBits ( ) ) , InVT . getVectorNumElements ( ) ) ;


<s> int intregs , intoffset ; machine_mode mode ; if ( cum -> floats_in_gpr == <NUM_LIT> && ( cum -> intoffset % <NUM_LIT> == <NUM_LIT> || ( cum -> intoffset == - <NUM_LIT> && final ) ) ) { cum -> words ++ ; cum -> floats_in_gpr = <NUM_LIT> ; } if ( cum -> intoffset == - <NUM_LIT> ) return ; intoffset = cum -> intoffset ; cum -> intoffset = - <NUM_LIT> ; cum -> floats_in_gpr = <NUM_LIT> ; if ( intoffset % BITS_PER_WORD != <NUM_LIT> ) { mode = mode_for_size ( BITS_PER_WORD - intoffset % BITS_PER_WORD , MODE_INT , <NUM_LIT> ) ;


<s> if ( crtl -> calls_eh_return ) { insn = emit_insn ( gen_addsi3 ( stack_pointer_rtx , stack_pointer_rtx , EH_RETURN_STACKADJ_RTX ) ) ; } if ( cr16_interrupt_function_p ( ) ) { insn = emit_jump_insn ( gen_interrupt_return ( ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else if ( crtl -> calls_eh_return ) { insn = emit_jump_insn ( gen_pop_and_popret_return ( GEN_INT ( current_frame_info . reg_size ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;


if ( ! isMemory ( ) || Memory . OffsetRegNum != <NUM_LIT> || Memory . Alignment != <NUM_LIT> ) return false ;


<s> assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned InsertPSMask ; if ( ! matchVectorShuffleAsInsertPS ( V1 , V2 , InsertPSMask , Zeroable , Mask , DAG ) ) return SDValue ( ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getConstant ( InsertPSMask , DL , <STR_LIT> ) ) ;


<s> SmallVector < Type * , <NUM_LIT> > ArgTys ; Value * Callee = II -> getCalledValue ( ) ; FunctionType * CalleeFTy ; if ( auto * F = dyn_cast < Function > ( Callee ) ) CalleeFTy = F -> getFunctionType ( ) ; else { auto * CalleeTy = dyn_cast < PointerType > ( Callee -> getType ( ) ) -> getElementType ( ) ; CalleeFTy = dyn_cast < FunctionType > ( CalleeTy ) ; } std :: string Sig = getSignature ( CalleeFTy ) ; if ( InvokeWrappers . find ( Sig ) != InvokeWrappers . end ( ) ) return InvokeWrappers [ Sig ] ; ArgTys . push_back ( PointerType :: getUnqual ( CalleeFTy ) ) ; ArgTys . append ( CalleeFTy -> param_begin ( ) , CalleeFTy -> param_end ( ) ) ; FunctionType * FTy = FunctionType :: get ( CalleeFTy -> getReturnType ( ) , ArgTys , CalleeFTy -> isVarArg ( ) ) ;

Function * F = Function :: Create ( FTy , GlobalValue :: ExternalLinkage , <STR_LIT> + Sig , & M ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler :: Success ;


<s> if ( Pattern == <STR_LIT> ) { LLVMContext & Ctx = II . getContext ( ) ; IRBuilder < > Builder ( Ctx ) ; Builder . SetInsertPoint ( & II ) ; Constant * StepVal = ConstantInt :: get ( II . getType ( ) , NumElts ) ; auto * VScale = Builder . CreateVScale ( StepVal ) ; VScale -> takeName ( & II ) ; return IC . replaceInstUsesWith ( II , VScale ) ; } unsigned MinNumElts = getNumElementsFromSVEPredPattern ( Pattern ) ;

return MinNumElts && NumElts >= MinNumElts ? Optional < Instruction * > ( IC . replaceInstUsesWith ( II , ConstantInt :: get ( II . getType ( ) , MinNumElts ) ) ) : None ;


<s> static inline HOST_WIDE_INT htm_spr_num ( enum rs6000_builtins code ) { if ( code == HTM_BUILTIN_GET_TFHAR || code == HTM_BUILTIN_SET_TFHAR ) return TFHAR_SPR ; else if ( code == HTM_BUILTIN_GET_TFIAR || code == HTM_BUILTIN_SET_TFIAR ) return TFIAR_SPR ; else if ( code == HTM_BUILTIN_GET_TEXASR || code == HTM_BUILTIN_SET_TEXASR ) return TEXASR_SPR ; gcc_assert ( code == HTM_BUILTIN_GET_TEXASRU || code == HTM_BUILTIN_SET_TEXASRU ) ; return TEXASRU_SPR ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( N1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( N0 , N1 ) ; if ( N0 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue N00 = N0 -> getOperand ( <NUM_LIT> ) ; SDValue N01 = N0 -> getOperand ( <NUM_LIT> ) ; N01 = peekThroughBitcasts ( N01 ) ; if ( ! <STR_LIT> ( N01 . getNode ( ) ) ) { if ( ! VT . is256BitVector ( ) || N01 -> getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue V1 = N01 -> getOperand ( <NUM_LIT> ) ; SDValue V2 = N01 -> getOperand ( <NUM_LIT> ) ; if ( V1 . getOpcode ( ) != <STR_LIT> || ! V1 . getOperand ( <NUM_LIT> ) . isUndef ( ) || ! <STR_LIT> ( V1 . getOperand ( <NUM_LIT> ) . getNode ( ) ) || ! <STR_LIT> ( V2 . getNode ( ) ) ) return SDValue ( ) ; } return DAG . getNode ( <STR_LIT> , DL , VT , N00 , N1 ) ;


<s> rtl_opt_pass * make_pass_align_insns ( gcc :: context * ctxt ) { return new pass_align_insns ( ctxt ) ;


<s> dwarf = gen_rtx_SET ( VOIDmode , dest , plus_constant ( Pmode , src , size ) ) ; add_reg_note ( insn , REG_CFA_ADJUST_CFA , dwarf ) ;


<s> if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return <STR_LIT> ;

return TargetLowering :: getRegisterTypeForCallingConv ( Context , VT ) ;


<s> vqtbx2q_u8 ( uint8x16_t r , uint8x16x2_t tab , uint8x16_t idx ) { __builtin_aarch64_simd_oi __o ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregoiv16qi ( __o , ( int8x16_t ) tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ;

return ( uint8x16_t ) __builtin_aarch64_tbx4v16qi ( ( int8x16_t ) r , __o , ( int8x16_t ) idx ) ;


<s> if ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) return <NUM_LIT> * <NUM_LIT> / ElemWidth ;

return ( ElemWidth == <NUM_LIT> && ST -> has16BitInsts ( ) ) ? <NUM_LIT> : ( ElemWidth == <NUM_LIT> && ST -> hasPackedFP32Ops ( ) ) ? <NUM_LIT> : <NUM_LIT> ;


<s> Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( ) ) ; }

OffImm = CurDAG -> getTargetConstant ( RHSC / <NUM_LIT> , <STR_LIT> ) ;


<s> static void s390_optimize_register_info ( ) { char clobbered_regs [ <NUM_LIT> ] ; int i , j ; gcc_assert ( epilogue_completed ) ; gcc_assert ( ! cfun -> machine -> split_branches_pending_p ) ; s390_regs_ever_clobbered ( clobbered_regs ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) clobbered_regs [ i ] = clobbered_regs [ i ] && ! global_regs [ i ] ; clobbered_regs [ RETURN_REGNUM ] |= ( TARGET_TPF_PROFILING || cfun_frame_layout . save_return_addr_p || crtl -> calls_eh_return ) ; memset ( cfun_frame_layout . gpr_save_slots , <NUM_LIT> , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( ! clobbered_regs [ i ] ) cfun_gpr_save_slot ( i ) = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < <NUM_LIT> && cfun_gpr_save_slot ( i ) != - <NUM_LIT> ; i ++ ) ; for ( j = <NUM_LIT> ; j > i && cfun_gpr_save_slot ( j ) != - <NUM_LIT> ; j -- ) ; cfun_frame_layout . first_restore_gpr = ( i == <NUM_LIT> ) ? - <NUM_LIT> : i ; cfun_frame_layout . last_restore_gpr = ( i == <NUM_LIT> ) ? - <NUM_LIT> : j ; s390_register_info_stdarg_gpr ( ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> && cfun_gpr_save_slot ( i ) != - <NUM_LIT> ; i ++ ) ;


<s> int data_ref_p ( rtx X ) { if ( TARGET_PIC ) return <NUM_LIT> ; if ( TARGET_BIG ) return ( data_ref_p_1 ( X ) || ( GET_CODE ( X ) == CONST && data_ref_p_1 ( XEXP ( X , <NUM_LIT> ) ) ) ) ;


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> cfun -> machine -> doloop_tag_from_end = is_end ; } tag = GEN_INT ( cfun -> machine -> doloop_tags - <NUM_LIT> ) ; machine_mode opmode = GET_MODE ( operands [ <NUM_LIT> ] ) ;

gcc_assert ( opmode == HImode || opmode == SImode ) ;


<s> void <ISA_LIT>CFGStructurizer :: removeSuccessor ( MachineBasicBlock * MBB ) { while ( MBB -> succ_size ( ) ) MBB -> removeSuccessor ( * MBB -> succ_begin ( ) ) ;


<s> assert ( DefMI . getNumOperands ( ) >= <NUM_LIT> && <STR_LIT> ) ; RegMO = & DefMI . getOperand ( <NUM_LIT> ) ;

ImmMO = & DefMI . getOperand ( <NUM_LIT> ) ;


<s> rs6000_cost_data * data = XNEW ( struct _rs6000_cost_data ) ; data -> loop_info = loop_info ; data -> cost [ vect_prologue ] = <NUM_LIT> ; data -> cost [ vect_body ] = <NUM_LIT> ; data -> cost [ vect_epilogue ] = <NUM_LIT> ; rs6000_vect_nonmem = false ;


<s> } const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { switch ( Op . getReg ( ) ) { case <STR_LIT> : break ; default : printRegOperand ( Op . getReg ( ) , O , MRI ) ; break ; } } else if ( Op . isImm ( ) ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; if ( RCID != - <NUM_LIT> ) { const MCRegisterClass & ImmRC = MRI . getRegClass ( RCID ) ; if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate32 ( Op . getImm ( ) , O ) ; else if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate64 ( Op . getImm ( ) , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } else if ( Desc . OpInfo [ OpNo ] . OperandType == MCOI :: OPERAND_IMMEDIATE ) { printImmediate32 ( Op . getImm ( ) , O ) ; } else { O << formatDec ( Op . getImm ( ) ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; const MCRegisterClass & ImmRC = MRI . getRegClass ( Desc . OpInfo [ OpNo ] . RegClass ) ; if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , O ) ; else if ( ImmRC . getSize ( ) == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , O ) ; else llvm_unreachable ( <STR_LIT> ) ; }


<s> explicit <ISA_LIT>FloatMCExpr ( VariantKind Kind , APFloat Flt ) : Kind ( Kind ) , Flt ( std :: move ( Flt ) ) {


<s> const MCOperand & DstRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( DstRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & BaseRegOp = Inst . getOperand ( <NUM_LIT> ) ; assert ( BaseRegOp . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetOp = Inst . getOperand ( <NUM_LIT> ) ; <ISA_LIT>TargetStreamer & TOut = getTargetStreamer ( ) ; unsigned DstReg = DstRegOp . getReg ( ) ; unsigned BaseReg = BaseRegOp . getReg ( ) ; unsigned TmpReg = DstReg ; const MCInstrDesc & Desc = getInstDesc ( Inst . getOpcode ( ) ) ; int16_t DstRegClass = Desc . OpInfo [ <NUM_LIT> ] . RegClass ; unsigned DstRegClassID = getContext ( ) . getRegisterInfo ( ) -> getRegClass ( DstRegClass ) . getID ( ) ; bool IsGPR = ( DstRegClassID == <STR_LIT> ) || ( DstRegClassID == <STR_LIT> ) ; if ( ! IsLoad || ! IsGPR || ( BaseReg == DstReg ) ) { TmpReg = getATReg ( IDLoc ) ; if ( ! TmpReg ) return ; } if ( OffsetOp . isImm ( ) ) { int64_t LoOffset = OffsetOp . getImm ( ) & <NUM_LIT> ; int64_t HiOffset = OffsetOp . getImm ( ) & ~ <NUM_LIT> ; if ( LoOffset & <NUM_LIT> ) HiOffset += <NUM_LIT> ; bool IsLargeOffset = HiOffset != <NUM_LIT> ; if ( IsLargeOffset ) { bool Is32BitImm = ( HiOffset >> <NUM_LIT> ) == <NUM_LIT> ; if ( loadImmediate ( HiOffset , TmpReg , <STR_LIT> , Is32BitImm , true , IDLoc , Out , STI ) ) return ; } if ( BaseReg != <STR_LIT> && BaseReg != <STR_LIT> ) TOut . emitRRR ( isGP64bit ( ) ? <STR_LIT> : <STR_LIT> , TmpReg , TmpReg , BaseReg , IDLoc , STI ) ; TOut . emitRRI ( Inst . getOpcode ( ) , DstReg , TmpReg , LoOffset , IDLoc , STI ) ; return ; } assert ( OffsetOp . isExpr ( ) && <STR_LIT> ) ; if ( inPicMode ( ) ) { expandLoadAddress ( TmpReg , <STR_LIT> , OffsetOp , ! ABI . ArePtrs64bit ( ) , IDLoc , Out , STI ) ; TOut . emitRRI ( Inst . getOpcode ( ) , DstReg , TmpReg , <NUM_LIT> , IDLoc , STI ) ; } else { const MCExpr * ExprOffset = OffsetOp . getExpr ( ) ; MCOperand LoOperand = MCOperand :: createExpr ( <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_LO , ExprOffset , getContext ( ) ) ) ; MCOperand HiOperand = MCOperand :: createExpr ( <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_HI , ExprOffset , getContext ( ) ) ) ;

if ( IsLoad ) TOut . emitLoadWithSymOffset ( Inst . getOpcode ( ) , DstReg , BaseReg , HiOperand , LoOperand , TmpReg , IDLoc , STI ) ;


<s> StringRef getPassName ( ) const override {


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const {


<s> if ( Subtarget . isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , dl , PtrVT ) , Result ) ; }


<s> return __builtin_mve_vmlaldavq_uv8hi ( __a , __b ) ;


<s> raw_svector_ostream OS ( Str ) ; printSavedRegsBitmask ( OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ;

OutStreamer . EmitRawText ( StringRef ( <STR_LIT> ) ) ;


<s> if ( ImmNode . getOpcode ( ) == <STR_LIT> ) { if ( ImmNode . getValueType ( ) . getScalarSizeInBits ( ) != ScalarBits ) return false ; ImmNode = ImmNode . getOperand ( <NUM_LIT> ) ; } if ( ImmNode . getValueType ( ) . getScalarSizeInBits ( ) != ScalarBits ) return false ; APFloat ImmAPF ( <NUM_LIT> ) ; switch ( ImmNode . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { if ( ! isa < ConstantSDNode > ( ImmNode . getOperand ( <NUM_LIT> ) ) ) return false ; unsigned Imm = ImmNode . getConstantOperandVal ( <NUM_LIT> ) ; if ( ImmNode . getOpcode ( ) == <STR_LIT> ) Imm = <STR_LIT> ( Imm , ScalarBits ) ; ImmAPF = APFloat ( ScalarBits == <NUM_LIT> ? APFloat :: IEEEsingle ( ) : APFloat :: IEEEhalf ( ) , APInt ( ScalarBits , Imm ) ) ; break ; } case <STR_LIT> : { ImmAPF = APFloat ( <STR_LIT> ( ImmNode . getConstantOperandVal ( <NUM_LIT> ) ) ) ; break ; } default : return false ; } APFloat ToConvert = ImmAPF ; if ( FixedToFloat ) { if ( ! ImmAPF . getExactInverse ( & ToConvert ) ) return false ; } APSInt Converted ( <NUM_LIT> , false ) ; bool IsExact ; ToConvert . convertToInteger ( Converted , llvm :: RoundingMode :: NearestTiesToEven , & IsExact ) ; if ( ! IsExact || ! Converted . isPowerOf2 ( ) ) return false ; unsigned FracBits = Converted . logBase2 ( ) ; if ( FracBits > ScalarBits ) return false ; SmallVector < SDValue , <NUM_LIT> > Ops { VecVal , CurDAG -> getConstant ( FracBits , SDLoc ( N ) , <STR_LIT> ) } ; AddEmptyMVEPredicateToOps ( Ops , SDLoc ( N ) , Type ) ; unsigned int Opcode ;


<s> return ( uint8x16_t ) __builtin_neon_vtstv16qi ( ( int8x16_t ) __a , ( int8x16_t ) __b ) ;


<s> DwarfAbbrevSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfStrSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLocSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfARangesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;

DwarfRangesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;


<s> bool constrainRegOperands ( MachineInstrBuilder & MIB , MachineFunction * MF ) { if ( ! MF ) MF = MIB -> getMF ( ) ; const auto & Subtarget = MF -> getSubtarget ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ;

const RegisterBankInfo * RBI = Subtarget . getRegBankInfo ( ) ;


<s> break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( LHS ) ) { LHS = RHS ; RHS = DAG . getConstant ( C -> getSExtValue ( ) + <NUM_LIT> , dl , C -> getValueType ( <NUM_LIT> ) ) ; TCC = <STR_LIT> ; break ; } TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( LHS ) ) { LHS = RHS ; RHS = DAG . getConstant ( C -> getSExtValue ( ) + <NUM_LIT> , dl , C -> getValueType ( <NUM_LIT> ) ) ; TCC = <STR_LIT> ; break ; } TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : if ( const ConstantSDNode * C = dyn_cast < ConstantSDNode > ( LHS ) ) { LHS = RHS ; RHS = DAG . getConstant ( C -> getSExtValue ( ) + <NUM_LIT> , dl , C -> getValueType ( <NUM_LIT> ) ) ; TCC = <STR_LIT> ; break ; }


<s> fprintf ( dump_file , <STR_LIT> , depth , par -> mask , par -> forked_block ? par -> forked_block -> index : - <NUM_LIT> , par -> join_block ? par -> join_block -> index : - <NUM_LIT> ) ; fprintf ( dump_file , <STR_LIT> ) ; basic_block block ; for ( unsigned ix = <NUM_LIT> ; par -> blocks . iterate ( ix , & block ) ; ix ++ ) fprintf ( dump_file , <STR_LIT> , block -> index ) ; fprintf ( dump_file , <STR_LIT> ) ; if ( par -> inner ) nvptx_dump_pars ( par -> inner , depth + <NUM_LIT> ) ;

if ( par -> next ) nvptx_dump_pars ( par -> next , depth ) ;


<s> } else if ( NONJUMP_INSN_P ( insn ) || CALL_P ( insn ) ) { rtx pool_ref = NULL_RTX ; find_constant_pool_ref ( PATTERN ( insn ) , & pool_ref ) ; if ( pool_ref ) { rtx constant = get_pool_constant ( pool_ref ) ; machine_mode mode = get_pool_mode ( pool_ref ) ; s390_add_constant ( pool , constant , mode ) ; } } if ( NOTE_P ( insn ) && NOTE_KIND ( insn ) == NOTE_INSN_SWITCH_TEXT_SECTIONS && ! pool -> emit_pool_after ) pool -> emit_pool_after = PREV_INSN ( insn ) ; } gcc_assert ( pool -> pool_insn || pool -> size == <NUM_LIT> ) ; if ( pool -> size >= <NUM_LIT> ) { remove_insn ( pool -> pool_insn ) ;


<s> for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedCPU64Regs ) ; ++ I ) Reserved . set ( ReservedCPU64Regs [ I ] ) ; for ( RegIter Reg = <STR_LIT> -> begin ( ) ; Reg != <STR_LIT> -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = <STR_LIT> -> begin ( ) ; Reg != <STR_LIT> -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ; for ( RegIter Reg = <STR_LIT> -> begin ( ) ; Reg != <STR_LIT> -> end ( ) ; ++ Reg ) Reserved . set ( * Reg ) ;


<s> if ( RC -> getSize ( ) == <NUM_LIT> && <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; } bool HasAVX = TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX ( ) ; switch ( RC -> getSize ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ) if ( isHReg ( Reg ) || <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) return load ? <STR_LIT> : <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; return load ? <STR_LIT> : <STR_LIT> ; case <NUM_LIT> : { assert ( <STR_LIT> . hasSubClassEq ( RC ) && <STR_LIT> ) ; if ( isStackAligned ) return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) : ( HasAVX ? <STR_LIT> : <STR_LIT> ) ;

else return load ? ( HasAVX ? <STR_LIT> : <STR_LIT> ) :


<s> <ISA_LIT>ModeRegisterDefaults Mode ; Mode . IEEE = ! <STR_LIT> ( CC ) ;


<s> unsigned GlobalBaseReg = TM . getSubtargetImpl ( ) -> getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ; return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( ) ) . getNode ( ) ;


<s> return :: isPSHUFDMask ( N -> getMask ( ) , N -> getValueType ( <NUM_LIT> ) ) ;


<s> StringRef getPassName ( ) const override {


<s> } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = Subtarget -> hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return <NUM_LIT> ; } unsigned Align = DL . getPrefTypeAlignment ( CFP -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( CFP -> getType ( ) ) ; } unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = Subtarget -> classifyLocalReference ( nullptr ) ; if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( Subtarget -> is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; unsigned CPI = MCP . getConstantPoolIndex ( CFP , Align ) ; unsigned ResultReg = createResultReg ( RC ) ; if ( CM == CodeModel :: Large ) { unsigned AddrReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , AddrReg ) . addConstantPoolIndex ( CPI , <NUM_LIT> , OpFlag ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; addDirectMem ( MIB , AddrReg ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , DL . getPointerSize ( ) , Align ) ; MIB -> addMemOperand ( * FuncInfo . MF , MMO ) ; return ResultReg ; } addConstantPoolReference ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) , CPI , PICBase , OpFlag ) ;


<s> if ( auto * GEP = dyn_cast < GetElementPtrInst > ( Inst ) ) for ( auto Usr : GEP -> users ( ) ) if ( auto I = dyn_cast < Instruction > ( Usr ) ) if ( hasVolatileAccess ( I ) ) return true ; return false ;


<s> if ( set ) { rtx tmp = SET_SRC ( set ) ; if ( REG_P ( tmp ) && HARD_REGISTER_P ( tmp ) && ! TEST_HARD_REG_BIT ( fixed_reg_set , REGNO ( tmp ) ) && ix86_class_likely_spilled_p ( REGNO_REG_CLASS ( REGNO ( tmp ) ) ) ) return current_sched_info -> sched_max_insns_priority ; } return priority ;


<s> <ISA_LIT>Disassembler ( ) : MCDisassembler ( ) {


<s> VarArgsLoweringHelper ( <ISA_LIT>MachineFunctionInfo * FuncInfo , const SDLoc & Loc , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget , CallingConv :: ID CallConv , CCState & CCInfo ) : FuncInfo ( FuncInfo ) , DL ( Loc ) , DAG ( DAG ) , Subtarget ( Subtarget ) , TheMachineFunction ( DAG . getMachineFunction ( ) ) , TheFunction ( TheMachineFunction . getFunction ( ) ) , FrameInfo ( TheMachineFunction . getFrameInfo ( ) ) , FrameLowering ( * Subtarget . getFrameLowering ( ) ) , TargLowering ( DAG . getTargetLoweringInfo ( ) ) , CallConv ( CallConv ) , CCInfo ( CCInfo ) {


<s> return __builtin_mve_vidupq_n_uv4si ( __a , __imm ) ;


<s> setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } if ( STI . getHasAlu32 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( MVT VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Expand ) ; } setBooleanContents ( ZeroOrOneBooleanContent ) ; setMinFunctionAlignment ( <NUM_LIT> ) ; setPrefFunctionAlignment ( <NUM_LIT> ) ; if ( <ISA_LIT>ExpandMemcpyInOrder ) { MaxStoresPerMemset = MaxStoresPerMemsetOptSize = <NUM_LIT> ; MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = <NUM_LIT> ; MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = <NUM_LIT> ; } else { unsigned CommonMaxStores = STI . getSelectionDAGInfo ( ) -> getCommonMaxStoresPerMemFunc ( ) ; MaxStoresPerMemset = MaxStoresPerMemsetOptSize = CommonMaxStores ; MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = CommonMaxStores ; MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = CommonMaxStores ;


<s> bool BlackfinFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const {


<s> unsigned DstMI , SrcMI ; for ( MachineInstr :: const_mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { const MachineOperand & MO = * I ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isDef ( ) ) { Register Reg = MO . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) DstMI = Reg ; else DstMI = TRI -> getMatchingSuperReg ( Reg , <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( TRI -> getHWRegChan ( Reg ) ) , & <STR_LIT> ) ;


<s> bool <ISA_LIT>FastISel :: SelectTrunc ( const Instruction * I ) { Value * Src = I -> getOperand ( <NUM_LIT> ) ; EVT SrcVT = TLI . getValueType ( DL , Src -> getType ( ) , true ) ;

EVT DestVT = TLI . getValueType ( DL , I -> getType ( ) , true ) ;


<s> static bool IsComment ( MachineInstr * I ) {

return I -> getNumOperands ( ) == <NUM_LIT> && I -> getOperand ( <NUM_LIT> ) . isMetadata ( ) ;


<s> if ( AddeOp0 . getNode ( ) == AddeOp1 . getNode ( ) ) return SDValue ( ) ; bool IsLeftOperandMUL = false ; SDValue MULOp = findMUL_LOHI ( AddeOp0 ) ; if ( MULOp == SDValue ( ) ) MULOp = findMUL_LOHI ( AddeOp1 ) ; else IsLeftOperandMUL = true ; if ( MULOp == SDValue ( ) ) return SDValue ( ) ; unsigned Opc = MULOp -> getOpcode ( ) ; unsigned FinalOpc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue * HiAdd = nullptr ; SDValue * LoMul = nullptr ; SDValue * LowAdd = nullptr ; if ( ( AddeOp0 != MULOp . getValue ( <NUM_LIT> ) ) && ( AddeOp1 != MULOp . getValue ( <NUM_LIT> ) ) ) return SDValue ( ) ; if ( IsLeftOperandMUL ) HiAdd = & AddeOp1 ; else HiAdd = & AddeOp0 ; if ( AddcOp0 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp0 ; LowAdd = & AddcOp1 ; } if ( AddcOp1 == MULOp . getValue ( <NUM_LIT> ) ) { LoMul = & AddcOp1 ; LowAdd = & AddcOp0 ; } if ( ! LoMul ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( LoMul -> getOperand ( <NUM_LIT> ) ) ; Ops . push_back ( * LowAdd ) ;


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count ) const { for ( uint64_t i = <NUM_LIT> ; i < Count ; ++ i ) OS << char ( <STR_LIT> ) ;


<s> if ( <NUM_LIT> <= param && param <= <NUM_LIT> ) nios2_register_custom_code ( param , CCS_FPU , fpu_insn_index ) ;

else if ( param != - <NUM_LIT> ) error ( <STR_LIT> , N2FPU_NAME ( fpu_insn_index ) , param ) ;


<s> __builtin_ia32_storeupd128_mask ( ( double * ) __P , ( __v2df ) __A , ( __mmask8 ) __U ) ;


<s> case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( Flags . isByVal ( ) ) Arg = ByValArgs [ J ++ ] ; if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo ( ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ArrayRef < SDValue > ( & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ) ; SDValue InFlag ; for ( unsigned I = <NUM_LIT> , E = RegsToPass . size ( ) ; I != E ; ++ I ) { Chain = DAG . getCopyToReg ( Chain , DL , RegsToPass [ I ] . first , RegsToPass [ I ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } uint8_t OpFlag = <STR_LIT> ; if ( G ) { Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , DL , getPointerTy ( DAG . getDataLayout ( ) ) , <NUM_LIT> , OpFlag ) ; } else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) , OpFlag ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> MaxNumVGPRs = ST -> getMaxNumVGPRs ( MF ) ; MaxNumVGPRs = std :: min ( ST -> getMaxNumVGPRs ( MFI -> getOccupancy ( ) ) , MaxNumVGPRs ) ; CSRegs = MRI -> getCalleeSavedRegs ( ) ; using Candidate = std :: pair < const MachineInstr * , bool > ; SmallVector < Candidate , <NUM_LIT> > Candidates ; for ( const MachineBasicBlock & MBB : MF ) { for ( const MachineInstr & MI : MBB ) { switch ( CheckNSA ( MI ) ) { default : continue ; case NSA_Status :: CONTIGUOUS : Candidates . push_back ( std :: make_pair ( & MI , true ) ) ; break ; case NSA_Status :: NON_CONTIGUOUS : Candidates . push_back ( std :: make_pair ( & MI , false ) ) ; ++ NumNSAInstructions ; break ; } } } bool Changed = false ; for ( auto & C : Candidates ) { if ( C . second ) continue ; const MachineInstr * MI = C . first ; if ( CheckNSA ( * MI , true ) == NSA_Status :: CONTIGUOUS ) { C . second = true ; ++ NumNSAConverted ; continue ; } const <STR_LIT> * Info = <STR_LIT> ( MI -> getOpcode ( ) ) ; int VAddr0Idx = <STR_LIT> ( MI -> getOpcode ( ) , <STR_LIT> :: vaddr0 ) ; SmallVector < LiveInterval * , <NUM_LIT> > Intervals ; SmallVector < unsigned , <NUM_LIT> > OrigRegs ; SlotIndex MinInd , MaxInd ; for ( unsigned I = <NUM_LIT> ; I < Info -> VAddrDwords ; ++ I ) { const MachineOperand & Op = MI -> getOperand ( VAddr0Idx + I ) ; Register Reg = Op . getReg ( ) ; LiveInterval * LI = & LIS -> getInterval ( Reg ) ; if ( llvm :: find ( Intervals , LI ) != Intervals . end ( ) ) { Intervals . clear ( ) ; break ;


<s> TargetRegistry :: RegisterMCInstrInfo ( T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( T , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCAsmBackend ( T , create<ISA_LIT>AsmBackend ) ;

TargetRegistry :: RegisterMCCodeEmitter ( T , create<ISA_LIT>MCCodeEmitter ) ;


<s> EVT VT = <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; LROpOut = getReturnAddrFrameIndex ( DAG ) ; LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = SDValue ( LROpOut . getNode ( ) , <NUM_LIT> ) ; if ( isDarwinABI ) { FPOpOut = getFramePointerFrameIndex ( DAG ) ; FPOpOut = DAG . getLoad ( VT , dl , Chain , FPOpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = SDValue ( FPOpOut . getNode ( ) , <NUM_LIT> ) ; }


<s> case LEU : cr16_cmp_str = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } fprintf ( file , <STR_LIT> , cr16_cmp_str ) ; return ; } case '$' : putc ( '$' , file ) ; return ; case 'p' : if ( GET_CODE ( x ) == REG ) { fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) ] ) ; return ; } break ; case 'b' : fprintf ( file , <STR_LIT> , INTVAL ( x ) ) ; return ; case 'r' : fprintf ( file , <STR_LIT> , cr16_operand_bit_pos ( INTVAL ( x ) , <NUM_LIT> ) ) ; return ; case 's' : fprintf ( file , <STR_LIT> , cr16_operand_bit_pos ( INTVAL ( x ) , <NUM_LIT> ) ) ; return ; case 'g' : ptr_dereference = <NUM_LIT> ; case 'f' : case <NUM_LIT> : switch ( GET_CODE ( x ) ) { case REG : if ( GET_MODE_BITSIZE ( GET_MODE ( x ) ) > BITS_PER_WORD ) { if ( LONG_REG_P ( REGNO ( x ) ) ) fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) ] ) ; else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) + <NUM_LIT> ] , reg_names [ REGNO ( x ) ] ) ; } else fprintf ( file , <STR_LIT> , reg_names [ REGNO ( x ) ] ) ; return ; case MEM : output_address ( GET_MODE ( x ) , XEXP ( x , <NUM_LIT> ) ) ; return ; case CONST_DOUBLE : { long l ; REAL_VALUE_TO_TARGET_SINGLE ( * CONST_DOUBLE_REAL_VALUE ( x ) , l ) ; fprintf ( file , <STR_LIT> , l ) ; return ; } case CONST_INT : { fprintf ( file , <STR_LIT> , INTVAL ( x ) ) ; return ; } case UNSPEC : switch ( XINT ( x , <NUM_LIT> ) ) { default : gcc_unreachable ( ) ; } break ; default : if ( ! ptr_dereference ) { putc ( '$' , file ) ; } cr16_print_operand_address ( file , VOIDmode , x ) ; return ; } default : output_operand_lossage ( <STR_LIT> ) ; } gcc_unreachable ( ) ;


<s> if ( TARGET_H8300 ) return ( ( regno & <NUM_LIT> ) == <NUM_LIT> ) || ( mode == HImode ) || ( mode == QImode ) ; else return regno == MAC_REG ? mode == SImode : <NUM_LIT> ;


<s> if ( landBlkHasOtherPred ) { unsigned immReg = funcRep -> getRegInfo ( ) . createVirtualRegister ( I32RC ) ; CFGTraits :: insertAssignInstrBefore ( insertPos , passRep , immReg , <NUM_LIT> ) ; unsigned cmpResReg = funcRep -> getRegInfo ( ) . createVirtualRegister ( I32RC ) ; CFGTraits :: insertCompareInstrBefore ( landBlk , insertPos , passRep , cmpResReg , initReg , immReg ) ; CFGTraits :: insertCondBranchBefore ( landBlk , insertPos , AMDGPU :: IF_PREDICATE_SET , passRep , cmpResReg , DebugLoc ( ) ) ; } CFGTraits :: insertCondBranchBefore ( landBlk , insertPos , AMDGPU :: IF_PREDICATE_SET , passRep , initReg , DebugLoc ( ) ) ; if ( migrateTrue ) { migrateInstruction ( trueBlk , landBlk , insertPos ) ; CFGTraits :: insertAssignInstrBefore ( trueBlk , passRep , initReg , <NUM_LIT> ) ; } CFGTraits :: insertInstrBefore ( insertPos , AMDGPU :: ELSE , passRep ) ; if ( migrateFalse ) { migrateInstruction ( falseBlk , landBlk , insertPos ) ; CFGTraits :: insertAssignInstrBefore ( falseBlk , passRep , initReg , <NUM_LIT> ) ; } if ( landBlkHasOtherPred ) { CFGTraits :: insertInstrBefore ( insertPos , AMDGPU :: ENDIF , passRep ) ; for ( typename BlockT :: pred_iterator predIter = landBlk -> pred_begin ( ) , predIterEnd = landBlk -> pred_end ( ) ; predIter != predIterEnd ;


<s> if ( Best == Last || BetterThan ( * I , * Best ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; Best = I ; } } if ( Matched == FindBest_PerfectMatch ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> if ( n_src == <NUM_LIT> ) avr_asm_len ( AVR_HAVE_MOVW ? <STR_LIT> : <STR_LIT> , xop , plen , <NUM_LIT> ) ; if ( n_src == <NUM_LIT> || ! AVR_HAVE_MOVW ) avr_asm_len ( <STR_LIT> , xop , plen , <NUM_LIT> ) ; } if ( REGNO ( xop [ <NUM_LIT> ] ) == REGNO ( xop [ <NUM_LIT> ] ) || ! reg_unused_after ( insn , r_msb ) ) { avr_asm_len ( <STR_LIT> , & r_msb , plen , <NUM_LIT> ) ; r_msb = tmp_reg_rtx ; } avr_asm_len ( <STR_LIT> , & r_msb , plen , <NUM_LIT> ) ;

for ( unsigned n = n_src ; n < n_dest ; n ++ ) avr_asm_len ( <STR_LIT> , & all_regs_rtx [ REGNO ( xop [ <NUM_LIT> ] ) + n ] , plen , <NUM_LIT> ) ;


<s> CM = RM == Reloc :: PIC_ ? CodeModel :: Small : CodeModel :: Medium ; break ; case CodeModel :: JITDefault : CM = CodeModel :: Large ;


<s> assert ( GlueChain -> getNumValues ( ) == <NUM_LIT> ) ; SDVTList VTList = DAG . getVTList ( VT , <STR_LIT> , <STR_LIT> ) ; switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; }

return DAG . getNode ( Opcode , SL , VTList , { GlueChain . getValue ( <NUM_LIT> ) , A , B , GlueChain . getValue ( <NUM_LIT> ) } , Flags ) ;


<s> if ( REG_NOTE_KIND ( link ) == REG_DEP_ANTI || REG_NOTE_KIND ( link ) == REG_DEP_OUTPUT ) return <NUM_LIT> ; if ( REG_NOTE_KIND ( link ) == <NUM_LIT> && CALL_P ( insn ) ) return <NUM_LIT> ; if ( ( i_pat = single_set ( insn ) ) != NULL && MEM_P ( SET_SRC ( i_pat ) ) && ( d_pat = single_set ( dep ) ) != NULL && MEM_P ( SET_DEST ( d_pat ) ) ) {

rtx src_mem = XEXP ( SET_SRC ( i_pat ) , <NUM_LIT> ) ;


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case Function :: PrivateLinkage : case Function :: InternalLinkage : break ; case Function :: ExternalLinkage : O << <STR_LIT> << CurrentFnName << <STR_LIT> << <STR_LIT> << CurrentFnName << <STR_LIT> ; break ; case Function :: WeakAnyLinkage : case Function :: WeakODRLinkage : case Function :: LinkOnceAnyLinkage : case Function :: LinkOnceODRLinkage : O << <STR_LIT> << CurrentFnName << <STR_LIT> ; O << <STR_LIT> << CurrentFnName << <STR_LIT> ; break ; } O << CurrentFnName << <STR_LIT> ; DW -> BeginFunction ( & MF ) ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( I != MF . begin ( ) ) { printBasicBlockLabel ( I , true , true ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { printMachineInstruction ( II ) ; } } O << <STR_LIT> << CurrentFnName << <STR_LIT> << CurrentFnName << <STR_LIT> ; EmitJumpTableInfo ( MF . getJumpTableInfo ( ) , MF ) ; DW -> EndFunction ( & MF ) ; return false ;


<s> else if ( ValVT . isVector ( ) ) return LowerSTOREVector ( Op , DAG ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> std :: pair < Register , Register > <ISA_LIT>InstructionSelector :: selectAddrLoHi ( MachineInstr & MI ) { MachineIRBuilder Builder ( MI ) ; LLT S8 = LLT :: scalar ( <NUM_LIT> ) ; auto LoImm = Builder . buildInstr ( <STR_LIT> , { S8 } , { } ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; LoImm -> getOperand ( <NUM_LIT> ) . setTargetFlags ( <STR_LIT> ) ; if ( ! constrainSelectedInstRegOperands ( * LoImm , TII , TRI , RBI ) ) llvm_unreachable ( <STR_LIT> ) ; auto HiImm = Builder . buildInstr ( <STR_LIT> , { S8 } , { } ) . add ( MI . getOperand ( <NUM_LIT> ) ) ;

HiImm -> getOperand ( <NUM_LIT> ) . setTargetFlags ( <STR_LIT> ) ;


<s> uint8_t get_sew ( ) const { return m_sew ;


<s> const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; const <ISA_LIT>FrameLowering & TFI = * Subtarget . getFrameLowering ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; const unsigned ProbeSize = getStackProbeSize ( * MF ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; MachineBasicBlock * testMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * tailMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * blockMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator MBBIter = ++ MBB -> getIterator ( ) ; MF -> insert ( MBBIter , testMBB ) ; MF -> insert ( MBBIter , blockMBB ) ; MF -> insert ( MBBIter , tailMBB ) ; Register sizeVReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register physSPReg = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; Register TmpStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; Register FinalStackPtr = MRI . createVirtualRegister ( TFI . Uses64BitFramePtr ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * MBB , { MI } , DL , TII -> get ( TargetOpcode :: COPY ) , TmpStackPtr ) . addReg ( physSPReg ) ; { const unsigned Opc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , { MI } , DL , TII -> get ( Opc ) , FinalStackPtr ) . addReg ( TmpStackPtr ) . addReg ( sizeVReg ) ; } BuildMI ( testMBB , DL , TII -> get ( TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ) ) . addReg ( physSPReg ) . addReg ( FinalStackPtr ) ; BuildMI ( testMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( tailMBB ) . addImm ( <STR_LIT> ) ; testMBB -> addSuccessor ( blockMBB ) ; testMBB -> addSuccessor ( tailMBB ) ; BuildMI ( blockMBB , DL , TII -> get ( getSUBriOpcode ( TFI . Uses64BitFramePtr , ProbeSize ) ) , physSPReg ) . addReg ( physSPReg ) . addImm ( ProbeSize ) ; const unsigned MovMIOpc = TFI . Uses64BitFramePtr ? <STR_LIT> : <STR_LIT> ; addRegOffset ( BuildMI ( blockMBB , DL , TII -> get ( MovMIOpc ) ) , physSPReg , false , <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( blockMBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( testMBB ) ;


<s> unsigned PO = Offset + Size ; unsigned LA = std :: max ( unsigned ( PostAlign ) , LogAlign ) ;


<s> LoopStats ( unsigned Phi_ , unsigned Iter_ , MachineLoop * L_ ) : Phi ( Phi_ ) , Iter ( Iter_ ) , CounterReg ( <NUM_LIT> ) , ImmStep ( false ) , L ( L_ ) {


<s> int value = ( int ) MI -> getOperand ( OpNo ) . getImm ( ) ; assert ( ( value >= <NUM_LIT> && value <= <NUM_LIT> ) && <STR_LIT> ) ; O << - value ;


<s> bool <ISA_LIT>AnnotateUniformValues :: doInitialization ( Module & M ) { AMDGPUA<ISA_LIT> = <STR_LIT> ( M ) ; return false ;


<s> if ( min_offset < <NUM_LIT> || max_offset >= <NUM_LIT> ) return SImode ; else {

if ( max_offset >= <NUM_LIT> ) return HImode ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ;

if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! Subtarget -> isABI_N64 ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ;


<s> <ISA_LIT>Operand ( KindTy K , <ISA_LIT>AsmParser & Parser ) : MCParsedAsmOperand ( ) , Kind ( K ) , AsmParser ( Parser ) {


<s> Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; Offset += MO . getOffset ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; Offset += MO . getOffset ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , Kind , * Ctx ) ; if ( ! Offset ) return MCOperand :: createExpr ( MCSym ) ;


<s> emitInlineJumpTable ( MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ) ; return ; } unsigned Binary = getBinaryCodeForInstr ( MI ) ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; if ( TID . Opcode == <STR_LIT> ) Binary |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( <STR_LIT> ) ; else Binary |= getMachineOpValue ( MI , <NUM_LIT> ) ; emitWordLE ( Binary ) ;


<s> RxSBGOperands RxSBG [ ] = { RxSBGOperands ( Opcode , N -> getOperand ( <NUM_LIT> ) ) , RxSBGOperands ( Opcode , N -> getOperand ( <NUM_LIT> ) ) } ; unsigned Count [ ] = { <NUM_LIT> , <NUM_LIT> } ; for ( unsigned I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) while ( expandRxSBG ( RxSBG [ I ] ) ) if ( RxSBG [ I ] . Input . getOpcode ( ) != <STR_LIT> ) Count [ I ] += <NUM_LIT> ; if ( Count [ <NUM_LIT> ] == <NUM_LIT> && Count [ <NUM_LIT> ] == <NUM_LIT> ) return false ; unsigned I = Count [ <NUM_LIT> ] > Count [ <NUM_LIT> ] ? <NUM_LIT> : <NUM_LIT> ; SDValue Op0 = N -> getOperand ( I ^ <NUM_LIT> ) ; if ( Opcode == <STR_LIT> && ( RxSBG [ I ] . Mask & <NUM_LIT> ) == <NUM_LIT> ) if ( auto * Load = dyn_cast < LoadSDNode > ( Op0 . getNode ( ) ) ) if ( Load -> getMemoryVT ( ) == <STR_LIT> ) return false ;

if ( Opcode == <STR_LIT> && detectOrAndInsertion ( Op0 , RxSBG [ I ] . Mask ) ) {


<s> return ggc_alloc_cleared ( sizeof ( struct machine_function ) ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ;


<s> if ( ImmMO . isGlobal ( ) ) { const DataLayout & DL = ImmMO . getGlobal ( ) -> getParent ( ) -> getDataLayout ( ) ; if ( ImmMO . getGlobal ( ) -> getPointerAlignment ( DL ) < III . ImmMustBeMultipleOf ) return false ; } return true ; } if ( ImmMO . isImm ( ) ) { APInt ActualValue ( <NUM_LIT> , ImmMO . getImm ( ) + BaseImm , true ) ; if ( III . SignedImm && ! ActualValue . isSignedIntN ( III . ImmWidth ) ) return false ; if ( ! III . SignedImm && ! ActualValue . isIntN ( III . ImmWidth ) ) return false ; Imm = SignExtend64 < <NUM_LIT> > ( ImmMO . getImm ( ) + BaseImm ) ; if ( Imm % III . ImmMustBeMultipleOf ) return false ; if ( III . TruncateImmTo ) Imm &= ( ( <NUM_LIT> << III . TruncateImmTo ) - <NUM_LIT> ) ; }


<s> if ( IsNegative ) Val = - Val ; Operands . push_back ( make_unique < <ISA_LIT>Operand > ( <STR_LIT> , Flt . getLoc ( ) , Flt . getEndLoc ( ) , <STR_LIT> { Val } ) ) ; Parser . Lex ( ) ;


<s> unsigned getMaxMemcpyTPInlineSizeThreshold ( ) const { return <NUM_LIT> ;


<s> unsigned <ISA_LIT>RegisterInfo :: getEHHandlerRegister ( ) const {


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; const int VALUWaitStates = <NUM_LIT> ; int WaitStatesNeeded = <NUM_LIT> ; if ( ! TRI -> isVGPR ( MRI , Def . getReg ( ) ) ) return WaitStatesNeeded ; unsigned Reg = Def . getReg ( ) ; auto IsHazardFn = [ this , Reg , TRI ] ( MachineInstr * MI ) { int DataIdx = createsVALUHazard ( * MI ) ;

return DataIdx >= <NUM_LIT> && TRI -> regsOverlap ( MI -> getOperand ( DataIdx ) . getReg ( ) , Reg ) ;


<s> inline int vec_any_numeric ( vector float a1 ) { return __builtin_altivec_vcmpeqfp_p ( __CR6_EQ_REV , a1 , a1 ) ;


<s> <STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeCondition ( CC ) ) ;


<s> getTargetStreamer ( ) . emitARM64WinCFIContext ( ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; auto SE = cast < MCSymbolRefExpr > ( getImm ( ) ) ; unsigned Imm = <NUM_LIT> ; for ( char c : SE -> getSymbol ( ) . getName ( ) ) { switch ( c ) { default : llvm_unreachable ( <STR_LIT> ) ; case 'i' : Imm |= <STR_LIT> ; break ; case 'o' : Imm |= <STR_LIT> ; break ; case 'r' : Imm |= <STR_LIT> ; break ; case 'w' : Imm |= <STR_LIT> ; break ; } } Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue SplitF64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = SplitF64 . getValue ( <NUM_LIT> ) ; SDValue Hi = SplitF64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; assert ( RegLo < <STR_LIT> && <STR_LIT> ) ; Register RegHi = RegLo + <NUM_LIT> ; if ( STI . isRegisterReservedByUser ( RegLo ) || STI . isRegisterReservedByUser ( RegHi ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; if ( STI . isRegisterReservedByUser ( VA . getLocReg ( ) ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Glue . getNode ( ) ) { RetOps . push_back ( Glue ) ; } const Function & Func = DAG . getMachineFunction ( ) . getFunction ( ) ; if ( Func . hasFnAttribute ( <STR_LIT> ) ) { if ( ! Func . getReturnType ( ) -> isVoidTy ( ) ) report_fatal_error ( <STR_LIT> ) ;

MachineFunction & MF = DAG . getMachineFunction ( ) ;


<s> <ISA_LIT>PerfHint :: MemAccessInfo <ISA_LIT>PerfHint :: makeMemAccessInfo ( Instruction * Inst ) const { MemAccessInfo MAI ;

const Value * MO = getMemoryInstrPtrAndType ( Inst ) . first ;


<s> <ISA_LIT>AddressSanitizer ( const MCSubtargetInfo * & STI ) : <ISA_LIT>AsmInstrumentation ( STI ) , RepPrefix ( false ) , OrigSPOffset ( <NUM_LIT> ) {


<s> void EmitConstant ( uint64_t Val , unsigned Size , raw_ostream & OS ) const { for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { EmitByte ( Val & <NUM_LIT> , OS ) ;


<s> TypeNo = TypeNo << <STR_LIT> ; if ( Ty . getTag ( ) == dwarf :: DW_TAG_structure_type ) TypeNo = TypeNo | <STR_LIT> ; else TypeNo = TypeNo | <STR_LIT> ; TagName = CTy . getName ( ) ; std :: string UniqueSuffix = <STR_LIT> + Ty -> getNameStr ( ) . substr ( <NUM_LIT> ) ; TagName += UniqueSuffix ; unsigned short size = CTy . getSizeInBits ( ) / <NUM_LIT> ;


<s> } } } SmallPtrSet < Instruction * , <NUM_LIT> > Dead ; while ( ! MaybeDead . empty ( ) ) { auto * I = MaybeDead . front ( ) ; MaybeDead . remove ( I ) ; if ( I -> hasNUsesOrMore ( <NUM_LIT> ) ) continue ; for ( auto & U : I -> operands ( ) ) if ( auto * OpI = dyn_cast < Instruction > ( U ) ) MaybeDead . insert ( OpI ) ; Dead . insert ( I ) ; } for ( auto * I : Dead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ;


<s> const uint32_t * <ISA_LIT>BaseRegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ;


<s> } else if ( BoundCtrl == - <NUM_LIT> ) {


<s> MachineInstr * <ISA_LIT>InstrInfo :: emitFrameIndexDebugValue ( MachineFunction & MF , int FrameIx , uint64_t Offset , const MDNode * MDPtr , DebugLoc DL ) const { <ISA_LIT>AddressMode AM ;


<s> default : Op = <STR_LIT> ( RegNo , RegKind , S , E ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; case <STR_LIT> : if ( name == <STR_LIT> ) Op = <STR_LIT> ( <STR_LIT> , S ) ; else Op = <STR_LIT> ( <STR_LIT> , S ) ; break ; } break ; } if ( match<ISA_LIT>AsmModifiers ( EVal , E ) ) { E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Op = <STR_LIT> ( EVal , S , E ) ; } break ; case AsmToken :: Minus : case AsmToken :: Integer : case AsmToken :: LParen : case AsmToken :: Dot : if ( ! getParser ( ) . parseExpression ( EVal , E ) ) Op = <STR_LIT> ( EVal , S , E ) ; break ; case AsmToken :: Identifier : { StringRef Identifier ; if ( ! getParser ( ) . parseIdentifier ( Identifier ) ) { E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; if ( isCall && getContext ( ) . getObjectFileInfo ( ) -> getRelocM ( ) == Reloc :: PIC_ ) Res = <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_WPLT30 , Res , getContext ( ) ) ; Op = <STR_LIT> ( Res , S , E ) ; }


<s> unsigned Register = <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . getRegister ( RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success ;


<s> Value * <ISA_LIT>IREmitter :: visitTLSBASEADDR ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> if ( Trace ) dbgs ( ) << <STR_LIT> << printMBBReference ( B ) << <STR_LIT> << MI ; assert ( MI . isBranch ( ) && <STR_LIT> ) ; InstrExec . insert ( & MI ) ; bool Eval = ME . evaluate ( MI , Map , BTs , FallsThrough ) ; if ( ! Eval ) { DefaultToAll = true ; FallsThrough = true ; if ( Trace ) dbgs ( ) << <STR_LIT> ; } else if ( ! DefaultToAll ) { if ( Trace ) { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> , n = BTs . size ( ) ; i < n ; ++ i ) dbgs ( ) << <STR_LIT> << printMBBReference ( * BTs [ i ] ) ; if ( FallsThrough ) dbgs ( ) << <STR_LIT> ; else dbgs ( ) << <STR_LIT> ; } Targets . insert ( BTs . begin ( ) , BTs . end ( ) ) ; } ++ It ; } while ( FallsThrough && It != End ) ; if ( ! DefaultToAll ) { for ( const MachineBasicBlock * SB : B . successors ( ) ) { if ( SB -> isEHPad ( ) ) Targets . insert ( SB ) ; } if ( FallsThrough ) { MachineFunction :: const_iterator BIt = B . getIterator ( ) ; MachineFunction :: const_iterator Next = std :: next ( BIt ) ; if ( Next != MF . end ( ) ) Targets . insert ( & * Next ) ; }


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveOptionRVC ( ) {


<s> if ( SubRegIdx != <STR_LIT> && SubRegIdx != <STR_LIT> ) continue ; SDValue Move = N -> getOperand ( <NUM_LIT> ) ; if ( ! Move . isMachineOpcode ( ) ) continue ; switch ( Move . getMachineOpcode ( ) ) { default : continue ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return <ISA_LIT>ATTInstPrinter :: getRegisterName ( Reg ) ;


<s> return __aarch64_vdupq_laneq_s64 ( __a , __b ) ;


<s> Args . push_back ( RegNode ) ; Instruction * InsertPt = EscapeCall ; if ( ! EscapeCall ) InsertPt = F . getEntryBlock ( ) . getTerminator ( ) ; IRBuilder < > Builder ( InsertPt ) ; Builder . CreateCall ( FrameEscape , Args ) ; if ( EscapeCall ) EscapeCall -> eraseFromParent ( ) ; return Args . size ( ) - <NUM_LIT> ;


<s> bool IsSrcConstant [ <NUM_LIT> ] = { getTargetConstantBitsFromNode ( V1 , EltSizeInBits , UndefSrcElts [ <NUM_LIT> ] , SrcEltBits [ <NUM_LIT> ] , true , false ) , getTargetConstantBitsFromNode ( V2 , EltSizeInBits , UndefSrcElts [ <NUM_LIT> ] , SrcEltBits [ <NUM_LIT> ] , true , false ) } ; for ( int i = <NUM_LIT> , Size = Mask . size ( ) ; i < Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; unsigned SrcIdx = M / Size ; SDValue V = M < Size ? V1 : V2 ; M %= Size ; if ( V . isUndef ( ) ) { Mask [ i ] = SM_SentinelUndef ; continue ; } if ( V . getOpcode ( ) == <STR_LIT> && ( Size % V . getValueType ( ) . getVectorNumElements ( ) ) == <NUM_LIT> ) { int Scale = Size / V . getValueType ( ) . getVectorNumElements ( ) ; int Idx = M / Scale ; if ( Idx != <NUM_LIT> && ! VT . isFloatingPoint ( ) ) Mask [ i ] = SM_SentinelUndef ; else if ( Idx == <NUM_LIT> && <STR_LIT> ( V . getOperand ( <NUM_LIT> ) ) ) Mask [ i ] = SM_SentinelZero ; continue ;


<s> BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <STR_LIT> :: ET_NULL ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addReg ( <STR_LIT> , RegState :: Undef ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ;

BuildMI ( MBB , I , DL , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ;


<s> } for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) Ops . push_back ( CLI . DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; const TargetRegisterInfo * TRI = getTargetMachine ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CLI . CallConv ) ; assert ( Mask && <STR_LIT> ) ; if ( Subtarget . in<ISA_LIT>16HardFloat ( ) ) { if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( CLI . Callee ) ) { llvm :: StringRef Sym = G -> getGlobal ( ) -> getName ( ) ; Function * F = G -> getGlobal ( ) -> getParent ( ) -> getFunction ( Sym ) ; if ( F && F -> hasFnAttribute ( <STR_LIT> ) ) { Mask = <ISA_LIT>RegisterInfo :: get<ISA_LIT>16RetHelperMask ( ) ; }


<s> addAlignedMemoryOperands ( Inst , N ) ;


<s> default : RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : RegLst = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; break ; } unsigned RegNum = RegLst & <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i <= RegNum ; i ++ ) Inst . addOperand ( MCOperand :: createReg ( Regs [ i ] ) ) ;

Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;


<s> else if ( saved_warn_return_type_count ) saved_warn_return_type_count = <NUM_LIT> ; } else { warning ( OPT_Wattributes , <STR_LIT> , IDENTIFIER_POINTER ( name ) ) ; * no_add_attrs = true ;


<s> auto_sbitmap to_clear_bitmap ( maxregno + <NUM_LIT> ) ; rtx r1_reg , result_rtl , clearing_reg = NULL_RTX ; tree result_type ; bitmap_clear ( to_clear_bitmap ) ; bitmap_set_range ( to_clear_bitmap , R0_REGNUM , NUM_ARG_REGS ) ; bitmap_set_bit ( to_clear_bitmap , IP_REGNUM ) ; if ( TARGET_HARD_FLOAT ) { int float_bits = D7_VFP_REGNUM - FIRST_VFP_REGNUM + <NUM_LIT> ; bitmap_set_range ( to_clear_bitmap , FIRST_VFP_REGNUM , float_bits ) ; emit_use ( gen_rtx_REG ( SImode , IP_REGNUM ) ) ; bitmap_clear_bit ( to_clear_bitmap , IP_REGNUM ) ; emit_use ( gen_rtx_REG ( SImode , <NUM_LIT> ) ) ; bitmap_clear_bit ( to_clear_bitmap , <NUM_LIT> ) ; } for ( regno = NUM_ARG_REGS ; regno <= maxregno ; regno ++ ) { if ( IN_RANGE ( regno , FIRST_VFP_REGNUM , D7_VFP_REGNUM ) ) continue ; if ( IN_RANGE ( regno , IP_REGNUM , PC_REGNUM ) ) continue ; if ( call_used_regs [ regno ] ) bitmap_set_bit ( to_clear_bitmap , regno ) ; } result_type = TREE_TYPE ( DECL_RESULT ( current_function_decl ) ) ; if ( ! VOID_TYPE_P ( result_type ) ) { uint64_t to_clear_return_mask ; result_rtl = arm_function_value ( result_type , current_function_decl , <NUM_LIT> ) ; gcc_assert ( REG_P ( result_rtl ) ) ; to_clear_return_mask = compute_not_to_clear_mask ( result_type , result_rtl , <NUM_LIT> , & padding_bits_to_clear ) ; if ( to_clear_return_mask ) { gcc_assert ( ( unsigned ) maxregno < sizeof ( long long ) * __CHAR_BIT__ ) ; for ( regno = R0_REGNUM ; regno <= maxregno ; regno ++ ) { if ( to_clear_return_mask & ( <NUM_LIT> << regno ) ) bitmap_clear_bit ( to_clear_bitmap , regno ) ; } } } if ( padding_bits_to_clear != <NUM_LIT> ) { int to_clear_bitmap_size = SBITMAP_SIZE ( ( sbitmap ) to_clear_bitmap ) ; auto_sbitmap to_clear_arg_regs_bitmap ( to_clear_bitmap_size ) ; bitmap_clear ( to_clear_arg_regs_bitmap ) ; bitmap_set_range ( to_clear_arg_regs_bitmap , R1_REGNUM , NUM_ARG_REGS - <NUM_LIT> ) ; gcc_assert ( bitmap_subset_p ( to_clear_arg_regs_bitmap , to_clear_bitmap ) ) ; } clearing_reg = gen_rtx_REG ( SImode , TARGET_THUMB1 ? R0_REGNUM : LR_REGNUM ) ;


<s> static SDValue getZeroVector ( EVT VT , SelectionDAG & DAG , SDLoc dl ) { assert ( VT . isVector ( ) && <STR_LIT> ) ; SDValue EncodedVal = DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; EVT VmovVT = VT . is128BitVector ( ) ? <STR_LIT> : <STR_LIT> ; SDValue Vmov = DAG . getNode ( <STR_LIT> , dl , VmovVT , EncodedVal ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vmov ) ;


<s> break ; case 'n' : case 'w' : Size = ( Suffix == 'n' ? <NUM_LIT> : <NUM_LIT> ) ; assert ( IsThumb ) ; EmitThumbMappingSymbol ( ) ; for ( unsigned II = <NUM_LIT> , IE = Size ; II != IE ; II = II + <NUM_LIT> ) { const unsigned I0 = LittleEndian ? II + <NUM_LIT> : II + <NUM_LIT> ; const unsigned I1 = LittleEndian ? II + <NUM_LIT> : II + <NUM_LIT> ; Buffer [ Size - II - <NUM_LIT> ] = uint8_t ( Inst >> I0 * CHAR_BIT ) ; Buffer [ Size - II - <NUM_LIT> ] = uint8_t ( Inst >> I1 * CHAR_BIT ) ; }


<s> machine_mode mode = GET_MODE ( x ) ;

return VOIDmode == mode ? x : simplify_gen_subreg ( int_mode_for_mode ( mode ) . require ( ) , x , mode , <NUM_LIT> ) ;


<s> EVT NewVT = getExtensionTo64Bits ( OrigTy ) ;

return DAG . getNode ( ExtOpcode , N -> getDebugLoc ( ) , NewVT , N ) ;


<s> int regno ; int reglimit = STACK_POINTER_REGNUM ; int lastreg = - <NUM_LIT> ; if ( ! reload_completed || frame_pointer_needed || get_frame_size ( ) != <NUM_LIT> || current_function_pretend_args_size || current_function_args_size || current_function_outgoing_args_size || current_function_calls_eh_return || ! TARGET_PROLOGUE_EPILOGUE ) return <NUM_LIT> ; for ( regno = <NUM_LIT> ; regno < reglimit ; regno ++ ) if ( ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) || ( regno == ( int ) PIC_OFFSET_TABLE_REGNUM && ( current_function_uses_pic_offset_table || ( flag_pic && regs_ever_live [ regno + <NUM_LIT> ] && ! call_used_regs [ regno + <NUM_LIT> ] ) ) ) ) { if ( lastreg != regno - <NUM_LIT> ) return <NUM_LIT> ; lastreg = regno ; } return <NUM_LIT> ;


<s> int Opcode = MI . getOpcode ( ) ; if ( ( Opcode != <STR_LIT> ) && ( Opcode != <STR_LIT> ) ) { return ; } if ( DstReg != MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) { return ; } switch ( Opcode ) { case <STR_LIT> : Offset += - MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> :

Offset += MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> if ( M == - <NUM_LIT> ) continue ; MinSrc = ( MinSrc == - <NUM_LIT> ) ? M : std :: min ( MinSrc , M ) ; MaxSrc = ( MaxSrc == - <NUM_LIT> ) ? M : std :: max ( MaxSrc , M ) ;


<s> if ( VT . getSimpleVT ( ) . isVector ( ) ) { if ( Subtarget . hasVSX ( ) ) {

if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ;


<s> return ; } case <STR_LIT> : { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( IID == <STR_LIT> ) { SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc SL ( N ) ; SDValue Cvt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src0 , Src1 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cvt ) ) ; return ; } break ; } case <STR_LIT> : { SDValue Chain ; if ( SDValue Res = lowerIntrinsicWChain_IllegalReturnType ( SDValue ( N , <NUM_LIT> ) , Chain , DAG ) ) { Results . push_back ( Res ) ; Results . push_back ( Chain ) ; return ; } break ; } case <STR_LIT> : { SDLoc SL ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; EVT NewVT = getEquivalentMemType ( * DAG . getContext ( ) , VT ) ;

SDValue LHS = DAG . getNode ( <STR_LIT> , SL , NewVT , N -> getOperand ( <NUM_LIT> ) ) ;


cum -> words += ( arg_size + ( ( cum -> words & <NUM_LIT> ) && type != NULL_TREE && arg_size > <NUM_LIT> ) ) ;


<s> void <ISA_LIT>InstPrinter :: printS8ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) {

printSImmOperand < <NUM_LIT> > ( MI , OpNum , O ) ;


<s> Tokens . emplace_back ( Lexer . getTok ( ) ) ; Lex ( ) ; switch ( Tokens . back ( ) . getKind ( ) ) { case AsmToken :: TokenKind :: Hash : if ( Tokens . size ( ) > <NUM_LIT> ) if ( ( Tokens . end ( ) - <NUM_LIT> ) -> getKind ( ) == AsmToken :: TokenKind :: Plus ) { Tokens . insert ( Tokens . end ( ) - <NUM_LIT> , AsmToken ( AsmToken :: TokenKind :: Comma , Comma ) ) ; Done = true ; } break ;


<s> } } ; std :: vector < CalleeSavedInfo > Spills ; Spills . push_back ( CalleeSavedInfo ( Regs . getAddressOfCalleeRegister ( ) ) ) ; if ( hasFP ( MF ) || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) Spills . push_back ( CalleeSavedInfo ( RegSP ) ) ; ProcessCSI ( CSI ) ; MFI -> setRestoreGPRRegs ( LowGPR , HighGPR , LowOffset ) ; ProcessCSI ( Spills ) ; MFI -> setSpillGPRRegs ( LowGPR , HighGPR , LowOffset ) ; for ( auto & CS : CSI ) { if ( CS . getFrameIdx ( ) != INT32_MAX ) continue ; unsigned Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ;

Align Alignment = TRI -> getSpillAlign ( * RC ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> void mips_final_prescan_insn ( rtx_insn * insn , rtx * opvec , int noperands ) { if ( INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) == UNSPEC_VOLATILE && XINT ( PATTERN ( insn ) , <NUM_LIT> ) == UNSPEC_CONSTTABLE ) mips_set_text_contents_type ( asm_out_file , <STR_LIT> , INTVAL ( XVECEXP ( PATTERN ( insn ) , <NUM_LIT> , <NUM_LIT> ) ) , FALSE ) ; if ( mips_need_noat_wrapper_p ( insn , opvec , noperands ) ) mips_push_asm_switch ( & mips_noat ) ;


<s> } else return ; <STR_LIT> ExtType = ( C . ICmpType == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( C . Op0 . getValueType ( ) != <STR_LIT> || Load -> getExtensionType ( ) != ExtType ) { C . Op0 = DAG . getExtLoad ( ExtType , SDLoc ( Load ) , <STR_LIT> , Load -> getChain ( ) , Load -> getBasePtr ( ) , Load -> getPointerInfo ( ) , Load -> getMemoryVT ( ) , Load -> getAlignment ( ) , Load -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Load , <NUM_LIT> ) , C . Op0 . getValue ( <NUM_LIT> ) ) ; } if ( C . Op1 . getValueType ( ) != <STR_LIT> || Value != ConstOp1 -> getZExtValue ( ) ) C . Op1 = DAG . getConstant ( Value , DL , <STR_LIT> ) ;


<s> signedDecoder < <NUM_LIT> > ( MI , tmp , Decoder ) ;


<s> for ( i = <NUM_LIT> ; i < num_elements ; i ++ ) { bool invert = opts [ i ] . invert ; const char * name = opts [ i ] . name ; const char * no_str = <STR_LIT> ; HOST_WIDE_INT mask = opts [ i ] . mask ; size_t len = comma_len + prefix_len + strlen ( name ) ; if ( ! invert ) { if ( ( flags & mask ) == <NUM_LIT> ) { no_str = <STR_LIT> ; len += sizeof ( <STR_LIT> ) - <NUM_LIT> ; } flags &= ~ mask ; }


<s> isThumb2 = AFI -> isThumb2Function ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) {


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : GlobalBaseReg ( <NUM_LIT> ) , GlobalRetAddr ( <NUM_LIT> ) {


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > registered_target ( getThe<ISA_LIT>Target ( ) ) ;


<s> unsigned int b = __B ; return ( ( __m64 ) a * ( __m64 ) b ) ;


<s> if ( Denominator . getValueType ( ) != <STR_LIT> ) report_fatal_error ( <STR_LIT> ) ; SDValue Div = SDValue ( DAG . getMachineNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Denominator ) , <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , <STR_LIT> , Div ) ;


<s> int getIntImmCost ( <STR_LIT> IID , unsigned Idx , const APInt & Imm , Type * Ty ) {


<s> addPass ( create<ISA_LIT>IssueVZeroUpperPass ( ) ) ; ShouldPrint = true ; } if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . padShortFunctions ( ) ) { addPass ( create<ISA_LIT>PadShortFunctions ( ) ) ; ShouldPrint = true ; }

if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>Subtarget ( ) . LEAusesAG ( ) ) {


<s> std :: vector < std :: string > modr_edmod ( ArpRn2 a , ArpStep2 asi , ArpStep2 asj ) {

return D ( <STR_LIT> , MemARPSI ( a , asi ) , MemARPSJ ( a , asj ) , <STR_LIT> ) ;


<s> else if ( Subtarget -> isTargetDarwin ( ) ) return LowerDarwin_VASTART ( Op , DAG ) ; else return LowerAAPCS_VASTART ( Op , DAG ) ;


<s> SDValue VQ = compressHvxPred ( Val , dl , WordTy , DAG ) ; unsigned BitWidth = ResTy . getSizeInBits ( ) ; if ( BitWidth < <NUM_LIT> ) { SDValue W0 = extractHvxElementReg ( VQ , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) , dl , <STR_LIT> , DAG ) ; if ( BitWidth == <NUM_LIT> ) return W0 ; assert ( BitWidth < <NUM_LIT> ) ; return DAG . getZExtOrTrunc ( W0 , dl , ResTy ) ; } assert ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Words ; for ( unsigned i = <NUM_LIT> ; i != BitWidth / <NUM_LIT> ; ++ i ) { SDValue W = extractHvxElementReg ( VQ , DAG . getConstant ( i , dl , <STR_LIT> ) , dl , <STR_LIT> , DAG ) ; Words . push_back ( W ) ; } SmallVector < SDValue , <NUM_LIT> > Combines ; assert ( Words . size ( ) % <NUM_LIT> == <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Words . size ( ) ; i < e ; i += <NUM_LIT> ) { SDValue C = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { Words [ i + <NUM_LIT> ] , Words [ i ] } ) ; Combines . push_back ( C ) ; } if ( BitWidth == <NUM_LIT> ) return Combines [ <NUM_LIT> ] ; return DAG . getNode ( <STR_LIT> , dl , ResTy , Combines ) ; } if ( isHvxBoolTy ( ResTy ) && ValTy . isScalarInteger ( ) ) { unsigned BitWidth = ValTy . getSizeInBits ( ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; assert ( BitWidth == HwLen ) ; MVT ValAsVecTy = <STR_LIT> ( <STR_LIT> , BitWidth / <NUM_LIT> ) ; SDValue ValAsVec = DAG . getBitcast ( ValAsVecTy , Val ) ; SmallVector < SDValue , <NUM_LIT> > Bytes ; SmallVector < SDValue , <NUM_LIT> > Tmp ; for ( unsigned I = <NUM_LIT> ; I != HwLen / <NUM_LIT> ; ++ I ) { SDValue Idx = DAG . getConstant ( I , dl , <STR_LIT> ) ; SDValue Byte = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValAsVec , Idx ) ; for ( unsigned J = <NUM_LIT> ; J != <NUM_LIT> ; ++ J ) {


<s> CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ case <STR_LIT> ## n : \ return HasSVE ? <STR_LIT> ## n : <STR_LIT> ## n CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ; CASE ( <NUM_LIT> ) ;


<s> BlockWaitcntBrackets * ScoreBrackets = BlockWaitcntBracketsMap [ & Block ] . get ( ) ; DEBUG ( { dbgs ( ) << <STR_LIT> << Block . getNumber ( ) ;


<s> CUMULATIVE_ARGS next_cum ; next_cum = * get_cumulative_args ( args_so_far ) ; arc_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , true ) ; first_anon_arg = next_cum ; if ( FUNCTION_ARG_REGNO_P ( first_anon_arg ) ) { int first_reg_offset = first_anon_arg ; if ( ! no_rtl ) { rtx regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( <NUM_LIT> ) ) ) ; move_block_from_reg ( first_reg_offset , regblock , MAX_ARC_PARM_REGS - first_reg_offset ) ; } * pretend_size = ( ( MAX_ARC_PARM_REGS - first_reg_offset ) * UNITS_PER_WORD ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx , bool IsBigEndian ) : MCDisassembler ( STI , Ctx ) , IsMicro<ISA_LIT> ( STI . getFeatureBits ( ) & <STR_LIT> ) , IsBigEndian ( IsBigEndian ) {


<s> Chain = Res . getValue ( <NUM_LIT> ) ; } else { Res = DAG . getNode ( Op . getOpcode ( ) , DL , WideVT , Src ) ; } Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; if ( IsStrict ) return DAG . getMergeValues ( { Res , Chain } , DL ) ; return Res ; } bool IsSigned = Op -> getOpcode ( ) == <STR_LIT> || Op -> getOpcode ( ) == <STR_LIT> ; if ( VT != <STR_LIT> || IsSigned ) return SDValue ( ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SDValue Sign = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , One ) , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , One ) ) ; SDValue IsNeg = DAG . getSetCC ( DL , <STR_LIT> , Src , Zero , <STR_LIT> ) ; SDValue SignSrc = DAG . getSelect ( DL , <STR_LIT> , IsNeg , Sign , Src ) ; SmallVector < SDValue , <NUM_LIT> > SignCvts ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Chains ( <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) {

SDValue Elt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SignSrc , DAG . getIntPtrConstant ( i , DL ) ) ;


<s> for ( StringSet < > :: iterator i = DLLExportedGVs . begin ( ) , e = DLLExportedGVs . end ( ) ; i != e ; ++ i ) O << <STR_LIT> << i -> getKeyData ( ) << <STR_LIT> ; for ( StringSet < > :: iterator i = DLLExportedFns . begin ( ) , e = DLLExportedFns . end ( ) ; i != e ; ++ i ) O << <STR_LIT> << i -> getKeyData ( ) << <STR_LIT> ; O << <STR_LIT> ; } bool Result = AsmPrinter :: doFinalization ( M ) ; O << <STR_LIT> ; return Result ;


<s> static int round_frame_size ( int size ) {

return ( ( size + STACK_BOUNDARY / BITS_PER_UNIT - <NUM_LIT> ) & - STACK_BOUNDARY / BITS_PER_UNIT ) ;


<s> InstrT * branchInstr = CFGTraits :: getNormalBlockBranchInstr ( curBlk ) ; if ( branchInstr == NULL ) { return <NUM_LIT> ; } assert ( CFGTraits :: isCondBranch ( branchInstr ) ) ; BlockT * trueBlk = CFGTraits :: getTrueBranch ( branchInstr ) ; BlockT * falseBlk = CFGTraits :: getFalseBranch ( curBlk , branchInstr ) ; BlockT * landBlk ; int cloned = <NUM_LIT> ; if ( trueBlk -> succ_size ( ) == <NUM_LIT> && falseBlk -> succ_size ( ) == <NUM_LIT> && * trueBlk -> succ_begin ( ) == * falseBlk -> succ_begin ( ) ) { landBlk = * trueBlk -> succ_begin ( ) ; } else if ( trueBlk -> succ_size ( ) == <NUM_LIT> && falseBlk -> succ_size ( ) == <NUM_LIT> ) { landBlk = NULL ; } else if ( trueBlk -> succ_size ( ) == <NUM_LIT> && * trueBlk -> succ_begin ( ) == falseBlk ) { landBlk = falseBlk ; falseBlk = NULL ; } else if ( falseBlk -> succ_size ( ) == <NUM_LIT> && * falseBlk -> succ_begin ( ) == trueBlk ) { landBlk = trueBlk ; trueBlk = NULL ; } else if ( falseBlk -> succ_size ( ) == <NUM_LIT> && isSameloopDetachedContbreak ( trueBlk , falseBlk ) ) { landBlk = * falseBlk -> succ_begin ( ) ; } else if ( trueBlk -> succ_size ( ) == <NUM_LIT> && isSameloopDetachedContbreak ( falseBlk , trueBlk ) ) { landBlk = * trueBlk -> succ_begin ( ) ; } else { return handleJumpintoIf ( curBlk , trueBlk , falseBlk ) ; } if ( landBlk != NULL && ( ( trueBlk && trueBlk -> pred_size ( ) > <NUM_LIT> ) || ( falseBlk && falseBlk -> pred_size ( ) > <NUM_LIT> ) ) ) { cloned += improveSimpleJumpintoIf ( curBlk , trueBlk , falseBlk , & landBlk ) ; } if ( trueBlk && trueBlk -> pred_size ( ) > <NUM_LIT> ) { trueBlk = cloneBlockForPredecessor ( trueBlk , curBlk ) ; ++ cloned ; } if ( falseBlk && falseBlk -> pred_size ( ) > <NUM_LIT> ) { falseBlk = cloneBlockForPredecessor ( falseBlk , curBlk ) ; ++ cloned ; } mergeIfthenelseBlock ( branchInstr , curBlk , trueBlk , falseBlk , landBlk ) ; ++ numIfPatternMatch ; numClonedBlock += cloned ;


<s> SMLoc End ; const MCExpr * Expr ; if ( getParser ( ) . parseExpression ( Expr , End ) ) { return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: createImm ( Expr , Start , End ) ) ; return MatchOperand_Success ;


<s> const char * const * xtensa_get_config_strings ( void ) {

static const char * const * config_strings ;


<s> break ; case GR8_REGS : case GR9_REGS : case GR89_REGS : case FDPIC_FPTR_REGS : case FDPIC_REGS : case ICC_REGS : case FCC_REGS : case CC_REGS : case ICR_REGS : case FCR_REGS : case CR_REGS : case LCR_REG : case LR_REG : case SPR_REGS : case QUAD_ACC_REGS : case ACCG_REGS :


<s> ReduceEntryFunArgs ( MachineInstr * argMI , const ReduceEntry & argEntry , MachineBasicBlock :: instr_iterator & argNextMII ) : MI ( argMI ) , Entry ( argEntry ) , NextMII ( argNextMII ) {


<s> bool disablePostRAScheduler ( ) const {


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> const SDValue * Root = & Base ; if ( Base . getOpcode ( ) == <STR_LIT> && Base . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Base . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( CN && ( CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Root = & Base . getOperand ( <NUM_LIT> ) ; } } if ( isa < FrameIndexSDNode > ( * Root ) ) {


<s> static SDValue Widen ( SelectionDAG * CurDAG , SDValue N ) { SDLoc dl ( N ) ; SDValue SubReg = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue ImpDef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , <STR_LIT> ) , <NUM_LIT> ) ; MachineSDNode * Node = CurDAG -> getMachineNode ( TargetOpcode :: INSERT_SUBREG , dl , <STR_LIT> , ImpDef , N , SubReg ) ;


unsigned NumEltsIdx = Log2_32 ( NumElts / <NUM_LIT> ) ;


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveUnreq ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveFnEnd ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCantUnwind ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePersonality ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveHandlerData ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveSetFP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePad ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveRegSave ( DirectiveID . getLoc ( ) , false ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveRegSave ( DirectiveID . getLoc ( ) , true ) ; else if ( IDVal == <STR_LIT> || IDVal == <STR_LIT> ) parseDirectiveLtorg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectivePersonalityIndex ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveUnwindRaw ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveMovSP ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveArchExtension ( DirectiveID . getLoc ( ) ) ;

else if ( IDVal == <STR_LIT> ) return parseDirectiveAlign ( DirectiveID . getLoc ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isSolo ( const MachineInstr & MI ) const { const uint64_t F = MI . getDesc ( ) . TSFlags ;


<s> const Instruction & PrevInst = * PrevIR . getInstruction ( ) ; const unsigned PrevInstIndex = PrevIR . getSourceIndex ( ) % SrcMgr . size ( ) ; const WaitCntInfo & PrevInstWaitInfo = InstrWaitCntInfo [ PrevInstIndex ] ; const int CyclesLeft = PrevInst . getCyclesLeft ( ) ; assert ( CyclesLeft != UNKNOWN_CYCLES && <STR_LIT> ) ; if ( PrevInstWaitInfo . VmCnt ) { CurrVmcnt ++ ; if ( ( unsigned ) CyclesLeft < CyclesToWaitVm ) CyclesToWaitVm = CyclesLeft ; } if ( PrevInstWaitInfo . ExpCnt ) { CurrExpcnt ++ ; if ( ( unsigned ) CyclesLeft < CyclesToWaitExp ) CyclesToWaitExp = CyclesLeft ; } if ( PrevInstWaitInfo . LgkmCnt ) { CurrLgkmcnt ++ ; if ( ( unsigned ) CyclesLeft < CyclesToWaitLgkm ) CyclesToWaitLgkm = CyclesLeft ; } if ( PrevInstWaitInfo . VsCnt ) { CurrVscnt ++ ; if ( ( unsigned ) CyclesLeft < CyclesToWaitVs ) CyclesToWaitVs = CyclesLeft ; } } unsigned CyclesToWait = ~ <NUM_LIT> ; if ( CurrVmcnt > Vmcnt && CyclesToWaitVm < CyclesToWait ) CyclesToWait = CyclesToWaitVm ; if ( CurrExpcnt > Expcnt && CyclesToWaitExp < CyclesToWait ) CyclesToWait = CyclesToWaitExp ; if ( CurrLgkmcnt > Lgkmcnt && CyclesToWaitLgkm < CyclesToWait ) CyclesToWait = CyclesToWaitLgkm ; if ( CurrVscnt > Vscnt && CyclesToWaitVs < CyclesToWait ) CyclesToWait = CyclesToWaitVs ; if ( CyclesToWait == ~ <NUM_LIT> ) return <NUM_LIT> ; return CyclesToWait ;


<s> return R . InsertAcc ( V ) ; case Instruction :: Add : { R . InsertAdd ( I ) ; Value * LHS = I -> getOperand ( <NUM_LIT> ) ; Value * RHS = I -> getOperand ( <NUM_LIT> ) ; bool ValidLHS = Search ( LHS , BB , R ) ; bool ValidRHS = Search ( RHS , BB , R ) ; if ( ValidLHS && ValidRHS ) return true ; return R . InsertAcc ( I ) ; } case Instruction :: Mul : { Value * MulOp0 = I -> getOperand ( <NUM_LIT> ) ; Value * MulOp1 = I -> getOperand ( <NUM_LIT> ) ;

return IsNarrowSequence < <NUM_LIT> > ( MulOp0 ) && IsNarrowSequence < <NUM_LIT> > ( MulOp1 ) ;


<s> vtrn_s16 ( int16x4_t a , int16x4_t b ) {

return ( int16x4x2_t ) { vtrn1_s16 ( a , b ) , vtrn2_s16 ( a , b ) } ;


<s> if ( ! isSequentialOrUndefInRange ( Mask , <NUM_LIT> , Split , TruncatedVectorStart , Delta ) ) return false ; if ( isAnyInRange ( Mask . slice ( Split , Size - Split ) , TruncatedVectorStart , TruncatedVectorStart + Size ) ) return false ; return true ;


<s> const uint8_t * P ; bool DecodePred ; } ; const DecodeTable Tables [ ] = { { DecoderTableVFP32 , false } , { DecoderTableVFPV832 , false } , { DecoderTableNEONData32 , true } , { DecoderTableNEONLoadStore32 , true } , { DecoderTableNEONDup32 , true } , { DecoderTablev8NEON32 , false } , { DecoderTablev8Crypto32 , false } , } ; for ( auto Table : Tables ) { Result = decodeInstruction ( Table . P , MI , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; if ( Table . DecodePred && ! DecodePredicateOperand ( MI , <NUM_LIT> , Address , this ) ) return MCDisassembler :: Fail ; return Result ; }


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI , bool IsILP32 ) { return std :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI , IsILP32 ) ;


<s> auto * GAN = cast < GlobalAddressSDNode > ( Op ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; auto * GV = GAN -> getGlobal ( ) ; int64_t Offset = GAN -> getOffset ( ) ; auto & HLOF = * HTM . getObjFileLowering ( ) ; Reloc :: Model RM = HTM . getRelocationModel ( ) ; if ( RM == Reloc :: Static ) { SDValue GA = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset ) ; const GlobalObject * GO = GV -> getAliaseeObject ( ) ; if ( GO && Subtarget . useSmallData ( ) && HLOF . isGlobalInSmallSection ( GO , HTM ) ) return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , GA ) ;


<s> } else save_regs_base = sp_offset = <NUM_LIT> ; if ( crtl -> limit_stack ) nios2_emit_stack_limit_check ( ) ; save_offset = save_regs_base + cfun -> machine -> save_reg_size ; for ( regno = LAST_GP_REG ; regno > <NUM_LIT> ; regno -- ) if ( cfun -> machine -> save_mask & ( <NUM_LIT> << regno ) ) { save_offset -= <NUM_LIT> ; save_reg ( regno , save_offset ) ; } if ( frame_pointer_needed ) { int fp_save_offset = save_regs_base + cfun -> machine -> fp_save_offset ; insn = emit_insn ( gen_add3_insn ( hard_frame_pointer_rtx , stack_pointer_rtx , gen_int_mode ( fp_save_offset , Pmode ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } if ( sp_offset ) {

rtx sp_adjust = gen_rtx_SET ( VOIDmode , stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , sp_offset ) ) ;


<s> SDValue Idx = Op . getOperand ( <NUM_LIT> ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT EltVT = Op . getValueType ( ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; if ( VecVT . getVectorElementType ( ) == <STR_LIT> ) { MVT WideVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; return DAG . getNode ( <STR_LIT> , DL , EltVT , Vec , Idx ) ;


<s> <ISA_LIT>AsmParser ( MCSubtargetInfo & sti , MCAsmParser & parser , const MCInstrInfo & MII ) : MCTargetAsmParser ( ) , STI ( sti ) , Parser ( parser ) { MCAsmParserExtension :: Initialize ( Parser ) ;

setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> unsigned Count = <NUM_LIT> ; do { -- MBBI ; MachineInstr & MI = * MBBI ; if ( ! MI . isDebugValue ( ) ) ++ Count ; if ( MI . mayStore ( ) && isMatchingStore ( LoadMI , MI ) && BaseReg == getLdStBaseOp ( MI ) . getReg ( ) && isLdOffsetInRangeOfSt ( LoadMI , MI , TII ) && ! ModifiedRegs [ getLdStRegOp ( MI ) . getReg ( ) ] ) { StoreI = MBBI ; return true ; } if ( MI . isCall ( ) ) return false ; trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( ModifiedRegs [ BaseReg ] ) return false ;

if ( MI . mayStore ( ) && mayAlias ( LoadMI , MI , TII ) ) return false ;


<s> Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setLibCallee ( CallingConv :: C , PtrTy , TlsGetAddr , std :: move ( Args ) ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue Ret = CallResult . first ; if ( model != TLSModel :: LocalDynamic ) return Ret ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; SDValue Add = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Ret ) ; return DAG . getNode ( <STR_LIT> , DL , PtrVT , Add , Lo ) ; } SDValue Offset ; if ( model == TLSModel :: InitialExec ) { SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; TGA = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; Offset = DAG . getLoad ( PtrVT , DL , DAG . getEntryNode ( ) , TGA , MachinePointerInfo ( ) ) ; } else { assert ( model == TLSModel :: LocalExec ) ; SDValue TGAHi = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue TGALo = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGAHi ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TGALo ) ; Offset = DAG . getNode ( <STR_LIT> , DL , PtrVT , Hi , Lo ) ; }

SDValue ThreadPointer = DAG . getNode ( <STR_LIT> , DL , PtrVT ) ;


<s> const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; } return ; } if ( isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src1 ) ) return ; if ( Opc == <STR_LIT> && Src1 . isReg ( ) && RI . isVGPR ( MRI , Src1 . getReg ( ) ) ) { unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; return ; } if ( HasImplicitSGPR || ! MI . isCommutable ( ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; if ( ( ! Src1 . isImm ( ) && ! Src1 . isReg ( ) ) || ! isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src0 ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int CommutedOpc = commuteOpcode ( MI ) ; if ( CommutedOpc == - <NUM_LIT> ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ;


<s> mSTM = mTM -> getSubtargetImpl ( ) ;


<s> bool hasCn<ISA_LIT> ( ) const { return STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> void SwitchMode ( unsigned mode ) { MCSubtargetInfo & STI = copySTI ( ) ; FeatureBitset AllModes ( { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) ; FeatureBitset OldMode = STI . getFeatureBits ( ) & AllModes ; FeatureBitset FB = ComputeAvailableFeatures ( STI . ToggleFeature ( OldMode . flip ( mode ) ) ) ; setAvailableFeatures ( FB ) ; assert ( FeatureBitset ( { mode } ) == ( STI . getFeatureBits ( ) & AllModes ) ) ;


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) { RegisterMCAsmInfoFn X ( The<ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ;

TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: glueCopyToM0LD<ISA_LIT>nit ( SDNode * N ) const { unsigned AS = cast < MemSDNode > ( N ) -> getAddressSpace ( ) ; if ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS ) { if ( Subtarget -> ldsRequiresM0Init ( ) ) return glueCopyToM0 ( N , CurDAG -> getTargetConstant ( - <NUM_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; } else if ( AS == <ISA_LIT>AS :: REGION_ADDRESS ) { MachineFunction & MF = CurDAG -> getMachineFunction ( ) ; unsigned Value = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getGDSSize ( ) ; return glueCopyToM0 ( N , CurDAG -> getTargetConstant ( Value , SDLoc ( N ) , <STR_LIT> ) ) ; }


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( ID ) {


<s> unsigned Dst = MRI . createVirtualRegister ( RC ) ; MachineInstr * Lo = BuildMI ( * MBB , MI , DL , get ( AMDGPU :: S_MOV_B32 ) , LoDst ) . addImm ( Op . getImm ( ) & <NUM_LIT> ) ;

MachineInstr * Hi = BuildMI ( * MBB , MI , DL , get ( AMDGPU :: S_MOV_B32 ) , HiDst ) . addImm ( Op . getImm ( ) >> <NUM_LIT> ) ;


<s> <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList2 , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT . getSimpleVT ( ) , Reg , LocVT . getSimpleVT ( ) , LocInfo ) ) ; return false ; } } } const Type * ArgTy = LocVT . getTypeForEVT ( State . getContext ( ) ) ; unsigned Alignment = State . getTarget ( ) . getSubtargetImpl ( ) -> getDataLayout ( ) -> getABITypeAlignment ( ArgTy ) ; unsigned Size = State . getTarget ( ) . getSubtargetImpl ( ) -> getDataLayout ( ) -> getTypeSizeInBits ( ArgTy ) / <NUM_LIT> ; if ( ArgFlags . isByVal ( ) ) { Size = ByValSize ; Alignment = <NUM_LIT> ;


<s> case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; is_cpu_z9_109 = <NUM_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : case <NUM_LIT> : cpu = <STR_LIT> ; break ; case <NUM_LIT> : cpu = <STR_LIT> ; break ; default : cpu = <STR_LIT> ; break ; } } if ( has_features == <NUM_LIT> && strncmp ( buf , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { const char * p ; p = strchr ( buf , ':' ) ; if ( p == NULL ) continue ; p ++ ; while ( * p != <NUM_LIT> ) { int i ; while ( ISSPACE ( * p ) ) p ++ ; for ( i = <NUM_LIT> ; ! ISSPACE ( p [ i ] ) && p [ i ] != <NUM_LIT> ; i ++ ) ; if ( i == <NUM_LIT> && strncmp ( p , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) has_dfp = <NUM_LIT> ; else if ( i == <NUM_LIT> && strncmp ( p , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) has_te = <NUM_LIT> ; else if ( i == <NUM_LIT> && strncmp ( p , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) has_vx = <NUM_LIT> ; else if ( i == <NUM_LIT> && strncmp ( p , <STR_LIT> , <NUM_LIT> ) == <NUM_LIT> ) has_highgprs = <NUM_LIT> ; p += i ; } has_features = <NUM_LIT> ; } } fclose ( f ) ; if ( cpu == NULL ) return NULL ; if ( arch ) { const char * opt_htm = <STR_LIT> ;


<s> if ( ! MI1 . hasOneMemOperand ( ) || ! MI2 . hasOneMemOperand ( ) ) return false ; auto MO1 = * MI1 . memoperands_begin ( ) ; auto MO2 = * MI2 . memoperands_begin ( ) ; if ( MO1 -> getAddrSpace ( ) != MO2 -> getAddrSpace ( ) ) return false ; auto Base1 = MO1 -> getValue ( ) ; auto Base2 = MO2 -> getValue ( ) ; if ( ! Base1 || ! Base2 ) return false ;

const MachineFunction & MF = * MI1 . getParent ( ) -> getParent ( ) ;


<s> return ( int16x4_t ) __builtin_neon_vclsv4hi ( __a ) ;


<s> const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue TgtBA = DAG . getBlockAddress ( BA , PtrVT , true ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , PtrVT , TgtBA , Zero ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , PtrVT , TgtBA , Zero ) ; const TargetMachine & TM = DAG . getTarget ( ) ;

if ( TM . getRelocationModel ( ) == Reloc :: Static || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isDarwin ( ) ) {


<s> MCSymbol * DoCopyData = Context . getOrCreateSymbol ( <STR_LIT> ) ; MCSymbol * DoClearBss = Context . getOrCreateSymbol ( <STR_LIT> ) ; OS . emitRawComment ( <STR_LIT> ) ; OS . emitRawComment ( <STR_LIT> ) ;

OS . EmitSymbolAttribute ( DoCopyData , MCSA_Global ) ;


<s> bool useSoftFpu ( ) const { return UseSoftFpu ;


<s> std :: pair < unsigned , MVT > LT = TLI -> getTypeLegalizationCost ( ValTy ) ; MVT MTy = LT . second ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry < <STR_LIT> > SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ;