<s> break ; case <STR_LIT> : case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : if ( ( Value & <NUM_LIT> ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; } Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; }


<s> <ISA_LIT>AsmPrinter :: <ISA_LIT>AsmPrinter ( llvm :: TargetMachine & TM , std :: unique_ptr < llvm :: MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MCInstLowering ( OutContext , * this ) {


<s> bool <ISA_LIT>DAGToDAGISel :: SelectMUBUFOffset ( SDValue Addr , SDValue & SRsrc , SDValue & Soffset , SDValue & Offset , SDValue & SLC ) const { SDValue GLC , TFE ;

return SelectMUBUFOffset ( Addr , SRsrc , Soffset , Offset , GLC , SLC , TFE ) ;


<s> __o = __builtin_aarch64_ld4v2si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o , <NUM_LIT> ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __blci_u32 ( unsigned int __X ) {


<s> PHILinearizeDestIterator ( PHILinearize :: PHIInfoT :: iterator I ) : Iter ( I ) {


<s> vld4q_u64 ( const uint64_t * __a ) { uint64x2x4_t ret ; __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_ld4v2di ( ( const __builtin_aarch64_simd_di * ) __a ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( uint64x2_t ) __builtin_aarch64_get_qregxiv2di ( __o , <NUM_LIT> ) ;


<s> assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Read2Desc = TII -> get ( Opc ) ; const TargetRegisterClass * SuperRC = ( EltSize == <NUM_LIT> ) ? & AMDGPU :: VReg_64RegClass : & AMDGPU :: VReg_128RegClass ; unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; DebugLoc DL = I -> getDebugLoc ( ) ; MachineInstrBuilder Read2 = BuildMI ( * MBB , I , DL , Read2Desc , DestReg ) . addImm ( <NUM_LIT> ) . addOperand ( * AddrReg ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addMemOperand ( * I -> memoperands_begin ( ) ) . addMemOperand ( * Paired -> memoperands_begin ( ) ) ; LIS -> InsertMachineInstrInMaps ( Read2 ) ; unsigned SubRegIdx0 = ( EltSize == <NUM_LIT> ) ? AMDGPU :: sub0 : AMDGPU :: sub0_sub1 ; unsigned SubRegIdx1 = ( EltSize == <NUM_LIT> ) ? AMDGPU :: sub1 : AMDGPU :: sub2_sub3 ; updateRegDefsUses ( DestReg0 , DestReg , SubRegIdx0 ) ; updateRegDefsUses ( DestReg1 , DestReg , SubRegIdx1 ) ; LIS -> RemoveMachineInstrFromMaps ( I ) ; LIS -> RemoveMachineInstrFromMaps ( Paired ) ; I -> eraseFromParent ( ) ; Paired -> eraseFromParent ( ) ; LiveInterval & AddrRegLI = LIS -> getInterval ( AddrReg -> getReg ( ) ) ; LIS -> shrinkToUses ( & AddrRegLI ) ; LIS -> getInterval ( DestReg ) ; DEBUG ( dbgs ( ) << <STR_LIT> << * Read2 << '\n' ) ; return Read2 . getInstr ( ) ;


<s> return IsScalar ? <STR_LIT> : <STR_LIT> ;


<s> return ( ( vec_double2 ) ( si_fesd ( ( qword ) ( a ) ) ) ) ;


<s> void setSRetReturnReg ( unsigned Reg ) { SRetReturnReg = Reg ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> bool <ISA_LIT>DAGToDAGISel :: MemOpHasPtr32 ( SDNode * N ) const { return addrSpaceHasPtr32 ( cast < MemSDNode > ( N ) -> getAddressSpace ( ) ) ;


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; MachineBasicBlock :: iterator MBBI ( MI ) ; int Offset ; MachineBasicBlock :: iterator MergeInstr = findIncDecBefore ( MBBI , Base , Pred , PredReg , Offset ) ; unsigned NewOpc ; if ( ! isAM5 && Offset == Bytes ) { NewOpc = getPreIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else if ( Offset == - Bytes ) { NewOpc = getPreIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else { MergeInstr = findIncDecAfter ( MBBI , Base , Pred , PredReg , Offset ) ; if ( Offset == Bytes ) { NewOpc = getPostIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else if ( ! isAM5 && Offset == - Bytes ) { NewOpc = getPostIndexedLoadStoreOpcode ( Opcode , <STR_LIT> ) ; } else return false ; } MBB . erase ( MergeInstr ) ; <STR_LIT> AddSub = Offset < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; bool isLd = isLoadSingle ( Opcode ) ; if ( isAM5 ) { MachineOperand & MO = MI -> getOperand ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addReg ( Base , getDefRegState ( true ) ) . addReg ( Base , getKillRegState ( isLd ? BaseKill : false ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( MO . getReg ( ) , ( isLd ? getDefRegState ( true ) : getKillRegState ( MO . isKill ( ) ) ) ) . cloneMemRefs ( * MI ) ; } else if ( isLd ) { if ( isAM2 ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) . cloneMemRefs ( * MI ) ; } else { int Imm = <STR_LIT> ( AddSub , Bytes , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( Base , RegState :: Define ) . addReg ( Base ) . addReg ( <NUM_LIT> ) . addImm ( Imm ) . add ( predOps ( Pred , PredReg ) ) . cloneMemRefs ( * MI ) ; }


<s> bool <ISA_LIT>DAGToDAGISel :: SelectAddr ( SDValue Addr , SDValue & Base , SDValue & Offset ) { return true ;


<s> lowerJumpTable ( SDValue Op , SelectionDAG & DAG ) const {

JumpTableSDNode * N = cast < JumpTableSDNode > ( Op ) ;


<s> static bool allocateFloat ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { switch ( LocVT . SimpleTy ) {


<s> static const <STR_LIT> * lookupSysReg ( unsigned Val , bool Read , const MCSubtargetInfo & STI ) { const <STR_LIT> * Reg = <STR_LIT> ( Val ) ; if ( Reg && ! isValidSysReg ( Reg , Read , STI ) ) Reg = <STR_LIT> ( Reg -> AltName ) ; return Reg ;


<s> if ( TID . isBranch ( ) && ! TID . isBarrier ( ) ) return true ;

if ( ! TID . isPredicable ( ) ) return true ;


<s> StringRef getPassName ( ) const override {


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ) ;


<s> static __inline __m128d __attribute__ ( ( __always_inline__ ) ) _mm_loadu_pd ( double const * __P ) { return __builtin_ia32_loadupd ( __P ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( StackGrowsDown , sti . getStackAlignment ( ) , <NUM_LIT> , <NUM_LIT> ) , STI ( sti ) {


<s> bool isSpecial ; bool isSigned = checkDTSpecial ( Desc , & isSpecial ) ; if ( isSpecial ) return isSigned ; <ISA_LIT>II :: OpType optype = getOpType ( Desc , MI ) ; isSigned = ( optype == <ISA_LIT>II :: OpType :: INT32 || optype == <ISA_LIT>II :: OpType :: INT16 || optype == <ISA_LIT>II :: OpType :: INT8 || optype == <ISA_LIT>II :: OpType :: INT4 ) ;


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ;


<s> total_size = extra_size + pretend_size + args_size + var_size ; reg_size = <NUM_LIT> ; reg_mask = <NUM_LIT> ; for ( regno = GPR_R0 ; regno <= GPR_LAST ; regno ++ ) { if ( MUST_SAVE_REGISTER ( regno ) ) { reg_size += UNITS_PER_WORD ; reg_mask |= <NUM_LIT> << regno ; } } current_frame_info . save_fp = ( regs_ever_live [ GPR_FP ] || frame_pointer_needed || interrupt_handler ) ;


<s> PointerType * PtrTy = PointerType :: get ( ParamTy , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned TypeSize = DL . getTypeStoreSize ( ParamTy ) ;

Register PtrReg = lowerParameterPtr ( MIRBuilder , ParamTy , Offset ) ;


<s> InstructionSelector :: ComplexRendererFns <ISA_LIT>InstructionSelector :: selectDS128Bit8ByteAligned ( MachineOperand & Root ) const {

return selectDSReadWrite2 ( Root , true ) ;


<s> if ( ! isLegalRegList ( regList . List1From , regList . List1To ) ) return false ; if ( ! isLegalRegList ( regList . List2From , regList . List2To ) ) return false ;

if ( ! isLegalRegList ( regList . List3From , regList . List3To ) ) return false ;


<s> if ( ( ResT == <STR_LIT> || ResT == <STR_LIT> ) && ( SatVT == <STR_LIT> || SatVT == <STR_LIT> ) ) return Op ; if ( ResT == <STR_LIT> && SatVT == <STR_LIT> ) return Op ; return SDValue ( ) ;


<s> auto GetWasmConversionOp = [ ] ( unsigned Op ) { switch ( Op ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; } llvm_unreachable ( <STR_LIT> ) ; } ; if ( N -> getOpcode ( ) == <STR_LIT> ) { auto Conversion = N -> getOperand ( <NUM_LIT> ) ; auto ConversionOp = Conversion . getOpcode ( ) ; MVT ExpectedSourceType ; switch ( ConversionOp ) { case <STR_LIT> : case <STR_LIT> : ExpectedSourceType = <STR_LIT> ; break ; case <STR_LIT> : ExpectedSourceType = <STR_LIT> ; break ; default : return SDValue ( ) ; } if ( Conversion . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; auto Source = Conversion . getOperand ( <NUM_LIT> ) ; if ( Source . getValueType ( ) != ExpectedSourceType ) return SDValue ( ) ; auto IndexNode = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( IndexNode == nullptr || IndexNode -> getZExtValue ( ) != <NUM_LIT> ) return SDValue ( ) ; auto Op = GetWasmConversionOp ( ConversionOp ) ; return DAG . getNode ( Op , SDLoc ( N ) , ResVT , Source ) ; } auto ConversionOp = N -> getOpcode ( ) ; MVT ExpectedExtractType ; MVT ExpectedSourceType ; switch ( ConversionOp ) { case <STR_LIT> : case <STR_LIT> : ExpectedExtractType = <STR_LIT> ; ExpectedSourceType = <STR_LIT> ; break ; case <STR_LIT> : ExpectedExtractType = <STR_LIT> ; ExpectedSourceType = <STR_LIT> ; break ;


<s> case TImode : return V1TImode ; case DImode : return V2DImode ; case SImode : return V4SImode ; case HImode : return V8HImode ; case QImode : return V16QImode ; default : ; } if ( TARGET_SPE ) switch ( mode ) { case SFmode : return V2SFmode ; case SImode : return V2SImode ; default : ;


<s> Types . resize ( std :: max ( i + <NUM_LIT> , Types . size ( ) ) , <STR_LIT> ) ; return Types [ i ] ;


<s> if ( isLaneMaskReg ( DstReg ) || isVreg1 ( DstReg ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; DebugLoc DL = MI . getDebugLoc ( ) ; assert ( TII -> getRegisterInfo ( ) . getRegSizeInBits ( DstReg , * MRI ) == <NUM_LIT> ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ) ; ConstrainRegs . insert ( SrcReg ) ; BuildMI ( MBB , MI , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addReg ( SrcReg ) ;


<s> struct extern_list * p ; p = ( struct extern_list * ) ggc_alloc ( sizeof * p ) ; p -> next = extern_head ; p -> decl = decl ; p -> name = name ; extern_head = p ;


<s> dbgs ( ) << <STR_LIT> << <STR_LIT> ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: SelectPostStore ( SDNode * N , unsigned NumVecs , unsigned Opc ) { SDLoc dl ( N ) ; EVT VT = N -> getOperand ( <NUM_LIT> ) -> getValueType ( <NUM_LIT> ) ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; bool Is128Bit = VT . getSizeInBits ( ) == <NUM_LIT> ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = Is128Bit ? createQTuple ( Regs ) : createDTuple ( Regs ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( NumVecs + <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ;

SDNode * St = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ;


<s> vld1q_dup_u32 ( const uint32_t * __a ) { return ( uint32x4_t ) __builtin_neon_vld1_dupv4si ( ( const __builtin_neon_si * ) __a ) ;


<s> IsKillSet = true ; for ( int i = <NUM_LIT> , e = EndMI . getNumOperands ( ) ; i != e ; ++ i ) if ( i != UseIndex ) clearOperandKillInfo ( EndMI , i ) ; } MachineBasicBlock :: reverse_iterator It = EndMI ; MachineBasicBlock :: reverse_iterator E = EndMI . getParent ( ) -> rend ( ) ; It ++ ; MachineOperand * MO = nullptr ; for ( ; It != E ; ++ It ) { if ( It -> isDebugInstr ( ) || It -> isPosition ( ) ) continue ; for ( int i = <NUM_LIT> , e = It -> getNumOperands ( ) ; i != e ; ++ i ) clearOperandKillInfo ( * It , i ) ; if ( ! IsKillSet ) { if ( ( MO = It -> findRegisterUseOperand ( RegNo , false , & getRegisterInfo ( ) ) ) ) { IsKillSet = true ; MO -> setIsKill ( true ) ; continue ; } else if ( ( MO = It -> findRegisterDefOperand ( RegNo , false , true , & getRegisterInfo ( ) ) ) ) { assert ( & * It == & StartMI && <STR_LIT> ) ; MO -> setIsDead ( true ) ; break ;


<s> O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> : O << <STR_LIT> ; break ; case <NUM_LIT> :


<s> if ( Scale < <NUM_LIT> ) return false ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Scale == <NUM_LIT> ) return true ; Scale = Scale & ~ <NUM_LIT> ; return Scale == <NUM_LIT> || Scale == <NUM_LIT> || Scale == <NUM_LIT> ; case <STR_LIT> : if ( ( ( unsigned ) AM . HasBaseReg + Scale ) <= <NUM_LIT> ) return true ; return false ; case <STR_LIT> : if ( Scale & <NUM_LIT> ) return false ; return isPowerOf2_32 ( Scale ) ;


<s> const REAL_VALUE_TYPE * r ; if ( GET_MODE ( op ) != SFmode ) return false ;


<s> void <ISA_LIT>TargetMachine :: addAnalysisPasses ( PassManagerBase & PM ) {


<s> Value * Ordering = Builder . getIntN ( XLen , static_cast < uint64_t > ( Ord ) ) ; <STR_LIT> CmpXchgIntrID = <STR_LIT> ; if ( XLen == <NUM_LIT> ) { CmpVal = Builder . CreateSExt ( CmpVal , Builder . getInt64Ty ( ) ) ; NewVal = Builder . CreateSExt ( NewVal , Builder . getInt64Ty ( ) ) ; Mask = Builder . CreateSExt ( Mask , Builder . getInt64Ty ( ) ) ; CmpXchgIntrID = <STR_LIT> ; } Type * Tys [ ] = { AlignedAddr -> getType ( ) } ; Function * MaskedCmpXchg = <STR_LIT> ( CI -> getModule ( ) , CmpXchgIntrID , Tys ) ;

Value * Result = Builder . CreateCall ( MaskedCmpXchg , { AlignedAddr , CmpVal , NewVal , Mask , Ordering } ) ;


<s> case OPW128 : return AReg_128RegClassID ; case OPW160 : return AReg_160RegClassID ; case OPW256 : return AReg_256RegClassID ; case OPW512 : return AReg_512RegClassID ; case OPW1024 : return AReg_1024RegClassID ; }


<s> MachineInstrBuilder MIB ; if ( Subtarget . isGP64bit ( ) ) MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) ; else MIB = BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Undef ) ; for ( auto & MO : I -> operands ( ) ) { if ( MO . isImplicit ( ) ) MIB . add ( MO ) ; }


return ( STI . getFeatureBits ( ) & <STR_LIT> ) ;


<s> if ( ST -> hasMVEIntegerOps ( ) ) return <NUM_LIT> ; return <NUM_LIT> ; } if ( ST -> isThumb1Only ( ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> return ( AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) ) ; case <NUM_LIT> : * len = <NUM_LIT> ; return ( AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) ) ; case <NUM_LIT> : if ( test_hard_reg_class ( LD_REGS , operands [ <NUM_LIT> ] ) ) { * len = <NUM_LIT> ; return ( AS1 ( swap , % <NUM_LIT> ) CR_TAB AS2 ( andi , % <NUM_LIT> , <NUM_LIT> ) ) ; } * len = <NUM_LIT> ; return ( AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) ) ; case <NUM_LIT> : if ( test_hard_reg_class ( LD_REGS , operands [ <NUM_LIT> ] ) ) { * len = <NUM_LIT> ; return ( AS1 ( swap , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS2 ( andi , % <NUM_LIT> , <NUM_LIT> ) ) ; } * len = <NUM_LIT> ; return ( AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) ) ; case <NUM_LIT> : if ( test_hard_reg_class ( LD_REGS , operands [ <NUM_LIT> ] ) ) { * len = <NUM_LIT> ; return ( AS1 ( swap , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS2 ( andi , % <NUM_LIT> , <NUM_LIT> ) ) ; } * len = <NUM_LIT> ; return ( AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) CR_TAB AS1 ( lsr , % <NUM_LIT> ) ) ; case <NUM_LIT> : * len = <NUM_LIT> ; return ( AS1 ( rol , % <NUM_LIT> ) CR_TAB AS1 ( clr , % <NUM_LIT> ) CR_TAB AS1 ( rol , % <NUM_LIT> ) ) ; }


<s> tree return_type ; return_type = DECL_RESULT ( current_function_decl ) ; if ( regno == GP_REG_FIRST + <NUM_LIT> && regs_ever_live [ regno ] ) return true ; if ( regno == GP_REG_FIRST + <NUM_LIT> && mips16_hard_float && ! aggregate_value_p ( return_type , current_function_decl ) && GET_MODE_CLASS ( DECL_MODE ( return_type ) ) == MODE_FLOAT && GET_MODE_SIZE ( DECL_MODE ( return_type ) ) <= UNITS_PER_FPVALUE ) return true ; } return false ;


<s> if ( ! doMergeWithPrevious ) MBBI = NI ; } else if ( ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) && PI -> getOperand ( <NUM_LIT> ) . getReg ( ) == StackPtr ) { Offset -= PI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MBB . erase ( PI ) ; if ( ! doMergeWithPrevious ) MBBI = NI ; } return Offset ;


<s> R600MCCodeEmitter ( const MCInstrInfo & mcii , const MCRegisterInfo & mri , const MCSubtargetInfo & sti , MCContext & ctx ) : MCII ( mcii ) , MRI ( mri ) , STI ( sti ) , Ctx ( ctx ) {


<s> static bool isMOVLPMask ( ArrayRef < int > Mask , EVT VT ) { if ( VT . getSizeInBits ( ) != <NUM_LIT> ) return false ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i != NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i + NumElems ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> ; i != NumElems ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ;


<s> rtx d = CONST_DOUBLE_FROM_REAL_VALUE ( dconst , mode ) ; reg = force_reg ( mode , d ) ; } else if ( mode == V4SFmode ) { rtx d = CONST_DOUBLE_FROM_REAL_VALUE ( dconst , SFmode ) ; rtvec v = gen_rtvec ( <NUM_LIT> , d , d , d , d ) ;


<s> <ISA_LIT>IncomingValueHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI ) : CallLowering :: IncomingValueHandler ( MIRBuilder , MRI ) {


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const MachineModuleInfo & MMI = MF . getMMI ( ) ; const TargetRegisterInfo * RI = TM . getRegisterInfo ( ) ;

return ( DisableFramePointerElim ( MF ) || RI -> needsStackRealignment ( MF ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getForceFramePointer ( ) || MMI . callsUnwindInit ( ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: isLoadFromStackSlot ( const MachineInstr * mi , int & fi ) const { if ( ( mi -> getOpcode ( ) == <STR_LIT> || mi -> getOpcode ( ) == <STR_LIT> || mi -> getOpcode ( ) == <STR_LIT> || mi -> getOpcode ( ) == <STR_LIT> ) && mi -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { fi = mi -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;

return mi -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> if ( ! TARGET_LINKED_FP ) return ! current_function_sp_is_unchanging ; if ( ! current_function_is_leaf ) return TRUE ; if ( get_frame_size ( ) != <NUM_LIT> ) return TRUE ; if ( cfun -> stdarg ) return TRUE ; if ( ! current_function_sp_is_unchanging ) return TRUE ; if ( ! TARGET_FDPIC && flag_pic && cfun -> uses_pic_offset_table ) return TRUE ; if ( profile_flag ) return TRUE ;

if ( cfun -> machine -> frame_needed ) return TRUE ;


<s> if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else {


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) {

return new <ISA_LIT>TargetELFStreamer ( S , STI ) ;


<s> SelectionDAGISel ( tm ) , TM ( tm ) , Subtarget ( tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ) {


<s> if ( MI != MBB . end ( ) ) dl = MI -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , dl , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) ;

else if ( RC == & <STR_LIT> || <STR_LIT> . contains ( DestReg ) ) {


<s> if ( ! Stubs . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( <NUM_LIT> ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } MCTargetStreamer & TS = * OutStreamer -> getTargetStreamer ( ) ; <ISA_LIT>TargetStreamer & ATS = static_cast < <ISA_LIT>TargetStreamer & > ( TS ) ; if ( OptimizationGoals > <NUM_LIT> && ( Subtarget -> isTargetAEABI ( ) || Subtarget -> isTargetGNUAEABI ( ) ) ) ATS . emitAttribute ( <STR_LIT> , OptimizationGoals ) ;


<s> if ( newElfFlags & llvm :: ELF :: EF_MIPS_PIC ) newElfFlags |= llvm :: ELF :: EF_MIPS_CPIC ; if ( newElfFlags & llvm :: ELF :: EF_MIPS_ARCH_ASE_M16 ) { error ( diag :: error_<ISA_LIT>_m16_unsupported ) << pInput . name ( ) ; return false ; } if ( ! oldElfFlags ) { oldElfFlags = newElfFlags ; return true ; } uint64_t newPic = newElfFlags & ( llvm :: ELF :: EF_MIPS_PIC | llvm :: ELF :: EF_MIPS_CPIC ) ; uint64_t oldPic = oldElfFlags & ( llvm :: ELF :: EF_MIPS_PIC | llvm :: ELF :: EF_MIPS_CPIC ) ; if ( ( newPic != <NUM_LIT> ) != ( oldPic != <NUM_LIT> ) ) warning ( diag :: warn_<ISA_LIT>_abicalls_linking ) << pInput . name ( ) ; if ( ! ( newPic & llvm :: ELF :: EF_MIPS_PIC ) ) oldElfFlags &= ~ llvm :: ELF :: EF_MIPS_PIC ; if ( newPic ) oldElfFlags |= llvm :: ELF :: EF_MIPS_CPIC ; uint64_t newArch = newElfFlags & llvm :: ELF :: EF_MIPS_ARCH ; uint64_t oldArch = oldElfFlags & llvm :: ELF :: EF_MIPS_ARCH ;

if ( ! isIsaMatched ( newArch , oldArch ) ) {


return ( __a == __AARCH64_UINT64_C ( <NUM_LIT> ) ) ;


<s> void <ISA_LIT>RegisterSema :: insertExternalWrapperAsm ( BasicBlock * WrapperBB , Function * ExtFn ) { DCIRBuilder WBuilder ( WrapperBB ) ; Type * ArgTypes [ <NUM_LIT> ] = { RegSetType -> getPointerTo ( ) , ExtFn -> getType ( ) } ;

Function * EWFn = cast < Function > ( ExtFn -> getParent ( ) -> getOrInsertFunction ( <STR_LIT> , FunctionType :: get ( Type :: getVoidTy ( * Ctx ) , ArgTypes , false ) ) ) ;


<s> rtx body = PATTERN ( insn ) ; rtx dest_address = XEXP ( SET_DEST ( body ) , <NUM_LIT> ) ; rtx swap_reg = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; if ( ! REG_P ( dest_address ) && ! rs6000_sum_of_two_registers_p ( dest_address ) ) return false ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( insn ) ; df_ref use ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ;

if ( ! rtx_equal_p ( DF_REF_REG ( use ) , swap_reg ) ) continue ;


<s> switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'z' : return C_Other ; case 'x' : case 'w' :


<s> bool hasVOP3PInsts ( ) const { return HasVOP3PInsts ;


<s> New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = TII . getFramePoppedByCallee ( * I ) ) { MachineInstr & Old = * I ; MachineInstr * New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( CalleeAmt ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } return MBB . erase ( I ) ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) {

return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> break ; case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ; Rs = L . getOperand ( <NUM_LIT> ) ; Rt = L . getOperand ( <NUM_LIT> ) ; compoundOpcode = cmpgtuBitOpcode [ getCompoundOp ( R ) ] ; CompoundInsn = new ( Context ) MCInst ; CompoundInsn -> setOpcode ( compoundOpcode ) ; CompoundInsn -> addOperand ( Rs ) ; CompoundInsn -> addOperand ( Rt ) ; CompoundInsn -> addOperand ( R . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( L . getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) compoundOpcode = cmpeqn1BitOpcode [ getCompoundOp ( R ) ] ; else compoundOpcode = cmpeqiBitOpcode [ getCompoundOp ( R ) ] ; Rs = L . getOperand ( <NUM_LIT> ) ; CompoundInsn = new ( Context ) MCInst ; CompoundInsn -> setOpcode ( compoundOpcode ) ; CompoundInsn -> addOperand ( Rs ) ; if ( L . getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) CompoundInsn -> addOperand ( L . getOperand ( <NUM_LIT> ) ) ; CompoundInsn -> addOperand ( R . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( L . getOperand ( <NUM_LIT> ) . getImm ( ) == - <NUM_LIT> ) compoundOpcode = cmpgtn1BitOpcode [ getCompoundOp ( R ) ] ; else compoundOpcode = cmpgtiBitOpcode [ getCompoundOp ( R ) ] ; Rs = L . getOperand ( <NUM_LIT> ) ; CompoundInsn = new ( Context ) MCInst ; CompoundInsn -> setOpcode ( compoundOpcode ) ; CompoundInsn -> addOperand ( Rs ) ; if ( L . getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) CompoundInsn -> addOperand ( L . getOperand ( <NUM_LIT> ) ) ; CompoundInsn -> addOperand ( R . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ; Rs = L . getOperand ( <NUM_LIT> ) ; compoundOpcode = cmpgtuiBitOpcode [ getCompoundOp ( R ) ] ; CompoundInsn = new ( Context ) MCInst ; CompoundInsn -> setOpcode ( compoundOpcode ) ; CompoundInsn -> addOperand ( Rs ) ; CompoundInsn -> addOperand ( L . getOperand ( <NUM_LIT> ) ) ; CompoundInsn -> addOperand ( R . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : DEBUG ( dbgs ( ) << <STR_LIT> ) ; Rs = L . getOperand ( <NUM_LIT> ) ; compoundOpcode = tstBitOpcode [ getCompoundOp ( R ) ] ; CompoundInsn = new ( Context ) MCInst ; CompoundInsn -> setOpcode ( compoundOpcode ) ; CompoundInsn -> addOperand ( Rs ) ; CompoundInsn -> addOperand ( R . getOperand ( <NUM_LIT> ) ) ; break ; }


<s> SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; EVT AVT ; SDValue Count ; ConstantSDNode * ValC = dyn_cast < ConstantSDNode > ( Src ) ; unsigned BytesLeft = <NUM_LIT> ; bool TwoRepStos = false ; if ( ValC ) { unsigned ValReg ; uint64_t Val = ValC -> getZExtValue ( ) & <NUM_LIT> ; switch ( Align & <NUM_LIT> ) { case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; break ; case <NUM_LIT> : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; Val = ( Val << <NUM_LIT> ) | Val ; if ( Subtarget -> is64Bit ( ) && ( ( Align & <NUM_LIT> ) == <NUM_LIT> ) ) { AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Val = ( Val << <NUM_LIT> ) | Val ; } break ; default : AVT = <STR_LIT> ; ValReg = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal ) ; break ; } if ( AVT . bitsGT ( <STR_LIT> ) ) { unsigned UBytes = AVT . getSizeInBits ( ) / <NUM_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal / UBytes ) ; BytesLeft = SizeVal % UBytes ; } Chain = DAG . getCopyToReg ( Chain , dl , ValReg , DAG . getConstant ( Val , AVT ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } else { AVT = <STR_LIT> ; Count = DAG . getIntPtrConstant ( SizeVal ) ; Chain = DAG . getCopyToReg ( Chain , dl , <STR_LIT> , Src , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Count , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> , Dst , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;

SDValue Ops [ ] = { Chain , DAG . getValueType ( AVT ) , InFlag } ;


<s> for ( Function & F : M . functions ( ) ) { if ( ! llvm :: <STR_LIT> ( & F ) ) continue ; Function * K = & F ; KernelToCallees [ K ] = collectReachableCallees ( K ) ; }


<s> const Value * V = FLI -> getValueFromVirtualReg ( Reg ) ; if ( V ) return KDA -> isDivergent ( V ) ; assert ( Reg == FLI -> DemoteRegister || isCopyFromRegOfInlineAsm ( N ) ) ; return ! TRI . isSGPRReg ( MRI , Reg ) ; } break ; case <STR_LIT> : { const LoadSDNode * L = cast < LoadSDNode > ( N ) ; unsigned AS = L -> getAddressSpace ( ) ; return AS == <ISA_LIT>AS :: PRIVATE_ADDRESS || AS == <ISA_LIT>AS :: FLAT_ADDRESS ; } break ; case <STR_LIT> : return true ; break ; case <STR_LIT> : { } return <STR_LIT> ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; case <STR_LIT> : return <STR_LIT> ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) ; case <STR_LIT> : case <STR_LIT> :


<s> return dyn_cast_or_null < BlockAddress > ( CVal ) ;


<s> return ( NumLoads <= <NUM_LIT> && ( Offset1 - Offset0 ) < <NUM_LIT> ) ;


<s> MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; unsigned Align = MFI . getObjectAlignment ( FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( PseudoSourceValue :: getFixedStack ( FI ) ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , Align ) ; if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; } else if ( RC == & <STR_LIT> ) {


<s> bool <ISA_LIT>FastISel :: SelectRet ( const Instruction * I ) { const ReturnInst * Ret = cast < ReturnInst > ( I ) ; const Function & F = * I -> getParent ( ) -> getParent ( ) ; if ( ! FuncInfo . CanLowerReturn ) return false ; if ( TLI . supportSwiftError ( ) && F . getAttributes ( ) . hasAttrSomewhere ( Attribute :: SwiftError ) ) return false ; if ( TLI . supportSplitCSR ( FuncInfo . MF ) ) return false ; SmallVector < unsigned , <NUM_LIT> > RetRegs ; CallingConv :: ID CC = F . getCallingConv ( ) ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( CC , F . getReturnType ( ) , F . getAttributes ( ) , Outs , TLI , DL ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , CCAssignFnForCall ( CC , true , F . isVarArg ( ) ) ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ;

if ( ! VA . isRegLoc ( ) ) return false ;


<s> if ( Op1 . isImm ( ) ) { BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , P . second ) . addImm ( Op1 . getImm ( ) ) ; } else if ( Op1 . isReg ( ) ) { BuildMI ( B , MI , DL , TII -> get ( TargetOpcode :: COPY ) , P . second ) . addReg ( Op1 . getReg ( ) , getRegState ( Op1 ) , Op1 . getSubReg ( ) ) ; } else llvm_unreachable ( <STR_LIT> ) ;


<s> psllh_u ( uint16x4_t s , uint8_t amount ) {

return __builtin_loongson_psllh_u ( s , amount ) ;


<s> LLT Ty = MRI . getType ( DefReg ) ; unsigned NewOpc ; if ( Ty == LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) NewOpc = <STR_LIT> ; else if ( Ty == LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) NewOpc = STI . isTarget64BitILP32 ( ) ? <STR_LIT> : <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; I . setDesc ( TII . get ( NewOpc ) ) ; MachineInstrBuilder MIB ( MF , I ) ;


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> if ( vcall_offset != <NUM_LIT> ) { emit_move_insn ( temp , gen_rtx_MEM ( Pmode , this_rtx ) ) ; arm_split_constant ( PLUS , Pmode , NULL_RTX , vcall_offset , temp , temp , false ) ; emit_move_insn ( temp , gen_rtx_MEM ( Pmode , temp ) ) ; emit_insn ( gen_add3_insn ( this_rtx , this_rtx , temp ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } rtx funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; rtx_insn * insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx , NULL_RTX ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; insn = get_insns ( ) ;


return ( int32x4_t ) __builtin_neon_vld1_lanev4si ( ( const __builtin_neon_si * ) __a , __b , __c ) ;


<s> SDValue False = N -> getOperand ( <NUM_LIT> ) ; if ( LHS . getOperand ( <NUM_LIT> ) . getNode ( ) != True . getNode ( ) || LHS . getOperand ( <NUM_LIT> ) . getNode ( ) != False . getNode ( ) || RHS . getNode ( ) != False . getNode ( ) || cast < CondCodeSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> get ( ) != <STR_LIT> ) { return SDValue ( ) ; } <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( LHS -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; CCOpcode = <STR_LIT> ( CCOpcode , LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) ; return DAG . getSelectCC ( N -> getDebugLoc ( ) , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , LHS . getOperand ( <NUM_LIT> ) , CCOpcode ) ; } case <STR_LIT> : { SDValue Arg = N -> getOperand ( <NUM_LIT> ) ; if ( Arg . getOpcode ( ) != <STR_LIT> ) break ; SDValue NewBldVec [ <NUM_LIT> ] = { DAG . getUNDEF ( <STR_LIT> ) , DAG . getUNDEF ( <STR_LIT> ) , DAG . getUNDEF ( <STR_LIT> ) , DAG . getUNDEF ( <STR_LIT> ) } ; SDValue NewArgs [ <NUM_LIT> ] = { N -> getOperand ( <NUM_LIT> ) , SDValue ( ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) } ; for ( unsigned i = <NUM_LIT> ; i < Arg . getNumOperands ( ) ; i ++ ) { if ( ConstantFPSDNode * C = dyn_cast < ConstantFPSDNode > ( Arg . getOperand ( i ) ) ) { if ( C -> isZero ( ) ) { NewArgs [ <NUM_LIT> + i ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; } else if ( C -> isExactlyValue ( <NUM_LIT> ) ) { NewArgs [ <NUM_LIT> + i ] = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; } else { NewBldVec [ i ] = Arg . getOperand ( i ) ; } } else { NewBldVec [ i ] = Arg . getOperand ( i ) ; } } DebugLoc DL = N -> getDebugLoc ( ) ; NewArgs [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewBldVec , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , NewArgs , <NUM_LIT> ) ; } }


<s> else if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else if ( MO . isExpr ( ) ) MO . getExpr ( ) -> print ( O , MAI ) ;


<s> getTargetStreamer ( ) . EmitARM64WinCFIEpilogStart ( ) ;


<s> MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; bool IsEHFuncletEpilogue = MBBI == MBB . end ( ) ? false : isFuncletReturnInstr ( * MBBI ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; int FIOffset ; unsigned BasePtr ; if ( MI . isReturn ( ) ) { assert ( ( ! needsStackRealignment ( MF ) || MF . getFrameInfo ( ) . isFixedObjectIndex ( FrameIndex ) ) && <STR_LIT> ) ; FIOffset = TFI -> getFrameIndexReferenceSP ( MF , FrameIndex , BasePtr , <NUM_LIT> ) ; } else if ( TFI -> Is64Bit && ( MBB . isEHFuncletEntry ( ) || IsEHFuncletEpilogue ) ) { FIOffset = TFI -> getWin64EHFrameIndexRef ( MF , FrameIndex , BasePtr ) ; } else { FIOffset = TFI -> getFrameIndexReference ( MF , FrameIndex , BasePtr ) ; } unsigned Opc = MI . getOpcode ( ) ; if ( Opc == TargetOpcode :: LOCAL_ESCAPE ) { MachineOperand & FI = MI . getOperand ( FIOperandNum ) ; FI . ChangeToImmediate ( FIOffset ) ; return ; } Register MachineBasePtr = BasePtr ; if ( Opc == <STR_LIT> && <STR_LIT> . contains ( BasePtr ) ) MachineBasePtr = get<ISA_LIT>SubSuperRegister ( BasePtr , <NUM_LIT> ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( MachineBasePtr , false ) ; if ( BasePtr == StackPtr ) FIOffset += SPAdj ; if ( Opc == TargetOpcode :: STACKMAP || Opc == TargetOpcode :: PATCHPOINT ) { assert ( BasePtr == FramePtr && <STR_LIT> ) ; int64_t Offset = MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) + FIOffset ; MI . getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ; return ; }

if ( MI . getOperand ( FIOperandNum + <NUM_LIT> ) . isImm ( ) ) {


<s> return ( vector unsigned int ) __builtin_altivec_vsubuws ( ( vector signed int ) a1 , ( vector signed int ) a2 ) ;


<s> if ( offset_value . coeffs [ <NUM_LIT> ] > <NUM_LIT> ) return aarch64_output_sve_cnt_immediate ( <STR_LIT> , <STR_LIT> , AARCH64_SV_ALL , offset_value . coeffs [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> SDValue SplatVal ; if ( ! ( ShiftVec = dyn_cast < BuildVectorSDNode > ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) || ! ( SplatVal = ShiftVec -> getSplatValue ( ) ) ) return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; ConstantSDNode * SplatConst = dyn_cast < ConstantSDNode > ( SplatVal ) ; if ( ! SplatConst || Op . getSimpleValueType ( ) != <STR_LIT> ) return Op ; unsigned Opcode ;


<s> const MCRegisterInfo * RegInfo = D -> getContext ( ) . getRegisterInfo ( ) ; return * ( RegInfo -> getRegClass ( RC ) . begin ( ) + RegNo ) ;


<s> SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue tricoreCC ; SDValue Flag = EmitCMP ( LHS , RHS , CC , dl , DAG , tricoreCC ) ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , Flag . getValue ( <NUM_LIT> ) , tricoreCC , Flag . getValue ( <NUM_LIT> ) ) ;


<s> return getGeneration ( ) == <ISA_LIT>Subtarget :: GFX9 ;


<s> auto IsFalseIfZero = [ ] ( <STR_LIT> CC , int Imm ) { return ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) || ( CC == <STR_LIT> && Imm == <NUM_LIT> ) ; } ; assert ( ( IsTrueIfZero ( CC , Imm ) || IsFalseIfZero ( CC , Imm ) ) && <STR_LIT> ) ; SDLoc dl ( Int ) ; SelectionDAG & DAG = DCI . DAG ; SDValue Elements = Int . getOperand ( <NUM_LIT> ) ; unsigned IntOp = cast < ConstantSDNode > ( Int -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; assert ( ( N -> hasOneUse ( ) && N -> use_begin ( ) -> getOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; SDNode * Br = * N -> use_begin ( ) ; SDValue OtherTarget = Br -> getOperand ( <NUM_LIT> ) ; auto UpdateUncondBr = [ ] ( SDNode * Br , SDValue Dest , SelectionDAG & DAG ) { SDValue NewBrOps [ ] = { Br -> getOperand ( <NUM_LIT> ) , Dest } ; SDValue NewBr = DAG . getNode ( <STR_LIT> , SDLoc ( Br ) , <STR_LIT> , NewBrOps ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Br , <NUM_LIT> ) , NewBr ) ; } ; if ( IntOp == <STR_LIT> ) { SDValue Res ; if ( IsTrueIfZero ( CC , Imm ) ) { SDValue Ops [ ] = { Chain , Elements , Dest } ; Res = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops ) ; } else { UpdateUncondBr ( Br , Dest , DAG ) ;

SDValue Ops [ ] = { Chain , Elements , OtherTarget } ;


<s> <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; unsigned SP = <STR_LIT> ; unsigned ADDiu = <STR_LIT> ; unsigned StackAlign = getStackAlignment ( ) ; unsigned LocalVarAreaOffset = <ISA_LIT>FI -> getMaxCallFrameSize ( ) ; uint64_t StackSize = RoundUpToAlignment ( LocalVarAreaOffset , StackAlign ) + RoundUpToAlignment ( MFI -> getStackSize ( ) , StackAlign ) ; MFI -> setStackSize ( StackSize ) ; if ( StackSize == <NUM_LIT> && ! MFI -> adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; std :: vector < MachineMove > & Moves = MMI . getFrameMoves ( ) ; MachineLocation DstML , SrcML ; if ( isInt < <NUM_LIT> > ( - StackSize ) ) BuildMI ( MBB , MBBI , dl , TII . get ( ADDiu ) , SP ) . addReg ( SP ) . addImm ( - StackSize ) ; else { assert ( <STR_LIT> ) ; } MCSymbol * AdjustSPLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( AdjustSPLabel ) ; DstML = MachineLocation ( MachineLocation :: VirtualFP ) ; SrcML = MachineLocation ( MachineLocation :: VirtualFP , - StackSize ) ; Moves . push_back ( MachineMove ( AdjustSPLabel , DstML , SrcML ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; MCSymbol * CSLabel = MMI . getContext ( ) . CreateTempSymbol ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: PROLOG_LABEL ) ) . addSym ( CSLabel ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; { DstML = MachineLocation ( MachineLocation :: VirtualFP , Offset ) ; SrcML = MachineLocation ( Reg ) ; Moves . push_back ( MachineMove ( CSLabel , DstML , SrcML ) ) ; }


<s> if ( pass_as_float ) { tree next_fp_tmp = create_tmp_var ( TREE_TYPE ( f_next_fp ) ) ; tree cmp ; bool is_double = size == <NUM_LIT> && TREE_CODE ( eff_type ) == REAL_TYPE ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_fp ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; gimplify_assign ( unshare_expr ( next_fp_tmp ) , valist , pre_p ) ; tmp = next_fp_limit ; if ( size > <NUM_LIT> && ! is_double ) tmp = fold_build_pointer_plus_hwi ( unshare_expr ( tmp ) , <NUM_LIT> - size ) ; tmp = build2 ( GE_EXPR , boolean_type_node , unshare_expr ( next_fp_tmp ) , unshare_expr ( tmp ) ) ; cmp = build3 ( COND_EXPR , void_type_node , tmp , build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_false ) ) , NULL_TREE ) ; if ( ! is_double ) gimplify_and_add ( cmp , pre_p ) ; if ( TYPE_ALIGN ( eff_type ) > BITS_PER_WORD || ( is_double || size == <NUM_LIT> ) ) { tmp = fold_convert ( sizetype , next_fp_tmp ) ; tmp = build2 ( BIT_AND_EXPR , sizetype , tmp , size_int ( UNITS_PER_WORD ) ) ; tmp = fold_build_pointer_plus ( unshare_expr ( next_fp_tmp ) , tmp ) ; gimplify_assign ( unshare_expr ( next_fp_tmp ) , tmp , pre_p ) ; } if ( is_double ) gimplify_and_add ( cmp , pre_p ) ; if ( TYPE_MODE ( eff_type ) == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN ) { tree subtype = TREE_TYPE ( eff_type ) ; tree real , imag ; imag = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; imag = get_initialized_tmp_var ( imag , pre_p , NULL ) ; real = std_gimplify_va_arg_expr ( next_fp_tmp , subtype , pre_p , NULL ) ; real = get_initialized_tmp_var ( real , pre_p , NULL ) ; result = build2 ( COMPLEX_EXPR , eff_type , real , imag ) ; if ( type != eff_type ) result = build1 ( VIEW_CONVERT_EXPR , type , result ) ; result = get_initialized_tmp_var ( result , pre_p , NULL ) ; } tmp = build1 ( GOTO_EXPR , void_type_node , unshare_expr ( lab_over ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( LABEL_EXPR , void_type_node , unshare_expr ( lab_false ) ) ; gimplify_and_add ( tmp , pre_p ) ; tmp = build1 ( ADDR_EXPR , pptr_type_node , unshare_expr ( next_stack ) ) ; gimplify_assign ( unshare_expr ( addr ) , tmp , pre_p ) ; gimplify_assign ( unshare_expr ( next_fp_tmp ) , unshare_expr ( valist ) , pre_p ) ; gimplify_assign ( unshare_expr ( valist ) , unshare_expr ( next_fp_tmp ) , post_p ) ; valist = next_fp_tmp ; } else { tmp = fold_build_pointer_plus_hwi ( unshare_expr ( next_o ) , rsize ) ; tmp = build2 ( GT_EXPR , boolean_type_node , tmp , unshare_expr ( next_o_limit ) ) ;


<s> switch ( from ) { case FRAME_POINTER_REGNUM : offset = cfun -> machine -> out_args_size ; break ; case ARG_POINTER_REGNUM : offset = cfun -> machine -> total_size ; offset -= crtl -> args . pretend_args_size ;


<s> auto E = CurrentISELList . end ( ) ; while ( I != E ) { assert ( isISEL ( * * I ) && <STR_LIT> ) ; MachineOperand & Dest = ( * I ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & TrueValue = ( * I ) -> getOperand ( <NUM_LIT> ) ; MachineOperand & FalseValue = ( * I ) -> getOperand ( <NUM_LIT> ) ; if ( useSameRegister ( Dest , TrueValue ) && useSameRegister ( Dest , FalseValue ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << * * I << <STR_LIT> ) ; NumRemoved ++ ; ( * I ) -> eraseFromParent ( ) ; I ++ ; } else if ( useSameRegister ( TrueValue , FalseValue ) ) { MachineBasicBlock * MBB = ( * I ) -> getParent ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> void <ISA_LIT>AsmPrinter :: emitFunctionBodyEnd ( ) {


<s> void <ISA_LIT>InstPrinter :: printAddrBO ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { const MCOperand & Base = MI -> getOperand ( OpNum ) ; const MCOperand & Offset = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned Opcode = MI -> getOpcode ( ) ; switch ( Opcode ) { default : if ( Base . isReg ( ) ) O << <STR_LIT> << StringRef ( getRegisterName ( Base . getReg ( ) ) ) . lower ( ) << <STR_LIT> ; if ( Offset . isExpr ( ) ) Offset . getExpr ( ) -> print ( O , & MAI ) ;


<s> SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FI , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> int pos ; int i ; rtx_insn * tmp ; rtx load_mem , str_mem ; if ( is_store_insn ( last_scheduled_insn , & str_mem ) ) load_store_pendulum -- ; else if ( is_load_insn ( last_scheduled_insn , & load_mem ) ) load_store_pendulum ++ ; else return cached_can_issue_more ; if ( ( load_store_pendulum == <NUM_LIT> ) || ( * pn_ready <= <NUM_LIT> ) ) return cached_can_issue_more ; if ( load_store_pendulum == <NUM_LIT> ) { pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) ) { tmp = ready [ pos ] ; for ( i = pos ; i < * pn_ready - <NUM_LIT> ; i ++ ) ready [ i ] = ready [ i + <NUM_LIT> ] ; ready [ * pn_ready - <NUM_LIT> ] = tmp ; if ( ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( tmp ) ) INSN_PRIORITY ( tmp ) ++ ; break ; } pos -- ; } } else if ( load_store_pendulum == - <NUM_LIT> ) { pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_load_insn ( ready [ pos ] , & load_mem ) && ! sel_sched_p ( ) && INSN_PRIORITY_KNOWN ( ready [ pos ] ) ) { INSN_PRIORITY ( ready [ pos ] ) ++ ; load_store_pendulum -- ; break ; } pos -- ; } } else if ( load_store_pendulum == - <NUM_LIT> ) { int first_store_pos = - <NUM_LIT> ; pos = * pn_ready - <NUM_LIT> ; while ( pos >= <NUM_LIT> ) { if ( is_store_insn ( ready [ pos ] , & str_mem ) ) { rtx str_mem2 ; if ( first_store_pos == - <NUM_LIT> ) first_store_pos = pos ; if ( is_store_insn ( last_scheduled_insn , & str_mem2 ) && adjacent_mem_locations ( str_mem , str_mem2 ) ) { tmp = ready [ pos ] ;


<s> static MCCodeGenInfo * createAMDGPUMCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ;

X -> InitMCCodeGenInfo ( RM , CM , OL ) ;


<s> void addImm0_1Operands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; Register BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <NUM_LIT> ) ; for ( const MCPhysReg & SubReg : subregs_inclusive ( BasePtr ) ) Reserved . set ( SubReg ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ;


<s> void <ISA_LIT>FunctionInfo :: anchor ( ) {


<s> bool <ISA_LIT>SEDAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) {

Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> } if ( Mask . getOpcode ( ) != <STR_LIT> ) return false ; bool FirstImmediate = true ; uint64_t ImmNumber ; for ( unsigned i = <NUM_LIT> , e = Mask . getNumOperands ( ) ; i != e ; ++ i ) { SDValue Op = Mask . getOperand ( i ) ; if ( Op . getOpcode ( ) == <STR_LIT> ) continue ;

if ( ! isa < ConstantSDNode > ( Op ) ) return false ;


<s> SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , DstVT , Dst , DAG . getConstant ( <NUM_LIT> , DstVT ) ) ; SDValue Chain2 = DAG . getStore ( Chain , DL , Byte , Dst2 , DstPtrInfo . getWithOffset ( <NUM_LIT> ) , false , false , <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain1 , Chain2 ) ; } } assert ( Bytes >= <NUM_LIT> && <STR_LIT> ) ; if ( Bytes <= <NUM_LIT> ) { Chain = DAG . getStore ( Chain , DL , Byte , Dst , DstPtrInfo , false , false , Align ) ; SDValue Dst2 = DAG . getNode ( <STR_LIT> , DL , DstVT , Dst , DAG . getConstant ( <NUM_LIT> , DstVT ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Dst2 , Dst , DAG . getConstant ( Bytes - <NUM_LIT> , <STR_LIT> ) ) ; } }


<s> bool <ISA_LIT>TargetLowering :: isCheapToSpeculateCttz ( ) const { return true ;


<s> if ( ElemTy != <STR_LIT> ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; } setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; if ( VT . isInteger ( ) ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Custom ) ; } if ( VT . isInteger ( ) && VT != PromotedBitwiseVT ) { setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Promote ) ; AddPromotedToType ( <STR_LIT> , VT . getSimpleVT ( ) , PromotedBitwiseVT . getSimpleVT ( ) ) ; } setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ; setOperationAction ( <STR_LIT> , VT . getSimpleVT ( ) , Expand ) ;


<s> unsigned A15SDOptimizer :: getDPRLaneFromSPR ( unsigned SReg ) { unsigned DReg = TRI -> getMatchingSuperReg ( SReg , <STR_LIT> , & <STR_LIT> ) ;

if ( DReg != <STR_LIT> ) return <STR_LIT> ;


return ( __m256d ) __builtin_ia32_rsqrt14pd256_mask ( ( __v4df ) __A , ( __v4df ) _mm256_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> ptx_dumpbase = concat ( dumppfx , <STR_LIT> , NULL ) ; if ( save_temps ) ptx_cfile_name = ptx_dumpbase ; else ptx_cfile_name = make_temp_file ( <STR_LIT> ) ; out = fopen ( ptx_cfile_name , <STR_LIT> ) ; if ( ! out ) fatal_error ( input_location , <STR_LIT> , ptx_cfile_name ) ; if ( offload_abi == OFFLOAD_ABI_LP64 ) { char * mko_dumpbase = concat ( dumppfx , <STR_LIT> , NULL ) ; if ( save_temps ) ptx_name = mko_dumpbase ; else ptx_name = make_temp_file ( <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , mko_dumpbase ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , ptx_name ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; const char * * new_argv = XOBFINISH ( & argv_obstack , const char * * ) ; char * execpath = getenv ( <STR_LIT> ) ; char * cpath = getenv ( <STR_LIT> ) ; char * lpath = getenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; unsetenv ( <STR_LIT> ) ; if ( save_temps ) omp_requires_file = concat ( dumppfx , <STR_LIT> , NULL ) ; else omp_requires_file = make_temp_file ( <STR_LIT> ) ; xputenv ( concat ( <STR_LIT> , omp_requires_file , NULL ) ) ; fork_execute ( new_argv [ <NUM_LIT> ] , CONST_CAST ( char * * , new_argv ) , true , <STR_LIT> ) ; obstack_free ( & argv_obstack , NULL ) ; unsetenv ( <STR_LIT> ) ; xputenv ( concat ( <STR_LIT> , execpath , NULL ) ) ; xputenv ( concat ( <STR_LIT> , cpath , NULL ) ) ; xputenv ( concat ( <STR_LIT> , lpath , NULL ) ) ; in = fopen ( omp_requires_file , <STR_LIT> ) ; if ( ! in ) fatal_error ( input_location , <STR_LIT> , omp_requires_file ) ; uint32_t omp_requires ; if ( fread ( & omp_requires , sizeof ( omp_requires ) , <NUM_LIT> , in ) != <NUM_LIT> ) fatal_error ( input_location , <STR_LIT> , omp_requires_file ) ; fclose ( in ) ; in = fopen ( ptx_name , <STR_LIT> ) ; if ( ! in ) fatal_error ( input_location , <STR_LIT> ) ; process ( in , out , omp_requires ) ;


<s> auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; unsigned AddrReg = MRI . createGenericVirtualRegister ( LLT :: pointer ( MPO . getAddrSpace ( ) , <NUM_LIT> ) ) ; MIRBuilder . buildFrameIndex ( AddrReg , FI ) ; return AddrReg ;


<s> RegisterAsmParser < <ISA_LIT>AsmParser > X ( The<ISA_LIT>Target ) ; RegisterAsmParser < <ISA_LIT>AsmParser > Y ( TheThumbTarget ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : TargetOpcode = <STR_LIT> ; break ; case <STR_LIT> : TargetOpcode = <STR_LIT> ; break ; case <STR_LIT> : TargetOpcode = <STR_LIT> ; break ; } if ( VT . isVector ( ) && TLI . isOperationLegal ( Opcode , VT ) && N1 -> getOpcode ( ) == <STR_LIT> ) if ( ConstantSDNode * Mask = isConstOrConstSplat ( N1 -> getOperand ( <NUM_LIT> ) ) ) if ( Mask -> getZExtValue ( ) == OpSizeInBits - <NUM_LIT> ) return DAG . getNode ( TargetOpcode , SDLoc ( N ) , VT , N0 , N1 -> getOperand ( <NUM_LIT> ) ) ; return SDValue ( ) ;


SmallVector < SDValue , <NUM_LIT> > Stores ;


<s> return LLT :: scalar ( PowerOf2Ceil ( Ty . getSizeInBits ( ) ) ) ;


<s> if ( ! Op || any_of ( Ops , [ & ] ( Use * U ) { return U -> get ( ) == Op ; } ) ) continue ; if ( ! match ( Op , m_Shuffle ( m_InsertElt ( m_Undef ( ) , m_Value ( ) , m_ZeroInt ( ) ) , m_Undef ( ) , m_ZeroMask ( ) ) ) ) continue ; for ( Use & U : Op -> uses ( ) ) { Instruction * Insn = cast < Instruction > ( U . getUser ( ) ) ; if ( ! IsSinker ( Insn , U . getOperandNo ( ) ) ) return false ; } Ops . push_back ( & Op -> getOperandUse ( <NUM_LIT> ) ) ; Ops . push_back ( & OpIdx . value ( ) ) ;


<s> bool isMemDisp12 ( MemoryKind MemKind , RegisterKind RegKind ) const {

return isMem ( MemKind , RegKind ) && inRange ( Mem . Disp , <NUM_LIT> , <NUM_LIT> , true ) ;


<s> static std :: pair < SDValue , SDValue > getBoundedStrlen ( SelectionDAG & DAG , const SDLoc & DL , SDValue Chain , SDValue Src , SDValue Limit ) { EVT PtrVT = Src . getValueType ( ) ; SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> , <STR_LIT> ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; Chain = End . getValue ( <NUM_LIT> ) ;

SDValue Len = DAG . getNode ( <STR_LIT> , DL , PtrVT , End , Src ) ;


<s> const MachineOperand & Src2 = MI . getOperand ( <NUM_LIT> ) ; Register R1 ( Src1 ) ; bool Eval = false ; LatticeCell RC ; switch ( Opc ) { default : return false ; case <STR_LIT> : case <STR_LIT> : Eval = evaluateANDrr ( R1 , Register ( Src2 ) , Inputs , RC ) ; break ; case <STR_LIT> : { if ( ! Src2 . isImm ( ) ) return false ; APInt A ( <NUM_LIT> , Src2 . getImm ( ) , true ) ; Eval = evaluateANDri ( R1 , A , Inputs , RC ) ; break ; } case <STR_LIT> : case <STR_LIT> : Eval = evaluateORrr ( R1 , Register ( Src2 ) , Inputs , RC ) ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti , Align Alignment ) : TargetFrameLowering ( StackGrowsDown , Alignment , <NUM_LIT> , Alignment . value ( ) ) , STI ( sti ) {


<s> bool <ISA_LIT>PromoteAllocaImpl :: hasSufficientLocalMem ( const Function & F ) { FunctionType * FTy = F . getFunctionType ( ) ; const <ISA_LIT>Subtarget & ST = <ISA_LIT>Subtarget :: get ( TM , F ) ; for ( Type * ParamTy : FTy -> params ( ) ) { PointerType * PtrTy = dyn_cast < PointerType > ( ParamTy ) ; if ( PtrTy && PtrTy -> getAddressSpace ( ) == <ISA_LIT>AS :: LOCAL_ADDRESS ) { LocalMemLimit = <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; return false ; } } LocalMemLimit = ST . getLocalMemorySize ( ) ; if ( LocalMemLimit == <NUM_LIT> ) return false ; SmallVector < const Constant * , <NUM_LIT> > Stack ; SmallPtrSet < const Constant * , <NUM_LIT> > VisitedConstants ; SmallPtrSet < const GlobalVariable * , <NUM_LIT> > UsedLDS ; auto visitUsers = [ & ] ( const GlobalVariable * GV , const Constant * Val ) -> bool { for ( const User * U : Val -> users ( ) ) { if ( const Instruction * Use = dyn_cast < Instruction > ( U ) ) { if ( Use -> getParent ( ) -> getParent ( ) == & F ) return true ; } else { const Constant * C = cast < Constant > ( U ) ; if ( VisitedConstants . insert ( C ) . second ) Stack . push_back ( C ) ; } } return false ; } ; for ( GlobalVariable & GV : Mod -> globals ( ) ) { if ( GV . getAddressSpace ( ) != <ISA_LIT>AS :: LOCAL_ADDRESS ) continue ; if ( visitUsers ( & GV , & GV ) ) { UsedLDS . insert ( & GV ) ; Stack . clear ( ) ;


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) { if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>BoolRetToIntPass ( ) ) ; addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ; bool UsePrefetching = TM -> getTargetTriple ( ) . getVendor ( ) == Triple :: BGQ && getOptLevel ( ) != CodeGenOpt :: None ; if ( EnablePrefetch . getNumOccurrences ( ) > <NUM_LIT> ) UsePrefetching = EnablePrefetch ; if ( UsePrefetching ) addPass ( create<ISA_LIT>LoopDataPrefetchPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ; addPass ( createEarlyCSEPass ( ) ) ; addPass ( createLICMPass ( ) ) ; }


<s> const TargetRegisterInfo & RI = * TM . getRegisterInfo ( ) ; unsigned stackReg = RI . getFrameRegister ( * MF ) ; unsigned returnReg = RI . getRARegister ( ) ; unsigned stackSize = MF -> getFrameInfo ( ) -> getStackSize ( ) ; getTargetStreamer ( ) . emitFrame ( stackReg , stackSize , returnReg ) ;


<s> Closure ( std :: initializer_list < RegDomain > LegalDstDomainList ) { for ( RegDomain D : LegalDstDomainList ) LegalDstDomains . set ( D ) ;


<s> return VT . isSimple ( ) || ! isOperationExpand ( Opcode , VT ) ;


<s> void <ISA_LIT>DAGToDAGISel :: SwapAllSelectUsers ( SDNode * N ) { SmallVector < SDNode * , <NUM_LIT> > ToReplace ; for ( SDNode :: use_iterator UI = N -> use_begin ( ) , UE = N -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; assert ( ( User -> getMachineOpcode ( ) == <STR_LIT> || User -> getMachineOpcode ( ) == <STR_LIT> ) && <STR_LIT> ) ; ToReplace . push_back ( User ) ; } for ( SmallVector < SDNode * , <NUM_LIT> > :: iterator UI = ToReplace . begin ( ) , UE = ToReplace . end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; SDNode * ResNode = CurDAG -> getMachineNode ( User -> getMachineOpcode ( ) , SDLoc ( User ) , User -> getValueType ( <NUM_LIT> ) , User -> getOperand ( <NUM_LIT> ) , User -> getOperand ( <NUM_LIT> ) , User -> getOperand ( <NUM_LIT> ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( User -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( ResNode -> dump ( CurDAG ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; ReplaceUses ( User , ResNode ) ;


<s> MBBInfos . resize ( MF -> size ( ) ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( TM . getInstrInfo ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MBBInfos . size ( ) ; I < E ; ++ I ) { MachineBasicBlock * MBB = MF -> getBlockNumbered ( I ) ; for ( MachineBasicBlock :: instr_iterator MI = MBB -> instr_begin ( ) ; MI != MBB -> instr_end ( ) ; ++ MI ) MBBInfos [ I ] . Size += TII -> GetInstSizeInBytes ( & * MI ) ;


<s> if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ; } bool DontMoveAcrossStores = true ; if ( ! MI -> isSafeToMove ( nullptr , DontMoveAcrossStores ) ) return nullptr ; return MI ;


<s> void adjustStoreVarArgsFI ( MachineFrameInfo * MFI ) const { if ( ! hasStoreVarArgs ( ) ) return ;

for ( unsigned i = <NUM_LIT> , e = FnStoreVarArgs . size ( ) ; i != e ; ++ i ) MFI -> setObjectOffset ( FnStoreVarArgs [ i ] . FI , FnStoreVarArgs [ i ] . SPOffset ) ;


<s> SDValue A64CMP = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TheBit , DAG . getConstant ( <NUM_LIT> , TheBit . getValueType ( ) ) , DAG . getCondCode ( <STR_LIT> ) ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , A64CMP , DAG . getConstant ( <STR_LIT> , <STR_LIT> ) , DestBB ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const {


<s> std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , false , false ) ; SDValue FIST = Vals . first , StackSlot = Vals . second ; if ( ! FIST . getNode ( ) ) return Op ; if ( StackSlot . getNode ( ) ) return DAG . getLoad ( Op . getValueType ( ) , SDLoc ( Op ) , FIST , StackSlot , MachinePointerInfo ( ) ) ;


<s> SDValue NewV1 = PromoteMVEPredVector ( dl , V1 , Op1VT , DAG ) ; MVT ElType = getVectorTyFromPredicateVector ( VT ) . getScalarType ( ) . getSimpleVT ( ) ; EVT SubVT = <STR_LIT> ( ElType , NumElts ) ; SDValue SubVec = DAG . getNode ( <STR_LIT> , dl , SubVT ) ; for ( unsigned i = Index , j = <NUM_LIT> ; i < ( Index + NumElts ) ; i ++ , j ++ ) { SDValue Elt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , NewV1 , DAG . getIntPtrConstant ( i , dl ) ) ;

SubVec = DAG . getNode ( <STR_LIT> , dl , SubVT , SubVec , Elt , DAG . getConstant ( j , dl , <STR_LIT> ) ) ;


<s> if ( Amount ) New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Amount ) ; } if ( New ) { New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; } } } else if ( I -> getOpcode ( ) == TII . getCallFrameDestroyOpcode ( ) ) { if ( uint64_t CalleeAmt = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) { MachineInstr & Old = * I ; MachineInstr * New = BuildMI ( MF , Old . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( CalleeAmt ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MBB . insert ( I , New ) ; }


<s> unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ;


<s> SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , <NUM_LIT> , MachineMemOperand :: MONonTemporal | MachineMemOperand :: MOInvariant ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI -> setAdjustsStack ( true ) ; const uint32_t * Mask = Subtarget -> getRegisterInfo ( ) -> getTLSCallPreservedMask ( ) ;

Chain = DAG . getCopyToReg ( Chain , DL , <STR_LIT> , DescAddr , SDValue ( ) ) ;


<s> int64_t CurOffset = - <NUM_LIT> ; for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { CS . setFrameIdx ( MFI . CreateFixedSpillStackObject ( <NUM_LIT> , CurOffset ) ) ; CurOffset -= <NUM_LIT> ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; Align Alignment = TRI -> getSpillAlign ( * RC ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; Alignment = std :: min ( Alignment , getStackAlign ( ) ) ;

CS . setFrameIdx ( MFI . CreateSpillStackObject ( Size , Alignment ) ) ;


<s> unsigned shift_c = <NUM_LIT> / n_elts ; unsigned i ; int hi_val = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < n_elts ; i ++ ) { rtx el = CONST_VECTOR_ELT ( const_vec , i ) ; unsigned HOST_WIDE_INT elpart ; gcc_assert ( CONST_INT_P ( el ) ) ; elpart = INTVAL ( el ) & ( ( <NUM_LIT> << el_prec ) - <NUM_LIT> ) ;

unsigned index = BYTES_BIG_ENDIAN ? n_elts - i - <NUM_LIT> : i ;


<s> int CFGStructurizer < PassT > :: serialPatternMatch ( BlockT * curBlk ) { if ( curBlk -> succ_size ( ) != <NUM_LIT> ) { return <NUM_LIT> ; } BlockT * childBlk = * curBlk -> succ_begin ( ) ; if ( childBlk -> pred_size ( ) != <NUM_LIT> || isActiveLoophead ( childBlk ) ) { return <NUM_LIT> ;


<s> bool <STR_LIT> ( SDValue Op , MVT EltVT , const <ISA_LIT>Subtarget & Subtarget , bool AssumeSingleUse ) {

assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ;


<s> <ISA_LIT>Operand * <ISA_LIT>AsmParser :: DefaultMemDIOperand ( SMLoc Loc ) { unsigned basereg = is64BitMode ( ) ? <STR_LIT> : ( is32BitMode ( ) ? <STR_LIT> : <STR_LIT> ) ; const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; return <STR_LIT> ( <NUM_LIT> , Disp , basereg , <NUM_LIT> , <NUM_LIT> , Loc , Loc , <NUM_LIT> ) ;


<s> return new <ISA_LIT>ExternalSymbolizer ( * Ctx , std :: move ( RelInfo ) , GetOpInfo , SymbolLookUp , DisInfo ) ;


<s> int DataIdx = createsVALUHazard ( MI ) ; return DataIdx >= <NUM_LIT> && TRI -> regsOverlap ( MI . getOperand ( DataIdx ) . getReg ( ) , Reg ) ; } ; int WaitStatesNeededForDef = VALUWaitStates - getWaitStatesSince ( IsHazardFn , VALUWaitStates ) ; WaitStatesNeeded = std :: max ( WaitStatesNeeded , WaitStatesNeededForDef ) ; return WaitStatesNeeded ;


<s> MI = II -> getIterator ( ) ; } if ( ! ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) ) continue ; if ( const auto & MOI = MOA . getLoadInfo ( MI ) ) Changed |= expandLoad ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getStoreInfo ( MI ) ) Changed |= expandStore ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicFenceInfo ( MI ) ) Changed |= expandAtomicFence ( MOI . getValue ( ) , MI ) ; else if ( const auto & MOI = MOA . getAtomicCmpxchgOrRmwInfo ( MI ) ) Changed |= expandAtomicCmpxchgOrRmw ( MOI . getValue ( ) , MI ) ; }


<s> const MCOperand & MO1 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; const MCOperand & MO2 = MI . getOperand ( OpIdx + <NUM_LIT> ) ; unsigned Rn = CTX . getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; unsigned Rm = CTX . getRegisterInfo ( ) . getEncodingValue ( MO1 . getReg ( ) ) ; unsigned ShImm = <STR_LIT> ( MO2 . getImm ( ) ) ;

bool isAdd = <STR_LIT> ( MO2 . getImm ( ) ) == <STR_LIT> ;


<s> const Function * F = MF . getFunction ( ) ; bool OptForSize = F -> hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ;


<s> return ( GET_MODE_SIZE ( from ) == GET_MODE_SIZE ( to ) || ( GET_MODE_SIZE ( from ) <= <NUM_LIT> && GET_MODE_SIZE ( to ) <= <NUM_LIT> ) || ( GET_MODE_SIZE ( from ) >= <NUM_LIT> && GET_MODE_SIZE ( to ) >= <NUM_LIT> ) ) ;


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {

FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> if ( kind1 != kind2 ) return <NUM_LIT> ; if ( ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type2 ) ) ) return <NUM_LIT> ; if ( ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type2 ) ) ) return <NUM_LIT> ; if ( ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type2 ) ) ) return <NUM_LIT> ; if ( ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type1 ) ) != ! lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type2 ) ) ) return <NUM_LIT> ;


<s> static Constant * SegmentOffset ( IRBuilderBase & IRB , int Offset , unsigned AddressSpace ) {

return ConstantExpr :: getIntToPtr ( ConstantInt :: get ( Type :: getInt32Ty ( IRB . getContext ( ) ) , Offset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( AddressSpace ) ) ;


<s> SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { if ( SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ) return Result ; if ( SDValue Result = PerformSHLSimplify ( N , DCI , Subtarget ) ) return Result ; } if ( Subtarget -> isThumb1Only ( ) ) if ( SDValue Result = CombineANDShift ( N , DCI , Subtarget ) ) return Result ;


<s> } } Result = decodeInstruction ( DecoderTableVFPV832 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { Result = decodeInstruction ( DecoderTableNEONDup32 , MI , Insn32 , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { uint32_t NEONLdStInsn = Insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } } if ( fieldFromInstruction ( Insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { uint32_t NEONDataInsn = Insn32 ; NEONDataInsn &= <NUM_LIT> ; NEONDataInsn |= ( NEONDataInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONDataInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTableNEONData32 , MI , NEONDataInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( Result , AddThumbPredicate ( MI ) ) ; return Result ; } uint32_t NEONCryptoInsn = Insn32 ; NEONCryptoInsn &= <NUM_LIT> ; NEONCryptoInsn |= ( NEONCryptoInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONCryptoInsn |= <NUM_LIT> ; Result = decodeInstruction ( DecoderTablev8Crypto32 , MI , NEONCryptoInsn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } uint32_t NEONv8Insn = Insn32 ; NEONv8Insn &= <NUM_LIT> ; Result = decodeInstruction ( DecoderTablev8NEON32 , MI , NEONv8Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; } } Result = decodeInstruction ( DecoderTableThumb2CoProc32 , MI , Insn32 , Address , this , STI ) ;


<s> uint8_t Exp = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; uint8_t Mantissa = Imm & <NUM_LIT> ; uint32_t I = <NUM_LIT> ; I |= Sign << <NUM_LIT> ; I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; I |= ( ( Exp & <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <NUM_LIT> ; I |= ( Exp & <NUM_LIT> ) << <NUM_LIT> ;


<s> return ival <= <NUM_LIT> && ival > <NUM_LIT> && ( ival & ( ival - <NUM_LIT> ) ) == <NUM_LIT> ;


<s> if ( GET_CODE ( x ) == HIGH && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == UNSPEC ) return true ; if ( GET_CODE ( x ) == CONST && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) != <NUM_LIT> ) return true ;

return TARGET_ELF && tls_referenced_p ( x ) ;


<s> static bool arm_legitimate_constant_p_1 ( machine_mode , rtx x ) { if ( GET_CODE ( x ) == CONST_VECTOR && ! neon_make_constant ( x , false ) ) return false ;

return flag_pic || ! label_mentioned_p ( x ) ;


<s> default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; FL = STI -> getFrameLowering ( ) ; bool Modified = false ; for ( MachineBasicBlock & MBB : MF ) Modified |= ExpandMBB ( MBB ) ; return Modified ;


<s> return ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) || ( Opcode == <STR_LIT> ) ;


<s> unsigned getInterleavedMemoryOpCost ( unsigned Opcode , Type * VecTy , unsigned Factor , ArrayRef < unsigned > Indices , unsigned Alignment , unsigned AddressSpace ) { return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace ) ;


<s> void <ISA_LIT>InstPrinter :: printAddrMode3Operand ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; unsigned IdxMode = <STR_LIT> ( MO3 . getImm ( ) ) ; if ( IdxMode == <STR_LIT> ) { printAM3PostIndexOp ( MI , Op , O ) ;


<s> static inline __ev64_opaque__ __ev_set_s16_internal ( __ev64_opaque__ a , int16_t b , uint32_t pos ) { union { __ev64_opaque__ v ;


<s> bool isVecListTwoDAllLanes ( ) const { if ( ! isSingleSpacedVectorAllLanes ( ) ) return false ;

return VectorList . Count == <NUM_LIT> ;


<s> bool isU1Imm ( ) const { return isImm ( <NUM_LIT> , <NUM_LIT> ) ;


<s> tree map_to_integral_tree_type ( tree input_tree_type ) { if ( INTEGRAL_TYPE_P ( TREE_TYPE ( input_tree_type ) ) ) return input_tree_type ;


<s> else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 's' ) { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else { if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } } else if ( SubVer == '6' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { isThumb = true ; if ( NoCPU ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '5' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '4' && Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' ) <ISA_LIT>ArchFeature = <STR_LIT> ; } if ( isThumb ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ; } if ( triple . isOSNaCl ( ) ) { if ( <ISA_LIT>ArchFeature . empty ( ) ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature += <STR_LIT> ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> No<ISA_LIT> = false ; PostRAScheduler = false ; IsR9Reserved = ReserveR9 ; UseMovt = false ; SupportsTailCall = false ; HasFP16 = false ; HasD16 = false ; HasHardwareDivide = false ; HasHardwareDivideIn<ISA_LIT> = false ; HasT2ExtractPack = false ; HasDataBarrier = false ; Pref32BitThumb = false ; AvoidCPSRPartialUpdate = false ; AvoidMOVsShifterOperand = false ; HasRAS = false ; HasMPExtension = false ; HasVirtualization = false ; FPOnlySP = false ; HasPerfMon = false ; HasTrustZone = false ; HasCrypto = false ; HasCRC = false ;


<s> return Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ;


<s> static SDValue lowerShuffleAsInsertPS ( const SDLoc & DL , SDValue V1 , SDValue V2 , ArrayRef < int > Mask , const APInt & Zeroable , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned InsertPSMask = <NUM_LIT> ; if ( ! matchShuffleAsInsertPS ( V1 , V2 , InsertPSMask , Zeroable , Mask , DAG ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 , DAG . getTargetConstant ( InsertPSMask , DL , <STR_LIT> ) ) ;


<s> Triple TheTriple ( TT ) ; if ( TheTriple . isOSDarwin ( ) || TheTriple . getEnvironment ( ) == Triple :: MachO ) return new Darwin<ISA_LIT>_64AsmBackend ( T , CPU ) ;

if ( TheTriple . isOSWindows ( ) && TheTriple . getEnvironment ( ) != Triple :: ELF ) return new Windows<ISA_LIT>AsmBackend ( T , true , CPU ) ;


<s> SDNode * User = * UI ; if ( User -> getOpcode ( ) != <STR_LIT> || UI . getUse ( ) . getResNo ( ) != Addr . getResNo ( ) ) continue ; if ( User -> isPredecessorOf ( LD ) || LD -> isPredecessorOf ( User ) ) continue ; if ( User -> isPredecessorOf ( Vector . getNode ( ) ) ) continue ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint32_t IncVal = CInc -> getZExtValue ( ) ; unsigned NumBytes = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; if ( IncVal != NumBytes ) continue ; Inc = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; } SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( LD -> getOperand ( <NUM_LIT> ) ) ; if ( IsLaneOp ) { Ops . push_back ( Vector ) ; Ops . push_back ( N -> getOperand ( <NUM_LIT> ) ) ; } Ops . push_back ( Addr ) ; Ops . push_back ( Inc ) ; EVT Tys [ <NUM_LIT> ] = { VT , <STR_LIT> , <STR_LIT> } ; SDVTList SDTys = DAG . getVTList ( Tys ) ; unsigned NewOp = IsLaneOp ? <STR_LIT> : <STR_LIT> ; SDValue UpdN = DAG . getMemIntrinsicNode ( NewOp , SDLoc ( N ) , SDTys , Ops , MemVT , LoadSDN -> getMemOperand ( ) ) ; std :: vector < SDValue > NewResults ; NewResults . push_back ( SDValue ( LD , <NUM_LIT> ) ) ; NewResults . push_back ( SDValue ( UpdN . getNode ( ) , <NUM_LIT> ) ) ; DCI . CombineTo ( LD , NewResults ) ; DCI . CombineTo ( N , SDValue ( UpdN . getNode ( ) , <NUM_LIT> ) ) ; DCI . CombineTo ( User , SDValue ( UpdN . getNode ( ) , <NUM_LIT> ) ) ; break ;


<s> static void rs6000_xcoff_asm_named_section ( const char * name , unsigned int flags , tree decl ATTRIBUTE_UNUSED ) { int smclass ; static const char * const suffix [ <NUM_LIT> ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( flags & SECTION_EXCLUDE ) smclass = <NUM_LIT> ; else if ( flags & SECTION_DEBUG ) { fprintf ( asm_out_file , <STR_LIT> , name ) ;


<s> MachineBasicBlock :: iterator MBBI = MI ; ++ MBBI ; assert ( MBBI != Entry -> end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) ; MBBI -> eraseFromParent ( ) ; bool RemovedAllMTVRSAVEs = true ; for ( MachineFunction :: iterator I = MF -> begin ( ) , E = MF -> end ( ) ; I != E ; ++ I ) { if ( I -> isReturnBlock ( ) ) { bool FoundIt = false ; for ( MBBI = I -> end ( ) ; MBBI != I -> begin ( ) ; ) { -- MBBI ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { MBBI -> eraseFromParent ( ) ; FoundIt = true ; break ; } } RemovedAllMTVRSAVEs &= FoundIt ; } } if ( RemovedAllMTVRSAVEs ) { MBBI = MI ; assert ( MBBI != Entry -> begin ( ) && <STR_LIT> ) ; -- MBBI ; assert ( MBBI -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Cst = DAG . getTargetConstantFP ( + <NUM_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Cst , Cst , Cst , Cst , Cst , Cst , Cst , Cst } ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ops , <NUM_LIT> ) ; }

return DAG . getNode ( <STR_LIT> , dl , VT , Vec ) ;


<s> if ( PI2 != MBB -> pred_end ( ) ) return false ; if ( ! Pred -> isLayoutSuccessor ( MBB ) ) return false ; if ( Pred -> empty ( ) ) return true ; MachineBasicBlock :: const_iterator I = Pred -> end ( ) ; while ( I != Pred -> begin ( ) && ! ( -- I ) -> getDesc ( ) . isTerminator ( ) ) ; return ! I -> getDesc ( ) . isBarrier ( ) ;


<s> return ( __m128i ) __builtin_ia32_compressdi128_mask ( ( __v2di ) __A , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 ) __U ) ;


<s> bool arrayed = imgType -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ;

return arrayed ? numComps + <NUM_LIT> : numComps ;


<s> if ( Subtarget -> hasV6T2Ops ( ) && isUInt < <NUM_LIT> > ( CI -> getZExtValue ( ) ) ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; unsigned ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( CI -> getZExtValue ( ) ) ) ; return ImmReg ; } if ( VT == <STR_LIT> && Subtarget -> hasV6T2Ops ( ) && CI -> isNegative ( ) ) { unsigned Imm = ( unsigned ) ~ ( CI -> getSExtValue ( ) ) ; bool UseImm = isThumb2 ? ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) : ( <STR_LIT> ( Imm ) != - <NUM_LIT> ) ; if ( UseImm ) { unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; unsigned ImmReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } if ( VT != <STR_LIT> ) return false ; unsigned DestReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ; unsigned Align = DL . getPrefTypeAlignment ( C -> getType ( ) ) ; if ( Align == <NUM_LIT> ) { Align = DL . getTypeAllocSize ( C -> getType ( ) ) ; } unsigned Idx = MCP . getConstantPoolIndex ( C , Align ) ; if ( isThumb2 ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) ) ; else { DestReg = constrainOperandRegClass ( TII . get ( <STR_LIT> ) , DestReg , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , DestReg ) . addConstantPoolIndex ( Idx ) . addImm ( <NUM_LIT> ) ) ;


<s> unsigned FP = <STR_LIT> ; unsigned ZERO = <STR_LIT> ; unsigned ADDu = <STR_LIT> ; const TargetRegisterClass * RC = & <STR_LIT> ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( StackSize == <NUM_LIT> && ! MFI . adjustsStack ( ) ) return ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; TII . adjustStackPtr ( SP , - StackSize , MBB , MBBI ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createDefCfaOffset ( nullptr , - StackSize ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; if ( CSI . size ( ) ) { for ( unsigned i = <NUM_LIT> ; i < CSI . size ( ) ; ++ i ) ++ MBBI ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; { unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , MRI -> getDwarfRegNum ( Reg , <NUM_LIT> ) , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } } }

if ( <ISA_LIT>FI -> callsEhReturn ( ) ) {


<s> SM . onNot ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onOr ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onLShift ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onRShift ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onXor ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onAnd ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SM . onMod ( ) ; } else if ( Name . equals_lower ( <STR_LIT> ) ) { SMLoc OffsetLoc = getTok ( ) . getLoc ( ) ; const MCExpr * Val = nullptr ; StringRef ID ; InlineAsmIdentifierInfo Info ; ParseError = ParseIntelOffsetOperator ( Val , ID , Info , End ) ; if ( ParseError ) return true ; StringRef ErrMsg ; ParseError = SM . onOffset ( Val , OffsetLoc , ID , Info , isParsingInlineAsm ( ) , ErrMsg ) ; if ( ParseError ) return Error ( SMLoc :: getFromPointer ( Name . data ( ) ) , ErrMsg ) ; } else { return false ;


<s> const char * getName ( ) const { return ( Available . getID ( ) == <ISA_LIT>SchedStrategy :: TopQID ) ? <STR_LIT> : <STR_LIT> ;


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override {


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) , TII ( tii ) {


<s> if ( TM . getSubtargetImpl ( ) -> in<ISA_LIT>16Mode ( ) ) return llvm :: create<ISA_LIT>16TargetLowering ( TM ) ;

return llvm :: create<ISA_LIT>SETargetLowering ( TM ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( Reg . Modifiers == - <NUM_LIT> ? <NUM_LIT> : Reg . Modifiers ) ) ;


<s> assert ( isPowerOf2_32 ( SegLen ) ) ; SmallVector < unsigned , <NUM_LIT> > SegList ; if ( SM . MaxSrc == - <NUM_LIT> ) return SegList ; unsigned Shift = Log2_32 ( SegLen ) ; BitVector Segs ( alignTo ( SM . MaxSrc + <NUM_LIT> , SegLen ) >> Shift ) ; for ( int M : SM . Mask ) { if ( M >= <NUM_LIT> ) Segs . set ( M >> Shift ) ; } for ( unsigned B : Segs . set_bits ( ) ) SegList . push_back ( B ) ;


<s> void adds6_0ExtOperands ( MCInst & Inst , unsigned N ) const { addSignedImmOperands ( Inst , N ) ;


<s> O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ;


<s> static DecodeStatus DecodeBranchConditionAlways ( MCInst & MI , uint64_t insn , uint64_t Address , const void * Decoder ) {

return DecodeAS ( MI , insn , Address , Decoder ) ;


return ( __m128i ) __builtin_ia32_vpopcountb_v16qi_mask ( ( __v16qi ) __A , ( __v16qi ) _mm_setzero_si128 ( ) , ( __mmask16 ) __U ) ;


return ( float32x4_t ) __builtin_neon_vrintav4sf ( __a ) ;


<s> static unsigned getMatchingLoType ( const MCAssembler & Asm , const ELFRelocationEntry & Reloc ) { unsigned Type = Reloc . Type ; if ( Type == ELF :: R_MIPS_HI16 ) return ELF :: R_MIPS_LO16 ; if ( Type == ELF :: R_MICROMIPS_HI16 ) return ELF :: R_MICROMIPS_LO16 ; if ( Type == ELF :: R_MIPS16_HI16 ) return ELF :: R_MIPS16_LO16 ; const MCSymbolData & SD = Asm . getSymbolData ( * Reloc . Symbol ) ; if ( MCELF :: GetBinding ( SD ) != ELF :: STB_LOCAL ) return ELF :: R_MIPS_NONE ; if ( Type == ELF :: R_MIPS_GOT16 ) return ELF :: R_MIPS_LO16 ; if ( Type == ELF :: R_MICROMIPS_GOT16 ) return ELF :: R_MICROMIPS_LO16 ;

if ( Type == ELF :: R_MIPS16_GOT16 ) return ELF :: R_MIPS16_LO16 ;


<s> NewMI2 . clearFlag ( MachineInstr :: MIFlag :: NoSWrap ) ; NewMI2 . clearFlag ( MachineInstr :: MIFlag :: NoUWrap ) ; NewMI2 . clearFlag ( MachineInstr :: MIFlag :: IsExact ) ; MachineOperand * OldFlagDef1 = OldMI1 . findRegisterDefOperand ( <STR_LIT> ) ; MachineOperand * OldFlagDef2 = OldMI2 . findRegisterDefOperand ( <STR_LIT> ) ; assert ( ! OldFlagDef1 == ! OldFlagDef2 && <STR_LIT> ) ; if ( ! OldFlagDef1 || ! OldFlagDef2 ) return ; assert ( OldFlagDef1 -> isDead ( ) && OldFlagDef2 -> isDead ( ) && <STR_LIT> ) ; MachineOperand * NewFlagDef1 = NewMI1 . findRegisterDefOperand ( <STR_LIT> ) ; MachineOperand * NewFlagDef2 = NewMI2 . findRegisterDefOperand ( <STR_LIT> ) ; assert ( NewFlagDef1 && NewFlagDef2 && <STR_LIT> ) ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> if ( ! isShifter ( ) ) return false ; <STR_LIT> ST = <STR_LIT> ( Shifter . Val ) ;


<s> else if ( Subtarget . usesFunctionDescriptors ( ) ) prepareDescriptorIndirectCall ( DAG , Callee , Glue , Chain , CallSeqStart , CS , dl , hasNest , Subtarget ) ; else prepareIndirectCall ( DAG , Callee , Glue , Chain , dl ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; buildCallOperands ( Ops , CallConv , dl , isTailCall , isVarArg , isPatchPoint , hasNest , DAG , RegsToPass , Glue , Chain , Callee , SPDiff , Subtarget , isIndirect ) ; if ( isTailCall ) { assert ( ( ( Callee . getOpcode ( ) == <STR_LIT> && cast < RegisterSDNode > ( Callee ) -> getReg ( ) == <STR_LIT> ) || Callee . getOpcode ( ) == <STR_LIT> || Callee . getOpcode ( ) == <STR_LIT> || isa < ConstantSDNode > ( Callee ) ) && <STR_LIT> <STR_LIT> ) ; assert ( CallOpc == <STR_LIT> && <STR_LIT> ) ; DAG . getMachineFunction ( ) . getFrameInfo ( ) . setHasTailCall ( ) ; return DAG . getNode ( CallOpc , dl , <STR_LIT> , Ops ) ; } std :: array < EVT , <NUM_LIT> > ReturnTypes = { { <STR_LIT> , <STR_LIT> } } ;

Chain = DAG . getNode ( CallOpc , dl , ReturnTypes , Ops ) ;


<s> return ( __m512i ) __builtin_ia32_loaddqudi512_mask ( ( const __v8di * ) __P , ( __v8di ) _mm512_setzero_si512 ( ) , ( __mmask8 ) __U ) ;


<s> UseI -> getOperand ( OpIdx ) . setTargetFlags ( <STR_LIT> ) ; } } else if ( UseI -> isCopy ( ) && Register :: isVirtualRegister ( UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) { uncheckUsesOf ( UseI -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI ) ; }


<s> if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; uint16_t Register = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> this -> m_insn_fma_head_map = new hash_map < rtx_insn * , fma_node * > ; this -> m_fma_forests . clear ( ) ;


<s> return ( Ops [ <NUM_LIT> ] << <NUM_LIT> ) | ( Ops [ <NUM_LIT> ] << <NUM_LIT> ) | ( Ops [ <NUM_LIT> ] << <NUM_LIT> ) | ( Ops [ <NUM_LIT> ] << <NUM_LIT> ) | ( Ops [ <NUM_LIT> ] ) ;


<s> if ( MMO -> getAddrSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS_32BIT ) return true ; if ( const Argument * Arg = dyn_cast < Argument > ( Ptr ) ) return <STR_LIT> ( Arg ) ;

const Instruction * I = dyn_cast < Instruction > ( Ptr ) ;


<s> FrameReg = RI -> getFrameRegister ( MF ) ; unsigned OffsetBytes = <NUM_LIT> * ( getStackWidth ( MF ) * <NUM_LIT> ) ; int UpperBound = FI == - <NUM_LIT> ? MFI -> getNumObjects ( ) : FI ; for ( int i = MFI -> getObjectIndexBegin ( ) ; i < UpperBound ; ++ i ) { OffsetBytes = alignTo ( OffsetBytes , MFI -> getObjectAlignment ( i ) ) ; OffsetBytes += MFI -> getObjectSize ( i ) ;

OffsetBytes = alignTo ( OffsetBytes , <NUM_LIT> ) ;


<s> if ( ( scale = SCALE_FOR_INDEX_P ( scale_rtx ) ) == - <NUM_LIT> ) return CRX_INVALID ; break ; default : return CRX_INVALID ; } break ; case POST_INC : case POST_DEC : retval = CRX_POST_INC ; base = XEXP ( addr , <NUM_LIT> ) ; side_effect = addr ; break ; case POST_MODIFY : retval = CRX_POST_INC ; base = XEXP ( addr , <NUM_LIT> ) ; side_effect = XEXP ( addr , <NUM_LIT> ) ; if ( base != XEXP ( side_effect , <NUM_LIT> ) ) return CRX_INVALID ; switch ( GET_CODE ( side_effect ) ) { case PLUS : case MINUS : disp = XEXP ( side_effect , <NUM_LIT> ) ; if ( ! RTX_SIGNED_INT_FITS_N_BITS ( disp , <NUM_LIT> ) ) return CRX_INVALID ; break ; default : return CRX_INVALID ; } break ; default : return CRX_INVALID ; } if ( base && ! crx_addr_reg_p ( base ) ) return CRX_INVALID ; if ( index && ! crx_addr_reg_p ( index ) ) return CRX_INVALID ; out -> base = base ; out -> index = index ; out -> disp = disp ; out -> scale = scale ;


<s> unsigned Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; if ( Reg ) return Reg ;


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Subtarget ( nullptr ) {


<s> return new <ISA_LIT>MCELFStreamer ( Context , std :: move ( MAB ) , OS , std :: move ( CE ) ) ;


<s> if ( Op . isReg ( ) && <STR_LIT> ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; case MCK_MISC : if ( Op . isImm ( ) && <STR_LIT> ( Op ) ) return MCTargetAsmParser :: Match_Success ; break ; }


<s> static __inline __m64 _mm_set1_pi8 ( char __b ) { unsigned int __w = ( unsigned char ) __b << <NUM_LIT> | ( unsigned char ) __b ; unsigned int __i = __w << <NUM_LIT> | __w ;


<s> if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else MO . getExpr ( ) -> print ( O , & MAI ) ;


<s> MachineInstr :: mmo_iterator MMOBegin = MI . memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI . memoperands_end ( ) ; MVT PVT = getPointerTy ( MF -> getDataLayout ( ) ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; const TargetRegisterClass * RC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned Tmp = MRI . createVirtualRegister ( RC ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ; unsigned FP = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SP = RegInfo -> getStackRegister ( ) ; MachineInstrBuilder MIB ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t SPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; unsigned PtrLoadOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned IJmpOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MachineBasicBlock * thisMBB = MBB ; if ( MF -> getMMI ( ) . getModule ( ) -> getModuleFlag ( <STR_LIT> ) ) { thisMBB = emitLongJmpShadowStackFix ( MI , thisMBB ) ; } MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , FP ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) MIB . add ( MI . getOperand ( i ) ) ; MIB . setMemRefs ( MMOBegin , MMOEnd ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrLoadOpc ) , Tmp ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI . getOperand ( i ) , LabelOffset ) ;

else MIB . add ( MI . getOperand ( i ) ) ;


<s> if ( ! AM . isDispAddrType ( ) ) return false ; return isInt ( AM . getDispSize ( ) - <NUM_LIT> , AM . Disp ) ;


<s> SmallVector < SDValue , <NUM_LIT> > Regs ( Node -> op_begin ( ) + <NUM_LIT> , Node -> op_begin ( ) + <NUM_LIT> + NF ) ; SDValue StoreVal = createTuple ( * CurDAG , Regs , NF , LMUL ) ; SmallVector < SDValue , <NUM_LIT> > Operands ; Operands . push_back ( StoreVal ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; if ( IsStrided ) { Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; Operands . push_back ( Node -> getOperand ( <NUM_LIT> + NF ) ) ; } else {