<s> bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MIBHI = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MI . eraseFromParent ( ) ;


<s> if ( write_symbols != NO_DEBUG ) { output_file_directive ( asm_out_file , main_input_filename ) ;

if ( want_version ) aputs ( <STR_LIT> ) ;


<s> CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ; SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ; SDValue PICLabel = DAG . getConstant ( <ISA_LIT>PCLabelIndex , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , Result , PICLabel ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; return ! ( MFI . hasCalls ( ) || ! MRI . reg_nodbg_empty ( <STR_LIT> ) || ! MRI . reg_nodbg_empty ( <STR_LIT> ) || hasFP ( MF ) ) ;


<s> return ( e8_consumed_by_addr_in_p ( consumer , def_reg1 ) || e8_consumed_by_addr_in_p ( consumer , def_reg2 ) ) ; } def_reg = SET_DEST ( PATTERN ( producer ) ) ; break ; case TYPE_LOAD : case TYPE_STORE : case TYPE_LOAD_MULTIPLE : case TYPE_STORE_MULTIPLE : if ( ! post_update_insn_p ( producer ) ) return false ; def_reg = extract_base_reg ( producer ) ; break ; default : gcc_unreachable ( ) ; } return e8_consumed_by_addr_in_p ( consumer , def_reg ) ;


<s> OS << ')' ; } else { getSubExpr ( ) -> print ( OS ) ; switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_LO : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HI : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HA : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHER : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHERA : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHEST : OS << <STR_LIT> ; break ; case VK_<ISA_LIT>_HIGHESTA : OS << <STR_LIT> ; break ;


<s> std :: swap ( asA , asB ) ; std :: swap ( A , B ) ; } if ( asA == <ISA_LIT>AS :: FLAT_ADDRESS && ( asB == <ISA_LIT>AS :: LOCAL_ADDRESS || asB == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ) { const auto * ObjA = getUnderlyingObject ( A . Ptr -> stripPointerCastsAndInvariantGroups ( ) ) ; if ( const LoadInst * LI = dyn_cast < LoadInst > ( ObjA ) ) { if ( LI -> getPointerAddressSpace ( ) == <ISA_LIT>AS :: CONSTANT_ADDRESS ) return NoAlias ;

} else if ( const Argument * Arg = dyn_cast < Argument > ( ObjA ) ) {


<s> return isInt < <NUM_LIT> > ( Imm ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> for ( MachineFunction :: iterator i = MF . begin ( ) , ie = MF . end ( ) ; i != ie ; ++ i ) { unsigned align ; if ( PMFI -> isMethodCacheRegionEntry ( i ) ) { align = MinSubfunctionAlignment ; } else { align = MinBasicBlockAlignment ; } if ( align > i -> getAlignment ( ) ) { i -> setAlignment ( align ) ; Changed = true ;


<s> else if ( DECL_FUNCTION_SPECIFIC_TARGET ( ix86_previous_fndecl ) ) old_tree = DECL_FUNCTION_SPECIFIC_TARGET ( ix86_previous_fndecl ) ; else old_tree = target_option_default_node ; if ( fndecl == NULL_TREE ) { if ( old_tree != target_option_current_node ) ix86_reset_previous_fndecl ( ) ; return ; } tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET ( fndecl ) ; if ( new_tree == NULL_TREE ) new_tree = target_option_default_node ; if ( old_tree != new_tree ) { cl_target_option_restore ( & global_options , TREE_TARGET_OPTION ( new_tree ) ) ; if ( TREE_TARGET_GLOBALS ( new_tree ) ) restore_target_globals ( TREE_TARGET_GLOBALS ( new_tree ) ) ; else if ( new_tree == target_option_default_node ) restore_target_globals ( & default_target_globals ) ; else TREE_TARGET_GLOBALS ( new_tree ) = save_target_globals_default_opts ( ) ; } ix86_previous_fndecl = fndecl ; if ( TARGET_64BIT && ( call_used_regs [ SI_REG ] == ( cfun -> machine -> call_abi == MS_ABI ) ) ) reinit_regs ( ) ;


<s> return ( poly16x8_t ) __builtin_neon_vreinterpretv8hiv2di ( ( int64x2_t ) __a ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Immediate ) ; Op -> Imm . Val = Val ;


<s> return ( int8x16_t ) __builtin_neon_vclsv16qi ( __a ) ;


<s> return create<ISA_LIT>ELFObjectWriter ( OS , is64 , isLittleEndian ( ) , OSABI ) ;


<s> if ( ! isIntrinsic ) return ( Cnt >= <NUM_LIT> && Cnt <= ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) ) ;

if ( Cnt >= - ( isNarrow ? ElementBits / <NUM_LIT> : ElementBits ) && Cnt <= - <NUM_LIT> ) {


<s> void <ISA_LIT>RequirementHandler :: addCapability ( Capability :: Capability toAdd ) { addCapabilities ( { toAdd } ) ;


<s> if ( ! ( ( VT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( VT . is256BitVector ( ) && Subtarget . hasInt256 ( ) ) ) ) return SDValue ( ) ; SDValue X , Y , Mask ; if ( ! matchLogicBlend ( N , X , Y , Mask ) ) return SDValue ( ) ; Mask = peekThroughBitcasts ( Mask ) ; X = peekThroughBitcasts ( X ) ; Y = peekThroughBitcasts ( Y ) ; EVT MaskVT = Mask . getValueType ( ) ; unsigned EltBits = MaskVT . getScalarSizeInBits ( ) ; if ( ! MaskVT . isInteger ( ) || DAG . ComputeNumSignBits ( Mask ) != EltBits ) return SDValue ( ) ; SDLoc DL ( N ) ; if ( X . getValueType ( ) == MaskVT && Y . getValueType ( ) == MaskVT && DAG . getTargetLoweringInfo ( ) . isOperationLegal ( <STR_LIT> , MaskVT ) ) { auto IsNegV = [ ] ( SDNode * N , SDValue V ) { return N -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) == V && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) . getNode ( ) ) ; } ; SDValue V ; if ( IsNegV ( Y . getNode ( ) , X ) ) V = X ; else if ( IsNegV ( X . getNode ( ) , Y ) ) V = Y ; if ( V ) { SDValue SubOp1 = DAG . getNode ( <STR_LIT> , DL , MaskVT , V , Mask ) ; SDValue SubOp2 = Mask ; if ( V == Y ) std :: swap ( SubOp1 , SubOp2 ) ; SDValue Res = DAG . getNode ( <STR_LIT> , DL , MaskVT , SubOp1 , SubOp2 ) ; return DAG . getBitcast ( VT , Res ) ; } } if ( ! Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; MVT BlendVT = VT . is256BitVector ( ) ? <STR_LIT> : <STR_LIT> ; X = DAG . getBitcast ( BlendVT , X ) ; Y = DAG . getBitcast ( BlendVT , Y ) ; Mask = DAG . getBitcast ( BlendVT , Mask ) ;

Mask = DAG . getSelect ( DL , BlendVT , Mask , Y , X ) ;


<s> case <NUM_LIT> : return MCSymbolRefExpr :: VK_None ; case <STR_LIT> : return MCSymbolRefExpr :: VK_GOT ;


<s> PrintExpr ( const HCE :: ExtExpr & E , const <ISA_LIT>RegisterInfo & I ) : Ex ( E ) , HRI ( I ) {


<s> if ( Info . IsFixed ) Res = AssignFn ( ValNo , ValVT , LocVT , LocInfo , Flags , State ) ; else Res = AssignFnVarArg ( ValNo , ValVT , LocVT , LocInfo , Flags , State ) ;

StackSize = State . getNextStackOffset ( ) ;


<s> void <ISA_LIT>TargetLowering :: LowerAsmOperandForConstraint ( SDValue Op , char Letter , bool hasMemory , std :: vector < SDValue > & Ops , SelectionDAG & DAG ) const { SDValue Result ( <NUM_LIT> , <NUM_LIT> ) ; switch ( Letter ) { default : break ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : { ConstantSDNode * CST = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! CST ) return ; unsigned Value = CST -> getZExtValue ( ) ; switch ( Letter ) { default : llvm_unreachable ( <STR_LIT> ) ; case 'I' : if ( ( short ) Value == ( int ) Value ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case 'J' : case 'L' : if ( ( short ) Value == <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case 'K' : if ( ( Value >> <NUM_LIT> ) == <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case 'M' : if ( Value > <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case 'N' : if ( ( int ) Value > <NUM_LIT> && isPowerOf2_32 ( Value ) ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case 'O' : if ( Value == <NUM_LIT> ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; case 'P' : if ( ( short ) - Value == ( int ) - Value ) Result = DAG . getTargetConstant ( Value , Op . getValueType ( ) ) ; break ; } break ; } } if ( Result . getNode ( ) ) { Ops . push_back ( Result ) ; return ; }

TargetLowering :: LowerAsmOperandForConstraint ( Op , Letter , hasMemory , Ops , DAG ) ;


<s> vst1q_u64 ( uint64_t * a , uint64x2_t b ) {

__builtin_aarch64_st1v2di ( ( __builtin_aarch64_simd_di * ) a , ( int64x2_t ) b ) ;


<s> if ( ! MFI . isCalleeSavedInfoValid ( ) ) return false ; const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( auto & CS : CSI ) { if ( <STR_LIT> . contains ( CS . getReg ( ) ) || <STR_LIT> . contains ( CS . getReg ( ) ) ) { assert ( ( Max == std :: numeric_limits < int > :: min ( ) || Max + <NUM_LIT> == CS . getFrameIdx ( ) ) && <STR_LIT> ) ; Min = std :: min ( Min , CS . getFrameIdx ( ) ) ; Max = std :: max ( Max , CS . getFrameIdx ( ) ) ; } }

return Min != std :: numeric_limits < int > :: max ( ) ;


<s> else add_reg_note ( insn , REG_CFA_ADJUST_CFA , gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - <NUM_LIT> ) ) ) ;


return ( mips_fpr_return_fields ( valtype , fields , & has_cxx_zero_width_bf , & has_cxx17_empty_base ) == <NUM_LIT> || has_cxx_zero_width_bf ) ;


<s> if ( Rn == <NUM_LIT> ) return MCDisassembler :: Fail ; default : break ; } if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rn , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> if ( ! HasControlFlow ( MI ) ) return false ; if ( IsDirectBranch ( MI ) ) return false ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Opc = MI . getOpcode ( ) ; unsigned NewOpc = <NUM_LIT> ; switch ( Opc ) { case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } if ( NewOpc ) { MachineInstrBuilder NewMI = BuildMI ( MBB , MBBI , DL , TII -> get ( NewOpc ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; if ( Is64Bit ) { NewMI . addReg ( UseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; } MI . eraseFromParent ( ) ; return true ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { if ( Is64Bit ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) ; if ( Opc == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( UseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ; }

BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( UseZeroBasedSandbox ? <NUM_LIT> : <STR_LIT> ) ;


<s> tree actual = get_argument_type ( argno ) ; if ( actual == error_mark_node ) return NUM_TYPE_SUFFIXES ; for ( unsigned int size_i = <NUM_LIT> ; size_i < MAX_TUPLE_SIZE ; ++ size_i ) for ( unsigned int suffix_i = <NUM_LIT> ; suffix_i < NUM_TYPE_SUFFIXES ; ++ suffix_i ) { vector_type_index type_i = type_suffixes [ suffix_i ] . vector_type ; tree type = acle_vector_types [ size_i ] [ type_i ] ; if ( type && matches_type_p ( type , actual ) ) { if ( size_i + <NUM_LIT> == num_vectors ) return type_suffix_index ( suffix_i ) ;

if ( num_vectors == <NUM_LIT> ) error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl ) ;


<s> bool hasAVX2 ( ) const { return <ISA_LIT>SSELevel >= AVX2 ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) , MCInstLowering ( * this ) { Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> if ( GET_CODE ( src ) == CONST || GET_CODE ( src ) == MEM ) src = XEXP ( src , <NUM_LIT> ) ; else if ( GET_CODE ( src ) == SYMBOL_REF || GET_CODE ( src ) == LABEL_REF || GET_CODE ( src ) == PLUS ) break ;


<s> case NOT : case NEG : case COMPARE : if ( mode == SImode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else if ( mode == DImode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case MULT : if ( mode == SImode ) * total = COSTS_N_INSNS ( <NUM_LIT> ) ; else * total = COSTS_N_INSNS ( <NUM_LIT> ) ; return true ; case DIV :


<s> FunctionPass * createTargetRegisterAllocator ( bool ) override {


<s> if ( hasStackGuardSlotTLS ( Subtarget . getTargetTriple ( ) ) ) { if ( Subtarget . isTargetFuchsia ( ) ) { return SegmentOffset ( IRB , <NUM_LIT> , getAddressSpace ( ) ) ; } else { unsigned Offset = ( Subtarget . is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; return SegmentOffset ( IRB , Offset , getAddressSpace ( ) ) ; } }

return TargetLowering :: getIRStackGuard ( IRB ) ;


<s> if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < ( regs - <NUM_LIT> ) ; ++ i ) {

if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ++ Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> if ( CompareRHS -> getZExtValue ( ) == FalseVal -> getZExtValue ( ) ) Invert = ! Invert ; else if ( CompareRHS -> getZExtValue ( ) != TrueVal -> getZExtValue ( ) ) return false ; auto * NewCCValid = dyn_cast < ConstantSDNode > ( CompareLHS -> getOperand ( <NUM_LIT> ) ) ; auto * NewCCMask = dyn_cast < ConstantSDNode > ( CompareLHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! NewCCValid || ! NewCCMask ) return false ; CCValid = NewCCValid -> getZExtValue ( ) ; CCMask = NewCCMask -> getZExtValue ( ) ; if ( Invert ) CCMask ^= CCValid ; CCReg = CompareLHS -> getOperand ( <NUM_LIT> ) ; return true ; } if ( CompareLHS -> getOpcode ( ) == <STR_LIT> ) { auto * SRACount = dyn_cast < ConstantSDNode > ( CompareLHS -> getOperand ( <NUM_LIT> ) ) ; if ( ! SRACount || SRACount -> getZExtValue ( ) != <NUM_LIT> ) return false ;

auto * SHL = CompareLHS -> getOperand ( <NUM_LIT> ) . getNode ( ) ;


<s> if ( ! GlobalBaseReg ) { getGlobalBaseReg ( ) ;


<s> if ( ! NegN2 ) return SDValue ( ) ; unsigned NewOpcode = negateFMAOpcode ( N -> getOpcode ( ) , false , true , false ) ;

if ( N -> getNumOperands ( ) == <NUM_LIT> ) return DAG . getNode ( NewOpcode , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , NegN2 , N -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( ! SelectAddr ( Op , Op , Op0 , Op1 , Op2 , Op3 , Op4 ) ) return true ; break ; } OutOps . push_back ( Op0 ) ; OutOps . push_back ( Op1 ) ; OutOps . push_back ( Op2 ) ;


<s> static bool rs6000_debug_secondary_memory_needed ( machine_mode mode , reg_class_t from_class , reg_class_t to_class ) { bool ret = rs6000_secondary_memory_needed ( mode , from_class , to_class ) ; fprintf ( stderr , <STR_LIT> <STR_LIT> , ret ? <STR_LIT> : <STR_LIT> , reg_class_names [ from_class ] , reg_class_names [ to_class ] , GET_MODE_NAME ( mode ) ) ; return ret ;


<s> if ( CSI . empty ( ) ) return false ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * ZFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; auto & Regs = Subtarget . getSpecialRegisters < <ISA_LIT>XPLINK64Registers > ( ) ; DebugLoc DL = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { Register Reg = CSI [ I ] . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; if ( <STR_LIT> . contains ( Reg ) ) TII -> loadRegFromStackSlot ( MBB , MBBI , Reg , CSI [ I ] . getFrameIdx ( ) , & <STR_LIT> , TRI ) ; } <STR_LIT> RestoreGPRs = ZFI -> getRestoreGPRRegs ( ) ; if ( RestoreGPRs . LowGPR ) { assert ( isInt < <NUM_LIT> > ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) ) ; if ( RestoreGPRs . LowGPR == RestoreGPRs . HighGPR ) BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , RestoreGPRs . LowGPR ) . addReg ( Regs . getStackPointerRegister ( ) ) . addImm ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) . addReg ( <NUM_LIT> ) ; else { MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) ; MIB . addReg ( RestoreGPRs . LowGPR , RegState :: Define ) ; MIB . addReg ( RestoreGPRs . HighGPR , RegState :: Define ) ; MIB . addReg ( Regs . getStackPointerRegister ( ) ) ; MIB . addImm ( Regs . getStackPointerBias ( ) + RestoreGPRs . GPROffset ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { Register Reg = CSI [ I ] . getReg ( ) ; if ( Reg > RestoreGPRs . LowGPR && Reg < RestoreGPRs . HighGPR ) MIB . addReg ( Reg , RegState :: ImplicitDefine ) ; } }


<s> const MCAsmInfo * MAI = TM -> getMCAsmInfo ( ) ; addPass ( create<ISA_LIT>RetpolineThunksPass ( ) ) ; if ( TT . isOSWindows ( ) && TT . getArch ( ) == Triple :: x86_64 ) addPass ( create<ISA_LIT>AvoidTrailingCallPass ( ) ) ;

if ( ! TT . isOSDarwin ( ) && ( ! TT . isOSWindows ( ) || MAI -> getExceptionHandlingType ( ) == ExceptionHandling :: DwarfCFI ) ) addPass ( createCFIInstrInserter ( ) ) ;


<s> assert ( VA . getLocInfo ( ) != CCValAssign :: FPExt && <STR_LIT> ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) { if ( ValVT == <STR_LIT> ) { if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; if ( ! Subtarget -> hasSSE2 ( ) ) ValToCopy = DAG . getBitcast ( <STR_LIT> , ValToCopy ) ; } } } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( unsigned SRetReg = FuncInfo -> getSRetReturnReg ( ) ) { SDValue Val = DAG . getCopyFromReg ( Chain , dl , SRetReg , getPointerTy ( MF . getDataLayout ( ) ) ) ; unsigned RetValReg = ( Subtarget -> is64Bit ( ) && ! Subtarget -> isTarget64BitILP32 ( ) ) ? <STR_LIT> : <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , dl , RetValReg , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ;

RetOps . push_back ( DAG . getRegister ( RetValReg , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ;


<s> std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) . getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: AddrSpaceCast : { PointerType * DstTy = cast < PointerType > ( CE -> getType ( ) ) ; if ( DstTy -> getAddressSpace ( ) == <NUM_LIT> ) { return lowerConstantForGV ( cast < const Constant > ( CE -> getOperand ( <NUM_LIT> ) ) , true ) ; } std :: string S ; raw_string_ostream OS ( S ) ; OS << <STR_LIT> ; CE -> printAsOperand ( OS , false , ! MF ? nullptr : MF -> getFunction ( ) . getParent ( ) ) ; report_fatal_error ( OS . str ( ) ) ; } case Instruction :: GetElementPtr : { const DataLayout & DL = getDataLayout ( ) ; APInt OffsetAI ( DL . getPointerTypeSizeInBits ( CE -> getType ( ) ) , <NUM_LIT> ) ; cast < GEPOperator > ( CE ) -> accumulateConstantOffset ( DL , OffsetAI ) ; const MCExpr * Base = lowerConstantForGV ( CE -> getOperand ( <NUM_LIT> ) , ProcessingGeneric ) ; if ( ! OffsetAI ) return Base ; int64_t Offset = OffsetAI . getSExtValue ( ) ; return MCBinaryExpr :: createAdd ( Base , MCConstantExpr :: create ( Offset , Ctx ) , Ctx ) ; }


<s> void addModImmNotOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> return false ; } if ( pConfig . targets ( ) . triple ( ) . isOSWindows ( ) ) { assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> SDNodeFlags Flags ; Flags . setAllowReassociation ( true ) ; for ( int i = ExtraSteps ; i > <NUM_LIT> ; -- i ) { SDValue Step = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Estimate , Flags ) ; Step = DAG . getNode ( <STR_LIT> , DL , VT , Operand , Step , Flags ) ; Estimate = DAG . getNode ( <STR_LIT> , DL , VT , Estimate , Step , Flags ) ;


<s> static <ISA_LIT>Operand :: Ptr CreateImm ( const <ISA_LIT>AsmParser * AsmParser , int64_t Val , SMLoc Loc , ImmTy Type = ImmTyNone , bool IsFPImm = false ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( Immediate , AsmParser ) ; Op -> Imm . Val = Val ; Op -> Imm . IsFPImm = IsFPImm ; Op -> Imm . Type = Type ; Op -> Imm . Mods = Modifiers ( ) ; Op -> StartLoc = Loc ;


<s> unsigned HOST_WIDE_INT v = value > <NUM_LIT> ? value : - value ; int sz = GET_MODE_SIZE ( mode ) ; int shift = sz == <NUM_LIT> ? <NUM_LIT> : sz == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; unsigned HOST_WIDE_INT mask = sz == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ;

return ( v & ~ ( mask << shift ) ) == <NUM_LIT> ;


<s> addPass ( createSPSchedulerPass ( get<ISA_LIT>TargetMachine ( ) ) ) ; } else { if ( getOptLevel ( ) != CodeGenOpt :: None && ! DisableIfConverter ) { addPass ( & IfConverterID ) ; addPass ( & UnreachableMachineBlockElimID ) ; } } addPass ( create<ISA_LIT>StackCacheAnalysisInfo ( get<ISA_LIT>TargetMachine ( ) ) ) ; if ( EnableStackCacheAnalysis ) { addPass ( create<ISA_LIT>StackCacheAnalysis ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; break ; case <STR_LIT> : case <STR_LIT> : break ; } DecodeGPR64RegisterClass ( Inst , Rt , Addr , Decoder ) ; DecodeGPR64spRegisterClass ( Inst , Rn , Addr , Decoder ) ; DecodeSImm < <NUM_LIT> > ( Inst , offset , Addr , Decoder ) ; if ( writeback && Rt == Rn && Rn != <NUM_LIT> ) {


<s> if ( Desc . getOpcode ( ) == <STR_LIT> ) Size += GetInstSizeWithDesc ( * MI , & get ( <STR_LIT> ) , IsPIC , Is64BitMode ) ;


<s> } case <STR_LIT> : { if ( SDValue Res = lowerEXTRACT_VECTOR_ELT ( SDValue ( N , <NUM_LIT> ) , DAG ) ) Results . push_back ( Res ) ; return ; } case <STR_LIT> : { unsigned IID = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( IID ) { case <STR_LIT> : { SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc SL ( N ) ; SDValue Cvt = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src0 , Src1 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cvt ) ) ; return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = N -> getOperand ( <NUM_LIT> ) ; SDLoc SL ( N ) ; unsigned Opcode ; if ( IID == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( IID == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( IID == <STR_LIT> ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( isTypeLegal ( VT ) ) Results . push_back ( DAG . getNode ( Opcode , SL , VT , Src0 , Src1 ) ) ; else { SDValue Cvt = DAG . getNode ( Opcode , SL , <STR_LIT> , Src0 , Src1 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Cvt ) ) ; } return ; } } break ; } case <STR_LIT> : {

if ( SDValue Res = LowerINTRIN<ISA_LIT>C_W_CHAIN ( SDValue ( N , <NUM_LIT> ) , DAG ) ) {


<s> if ( ! Strict ) return <NUM_LIT> <= StreamId && isUInt < STREAM_ID_WIDTH_ > ( StreamId ) ; switch ( MsgId ) { case ID_GS : return STREAM_ID_FIRST_ <= StreamId && StreamId < STREAM_ID_LAST_ ; case ID_GS_DONE : return ( OpId == OP_GS_NOP ) ? ( StreamId == STREAM_ID_NONE_ ) :

( STREAM_ID_FIRST_ <= StreamId && StreamId < STREAM_ID_LAST_ ) ;


<s> static rtx nios2_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type ATTRIBUTE_UNUSED , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; rtx return_rtx = NULL_RTX ; if ( cum -> regs_used < NUM_ARG_REGS ) return_rtx = gen_rtx_REG ( mode , FIRST_ARG_REGNO + cum -> regs_used ) ; return return_rtx ;


<s> unsigned PtrStoreOpc = <NUM_LIT> ; unsigned LabelReg = <NUM_LIT> ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; Reloc :: Model RM = MF -> getTarget ( ) . getRelocationModel ( ) ; bool UseImmLabel = ( MF -> getTarget ( ) . getCodeModel ( ) == CodeModel :: Small ) && ( RM == Reloc :: Static || RM == Reloc :: DynamicNoPIC ) ; if ( ! UseImmLabel ) { PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; LabelReg = MRI . createVirtualRegister ( PtrRC ) ; if ( Subtarget -> is64Bit ( ) ) { MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB ) . addReg ( <NUM_LIT> ) ; } else { const <ISA_LIT>InstrInfo * XII = static_cast < const <ISA_LIT>InstrInfo * > ( TII ) ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) , LabelReg ) . addReg ( XII -> getGlobalBaseReg ( MF ) ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( restoreMBB , Subtarget -> ClassifyBlockAddressReference ( ) ) . addReg ( <NUM_LIT> ) ; } } else PtrStoreOpc = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( PtrStoreOpc ) ) ; for ( unsigned i = <NUM_LIT> ; i < <STR_LIT> ; ++ i ) { if ( i == <STR_LIT> ) MIB . addDisp ( MI -> getOperand ( MemOpndSlot + i ) , LabelOffset ) ; else MIB . addOperand ( MI -> getOperand ( MemOpndSlot + i ) ) ; } if ( ! UseImmLabel ) MIB . addReg ( LabelReg ) ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> int fr30_const_double_is_zero ( rtx operand ) { REAL_VALUE_TYPE d ; if ( operand == NULL || GET_CODE ( operand ) != CONST_DOUBLE ) return <NUM_LIT> ; REAL_VALUE_FROM_CONST_DOUBLE ( d , operand ) ; return REAL_VALUES_EQUAL ( d , dconst0 ) ;


<s> virtual const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {


<s> return lowerToTLSGeneralDynamicModel ( Op , DAG ) ;


<s> static HOST_WIDE_INT cris_preferred_minimum_alignment ( void ) { if ( ! TARGET_CONST_ALIGN ) return <NUM_LIT> ; if ( TARGET_ALIGN_BY_32 ) return <NUM_LIT> ;


<s> Mem = CurDAG -> getTargetConstant ( Val , SDLoc ( N ) , <STR_LIT> ) ; return true ; } case <STR_LIT> : { Mem = N -> getOperand ( <NUM_LIT> ) ; return true ; }


<s> int branch_dest ( rtx branch ) { rtx pat = PATTERN ( branch ) ;

rtx dest = ( GET_CODE ( pat ) == PARALLEL ? SET_SRC ( XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ) : SET_SRC ( pat ) ) ;


<s> unsigned BrOffset = getOffsetOf ( MI ) + PCAdj ; unsigned DestOffset = BBInfo [ DestBB -> getNumber ( ) ] . Offset ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * MI -> getParent ( ) ) << <STR_LIT> << MaxDisp << <STR_LIT> << getOffsetOf ( MI ) << <STR_LIT> << DestOffset << <STR_LIT> << int ( DestOffset - BrOffset ) << <STR_LIT> << * MI ) ; if ( BrOffset <= DestOffset ) {

if ( DestOffset - BrOffset <= MaxDisp ) return true ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( StackDirection D , Align StackAl , int LAO , Align TransAl , bool StackReal ) : TargetFrameLowering ( D , StackAl , LAO , TransAl , StackReal ) {


<s> store_reg ( i , offset , HARD_FRAME_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; gr_saved ++ ; } gr_saved ++ ; } else { offset = local_fsize - actual_fsize ; if ( DO_FRAME_NOTES && crtl -> calls_eh_return ) { unsigned int i , regno ; for ( i = <NUM_LIT> ; ; ++ i ) { regno = EH_RETURN_DATA_REGNO ( i ) ; if ( regno == INVALID_REGNUM ) break ; if ( merge_sp_adjust_with_store ) { store_reg_modify ( STACK_POINTER_REGNUM , regno , - offset ) ; merge_sp_adjust_with_store = <NUM_LIT> ; } else store_reg ( regno , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; } } for ( i = <NUM_LIT> ; i >= <NUM_LIT> ; i -- ) if ( df_regs_ever_live_p ( i ) && ! call_used_or_fixed_reg_p ( i ) ) { if ( merge_sp_adjust_with_store ) { store_reg_modify ( STACK_POINTER_REGNUM , i , - offset ) ; merge_sp_adjust_with_store = <NUM_LIT> ; } else store_reg ( i , offset , STACK_POINTER_REGNUM ) ; offset += UNITS_PER_WORD ; gr_saved ++ ; } if ( merge_sp_adjust_with_store ) set_reg_plus_d ( STACK_POINTER_REGNUM , STACK_POINTER_REGNUM , actual_fsize , <NUM_LIT> ) ; } if ( flag_pic && actual_fsize != <NUM_LIT> && ! TARGET_64BIT ) { rtx addr = gen_rtx_PLUS ( word_mode , stack_pointer_rtx , GEN_INT ( - <NUM_LIT> ) ) ; emit_move_insn ( gen_rtx_MEM ( word_mode , addr ) , pic_offset_table_rtx ) ; } offset = ( offset + <NUM_LIT> ) & ~ <NUM_LIT> ; if ( save_fregs ) { rtx base ; if ( frame_pointer_needed ) { set_reg_plus_d ( <NUM_LIT> , HARD_FRAME_POINTER_REGNUM , offset , <NUM_LIT> ) ; base = hard_frame_pointer_rtx ; } else { set_reg_plus_d ( <NUM_LIT> , STACK_POINTER_REGNUM , offset , <NUM_LIT> ) ; base = stack_pointer_rtx ; } for ( i = FP_SAVED_REG_LAST ; i >= FP_SAVED_REG_FIRST ; i -= FP_REG_STEP ) { if ( df_regs_ever_live_p ( i ) || ( ! TARGET_64BIT && df_regs_ever_live_p ( i + <NUM_LIT> ) ) ) { rtx addr , reg ; rtx_insn * insn ; addr = gen_rtx_MEM ( DFmode , gen_rtx_POST_INC ( word_mode , tmpreg ) ) ; reg = gen_rtx_REG ( DFmode , i ) ; insn = emit_move_insn ( addr , reg ) ; if ( DO_FRAME_NOTES ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; if ( TARGET_64BIT ) { rtx mem = gen_rtx_MEM ( DFmode , plus_constant ( Pmode , base , offset ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( mem , reg ) ) ; } else {

rtx meml = gen_rtx_MEM ( SFmode , plus_constant ( Pmode , base , offset ) ) ;


<s> void <ISA_LIT>TargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; SmallDataSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) ) ;

SmallBSSSection = getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_NOBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getBSS ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printLdStmModeOperand ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { <STR_LIT> Mode = <STR_LIT> ( MI -> getOperand ( OpNum ) . getImm ( ) ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = MF . getDataLayout ( ) ; const Function & F = * MF . getFunction ( ) ; ArgInfo OrigArg { VReg , Val -> getType ( ) } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; if ( ! splitToValueTypes ( OrigArg , SplitArgs , DL , MRI , [ & ] ( ArrayRef < unsigned > Regs ) { MIRBuilder . buildUnmerge ( Regs , VReg ) ; } ) ) return false ; FuncReturnHandler Handler ( MIRBuilder , MRI , MIB , RetCC_<ISA_LIT> ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ;


<s> break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>32R6 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R2 ( ) ; break ; case <STR_LIT> : selectArch ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveSet<ISA_LIT>64R6 ( ) ; break ; }


<s> bool got_really_used = false ; if ( ! reload_completed || frame_pointer_needed || get_frame_size ( ) != <NUM_LIT> || current_function_pretend_args_size || current_function_args_size || current_function_outgoing_args_size || current_function_calls_eh_return || ! TARGET_PROLOGUE_EPILOGUE ) return false ; if ( current_function_uses_pic_offset_table ) { push_topmost_sequence ( ) ; got_really_used = reg_used_between_p ( pic_offset_table_rtx , get_insns ( ) , NULL_RTX ) ; pop_topmost_sequence ( ) ; }

for ( regno = <NUM_LIT> ; regno < reglimit ; regno ++ ) if ( cris_reg_saved_in_regsave_area ( regno , got_really_used ) ) return false ;


<s>
while
(
StrStartIndex
<
NumOps
)
{
if
(
MI
->
getOperand
(
StrStartIndex
)
.
isReg
(
)
)
break
;
std
::
string
Str
=
get<ISA_LIT>StringOperand
(
*
MI
,
OpNo
)
;
if
(
StrStartIndex
!=
OpNo
)
O
<<
' '
;
O
<<
'"'
;
for
(
char
c
:
Str
)
{
if
(
c
==
'"'
)
O
.
write
(
'\\'
)
;
O
.
write
(
c
)
;
}
O
<<
'"'
;
unsigned
numOpsInString
=
(
Str
.
size
(
)
/
<NUM_LIT>
)
+
<NUM_LIT>
;
StrStartIndex
+=
numOpsInString
;
if
(
MI
->
getOpcode
(
)
==
<STR_LIT>
&&
MI
->
getOperand
(
<NUM_LIT>
)
.
getImm
(
)
==
Decoration
::
LinkageAttributes
)
{
O
<<
' '
;

printSymbolicOperand < OperandCategory :: LinkageTypeOperand > ( MI , StrStartIndex , O ) ;


<s> unsigned <ISA_LIT>Disassembler :: getVgprClassId ( const OpWidthTy Width ) const { using namespace <ISA_LIT> ; assert ( OPW_FIRST_ <= Width && Width < OPW_LAST_ ) ; switch ( Width ) { default : case OPW32 : return VGPR_32RegClassID ; case OPW64 : return VReg_64RegClassID ; case OPW128 : return VReg_128RegClassID ; }


<s> getTargetStreamer ( ) . emitTextAttribute ( <STR_LIT> , CPU ) ; if ( ! getSTI ( ) . isCPUStringValid ( CPU ) ) { Error ( L , <STR_LIT> ) ;


<s> return create<ISA_LIT>AsmBackend ( T , STI , MRI , Options , true ) ;


<s> <ISA_LIT>FTAOElim ( ) : MachineFunctionPass ( ID ) {


<s> case <STR_LIT> : hiOpc = <STR_LIT> ; break ; case <STR_LIT> : hasChain = true ; break ; case <STR_LIT> : hiOpc = <STR_LIT> ; break ; case <STR_LIT> : hasChain = true ; break ; } SDValue Lo ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; if ( hasChain ) { Lo = DAG . getNode ( Op . getOpcode ( ) , dl , VTs , Src1Lo , Src2Lo , Op . getOperand ( <NUM_LIT> ) ) ; } else { Lo = DAG . getNode ( Op . getOpcode ( ) , dl , VTs , Src1Lo , Src2Lo ) ; } SDValue Hi = DAG . getNode ( hiOpc , dl , VTs , Src1Hi , Src2Hi , Lo . getValue ( <NUM_LIT> ) ) ; SDValue Carry = Hi . getValue ( <NUM_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi ) ; Hi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Dst = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Hi , Lo ) ;

SDValue Ops [ <NUM_LIT> ] = { Dst , Carry } ;


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo , Args , CxtI ) ; InstructionCost Cost = BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Op1Info , Op2Info , Opd1PropInfo , Opd2PropInfo ) ; return vectorCostAdjustment ( Cost , Opcode , Ty , nullptr ) ;


<s> bool <ISA_LIT>AnnotateUniformValues :: runOnFunction ( Function & F ) { if ( skipFunction ( F ) ) return false ; DA = & getAnalysis < LegacyDivergenceAnalysis > ( ) ; MSSA = & getAnalysis < MemorySSAWrapperPass > ( ) . getMSSA ( ) ; isEntryFunc = <STR_LIT> ( F . getCallingConv ( ) ) ; visit ( F ) ; noClobberClones . clear ( ) ; return true ;


<s> static void spu_conditional_register_usage ( void ) { if ( flag_pic ) {


<s> x = emit_insn ( gen_movsi_pop ( gen_rtx_REG ( Pmode , regno ) , stack_pointer_rtx ) ) ; add_reg_note ( x , REG_INC , stack_pointer_rtx ) ;


<s> Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( ) ) ; auto * RBI = new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ; InstSelector . reset ( create<ISA_LIT>InstructionSelector ( * static_cast < const <ISA_LIT>TargetMachine * > ( & TM ) , * this , * RBI ) ) ;


<s> default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SmallSet < uint16_t , <NUM_LIT> > Uses ; for ( unsigned i = <NUM_LIT> , e = MBBI -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MBBI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isDef ( ) ) continue ; unsigned Reg = MO . getReg ( ) ;


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( <STR_LIT> ( <STR_LIT> , NrBitsToZero ) ) . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ; } } else { assert ( CanUseBFC ) ;

BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addImm ( ~ AlignMask ) . add ( predOps ( <STR_LIT> ) ) ;


<s> ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregxiv8qi ( __o , <NUM_LIT> ) ; return ret ;


<s> bool <ISA_LIT>PromoteKernelArguments :: runOnFunction ( Function & F ) {

MemorySSA & MSSA = getAnalysis < MemorySSAWrapperPass > ( ) . getMSSA ( ) ;


<s> static void printExpr ( const MCExpr * Expr , raw_ostream & OS ) { int Offset = <NUM_LIT> ; const MCSymbolRefExpr * SRE ; if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { SRE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ;


<s> std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TT , CPU ) ; if ( ! FS . empty ( ) ) {

if ( ! ArchFS . empty ( ) ) ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ;


crtl -> stack_realign_finalized = true ;


<s> return isAmdHsaOS ( ) || isMesaKernel ( F ) ;


<s> ++ Count ; break ; case <STR_LIT> : BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; ++ Count ; break ; default : { unsigned Opc = GetCondBranchFromCond ( CC ) ; BuildMI ( & MBB , DL , get ( Opc ) ) . addMBB ( TBB ) ; ++ Count ; } } if ( FBB ) {

BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> tree bits = build_int_cst ( unsigned_type_node , shift ) ; tree kind = build_int_cst ( unsigned_type_node , SHUFFLE_DOWN ) ; tree expr ; if ( var_type != dest_type ) { tree real = fold_build1 ( REALPART_EXPR , var_type , var ) ; real = fold_build1 ( code , arg_type , real ) ; real = build_call_expr_loc ( loc , call , <NUM_LIT> , real , bits , kind ) ; real = fold_build1 ( code , var_type , real ) ; tree imag = fold_build1 ( IMAGPART_EXPR , var_type , var ) ; imag = fold_build1 ( code , arg_type , imag ) ; imag = build_call_expr_loc ( loc , call , <NUM_LIT> , imag , bits , kind ) ; imag = fold_build1 ( code , var_type , imag ) ; expr = fold_build2 ( COMPLEX_EXPR , dest_type , real , imag ) ; } else { expr = fold_build1 ( code , arg_type , var ) ; expr = build_call_expr_loc ( loc , call , <NUM_LIT> , expr , bits , kind ) ; expr = fold_build1 ( code , dest_type , expr ) ; } gimplify_assign ( dest_var , expr , seq ) ;


if ( GET_CODE ( x ) == PLUS && rtx_equal_p ( XEXP ( x , <NUM_LIT> ) , rgp ) ) iter . skip_subrtxes ( ) ;


<s> static bool hasVariantSymbol ( const MCInst & MI ) { for ( auto & Operand : MI ) {

if ( ! Operand . isExpr ( ) ) continue ;


<s> auto Op = make_unique < <ISA_LIT>Operand > ( Expression ) ; Op -> Expr . Val = Val ; Op -> Expr . CRVal = EvaluateCRExpr ( Val ) ; Op -> StartLoc = S ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; Register FrameReg = RI . getFrameRegister ( MF ) ; int XLenInBytes = Subtarget . getXLen ( ) / <NUM_LIT> ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , FrameReg , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { int Offset = - ( XLenInBytes * <NUM_LIT> ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ;

FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) ) ;


<s> rtx op = GEN_INT ( mask | ( is_call << GOMP_DIM_MAX ) ) ;

if ( ! is_call ) emit_insn ( gen_nvptx_fork ( op ) ) ;


<s> instr -> getOperand ( <NUM_LIT> ) . setMBB ( blk ) ;


<s> SmallVector < Instruction * , <NUM_LIT> > StructStoreWorkList ; for ( auto I = inst_begin ( F ) , E = inst_end ( F ) ; I != E ; ++ I ) { if ( isVectorLibCall ( & * I ) ) VectorWorkList . push_back ( & * I ) ; else if ( isMemLibCall ( & * I ) ) MemWorkList . push_back ( & * I ) ; else if ( isStructMemOp < LoadInst > ( & * I ) ) StructLoadWorkList . push_back ( & * I ) ; else if ( isStructMemOp < StoreInst > ( & * I ) ) StructStoreWorkList . push_back ( & * I ) ; } for ( auto I : VectorWorkList ) Changed |= ExpandCallToLoop ( cast < IntrinsicInst > ( I ) ) ; for ( auto I : MemWorkList ) Changed |= ExpandMemCallToLoop ( cast < MemIntrinsic > ( I ) ) ; for ( auto I : StructLoadWorkList ) Changed |= ExpandStructLoad ( cast < LoadInst > ( I ) ) ; for ( auto I : StructStoreWorkList ) Changed |= ExpandStructStore ( cast < StoreInst > ( I ) ) ; return Changed ;


<s> SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; EVT VT = Op . getValueType ( ) ; SDValue Overflow = DAG . getNode ( <STR_LIT> , dl , VT , TVal , FVal , <ISA_LIT>cc , CCR , OverflowCmp ) ;

SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ;


<s> if ( is256BitLaneRepeatedShuffleMask ( <STR_LIT> , Mask , Repeated256Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Repeated256Mask , DL , DAG ) ) ; } if ( SDValue Shuf128 = lowerV4X128VectorShuffle ( DL , <STR_LIT> , Mask , Zeroable , V1 , V2 , Subtarget , DAG ) ) return Shuf128 ; if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ;

if ( SDValue Blend = lowerVectorShuffleAsBlend ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Blend ;


<s> unsigned NumLaneElems = NumElems / NumLanes ; if ( NumLaneElems != <NUM_LIT> && NumLaneElems != <NUM_LIT> ) return false ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; bool symetricMaskRequired = ( VT . getSizeInBits ( ) >= <NUM_LIT> ) && ( EltSize == <NUM_LIT> ) ; SmallVector < int , <NUM_LIT> > MaskVal ( NumLaneElems , - <NUM_LIT> ) ; unsigned HalfLaneElems = NumLaneElems / <NUM_LIT> ; for ( unsigned l = <NUM_LIT> ; l != NumElems ; l += NumLaneElems ) { for ( unsigned i = <NUM_LIT> ; i != NumLaneElems ; ++ i ) { int Idx = Mask [ i + l ] ; unsigned RngStart = l + ( ( Commuted == ( i < HalfLaneElems ) ) ? NumElems : <NUM_LIT> ) ; if ( ! isUndefOrInRange ( Idx , RngStart , RngStart + NumLaneElems ) ) return false ;

if ( ! symetricMaskRequired || Idx < <NUM_LIT> ) continue ;


<s> DebugLoc DL ; if ( MBBI != MBB . end ( ) ) DL = MBBI -> getDebugLoc ( ) ; if ( Subtarget . hasPA ( ) && MBBI != MBB . end ( ) && MBBI -> getOpcode ( ) == <STR_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( MFI . shouldSignWithBKey ( ) ? <STR_LIT> : <STR_LIT> ) ) . copyImplicitOps ( * MBBI ) ; MBB . erase ( MBBI ) ; } else {

BuildMI ( MBB , MBBI , DL , TII -> get ( MFI . shouldSignWithBKey ( ) ? <STR_LIT> : <STR_LIT> ) ) . setMIFlag ( MachineInstr :: FrameDestroy ) ;


<s> if ( Src . getValueType ( ) . bitsGT ( <STR_LIT> ) ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; else Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; Entry . Node = Src ; Entry . Ty = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; Entry . isSExt = true ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( Chain , Type :: getVoidTy ( * DAG . getContext ( ) ) , false , false , false , false , <NUM_LIT> , TLI . getLibcallCallingConv ( RTLIB :: MEMSET ) , false , false , false , DAG . getExternalSymbol ( TLI . getLibcallName ( RTLIB :: MEMSET ) , TLI . getPointerTy ( ) ) , Args , DAG , dl ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ;


<s> return ( const <ISA_LIT>TargetObjectFile & ) AsmPrinter :: getObjFileLowering ( ) ;


<s> static void adjustBranch ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) {

unsigned_width ( Size + <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ;


<s> static bool virtual_stack_registers_memory_p ( rtx op ) { int regnum ; if ( GET_CODE ( op ) == REG ) regnum = REGNO ( op ) ; else if ( GET_CODE ( op ) == PLUS && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == REG && GET_CODE ( XEXP ( op , <NUM_LIT> ) ) == CONST_INT ) regnum = REGNO ( XEXP ( op , <NUM_LIT> ) ) ; else return false ; return ( regnum >= FIRST_VIRTUAL_REGISTER && regnum <= LAST_VIRTUAL_POINTER_REGISTER ) ;


<s> static int eco32_return_pops_args ( tree fundecl ATTRIBUTE_UNUSED , tree funtype ATTRIBUTE_UNUSED , int size ATTRIBUTE_UNUSED ) { return <NUM_LIT> ;


<s> DebugLoc DL ; determineFrameLayout ( MF ) ; unsigned StackSize = MFI -> getStackSize ( ) ; BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) . addImm ( LPAC :: makePreOp ( LPAC :: ADD ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;

BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> C . initLRU ( TRI ) ; if ( C . LRU . available ( <STR_LIT> ) ) { NumBytesNoStackCalls += <NUM_LIT> ; C . setCallInfo ( MachineOutlinerNoLRSave , <NUM_LIT> ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( findRegisterToSaveLRTo ( C ) ) { NumBytesNoStackCalls += <NUM_LIT> ; C . setCallInfo ( MachineOutlinerRegSave , <NUM_LIT> ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else if ( C . UsedInSequence . available ( <STR_LIT> ) ) { NumBytesNoStackCalls += <NUM_LIT> ; C . setCallInfo ( MachineOutlinerDefault , <NUM_LIT> ) ; CandidatesWithoutStackFixups . push_back ( C ) ; } else { NumBytesNoStackCalls += SequenceSize ; } } if ( ! AllStackInstrsSafe || NumBytesNoStackCalls <= RepeatedSequenceLocs . size ( ) * <NUM_LIT> ) { RepeatedSequenceLocs = CandidatesWithoutStackFixups ; FrameID = MachineOutlinerNoLRSave ; } else { SetCandidateCallInfo ( MachineOutlinerDefault , <NUM_LIT> ) ; } if ( RepeatedSequenceLocs . size ( ) < <NUM_LIT> ) { RepeatedSequenceLocs . clear ( ) ; return outliner :: OutlinedFunction ( ) ; } } if ( FlagsSetInAll & MachineOutlinerMBBFlags :: HasCalls ) { bool ModStackToSaveLR = false ; if ( std :: any_of ( FirstCand . front ( ) , FirstCand . back ( ) , [ ] ( const MachineInstr & MI ) { return MI . isCall ( ) ; } ) ) ModStackToSaveLR = true ; else if ( FrameID != MachineOutlinerThunk && FrameID != MachineOutlinerTailCall && FirstCand . back ( ) -> isCall ( ) ) ModStackToSaveLR = true ; if ( ModStackToSaveLR ) { if ( ! AllStackInstrsSafe ) { RepeatedSequenceLocs . clear ( ) ; return outliner :: OutlinedFunction ( ) ; } NumBytesToCreateFrame += <NUM_LIT> ; } }

return outliner :: OutlinedFunction ( RepeatedSequenceLocs , SequenceSize , NumBytesToCreateFrame , FrameID ) ;


<s> BenesNetwork ( ArrayRef < ElemType > Ord ) : PermNetwork ( Ord , <NUM_LIT> ) {


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { if ( Register :: isVirtualRegister ( SrcReg ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( SrcReg , & <STR_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , getKillRegState ( isKill ) , TRI ) ; AddDReg ( MIB , SrcReg , <STR_LIT> , <NUM_LIT> , TRI ) ; MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . add ( predOps ( <STR_LIT> ) ) ; return ; } <ISA_LIT>BaseInstrInfo :: storeRegToStackSlot ( MBB , I , SrcReg , isKill , FI , RC , TRI ) ;


<s> bool isVolatile = ST -> isVolatile ( ) ; bool isNonTemporal = ST -> isNonTemporal ( ) ; Tmp3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Tmp3 ) ; SDValue Result = DAG . getStore ( Tmp1 , dl , Tmp3 , Tmp2 , ST -> getPointerInfo ( ) , isVolatile , isNonTemporal , Alignment ) ;


<s> for ( const SDep & PI : SU -> Preds ) { unsigned PredReadyCycle = PI . getSUnit ( ) -> TopReadyCycle ; unsigned MinLatency = PI . getLatency ( ) ; Top . MaxMinLatency = std :: max ( MinLatency , Top . MaxMinLatency ) ; if ( SU -> TopReadyCycle < PredReadyCycle + MinLatency ) SU -> TopReadyCycle = PredReadyCycle + MinLatency ; }

Top . releaseNode ( SU , SU -> TopReadyCycle ) ;


<s> return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; case <STR_LIT> : FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;


<s> uint64_t Bits = getBinaryCodeForInstr ( MI , Fixups ) ; unsigned Size = <NUM_LIT> ; unsigned Opcode = MI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) Size = <NUM_LIT> ; int ShiftValue = ( Size * <NUM_LIT> ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { OS << ( char ) ( Bits >> ShiftValue ) ; Bits <<= <NUM_LIT> ; }


<s> return findCommutedOpIndices ( MI . getDesc ( ) , SrcOpIdx0 , SrcOpIdx1 ) ;


<s> return new <ISA_LIT>16TargetLowering ( TM ) ;


<s> if ( lowerLongBranch ( MI , OutMI ) ) return ; OutMI . setOpcode ( MI -> getOpcode ( ) ) ;

for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) {


<s> auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , true ) ; MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ; auto AddrReg = MIRBuilder . buildFrameIndex ( LLT :: pointer ( <ISA_LIT>AS :: PRIVATE_ADDRESS , <NUM_LIT> ) , FI ) ; StackUsed = std :: max ( StackUsed , Size + Offset ) ; return AddrReg . getReg ( <NUM_LIT> ) ;


<s> default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } } if ( ! SpecRegRBit && ( Mask == <NUM_LIT> || Mask == <NUM_LIT> || Mask == <NUM_LIT> ) ) { O << <STR_LIT> ; switch ( Mask ) { default : assert ( <NUM_LIT> ) ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; case <NUM_LIT> : O << <STR_LIT> ; return ; } llvm_unreachable ( <STR_LIT> ) ; } if ( SpecRegRBit ) O << <STR_LIT> ; else O << <STR_LIT> ; if ( Mask ) { O << '_' ; if ( Mask & <NUM_LIT> ) O << 'f' ;


<s> int RegNum = parseRegisterName ( & MatchRegisterName ) ;

if ( RegNum == <STR_LIT> ) RegNum = parseRegisterName ( & MatchRegisterAltName ) ;


<s> MCSection<ISA_LIT> ( const StringRef & Section , unsigned Type , unsigned Flags , SectionKind K , bool isExplicit ) : MCSectionELF ( Section , Type , Flags , K , isExplicit ) {


<s> rtx tmp = gen_reg_rtx ( V2DImode ) ; emit_insn ( gen_vec_concatv2di ( tmp , lo , hi ) ) ;

return force_reg ( V1TImode , gen_lowpart ( V1TImode , tmp ) ) ;


<s> switch ( MO . getTargetFlags ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <NUM_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_None , Ctx ) ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_<ISA_LIT>_LO16 , Ctx ) ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_<ISA_LIT>_HI16 , Ctx ) ; break ; case <STR_LIT> : Expr = MCSymbolRefExpr :: Create ( Symbol , MCSymbolRefExpr :: VK_<ISA_LIT>_PLT , Ctx ) ; break ; } if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; return MCOperand :: CreateExpr ( Expr ) ;


<s> unsigned Reg2 = CSI [ idx + <NUM_LIT> ] . getReg ( ) ; assert ( CSI [ idx ] . getFrameIdx ( ) + <NUM_LIT> == CSI [ idx + <NUM_LIT> ] . getFrameIdx ( ) && <STR_LIT> ) ; unsigned StrOpc ; assert ( ( Count & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; assert ( ( i & <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else if ( <STR_LIT> . contains ( Reg1 ) ) { assert ( <STR_LIT> . contains ( Reg2 ) && <STR_LIT> ) ; if ( i == <NUM_LIT> ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else llvm_unreachable ( <STR_LIT> ) ; DEBUG ( dbgs ( ) << <STR_LIT> << TRI -> getName ( Reg1 ) << <STR_LIT> << TRI -> getName ( Reg2 ) << <STR_LIT> << CSI [ idx ] . getFrameIdx ( ) << <STR_LIT> << CSI [ idx + <NUM_LIT> ] . getFrameIdx ( ) << <STR_LIT> ) ;

const int Offset = ( i == <NUM_LIT> ) ? - Count : i ;


<s> if ( i == <NUM_LIT> && isThisReturn ) { assert ( ! VA . needsCustom ( ) && VA . getLocVT ( ) == <STR_LIT> && <STR_LIT> ) ; InVals . push_back ( ThisVal ) ; continue ; } SDValue Val ; if ( VA . needsCustom ( ) && ( VA . getLocVT ( ) == <STR_LIT> || VA . getLocVT ( ) == <STR_LIT> ) ) { SDValue Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; SDValue Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; if ( ! Subtarget -> isLittle ( ) ) std :: swap ( Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ;


<s> if ( VT == <STR_LIT> || VT == <STR_LIT> ) continue ; if ( VT . isFloatingPoint ( ) || VT . isVector ( ) ) return Sched :: Latency ; } if ( ! N -> isMachineOpcode ( ) ) return Sched :: RegPressure ; const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; const TargetInstrDesc & TID = TII -> get ( N -> getMachineOpcode ( ) ) ; if ( TID . getNumDefs ( ) == <NUM_LIT> ) return Sched :: RegPressure ; if ( ! Itins -> isEmpty ( ) && Itins -> getOperandCycle ( TID . getSchedClass ( ) , <NUM_LIT> ) > <NUM_LIT> ) return Sched :: Latency ; return Sched :: RegPressure ;


<s> void <ISA_LIT>CFGStackify :: fixEndsAtEndOfFunction ( MachineFunction & MF ) { const auto & MFI = * MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( MFI . getResults ( ) . empty ( ) ) return ; <STR_LIT> RetType = MFI . getResults ( ) . size ( ) > <NUM_LIT> ? <STR_LIT> :: Multivalue : <STR_LIT> ( <STR_LIT> ( MFI . getResults ( ) . front ( ) ) ) ; SmallVector < MachineBasicBlock :: reverse_iterator , <NUM_LIT> > Worklist ; Worklist . push_back ( MF . rbegin ( ) -> rbegin ( ) ) ; auto Process = [ & ] ( MachineBasicBlock :: reverse_iterator It ) { auto * MBB = It -> getParent ( ) ; while ( It != MBB -> rend ( ) ) { MachineInstr & MI = * It ++ ;

if ( MI . isPosition ( ) || MI . isDebugInstr ( ) ) continue ;


<s> const MCInstrDesc & MCID = TII . get ( UnfoldedOpc ) ;

return TII . getRegClass ( MCID , Index , & TII . getRegisterInfo ( ) , MF ) ;


<s> static enum rtx_code ix86_prepare_sse_fp_compare_args ( rtx dest , enum rtx_code code , rtx * pop0 , rtx * pop1 ) { rtx tmp ; switch ( code ) { case LTGT : case UNEQ : return UNKNOWN ; case LT : case LE : case UNGT : case UNGE : break ; case EQ : case NE : case UNORDERED :


<s> while ( ! OrigBB -> succ_empty ( ) ) { MachineBasicBlock * Succ = * OrigBB -> succ_begin ( ) ; OrigBB -> removeSuccessor ( Succ ) ; NewBB -> addSuccessor ( Succ ) ; assert ( ( Succ -> empty ( ) || Succ -> begin ( ) -> getOpcode ( ) != TargetInstrInfo :: PHI ) && <STR_LIT> ) ; } OrigBB -> addSuccessor ( NewBB ) ; MF . RenumberBlocks ( NewBB ) ; BBSizes . insert ( BBSizes . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; BBOffsets . insert ( BBOffsets . begin ( ) + NewBB -> getNumber ( ) , <NUM_LIT> ) ; std :: vector < MachineBasicBlock * > :: iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ; MachineBasicBlock * WaterBB = * IP ; if ( WaterBB == OrigBB ) WaterList . insert ( next ( IP ) , NewBB ) ; else WaterList . insert ( IP , OrigBB ) ; unsigned NewBBSize = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = NewBB -> begin ( ) , E = NewBB -> end ( ) ; I != E ; ++ I ) NewBBSize += TII -> GetInstSizeInBytes ( I ) ; unsigned OrigBBI = OrigBB -> getNumber ( ) ; unsigned NewBBI = NewBB -> getNumber ( ) ; BBSizes [ NewBBI ] = NewBBSize ; unsigned delta = isThumb ? <NUM_LIT> : <NUM_LIT> ; BBSizes [ OrigBBI ] -= NewBBSize - delta ; BBOffsets [ NewBBI ] = BBOffsets [ OrigBBI ] + BBSizes [ OrigBBI ] ; AdjustBBOffsetsAfter ( NewBB , delta ) ; return NewBB ;


<s> SDValue Ptr = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , BasePtr , DAG . getConstant ( Offset , <STR_LIT> ) ) ; SDValue PtrOffset = DAG . getUNDEF ( getPointerTy ( <STR_LIT> ) ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ;

return DAG . getLoad ( <STR_LIT> , Signed ? <STR_LIT> : <STR_LIT> , VT , SL , Chain , Ptr , PtrOffset , PtrInfo , MemVT , false , true , true , DL -> getABITypeAlignment ( Ty ) ) ;


<s> BuildMI ( MBB , MI , DL , MCID ) . addDef ( Dst ) . addUse ( Dst ) . addReg ( Mod ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; } else if ( MI . getFlag ( MachineInstr :: FrameSetup ) ) { BuildMI ( MBB , MI , DL , MCID ) . addDef ( Dst ) . addUse ( Dst ) . addReg ( Dst ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MI , DL , MCID ) . addDef ( Dst ) . addUse ( Dst ) . addReg ( Mod ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MI , DL , MCID ) . addDef ( Dst ) . addUse ( Dst ) . addReg ( Mod ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MI , DL , MCID ) . addDef ( Dst ) . addUse ( Dst ) . addReg ( Mod ) . addImm ( <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } else { BuildMI ( MBB , MI , DL , MCID ) . addDef ( Dst ) . addUse ( Dst ) . addReg ( Dst ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , MCID ) . addDef ( Dst ) . addUse ( Dst ) . addReg ( Mod ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , MCID ) . addDef ( Dst ) . addUse ( Dst ) . addReg ( Mod ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MI , DL , MCID ) . addDef ( Dst ) . addUse ( Dst ) . addReg ( Mod ) . addImm ( <NUM_LIT> ) ; }


<s> } else aarch64_expand_sve_vec_cmp_int ( pred , GET_CODE ( ops [ <NUM_LIT> ] ) , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] ) ; rtvec vec = gen_rtvec ( <NUM_LIT> , pred , ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] ) ;

emit_set_insn ( ops [ <NUM_LIT> ] , gen_rtx_UNSPEC ( data_mode , vec , UNSPEC_SEL ) ) ;


<s> static section * spu_select_section ( tree decl , int reloc , unsigned HOST_WIDE_INT align ) {

if ( TREE_TYPE ( decl ) != error_mark_node && TYPE_ADDR_SPACE ( TREE_TYPE ( decl ) ) == ADDR_SPACE_EA ) {


<s> bool <ISA_LIT>InstructionSelector :: selectMergeValues ( MachineInstr & I , MachineRegisterInfo & MRI , MachineFunction & MF , CodeGenCoverage & CoverageInfo ) const { assert ( ( I . getOpcode ( ) == TargetOpcode :: G_MERGE_VALUES ) && <STR_LIT> ) ; unsigned DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg0 = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg0 ) ; unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const RegisterBank & RegBank = * RBI . getRegBank ( DstReg , MRI , TRI ) ; unsigned DefReg = MRI . createGenericVirtualRegister ( DstTy ) ; MRI . setRegBank ( DefReg , RegBank ) ; if ( ! emitInsertSubreg ( DefReg , I . getOperand ( <NUM_LIT> ) . getReg ( ) , I , MRI , MF ) ) return false ; for ( unsigned Idx = <NUM_LIT> ; Idx < I . getNumOperands ( ) ; ++ Idx ) { unsigned Tmp = MRI . createGenericVirtualRegister ( DstTy ) ; MRI . setRegBank ( Tmp , RegBank ) ; MachineInstr & InsertInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_INSERT ) , Tmp ) . addReg ( DefReg ) . addReg ( I . getOperand ( Idx ) . getReg ( ) ) . addImm ( ( Idx - <NUM_LIT> ) * SrcSize ) ; DefReg = Tmp ; if ( ! select ( InsertInst , CoverageInfo ) ) return false ; } MachineInstr & CopyInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( DefReg ) ; if ( ! select ( CopyInst , CoverageInfo ) ) return false ;


<s> MCSection * <ISA_LIT>TargetObjectFile :: getSectionForConstant ( const DataLayout & DL , SectionKind Kind , const Constant * C , unsigned & Align ) const {

if ( IsConstantInSmallSection ( DL , C , * TM ) ) return SmallDataSection ;


<s> if ( ASM_OUTPUT_SPECIAL_POOL_ENTRY_P ( x , mode ) ) toc_section ( ) ;

else read_only_private_data_section ( ) ;


<s> if ( ST . is<ISA_LIT>64 ( ) || ST . isSVR4ABI ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; if ( ST . is<ISA_LIT>64 ( ) ) Ret += <STR_LIT> ; else Ret += <STR_LIT> ; return Ret ;


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) {


<s> src0 = gen_reg_rtx ( GET_MODE ( op0 ) ) ; emit_move_insn ( src0 , op0 ) ; } if ( GET_MODE ( op0 ) == HImode && INTVAL ( operands [ <NUM_LIT> ] ) >= <NUM_LIT> && GET_CODE ( op0 ) == MEM ) { rtx new_mem = gen_rtx_MEM ( QImode , plus_constant ( Pmode , XEXP ( op0 , <NUM_LIT> ) , <NUM_LIT> ) ) ; MEM_COPY_ATTRIBUTES ( new_mem , op0 ) ; mask >>= <NUM_LIT> ; } if ( INTVAL ( operands [ <NUM_LIT> ] ) == <NUM_LIT> ) { if ( GET_MODE ( op0 ) == HImode ) mask ^= <NUM_LIT> ; else mask ^= <NUM_LIT> ; } if ( GET_MODE ( op0 ) == HImode ) { if ( mask & <NUM_LIT> ) mask -= <NUM_LIT> ; } else { if ( mask & <NUM_LIT> ) mask -= <NUM_LIT> ; }

switch ( ( INTVAL ( operands [ <NUM_LIT> ] ) ? <NUM_LIT> : <NUM_LIT> ) + ( ( GET_MODE ( op0 ) == HImode ) ? <NUM_LIT> : <NUM_LIT> ) + ( TARGET_A24 ? <NUM_LIT> : <NUM_LIT> ) ) {


<s> unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( Op . getValueType ( ) . isFloatingPoint ( ) ) return SDValue ( ) ; unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : case <STR_LIT> : { if ( ! Op . getValueType ( ) . isFloatingPoint ( ) ) { unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } unsigned NewOpc = ( IntNo == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( NewOpc , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> :

return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> int TagOffset = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDNode * Out = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , { FiOp , CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) , CurDAG -> getTargetConstant ( TagOffset , DL , <STR_LIT> ) } ) ;


<s> } else if ( Subtarget . isLikeA9 ( ) || Subtarget . isSwift ( ) ) { UseCycle = RegNo ; bool isSStore = false ; switch ( UseMCID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : isSStore = true ; break ; } if ( ( isSStore && ( RegNo % <NUM_LIT> ) ) || UseAlign < <NUM_LIT> ) ++ UseCycle ; } else {


<s> Reg = getTargetVShiftNode ( <STR_LIT> , DL , <STR_LIT> , Reg , ShAmt , DAG ) ; Reg = getTargetVShiftNode ( <STR_LIT> , DL , <STR_LIT> , Reg , ShAmt , DAG ) ; }

for ( unsigned i = <NUM_LIT> , e = Regs . size ( ) / <NUM_LIT> ; i < e ; i ++ ) Regs [ i ] = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Regs [ i * <NUM_LIT> ] , Regs [ i * <NUM_LIT> + <NUM_LIT> ] ) ;


<s> unsigned Encoding ; const MCOperand Op1 = Inst . getOperand ( OpNo + <NUM_LIT> ) ; const MCOperand Op2 = Inst . getOperand ( OpNo + <NUM_LIT> ) ; const MCOperand AluOp = Inst . getOperand ( OpNo + <NUM_LIT> ) ; assert ( Op1 . isReg ( ) && <STR_LIT> ) ; assert ( ( Op2 . isImm ( ) || Op2 . isExpr ( ) ) && <STR_LIT> ) ; assert ( ( LPAC :: getAluOp ( AluOp . getImm ( ) ) == LPAC :: ADD ) && <STR_LIT> ) ; Encoding = ( get<ISA_LIT>RegisterNumbering ( Op1 . getReg ( ) ) << <NUM_LIT> ) ; if ( Op2 . isImm ( ) ) { assert ( isInt < <NUM_LIT> > ( Op2 . getImm ( ) ) && <STR_LIT> ) ; Encoding |= ( Op2 . getImm ( ) & <NUM_LIT> ) ;


<s> rtx op00 , op02 , op10 , op12 ; op00 = msp430_subreg ( HImode , operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; op02 = msp430_subreg ( HImode , operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; if ( GET_CODE ( operands [ <NUM_LIT> ] ) == CONST || GET_CODE ( operands [ <NUM_LIT> ] ) == SYMBOL_REF ) { op10 = gen_rtx_ZERO_EXTRACT ( HImode , operands [ <NUM_LIT> ] , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; op10 = gen_rtx_CONST ( HImode , op10 ) ; op12 = gen_rtx_ZERO_EXTRACT ( HImode , operands [ <NUM_LIT> ] , GEN_INT ( <NUM_LIT> ) , GEN_INT ( <NUM_LIT> ) ) ; op12 = gen_rtx_CONST ( HImode , op12 ) ; } else { op10 = msp430_subreg ( HImode , operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; op12 = msp430_subreg ( HImode , operands [ <NUM_LIT> ] , SImode , <NUM_LIT> ) ; } if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { operands [ <NUM_LIT> ] = op02 ; operands [ <NUM_LIT> ] = op12 ; operands [ <NUM_LIT> ] = op00 ; operands [ <NUM_LIT> ] = op10 ; }

else if ( rtx_equal_p ( op00 , op12 ) || ( REG_P ( op00 ) && reg_mentioned_p ( op00 , op10 ) ) || ( REG_P ( op10 ) && reg_mentioned_p ( op10 , op00 ) ) ) {


<s> unsigned Opc = Op . getOpcode ( ) ; bool IsPairOp = isHvxPairTy ( ty ( Op ) ) || llvm :: any_of ( Op . getNode ( ) -> ops ( ) , [ this ] ( SDValue V ) { return isHvxPairTy ( ty ( V ) ) ; } ) ; if ( IsPairOp ) { switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : return SplitHvxMemOp ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SplitHvxPairOp ( Op , DAG ) ; } } switch ( Opc ) { default : break ; case <STR_LIT> : return LowerHvxBuildVector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxConcatVectors ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxInsertElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractSubvector ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtractElement ( Op , DAG ) ; case <STR_LIT> : return LowerHvxAnyExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxSignExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxZeroExt ( Op , DAG ) ; case <STR_LIT> : return LowerHvxCttz ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerHvxShift ( Op , DAG ) ; case <STR_LIT> : return LowerHvxMul ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerHvxMulh ( Op , DAG ) ; case <STR_LIT> : return LowerHvxExtend ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return Op ; case <STR_LIT> : return SDValue ( ) ; } Op . dumpr ( & DAG ) ;


<s> case <STR_LIT> : if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue P = getInstr ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG ) ; SDValue T = DAG . getAnyExtOrTrunc ( P , dl , <STR_LIT> ) ; Results . push_back ( T ) ; } break ; }


<s> std :: string get<ISA_LIT>RegClassName ( TargetRegisterClass const * RC ) { if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else if ( RC == & <STR_LIT> ) { return <STR_LIT> ; } else {


<s> MachineBasicBlock * MBB = MI . getParent ( ) ; const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; auto I = MI . getIterator ( ) ; auto E = std :: next ( I ) ;

BuildMI ( * MBB , E , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ;


<s> EVT VT = Op . getValueType ( ) ; if ( ! VT . isSimple ( ) || ! VT . isVector ( ) ) return false ; APInt KnownUndef , KnownZero ; unsigned NumElts = Op . getValueType ( ) . getVectorNumElements ( ) ; APInt DemandedElts = APInt :: getAllOnesValue ( NumElts ) ;

return getTargetShuffleInputs ( Op , DemandedElts , Inputs , Mask , KnownUndef , KnownZero , DAG , Depth , ResolveKnownElts ) ;


<s> } Size = <NUM_LIT> ; Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return MCDisassembler :: Success ;


<s> const char * nds32_output_casesi_pc_relative ( rtx * operands ) { machine_mode mode ; rtx diff_vec ; diff_vec = PATTERN ( NEXT_INSN ( as_a < rtx_insn * > ( operands [ <NUM_LIT> ] ) ) ) ; gcc_assert ( GET_CODE ( diff_vec ) == ADDR_DIFF_VEC ) ; if ( flag_pic ) { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; } else output_asm_insn ( <STR_LIT> , operands ) ; mode = GET_MODE ( diff_vec ) ; switch ( mode ) { case E_QImode : output_asm_insn ( <STR_LIT> , operands ) ; break ; case E_HImode : output_asm_insn ( <STR_LIT> , operands ) ; break ; case E_SImode : output_asm_insn ( <STR_LIT> , operands ) ; break ; default : gcc_unreachable ( ) ; } output_asm_insn ( <STR_LIT> , operands ) ; if ( TARGET_16_BIT ) return <STR_LIT> ; else return <STR_LIT> ;


<s> SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue WordOff = DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ; SDValue OffsetSlot = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackSlot , WordOff ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ; SDValue Fild = DAG . getMemIntrinsicNode ( <STR_LIT> , dl , Tys , Ops , <STR_LIT> , MMO ) ; APInt FF ( <NUM_LIT> , <NUM_LIT> ) ; SDValue SignSet = DAG . getSetCC ( dl , getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> ) ; SDValue FudgePtr = DAG . getConstantPool ( ConstantInt :: get ( * DAG . getContext ( ) , FF . zext ( <NUM_LIT> ) ) , getPointerTy ( ) ) ; SDValue Zero = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Four = DAG . getIntPtrConstant ( <NUM_LIT> ) ; SDValue Offset = DAG . getNode ( <STR_LIT> , dl , Zero . getValueType ( ) , SignSet , Zero , Four ) ; FudgePtr = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FudgePtr , Offset ) ; SDValue Fudge = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , DAG . getEntryNode ( ) , FudgePtr , MachinePointerInfo :: getConstantPool ( ) , <STR_LIT> , false , false , false , <NUM_LIT> ) ;

SDValue Add = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Fild , Fudge ) ;


<s> } ; if ( Op1 . getOpcode ( ) == <STR_LIT> && IsNonOpaqueConstant ( Op0 ) && IsNonOpaqueConstant ( Op1 . getOperand ( <NUM_LIT> ) ) && Op1 -> hasOneUse ( ) ) { SDLoc DL ( N ) ; EVT VT = Op0 . getValueType ( ) ; SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getNOT ( SDLoc ( Op1 ) , Op1 . getOperand ( <NUM_LIT> ) , VT ) ) ; SDValue NewAdd = DAG . getNode ( <STR_LIT> , DL , VT , Op0 , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , NewXor , NewAdd ) ; } if ( SDValue V = combineToHorizontalAddSub ( N , DAG , Subtarget ) ) return V ; return combineAddOrSubToADCOrSBB ( N , DAG ) ;


<s> unsigned getChannelFromSubReg ( unsigned SubReg ) const {

return SubReg ? ( getSubRegIdxOffset ( SubReg ) + <NUM_LIT> ) / <NUM_LIT> : <NUM_LIT> ;


<s> bool HasBP = RegInfo -> hasBasePointer ( MF ) ; unsigned FrameSize = determineFrameLayout ( MF , false ) ; int NegFrameSize = - FrameSize ; bool IsLargeFrame = ! isInt < <NUM_LIT> > ( NegFrameSize ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

unsigned MaxAlign = MFI . getMaxAlignment ( ) ;


<s> int FI = MF . getFrameInfo ( ) -> CreateFixedObject ( OpSize , Offset ) ; MVT VT = is<ISA_LIT>64 ? <STR_LIT> : <STR_LIT> ; SDValue FIN = DAG . getFrameIndex ( FI , VT ) ; TailCallArgumentInfo Info ; Info . Arg = Arg ; Info . FrameIdxOp = FIN ; Info . FrameIdx = FI ; TailCallArguments . push_back ( Info ) ;


<s> { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { <STR_LIT> , <STR_LIT> } } , } ; unsigned Opcode = MI . getOpcode ( ) ; auto Found = VFMKMap . find ( Opcode ) ; if ( Found == VFMKMap . end ( ) ) report_fatal_error ( <STR_LIT> ) ; unsigned OpcodeUpper = ( * Found ) . second . first ; unsigned OpcodeLower = ( * Found ) . second . second ; MachineBasicBlock * MBB = MI . getParent ( ) ;


<s> return Is64Bit ? COFF :: IMAGE_REL_AMD64_ADDR32 : COFF :: IMAGE_REL_I386_DIR32 ; case FK_Data_8 : if ( Is64Bit ) return COFF :: IMAGE_REL_AMD64_ADDR64 ; llvm_unreachable ( <STR_LIT> ) ; case FK_SecRel_4 : return Is64Bit ? COFF :: IMAGE_REL_AMD64_SECREL : COFF :: IMAGE_REL_I386_SECREL ; default :


<s> static tree alpha_fold_builtin_cmpbge ( unsigned HOST_WIDE_INT opint [ ] , long op_const ) { if ( op_const == <NUM_LIT> ) { int i , val ; for ( i = <NUM_LIT> , val = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { unsigned HOST_WIDE_INT c0 = ( opint [ <NUM_LIT> ] >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ; unsigned HOST_WIDE_INT c1 = ( opint [ <NUM_LIT> ] >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ; if ( c0 >= c1 ) val |= <NUM_LIT> << i ;


<s> SDValue FIPtr = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Chain = DAG . getStore ( Chain , DL , Entry . Node , FIPtr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; Entry . Node = FIPtr ; Entry . Ty = PointerType :: getUnqual ( ArgTy ) ; }


<s> M . getFunctionList ( ) . push_back ( NewFunc ) ; F -> replaceAllUsesWith ( NewFunc ) ; } for ( Function & F : M ) { if ( F . hasLocalLinkage ( ) && ! F . hasFnAttribute ( Attribute :: NoInline ) ) { F . addFnAttr ( Attribute :: AlwaysInline ) ; } } return false ;


<s> bool <ISA_LIT>PacketizerList :: canReserveResourcesForConstExt ( MachineInstr * MI ) { const <ISA_LIT>InstrInfo * QII = ( const <ISA_LIT>InstrInfo * ) TII ; assert ( QII -> isExtended ( MI ) && <STR_LIT> ) ; MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; MachineInstr * PseudoMI = MF -> CreateMachineInstr ( QII -> get ( <STR_LIT> ) , MI -> getDebugLoc ( ) ) ; bool CanReserve = ResourceTracker -> canReserveResources ( PseudoMI ) ; MF -> DeleteMachineInstr ( PseudoMI ) ;


<s> MachineInstr * BranchMI = getLoopendBlockBranchInstr ( ExitingMBB ) ; assert ( BranchMI && isCondBranch ( BranchMI ) ) ; DebugLoc DL = BranchMI -> getDebugLoc ( ) ; MachineBasicBlock * TrueBranch = getTrueBranch ( BranchMI ) ; MachineBasicBlock :: iterator I = BranchMI ;

if ( TrueBranch != LandMBB ) reversePredicateSetter ( I ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ;


<s> void LLVMInitializeBlackfinAsmPrinter ( ) {

RegisterAsmPrinter < BlackfinAsmPrinter > X ( TheBlackfinTarget ) ;


<s> bool Changed = false ; for ( MachineInstr & MI : llvm :: make_early_inc_range ( * MBB ) ) { if ( isProfitableToTransform ( MI ) ) { transformInstruction ( MI ) ; Changed = true ; } }


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override {


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedStore ( Type * DataType , MaybeAlign Alignment ) { return isLegalMaskedLoad ( DataType , Alignment ) ;


<s> int <ISA_LIT>ABIInfo :: EhDataRegSize ( ) const { if ( ThisABI == <STR_LIT> ) return <NUM_LIT> ;


<s> unsigned getReg ( ) const override { assert ( Kind == k_Register && <STR_LIT> ) ;


<s> bool willForceRelocations ( ) const {

return ForceRelocs || STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> big_mode = from_mode ; } if ( reg_classes_intersect_p ( VEC_REGS , rclass ) && ( GET_MODE_SIZE ( small_mode ) < <NUM_LIT> || s390_class_max_nregs ( VEC_REGS , big_mode ) == <NUM_LIT> ) ) return <NUM_LIT> ; if ( reg_classes_intersect_p ( ACCESS_REGS , rclass ) ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> DebugLoc DL = MBB . findDebugLoc ( MI ) ; addFrameReference ( BuildMI ( MBB , MI , DL , get ( Opc ) , DestReg ) , FrameIdx ) ;


<s> unsigned PrevNum = Start . getNumber ( ) ;

for ( auto & MBB : make_range ( MachineFunction :: iterator ( Start ) , MF -> end ( ) ) ) {


<s> static void sparc_asm_function_prologue ( FILE * file , HOST_WIDE_INT size ATTRIBUTE_UNUSED ) {

if ( ! TARGET_FLAT ) gcc_assert ( sparc_leaf_function_p == crtl -> uses_only_leaf_regs ) ;


<s> if ( GET_CODE ( patt ) == SET ) { rtx lhs = XEXP ( patt , <NUM_LIT> ) ; if ( REG_P ( lhs ) && REGNO ( lhs ) == STATIC_CHAIN_REGNUM ) return true ; } } }


<s> static void lm32_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode , tree type , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int first_anon_arg ; tree fntype ; fntype = TREE_TYPE ( current_function_decl ) ; if ( stdarg_p ( fntype ) ) first_anon_arg = * cum + LM32_FIRST_ARG_REG ; else { int size ; if ( mode == BLKmode ) size = int_size_in_bytes ( type ) ; else size = GET_MODE_SIZE ( mode ) ; first_anon_arg = * cum + LM32_FIRST_ARG_REG + ( ( size + UNITS_PER_WORD - <NUM_LIT> ) / UNITS_PER_WORD ) ; } if ( ( first_anon_arg < ( LM32_FIRST_ARG_REG + LM32_NUM_ARG_REGS ) ) && ! no_rtl ) { int first_reg_offset = first_anon_arg ; int size = LM32_FIRST_ARG_REG + LM32_NUM_ARG_REGS - first_anon_arg ; rtx regblock ; regblock = gen_rtx_MEM ( BLKmode , plus_constant ( Pmode , arg_pointer_rtx , FIRST_PARM_OFFSET ( <NUM_LIT> ) ) ) ; move_block_from_reg ( first_reg_offset , regblock , size ) ;

* pretend_size = size * UNITS_PER_WORD ;


<s> for ( unsigned i = <NUM_LIT> , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ; i < e ; ++ i ) { EmittedInstrs . push_front ( nullptr ) ; } EmittedInstrs . resize ( getMaxLookAhead ( ) ) ;


<s> } if ( ! isEmptyXXStructor ( M . getNamedGlobal ( <STR_LIT> ) ) ) { report_fatal_error ( <STR_LIT> ) ; return true ; } if ( ! isEmptyXXStructor ( M . getNamedGlobal ( <STR_LIT> ) ) ) { report_fatal_error ( <STR_LIT> ) ; return true ; } SmallString < <NUM_LIT> > Str1 ; raw_svector_ostream OS1 ( Str1 ) ; MMI = getAnalysisIfAvailable < MachineModuleInfo > ( ) ; const_cast < TargetLoweringObjectFile & > ( getObjFileLowering ( ) ) . Initialize ( OutContext , TM ) ; Mang = new Mangler ( ) ; emitHeader ( M , OS1 , STI ) ;

OutStreamer -> EmitRawText ( OS1 . str ( ) ) ;


<s> assert ( ( Kind == k_MImmOp ) && <STR_LIT> ) ;


<s> MachineInstr * <ISA_LIT>FrameLowering :: emitStackProbeInlineStub ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , const DebugLoc & DL , bool InProlog ) const {


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitCSetForFCmp ( Register Dst , CmpInst :: Predicate Pred , MachineIRBuilder & MIRBuilder ) const { MachineRegisterInfo & MRI = * MIRBuilder . getMRI ( ) ; LLT Ty = MRI . getType ( Dst ) ; assert ( ! Ty . isVector ( ) && Ty . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; const Register ZReg = <STR_LIT> ; <STR_LIT> CC1 , CC2 ; changeFCMPPredTo<ISA_LIT>CC ( Pred , CC1 , CC2 ) ; auto InvCC1 = <STR_LIT> ( CC1 ) ; if ( CC2 == <STR_LIT> ) return emitCSINC ( Dst , ZReg , ZReg , InvCC1 , MIRBuilder ) ; const TargetRegisterClass * RC = & <STR_LIT> ;

Register Def1Reg = MRI . createVirtualRegister ( RC ) ;


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> bool <ISA_LIT>Subtarget :: enableMachinePipeliner ( ) const {

return getSchedModel ( ) . hasInstrSchedModel ( ) && EnableMachinePipeliner ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; case <STR_LIT> : return getRegBank ( <STR_LIT> ) ; default :


<s> <ISA_LIT>ABIInfo <ISA_LIT>ABIInfo :: computeTargetABI ( Triple TT , StringRef CPU , const MCTargetOptions & Options ) { if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: O32 ( ) ; else if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: N32 ( ) ; else if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: N64 ( ) ; else if ( Options . getABIName ( ) . startswith ( <STR_LIT> ) ) return <ISA_LIT>ABIInfo :: EABI ( ) ; else if ( ! Options . getABIName ( ) . empty ( ) ) llvm_unreachable ( <STR_LIT> ) ; if ( CPU . empty ( ) || CPU == <STR_LIT> ) { if ( TT . getArch ( ) == Triple :: mips || TT . getArch ( ) == Triple :: mipsel ) CPU = <STR_LIT> ; else CPU = <STR_LIT> ;


<s> CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , TLI . getPointerTy ( ) ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ; return CallResult . second ;


<s> i = pru_get_ctable_base_index ( caddr ) ; gcc_assert ( i >= <NUM_LIT> ) ;

return caddr - pru_ctable [ i ] . base ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; SDValue <ISA_LIT>CC ; SDValue Flag = EmitCmp ( LHS , RHS , CC , <ISA_LIT>CC , DAG ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ;


<s> void emitLocalCommonSymbolSorted ( MCSymbol * Symbol , uint64_t Size , unsigned ByteAlignment , unsigned AccessSize ) override { <ISA_LIT>MCELFStreamer & <ISA_LIT>ELFStreamer = static_cast < <ISA_LIT>MCELFStreamer & > ( getStreamer ( ) ) ;

<ISA_LIT>ELFStreamer . <ISA_LIT>MCEmitLocalCommonSymbol ( Symbol , Size , ByteAlignment , AccessSize ) ;


<s> CallContext ( ) : Call ( nullptr ) , SPCopy ( nullptr ) , ExpectedDist ( <NUM_LIT> ) , MovVector ( <NUM_LIT> , nullptr ) , NoStackParams ( false ) , UsePush ( false ) {


<s> auto RHS = In . getOperand ( <NUM_LIT> ) ; if ( ! IsConstVectorInRange ( RHS , <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Operands [ <NUM_LIT> ] ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; if ( IsConstVectorInRange ( Operands [ <NUM_LIT> ] , <NUM_LIT> , ScalarVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) && Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> && Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) { SDValue VecOnes = DAG . getConstant ( <NUM_LIT> , DL , InVT ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , InVT , Operands [ <NUM_LIT> ] , VecOnes ) ; Operands [ <NUM_LIT> ] = DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT> ] ) ; } if ( Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> ) std :: swap ( Operands [ <NUM_LIT> ] , Operands [ <NUM_LIT> ] ) ; else if ( Operands [ <NUM_LIT> ] . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( ! IsConstVectorInRange ( Operands [ i ] , <NUM_LIT> , <NUM_LIT> ) ) continue ; std :: swap ( Operands [ i ] , Operands [ <NUM_LIT> ] ) ; for ( int j = <NUM_LIT> ; j < <NUM_LIT> ; ++ j ) if ( Operands [ j ] . getOpcode ( ) != <STR_LIT> || Operands [ j ] . getOperand ( <NUM_LIT> ) . getValueType ( ) != VT ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) , Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) ) ;


<s> OS << <STR_LIT> << StringRef ( getRegisterName ( RegNo ) ) ;


<s> unsigned int <ISA_LIT>InstrInfo :: getTailDuplicateSize ( CodeGenOpt :: Level OptLevel ) const {

return OptLevel >= CodeGenOpt :: Aggressive ? <NUM_LIT> : <NUM_LIT> ;


<s> if ( ( load0 > <NUM_LIT> || store0 > <NUM_LIT> || CVIloads > <NUM_LIT> || CVIstores > <NUM_LIT> ) || ( duplex > <NUM_LIT> || ( duplex && memory ) ) || ( solo && size ( ) > <NUM_LIT> ) || ( onlyAX && neitherAnorX > <NUM_LIT> ) || ( onlyAX && xtypeFloat ) ) { Error = SHUFFLE_ERROR_INVALID ; return false ; } if ( jump1 && jumps > <NUM_LIT> ) { Error = SHUFFLE_ERROR_BRANCHES ; return false ; } bool bOnlySlot3 = false ; for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) { MCInst const * ID = ISJ -> getDesc ( ) ; if ( ! ISJ -> Core . getUnits ( ) ) { Error = SHUFFLE_ERROR_UNKNOWN ; return false ; } if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . getOpcode ( ) != <STR_LIT> ) if ( onlyNo1 ) ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & ~ slotOne ) ; if ( <ISA_LIT>MCInstrInfo :: getType ( MCII , * ID ) != <STR_LIT> ) if ( onlyAin1 ) ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & ~ slotOne ) ; if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . isBranch ( ) || <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . isCall ( ) ) if ( jumps > <NUM_LIT> ) { if ( slotJump < slotLastJump ) { Error = SHUFFLE_ERROR_BRANCHES ; return false ; } ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotJump ) ; slotJump >>= <NUM_LIT> ; } if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . mayLoad ( ) ) { if ( loads == <NUM_LIT> && loads == memory ) ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotSingleLoad ) ; } if ( <ISA_LIT>MCInstrInfo :: getDesc ( MCII , * ID ) . mayStore ( ) ) { if ( ! store0 ) { if ( stores == <NUM_LIT> ) ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotSingleStore ) ; else if ( stores > <NUM_LIT> ) { if ( slotLoadStore < slotLastLoadStore ) { Error = SHUFFLE_ERROR_STORES ; return false ; } ISJ -> Core . setUnits ( ISJ -> Core . getUnits ( ) & slotLoadStore ) ; slotLoadStore >>= <NUM_LIT> ; } } if ( store1 && stores > <NUM_LIT> ) { Error = SHUFFLE_ERROR_STORES ; return false ; } } if ( ISJ -> Core . getUnits ( ) == slotThree ) bOnlySlot3 = true ; if ( ! ISJ -> Core . getUnits ( ) ) {


<s> if ( ! GEP ) continue ; const Value * Ptr = GEP -> getPointerOperand ( ) ; const AllocaInst * Alloca = dyn_cast < AllocaInst > ( GetUnderlyingObject ( Ptr ) ) ; if ( Alloca ) { UP . Threshold = <NUM_LIT> ; }


<s> bool isRegion ( ) { return getRegionMRT ( ) != nullptr ;


<s> if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; uint64_t NopCount = Count / <NUM_LIT> ; while ( NopCount -- ) OS . write ( <STR_LIT> , <NUM_LIT> ) ; return true ;


<s> static rtx fr30_function_arg ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ;

if ( ! named || fr30_must_pass_in_stack ( mode , type ) || * cum >= FR30_NUM_ARG_REGS ) return NULL_RTX ;


<s> FstHalf = SVOp -> getMaskElt ( i ) / HalfSize ; break ; } } for ( unsigned i = HalfSize ; i < HalfSize * <NUM_LIT> ; ++ i ) { if ( SVOp -> getMaskElt ( i ) > <NUM_LIT> ) { SndHalf = SVOp -> getMaskElt ( i ) / HalfSize ; break ; } } return ( FstHalf | ( SndHalf << <NUM_LIT> ) ) ;


<s> copy1MBB -> transferSuccessors ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( copy1MBB ) ; BB = copy0MBB ; BB -> addSuccessor ( copy1MBB ) ; BB = copy1MBB ; BuildMI ( BB , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) ; F -> DeleteMachineInstr ( MI ) ;


<s> tmp2 = gen_reg_rtx ( mode ) ; emit_insn ( gen_vec_setv8hf_0 ( tmp2 , CONST0_RTX ( mode ) , tmp1 ) ) ; tmp1 = gen_lowpart ( mode , tmp2 ) ; } else { tmp1 = gen_reg_rtx ( SImode ) ; emit_move_insn ( tmp1 , gen_lowpart ( SImode , val ) ) ; tmp2 = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_vec_setv4si_0 ( tmp2 , CONST0_RTX ( V4SImode ) , tmp1 ) ) ; tmp1 = gen_lowpart ( mode , tmp2 ) ; } emit_move_insn ( dperm . op0 , tmp1 ) ; ok = ( expand_vec_perm_1 ( & dperm ) || expand_vec_perm_broadcast_1 ( & dperm ) ) ; gcc_assert ( ok ) ; return ok ; } goto widen ; case E_V16QImode : if ( TARGET_AVX2 ) return ix86_vector_duplicate_value ( mode , target , val ) ; if ( TARGET_SSE2 ) goto permute ; goto widen ; widen : { machine_mode smode , wsmode , wvmode ; rtx x ; smode = GET_MODE_INNER ( mode ) ; wvmode = get_mode_wider_vector ( mode ) ; wsmode = GET_MODE_INNER ( wvmode ) ; val = convert_modes ( wsmode , smode , val , true ) ; if ( smode == QImode && ! TARGET_PARTIAL_REG_STALL ) emit_insn ( gen_insv_1 ( wsmode , val , val ) ) ; else { x = expand_simple_binop ( wsmode , ASHIFT , val , GEN_INT ( GET_MODE_BITSIZE ( smode ) ) , NULL_RTX , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; val = expand_simple_binop ( wsmode , IOR , val , x , x , <NUM_LIT> , OPTAB_LIB_WIDEN ) ; } x = gen_reg_rtx ( wvmode ) ; ok = ix86_expand_vector_init_duplicate ( mmx_ok , wvmode , x , val ) ; gcc_assert ( ok ) ; emit_move_insn ( target , gen_lowpart ( GET_MODE ( target ) , x ) ) ; return ok ; } case E_V16HImode : case E_V16HFmode :


<s> <ISA_LIT>FrameLowering :: ~ <ISA_LIT>FrameLowering ( ) {


<s> int GCNHazardRecognizer :: checkRWLaneHazards ( MachineInstr * RWLane ) { const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ;

const MachineOperand * LaneSelectOp = TII -> getNamedOperand ( * RWLane , <STR_LIT> :: src1 ) ;


<s> EVT VT = Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ; LROpOut = getReturnAddrFrameIndex ( DAG ) ; LROpOut = DAG . getLoad ( VT , dl , Chain , LROpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; Chain = SDValue ( LROpOut . getNode ( ) , <NUM_LIT> ) ; if ( isDarwinABI ) { FPOpOut = getFramePointerFrameIndex ( DAG ) ; FPOpOut = DAG . getLoad ( VT , dl , Chain , FPOpOut , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;

Chain = SDValue ( FPOpOut . getNode ( ) , <NUM_LIT> ) ;


<s> <ISA_LIT>64TargetMachine :: <ISA_LIT>64TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , RM , CM , true ) {


<s> static bool isInstrUniform ( const MachineInstr & MI ) {

if ( ! MI . hasOneMemOperand ( ) ) return false ;


<s> if ( crtl -> uses_pic_offset_table == <NUM_LIT> ) return ; gcc_assert ( flag_pic != <NUM_LIT> ) ; pat = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ; pat = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , pat ) , ARC_UNSPEC_GOT ) ; pat = gen_rtx_CONST ( Pmode , pat ) ;

pat = gen_rtx_SET ( baseptr_rtx , pat ) ;


<s> if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ; OutStreamer -> PushSection ( ) ; OutStreamer -> SwitchSection ( Ctx . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC ) ) ; OutStreamer -> emitSymbolValue ( DotSym , <NUM_LIT> ) ;


<s> void LLVMInitializeDcpu16Target ( ) { RegisterTargetMachine < Dcpu16TargetMachine > X ( TheDcpu16Target ) ;


<s> vqrdmulh_n_s32 ( int32x2_t a , int32_t b ) { int32x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result ;


<s> if ( <ISA_LIT>Relocator :: SymVal == got_entry -> getValue ( ) ) got_entry -> setValue ( pReloc . symValue ( ) ) ; Relocation * dyn_rel = pParent . getRelRelMap ( ) . lookUp ( pReloc ) ; if ( ( dyn_rel != NULL ) && ( <ISA_LIT>Relocator :: SymVal == dyn_rel -> addend ( ) ) ) { dyn_rel -> setAddend ( pReloc . symValue ( ) ) ; }

Relocator :: Address GOT_S = helper_get_GOT_address ( pReloc , pParent ) ;


<s> for ( prev = vec_lab ; ; prev = PREV_INSN ( prev ) ) { if ( GET_CODE ( prev ) != JUMP_INSN ) continue ; prevpat = PATTERN ( prev ) ; if ( GET_CODE ( prevpat ) != PARALLEL || XVECLEN ( prevpat , <NUM_LIT> ) != <NUM_LIT> ) continue ; x = XVECEXP ( prevpat , <NUM_LIT> , <NUM_LIT> ) ; if ( GET_CODE ( x ) != USE ) continue ; x = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( x ) == LABEL_REF && XEXP ( x , <NUM_LIT> ) == vec_lab ) break ;


<s> MCInst JalrInst ; JalrInst . setLoc ( IDLoc ) ; const MCOperand FirstRegOp = Inst . getOperand ( <NUM_LIT> ) ; const unsigned Opcode = Inst . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { if ( inMicro<ISA_LIT>Mode ( ) ) { JalrInst . setOpcode ( <STR_LIT> ) ; JalrInst . addOperand ( FirstRegOp ) ; } else { JalrInst . setOpcode ( <STR_LIT> ) ; JalrInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; JalrInst . addOperand ( FirstRegOp ) ; } } else if ( Opcode == <STR_LIT> ) { JalrInst . setOpcode ( inMicro<ISA_LIT>Mode ( ) ? <STR_LIT> : <STR_LIT> ) ; JalrInst . addOperand ( FirstRegOp ) ; const MCOperand SecondRegOp = Inst . getOperand ( <NUM_LIT> ) ; JalrInst . addOperand ( SecondRegOp ) ; } Instructions . push_back ( JalrInst ) ; if ( AssemblerOptions . back ( ) -> isReorder ( ) ) { MCInst NopInst ; NopInst . setOpcode ( <STR_LIT> ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; NopInst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; Instructions . push_back ( NopInst ) ;