<s> const MCExpr * CallExpr = Func . getExpr ( ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addOperand ( MCOperand :: createExpr ( CallExpr ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; <STR_LIT> :: write ( OS , Binary , <STR_LIT> ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ;

else TmpInst = MCInstBuilder ( <STR_LIT> ) . addReg ( Ra ) . addReg ( Ra ) . addImm ( <NUM_LIT> ) ;


<s> void addMemImm0_1020s4OffsetOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; int32_t Val = Memory . OffsetImm ? Memory . OffsetImm -> getValue ( ) / <NUM_LIT> : <NUM_LIT> ; Inst . addOperand ( MCOperand :: createReg ( Memory . BaseRegNum ) ) ; Inst . addOperand ( MCOperand :: createImm ( Val ) ) ;


<s> return CONST_INT_P ( val ) && INTVAL ( val ) == trunc_int_for_mode ( HOST_WIDE_INT_C ( <NUM_LIT> ) , mode ) ;


<s> Scl = DAG . getNode ( <STR_LIT> , dl , SrcVT . getScalarType ( ) , Scl ) ; return DAG . getZExtOrTrunc ( Scl , dl , VT ) ; } return SDValue ( ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getBitcast ( VT , InputVector ) ; } if ( InputVector . getOpcode ( ) == <STR_LIT> && InputVector . hasOneUse ( ) && VT == <STR_LIT> && SrcVT == <STR_LIT> && isNullConstant ( EltIdx ) ) { SDValue MMXSrc = InputVector . getOperand ( <NUM_LIT> ) ; if ( MMXSrc . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , MMXSrc ) ; } if ( SDValue SAD = combineBasicSADPattern ( N , DAG , Subtarget ) ) return SAD ; if ( SDValue Cmp = combinePredicateReduction ( N , DAG , Subtarget ) ) return Cmp ; if ( SDValue MinMax = combineMinMaxReduction ( N , DAG , Subtarget ) ) return MinMax ; if ( SDValue V = combineArithReduction ( N , DAG , Subtarget ) ) return V ; if ( SDValue V = scalarizeExtEltFP ( N , DAG ) ) return V ; if ( CIdx && SrcVT . getScalarType ( ) == <STR_LIT> ) { SmallVector < SDNode * , <NUM_LIT> > BoolExtracts ; unsigned ResNo = InputVector . getResNo ( ) ; auto IsBoolExtract = [ & BoolExtracts , & ResNo ] ( SDNode * Use ) { if ( Use -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Use -> getOperand ( <NUM_LIT> ) ) && Use -> getOperand ( <NUM_LIT> ) . getResNo ( ) == ResNo && Use -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { BoolExtracts . push_back ( Use ) ; return true ; } return false ; } ; if ( all_of ( InputVector -> uses ( ) , IsBoolExtract ) && BoolExtracts . size ( ) > <NUM_LIT> ) {

EVT BCVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , NumSrcElts ) ;


<s> int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; Amount = alignTo ( Amount , Align ) ; if ( ! IsDestroy ) Amount = - Amount ; if ( CalleePopAmount == <NUM_LIT> ) { assert ( Amount > - <NUM_LIT> && Amount < <NUM_LIT> && <STR_LIT> ) ; emitFrameOffset ( MBB , I , DL , <STR_LIT> , <STR_LIT> , { Amount , <STR_LIT> } , TII ) ; } } else if ( CalleePopAmount != <NUM_LIT> ) { assert ( CalleePopAmount < <NUM_LIT> && <STR_LIT> ) ; emitFrameOffset ( MBB , I , DL , <STR_LIT> , <STR_LIT> , { - ( int64_t ) CalleePopAmount , <STR_LIT> } , TII ) ;


<s> MIRBuilder . setInstr ( MI ) ; unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( Dst ) ; LLT SrcTy = MRI . getType ( Src ) ; unsigned DestAS = DstTy . getAddressSpace ( ) ; unsigned SrcAS = SrcTy . getAddressSpace ( ) ; assert ( ! DstTy . isVector ( ) ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; if ( ST . getTargetLowering ( ) -> isNoopAddrSpaceCast ( SrcAS , DestAS ) ) { MI . setDesc ( MIRBuilder . getTII ( ) . get ( TargetOpcode :: G_BITCAST ) ) ; return true ; } if ( SrcAS == <ISA_LIT>AS :: FLAT_ADDRESS ) { assert ( DestAS == <ISA_LIT>AS :: LOCAL_ADDRESS || DestAS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; unsigned NullVal = TM . getNullPointerValue ( DestAS ) ; unsigned SegmentNullReg = MRI . createGenericVirtualRegister ( DstTy ) ; unsigned FlatNullReg = MRI . createGenericVirtualRegister ( SrcTy ) ; MIRBuilder . buildConstant ( SegmentNullReg , NullVal ) ; MIRBuilder . buildConstant ( FlatNullReg , <NUM_LIT> ) ; unsigned PtrLo32 = MRI . createGenericVirtualRegister ( DstTy ) ; MIRBuilder . buildExtract ( PtrLo32 , Src , <NUM_LIT> ) ; unsigned CmpRes = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ; MIRBuilder . buildICmp ( CmpInst :: ICMP_NE , CmpRes , Src , FlatNullReg ) ; MIRBuilder . buildSelect ( Dst , CmpRes , PtrLo32 , SegmentNullReg ) ; MI . eraseFromParent ( ) ; return true ; } assert ( SrcAS == <ISA_LIT>AS :: LOCAL_ADDRESS || SrcAS == <ISA_LIT>AS :: PRIVATE_ADDRESS ) ; unsigned FlatNullReg = MRI . createGenericVirtualRegister ( DstTy ) ; unsigned SegmentNullReg = MRI . createGenericVirtualRegister ( SrcTy ) ; MIRBuilder . buildConstant ( SegmentNullReg , TM . getNullPointerValue ( SrcAS ) ) ; MIRBuilder . buildConstant ( FlatNullReg , TM . getNullPointerValue ( DestAS ) ) ; unsigned ApertureReg = getSegmentAperture ( DestAS , MRI , MIRBuilder ) ; unsigned CmpRes = MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) ;

MIRBuilder . buildICmp ( CmpInst :: ICMP_NE , CmpRes , Src , SegmentNullReg ) ;


builtin_function ( <STR_LIT> , FUNTYPE2 ( FLOAT , FLOAT , INT ) , PDP10_BUILTIN_FSC , BUILT_IN_MD , <NUM_LIT> ) ;


<s> return isRegOrImmWithInputMods ( <STR_LIT> , <STR_LIT> ) ;


<s> const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; if ( NumBytes >= - <NUM_LIT> && NumBytes < <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( NumBytes ) ; return ; } BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( Lo_32 ( NumBytes ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( M0 ( <NUM_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( Hi_32 ( NumBytes ) ) ;


<s> gcc_assert ( GET_MODE_NUNITS ( o ) == GET_MODE_NUNITS ( n ) * <NUM_LIT> ) ;

gcc_assert ( GET_MODE_SIZE ( o ) == GET_MODE_SIZE ( n ) ) ;


<s> if ( ! tryAddingSymbolicOperand ( Address , Address + SignExtend32 < <NUM_LIT> > ( Val ) + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( SignExtend32 < <NUM_LIT> > ( Val ) ) ) ; return MCDisassembler :: Success ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>leTargetMachine > X ( The<ISA_LIT>leTarget ) ; RegisterTargetMachine < <ISA_LIT>beTargetMachine > Y ( The<ISA_LIT>beTarget ) ; RegisterTargetMachine < <ISA_LIT>leTargetMachine > Z ( TheARM64Target ) ; auto PR = PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( * PR ) ;

initialize<ISA_LIT>ExpandPseudoPass ( * PR ) ;


<s> } info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; return ( loongarch_valid_base_register_p ( info -> reg , mode , strict_p ) && loongarch_valid_offset_p ( info -> offset , mode ) ) ; case LO_SUM : info -> type = ADDRESS_LO_SUM ; info -> reg = XEXP ( x , <NUM_LIT> ) ; info -> offset = XEXP ( x , <NUM_LIT> ) ; info -> symbol_type = loongarch_classify_symbolic_expression ( info -> offset ) ; return ( loongarch_valid_base_register_p ( info -> reg , mode , strict_p ) && loongarch_valid_lo_sum_p ( info -> symbol_type , mode , info -> offset ) ) ; case CONST_INT :


<s> if ( Fold . isImm ( ) ) { if ( MI -> getDesc ( ) . TSFlags & <STR_LIT> && ! ( MI -> getDesc ( ) . TSFlags & <STR_LIT> ) && <STR_LIT> ( Fold . ImmToFold , ST . hasInv2PiInlineImm ( ) ) ) { unsigned Opcode = MI -> getOpcode ( ) ; int OpNo = MI -> getOperandNo ( & Old ) ; int ModIdx = - <NUM_LIT> ; if ( OpNo == <STR_LIT> ( Opcode , <STR_LIT> :: src0 ) ) ModIdx = <STR_LIT> :: src0_modifiers ; else if ( OpNo == <STR_LIT> ( Opcode , <STR_LIT> :: src1 ) ) ModIdx = <STR_LIT> :: src1_modifiers ; else if ( OpNo == <STR_LIT> ( Opcode , <STR_LIT> :: src2 ) ) ModIdx = <STR_LIT> :: src2_modifiers ; assert ( ModIdx != - <NUM_LIT> ) ; ModIdx = <STR_LIT> ( Opcode , ModIdx ) ; MachineOperand & Mod = MI -> getOperand ( ModIdx ) ; unsigned Val = Mod . getImm ( ) ; if ( ! ( Val & <STR_LIT> ) && ( Val & <STR_LIT> ) ) { switch ( TII . get ( Opcode ) . OpInfo [ OpNo ] . OperandType ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! isUInt < <NUM_LIT> > ( Fold . ImmToFold ) ) { if ( ! ( Fold . ImmToFold & <NUM_LIT> ) ) { Mod . setImm ( Mod . getImm ( ) | <STR_LIT> ) ; Mod . setImm ( Mod . getImm ( ) & ~ <STR_LIT> ) ; Old . ChangeToImmediate ( ( Fold . ImmToFold >> <NUM_LIT> ) & <NUM_LIT> ) ; return true ; } Mod . setImm ( Mod . getImm ( ) & ~ <STR_LIT> ) ; Old . ChangeToImmediate ( Fold . ImmToFold & <NUM_LIT> ) ; return true ; } break ; default : break ; } } } } if ( ( Fold . isImm ( ) || Fold . isFI ( ) || Fold . isGlobal ( ) ) && Fold . needsShrink ( ) ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; auto Liveness = MBB -> computeRegisterLiveness ( & TRI , <STR_LIT> , MI , <NUM_LIT> ) ; if ( Liveness != MachineBasicBlock :: LQR_Dead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI << <STR_LIT> ) ; return false ; } MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; int Op32 = Fold . getShrinkOpcode ( ) ; MachineOperand & Dst0 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & Dst1 = MI -> getOperand ( <NUM_LIT> ) ; assert ( Dst0 . isDef ( ) && Dst1 . isDef ( ) ) ; bool HaveNonDbgCarryUse = ! MRI . use_nodbg_empty ( Dst1 . getReg ( ) ) ; const TargetRegisterClass * Dst0RC = MRI . getRegClass ( Dst0 . getReg ( ) ) ; Register NewReg0 = MRI . createVirtualRegister ( Dst0RC ) ;

MachineInstr * Inst32 = TII . buildShrunkInst ( * MI , Op32 ) ;


<s> static rtx_insn * get_next_active_insn ( rtx_insn * insn , rtx_insn * tail ) { if ( insn == NULL_RTX || insn == tail ) return NULL ; while ( <NUM_LIT> ) {


<s> return ( __m256d ) __builtin_ia32_rsqrt14pd256_mask ( ( __v4df ) __A , ( __v4df ) _mm256_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> setAction ( { Op , s32 } , Legal ) ; for ( auto Ty : { s1 , s8 , s16 } ) setAction ( { Op , <NUM_LIT> , Ty } , Legal ) ; } if ( ST . hasVFP2 ( ) ) { setAction ( { G_FADD , s32 } , Legal ) ; setAction ( { G_FADD , s64 } , Legal ) ; setAction ( { G_LOAD , s64 } , Legal ) ;


<s> unsigned <ISA_LIT>CodeEmitter :: getMachineOpValue ( const MachineInstr & MI , const MachineOperand & MO ) const { if ( MO . isReg ( ) ) { assert ( ( MI . getOpcode ( ) != <STR_LIT> && MI . getOpcode ( ) != <STR_LIT> ) || MO . getReg ( ) < <STR_LIT> || MO . getReg ( ) > <STR_LIT> ) ; return get<ISA_LIT>RegisterNumbering ( MO . getReg ( ) ) ; } assert ( MO . isImm ( ) && <STR_LIT> ) ;


<s> if ( ! DCI . isBeforeLegalizeOps ( ) && N -> getOpcode ( ) == <STR_LIT> && ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { SDNode * ABDNode = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; SDValue NewABD = tryCombineLongOpWithDup ( <STR_LIT> , ABDNode , DCI , DAG ) ; if ( ! NewABD . getNode ( ) ) return SDValue ( ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , N -> getValueType ( <NUM_LIT> ) , NewABD ) ; } return SDValue ( ) ;


<s> _mm_cvt_roundsd_u64 ( __m128d __A , const int __R ) { return ( unsigned long long ) __builtin_ia32_vcvtsd2usi64 ( ( __v2df ) __A , __R ) ;


<s> SDValue <ISA_LIT>SelectionDAGInfo :: EmitTargetCodeForMemcpy ( SelectionDAG & DAG , SDLoc dl , SDValue Chain , SDValue Dst , SDValue Src , SDValue Size , unsigned Align , bool isVolatile , bool AlwaysInline , MachinePointerInfo DstPtrInfo , MachinePointerInfo SrcPtrInfo ) const { unsigned SizeBitWidth = Size . getValueType ( ) . getSizeInBits ( ) ;

if ( ! AlwaysInline && ( Align & <NUM_LIT> ) == <NUM_LIT> && DAG . MaskedValueIsZero ( Size , APInt ( SizeBitWidth , <NUM_LIT> ) ) ) {


<s> std :: vector < std :: string > rep ( Register a ) {


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyStart ( ) { O << <STR_LIT> << * CurrentFnSym << <STR_LIT> ;


<s> bool dominates ( const Waitcnt & Other ) const { return VmCnt <= Other . VmCnt && ExpCnt <= Other . ExpCnt && LgkmCnt <= Other . LgkmCnt && VsCnt <= Other . VsCnt ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerFixedLengthVectorLoadToRVV ( SDValue Op , SelectionDAG & DAG ) const { auto * Load = cast < LoadSDNode > ( Op ) ; SDLoc DL ( Op ) ; MVT VT = Op . getSimpleValueType ( ) ; MVT ContainerVT = getContainerForFixedLengthVector ( VT ) ; SDValue VL = DAG . getConstant ( VT . getVectorNumElements ( ) , DL , Subtarget . getXLenVT ( ) ) ; SDVTList VTs = DAG . getVTList ( { ContainerVT , <STR_LIT> } ) ; SDValue NewLoad = DAG . getMemIntrinsicNode ( <STR_LIT> , DL , VTs , { Load -> getChain ( ) , Load -> getBasePtr ( ) , VL } , Load -> getMemoryVT ( ) , Load -> getMemOperand ( ) ) ; SDValue Result = convertFromScalableVector ( VT , NewLoad , DAG , Subtarget ) ;

return DAG . getMergeValues ( { Result , Load -> getChain ( ) } , DL ) ;


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT ) const override {


<s> if ( X . getOpcode ( ) == <STR_LIT> ) { SDValue A = emitOrXorXorTree ( Op0 , DL , DAG , VecVT , CmpVT , HasPT , SToV ) ; SDValue B = emitOrXorXorTree ( Op1 , DL , DAG , VecVT , CmpVT , HasPT , SToV ) ; if ( VecVT != CmpVT ) return DAG . getNode ( <STR_LIT> , DL , CmpVT , A , B ) ; if ( HasPT ) return DAG . getNode ( <STR_LIT> , DL , VecVT , A , B ) ; return DAG . getNode ( <STR_LIT> , DL , CmpVT , A , B ) ; } else if ( X . getOpcode ( ) == <STR_LIT> ) {


return ( __m512i ) __builtin_ia32_pmovsxbd512_mask ( ( __v16qi ) __A , ( __v16si ) _mm512_undefined_si512 ( ) , ( __mmask16 ) - <NUM_LIT> ) ;


<s> if ( Ty -> isVectorTy ( ) && Ty -> isFPOrFPVectorTy ( ) ) return true ;


<s> const TargetRegisterClass & RC = <STR_LIT> ; const TargetRegisterInfo & TRI = * MF . getSubtarget ( ) . getRegisterInfo ( ) ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned Size = TRI . getSpillSize ( RC ) ; Align Alignment = TRI . getSpillAlign ( RC ) ;

if ( XFI -> isLargeFrame ( MF ) || hasFP ( MF ) ) RS -> addScavengingFrameIndex ( MFI . CreateStackObject ( Size , Alignment , false ) ) ;


<s> const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ; break ; } case MCExpr :: SymbolRef : {

const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ;


<s> } unsigned Opcode = MI -> getOpcode ( ) ; unsigned OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; if ( OpcodeForOffset ) MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; else { int64_t OldOffset = Offset ; int64_t Mask = <NUM_LIT> ; do { Offset = OldOffset & Mask ; OpcodeForOffset = TII -> getOpcodeForOffset ( Opcode , Offset ) ; Mask >>= <NUM_LIT> ; assert ( Mask && <STR_LIT> ) ; } while ( ! OpcodeForOffset ) ; unsigned ScratchReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; int64_t HighOffset = OldOffset - Offset ; if ( MI -> getDesc ( ) . TSFlags & <STR_LIT> && MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getReg ( ) == <NUM_LIT> ) { TII -> loadImmediate ( MBB , MI , ScratchReg , HighOffset ) ; MI -> getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . ChangeToRegister ( ScratchReg , false , false , true ) ; } else { unsigned LAOpcode = TII -> getOpcodeForOffset ( <STR_LIT> , HighOffset ) ; if ( LAOpcode ) BuildMI ( MBB , MI , DL , TII -> get ( LAOpcode ) , ScratchReg ) . addReg ( BasePtr ) . addImm ( HighOffset ) . addReg ( <NUM_LIT> ) ;


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const { bool is64 = getPointerSize ( ) == <NUM_LIT> ; return createMachObjectWriter ( OS , is64 , ( is64 ? object :: mach :: CTM_PowerPC64 : object :: mach :: CTM_PowerPC ) , object :: mach :: CS<ISA_LIT>_ALL , false ) ;


<s> bool <ISA_LIT>AsmParser :: parseDirective<ISA_LIT> ( SMLoc L ) { if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) || check ( ! has<ISA_LIT> ( ) , L , <STR_LIT> ) ) return true ; if ( isThumb ( ) ) SwitchMode ( ) ;

getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code32 ) ;


<s> bool <ISA_LIT>TTIImpl :: supportsEfficientVectorElementLoadStore ( ) const {


<s> bool hasLoadLinkedStoreConditional ( ) const override {


<s> return <ISA_LIT>Lowering -> SelectAddressRegImm ( N , Disp , Base , * CurDAG , <NUM_LIT> ) ;


<s> Relocator :: DWord target = pReloc . target ( ) ; Relocator :: DWord T = getThumbBit ( pReloc ) ; Relocator :: DWord A = helper_sign_extend ( target , <NUM_LIT> ) + pReloc . addend ( ) ; Relocator :: DWord P = pReloc . place ( ) ;

Relocator :: Address S = pReloc . symValue ( ) ;


<s> const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned bytes = Desc . getSize ( ) ; for ( unsigned i = <NUM_LIT> ; i < bytes ; i ++ ) { OS . write ( ( uint8_t ) ( ( Encoding >> ( <NUM_LIT> * i ) ) & <NUM_LIT> ) ) ; } if ( bytes > <NUM_LIT> ) return ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i < e ; ++ i ) { if ( ! isSrcOperand ( Desc , i ) ) continue ; int RCID = Desc . OpInfo [ i ] . RegClass ; const MCRegisterClass & RC = MRI . getRegClass ( RCID ) ; const MCOperand & Op = MI . getOperand ( i ) ; if ( getLitEncoding ( Op , RC . getSize ( ) ) != <NUM_LIT> ) continue ; int64_t Imm = <NUM_LIT> ; if ( Op . isImm ( ) ) Imm = Op . getImm ( ) ; else if ( Op . isExpr ( ) ) { if ( const MCConstantExpr * C = dyn_cast < MCConstantExpr > ( Op . getExpr ( ) ) ) Imm = C -> getValue ( ) ;

} else if ( ! Op . isExpr ( ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> SmallVector < MachineInstr * , <NUM_LIT> > NewMIs ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; LoadRegFromStackSlot ( MF , DL , DestReg , FrameIdx , RC , NewMIs ) ;

for ( unsigned i = <NUM_LIT> , e = NewMIs . size ( ) ; i != e ; ++ i ) MBB . insert ( MI , NewMIs [ i ] ) ;


<s> } if ( OpVT == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; SDValue AnyExt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ;

assert ( OpVT . is128BitVector ( ) && <STR_LIT> ) ;


<s> unsigned getRegisterBitWidth ( bool Vector ) const {


<s> case MachineOperand :: MO_GlobalAddress : return lowerSymbolOperand ( MO , Mang -> getSymbol ( MO . getGlobal ( ) ) , MO . getOffset ( ) ) ; case MachineOperand :: MO_ExternalSymbol : { StringRef Name = MO . getSymbolName ( ) ; return lowerSymbolOperand ( MO , AsmPrinter . GetExternalSymbolSymbol ( Name ) , MO . getOffset ( ) ) ; } case MachineOperand :: MO_JumpTableIndex : return lowerSymbolOperand ( MO , AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) , <NUM_LIT> ) ; case MachineOperand :: MO_ConstantPoolIndex : return lowerSymbolOperand ( MO , AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) , MO . getOffset ( ) ) ; case MachineOperand :: MO_BlockAddress : {

const BlockAddress * BA = MO . getBlockAddress ( ) ;


<s> return __builtin_arm_crc32cw ( __a , __b ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else llvm_unreachable ( <STR_LIT> ) ;


<s> else DecVal = ( Val << <NUM_LIT> ) ;

if ( ! tryAddingSymbolicOperand ( Address , Address + DecVal + <NUM_LIT> , true , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: createImm ( isNeg ? - DecVal : DecVal ) ) ;


<s> memcpy ( m_old_have_regs_of_mode , have_regs_of_mode , sizeof ( have_regs_of_mode ) ) ; for ( int i = <NUM_LIT> ; i < NUM_MACHINE_MODES ; ++ i ) if ( aarch64_sve_mode_p ( ( machine_mode ) i ) ) have_regs_of_mode [ i ] = true ;


<s> case Shape :: SK_Multiple : { multiple ( cast < MultipleShape > ( var ) ) ; break ; } case Shape :: SK_Loop : { loop ( cast < LoopShape > ( var ) ) ;


<s> <ISA_LIT>AsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) {


<s> AMDGPUPassConfig ( TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue r0 = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Addr = getTargetNode ( N , DL , Ty , DAG , <NUM_LIT> ) ; return SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , r0 , Addr ) , <NUM_LIT> ) ;


<s> void addDataSecEntry ( uint32_t Id , const MCSymbol * Sym , uint32_t Size ) { Vars . push_back ( std :: make_tuple ( Id , Sym , Size ) ) ;


<s> void DecodeScalarMoveMask ( unsigned NumElts , bool IsLoad , SmallVectorImpl < int > & ShuffleMask ) {


<s> assert ( <NUM_LIT> && <STR_LIT> ) ; unsigned GlobalBaseReg = getInstrInfo ( ) -> getGlobalBaseReg ( MF ) ;

return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ;


<s> static int unspec_sqrdcmlah ( int rot ) { switch ( rot ) { case <NUM_LIT> : return UNSPEC_SQRDCMLAH ; case <NUM_LIT> : return UNSPEC_SQRDCMLAH90 ; case <NUM_LIT> : return UNSPEC_SQRDCMLAH180 ; case <NUM_LIT> : return UNSPEC_SQRDCMLAH270 ; default : gcc_unreachable ( ) ; }


<s> bool isGFX8Plus ( const MCSubtargetInfo & STI ) {

return isVI ( STI ) || isGFX9Plus ( STI ) ;


<s> if ( ! hasBZHI ( Subtarget , VT ) ) return SDValue ( ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) { SDValue N = Node -> getOperand ( i ) ; LoadSDNode * Ld = dyn_cast < LoadSDNode > ( N . getNode ( ) ) ; if ( ! Ld ) return SDValue ( ) ; const Value * MemOp = Ld -> getMemOperand ( ) -> getValue ( ) ; if ( ! MemOp ) return SDValue ( ) ; if ( const GetElementPtrInst * GEP = dyn_cast < GetElementPtrInst > ( MemOp ) ) { if ( GlobalVariable * GV = dyn_cast < GlobalVariable > ( GEP -> getOperand ( <NUM_LIT> ) ) ) { if ( GV -> isConstant ( ) && GV -> hasDefinitiveInitializer ( ) ) { Constant * Init = GV -> getInitializer ( ) ; Type * Ty = Init -> getType ( ) ; if ( ! isa < ConstantDataArray > ( Init ) || ! Ty -> getArrayElementType ( ) -> isIntegerTy ( ) || Ty -> getArrayElementType ( ) -> getScalarSizeInBits ( ) != VT . getSizeInBits ( ) || Ty -> getArrayNumElements ( ) > Ty -> getArrayElementType ( ) -> getScalarSizeInBits ( ) ) continue ; uint64_t ArrayElementCount = Init -> getType ( ) -> getArrayNumElements ( ) ; bool ConstantsMatch = true ;

for ( uint64_t j = <NUM_LIT> ; j < ArrayElementCount ; j ++ ) {


<s> unsigned AlignmentHint = <NUM_LIT> ; if ( MMO -> getAlign ( ) >= Align ( <NUM_LIT> ) ) AlignmentHint = <NUM_LIT> ; else if ( MMO -> getAlign ( ) >= Align ( <NUM_LIT> ) ) AlignmentHint = <NUM_LIT> ; if ( AlignmentHint == <NUM_LIT> ) return ; LoweredMI . setOpcode ( Opcode ) ; LoweredMI . addOperand ( MCOperand :: createImm ( AlignmentHint ) ) ;


<s> SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( getDataLayout ( ) -> getPointerSize ( ) , <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddressFrameIndex ( DAG ) ;

return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , RetAddrFI , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> bool <ISA_LIT>PassConfig :: addPreEmitPass ( ) { if ( get<ISA_LIT>Subtarget ( ) . isThumb2 ( ) ) { if ( ! get<ISA_LIT>Subtarget ( ) . prefers32BitThumb ( ) ) addPass ( createThumb2SizeReductionPass ( ) ) ; addPass ( & UnpackMachineBundlesID ) ;


<s> short <ISA_LIT>InstrInfo :: getBaseWithLongOffset ( const MachineInstr * MI ) const {

return <STR_LIT> ( MI -> getOpcode ( ) ) ;


<s> static unsigned int rx_hard_regno_nregs ( unsigned int , machine_mode mode ) {

return CLASS_MAX_NREGS ( <NUM_LIT> , mode ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerATOMIC_FENCE ( SDValue Op , SelectionDAG & DAG ) const {


return ( __m128i ) __builtin_ia32_pmovdw256_mask ( ( __v8si ) __A , ( __v8hi ) _mm_setzero_si128 ( ) , __M ) ;


<s> if ( HardenLoads ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> ) ; for ( auto & MBB : MF ) Modified |= slhLoads ( MBB ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SmallVector < MachineBasicBlock * , <NUM_LIT> > EntryBlocks ; EntryBlocks . push_back ( & MF . front ( ) ) ; for ( const LandingPadInfo & LPI : MF . getLandingPads ( ) ) EntryBlocks . push_back ( LPI . LandingPadBlock ) ; for ( auto Entry : EntryBlocks ) insertSPToRegTaintPropagation ( * Entry , Entry -> SkipPHIsLabelsAndDebug ( Entry -> begin ( ) ) ) ; for ( auto & MBB : MF ) { bool UsesFullSpeculationBarrier = false ; Modified |= instrumentControlFlow ( MBB , UsesFullSpeculationBarrier ) ; Modified |= lowerSpeculationSafeValuePseudos ( MBB , UsesFullSpeculationBarrier ) ; } return Modified ;


<s> CallFlags ( CallingConv :: ID CC , bool IsTailCall , bool IsVarArg , bool IsPatchPoint , bool IsIndirect , bool HasNest , bool NoMerge ) : CallConv ( CC ) , IsTailCall ( IsTailCall ) , IsVarArg ( IsVarArg ) , IsPatchPoint ( IsPatchPoint ) , IsIndirect ( IsIndirect ) , HasNest ( HasNest ) , NoMerge ( NoMerge ) {


<s> cvtStExtTWriteBackReg ( MCInst & Inst , const SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;

( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ;


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ; return ( Val >= <NUM_LIT> && Val < <NUM_LIT> ) ;


<s> if ( ResTy == MatchOperand_ParseFail ) return true ; switch ( getLexer ( ) . getKind ( ) ) { default : Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; case AsmToken :: Identifier : if ( ! TryParseRegisterWithWriteBack ( Operands ) ) return false ; if ( ! TryParseShiftRegister ( Operands ) ) return false ; case AsmToken :: Integer : case AsmToken :: Dot : { const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( IdVal , S , E ) ) ; return false ; } case AsmToken :: LBrac : return ParseMemory ( Operands ) ; case AsmToken :: LCurly : return ParseRegisterList ( Operands ) ; case AsmToken :: Hash : S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( ImmVal , S , E ) ) ;


<s> InsertPts . insert ( InsertionPoints :: value_type ( NewPt , IPI -> second ) ) ; IPI = InsertPts . find ( OldInstr ) ;


<s> return LowerOperationWrapper ( N , Results , DAG ) ;


<s> for ( DenseMap < unsigned , unsigned > :: const_iterator It = R<ISA_LIT> . RegToChan . begin ( ) , E = R<ISA_LIT> . RegToChan . end ( ) ; It != E ; ++ It ) { PreviousRegSeqByReg [ ( * It ) . first ] . push_back ( R<ISA_LIT> . Instr ) ; } PreviousRegSeqByUndefCount [ R<ISA_LIT> . UndefReg . size ( ) ] . push_back ( R<ISA_LIT> . Instr ) ;

PreviousRegSeq [ R<ISA_LIT> . Instr ] = R<ISA_LIT> ;


<s> bool <ISA_LIT>GNULDBackend :: finalizeTargetSymbols ( ) { return true ;


<s> Type * SrcTy = Src -> getType ( ) ; if ( ! isTypeLegal ( SrcTy , SrcVT ) ) return false ; if ( SrcVT != <STR_LIT> && SrcVT != <STR_LIT> ) return false ; unsigned SrcReg = getRegForValue ( Src ) ; if ( SrcReg == <NUM_LIT> ) return false ; const TargetRegisterClass * InRC = MRI . getRegClass ( SrcReg ) ; if ( InRC == & <STR_LIT> ) SrcReg = copyRegToRegClass ( & <STR_LIT> , SrcReg ) ; else if ( InRC == & <STR_LIT> ) SrcReg = copyRegToRegClass ( & <STR_LIT> , SrcReg ) ; unsigned DestReg ; unsigned Opc ; auto RC = MRI . getRegClass ( SrcReg ) ; if ( <ISA_LIT>SubTarget -> hasSPE ( ) ) { DestReg = createResultReg ( & <STR_LIT> ) ; if ( IsSigned ) Opc = InRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; else Opc = InRC == & <STR_LIT> ? <STR_LIT> : <STR_LIT> ; } else if ( isVSFRCRegClass ( RC ) ) { DestReg = createResultReg ( & <STR_LIT> ) ; if ( DstVT == <STR_LIT> ) Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; else Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; } else { DestReg = createResultReg ( & <STR_LIT> ) ; if ( DstVT == <STR_LIT> ) if ( IsSigned ) Opc = <STR_LIT> ; else Opc = <ISA_LIT>SubTarget -> hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ;


<s> switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default :


<s> return ! static_cast < const <ISA_LIT>RegisterInfo & > ( TRI ) . isSGPRClass ( & RC ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ;


<s> } SmallPtrSet < Instruction * , <NUM_LIT> > Dead ; while ( ! MaybeDead . empty ( ) ) { auto * I = MaybeDead . front ( ) ; MaybeDead . remove ( I ) ; if ( I -> hasNUsesOrMore ( <NUM_LIT> ) ) continue ; for ( auto & U : I -> operands ( ) ) if ( auto * OpI = dyn_cast < Instruction > ( U ) ) MaybeDead . insert ( OpI ) ; I -> dropAllReferences ( ) ; Dead . insert ( I ) ; } for ( auto * I : Dead ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; I -> dump ( ) ) ; I -> eraseFromParent ( ) ; } for ( auto I : L -> blocks ( ) ) DeleteDeadPHIs ( I ) ;


<s> case 'Q' : case 'R' : case 'S' : case 'T' : if ( GET_CODE ( op ) != MEM ) return <NUM_LIT> ; return s390_check_qrst_address ( c , XEXP ( op , <NUM_LIT> ) , true ) ; case 'U' : return ( s390_check_qrst_address ( 'Q' , op , true ) || s390_check_qrst_address ( 'R' , op , true ) ) ; case 'W' : return ( s390_check_qrst_address ( 'S' , op , true ) || s390_check_qrst_address ( 'T' , op , true ) ) ;


<s> SDLoc DL ( Op ) ; LoadSDNode * LN = cast < LoadSDNode > ( Op . getNode ( ) ) ; const SDValue & Base = LN -> getBasePtr ( ) ; const SDValue & Offset = LN -> getOffset ( ) ; if ( Is<ISA_LIT>Global ( Base ) ) { if ( ! Offset -> isUndef ( ) ) report_fatal_error ( <STR_LIT> , false ) ; SDVTList Tys = DAG . getVTList ( LN -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ; SDValue Ops [ ] = { LN -> getChain ( ) , Base } ; return DAG . getMemIntrinsicNode ( <STR_LIT> , DL , Tys , Ops , LN -> getMemoryVT ( ) , LN -> getMemOperand ( ) ) ; } if ( Optional < unsigned > Local = Is<ISA_LIT>Local ( Base , DAG ) ) { if ( ! Offset -> isUndef ( ) ) report_fatal_error ( <STR_LIT> , false ) ; SDValue Idx = DAG . getTargetConstant ( * Local , Base , <STR_LIT> ) ; EVT LocalVT = LN -> getValueType ( <NUM_LIT> ) ; SDValue LocalGet = DAG . getNode ( <STR_LIT> , DL , LocalVT , { LN -> getChain ( ) , Idx } ) ;

SDValue Result = DAG . getMergeValues ( { LocalGet , LN -> getChain ( ) } , DL ) ;


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { printRegName ( O , Op . getReg ( ) ) ; return ; }


<s> DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: HVXMemLatencyMutation > ( ) ) ; DAG -> addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: CallMutation > ( ) ) ;

DAG -> addMutation ( createCopyConstrainDAGMutation ( DAG -> TII , DAG -> TRI ) ) ;


<s> <ISA_LIT>ebTargetMachine :: <ISA_LIT>ebTargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , false ) {


<s> MCAsmParserExtension :: Initialize ( _Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; ITState . CurPosition = ~ <NUM_LIT> ; NextSymbolIsThumb = false ;


<s> int64_t ElementBits = VT . getScalarSizeInBits ( ) ; if ( ! getVShiftImm ( Op , ElementBits , Cnt ) ) return false ;

return ( Cnt >= <NUM_LIT> && ( isLong ? Cnt - <NUM_LIT> : Cnt ) < ElementBits ) ;


<s> auto Pos = llvm :: <STR_LIT> ( ) ; AAPointerInfo :: OffsetAndSize OAS ( Pos , <NUM_LIT> ) ;

return funcRetrievesImplicitKernelArg ( A , OAS ) ;


<s> IFOrdering ( const UnsignedMap & UC , const RegisterOrdering & BO ) : UseC ( UC ) , BaseOrd ( BO ) {


<s> Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant ( ) , getKind ( ) ) ;


<s> return false ; } unsigned PtrSize = ValTy . getElementType ( ) . getSizeInBits ( ) ; const LLT NewTy = LLT :: vector ( ValTy . getElementCount ( ) , PtrSize ) ; auto & MMO = * * MI . memoperands_begin ( ) ; MMO . setType ( NewTy ) ; if ( MI . getOpcode ( ) == TargetOpcode :: G_STORE ) { auto Bitcast = MIRBuilder . buildBitcast ( NewTy , ValReg ) ; MIRBuilder . buildStore ( Bitcast . getReg ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) , MMO ) ;


<s> static void EmitHiLo ( MCStreamer & OutStreamer , MCSymbol * GOTSym , <ISA_LIT>MCExpr :: VariantKind HiKind , <ISA_LIT>MCExpr :: VariantKind LoKind , MCOperand & RD , MCContext & OutContext , const MCSubtargetInfo & STI ) {

MCOperand hi = create<ISA_LIT>MCOperand ( HiKind , GOTSym , OutContext ) ;


<s> void LinearizedRegion :: setHasLoop ( bool Value ) { HasLoop = Value ;


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineFunction * F = MBB -> getParent ( ) ; MachineFunction :: iterator MBBIter = ++ MBB -> getIterator ( ) ; MachineBasicBlock * XMMSaveMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * EndMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( MBBIter , XMMSaveMBB ) ; F -> insert ( MBBIter , EndMBB ) ; EndMBB -> splice ( EndMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; EndMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( XMMSaveMBB ) ; XMMSaveMBB -> addSuccessor ( EndMBB ) ; const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned CountReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t RegSaveFrameIndex = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; int64_t VarArgsFPOffset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! Subtarget . isCallingConvWin64 ( F -> getFunction ( ) . getCallingConv ( ) ) ) { BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addReg ( CountReg ) . addReg ( CountReg ) ; BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) ) . addMBB ( EndMBB ) . addImm ( <STR_LIT> ) ; MBB -> addSuccessor ( EndMBB ) ; } assert ( ( MI . getNumOperands ( ) <= <NUM_LIT> || ! MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . isReg ( ) || MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && <STR_LIT> ) ; unsigned MOVOpc = Subtarget . hasAVX ( ) ? <STR_LIT> : <STR_LIT> ; for ( int i = <NUM_LIT> , e = MI . getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { int64_t Offset = ( i - <NUM_LIT> ) * <NUM_LIT> + VarArgsFPOffset ; MachineMemOperand * MMO = F -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * F , RegSaveFrameIndex , Offset ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( XMMSaveMBB , DL , TII -> get ( MOVOpc ) ) . addFrameIndex ( RegSaveFrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) . addReg ( MI . getOperand ( i ) . getReg ( ) ) . addMemOperand ( MMO ) ;


<s> Instruction & Inst = * I ; if ( const ReturnInst * RI = dyn_cast < ReturnInst > ( I ) ) { Value * RVal = RI -> getReturnValue ( ) ; if ( ! RVal ) continue ; Type * T = RVal -> getType ( ) ; FPReturnVariant RV = whichFPReturnVariant ( T ) ; if ( RV == NoFPRet ) continue ; static const char * Helper [ NoFPRet ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const char * Name = Helper [ RV ] ; AttributeSet A ; Value * Params [ ] = { RVal } ; Modified = true ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , <STR_LIT> ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: ReadNone ) ; A = A . addAttribute ( C , AttributeSet :: FunctionIndex , Attribute :: NoInline ) ; Value * F = ( M -> getOrInsertFunction ( Name , A , MyVoid , T , NULL ) ) ; CallInst :: Create ( F , Params , <STR_LIT> , & Inst ) ; } else if ( const CallInst * CI = dyn_cast < CallInst > ( I ) ) { if ( Subtarget . getRelocationModel ( ) != Reloc :: PIC_ ) { Function * F_ = CI -> getCalledFunction ( ) ;

if ( F_ && ! isIntrinsicInline ( F_ ) && needsFPHelperFromSig ( * F_ ) ) {


<s> LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;

InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ;


<s> SDLoc dl ( Op ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; EVT VT = Op . getValueType ( ) ; EVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; EVT NodeTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDValue Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , None ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> , dl , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD1 , CWD2 ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , dl , VT , RetVal ) ;


<s> if ( <ISA_LIT>InstrInfo :: isSMRD ( * MI ) && checkSMRDHazards ( MI ) > <NUM_LIT> ) return NoopHazard ;

if ( <ISA_LIT>InstrInfo :: isVMEM ( * MI ) && checkVMEMHazards ( MI ) > <NUM_LIT> ) return NoopHazard ;


<s> if ( Code . LastM == MA . Id ) Code . LastM = NA . Id ;


<s> inline bool is_t2_so_imm_not ( unsigned Imm ) const { return <STR_LIT> ( ~ Imm ) != - <NUM_LIT> ;


<s> logical_func = ( GET_CODE ( old_true ) == EQ ) ? gen_andcr : gen_andncr ; * p_true = gen_rtx_NE ( CC_CCRmode , cr , const0_rtx ) ; * p_false = gen_rtx_EQ ( CC_CCRmode , cr , const0_rtx ) ; } else { old_test = old_false ; test_expr = false_expr ; logical_func = ( GET_CODE ( old_false ) == EQ ) ? gen_orcr : gen_orncr ; * p_true = gen_rtx_EQ ( CC_CCRmode , cr , const0_rtx ) ; * p_false = gen_rtx_NE ( CC_CCRmode , cr , const0_rtx ) ; } frv_ifcvt_add_insn ( ( * logical_func ) ( cr , cr , new_cr ) , BB_END ( bb ) , TRUE ) ; cc = XEXP ( test_expr , <NUM_LIT> ) ; compare = gen_rtx_fmt_ee ( GET_CODE ( test_expr ) , CC_CCRmode , cc , const0_rtx ) ; if_else = gen_rtx_IF_THEN_ELSE ( CC_CCRmode , old_test , compare , const0_rtx ) ; check_insn = gen_rtx_SET ( VOIDmode , new_cr , if_else ) ; frv_ifcvt_add_insn ( check_insn , BB_END ( bb ) , TRUE ) ; if ( TARGET_DEBUG_COND_EXEC ) { fputs ( <STR_LIT> , stderr ) ; debug_rtx ( * p_true ) ; fputs ( <STR_LIT> , stderr ) ; debug_rtx ( * p_false ) ; } return ; fail : * p_true = * p_false = NULL_RTX ; if ( new_cr ) { CLEAR_HARD_REG_BIT ( frv_ifcvt . tmp_reg . regs , REGNO ( new_cr ) ) ; * p_new_cr = NULL_RTX ; } if ( TARGET_DEBUG_COND_EXEC ) fputs ( <STR_LIT> , stderr ) ; return ;


<s> bool <ISA_LIT>AsmParser :: RegisterMatchesArch ( unsigned MatchNum ) const { if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( MatchNum ) ) if ( ! getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) return false ;


<s> if ( C . CallConstructionID == MachineOutlinerTailCall ) { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ;


<s> return new <ISA_LIT>PassConfig ( * this , & PM ) ;


<s> if ( ( mask & <NUM_LIT> ) != <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i <<= <NUM_LIT> ) if ( ( mask & i ) == <NUM_LIT> ) ++ count ;


<s> void <ISA_LIT>TargetMachine :: anchor ( ) {


<s> explicit <ISA_LIT>FastISel ( FunctionLoweringInfo & funcInfo , const TargetLibraryInfo * libInfo ) : FastISel ( funcInfo , libInfo ) {


<s> MachineFunction & MF = * B . getParent ( ) ; auto & HST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; auto & MFI = MF . getFrameInfo ( ) ; auto & HRI = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ; MachineInstr * MI = & * It ; if ( ! MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) return false ; LivePhysRegs LPR ( & HRI ) ; LPR . addLiveIns ( B ) ; SmallVector < std :: pair < unsigned , const MachineOperand * > , <NUM_LIT> > Clobbers ; for ( auto R = B . begin ( ) ; R != It ; ++ R ) LPR . stepForward ( * R , Clobbers ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned SrcR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcLo = HRI . getSubReg ( SrcR , <STR_LIT> ) ; unsigned SrcHi = HRI . getSubReg ( SrcR , <STR_LIT> ) ; bool IsKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool Is128B = HST . useHVXDblOps ( ) ; auto * RC = ! Is128B ? & <STR_LIT> : & <STR_LIT> ; unsigned Size = RC -> getSize ( ) ; unsigned NeedAlign = RC -> getAlignment ( ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned StoreOpc ;


<s> if ( ! User -> isMachineOpcode ( ) ) return false ; if ( User -> getMachineOpcode ( ) != <STR_LIT> && User -> getMachineOpcode ( ) != <STR_LIT> ) return false ; SDNode * Op2 = User -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ! Op2 -> isMachineOpcode ( ) ) return false ; if ( Op2 -> getMachineOpcode ( ) != <STR_LIT> && Op2 -> getMachineOpcode ( ) != <STR_LIT> ) return false ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op2 -> getOperand ( <NUM_LIT> ) ) ; if ( ! C ) return false ; if ( ! C -> isNullValue ( ) ) return false ; }


<s> Result = decodeInstruction ( DecoderTable32 , instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; }


<s> AU . addRequired < MachineDominanceFrontier > ( ) ;


<s> if ( hard_frame_needed ) regs [ i ++ ] = gen_rtx_REG ( Pmode , HARD_FRAME_POINTER_REGNUM ) ; if ( ! ( REGNO ( fp ) == STACK_POINTER_REGNUM || ( hard_frame_needed && REGNO ( fp ) == HARD_FRAME_POINTER_REGNUM ) ) ) regs [ i ++ ] = fp ;


<s> AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT> ) ; return Modified ;


<s> static <ISA_LIT>Operand :: Ptr CreateExpr ( const <ISA_LIT>AsmParser * AsmParser , const class MCExpr * Expr , SMLoc S ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( Expression , AsmParser ) ; Op -> Expr = Expr ; Op -> StartLoc = S ; Op -> EndLoc = S ; return Op ;


<s> assert ( CPI < ConstPoolId2AddrMap . size ( ) ) ; ConstPoolId2AddrMap [ CPI ] = Addr ;


<s> if ( Ty -> isIntOrIntVectorTy ( ) ) { ISD = IsUnsigned ? <STR_LIT> : <STR_LIT> ; } else { assert ( Ty -> isFPOrFPVectorTy ( ) && <STR_LIT> ) ; ISD = <STR_LIT> ; } static const CostTblEntry SSE1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE41CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry AVX512CostTbl [ ] = {


<s> bool <ISA_LIT>AsmPrinter :: printAsmRegInClass ( const MachineOperand & MO , const TargetRegisterClass * RC , bool isVector , raw_ostream & O ) { assert ( MO . isReg ( ) && <STR_LIT> ) ;

const <ISA_LIT>RegisterInfo * RI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getRegisterInfo ( ) ;


<s> unsigned Val = MI -> getOperand ( OpNo ) . getImm ( ) ; bool Valid ; StringRef Name = <STR_LIT> ( ) . toString ( Val , STI . getFeatureBits ( ) , Valid ) ; if ( Valid ) O << Name . upper ( ) ;

else O << <STR_LIT> << formatImm ( Val ) ;


<s> CurInstKind = NextInstKind ; } if ( CurInstKind == IDAlu ) { switch ( getAluKind ( SU ) ) { case AluT_XYZW : CurEmitted += <NUM_LIT> ; break ; case AluDiscarded : break ; default : { ++ CurEmitted ; for ( MachineInstr :: mop_iterator It = SU -> getInstr ( ) -> operands_begin ( ) , E = SU -> getInstr ( ) -> operands_end ( ) ; It != E ; ++ It ) { MachineOperand & MO = * It ; if ( MO . isReg ( ) && MO . getReg ( ) == AMDGPU :: ALU_LITERAL_X ) ++ CurEmitted ; } } } } else { ++ CurEmitted ; } DEBUG ( dbgs ( ) << CurEmitted << <STR_LIT> ) ; if ( CurInstKind != IDFetch ) { MoveUnits ( Pending [ IDFetch ] , Available [ IDFetch ] ) ; }

MoveUnits ( Pending [ IDOther ] , Available [ IDOther ] ) ;


<s> auto SetI = BuildMI ( TestMBB , TestPos , TestLoc , TII -> get ( <STR_LIT> ) , Reg ) . addImm ( Cond ) ; ( void ) SetI ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; SetI -> dump ( ) ) ; ++ NumSetCCsInserted ;


<s> case VK_<ISA_LIT>_TPREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_ADD : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GOT_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_HI : return <STR_LIT> ; case VK_<ISA_LIT>_CAPTAB_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TPREL_CINCOFFSET : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_IE_CAPTAB_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_TLS_GD_CAPTAB_PCREL_HI : return <STR_LIT> ; case VK_<ISA_LIT>_CALL : return <STR_LIT> ; case VK_<ISA_LIT>_CALL_PLT : return <STR_LIT> ; case VK_<ISA_LIT>_CCALL : return <STR_LIT> ; case VK_<ISA_LIT>_32_PCREL : return <STR_LIT> ; }


<s> FunctionPass * llvm :: createPromoteMemoryToRegsPass ( ) {


<s> RCPair <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const std :: string & Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'l' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'h' : if ( Subtarget -> isThumb ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'r' : if ( Subtarget -> isThumb1Only ( ) ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; case 'w' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : if ( VT == <STR_LIT> ) break ; if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 't' : if ( VT == <STR_LIT> ) return RCPair ( <NUM_LIT> , & <STR_LIT> ) ; break ; } } if ( StringRef ( <STR_LIT> ) . equals_lower ( Constraint ) ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ;

return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ;


<s> const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! MCE ) return false ; int64_t Val = MCE -> getValue ( ) ;

return ( Val >= <NUM_LIT> && Val < <NUM_LIT> ) ;


<s> Mop != Instr -> operands_end ( ) ; ++ Mop ) { if ( isSameOperand ( * Mop , * Reg ) ) return true ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> <ISA_LIT>AbstractMemberAccessLegacyPass ( <ISA_LIT>TargetMachine * TM = nullptr ) : FunctionPass ( ID ) , TM ( TM ) {


<s> const SDNodeFlags * Flags = Op -> getFlags ( ) ; if ( Unsafe || Flags -> hasAllowReciprocal ( ) ) { SDNodeFlags Flags ; Flags . setUnsafeAlgebra ( true ) ; SDValue Recip = DAG . getNode ( <STR_LIT> , SL , VT , RHS ) ; return DAG . getNode ( <STR_LIT> , SL , VT , LHS , Recip , & Flags ) ; }


<s> Type * indType = len -> getType ( ) ; BasicBlock * origBB = splitAt -> getParent ( ) ; BasicBlock * newBB = splitAt -> getParent ( ) -> splitBasicBlock ( splitAt , <STR_LIT> ) ; BasicBlock * loopBB = BasicBlock :: Create ( Context , <STR_LIT> , & F , newBB ) ; origBB -> getTerminator ( ) -> setSuccessor ( <NUM_LIT> , loopBB ) ; IRBuilder < > builder ( origBB , origBB -> getTerminator ( ) ) ; unsigned srcAS = dyn_cast < PointerType > ( srcAddr -> getType ( ) ) -> getAddressSpace ( ) ; unsigned dstAS = dyn_cast < PointerType > ( dstAddr -> getType ( ) ) -> getAddressSpace ( ) ; srcAddr = builder . CreateBitCast ( srcAddr , Type :: getInt8PtrTy ( Context , srcAS ) ) ; dstAddr = builder . CreateBitCast ( dstAddr , Type :: getInt8PtrTy ( Context , dstAS ) ) ; IRBuilder < > loop ( loopBB ) ; PHINode * ind = loop . CreatePHI ( indType , <NUM_LIT> ) ; ind -> addIncoming ( ConstantInt :: get ( indType , <NUM_LIT> ) , origBB ) ; Value * val = loop . CreateLoad ( loop . CreateGEP ( srcAddr , ind ) , srcVolatile ) ; loop . CreateStore ( val , loop . CreateGEP ( dstAddr , ind ) , dstVolatile ) ; Value * newind = loop . CreateAdd ( ind , ConstantInt :: get ( indType , <NUM_LIT> ) ) ; ind -> addIncoming ( newind , loopBB ) ; loop . CreateCondBr ( loop . CreateICmpULT ( newind , len ) , loopBB , newBB ) ;


<s> gcc_assert ( ! last_bytes || part_bytes_reg ) ; if ( BYTES_BIG_ENDIAN && last_bytes ) { rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp , part_bytes_reg , GEN_INT ( <NUM_LIT> * ( <NUM_LIT> - last_bytes ) ) ) ) ; part_bytes_reg = tmp ; while ( last_bytes ) { mem = adjust_automodify_address ( dstbase , QImode , plus_constant ( Pmode , dst , last_bytes - <NUM_LIT> ) , dstoffset + last_bytes - <NUM_LIT> ) ; emit_move_insn ( mem , gen_lowpart ( QImode , part_bytes_reg ) ) ; if ( -- last_bytes ) { tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_lshrsi3 ( tmp , part_bytes_reg , GEN_INT ( <NUM_LIT> ) ) ) ; part_bytes_reg = tmp ; } } } else { if ( last_bytes > <NUM_LIT> ) { mem = adjust_automodify_address ( dstbase , HImode , dst , dstoffset ) ; emit_move_insn ( mem , gen_lowpart ( HImode , part_bytes_reg ) ) ; last_bytes -= <NUM_LIT> ; if ( last_bytes ) { rtx tmp = gen_reg_rtx ( SImode ) ; emit_insn ( gen_addsi3 ( dst , dst , const2_rtx ) ) ; emit_insn ( gen_lshrsi3 ( tmp , part_bytes_reg , GEN_INT ( <NUM_LIT> ) ) ) ; part_bytes_reg = tmp ; dstoffset += <NUM_LIT> ; } } if ( last_bytes ) {

mem = adjust_automodify_address ( dstbase , QImode , dst , dstoffset ) ;


<s> if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } else if ( Store -> getMemoryVT ( ) == <STR_LIT> ) { Mask = <NUM_LIT> ; } SDValue Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , Store -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue MaskedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) , DAG . getConstant ( Mask , <STR_LIT> ) ) ; SDValue ShiftedValue = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MaskedValue , ShiftAmt ) ; SDValue RotrAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , ShiftAmt ) ; SDValue DstMask = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( Mask , <STR_LIT> ) , RotrAmt ) ; Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , DstMask ) ; Dst = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Dst , ShiftedValue ) ; Values . push_back ( Dst ) ; } else if ( VT == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { Values . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Store -> getValue ( ) , DAG . getConstant ( i , <STR_LIT> ) ) ) ; }


<s> if ( mode == SImode ) gcc_assert ( ! TARGET_IDIV ) ; machine_mode libval_mode = smallest_mode_for_size ( <NUM_LIT> * GET_MODE_BITSIZE ( mode ) , MODE_INT ) ; rtx libval = emit_library_call_value ( libfunc , NULL_RTX , LCT_CONST , libval_mode , <NUM_LIT> , op0 , GET_MODE ( op0 ) , op1 , GET_MODE ( op1 ) ) ;

rtx quotient = simplify_gen_subreg ( mode , libval , libval_mode , <NUM_LIT> ) ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ; return X ;


<s> std :: vector < std :: string > modr_eemod ( ArpRn2 a , ArpStep2 asi , ArpStep2 asj ) { return D ( <STR_LIT> , MemARPSI ( a , asi ) , MemARPSJ ( a , asj ) , <STR_LIT> ) ;


<s> unsigned Reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Reg = getReg ( Decoder , <STR_LIT> , Reg ) ; Base = getReg ( Decoder , <STR_LIT> , Base ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; Inst . addOperand ( MCOperand :: createReg ( Base ) ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler :: Success ;


<s> break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : return <NUM_LIT> ; } Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = Subtarget -> classifyLocalReference ( nullptr ) ; if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( Subtarget -> is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; unsigned CPI = MCP . getConstantPoolIndex ( CFP , Alignment . value ( ) ) ; unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT . SimpleTy ) ) ; if ( CM == CodeModel :: Large ) {

unsigned AddrReg = createResultReg ( & <STR_LIT> ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; case 'i' : Imm |= <STR_LIT> ; break ; case 'o' : Imm |= <STR_LIT> ; break ; case 'r' : Imm |= <STR_LIT> ; break ; case 'w' : Imm |= <STR_LIT> ; break ; } } Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case CodeModel :: Small : case CodeModel :: Kernel : { return <STR_LIT> ; } case CodeModel :: Medium : { if ( isPositionIndependent ( ) ) { if ( IsM68020 ) {


<s> void <ISA_LIT>CompilationCallback ( ) { llvm_unreachable ( <STR_LIT> ) ;


<s> EVT ExVT = N -> getValueType ( <NUM_LIT> ) ; unsigned ES = ExVT . getVectorElementType ( ) . getSizeInBits ( ) ; uint64_t MV = <NUM_LIT> , Bit = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NE ; ++ i ) { MV |= Bit ; Bit <<= ES ; } SDValue Ones = CurDAG -> getTargetConstant ( MV , dl , <STR_LIT> ) ; SDNode * OnesReg = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Ones ) ; if ( ExVT . getSizeInBits ( ) == <NUM_LIT> ) { SDNode * And = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Mask , <NUM_LIT> ) , SDValue ( OnesReg , <NUM_LIT> ) ) ; SDValue SubR = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , dl , ExVT , SDValue ( And , <NUM_LIT> ) , SubR ) ) ; return ; } ReplaceNode ( N , CurDAG -> getMachineNode ( <STR_LIT> , dl , ExVT , SDValue ( Mask , <NUM_LIT> ) , SDValue ( OnesReg , <NUM_LIT> ) ) ) ; return ; } SDNode * IsIntrinsic = N -> getOperand ( <NUM_LIT> ) . getNode ( ) ; if ( ( IsIntrinsic -> getOpcode ( ) == <STR_LIT> ) ) { unsigned ID = cast < ConstantSDNode > ( IsIntrinsic -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( doesIntrinsicReturnPredicate ( ID ) ) { if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDNode * Result_1 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IsIntrinsic , <NUM_LIT> ) ) ; SDNode * Result_2 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , TargetConst0 ) ; SDNode * Result_3 = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , SDValue ( Result_2 , <NUM_LIT> ) , SDValue ( Result_1 , <NUM_LIT> ) ) ; ReplaceNode ( N , Result_3 ) ; return ; } if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDNode * RsPd = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( IsIntrinsic , <NUM_LIT> ) ) ; ReplaceNode ( N , RsPd ) ; return ; }


<s> static tree arm_cxx_guard_type ( void ) { return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node ;


<s> const <ISA_LIT>Subtarget * getST ( ) const {


<s> } else { assert ( MO . isExpr ( ) && <STR_LIT> ) ;

MO . getExpr ( ) -> print ( O , & MAI ) ;


<s> DAG . getContext ( ) -> emitError ( <STR_LIT> ) ; return SDValue ( ) ; } MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ;

SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> , VT ) ;


<s> case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ; if ( ! isInt < <NUM_LIT> > ( Value ) && Ctx ) { Ctx -> reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; return <NUM_LIT> ; } break ; case <STR_LIT> : Value -= <NUM_LIT> ; Value = ( int64_t ) Value / <NUM_LIT> ;


<s> return isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && N -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ; } else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { return N -> getOperand ( <NUM_LIT> ) == N -> getOperand ( <NUM_LIT> ) && isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) && N -> getConstantOperandVal ( <NUM_LIT> ) == <NUM_LIT> ; } return false ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> :

return isIntN ( <NUM_LIT> , SignExtend64 ( BrOffset + <NUM_LIT> , XLen ) ) ;


<s> return ( __m512 ) __builtin_ia32_broadcastf32x2_512_mask ( ( __v4sf ) __A , ( __v16sf ) _mm512_setzero_ps ( ) , __M ) ;


<s> BBI . PostAlign = <NUM_LIT> ; for ( MachineInstr & I : * MBB ) { BBI . Size += TII -> getInstSizeInBytes ( I ) ; if ( I . isInlineAsm ( ) ) BBI . Unalign = isThumb ? <NUM_LIT> : <NUM_LIT> ; else if ( isThumb && mayOptimizeThumb2Instruction ( & I ) ) BBI . Unalign = <NUM_LIT> ; } if ( ! MBB -> empty ( ) && MBB -> back ( ) . getOpcode ( ) == <STR_LIT> ) { BBI . PostAlign = <NUM_LIT> ; MBB -> getParent ( ) -> ensureLogAlignment ( <NUM_LIT> ) ;


<s> long long d ; __asm__ ( <STR_LIT> : <STR_LIT> ( d ) : <STR_LIT> ( a ) ) ;


<s> case LT : case LTU : return IMM12_OPERAND ( x ) ; case EQ : case NE : case GT : case GTU : return x == <NUM_LIT> ; case GE : case GEU : return x == <NUM_LIT> ; case LE : return IMM12_OPERAND ( x + <NUM_LIT> ) ; case LEU : return IMM12_OPERAND ( x + <NUM_LIT> ) && x + <NUM_LIT> != <NUM_LIT> ; case SIGN_EXTRACT : case ZERO_EXTRACT :


<s> MachineBasicBlock * MBB = & * I ; if ( ! MDT -> isReachableFromEntry ( MBB ) ) continue ;

for ( MachineBasicBlock :: iterator MII = MBB -> getFirstTerminator ( ) , MIIE = MBB -> end ( ) ; MII != MIIE ; ++ MII ) {


<s> case ELF :: R_LANAI_21_F : case ELF :: R_LANAI_25 : case ELF :: R_LANAI_32 : case ELF :: R_LANAI_HI16 : return true ; default : return false ; }


<s> DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; if ( MBBI -> getOpcode ( ) != <STR_LIT> ) llvm_unreachable ( <STR_LIT> ) ; if ( hasFP ( MF ) ) { } int stacksize = ( int ) MFI -> getStackSize ( ) ; if ( hasFP ( MF ) ) stacksize += <NUM_LIT> ;

TII . adjustStackPtr ( stacksize , MBB , MBBI ) ;


<s> res . as_char [ <NUM_LIT> ] = __b2 ; res . as_char [ <NUM_LIT> ] = __b3 ; res . as_char [ <NUM_LIT> ] = __b4 ; res . as_char [ <NUM_LIT> ] = __b5 ; res . as_char [ <NUM_LIT> ] = __b6 ;


<s> case <STR_LIT> : break ; case <STR_LIT> : \ return <STR_LIT> # NODE ; }


<s> static MachineInstr * elideCopies ( MachineInstr * MI , const MachineRegisterInfo * MRI ) { while ( true ) {

if ( ! MI -> isFullCopy ( ) ) return MI ;


<s> return ( epilogue_completed && cfun -> machine -> no_caller_saved_registers && ! fixed_regs [ regno ] && ! STACK_REGNO_P ( regno ) && ! MMX_REGNO_P ( regno ) ) ;


<s> if ( ConvertResult && ! ConvertResult ( Value ) ) { return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , Value , S , ImmTy ) ) ; return MatchOperand_Success ;


<s> if ( ! target || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ; gcc_assert ( ( GET_MODE ( op0 ) == mode0 || GET_MODE ( op0 ) == VOIDmode ) && ( GET_MODE ( op1 ) == mode1 || GET_MODE ( op1 ) == VOIDmode ) && ( GET_MODE ( op2 ) == mode2 || GET_MODE ( op2 ) == VOIDmode ) ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op1 , mode1 ) ) op1 = copy_to_mode_reg ( mode1 , op1 ) ; if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op2 , mode2 ) ) op2 = copy_to_mode_reg ( mode2 , op2 ) ; if ( builtin_sha1cpm_p ) op3 = GEN_INT ( TARGET_BIG_END ? <NUM_LIT> : <NUM_LIT> ) ; if ( builtin_sha1cpm_p ) pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 , op3 ) ; else pat = GEN_FCN ( icode ) ( target , op0 , op1 , op2 ) ; if ( ! pat ) return <NUM_LIT> ;


return __builtin_mve_vabsq_m_fv4sf ( __arm_vuninitializedq_f32 ( ) , __a , __p ) ;


<s> void pdp11_output_labelref ( FILE * file , const char * name ) { if ( ! TARGET_DEC_ASM ) fputs ( USER_LABEL_PREFIX , file ) ; fputs ( name , file ) ;


<s> int NumLCM = BaseOpcode -> LodOrClampOrMip ? <NUM_LIT> : <NUM_LIT> ; int NumVAddr = BaseOpcode -> NumExtraArgs + NumGradients + NumCoords + NumLCM ; return { NumVAddr , NumGradients } ;


<s> MachineInstr & UseMI = * MRI . use_instr_nodbg_begin ( CondDef ) ; return UseMI . getParent ( ) == MI . getParent ( ) && UseMI . getOpcode ( ) == <STR_LIT> ? & UseMI : nullptr ;


<s> static const unsigned LoadAcqs [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; static const unsigned StoreBares [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; static const unsigned StoreRels [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ;

const unsigned ( * LoadOps ) [ <NUM_LIT> ] , ( * StoreOps ) [ <NUM_LIT> ] ;


<s> const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) return MO . getImm ( ) >> <NUM_LIT> ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , Expr , MCFixupKind ( <STR_LIT> ) ) ) ;


<s> TII = STI . getInstrInfo ( ) ; for ( Block & MBB : MF ) {

bool BlockModified = runOnBasicBlock ( MBB ) ;


<s> gimple * fold_type ( gimple_folder & f ) const { T arg0 , arg1 ; if ( ! poly_int_tree_p ( gimple_call_arg ( f . call , <NUM_LIT> ) , & arg0 ) || ! poly_int_tree_p ( gimple_call_arg ( f . call , <NUM_LIT> ) , & arg1 ) ) return NULL ; if ( m_eq_p ? known_gt ( arg0 , arg1 ) : known_ge ( arg0 , arg1 ) ) return f . fold_to_pfalse ( ) ; if ( m_eq_p ? maybe_gt ( arg0 , arg1 ) : maybe_ge ( arg0 , arg1 ) ) return NULL ; poly_uint64 diff = arg1 - arg0 ; poly_uint64 nelts = GET_MODE_NUNITS ( f . vector_mode ( <NUM_LIT> ) ) ;


<s> LastMappingSymbols . clear ( ) ; LastEMS = EMS_None ;


<s> maybeUpdateTerminator ( MBB ) ; break ; } for ( ; ; ) { Next = Ready . top ( ) ; Ready . pop ( ) ; if ( ! Entries . empty ( ) && ! MDT . dominates ( Entries . back ( ) . TheRegion -> getHeader ( ) , Next ) ) { Entries . back ( ) . Deferred . push_back ( Next ) ; continue ; } break ; } } Next -> moveAfter ( MBB ) ; maybeUpdateTerminator ( MBB ) ; MBB = Next ; } assert ( Entries . empty ( ) && <STR_LIT> ) ; MF . RenumberBlocks ( ) ; SmallSetVector < const Region * , <NUM_LIT> > OnStack ; OnStack . insert ( nullptr ) ; for ( auto & MBB : MF ) { assert ( MBB . getNumber ( ) >= <NUM_LIT> && <STR_LIT> ) ; const Region * Region = RI . getRegionFor ( & MBB ) ; if ( Region && & MBB == Region -> getHeader ( ) ) { if ( Region -> isLoop ( ) ) { for ( auto Pred : MBB . predecessors ( ) ) assert ( ( Pred -> getNumber ( ) < MBB . getNumber ( ) || Region -> contains ( Pred ) ) && <STR_LIT> <STR_LIT> ) ; } else { for ( auto Pred : MBB . predecessors ( ) ) assert ( Pred -> getNumber ( ) < MBB . getNumber ( ) && <STR_LIT> ) ; } assert ( OnStack . insert ( Region ) && <STR_LIT> ) ; } else { for ( auto Pred : MBB . predecessors ( ) ) assert ( Pred -> getNumber ( ) < MBB . getNumber ( ) && <STR_LIT> ) ;

assert ( OnStack . count ( RI . getRegionFor ( & MBB ) ) && <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( shiftLo >> <NUM_LIT> == <NUM_LIT> ) return Fail ; DecodeGPR32RegisterClass ( Inst , Rd , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rn , Addr , Decoder ) ; DecodeGPR32RegisterClass ( Inst , Rm , Addr , Decoder ) ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( shiftHi == <NUM_LIT> ) return Fail ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

DecodeGPR64RegisterClass ( Inst , Rd , Addr , Decoder ) ;


<s> if ( NumElts <= LargestEltVT . getSizeInBits ( ) ) { assert ( isPowerOf2_32 ( NumElts ) && <STR_LIT> ) ; WideEltVT = <STR_LIT> ( NumElts ) ; WidenVecLen = <NUM_LIT> ; ExtractElementIdx = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; ExtractBitIdx = Idx ; } else { WideEltVT = LargestEltVT ; WidenVecLen = NumElts / WideEltVT . getSizeInBits ( ) ; ExtractElementIdx = DAG . getNode ( <STR_LIT> , DL , XLenVT , Idx , DAG . getConstant ( Log2_64 ( WideEltVT . getSizeInBits ( ) ) , DL , XLenVT ) ) ; ExtractBitIdx = DAG . getNode ( <STR_LIT> , DL , XLenVT , Idx , DAG . getConstant ( WideEltVT . getSizeInBits ( ) - <NUM_LIT> , DL , XLenVT ) ) ; } MVT WideVT = <STR_LIT> ( WideEltVT , WidenVecLen ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; SDValue ExtractElt = DAG . getNode ( <STR_LIT> , DL , XLenVT , Vec , ExtractElementIdx ) ; SDValue ShiftRight = DAG . getNode ( <STR_LIT> , DL , XLenVT , ExtractElt , ExtractBitIdx ) ; return DAG . getNode ( <STR_LIT> , DL , XLenVT , ShiftRight , DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ) ; } } MVT WideVT = <STR_LIT> ( <STR_LIT> , VecVT . getVectorElementCount ( ) ) ; Vec = DAG . getNode ( <STR_LIT> , DL , WideVT , Vec ) ; return DAG . getNode ( <STR_LIT> , DL , EltVT , Vec , Idx ) ; }


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( ! Is64Bit || ! Subtarget . hasAVX512 ( ) ) { for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) {


<s> if ( isa_and_nonnull < StoreInst > ( I ) ) { Value * Ptr = I -> getOperand ( <NUM_LIT> ) ; if ( auto * GEP = dyn_cast < GetElementPtrInst > ( Ptr ) ) { if ( ! all_of ( GEP -> indices ( ) , [ ] ( Value * V ) { return isa < Constant > ( V ) ; } ) ) return TTI :: TCC_Basic * <NUM_LIT> ; } } return TTI :: TCC_Basic ; } if ( auto * VTy = dyn_cast < FixedVectorType > ( Src ) ) { unsigned NumElem = VTy -> getNumElements ( ) ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( NumElem == <NUM_LIT> && VTy -> getScalarSizeInBits ( ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ! isPowerOf2_32 ( NumElem ) ) { APInt DemandedElts = APInt :: getAllOnesValue ( NumElem ) ; int Cost = BaseT :: getMemoryOpCost ( Opcode , VTy -> getScalarType ( ) , Alignment , AddressSpace , CostKind ) ; int SplitCost = getScalarizationOverhead ( VTy , DemandedElts , Opcode == Instruction :: Load , Opcode == Instruction :: Store ) ; return NumElem * Cost + SplitCost ; } } if ( TLI -> getValueType ( DL , Src , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Src , Alignment , AddressSpace , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; assert ( ( Opcode == Instruction :: Load || Opcode == Instruction :: Store ) && <STR_LIT> ) ; int Cost = LT . first * <NUM_LIT> ; if ( LT . second . getStoreSize ( ) == <NUM_LIT> && ST -> isUnalignedMem32Slow ( ) ) Cost *= <NUM_LIT> ;


<s> bool hasV8_5aOps ( ) const { return HasV8_5aOps ;


<s> bool hasMMA ( ) const { return HasMMA ;


<s> case <STR_LIT> : return performANDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performADDCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSHLCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performSUBCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performCIncOffsetToCandAddrCombine ( N , DAG , DCI , Subtarget ) ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>TargetMachine & TM ) : TargetFrameLowering ( StackGrowsUp , Align ( <NUM_LIT> ) , <NUM_LIT> ) , tm ( TM ) {


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getMemBase ( ) ) ) ;


<s> Counters Counts , WaitOn ; Counts . Named . VM = decodeVmcnt ( IV , Imm ) ; Counts . Named . EXP = decodeExpcnt ( IV , Imm ) ; Counts . Named . LGKM = decodeLgkmcnt ( IV , Imm ) ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Counts . Array [ i ] <= LastIssued . Array [ i ] ) WaitOn . Array [ i ] = LastIssued . Array [ i ] - Counts . Array [ i ] ; else WaitOn . Array [ i ] = <NUM_LIT> ; } increaseCounters ( DelayedWaitOn , WaitOn ) ;


<s> cfun_set_fpr_save ( i ) ; if ( i >= FPR8_REGNUM ) cfun_frame_layout . high_fprs ++ ; } clobbered_regs [ <NUM_LIT> ] |= ( ( flag_pic && df_regs_ever_live_p ( PIC_OFFSET_TABLE_REGNUM ) ) || ( flag_split_stack && cfun -> stdarg && ( crtl -> is_leaf || TARGET_TPF_PROFILING || has_hard_reg_initial_val ( Pmode , RETURN_REGNUM ) ) ) ) ; clobbered_regs [ BASE_REGNUM ] |= ( cfun -> machine -> base_reg && REGNO ( cfun -> machine -> base_reg ) == BASE_REGNUM ) ; clobbered_regs [ HARD_FRAME_POINTER_REGNUM ] |= ! ! frame_pointer_needed ; clobbered_regs [ RETURN_REGNUM ] |= ( ! crtl -> is_leaf || TARGET_TPF_PROFILING || cfun -> machine -> split_branches_pending_p || cfun_frame_layout . save_return_addr_p || crtl -> calls_eh_return ) ; clobbered_regs [ STACK_POINTER_REGNUM ] |= ( ! crtl -> is_leaf || TARGET_TPF_PROFILING || cfun_save_high_fprs_p || get_frame_size ( ) > <NUM_LIT> || ( reload_completed && cfun_frame_layout . frame_size > <NUM_LIT> ) || cfun -> calls_alloca ) ; memset ( cfun_frame_layout . gpr_save_slots , SAVE_SLOT_NONE , <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) if ( clobbered_regs [ i ] ) cfun_gpr_save_slot ( i ) = SAVE_SLOT_STACK ; s390_register_info_stdarg_fpr ( ) ;


<s> isLoadFromStackSlot ( const MachineInstr * MI , int & FrameIndex ) const { if ( ( MI -> getOpcode ( ) == <STR_LIT> ) || ( MI -> getOpcode ( ) == <STR_LIT> ) || ( MI -> getOpcode ( ) == <STR_LIT> ) ) {

if ( ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) && ( isZeroImm ( MI -> getOperand ( <NUM_LIT> ) ) ) ) {


__o = __builtin_aarch64_ld3v2si ( ( const __builtin_aarch64_simd_si * ) __a ) ;


<s> if ( side_effects_p ( operands [ <NUM_LIT> ] ) || modified_in_p ( operands [ <NUM_LIT> ] , current_output_insn ) ) flags_operand2 = NULL_RTX ; else flags_operand2 = operands [ <NUM_LIT> ] ; return ; } if ( flags_operand1 != NULL_RTX && modified_in_p ( flags_operand1 , current_output_insn ) ) flags_operand1 = NULL_RTX ; if ( flags_operand2 != NULL_RTX && modified_in_p ( flags_operand2 , current_output_insn ) ) flags_operand2 = NULL_RTX ;


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableDeadRegisterElimination ) addPass ( create<ISA_LIT>DeadRegisterDefinitions ( ) ) ;

if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isCortexA57 ( ) && ! static_cast < const <ISA_LIT>TargetMachine * > ( TM ) -> isPBQPUsed ( ) ) addPass ( create<ISA_LIT>A57FPLoadBalancing ( ) ) ;


<s> OpBegins . push_back ( OpBegins . back ( ) + Size ) ;


<s> static int getIDWithAttrMask ( uint16_t * instructionID , struct InternalInstruction * insn , uint16_t attrMask ) { bool hasModRMExtension ; InstructionContext instructionClass = contextForAttrs ( attrMask ) ; hasModRMExtension = modRMRequired ( insn -> opcodeType , instructionClass , insn -> opcode ) ; if ( hasModRMExtension ) { if ( readModRM ( insn ) ) return - <NUM_LIT> ; * instructionID = decode ( insn -> opcodeType , instructionClass , insn -> opcode , insn -> modRM ) ; } else {

* instructionID = decode ( insn -> opcodeType , instructionClass , insn -> opcode , <NUM_LIT> ) ;


<s> rtx neg_src ; if ( short_mode ) src = gen_lowpart ( wmode , src ) ; neg_src = gen_rtx_NEG ( wmode , src ) ; emit_insn ( gen_rtx_SET ( src , neg_src ) ) ; if ( short_mode ) src = gen_lowpart ( mode , src ) ; } case PLUS : ldop_code = AARCH64_LDOP_PLUS ; break ; case IOR : ldop_code = AARCH64_LDOP_OR ; break ; case XOR : ldop_code = AARCH64_LDOP_XOR ; break ; case AND : { rtx not_src ; if ( short_mode ) src = gen_lowpart ( wmode , src ) ; not_src = gen_rtx_NOT ( wmode , src ) ; emit_insn ( gen_rtx_SET ( src , not_src ) ) ; if ( short_mode ) src = gen_lowpart ( mode , src ) ; } ldop_code = AARCH64_LDOP_BIC ; break ; default : gcc_unreachable ( ) ; } aarch64_emit_atomic_load_op ( ldop_code , mode , out_data , src , mem , model_rtx ) ; if ( ! out_result ) return ; if ( short_mode ) { src = gen_lowpart ( wmode , src ) ; out_data = gen_lowpart ( wmode , out_data ) ; out_result = gen_lowpart ( wmode , out_result ) ; } x = NULL_RTX ; switch ( code ) { case MINUS : case PLUS : x = gen_rtx_PLUS ( wmode , out_data , src ) ; break ; case IOR : x = gen_rtx_IOR ( wmode , out_data , src ) ; break ; case XOR : x = gen_rtx_XOR ( wmode , out_data , src ) ; break ; case AND : aarch64_emit_bic ( wmode , out_result , out_data , src , <NUM_LIT> ) ; return ; default :


<s> ptr -> x_ix86_cmodel = CM_SMALL_PIC ; break ; case CM_MEDIUM : ptr -> x_ix86_cmodel = CM_MEDIUM_PIC ; break ; case CM_LARGE : ptr -> x_ix86_cmodel = CM_LARGE_PIC ; break ; case CM_KERNEL : error ( <STR_LIT> , <STR_LIT> ) ; break ; default :


<s> bool NeedQueuePtr = false ; bool HaveCall = false ; bool IsFunc = ! <STR_LIT> ( F . getCallingConv ( ) ) ; for ( BasicBlock & BB : F ) { for ( Instruction & I : BB ) { CallSite CS ( & I ) ; if ( CS ) { Function * Callee = CS . getCalledFunction ( ) ; if ( ! Callee ) { if ( ! CS . isInlineAsm ( ) ) HaveCall = true ; continue ; } <STR_LIT> IID = Callee -> getIntrinsicID ( ) ; if ( IID == <STR_LIT> ) { HaveCall = true ; copyFeaturesToFunction ( F , * Callee , NeedQueuePtr ) ; Changed = true ; } else { bool NonKernelOnly = false ;

StringRef AttrName = intrinsicToAttrName ( IID , NonKernelOnly , NeedQueuePtr ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) {


<s> auto * Shift = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ; if ( ! Shift ) return false ; uint64_t Amount = Shift -> getZExtValue ( ) ; if ( Amount >= N . getValueSizeInBits ( ) ) return false ; ShiftVal = Amount ;


<s> unsigned getArgumentStackToRestore ( ) const { return ArgumentStackToRestore ;


<s> bool <ISA_LIT>CommonGEP :: isInMainPath ( BasicBlock * B , Loop * L ) { BasicBlock * HB = L -> getHeader ( ) ;

BasicBlock * LB = L -> getLoopLatch ( ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> virtual const <ISA_LIT>Z80RegisterInfo & getRegisterInfo ( ) const {


<s> if ( i == First ) continue ; if ( Elem [ i ] == Elem [ First ] || Elem [ i ] . getOpcode ( ) == <STR_LIT> ) continue ; IsSplat = false ; break ; } if ( IsSplat ) return DAG . getNode ( <STR_LIT> , dl , VecTy , Elem [ First ] ) ; } if ( AllConst ) { uint64_t Val = <NUM_LIT> ; unsigned W = ElemTy . getSizeInBits ( ) ; uint64_t Mask = ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : ( ElemTy == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != Num ; ++ i ) Val = ( Val << W ) | ( Consts [ i ] -> getZExtValue ( ) & Mask ) ; SDValue V0 = DAG . getConstant ( Val , dl , <STR_LIT> ) ; return DAG . getBitcast ( VecTy , V0 ) ; } MVT HalfTy = <STR_LIT> ( ElemTy , Num / <NUM_LIT> ) ; SDValue L = ( ElemTy == <STR_LIT> ) ? Elem [ <NUM_LIT> ] : buildVector32 ( { Elem . data ( ) , Num / <NUM_LIT> } , dl , HalfTy , DAG ) ; SDValue H = ( ElemTy == <STR_LIT> ) ? Elem [ <NUM_LIT> ] : buildVector32 ( { Elem . data ( ) + Num / <NUM_LIT> , Num / <NUM_LIT> } , dl , HalfTy , DAG ) ; unsigned Id = <STR_LIT> ;

SDNode * N = DAG . getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VecTy , { DAG . getTargetConstant ( Id , dl , <STR_LIT> ) , L , DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) , H , DAG . getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) } ) ;


<s> Op -> ISBOpt . Val = Opt ; Op -> StartLoc = S ; Op -> EndLoc = S ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const {


<s> bool <ISA_LIT>AsmParser :: parseDirectiveThumb ( SMLoc L ) { if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) return Error ( L , <STR_LIT> ) ; Parser . Lex ( ) ; if ( ! isThumb ( ) ) SwitchMode ( ) ;

getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( MCAF_Code16 ) ;


<s> case MCContext :: IsMachO : CurrentFormat = MACHO ; break ; case MCContext :: IsELF : CurrentFormat = ELF ; break ; case MCContext :: IsCOFF : CurrentFormat = COFF ; break ; case MCContext :: IsWasm : CurrentFormat = WASM ; break ; case MCContext :: IsGOFF : case MCContext :: IsSPIRV : case MCContext :: IsXCOFF : case MCContext :: IsDXContainer : llvm_unreachable ( <STR_LIT> ) ; break ; } if ( ~ Prefix -> SupportedFormats & CurrentFormat ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } RefKind = Prefix -> VariantKind ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; }


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << FI << <STR_LIT> << MFI . getObjectOffset ( FI ) << <STR_LIT> ) ; FrameReg = <STR_LIT> ;


<s> return <NUM_LIT> ; } if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return <STR_LIT> ( RegNo , Start , End ) ; getParser ( ) . Lex ( ) ; return ParseMemOperand ( RegNo , Start ) ; } case AsmToken :: Dollar : { SMLoc Start = Parser . getTok ( ) . getLoc ( ) , End ; Parser . Lex ( ) ; const MCExpr * Val ; if ( getParser ( ) . ParseExpression ( Val , End ) ) return <NUM_LIT> ; return <STR_LIT> ( Val , Start , End ) ;


<s> return DAG -> getNode ( <STR_LIT> , dl , VT , Cond , TrueVal , FalseVal ) ;


<s> Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { const TargetInstrInfo & TII = * MF . getTarget ( ) . getInstrInfo ( ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( FIOperandNum ) . ChangeToRegister ( BasePtr , false ) ; if ( Offset == <NUM_LIT> ) return ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Offset < <NUM_LIT> ) BuildMI ( MBB , llvm :: next ( II ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( - Offset ) ; else BuildMI ( MBB , llvm :: next ( II ) , dl , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( Offset ) ;


<s> for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) { destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; srcmem = adjust_address ( copy_rtx ( srcmem ) , mode , GET_MODE_SIZE ( mode ) ) ; } emit_move_insn ( destmem , srcmem ) ; } } else { rtx tmpreg [ <NUM_LIT> ] ; gcc_assert ( unroll <= <NUM_LIT> ) ; for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { tmpreg [ i ] = gen_reg_rtx ( mode ) ; if ( i ) srcmem = adjust_address ( copy_rtx ( srcmem ) , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( tmpreg [ i ] , srcmem ) ; } for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( destmem , tmpreg [ i ] ) ; } } } else for ( i = <NUM_LIT> ; i < unroll ; i ++ ) { if ( i ) destmem = adjust_address ( copy_rtx ( destmem ) , mode , GET_MODE_SIZE ( mode ) ) ; emit_move_insn ( destmem , value ) ; } tmp = expand_simple_binop ( iter_mode , PLUS , iter , piece_size , iter , true , OPTAB_LIB_WIDEN ) ; if ( tmp != iter ) emit_move_insn ( iter , tmp ) ;

emit_cmp_and_jump_insns ( iter , size , LT , NULL_RTX , iter_mode , true , top_label ) ;


<s> void <ISA_LIT>DbgInfo :: EmitSymbol ( std :: string Name , short Class , unsigned short Type , unsigned long Value ) { O << <STR_LIT> << <STR_LIT> << Name << <STR_LIT> << Type << <STR_LIT> << Class ; if ( Value > <NUM_LIT> ) O << <STR_LIT> << Value ;


<s> MDT = & getAnalysis < MachineDominatorTree > ( ) ; MPDT = & getAnalysis < MachinePostDominatorTree > ( ) ; TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ;


<s> <STR_LIT> CC = ( <STR_LIT> ) ( int ) Cond [ <NUM_LIT> ] . getImm ( ) ; Cond [ <NUM_LIT> ] . setImm ( <STR_LIT> ( CC ) ) ;


<s> <ISA_LIT>65816TargetStreamer & streamer = getTargetStreamer ( ) ; streamer . EmitSegEndDirective ( ) ;


<s> bool mayNeedAGPRs ( ) const { return MayNeedAGPRs ;


<s> MCSymbol * PICBase = MF -> getPICBaseSymbol ( ) ; OutStreamer . EmitLabel ( RelocSymbol ) ; const MCExpr * OffsExpr = MCBinaryExpr :: CreateSub ( MCSymbolRefExpr :: Create ( OutContext . GetOrCreateSymbol ( Twine ( <STR_LIT> ) ) , OutContext ) , MCSymbolRefExpr :: Create ( PICBase , OutContext ) , OutContext ) ; OutStreamer . EmitValue ( OffsExpr , <NUM_LIT> ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; return ; } else return AsmPrinter :: EmitFunctionEntryLabel ( ) ; } if ( Subtarget . isELFv2ABI ( ) ) return AsmPrinter :: EmitFunctionEntryLabel ( ) ; MCSectionSubPair Current = OutStreamer . getCurrentSection ( ) ; const MCSectionELF * Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ; OutStreamer . EmitValueToAlignment ( <NUM_LIT> ) ; MCSymbol * Symbol1 = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol1 , OutContext ) , <NUM_LIT> ) ; MCSymbol * Symbol2 = OutContext . GetOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( Symbol2 , MCSymbolRefExpr :: VK_<ISA_LIT>_TOCBASE , OutContext ) , <NUM_LIT> ) ; OutStreamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; OutStreamer . SwitchSection ( Current . first , Current . second ) ; MCSymbol * RealFnSym = OutContext . GetOrCreateSymbol ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitLabel ( RealFnSym ) ;


<s> return __builtin_mve_vhaddq_m_uv4si ( __arm_vuninitializedq_u32 ( ) , __a , __b , __p ) ;


<s> BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } bool FallThru = FBB == nullptr ; unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; unsigned Opc = GetCondBranchFromCond ( CC ) ;

BuildMI ( & MBB , DL , get ( Opc ) ) . addMBB ( TBB ) ;


<s> return ( float64x1_t ) { vgetq_lane_f64 ( __a , <NUM_LIT> ) } ;


return ( __m128i ) __builtin_ia32_expandloadhi128_maskz ( ( const __v8hi * ) __B , ( __v8hi ) _mm_setzero_si128 ( ) , ( __mmask8 ) __A ) ;


<s> bool hasMIMG_R128 ( ) const { return <STR_LIT> ( getSTI ( ) ) ;


<s> MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOStore ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = IsN64 ? <STR_LIT> : <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> return __builtin_mve_vcreateq_uv4si ( __a , __b ) ;


<s> return VGPRPressureSets . test ( SetID ) && ! SGPRPressureSets . test ( SetID ) && ! AGPRPressureSets . test ( SetID ) ;


<s> ret = emit_library_call_value ( libcall , NULL_RTX , <NUM_LIT> , dmode , <NUM_LIT> , operands [ <NUM_LIT> ] , smode ) ; equiv = gen_rtx_fmt_e ( code , dmode , operands [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : ret = emit_library_call_value ( libcall , NULL_RTX , <NUM_LIT> , dmode , <NUM_LIT> , operands [ <NUM_LIT> ] , smode , operands [ <NUM_LIT> ] , smode ) ; equiv = gen_rtx_fmt_ee ( code , dmode , operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; break ;


<s> bool <ISA_LIT>RegisterInfo :: trackLivenessAfterRegAlloc ( const MachineFunction & ) const {


<s> SDValue rotate ; if ( ( alignment % <NUM_LIT> ) == <NUM_LIT> ) { ConstantSDNode * CN ; if ( basePtr . getOpcode ( ) == <STR_LIT> && ( CN = dyn_cast < ConstantSDNode > ( basePtr . getOperand ( <NUM_LIT> ) ) ) != <NUM_LIT> ) { int64_t offset = CN -> getSExtValue ( ) ; int64_t rotamt = int64_t ( ( offset & <NUM_LIT> ) - pso ) ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getConstant ( rotamt , <STR_LIT> ) ; basePtr = basePtr . getOperand ( <NUM_LIT> ) ; if ( ( offset & ~ <NUM_LIT> ) > <NUM_LIT> ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( ( offset & ~ <NUM_LIT> ) , PtrVT ) ) ; } } else if ( ( basePtr . getOpcode ( ) == <STR_LIT> ) || ( basePtr . getOpcode ( ) == <STR_LIT> && basePtr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && basePtr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) ) { int64_t rotamt = - pso ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getConstant ( rotamt , <STR_LIT> ) ; } else { int64_t rotamt = - pso ; if ( rotamt < <NUM_LIT> ) rotamt += <NUM_LIT> ; rotate = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( rotamt , PtrVT ) ) ; } } else { if ( basePtr . getOpcode ( ) == <STR_LIT> ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; SDValue Flag ; SDValue Op0 = basePtr . getOperand ( <NUM_LIT> ) ; SDValue Op1 = basePtr . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantSDNode > ( Op1 ) ) { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; the_chain = DAG . getCopyToReg ( the_chain , dl , VReg , basePtr , Flag ) ; basePtr = DAG . getCopyFromReg ( the_chain , dl , VReg , PtrVT ) ; } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Op0 , Op1 ) ; } } else { basePtr = DAG . getNode ( <STR_LIT> , dl , PtrVT , basePtr , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ;


<s> top = get_insns ( ) ; pop_topmost_sequence ( ) ; return reg_set_between_p ( gen_rtx_REG ( Pmode , REG_RA ) , top , NULL ) ;


<s> StringRef getPassName ( ) const override {


<s> unsigned destregnum = Instr -> getOperand ( <NUM_LIT> ) . getReg ( ) ; SmallVector < unsigned , <NUM_LIT> > dest = getScalarRegisters ( destregnum ) ; DebugLoc DL = Instr -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> ; i < numcopies ; i ++ ) copies . push_back ( BuildMI ( F , DL , InstrInfo -> get ( getScalarVersion ( Instr ) ) , dest [ i ] ) . addOperand ( Instr -> getOperand ( <NUM_LIT> + i ) ) ) ;


<s> break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } } MIB = BuildMI ( * I -> getParent ( ) , I , I -> getDebugLoc ( ) , get ( NewOpc ) ) ; if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) { if ( NewOpc == <STR_LIT> || NewOpc == <STR_LIT> ) MIB -> RemoveOperand ( <NUM_LIT> ) ; for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { MIB . add ( I -> getOperand ( J ) ) ; } MIB . addImm ( <NUM_LIT> ) ; } else { for ( unsigned J = <NUM_LIT> , E = I -> getDesc ( ) . getNumOperands ( ) ; J < E ; ++ J ) { if ( BranchWithZeroOperand && ( unsigned ) ZeroOperandPosition == J ) continue ; MIB . add ( I -> getOperand ( J ) ) ; } } MIB . copyImplicitOps ( * I ) ;


<s> vtrnq_u16 ( uint16x8_t a , uint16x8_t b ) {

return ( uint16x8x2_t ) { vtrn1q_u16 ( a , b ) , vtrn2q_u16 ( a , b ) } ;


<s> case NSHST : return <STR_LIT> ; case NSHLD : return HasV8 ? <STR_LIT> : <STR_LIT> ; case RESERVED_4 : return <STR_LIT> ; case OSH : return <STR_LIT> ; case OSHST : return <STR_LIT> ;

case OSHLD : return HasV8 ? <STR_LIT> : <STR_LIT> ;


<s> } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == <NUM_LIT> ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; if ( ST -> isThumb ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; } if ( Opcode == Instruction :: Xor && Imm . isAllOnes ( ) ) return <NUM_LIT> ; if ( Inst && ( ( ST -> hasV6Ops ( ) && ! ST -> isThumb ( ) ) || ST -> isThumb2 ( ) ) && Ty -> getIntegerBitWidth ( ) <= <NUM_LIT> ) { if ( isSSATMinMaxPattern ( Inst , Imm ) || ( isa < ICmpInst > ( Inst ) && Inst -> hasOneUse ( ) && isSSATMinMaxPattern ( cast < Instruction > ( * Inst -> user_begin ( ) ) , Imm ) ) ) return <NUM_LIT> ; } if ( Inst && ST -> hasVFP2Base ( ) && isFPSatMinMaxPattern ( Inst , Imm ) ) return <NUM_LIT> ;

if ( Inst && Opcode == Instruction :: ICmp && Idx == <NUM_LIT> && Imm . isAllOnesValue ( ) ) {


<s> case RX_BUILTIN_MVFACMI : return rx_expand_int_builtin_0_arg ( target , gen_mvfacmi ) ; case RX_BUILTIN_MVTACHI : return rx_expand_void_builtin_1_arg ( op , gen_mvtachi , true ) ; case RX_BUILTIN_MVTACLO : return rx_expand_void_builtin_1_arg ( op , gen_mvtaclo , true ) ; case RX_BUILTIN_RMPA : if ( rx_allow_string_insns ) emit_insn ( gen_rmpa ( ) ) ; else error ( <STR_LIT> <STR_LIT> ) ; return NULL_RTX ; case RX_BUILTIN_MVFC : return rx_expand_builtin_mvfc ( arg , target ) ; case RX_BUILTIN_MVTC : return rx_expand_builtin_mvtc ( exp ) ; case RX_BUILTIN_MVTIPL : return rx_expand_builtin_mvtipl ( op ) ; case RX_BUILTIN_RACW : return rx_expand_void_builtin_1_arg ( op , gen_racw , false ) ; case RX_BUILTIN_ROUND : return rx_expand_builtin_round ( op , target ) ; case RX_BUILTIN_REVW : return rx_expand_int_builtin_1_arg ( op , target , gen_revw , false ) ; case RX_BUILTIN_WAIT : emit_insn ( gen_wait ( ) ) ; return NULL_RTX ; default :


<s> unsigned FullSize = <NUM_LIT> ; uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; Data [ Offset + Idx ] = static_cast < uint8_t > ( ( CurVal >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> i ++ ) { dbgs ( ) << <STR_LIT> ; ( * i ) -> dump ( false ) ; dbgs ( ) << <STR_LIT> ;


<s> Value * <ISA_LIT>TargetLowering :: getSafeStackPointerLocation ( IRBuilder < > & IRB ) const { if ( Subtarget -> isTargetAndroid ( ) ) return UseTlsOffset ( IRB , <NUM_LIT> ) ;

if ( Subtarget -> isTargetFuchsia ( ) ) return UseTlsOffset ( IRB , - <NUM_LIT> ) ;


<s> return __arm_vmullbq_int_s32 ( __a , __b ) ;


<s> dst = replace_equiv_address_nv ( dst , dst_reg ) ; bytes -= rem ; if ( rem > <NUM_LIT> ) { if ( CONST_INT_P ( value_rtx ) ) { const unsigned HOST_WIDE_INT value = UINTVAL ( value_rtx ) & <NUM_LIT> ; emit_move_insn ( adjust_address_nv ( dst , HImode , bytes ) , gen_int_mode ( ( value << <NUM_LIT> ) | value , HImode ) ) ; } else { rtx temp = convert_to_mode ( QImode , value_rtx , <NUM_LIT> ) ; emit_move_insn ( adjust_address_nv ( dst , QImode , bytes ) , temp ) ;

emit_move_insn ( adjust_address_nv ( dst , QImode , bytes + <NUM_LIT> ) , temp ) ;