<s> if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( ! TM . isPositionIndependent ( ) ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ; } if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { auto * CN = cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( isInt < <NUM_LIT> > ( CN -> getSExtValue ( ) ) ) { if ( SPAllowed ) { if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , DL , ValTy ) ; return true ; } } Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , DL , ValTy ) ; return true ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { if ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { SDValue Opnd0 = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( isa < ConstantPoolSDNode > ( Opnd0 ) || isa < GlobalAddressSDNode > ( Opnd0 ) || isa < JumpTableSDNode > ( Opnd0 ) ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Opnd0 ; return true ; } } } Base = Addr ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , ValTy ) ; return true ;


<s> Hi = DAG . getBitcast ( <STR_LIT> , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; } if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && DstVT . isVector ( ) ) return Lower512IntUnary ( Op , DAG ) ; if ( ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) && DstVT . isScalarInteger ( ) ) { assert ( ! Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; MVT SExtVT = SrcVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDLoc DL ( Op ) ; SDValue V = DAG . getSExtOrTrunc ( Src , DL , SExtVT ) ; V = getPMOVMSKB ( DL , V , DAG , Subtarget ) ; return DAG . getZExtOrTrunc ( V , DL , DstVT ) ; } if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { assert ( Subtarget . hasSSE2 ( ) && <STR_LIT> ) ; if ( DstVT != <STR_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; SDLoc dl ( Op ) ; unsigned NumElts ; MVT SVT ; if ( SrcVT . isVector ( ) ) { NumElts = SrcVT . getVectorNumElements ( ) ; SVT = SrcVT . getVectorElementType ( ) ; for ( unsigned i = <NUM_LIT> , e = NumElts ; i != e ; ++ i ) Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , SVT , Src , DAG . getIntPtrConstant ( i , dl ) ) ) ; } else { assert ( SrcVT == <STR_LIT> && ! Subtarget . is64Bit ( ) && <STR_LIT> ) ; Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ) ; Elts . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ) ; NumElts = <NUM_LIT> ; SVT = <STR_LIT> ; } Elts . append ( NumElts , DAG . getUNDEF ( SVT ) ) ; EVT NewVT = EVT :: getVectorVT ( * DAG . getContext ( ) , SVT , NumElts * <NUM_LIT> ) ; SDValue BV = DAG . getBuildVector ( NewVT , dl , Elts ) ; SDValue ToV2F64 = DAG . getBitcast ( <STR_LIT> , BV ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ToV2F64 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } assert ( Subtarget . is64Bit ( ) && ! Subtarget . hasSSE2 ( ) && Subtarget . hasMMX ( ) && <STR_LIT> ) ; assert ( ( DstVT == <STR_LIT> || ( DstVT . isVector ( ) && DstVT . getSizeInBits ( ) == <NUM_LIT> ) ) && <STR_LIT> ) ;

if ( SrcVT == <STR_LIT> && DstVT . isVector ( ) ) return Op ;


<s> start &= <NUM_LIT> ; if ( start >= prec || len == <NUM_LIT> ) res = <NUM_LIT> ; else if ( ! tree_fits_uhwi_p ( args [ <NUM_LIT> ] ) ) break ; else res = tree_to_uhwi ( args [ <NUM_LIT> ] ) >> start ; if ( len > prec ) len = prec ; if ( len < HOST_BITS_PER_WIDE_INT ) res &= ( HOST_WIDE_INT_1U << len ) - <NUM_LIT> ; return build_int_cstu ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) , res ) ; } break ; case IX86_BUILTIN_BZHI32 : case IX86_BUILTIN_BZHI64 : gcc_assert ( n_args == <NUM_LIT> ) ; if ( tree_fits_uhwi_p ( args [ <NUM_LIT> ] ) ) { unsigned int idx = tree_to_uhwi ( args [ <NUM_LIT> ] ) & <NUM_LIT> ; if ( idx >= TYPE_PRECISION ( TREE_TYPE ( args [ <NUM_LIT> ] ) ) ) return args [ <NUM_LIT> ] ; if ( ! tree_fits_uhwi_p ( args [ <NUM_LIT> ] ) ) break ; unsigned HOST_WIDE_INT res = tree_to_uhwi ( args [ <NUM_LIT> ] ) ; res &= ~ ( HOST_WIDE_INT_M1U << idx ) ; return build_int_cstu ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) , res ) ; } break ; case IX86_BUILTIN_PDEP32 : case IX86_BUILTIN_PDEP64 : gcc_assert ( n_args == <NUM_LIT> ) ; if ( tree_fits_uhwi_p ( args [ <NUM_LIT> ] ) && tree_fits_uhwi_p ( args [ <NUM_LIT> ] ) ) { unsigned HOST_WIDE_INT src = tree_to_uhwi ( args [ <NUM_LIT> ] ) ; unsigned HOST_WIDE_INT mask = tree_to_uhwi ( args [ <NUM_LIT> ] ) ; unsigned HOST_WIDE_INT res = <NUM_LIT> ; unsigned HOST_WIDE_INT m , k = <NUM_LIT> ; for ( m = <NUM_LIT> ; m ; m <<= <NUM_LIT> ) if ( ( mask & m ) != <NUM_LIT> ) { if ( ( src & k ) != <NUM_LIT> ) res |= m ; k <<= <NUM_LIT> ; } return build_int_cstu ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) , res ) ; } break ; case IX86_BUILTIN_PEXT32 : case IX86_BUILTIN_PEXT64 : gcc_assert ( n_args == <NUM_LIT> ) ; if ( tree_fits_uhwi_p ( args [ <NUM_LIT> ] ) && tree_fits_uhwi_p ( args [ <NUM_LIT> ] ) ) { unsigned HOST_WIDE_INT src = tree_to_uhwi ( args [ <NUM_LIT> ] ) ; unsigned HOST_WIDE_INT mask = tree_to_uhwi ( args [ <NUM_LIT> ] ) ; unsigned HOST_WIDE_INT res = <NUM_LIT> ; unsigned HOST_WIDE_INT m , k = <NUM_LIT> ; for ( m = <NUM_LIT> ; m ; m <<= <NUM_LIT> ) if ( ( mask & m ) != <NUM_LIT> ) { if ( ( src & m ) != <NUM_LIT> ) res |= k ; k <<= <NUM_LIT> ; } return build_int_cstu ( TREE_TYPE ( TREE_TYPE ( fndecl ) ) , res ) ;


<s> for ( regno = FIRST_PSEUDO_REGISTER - <NUM_LIT> ; regno -- > <NUM_LIT> ; ) if ( ! SSE_REGNO_P ( regno ) && ix86_save_reg ( regno , true ) ) { insn = emit_insn ( gen_push ( gen_rtx_REG ( word_mode , regno ) ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; }


<s> unsigned <ISA_LIT>BitcodeWriter :: getEncodedUnaryOpcode ( unsigned Opcode ) { switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case Instruction :: FNeg : return bitc :: UNOP_FNEG ; }


<s> if ( const auto * FuncTy = dyn_cast < FunctionType > ( Global -> getValueType ( ) ) ) { const MachineFunction & MF = * MO . getParent ( ) -> getParent ( ) -> getParent ( ) ; const TargetMachine & TM = MF . getTarget ( ) ; const Function & CurrentFunc = MF . getFunction ( ) ; SmallVector < <STR_LIT> , <NUM_LIT> > Returns ; SmallVector < <STR_LIT> , <NUM_LIT> > Params ; <STR_LIT> iPTR = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAddr64 ( ) ? <STR_LIT> :: I64 : <STR_LIT> :: I32 ; SmallVector < MVT , <NUM_LIT> > ResultMVTs ; ComputeLegalValueVTs ( CurrentFunc , TM , FuncTy -> getReturnType ( ) , ResultMVTs ) ; if ( ResultMVTs . size ( ) <= <NUM_LIT> ) for ( MVT ResultMVT : ResultMVTs ) Returns . push_back ( <STR_LIT> ( ResultMVT ) ) ; else Params . push_back ( iPTR ) ; for ( Type * Ty : FuncTy -> params ( ) ) { SmallVector < MVT , <NUM_LIT> > ParamMVTs ; ComputeLegalValueVTs ( CurrentFunc , TM , Ty , ParamMVTs ) ; for ( MVT ParamMVT : ParamMVTs ) Params . push_back ( <STR_LIT> ( ParamMVT ) ) ; } if ( FuncTy -> isVarArg ( ) ) Params . push_back ( iPTR ) ; WasmSym -> setReturns ( std :: move ( Returns ) ) ;

WasmSym -> setParams ( std :: move ( Params ) ) ;


<s> if ( Requested && Requested > getMaxNumVGPRs ( WavesPerEU . first ) ) Requested = <NUM_LIT> ; if ( WavesPerEU . second && Requested && Requested < getMinNumVGPRs ( WavesPerEU . second ) ) Requested = <NUM_LIT> ;

if ( Requested ) MaxNumVGPRs = Requested ;


<s> static DecodeStatus DecodeCCRRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) {

Inst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ;


<s> rtx insn ; if ( val == NULL_RTX || INTVAL ( val ) == <NUM_LIT> ) { gcc_assert ( dest != src ) ; insn = emit_move_insn ( dest , src ) ; } else if ( ok_for_max_constant ( INTVAL ( val ) ) ) insn = emit_insn ( gen_addsi3 ( dest , src , val ) ) ; else { val = gen_rtx_CONST ( SImode , gen_rtx_UNSPEC ( SImode , gen_rtvec ( <NUM_LIT> , val ) , UNSPEC_CONST ) ) ;


<s> void recordRelocation ( MachObjectWriter * Writer , MCAssembler & Asm , const MCAsmLayout & Layout , const MCFragment * Fragment , const MCFixup & Fixup , MCValue Target , uint64_t & FixedValue ) override { if ( Writer -> is64Bit ( ) ) { report_fatal_error ( <STR_LIT> ) ; } else Record<ISA_LIT>Relocation ( Writer , Asm , Layout , Fragment , Fixup , Target , FixedValue ) ;


<s> PrintLaneMaskOpt ( LaneBitmask M ) : Mask ( M ) {


<s> case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerEH_RETURN ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBALADDRESS ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerGLOBAL_OFFSET_TABLE ( Op , DAG ) ; case <STR_LIT> : return LowerVACOPY ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : return LowerPREFETCH ( Op , DAG ) ; case <STR_LIT> : return LowerREADCYCLECOUNTER ( Op , DAG ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( QFRegs [ getReg ( ) ] ) ) ;


<s> if ( Flags . isSExt ( ) ) ArgVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgVal , DAG . getValueType ( ObjectVT ) ) ;

else if ( Flags . isZExt ( ) ) ArgVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgVal , DAG . getValueType ( ObjectVT ) ) ;


<s> TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>RegisterInfo * LRI = static_cast < const <ISA_LIT>RegisterInfo * > ( STI . getRegisterInfo ( ) ) ; int Offset = - <NUM_LIT> ; MFI -> CreateFixedObject ( <NUM_LIT> , Offset , true ) ; Offset -= <NUM_LIT> ; MFI -> CreateFixedObject ( <NUM_LIT> , Offset , true ) ; Offset -= <NUM_LIT> ; if ( LRI -> hasBasePointer ( MF ) ) { MFI -> CreateFixedObject ( <NUM_LIT> , Offset , true ) ;

SavedRegs . reset ( LRI -> getBaseRegister ( ) ) ;


<s> return ( __m256d ) __builtin_ia32_getmantpd256_mask ( ( __v4df ) __A , ( __C << <NUM_LIT> ) | __B , ( __v4df ) _mm256_setzero_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> AI . PrivateSegmentBuffer = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . DispatchPtr = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . QueuePtr = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . ImplicitArgPtr = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . DispatchID = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . WorkGroupIDX = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . WorkGroupIDY = ArgDescriptor :: createRegister ( <STR_LIT> ) ; AI . WorkGroupIDZ = ArgDescriptor :: createRegister ( <STR_LIT> ) ; const unsigned Mask = <NUM_LIT> ;

AI . WorkItemIDX = ArgDescriptor :: createRegister ( <STR_LIT> , Mask ) ;


<s> ConstantSDNode * Offset = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! Offset ) break ; SDValue BitsFrom = N -> getOperand ( <NUM_LIT> ) ; uint32_t OffsetVal = Offset -> getZExtValue ( ) & <NUM_LIT> ; bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal ) ; } APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) {

SDValue ShiftVal = DAG . getConstant ( OffsetVal , <STR_LIT> ) ;


<s> case Instruction :: ICmp : return selectICmp ( I ) ; case Instruction :: FCmp : return selectFCmp ( I ) ; case Instruction :: BitCast : return selectBitCast ( I ) ; case Instruction :: Load : return selectLoad ( I ) ; case Instruction :: Store : return selectStore ( I ) ; case Instruction :: Br : return selectBr ( I ) ; case Instruction :: Ret : return selectRet ( I ) ; case Instruction :: Unreachable : return selectUnreachable ( I ) ;


<s> assert ( isa < VectorType > ( VecTy ) && <STR_LIT> ) ; bool EltIs64Bits = DL . getTypeAllocSizeInBits ( VecTy -> getScalarType ( ) ) == <NUM_LIT> ; if ( Factor <= TLI -> getMaxSupportedInterleaveFactor ( ) && ! EltIs64Bits ) { unsigned NumElts = VecTy -> getVectorNumElements ( ) ;

Type * SubVecTy = VectorType :: get ( VecTy -> getScalarType ( ) , NumElts / Factor ) ;


<s> parseFPImm ( SmallVectorImpl < MCParsedAsmOperand * > & Operands ) { SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Hash ) ) return MatchOperand_NoMatch ; Parser . Lex ( ) ; bool isNegative = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Minus ) ) { isNegative = true ; Parser . Lex ( ) ; } const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Real ) ) { APFloat RealVal ( APFloat :: IEEEdouble , Tok . getString ( ) ) ; uint64_t IntVal = RealVal . bitcastToAPInt ( ) . getZExtValue ( ) ; IntVal ^= ( uint64_t ) isNegative << <NUM_LIT> ; int Val = <STR_LIT> ( APInt ( <NUM_LIT> , IntVal ) ) ; Parser . Lex ( ) ; if ( Val == - <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateFPImm ( Val , S , getContext ( ) ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: Integer ) ) { int64_t Val = Tok . getIntVal ( ) ; Parser . Lex ( ) ; if ( Val > <NUM_LIT> || Val < <NUM_LIT> ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ;


<s> break ; } if ( I -> readsRegister ( <STR_LIT> , TRI ) ) SingleUseCondition = false ; } if ( ! ConditionDef ) return true ; if ( SingleUseCondition ) { for ( auto * Succ : MBB . successors ( ) ) if ( Succ -> isLiveIn ( <STR_LIT> ) ) SingleUseCondition = false ; } MBP . ConditionDef = ConditionDef ; MBP . SingleUseCondition = SingleUseCondition ; const unsigned TestOpcode = Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ConditionDef -> getOpcode ( ) == TestOpcode && ConditionDef -> getNumOperands ( ) == <NUM_LIT> && ConditionDef -> getOperand ( <NUM_LIT> ) . isIdenticalTo ( ConditionDef -> getOperand ( <NUM_LIT> ) ) && ( Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) ) {

MBP . LHS = ConditionDef -> getOperand ( <NUM_LIT> ) ;


<s> if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , DL ) ;

return DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , LocMemOffset ) ) ;


<s> if ( CurInstKind == IDAlu && ! Available [ IDFetch ] . empty ( ) ) { float ALUFetchRationEstimate = ( AluInstCount + AvailablesAluCount ( ) + Pending [ IDAlu ] . size ( ) ) / ( FetchInstCount + Available [ IDFetch ] . size ( ) ) ; unsigned NeededWF = <NUM_LIT> / ALUFetchRationEstimate ; DEBUG ( dbgs ( ) << NeededWF << <STR_LIT> ) ; unsigned NearRegisterRequirement = <NUM_LIT> * Available [ IDFetch ] . size ( ) ; if ( NeededWF > getWFCountLimitedByGPR ( NearRegisterRequirement ) ) AllowSwitchFromAlu = true ; } if ( ! SU && ( ( AllowSwitchToAlu && CurInstKind != IDAlu ) || ( ! AllowSwitchFromAlu && CurInstKind == IDAlu ) ) ) { SU = pickAlu ( ) ; if ( ! SU && ! PhysicalRegCopy . empty ( ) ) { SU = PhysicalRegCopy . front ( ) ; PhysicalRegCopy . erase ( PhysicalRegCopy . begin ( ) ) ; } if ( SU ) { if ( CurEmitted >= InstKindLimit [ IDAlu ] ) CurEmitted = <NUM_LIT> ; NextInstKind = IDAlu ; } } if ( ! SU ) { SU = pickOther ( IDFetch ) ; if ( SU ) NextInstKind = IDFetch ; } if ( ! SU ) { SU = pickOther ( IDOther ) ; if ( SU ) NextInstKind = IDOther ; } DEBUG ( if ( SU ) { dbgs ( ) << <STR_LIT> ; SU -> dump ( DAG ) ; } else { dbgs ( ) << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i < DAG -> SUnits . size ( ) ; i ++ ) {


<s> const <ISA_LIT>RegisterInfo & ARI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ;


<s> case MODE_FLOAT : case MODE_COMPLEX_FLOAT : case MODE_VECTOR_FLOAT : if ( TARGET_HARD_FLOAT ) return mips_set_reg_reg_piece_cost ( mode , UNITS_PER_HWFPVALUE ) ; default : return mips_set_reg_reg_piece_cost ( mode , UNITS_PER_WORD ) ; }


<s> virtual ~ <ISA_LIT>Operand ( ) { switch ( Kind ) { case k_Immediate : break ;


<s> if ( ! MEM_SIZE_KNOWN_P ( * str_mem ) ) return false ; machine_mode mode = GET_MODE ( * str_mem ) ; HOST_WIDE_INT size = MEM_SIZE ( * str_mem ) ; if ( INTEGRAL_MODE_P ( mode ) ) return ( size == <NUM_LIT> || size == <NUM_LIT> ) ;

else if ( FLOAT_MODE_P ( mode ) ) return ( size == <NUM_LIT> ) ;


<s> rtx last , next , fold , x ; bool ok ; last = in ; fold = gen_reg_rtx ( vmode ) ; switch ( vmode ) { case E_V2SFmode : perm2 [ <NUM_LIT> ] = <NUM_LIT> ; perm2 [ <NUM_LIT> ] = <NUM_LIT> ; ok = mips_expand_vselect_vconcat ( fold , last , last , perm2 , <NUM_LIT> ) ; gcc_assert ( ok ) ; break ; case E_V2SImode : emit_insn ( gen_loongson_punpckhwd ( fold , last , last ) ) ; break ; case E_V4HImode : emit_insn ( gen_loongson_punpckhwd_hi ( fold , last , last ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( gen_vec_shr_v4hi ( fold , last , x ) ) ; break ; case E_V8QImode : emit_insn ( gen_loongson_punpckhwd_qi ( fold , last , last ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( gen_vec_shr_v8qi ( fold , last , x ) ) ; next = gen_reg_rtx ( vmode ) ; emit_insn ( gen ( next , last , fold ) ) ; last = next ; fold = gen_reg_rtx ( vmode ) ; x = force_reg ( SImode , GEN_INT ( <NUM_LIT> ) ) ; emit_insn ( gen_vec_shr_v8qi ( fold , last , x ) ) ; break ;


<s> const std :: vector < <ISA_LIT>Section * > & getBSSSections ( ) const {


<s> <ISA_LIT>AdjustOpt ( ) : ModulePass ( ID ) {


<s> bool generateCompositeMacros ( ) const override { return true ;


<s> PM . add ( create<ISA_LIT>FPMoverPass ( * this ) ) ; PM . add ( create<ISA_LIT>DelaySlotFillerPass ( * this ) ) ;


<s> const MCSymbolRefExpr * PersonalityRef = MCSymbolRefExpr :: Create ( PersonalitySym , MCSymbolRefExpr :: VK_<ISA_LIT>_NONE , getContext ( ) ) ; AddValueSymbols ( PersonalityRef ) ; MCDataFragment * DF = getOrCreateDataFragment ( ) ; DF -> getFixups ( ) . push_back ( MCFixup :: Create ( DF -> getContents ( ) . size ( ) , PersonalityRef , MCFixup :: getKindForSize ( <NUM_LIT> , false ) ) ) ;


<s> if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ;


<s> if ( REG_P ( arg ) && GET_MODE ( arg ) != word_mode ) arg = gen_rtx_REG ( word_mode , REGNO ( arg ) ) ; return gen_rtx_SET ( VOIDmode , gen_rtx_MEM ( word_mode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) , arg ) ;


<s> bool AMDGPUInstrInfo :: SubsumesPredicate ( const SmallVectorImpl < MachineOperand > & Pred1 , const SmallVectorImpl < MachineOperand > & Pred2 ) const {


<s> unsigned <ISA_LIT>HazardRecognizer :: getNumDecoderSlots ( SUnit * SU ) const { const MCSchedClassDesc * SC = getSchedClass ( SU ) ; if ( ! SC -> isValid ( ) ) return <NUM_LIT> ;

assert ( ( SC -> NumMicroOps != <NUM_LIT> || ( SC -> BeginGroup && ! SC -> EndGroup ) ) && <STR_LIT> ) ;


<s> switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_ADDRSPACE_CAST : return legalizeAddrSpaceCast ( MI , MRI , B ) ; case TargetOpcode :: G_FRINT : return legalizeFrint ( MI , MRI , B ) ; case TargetOpcode :: G_FCEIL : return legalizeFceil ( MI , MRI , B ) ; case TargetOpcode :: G_INTRIN<ISA_LIT>C_TRUNC : return legalizeIntrinsicTrunc ( MI , MRI , B ) ; case TargetOpcode :: G_<ISA_LIT>TOFP : return legalizeITOFP ( MI , MRI , B , true ) ; case TargetOpcode :: G_UITOFP : return legalizeITOFP ( MI , MRI , B , false ) ; case TargetOpcode :: G_FMINNUM : case TargetOpcode :: G_FMAXNUM : case TargetOpcode :: G_FMINNUM_IEEE :


<s> offset = rs6000_machopic_legitimize_pic_address ( XEXP ( XEXP ( orig , <NUM_LIT> ) , <NUM_LIT> ) , Pmode , reg ) ; if ( GET_CODE ( offset ) == CONST_INT ) { if ( SMALL_INT ( offset ) ) return plus_constant ( Pmode , base , INTVAL ( offset ) ) ; else if ( ! reload_in_progress && ! reload_completed ) offset = force_reg ( Pmode , offset ) ; else { rtx mem = force_const_mem ( Pmode , orig ) ;

return machopic_legitimize_pic_address ( mem , Pmode , reg ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) { DebugLoc DL = Op . getDebugLoc ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue Result = DAG . getBlockAddress ( BA , getPointerTy ( ) , true ) ; return DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , Result ) ;


<s> return strncmp ( DLL_IMPORT_PREFIX , symbol , strlen ( DLL_IMPORT_PREFIX ) ) == <NUM_LIT> ;


<s> if ( ExtIdxVal != <NUM_LIT> ) { int VecNumElts = OpVT . getVectorNumElements ( ) ; int SubVecNumElts = SubVecVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ( VecNumElts ) ; for ( int i = <NUM_LIT> ; i != VecNumElts ; ++ i ) Mask [ i ] = i ; for ( int i = <NUM_LIT> ; i != SubVecNumElts ; ++ i ) Mask [ i + IdxVal ] = i + ExtIdxVal + VecNumElts ; return DAG . getVectorShuffle ( OpVT , dl , Vec , SubVec . getOperand ( <NUM_LIT> ) , Mask ) ; } } if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . getSizeInBits ( ) == SubVecVT . getSizeInBits ( ) * <NUM_LIT> ) { auto * Idx2 = dyn_cast < ConstantSDNode > ( Vec . getOperand ( <NUM_LIT> ) ) ; if ( Idx2 && Idx2 -> getZExtValue ( ) == <NUM_LIT> ) { SDValue SubVec2 = Vec . getOperand ( <NUM_LIT> ) ; if ( auto * FirstLd = dyn_cast < LoadSDNode > ( peekThroughBitcasts ( SubVec2 ) ) ) {


<s> case <STR_LIT> : { int OperandSize = Mask . size ( ) / V . getNumOperands ( ) ; V = V . getOperand ( BroadcastIdx / OperandSize ) ; BroadcastIdx %= OperandSize ; continue ; } case <STR_LIT> : { SDValue VOuter = V . getOperand ( <NUM_LIT> ) , VInner = V . getOperand ( <NUM_LIT> ) ; auto ConstantIdx = dyn_cast < ConstantSDNode > ( V . getOperand ( <NUM_LIT> ) ) ; if ( ! ConstantIdx ) break ; int BeginIdx = ( int ) ConstantIdx -> getZExtValue ( ) ; int EndIdx = BeginIdx + ( int ) VInner . getValueType ( ) . getVectorNumElements ( ) ; if ( BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx ) { BroadcastIdx -= BeginIdx ; V = VInner ; } else { V = VOuter ; }


<s> case <NUM_LIT> : return Signed ? <NUM_LIT> : <NUM_LIT> ; case <NUM_LIT> : return Signed ? <NUM_LIT> : <NUM_LIT> ; case <NUM_LIT> :


<s> static DecodeStatus DecodeBranchTarget10MM ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) {

int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) << <NUM_LIT> ;


<s> while ( Current != Pool . end ( ) ) { delete * Current ; ++ Current ; }


<s> Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CodePointerSize = <NUM_LIT> ;


<s> public : <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler & mang , AsmPrinter & printer ) : Ctx ( ctx ) , Mang ( mang ) , Printer ( printer ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetBlockAddressSymbol ( const MachineOperand & MO ) const ;


<s> if ( SyntaxVariant == <NUM_LIT> ) return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ; return <NUM_LIT> ;


<s> while ( CallStack . size ( ) ) { auto StackElem = CallStack . top ( ) ; if ( StackElem . second . Kind == <ISA_LIT>PreserveFieldInfoAI ) return true ; CallStack . pop ( ) ; } return false ;


<s> return __builtin_ia32_ptestz256 ( ( __v4di ) __M , ( __v4di ) __V ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> unsigned DestReg = GA . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! GB . readsRegister ( DestReg ) ) return - <NUM_LIT> ; if ( DestReg == <STR_LIT> ) return <STR_LIT> ; if ( DestReg == <STR_LIT> ) return <STR_LIT> ; return - <NUM_LIT> ;


<s> explicit <ISA_LIT>AdvSIMDScalar ( ) : MachineFunctionPass ( ID ) {


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> rtx dest = XEXP ( SET_SRC ( single_set ( branch2 ) ) , <NUM_LIT> ) ; rtx_insn * insn ; int distance ; for ( distance = <NUM_LIT> , insn = NEXT_INSN ( branch1 ) ; insn && distance < <NUM_LIT> ; insn = PREV_INSN ( insn ) ) { if ( insn == dest ) return true ; else distance += get_attr_length ( insn ) ; } for ( distance = <NUM_LIT> , insn = NEXT_INSN ( branch1 ) ; insn && distance < <NUM_LIT> ; insn = NEXT_INSN ( insn ) ) { if ( insn == dest ) return true ; else distance += get_attr_length ( insn ) ; } } return false ;


<s> ConstantSDNode * CAddr ; if ( Addr . getOpcode ( ) == <STR_LIT> ) { CAddr = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ; if ( ! CAddr || ! <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( CAddr -> getZExtValue ( ) ) ) return false ; if ( ! IsCopyFromSGPR ( * TRI , Addr . getOperand ( <NUM_LIT> ) ) ) return false ; SOffset = Addr . getOperand ( <NUM_LIT> ) ; } else if ( ( CAddr = dyn_cast < ConstantSDNode > ( Addr ) ) && <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( CAddr -> getZExtValue ( ) ) ) { SOffset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; } else { return false ; }

SRsrc = CurDAG -> getRegister ( Info -> getScratchRSrcReg ( ) , <STR_LIT> ) ;


<s> int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset > <NUM_LIT> || Offset < - <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : case <STR_LIT> : { int64_t Offset = int64_t ( Value ) - <NUM_LIT> ; if ( Offset & <NUM_LIT> ) return <STR_LIT> ; else if ( Offset > <NUM_LIT> || Offset < <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : { int64_t Offset = ( Value & ~ <NUM_LIT> ) ; if ( Offset == <NUM_LIT> ) return <STR_LIT> ; break ; } case <STR_LIT> : return checkPCRelOffset ( Value , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , + <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , + <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , + <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , <NUM_LIT> , + <NUM_LIT> ) ; case <STR_LIT> : return checkPCRelOffset ( Value , - <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : { if ( Value != <NUM_LIT> && Value != <NUM_LIT> ) return <STR_LIT> ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; }


<s> if ( Subtarget . useHVXOps ( ) && Subtarget . isHVXVectorType ( VecTy ) ) return LowerHvxExtractElement ( Op , DAG ) ; MVT ElemTy = ty ( Vec ) . getVectorElementType ( ) ; return extractVector ( Vec , Op . getOperand ( <NUM_LIT> ) , SDLoc ( Op ) , ElemTy , ty ( Op ) , DAG ) ;


<s> if ( ! config ( ) . isCodeStatic ( ) && m_pDynamic == NULL ) m_pDynamic = new <ISA_LIT>ELFDynamic ( * this , config ( ) ) ; if ( LinkerConfig :: Object != config ( ) . codeGenType ( ) ) { if ( config ( ) . options ( ) . hasNow ( ) ) { if ( LinkerConfig :: DynObj == config ( ) . codeGenType ( ) || m_pGOT -> hasGOT1 ( ) || m_pGOTSymbol != NULL ) { m_pGOT -> finalizeSectionSize ( ) ; defineGOTSymbol ( pBuilder ) ; } } else { if ( LinkerConfig :: DynObj == config ( ) . codeGenType ( ) || m_pGOTPLT -> hasGOT1 ( ) || m_pGOTSymbol != NULL ) { m_pGOTPLT -> finalizeSectionSize ( ) ; defineGOTSymbol ( pBuilder ) ; } if ( m_pGOT -> hasGOT1 ( ) ) m_pGOT -> finalizeSectionSize ( ) ; } if ( m_pPLT -> hasPLT1 ( ) ) m_pPLT -> finalizeSectionSize ( ) ; ELFFileFormat * file_format = getOutputFormat ( ) ; if ( ! m_pRelaDyn -> empty ( ) ) { assert ( ! config ( ) . isCodeStatic ( ) && <STR_LIT> ) ; file_format -> getRelaDyn ( ) . setSize ( m_pRelaDyn -> numOfRelocs ( ) * getRelaEntrySize ( ) ) ;


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedScatter ( Type * DataType , Align Alignment ) {

if ( ! ST -> hasAVX512 ( ) ) return false ;


<s> return ( __m128i ) __builtin_ia32_punpcklqdq128 ( ( __v2di ) __A , ( __v2di ) __B ) ;


<s> -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ;


<s> plus1 = XEXP ( address , <NUM_LIT> ) ; if ( REG_P ( plus0 ) && CONST_INT_P ( plus1 ) ) { if ( satisfies_constraint_Iu03 ( plus1 ) ) return ( COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ) ; else return COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; } if ( ARITHMETIC_P ( plus0 ) || ARITHMETIC_P ( plus1 ) ) return ( COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ) ; return COSTS_N_INSNS ( <NUM_LIT> ) ;


<s> SDValue NewCall = DAG . getCall ( TheCall -> getCallingConv ( ) , dl , TheCall -> isVarArg ( ) , TheCall -> isTailCall ( ) , TheCall -> isInreg ( ) , VTs , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; return NewCall ; } SDValue ZeroOperand = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue SeqStart = DAG . getCALLSEQ_START ( Chain , ZeroOperand ) ; Chain = getChain ( SeqStart ) ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { GlobalValue * GV = G -> getGlobal ( ) ; Callee = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ; } if ( ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , <STR_LIT> ) ; } SDValue OperFlag = getOutFlag ( Chain ) ; std :: string Name ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Name = G -> getGlobal ( ) -> getName ( ) ; if ( ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Name = ES -> getSymbol ( ) ; char * argFrame = new char [ strlen ( Name . c_str ( ) ) + <NUM_LIT> ] ; sprintf ( argFrame , <STR_LIT> , Name . c_str ( ) ) ; SDValue ArgLabel = DAG . getTargetExternalSymbol ( argFrame , <STR_LIT> ) ; char * retName = new char [ strlen ( Name . c_str ( ) ) + <NUM_LIT> ] ; sprintf ( retName , <STR_LIT> , Name . c_str ( ) ) ; SDValue RetLabel = DAG . getTargetExternalSymbol ( retName , <STR_LIT> ) ; SDValue CallArgs = LowerCallArguments ( Op , Chain , ArgLabel , OperFlag , DAG ) ; Chain = getChain ( CallArgs ) ; OperFlag = getOutFlag ( CallArgs ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;

SDValue PICCall = DAG . getNode ( <STR_LIT> , dl , Tys , Chain , Callee , OperFlag ) ;


<s> if ( MI1 -> getOpcode ( ) != Opcode ) return false ; if ( MI0 -> getNumOperands ( ) != MI1 -> getNumOperands ( ) ) return false ; const MachineOperand & MO0 = MI0 -> getOperand ( <NUM_LIT> ) ; const MachineOperand & MO1 = MI1 -> getOperand ( <NUM_LIT> ) ; if ( MO0 . getOffset ( ) != MO1 . getOffset ( ) ) return false ; const MachineFunction * MF = MI0 -> getParent ( ) -> getParent ( ) ; const MachineConstantPool * MCP = MF -> getConstantPool ( ) ; int CPI0 = MO0 . getIndex ( ) ;


<s> return <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) || <STR_LIT> . contains ( Reg ) ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) , STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( STI . getRegisterInfo ( ) ) , SlotSize ( <NUM_LIT> ) {


<s> if ( Op -> getOpcode ( ) != <STR_LIT> ) return false ; if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { uint64_t RHSC = RHS -> getZExtValue ( ) ; if ( ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) ) return false ; Base = Op -> getOperand ( <NUM_LIT> ) ; Offset = DAG . getConstant ( RHSC , VT ) ; AM = <STR_LIT> ; return true ; } return false ;


<s> } } else if ( SwapVector [ EntryIdx ] . IsStore && SwapVector [ EntryIdx ] . IsSwap ) { MachineInstr * MI = SwapVector [ EntryIdx ] . VSEMI ; unsigned UseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * DefMI = MRI -> getVRegDef ( UseReg ) ; int DefIdx = SwapMap [ DefMI ] ; if ( ! SwapVector [ DefIdx ] . IsSwap || SwapVector [ DefIdx ] . IsLoad || SwapVector [ DefIdx ] . IsStore ) { SwapVector [ Repr ] . WebRejected = <NUM_LIT> ; DEBUG ( dbgs ( ) << format ( <STR_LIT> , Repr ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << DefIdx << <STR_LIT> ) ; DEBUG ( DefMI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> << EntryIdx << <STR_LIT> ) ; DEBUG ( MI -> dump ( ) ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; } } } DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> DebugLoc DL ; unsigned V0 , V1 , GlobalBaseReg = <ISA_LIT>FI -> getGlobalBaseReg ( ) ; const TargetRegisterClass * RC ; const <ISA_LIT>ABIInfo & ABI = static_cast < const <ISA_LIT>TargetMachine & > ( TM ) . getABI ( ) ; RC = ( ABI . IsN64 ( ) ) ? & <STR_LIT> : & <STR_LIT> ; V0 = RegInfo . createVirtualRegister ( RC ) ; V1 = RegInfo . createVirtualRegister ( RC ) ; if ( ABI . IsN64 ( ) ) { MF . getRegInfo ( ) . addLiveIn ( <STR_LIT> ) ; MBB . addLiveIn ( <STR_LIT> ) ; const GlobalValue * FName = MF . getFunction ( ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V0 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , V1 ) . addReg ( V0 ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( V1 ) . addGlobalAddress ( FName , <NUM_LIT> , <STR_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( CoprocOption . Val ) ) ;


<s> static bool arc_can_use_doloop_p ( const widest_int & iterations , const widest_int & , unsigned int loop_depth , bool entered_at_top ) { if ( loop_depth > <NUM_LIT> ) return false ;

if ( TARGET_ARC700 && ! entered_at_top && wi :: gtu_p ( iterations , <NUM_LIT> ) && wi :: leu_p ( iterations , flag_pic ? <NUM_LIT> : <NUM_LIT> ) ) return false ;


<s> void recordFnStart ( SMLoc L ) { FnStartLocs . push_back ( L ) ;


<s> SDValue Input = OrigSToV . getOperand ( <NUM_LIT> ) ; if ( Input . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * Idx = dyn_cast < ConstantSDNode > ( Input . getOperand ( <NUM_LIT> ) ) ; SDValue OrigVector = Input . getOperand ( <NUM_LIT> ) ; if ( Idx && VT == OrigVector . getValueType ( ) ) { SmallVector < int , <NUM_LIT> > NewMask ( VT . getVectorNumElements ( ) , - <NUM_LIT> ) ; NewMask [ VT . getVectorNumElements ( ) / <NUM_LIT> ] = Idx -> getZExtValue ( ) ;

return DAG . getVectorShuffle ( VT , dl , OrigVector , OrigVector , NewMask ) ;


<s> <ISA_LIT>ControlFlowFinalizer ( ) : MachineFunctionPass ( ID ) {


<s> const HOST_WIDE_INT size = int_size_in_bytes ( type ) ;

return ( size == - <NUM_LIT> || size > UNITS_PER_WORD * NUM_ARGUMENT_REGISTERS ) ;


<s> int64_t Offset = OFFSET_DEFAULT_ ; int64_t Width = WIDTH_DEFAULT_ ; if ( parseHwregBody ( HwReg , Offset , Width ) && validateHwreg ( HwReg , Offset , Width , Loc ) ) { ImmVal = encodeHwreg ( HwReg . Id , Offset , Width ) ; } } else if ( parseExpr ( ImmVal ) ) { if ( ImmVal < <NUM_LIT> || ! isUInt < <NUM_LIT> > ( ImmVal ) ) Error ( Loc , <STR_LIT> ) ; }

Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , ImmVal , Loc , <ISA_LIT>Operand :: ImmTyHwreg ) ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> output_addr_const ( asm_out_file , x ) ; fputs ( <STR_LIT> ASM_COMMENT_START <STR_LIT> , asm_out_file ) ; fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , x ) ; fputs ( <STR_LIT> ASM_COMMENT_START <STR_LIT> , asm_out_file ) ; return true ; } else if ( CONST_FIXED_P ( x ) ) { for ( unsigned n = <NUM_LIT> ; n < size ; n ++ ) {

rtx xn = simplify_gen_subreg ( QImode , x , GET_MODE ( x ) , n ) ;


<s> if ( any_of ( make_range ( std :: next ( FirstRealElt ) , M . end ( ) ) , [ & ExpectedElt ] ( int Elt ) { return Elt != ExpectedElt ++ && Elt >= <NUM_LIT> ; } ) ) return None ; uint64_t Imm = ExpectedElt . getZExtValue ( ) ;


<s> bool <ISA_LIT>EarlyIfConversion :: usesUndefVReg ( const MachineInstr * MI ) const { for ( const MachineOperand & MO : MI -> operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isUse ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; const MachineInstr * DefI = MRI -> getVRegDef ( R ) ;


<s> if ( MF . hasEHFunclets ( ) ) return true ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> hasStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) > DefaultSafeSPDisplacement ) return true ;


<s> bool requiresRealignment = ( ( MFI -> getMaxAlignment ( ) > StackAlign ) || F -> getFnAttributes ( ) . hasStackAlignmentAttr ( ) ) ; if ( ForceStackAlign ) return canRealignStack ( MF ) ;

return requiresRealignment && canRealignStack ( MF ) ;


<s> SDValue In = Op . getOperand ( <NUM_LIT> ) ; MVT SVT = In . getSimpleValueType ( ) ; assert ( SVT == <STR_LIT> && <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , In , DAG . getUNDEF ( SVT ) ) ) ;


<s> void <ISA_LIT>InstrInfo :: AnalyzeCondBr ( const MachineInstr * Inst , unsigned Opc , MachineBasicBlock * & BB , SmallVectorImpl < MachineOperand > & Cond ) const {

assert ( getAnalyzableBrOpc ( Opc ) && <STR_LIT> ) ;


<s> if ( Top . NT != NT1 && Top . NT != NT2 ) return error ( Twine ( <STR_LIT> ) + nestingString ( Top . NT ) . second + <STR_LIT> + Ins ) ;


<s> for ( ++ I ; I != E && I -> isBundledWithPred ( ) ; ++ I ) { ++ Count ; Lat = std :: max ( Lat , SchedModel . computeInstrLatency ( & * I ) ) ;


<s> unsigned Rt = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rt2 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned Rn = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned addr = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned W = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned U = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned P = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; bool writeback = ( W == <NUM_LIT> ) | ( P == <NUM_LIT> ) ; addr |= ( U << <NUM_LIT> ) | ( Rn << <NUM_LIT> ) ; if ( writeback && ( Rn == Rt || Rn == Rt2 ) ) Check ( S , MCDisassembler :: SoftFail ) ; if ( Rt == Rt2 ) Check ( S , MCDisassembler :: SoftFail ) ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rt2 , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> bool <ISA_LIT>GenPredicate :: isPredReg ( unsigned R ) { if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) return false ; const TargetRegisterClass * RC = MRI -> getRegClass ( R ) ;


<s> return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> std :: string ArchFS = <STR_LIT> ( TT ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) {

ArchFS = ( Twine ( ArchFS ) + <STR_LIT> + FS ) . str ( ) ;


<s> assert ( Op . isImm ( ) && <STR_LIT> ) ; int64_t Res ; if ( ! Op . getImm ( ) -> evaluateAsAbsolute ( Res ) || Res > <NUM_LIT> ) { Error ( Op . getStartLoc ( ) , <STR_LIT> ) ; return false ; } return true ; }


<s> } <STR_LIT> CC ; SDValue LHS , RHS ; if ( CCVal . getOpcode ( ) == <STR_LIT> ) { LHS = CCVal . getOperand ( <NUM_LIT> ) ; RHS = CCVal . getOperand ( <NUM_LIT> ) ; CC = cast < CondCodeSDNode > ( CCVal -> getOperand ( <NUM_LIT> ) ) -> get ( ) ; } else { LHS = CCVal ; RHS = DAG . getConstant ( <NUM_LIT> , DL , CCVal . getValueType ( ) ) ;


<s> void addMemNoOffsetT2Operands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> T UImm = static_cast < T > ( Imm ) ; if ( <STR_LIT> ( UImm , RegSize ) ) return false ; SmallVector < <ISA_LIT>_IMM :: ImmInsnModel , <NUM_LIT> > Insn ; <ISA_LIT>_IMM :: expandMOVImm ( UImm , RegSize , Insn ) ; if ( Insn . size ( ) == <NUM_LIT> ) return false ; unsigned LowestBitSet = countTrailingZeros ( UImm ) ; unsigned HighestBitSet = Log2_64 ( UImm ) ; T NewImm1 = ( static_cast < T > ( <NUM_LIT> ) << HighestBitSet ) - ( static_cast < T > ( <NUM_LIT> ) << LowestBitSet ) ; T NewImm2 = UImm | ~ NewImm1 ; if ( ! <STR_LIT> ( NewImm2 , RegSize ) ) return false ; Imm1Enc = <STR_LIT> ( NewImm1 , RegSize ) ; Imm2Enc = <STR_LIT> ( NewImm2 , RegSize ) ;


<s> auto * BE = cast < MCBinaryExpr > ( Expr ) ; if ( BE -> getOpcode ( ) == MCBinaryExpr :: Sub ) return false ; return needsPCRel ( BE -> getLHS ( ) ) || needsPCRel ( BE -> getRHS ( ) ) ; } case MCExpr :: Unary : return needsPCRel ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) ) ;


<s> if ( GET_CODE ( val ) != REG && GET_CODE ( val ) != CONST_INT ) val = copy_to_mode_reg ( QImode , val ) ; if ( GET_CODE ( out ) != REG ) out = gen_reg_rtx ( QImode ) ; in = simplify_gen_subreg ( HImode , in , QImode , <NUM_LIT> ) ; outsub = simplify_gen_subreg ( HImode , out , QImode , <NUM_LIT> ) ; if ( GET_CODE ( val ) != CONST_INT ) val = simplify_gen_subreg ( HImode , val , QImode , <NUM_LIT> ) ; emit_insn ( gen_andhi3 ( outsub , in , val ) ) ;

if ( out != operands [ <NUM_LIT> ] ) emit_move_insn ( operands [ <NUM_LIT> ] , out ) ;


<s> int64_t offset = cast < GlobalAddressSDNode > ( op ) -> getOffset ( ) ; SDValue res = DAG . getTargetGlobalAddress ( GV , op -> getDebugLoc ( ) , getPointerTy ( ) , offset ) ; return DAG . getNode ( <STR_LIT> , op . getDebugLoc ( ) , getPointerTy ( ) , res ) ;


<s> unsigned AddrReg = getRegForValue ( BI -> getOperand ( <NUM_LIT> ) ) ; if ( AddrReg == <NUM_LIT> ) return false ; const MCInstrDesc & II = TII . get ( <STR_LIT> ) ; AddrReg = constrainOperandRegClass ( II , AddrReg , II . getNumDefs ( ) ) ;

BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , II ) . addReg ( AddrReg ) ;


<s> static bool isJump ( unsigned Opcode ) {

return Opcode == AMDGPU :: JUMP || Opcode == AMDGPU :: JUMP_COND ;


<s> static bool contains_core_p ( unsigned * arr , unsigned core ) {

if ( arr [ <NUM_LIT> ] != INVALID_CORE ) {


<s> const class xlogue_layout & xlogue_layout :: get_instance ( ) { enum xlogue_stub_sets stub_set ;

bool aligned_plus_8 = cfun -> machine -> call_ms2sysv_pad_in ;


<s> for ( <STR_LIT> & Inst : Seq ) { SDValue SDImm = CurDAG -> getTargetConstant ( Inst . Imm , DL , XLenVT ) ; if ( Inst . Opc == <STR_LIT> ) Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , XLenVT , SDImm ) ; else Result = CurDAG -> getMachineNode ( Inst . Opc , DL , XLenVT , SrcReg , SDImm ) ; SrcReg = SDValue ( Result , <NUM_LIT> ) ; }


<s> SDLoc SL ( In ) ; Src = CurDAG -> getTargetConstantFP ( C -> getValueAPF ( ) , SL , C -> getValueType ( <NUM_LIT> ) ) ; } else Src = In ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : LLVMTargetMachine ( T , TT . isArch64Bit ( ) ? <STR_LIT> : <STR_LIT> , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( make_unique < <ISA_LIT>TargetObjectFile > ( ) ) { this -> Options . TrapUnreachable = true ; initAsmInfo ( ) ;


<s> void emit<ISA_LIT>RegisterScratch ( unsigned reg ) override {


<s> if ( ( ShuffleMask [ Start ] % <NUM_LIT> == <NUM_LIT> ) && isSequentialMask ( ShuffleMask . slice ( Start , <NUM_LIT> ) ) ) { unsigned NewStart = ShuffleMask [ Start ] ; unsigned ArgNo = NewStart >= SVN -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; if ( ArgNo ) NewStart -= SVN -> getValueType ( <NUM_LIT> ) . getVectorNumElements ( ) ; return getSubRegisterValue ( SVN -> getOperand ( ArgNo ) , ResTy , NewStart , DL , DAG ) ; } } if ( SubRegSource . getOpcode ( ) == <STR_LIT> ) {

SDValue SubVectorStart = DAG . getConstant ( APInt ( <NUM_LIT> , Start ) , DL , <STR_LIT> ) ;


<s> uint8_t BitG = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t BitH = ( Imm & <NUM_LIT> ) != <NUM_LIT> ; uint8_t EncVal = BitA ; EncVal <<= <NUM_LIT> ; EncVal |= BitB ; EncVal <<= <NUM_LIT> ; EncVal |= BitC ; EncVal <<= <NUM_LIT> ; EncVal |= BitD ;


<s> const unsigned VirtReg = MO . getReg ( ) ; if ( TRI -> isPhysicalRegister ( VirtReg ) ) continue ; if ( ! VRM -> hasPhys ( VirtReg ) ) continue ; unsigned PhysReg = VRM -> getPhys ( VirtReg ) ; const unsigned SubReg = MO . getSubReg ( ) ; if ( SubReg != <NUM_LIT> ) { PhysReg = TRI -> getSubReg ( PhysReg , SubReg ) ; MO . setSubReg ( <NUM_LIT> ) ; } MO . setReg ( PhysReg ) ; MO . setIsRenamable ( false ) ; } } } <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned Reg : RegsToRewrite ) { LIS -> removeInterval ( Reg ) ; const unsigned PhysReg = VRM -> getPhys ( Reg ) ; assert ( PhysReg != <NUM_LIT> ) ; MFI -> ReserveWWMRegister ( PhysReg ) ; } RegsToRewrite . clear ( ) ; MRI -> freezeReservedRegs ( MF ) ;


<s> AU . addRequired < AssumptionCacheTracker > ( ) ; AU . addRequired < DominatorTreeWrapperPass > ( ) ; AU . addRequired < TargetLibraryInfoWrapperPass > ( ) ;

AU . addRequired < TargetPassConfig > ( ) ;


<s> if ( score > max_score ) { max_score = score ; max_index = i ; } } if ( max_index != - <NUM_LIT> ) { if ( max_index != last_index ) { tmp = ready [ max_index ] ; ready [ max_index ] = ready [ last_index ] ; ready [ last_index ] = tmp ; if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> , INSN_UID ( ready [ last_index ] ) ) ; } else if ( verbose > <NUM_LIT> ) fprintf ( file , <STR_LIT> , INSN_UID ( ready [ last_index ] ) ) ; } if ( verbose > <NUM_LIT> ) { fprintf ( file , <STR_LIT> , sched_state . group_state ) ; for ( i = last_index ; i >= <NUM_LIT> ; i -- ) { unsigned int sched_mask ; rtx_insn * insn = ready [ i ] ; if ( recog_memoized ( insn ) < <NUM_LIT> ) continue ; sched_mask = s390_get_sched_attrmask ( insn ) ;

fprintf ( file , <STR_LIT> , INSN_UID ( insn ) , s390_sched_score ( insn ) ) ;


<s> switch ( getGeneration ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ;


<s> if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_AMD64_ADDR32NB ; return COFF :: IMAGE_REL_AMD64_ADDR32 ; case FK_Data_8 : return COFF :: IMAGE_REL_AMD64_ADDR64 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_AMD64_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_AMD64_SECREL ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( getMachine ( ) == COFF :: IMAGE_FILE_MACHINE_I386 ) { switch ( FixupKind ) { case FK_PCRel_4 : case <STR_LIT> : case <STR_LIT> : return COFF :: IMAGE_REL_I386_REL32 ; case FK_Data_4 : case <STR_LIT> : if ( Modifier == MCSymbolRefExpr :: VK_COFF_IMGREL32 ) return COFF :: IMAGE_REL_I386_DIR32NB ; return COFF :: IMAGE_REL_I386_DIR32 ; case FK_SecRel_2 : return COFF :: IMAGE_REL_I386_SECTION ; case FK_SecRel_4 : return COFF :: IMAGE_REL_I386_SECREL ;


<s> for ( size_t i = <NUM_LIT> ; i < strlen ( p ) ; ++ i ) if ( p [ i ] == '.' ) p [ i ] = '$' ; return p ;


<s> enum rtx_code code = GET_CODE ( op ) ; if ( code != PLUS && code != SMIN && code != SMAX ) return false ; rtx concat = XEXP ( op , <NUM_LIT> ) ; if ( GET_CODE ( concat ) != VEC_CONCAT ) return false ; rtx select0 = XEXP ( concat , <NUM_LIT> ) ; rtx select1 = XEXP ( concat , <NUM_LIT> ) ;

if ( GET_CODE ( select0 ) != VEC_SELECT || GET_CODE ( select1 ) != VEC_SELECT ) return false ;


<s> int GPRSize = FuncInfo -> getVarArgsGPRSize ( ) ; if ( GPRSize > <NUM_LIT> ) { SDValue GRTop , GRTopAddr ; GRTopAddr = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VAList , DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( ) ) ) ; GRTop = DAG . getFrameIndex ( FuncInfo -> getVarArgsGPRIndex ( ) , getPointerTy ( ) ) ; GRTop = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , GRTop , DAG . getConstant ( GPRSize , DL , getPointerTy ( ) ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , GRTop , GRTopAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ) ; } int FPRSize = FuncInfo -> getVarArgsFPRSize ( ) ; if ( FPRSize > <NUM_LIT> ) { SDValue VRTop , VRTopAddr ; VRTopAddr = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VAList , DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( ) ) ) ; VRTop = DAG . getFrameIndex ( FuncInfo -> getVarArgsFPRIndex ( ) , getPointerTy ( ) ) ; VRTop = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( ) , VRTop , DAG . getConstant ( FPRSize , DL , getPointerTy ( ) ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , VRTop , VRTopAddr , MachinePointerInfo ( SV , <NUM_LIT> ) , false , false , <NUM_LIT> ) ) ;


<s> } if ( IdxVal != <NUM_LIT> && ( InVec . getOpcode ( ) == <STR_LIT> || InVec . getOpcode ( ) == <STR_LIT> ) ) return extractSubVector ( InVec , <NUM_LIT> , DAG , SDLoc ( N ) , VT . getSizeInBits ( ) ) ; if ( InVec . getOpcode ( ) == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) return InVec . getOperand ( <NUM_LIT> ) ; if ( IdxVal == <NUM_LIT> && InVec . hasOneUse ( ) ) { unsigned InOpcode = InVec . getOpcode ( ) ; if ( VT == <STR_LIT> && InVecVT == <STR_LIT> ) { if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , InVec . getOperand ( <NUM_LIT> ) ) ; } if ( InOpcode == <STR_LIT> && Subtarget . hasVLX ( ) && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , InVec . getOperand ( <NUM_LIT> ) ) ; } if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) { return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , InVec . getOperand ( <NUM_LIT> ) ) ; } } if ( ( InOpcode == <STR_LIT> || InOpcode == <STR_LIT> || InOpcode == <STR_LIT> || InOpcode == <STR_LIT> || InOpcode == <STR_LIT> || InOpcode == <STR_LIT> ) && VT . is128BitVector ( ) && InVec . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) . is128BitVector ( ) ) { unsigned ExtOp = getOpcode_EXTEND_VECTOR_INREG ( InOpcode ) ; return DAG . getNode ( ExtOp , SDLoc ( N ) , VT , InVec . getOperand ( <NUM_LIT> ) ) ; } if ( InOpcode == <STR_LIT> && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) && InVec . getOperand ( <NUM_LIT> ) . getValueType ( ) . is256BitVector ( ) ) { SDLoc DL ( N ) ; SDValue Ext0 = extractSubVector ( InVec . getOperand ( <NUM_LIT> ) , <NUM_LIT> , DAG , DL , <NUM_LIT> ) ; SDValue Ext1 = extractSubVector ( InVec . getOperand ( <NUM_LIT> ) , <NUM_LIT> , DAG , DL , <NUM_LIT> ) ; SDValue Ext2 = extractSubVector ( InVec . getOperand ( <NUM_LIT> ) , <NUM_LIT> , DAG , DL , <NUM_LIT> ) ; return DAG . getNode ( InOpcode , DL , VT , Ext0 , Ext1 , Ext2 ) ;


<s> SDValue Increment = DAG . getConstant ( SclrLoadTy . getSizeInBits ( ) / <NUM_LIT> , TLI . getPointerTy ( ) ) ; SDValue Res = DAG . getUNDEF ( LoadUnitVecVT ) ; for ( unsigned i = <NUM_LIT> ; i < NumLoads ; ++ i ) { SDValue ScalarLoad = DAG . getLoad ( SclrLoadTy , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Ld -> getAlignment ( ) ) ; Chains . push_back ( ScalarLoad . getValue ( <NUM_LIT> ) ) ; if ( i == <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT , ScalarLoad ) ; else Res = DAG . getNode ( <STR_LIT> , dl , LoadUnitVecVT , Res , ScalarLoad , DAG . getIntPtrConstant ( i ) ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; } SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chains ) ; SDValue SlicedVec = DAG . getNode ( <STR_LIT> , dl , WideVecVT , Res ) ; unsigned SizeRatio = RegSz / MemSz ; if ( Ext == <STR_LIT> ) { if ( Subtarget -> hasSSE41 ( ) ) { SDValue Sext = DAG . getNode ( <STR_LIT> , dl , RegVT , SlicedVec ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( Ld , <NUM_LIT> ) , TF ) ; return Sext ; } assert ( TLI . isOperationLegalOrCustom ( <STR_LIT> , RegVT ) && <STR_LIT> ) ; SmallVector < int , <NUM_LIT> > ShuffleVec ( NumElems * SizeRatio , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) ShuffleVec [ i * SizeRatio + SizeRatio - <NUM_LIT> ] = i ; SDValue Shuff = DAG . getVectorShuffle ( WideVecVT , dl , SlicedVec , DAG . getUNDEF ( WideVecVT ) , & ShuffleVec [ <NUM_LIT> ] ) ; Shuff = DAG . getNode ( <STR_LIT> , dl , RegVT , Shuff ) ; unsigned Amt = RegVT . getVectorElementType ( ) . getSizeInBits ( ) - MemVT . getVectorElementType ( ) . getSizeInBits ( ) ; Shuff = DAG . getNode ( <STR_LIT> , dl , RegVT , Shuff , DAG . getConstant ( Amt , RegVT ) ) ;


<s> nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( ImageOperand :: MinLod ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( ImageOperand :: MinLod ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( ImageOperand :: MakeTexelAvailableKHR ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( ImageOperand :: MakeTexelAvailableKHR ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( ImageOperand :: MakeTexelVisibleKHR ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( ImageOperand :: MakeTexelVisibleKHR ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( ImageOperand :: NonPrivateTexelKHR ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( ImageOperand :: NonPrivateTexelKHR ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( ImageOperand :: VolatileTexelKHR ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( ImageOperand :: VolatileTexelKHR ) ) { nameString += sep + <STR_LIT> ; sep = <STR_LIT> ; } if ( e == static_cast < uint32_t > ( ImageOperand :: SignExtend ) ) return <STR_LIT> ; if ( e & static_cast < uint32_t > ( ImageOperand :: SignExtend ) ) { nameString += sep + <STR_LIT> ;


<s> if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) sec = <NUM_LIT> ; else sec = <NUM_LIT> ; } else if ( decl_readonly_section ( decl , reloc ) ) sec = <NUM_LIT> ; if ( name [ <NUM_LIT> ] == '@' && name [ <NUM_LIT> ] == '.' ) { switch ( name [ <NUM_LIT> ] ) { case 'b' : sec = <NUM_LIT> ; break ; case 't' : if ( sec == <NUM_LIT> ) sec = <NUM_LIT> ; else sec = <NUM_LIT> ; break ; case 'f' : if ( sec == <NUM_LIT> ) sec = <NUM_LIT> ;

else if ( sec == <NUM_LIT> ) sec = <NUM_LIT> ;


<s> return TARGET_RED_ZONE && ! TARGET_64BIT_MS_ABI ;


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; SmallVector < <STR_LIT> , <NUM_LIT> > LocalIns ; getOriginalFunctionArgs ( DAG , DAG . getMachineFunction ( ) . getFunction ( ) , Ins , LocalIns ) ; AnalyzeFormalArguments ( CCInfo , LocalIns ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; EVT VT = Ins [ i ] . VT ; EVT MemVT = LocalIns [ i ] . VT ; PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <STR_LIT> ) ; SDValue Arg = DAG . getExtLoad ( <STR_LIT> , DL , VT , Chain , DAG . getConstant ( <NUM_LIT> + VA . getLocMemOffset ( ) , <STR_LIT> ) , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , MemVT , false , false , <NUM_LIT> ) ; InVals . push_back ( Arg ) ; } return Chain ;


<s> return static_cast < MCELFStreamer & > ( Streamer ) ;


<s> if ( OptLevel == CodeGenOpt :: None ) return true ; if ( ! CheckVMLxHazard ) return true ; if ( ! Subtarget -> isCortexA7 ( ) && ! Subtarget -> isCortexA8 ( ) && ! Subtarget -> isCortexA9 ( ) && ! Subtarget -> isSwift ( ) ) return true ; if ( ! N -> hasOneUse ( ) ) return false ; SDNode * Use = * N -> use_begin ( ) ; if ( Use -> getOpcode ( ) == <STR_LIT> ) return true ; if ( Use -> isMachineOpcode ( ) ) { const <ISA_LIT>BaseInstrInfo * TII = static_cast < const <ISA_LIT>BaseInstrInfo * > ( CurDAG -> getTarget ( ) . getInstrInfo ( ) ) ;

const MCInstrDesc & MCID = TII -> get ( Use -> getMachineOpcode ( ) ) ;


<s> virtual const TargetRegisterInfo * getRegisterInfo ( ) const {

return & InstrInfo . getRegisterInfo ( ) ;


<s> for ( auto I = B . begin ( ) , E = B . end ( ) , NextI = I ; I != E ; ++ I ) { NextI = std :: next ( I ) ; MachineInstr * MI = & * I ; if ( MI -> getOpcode ( ) == TargetOpcode :: COPY ) continue ; if ( MI -> hasUnmodeledSideEffects ( ) || MI -> isInlineAsm ( ) ) continue ; unsigned NumD = MI -> getDesc ( ) . getNumDefs ( ) ; if ( NumD != <NUM_LIT> ) continue ; BitTracker :: RegisterRef RD = MI -> getOperand ( <NUM_LIT> ) ; if ( ! BT . has ( RD . Reg ) ) continue ; const BitTracker :: RegisterCell & DC = BT . lookup ( RD . Reg ) ; auto At = MI -> isPHI ( ) ? B . getFirstNonPHI ( ) : MachineBasicBlock :: iterator ( MI ) ; for ( auto & Op : MI -> uses ( ) ) { if ( ! Op . isReg ( ) ) continue ; BitTracker :: RegisterRef RS = Op ; if ( ! BT . has ( RS . Reg ) ) continue ; if ( ! HBS :: isTransparentCopy ( RD , RS , MRI ) ) continue ; unsigned BN , BW ; if ( ! HBS :: getSubregMask ( RS , BN , BW , MRI ) ) continue ; const BitTracker :: RegisterCell & SC = BT . lookup ( RS . Reg ) ; if ( ! usedBitsEqual ( RD , RS ) && ! HBS :: isEqual ( DC , <NUM_LIT> , SC , BN , BW ) ) continue ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; const TargetRegisterClass * FRC = HBS :: getFinalVRegClass ( RD , MRI ) ; unsigned NewR = MRI . createVirtualRegister ( FRC ) ;

BuildMI ( B , At , DL , HII . get ( TargetOpcode :: COPY ) , NewR ) . addReg ( RS . Reg , <NUM_LIT> , RS . Sub ) ;


<s> static inline unsigned isImmPCRel ( uint64_t TSFlags ) { switch ( TSFlags & <STR_LIT> ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> :


<s> if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! tryAddingSymbolicOperand ( Address , imm , false , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ;


<s> static bool requiresFixups ( MCContext & C , const MCExpr * Value , const MCExpr * & LHS , const MCExpr * & RHS ) { const auto * MBE = dyn_cast < MCBinaryExpr > ( Value ) ; if ( MBE == nullptr ) return false ; MCValue E ; if ( ! Value -> evaluateAsRelocatable ( E , nullptr , nullptr ) ) return false ; if ( E . getSymA ( ) == nullptr || E . getSymB ( ) == nullptr ) return false ; const auto & A = E . getSymA ( ) -> getSymbol ( ) ; const auto & B = E . getSymB ( ) -> getSymbol ( ) ; LHS = MCBinaryExpr :: create ( MCBinaryExpr :: Add , MCSymbolRefExpr :: create ( & A , C ) , MCConstantExpr :: create ( E . getConstant ( ) , C ) , C ) ;


<s> Type * RetTy = Type :: getInt32Ty ( * DAG . getContext ( ) ) ; ArgListTy Args ; SDValue Chain = DAG . getEntryNode ( ) ; Chain = LowerF128_LibCallArg ( Chain , Args , LHS , DL , DAG ) ; Chain = LowerF128_LibCallArg ( Chain , Args , RHS , DL , DAG ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( Chain ) . setCallee ( CallingConv :: C , RetTy , Callee , std :: move ( Args ) , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; SDValue Result = CallInfo . first ; switch ( <ISA_LIT>CC ) { default : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue Mask = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; Result = DAG . getNode ( <STR_LIT> , DL , Result . getValueType ( ) , Result , Mask ) ; SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ; <ISA_LIT>CC = <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , RHS ) ; } case <STR_LIT> : { SDValue RHS = DAG . getTargetConstant ( <NUM_LIT> , Result . getValueType ( ) ) ;


<s> return __builtin_mve_vcmpneq_n_fv8hf ( __a , __b ) ;


<s> auto & Inst = RF . getInst ( ) ; auto & STI = * RF . getSubtargetInfo ( ) ;

bool Is16BitMode = STI . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> || VT == <STR_LIT> ) ; unsigned Opc = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Ops [ <NUM_LIT> ] ; SelectVOP3Mods0 ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;

SelectVOP3Mods ( N -> getOperand ( <NUM_LIT> ) , Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) ;


<s> for ( Function :: const_arg_iterator argi = F -> arg_begin ( ) , arge = F -> arg_end ( ) ; argi != arge ; ++ argi ) { const Type * Ty = argi -> getType ( ) ; ArgSize += TD -> getTypeAllocSize ( Ty ) ; } O << PAN :: getArgsLabel ( CurrentFnSym -> getName ( ) ) << <STR_LIT> << ArgSize << <STR_LIT> ; int TempSize = PTLI -> GetTmpSize ( ) ; if ( TempSize > <NUM_LIT> ) O << PAN :: getTempdataLabel ( CurrentFnSym -> getName ( ) ) << <STR_LIT> << TempSize << '\n' ;


<s> Known = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ; Known2 = DAG . computeKnownBits ( Op . getOperand ( <NUM_LIT> ) , Depth + <NUM_LIT> ) ;


<s> static SDValue LowerSVEIntrinsicEXT ( SDNode * N , SelectionDAG & DAG ) { SDLoc dl ( N ) ; LLVMContext & Ctx = * DAG . getContext ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned ElemSize = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; EVT ByteVT = EVT :: getVectorVT ( Ctx , <STR_LIT> , { VT . getSizeInBits ( ) / <NUM_LIT> , true } ) ; SDValue Op0 = DAG . getNode ( <STR_LIT> , dl , ByteVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Op1 = DAG . getNode ( <STR_LIT> , dl , ByteVT , N -> getOperand ( <NUM_LIT> ) ) ;

SDValue Op2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( ElemSize , dl , <STR_LIT> ) ) ;


<s> const auto & MBBs = MJTI -> getJumpTables ( ) [ JT -> getIndex ( ) ] . MBBs ; for ( auto MBB : MBBs ) Ops . push_back ( DAG . getBasicBlock ( MBB ) ) ; Ops . push_back ( DAG . getBasicBlock ( MBBs [ <NUM_LIT> ] ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ;


<s> case BRIG_TYPE_S32 : return <STR_LIT> ; case BRIG_TYPE_F32 : return <STR_LIT> ; case BRIG_TYPE_U64 : return <STR_LIT> ; case BRIG_TYPE_S64 : return <STR_LIT> ; case BRIG_TYPE_F64 : return <STR_LIT> ; case BRIG_TYPE_U8 : return <STR_LIT> ; case BRIG_TYPE_S8 : return <STR_LIT> ; case BRIG_TYPE_U16 : return <STR_LIT> ; case BRIG_TYPE_S16 : return <STR_LIT> ; default :


<s> const MachineOperand & MO3 = MI -> getOperand ( Op + <NUM_LIT> ) ; O << getRegisterName ( MO1 . getReg ( ) ) ; O << <STR_LIT> << <STR_LIT> ( <STR_LIT> ( MO3 . getImm ( ) ) ) << <STR_LIT> ; if ( MO2 . getReg ( ) ) { O << getRegisterName ( MO2 . getReg ( ) ) ;

assert ( <STR_LIT> ( MO3 . getImm ( ) ) == <NUM_LIT> ) ;


<s> if ( TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL ) error ( <STR_LIT> ) ; microblaze_sched_use_dfa = <NUM_LIT> ; microblaze_abicalls = MICROBLAZE_ABICALLS_NO ; real_maxval ( & dfhigh , <NUM_LIT> , DFmode ) ; real_maxval ( & dflow , <NUM_LIT> , DFmode ) ; real_maxval ( & sfhigh , <NUM_LIT> , SFmode ) ; real_maxval ( & sflow , <NUM_LIT> , SFmode ) ; microblaze_print_operand_punct [ '?' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '#' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '&' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '!' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '*' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '@' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '.' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '(' ] = <NUM_LIT> ; microblaze_print_operand_punct [ ')' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '[' ] = <NUM_LIT> ; microblaze_print_operand_punct [ ']' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '<' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '>' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '{' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '}' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '^' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '$' ] = <NUM_LIT> ; microblaze_print_operand_punct [ '+' ] = <NUM_LIT> ; for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) microblaze_dbx_regno [ i ] = - <NUM_LIT> ; start = GP_DBX_FIRST - GP_REG_FIRST ; for ( i = GP_REG_FIRST ; i <= GP_REG_LAST ; i ++ ) microblaze_dbx_regno [ i ] = i + start ; for ( mode = VOIDmode ; mode != MAX_MACHINE_MODE ; mode = ( machine_mode ) ( ( int ) mode + <NUM_LIT> ) ) { register int size = GET_MODE_SIZE ( mode ) ; for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) { register int ok ; if ( mode == CCmode ) {

ok = ( ST_REG_P ( regno ) || GP_REG_P ( regno ) ) ;


<s> const bool NonPCrelGEPRequired = ! Subtarget -> isUsingPCRelativeCalls ( ) && Subtarget -> isELFv2ABI ( ) && UsesX2OrR2 ; if ( NonPCrelGEPRequired || PCrelGEPRequired ) { MCSymbol * GlobalEntryLabel = <ISA_LIT>FI -> getGlobalEPSymbol ( * MF ) ; OutStreamer -> emitLabel ( GlobalEntryLabel ) ; const MCSymbolRefExpr * GlobalEntryLabelExp = MCSymbolRefExpr :: create ( GlobalEntryLabel , OutContext ) ; if ( TM . getCodeModel ( ) != CodeModel :: Large ) { MCSymbol * TOCSymbol = OutContext . getOrCreateSymbol ( StringRef ( <STR_LIT> ) ) ; const MCExpr * TOCDeltaExpr = MCBinaryExpr :: createSub ( MCSymbolRefExpr :: create ( TOCSymbol , OutContext ) , GlobalEntryLabelExp , OutContext ) ; const MCExpr * TOCDeltaHi = <ISA_LIT>MCExpr :: createHa ( TOCDeltaExpr , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaHi ) ) ; const MCExpr * TOCDeltaLo = <ISA_LIT>MCExpr :: createLo ( TOCDeltaExpr , OutContext ) ; EmitToStreamer ( * OutStreamer , MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addExpr ( TOCDeltaLo ) ) ; } else {

MCSymbol * TOCOffset = <ISA_LIT>FI -> getTOCOffsetSymbol ( * MF ) ;


<s> Value * FunctionName = CreateStringPtr ( BB , F . getName ( ) ) ; Value * Args [ ] = { FunctionName , ConstantInt :: get ( I16 , F . arg_size ( ) ) } ; CallInst :: Create ( Fn , Args , <STR_LIT> , & BB ) ;


<s> mHWBits . set ( <STR_LIT> ) ; } mSWBits . set ( <STR_LIT> ) ; mHWBits . reset ( <STR_LIT> ) ;


<s> unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Src ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Dst ) ; Skip ( MI , MI . getOperand ( <NUM_LIT> ) ) ; MI . eraseFromParent ( ) ;


<s> for ( MachineBasicBlock :: iterator UseI = Def ; UseI != BBEnd ; ++ UseI ) { AluInstCount += OccupiedDwords ( * UseI ) ; if ( ! SubstituteKCacheBank ( * UseI , KCacheBanks , false ) ) return false ; if ( AluInstCount >= TII -> getMaxAlusPerClause ( ) ) return false ;

if ( UseI -> readsRegister ( MOI -> getReg ( ) , & TRI ) ) LastUseCount = AluInstCount ;


<s> int <ISA_LIT>TTIImpl :: getMemoryOpCost ( unsigned Opcode , Type * Src , unsigned Alignment , unsigned AddressSpace , const Instruction * I ) { std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , Src ) ; if ( Src -> isVectorTy ( ) && Alignment != <NUM_LIT> && Src -> getVectorElementType ( ) -> isDoubleTy ( ) ) {


<s> int getVarArgsFrameIndex ( ) const { return VarArgsFrameIndex ;


<s> if ( is<ISA_LIT>NEONPred ( MI ) ) AddDefaultPred ( MIB ) ; bool CPSR = false ; if ( DefinesOptionalPredicate ( MI , & CPSR ) ) {


<s> static MCASMInfo * createNPEngineMCASMInfo ( const MCRegisterInfo & MRI , StringRef TT ) { MCASMInfo * MAI = new NPEngineMCASMInfo ( TT ) ; return MAI ;


<s> bool GCNPassConfig :: addInstSelector ( ) { <ISA_LIT>PassConfig :: addInstSelector ( ) ; addPass ( create<ISA_LIT>LowerI1CopiesPass ( ) ) ; addPass ( & <ISA_LIT>FixSGPRCopiesID ) ; addPass ( create<ISA_LIT>FoldOperandsPass ( ) ) ; return false ;


<s> void <ISA_LIT>ELFMCAsmInfo :: anchor ( ) {


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) , Subtarget ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ) {


<s> return gen_store_pairdi ( mem1 , reg1 , mem2 , reg2 ) ; case DFmode : return gen_store_pairdf ( mem1 , reg1 , mem2 , reg2 ) ; default : gcc_unreachable ( ) ; }


<s> EmitInstrRegReg ( MovOpc , Reg1 , FPReg1 ) ; EmitInstrRegReg ( MovOpc , Reg2 , FPReg2 ) ;


<s> if ( ImmOffset ) Expr = MCBinaryExpr :: CreateAdd ( Expr , MCConstantExpr :: Create ( ImmOffset , Ctx ) , Ctx ) ; Fixups . push_back ( MCFixup :: Create ( CurByte , Expr , FixupKind ) ) ; EmitConstant ( <NUM_LIT> , Size , CurByte , OS ) ;


<s> if ( hasMSA ( ) && ! isFP64bit ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> , false ) ; if ( ! isABI_O32 ( ) && ! useOddSPReg ( ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( IsFPXX && ( isABI_N32 ( ) || isABI_N64 ( ) ) ) report_fatal_error ( <STR_LIT> , false ) ; if ( has<ISA_LIT>64r6 ( ) && InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> , false ) ; if ( UseIndirectJumpsHazard ) { if ( InMicro<ISA_LIT>Mode ) report_fatal_error ( <STR_LIT> ) ; if ( ! has<ISA_LIT>32r2 ( ) ) report_fatal_error ( <STR_LIT> ) ; } if ( has<ISA_LIT>32r6 ( ) ) { StringRef ISA = has<ISA_LIT>64r6 ( ) ? <STR_LIT> : <STR_LIT> ; assert ( isFP64bit ( ) ) ; assert ( isNaN2008 ( ) ) ; if ( hasDSP ( ) ) report_fatal_error ( ISA + <STR_LIT> , false ) ; } if ( NoABICalls && TM . isPositionIndependent ( ) ) report_fatal_error ( <STR_LIT> ) ; if ( isABI_N64 ( ) && ! TM . isPositionIndependent ( ) && ! hasSym32 ( ) ) NoABICalls = true ; UseSmallSection = GPOpt ; if ( ! NoABICalls && GPOpt ) { errs ( ) << <STR_LIT> << <STR_LIT> ; UseSmallSection = false ; }


<s> case <STR_LIT> : return lowerGlobalTLSAddress ( cast < GlobalAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( cast < BlockAddressSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerJumpTable ( cast < JumpTableSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerConstantPool ( cast < ConstantPoolSDNode > ( Op ) , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerVAARG ( Op , DAG ) ;


<s> assert ( SUI -> getInstr ( ) && SUJ -> getInstr ( ) ) ; return false ;


<s> if ( STI -> getFeatureBits ( ) . test ( FeatureTrapHandler ) ) MaxNumSGPRs -= std :: min ( MaxNumSGPRs , ( unsigned ) TRAP_NUM_SGPRS ) ; MaxNumSGPRs = alignDown ( MaxNumSGPRs , getSGPRAllocGranule ( STI ) ) ; return std :: min ( MaxNumSGPRs , AddressableNumSGPRs ) ;


<s> LOHInstToLabel [ MI ] = LOHLabel ; OutStreamer . EmitLabel ( LOHLabel ) ; } switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : { if ( isVerbose ( ) && OutStreamer . hasRawTextSupport ( ) ) { SmallString < <NUM_LIT> > TmpStr ; raw_svector_ostream OS ( TmpStr ) ; PrintDebugValueComment ( MI , OS ) ; OutStreamer . EmitRawText ( StringRef ( OS . str ( ) ) ) ; } return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MCInst TmpInst ; TmpInst . setOpcode ( getRealIndexedOpcode ( MI -> getOpcode ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) ; TmpInst . addOperand ( MCOperand :: CreateImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ) ; EmitToStreamer ( OutStreamer , TmpInst ) ; return ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MCInst TmpInst ;


<s> if ( F . hasFnAttribute ( Attribute :: AttrKind :: AlwaysInline ) ) { FuncControl |= FunctionControl :: Inline ; } if ( F . hasFnAttribute ( Attribute :: AttrKind :: ReadNone ) ) { FuncControl |= FunctionControl :: Pure ; } if ( F . hasFnAttribute ( Attribute :: AttrKind :: ReadOnly ) ) {

FuncControl |= FunctionControl :: Const ;


<s> return { <STR_LIT> , <NUM_LIT> , <NUM_LIT> } ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc DL ( N ) ; if ( ! DCI . isBeforeLegalizeOps ( ) && N0 . getOpcode ( ) == <STR_LIT> ) { SDValue Setcc = DAG . getNode ( <STR_LIT> , DL , VT , N0 -> getOperand ( <NUM_LIT> ) , N0 -> getOperand ( <NUM_LIT> ) ) ; bool ReplaceOtherUses = ! N0 . hasOneUse ( ) ; DCI . CombineTo ( N , Setcc ) ; if ( ReplaceOtherUses ) { SDValue Trunc = DAG . getNode ( <STR_LIT> , SDLoc ( N0 ) , N0 . getValueType ( ) , Setcc ) ; DCI . CombineTo ( N0 . getNode ( ) , Trunc ) ; } return SDValue ( N , <NUM_LIT> ) ; } if ( SDValue NewCMov = combineToExtendCMOV ( N , DAG ) ) return NewCMov ; if ( ! DCI . isBeforeLegalizeOps ( ) ) return SDValue ( ) ;

if ( SDValue V = combineExtSetcc ( N , DAG , Subtarget ) ) return V ;


<s> const char * nds32_output_stack_pop ( rtx par_rtx ATTRIBUTE_UNUSED ) { char pattern [ <NUM_LIT> ] ; rtx operands [ <NUM_LIT> ] ; int rb_eh_data = cfun -> machine -> eh_return_data_first_regno ; int re_eh_data = cfun -> machine -> eh_return_data_last_regno ; int first_eh_data_regno = EH_RETURN_DATA_REGNO ( <NUM_LIT> ) ; int rb_callee_saved = cfun -> machine -> callee_saved_first_gpr_regno ; int re_callee_saved = cfun -> machine -> callee_saved_last_gpr_regno ; if ( reg_mentioned_p ( gen_rtx_REG ( SImode , first_eh_data_regno ) , par_rtx ) ) { operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , rb_eh_data ) ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_eh_data ) ; snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; return <STR_LIT> ; } if ( TARGET_V3PUSH && ! nds32_isr_function_p ( current_function_decl ) && ( cfun -> machine -> va_args_size == <NUM_LIT> ) ) { int sp_adjust ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_callee_saved ) ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca ) operands [ <NUM_LIT> ] = GEN_INT ( sp_adjust ) ; else { if ( cfun -> machine -> callee_saved_first_fpr_regno != SP_REGNUM ) { sp_adjust = cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; operands [ <NUM_LIT> ] = GEN_INT ( sp_adjust ) ; } else { operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> ) ; } } snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; } else { int pop_en4_only_p = <NUM_LIT> ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , rb_callee_saved ) ; operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_callee_saved ) ; if ( ! cfun -> machine -> fp_size && ! cfun -> machine -> gp_size && ! cfun -> machine -> lp_size && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM && REGNO ( operands [ <NUM_LIT> ] ) == SP_REGNUM ) { return <STR_LIT> ; }


<s> return <NUM_LIT> ; } unsigned Reg = II -> getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) ; int32_t Imm12 = MO1 . getImm ( ) ; uint32_t Binary ; Binary = Imm12 & <NUM_LIT> ; if ( Imm12 >= <NUM_LIT> ) Binary |= ( <NUM_LIT> << <NUM_LIT> ) ;


<s> MachineInstr * AMDGPUCFGStructurizer :: getReturnInstr ( MachineBasicBlock * MBB ) { MachineBasicBlock :: reverse_iterator It = MBB -> rbegin ( ) ; if ( It != MBB -> rend ( ) ) { MachineInstr * instr = & ( * It ) ;

if ( instr -> getOpcode ( ) == AMDGPU :: RETURN ) return instr ;


<s> <ISA_LIT>MCExpr :: VariantKind VK = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ; if ( ! isImm ( ) || evaluateConstantImm ( getImm ( ) , Imm , VK ) ) return false ;

return <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK ) && ( VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL || VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ) ;


<s> vqrdmulhq_n_s16 ( int16x8_t a , int16_t b ) { int16x8_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ; return result ;


<s> <ISA_LIT>AddressSanitizer ( const MCSubtargetInfo & STI ) : STI ( STI ) {


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> if ( MAI -> doesSupportExceptionHandling ( ) && MMI ) { const std :: vector < Function * > & Personalities = MMI -> getPersonalities ( ) ; for ( std :: vector < Function * > :: const_iterator I = Personalities . begin ( ) , E = Personalities . end ( ) ; I != E ; ++ I ) { if ( * I ) { MCSymbol * NLPSym = GetSymbolWithGlobalValueBase ( * I , <STR_LIT> ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = MMIMacho . getGVStubEntry ( NLPSym ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( Mang -> getSymbol ( * I ) , true ) ; } } } Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFMacho . getNonLazySymbolPointerSection ( ) ) ; EmitAlignment ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; MachineModuleInfoImpl :: StubValueTy & MCSym = Stubs [ i ] . second ; OutStreamer . EmitSymbolAttribute ( MCSym . getPointer ( ) , MCSA_IndirectSymbol ) ; if ( MCSym . getInt ( ) ) OutStreamer . EmitIntValue ( <NUM_LIT> , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ; else OutStreamer . EmitValue ( MCSymbolRefExpr :: Create ( MCSym . getPointer ( ) , OutContext ) , is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , <NUM_LIT> ) ; } Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } Stubs = MMIMacho . GetHiddenGVStubList ( ) ;


<s> } else { TargetABI = <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ; } } else if ( TT . isOSWindows ( ) ) { TargetABI = <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ; } else { switch ( TT . getEnvironment ( ) ) { case llvm :: Triple :: Android : case llvm :: Triple :: GNUEABI : case llvm :: Triple :: GNUEABIHF : case llvm :: Triple :: EABIHF : case llvm :: Triple :: EABI : TargetABI = <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ; break ; case llvm :: Triple :: GNU : TargetABI = <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ; break ; default : if ( TT . getOS ( ) == llvm :: Triple :: NetBSD ) TargetABI = <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_APCS ; else TargetABI = <ISA_LIT>BaseTargetMachine :: <ISA_LIT>_ABI_AAPCS ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


return ( int8x8_t ) __builtin_neon_vreinterpretv8qiv8qi ( ( int8x8_t ) __a ) ;


<s> void <ISA_LIT>Subtarget :: resetSubtargetFeatures ( StringRef CPU , StringRef FS ) { if ( CPUString . empty ( ) ) { if ( isTargetIOS ( ) && TargetTriple . getArchName ( ) . endswith ( <STR_LIT> ) ) CPUString = <STR_LIT> ; else CPUString = <STR_LIT> ; } std :: string ArchFS = <ISA_LIT>_MC :: Parse<ISA_LIT>Triple ( TargetTriple . getTriple ( ) , CPUString ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) ArchFS = ArchFS + <STR_LIT> + FS . str ( ) ; else ArchFS = FS ; } ParseSubtargetFeatures ( CPUString , ArchFS ) ; assert ( hasV6T2Ops ( ) || ! hasThumb2 ( ) ) ; SchedModel = getSchedModelForCPU ( CPUString ) ; InstrItins = getInstrItineraryForCPU ( CPUString ) ; if ( TargetABI == <ISA_LIT>_ABI_UNKNOWN ) { switch ( TargetTriple . getEnvironment ( ) ) { case Triple :: Android : case Triple :: EABI : case Triple :: EABIHF : case Triple :: GNUEABI : case Triple :: GNUEABIHF : TargetABI = <ISA_LIT>_ABI_AAPCS ; break ; default : if ( ( isTargetIOS ( ) && isMClass ( ) ) || ( TargetTriple . isOSBinFormatMachO ( ) && TargetTriple . getOS ( ) == Triple :: UnknownOS ) ) TargetABI = <ISA_LIT>_ABI_AAPCS ; else TargetABI = <ISA_LIT>_ABI_APCS ;


<s> int <ISA_LIT>CFGStructurizer :: handleJumpintoIfImp ( MachineBasicBlock * HeadMBB , MachineBasicBlock * TrueMBB , MachineBasicBlock * FalseMBB ) { int Num = <NUM_LIT> ; MachineBasicBlock * DownBlk ; DownBlk = TrueMBB ; DEBUG ( dbgs ( ) << <STR_LIT> << HeadMBB -> getNumber ( ) << <STR_LIT> << TrueMBB -> getNumber ( ) << <STR_LIT> << TrueMBB -> succ_size ( ) << <STR_LIT> << FalseMBB -> getNumber ( ) << <STR_LIT> ; ) ; while ( DownBlk ) { DEBUG ( dbgs ( ) << <STR_LIT> << DownBlk -> getNumber ( ) ; ) ; if ( singlePathTo ( FalseMBB , DownBlk ) == SinglePath_InPath ) { DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; Num += cloneOnSideEntryTo ( HeadMBB , TrueMBB , DownBlk ) ; Num += cloneOnSideEntryTo ( HeadMBB , FalseMBB , DownBlk ) ; numClonedBlock += Num ; Num += serialPatternMatch ( * HeadMBB -> succ_begin ( ) ) ; Num += serialPatternMatch ( * std :: next ( HeadMBB -> succ_begin ( ) ) ) ; Num += ifPatternMatch ( HeadMBB ) ; assert ( Num > <NUM_LIT> ) ; break ; } DEBUG ( dbgs ( ) << <STR_LIT> ; ) ;

DownBlk = ( DownBlk -> succ_size ( ) == <NUM_LIT> ) ? ( * DownBlk -> succ_begin ( ) ) : nullptr ;


<s> int CC = ( int ) MI -> getOperand ( opNum ) . getImm ( ) ;

O << <ISA_LIT>CondCodeToString ( ( <STR_LIT> ) CC ) ;


<s> int size = <NUM_LIT> ; for ( unsigned long i = <NUM_LIT> ; i < m_loopInfoVec . size ( ) ; i ++ ) { if ( m_loopInfoVec [ i ] . is_Valid ( ) ) {

loopTemp [ m_loopInfoVec [ i ] . get_DIM ( ) ] = m_loopInfoVec [ i ] ;


<s> const TargetRegisterClass * RC ; if ( HasSPE ) RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; else RC = ( ( VT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ) ; Register DestReg = createResultReg ( RC ) ; CodeModel :: Model CModel = TM . getCodeModel ( ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( * FuncInfo . MF ) , MachineMemOperand :: MOLoad , ( VT == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> , Alignment ) ; unsigned Opc ; if ( HasSPE ) Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; else Opc = ( ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ; Register TmpReg = createResultReg ( & <STR_LIT> ) ; <ISA_LIT>FuncInfo -> setUsesTOCBasePtr ( ) ; if ( CModel == CodeModel :: Small ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addConstantPoolIndex ( Idx ) . addReg ( <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg ) . addReg ( <STR_LIT> ) . addConstantPoolIndex ( Idx ) ; if ( CModel == CodeModel :: Large ) { Register TmpReg2 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , TmpReg2 ) . addConstantPoolIndex ( Idx ) . addReg ( TmpReg ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addImm ( <NUM_LIT> ) . addReg ( TmpReg2 ) ; } else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , DestReg ) . addConstantPoolIndex ( Idx , <NUM_LIT> , <STR_LIT> ) . addReg ( TmpReg ) . addMemOperand ( MMO ) ; }


<s> if ( Loop && MBB == Loop -> getHeader ( ) ) {


<s> SDValue ReturnAddress ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; ReturnAddress = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } else { Register Reg = MF . addLiveIn ( <STR_LIT> , & <STR_LIT> ) ; ReturnAddress = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , Reg , VT ) ; } SDNode * St ; if ( Subtarget -> hasPAuth ( ) ) { St = DAG . getMachineNode ( <STR_LIT> , DL , VT , ReturnAddress ) ; } else {

SDValue Chain = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , ReturnAddress ) ;


<s> return __aarch64_vdup_laneq_s16 ( __a , __b ) ;


<s> assert ( IA . Id != <NUM_LIT> && RA . Id != <NUM_LIT> ) ; uint16_t Flags = RA . Addr -> getFlags ( ) | NodeAttrs :: Shadow ; auto IsShadow = [ Flags ] ( NodeAddr < RefNode * > TA ) -> bool { return TA . Addr -> getFlags ( ) == Flags ; } ; return locateNextRef ( IA , RA , IsShadow ) . second ;


<s> else if ( trySkipId ( <STR_LIT> ) ) CPolOff = <STR_LIT> :: DLC ; else if ( trySkipId ( <STR_LIT> ) ) CPolOn = <STR_LIT> :: SCC ; else if ( trySkipId ( <STR_LIT> ) ) CPolOff = <STR_LIT> :: SCC ; else return MatchOperand_NoMatch ; if ( ! isGFX10Plus ( ) && ( ( CPolOn | CPolOff ) & <STR_LIT> :: DLC ) ) { Error ( S , <STR_LIT> ) ; return MatchOperand_ParseFail ; } if ( ! isGFX90A ( ) && ( ( CPolOn | CPolOff ) & <STR_LIT> :: SCC ) ) { Error ( S , <STR_LIT> ) ;


<s> unsigned char SH = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char MB = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned char ME = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( SH <= <NUM_LIT> && MB == <NUM_LIT> && ME == ( <NUM_LIT> - SH ) ) { O << <STR_LIT> ; FoundMnemonic = true ; } if ( SH <= <NUM_LIT> && MB == ( <NUM_LIT> - SH ) && ME == <NUM_LIT> ) { O << <STR_LIT> ; FoundMnemonic = true ; SH = <NUM_LIT> - SH ; } if ( FoundMnemonic ) { printOperand ( MI , <NUM_LIT> ) ; O << <STR_LIT> ; printOperand ( MI , <NUM_LIT> ) ; O << <STR_LIT> << ( unsigned int ) SH << '\n' ;


<s> case V8SImode : case V4SImode : case V8SFmode : case V4SFmode : vec_mode = mode ; mode = GET_MODE_INNER ( mode ) ; imode = SImode ; lo = <NUM_LIT> , hi = lo < <NUM_LIT> ; break ; case V8DImode : case V4DImode : case V2DImode : case V8DFmode : case V4DFmode : case V2DFmode : vec_mode = mode ; mode = GET_MODE_INNER ( mode ) ; imode = DImode ; if ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> ) lo = ( HOST_WIDE_INT ) <NUM_LIT> << shift , hi = - <NUM_LIT> ; else lo = <NUM_LIT> , hi = ( HOST_WIDE_INT ) <NUM_LIT> << ( shift - HOST_BITS_PER_WIDE_INT ) ; break ; case TImode : case TFmode : vec_mode = VOIDmode ; if ( HOST_BITS_PER_WIDE_INT >= <NUM_LIT> ) {


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC -> hasSuperClassEq ( & <STR_LIT> ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) ;

else BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) ;


<s> if ( isLoad ) { status = DecodeRD ( MI , rd , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; } status = DecodeIntRegsRegisterClass ( MI , rs1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; if ( isImm ) MI . addOperand ( MCOperand :: createImm ( simm13 ) ) ; else { status = DecodeIntRegsRegisterClass ( MI , rs2 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ; }

if ( hasAsi ) MI . addOperand ( MCOperand :: createImm ( asi ) ) ;


<s> temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; temp . val [ <NUM_LIT> ] = vcombine_p16 ( val . val [ <NUM_LIT> ] , vcreate_p16 ( __AARCH64_UINT64_C ( <NUM_LIT> ) ) ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregciv8hi ( __o , ( int16x8_t ) temp . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {


<s> MCSym = MBB -> getSymbol ( ) ; } else { assert ( ACPV -> isExtSymbol ( ) && <STR_LIT> ) ; auto Sym = cast < <ISA_LIT>ConstantPoolSymbol > ( ACPV ) -> getSymbol ( ) ; MCSym = GetExternalSymbolSymbol ( Sym ) ; } const MCExpr * Expr = MCSymbolRefExpr :: create ( MCSym , getModifierVariantKind ( ACPV -> getModifier ( ) ) , OutContext ) ; if ( ACPV -> getPCAdjustment ( ) ) { MCSymbol * PCLabel = getPICLabel ( DL . getPrivateGlobalPrefix ( ) , getFunctionNumber ( ) , ACPV -> getLabelId ( ) , OutContext ) ; const MCExpr * PCRelExpr = MCSymbolRefExpr :: create ( PCLabel , OutContext ) ; PCRelExpr = MCBinaryExpr :: createAdd ( PCRelExpr , MCConstantExpr :: create ( ACPV -> getPCAdjustment ( ) , OutContext ) , OutContext ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) { MCSymbol * DotSym = OutContext . createTempSymbol ( ) ;


<s> raw_svector_ostream OS ( Str ) ; printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ;


<s> case 'x' : return POINTER_X_REGS ; case 'y' : return POINTER_Y_REGS ; case 'z' : return POINTER_Z_REGS ; case 'q' : return STACK_REG ; default : break ;


<s> } } if ( Parser . getTok ( ) . getKind ( ) != AsmToken :: Identifier || Parser . getLexer ( ) . peekTok ( ) . getKind ( ) != AsmToken :: LParen ) { return true ; } StringRef ModifierName = Parser . getTok ( ) . getString ( ) ; ModifierKind = <ISA_LIT>MCExpr :: getKindByName ( ModifierName . str ( ) . c_str ( ) ) ; if ( ModifierKind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { Parser . Lex ( ) ; Parser . Lex ( ) ; } else { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } MCExpr const * InnerExpression ;

if ( getParser ( ) . parseExpression ( InnerExpression ) ) return true ;


<s> OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetKnownWindowsMSVC ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( SymbolName ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( Subtarget -> isTargetCOFF ( ) ) { std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; for ( const auto & Function : M ) if ( Function . hasDLLExportStorageClass ( ) ) DLLExportedFns . push_back ( getSymbol ( & Function ) ) ; for ( const auto & Global : M . globals ( ) ) if ( Global . hasDLLExportStorageClass ( ) ) DLLExportedGlobals . push_back ( getSymbol ( & Global ) ) ; for ( const auto & Alias : M . aliases ( ) ) { if ( ! Alias . hasDLLExportStorageClass ( ) ) continue ; if ( Alias . getType ( ) -> getElementType ( ) -> isFunctionTy ( ) ) DLLExportedFns . push_back ( getSymbol ( & Alias ) ) ; else DLLExportedGlobals . push_back ( getSymbol ( & Alias ) ) ; } if ( ! DLLExportedGlobals . empty ( ) || ! DLLExportedFns . empty ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; for ( auto & Symbol : DLLExportedGlobals ) GenerateExportDirective ( Symbol , true ) ; for ( auto & Symbol : DLLExportedFns ) GenerateExportDirective ( Symbol , false ) ; }


<s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> <ISA_LIT>RegNumbering ( ) : MachineFunctionPass ( ID ) {


<s> void printDstIdx64 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {


<s> return ( ( qword ) ( vec_andc ( vec_sr ( ( vec_ushort8 ) ( a ) , neg_b ) , mask ) ) ) ;


<s> if ( InstrInfo . hasAVLReg ( ) && InstrInfo . AVLReg == <STR_LIT> ) { if ( SEW == InstrInfo . SEW ) return true ; } if ( ! hasSameAVL ( InstrInfo ) ) return false ; if ( hasSameVTYPE ( InstrInfo ) ) return true ; if ( InstrInfo . MaskRegOp && hasSameVLMAX ( InstrInfo ) && TailAgnostic == InstrInfo . TailAgnostic && MaskAgnostic == InstrInfo . MaskAgnostic ) return true ;

if ( InstrInfo . StoreOp && VLMul == InstrInfo . VLMul && SEW == InstrInfo . SEW ) return true ;


<s> const TargetInstrDesc & UseTID = get ( UseNode -> getMachineOpcode ( ) ) ; const MachineSDNode * DefMN = dyn_cast < MachineSDNode > ( DefNode ) ; unsigned DefAlign = ! DefMN -> memoperands_empty ( ) ? ( * DefMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; const MachineSDNode * UseMN = dyn_cast < MachineSDNode > ( UseNode ) ; unsigned UseAlign = ! UseMN -> memoperands_empty ( ) ? ( * UseMN -> memoperands_begin ( ) ) -> getAlignment ( ) : <NUM_LIT> ; int Latency = getOperandLatency ( ItinData , DefTID , DefIdx , DefAlign , UseTID , UseIdx , UseAlign ) ; if ( Latency > <NUM_LIT> && ( Subtarget . isCortexA8 ( ) || Subtarget . isCortexA9 ( ) ) ) { switch ( DefTID . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : { unsigned ShOpVal = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; unsigned ShImm = <STR_LIT> ( ShOpVal ) ; if ( ShImm == <NUM_LIT> || ( ShImm == <NUM_LIT> && <STR_LIT> ( ShOpVal ) == <STR_LIT> ) ) -- Latency ; break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned ShAmt = cast < ConstantSDNode > ( DefNode -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( ShAmt == <NUM_LIT> || ShAmt == <NUM_LIT> ) -- Latency ; break ;


<s> uint64_t <ISA_LIT>MCCodeEmitter :: getBranchTargetOpValue ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ;

Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


<s> return __builtin_mve_vcaddq_rot270_sv16qi ( __a , __b ) ;


SplitArgs . emplace_back ( OrigArg . Regs [ i ] , SplitTy , OrigArg . Flags [ <NUM_LIT> ] , OrigArg . IsFixed ) ;


<s> Mangler & Mang ; AsmPrinter & Printer ; public : <ISA_LIT>MCInstLower ( MCContext & ctx , Mangler & mang , AsmPrinter & printer ) : Ctx ( ctx ) , Mang ( mang ) , Printer ( printer ) { } void Lower ( const MachineInstr * MI , MCInst & OutMI ) const ; MCOperand LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const ; MCSymbol * GetGlobalAddressSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetExternalSymbolSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetJumpTableSymbol ( const MachineOperand & MO ) const ; MCSymbol * GetConstantPoolIndexSymbol ( const MachineOperand & MO ) const ;


<s> PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ; initializeGlobalISel ( PR ) ;

initialize<ISA_LIT>ModuleAnalysisPass ( PR ) ;


<s> if ( reg < <STR_LIT> || reg > <STR_LIT> ) return false ; if ( OrMI -> getOpcode ( ) == <STR_LIT> && OrMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && OrMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> ) return false ; if ( OrMI -> getOpcode ( ) == <STR_LIT> && OrMI -> getOperand ( <NUM_LIT> ) . getReg ( ) != <STR_LIT> && ( ! OrMI -> getOperand ( <NUM_LIT> ) . isImm ( ) || OrMI -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) ) return false ; RestoreMI -> eraseFromParent ( ) ;

OrMI -> setDesc ( TII -> get ( ( OrMI -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ) ) ;


<s> if ( ThreeOp ) return MIB . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addImm ( Offset ) ; return MIB . addFrameIndex ( FI ) . addImm ( Offset ) ;


<s> return ( val % <NUM_LIT> == <NUM_LIT> && isImmUs ( val / <NUM_LIT> ) ) ;


<s> this -> OrigTy = cast < IntegerType > ( OrigTy ) ; assert ( OrigTy -> getPrimitiveSizeInBits ( ) < ExtTy -> getPrimitiveSizeInBits ( ) && <STR_LIT> ) ; this -> Visited = & Visited ; this -> Sources = & Sources ; this -> Sinks = & Sinks ; this -> SafeToPromote = & SafeToPromote ; for ( auto * I : Sinks ) { if ( auto * Call = dyn_cast < CallInst > ( I ) ) { for ( unsigned i = <NUM_LIT> ; i < Call -> getNumArgOperands ( ) ; ++ i ) { Value * Arg = Call -> getArgOperand ( i ) ;

TruncTysMap [ Call ] . push_back ( Arg -> getType ( ) ) ;