<s> <STR_LIT> <ISA_LIT>TargetLowering :: getSetCCResultType ( EVT VT ) const {

return ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) ? VT . getSimpleVT ( ) . SimpleTy :


<s> else if ( TARGET_EMBEDDED_DATA ) { mergeable_constant_section ( mode , align , <NUM_LIT> ) ; } else { if ( GET_MODE_SIZE ( mode ) <= ( unsigned ) mips_section_threshold && mips_section_threshold > <NUM_LIT> ) named_section ( <NUM_LIT> , <STR_LIT> , <NUM_LIT> ) ;

else if ( flag_pic && symbolic_expression_p ( x ) ) named_section ( <NUM_LIT> , <STR_LIT> , <NUM_LIT> ) ;


<s> } StoreSDNode * Store = cast < StoreSDNode > ( Op ) ; if ( Store -> getAddressSpace ( ) == <STR_LIT> && Store -> getValue ( ) . getValueType ( ) . isVector ( ) ) { return SplitVectorStore ( Op , DAG ) ; } return SDValue ( ) ;


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterAsmParser < <ISA_LIT>_32ATTAsmParser > X ( The<ISA_LIT>_32Target ) ;

RegisterAsmParser < <ISA_LIT>_64ATTAsmParser > Y ( The<ISA_LIT>_64Target ) ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS ) const { CodeModel :: Model M = getTargetMachine ( ) . getCodeModel ( ) ; Reloc :: Model R = getTargetMachine ( ) . getRelocationModel ( ) ; if ( ! <STR_LIT> ( AM . BaseOffs , M , AM . BaseGV != nullptr ) ) return false ; if ( AM . BaseGV ) { unsigned GVFlags = Subtarget . ClassifyGlobalReference ( AM . BaseGV , getTargetMachine ( ) ) ; if ( isGlobalStubReference ( GVFlags ) ) return false ; if ( AM . HasBaseReg && isGlobalRelativeToPICBase ( GVFlags ) ) return false ; if ( ( M != CodeModel :: Small || R != Reloc :: Static ) && Subtarget . is64Bit ( ) && ( AM . BaseOffs || AM . Scale > <NUM_LIT> ) ) return false ; } switch ( AM . Scale ) { case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : break ;


<s> if ( ! VF . isScalable ( ) ) return true ; Type * Ty = RdxDesc . getRecurrenceType ( ) ; if ( ! isLegalElementTypeForRVV ( Ty ) ) return false ; switch ( RdxDesc . getRecurrenceKind ( ) ) { case RecurKind :: Add :


<s> { <STR_LIT> , winnt_d_handle_target_object_format } , { NULL , NULL } , } ;

d_add_target_info_handlers ( handlers ) ;


<s> if ( ST -> isCortexA57 ( ) ) return <NUM_LIT> ; return <NUM_LIT> ;


Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( Fixup ) , MI . getLoc ( ) ) ) ;


<s> unsigned Base = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DecodeGPRMM16RegisterClass ( Inst , Reg , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DecodeGPRMM16ZeroRegisterClass ( Inst , Reg , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; break ; } if ( DecodeGPRMM16RegisterClass ( Inst , Base , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : if ( Offset == <NUM_LIT> ) Inst . addOperand ( MCOperand :: createImm ( - <NUM_LIT> ) ) ; else Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; break ;


<s> int * regs_ever_clobbered = ( int * ) data ; unsigned int i , regno ; enum machine_mode mode = GET_MODE ( setreg ) ; if ( GET_CODE ( setreg ) == SUBREG ) { rtx inner = SUBREG_REG ( setreg ) ;

if ( ! GENERAL_REG_P ( inner ) ) return ;


<s> return for_each_rtx ( & PATTERN ( insn ) , find_lo_sum_using_gp , NULL ) > <NUM_LIT> ;


<s> return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ;


<s> bool isUncondLoad ( const MachineInstr * MI , int & fi ) const {

if ( ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == TgtReg && ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> && MI -> getOperand ( <NUM_LIT> ) . isFI ( ) ) {


<s> unsigned ElemNum = BO . getType ( ) -> getVectorNumElements ( ) ; if ( ! isPowerOf2_32 ( ElemNum ) ) return false ; unsigned ElemNumToReduce = ElemNum ; SmallVector < const User * , <NUM_LIT> > UsersToVisit { & BO } ; SmallPtrSet < const User * , <NUM_LIT> > Visited ; bool ReduxExtracted = false ; while ( ! UsersToVisit . empty ( ) ) { auto User = UsersToVisit . back ( ) ; UsersToVisit . pop_back ( ) ; if ( ! Visited . insert ( User ) . second ) continue ; for ( const auto * U : User -> users ( ) ) { auto * Inst = dyn_cast < Instruction > ( U ) ; if ( ! Inst ) return false ; if ( Inst -> getOpcode ( ) == Opcode || isa < PHINode > ( U ) ) { if ( auto * FPOp = dyn_cast < FPMathOperator > ( Inst ) ) if ( ! isa < PHINode > ( FPOp ) && ! FPOp -> getFastMathFlags ( ) . isFast ( ) ) return false ; UsersToVisit . push_back ( U ) ;

} else if ( auto * ShufInst = dyn_cast < ShuffleVectorInst > ( U ) ) {


<s> if ( ! isTypeLegal ( I -> getType ( ) , DestVT ) || DestVT . isVector ( ) ) return false ; assert ( ( DestVT == <STR_LIT> || DestVT == <STR_LIT> ) && <STR_LIT> ) ; unsigned SrcReg = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg == <NUM_LIT> ) return false ; EVT SrcVT = TLI . getValueType ( I -> getOperand ( <NUM_LIT> ) -> getType ( ) , true ) ; if ( SrcVT == <STR_LIT> || SrcVT == <STR_LIT> || SrcVT == <STR_LIT> ) { SrcReg = EmitIntExt ( SrcVT . getSimpleVT ( ) , SrcReg , <STR_LIT> , ! Signed ) ; if ( SrcReg == <NUM_LIT> ) return false ; } MRI . constrainRegClass ( SrcReg , SrcVT == <STR_LIT> ? & <STR_LIT> : & <STR_LIT> ) ; unsigned Opc ; if ( SrcVT == <STR_LIT> ) { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { if ( Signed ) Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; else Opc = ( DestVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( DestVT ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> return MatchOperand_ParseFail ; } Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , Imm , S , <ISA_LIT>Operand :: ImmTyEndpgm ) ) ;


<s> SlotIndex UseIdx = LIS -> getInstructionIndex ( Use ) ; SlotIndex DefIdx ; if ( Reg . isVirtual ( ) ) { if ( ! LIS -> hasInterval ( Reg ) ) return nullptr ; LiveInterval & LI = LIS -> getInterval ( Reg ) ; LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask ( SubReg ) : MRI . getMaxLaneMaskForVReg ( Reg ) ; VNInfo * V = nullptr ; if ( LI . hasSubRanges ( ) ) { for ( auto & S : LI . subranges ( ) ) { if ( ( S . LaneMask & SubLanes ) == SubLanes ) { V = S . getVNInfoAt ( UseIdx ) ; break ; } }


<s> static __inline qword si_andhi ( qword a , signed short b ) { return ( ( qword ) ( vec_and ( ( vec_short8 ) ( a ) , vec_splat ( ( vec_short8 ) ( si_from_short ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> MCELFStreamer * create<ISA_LIT>NaClELFStreamer ( MCContext & Context , MCAsmBackend & TAB , raw_ostream & OS , MCCodeEmitter * Emitter , const MCSubtargetInfo & STI , bool RelaxAll , bool NoExecStack ) { <ISA_LIT>NaClELFStreamer * S = new <ISA_LIT>NaClELFStreamer ( Context , TAB , OS , Emitter , STI ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; if ( NoExecStack ) S -> getAssembler ( ) . setNoExecStack ( true ) ; S -> EmitBundleAlignMode ( MIPS_NACL_BUNDLE_ALIGN ) ;


<s> MinSubfunctionAlignment = PST -> getMinSubfunctionAlignment ( ) . value ( ) ;


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitINSERT_DF_VIDX ( MachineInstr * MI , MachineBasicBlock * BB , unsigned EltSizeInBytes , bool IsFP ) const { return BB ;


<s> int imm3 = MI . getOperand ( imm3_pos ) . getImm ( ) ; if ( imm2 + imm3 <= <NUM_LIT> ) { MachineInstrBuilder newMI = BuildMI ( * BB , MI , DL , TII -> get ( unsign ? <STR_LIT> : <STR_LIT> ) ) ; newMI . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; newMI . addOperand ( MI . getOperand ( src1_pos ) ) ; newMI . addImm ( <NUM_LIT> - imm2 - imm3 ) ; newMI . addImm ( imm3 ) ; } else { MachineInstrBuilder newMI = BuildMI ( * BB , MI , DL , TII -> get ( <STR_LIT> ) ) ;


<s> con += <NUM_LIT> ; if ( strchr ( con , ',' ) != NULL ) { error_at ( loc , <STR_LIT> ) ; continue ; } bool invert = false ; if ( con [ <NUM_LIT> ] == 'n' ) invert = true , con ++ ; machine_mode mode = CCmode ; rtx_code code = UNKNOWN ; switch ( con [ <NUM_LIT> ] ) { case 'a' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCAmode , code = EQ ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCCmode , code = NE ; break ; case 'b' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCCmode , code = EQ ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCAmode , code = NE ; break ; case 'c' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCCmode , code = EQ ; break ; case 'e' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCZmode , code = EQ ; break ; case 'g' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = GT ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = GE ; break ; case 'l' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = LT ; else if ( con [ <NUM_LIT> ] == 'e' && con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCGCmode , code = LE ; break ; case 'o' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCOmode , code = EQ ; break ; case 'p' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCPmode , code = EQ ; break ; case 's' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCSmode , code = EQ ; break ; case 'z' : if ( con [ <NUM_LIT> ] == <NUM_LIT> ) mode = CCZmode , code = EQ ; break ; } if ( code == UNKNOWN ) { error_at ( loc , <STR_LIT> , constraints [ i ] ) ; continue ; } if ( invert ) code = reverse_condition ( code ) ; rtx dest = outputs [ i ] ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGLOBAL_OFFSET_TABLE ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetELF ( ) && <STR_LIT> ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createPICLabelUId ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDLoc dl ( Op ) ; unsigned PCAdj = Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolSymbol :: Create ( * DAG . getContext ( ) , <STR_LIT> , <ISA_LIT>PCLabelIndex , PCAdj ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;

SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( ) , false , false , false , <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Inst . getFlag ( MachineInstr :: MIFlag :: FmReassoc ) && Inst . getFlag ( MachineInstr :: MIFlag :: FmNsz ) ; case <STR_LIT> :


<s> int SchedClass = <ISA_LIT>MCInstrInfo :: getDesc ( MCII , MCI ) . getSchedClass ( ) ; unsigned Slots = <NUM_LIT> ; for ( unsigned Stage = II [ SchedClass ] . FirstStage + <NUM_LIT> ; Stage < II [ SchedClass ] . LastStage ; ++ Stage ) { unsigned Units = ( Stage + <ISA_LIT>Stages ) -> getUnits ( ) ; if ( Units > <ISA_LIT>GetLastSlot ( ) ) break ; Slots |= Units ;


<s> case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {

return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> case ADDRESS_REG_UXTW : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM , addr . shift ) ; return ; case ADDRESS_REG_SXTW : if ( addr . shift == <NUM_LIT> ) asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM ) ; else asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , REGNO ( addr . offset ) - R0_REGNUM , addr . shift ) ; return ; case ADDRESS_REG_WB : switch ( GET_CODE ( x ) ) { case PRE_INC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , GET_MODE_SIZE ( mode ) ) ; return ; case POST_INC : asm_fprintf ( f , <STR_LIT> , reg_names [ REGNO ( addr . base ) ] , GET_MODE_SIZE ( mode ) ) ; return ;


<s> std :: string LowerCase = Parser . getTok ( ) . getIdentifier ( ) . lower ( ) ; RefKind = StringSwitch < <ISA_LIT>MCExpr :: VariantKind > ( LowerCase ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G3 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G2_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_S ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_ABS_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_DTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G2 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G1_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_HI12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOT_LO12 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_PAGE ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_LO12_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G1 ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_GOTTPREL_G0_NC ) . Case ( <STR_LIT> , <ISA_LIT>MCExpr :: VK_TLSDESC_PAGE ) . Default ( <ISA_LIT>MCExpr :: VK_INVALID ) ; if ( RefKind == <ISA_LIT>MCExpr :: VK_INVALID ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Parser . Lex ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Colon ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; }


<s> unsigned getThumbBRTargetOpValue ( const MachineInstr & MI , unsigned Op ) const {


<s> AU . addPreserved < LiveVariables > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ;

AU . addPreserved < MachineLoopInfo > ( ) ;


<s> decl = NULL ; } if ( ! TARGET_64BIT && align == <NUM_LIT> && ix86_preferred_stack_boundary < <NUM_LIT> && ( mode == DImode || ( type && TYPE_MODE ( type ) == DImode ) ) && ( ! type || ! TYPE_USER_ALIGN ( type ) ) && ( ! decl || ! DECL_USER_ALIGN ( decl ) ) ) align = <NUM_LIT> ; if ( ! type ) { if ( mode == XFmode && align < GET_MODE_ALIGNMENT ( DFmode ) ) align = GET_MODE_ALIGNMENT ( DFmode ) ; return align ; } if ( TARGET_IAMCU ) return align ; if ( TARGET_64BIT && optimize_function_for_speed_p ( cfun ) && TARGET_SSE ) { if ( AGGREGATE_TYPE_P ( type ) && ( va_list_type_node == NULL_TREE || ( TYPE_MAIN_VARIANT ( type ) != TYPE_MAIN_VARIANT ( va_list_type_node ) ) ) && TYPE_SIZE ( type ) && TREE_CODE ( TYPE_SIZE ( type ) ) == INTEGER_CST && wi :: geu_p ( TYPE_SIZE ( type ) , <NUM_LIT> ) && align < <NUM_LIT> ) return <NUM_LIT> ; } if ( TREE_CODE ( type ) == ARRAY_TYPE ) { if ( TYPE_MODE ( TREE_TYPE ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( TYPE_MODE ( TREE_TYPE ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) {

if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ;


<s> default : return SDValue ( ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerDSPIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return lowerMSABinaryIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return lowerMSABranchIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerMSABranchIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return lowerMSABranchIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : return lowerMSABranchIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return lowerMSABinaryIntr ( Op , DAG , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return lowerMSABinaryIntr ( Op , DAG , <STR_LIT> ) ;


<s> result . set_src = NULL_RTX ; if ( ! REG_P ( reg ) || insn == NULL_RTX ) return result ; for ( rtx_insn * i = stepfunc ( insn ) ; i != NULL_RTX ; i = stepfunc ( i ) ) { if ( BARRIER_P ( i ) ) break ; if ( ! INSN_P ( i ) || DEBUG_INSN_P ( i ) ) continue ; if ( reg_set_p ( reg , i ) ) { if ( CALL_P ( i ) ) break ; result . insn = i ; result . set_rtx = set_of ( reg , i ) ; if ( result . set_rtx == NULL_RTX || GET_CODE ( result . set_rtx ) != SET ) break ; result . set_src = XEXP ( result . set_rtx , <NUM_LIT> ) ; if ( ignore_reg_reg_copies && REG_P ( result . set_src ) ) { reg = result . set_src ; continue ; }

if ( ignore_reg_reg_copies && SUBREG_P ( result . set_src ) && REG_P ( SUBREG_REG ( result . set_src ) ) ) {


<s> unsigned getNumFixupKinds ( ) const { return <STR_LIT> ;


<s> void <ISA_LIT>MCAsmStreamer :: EmitThumbFunc ( MCSymbol * Func ) {


<s> Ops . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; for ( const MachineOperand & MO : make_range ( MI . operands_begin ( ) + MI . getDesc ( ) . getNumDefs ( ) + <NUM_LIT> , MI . operands_begin ( ) + MI . getNumExplicitOperands ( ) ) ) Ops . push_back ( MO ) ; Ops . push_back ( MI . getOperand ( MI . getDesc ( ) . getNumDefs ( ) ) ) ; while ( MI . getNumOperands ( ) > MI . getDesc ( ) . getNumDefs ( ) ) MI . RemoveOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) ; for ( const MachineOperand & MO : Ops ) MI . addOperand ( MO ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; Changed = true ; } }


<s> else llvm_unreachable ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } StringRef IDVal = Parser . getTok ( ) . getIdentifier ( ) ; if ( IDVal == <STR_LIT> ) { RefKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO16 ; } else if ( IDVal == <STR_LIT> ) { RefKind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI16 ; } else { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return true ; } Parser . Lex ( ) ;

if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) {


<s> if ( isVectorPredicated ( & MI ) ) { if ( MI . mayLoad ( ) ) FalseLanesZero . insert ( & MI ) ; Predicated . insert ( & MI ) ; continue ; } if ( MI . getNumDefs ( ) == <NUM_LIT> ) continue ; if ( ! producesFalseLanesZero ( MI , QPRs , RDA , FalseLanesZero ) ) { if ( retainsPreviousHalfElement ( MI ) || isHorizontalReduction ( MI ) ) return false ; FalseLanesUnknown . insert ( & MI ) ; } else if ( ! isHorizontalReduction ( MI ) ) FalseLanesZero . insert ( & MI ) ; } auto HasPredicatedUsers = [ this ] ( MachineInstr * MI , const MachineOperand & MO , SmallPtrSetImpl < MachineInstr * > & Predicated ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > Uses ; RDA . getGlobalUses ( MI , MO . getReg ( ) , Uses ) ; for ( auto * Use : Uses ) { if ( Use != MI && ! Predicated . count ( Use ) ) return false ; }


<s> EXECUTE_IF_SET_IN_BITMAP ( insns , <NUM_LIT> , id , bi ) { rtx_insn * insn = DF_INSN_UID_GET ( id ) -> insn ; convert_insn_common ( insn ) ; convert_insn ( insn ) ; converted_insns ++ ;


<s> Clamp = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Omod = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; return SelectVOP3Mods ( In , Src , SrcMods ) ;


<s> uint32_t Binary = <NUM_LIT> ; const MachineOperand & MO = MI . getOperand ( Op ) ; uint32_t Reg = getMachineOpValue ( MI , MO ) ; Binary |= ( Reg << <NUM_LIT> ) ; if ( MO . isReg ( ) ) { const MachineOperand & MO1 = MI . getOperand ( Op + <NUM_LIT> ) ; if ( uint32_t ImmOffs = <STR_LIT> ( MO1 . getImm ( ) ) ) { if ( <STR_LIT> ( MO1 . getImm ( ) ) == <STR_LIT> ) Binary |= <NUM_LIT> << <NUM_LIT> ; Binary |= ImmOffs & <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerDarwinGlobalTLSAddress ( SDValue Op , SelectionDAG & DAG ) const { assert ( Subtarget -> isTargetDarwin ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; MVT PtrVT = getPointerTy ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; SDValue TLVPAddr = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , <STR_LIT> ) ; SDValue DescAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLVPAddr ) ; SDValue Chain = DAG . getEntryNode ( ) ; SDValue FuncTLVGet = DAG . getLoad ( <STR_LIT> , DL , Chain , DescAddr , MachinePointerInfo :: getGOT ( ) , false , true , true , <NUM_LIT> ) ; Chain = FuncTLVGet . getValue ( <NUM_LIT> ) ;

MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ;


<s> EVT PtrVT = getPointerTy ( ) ; SDLoc dl ( Op ) ; switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerVAARG ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerBR_JT ( Op , DAG ) ; case <STR_LIT> : { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ) ; }


<s> } if ( PostInc ) { int64_t Inc = Load ? MI -> getOperand ( <NUM_LIT> ) . getImm ( ) : MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineOperand & UpdOp = Load ? MI -> getOperand ( <NUM_LIT> ) : MI -> getOperand ( <NUM_LIT> ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( UpdOp . getReg ( ) ) ; unsigned NewR = MRI -> createVirtualRegister ( RC ) ; assert ( ! UpdOp . getSubReg ( ) && <STR_LIT> ) ; BuildMI ( B , MI , DL , TII -> get ( <STR_LIT> ) , NewR ) . addReg ( AdrOp . getReg ( ) , RSA ) . addImm ( Inc ) ; MRI -> replaceRegWith ( UpdOp . getReg ( ) , NewR ) ; } MachineFunction & MF = * B . getParent ( ) ; for ( auto & MO : MI -> memoperands ( ) ) { const MachinePointerInfo & Ptr = MO -> getPointerInfo ( ) ; unsigned F = MO -> getFlags ( ) ; int A = MO -> getAlignment ( ) ; auto * Tmp1 = MF . getMachineMemOperand ( Ptr , F , <NUM_LIT> , A ) ; LowI -> addMemOperand ( MF , Tmp1 ) ;

auto * Tmp2 = MF . getMachineMemOperand ( Ptr , F , <NUM_LIT> , std :: min ( A , <NUM_LIT> ) ) ;


<s> MachineBasicBlock * WaterBB = * IP ; unsigned Growth ; if ( WaterIsInRange ( UserOffset , WaterBB , U , Growth ) && ( WaterBB -> getNumber ( ) < U . HighWaterMark -> getNumber ( ) || NewWaterList . count ( WaterBB ) ) && Growth < BestGrowth ) { BestGrowth = Growth ; WaterIter = IP ; DEBUG ( dbgs ( ) << <STR_LIT> << WaterBB -> getNumber ( ) << <STR_LIT> << Growth << '\n' ) ; if ( BestGrowth == <NUM_LIT> ) return true ; } if ( IP == B ) break ;


<s> if ( ! HasVCTP || MI . getOpcode ( ) != <STR_LIT> ) continue ; MachineInstrBuilder MIBuilder = BuildMI ( MBB , & MI , MI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; ( void ) MIBuilder ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI . dump ( ) ; dbgs ( ) << <STR_LIT> ; MIBuilder . getInstr ( ) -> dump ( ) ) ; DeadInstructions . push_back ( & MI ) ;


<s> <ISA_LIT>SimplifyAddress ( Addr , VT , UseOffset , IndexReg ) ; bool IsVSFRC = ( ResultReg != <NUM_LIT> ) && isVSFRCRegister ( ResultReg ) ; if ( IsVSFRC && ( Opc == <STR_LIT> ) && ( Addr . BaseType != Address :: FrameIndexBase ) && UseOffset && ( Addr . Offset == <NUM_LIT> ) ) { UseOffset = false ; } if ( ResultReg == <NUM_LIT> ) ResultReg = createResultReg ( UseRC ) ; if ( Addr . BaseType == Address :: FrameIndexBase ) { if ( IsVSFRC && Opc == <STR_LIT> ) return false ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( Addr . Base . FI , Addr . Offset ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( Addr . Base . FI ) , MFI . getObjectAlignment ( Addr . Base . FI ) ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addFrameIndex ( Addr . Base . FI ) . addMemOperand ( MMO ) ; } else if ( UseOffset ) { if ( IsVSFRC && Opc == <STR_LIT> ) return false ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addImm ( Addr . Offset ) . addReg ( Addr . Base . Reg ) ; } else { switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = IsVSFRC ? <STR_LIT> : <STR_LIT> ; break ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addReg ( Addr . Base . Reg ) . addReg ( IndexReg ) ; }


<s> SDValue Operands [ ] = { StoreVal , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , Node -> getOperand ( <NUM_LIT> + NF ) , SEW , Node -> getOperand ( <NUM_LIT> ) } ; EVT IndexVT = Node -> getOperand ( <NUM_LIT> + NF ) -> getValueType ( <NUM_LIT> ) ; <ISA_LIT>VLMUL IndexLMUL = getLMUL ( IndexVT ) ; unsigned IndexScalarSize = IndexVT . getScalarSizeInBits ( ) ; const <STR_LIT> * P = <STR_LIT> ( IntNo , IndexScalarSize , static_cast < unsigned > ( LMUL ) , static_cast < unsigned > ( IndexLMUL ) ) ; SDNode * Store = CurDAG -> getMachineNode ( P -> Pseudo , DL , Node -> getValueType ( <NUM_LIT> ) , Operands ) ;


<s> if ( IID == <NUM_LIT> ) return false ; uint8_t index = <NUM_LIT> ; Name . consumeInteger ( <NUM_LIT> , index ) ; if ( index >= Prefetches . size ( ) ) Prefetches . resize ( index + <NUM_LIT> ) ; Prefetches [ index ] = { IID , D } ; max_index = std :: max ( max_index , static_cast < int16_t > ( index ) ) ; } } assert ( max_index + <NUM_LIT> >= <NUM_LIT> && <STR_LIT> ) ; assert ( static_cast < size_t > ( max_index + <NUM_LIT> ) == Prefetches . size ( ) && <STR_LIT> <STR_LIT> ) ;


<s> unsigned char VEX_B = <NUM_LIT> ; unsigned char VEX_W = <NUM_LIT> ; unsigned char VEX_5M = <NUM_LIT> ; unsigned char VEX_4V = <NUM_LIT> ; unsigned char VEX_L = <NUM_LIT> ; unsigned char VEX_PP = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) VEX_W = <NUM_LIT> ; if ( ( TSFlags >> <STR_LIT> ) & <STR_LIT> ) VEX_L = <NUM_LIT> ; switch ( TSFlags & <STR_LIT> ) { default : break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; case <STR_LIT> : VEX_PP = <NUM_LIT> ; break ; } switch ( TSFlags & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; case <STR_LIT> : VEX_5M = <NUM_LIT> ; break ; } unsigned NumOps = Desc -> getNumOperands ( ) ; unsigned CurOp = <NUM_LIT> ; if ( NumOps > <NUM_LIT> && Desc -> getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ++ CurOp ; else if ( NumOps > <NUM_LIT> && Desc -> getOperandConstraint ( <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) { assert ( Desc -> getOperandConstraint ( NumOps - <NUM_LIT> , MCOI :: TIED_TO ) == <NUM_LIT> ) ; CurOp += <NUM_LIT> ; } switch ( TSFlags & <STR_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : { if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ; if ( <STR_LIT> ( MI . getOperand ( <STR_LIT> ) . getReg ( ) ) ) VEX_X = <NUM_LIT> ; CurOp = <STR_LIT> ; if ( HasVEX_4V ) VEX_4V = getVEXRegisterEncoding ( MI , CurOp ++ ) ; const MachineOperand & MO = MI . getOperand ( CurOp ) ; if ( MO . isReg ( ) && <STR_LIT> ( MO . getReg ( ) ) ) VEX_R = <NUM_LIT> ; break ; } case <STR_LIT> : if ( <STR_LIT> ( MI . getOperand ( CurOp ) . getReg ( ) ) ) VEX_R = <NUM_LIT> ; CurOp ++ ; if ( HasVEX_4V ) { VEX_4V = getVEXRegisterEncoding ( MI , CurOp ) ; CurOp ++ ; }

if ( <STR_LIT> ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) ) VEX_B = <NUM_LIT> ;


<s> <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; assert ( MFI -> isEntryFunction ( ) ) ; Register ScratchRsrcReg = MFI -> getScratchRSrcReg ( ) ; if ( ! ScratchRsrcReg || ( ! MRI . isPhysRegUsed ( ScratchRsrcReg ) && allStackObjectsAreDead ( MF ) ) ) return Register ( ) ; if ( ST . hasSGPRInitBug ( ) || ScratchRsrcReg != TRI -> reservedPrivateSegmentBufferReg ( MF ) ) return ScratchRsrcReg ; unsigned NumPreloaded = ( MFI -> getNumPreloadedSGPRs ( ) + <NUM_LIT> ) / <NUM_LIT> ; ArrayRef < MCPhysReg > AllSGPR128s = TRI -> getAllSGPR128 ( MF ) ; AllSGPR128s = AllSGPR128s . slice ( std :: min ( static_cast < unsigned > ( AllSGPR128s . size ( ) ) , NumPreloaded ) ) ; Register GITPtrLoReg = MFI -> getGITPtrLoReg ( MF ) ; for ( MCPhysReg Reg : AllSGPR128s ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) && ! TRI -> isSubRegisterEq ( Reg , GITPtrLoReg ) ) { MRI . replaceRegWith ( ScratchRsrcReg , Reg ) ; MFI -> setScratchRSrcReg ( Reg ) ; return Reg ; }


<s> Op -> Imm . Val = Val ; Op -> StartLoc = S ; Op -> EndLoc = E ;


<s> void addu6_0ExtOperands ( MCInst & Inst , unsigned N ) const {


<s> assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex256CompressTable ) && <STR_LIT> ) ; TableChecked . store ( true , std :: memory_order_relaxed ) ; } ArrayRef < <ISA_LIT>EvexToVexCompressTableEntry > Table = ( Desc . TSFlags & <STR_LIT> ) ? makeArrayRef ( <ISA_LIT>EvexToVex256CompressTable ) : makeArrayRef ( <ISA_LIT>EvexToVex128CompressTable ) ; const auto * I = llvm :: lower_bound ( Table , MI . getOpcode ( ) ) ; if ( I == Table . end ( ) || I -> EvexOpcode != MI . getOpcode ( ) ) return false ; unsigned NewOpc = I -> VexOpcode ; if ( usesExtendedRegister ( MI ) ) return false ; if ( ! performCustomAdjustments ( MI , NewOpc , ST ) ) return false ;

MI . setDesc ( TII -> get ( NewOpc ) ) ;


<s> const MCSymbol * AUIPCSymbol = & AUIPCSRE -> getSymbol ( ) ; const auto * DF = dyn_cast_or_null < MCDataFragment > ( AUIPCSymbol -> getFragment ( ) ) ; if ( ! DF ) return nullptr ; uint64_t Offset = AUIPCSymbol -> getOffset ( ) ; if ( DF -> getContents ( ) . size ( ) == Offset ) { DF = dyn_cast_or_null < MCDataFragment > ( DF -> getNextNode ( ) ) ;


<s> if ( target == NULL_RTX || GET_MODE ( target ) != tmode || ! insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ( target , tmode ) ) { target = gen_reg_rtx ( tmode ) ; } for ( n = <NUM_LIT> ; n < n_args ; n ++ ) { tree arg = CALL_EXPR_ARG ( exp , n ) ; rtx op = expand_expr ( arg , NULL_RTX , VOIDmode , EXPAND_NORMAL ) ; machine_mode opmode = GET_MODE ( op ) ; machine_mode mode = insn_data [ icode ] . operand [ n + <NUM_LIT> ] . mode ; if ( ( opmode == SImode || opmode == VOIDmode ) && mode == HImode ) { opmode = HImode ; op = gen_lowpart ( HImode , op ) ; } gcc_assert ( opmode == mode || opmode == VOIDmode ) ; if ( ! insn_data [ icode ] . operand [ n + <NUM_LIT> ] . predicate ( op , mode ) ) op = copy_to_mode_reg ( mode , op ) ; xop [ n ] = op ; } switch ( n_args ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , xop [ <NUM_LIT> ] ) ; break ;

case <NUM_LIT> : pat = GEN_FCN ( icode ) ( target , xop [ <NUM_LIT> ] , xop [ <NUM_LIT> ] ) ; break ;


<s> static unsigned HOST_WIDE_INT rs6000_asan_shadow_offset ( void ) { return ( unsigned HOST_WIDE_INT ) <NUM_LIT> << ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerToTLSInitialExecModel ( GlobalAddressSDNode * GA , SelectionDAG & DAG ) const { SDLoc dl ( GA ) ; int64_t Offset = GA -> getOffset ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue TP = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , <STR_LIT> , PtrVT ) ; bool IsPositionIndependent = isPositionIndependent ( ) ; unsigned char TF = IsPositionIndependent ? <STR_LIT> : <STR_LIT> ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , dl , PtrVT , Offset , TF ) ; SDValue Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , TGA ) ; if ( IsPositionIndependent ) { SDValue GOT = LowerGLOBAL_OFFSET_TABLE ( Sym , DAG ) ;

Sym = DAG . getNode ( <STR_LIT> , dl , PtrVT , GOT , Sym ) ;


<s> It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; } else { It = MBB . insert ( It , BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) . addGlobalAddress ( M . getNamedValue ( MF . getName ( ) ) ) ) ; }


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ;

Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> if ( Subtarget . hasStdExtZbp ( ) ) { if ( auto GREV = combineORToGREV ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GREV ; if ( auto GORC = combineORToGORC ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return GORC ;

if ( auto SHFL = combineORToSHFL ( SDValue ( N , <NUM_LIT> ) , DAG , Subtarget ) ) return SHFL ;


<s> union { vec_uint4 v ; unsigned short s [ <NUM_LIT> ] ; } shmask ; shmask . v = ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ; shmask . s [ ( si_to_uint ( ( qword ) ( vec_add ( ( vec_uint4 ) ( a ) , ( vec_uint4 ) ( b ) ) ) ) >> <NUM_LIT> ) & <NUM_LIT> ] = <NUM_LIT> ; return ( ( qword ) ( shmask . v ) ) ;


<s> static bool isX87ControlInstruction ( MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ; }


<s> Value -= <NUM_LIT> ; Value >>= <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Value = ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; break ; } return Value ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) {

addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;


<s> if ( NumElems != <NUM_LIT> && NumElems != <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < NumElems / <NUM_LIT> ; ++ i ) if ( ! isUndefOrEqual ( N -> getOperand ( i ) , i + NumElems ) ) return false ; for ( unsigned i = NumElems / <NUM_LIT> ; i < NumElems ; ++ i ) if ( ! isUndefOrEqual ( N -> getOperand ( i ) , i ) ) return false ; return true ;


<s> void \ _Jv_RegisterClasses ( void * p __attribute__ ( ( unused ) ) ) {


<s> vld3_f32 ( const float32_t * __a ) { float32x2x3_t ret ; __builtin_aarch64_simd_ci __o ; __o = __builtin_aarch64_ld3v2sf ( ( const __builtin_aarch64_simd_sf * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float32x2_t ) __builtin_aarch64_get_dregciv2sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x2_t ) __builtin_aarch64_get_dregciv2sf ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float32x2_t ) __builtin_aarch64_get_dregciv2sf ( __o , <NUM_LIT> ) ; return ret ;


<s> for ( auto & BB : L -> blocks ( ) ) for ( auto & I : * BB ) { if ( isa < CallInst > ( & I ) || isa < InvokeInst > ( & I ) ) { if ( const Function * F = cast < CallBase > ( I ) . getCalledFunction ( ) ) { if ( isLoweredToCall ( F ) ) HasCall = true ; if ( F -> getIntrinsicID ( ) == <STR_LIT> || F -> getIntrinsicID ( ) == <STR_LIT> ) NumStores ++ ; } else { HasCall = true ; } } if ( isa < StoreInst > ( & I ) ) { Type * MemAccessTy = I . getOperand ( <NUM_LIT> ) -> getType ( ) ; NumStores += getMemoryOpCost ( Instruction :: Store , MemAccessTy , None , <NUM_LIT> , TTI :: TCK_RecipThroughput ) ; }


<s> uint32_t getISAExtensionSetValue ( ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : unsigned Width ; return getMemOpBaseRegImmOfsWidth ( LdSt , BaseReg , Offset , Width , TRI ) ; }


return ( uint16x8_t ) __builtin_aarch64_clzv8hi ( ( int16x8_t ) __a ) ;


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; if ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) OutMI . addOperand ( lowerOperand ( MO ) ) ;


<s> if ( TII -> isALUInstr ( MI . getOpcode ( ) ) ) return true ; if ( TII -> isVector ( MI ) || TII -> isCubeOp ( MI . getOpcode ( ) ) ) return true ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default :


<s> SDValue <ISA_LIT>TargetLowering :: lowerExp ( SDValue Op , SelectionDAG & DAG ) const {

return lowerLibCallBase ( <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , Op , DAG ) ;


<s> IPMConversion ( unsigned xorValue , int64_t addValue , unsigned bit ) : XORValue ( xorValue ) , AddValue ( addValue ) , Bit ( bit ) {


<s> default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>8 ; case FK_Data_2 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>16 ; case FK_Data_4 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>32 ; case FK_Data_8 : return ELF :: R_<ISA_LIT>ARC_DI<ISA_LIT>64 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>30 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WDI<ISA_LIT>19 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_PC10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_WPLT30 ; } } switch ( Fixup . getTargetKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_Data_1 : return ELF :: R_<ISA_LIT>ARC_8 ; case FK_Data_2 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA16 : ELF :: R_<ISA_LIT>ARC_16 ) ; case FK_Data_4 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA32 : ELF :: R_<ISA_LIT>ARC_32 ) ; case FK_Data_8 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA64 : ELF :: R_<ISA_LIT>ARC_64 ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_13 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_LO10 ;

case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_H44 ;


<s> static bool areCFlagsAccessedBetweenInstrs ( MachineBasicBlock :: iterator From , MachineBasicBlock :: iterator To , const TargetRegisterInfo * TRI , const AccessKind AccessToCheck = AK_All ) { if ( To == To -> getParent ( ) -> begin ( ) ) return true ; if ( To -> getParent ( ) != From -> getParent ( ) ) return true ; assert ( std :: find_if ( ++ To . getReverse ( ) , To -> getParent ( ) -> rend ( ) , [ From ] ( MachineInstr & MI ) { return MI . getIterator ( ) == From ; } ) != To -> getParent ( ) -> rend ( ) ) ; for ( const MachineInstr & Instr : instructionsWithoutDebug ( ++ To . getReverse ( ) , From . getReverse ( ) ) ) {

if ( ( ( AccessToCheck & AK_Write ) && Instr . modifiesRegister ( <STR_LIT> , TRI ) ) || ( ( AccessToCheck & AK_Read ) && Instr . readsRegister ( <STR_LIT> , TRI ) ) ) return true ;


<s> void setFunction ( Function & Func ) { F = & Func ;


<s> <ISA_LIT>IntelAsmPrinter ( raw_ostream & O , <ISA_LIT>TargetMachine & TM , const TargetAsmInfo * T , bool F ) : AsmPrinter ( O , TM , T , F ) {


<s> if ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isPICStyleGOT ( ) ) PC = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; else PC = GlobalBaseReg ; BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , PC ) . addImm ( <NUM_LIT> ) ; if ( TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . isPICStyleGOT ( ) ) { BuildMI ( FirstMBB , MBBI , DL , TII -> get ( <STR_LIT> ) , GlobalBaseReg ) . addReg ( PC ) . addExternalSymbol ( <STR_LIT> , <STR_LIT> ) ;


<s> const TargetRegisterClass * SuperRC = ( CI . EltSize == <NUM_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; DebugLoc DL = CI . I -> getDebugLoc ( ) ; unsigned BaseReg = AddrReg -> getReg ( ) ; unsigned BaseRegFlags = <NUM_LIT> ; if ( CI . BaseOff ) { BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BaseRegFlags = RegState :: Kill ; BuildMI ( * MBB , CI . Paired , DL , TII -> get ( <STR_LIT> ) , BaseReg ) . addImm ( CI . BaseOff ) . addReg ( AddrReg -> getReg ( ) ) ; } MachineInstrBuilder Read2 = BuildMI ( * MBB , CI . Paired , DL , Read2Desc , DestReg ) . addReg ( BaseReg , BaseRegFlags ) . addImm ( NewOffset0 ) . addImm ( NewOffset1 ) . addImm ( <NUM_LIT> ) . setMemRefs ( CI . I -> mergeMemRefsWith ( * CI . Paired ) ) ; ( void ) Read2 ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , CI . Paired , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1 , CI . InstsToMove ) ; MachineBasicBlock :: iterator Next = std :: next ( CI . I ) ; CI . I -> eraseFromParent ( ) ;


<s> case CONST_DOUBLE : return true ; case NEG : return arc_legitimate_constant_p ( mode , XEXP ( x , <NUM_LIT> ) ) ; case PLUS : case MINUS : { bool t1 = arc_legitimate_constant_p ( mode , XEXP ( x , <NUM_LIT> ) ) ; bool t2 = arc_legitimate_constant_p ( mode , XEXP ( x , <NUM_LIT> ) ) ; return ( t1 && t2 ) ; } case CONST_VECTOR : switch ( mode ) { case E_V2HImode : return TARGET_PLUS_DMPY ;


<s> bool isSImm8 ( ) const { return isSImm < <NUM_LIT> > ( ) ;


<s> const Function & F = MF . getFunction ( ) ; const DataLayout & DL = F . getParent ( ) -> getDataLayout ( ) ; PointerType * PtrTy = PointerType :: get ( ParamTy , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; unsigned TypeSize = DL . getTypeStoreSize ( ParamTy ) ;

unsigned PtrReg = lowerParameterPtr ( MIRBuilder , ParamTy , Offset ) ;


<s> vec_int4 minus_a ; minus_a = spu_add ( spu_sub ( <NUM_LIT> , a ) , ( vec_int4 ) ( spu_cmpeq ( a , ( ( vec_int4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ) ) ; return ( spu_sel ( minus_a , a , spu_cmpgt ( a , - <NUM_LIT> ) ) ) ;


<s> int V2AdjIndex = V2Index ^ <NUM_LIT> ; if ( Mask [ V2AdjIndex ] < <NUM_LIT> ) { if ( V2Index < <NUM_LIT> ) std :: swap ( LowV , HighV ) ; NewMask [ V2Index ] -= <NUM_LIT> ; } else { int V1Index = V2AdjIndex ; int BlendMask [ <NUM_LIT> ] = { Mask [ V2Index ] - <NUM_LIT> , <NUM_LIT> , Mask [ V1Index ] , <NUM_LIT> } ; V2 = DAG . getNode ( <STR_LIT> , DL , VT , V2 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DL , DAG ) ) ; if ( V2Index < <NUM_LIT> ) { LowV = V2 ; HighV = V1 ; } else { HighV = V2 ; } NewMask [ V1Index ] = <NUM_LIT> ; NewMask [ V2Index ] = <NUM_LIT> ; } } else if ( NumV2Elements == <NUM_LIT> ) { if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; } else if ( Mask [ <NUM_LIT> ] < <NUM_LIT> && Mask [ <NUM_LIT> ] < <NUM_LIT> ) { NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; NewMask [ <NUM_LIT> ] -= <NUM_LIT> ; HighV = V1 ; LowV = V2 ; } else { int BlendMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] < <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> , ( Mask [ <NUM_LIT> ] >= <NUM_LIT> ? Mask [ <NUM_LIT> ] : Mask [ <NUM_LIT> ] ) - <NUM_LIT> } ; V1 = DAG . getNode ( <STR_LIT> , DL , VT , V1 , V2 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DL , DAG ) ) ; LowV = HighV = V1 ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; NewMask [ <NUM_LIT> ] = Mask [ <NUM_LIT> ] < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ;


<s> case <STR_LIT> : { const RegisterSDNode * R = nullptr ; if ( N -> getOpcode ( ) == <STR_LIT> ) { R = dyn_cast < RegisterSDNode > ( N ) ; } else { R = dyn_cast < RegisterSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; } if ( R ) { const MachineFunction * MF = FLI -> MF ; const <ISA_LIT>Subtarget & ST = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const <ISA_LIT>RegisterInfo & TRI = ST . getInstrInfo ( ) -> getRegisterInfo ( ) ; unsigned Reg = R -> getReg ( ) ; if ( TRI . isPhysicalRegister ( Reg ) ) return TRI . isVGPR ( MRI , Reg ) ; if ( MRI . isLiveIn ( Reg ) ) { if ( ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( MRI . getLiveInPhysReg ( Reg ) == <STR_LIT> ) || ( TRI . isVGPR ( MRI , Reg ) ) ) return true ; else if ( ! <STR_LIT> ( FLI -> Fn -> getCallingConv ( ) ) ) return true ; } return ! DA || DA -> isDivergent ( FLI -> getValueFromVirtualReg ( Reg ) ) ; } } break ; case <STR_LIT> : { const LoadSDNode * L = dyn_cast < LoadSDNode > ( N ) ; if ( L -> getMemOperand ( ) -> getAddrSpace ( ) == Subtarget -> get<ISA_LIT>AS ( ) . PRIVATE_ADDRESS ) return true ; } break ; case <STR_LIT> : return true ; break ; case <STR_LIT> : {


<s> eco32_compute_frame ( ) ; if ( cfun -> machine -> save_ret ) return gen_rtx_MEM ( Pmode , plus_constant ( Pmode , arg_pointer_rtx , - UNITS_PER_WORD ) ) ; return get_hard_reg_initial_val ( Pmode , RETURN_ADDRESS_REGNUM ) ;


<s> if ( cfun && cfun -> decl ) return lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( cfun -> decl ) ) ;


<s> return new <ISA_LIT>AtomicOptimizer ( ) ;


<s> emit_insn ( gen_sse_loadlps ( t , t , m ) ) ; m = adjust_address ( op1 , V2SFmode , <NUM_LIT> ) ; emit_insn ( gen_sse_loadhps ( t , t , m ) ) ; if ( mode != V4SFmode ) emit_move_insn ( op0 , gen_lowpart ( mode , t ) ) ; } } else if ( MEM_P ( op0 ) ) { if ( TARGET_SSE2 && mode == V2DFmode ) { m = adjust_address ( op0 , DFmode , <NUM_LIT> ) ; emit_insn ( gen_sse2_storelpd ( m , op1 ) ) ; m = adjust_address ( op0 , DFmode , <NUM_LIT> ) ; emit_insn ( gen_sse2_storehpd ( m , op1 ) ) ; } else { if ( mode != V4SFmode ) op1 = gen_lowpart ( V4SFmode , op1 ) ; m = adjust_address ( op0 , V2SFmode , <NUM_LIT> ) ; emit_insn ( gen_sse_storelps ( m , op1 ) ) ; m = adjust_address ( op0 , V2SFmode , <NUM_LIT> ) ; emit_insn ( gen_sse_storehps ( m , copy_rtx ( op1 ) ) ) ; } } else gcc_unreachable ( ) ;


<s> if ( target_mcu == NULL ) return true ; if ( target_mcu == cached_match ) return cached_result ; cached_match = target_mcu ;

for ( i = ARRAY_SIZE ( msp430_mcu_data ) ; i -- ; ) if ( strcasecmp ( target_mcu , msp430_mcu_data [ i ] . name ) == <NUM_LIT> ) return cached_result = msp430_mcu_data [ i ] . hwmpy == <NUM_LIT> ;


<s> SDLoc dl ( N ) ; SDValue Cond = N -> getOperand ( <NUM_LIT> ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; SDValue RHS = N -> getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) == <STR_LIT> ) { SDValue CondSrc = Cond -> getOperand ( <NUM_LIT> ) ; if ( CondSrc -> getOpcode ( ) == <STR_LIT> ) Cond = CondSrc -> getOperand ( <NUM_LIT> ) ; } MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; MVT EltVT = VT . getVectorElementType ( ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( VT . is512BitVector ( ) ) return SDValue ( ) ;

if ( ! Subtarget -> hasSSE41 ( ) || EltVT == <STR_LIT> ) return SDValue ( ) ;


<s> case OPW32 : case OPW16 : return SGPR_32RegClassID ; case OPW64 : return SGPR_64RegClassID ; case OPW128 : return SGPR_128RegClassID ; }


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> if ( TLOF . IsConstantInSmallSection ( N -> getConstVal ( ) , getTargetMachine ( ) ) ) return getAddrGPRel ( N , Ty , DAG ) ; return getAddrNonPIC ( N , Ty , DAG ) ; }

return getAddrLocal ( N , Ty , DAG , Subtarget . isABI_N32 ( ) || Subtarget . isABI_N64 ( ) ) ;


<s> r = REGNO ( reg ) ; if ( FP_REGNO_P ( r ) ) { if ( mode == SFmode ) store_string = <STR_LIT> ; else if ( mode == DFmode ) store_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( ALTIVEC_REGNO_P ( r ) && TARGET_P9_DFORM_SCALAR ) { if ( mode == SFmode ) store_string = <STR_LIT> ; else if ( mode == DFmode || mode == DImode ) store_string = <STR_LIT> ; else gcc_unreachable ( ) ; } else if ( INT_REGNO_P ( r ) ) { switch ( mode ) { case E_QImode : store_string = <STR_LIT> ; break ; case E_HImode : store_string = <STR_LIT> ; break ; case E_SImode : case E_SFmode : store_string = <STR_LIT> ; break ; case E_DImode : case E_DFmode : if ( ! TARGET_POWERPC64 ) gcc_unreachable ( ) ; store_string = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; }


<s> inline void function_expander :: add_input_operand ( machine_mode mode , rtx op ) {

create_input_operand ( & m_ops [ opno ++ ] , op , mode ) ;


<s> return MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ;


<s> <ISA_LIT>MCExpr :: <ISA_LIT>MCExpr ( MCExpr const * Expr ) : Expr ( Expr ) , MustNotExtend ( false ) , MustExtend ( false ) , S27_2_reloc ( false ) , SignMismatch ( false ) {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; N -> setNodeId ( - <NUM_LIT> ) ; return ; } SDLoc Dl ( N ) ; unsigned Opcode = N -> getOpcode ( ) ; bool IsSelected = false ; switch ( Opcode ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> addPass ( create<ISA_LIT>ArgumentMove ( ) ) ; addPass ( create<ISA_LIT>SetP2AlignOperands ( ) ) ; addPass ( create<ISA_LIT>FixBrTableDefaults ( ) ) ; return false ;


<s> SDValue Vec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue SubVec = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; SDValue Idx = Op . getNode ( ) -> getOperand ( <NUM_LIT> ) ; if ( Op . getNode ( ) -> getValueType ( <NUM_LIT> ) . is256BitVector ( ) && SubVec . getNode ( ) -> getValueType ( <NUM_LIT> ) . is128BitVector ( ) && isa < ConstantSDNode > ( Idx ) ) { unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ; return Insert128BitVector ( Vec , SubVec , IdxVal , DAG , dl ) ; } }


<s> bool <ISA_LIT>AsmParser :: MatchAndEmitInstruction ( SMLoc IDLoc , unsigned & Opcode , OperandVector & Operands , MCStreamer & Out , uint64_t & ErrorInfo , bool MatchingInlineAsm ) { MCInst Inst ; SMLoc ErrorLoc ; if ( PreMatchCheck ( Operands ) ) return Error ( IDLoc , <STR_LIT> ) ; switch ( MatchInstructionImpl ( Operands , Inst , ErrorInfo , MatchingInlineAsm ) ) { default : break ; case Match_Success : Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , getSTI ( ) ) ; return false ; case Match_MissingFeature : return Error ( IDLoc , <STR_LIT> ) ; case Match_MnemonicFail :


<s> auto & Dep = PacketSU -> Succs [ i ] ; if ( Dep . getSUnit ( ) == PacketSUDep && Dep . getKind ( ) == SDep :: Anti && Dep . getReg ( ) == DepReg ) return true ; } } } return false ;


<s> MachineInstrBuilder MIB1 = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; MIB1 . addReg ( <STR_LIT> ) ; MIB1 . addImm ( - <NUM_LIT> ) ; MachineInstrBuilder MIB0 = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; MIB0 . addReg ( <STR_LIT> ) ; MachineInstrBuilder MIB2 = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; MIB2 . addReg ( <STR_LIT> ) ; MIB2 . addImm ( - <NUM_LIT> ) ; MachineInstrBuilder MIB3 = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , <STR_LIT> ) ; MIB3 . addReg ( <STR_LIT> ) ;


<s> void EmitByte ( unsigned char C , raw_ostream & OS ) const { OS << ( char ) C ;


<s> return SGPRPressureSets . test ( SetID ) && ! VGPRPressureSets . test ( SetID ) && ! AGPRPressureSets . test ( SetID ) ;


<s> unsigned Reg ; if ( ( Reg = isLoadFromStackSlot ( MI , FrameIndex ) ) ) return Reg ; const MachineMemOperand * Dummy ;

return hasLoadFromStackSlot ( MI , Dummy , FrameIndex ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS , bool isLittle = false ) : LLVMTargetMachine ( T , TT ) , Subtarget ( TT , FS , isLittle ) , DataLayout ( isLittle ? std :: string ( <STR_LIT> ) : std :: string ( <STR_LIT> ) ) , InstrInfo ( * this ) , FrameInfo ( TargetFrameInfo :: StackGrowsUp , <NUM_LIT> , <NUM_LIT> ) , TLInfo ( * this ) {

if ( getRelocationModel ( ) == Reloc :: Default ) {


<s> const MCPhysReg * <ISA_LIT>TargetLowering :: getScratchRegisters ( CallingConv :: ID ) const {

static const MCPhysReg ScratchRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ;


<s> static void insertSext ( const <ISA_LIT>InstrInfo * TII , DebugLoc DL , MachineBasicBlock * MBB , unsigned ValReg , unsigned ShamtReg ) {

BuildMI ( MBB , DL , TII -> get ( <STR_LIT> ) , ValReg ) . addReg ( ValReg ) . addReg ( ShamtReg ) ;


<s> CCInfo . AllocateReg ( AMDGPU :: VGPR0 ) ; CCInfo . AllocateReg ( AMDGPU :: VGPR1 ) ; } if ( Info -> getShaderType ( ) == ShaderType :: COMPUTE ) { if ( Subtarget -> isAmdHsaOS ( ) ) Info -> NumUserSGPRs = <NUM_LIT> ; else Info -> NumUserSGPRs = <NUM_LIT> ; unsigned InputPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: INPUT_PTR ) ; unsigned InputPtrRegLo = TRI -> getPhysRegSubReg ( InputPtrReg , & AMDGPU :: SReg_32RegClass , <NUM_LIT> ) ; unsigned InputPtrRegHi = TRI -> getPhysRegSubReg ( InputPtrReg , & AMDGPU :: SReg_32RegClass , <NUM_LIT> ) ; unsigned ScratchPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: SCRATCH_PTR ) ; unsigned ScratchPtrRegLo = TRI -> getPhysRegSubReg ( ScratchPtrReg , & AMDGPU :: SReg_32RegClass , <NUM_LIT> ) ; unsigned ScratchPtrRegHi = TRI -> getPhysRegSubReg ( ScratchPtrReg , & AMDGPU :: SReg_32RegClass , <NUM_LIT> ) ; CCInfo . AllocateReg ( InputPtrRegLo ) ; CCInfo . AllocateReg ( InputPtrRegHi ) ; CCInfo . AllocateReg ( ScratchPtrRegLo ) ; CCInfo . AllocateReg ( ScratchPtrRegHi ) ; MF . addLiveIn ( InputPtrReg , & AMDGPU :: SReg_64RegClass ) ; MF . addLiveIn ( ScratchPtrReg , & AMDGPU :: SReg_64RegClass ) ; } if ( Info -> getShaderType ( ) == ShaderType :: COMPUTE ) { getOriginalFunctionArgs ( DAG , DAG . getMachineFunction ( ) . getFunction ( ) , Ins , Splits ) ; } AnalyzeFormalArguments ( CCInfo , Splits ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) , ArgIdx = <NUM_LIT> ; i != e ; ++ i ) { const <STR_LIT> & Arg = Ins [ i ] ; if ( Skipped [ i ] ) { InVals . push_back ( DAG . getUNDEF ( Arg . VT ) ) ; continue ; } CCValAssign & VA = ArgLocs [ ArgIdx ++ ] ; MVT VT = VA . getLocVT ( ) ; if ( VA . isMemLoc ( ) ) { VT = Ins [ i ] . VT ; EVT MemVT = Splits [ i ] . VT ; const unsigned Offset = <NUM_LIT> + VA . getLocMemOffset ( ) ; SDValue Arg = LowerParameter ( DAG , VT , MemVT , DL , DAG . getRoot ( ) , Offset , Ins [ i ] . Flags . isSExt ( ) ) ;

const PointerType * ParamTy = dyn_cast < PointerType > ( FType -> getParamType ( Ins [ i ] . OrigArgIndex ) ) ;


<s> if ( ( AddrSpace & <STR_LIT> ) != <STR_LIT> ) { switch ( Scope ) { case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default :


<s> if ( getParser ( ) . parseAbsoluteExpression ( CntVal ) ) return true ; <STR_LIT> ISA = <STR_LIT> ( getSTI ( ) . getCPU ( ) ) ; bool Failed = true ; bool Sat = CntName . endswith ( <STR_LIT> ) ; if ( CntName == <STR_LIT> || CntName == <STR_LIT> ) { Failed = encodeCnt ( ISA , IntVal , CntVal , Sat , encodeVmcnt , decodeVmcnt ) ; } else if ( CntName == <STR_LIT> || CntName == <STR_LIT> ) { Failed = encodeCnt ( ISA , IntVal , CntVal , Sat , encodeExpcnt , decodeExpcnt ) ; } else if ( CntName == <STR_LIT> || CntName == <STR_LIT> ) { Failed = encodeCnt ( ISA , IntVal , CntVal , Sat , encodeLgkmcnt , decodeLgkmcnt ) ; } if ( Failed ) { Error ( ValLoc , <STR_LIT> + CntName ) ; return true ;


<s> if ( I != MBB . end ( ) && ! I -> isDebugValue ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ;

const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ;


<s> void <ISA_LIT>BitcodeWriter :: pushValue ( const Value * V , unsigned InstID , SmallVectorImpl < unsigned > & Vals ) { unsigned ValID = VE . getValueID ( V ) ; Vals . push_back ( InstID - ValID ) ;


<s> const Constant * C = CN -> getConstVal ( ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small :

return DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetConstantPool ( C , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getTargetConstantPool ( C , PtrVT , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( CN -> getAlignment ( ) , <STR_LIT> ) ) ;


<s> emit_insn ( gen_add2_insn ( base_tmp , element_offset ) ) ; } new_addr = gen_rtx_PLUS ( Pmode , op0 , base_tmp ) ; } } else { emit_move_insn ( base_tmp , addr ) ; new_addr = gen_rtx_PLUS ( Pmode , base_tmp , element_offset ) ; } if ( GET_CODE ( new_addr ) == PLUS ) { rtx op1 = XEXP ( new_addr , <NUM_LIT> ) ; addr_mask_type addr_mask ; int scalar_regno = regno_or_subregno ( scalar_reg ) ; gcc_assert ( scalar_regno < FIRST_PSEUDO_REGISTER ) ; if ( INT_REGNO_P ( scalar_regno ) ) addr_mask = reg_addr [ scalar_mode ] . addr_mask [ RELOAD_REG_GPR ] ; else if ( FP_REGNO_P ( scalar_regno ) ) addr_mask = reg_addr [ scalar_mode ] . addr_mask [ RELOAD_REG_FPR ] ; else if ( ALTIVEC_REGNO_P ( scalar_regno ) ) addr_mask = reg_addr [ scalar_mode ] . addr_mask [ RELOAD_REG_VMX ] ; else gcc_unreachable ( ) ; if ( REG_P ( op1 ) || SUBREG_P ( op1 ) ) valid_addr_p = ( addr_mask & RELOAD_REG_INDEXED ) != <NUM_LIT> ; else valid_addr_p = ( addr_mask & RELOAD_REG_OFFSET ) != <NUM_LIT> ; } else if ( REG_P ( new_addr ) || SUBREG_P ( new_addr ) ) valid_addr_p = true ; else valid_addr_p = false ; if ( ! valid_addr_p ) { emit_move_insn ( base_tmp , new_addr ) ;


<s> auto & block_info = m_vector_manager -> vector_block_infos [ bb -> index ( ) ] ; if ( block_info . local_dem . empty_p ( ) ) return ; vector_insn_info curr_info ; for ( insn_info * insn : bb -> real_nondebug_insns ( ) ) { const vector_insn_info prev_info = curr_info ; enum vsetvl_type type = NUM_VSETVL_TYPE ; transfer_before ( curr_info , insn ) ; if ( has_vtype_op ( insn -> rtl ( ) ) ) { if ( static_cast < const vl_vtype_info & > ( prev_info ) != static_cast < const vl_vtype_info & > ( curr_info ) ) { const auto require = m_vector_manager -> vector_insn_infos [ insn -> uid ( ) ] ; if ( ! require . compatible_p ( static_cast < const vl_vtype_info & > ( prev_info ) ) ) type = insert_vsetvl ( EMIT_BEFORE , insn -> rtl ( ) , require , prev_info ) ; } } if ( type == VSETVL_VTYPE_CHANGE_ONLY ) { curr_info . set_avl_info ( prev_info . get_avl_info ( ) ) ;


<s> MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ; else llvm_unreachable ( <STR_LIT> ) ;


<s> if ( VT == <STR_LIT> ) return ! Subtarget -> hasFP64 ( ) ;

if ( VT == <STR_LIT> ) return ! Subtarget -> hasFullFP16 ( ) ;


<s> SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , <NUM_LIT> ) ; if ( SplitVTs . size ( ) != <NUM_LIT> ) { return false ; } EVT VT = SplitVTs [ <NUM_LIT> ] ; unsigned NumParts = TLI . getNumRegisters ( Context , VT ) ; if ( NumParts == <NUM_LIT> ) { SplitArgs . emplace_back ( OrigArg . Reg , VT . getTypeForEVT ( Context ) , OrigArg . Flags , OrigArg . IsFixed ) ; return true ; } SmallVector < unsigned , <NUM_LIT> > SplitRegs ; EVT PartVT = TLI . getRegisterType ( Context , VT ) ; Type * PartTy = PartVT . getTypeForEVT ( Context ) ; for ( unsigned i = <NUM_LIT> ; i < NumParts ; ++ i ) { ArgInfo Info = ArgInfo { MRI . createGenericVirtualRegister ( getLLTForType ( * PartTy , DL ) ) , PartTy , OrigArg . Flags } ; SplitArgs . push_back ( Info ) ; SplitRegs . push_back ( Info . Reg ) ;


<s> rtx chr2 = gen_reg_rtx ( SImode ) ; rtx chr1_di = simplify_gen_subreg ( DImode , chr1 , SImode , <NUM_LIT> ) ; rtx chr2_di = simplify_gen_subreg ( DImode , chr2 , SImode , <NUM_LIT> ) ; emit_insn ( gen_vclzlsbb_v16qi ( diffix , vec_result ) ) ; emit_insn ( gen_vextublx ( chr1 , diffix , str1 ) ) ; emit_insn ( gen_vextublx ( chr2 , diffix , str2 ) ) ; do_sub3 ( result , chr1_di , chr2_di ) ; } else { gcc_assert ( TARGET_P8_VECTOR ) ; rtx diffix = gen_reg_rtx ( DImode ) ; rtx result_gbbd = gen_reg_rtx ( V16QImode ) ; emit_insn ( gen_p8v_vgbbd ( result_gbbd , vec_result ) ) ; rtx result_shifted = gen_reg_rtx ( V16QImode ) ; int shift_amt = ( BYTES_BIG_ENDIAN ) ? <NUM_LIT> : <NUM_LIT> ; emit_insn ( gen_altivec_vsldoi_v16qi ( result_shifted , result_gbbd , result_gbbd , GEN_INT ( shift_amt ) ) ) ; rtx diffix_df = simplify_gen_subreg ( DFmode , diffix , DImode , <NUM_LIT> ) ; emit_insn ( gen_p8_mfvsrd_3_v16qi ( diffix_df , result_shifted ) ) ; rtx count = gen_reg_rtx ( DImode ) ; if ( BYTES_BIG_ENDIAN ) emit_insn ( gen_clzdi2 ( count , diffix ) ) ; else emit_insn ( gen_ctzdi2 ( count , diffix ) ) ; do_add3 ( off_reg , off_reg , count ) ; rtx chr1 = gen_reg_rtx ( QImode ) ; rtx chr2 = gen_reg_rtx ( QImode ) ; rtx addr1 = gen_rtx_PLUS ( Pmode , s1addr , off_reg ) ; do_load_for_compare_from_addr ( QImode , chr1 , addr1 , orig_src1 ) ; rtx addr2 = gen_rtx_PLUS ( Pmode , s2addr , off_reg ) ; do_load_for_compare_from_addr ( QImode , chr2 , addr2 , orig_src2 ) ; machine_mode rmode = GET_MODE ( result ) ; rtx chr1_rm = simplify_gen_subreg ( rmode , chr1 , QImode , <NUM_LIT> ) ;

rtx chr2_rm = simplify_gen_subreg ( rmode , chr2 , QImode , <NUM_LIT> ) ;


<s> } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getSizeInBits ( ) / <NUM_LIT> ; if ( ObjSize > StackSlotSize ) { errs ( ) << <STR_LIT> << EVT ( VA . getLocVT ( ) ) . getEVTString ( ) << <STR_LIT> ; } int FI = MFI -> CreateFixedObject ( ObjSize , LRSaveSize + VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; InVals . push_back ( DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , <NUM_LIT> ) ) ; } } if ( isVarArg ) { static const unsigned ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; <ISA_LIT>FunctionInfo * XFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FirstVAReg = CCInfo . getFirstUnallocated ( ArgRegs , array_lengthof ( ArgRegs ) ) ; if ( FirstVAReg < array_lengthof ( ArgRegs ) ) { SmallVector < SDValue , <NUM_LIT> > MemOps ; int offset = <NUM_LIT> ; for ( int i = array_lengthof ( ArgRegs ) - <NUM_LIT> ; i >= ( int ) FirstVAReg ; -- i ) { int FI = MFI -> CreateFixedObject ( <NUM_LIT> , offset , true ) ; if ( i == ( int ) FirstVAReg ) { XFI -> setVarArgsFrameIndex ( FI ) ; } offset -= StackSlotSize ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; unsigned VReg = RegInfo . createVirtualRegister ( <STR_LIT> ) ; RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ;

SDValue Val = DAG . getCopyFromReg ( Chain , dl , VReg , <STR_LIT> ) ;


<s> if ( SrcReg1 == <NUM_LIT> ) return false ; unsigned SrcReg2 = getRegForValue ( I -> getOperand ( <NUM_LIT> ) ) ; if ( SrcReg2 == <NUM_LIT> ) return false ; unsigned ResultReg = createResultReg ( & <STR_LIT> ) ; SrcReg1 = constrainOperandRegClass ( TII . get ( Opc ) , SrcReg1 , <NUM_LIT> ) ; SrcReg2 = constrainOperandRegClass ( TII . get ( Opc ) , SrcReg2 , <NUM_LIT> ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Opc ) , ResultReg ) . addReg ( SrcReg1 ) . addReg ( SrcReg2 ) ) ; UpdateValueMap ( I , ResultReg ) ; return true ;


<s> <STR_LIT> AM = LdSt -> getAddressingMode ( ) ; if ( AM != <STR_LIT> ) return false ; Offset = N ;

if ( ConstantSDNode * NC = dyn_cast < ConstantSDNode > ( N ) ) {


<s> if ( TRI . needsStackRealignment ( MF ) ) { HasFP = true ; const unsigned Alignment = MFI . getMaxAlignment ( ) ; RoundedSize += Alignment ; LiveRegs . init ( TRI ) ; LiveRegs . addLiveIns ( MBB ) ; unsigned ScratchSPReg = findScratchNonCalleeSaveRegister ( MF , LiveRegs , <STR_LIT> ) ; assert ( ScratchSPReg != <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , ScratchSPReg ) . addReg ( StackPtrReg ) . addImm ( ( Alignment - <NUM_LIT> ) * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , FramePtrReg ) . addReg ( ScratchSPReg , RegState :: Kill ) . addImm ( - Alignment * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; FuncInfo -> setIsStackRealigned ( true ) ; } else if ( ( HasFP = hasFP ( MF ) ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , FramePtrReg ) . addReg ( StackPtrReg ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( HasFP && RoundedSize != <NUM_LIT> ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , StackPtrReg ) . addReg ( StackPtrReg ) . addImm ( RoundedSize * ST . getWavefrontSize ( ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : TargetInstrInfoImpl ( <ISA_LIT>Insts , array_lengthof ( <ISA_LIT>Insts ) ) , RI ( tm , * this ) , TM ( tm ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const {


<s> return new MCInstrAnalysis ( Info ) ;


<s> Op -> CondCode . Code = Code ; Op -> StartLoc = S ; Op -> EndLoc = E ; return Op ;


<s> virtual const <ISA_LIT>ompactSelectionDAGInfo * getSelectionDAGInfo ( ) const {


<s> operands [ <NUM_LIT> ] = force_reg ( mode , op1 ) ;

if ( ! REG_P ( operands [ <NUM_LIT> ] ) && ( ! CONST_INT_P ( operands [ <NUM_LIT> ] ) || ( mode == SImode && operands [ <NUM_LIT> ] != CONST0_RTX ( SImode ) && ( ( comparison != EQ && comparison != NE ) || ( REG_P ( op1 ) && REGNO ( op1 ) != R0_REG ) || ! satisfies_constraint_I08 ( operands [ <NUM_LIT> ] ) ) ) ) ) operands [ <NUM_LIT> ] = force_reg ( mode , operands [ <NUM_LIT> ] ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << MF . getName ( ) << '\n' ) ; TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) { bool LocalChange = false ; for ( MachineBasicBlock :: iterator I = MBB . getFirstTerminator ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineInstr & MI = * I ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsStore = Desc . mayStore ( ) ; bool Scavenged = false ; unsigned SOffset = ScratchOffsetReg ; const unsigned EltSize = <NUM_LIT> ; const TargetRegisterClass * RC = getRegClassForReg ( MF -> getRegInfo ( ) , ValueReg ) ; unsigned NumSubRegs = <STR_LIT> ( RC -> getID ( ) ) / ( EltSize * CHAR_BIT ) ; unsigned Size = NumSubRegs * EltSize ; int64_t Offset = InstOffset + MFI . getObjectOffset ( Index ) ; int64_t ScratchOffsetRegDelta = <NUM_LIT> ; unsigned Align = MFI . getObjectAlignment ( Index ) ; const MachinePointerInfo & BasePtrInfo = MMO -> getPointerInfo ( ) ; Register TmpReg = hasAGPRs ( RC ) ? TII -> getNamedOperand ( * MI , <STR_LIT> :: tmp ) -> getReg ( ) : Register ( ) ; assert ( ( Offset % EltSize ) == <NUM_LIT> && <STR_LIT> ) ; if ( ! isUInt < <NUM_LIT> > ( Offset + Size - EltSize ) ) { SOffset = <STR_LIT> ; Offset *= ST . getWavefrontSize ( ) ; if ( RS ) SOffset = RS -> scavengeRegister ( & <STR_LIT> , MI , <NUM_LIT> , false ) ; if ( SOffset == <STR_LIT> ) { SOffset = ScratchOffsetReg ; ScratchOffsetRegDelta = Offset ; } else { Scavenged = true ; } BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , SOffset ) . addReg ( ScratchOffsetReg ) . addImm ( Offset ) ; Offset = <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> , e = NumSubRegs ; i != e ; ++ i , Offset += EltSize ) { Register SubReg = NumSubRegs == <NUM_LIT> ? Register ( ValueReg ) : getSubReg ( ValueReg , getSubRegFromChannel ( i ) ) ; unsigned SOffsetRegState = <NUM_LIT> ;

unsigned SrcDstRegState = getDefRegState ( ! IsStore ) ;


<s> EVT DstTy = Op . getValueType ( ) ; EVT TheVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; if ( TheVT != <STR_LIT> && TheVT != <STR_LIT> && TheVT != <STR_LIT> ) { return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; } bool UnsignedFixup = ! IsSigned && DstTy == <STR_LIT> && ( ! Subtarget . is64Bit ( ) || ! isScalarFPTypeInSSEReg ( TheVT ) ) ; if ( ! IsSigned && DstTy != <STR_LIT> && ! Subtarget . hasAVX512 ( ) ) { assert ( DstTy == <STR_LIT> && <STR_LIT> ) ; DstTy = <STR_LIT> ; } assert ( DstTy . getSimpleVT ( ) <= <STR_LIT> && DstTy . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; if ( Subtarget . is64Bit ( ) && DstTy == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ) ) return std :: make_pair ( SDValue ( ) , SDValue ( ) ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned MemSize = DstTy . getSizeInBits ( ) / <NUM_LIT> ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( MemSize , MemSize , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; unsigned Opc ; switch ( DstTy . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } SDValue Chain = DAG . getEntryNode ( ) ; SDValue Value = Op . getOperand ( <NUM_LIT> ) ; SDValue Adjust ; if ( UnsignedFixup ) { APFloat Thresh ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> ) ) ; LLVM_ATTRIBUTE_UNUSED APFloat :: opStatus Status = APFloat :: opOK ; bool LosesInfo = false ; if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: IEEEdouble , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; else if ( TheVT == <STR_LIT> ) Status = Thresh . convert ( APFloat :: x87DoubleExtended , APFloat :: rmNearestTiesToEven , & LosesInfo ) ; assert ( Status == APFloat :: opOK && ! LosesInfo && <STR_LIT> ) ; SDValue ThreshVal = DAG . getConstantFP ( Thresh , DL , TheVT ) ;

SDValue Cmp = DAG . getSetCC ( DL , getSetCCResultType ( DAG . getDataLayout ( ) , * DAG . getContext ( ) , TheVT ) , Value , ThreshVal , <STR_LIT> ) ;


<s> SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue NOOP ( DAG . getMachineNode ( <STR_LIT> , SDLoc ( Op ) , VTs , Ops ) , <NUM_LIT> ) ;


<s> Counters Limit = ZeroCounts ; unsigned Sum = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { LastIssued . Array [ i ] += Increment . Array [ i ] ; if ( Increment . Array [ i ] ) Limit . Array [ i ] = LastIssued . Array [ i ] ; Sum += Increment . Array [ i ] ; } if ( Sum == <NUM_LIT> ) { LastOpcodeType = OTHER ; return ; } if ( MBB . getParent ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getGeneration ( ) >= <ISA_LIT>Subtarget :: VOLCANIC_ISLANDS ) { if ( ( LastOpcodeType == SMEM && TII -> isSMRD ( I -> getOpcode ( ) ) ) || ( LastOpcodeType == VMEM && Increment . Named . VM ) ) { BuildMI ( MBB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) ; LastInstWritesM0 = false ; } if ( TII -> isSMRD ( I -> getOpcode ( ) ) ) LastOpcodeType = SMEM ; else if ( Increment . Named . VM ) LastOpcodeType = VMEM ; } if ( Increment . Named . EXP ) { ExpInstrTypesSeen |= I -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; } for ( unsigned i = <NUM_LIT> , e = I -> getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & Op = I -> getOperand ( i ) ; if ( ! isOpRelevant ( Op ) ) continue ; const TargetRegisterClass * RC = TII -> getOpRegClass ( * I , i ) ; RegInterval Interval = getRegInterval ( RC , Op ) ; for ( unsigned j = Interval . first ; j < Interval . second ; ++ j ) { if ( Op . isDef ( ) ) DefinedRegs [ j ] = Limit ; if ( Op . isUse ( ) ) UsedRegs [ j ] = Limit ;


<s> MachineFrameInfo & MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; if ( ! isVarArg ) CCInfo . AllocateStack ( XFI -> getReturnStackOffset ( ) , Align ( <NUM_LIT> ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; RetOps . push_back ( DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ;


<s> } else { if ( RelocM == Reloc :: PIC_ ) { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ; if ( isDecl || GV -> hasCommonLinkage ( ) ) return true ; return false ; } else { if ( ! isDecl && ! GV -> isWeakForLinker ( ) ) return false ; if ( ! GV -> hasHiddenVisibility ( ) ) return true ;


<s> uint64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;

assert ( Value < <NUM_LIT> && <STR_LIT> ) ;


<s> void <ISA_LIT>FrameLowering :: emitCalleeSavedFrameMoves ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MBBI , DebugLoc DL , unsigned FramePtr ) const { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineModuleInfo & MMI = MF . getMMI ( ) ; const MCRegisterInfo * MRI = MMI . getContext ( ) . getRegisterInfo ( ) ; const <ISA_LIT>InstrInfo & TII = * TM . getInstrInfo ( ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; if ( CSI . empty ( ) ) return ; const <ISA_LIT>RegisterInfo * RegInfo = TM . getRegisterInfo ( ) ; bool HasFP = hasFP ( MF ) ; int stackGrowth = - RegInfo -> getSlotSize ( ) ; int64_t MaxOffset = <NUM_LIT> ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) MaxOffset = std :: min ( MaxOffset , MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ) ; int64_t saveAreaOffset = ( HasFP ? <NUM_LIT> : <NUM_LIT> ) * stackGrowth ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) {

int64_t Offset = MFI -> getObjectOffset ( I -> getFrameIdx ( ) ) ;


<s> static MCStreamer * create<ISA_LIT>MCStreamer ( const Triple & T , MCContext & Ctx , std :: unique_ptr < MCAsmBackend > && MAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > && Emitter , bool RelaxAll ) {

return createELFStreamer ( Ctx , std :: move ( MAB ) , OS , std :: move ( Emitter ) , RelaxAll ) ;


<s> return ( Node -> NumPreds > <NUM_LIT> || Node -> NumSuccs > <NUM_LIT> ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> inline SDValue getSmallIPtrImm ( unsigned Imm ) {

return CurDAG -> getTargetConstant ( Imm , <ISA_LIT>Lowering . getPointerTy ( ) ) ;


return TargetTriple . getOS ( ) == Triple :: NetBSD ;


<s> MadeChange |= doPeepholeSExtW ( N ) ; MadeChange |= doPeepholeLoadStoreADDI ( N ) ; } if ( MadeChange ) CurDAG -> RemoveDeadNodes ( ) ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> assert ( ( ( AS + <NUM_LIT> ) & ~ ADDR_SPACE ) == <NUM_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printLogicalImm32 ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { uint64_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> const MCRegisterInfo * RegInfo = D -> getContext ( ) . getRegisterInfo ( ) ; return * ( RegInfo -> getRegClass ( RC ) . begin ( ) + RegNo ) ;


<s> bool hasVFP4 ( ) const { return HasVFPv4 ;


<s> bool aarch64_can_tag_addresses ( ) { return ! TARGET_ILP32 ;


<s> EVT VT = Op . getValueType ( ) ; if ( Op . getResNo ( ) != <NUM_LIT> || VT == <STR_LIT> ) return ; assert ( Known . getBitWidth ( ) == VT . getScalarSizeInBits ( ) && <STR_LIT> ) ; assert ( ( ! VT . isVector ( ) || ( DemandedElts . getBitWidth ( ) == VT . getVectorNumElements ( ) ) ) && <STR_LIT> ) ; unsigned BitWidth = Known . getBitWidth ( ) ; unsigned Opcode = Op . getOpcode ( ) ; if ( Opcode == <STR_LIT> ) { bool IsLogical = false ; unsigned Id = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; switch ( Id ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : computeKnownBitsBinOp ( Op , Known , DemandedElts , DAG , Depth , <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( ! cfun -> machine -> frame_locked ) { int rv = MEP_SAVES_NO ; if ( cfun -> machine -> reg_save_slot [ r ] ) rv = MEP_SAVES_YES ; else if ( r == LP_REGNO && ( profile_arc_flag > <NUM_LIT> || profile_flag > <NUM_LIT> ) ) rv = MEP_SAVES_YES ; else if ( r == FRAME_POINTER_REGNUM && frame_pointer_needed ) rv = MEP_SAVES_YES ; else if ( ( ! call_used_regs [ r ] || r == LP_REGNO ) && df_regs_ever_live_p ( r ) ) rv = MEP_SAVES_YES ; else if ( crtl -> calls_eh_return && ( r == <NUM_LIT> || r == <NUM_LIT> ) ) rv = MEP_SAVES_YES ; else if ( mep_interrupt_saved_reg ( r ) ) rv = MEP_SAVES_YES ; cfun -> machine -> reg_saved [ r ] = rv ; } return cfun -> machine -> reg_saved [ r ] == MEP_SAVES_YES ;


<s> imm |= ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! Check ( S , DecoderGPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( ! tryAddingSymbolicOperand ( Address , imm , false , <NUM_LIT> , Inst , Decoder ) ) Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ;


<s> const MCOperand & Op = MI -> getOperand ( OpNum ) ; if ( Op . isImm ( ) ) { O << <STR_LIT> << ( Op . getImm ( ) << <NUM_LIT> ) ;


<s> if ( ! riscv_tls_symbol ) riscv_tls_symbol = init_one_libfunc ( <STR_LIT> ) ; func = gen_rtx_MEM ( FUNCTION_MODE , riscv_tls_symbol ) ; start_sequence ( ) ; emit_insn ( riscv_got_load_tls_gd ( a0 , sym ) ) ; insn = emit_call_insn ( gen_call_value ( result , func , const0_rtx , NULL ) ) ; RTL_CONST_CALL_P ( insn ) = <NUM_LIT> ;

use_reg ( & CALL_INSN_FUNCTION_USAGE ( insn ) , a0 ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , LittleEndian ) , TT , CPU , FS , Options , RM , CM , OL ) , TLOF ( createTLOF ( Triple ( getTargetTriple ( ) ) ) ) , isLittle ( LittleEndian ) { initAsmInfo ( ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


initializeThumb2SizeReducePass ( Registry ) ;


<s> unsigned int n_insns = <NUM_LIT> ; if ( align > ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ) align = ( TARGET_64BIT ? <NUM_LIT> : <NUM_LIT> ) ; n_insns = <NUM_LIT> ; if ( n_bytes % ( <NUM_LIT> * align ) != <NUM_LIT> ) { if ( ( n_bytes % ( <NUM_LIT> * align ) ) >= align ) n_insns += <NUM_LIT> ; if ( ( n_bytes % align ) != <NUM_LIT> ) n_insns += <NUM_LIT> ; }


<s> <ISA_LIT>ELFObjectWriter ( bool Is64Bit , uint8_t OSABI ) : MCELFObjectTargetWriter ( Is64Bit , OSABI , Is64Bit ? ELF :: EM_<ISA_LIT>ARCV9 : ELF :: EM_<ISA_LIT>ARC , true ) {


<s> static inline bool mode_supports_vmx_dform ( machine_mode mode ) {

return ( ( reg_addr [ mode ] . addr_mask [ RELOAD_REG_VMX ] & RELOAD_REG_OFFSET ) != <NUM_LIT> ) ;


<s> return inITBlock ( ) && ITState . IsExplicit ;


<s> return ( __m128i ) __builtin_ia32_vaesenclast_v16qi ( ( __v16qi ) __A , ( __v16qi ) __B ) ;


<s> MFI -> setReturnAddressIsTaken ( true ) ; if ( TLI . verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; uint64_t depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; SDValue RetAddr ; if ( depth == <NUM_LIT> ) { unsigned RetReg = MF . addLiveIn ( <STR_LIT> , TLI . getRegClassFor ( TLI . getPointerTy ( ) ) ) ; RetAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , RetReg , VT ) ; return RetAddr ; }

SDValue FrameAddr = getFRAMEADDR ( depth - <NUM_LIT> , Op , DAG , Subtarget ) ;


<s> else if ( mode == V4DImode ) { umul = gen_vec_widen_umult_even_v8si ; nmode = V8SImode ; } else if ( mode == V8DImode ) { umul = gen_vec_widen_umult_even_v16si ; nmode = V16SImode ; } else gcc_unreachable ( ) ; t1 = gen_reg_rtx ( mode ) ; emit_insn ( umul ( t1 , gen_lowpart ( nmode , op1 ) , gen_lowpart ( nmode , op2 ) ) ) ; t6 = GEN_INT ( <NUM_LIT> ) ; t2 = expand_binop ( mode , lshr_optab , op1 , t6 , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; t3 = expand_binop ( mode , lshr_optab , op2 , t6 , NULL , <NUM_LIT> , OPTAB_DIRECT ) ; t4 = gen_reg_rtx ( mode ) ; t5 = gen_reg_rtx ( mode ) ; emit_insn ( umul ( t4 , gen_lowpart ( nmode , t2 ) , gen_lowpart ( nmode , op2 ) ) ) ; emit_insn ( umul ( t5 , gen_lowpart ( nmode , t3 ) , gen_lowpart ( nmode , op1 ) ) ) ; t4 = expand_binop ( mode , add_optab , t4 , t5 , t4 , <NUM_LIT> , OPTAB_DIRECT ) ; t4 = expand_binop ( mode , ashl_optab , t4 , t6 , t4 , <NUM_LIT> , OPTAB_DIRECT ) ; force_expand_binop ( mode , add_optab , t1 , t4 , op0 , <NUM_LIT> , OPTAB_DIRECT ) ;


<s> BranchCode = getOppositeCondition ( BranchCode ) ; unsigned JNCC = getBrCond ( BranchCode ) . getOpcode ( ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) {


<s> const MachineOperand & Disp = MI -> getOperand ( OpNum + <NUM_LIT> ) ; if ( Base . isGlobal ( ) ) printOperand ( MI , OpNum , <STR_LIT> ) ; else if ( Disp . isImm ( ) && ! Base . getReg ( ) ) printOperand ( MI , OpNum ) ; else if ( Base . getReg ( ) ) { if ( Disp . getImm ( ) ) {

printOperand ( MI , OpNum + <NUM_LIT> , <STR_LIT> ) ;


<s> case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; isLoad = false ; isLaneOp = true ; break ; } } else { isLaneOp = true ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; NumVecs = <NUM_LIT> ; break ; } } EVT VecTy ; if ( isLoad ) VecTy = N -> getValueType ( <NUM_LIT> ) ; else VecTy = N -> getOperand ( AddrOpIdx + <NUM_LIT> ) . getValueType ( ) ; unsigned NumBytes = NumVecs * VecTy . getSizeInBits ( ) / <NUM_LIT> ; if ( isLaneOp ) NumBytes /= VecTy . getVectorNumElements ( ) ; SDValue Inc = User -> getOperand ( User -> getOperand ( <NUM_LIT> ) == Addr ? <NUM_LIT> : <NUM_LIT> ) ; if ( ConstantSDNode * CInc = dyn_cast < ConstantSDNode > ( Inc . getNode ( ) ) ) { uint32_t IncVal = CInc -> getZExtValue ( ) ; if ( IncVal != NumBytes ) continue ; Inc = DAG . getTargetConstant ( IncVal , <STR_LIT> ) ; } EVT Tys [ <NUM_LIT> ] ;

unsigned NumResultVecs = ( isLoad ? NumVecs : <NUM_LIT> ) ;


<s> IsV1Zeroable = false ; break ; } SDValue V2S = getScalarValueForVectorElement ( V2 , Mask [ V2Index ] - Mask . size ( ) , DAG ) ; if ( V2S && DAG . getTargetLoweringInfo ( ) . isTypeLegal ( V2S . getValueType ( ) ) ) { V2S = DAG . getBitcast ( EltVT , V2S ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { if ( ! IsV1Zeroable ) return SDValue ( ) ; ExtVT = <STR_LIT> ; V2S = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2S ) ; } V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2S ) ; } else if ( Mask [ V2Index ] != ( int ) Mask . size ( ) || EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { return SDValue ( ) ; } if ( ! IsV1Zeroable ) { assert ( VT == ExtVT && <STR_LIT> ) ; if ( ! VT . isFloatingPoint ( ) || V2Index != <NUM_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > V1Mask ( Mask . begin ( ) , Mask . end ( ) ) ; V1Mask [ V2Index ] = - <NUM_LIT> ; if ( ! isNoopShuffleMask ( V1Mask ) ) return SDValue ( ) ; if ( Subtarget . hasSSE41 ( ) ) return SDValue ( ) ; assert ( ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) && <STR_LIT> ) ; return DAG . getNode ( EltVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> , DL , ExtVT , V1 , V2 ) ; } if ( VT . isFloatingPoint ( ) && V2Index != <NUM_LIT> ) return SDValue ( ) ;

V2 = DAG . getNode ( <STR_LIT> , DL , ExtVT , V2 ) ;


<s> LLVM_DEBUG ( errs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( SI . dump ( ) ) ; BuildMI ( * SI . getParent ( ) , SI , SI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addReg ( SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( * SI . getParent ( ) , SI , SI . getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , SI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( <STR_LIT> ) ;


<s> type = TYPE_MOFFS32 ; break ; case <NUM_LIT> : type = TYPE_MOFFS64 ; break ; } } else if ( type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || type == TYPE_IMM64 ) { uint32_t Opcode = mcInst . getOpcode ( ) ; switch ( operand . encoding ) { default : break ; case ENCODING_IB : if ( Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> && Opcode != <STR_LIT> ) type = TYPE_MOFFS8 ; break ; case ENCODING_IW : type = TYPE_MOFFS16 ; break ; case ENCODING_ID : type = TYPE_MOFFS32 ; break ; case ENCODING_IO :


<s> Inst . addOperand ( MCOperand :: createImm ( getImm ( ) ) ) ;


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override {


<s> Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; result = decodeInstruction ( DecoderTableVFP32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; UpdateThumbVFPPredicate ( MI ) ; return result ; } } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; result = decodeInstruction ( DecoderTableNEONDup32 , MI , insn32 , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; uint32_t NEONLdStInsn = insn32 ; NEONLdStInsn &= <NUM_LIT> ; NEONLdStInsn |= <NUM_LIT> ; result = decodeInstruction ( DecoderTableNEONLoadStore32 , MI , NEONLdStInsn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ; return result ; } } if ( fieldFromInstruction ( insn32 , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { MI . clear ( ) ; uint32_t NEONDataInsn = insn32 ; NEONDataInsn &= <NUM_LIT> ; NEONDataInsn |= ( NEONDataInsn & <NUM_LIT> ) >> <NUM_LIT> ; NEONDataInsn |= <NUM_LIT> ; result = decodeInstruction ( DecoderTableNEONData32 , MI , NEONDataInsn , Address , this , STI ) ; if ( result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; Check ( result , AddThumbPredicate ( MI ) ) ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> ) , STI ( STI ) {


<s> ShuffMask . push_back ( I + VecLen ) ; } VectorPair P = opSplit ( opCastElem ( M , ElemTy , DAG ) , dl , DAG ) ; return getByteShuffle ( dl , P . first , P . second , ShuffMask , DAG ) ; } case <STR_LIT> : { SDValue S16 = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue T0 = getNode ( <STR_LIT> , dl , ResTy , { Vs , Vt } , DAG ) ; SDValue T1 = getNode ( <STR_LIT> , dl , ResTy , { T0 , S16 } , DAG ) ; SDValue T2 = getNode ( <STR_LIT> , dl , ResTy , { T1 , Vs , Vt } , DAG ) ; return T2 ; } default :


<s> void setCPR1SizeFromPredicates ( const PredicateLibrary & P ) { if ( P . mipsSEUsesSoftFloat ( ) ) CPR1Size = AFL_REG_NONE ; else if ( P . hasMSA ( ) ) CPR1Size = AFL_REG_128 ;

else CPR1Size = P . isFP64bit ( ) ? AFL_REG_64 : AFL_REG_32 ;


gsi_insert_seq_before ( gsi , latch_seq , GSI_SAME_STMT ) ;


<s> rtx swap_reg = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; gcc_assert ( REG_P ( dest_address ) || rs6000_sum_of_two_registers_p ( dest_address ) ) ; struct df_insn_info * insn_info = DF_INSN_INFO_GET ( store_insn ) ; df_ref use ; rtx_insn * swap_insn = NULL ; unsigned uid2 = <NUM_LIT> ; FOR_EACH_INSN_INFO_USE ( use , insn_info ) { struct df_link * def_link = DF_REF_CHAIN ( use ) ; if ( ! rtx_equal_p ( DF_REF_REG ( use ) , swap_reg ) ) continue ; gcc_assert ( def_link && def_link -> ref && ! def_link -> next && ! DF_REF_IS_ARTIFICIAL ( def_link -> ref ) ) ; swap_insn = DF_REF_INSN ( def_link -> ref ) ; uid2 = INSN_UID ( swap_insn ) ; gcc_assert ( insn_entry [ uid2 ] . is_swap && ! insn_entry [ uid2 ] . is_load && ! insn_entry [ uid2 ] . is_store ) ; break ; } gcc_assert ( swap_insn ) ; rtx set = single_set ( store_insn ) ; gcc_assert ( set ) ; rtx dest_exp = SET_DEST ( set ) ; rtx src_exp = XEXP ( SET_SRC ( body ) , <NUM_LIT> ) ; enum machine_mode mode = GET_MODE ( dest_exp ) ; gcc_assert ( MEM_P ( dest_exp ) ) ; gcc_assert ( MEM_ALIGN ( dest_exp ) >= <NUM_LIT> ) ; rtx stvx ; stvx = rs6000_gen_stvx ( mode , dest_exp , src_exp ) ; rtx_insn * new_insn = emit_insn_before ( stvx , store_insn ) ; rtx new_body = PATTERN ( new_insn ) ;

gcc_assert ( ( GET_CODE ( new_body ) == SET ) && MEM_P ( SET_DEST ( new_body ) ) ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> if ( Printer . TM . getTargetTriple ( ) . isOSDarwin ( ) ) return lowerSymbolOperandDarwin ( MO , Sym ) ; if ( Printer . TM . getTargetTriple ( ) . isOSBinFormatCOFF ( ) ) return lowerSymbolOperandCOFF ( MO , Sym ) ; assert ( Printer . TM . getTargetTriple ( ) . isOSBinFormatELF ( ) && <STR_LIT> ) ;

return lowerSymbolOperandELF ( MO , Sym ) ;


<s> return ( uint64x1_t ) { vcvtad_u64_f64 ( __a [ <NUM_LIT> ] ) } ;


<s> Value * <ISA_LIT>IREmitter :: visitVZIP ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> if ( std :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ; MachineBasicBlock * NextBB = & * std :: next ( MBBI ) ;

return llvm :: is_contained ( MBB -> successors ( ) , NextBB ) ;


<s> unsigned getRegisterListOpValue ( const MachineInstr & MI , unsigned Op ) const {


<s> bool EvexToVexInstPass :: CompressEvexToVexImpl ( MachineInstr & MI ) const { const MCInstrDesc & Desc = MI . getDesc ( ) ; if ( ( Desc . TSFlags & <STR_LIT> ) != <STR_LIT> ) return false ; if ( Desc . TSFlags & ( <STR_LIT> | <STR_LIT> ) ) return false ; if ( Desc . TSFlags & <STR_LIT> ) return false ; static std :: atomic < bool > TableChecked ( false ) ; if ( ! TableChecked . load ( std :: memory_order_relaxed ) ) { assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex128CompressTable ) && <STR_LIT> ) ; assert ( llvm :: is_sorted ( <ISA_LIT>EvexToVex256CompressTable ) && <STR_LIT> ) ; TableChecked . store ( true , std :: memory_order_relaxed ) ; } ArrayRef < <ISA_LIT>EvexToVexCompressTableEntry > Table = ( Desc . TSFlags & <STR_LIT> ) ? makeArrayRef ( <ISA_LIT>EvexToVex256CompressTable ) : makeArrayRef ( <ISA_LIT>EvexToVex128CompressTable ) ; const auto * I = llvm :: lower_bound ( Table , MI . getOpcode ( ) ) ; if ( I == Table . end ( ) || I -> EvexOpcode != MI . getOpcode ( ) ) return false ; unsigned NewOpc = I -> VexOpcode ;

if ( usesExtendedRegister ( MI ) ) return false ;


<s> } if ( Addr . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = <NUM_LIT> ; if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> && CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , <STR_LIT> ) ; return true ;


<s> if ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getNode ( ) -> hasOneUse ( ) ) { SDValue Result = combineSelectAndUse ( N , N1 , N0 , DCI ) ; if ( Result . getNode ( ) ) return Result ;


<s> if ( blocks [ i ] -> getMBB ( ) == MBB ) {

return ! Priv -> LRs . at ( pred ) . hasDefBefore ( i ) ;


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; printOperand ( MI , OpNo , O ) ;


<s> SMLoc ExprLoc = getLexer ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( Value ) ) return false ; if ( const auto * MCE = dyn_cast < MCConstantExpr > ( Value ) ) { assert ( Size <= <NUM_LIT> && <STR_LIT> ) ; uint64_t IntValue = MCE -> getValue ( ) ; if ( ! isUIntN ( <NUM_LIT> * Size , IntValue ) && ! isIntN ( <NUM_LIT> * Size , IntValue ) ) return Error ( ExprLoc , <STR_LIT> ) ; getStreamer ( ) . EmitIntValue ( IntValue , Size ) ;


<s> if ( Subtarget . isGVIndirectSymbol ( GV ) ) { MIB = BuildMI ( MBB , MI , DL , get ( LoadOpc ) , Reg ) ; MIB . addReg ( Reg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ; unsigned Flag = MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant ; MachineMemOperand * MMO = MBB . getParent ( ) -> getMachineMemOperand ( MachinePointerInfo :: getGOT ( * MBB . getParent ( ) ) , Flag , <NUM_LIT> , <NUM_LIT> ) ; MIB . addMemOperand ( MMO ) ; AddDefaultPred ( MIB ) ;