<s> return <NUM_LIT> ; } unsigned Opcode = <NUM_LIT> ; int Offs = cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getSExtValue ( ) ; switch ( VT . SimpleTy ) { case <STR_LIT> : { if ( Offs != <NUM_LIT> ) { return <NUM_LIT> ; } Opcode = <STR_LIT> ; break ; } case <STR_LIT> : { if ( Offs != <NUM_LIT> ) { return <NUM_LIT> ; } Opcode = <STR_LIT> ;


<s> const int buf_size = <NUM_LIT> ; char float_buf [ buf_size ] = { } ; real_to_decimal_for_mode ( float_buf , CONST_DOUBLE_REAL_VALUE ( info . value ) , buf_size , buf_size , <NUM_LIT> , info . elt_mode ) ; snprintf ( templ , sizeof ( templ ) , <STR_LIT> , element_char , float_buf ) ; return templ ; } }

snprintf ( templ , sizeof ( templ ) , <STR_LIT> HOST_WIDE_INT_PRINT_DEC , element_char , INTVAL ( info . value ) ) ;


<s> if ( Reg == <STR_LIT> && PMFI . getS0SpillReg ( ) ) { TII . copyPhysReg ( MBB , MI , DL , PMFI . getS0SpillReg ( ) , Reg , true ) ; std :: prev ( MI ) -> setFlag ( MachineInstr :: FrameSetup ) ; continue ; } if ( <STR_LIT> . contains ( Reg ) ) { TII . copyPhysReg ( MBB , MI , DL , <STR_LIT> , Reg , true ) ; std :: prev ( MI ) -> setFlag ( MachineInstr :: FrameSetup ) ; Reg = <STR_LIT> ; } const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CSI [ i - <NUM_LIT> ] . getFrameIdx ( ) , RC , TRI ) ; std :: prev ( MI ) -> setFlag ( MachineInstr :: FrameSetup ) ; spilledSize += <NUM_LIT> ; }


<s> GPR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; FGR32RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; FGR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; AFGR64RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ; MSA128BRegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ;

COP2RegClass = & ( TRI -> getRegClass ( <STR_LIT> ) ) ;


<s> AU . addRequired < AAResultsWrapperPass > ( ) ; AU . addPreserved < AAResultsWrapperPass > ( ) ;

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> return ( uint16x4_t ) __builtin_aarch64_addhnv4si ( ( int32x4_t ) __a , ( int32x4_t ) __b ) ;


<s> virtual ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> unsigned Size = getIntelMemOperandSize ( Tok . getString ( ) ) ; if ( Size ) { Parser . Lex ( ) ; if ( Tok . getString ( ) != <STR_LIT> && Tok . getString ( ) != <STR_LIT> ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; } Start = Tok . getLoc ( ) ; if ( getLexer ( ) . is ( AsmToken :: Integer ) || getLexer ( ) . is ( AsmToken :: Minus ) || getLexer ( ) . is ( AsmToken :: LParen ) ) { AsmToken StartTok = Tok ; IntelExprStateMachine SM ( <NUM_LIT> , true , false ) ; if ( <ISA_LIT>Operand * Err = ParseIntelExpression ( SM , End ) ) return Err ; int64_t Imm = SM . getImm ( ) ; if ( isParsingInlineAsm ( ) ) { unsigned Len = Tok . getLoc ( ) . getPointer ( ) - Start . getPointer ( ) ; if ( StartTok . getString ( ) . size ( ) == Len ) InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_ImmPrefix , Start ) ) ; else InstInfo -> AsmRewrites -> push_back ( AsmRewrite ( AOK_Imm , Start , Len , Imm ) ) ; } if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) { const MCExpr * ImmExpr = MCConstantExpr :: Create ( Imm , getContext ( ) ) ; return <STR_LIT> ( ImmExpr , Start , End ) ; }

if ( Imm < <NUM_LIT> ) return ErrorOperand ( Start , <STR_LIT> <STR_LIT> ) ;


<s> static LegalityPredicate isSmallOddVector ( unsigned TypeIdx ) { return [ = ] ( const LegalityQuery & Query ) {

const LLT Ty = Query . Types [ TypeIdx ] ;


<s> case <STR_LIT> : return std :: make_tuple ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstantFP ( <NUM_LIT> , DL , EltVT ) ) ; case <STR_LIT> : return std :: make_tuple ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return std :: make_tuple ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getNeutralElement ( BaseOpcode , DL , EltVT , Flags ) ) ; case <STR_LIT> : return std :: make_tuple ( <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getNeutralElement ( BaseOpcode , DL , EltVT , Flags ) ) ; }


<s> static void processShaderInputArgs ( SmallVectorImpl < <STR_LIT> > & Splits , CallingConv :: ID CallConv , ArrayRef < <STR_LIT> > Ins , BitVector & Skipped , FunctionType * FType , <ISA_LIT>MachineFunctionInfo * Info ) { for ( unsigned I = <NUM_LIT> , E = Ins . size ( ) , P<ISA_LIT>nputNum = <NUM_LIT> ; I != E ; ++ I ) { const <STR_LIT> * Arg = & Ins [ I ] ; assert ( ( ! Arg -> VT . isVector ( ) || Arg -> VT . getScalarSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( CallConv == CallingConv :: <ISA_LIT>_PS && ! Arg -> Flags . isInReg ( ) && P<ISA_LIT>nputNum <= <NUM_LIT> ) { bool SkipArg = ! Arg -> Used && ! Info -> isP<ISA_LIT>nputAllocated ( P<ISA_LIT>nputNum ) ; if ( Arg -> Flags . isSplit ( ) ) { while ( ! Arg -> Flags . isSplitEnd ( ) ) { assert ( ( ! Arg -> VT . isVector ( ) || Arg -> VT . getScalarSizeInBits ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( ! SkipArg ) Splits . push_back ( * Arg ) ; Arg = & Ins [ ++ I ] ; } } if ( SkipArg ) { Skipped . set ( Arg -> getOrigArgIndex ( ) ) ; ++ P<ISA_LIT>nputNum ;


<s> loongarch_function_arg_advance ( pack_cumulative_args ( & local_cum ) , arg ) ; gp_saved = MAX_ARGS_IN_REGISTERS - local_cum . num_gprs ; if ( ! no_rtl && gp_saved > <NUM_LIT> ) { rtx ptr = plus_constant ( Pmode , virtual_incoming_args_rtx , REG_PARM_STACK_SPACE ( cfun -> decl ) - gp_saved * UNITS_PER_WORD ) ; rtx mem = gen_frame_mem ( BLKmode , ptr ) ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; move_block_from_reg ( local_cum . num_gprs + GP_ARG_FIRST , mem , gp_saved ) ; } if ( REG_PARM_STACK_SPACE ( cfun -> decl ) == <NUM_LIT> ) cfun -> machine -> varargs_size = gp_saved * UNITS_PER_WORD ;


<s> unsigned NumVectors = getNumVectorRegs ( Tp ) ; if ( Tp -> getScalarType ( ) -> isFP128Ty ( ) ) return ( Kind == TargetTransformInfo :: SK_Broadcast ? NumVectors - <NUM_LIT> : <NUM_LIT> ) ; switch ( Kind ) {

case TargetTransformInfo :: SK_ExtractSubvector :


<s> void BT :: run ( ) { reset ( ) ; assert ( FlowQ . empty ( ) ) ; using MachineFlowGraphTraits = GraphTraits < const MachineFunction * > ; const MachineBasicBlock * Entry = MachineFlowGraphTraits :: getEntryNode ( & MF ) ; unsigned MaxBN = <NUM_LIT> ;

for ( const MachineBasicBlock & B : MF ) {


<s> EVT CopyVT = VA . getLocVT ( ) ; Chain = DAG . getCopyFromReg ( Chain , DL , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue Val = Chain . getValue ( <NUM_LIT> ) ; if ( VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ;

InFlag = Chain . getValue ( <NUM_LIT> ) ;


<s> for ( auto I = MRI . use_begin ( FromReg ) , E = MRI . use_end ( ) ; I != E ; ) { MachineOperand & O = * I ++ ; MachineInstr * Where = O . getParent ( ) ; if ( Where -> getOpcode ( ) == TargetOpcode :: PHI ) { MachineBasicBlock * Pred = Where -> getOperand ( & O - & Where -> getOperand ( <NUM_LIT> ) + <NUM_LIT> ) . getMBB ( ) ; if ( ! MDT . dominates ( & MBB , Pred ) ) continue ; } else { if ( & MI == Where || ! MDT . dominates ( & MI , Where ) ) continue ; } Changed = true ; DEBUG ( dbgs ( ) << <STR_LIT> << O << <STR_LIT> << * Where << <STR_LIT> << MI << <STR_LIT> ) ; O . setReg ( ToReg ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isDead ( ) && <STR_LIT> ) ;


<s> AddPromotedToType ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> unsigned <ISA_LIT>TargetLowering :: getNumInterleavedAccesses ( VectorType * VecTy , const DataLayout & DL , bool UseScalable ) const { unsigned VecSize = UseScalable ? Subtarget -> getMinSVEVectorSizeInBits ( ) : <NUM_LIT> ; return std :: max < unsigned > ( <NUM_LIT> , ( DL . getTypeSizeInBits ( VecTy ) + <NUM_LIT> ) / VecSize ) ;


<s> if ( ! isImm ( ) ) return false ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ;


<s> <ISA_LIT>ELFStreamer ( MCContext & C , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > MOW , std :: unique_ptr < MCCodeEmitter > MCE ) : MCELFStreamer ( C , std :: move ( MAB ) , std :: move ( MOW ) , std :: move ( MCE ) ) {


<s> if ( ! CurrCycleInstr ) return ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned NumWaitStates = TII -> getNumWaitStates ( * CurrCycleInstr ) ; EmittedInstrs . push_front ( CurrCycleInstr ) ; for ( unsigned i = <NUM_LIT> , e = std :: min ( NumWaitStates , getMaxLookAhead ( ) ) ;


<s> static void rs6000_secondary_reload_fail ( int line , rtx reg , rtx mem , rtx scratch , bool store_p ) { rs6000_secondary_reload_trace ( line , reg , mem , scratch , store_p ) ;


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { storeRegPairToStackSlot ( getRegisterInfo ( ) , MBB , MBBI , get ( <STR_LIT> ) , SrcReg , isKill , <STR_LIT> , <STR_LIT> , FI , MMO ) ; return ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; case <NUM_LIT> : if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasNEON ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; Offset = false ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { assert ( Subtarget . hasSVE ( ) && <STR_LIT> ) ; Opc = <STR_LIT> ; StackID = TargetStackID :: ScalableVector ; } break ; } assert ( Opc && <STR_LIT> ) ; MFI . setStackID ( FI , StackID ) ; const MachineInstrBuilder MI = BuildMI ( MBB , MBBI , DebugLoc ( ) , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) ;

if ( Offset ) MI . addImm ( <NUM_LIT> ) ;


<s> ScheduleDAGInstrs * createPostMachineScheduler ( MachineSchedContext * C ) const override { const <ISA_LIT>Subtarget & ST = C -> MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( ST . use<ISA_LIT>PostRASchedStrategy ( ) ) return create<ISA_LIT>PostMachineScheduler ( C ) ; return nullptr ;


<s> TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; assert ( isLeafProc ( MF ) && <STR_LIT> ) ;


<s> if ( MIa -> hasUnmodeledSideEffects ( ) || MIb -> hasUnmodeledSideEffects ( ) ) return false ; if ( MIa -> hasOrderedMemoryRef ( ) || MIb -> hasOrderedMemoryRef ( ) ) return false ; if ( isDS ( * MIa ) ) { if ( isDS ( * MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( * MIb ) ; } if ( isMUBUF ( * MIa ) || isMTBUF ( * MIa ) ) { if ( isMUBUF ( * MIb ) || isMTBUF ( * MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( * MIb ) && ! isSMRD ( * MIb ) ; } if ( isSMRD ( * MIa ) ) { if ( isSMRD ( * MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ; return ! isFLAT ( * MIb ) && ! isMUBUF ( * MIa ) && ! isMTBUF ( * MIa ) ; } if ( isFLAT ( * MIa ) ) { if ( isFLAT ( * MIb ) ) return checkInstOffsetsDoNotOverlap ( MIa , MIb ) ;


<s> SDVTList VTs = DAG . getVTList ( PtrVT , <STR_LIT> , <STR_LIT> ) ; SDValue End = DAG . getNode ( <STR_LIT> , DL , VTs , Chain , Limit , Src , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> return SelectAddrModeUnscaled ( N , <NUM_LIT> , Base , OffImm ) ;


<s> BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } else { cerr << <STR_LIT> << FrameSize << <STR_LIT> ; abort ( ) ; } if ( hasDebugInfo ) { std :: vector < MachineMove > & Moves = MMI -> getFrameMoves ( ) ; MachineLocation SPDst ( MachineLocation :: VirtualFP ) ; MachineLocation SPSrc ( MachineLocation :: VirtualFP , - FrameSize ) ; Moves . push_back ( MachineMove ( FrameLabelId , SPDst , SPSrc ) ) ; const std :: vector < CalleeSavedInfo > & CSI = MFI -> getCalleeSavedInfo ( ) ; for ( unsigned I = <NUM_LIT> , E = CSI . size ( ) ; I != E ; ++ I ) { int Offset = MFI -> getObjectOffset ( CSI [ I ] . getFrameIdx ( ) ) ; unsigned Reg = CSI [ I ] . getReg ( ) ; if ( Reg == <STR_LIT> ) continue ; MachineLocation CSDst ( MachineLocation :: VirtualFP , Offset ) ; MachineLocation CSSrc ( Reg ) ; Moves . push_back ( MachineMove ( FrameLabelId , CSDst , CSSrc ) ) ; } unsigned ReadyLabelId = MMI -> NextLabelID ( ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addImm ( ReadyLabelId ) ; MachineLocation FPDst ( <STR_LIT> ) ; MachineLocation FPSrc ( MachineLocation :: VirtualFP ) ; Moves . push_back ( MachineMove ( ReadyLabelId , FPDst , FPSrc ) ) ;


<s> OffsetStride = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OffsetStride = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : OffsetStride = <NUM_LIT> ; break ; } if ( Offset % OffsetStride != <NUM_LIT> ) return false ; Offset /= OffsetStride ;


<s> MachineFunction :: iterator MBBI = ++ OrigBB -> getIterator ( ) ; MF -> insert ( MBBI , NewBB ) ; NewBB -> splice ( NewBB -> end ( ) , OrigBB , MI , OrigBB -> end ( ) ) ; BuildMI ( OrigBB , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addMBB ( NewBB ) ; ++ NumSplit ; NewBB -> transferSuccessors ( OrigBB ) ; OrigBB -> addSuccessor ( NewBB ) ; MF -> RenumberBlocks ( NewBB ) ; BBInfo . insert ( BBInfo . begin ( ) + NewBB -> getNumber ( ) , BasicBlockInfo ( ) ) ;

water_iterator IP = std :: lower_bound ( WaterList . begin ( ) , WaterList . end ( ) , OrigBB , CompareMBBNumbers ) ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new TargetPassConfig ( * this , PM ) ;


<s> case <STR_LIT> : return getReductionSDNode ( <STR_LIT> , dl , Op , DAG ) ; case <STR_LIT> : return getReductionSDNode ( <STR_LIT> , dl , Op , DAG ) ; case <STR_LIT> : return getReductionSDNode ( <STR_LIT> , dl , Op , DAG ) ; case <STR_LIT> : { return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } case <STR_LIT> : { return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , DAG . getConstant ( <STR_LIT> , dl , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } default : llvm_unreachable ( <STR_LIT> ) ; }


<s> return decodeRegisterClass ( Inst , RegNo , <STR_LIT> , <NUM_LIT> ) ;


<s> <ISA_LIT>VectorConstantInfo :: <ISA_LIT>VectorConstantInfo ( BuildVectorSDNode * BVN ) { assert ( BVN -> isConstant ( ) && <STR_LIT> ) ;


<s> if ( rx_pid_data_operand ( op ) == PID_UNENCODED ) { if ( GET_CODE ( op ) == MEM ) { rtx a = gen_pid_addr ( gen_rtx_REG ( SImode , rx_pid_base_regnum ( ) ) , XEXP ( op , <NUM_LIT> ) ) ; op = replace_equiv_address ( op , a ) ;


<s> BBUtils = std :: unique_ptr < <ISA_LIT>BasicBlockUtils > ( new <ISA_LIT>BasicBlockUtils ( MF ) ) ; MF . RenumberBlocks ( ) ; BBUtils -> computeAllBlockSizes ( ) ; BBUtils -> adjustBBOffsetsAfter ( & MF . front ( ) ) ; bool Changed = false ; for ( auto * ML : * MLI ) Changed |= processPostOrderLoops ( ML ) ; return Changed ;


<s> llvm_unreachable ( <STR_LIT> ) ; } } } else { for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) { <ISA_LIT>Operand & Op = ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) ; if ( Op . isMod ( ) ) { OptionalIdx [ Op . getImmTy ( ) ] = I ; } else { Op . addRegOrImmOperands ( Inst , <NUM_LIT> ) ; } } } if ( <STR_LIT> ( Opc , <STR_LIT> :: clamp ) != - <NUM_LIT> ) { addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyClamp<ISA_LIT> ) ; } if ( <STR_LIT> ( Opc , <STR_LIT> :: omod ) != - <NUM_LIT> ) { addOptionalImmOperand ( Inst , Operands , OptionalIdx , <ISA_LIT>Operand :: ImmTyOMod<ISA_LIT> ) ; } if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) { auto it = Inst . begin ( ) ; std :: advance ( it , <STR_LIT> ( Opc , <STR_LIT> :: src2_modifiers ) ) ; it = Inst . insert ( it , MCOperand :: createImm ( <NUM_LIT> ) ) ; ++ it ; Inst . insert ( it , Inst . getOperand ( <NUM_LIT> ) ) ; }


<s> if ( GENERAL_REGNO_P ( regno ) ) return SImode ; else if ( SSE_REGNO_P ( regno ) ) return V4SFmode ; else if ( MASK_REGNO_P ( regno ) ) return HImode ; else if ( MMX_REGNO_P ( regno ) ) return V2SImode ; else gcc_unreachable ( ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const AMDGPUFrameLowering * TFL = static_cast < const AMDGPUFrameLowering * > ( getTargetMachine ( ) . getSubtargetImpl ( ) -> getFrameLowering ( ) ) ;

FrameIndexSDNode * FIN = cast < FrameIndexSDNode > ( Op ) ;


<s> MCSectionELF * KernelInfoSection = getContext ( ) . getELFSection ( KernelInfoSectionName , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ; KernelInfoSection -> getFragmentList ( ) . clear ( ) ; MCDataFragment * Fragment = new MCDataFragment ( KernelInfoSection ) ; StringRef BareFileName = llvm :: sys :: path :: stem ( RootFileName ) ; std :: string KernelInfo = GenerateKernelInfo ( BareFileName ) ; Fragment -> getContents ( ) . append ( KernelInfo . begin ( ) , KernelInfo . end ( ) ) ; Fragment -> setAlignToBundleEnd ( true ) ; Out . SwitchSection ( KernelInfoSection ) ; Out . PopSection ( ) ; } if ( IndexMap ) { Out . PushSection ( ) ;

MCSectionELF * IndexMapSection = getContext ( ) . getELFSection ( IndexMapSectionName , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC ) ;


<s> bool isDOT ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> PCSymbol = <STR_LIT> ; CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ; if ( ! is64Bit ) Data64bitsDirective = <NUM_LIT> ; AssemblerDialect = <NUM_LIT> ; SupportsDebugInformation = true ;


<s> <ISA_LIT>CodeEmitter ( TargetMachine & tm , MachineCodeEmitter & mce , const <ISA_LIT>InstrInfo & ii ) : MachineFunctionPass ( & ID ) , II ( & ii ) , TM ( tm ) , MCE ( mce ) {


<s> void printS10ImmOperand ( const MachineInstr * MI , unsigned OpNo ) {

short value = ( short ) ( ( ( int ) MI -> getOperand ( OpNo ) . getImm ( ) << <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> uint64x2_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , PTXVersion ( <NUM_LIT> ) , SmVersion ( <NUM_LIT> ) , TM ( TM ) , InstrInfo ( ) , TLInfo ( TM , initializeSubtargetDependencies ( CPU , FS ) ) , FrameLowering ( ) {


<s> uint64_t Len = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) - <NUM_LIT> ; assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) && isUInt < <NUM_LIT> > ( Len ) ) ; return ( Len << <NUM_LIT> ) | ( Base << <NUM_LIT> ) | Disp ;


<s> if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t i = <NUM_LIT> ; i < Count ; i += <NUM_LIT> ) <STR_LIT> :: write < uint32_t > ( OS , <NUM_LIT> , Endian ) ;


<s> return IRB . CreatePointerCast ( IRB . CreateConstGEP1_32 ( IRB . CreateCall ( ThreadPointerFunc ) , TlsOffset ) , Type :: getInt8PtrTy ( IRB . getContext ( ) ) -> getPointerTo ( <NUM_LIT> ) ) ;


<s> Stubs = MMIMacho . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer -> SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( * OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer -> AddBlankLine ( ) ; } SM . serializeToStackMapSection ( ) ; FM . serializeToFaultMapSection ( ) ; OutStreamer -> EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( TT . isKnownWindowsMSVCEnvironment ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = ( TT . getArch ( ) == Triple :: x86_64 ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . getOrCreateSymbol ( SymbolName ) ; OutStreamer -> EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( TT . isOSBinFormatCOFF ( ) ) { SM . serializeToStackMapSection ( ) ; } if ( TT . isOSBinFormatELF ( ) ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> static Optional < <ISA_LIT>BitmanipPat > matchSHFLPat ( SDValue Op ) { static const uint64_t BitmanipMasks [ ] = {


<s> switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'L' :

if ( ! MI -> getOperand ( OpNo ) . isReg ( ) || OpNo + <NUM_LIT> == MI -> getNumOperands ( ) || ! MI -> getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) return true ;


<s> if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_i ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_o ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_v ; else if ( ConstraintCode == <STR_LIT> ) return InlineAsm :: Constraint_X ;

return TargetLowering :: getInlineAsmMemConstraint ( ConstraintCode ) ;


<s> return e . use_exact_insn ( code_for_while ( m_unspec , Pmode , e . gp_mode ( <NUM_LIT> ) ) ) ;


<s> EVT Evt = TLI . getValueType ( Ty , true ) ; if ( Evt == <STR_LIT> || ! Evt . isSimple ( ) ) return false ;


<s> void initializePass ( ) override { pushTTIStack ( this ) ;


<s> } else { if ( ( ( I + <NUM_LIT> ) >= ( AddrIdx + NumVAddrs ) ) || ( ( NumGradients / <NUM_LIT> ) % <NUM_LIT> == <NUM_LIT> && ( I == DimIdx + ( NumGradients / <NUM_LIT> ) - <NUM_LIT> || I == DimIdx + NumGradients - <NUM_LIT> ) ) ) { PackedAddrs . push_back ( B . buildBuildVector ( V2S16 , { AddrReg , B . buildUndef ( S16 ) . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ) ; } else {

PackedAddrs . push_back ( B . buildBuildVector ( V2S16 , { AddrReg , MI . getOperand ( I + <NUM_LIT> ) . getReg ( ) } ) . getReg ( <NUM_LIT> ) ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T , StringRef CPU ) : MCAsmBackend ( ) , CPU ( CPU ) , MaxNopLength ( ( CPU == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ) {

HasNopl = CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> && CPU != <STR_LIT> ;


<s> <STR_LIT> ( AMDGPUSubtarget * ST ) : AMDGPU7XXDevice ( ST ) {


<s> return isInlinableImm ( ) || ( isReg ( ) && isRegClass ( <STR_LIT> ) ) ;


<s> if ( TT . isOSBinFormatELF ( ) ) return make_unique < TargetLoweringObjectFileELF > ( ) ; if ( TT . isKnownWindowsMSVCEnvironment ( ) ) return make_unique < <ISA_LIT>WindowsTargetObjectFile > ( ) ; if ( TT . isOSBinFormatCOFF ( ) ) return make_unique < TargetLoweringObjectFileCOFF > ( ) ;


<s> std :: vector < std :: string > modr_dmod ( Rn a , StepZIDS as ) { return D ( <STR_LIT> , MemR ( a , as ) , <STR_LIT> ) ;


<s> condition_rtx = rs6000_generate_compare ( code ) ; loc_ref = gen_rtx_LABEL_REF ( VOIDmode , loc ) ; emit_jump_insn ( gen_rtx_SET ( VOIDmode , pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , condition_rtx , loc_ref , pc_rtx ) ) ) ;


<s> Register NewBase ; int64_t NewOffset ;

if ( mi_match ( Root , MRI , m_GPtrAdd ( m_Reg ( NewBase ) , m_ICst ( NewOffset ) ) ) && isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( NewOffset ) ) {


<s> static bool isStartChunk ( uint64_t Chunk ) {

if ( Chunk == <NUM_LIT> || Chunk == std :: numeric_limits < uint64_t > :: max ( ) ) return false ;


<s> void <ISA_LIT>ELFStreamer :: EmitRegSave ( const SmallVectorImpl < unsigned > & RegList , bool IsVector ) {


<s> return any_of ( MF , [ & TII ] ( const MachineBasicBlock & MBB ) { return any_of ( MBB , [ & TII ] ( const MachineInstr & MI ) { return TII . isRVVSpill ( MI , true ) ; } ) ; } ) ;


<s> std :: swap ( Reg1 , Reg2 ) ; std :: swap ( FrameIdxReg1 , FrameIdxReg2 ) ; } MachineInstrBuilder MIB = BuildMI ( MBB , MI , DL , TII . get ( LdrOpc ) ) ; if ( RPI . isPaired ( ) ) { MIB . addReg ( Reg2 , getDefRegState ( true ) ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdxReg2 ) , MachineMemOperand :: MOLoad , Size , Align ) ) ; } MIB . addReg ( Reg1 , getDefRegState ( true ) ) . addReg ( <STR_LIT> ) . addImm ( RPI . Offset ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; MIB . addMemOperand ( MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdxReg1 ) , MachineMemOperand :: MOLoad , Size , Align ) ) ; if ( NeedsWinCFI ) InsertSEH ( MIB , TII , MachineInstr :: FrameDestroy ) ; } ; for ( const RegPairInfo & RPI : reverse ( RegPairs ) ) if ( RPI . isScalable ( ) ) EmitMI ( RPI ) ; if ( ReverseCSRRestoreSeq ) { for ( const RegPairInfo & RPI : reverse ( RegPairs ) ) if ( ! RPI . isScalable ( ) ) EmitMI ( RPI ) ; } else for ( const RegPairInfo & RPI : RegPairs ) if ( ! RPI . isScalable ( ) ) EmitMI ( RPI ) ;


<s> int64_t Val ; if ( ! isImm ( ) || ! Imm -> evaluateAsAbsolute ( Val ) ) return false ; if ( Val >= <NUM_LIT> && Val <= <NUM_LIT> ) return true ;


<s> return __builtin_mve_vcvtmq_uv8hi ( __a ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetReorder ( ) { setCanHaveModuleDir ( false ) ;


<s> if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( DecoderTable<ISA_LIT>32 , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { PostOperandDecodeAdjust ( Instr , Insn ) ; Size = <NUM_LIT> ;


<s> for ( regno = regs_info -> first ; regno <= regs_info -> last ; regno ++ ) if ( info -> save_p [ regno ] ) frv_frame_access ( accessor , info -> save_p [ regno ] == REG_SAVE_2WORDS ? gen_rtx_REG ( DImode , regno ) : gen_rtx_REG ( SImode , regno ) , info -> reg_offset [ regno ] ) ;


<s> addPass ( & <ISA_LIT>InsertSkipsPassID ) ; addPass ( create<ISA_LIT>MemoryLegalizerPass ( ) ) ;

addPass ( create<ISA_LIT>DebuggerInsertNopsPass ( ) ) ;


<s> rtx m68k_libcall_value ( machine_mode mode ) { switch ( mode ) { case E_SFmode : case E_DFmode :


<s> <ISA_LIT>IntelInstPrinter ( raw_ostream & O , const MCAsmInfo & MAI ) : MCInstPrinter ( O , MAI ) {


<s> if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && Opc == <STR_LIT> ) return true ; return false ;


<s> AMDGPUAsmBackend ( const Target & T ) : MCAsmBackend ( ) {


<s> static rtx get_vector_offset ( rtx mem , rtx element , rtx base_tmp , unsigned scalar_size ) { if ( CONST_INT_P ( element ) ) return GEN_INT ( INTVAL ( element ) * scalar_size ) ; gcc_assert ( satisfies_constraint_Q ( mem ) ) ; rtx num_ele_m1 = GEN_INT ( GET_MODE_NUNITS ( GET_MODE ( mem ) ) - <NUM_LIT> ) ; rtx and_op = gen_rtx_AND ( Pmode , element , num_ele_m1 ) ; emit_insn ( gen_rtx_SET ( base_tmp , and_op ) ) ; int shift = exact_log2 ( scalar_size ) ; gcc_assert ( shift >= <NUM_LIT> ) ; if ( shift > <NUM_LIT> ) {

rtx shift_op = gen_rtx_ASHIFT ( Pmode , base_tmp , GEN_INT ( shift ) ) ;


<s> const <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return new yaml :: <ISA_LIT>MachineFunctionInfo ( * MFI , * MF . getSubtarget ( ) . getRegisterInfo ( ) , MF ) ;


<s> return ( NONDEBUG_INSN_P ( insn ) && GET_CODE ( PATTERN ( insn ) ) != USE && GET_CODE ( PATTERN ( insn ) ) != CLOBBER ) ;


<s> } Vec = { Imm } ; if ( isSVECpyImm ( Vec . D ) ) return false ; if ( isSVEMaskOfIdenticalElements < int32_t > ( Imm ) && isSVECpyImm ( Vec . S [ <NUM_LIT> ] ) ) return false ; if ( isSVEMaskOfIdenticalElements < int16_t > ( Imm ) && isSVECpyImm ( Vec . H [ <NUM_LIT> ] ) ) return false ; if ( isSVEMaskOfIdenticalElements < int8_t > ( Imm ) && isSVECpyImm ( Vec . B [ <NUM_LIT> ] ) ) return false ;

return isLogicalImmediate ( Vec . D , <NUM_LIT> ) ;


<s> EmitSingleSection ( PTOF -> SHAREDUDATASection ( ) ) ;


<s> return sh_media_LDHI_Q ( p , <NUM_LIT> ) | sh_media_LDLO_Q ( p , <NUM_LIT> ) ; return sh_media_LDLO_Q ( p , <NUM_LIT> ) | sh_media_LDHI_Q ( p , <NUM_LIT> ) ;


<s> case GK_CYPRESS : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CYPRESS ; case GK_JUNIPER : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_JUNIPER ; case GK_REDWOOD : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_REDWOOD ; case GK_SUMO : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_SUMO ; case GK_BARTS : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_BARTS ; case GK_CAICOS : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CAICOS ; case GK_CAYMAN : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_CAYMAN ; case GK_TURKS : return ELF :: EF_AMDGPU_MACH_<ISA_LIT>_TURKS ; case GK_GFX600 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX600 ; case GK_GFX601 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX601 ; case GK_GFX602 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX602 ; case GK_GFX700 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX700 ; case GK_GFX701 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX701 ; case GK_GFX702 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX702 ; case GK_GFX703 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX703 ; case GK_GFX704 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX704 ; case GK_GFX705 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX705 ; case GK_GFX801 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX801 ; case GK_GFX802 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX802 ; case GK_GFX803 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX803 ; case GK_GFX805 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX805 ; case GK_GFX810 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX810 ; case GK_GFX900 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX900 ; case GK_GFX902 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX902 ; case GK_GFX904 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX904 ; case GK_GFX906 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX906 ; case GK_GFX908 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX908 ; case GK_GFX909 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX909 ; case GK_GFX90A : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX90A ; case GK_GFX90C : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX90C ; case GK_GFX940 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX940 ; case GK_GFX1010 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1010 ;

case GK_GFX1011 : return ELF :: EF_<ISA_LIT>_MACH_AMDGCN_GFX1011 ;


<s> HOST_WIDE_INT size = arg . type_size_in_bytes ( ) ; struct loongarch_arg_info info ; CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; if ( cum != NULL ) { loongarch_get_arg_info ( & info , cum , arg . mode , arg . type , arg . named , false ) ; if ( info . num_fprs ) return false ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; if ( MBBI -> getOpcode ( ) == <STR_LIT> ) { assert ( MBBI -> getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return ; } if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasV4TOps ( ) && MBBI -> getOpcode ( ) == <STR_LIT> && ! DisableDeallocRet ) { MachineBasicBlock :: iterator BeforeJMPR = MBB . begin ( ) == MBBI ? MBBI : std :: prev ( MBBI ) ; if ( BeforeJMPR != MBBI && BeforeJMPR -> getOpcode ( ) == <STR_LIT> ) { MBB . erase ( MBBI ) ; return ; } MachineInstrBuilder MIB = BuildMI ( MBB , MBBI_end , dl , TII . get ( <STR_LIT> ) ) ; MIB -> copyImplicitOps ( * MBB . getParent ( ) , & * MBBI ) ; MBB . erase ( MBBI ) ;


<s> EmitARM64WinUnwindCode ( Win64EH :: UOP_SaveFRegX , Reg , Offset ) ;


<s> Value * VecBasePtr = Builder . CreateBitCast ( LI -> getPointerOperand ( ) , VecBasePtrTy ) ; for ( unsigned i = <NUM_LIT> ; i < NumSubVectors ; i ++ ) { Value * NewBasePtr = Builder . CreateGEP ( VecBasePtr , Builder . getInt32 ( i ) ) ; Instruction * NewLoad = Builder . CreateAlignedLoad ( NewBasePtr , LI -> getAlignment ( ) ) ; DecomposedVectors . push_back ( NewLoad ) ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; const MCInstrDesc & MCID = TII . get ( ADDriOpc ) ; MRI . constrainRegClass ( BaseReg , TII . getRegClass ( MCID , <NUM_LIT> , this , MF ) ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , Ins , DL , MCID , BaseReg ) . addFrameIndex ( FrameIdx ) . addImm ( Offset ) ;

if ( ! AFI -> isThumb1OnlyFunction ( ) ) MIB . add ( predOps ( <STR_LIT> ) ) . add ( condCodeOp ( ) ) ;


<s> } bool IsExtendedRegisterWorthFolding = isWorthFolding ( N ) ; if ( IsExtendedRegisterWorthFolding && RHS . getOpcode ( ) == <STR_LIT> && SelectExtendedSHL ( RHS , Size , true , Offset , SignExtend ) ) { Base = LHS ; DoShift = CurDAG -> getTargetConstant ( true , <STR_LIT> ) ; return true ; } if ( IsExtendedRegisterWorthFolding && LHS . getOpcode ( ) == <STR_LIT> && SelectExtendedSHL ( LHS , Size , true , Offset , SignExtend ) ) { Base = RHS ; DoShift = CurDAG -> getTargetConstant ( true , <STR_LIT> ) ; return true ; } DoShift = CurDAG -> getTargetConstant ( false , <STR_LIT> ) ; <STR_LIT> Ext = <STR_LIT> ; if ( IsExtendedRegisterWorthFolding && ( Ext = getExtendTypeForNode ( LHS , true ) ) != <STR_LIT> ) { Base = RHS ; Offset = narrowIfNeeded ( CurDAG , LHS . getOperand ( <NUM_LIT> ) ) ; SignExtend = CurDAG -> getTargetConstant ( Ext == <STR_LIT> , <STR_LIT> ) ; if ( isWorthFolding ( LHS ) ) return true ; } if ( IsExtendedRegisterWorthFolding && ( Ext = getExtendTypeForNode ( RHS , true ) ) != <STR_LIT> ) { Base = LHS ; Offset = narrowIfNeeded ( CurDAG , RHS . getOperand ( <NUM_LIT> ) ) ; SignExtend = CurDAG -> getTargetConstant ( Ext == <STR_LIT> , <STR_LIT> ) ; if ( isWorthFolding ( RHS ) ) return true ; } return false ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getSDWAVopcDstEncoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { using namespace <STR_LIT> ; uint64_t RegEnc = <NUM_LIT> ; const MCOperand & MO = MI . getOperand ( OpNo ) ; unsigned Reg = MO . getReg ( ) ;

if ( Reg != <STR_LIT> && Reg != <STR_LIT> ) {


<s> bool <ISA_LIT>InstrInfo :: isVOP2 ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


<s> virtual void getNoopForElfTarget ( MCInst & NopInst ) const { getNoopForMachoTarget ( NopInst ) ;


<s> <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , <ISA_LIT>ArchVersion ( <ISA_LIT>32 ) , <ISA_LIT>ABI ( UnknownABI ) , IsLittle ( little ) , IsSingleFloat ( false ) , IsFP64bit ( false ) , IsGP64bit ( false ) , HasVFPU ( false ) , IsLinux ( true ) , HasSEInReg ( false ) , HasCondMov ( false ) , HasSwap ( false ) , HasBitCount ( false ) , HasFPIdx ( false ) , In<ISA_LIT>16Mode ( false ) , InMicro<ISA_LIT>Mode ( false ) , HasDSP ( false ) , HasDSPR2 ( false ) , IsAndroid ( false ) , RM ( _RM ) {


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ;


<s> auto ZExt = cast < ZExtInst > ( V ) ; if ( ZExt -> getDestTy ( ) != ExtTy ) continue ; Value * Src = ZExt -> getOperand ( <NUM_LIT> ) ; if ( ZExt -> getSrcTy ( ) == ZExt -> getDestTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ZExt << <STR_LIT> ) ; ReplaceAllUsersOfWith ( ZExt , Src ) ; continue ; } if ( NewInsts . count ( Src ) && isa < TruncInst > ( Src ) && Src -> getType ( ) == OrigTy ) { auto * Trunc = cast < TruncInst > ( Src ) ; assert ( Trunc -> getOperand ( <NUM_LIT> ) -> getType ( ) == ExtTy && <STR_LIT> ) ; ReplaceAllUsersOfWith ( ZExt , Trunc -> getOperand ( <NUM_LIT> ) ) ; } } for ( auto * I : InstsToRemove ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * I << <STR_LIT> ) ; I -> dropAllReferences ( ) ; I -> eraseFromParent ( ) ; } InstsToRemove . clear ( ) ; NewInsts . clear ( ) ; TruncTysMap . clear ( ) ; Promoted . clear ( ) ;


<s> bool isMemoryRegisterOffset32 ( ) const { return isMem ( ) && Mem . Mode == RegisterOffset && ( Mem . ShiftVal == <NUM_LIT> || Mem . ShiftVal == <NUM_LIT> ) ;


<s> SDValue Orig = Ext -> getOperand ( <NUM_LIT> ) ; if ( Store -> getMemoryVT ( ) != Orig . getValueType ( ) ) return SDValue ( ) ; return DAG . getStore ( Store -> getChain ( ) , SDLoc ( Store ) , Orig , Store -> getBasePtr ( ) , Store -> getMemOperand ( ) ) ; } return SDValue ( ) ;


<s> const BasicBlockInfo & BBI = BBInfo [ U . MI -> getParent ( ) -> getNumber ( ) ] ;

unsigned KnownBits = BBI . internalKnownBits ( ) ;


<s> ( ( <ISA_LIT>Operand & ) * Operands [ I ++ ] ) . addRegOperands ( Inst , <NUM_LIT> ) ; }

for ( unsigned E = Operands . size ( ) ; I != E ; ++ I ) ( ( <ISA_LIT>Operand & ) * Operands [ I ] ) . addRegOrImmOperands ( Inst , <NUM_LIT> ) ;


<s> RegPairInfo ( ) : Reg1 ( <STR_LIT> ) , Reg2 ( <STR_LIT> ) {


<s> } if ( Addr . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = <NUM_LIT> ; if ( ( Addr . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> && CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = Addr . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , <STR_LIT> ) ; return true ; }


<s> void relaxInstruction ( const MCInst & Inst , const MCSubtargetInfo & STI , MCInst & Res ) const override {


<s> Value * <ISA_LIT>IREmitter :: visitVTST ( const SDNode * N ) { llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> static void aarch64_push_regs ( unsigned regno1 , unsigned regno2 , HOST_WIDE_INT adjustment ) { rtx_insn * insn ; machine_mode mode = ( regno1 <= R30_REGNUM ) ? E_DImode : E_DFmode ;

if ( regno2 == INVALID_REGNUM ) return aarch64_pushwb_single_reg ( mode , regno1 , adjustment ) ;


<s> void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( The<ISA_LIT>Target ) ; RegisterMCAsmParser < <ISA_LIT>AsmParser > Y ( TheThumbTarget ) ;


<s> HazardType RetVal = Hazard ; if ( isNewStore ( * MI ) ) { MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; MachineInstr * NewMI = MF -> CreateMachineInstr ( TII -> get ( TII -> getDotNewOp ( * MI ) ) , MI -> getDebugLoc ( ) ) ; if ( Resources -> canReserveResources ( * NewMI ) ) RetVal = NoHazard ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( RetVal == NoHazard ) << <STR_LIT> ) ;


<s> for ( RegisterRef I : RRs ) if ( I != RR && RegisterAggr :: isCoverOf ( I , RR , TRI ) ) RR = I ; return RR ; } ; RegisterSet MaxDF ; for ( RegisterRef I : HasDF -> second ) MaxDF . insert ( MaxCoverIn ( I , HasDF -> second ) ) ; std :: vector < RegisterRef > MaxRefs ; RegisterSet & RefB = RefM [ BA . Id ] ; for ( RegisterRef I : MaxDF ) MaxRefs . push_back ( MaxCoverIn ( I , RefB ) ) ; std :: sort ( MaxRefs . begin ( ) , MaxRefs . end ( ) ) ; auto NewEnd = std :: unique ( MaxRefs . begin ( ) , MaxRefs . end ( ) ) ; MaxRefs . erase ( NewEnd , MaxRefs . end ( ) ) ; auto Aliased = [ this , & MaxRefs ] ( RegisterRef RR , std :: vector < unsigned > & Closure ) -> bool { for ( unsigned I : Closure ) if ( alias ( RR , MaxRefs [ I ] ) ) return true ; return false ; } ; NodeList Preds ; const MachineBasicBlock * MBB = BA . Addr -> getCode ( ) ; for ( MachineBasicBlock * PB : MBB -> predecessors ( ) ) Preds . push_back ( findBlock ( PB ) ) ; while ( ! MaxRefs . empty ( ) ) { std :: vector < unsigned > ClosureIdx = { <NUM_LIT> } ; for ( unsigned i = <NUM_LIT> ; i != MaxRefs . size ( ) ; ++ i ) if ( Aliased ( MaxRefs [ i ] , ClosureIdx ) ) ClosureIdx . push_back ( i ) ; unsigned CS = ClosureIdx . size ( ) ; NodeAddr < PhiNode * > PA = newPhi ( BA ) ; for ( unsigned X = <NUM_LIT> ; X != CS ; ++ X ) { RegisterRef RR = MaxRefs [ ClosureIdx [ X ] ] ; uint16_t PhiFlags = NodeAttrs :: PhiRef | NodeAttrs :: Preserving ; NodeAddr < DefNode * > DA = newDef ( PA , RR , PhiFlags ) ; PA . Addr -> addMember ( DA , * this ) ;


<s> EVT VT = Op . getValueType ( ) ; SDValue V = Op . getOperand ( <NUM_LIT> ) ; if ( V . getValueType ( ) . isVector ( ) ) { assert ( V . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; SDValue TVal = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue FVal = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; <STR_LIT> Pred = cast < TestCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( ( Pred == <STR_LIT> ) || ( Pred == <STR_LIT> ) ) { V = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , V ) ; Pred = ( Pred == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } SDValue Pg = DAG . getNode ( <STR_LIT> , dl , V . getValueType ( ) , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; <STR_LIT> CC = changeTestCCTo<ISA_LIT>CC ( Pred ) ; SDValue CCVal = DAG . getConstant ( getInvertedCondCode ( CC ) , dl , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Pg , V ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CCVal , Cmp ) ;


<s> imm = ( imm << <NUM_LIT> ) & <NUM_LIT> ; assert ( RestoreMI -> getOpcode ( ) == <STR_LIT> ) ; RestoreMI -> setDesc ( TII -> get ( <STR_LIT> ) ) ; RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( reg - <STR_LIT> + <STR_LIT> ) ;

RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( <STR_LIT> ) ;


<s> bool Changed = false ; SmallSetVector < Function * , <NUM_LIT> > Functions ; for ( auto & F : M . getFunctionList ( ) ) { if ( ! F . isDeclaration ( ) ) continue ; switch ( F . getIntrinsicID ( ) ) {


<s> for ( p = <STR_LIT> ; * p ; p ++ ) loongarch_print_operand_punct [ ( unsigned char ) * p ] = true ;


<s> gcc_assert ( REG_P ( newbase ) ) ; int limit = <NUM_LIT> - GET_MODE_SIZE ( GET_MODE ( m ) ) ; if ( REGNO ( base ) == SP_REG ) { if ( addend >= <NUM_LIT> && addend <= limit ) return m ; } if ( addend < <NUM_LIT> || ( addend > limit && REGNO ( newbase ) != BC_REG ) || ( addendr && ( GET_CODE ( addendr ) != CONST_INT ) && ( ( REGNO ( newbase ) != BC_REG ) ) ) ) { EM ( emit_insn_before ( gen_movhi ( AX , base ) , before ) ) ; EM ( emit_insn_before ( gen_addhi3 ( AX , AX , addendr ) , before ) ) ; EM ( emit_insn_before ( gen_movhi ( newbase , AX ) , before ) ) ; record_content ( AX , NULL_RTX ) ; record_content ( newbase , NULL_RTX ) ; base = newbase ; addend = <NUM_LIT> ; addendr = <NUM_LIT> ; } else { base = gen_and_emit_move ( newbase , base , before , true ) ; } if ( addend ) { record_content ( base , NULL_RTX ) ; base = gen_rtx_PLUS ( HImode , base , GEN_INT ( addend ) ) ; } else if ( addendr ) { record_content ( base , NULL_RTX ) ; base = gen_rtx_PLUS ( HImode , base , addendr ) ; } if ( need_es ) { m = change_address ( m , GET_MODE ( m ) , gen_es_addr ( base ) ) ;


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ;

X -> initMCCodeGenInfo ( RM , CM , OL ) ;


<s> static DecodeStatus decodePC16DBLOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodePCDBLOperand < <NUM_LIT> > ( Inst , Imm , Address ) ;


<s> if ( N . getNode ( ) -> getNodeId ( ) == - <NUM_LIT> || N . getNode ( ) -> getNodeId ( ) > Pos -> getNodeId ( ) ) { DAG -> RepositionNode ( Pos , N . getNode ( ) ) ;

N . getNode ( ) -> setNodeId ( Pos -> getNodeId ( ) ) ;


<s> if ( ! member ) continue ; for ( member = OVL_CURRENT ( member ) ; member ; member = OVL_NEXT ( member ) ) { if ( TREE_CODE ( member ) != FUNCTION_DECL ) continue ; if ( DECL_PURE_VIRTUAL_P ( member ) ) continue ; if ( ! DECL_VIRTUAL_P ( member ) ) continue ; if ( lookup_attribute ( attribute_name , DECL_ATTRIBUTES ( member ) ) ) { print_node_brief ( stderr , <STR_LIT> , ctype , <NUM_LIT> ) ; fprintf ( stderr , <STR_LIT> , attribute_name ) ; print_node_brief ( stderr , <STR_LIT> , member , <NUM_LIT> ) ; fprintf ( stderr , <STR_LIT> ) ; return true ; } } } } print_node_brief ( stderr , <STR_LIT> , ctype , <NUM_LIT> ) ;


<s> EVT InVT = In . getValueType ( ) ; EVT OutVT = N -> getValueType ( <NUM_LIT> ) ; APInt Mask = APInt :: getLowBitsSet ( InVT . getScalarSizeInBits ( ) , OutVT . getScalarSizeInBits ( ) ) ; In = DAG . getNode ( <STR_LIT> , DL , InVT , In , DAG . getConstant ( Mask , DL , InVT ) ) ; return truncateVectorWithPACK ( <STR_LIT> , OutVT , In , DL , DAG , Subtarget ) ;


<s> return __builtin_loongson_pinsrh_3_s ( s , t ) ;


<s> if ( CallerBits == ( CalleeBits & TargetFeatures ) ) { NewRoots . insert ( & F ) ; continue ; } Function * NewF = findFunction ( CallerBits , & F ) ; if ( ! NewF ) { FeatureBitset NewFeatures ( ( CalleeBits & ~ TargetFeatures ) | CallerBits ) ; if ( ! AllowClone ) { setFeatures ( F , NewFeatures ) ; NewRoots . insert ( & F ) ; Changed = true ; break ; } NewF = cloneWithFeatures ( F , NewFeatures ) ; Clones . push_back ( Clone ( CallerBits , & F , NewF ) ) ; NewRoots . insert ( NewF ) ; } ToReplace . push_back ( std :: make_pair ( CI , NewF ) ) ; Replaced . insert ( & F ) ; Changed = true ; } while ( ! ToReplace . empty ( ) ) { auto R = ToReplace . pop_back_val ( ) ; R . first -> setCalledFunction ( R . second ) ; }


<s> case <STR_LIT> : return false ; case <STR_LIT> : IdxOn = false ; ToRemove . push_back ( & * I ) ; break ; default : if ( I -> modifiesRegister ( <STR_LIT> , TRI ) ) return false ; if ( IdxReg && I -> modifiesRegister ( IdxReg , TRI ) ) return false ; if ( llvm :: any_of ( I -> operands ( ) , [ & MRI , this ] ( const MachineOperand & MO ) { return MO . isReg ( ) && TRI -> isVectorRegister ( MRI , MO . getReg ( ) ) ; } ) ) { if ( ! IdxOn || ! ( ( I -> getOpcode ( ) == <STR_LIT> && I -> hasRegisterImplicitUseOperand ( <STR_LIT> ) ) || I -> getOpcode ( ) == <STR_LIT> ) ) return false ; } } } MI . eraseFromParent ( ) ; for ( MachineInstr * RI : ToRemove ) RI -> eraseFromParent ( ) ; return true ;


<s> return DAG . getNode ( Op . getOpcode ( ) , dl , <STR_LIT> , Op . getOperand ( MemOp ^ <NUM_LIT> ) , NewVal ) ; } else { return Op ;


<s> MemoryLocation StoreLoc ( Ptr , AccessSize ) ;

for ( auto * B : L -> blocks ( ) ) for ( auto & I : * B ) if ( Ignored . count ( & I ) == <NUM_LIT> && isModOrRefSet ( intersectModRef ( AA . getModRefInfo ( & I , StoreLoc ) , Access ) ) ) return true ;


<s> MVT VT = CEVT . getSimpleVT ( ) ; if ( const ConstantFP * CFP = dyn_cast < ConstantFP > ( C ) ) return <ISA_LIT>MaterializeFP ( CFP , VT ) ; else if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( C ) ) return <ISA_LIT>MaterializeGV ( GV , VT ) ;

else if ( isa < ConstantInt > ( C ) ) return <ISA_LIT>MaterializeInt ( C , VT ) ;


<s> const bool IsVALU = DstRB -> getID ( ) == <STR_LIT> ; MachineBasicBlock * MBB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( IsVALU ) { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addImm ( Subtarget -> getWavefrontSizeLog2 ( ) ) . addReg ( SrcReg ) ; } else { BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) . addImm ( Subtarget -> getWavefrontSizeLog2 ( ) ) ;


<s> static Iter getNextMachineInstrInBB ( Iter Position ) { Iter I = Position , E = Position -> getParent ( ) -> end ( ) ; I = std :: find_if_not ( I , E , [ ] ( const Iter & Insn ) { return Insn -> isTransient ( ) ; } ) ; return I ;


<s> void <ISA_LIT>LinuxAsmPrinter :: emitGNUAttributes ( Module & M ) { Metadata * MD = M . getModuleFlag ( <STR_LIT> ) ; MDString * FloatABI = dyn_cast_or_null < MDString > ( MD ) ; if ( ! FloatABI ) return ; StringRef flt = FloatABI -> getString ( ) ; if ( flt == <STR_LIT> ) OutStreamer -> emitGNUAttribute ( Tag_GNU_Power_ABI_FP , Val_GNU_Power_ABI_HardFloat_DP | Val_GNU_Power_ABI_LDBL_IBM128 ) ; else if ( flt == <STR_LIT> ) OutStreamer -> emitGNUAttribute ( Tag_GNU_Power_ABI_FP , Val_GNU_Power_ABI_HardFloat_DP | Val_GNU_Power_ABI_LDBL_IEEE128 ) ;

else if ( flt == <STR_LIT> ) OutStreamer -> emitGNUAttribute ( Tag_GNU_Power_ABI_FP , Val_GNU_Power_ABI_HardFloat_DP | Val_GNU_Power_ABI_LDBL_64 ) ;


<s> if ( ! VT . isSimple ( ) || VT == <STR_LIT> ) return false ; if ( AddrSpace == <STR_LIT> ) { return Align % <NUM_LIT> == <NUM_LIT> ;


<s> assert ( getStackGrowthDirection ( ) == TargetFrameLowering :: StackGrowsDown && <STR_LIT> ) ; int MinCSFrameIndex , MaxCSFrameIndex ; int64_t SVEStackSize = assignSVEStackObjectOffsets ( MFI , MinCSFrameIndex , MaxCSFrameIndex ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; AFI -> setStackSizeSVE ( alignTo ( SVEStackSize , <NUM_LIT> ) ) ; AFI -> setMinMaxSVECSFrameIndex ( MinCSFrameIndex , MaxCSFrameIndex ) ; if ( ! MF . hasEHFunclets ( ) ) return ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; WinEHFuncInfo & EHInfo = * MF . getWinEHFuncInfo ( ) ; MachineBasicBlock & MBB = MF . front ( ) ; auto MBBI = MBB . begin ( ) ;

while ( MBBI != MBB . end ( ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) ) ++ MBBI ;


<s> <ISA_LIT>MCExpr :: VariantKind VK ; bool IsConstantImm = evaluateConstantImm ( Imm , VK ) ; bool IsValid ;

if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ;


<s> } if ( ! CheckPreds && Preds . empty ( ) ) return true ; if ( CheckPreds ) { queue_preds : if ( MachineFunction :: iterator ( MBB ) == MBB -> getParent ( ) -> begin ( ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << BI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << BI -> getParent ( ) -> getFullName ( ) << <STR_LIT> << * BI << <STR_LIT> ) ; return false ; } for ( MachineBasicBlock :: pred_iterator PI = MBB -> pred_begin ( ) , PIE = MBB -> pred_end ( ) ; PI != PIE ; ++ PI ) Preds . push_back ( * PI ) ; } do {


<s> TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; const auto & MLI = getAnalysis < MachineLoopInfo > ( ) ; const auto & MDT = getAnalysis < MachineDominatorTree > ( ) ; const auto & MDF = getAnalysis < MachineDominanceFrontier > ( ) ; std :: unique_ptr < MachineGadgetGraph > Graph = getGadgetGraph ( MF , MLI , MDT , MDF ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( Graph == nullptr ) return false ; if ( EmitDotVerify ) { writeGadgetGraph ( outs ( ) , MF , Graph . get ( ) ) ; return false ; } if ( EmitDot || EmitDotOnly ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; std :: error_code FileError ; std :: string FileName = <STR_LIT> ; FileName += MF . getName ( ) ; FileName += <STR_LIT> ; raw_fd_ostream FileOut ( FileName , FileError ) ; if ( FileError ) errs ( ) << FileError . message ( ) ; writeGadgetGraph ( FileOut , MF , Graph . get ( ) ) ; FileOut . close ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; if ( EmitDotOnly ) return false ; } int FencesInserted ; if ( ! OptimizePluginPath . empty ( ) ) { if ( ! OptimizeDL . isValid ( ) ) { std :: string ErrorMsg ; OptimizeDL = llvm :: sys :: DynamicLibrary :: getPermanentLibrary ( OptimizePluginPath . c_str ( ) , & ErrorMsg ) ; if ( ! ErrorMsg . empty ( ) ) report_fatal_error ( <STR_LIT> + ErrorMsg + '\"' ) ; OptimizeCut = ( OptimizeCutT ) OptimizeDL . getAddressOfSymbol ( <STR_LIT> ) ; if ( ! OptimizeCut ) report_fatal_error ( <STR_LIT> ) ; } FencesInserted = hardenLoadsWithPlugin ( MF , std :: move ( Graph ) ) ; } else { FencesInserted = hardenLoadsWithHeuristic ( MF , std :: move ( Graph ) ) ; } if ( FencesInserted > <NUM_LIT> ) ++ NumFunctionsMitigated ; NumFences += FencesInserted ; return ( FencesInserted > <NUM_LIT> ) ;


<s> MCSection * findAssociatedSection ( ) const override {


<s> Val = DAG . getNode ( <STR_LIT> , dl , ValVT , Val ) ; } else { Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ( ValVT . getSizeInBits ( ) ) , Val ) ; Val = DAG . getNode ( <STR_LIT> , dl , ValVT , Val ) ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> bool Modified = false ; ( void ) std :: initializer_list < int > {

Modified |= std :: get < ThunkInserterT > ( ThunkInserters ) . run ( MMI , MF ) ... } ;


<s> const Function & F = MF . getFunction ( ) ; F . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { F , ( <STR_LIT> <STR_LIT> ) } ) ;


<s> assert ( Dst0 . isDef ( ) && Dst1 . isDef ( ) ) ; bool HaveNonDbgCarryUse = ! MRI . use_nodbg_empty ( Dst1 . getReg ( ) ) ; const TargetRegisterClass * Dst0RC = MRI . getRegClass ( Dst0 . getReg ( ) ) ; unsigned NewReg0 = MRI . createVirtualRegister ( Dst0RC ) ; const TargetRegisterClass * Dst1RC = MRI . getRegClass ( Dst1 . getReg ( ) ) ; unsigned NewReg1 = MRI . createVirtualRegister ( Dst1RC ) ; MachineInstr * Inst32 = TII . buildShrunkInst ( * MI , Op32 ) ; if ( HaveNonDbgCarryUse ) { BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII . get ( <STR_LIT> ) , Dst1 . getReg ( ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } Dst0 . setReg ( NewReg0 ) ; Dst1 . setReg ( NewReg1 ) ; if ( Fold . isCommuted ( ) ) TII . commuteInstruction ( * Inst32 , false ) ; return true ; } Old . ChangeToImmediate ( Fold . ImmToFold ) ; return true ; } assert ( ! Fold . needsShrink ( ) && <STR_LIT> ) ; if ( Fold . isFI ( ) ) { Old . ChangeToFrameIndex ( Fold . FrameIndexToFold ) ; return true ;


<s> <ISA_LIT>AsmInstPrinter :: <ISA_LIT>AsmInstPrinter ( MCInstPrinter * RawPrinter ) : MCInstPrinter ( * RawPrinter ) , RawPrinter ( RawPrinter ) {


<s> const MachineOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . getType ( ) == MachineOperand :: MO_Register ) { assert ( TargetRegisterInfo :: isPhysicalRegister ( MO . getReg ( ) ) && <STR_LIT> ) ; O << TM . getRegisterInfo ( ) -> get ( MO . getReg ( ) ) . AsmName ; } else {


<s> return __builtin_ia32_rsqrtph128_mask ( __B , _mm_setzero_ph ( ) , __A ) ;


<s> if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectTrue ; False = SelectFalse ; } else if ( CMOVTrueVal == <NUM_LIT> && CMOVFalseVal == <NUM_LIT> ) { True = SelectFalse ; False = SelectTrue ; } if ( True . getNode ( ) && False . getNode ( ) ) { EVT VT = Cond . getValueType ( ) ; SDValue <ISA_LIT>cc = Cond . getOperand ( <NUM_LIT> ) ; SDValue CCR = Cond . getOperand ( <NUM_LIT> ) ; SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , True , False , <ISA_LIT>cc , CCR , Cmp ) ; } } }

return DAG . getSelectCC ( dl , Cond , DAG . getConstant ( <NUM_LIT> , Cond . getValueType ( ) ) , SelectTrue , SelectFalse , <STR_LIT> ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { if ( isVarArg ) { report_fatal_error ( <STR_LIT> ) ; } SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ;

for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i < e ; ++ i ) {


<s> static SDValue combineBEXTR ( SDNode * N , SelectionDAG & DAG , TargetLowering :: DAGCombinerInfo & DCI , const <ISA_LIT>Subtarget & Subtarget ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned NumBits = VT . getSizeInBits ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; APInt DemandedMask ( APInt :: getAllOnes ( NumBits ) ) ; if ( TLI . SimplifyDemandedBits ( SDValue ( N , <NUM_LIT> ) , DemandedMask , DCI ) ) return SDValue ( N , <NUM_LIT> ) ; return SDValue ( ) ;


<s> <ISA_LIT>ConstantPoolSymbol :: <ISA_LIT>ConstantPoolSymbol ( LLVMContext & C , StringRef s , unsigned id , unsigned char PCAdj , <STR_LIT> Modifier , bool AddCurrentAddress ) : <ISA_LIT>ConstantPoolValue ( C , id , <STR_LIT> , PCAdj , Modifier , AddCurrentAddress ) , S ( std :: string ( s ) ) {


<s> } ; auto IsExpiredFn = [ InstType , & IsHazardInst ] ( const MachineInstr & I , int ) { auto InstType2 = IsHazardInst ( I ) ; if ( InstType == InstType2 ) return true ; return I . getOpcode ( ) == <STR_LIT> && I . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && ! I . getOperand ( <NUM_LIT> ) . getImm ( ) ; } ; return :: getWaitStatesSince ( IsHazardFn , & I , IsExpiredFn ) != std :: numeric_limits < int > :: max ( ) ; } ;

if ( :: getWaitStatesSince ( IsHazardFn , MI , IsExpiredFn ) == std :: numeric_limits < int > :: max ( ) ) return false ;


<s> static SDValue getMOVDDup ( SDValue & Op , DebugLoc & dl , SDValue V1 , SelectionDAG & DAG ) { EVT VT = Op . getValueType ( ) ; V1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , getTargetShuffleNode ( <STR_LIT> , dl , <STR_LIT> , V1 , DAG ) ) ;


<s> if ( DAG . getTarget ( ) . Options . EmulatedTLS ) return LowerToTLSEmulatedModel ( GA , DAG ) ; if ( Subtarget -> isTargetDarwin ( ) ) return LowerDarwinGlobalTLSAddress ( Op , DAG ) ; if ( Subtarget -> isTargetELF ( ) ) return LowerELFGlobalTLSAddress ( Op , DAG ) ;


<s> MIB . addDef ( PhysReg , RegState :: Implicit ) ;


<s> DecodeStatus <ISA_LIT>InstrDecomposer :: getLLVMInst ( uint64_t & Insn , const std :: map < Fields , Field > & Layout , <ISA_LIT>II :: IType SlotType ) { Insn = <NUM_LIT> ; uint64_t bits = <NUM_LIT> ; for ( auto FieldLayout : Layout ) { std :: bitset < <NUM_LIT> > FieldBits = Bundle >> FieldLayout . second . startBin ; FieldBits &= MASK ( FieldLayout . second . size ) ; bits = static_cast < uint64_t > ( FieldBits . to_ulong ( ) ) ;

Insn |= bits << FieldLayout . second . startLLVM ;


<s> if ( Imm <= <NUM_LIT> ) { O << <STR_LIT> ; O << formatDec ( Imm & <NUM_LIT> ) << <STR_LIT> ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; O << formatDec ( ( Imm & <NUM_LIT> ) >> <NUM_LIT> ) << <STR_LIT> ; } else if ( ( Imm >= <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( ( Imm >= <NUM_LIT> ) && ( Imm <= <NUM_LIT> ) ) { O << <STR_LIT> ; printU4ImmDecOperand ( MI , OpNo , O ) ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ; } else if ( Imm == <NUM_LIT> ) { O << <STR_LIT> ;


<s> if ( get_attr_zEC12_groupalone ( insn ) ) mask |= S390_SCHED_ATTR_MASK_GROUPALONE ; break ; case PROCESSOR_2964_Z13 : if ( get_attr_z13_cracked ( insn ) ) mask |= S390_SCHED_ATTR_MASK_CRACKED ; if ( get_attr_z13_expanded ( insn ) ) mask |= S390_SCHED_ATTR_MASK_EXPANDED ; if ( get_attr_z13_endgroup ( insn ) ) mask |= S390_SCHED_ATTR_MASK_ENDGROUP ; if ( get_attr_z13_groupalone ( insn ) ) mask |= S390_SCHED_ATTR_MASK_GROUPALONE ; if ( get_attr_z13_groupoftwo ( insn ) ) mask |= S390_SCHED_ATTR_MASK_GROUPOFTWO ; break ; case PROCESSOR_3906_Z14 : if ( get_attr_z14_cracked ( insn ) ) mask |= S390_SCHED_ATTR_MASK_CRACKED ; if ( get_attr_z14_expanded ( insn ) ) mask |= S390_SCHED_ATTR_MASK_EXPANDED ; if ( get_attr_z14_endgroup ( insn ) ) mask |= S390_SCHED_ATTR_MASK_ENDGROUP ; if ( get_attr_z14_groupalone ( insn ) ) mask |= S390_SCHED_ATTR_MASK_GROUPALONE ; if ( get_attr_z14_groupoftwo ( insn ) ) mask |= S390_SCHED_ATTR_MASK_GROUPOFTWO ; break ; case PROCESSOR_8561_Z15 : if ( get_attr_z15_cracked ( insn ) ) mask |= S390_SCHED_ATTR_MASK_CRACKED ; if ( get_attr_z15_expanded ( insn ) ) mask |= S390_SCHED_ATTR_MASK_EXPANDED ; if ( get_attr_z15_endgroup ( insn ) ) mask |= S390_SCHED_ATTR_MASK_ENDGROUP ; if ( get_attr_z15_groupalone ( insn ) ) mask |= S390_SCHED_ATTR_MASK_GROUPALONE ; if ( get_attr_z15_groupoftwo ( insn ) ) mask |= S390_SCHED_ATTR_MASK_GROUPOFTWO ; break ; case PROCESSOR_3931_Z16 : if ( get_attr_z16_cracked ( insn ) ) mask |= S390_SCHED_ATTR_MASK_CRACKED ; if ( get_attr_z16_expanded ( insn ) ) mask |= S390_SCHED_ATTR_MASK_EXPANDED ;

if ( get_attr_z16_endgroup ( insn ) ) mask |= S390_SCHED_ATTR_MASK_ENDGROUP ;


<s> MachineInstr * NewMI = MF . CreateMachineInstr ( TII . get ( Opcode ) , MI . getDebugLoc ( ) , true ) ; MachineInstrBuilder MIB ( MF , NewMI ) ; addOperands ( MIB , MOs ) ; unsigned NumOps = MI . getDesc ( ) . getNumOperands ( ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumOps ; ++ i ) { MachineOperand & MO = MI . getOperand ( i + <NUM_LIT> ) ; MIB . add ( MO ) ; }

for ( unsigned i = NumOps + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) {


<s> return __builtin_aarch64_usqaddv4si_uus ( __a , __b ) ;


<s> static SDValue Concat256BitVectors ( SDValue V1 , SDValue V2 , EVT VT , unsigned NumElems , SelectionDAG & DAG , SDLoc dl ) {

SDValue V = Insert256BitVector ( DAG . getUNDEF ( VT ) , V1 , <NUM_LIT> , DAG , dl ) ;


<s> static SDValue getAVX2GatherNode ( unsigned Opc , SDValue Op , SelectionDAG & DAG , SDValue Src , SDValue Mask , SDValue Base , SDValue Index , SDValue ScaleOp , SDValue Chain , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc dl ( Op ) ; auto * C = dyn_cast < ConstantSDNode > ( ScaleOp ) ; if ( ! C ) return SDValue ( ) ; SDValue Scale = DAG . getTargetConstant ( C -> getZExtValue ( ) , dl , <STR_LIT> ) ; EVT MaskVT = Mask . getValueType ( ) . changeVectorElementTypeToInteger ( ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; if ( Src . isUndef ( ) || <STR_LIT> ( Mask . getNode ( ) ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ;

MemIntrinsicSDNode * MemIntr = cast < MemIntrinsicSDNode > ( Op ) ;


<s> inline bool isUncondBranch ( const MachineInstr * I ) {


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>RegisterInfo * RegInfo = static_cast < const <ISA_LIT>RegisterInfo * > ( DAG . getSubtarget ( ) . getRegisterInfo ( ) ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - ( int64_t ) SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {


<s> rtx mem = XEXP ( set , opn ) ; rtx addr = XEXP ( mem , <NUM_LIT> ) ;

if ( GET_CODE ( mem ) != MEM ) return <NUM_LIT> ;


<s> void scalar_chain :: add_to_queue ( unsigned insn_uid ) {

if ( ! bitmap_set_bit ( queue , insn_uid ) ) return ;


<s> if ( Register == ~ <NUM_LIT> ) return MCDisassembler :: Fail ;

Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> if ( ! thisBlockISELs . empty ( ) ) ISELInstructions . insert ( std :: make_pair ( MBB . getNumber ( ) , thisBlockISELs ) ) ;


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> NaCl<ISA_LIT>_64AsmBackend ( const Target & T , uint8_t OSABI , StringRef CPU ) : ELF<ISA_LIT>_64AsmBackend ( T , OSABI , CPU ) {


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool NonScalarIntSafe , bool MemcpyStrSrc , MachineFunction & MF ) const { const Function * F = MF . getFunction ( ) ; if ( NonScalarIntSafe && ! F -> hasFnAttr ( Attribute :: NoImplicitFloat ) ) { if ( Size >= <NUM_LIT> && ( Subtarget -> isUnalignedMemAccessFast ( ) || ( ( DstAlign == <NUM_LIT> || DstAlign >= <NUM_LIT> ) && ( SrcAlign == <NUM_LIT> || SrcAlign >= <NUM_LIT> ) ) ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> ) { if ( Subtarget -> hasSSE2 ( ) ) return <STR_LIT> ; if ( Subtarget -> hasSSE1 ( ) ) return <STR_LIT> ; } else if ( ! MemcpyStrSrc && Size >= <NUM_LIT> && ! Subtarget -> is64Bit ( ) && Subtarget -> getStackAlignment ( ) >= <NUM_LIT> && Subtarget -> hasSSE2 ( ) ) { return <STR_LIT> ; } } if ( Subtarget -> is64Bit ( ) && Size >= <NUM_LIT> ) return <STR_LIT> ;


<s> vec_uint4 bv ; vec_uint4 mask ; bv = vec_splat ( ( vec_uint4 ) ( si_from_uint ( b ) ) , <NUM_LIT> ) ;

mask = ( vec_uint4 ) vec_sra ( vec_sl ( bv , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) , ( ( vec_uint4 ) { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) ;


<s> bool ia64_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ) {

return ( to == BR_REG ( <NUM_LIT> ) ? crtl -> is_leaf : true ) ;


<s> int lo = UsedOps . size ( ) * MaskWidth ; int hi = lo + MaskWidth ; if ( any_of ( Mask , [ lo , hi ] ( int i ) { return ( lo <= i ) && ( i < hi ) ; } ) ) { UsedOps . push_back ( Ops [ i ] ) ; continue ; } for ( int & M : Mask ) if ( lo <= M ) M -= MaskWidth ; } Ops = UsedOps ;


<s> } else { SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; } if ( MI -> mayStore ( ) ) { assert ( DstReg == <STR_LIT> && <STR_LIT> ) ; SmallVector < unsigned , <NUM_LIT> > RegList ; unsigned StartOp = <NUM_LIT> + <NUM_LIT> ; unsigned NumOffset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : StartOp = <NUM_LIT> ; NumOffset = <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( SrcReg == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = StartOp , NumOps = MI -> getNumOperands ( ) - NumOffset ; i != NumOps ; ++ i ) RegList . push_back ( MI -> getOperand ( i ) . getReg ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : assert ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; RegList . push_back ( SrcReg ) ; break ; } OutStreamer . EmitRegSave ( RegList , Opc == <STR_LIT> ) ; } else { if ( SrcReg == <STR_LIT> ) { int64_t Offset = <NUM_LIT> ; switch ( Opc ) { default : MI -> dump ( ) ; assert ( <NUM_LIT> && <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : Offset = <NUM_LIT> ; break ; case <STR_LIT> : Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; break ; case <STR_LIT> : Offset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> :

Offset = - MI -> getOperand ( <NUM_LIT> ) . getImm ( ) * <NUM_LIT> ;


<s> size_t CurFmtSpecifierIdx = <NUM_LIT> ; size_t PrevFmtSpecifierIdx = <NUM_LIT> ; while ( ( CurFmtSpecifierIdx = Fmt . find_first_of ( ConvSpecifiers , CurFmtSpecifierIdx ) ) != StringRef :: npos ) { bool ArgDump = false ; StringRef CurFmt = Fmt . substr ( PrevFmtSpecifierIdx , CurFmtSpecifierIdx - PrevFmtSpecifierIdx ) ; size_t pTag = CurFmt . find_last_of ( <STR_LIT> ) ; if ( pTag != StringRef :: npos ) { ArgDump = true ; while ( pTag && CurFmt [ -- pTag ] == '%' ) { ArgDump = ! ArgDump ; } } if ( ArgDump ) OpConvSpecifiers . push_back ( Fmt [ CurFmtSpecifierIdx ] ) ;

PrevFmtSpecifierIdx = ++ CurFmtSpecifierIdx ;


<s> StringRef getPassName ( ) const override {


<s> static void nvptx_print_address_operand ( FILE * file , rtx x , machine_mode ) { rtx off ; if ( GET_CODE ( x ) == CONST ) x = XEXP ( x , <NUM_LIT> ) ; switch ( GET_CODE ( x ) ) {


<s> MemOpQueueEntry ( int o , unsigned r , bool k , unsigned p , MachineBasicBlock :: iterator i ) : Offset ( o ) , Reg ( r ) , isKill ( k ) , Position ( p ) , MBBI ( i ) , Merged ( false ) {


<s> unsigned Mods = <NUM_LIT> ; SelectVOP3PMadMixModsImpl ( In , Src , Mods ) ; SrcMods = CurDAG -> getTargetConstant ( Mods , SDLoc ( In ) , <STR_LIT> ) ;


<s> CallReturnHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , CCAssignFn * AssignFn , MachineInstrBuilder & MIB ) : IncomingValueHandler ( MIRBuilder , MRI , AssignFn ) , MIB ( MIB ) {


<s> if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST ) { rtx unspec , offset ; split_const ( XEXP ( x , <NUM_LIT> ) , & unspec , & offset ) ; if ( GET_CODE ( unspec ) == UNSPEC && ! nios2_large_offset_p ( XINT ( unspec , <NUM_LIT> ) ) && offset != const0_rtx ) { rtx reg = force_reg ( Pmode , XEXP ( x , <NUM_LIT> ) ) ; unspec = copy_rtx ( unspec ) ;

XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) = plus_constant ( Pmode , XVECEXP ( unspec , <NUM_LIT> , <NUM_LIT> ) , INTVAL ( offset ) ) ;


<s> BlockData & BBInfo = BlockInfo [ MBB . getNumber ( ) ] ; for ( const MachineInstr & MI : MBB ) { if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { HadVectorOp = true ; BBInfo . Change = getInfoForVSETVLI ( MI ) ; continue ; } uint64_t TSFlags = MI . getDesc ( ) . TSFlags ; if ( <STR_LIT> ( TSFlags ) ) { HadVectorOp = true ; VSETVLIInfo NewInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; if ( ! BBInfo . Change . isValid ( ) ) { BBInfo . Change = NewInfo ; } else { if ( needVSETVLI ( NewInfo , BBInfo . Change ) ) BBInfo . Change = NewInfo ; } } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) { BBInfo . Change = <STR_LIT> ( ) ; }


<s> for ( const auto & I : IFMap ) { dbgs ( ) << <STR_LIT> << printReg ( I . first , HRI ) << <STR_LIT> ; const IFListType & LL = I . second ;

for ( const auto & J : LL ) dbgs ( ) << <STR_LIT> << PrintIFR ( J . first , HRI ) << <STR_LIT> << PrintRegSet ( J . second , HRI ) << '\n' ;


<s> int offset = frame_pointer_needed ? <NUM_LIT> : <NUM_LIT> ; offset += avr_regs_to_save ( NULL ) ;

return get_frame_size ( ) + <NUM_LIT> + <NUM_LIT> + offset ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( TLSRegister ) ; Op -> TLSReg . Sym = Sym ;


<s> unsigned SubRegCopy = MRI . createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) ) . addDef ( SubRegCopy ) . addUse ( CopyReg , <NUM_LIT> , <STR_LIT> ) ;


<s> Register Vec = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Ins = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT VecTy = MRI . getType ( Vec ) ; LLT EltTy = VecTy . getElementType ( ) ; assert ( EltTy == MRI . getType ( Ins ) ) ; if ( IdxVal -> Value < VecTy . getNumElements ( ) ) B . buildInsert ( Dst , Vec , Ins , IdxVal -> Value * EltTy . getSizeInBits ( ) ) ; else B . buildUndef ( Dst ) ;


<s> for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineInstr & MI = * I ; TII -> convertToISA ( MI , MF , MBB . findDebugLoc ( I ) ) ; }


<s> GCNUpwardRPTracker ( const LiveIntervals & LIS_ ) : LIS ( LIS_ ) {


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreatePrefix ( unsigned Prefixes , SMLoc StartLoc , SMLoc EndLoc ) { auto Res = std :: make_unique < <ISA_LIT>Operand > ( Prefix , StartLoc , EndLoc ) ; Res -> Pref . Prefixes = Prefixes ; return Res ;


<s> MachineIRBuilder & Builder = Helper . MIRBuilder ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( Dst ) ; LLT SrcTy = MRI . getType ( Src ) ; assert ( SrcTy == LLT :: scalar ( <NUM_LIT> ) ) ;

auto One = Builder . buildConstant ( DstTy , <NUM_LIT> ) ;


<s> unsigned long c ; unsigned long result ; if ( __builtin_constant_p ( __M ) && ( __builtin_popcountl ( __M ) <= <NUM_LIT> ) ) { for ( long i = <NUM_LIT> ; i < __builtin_popcountl ( __M ) ; i ++ ) { c = __builtin_clzl ( m ) ; p = ( p << <NUM_LIT> ) | c ; m ^= ( mask >> c ) ; } result = __builtin_bpermd ( p , __X ) ; } else { p = <NUM_LIT> - __builtin_popcountl ( __M ) ; result = <NUM_LIT> ; while ( m != <NUM_LIT> ) { unsigned long t ; c = __builtin_clzl ( m ) ; t = ( __X & ( mask >> c ) ) >> ( p - c ) ; m ^= ( mask >> c ) ; result |= ( t ) ; p ++ ;


<s> if ( LdVT == <STR_LIT> ) return <STR_LIT> ; if ( LdVT == <STR_LIT> ) return <STR_LIT> ; if ( LdVT == <STR_LIT> ) return <STR_LIT> ; if ( LdVT == <STR_LIT> ) return <STR_LIT> ; } else { assert ( Opc == <STR_LIT> && <STR_LIT> ) ; if ( LdVT == <STR_LIT> ) return <STR_LIT> ; if ( LdVT == <STR_LIT> ) return <STR_LIT> ; if ( LdVT == <STR_LIT> ) return <STR_LIT> ;


<s> Type * AllocatedType = Info . AI -> isArrayAllocation ( ) ? ArrayType :: get ( Info . AI -> getAllocatedType ( ) , cast < ConstantInt > ( Info . AI -> getArraySize ( ) ) -> getZExtValue ( ) ) : Info . AI -> getAllocatedType ( ) ; Type * PaddingType = ArrayType :: get ( Type :: getInt8Ty ( F -> getContext ( ) ) , AlignedSize - Size ) ; Type * TypeWithPadding = StructType :: get ( AllocatedType , PaddingType ) ; auto * NewAI = new AllocaInst ( TypeWithPadding , Info . AI -> getType ( ) -> getAddressSpace ( ) , nullptr , <STR_LIT> , Info . AI ) ; NewAI -> takeName ( Info . AI ) ; NewAI -> setAlignment ( Info . AI -> getAlign ( ) ) ; NewAI -> setUsedWithInAlloca ( Info . AI -> isUsedWithInAlloca ( ) ) ; NewAI -> setSwiftError ( Info . AI -> isSwiftError ( ) ) ; NewAI -> copyMetadata ( * Info . AI ) ; auto * NewPtr = new BitCastInst ( NewAI , Info . AI -> getType ( ) , <STR_LIT> , Info . AI ) ; Info . AI -> replaceAllUsesWith ( NewPtr ) ; Info . AI -> eraseFromParent ( ) ;


<s> if ( VT == <STR_LIT> ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ;

if ( VT == <STR_LIT> && ! Subtarget -> isFPOnlySP ( ) ) return <STR_LIT> ( Imm ) != - <NUM_LIT> ;


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {


<s> case FK_Data_1 : case FK_Data_2 : case FK_Data_4 : case FK_Data_8 : case FK_Data_6b : return Value ; case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Value & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( ( Value >> <NUM_LIT> ) & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return ( ( Value + <NUM_LIT> ) >> <NUM_LIT> ) & <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Lo10 << <NUM_LIT> ) | ( Mid1 << <NUM_LIT> ) | Hi8 ; return Value ; } case <STR_LIT> : { if ( ! isInt < <NUM_LIT> > ( Value ) ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; if ( Value & <NUM_LIT> ) Ctx . reportError ( Fixup . getLoc ( ) , <STR_LIT> ) ; unsigned Sbit = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Hi1 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Mid6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Lo4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; Value = ( Sbit << <NUM_LIT> ) | ( Mid6 << <NUM_LIT> ) | ( Lo4 << <NUM_LIT> ) | ( Hi1 << <NUM_LIT> ) ; return Value ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { uint64_t UpperImm = ( Value + <NUM_LIT> ) & <NUM_LIT> ; uint64_t LowerImm = Value & <NUM_LIT> ; return UpperImm | ( ( LowerImm << <NUM_LIT> ) << <NUM_LIT> ) ; } case <STR_LIT> : case <STR_LIT> : { unsigned Bit11 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit4 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit9_8 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit10 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ; unsigned Bit6 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;

unsigned Bit7 = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;


<s> unsigned getExplicitKernelArgOffset ( const MachineFunction & MF ) const { return <NUM_LIT> ;


<s> unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != Idx ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != Idx ) ) return false ; Idx += <NUM_LIT> ; }


<s> if ( MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> || MI -> getOpcode ( ) == <STR_LIT> ) { return KnownHardwareLoops . count ( MI ) == <NUM_LIT> ; }


<s> if ( isDirect ) return STI . isThumb ( ) ? <STR_LIT> : <STR_LIT> ; if ( STI . isThumb ( ) ) return gettBLXrOpcode ( MF ) ; if ( STI . hasV5TOps ( ) ) return getBLXOpcode ( MF ) ; if ( STI . hasV4TOps ( ) ) return <STR_LIT> ;


<s> void <ISA_LIT>InstrInfo :: fixupPostOutline ( MachineBasicBlock & MBB ) const { for ( MachineInstr & MI : MBB ) { MachineOperand * Base ; unsigned Width ; int64_t Offset ; if ( ! MI . mayLoadOrStore ( ) || ! getMemOperandWithOffsetWidth ( MI , Base , Offset , Width , & RI ) || ( Base -> isReg ( ) && Base -> getReg ( ) != <STR_LIT> ) ) continue ; unsigned Scale ; int64_t Dummy1 , Dummy2 ; MachineOperand & StackOffsetOperand = getMemOpBaseRegImmOfsOffsetOperand ( MI ) ; assert ( StackOffsetOperand . isImm ( ) && <STR_LIT> ) ;

getMemOpInfo ( MI . getOpcode ( ) , Scale , Width , Dummy1 , Dummy2 ) ;


<s> if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) && Subtarget . hasSSE2 ( ) && ( AllowFloatDomain || ! Subtarget . hasSSE41 ( ) ) ) { std :: swap ( V1 , V2 ) ; Shuffle = <STR_LIT> ; ShuffleVT = MaskVT ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) && ( AllowFloatDomain || ! Subtarget . hasSSE41 ( ) ) ) { Shuffle = <STR_LIT> ; ShuffleVT = MaskVT ; return true ; } } if ( ( MaskVT == <STR_LIT> && Subtarget . hasSSE1 ( ) ) || ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE2 ( ) ) || ( MaskVT . is256BitVector ( ) && <NUM_LIT> <= EltSizeInBits && Subtarget . hasAVX ( ) ) || ( MaskVT . is256BitVector ( ) && Subtarget . hasAVX2 ( ) ) || ( MaskVT . is512BitVector ( ) && Subtarget . hasAVX512 ( ) ) ) {

if ( matchVectorShuffleWithUNPCK ( MaskVT , V1 , V2 , Shuffle , IsUnary , Mask , DL , DAG , Subtarget ) ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue Glue , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals , const SmallVectorImpl < SDValue > & OutVals , SDValue Callee ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; if ( Subtarget . useHVXOps ( ) ) CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>_HVX ) ; else CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { SDValue RetVal ; if ( RVLocs [ i ] . getValVT ( ) == <STR_LIT> ) { auto & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue FR0 = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , <STR_LIT> , Glue ) ; unsigned PredR = MRI . createVirtualRegister ( & <STR_LIT> ) ; SDValue TPR = DAG . getCopyToReg ( FR0 . getValue ( <NUM_LIT> ) , dl , PredR , FR0 . getValue ( <NUM_LIT> ) , FR0 . getValue ( <NUM_LIT> ) ) ; RetVal = DAG . getCopyFromReg ( TPR . getValue ( <NUM_LIT> ) , dl , PredR , <STR_LIT> ) ; Glue = TPR . getValue ( <NUM_LIT> ) ; Chain = TPR . getValue ( <NUM_LIT> ) ; } else {

RetVal = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , Glue ) ;


<s> } ( ) ; static const auto EqZeroOptions = [ this ] ( ) { TTI :: MemCmpExpansionOptions Options ; if ( ST -> hasAVX2 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( ST -> hasSSE2 ( ) ) Options . LoadSizes . push_back ( <NUM_LIT> ) ; if ( ST -> is64Bit ( ) ) {


<s> case <STR_LIT> : return TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; case <STR_LIT> : { unsigned FP = TFI -> hasFP ( MF ) ? <NUM_LIT> : <NUM_LIT> ; return <NUM_LIT> - FP - ( STI . isR9Reserved ( ) ? <NUM_LIT> : <NUM_LIT> ) ; } case <STR_LIT> :


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( ID ) {


<s> BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM ; } } else { unsigned NewOpc = ( isLd ) ? ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; unsigned NewOpc2 = ( isLd ) ? ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; if ( isLd && TRI -> regsOverlap ( EvenReg , BaseReg ) ) { assert ( ! TRI -> regsOverlap ( OddReg , BaseReg ) ) ; InsertLDR_STR ( MBB , MBBI , OffImm + <NUM_LIT> , isLd , NewOpc2 , OddReg , OddDeadKill , false , BaseReg , false , BaseUndef , Pred , PredReg , TII ) ; InsertLDR_STR ( MBB , MBBI , OffImm , isLd , NewOpc , EvenReg , EvenDeadKill , false , BaseReg , BaseKill , BaseUndef , Pred , PredReg , TII ) ; } else { if ( OddReg == EvenReg && EvenDeadKill ) { EvenDeadKill = false ; OddDeadKill = true ;


<s> static std :: pair < unsigned , int > computeIndirectRegAndOffset ( const <ISA_LIT>RegisterInfo & TRI , const TargetRegisterClass * SuperRC , unsigned VecReg , int Offset ) { int NumElts = SuperRC -> getSize ( ) / <NUM_LIT> ;

if ( Offset >= NumElts || Offset < <NUM_LIT> ) return std :: make_pair ( <STR_LIT> , Offset ) ;


<s> if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>FunctionInfo * XFI = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool emitFrameMoves = <ISA_LIT>RegisterInfo :: needsFrameMoves ( * MF ) ; DebugLoc DL ; if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; for ( const CalleeSavedInfo & I : CSI ) { Register Reg = I . getReg ( ) ; assert ( Reg != <STR_LIT> && ! ( Reg == <STR_LIT> && hasFP ( * MF ) ) && <STR_LIT> ) ; MBB . addLiveIn ( Reg ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , I . getFrameIdx ( ) , RC , TRI ) ; if ( emitFrameMoves ) { auto Store = MI ; -- Store ;

XFI -> getSpillLabels ( ) . push_back ( std :: make_pair ( Store , I ) ) ;


<s> const DataLayout & DL = DAG . getDataLayout ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>RegisterInfo * TRI = getSubtarget ( ) -> getRegisterInfo ( ) ; unsigned InputPtrReg = TRI -> getPreloadedValue ( MF , <ISA_LIT>RegisterInfo :: KERNARG_SEGMENT_PTR ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; MVT PtrVT = getPointerTy ( DL , AMDGPUA<ISA_LIT> . CONSTANT_ADDRESS ) ;

SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg ) , PtrVT ) ;


<s> addPass ( createPULPFixupHwLoops ( ) ) ; addPass ( create<ISA_LIT>ExpandAtomicPseudoPass ( ) ) ;


<s> else { strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; } strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , name_buf ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , label ) ; strcat ( tmp_buf , <STR_LIT> ) ; strcat ( tmp_buf , <STR_LIT> ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( TargetMachine * TM = nullptr , CodeGenOpt :: Level OptLevel = CodeGenOpt :: Default ) : SelectionDAGISel ( * TM , OptLevel ) { AMDGPUA<ISA_LIT> = <STR_LIT> ( * TM ) ;


<s> return decodeRegisterClass ( Inst , RegNo , <STR_LIT> ) ;


<s> uint64_t RegionSize = <NUM_LIT> ; for ( <ISA_LIT>GOTPLT :: iterator it = m_pGOTPLT -> begin ( ) , ie = m_pGOTPLT -> end ( ) ; it != ie ; ++ it , ++ buffer ) { got = & ( llvm :: cast < <ISA_LIT>GOTEntry > ( ( * it ) ) ) ; * buffer = static_cast < uint32_t > ( got -> getValue ( ) ) ; RegionSize += EntrySize ; }


<s> addMemoryRegisterOffsetOperands ( Inst , N , Mem . ShiftVal == <NUM_LIT> ) ;


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addFrameIndex ( SI -> second ) . addImm ( <NUM_LIT> ) ; return ResultReg ; } return <NUM_LIT> ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> <ISA_LIT>ArgumentMove ( ) : MachineFunctionPass ( ID ) {


<s> Reserved . set ( V ) ; Reserved . set ( VS ) ; Reserved . set ( CYCLES ) . set ( CYCLES2 ) ; Reserved . set ( L0 ) ; Reserved . set ( L1 ) ; Reserved . set ( L2 ) ; Reserved . set ( L3 ) ; Reserved . set ( SP ) ; Reserved . set ( RETS ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FP ) ; return Reserved ;


<s> if ( CostKind != TTI :: TCK_RecipThroughput ) return <NUM_LIT> ; if ( TLI -> getValueType ( DL , Ty , true ) == <STR_LIT> ) return BaseT :: getMemoryOpCost ( Opcode , Ty , Alignment , AddressSpace , CostKind ) ; auto LT = TLI -> getTypeLegalizationCost ( DL , Ty ) ; if ( ST -> isMisaligned128StoreSlow ( ) && Opcode == Instruction :: Store && LT . second . is128BitVector ( ) && ( ! Alignment || * Alignment < Align ( <NUM_LIT> ) ) ) { const int AmortizationCost = <NUM_LIT> ;

return LT . first * <NUM_LIT> * AmortizationCost ;


<s> void <ISA_LIT>InstPrinter :: printPImmediate ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { int16_t Imm ; if ( isConditionalBranch ( Inst ) ) { Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; } else if ( isUnconditionalBranch ( Inst ) ) Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; else return false ; Target = Addr + Size + Imm * Size ;


<s> void <ISA_LIT>SinglePathInfo :: analyzeFunction ( MachineFunction & MF ) { checkIrreducibility ( MF ) ;

Root = SPScope :: createSPScopeTree ( MF , getAnalysis < MachineLoopInfo > ( ) , TII ) ;


<s> MVT StoreSVT = StoreVT . getScalarType ( ) ; unsigned NumElems = StoreVT . getVectorNumElements ( ) ; unsigned ScalarSize = StoreSVT . getStoreSize ( ) ; SDLoc DL ( Store ) ; SmallVector < SDValue , <NUM_LIT> > Stores ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { unsigned Offset = i * ScalarSize ; SDValue Ptr = DAG . getMemBasePlusOffset ( Store -> getBasePtr ( ) , Offset , DL ) ; SDValue Scl = DAG . getNode ( <STR_LIT> , DL , StoreSVT , StoredVal , DAG . getIntPtrConstant ( i , DL ) ) ; SDValue Ch = DAG . getStore ( Store -> getChain ( ) , DL , Scl , Ptr , Store -> getPointerInfo ( ) . getWithOffset ( Offset ) , Store -> getOriginalAlign ( ) , Store -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> bool <ISA_LIT>InstrInfo :: isCoalescableExtInstr ( const MachineInstr & MI , unsigned & SrcReg , unsigned & DstReg , unsigned & SubIdx ) const { return false ;


<s> rtx lane_idx = expand_normal ( CALL_EXPR_ARG ( exp , <NUM_LIT> ) ) ; if ( CONST_INT_P ( lane_idx ) ) aarch64_simd_lane_bounds ( lane_idx , <NUM_LIT> , UINTVAL ( totalsize ) / UINTVAL ( elementsize ) , exp ) ; else error ( <STR_LIT> , exp ) ; } else error ( <STR_LIT> , exp ) ; return const0_rtx ; } aarch64_simd_builtin_datum * d = & aarch64_simd_builtin_data [ fcode - AARCH64_SIMD_PATTERN_START ] ; enum insn_code icode = d -> code ; builtin_simd_arg args [ SIMD_MAX_BUILTIN_ARGS + <NUM_LIT> ] ; int num_args = insn_data [ d -> code ] . n_operands ; int is_void = <NUM_LIT> ; int k ; is_void = ! ! ( d -> qualifiers [ <NUM_LIT> ] & qualifier_void ) ; num_args += is_void ; for ( k = <NUM_LIT> ; k < num_args ; k ++ ) { int qualifiers_k = k ; int operands_k = k - is_void ; int expr_args_k = k - <NUM_LIT> ; if ( d -> qualifiers [ qualifiers_k ] & qualifier_lane_index ) args [ k ] = SIMD_ARG_LANE_INDEX ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_immediate ) args [ k ] = SIMD_ARG_CONSTANT ; else if ( d -> qualifiers [ qualifiers_k ] & qualifier_maybe_immediate ) { rtx arg = expand_normal ( CALL_EXPR_ARG ( exp , ( expr_args_k ) ) ) ; bool op_const_int_p = ( CONST_INT_P ( arg ) && ( * insn_data [ icode ] . operand [ operands_k ] . predicate ) ( arg , insn_data [ icode ] . operand [ operands_k ] . mode ) ) ; args [ k ] = op_const_int_p ? SIMD_ARG_CONSTANT : SIMD_ARG_COPY_TO_REG ; } else args [ k ] = SIMD_ARG_COPY_TO_REG ; } args [ k ] = SIMD_ARG_STOP ;

return aarch64_simd_expand_args ( target , icode , ! is_void , exp , & args [ <NUM_LIT> ] ) ;


<s> unsigned Opcode = MI . getOpcode ( ) ; return Opcode == <STR_LIT> || Opcode == <STR_LIT> ;


<s> static const char * GetArchDefaultCPUName ( unsigned ID ) {


<s> static bool xstormy16_hard_regno_mode_ok ( unsigned int regno , machine_mode mode ) { return regno != <NUM_LIT> || mode == BImode ;


<s> return false ; } case <STR_LIT> : case <STR_LIT> : { if ( Subtarget -> hasNEON ( ) && ( AllowsUnaligned || isLittleEndian ( ) ) ) { if ( Fast ) * Fast = true ; return true ; }


<s> const MCInstrDesc & Desc = MII . get ( Opc ) ; if ( ( Desc . TSFlags & <STR_LIT> ) != <NUM_LIT> && ! hasIntClamp ( ) ) { int ClampIdx = <STR_LIT> ( Opc , <STR_LIT> :: clamp ) ; assert ( ClampIdx != - <NUM_LIT> ) ;

return Inst . getOperand ( ClampIdx ) . getImm ( ) == <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : if ( ! isUInt < <NUM_LIT> > ( Op . getImm ( ) ) && STI . getFeatureBits ( ) [ <STR_LIT> ] ) { printImmediate32 ( Op . getImm ( ) , STI , O ) ; break ; } if ( OpTy == <STR_LIT> ) { printImmediate16 ( static_cast < uint16_t > ( Op . getImm ( ) ) , STI , O ) ; break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : printImmediateInt16 ( static_cast < uint16_t > ( Op . getImm ( ) ) , STI , O ) ; break ; case <STR_LIT> : case <STR_LIT> : printImmediateV216 ( Op . getImm ( ) , STI , O ) ; break ; case MCOI :: OPERAND_UNKNOWN : case MCOI :: OPERAND_PCREL : O << formatDec ( Op . getImm ( ) ) ; break ; case MCOI :: OPERAND_REGISTER : O << <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isFPImm ( ) ) { if ( Op . getFPImm ( ) == <NUM_LIT> ) O << <STR_LIT> ; else { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; int RCID = Desc . OpInfo [ OpNo ] . RegClass ; unsigned RCBits = <STR_LIT> ( MRI . getRegClass ( RCID ) ) ; if ( RCBits == <NUM_LIT> ) printImmediate32 ( FloatToBits ( Op . getFPImm ( ) ) , STI , O ) ; else if ( RCBits == <NUM_LIT> ) printImmediate64 ( DoubleToBits ( Op . getFPImm ( ) ) , STI , O ) ; else llvm_unreachable ( <STR_LIT> ) ; } } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O , & MAI ) ; } else {


<s> switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> break ; } case S_BUFFER_LOAD_IMM : { MachineBasicBlock :: iterator NewMI = mergeSBufferLoadImmPair ( CI , Paired , InstsToMove ) ; CI . setMI ( NewMI , * TII , * STM ) ; OptimizeListAgain |= ( CI . Width + Paired . Width ) < <NUM_LIT> ; break ; } case BUFFER_LOAD : { MachineBasicBlock :: iterator NewMI = mergeBufferLoadPair ( CI , Paired , InstsToMove ) ; CI . setMI ( NewMI , * TII , * STM ) ; OptimizeListAgain |= ( CI . Width + Paired . Width ) < <NUM_LIT> ; break ; } case BUFFER_STORE : { MachineBasicBlock :: iterator NewMI = mergeBufferStorePair ( CI , Paired , InstsToMove ) ; CI . setMI ( NewMI , * TII , * STM ) ; OptimizeListAgain |= ( CI . Width + Paired . Width ) < <NUM_LIT> ; break ; } case MIMG : { MachineBasicBlock :: iterator NewMI = mergeImagePair ( CI , Paired , InstsToMove ) ; CI . setMI ( NewMI , * TII , * STM ) ; OptimizeListAgain |= ( CI . Width + Paired . Width ) < <NUM_LIT> ; break ; } case TBUFFER_LOAD : { MachineBasicBlock :: iterator NewMI = mergeTBufferLoadPair ( CI , Paired , InstsToMove ) ; CI . setMI ( NewMI , * TII , * STM ) ;


<s> CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : assert ( <NUM_LIT> && <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; if ( StackPtr . getNode ( ) == <NUM_LIT> ) StackPtr = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , <STR_LIT> ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , PseudoSourceValue :: getStack ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; }

SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;


<s> if ( MI . readsRegister ( MisspeculatingTaintReg , TRI ) || MI . modifiesRegister ( MisspeculatingTaintReg , TRI ) ) return true ; } }


<s> bool isMangled ( ) const { return Impl -> isMangled ( ) ;


<s> if ( Flags . isByVal ( ) && VA . isMemLoc ( ) ) { const unsigned Size = alignTo ( Flags . getByValSize ( ) ? Flags . getByValSize ( ) : PtrByteSize , PtrByteSize ) ; const int FI = MF . getFrameInfo ( ) . CreateFixedObject ( Size , VA . getLocMemOffset ( ) , false , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( FIN ) ; continue ; } if ( Flags . isByVal ( ) ) { assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; const MCPhysReg ArgReg = VA . getLocReg ( ) ; const <ISA_LIT>FrameLowering * FL = Subtarget . getFrameLowering ( ) ; if ( Flags . getNonZeroByValAlign ( ) > PtrByteSize ) report_fatal_error ( <STR_LIT> ) ; const unsigned StackSize = alignTo ( Flags . getByValSize ( ) , PtrByteSize ) ; const int FI = MF . getFrameInfo ( ) . CreateFixedObject ( StackSize , mapArgRegToOffsetAIX ( ArgReg , FL ) , false , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; InVals . push_back ( FIN ) ; const TargetRegisterClass * RegClass = Is<ISA_LIT>64 ? & <STR_LIT> : & <STR_LIT> ; auto HandleRegLoc = [ & , RegClass , LocVT ] ( const MCPhysReg PhysReg , unsigned Offset ) { const unsigned VReg = MF . addLiveIn ( PhysReg , RegClass ) ; SDValue CopyFrom = DAG . getCopyFromReg ( Chain , dl , VReg , LocVT ) ; SDValue Store = DAG . getStore ( CopyFrom . getValue ( <NUM_LIT> ) , dl , CopyFrom , DAG . getObjectPtrOffset ( dl , FIN , Offset ) , MachinePointerInfo :: getFixedStack ( MF , FI , Offset ) ) ; MemOps . push_back ( Store ) ; } ; unsigned Offset = <NUM_LIT> ; HandleRegLoc ( VA . getLocReg ( ) , Offset ) ; Offset += PtrByteSize ; for ( ; Offset != StackSize && ArgLocs [ I ] . isRegLoc ( ) ; Offset += PtrByteSize ) { assert ( ArgLocs [ I ] . getValNo ( ) == VA . getValNo ( ) && <STR_LIT> ) ; const CCValAssign RL = ArgLocs [ I ++ ] ; HandleRegLoc ( RL . getLocReg ( ) , Offset ) ; } if ( Offset != StackSize ) { assert ( ArgLocs [ I ] . getValNo ( ) == VA . getValNo ( ) && <STR_LIT> ) ; assert ( ArgLocs [ I ] . isMemLoc ( ) && <STR_LIT> ) ; ++ I ; } continue ; }


<s> Register PredReg ; if ( getInstrPredicate ( * MI , PredReg ) == <STR_LIT> ) { switch ( Opc ) { default : break ; case <STR_LIT> : if ( ReduceTo2Addr ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ) return true ; LLVM_FALLTHROUGH ; case <STR_LIT> : return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } } break ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; break ; case <STR_LIT> : { static const ReduceEntry NarrowEntry = { <STR_LIT> , <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; if ( ReduceToNarrow ( MBB , MI , NarrowEntry , LiveCPSR , IsSelfLoop ) ) return true ; return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } case <STR_LIT> : { Register PredReg ; if ( getInstrPredicate ( * MI , PredReg ) != <STR_LIT> ) break ; if ( MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ) return ReduceToNarrow ( MBB , MI , Entry , LiveCPSR , IsSelfLoop ) ; } }


<s> else ++ emptySlots ; } for ( iterator ISJ = begin ( ) ; ISJ != end ( ) ; ++ ISJ ) DEBUG ( dbgs ( ) . write_hex ( ISJ -> Core . getUnits ( ) ) ; if ( ISJ -> CVI . isValid ( ) ) { dbgs ( ) << '/' ; dbgs ( ) . write_hex ( ISJ -> CVI . getUnits ( ) ) << '|' ; dbgs ( ) << ISJ -> CVI . getLanes ( ) ; } dbgs ( ) << ':' << <ISA_LIT>MCInstrInfo :: getDesc ( MCII , ISJ -> getDesc ( ) ) . getOpcode ( ) ; dbgs ( ) << '\n' ) ; DEBUG ( dbgs ( ) << '\n' ) ;