<s> if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , NewEFLAGS ) ; } } } if ( CC == <STR_LIT> ) { return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , X , DAG . getConstant ( <NUM_LIT> , DL , VT ) , Y . getOperand ( <NUM_LIT> ) ) ; } if ( CC == <STR_LIT> ) { SDValue EFLAGS = Y -> getOperand ( <NUM_LIT> ) ; if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return DAG . getNode ( IsSub ? <STR_LIT> : <STR_LIT> , DL , DAG . getVTList ( VT , <STR_LIT> ) , X , DAG . getConstant ( <NUM_LIT> , DL , VT ) , NewEFLAGS ) ; } } if ( CC != <STR_LIT> && CC != <STR_LIT> ) return SDValue ( ) ; SDValue Cmp = Y . getOperand ( <NUM_LIT> ) ;

if ( Cmp . getOpcode ( ) != <STR_LIT> || ! Cmp . hasOneUse ( ) || ! <STR_LIT> ( Cmp . getOperand ( <NUM_LIT> ) ) || ! Cmp . getOperand ( <NUM_LIT> ) . getValueType ( ) . isInteger ( ) ) return SDValue ( ) ;


<s> bool <ISA_LIT>AsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { OS . write_zeros ( Count % <NUM_LIT> ) ; Count /= <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) <STR_LIT> :: write < uint32_t > ( OS , <NUM_LIT> , Endian ) ;


<s> return tentativeToken ; } else { return getLexer ( ) -> Lex ( ) ;


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset ) ;

PtrOff = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackPtr , PtrOff ) ;


<s> if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) == <STR_LIT> ) { SDValue ArgValue1 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; VA = ArgLocs [ ++ i ] ; SDValue ArgValue2 ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , FI ) ) ; } else { ArgValue2 = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue1 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ArgValue , ArgValue2 , DAG . getIntPtrConstant ( <NUM_LIT> , dl ) ) ; } else ArgValue = GetF64FormalArgument ( VA , ArgLocs [ ++ i ] , Chain , DAG , dl ) ; } else { const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else if ( RegVT == <STR_LIT> ) RC = AFI -> isThumb1OnlyFunction ( ) ? & <STR_LIT> : & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt :


<s> return vabsq_f32 ( __a ) < vabsq_f32 ( __b ) ;


<s> int neon_immediate_valid_for_logic ( rtx op , machine_mode mode , int inverse , rtx * modconst , int * elementwidth ) { rtx tmpconst ; int tmpwidth ;

int retval = neon_valid_immediate ( op , mode , inverse , & tmpconst , & tmpwidth ) ;


<s> auto KernelCodeStartOr = Kernel -> getCodeOffset ( this , * TextOr ) ; if ( ! KernelCodeStartOr ) return KernelCodeStartOr . takeError ( ) ; CodeStart = KernelCodeStartOr . get ( ) ; } else { consumeError ( ExpectedKernel . takeError ( ) ) ; } auto CodeEndI = std :: upper_bound ( FunctionMarkers . begin ( ) , FunctionMarkers . end ( ) , CodeStart ) ; uint64_t CodeEnd = CodeStart ;

if ( CodeEndI != FunctionMarkers . end ( ) ) CodeEnd = * CodeEndI ;


<s> bool <ISA_LIT>FrameLowering :: expandSpillMacros ( MachineFunction & MF , SmallVectorImpl < unsigned > & NewRegs ) const { auto & HII = * MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; bool Changed = false ; for ( auto & B : MF ) { MachineBasicBlock :: iterator NextI ; for ( auto I = B . begin ( ) , E = B . end ( ) ; I != E ; I = NextI ) { MachineInstr * MI = & * I ; NextI = std :: next ( I ) ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case TargetOpcode :: COPY : Changed |= expandCopy ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandStoreInt ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandLoadInt ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : Changed |= expandStoreVecPred ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : Changed |= expandLoadVecPred ( B , I , MRI , HII , NewRegs ) ; break ; case <STR_LIT> : case <STR_LIT> : Changed |= expandLoadVec2 ( B , I , MRI , HII , NewRegs ) ;


<s> static SDValue LowerAsSplatVectorLoad ( SDValue SrcOp , MVT VT , const SDLoc & dl , SelectionDAG & DAG ) { if ( LoadSDNode * LD = dyn_cast < LoadSDNode > ( SrcOp ) ) { SDValue Ptr = LD -> getBasePtr ( ) ; if ( ! <STR_LIT> ( LD ) || LD -> isVolatile ( ) ) return SDValue ( ) ; EVT PVT = LD -> getValueType ( <NUM_LIT> ) ; if ( PVT != <STR_LIT> && PVT != <STR_LIT> ) return SDValue ( ) ; int FI = - <NUM_LIT> ; int64_t Offset = <NUM_LIT> ; if ( FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ) { FI = FINode -> getIndex ( ) ; Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ;


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const { return RI ;


<s> if ( ! AFI -> isThumbFunction ( ) ) return false ; bool Modified = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ) { MachineBasicBlock & MBB = * MFI ; ++ MFI ; Modified |= InsertITInstructions ( MBB ) ; }

if ( Modified ) AFI -> setHasITBlocks ( true ) ;


<s> <ISA_LIT>FlagsCopyLoweringPass ( ) : MachineFunctionPass ( ID ) {


<s> struct ix86_frame & frame = cfun -> machine -> frame ; if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset ;

else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) return frame . hard_frame_pointer_offset - frame . frame_pointer_offset ;


<s> if ( REG_P ( x ) && REGNO ( x ) == GBR_REG ) return true ; if ( MAYBE_BASE_REGISTER_RTX_P ( x , strict ) ) return true ; else if ( ( GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC ) && ! TARGET_SHMEDIA && MAYBE_BASE_REGISTER_RTX_P ( XEXP ( x , <NUM_LIT> ) , strict ) ) return true ; else if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( REG_P ( xop0 ) && REGNO ( xop0 ) == GBR_REG ) return gbr_displacement ( xop1 , mode ) ; if ( GET_MODE_SIZE ( mode ) <= <NUM_LIT> && MAYBE_BASE_REGISTER_RTX_P ( xop0 , strict ) && sh_legitimate_index_p ( mode , xop1 , TARGET_SH2A , false ) ) return true ; if ( ( ALLOW_INDEXED_ADDRESS || GET_MODE ( x ) == DImode || ( ( xop0 == stack_pointer_rtx || xop0 == hard_frame_pointer_rtx ) && REG_P ( xop1 ) && REGNO ( xop1 ) == R0_REG ) || ( ( xop1 == stack_pointer_rtx || xop1 == hard_frame_pointer_rtx ) && REG_P ( xop0 ) && REGNO ( xop0 ) == R0_REG ) ) && ( ( ! TARGET_SHMEDIA && GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) || ( TARGET_SHMEDIA && GET_MODE_SIZE ( mode ) <= <NUM_LIT> ) || ( ( TARGET_SH4 || TARGET_SH2A_DOUBLE ) && TARGET_FMOVD && mode == DFmode ) ) ) { if ( MAYBE_BASE_REGISTER_RTX_P ( xop1 , strict ) && MAYBE_INDEX_REGISTER_RTX_P ( xop0 , strict ) ) return true ; if ( MAYBE_INDEX_REGISTER_RTX_P ( xop1 , strict ) && MAYBE_BASE_REGISTER_RTX_P ( xop0 , strict ) ) return true ;


<s> ++ EmittedInsts ; printInstruction ( MI ) ;


<s> static MCRegister convertFPR64ToFPR16 ( MCRegister Reg ) { assert ( Reg >= <STR_LIT> && Reg <= <STR_LIT> && <STR_LIT> ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned RegNo , SMLoc StartLoc , SMLoc EndLoc , bool AddressOf = false , SMLoc OffsetOfLoc = SMLoc ( ) , StringRef SymName = StringRef ( ) , void * OpDecl = nullptr ) { auto Res = llvm :: make_unique < <ISA_LIT>Operand > ( Register , StartLoc , EndLoc ) ; Res -> Reg . RegNo = RegNo ; Res -> AddressOf = AddressOf ; Res -> OffsetOfLoc = OffsetOfLoc ; Res -> SymName = SymName ;


<s> static DecodeStatus DecodeRestrictedUPredicateOperand ( MCInst & Inst , unsigned Val , uint64_t Address , const MCDisassembler * Decoder ) {

Inst . addOperand ( MCOperand :: createImm ( ( Val & <NUM_LIT> ) == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ) ;


<s> <ISA_LIT>MCErrInfo errInfo ; if ( <ISA_LIT>MCInstrInfo :: isBundle ( MCB ) && <ISA_LIT>MCInstrInfo :: bundleSize ( MCB ) > <NUM_LIT> ) { for ( auto const & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MCB ) ) {

if ( llvm :: <ISA_LIT>MCInstrInfo :: isSolo ( MCII , * I . getInst ( ) ) ) {


<s> for ( unsigned j = <NUM_LIT> ; j < Items . size ( ) ; j ++ ) O << MAI -> getGlobalDirective ( ) << * Mang -> getSymbol ( Items [ j ] ) << <STR_LIT> ;

O << MAI -> getCommentString ( ) << <STR_LIT> << <STR_LIT> ;


<s> else if ( IDVal . startswith ( <STR_LIT> ) ) return ParseDirectiveCode ( IDVal , DirectiveID . getLoc ( ) ) ; else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setParsingInlineAsm ( false ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; return false ; } else if ( IDVal . startswith ( <STR_LIT> ) ) { getParser ( ) . setAssemblerDialect ( <NUM_LIT> ) ; getParser ( ) . setParsingInlineAsm ( true ) ; if ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) Parser . Lex ( ) ; else if ( Parser . getTok ( ) . getString ( ) == <STR_LIT> ) return Error ( DirectiveID . getLoc ( ) , <STR_LIT> <STR_LIT> <STR_LIT> ) ; } return false ; } else if ( IDVal == <STR_LIT> ) return parseDirectiveEven ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOProc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOSetFrame ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOPushReg ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOStackAlloc ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndPrologue ( DirectiveID . getLoc ( ) ) ; else if ( IDVal == <STR_LIT> ) return parseDirectiveFPOEndProc ( DirectiveID . getLoc ( ) ) ;


<s> type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == bool_char_type_node ) return <STR_LIT> ; if ( type == bool_short_type_node ) return <STR_LIT> ;

if ( type == pixel_type_node ) return <STR_LIT> ;


<s> } else if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) { V2EltIdx0 = <NUM_LIT> ; } else assert ( <NUM_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != MaxElts ; ++ i ) { if ( SVN -> getMaskElt ( i ) < <NUM_LIT> ) continue ; unsigned SrcElt = SVN -> getMaskElt ( i ) ; if ( monotonic ) { if ( SrcElt >= V2EltIdx0 ) { if ( <NUM_LIT> >= ( ++ EltsFromV2 ) ) { V2Elt = ( V2EltIdx0 - SrcElt ) << <NUM_LIT> ; } } else if ( CurrElt != SrcElt ) { monotonic = false ; } ++ CurrElt ; } if ( rotate ) { if ( PrevElt > <NUM_LIT> && SrcElt < MaxElts ) { if ( ( PrevElt == SrcElt - <NUM_LIT> ) || ( PrevElt == MaxElts - <NUM_LIT> && SrcElt == <NUM_LIT> ) ) { PrevElt = SrcElt ; if ( SrcElt == <NUM_LIT> ) V0Elt = i ; } else { rotate = false ; } } else if ( PrevElt == <NUM_LIT> ) { PrevElt = SrcElt ; } else { rotate = false ; } } } if ( EltsFromV2 == <NUM_LIT> && monotonic ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; MVT PtrVT = DAG . getTargetLoweringInfo ( ) . getPointerTy ( ) ; SDValue InitTempReg = DAG . getCopyToReg ( DAG . getEntryNode ( ) , dl , VReg , DAG . getConstant ( <NUM_LIT> , PtrVT ) ) ; SDValue ShufMaskOp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getTargetConstant ( V2Elt , <STR_LIT> ) , DAG . getCopyFromReg ( InitTempReg , dl , VReg , PtrVT ) ) ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V2 , V1 , ShufMaskOp ) ; } else if ( rotate ) { int rotamt = ( MaxElts - V0Elt ) * EltVT . getSizeInBits ( ) / <NUM_LIT> ; return DAG . getNode ( <STR_LIT> , dl , V1 . getValueType ( ) , V1 , DAG . getConstant ( rotamt , <STR_LIT> ) ) ;


<s> int size ; char * buf ; if ( symtab -> state != PARSING ) return ; size = strlen ( string ) + <NUM_LIT> ; if ( size <= microblaze_section_threshold ) section_asm_op = SDATA2_SECTION_ASM_OP ; else section_asm_op = READONLY_DATA_SECTION_ASM_OP ;

buf = ACONCAT ( ( section_asm_op , <STR_LIT> , string , <STR_LIT> , NULL ) ) ;


<s> MVT EltVT ; if ( VT . isVector ( ) ) { LogicVT = VT ; EltVT = VT . getVectorElementType ( ) ; } else if ( IsF128 ) { LogicVT = <STR_LIT> ; EltVT = VT ; } else { LogicVT = ( VT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; EltVT = VT ; } unsigned EltBits = EltVT . getSizeInBits ( ) ; APInt MaskElt = IsFABS ? APInt :: getSignedMaxValue ( EltBits ) : APInt :: getSignMask ( EltBits ) ; const fltSemantics & Sem = EltVT == <STR_LIT> ? APFloat :: IEEEdouble ( ) : ( IsF128 ? APFloat :: IEEEquad ( ) : APFloat :: IEEEsingle ( ) ) ; SDValue Mask = DAG . getConstantFP ( APFloat ( Sem , MaskElt ) , dl , LogicVT ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; bool IsFNABS = ! IsFABS && ( Op0 . getOpcode ( ) == <STR_LIT> ) ; unsigned LogicOp = IsFABS ? <STR_LIT> : IsFNABS ? <STR_LIT> : <STR_LIT> ; SDValue Operand = IsFNABS ? Op0 . getOperand ( <NUM_LIT> ) : Op0 ; if ( VT . isVector ( ) || IsF128 ) return DAG . getNode ( LogicOp , dl , LogicVT , Operand , Mask ) ;

Operand = DAG . getNode ( <STR_LIT> , dl , LogicVT , Operand ) ;


<ISA_LIT>TargetStreamer :: emitDirectiveSet<ISA_LIT>32R3 ( ) ;


<s> void <ISA_LIT>PostRASchedStrategy :: initialize ( ScheduleDAGMI * dag ) { DAG = dag ; HazardRec . setDAG ( dag ) ;


<s> if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . Lex ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { return parseDirectiveSet ( ) ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { Parser . eatToEndOfStatement ( ) ; return false ; } if ( IDVal == <STR_LIT> ) { parseDirectiveGpWord ( ) ; return false ; }


<s> MVT InSVT = InVT . getScalarType ( ) ; assert ( VT . getScalarType ( ) . getScalarSizeInBits ( ) > InSVT . getScalarSizeInBits ( ) ) ; if ( VT != <STR_LIT> && VT != <STR_LIT> && VT != <STR_LIT> ) return SDValue ( ) ; if ( InSVT != <STR_LIT> && InSVT != <STR_LIT> && InSVT != <STR_LIT> ) return SDValue ( ) ; SDLoc dl ( Op ) ; if ( Subtarget -> hasSSE41 ( ) ) return DAG . getNode ( <STR_LIT> , dl , VT , In ) ; SDValue Curr = In ; MVT CurrVT = InVT ; while ( CurrVT != VT && CurrVT . getScalarType ( ) != <STR_LIT> ) { Curr = DAG . getNode ( <STR_LIT> , dl , CurrVT , DAG . getUNDEF ( CurrVT ) , Curr ) ;

MVT CurrSVT = <STR_LIT> ( CurrVT . getScalarSizeInBits ( ) * <NUM_LIT> ) ;


<s> M . getOrInsertGlobal ( <STR_LIT> , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; FunctionCallee SecurityCheckCookie = M . getOrInsertFunction ( <STR_LIT> , Type :: getVoidTy ( M . getContext ( ) ) , Type :: getInt8PtrTy ( M . getContext ( ) ) ) ; if ( Function * F = dyn_cast < Function > ( SecurityCheckCookie . getCallee ( ) ) ) F -> addParamAttr ( <NUM_LIT> , Attribute :: AttrKind :: InReg ) ;


<s> <ISA_LIT>PacketizerList ( MachineFunction & MF , MachineLoopInfo & MLI ) : VLIWPacketizerList ( MF , MLI ) , TII ( static_cast < const <ISA_LIT>InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ) , TRI ( TII -> getRegisterInfo ( ) ) {

VLIW5 = ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasCaymanISA ( ) ;


<s> static bool rs6000_can_inline_p ( tree caller , tree callee ) { bool ret = false ; tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET ( caller ) ; tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET ( callee ) ; if ( ! callee_tree ) ret = true ; else if ( ! caller_tree ) ret = false ;


<s> else return true ; if ( Parser . getLexer ( ) . peekTokens ( Tokens ) != Tokens . size ( ) ) return true ; if ( Tokens [ Tokens . size ( ) - <NUM_LIT> ] . isNot ( AsmToken :: At ) || Tokens [ Tokens . size ( ) - <NUM_LIT> ] . isNot ( AsmToken :: Identifier ) || Tokens [ Tokens . size ( ) - <NUM_LIT> ] . getIdentifier ( ) != <STR_LIT> ) return true ; if ( Tok . is ( AsmToken :: String ) ) { StringRef SymName ; if ( Parser . parseIdentifier ( SymName ) ) return true ; Res = MCSymbolRefExpr :: create ( Ctx . getOrCreateSymbol ( SymName ) , Ctx ) ; } else { if ( Parser . parsePrimaryExpr ( Res , EndLoc , nullptr ) ) return true ; } Parser . Lex ( ) ; Parser . Lex ( ) ; } if ( parseToken ( AsmToken :: LParen , <STR_LIT> ) ) return true ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; StringRef KeyStr = Parser . getTok ( ) . getIdentifier ( ) ; auto KeyIDOrNone = <ISA_LIT>StringToPACKeyID ( KeyStr ) ; if ( ! KeyIDOrNone ) return TokError ( <STR_LIT> + KeyStr + <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: Comma , <STR_LIT> ) ) return true ; if ( Parser . getTok ( ) . isNot ( AsmToken :: Integer ) ) return TokError ( <STR_LIT> ) ; int64_t Discriminator = Parser . getTok ( ) . getIntVal ( ) ; if ( ! isUInt < <NUM_LIT> > ( Discriminator ) ) return TokError ( <STR_LIT> + itostr ( Discriminator ) + <STR_LIT> ) ; Parser . Lex ( ) ; bool UseAddressDiversity = false ; if ( Parser . getTok ( ) . is ( AsmToken :: Comma ) ) {


<s> bool HasExtraAlign = HRI . hasStackRealignment ( MF ) ; bool NoOpt = MF . getTarget ( ) . getOptLevel ( ) == CodeGenOpt :: None ; auto & HMFI = * MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned FrameSize = MFI . getStackSize ( ) ; Register SP = HRI . getStackRegister ( ) ; Register FP = HRI . getFrameRegister ( ) ; Register AP = HMFI . getStackAlignBasePhysReg ( ) ; if ( AP == <NUM_LIT> ) AP = FP ; bool UseFP = false , UseAP = false ; if ( NoOpt && ! HasExtraAlign ) UseFP = true ; if ( MFI . isFixedObjectIndex ( FI ) || MFI . isObjectPreAllocated ( FI ) ) { UseFP |= ( HasAlloca || HasExtraAlign ) ; } else { if ( HasAlloca ) { if ( HasExtraAlign ) UseAP = true ; else UseFP = true ; } } bool HasFP = hasFP ( MF ) ; assert ( ( HasFP || ! UseFP ) && <STR_LIT> ) ; if ( Offset > <NUM_LIT> && ! HasFP ) Offset -= <NUM_LIT> ;


<s> return sz == <NUM_LIT> || sz == <NUM_LIT> || sz == <NUM_LIT> || sz == <NUM_LIT> || sz == <NUM_LIT> ;


<s> bool <ISA_LIT>InstrInfo :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned CalleeFrameSize = <NUM_LIT> ; unsigned LowReg = <NUM_LIT> , HighReg = <NUM_LIT> , StartOffset = - <NUM_LIT> , EndOffset = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ;


<s> if ( DAG . getMachineFunction ( ) . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) DAG . getMachineFunction ( ) . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Outs [ i ] . Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; }

if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ;


<s> FOR_EACH_SUBRTX ( iter , array , op , ALL ) {


<s> void <ISA_LIT>AsmPrinter :: LowerJumpTableDestSmall ( llvm :: MCStreamer & OutStreamer , const llvm :: MachineInstr & MI ) { Register DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register ScratchRegW = STI -> getRegisterInfo ( ) -> getSubReg ( ScratchReg , <STR_LIT> ) ; Register TableReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register EntryReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int JTIdx = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; bool IsByteEntry = MI . getOpcode ( ) == <STR_LIT> ;

auto Label = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getJumpTableEntryPCRelSymbol ( JTIdx ) ;


<s> if ( getArgType ( FInfo ) == <ISA_LIT>LibFunc :: F32 && ( getVecSize ( FInfo ) == <NUM_LIT> ) && ( FInfo . getPrefix ( ) != <ISA_LIT>LibFunc :: NATIVE ) ) { if ( Constant * FPExpr = getNativeFunction ( CI -> getModule ( ) , <ISA_LIT>LibFunc ( <ISA_LIT>LibFunc :: EI_SQRT , FInfo ) ) ) { Value * opr0 = CI -> getArgOperand ( <NUM_LIT> ) ; DEBUG ( errs ( ) << <STR_LIT> << * CI << <STR_LIT> << <STR_LIT> << * opr0 << <STR_LIT> ) ; Value * nval = CreateCallEx ( B , FPExpr , opr0 , <STR_LIT> ) ; replaceCall ( nval ) ; return true ; }


<s> return ( int16x8_t ) __builtin_aarch64_srshr_nv8hi ( __a , __b ) ;


<s> unsigned Offset = Fixup . getOffset ( ) ; unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize ; switch ( ( unsigned ) Kind ) { default : FullSize = <NUM_LIT> ; break ; } uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= ( uint64_t ) ( ( uint8_t ) Data [ Offset + Idx ] ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( ( uint64_t ) ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ;


<s> static inline uint32_t helper_reencode_ldst_pos_imm ( uint32_t pInst , uint32_t pImm ) {

return ( pInst & ~ ( get_mask ( <NUM_LIT> ) << <NUM_LIT> ) ) | ( ( pImm & get_mask ( <NUM_LIT> ) ) << <NUM_LIT> ) ;


<s> if ( I -> isDebugValue ( ) ) continue ; if ( isUnsafeToMoveAcross ( * I , I2UseReg , I2DestReg , TRI ) ) { isSafe = false ; break ; } if ( ! KillingInstr && KilledOperand && I -> readsRegister ( KilledOperand , TRI ) ) KillingInstr = & * I ; } if ( isSafe ) { if ( KillingInstr ) { bool Added = KillingInstr -> addRegisterKilled ( KilledOperand , TRI , true ) ; ( void ) Added ; assert ( Added && <STR_LIT> ) ; removeKillInfo ( I2 , KilledOperand ) ; } DoInsertAtI1 = true ; return true ; } } { MachineBasicBlock :: iterator I ( I1 ) , End ( I2 ) ; if ( ! ShouldCombineAggressively ) End = std :: next ( MachineBasicBlock :: iterator ( I2 ) ) ; unsigned I1UseReg = UseReg ( I1 . getOperand ( <NUM_LIT> ) ) ; MachineInstr * KillingInstr = nullptr ; unsigned KilledOperand = <NUM_LIT> ; while ( ++ I != End ) { MachineInstr & MI = * I ; if ( MI . isDebugValue ( ) ) { if ( MI . readsRegister ( I1DestReg , TRI ) ) DbgMItoMove . push_back ( & MI ) ; continue ; } if ( isUnsafeToMoveAcross ( MI , I1UseReg , I1DestReg , TRI ) || ( ! MI . killsRegister ( I1UseReg ) && MI . killsRegister ( I1UseReg , TRI ) ) ) return false ; if ( I1UseReg && MI . killsRegister ( I1UseReg ) ) { assert ( ! KillingInstr && <STR_LIT> ) ; KilledOperand = I1UseReg ; KillingInstr = & MI ; } } if ( KillingInstr ) { removeKillInfo ( * KillingInstr , KilledOperand ) ; bool Added = I1 . addRegisterKilled ( KilledOperand , TRI ) ; ( void ) Added ; assert ( Added && <STR_LIT> ) ; } DoInsertAtI1 = false ; } return true ;


<s> bool <ISA_LIT>TargetLowering :: isTruncateFree ( EVT VT1 , EVT VT2 ) const { if ( ! VT1 . isInteger ( ) || ! VT2 . isInteger ( ) ) return false ;

unsigned NumBits1 = VT1 . getSizeInBits ( ) ;


<s> unsigned VF = VecTy -> getNumElements ( ) / Factor ; MVT VT = <STR_LIT> ( <STR_LIT> ( VecTy -> getScalarType ( ) ) , VF ) ; if ( Opcode == Instruction :: Load ) { static const CostTblEntry AVX512InterleavedLoadTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedLoadTbl , Factor , VT ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; TTI :: ShuffleKind ShuffleKind = ( NumOfMemOps > <NUM_LIT> ) ? TTI :: SK_PermuteTwoSrc : TTI :: SK_PermuteSingleSrc ; InstructionCost ShuffleCost = getShuffleCost ( ShuffleKind , SingleMemOpTy , None , <NUM_LIT> , nullptr ) ; unsigned NumOfLoadsInInterleaveGrp = Indices . size ( ) ? Indices . size ( ) : Factor ; auto * ResultTy = FixedVectorType :: get ( VecTy -> getElementType ( ) , VecTy -> getNumElements ( ) / Factor ) ; InstructionCost NumOfResults = getTLI ( ) -> getTypeLegalizationCost ( DL , ResultTy ) . first * NumOfLoadsInInterleaveGrp ; unsigned NumOfUnfoldedLoads = NumOfResults > <NUM_LIT> ? NumOfMemOps : NumOfMemOps / <NUM_LIT> ; unsigned NumOfShufflesPerResult = std :: max ( ( unsigned ) <NUM_LIT> , ( unsigned ) ( NumOfMemOps - <NUM_LIT> ) ) ; InstructionCost NumOfMoves = <NUM_LIT> ; if ( NumOfResults > <NUM_LIT> && ShuffleKind == TTI :: SK_PermuteTwoSrc ) NumOfMoves = NumOfResults * NumOfShufflesPerResult / <NUM_LIT> ; InstructionCost Cost = NumOfResults * NumOfShufflesPerResult * ShuffleCost + NumOfUnfoldedLoads * MemOpCost + NumOfMoves ; return Cost ; } assert ( Opcode == Instruction :: Store && <STR_LIT> ) ; static const CostTblEntry AVX512InterleavedStoreTbl [ ] = { { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } , { <NUM_LIT> , <STR_LIT> , <NUM_LIT> } } ; if ( const auto * Entry = CostTableLookup ( AVX512InterleavedStoreTbl , Factor , VT ) ) return NumOfMemOps * MemOpCost + Entry -> Cost ; unsigned NumOfSources = Factor ; InstructionCost ShuffleCost = getShuffleCost ( TTI :: SK_PermuteTwoSrc , SingleMemOpTy , None , <NUM_LIT> , nullptr ) ; unsigned NumOfShufflesPerStore = NumOfSources - <NUM_LIT> ;

unsigned NumOfMoves = NumOfMemOps * NumOfShufflesPerStore / <NUM_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: shouldReduceLoadWidth ( SDNode * Load , <STR_LIT> ExtTy , EVT NewVT ) const {

return TargetLoweringBase :: shouldReduceLoadWidth ( Load , ExtTy , NewVT ) ;


<s> * dst = aarch64_move_pointer ( * dst , <NUM_LIT> ) ; return ; } if ( known_eq ( GET_MODE_BITSIZE ( mode ) , <NUM_LIT> ) ) { * dst = adjust_address ( * dst , GET_MODE ( src ) , <NUM_LIT> ) ; emit_move_insn ( * dst , src ) ; * dst = aarch64_move_pointer ( * dst , <NUM_LIT> ) ; return ; } rtx reg = lowpart_subreg ( mode , src , GET_MODE ( src ) ) ; * dst = adjust_address ( * dst , mode , <NUM_LIT> ) ; emit_move_insn ( * dst , reg ) ;

* dst = aarch64_progress_pointer ( * dst ) ;


<s> <ISA_LIT>TargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool isLittle ) : LLVMTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , Subtarget ( TT , CPU , FS , isLittle , RM ) , DataLayout ( isLittle ? ( Subtarget . isABI_N64 ( ) ? <STR_LIT> :


<s> const FeatureBitset ArchCheck ; const FeatureBitset Features ; } Extensions [ ] = { { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> } } , { ( <STR_LIT> | <STR_LIT> ) , { Feature_HasV7Bit , Feature_IsNotMClassBit } , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV7Bit , Feature_IsNotMClassBit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV6KBit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV7Bit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8_2aBit } , { <STR_LIT> , <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8Bit } , { <STR_LIT> } } , { <STR_LIT> , { Feature_HasV8_1MMainlineBit } , { <STR_LIT> } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , { <STR_LIT> , { } , { } } , } ; MCAsmParser & Parser = getParser ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Identifier ) ) return Error ( getLexer ( ) . getLoc ( ) , <STR_LIT> ) ; StringRef Name = Parser . getTok ( ) . getString ( ) ; SMLoc ExtLoc = Parser . getTok ( ) . getLoc ( ) ; Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; bool EnableFeature = true ; if ( Name . startswith_lower ( <STR_LIT> ) ) { EnableFeature = false ; Name = Name . substr ( <NUM_LIT> ) ; } unsigned FeatureKind = <STR_LIT> ( Name ) ;

if ( FeatureKind == <STR_LIT> ) return Error ( ExtLoc , <STR_LIT> + Name ) ;


<s> if ( IsFixed || Info . hasWorkGroupIDX ( ) ) allocateSGPR32Input ( CCInfo , ArgInfo . WorkGroupIDX ) ; if ( IsFixed || Info . hasWorkGroupIDY ( ) ) allocateSGPR32Input ( CCInfo , ArgInfo . WorkGroupIDY ) ;

if ( IsFixed || Info . hasWorkGroupIDZ ( ) ) allocateSGPR32Input ( CCInfo , ArgInfo . WorkGroupIDZ ) ;


<s> void setFrameAdjustment ( MachineInstr & I , int64_t V ) const {


<s> unsigned Directive = DAG -> MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getDarwinDirective ( ) ; if ( Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || Directive == <STR_LIT> || CurSlots == <NUM_LIT> ) {


<s> int <ISA_LIT>RegisterInfo :: getDwarfRegNum ( unsigned RegNum , bool isEH ) const {


<s> Filled = true ; } } else if ( searchForward ( MBB , I ) ) { Filled = true ; } } if ( Filled ) { MachineBasicBlock :: instr_iterator DSI = I . getInstrIterator ( ) ; if ( InMicro<ISA_LIT>Mode && TII -> getInstSizeInBytes ( * std :: next ( DSI ) ) == <NUM_LIT> && DSI -> isCall ( ) ) { DSI -> setDesc ( TII -> get ( getEquivalentCallShort ( DSI -> getOpcode ( ) ) ) ) ; } continue ; } } if ( ( InMicro<ISA_LIT>Mode || ( STI . has<ISA_LIT>32r6 ( ) && <ISA_LIT>CompactBranchPolicy != CB_Never ) ) && TII -> getEquivalentCompactForm ( I ) ) { I = replaceWithCompactBranch ( MBB , I , I -> getDebugLoc ( ) ) ; continue ; } BuildMI ( MBB , std :: next ( I ) , I -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIBundleBuilder ( MBB , I , std :: next ( I , <NUM_LIT> ) ) ; } return Changed ;


<s> if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) && ! <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return LowerCall_SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ;

return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ;


<s> for ( auto * DBI : DbgValues ) for ( auto & MO : DBI -> getDebugOperandsForReg ( CurrentReg ) ) MO . setReg ( Reg ) ; CurrentReg = Reg ;


<s> MCDisassembler ( STI , Ctx ) , IsBigEndian ( bigEndian ) {


<s> CPUser ( MachineInstr * mi , MachineInstr * cpemi , unsigned maxdisp , bool neg , unsigned longformmaxdisp , unsigned longformopcode ) : MI ( mi ) , CPEMI ( cpemi ) , MaxDisp ( maxdisp ) , LongFormMaxDisp ( longformmaxdisp ) , LongFormOpcode ( longformopcode ) , NegOk ( neg ) { HighWaterMark = CPEMI -> getParent ( ) ;


<s> TargetPassConfig :: addIRPasses ( ) ; if ( TM -> getOptLevel ( ) != CodeGenOpt :: None ) addPass ( createInterleavedAccessPass ( ) ) ; if ( TM -> getOptLevel ( ) == CodeGenOpt :: Aggressive && EnableGEPOpt ) { addPass ( createSeparateConstOffsetFromGEPPass ( TM , true ) ) ;


<s> <ISA_LIT>Symbolizer ( MCContext & Ctx , std :: unique_ptr < MCRelocationInfo > && RelInfo , void * disInfo ) : MCSymbolizer ( Ctx , std :: move ( RelInfo ) ) , DisInfo ( disInfo ) {


<s> HardClauseType getHardClauseType ( const MachineInstr & MI ) { if ( MI . mayLoad ( ) ) {

if ( <ISA_LIT>InstrInfo :: isVMEM ( MI ) || <ISA_LIT>InstrInfo :: isSegmentSpecificFLAT ( MI ) ) return HARDCLAUSE_VMEM ;


<s> return ( __m128i ) __builtin_ia32_pmovqd256_mask ( ( __v4di ) __A , ( __v4si ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> , n = MI -> getNumOperands ( ) ; i < n ; ++ i ) { const MachineOperand & Op = MI -> getOperand ( i ) ; if ( ! Op . isReg ( ) ) continue ; if ( Op . getReg ( ) == InpR ) return i == n - <NUM_LIT> ;


<s> int group_count = <NUM_LIT> ; issue_rate = rs6000_issue_rate ( ) ; can_issue_more = issue_rate ; insn = get_next_active_insn ( prev_head_insn , tail ) ; next_insn = get_next_active_insn ( insn , tail ) ; while ( insn != NULL_RTX ) { can_issue_more = rs6000_variable_issue ( dump , sched_verbose , insn , can_issue_more ) ; group_end = ( next_insn == NULL_RTX || GET_MODE ( next_insn ) == TImode ) ; if ( next_insn == NULL_RTX ) break ; if ( group_end ) { if ( can_issue_more && ( rs6000_sched_insert_nops == sched_finish_pad_groups ) && ! insn_terminates_group_p ( insn , current_group ) && ! insn_terminates_group_p ( next_insn , previous_group ) ) { if ( ! is_branch_slot_insn ( next_insn ) ) can_issue_more -- ;


<s> unsigned int flags = d -> flags ; if ( ! ( flags & FLAG_AUTO_FP ) && FLOAT_MODE_P ( d -> mode ) ) flags |= FLAG_FP ;

if ( ! flag_trapping_math ) flags &= ~ FLAG_RAISE_FP_EXCEPTIONS ;


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionEntryLabel ( ) { OutStreamer . EmitRawText ( <STR_LIT> + Twine ( CurrentFnSym -> getName ( ) ) ) ; OutStreamer . EmitLabel ( CurrentFnSym ) ;


<s> MachineBasicBlock & MBB = * MI -> getParent ( ) ; auto Next = skipIgnoreExecInstsTrivialSucc ( MBB , std :: next ( MI -> getIterator ( ) ) ) ; if ( Next == MBB . end ( ) || ! LoweredEndCf . count ( & * Next ) ) continue ; Register SavedExec = TII -> getNamedOperand ( * Next , <STR_LIT> :: src1 ) -> getReg ( ) ; assert ( SavedExec . isVirtual ( ) && <STR_LIT> ) ; const MachineInstr * Def = MRI -> getUniqueVRegDef ( SavedExec ) ; if ( Def && LoweredIf . count ( SavedExec ) ) {

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; MI -> dump ( ) ) ;


<s> <ISA_LIT>CodeEmitter ( TargetMachine & tm , JITCodeEmitter & mce ) : MachineFunctionPass ( ID ) , JTI ( nullptr ) , II ( nullptr ) , TD ( nullptr ) , TM ( tm ) , MCE ( mce ) , MCPEs ( nullptr ) , MJTEs ( nullptr ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) {


<s> const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget ( ) const { return * get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) ;


<s> bool ScheduleDAGPostRA :: addEdge ( SUnit * SuccSU , const SDep & PredDep ) { if ( SuccSU != & ExitSU ) { if ( Topo . IsReachable ( PredDep . getSUnit ( ) , SuccSU ) ) return false ;

Topo . AddPred ( SuccSU , PredDep . getSUnit ( ) ) ;


<s> O << <STR_LIT> ; bool first = true ; unsigned OIdx = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = Args . size ( ) ; i != e ; ++ i , ++ OIdx ) { Type * Ty = Args [ i ] . Ty ; if ( ! first ) { O << <STR_LIT> ; } first = false ; if ( ! Outs [ OIdx ] . Flags . isByVal ( ) ) { if ( Ty -> isAggregateType ( ) || Ty -> isVectorTy ( ) || Ty -> isIntegerTy ( <NUM_LIT> ) ) { unsigned align = <NUM_LIT> ; const CallInst * CallI = cast < CallInst > ( & CB ) ; if ( ! getAlign ( * CallI , i + <NUM_LIT> , align ) ) align = DL . getABITypeAlignment ( Ty ) ; unsigned sz = DL . getTypeAllocSize ( Ty ) ; O << <STR_LIT> << align << <STR_LIT> ; O << <STR_LIT> ; O << <STR_LIT> << sz << <STR_LIT> ; SmallVector < EVT , <NUM_LIT> > vtparts ; ComputeValueVTs ( * this , DL , Ty , vtparts ) ; if ( unsigned len = vtparts . size ( ) ) OIdx += len - <NUM_LIT> ; continue ; } assert ( ( getValueType ( DL , Ty ) == Outs [ OIdx ] . VT || ( getValueType ( DL , Ty ) == <STR_LIT> && Outs [ OIdx ] . VT == <STR_LIT> ) ) && <STR_LIT> ) ; unsigned sz = <NUM_LIT> ; if ( isa < IntegerType > ( Ty ) ) { sz = cast < IntegerType > ( Ty ) -> getBitWidth ( ) ; if ( sz < <NUM_LIT> ) sz = <NUM_LIT> ; } else if ( isa < PointerType > ( Ty ) ) { sz = PtrVT . getSizeInBits ( ) ; } else if ( Ty -> isHalfTy ( ) ) sz = <NUM_LIT> ; else sz = Ty -> getPrimitiveSizeInBits ( ) ; O << <STR_LIT> << sz << <STR_LIT> ; O << <STR_LIT> ; continue ; } auto * PTy = dyn_cast < PointerType > ( Ty ) ; assert ( PTy && <STR_LIT> ) ; Type * ETy = PTy -> getElementType ( ) ; Align align = Outs [ OIdx ] . Flags . getNonZeroByValAlign ( ) ;

unsigned sz = DL . getTypeAllocSize ( ETy ) ;


<s> _Unwind_Word _Unwind_GetCFA ( _Unwind_Context * context ) {

return ( ( phase1_vrs * ) context ) -> prev_sp ;


<s> Register ScratchReg ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) { assert ( FIOperandNum == <NUM_LIT> && <STR_LIT> ) ; unsigned Op = MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; ScratchReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( ScratchReg , false , false , true ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx ) : Ctx ( ctx ) , MCII ( mcii ) {


<s> if ( REG_P ( SET_SRC ( set ) ) && ! HARD_REGISTER_P ( SET_SRC ( set ) ) && push_operand ( SET_DEST ( set ) , mode ) ) return set ; df_ref ref ; FOR_EACH_INSN_DEF ( ref , insn ) if ( HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) && ! DF_REF_FLAGS_IS_SET ( ref , DF_REF_MUST_CLOBBER ) && DF_REF_REGNO ( ref ) != FLAGS_REG ) return NULL ; FOR_EACH_INSN_USE ( ref , insn ) if ( ! DF_REF_REG_MEM_P ( ref ) && HARD_REGISTER_P ( DF_REF_REAL_REG ( ref ) ) ) return NULL ; return set ;


<s> case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> :

return lowerShiftRightParts ( Op , DAG , false ) ;


<s> if ( HasFP ) MRI . setPhysRegUsed ( <STR_LIT> ) ; if ( MFFrame -> hasCalls ( ) ) MRI . setPhysRegUsed ( <STR_LIT> ) ; const MCPhysReg * CSRegs = TRI -> getCalleeSavedRegs ( & MF ) ; for ( unsigned I = <NUM_LIT> ; CSRegs [ I ] ; ++ I ) { unsigned Reg = CSRegs [ I ] ; if ( <STR_LIT> . contains ( Reg ) && MRI . isPhysRegUsed ( Reg ) ) { MRI . setPhysRegUsed ( <STR_LIT> ) ;


<s> case Instruction :: AShr : case Instruction :: Shl : if ( Opd2Info != TTI :: OK_UniformValue && Opd2Info != TTI :: OK_UniformConstantValue ) Cost = VTy -> getNumElements ( ) * ( TargetTransformInfo :: TCC_Basic + getArithmeticInstrCost ( Opcode , VTy -> getElementType ( ) ) + TargetTransformInfo :: TCC_Basic ) ; break ;


<s> if ( DT . find ( ConstVec , CurMF , Res ) == false ) { unsigned BitWidth = getScalarOrVectorBitWidth ( SpvType ) ; <ISA_LIT>Type * SpvBaseType = getOrCreate<ISA_LIT>IntegerType ( BitWidth , I , TII ) ; Register SpvScalConst ; if ( Val ) SpvScalConst = getOrCreateConstInt ( Val , I , SpvBaseType , TII ) ; LLT LLTy = LLT :: scalar ( <NUM_LIT> ) ; Register SpvVecConst = CurMF -> getRegInfo ( ) . createGenericVirtualRegister ( LLTy ) ; const unsigned ElemCnt = SpvType -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assignVectTypeToVReg ( SpvBaseType , ElemCnt , SpvVecConst , I , TII ) ; DT . add ( ConstVec , CurMF , SpvVecConst ) ;


<s> unsigned getExceptionPointerRegister ( const Constant * PersonalityFn ) const override { return <STR_LIT> ;


<s> gcc_assert ( ! VECTOR_MODE_P ( mode ) ) ;

vmode = aarch64_simd_container_mode ( mode , <NUM_LIT> ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {


<s> void setEmitGlobConsts ( bool Val = true ) { EmitGlobConsts = Val ;


<s> if ( TailCallReturnAddrDelta < <NUM_LIT> ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( StackPtr ) . addImm ( - TailCallReturnAddrDelta ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } uint64_t NumBytes = <NUM_LIT> ; if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - SlotSize ; if ( needsStackRealignment ( MF ) ) FrameSize = ( FrameSize + MaxAlign - <NUM_LIT> ) / MaxAlign * MaxAlign ; NumBytes = FrameSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; MFI -> setOffsetAdjustment ( - NumBytes ) ; BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( FramePtr , RegState :: Kill ) ; if ( needsFrameMoves ) { FrameLabelId = MMI -> NextLabelID ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( FrameLabelId ) ; } BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , FramePtr ) . addReg ( StackPtr ) ; for ( MachineFunction :: iterator I = next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) I -> addLiveIn ( FramePtr ) ; if ( needsStackRealignment ( MF ) ) { MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) , StackPtr ) . addReg ( StackPtr ) . addImm ( - MaxAlign ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; } } else { NumBytes = StackSize - <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; } unsigned ReadyLabelId = <NUM_LIT> ; if ( needsFrameMoves ) {


<s> <ISA_LIT>_32ATTAsmParser ( const Target & T , MCAsmParser & _Parser ) : <ISA_LIT>ATTAsmParser ( T , _Parser ) {


<s> if ( ! AM . Base . Reg . getNode ( ) ) AM . Base . Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; } Base = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) ? CurDAG -> getTargetFrameIndex ( AM . Base . FrameIndex , TLI . getPointerTy ( ) ) : AM . Base . Reg ;

if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , N -> getDebugLoc ( ) , <STR_LIT> , AM . Disp , <NUM_LIT> ) ;


<s> Operands . push_back ( <STR_LIT> ( IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } if ( Tok . is ( AsmToken :: EndOfStatement ) ) { SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; auto Base = <STR_LIT> ( <NUM_LIT> , getContext ( ) . getRegisterInfo ( ) , S , E , * this ) ; Operands . push_back ( <STR_LIT> ( std :: move ( Base ) , IdVal , S , E , * this ) ) ; return MatchOperand_Success ; } Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; } Res = parseAnyRegister ( Operands ) ; if ( Res != MatchOperand_Success ) return Res ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Parser . Lex ( ) ; if ( ! IdVal ) IdVal = MCConstantExpr :: Create ( <NUM_LIT> , getContext ( ) ) ; std :: unique_ptr < <ISA_LIT>Operand > op ( static_cast < <ISA_LIT>Operand * > ( Operands . back ( ) . release ( ) ) ) ; Operands . pop_back ( ) ; if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( IdVal ) ) { int64_t Imm ; if ( IdVal -> EvaluateAsAbsolute ( Imm ) ) IdVal = MCConstantExpr :: Create ( Imm , getContext ( ) ) ;

else if ( BE -> getLHS ( ) -> getKind ( ) != MCExpr :: SymbolRef ) IdVal = MCBinaryExpr :: Create ( BE -> getOpcode ( ) , BE -> getRHS ( ) , BE -> getLHS ( ) , getContext ( ) ) ;


<s> bool MVETailPredication :: TryConvert ( Value * TripCount ) { if ( ! IsPredicatedVectorLoop ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; SetVector < Instruction * > Predicates ; auto getPredicateOp = [ ] ( IntrinsicInst * I ) { unsigned IntrinsicID = I -> getIntrinsicID ( ) ; if ( IntrinsicID == <STR_LIT> || IntrinsicID == <STR_LIT> ) return <NUM_LIT> ; return ( IntrinsicID == <STR_LIT> || isGather ( I ) ) ? <NUM_LIT> : <NUM_LIT> ; } ; for ( auto * I : MaskedInsts ) { Value * PredOp = I -> getArgOperand ( getPredicateOp ( I ) ) ; auto * Predicate = dyn_cast < Instruction > ( PredOp ) ; if ( ! Predicate || Predicates . count ( Predicate ) ) continue ; auto * ActiveLaneMask = dyn_cast < IntrinsicInst > ( Predicate ) ; if ( ! ActiveLaneMask || ActiveLaneMask -> getIntrinsicID ( ) != <STR_LIT> ) continue ; Predicates . insert ( Predicate ) ;

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ActiveLaneMask << <STR_LIT> ) ;


<s> if ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) { FrameIdx = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> getCRSpillFrameIndex ( ) ; return true ; }


<s> static bool aarch64_validate_mcpu ( const char * str , const struct processor * * res , unsigned long * isa_flags ) { enum aarch64_parse_opt_result parse_res = aarch64_parse_cpu ( str , res , isa_flags ) ; if ( parse_res == AARCH64_PARSE_OK ) return true ; switch ( parse_res ) { case AARCH64_PARSE_MISSING_ARG : error ( <STR_LIT> , str ) ; break ; case AARCH64_PARSE_INVALID_ARG :


<s> m_direct_overloads = lang_GNU_CXX ( ) ; gcc_obstack_init ( & m_string_obstack ) ;


<s> nextarg = expand_builtin_saveregs ( ) ; std_expand_builtin_va_start ( valist , nextarg ) ;


<s> <ISA_LIT>MachineFunctionInfo ( const MachineFunction & MF ) {


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> assert ( IsKnown == ( MRSReg != - <NUM_LIT> ) && <STR_LIT> ) ; auto MSRMapper = <STR_LIT> ( ) ; uint32_t MSRReg = MSRMapper . fromString ( Tok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( MSRReg != - <NUM_LIT> ) && <STR_LIT> ) ; auto PStateMapper = <STR_LIT> ( ) ; uint32_t PStateField = PStateMapper . fromString ( Tok . getString ( ) , getSTI ( ) . getFeatureBits ( ) , IsKnown ) ; assert ( IsKnown == ( PStateField != - <NUM_LIT> ) && <STR_LIT> ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , MRSReg , MSRReg , PStateField , getContext ( ) ) ) ; Parser . Lex ( ) ;


<s> case <STR_LIT> : { const TargetRegisterClass * SrcRC = getOpRegClass ( Inst , <NUM_LIT> ) ; if ( RI . isAGPRClass ( SrcRC ) ) { if ( RI . isAGPRClass ( NewDstRC ) ) return nullptr ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NewDstRC = RI . getEquivalentAGPRClass ( NewDstRC ) ; break ; default : NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; } if ( ! NewDstRC ) return nullptr ; } else { if ( RI . isVGPRClass ( NewDstRC ) || NewDstRC == & <STR_LIT> ) return nullptr ; NewDstRC = RI . getEquivalentVGPRClass ( NewDstRC ) ; if ( ! NewDstRC ) return nullptr ; } return NewDstRC ; } default : return NewDstRC ; }


<s> switch ( CC ) { case <STR_LIT> : return <STR_LIT> ;


<s> __v4sf temp , rounded ; __vector unsigned long long result ;

temp = ( __v4sf ) vec_splat ( ( __vector long long ) __A , <NUM_LIT> ) ;


return createFastVGPRRegisterAllocator ( ) ;


<s> assert ( WAReg != UnusedReg ) ; WARegs [ TargetRegisterInfo :: virtReg2Index ( VReg ) ] = WAReg ;


<s> size_t AMDGPUDevice :: getMaxGDSSize ( ) const {


<s> const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { if ( ! MI . getOperand ( i ) . isReg ( ) || ! TargetRegisterInfo :: isVirtualRegister ( MI . getOperand ( i ) . getReg ( ) ) ) continue ; if ( TRI -> hasVGPRs ( MRI . getRegClass ( MI . getOperand ( i ) . getReg ( ) ) ) ) return true ; } return false ;


<s> CI -> eraseFromParent ( ) ; return true ; } StringRef calleeName = CI -> getOperand ( CI -> getNumOperands ( ) - <NUM_LIT> ) -> getName ( ) ; if ( calleeName . startswith ( <STR_LIT> ) ) { if ( optLevel == CodeGenOpt :: None ) { isConstVec . push_back ( CI ) ; return false ; } else { Constant * CV = dyn_cast < Constant > ( CI -> getOperand ( <NUM_LIT> ) ) ; Type * aType = Type :: getInt32Ty ( * mCTX ) ; Value * Val = ( CV != NULL ) ? ConstantInt :: get ( aType , <NUM_LIT> ) : ConstantInt :: get ( aType , <NUM_LIT> ) ; CI -> replaceAllUsesWith ( Val ) ; ++ ( * bbb ) ; CI -> eraseFromParent ( ) ; return true ; } } if ( calleeName . equals ( <STR_LIT> ) ) { ConstantInt * CV = dyn_cast < ConstantInt > ( CI -> getOperand ( <NUM_LIT> ) ) ; Type * aType = Type :: getInt32Ty ( * mCTX ) ; Value * Val = CV ; if ( Val ) { Val = ConstantInt :: get ( aType , mSTM -> device ( ) -> getDeviceFlag ( ) & CV -> getZExtValue ( ) ) ; } else { Val = ConstantInt :: get ( aType , <NUM_LIT> ) ; } CI -> replaceAllUsesWith ( Val ) ; ++ ( * bbb ) ; CI -> eraseFromParent ( ) ; return true ; } Function * F = dyn_cast < Function > ( CI -> getOperand ( CI -> getNumOperands ( ) - <NUM_LIT> ) ) ; if ( ! F ) { return false ; } if ( F -> getName ( ) . startswith ( <STR_LIT> ) && ! CI -> getNumUses ( ) && F -> getName ( ) . find ( <STR_LIT> ) == StringRef :: npos ) { std :: string buffer ( F -> getName ( ) . str ( ) + <STR_LIT> ) ; F = dyn_cast < Function > ( F -> getParent ( ) -> getOrInsertFunction ( buffer , F -> getFunctionType ( ) ) ) ; atomicFuncs . push_back ( std :: make_pair < CallInst * , Function * > ( CI , F ) ) ; } if ( ! mSTM -> device ( ) -> isSupported ( <STR_LIT> ) && ! mSTM -> device ( ) -> isSupported ( <STR_LIT> ) ) { return false ; } if ( ! mConvertAtomics ) { return false ;


<s> bool EverMadeChange = false ; while ( MadeChange ) { MadeChange = false ; for ( MachineFunction :: iterator MFI = Fn . begin ( ) , E = Fn . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; unsigned MBBStartOffset = <NUM_LIT> ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ; I != E ; ++ I ) { MachineBasicBlock * Dest = <NUM_LIT> ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; const MachineOperand * DestOp ; if ( ! TII -> isBranch ( I , Cond , DestOp ) ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } MachineBasicBlock * FBB = <NUM_LIT> ; Cond . clear ( ) ; if ( TII -> AnalyzeBranch ( MBB , Dest , FBB , Cond , false ) ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } if ( Cond . empty ( ) || Cond [ <NUM_LIT> ] . getImm ( ) == <STR_LIT> ) { MBBStartOffset += TII -> GetInstSizeInBytes ( I ) ; continue ; } int BranchSize ; if ( Dest -> getNumber ( ) <= MBB . getNumber ( ) ) { BranchSize = MBBStartOffset ; for ( unsigned i = Dest -> getNumber ( ) , e = MBB . getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } else { BranchSize = - MBBStartOffset ; for ( unsigned i = MBB . getNumber ( ) , e = Dest -> getNumber ( ) ; i != e ; ++ i ) BranchSize += BlockSizes [ i ] ; } if ( isInt < <NUM_LIT> > ( BranchSize ) ) { MBBStartOffset += <NUM_LIT> ; continue ; } MachineInstr * OldBranch = I ; DebugLoc dl = OldBranch -> getDebugLoc ( ) ; TII -> ReverseBranchCondition ( Cond ) ; TII -> InsertConstBranchAtInst ( MBB , I , <NUM_LIT> , Cond , dl ) ; I = BuildMI ( MBB , I , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( Dest ) ; OldBranch -> eraseFromParent ( ) ; BlockSizes [ MBB . getNumber ( ) ] += <NUM_LIT> ; MBBStartOffset += <NUM_LIT> ; ++ NumExpanded ; MadeChange = true ; } } EverMadeChange |= MadeChange ; }


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override { return TLOF . get ( ) ;


<s> void <ISA_LIT>TargetLowering :: LowerHvxOperationWrapper ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) const {


<s> bool MadeChange = false ; MachineJumpTableInfo * MJTI = MF . getJumpTableInfo ( ) ; if ( MJTI == <NUM_LIT> ) return false ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; for ( unsigned i = <NUM_LIT> , e = T2JumpTables . size ( ) ; i != e ; ++ i ) { MachineInstr * MI = T2JumpTables [ i ] ; const TargetInstrDesc & TID = MI -> getDesc ( ) ; unsigned NumOps = TID . getNumOperands ( ) ; unsigned JTOpIdx = NumOps - ( TID . isPredicable ( ) ? <NUM_LIT> : <NUM_LIT> ) ; MachineOperand JTOP = MI -> getOperand ( JTOpIdx ) ; unsigned JTI = JTOP . getIndex ( ) ; assert ( JTI < JT . size ( ) ) ; bool ByteOk = true ; bool HalfWordOk = true ; unsigned JTOffset = GetOffsetOf ( MI ) + <NUM_LIT> ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; for ( unsigned j = <NUM_LIT> , ee = JTBBs . size ( ) ; j != ee ; ++ j ) { MachineBasicBlock * MBB = JTBBs [ j ] ; unsigned DstOffset = BBOffsets [ MBB -> getNumber ( ) ] ; if ( ByteOk && ( DstOffset - JTOffset ) > ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ByteOk = false ; unsigned TBHLimit = ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ; if ( HalfWordOk && ( DstOffset - JTOffset ) > TBHLimit ) HalfWordOk = false ; if ( ! ByteOk && ! HalfWordOk ) break ; } if ( ByteOk || HalfWordOk ) { MachineBasicBlock * MBB = MI -> getParent ( ) ; unsigned BaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool BaseRegKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( ! BaseRegKill ) continue ;

unsigned IdxReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> bool startsBefore ( Chain * Other ) { return StartInstIdx < Other -> StartInstIdx ;


<s> return EmitLow ( DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Op , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) , DAG ) ;


<s> MOVEMState ( ) : Begin ( nullptr ) , End ( nullptr ) , Base ( <NUM_LIT> ) , Start ( INT_MIN ) , Stop ( INT_MAX ) , Mask ( <NUM_LIT> ) , Access ( AccessTy :: None ) {


<s> HasTBM = false ; HasMOVBE = false ; HasRDRAND = false ; HasF16C = false ; HasFSGSBase = false ; HasLZCNT = false ; HasBMI = false ; HasBMI2 = false ; HasVBMI = false ; HasIFMA = false ; HasRTM = false ; HasERI = false ; HasCDI = false ; HasPFI = false ; HasDQI = false ; HasBWI = false ; HasVLX = false ; HasADX = false ; HasPKU = false ; HasSHA = false ; HasPRFCHW = false ; HasRDSEED = false ; HasLAHFSAHF = false ; HasMWAITX = false ; HasCLZERO = false ; HasMPX = false ; IsBTMemSlow = false ; IsPMULLDSlow = false ; IsSHLDSlow = false ; IsUAMem16Slow = false ; IsUAMem32Slow = false ; HasSSEUnalignedMem = false ; HasCmpxchg16b = false ; UseLeaForSP = false ; HasFastPartialYMMorZMMWrite = false ; HasFastScalarFSQRT = false ; HasFastVectorFSQRT = false ; HasFastLZCNT = false ; HasFastSHLDRotate = false ; HasSlowDivide32 = false ; HasSlowDivide64 = false ; PadShortFunctions = false ; CallRegIndirect = false ; LEAUsesAG = false ; SlowLEA = false ; SlowIncDec = false ; stackAlignment = <NUM_LIT> ;


<s> <ISA_LIT>MachineScheduler ( MachineSchedContext * C , std :: unique_ptr < MachineSchedStrategy > S ) : ScheduleDAGMILive ( C , std :: move ( S ) ) { addMutation ( std :: make_unique < <ISA_LIT>Subtarget :: <ISA_LIT>DAGMutation > ( ) ) ;


<s> } MI . getOperand ( FIOperandNum ) . ChangeToRegister ( FrameIndex < <NUM_LIT> ? getBaseRegister ( MF ) : getFrameRegister ( MF ) , false ) ; bool isIXAddr = usesIXAddr ( MI ) ; bool noImmForm = ! MI . isInlineAsm ( ) && OpC != TargetOpcode :: STACKMAP && OpC != TargetOpcode :: PATCHPOINT && ! ImmToIdxMap . count ( OpC ) ; int Offset = MFI -> getObjectOffset ( FrameIndex ) ; Offset += MI . getOperand ( OffsetOperandNo ) . getImm ( ) ; if ( ! MF . getFunction ( ) -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: Naked ) ) { if ( ! ( hasBasePointer ( MF ) && FrameIndex < <NUM_LIT> ) ) Offset += MFI -> getStackSize ( ) ; } assert ( OpC != <STR_LIT> && <STR_LIT> ) ; if ( ! noImmForm && ( ( isInt < <NUM_LIT> > ( Offset ) && ( ! isIXAddr || ( Offset & <NUM_LIT> ) == <NUM_LIT> ) ) || OpC == TargetOpcode :: STACKMAP || OpC == TargetOpcode :: PATCHPOINT ) ) { MI . getOperand ( OffsetOperandNo ) . ChangeToImmediate ( Offset ) ; return ; } bool is64Bit = Subtarget . is<ISA_LIT>64 ( ) ; const TargetRegisterClass * G8RC = & <STR_LIT> ; const TargetRegisterClass * GPRC = & <STR_LIT> ; const TargetRegisterClass * RC = is64Bit ? G8RC : GPRC ; unsigned SRegHi = MF . getRegInfo ( ) . createVirtualRegister ( RC ) , SReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SRegHi ) . addImm ( Offset >> <NUM_LIT> ) ; BuildMI ( MBB , II , dl , TII . get ( is64Bit ? <STR_LIT> : <STR_LIT> ) , SReg ) . addReg ( SRegHi , RegState :: Kill ) . addImm ( Offset ) ; unsigned OperandBase ; if ( noImmForm ) OperandBase = <NUM_LIT> ; else if ( OpC != TargetOpcode :: INLINEASM ) { assert ( ImmToIdxMap . count ( OpC ) && <STR_LIT> ) ; unsigned NewOpcode = ImmToIdxMap . find ( OpC ) -> second ; MI . setDesc ( TII . get ( NewOpcode ) ) ; OperandBase = <NUM_LIT> ; } else { OperandBase = OffsetOperandNo ; } unsigned StackReg = MI . getOperand ( FIOperandNum ) . getReg ( ) ; MI . getOperand ( OperandBase ) . ChangeToRegister ( StackReg , false ) ;

MI . getOperand ( OperandBase + <NUM_LIT> ) . ChangeToRegister ( SReg , false , false , true ) ;


<s> const MCExpr * IdVal ; S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . ParseExpression ( IdVal ) ) return true ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; <ISA_LIT>Operand :: CreateImm ( Op , IdVal , S , E ) ; return false ; case AsmToken :: LBrac : return ParseMemory ( Op ) ; case AsmToken :: LCurly : return ParseRegisterList ( Op ) ; case AsmToken :: Hash : S = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ;

if ( getParser ( ) . ParseExpression ( ImmVal ) ) return true ;


<s> return parseNamedBit ( <STR_LIT> , Operands ) ;


return isMemDisp12 ( BDMem , ADDR32Reg ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeLDSTPtrReg ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { auto MO = MI . getOperand ( OpNo ) ; assert ( MO . isReg ( ) ) ; switch ( MO . getReg ( ) ) { case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ;


<s> BuildMI ( MBB , InsertBefore , DL , TII -> get ( <STR_LIT> ) , Out ) . addReg ( Ssub0 ) . addReg ( Ssub1 ) . addImm ( <NUM_LIT> ) . add ( predOps ( <STR_LIT> ) ) ;


<s> static void m32r_function_arg_advance ( cumulative_args_t cum_v , machine_mode mode , const_tree type , bool named ATTRIBUTE_UNUSED ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; * cum = ( ROUND_ADVANCE_CUM ( * cum , mode , type ) + ROUND_ADVANCE_ARG ( mode , type ) ) ;


<s> SDLoc DL ( Op ) ; SDValue Ops [ ] = { Chain , DAG . getTargetConstant ( <STR_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) , DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) } ; SDValue CurrentTEB = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Ops ) ; SDValue TEB = CurrentTEB . getValue ( <NUM_LIT> ) ; Chain = CurrentTEB . getValue ( <NUM_LIT> ) ; SDValue TLSArray = DAG . getNode ( <STR_LIT> , DL , PtrVT , TEB , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; TLSArray = DAG . getLoad ( PtrVT , DL , Chain , TLSArray , MachinePointerInfo ( ) ) ; SDValue TLSIndex = DAG . getTargetExternalSymbol ( <STR_LIT> , PtrVT , <STR_LIT> ) ; TLSIndex = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex ) ; TLSIndex = DAG . getLoad ( PtrVT , DL , Chain , TLSIndex , MachinePointerInfo ( ) ) ;

SDValue Slot = DAG . getNode ( <STR_LIT> , DL , PtrVT , TLSIndex , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ;


<s> int shift_opnum = get_attr_shift ( insn ) ; enum attr_type attr_type = get_attr_type ( dep ) ; if ( shift_opnum != <NUM_LIT> && ( attr_type == TYPE_ALU_SHIFT_IMM_LSL_1TO4 || attr_type == TYPE_ALU_SHIFT_IMM_OTHER || attr_type == TYPE_ALUS_SHIFT_IMM || attr_type == TYPE_LOGIC_SHIFT_IMM || attr_type == TYPE_LOGICS_SHIFT_IMM || attr_type == TYPE_ALU_SHIFT_REG || attr_type == TYPE_ALUS_SHIFT_REG || attr_type == TYPE_LOGIC_SHIFT_REG || attr_type == TYPE_LOGICS_SHIFT_REG || attr_type == TYPE_MOV_SHIFT || attr_type == TYPE_MVN_SHIFT || attr_type == TYPE_MOV_SHIFT_REG || attr_type == TYPE_MVN_SHIFT_REG ) ) { rtx shifted_operand ; int opno ; extract_insn ( insn ) ; shifted_operand = recog_data . operand [ shift_opnum ] ; extract_insn ( dep ) ; preprocess_constraints ( dep ) ; for ( opno = <NUM_LIT> ; opno < recog_data . n_operands ; opno ++ ) { if ( recog_data . operand_type [ opno ] == OP_IN ) continue ; if ( reg_overlap_mentioned_p ( recog_data . operand [ opno ] , shifted_operand ) ) { * cost = <NUM_LIT> ; return false ;


<s> void asm_conditional_branch ( rtx_insn * insn , rtx * operands , int n_nops , int predict_taken ) { int offset = branch_dest ( insn ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) ; int len = ( offset >= - <NUM_LIT> && offset <= <NUM_LIT> ? <NUM_LIT> : offset >= - <NUM_LIT> && offset <= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; int bp = predict_taken && len == <NUM_LIT> ? <NUM_LIT> : cbranch_predicted_taken_p ( insn ) ;

int idx = ( bp << <NUM_LIT> ) | ( GET_CODE ( operands [ <NUM_LIT> ] ) == EQ ? BRF : BRT ) ;


<s> if ( TARGET_V850E3V5_UP ) { if ( CALL_P ( insn ) ) { if ( TARGET_LONG_CALLS ) { if ( length == <NUM_LIT> ) length = <NUM_LIT> ; if ( length == <NUM_LIT> ) length = <NUM_LIT> ;


<s> S . setAttributeItem ( CPU_name , <STR_LIT> ( Arch ) , false ) ; if ( EmittedArch == <STR_LIT> :: INVALID ) S . setAttributeItem ( CPU_arch , <STR_LIT> ( Arch ) , false ) ; else S . setAttributeItem ( CPU_arch , <STR_LIT> ( EmittedArch ) , false ) ; switch ( Arch ) { case <STR_LIT> :: <ISA_LIT>V2 : case <STR_LIT> :: <ISA_LIT>V2A : case <STR_LIT> :: <ISA_LIT>V3 : case <STR_LIT> :: <ISA_LIT>V3M : case <STR_LIT> :: <ISA_LIT>V4 : S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V4T : case <STR_LIT> :: <ISA_LIT>V5T : case <STR_LIT> :: XSCALE : case <STR_LIT> :: <ISA_LIT>V5TE : case <STR_LIT> :: <ISA_LIT>V6 : S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; S . setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V6T2 : S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; S . setAttributeItem ( THUMB_ISA_use , AllowThumb32 , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V6K : case <STR_LIT> :: <ISA_LIT>V6KZ : S . setAttributeItem ( <ISA_LIT>_ISA_use , Allowed , false ) ; S . setAttributeItem ( THUMB_ISA_use , Allowed , false ) ; S . setAttributeItem ( Virtualization_use , AllowTZ , false ) ; break ; case <STR_LIT> :: <ISA_LIT>V6M : S . setAttributeItem ( THUMB_ISA_use , Allowed , false ) ;


<s> if ( M -> definesRegister ( SReg , TRI ) ) break ; if ( M -> modifiesRegister ( SReg , TRI ) ) return Changed ; ReadsSreg |= M -> readsRegister ( SReg , TRI ) ; } if ( M == E || ! M -> isMoveImmediate ( ) || ! M -> getOperand ( <NUM_LIT> ) . isImm ( ) || M -> getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return Changed ; if ( ! ReadsSreg && Op2 . isKill ( ) ) { A -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( - <NUM_LIT> ) ; M -> eraseFromParent ( ) ; } } if ( ! ReadsCond && A -> registerDefIsDead ( <STR_LIT> ) && MI . killsRegister ( CondReg , TRI ) ) A -> eraseFromParent ( ) ; bool IsVCCZ = MI . getOpcode ( ) == <STR_LIT> ; if ( SReg == ExecReg ) { if ( IsVCCZ ) { MI . eraseFromParent ( ) ; return true ; }

MI . setDesc ( TII -> get ( <STR_LIT> ) ) ;


<s> return getConstantVRegValWithLookThrough ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) && getConstantVRegValWithLookThrough ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( RegShiftedImm . SrcReg ) ) ;

unsigned Imm = ( RegShiftedImm . ShiftImm == <NUM_LIT> ? <NUM_LIT> : RegShiftedImm . ShiftImm ) ;


<s> void <ISA_LIT>InstPrinter :: printImmediateV216 ( uint32_t Imm , const MCSubtargetInfo & STI , raw_ostream & O ) { uint16_t Lo16 = static_cast < uint16_t > ( Imm ) ; printImmediate16 ( Lo16 , STI , O ) ;


<s> Builder . SetCurrentDebugLocation ( FDiv . getDebugLoc ( ) ) ; Function * Decl = <STR_LIT> ( Mod , <STR_LIT> ) ; Value * Num = FDiv . getOperand ( <NUM_LIT> ) ; Value * Den = FDiv . getOperand ( <NUM_LIT> ) ; Value * NewFDiv = nullptr ; if ( VectorType * VT = dyn_cast < VectorType > ( Ty ) ) { NewFDiv = UndefValue :: get ( VT ) ; for ( unsigned I = <NUM_LIT> , E = VT -> getNumElements ( ) ; I != E ; ++ I ) { Value * NumEltI = Builder . CreateExtractElement ( Num , I ) ; Value * DenEltI = Builder . CreateExtractElement ( Den , I ) ; Value * NewElt ; if ( shouldKeepFDivF32 ( NumEltI , UnsafeDiv ) ) { NewElt = Builder . CreateFDiv ( NumEltI , DenEltI ) ; } else { NewElt = Builder . CreateCall ( Decl , { NumEltI , DenEltI } ) ; }

NewFDiv = Builder . CreateInsertElement ( NewFDiv , NewElt , I ) ;


<s> case CEK_Special : llvm_unreachable ( <STR_LIT> ) ; break ; case CEK_ABS_HI : case CEK_ABS_LO :


<s> THMToTHMStub :: ~ THMToTHMStub ( ) {


<s> return Op ; } RTLIB :: Libcall LC ; if ( IsSigned ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; else LC = RTLIB :: getUINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ; return LowerF128ToCall ( Op , DAG , LC ) ;


<s> if ( Mov == <NUM_LIT> || ! TII -> isMov ( Mov -> getMachineOpcode ( ) ) ) return false ; const SDValue & Op = Mov -> getOperand ( <NUM_LIT> ) ; int32_t Value = analyzeImmediate ( Op . getNode ( ) ) ; if ( Value == - <NUM_LIT> ) { return false ; } else if ( Value == <NUM_LIT> ) { Operand = Op ; return true ; } else if ( Value == Immediate ) { Operand = Op ; return true ; } else if ( ! ScalarSlotUsed && ! Immediate ) { ScalarSlotUsed = true ; Immediate = Value ;


<s> return DAG . getMemcpy ( Chain , dl , Dst , Src , SizeNode , Flags . getByValAlign ( ) , false , false , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> if ( ( CI . Offset % CI . EltSize != <NUM_LIT> ) || ( Paired . Offset % CI . EltSize != <NUM_LIT> ) ) return false ; if ( CI . InstClass == TBUFFER_LOAD || CI . InstClass == TBUFFER_STORE ) { const llvm :: <STR_LIT> * Info0 = llvm :: <STR_LIT> ( CI . Format , STI ) ; if ( ! Info0 ) return false ; const llvm :: <STR_LIT> * Info1 = llvm :: <STR_LIT> ( Paired . Format , STI ) ; if ( ! Info1 ) return false ; if ( Info0 -> BitsPerComp != Info1 -> BitsPerComp || Info0 -> NumFormat != Info1 -> NumFormat ) return false ; if ( Info0 -> BitsPerComp != <NUM_LIT> ) return false ; if ( getBufferFormatWithCompCount ( CI . Format , CI . Width + Paired . Width , STI ) == <NUM_LIT> ) return false ; } uint32_t EltOffset0 = CI . Offset / CI . EltSize ; uint32_t EltOffset1 = Paired . Offset / CI . EltSize ; CI . UseST64 = false ; CI . BaseOff = <NUM_LIT> ; if ( ( CI . InstClass != DS_READ ) && ( CI . InstClass != DS_WRITE ) ) { return ( EltOffset0 + CI . Width == EltOffset1 || EltOffset1 + Paired . Width == EltOffset0 ) && CI . CPol == Paired . CPol ; } if ( ( EltOffset0 % <NUM_LIT> == <NUM_LIT> ) && ( EltOffset1 % <NUM_LIT> ) == <NUM_LIT> && isUInt < <NUM_LIT> > ( EltOffset0 / <NUM_LIT> ) && isUInt < <NUM_LIT> > ( EltOffset1 / <NUM_LIT> ) ) { if ( Modify ) { CI . Offset = EltOffset0 / <NUM_LIT> ; Paired . Offset = EltOffset1 / <NUM_LIT> ; CI . UseST64 = true ; } return true ; } if ( isUInt < <NUM_LIT> > ( EltOffset0 ) && isUInt < <NUM_LIT> > ( EltOffset1 ) ) { if ( Modify ) { CI . Offset = EltOffset0 ; Paired . Offset = EltOffset1 ; } return true ; } uint32_t Min = std :: min ( EltOffset0 , EltOffset1 ) ; uint32_t Max = std :: max ( EltOffset0 , EltOffset1 ) ; const uint32_t Mask = maskTrailingOnes < uint32_t > ( <NUM_LIT> ) * <NUM_LIT> ; if ( ( ( Max - Min ) & ~ Mask ) == <NUM_LIT> ) { if ( Modify ) { uint32_t BaseOff = mostAlignedValueInRange ( Max - <NUM_LIT> * <NUM_LIT> , Min ) ; BaseOff |= Min & maskTrailingOnes < uint32_t > ( <NUM_LIT> ) ; CI . BaseOff = BaseOff * CI . EltSize ; CI . Offset = ( EltOffset0 - BaseOff ) / <NUM_LIT> ; Paired . Offset = ( EltOffset1 - BaseOff ) / <NUM_LIT> ; CI . UseST64 = true ; } return true ;


<s> MF . push_back ( Label ) ; Iter = std :: next ( MachineFunction :: iterator ( Bottom ) ) ; } MachineBasicBlock * AfterLoop = & * Iter ; auto InsertPos = MBB . begin ( ) ; while ( InsertPos != MBB . end ( ) && InsertPos -> getOpcode ( ) == <STR_LIT> ) ++ InsertPos ; MachineInstr * Begin = BuildMI ( MBB , InsertPos , MBB . findDebugLoc ( InsertPos ) , TII . get ( <STR_LIT> ) ) . addImm ( int64_t ( <STR_LIT> :: Void ) ) ; DebugLoc EndDL = ( * AfterLoop -> pred_rbegin ( ) ) -> findBranchDebugLoc ( ) ; MachineInstr * End = BuildMI ( * AfterLoop , AfterLoop -> begin ( ) , EndDL , TII . get ( <STR_LIT> ) ) ; LoopTops [ End ] = Begin ; assert ( ( ! ScopeTops [ AfterLoop -> getNumber ( ) ] || ScopeTops [ AfterLoop -> getNumber ( ) ] -> getNumber ( ) < MBB . getNumber ( ) ) && <STR_LIT> ) ; if ( ! ScopeTops [ AfterLoop -> getNumber ( ) ] ) ScopeTops [ AfterLoop -> getNumber ( ) ] = & MBB ;


<s> Parser . Lex ( ) ; if ( ! parsePtrReg ( Operands , RegKind ) ) return MatchOperand_NoMatch ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RParen ) ) return MatchOperand_NoMatch ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , getLexer ( ) . getLoc ( ) ) ) ;


<s> } else if ( ! strncmp ( ACPV -> getSymbol ( ) , <STR_LIT> , <NUM_LIT> ) ) Name = ACPV -> getSymbol ( ) ; else Name = Mang -> makeNameProper ( ACPV -> getSymbol ( ) ) ; O << Name ; if ( ACPV -> hasModifier ( ) ) O << <STR_LIT> << ACPV -> getModifier ( ) << <STR_LIT> ; if ( ACPV -> getPCAdjustment ( ) != <NUM_LIT> ) { O << <STR_LIT> << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << ACPV -> getLabelId ( ) << <STR_LIT> << ( unsigned ) ACPV -> getPCAdjustment ( ) ; if ( ACPV -> mustAddCurrentAddress ( ) ) O << <STR_LIT> ;


<s> return true ; } } } } if ( N . getOpcode ( ) != <STR_LIT> && N . getOpcode ( ) != <STR_LIT> && ! CurDAG -> isBaseWithConstantOffset ( N ) ) return false ; if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) return false ; } <STR_LIT> AddSub = N . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; <STR_LIT> ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; unsigned ShAmt = <NUM_LIT> ; Base = N . getOperand ( <NUM_LIT> ) ; Offset = N . getOperand ( <NUM_LIT> ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( Offset , ShOpcVal , ShAmt ) ) Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ; } } else { ShOpcVal = <STR_LIT> ; } } if ( N . getOpcode ( ) != <STR_LIT> && ShOpcVal == <STR_LIT> && ! ( Subtarget -> isLikeA9 ( ) || Subtarget -> isSwift ( ) || N . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ) { ShOpcVal = <STR_LIT> ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) ; if ( ShOpcVal != <STR_LIT> ) { if ( ConstantSDNode * Sh = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ) { ShAmt = Sh -> getZExtValue ( ) ; if ( isShifterOpProfitable ( N . getOperand ( <NUM_LIT> ) , ShOpcVal , ShAmt ) ) { Offset = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Base = N . getOperand ( <NUM_LIT> ) ; } else { ShAmt = <NUM_LIT> ; ShOpcVal = <STR_LIT> ;


<s> bool hasLeonCasa ( ) const { return HasLeonCasa ;


<s> return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const MachineOperand OpFI = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpFI . isFI ( ) ) return <NUM_LIT> ; const MachineOperand OpOff = MI . getOperand ( <NUM_LIT> ) ; if ( ! OpOff . isImm ( ) || OpOff . getImm ( ) != <NUM_LIT> ) return <NUM_LIT> ; FrameIndex = OpFI . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } }


<s> } else if ( attr_type == TYPE_FPALU ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) { pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; } if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return <NUM_LIT> ; if ( reg_mentioned_p ( SET_DEST ( pat ) , SET_SRC ( dep_pat ) ) ) { if ( ! recog_memoized ( dep_insn ) ) return <NUM_LIT> ; switch ( get_attr_type ( dep_insn ) ) { case TYPE_FPDIVSGL : case TYPE_FPDIVDBL : case TYPE_FPSQRTSGL : case TYPE_FPSQRTDBL : return insn_default_latency ( dep_insn ) - <NUM_LIT> ; default : return <NUM_LIT> ; } } } return <NUM_LIT> ; case REG_DEP_OUTPUT : if ( attr_type == TYPE_FPLOAD ) { rtx pat = PATTERN ( insn ) ; rtx dep_pat = PATTERN ( dep_insn ) ; if ( GET_CODE ( pat ) == PARALLEL ) { pat = XVECEXP ( pat , <NUM_LIT> , <NUM_LIT> ) ; } if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) return <NUM_LIT> ; if ( reg_mentioned_p ( SET_DEST ( pat ) , SET_DEST ( dep_pat ) ) ) { if ( ! recog_memoized ( dep_insn ) ) return <NUM_LIT> ; switch ( get_attr_type ( dep_insn ) ) { case TYPE_FPALU : case TYPE_FPMULSGL : case TYPE_FPMULDBL : case TYPE_FPDIVSGL : case TYPE_FPDIVDBL : case TYPE_FPSQRTSGL : case TYPE_FPSQRTDBL : return insn_default_latency ( dep_insn ) - <NUM_LIT> ; default : return <NUM_LIT> ; } }


<s> return EmitAtomicBinary ( MI , BB , <NUM_LIT> , isThumb2 ? <STR_LIT> : <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , isThumb2 ? <STR_LIT> : <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , isThumb2 ? <STR_LIT> : <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , isThumb2 ? <STR_LIT> : <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , isThumb2 ? <STR_LIT> : <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , isThumb2 ? <STR_LIT> : <STR_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicBinary ( MI , BB , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : return EmitAtomicCmpSwap ( MI , BB , <NUM_LIT> ) ; case <STR_LIT> : { const BasicBlock * LLVM_BB = BB -> getBasicBlock ( ) ; MachineFunction :: iterator It = BB ; ++ It ; MachineBasicBlock * thisMBB = BB ; MachineFunction * F = BB -> getParent ( ) ; MachineBasicBlock * copy0MBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * sinkMBB = F -> CreateMachineBasicBlock ( LLVM_BB ) ; F -> insert ( It , copy0MBB ) ; F -> insert ( It , sinkMBB ) ; sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , llvm :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( sinkMBB ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , Register SrcReg , bool isKill , int FI , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FI ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ;

if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> MRE . r_word0 = ( ( Addr << <NUM_LIT> ) | ( Type << <NUM_LIT> ) | ( Log2Size << <NUM_LIT> ) | ( IsPCRel << <NUM_LIT> ) | MachO :: R_SCATTERED ) ;


<s> static const CostTblEntry < <STR_LIT> > SSE42CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX1CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX2CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; static const CostTblEntry < <STR_LIT> > AVX512CostTbl [ ] = { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST -> hasAVX512 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX512CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX2 ( ) ) if ( const auto * Entry = CostTableLookup ( AVX2CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasAVX ( ) ) if ( const auto * Entry = CostTableLookup ( AVX1CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; if ( ST -> hasSSE42 ( ) ) if ( const auto * Entry = CostTableLookup ( SSE42CostTbl , ISD , MTy ) ) return LT . first * Entry -> Cost ; return BaseT :: getCmpSelInstrCost ( Opcode , ValTy , CondTy ) ;


<s> tmpInst . setOpcode ( <STR_LIT> ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: CreateReg ( RegNo ) ) ; tmpInst . addOperand ( MCOperand :: CreateImm ( ( ( Value & ( <NUM_LIT> << Shift ) ) >> Shift ) ) ) ;


<s> unsigned <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const {


<s> SDValue ShOpHi = Op . getOperand ( <NUM_LIT> ) ; SDValue ShAmt = Op . getOperand ( <NUM_LIT> ) ; SDValue <ISA_LIT>CC ; unsigned Opc = ( Op . getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; assert ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) ; SDValue RevShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( VTBits , <STR_LIT> ) , ShAmt ) ; SDValue Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpLo , ShAmt ) ; SDValue ExtraShAmt = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ShAmt , DAG . getConstant ( VTBits , <STR_LIT> ) ) ; SDValue Tmp2 = DAG . getNode ( <STR_LIT> , dl , VT , ShOpHi , RevShAmt ) ; SDValue FalseVal = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , Tmp2 ) ; SDValue TrueVal = DAG . getNode ( Opc , dl , VT , ShOpHi , ExtraShAmt ) ; SDValue CCR = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue Cmp = get<ISA_LIT>Cmp ( ExtraShAmt , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , <STR_LIT> , <ISA_LIT>CC , DAG , dl ) ; SDValue Hi = DAG . getNode ( Opc , dl , VT , ShOpHi , ShAmt ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , VT , FalseVal , TrueVal , <ISA_LIT>CC , CCR , Cmp ) ; SDValue Ops [ <NUM_LIT> ] = { Lo , Hi } ; return DAG . getMergeValues ( Ops , <NUM_LIT> , dl ) ;


<s> LastMappingSymbols [ getPreviousSection ( ) . first ] = LastEMS ; LastEMS = LastMappingSymbols . lookup ( Section ) ;

MCELFStreamer :: changeSection ( Section , Subsection ) ;


<s> Error ( StrLoc , <STR_LIT> ) ; return false ; } unsigned AndMask = <NUM_LIT> ; unsigned OrMask = <NUM_LIT> ; unsigned XorMask = <NUM_LIT> ; for ( size_t i = <NUM_LIT> ; i < Ctl . size ( ) ; ++ i ) { unsigned Mask = <NUM_LIT> << ( BITMASK_WIDTH - <NUM_LIT> - i ) ; switch ( Ctl [ i ] ) {


<s> bool isPaired ( ) const { return Reg2 != <STR_LIT> ;


<s> unsigned <ISA_LIT>TTIImpl :: getCmpSelInstrCost ( unsigned Opcode , Type * ValTy , Type * CondTy ) { int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; if ( ST -> hasNEON ( ) && ValTy -> isVectorTy ( ) && ISD == <STR_LIT> ) { static const TypeConversionCostTblEntry < <STR_LIT> > NEONVectorSelectTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> * <NUM_LIT> + <NUM_LIT> * <NUM_LIT> + <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT>


<s> rtx scratch ; int move ; alpha_split_tmode_pair ( operands , TFmode , false ) ; move = <NUM_LIT> ; if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) move = <NUM_LIT> ; else if ( rtx_equal_p ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ) { if ( rtx_equal_p ( operands [ <NUM_LIT> ] , high_bit ) ) move = <NUM_LIT> ; else move = - <NUM_LIT> ; } if ( move < <NUM_LIT> ) emit_move_insn ( operands [ <NUM_LIT> ] , operands [ <NUM_LIT> ] ) ; scratch = operands [ move < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ] ;

emit_insn ( ( * operation ) ( scratch , high_bit , operands [ <NUM_LIT> ] ) ) ;


<s> switch ( RetOpcode ) { case <STR_LIT> : case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } uint64_t StackSize = MFI -> getStackSize ( ) ; unsigned CSSize = <ISA_LIT>FI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = <NUM_LIT> ; if ( hasFP ( MF ) ) { uint64_t FrameSize = StackSize - <NUM_LIT> ; NumBytes = FrameSize - CSSize ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; } else NumBytes = StackSize - CSSize ; while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = prior ( MBBI ) ; unsigned Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) break ; -- MBBI ; } DL = MBBI -> getDebugLoc ( ) ; if ( MFI -> hasVarSizedObjects ( ) ) {

BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> return <ISA_LIT>GenRegisterInfo :: getDwarfRegNumFull ( RegNum , <NUM_LIT> ) ;


<s> virtual bool doesSectionRequireSymbols ( const MCSection & Section ) const { return false ;


<s> assert ( isCondBranch ( MI ) ) ; MachineBasicBlock :: iterator I = MI ; MachineBasicBlock * TrueBranch = getTrueBranch ( MI ) ; int OldOpcode = MI -> getOpcode ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; bool UseContinueLogical = ( ( & * ContingMBB -> rbegin ( ) ) == MI ) ; if ( ! UseContinueLogical ) { int BranchOpcode = TrueBranch == ContMBB ? getBranchNzeroOpcode ( OldOpcode ) : getBranchZeroOpcode ( OldOpcode ) ; insertCondBranchBefore ( I , BranchOpcode , DL ) ; insertInstrEnd ( ContingMBB , <STR_LIT> , DL ) ; insertInstrEnd ( ContingMBB , <STR_LIT> , DL ) ; } else { int BranchOpcode = TrueBranch == ContMBB ? getContinueNzeroOpcode ( OldOpcode ) : getContinueZeroOpcode ( OldOpcode ) ; insertCondBranchBefore ( I , BranchOpcode , DL ) ;


<s> assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < Op . getNumOperands ( ) ; i ++ ) if ( ! <STR_LIT> ( Op . getOperand ( i ) . getNode ( ) ) ) return false ;


<s> RegisterTarget < Triple :: mips64 , true > A ( getThe<ISA_LIT>64Target ( ) , <STR_LIT> , <STR_LIT> ) ; RegisterTarget < Triple :: mips64el , true > B ( getThe<ISA_LIT>64elTarget ( ) , <STR_LIT> , <STR_LIT> ) ;


<s> Val = - Val ; } } if ( <STR_LIT> ( AsmParser -> getMII ( ) -> get ( Inst . getOpcode ( ) ) , Inst . getNumOperands ( ) ) ) { addLiteralImmOperand ( Inst , Val ) ; } else {

Inst . addOperand ( MCOperand :: createImm ( Val ) ) ;


<s> if ( is<ISA_LIT>LowRegister ( Reg ) ) return <STR_LIT> ; switch ( Reg ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; }

return TargetRegisterInfo :: getPhysicalRegisterRegClass ( Reg , VT ) ;


<s> DelJmp ( TargetMachine & tm ) : MachineFunctionPass ( ID ) {


<s> case <STR_LIT> : case <STR_LIT> : return LowerFP_TO_INT ( Op , DAG , SDLoc ( Op ) ) ; case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerSIGN_EXTEND_INREG ( Op , DAG ) ; case <STR_LIT> : return LowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerREM ( Op , DAG ) ; case <STR_LIT> : return LowerBSWAP ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_CMP_SWAP ( Op , DAG ) ;


<s> if ( Lookup ) return Lookup -> MaxVersion ;


<s> static void tilepro_file_end ( void ) { if ( NEED_INDICATE_EXEC_STACK ) file_end_indicate_exec_stack ( ) ;


<s> bool worker = mask & GOMP_DIM_MASK ( GOMP_DIM_WORKER ) ; bool large_vector = ( mask & GOMP_DIM_MASK ( GOMP_DIM_VECTOR ) ) && nvptx_mach_vector_length ( ) != PTX_WARP_SIZE ;


gcc_obstack_init ( & m_string_obstack ) ;


<s> MCDataFragment * Frag = getOrCreateDataFragment ( ) ;

Frag -> getFixups ( ) . push_back ( MCFixup :: create ( Frag -> getContents ( ) . size ( ) , Expr , Kind ) ) ;


<s> if ( MemOperand != - <NUM_LIT> ) { switch ( MI . getOperand ( MemOperand + <STR_LIT> ) . getReg ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ; break ; } } break ; case <STR_LIT> : EmitByte ( <NUM_LIT> , CurByte , OS ) ;


<s> bool hasSymbolicDisplacement ( ) const {

return GV != <NUM_LIT> || CP != <NUM_LIT> || ES != <NUM_LIT> || JT != - <NUM_LIT> || BlockAddr != <NUM_LIT> ;


<s> return <ISA_LIT>Operand :: CreateImm ( <NUM_LIT> , SMLoc ( ) , <ISA_LIT>Operand :: ImmTyLWE ) ;


<s> bool Is32Bit = ( MRI . getType ( LHS . getReg ( ) ) . getSizeInBits ( ) == <NUM_LIT> ) ; auto RC = Is32Bit ? & <STR_LIT> : & <STR_LIT> ;

return emitADDS ( MRI . createVirtualRegister ( RC ) , LHS , RHS , MIRBuilder ) ;


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > Y ( The<ISA_LIT>_64Target ) ; PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ;


<s> switch ( OpC ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> SDValue <ISA_LIT>TargetLowering :: lowerConstantPool ( SDValue Op , SelectionDAG & DAG ) const { ConstantPoolSDNode * N = cast < ConstantPoolSDNode > ( Op ) ; EVT Ty = Op . getValueType ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! ABI . IsN64 ( ) ) {

const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ;


<s> if ( Subtarget . isTargetWin64 ( ) || Subtarget . isTargetPS4 ( ) ) this -> Options . TrapUnreachable = true ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , true , <NUM_LIT> ) ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , false , <NUM_LIT> ) ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , true , <NUM_LIT> ) ; this -> Options . Reciprocals . setDefaults ( <STR_LIT> , true , <NUM_LIT> ) ;


<s> int ParitySrc [ <NUM_LIT> ] = { - <NUM_LIT> , - <NUM_LIT> } ; unsigned Size = Mask . size ( ) ; for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) { int M = Mask [ i ] ; if ( M < <NUM_LIT> ) continue ; if ( ( M % Size ) != i ) return false ; int Src = M / Size ; if ( ParitySrc [ i % <NUM_LIT> ] >= <NUM_LIT> && ParitySrc [ i % <NUM_LIT> ] != Src ) return false ; ParitySrc [ i % <NUM_LIT> ] = Src ; } if ( ParitySrc [ <NUM_LIT> ] < <NUM_LIT> || ParitySrc [ <NUM_LIT> ] < <NUM_LIT> || ParitySrc [ <NUM_LIT> ] == ParitySrc [ <NUM_LIT> ] ) return false ;

Op0Even = ParitySrc [ <NUM_LIT> ] == <NUM_LIT> ;


<s> } if ( ix86_cmodel == CM_LARGE_PIC && ! TARGET_PECOFF ) { rtx unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , ix86_tls_symbol ) , UNSPEC_PLTOFF ) ; return gen_rtx_PLUS ( Pmode , pic_offset_table_rtx , gen_rtx_CONST ( Pmode , unspec ) ) ; } return ix86_tls_symbol ;


<s> emit_insn ( gen_addxf3 ( e2 , e2 , e1 ) ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ; emit_label ( jump_label ) ; LABEL_NUSES ( jump_label ) = <NUM_LIT> ;


<s> static DecodeStatus DecodeACC64DSPRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo >= <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Reg = getReg ( Decoder , <STR_LIT> , RegNo ) ;

Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ;


<s> return performXorCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performMulCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performIntToFpCombine ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return performFpToIntCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performFDivCombine ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return performORCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : return performANDCombine ( N , DCI ) ; case <STR_LIT> : return performSRLCombine ( N , DCI ) ; case <STR_LIT> : return performIntrinsicCombine ( N , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performExtendCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSignExtendInRegCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performConcatVectorsCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performSelectCombine ( N , DCI ) ; case <STR_LIT> : return performVSelectCombine ( N , DCI . DAG ) ; case <STR_LIT> : if ( performTBISimplification ( N -> getOperand ( <NUM_LIT> ) , DCI , DAG ) ) return SDValue ( N , <NUM_LIT> ) ; break ; case <STR_LIT> : return performSTORECombine ( N , DCI , DAG , Subtarget ) ; case <STR_LIT> : return performBRCONDCombine ( N , DCI , DAG ) ; case <STR_LIT> : case <STR_LIT> : return performTBZCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performCONDCombine ( N , DCI , DAG , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , false ) ; case <STR_LIT> : return performNVCASTCombine ( N ) ; case <STR_LIT> : return performPostLD1Combine ( N , DCI , true ) ; case <STR_LIT> : case <STR_LIT> : switch ( cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performNEONPostLDSTCombine ( N , DCI , DAG ) ; case <STR_LIT> : return performLDNT1Combine ( N , DAG ) ;


<s> int LROffset = <ISA_LIT>FrameInfo :: getReturnSaveOffset ( is<ISA_LIT>64 , isDarwinABI ) ; RASI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , LROffset , true , false ) ; FI -> setReturnAddrSaveIndex ( RASI ) ;


<s> getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> static tree avr_handle_progmem_attribute ( tree * node , tree name , tree args ATTRIBUTE_UNUSED , int flags ATTRIBUTE_UNUSED , bool * no_add_attrs ) { if ( DECL_P ( * node ) ) { if ( TREE_CODE ( * node ) == TYPE_DECL ) {


<s> int RegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RegScavFI ) ; if ( RVVStackSize != <NUM_LIT> ) { int RVVRegScavFI = MFI . CreateStackObject ( RegInfo -> getSpillSize ( * RC ) , RegInfo -> getSpillAlign ( * RC ) , false ) ; RS -> addScavengingFrameIndex ( RVVRegScavFI ) ; } } if ( MFI . getCalleeSavedInfo ( ) . empty ( ) || RVFI -> useSaveRestoreLibCalls ( MF ) ) { RVFI -> setCalleeSavedStackSize ( <NUM_LIT> ) ; return ; } unsigned Size = <NUM_LIT> ; for ( const auto & Info : MFI . getCalleeSavedInfo ( ) ) { int FrameIdx = Info . getFrameIdx ( ) ;

if ( MFI . getStackID ( FrameIdx ) != TargetStackID :: Default ) continue ;


<s> unsigned Addr = getStackAddress ( VA , MMO ) ; unsigned ExtReg = extendRegister ( ValVReg , VA ) ; MIRBuilder . buildStore ( ExtReg , Addr , * MMO ) ;


<s> bool SNITCHFrepLoops :: isInvalidLoopOperation ( const MachineInstr * MI ) const { bool validInstr = true ; for ( auto MO : MI -> operands ( ) ) if ( MO . isReg ( ) && MO . getReg ( ) . isVirtual ( ) ) if ( MRI -> getRegClass ( MO . getReg ( ) ) != & <STR_LIT> || MRI -> getRegClass ( MO . getReg ( ) ) != & <STR_LIT> ) validInstr = false ;


<s> if ( Op . getValueType ( ) . isVector ( ) ) return SDValue ( ) ;

std :: pair < SDValue , SDValue > Vals = FP_TO_INTHelper ( Op , DAG , true ) ;


<s> SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; DebugLoc dl = GA -> getDebugLoc ( ) ; SDValue TGA = DAG . getTargetGlobalAddress ( GA -> getGlobal ( ) , GA -> getValueType ( <NUM_LIT> ) , GA -> getOffset ( ) , OperandFlags ) ; if ( InFlag ) { SDValue Ops [ ] = { Chain , TGA , * InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , <NUM_LIT> ) ; } else {


<s> const uint8_t ThisNopLength = ( uint8_t ) std :: min ( Count , MaxNopLength ) ; const uint8_t Prefixes = ThisNopLength <= <NUM_LIT> ? <NUM_LIT> : ThisNopLength - <NUM_LIT> ; for ( uint8_t i = <NUM_LIT> ; i < Prefixes ; i ++ ) OW -> Write8 ( <NUM_LIT> ) ; const uint8_t Rest = ThisNopLength - Prefixes ; for ( uint8_t i = <NUM_LIT> ; i < Rest ; i ++ ) OW -> Write8 ( Nops [ Rest - <NUM_LIT> ] [ i ] ) ; Count -= ThisNopLength ; } while ( Count != <NUM_LIT> ) ;


<s> SDNode * N = CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , DL , <STR_LIT> ) ;


<s> void emitBundleLock ( bool AlignToEnd ) override {


<s> gcc_assert ( GET_CODE ( x ) == CONST ) ; plus = XEXP ( x , <NUM_LIT> ) ; if ( GET_CODE ( plus ) == PLUS || GET_CODE ( plus ) == MINUS ) { rtx unspec ; rtx addend ; unspec = XEXP ( plus , <NUM_LIT> ) ; gcc_assert ( GET_CODE ( unspec ) == UNSPEC ) ; addend = XEXP ( plus , <NUM_LIT> ) ;


<s> MachineEvaluator ( const TargetRegisterInfo & T , MachineRegisterInfo & M ) : TRI ( T ) , MRI ( M ) {


<s> rtx ( * gen ) ( rtx , rtx , rtx , rtx ) ; rtx offset ; unsigned int location ; unsigned int next = d -> perm [ <NUM_LIT> ] + <NUM_LIT> ; if ( BYTES_BIG_ENDIAN ) return false ; for ( i = <NUM_LIT> ; i < nelt ; next ++ , i ++ ) { if ( next == <NUM_LIT> * nelt ) return false ; if ( d -> one_vector_p && ( next == nelt ) ) { if ( ( nelt == <NUM_LIT> ) && ( d -> vmode != V2DImode ) ) return false ; else next = <NUM_LIT> ; } if ( d -> perm [ i ] != next ) return false ; } location = d -> perm [ <NUM_LIT> ] ; switch ( d -> vmode ) { case V16QImode : gen = gen_neon_vextv16qi ; break ; case V8QImode : gen = gen_neon_vextv8qi ; break ; case V4HImode : gen = gen_neon_vextv4hi ; break ; case V8HImode : gen = gen_neon_vextv8hi ; break ; case V2SImode : gen = gen_neon_vextv2si ; break ; case V4SImode : gen = gen_neon_vextv4si ; break ; case V2SFmode : gen = gen_neon_vextv2sf ; break ; case V4SFmode : gen = gen_neon_vextv4sf ; break ; case V2DImode : gen = gen_neon_vextv2di ; break ;


<s> return ( __m512i ) __builtin_ia32_vpmultishiftqb512_mask ( ( __v64qi ) __X , ( __v64qi ) __Y , ( __v64qi ) _mm512_undefined_si512 ( ) , ( __mmask64 ) - <NUM_LIT> ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ;


<s> unsigned Opc = InFlag . getOpcode ( ) ; assert ( ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) || ( Opc == <STR_LIT> || Opc == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Ops [ ] = { CmpLHS , InFlag . getOperand ( <NUM_LIT> ) } ; SDValue LHS = Node -> getOperand ( <NUM_LIT> ) , RHS = Node -> getOperand ( <NUM_LIT> ) ; EVT VT = LHS . getValueType ( ) ; SDNode * Carry ; if ( Subtarget -> has<ISA_LIT>32II ( ) ) Carry = CurDAG -> getMachineNode ( <STR_LIT> , DL , VT , Ops ) ;


<s> } else if ( isShiftedImm ( ) ) { addExpr ( Inst , getShiftedImmVal ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( getShiftedImmShift ( ) ) ) ; } else { addExpr ( Inst , getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; }