<s> unsigned HOST_WIDE_INT stack_adjust ; arm_stack_offsets * offsets ; if ( ! reload_completed ) return <NUM_LIT> ; func_type = arm_current_func_type ( ) ; if ( func_type & ( ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN ) ) return <NUM_LIT> ; if ( IS_INTERRUPT ( func_type ) && ( frame_pointer_needed || TARGET_THUMB ) ) return <NUM_LIT> ; if ( TARGET_LDRD && current_tune -> prefer_ldrd_strd && ! optimize_function_for_size_p ( cfun ) ) return <NUM_LIT> ; offsets = arm_get_frame_offsets ( ) ; stack_adjust = offsets -> outgoing_args - offsets -> saved_regs ; if ( crtl -> args . pretend_args_size || cfun -> machine -> uses_anonymous_args || crtl -> calls_eh_return || cfun -> calls_alloca || ! ( stack_adjust == <NUM_LIT> || ( TARGET_APCS_FRAME && frame_pointer_needed && stack_adjust == <NUM_LIT> ) ) || ( ! ( TARGET_APCS_FRAME && frame_pointer_needed ) && arm_compute_static_chain_stack_bytes ( ) != <NUM_LIT> ) ) return <NUM_LIT> ; saved_int_regs = offsets -> saved_regs_mask ; if ( stack_adjust == <NUM_LIT> && ! arm_arch5t && TARGET_ARM ) { if ( ! call_used_regs [ <NUM_LIT> ] ) return <NUM_LIT> ;

if ( arm_size_return_regs ( ) >= ( <NUM_LIT> * UNITS_PER_WORD ) ) return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>TargetLowering :: isShuffleMaskLegal ( const SmallVectorImpl < int > & Mask , EVT VT ) const {

if ( Subtarget . useHVXOps ( ) ) return isStridedLoad ( Mask ) != StridedLoadKind :: NoPattern ;


<s> SDLoc DL ( Op ) ; MVT VT = Op -> getSimpleValueType ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned Opcode = Op -> getOperand ( <NUM_LIT> ) . getOpcode ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumElems ; ++ i ) if ( Opcode != Op -> getOperand ( i ) . getOpcode ( ) ) return SDValue ( ) ; bool IsShift = false ; switch ( Opcode ) { default : return SDValue ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsShift = true ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Op -> getSplatValue ( ) ) return SDValue ( ) ; if ( ! TLI . isOperationLegalOrPromote ( Opcode , VT ) ) return SDValue ( ) ; break ; } SmallVector < SDValue , <NUM_LIT> > LHSElts , RHSElts ; for ( SDValue Elt : Op -> ops ( ) ) { SDValue LHS = Elt . getOperand ( <NUM_LIT> ) ; SDValue RHS = Elt . getOperand ( <NUM_LIT> ) ; if ( ! isa < ConstantSDNode > ( RHS ) ) return SDValue ( ) ;

if ( RHS . getValueSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) {


<s> O << <STR_LIT> ; printRegName ( O , MO2 . getReg ( ) ) ;

O << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << markup ( <STR_LIT> ) << <STR_LIT> << markup ( <STR_LIT> ) ;


<s> break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = isZExt ? <STR_LIT> : <STR_LIT> ; else Opc = isZExt ? <STR_LIT> : <STR_LIT> ; } else { Opc = isZExt ? <STR_LIT> : <STR_LIT> ; useAM3 = true ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) Opc = <STR_LIT> ; else Opc = <STR_LIT> ; } else { Opc = <STR_LIT> ; } RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { needVMOV = true ; VT = <STR_LIT> ; Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; RC = isThumb2 ? & <STR_LIT> : & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; Opc = <STR_LIT> ; RC = TLI . getRegClassFor ( VT ) ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; if ( allocReg ) ResultReg = createResultReg ( RC ) ; assert ( ResultReg > <NUM_LIT> && <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; AddLoadStoreOperands ( VT , Addr , MIB , MachineMemOperand :: MOLoad , useAM3 ) ; if ( needVMOV ) { unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( ResultReg ) ) ; ResultReg = MoveReg ; }


<s> bool <ISA_LIT>LowerEmscriptenEHSjLj :: runEHOnFunction ( Function & F ) { Module & M = * F . getParent ( ) ; LLVMContext & C = F . getContext ( ) ; IRBuilder < > IRB ( C ) ; bool Changed = false ; SmallVector < Instruction * , <NUM_LIT> > ToErase ; SmallPtrSet < LandingPadInst * , <NUM_LIT> > LandingPads ; bool AllowExceptions = areAllExceptionsAllowed ( ) || EHWhitelistSet . count ( F . getName ( ) ) ; for ( BasicBlock & BB : F ) { auto * II = dyn_cast < InvokeInst > ( BB . getTerminator ( ) ) ; if ( ! II ) continue ; LandingPads . insert ( II -> getLandingPadInst ( ) ) ; IRB . SetInsertPoint ( II ) ; bool NeedInvoke = AllowExceptions && canThrow ( II -> getCalledValue ( ) ) ; if ( NeedInvoke ) { Value * Threw = wrapInvoke ( II ) ; ToErase . push_back ( II ) ; Value * Cmp = IRB . CreateICmpEQ ( Threw , IRB . getInt32 ( <NUM_LIT> ) , <STR_LIT> ) ; IRB . CreateCondBr ( Cmp , II -> getUnwindDest ( ) , II -> getNormalDest ( ) ) ; } else { SmallVector < Value * , <NUM_LIT> > Args ( II -> arg_begin ( ) , II -> arg_end ( ) ) ; CallInst * NewCall = IRB . CreateCall ( II -> getFunctionType ( ) , II -> getCalledValue ( ) , Args ) ; NewCall -> takeName ( II ) ; NewCall -> setCallingConv ( II -> getCallingConv ( ) ) ; NewCall -> setDebugLoc ( II -> getDebugLoc ( ) ) ; NewCall -> setAttributes ( II -> getAttributes ( ) ) ; II -> replaceAllUsesWith ( NewCall ) ;


<s> void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> if ( TT . isOSBinFormatCOFF ( ) ) { const TargetLoweringObjectFileCOFF & TLOFCOFF = static_cast < const TargetLoweringObjectFileCOFF & > ( getObjFileLowering ( ) ) ; std :: string Flags ; raw_string_ostream FlagsOS ( Flags ) ; for ( const auto & Function : M ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Function ) ; for ( const auto & Global : M . globals ( ) ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Global ) ; for ( const auto & Alias : M . aliases ( ) ) TLOFCOFF . emitLinkerFlagsForGlobal ( FlagsOS , & Alias ) ; FlagsOS . flush ( ) ; if ( ! Flags . empty ( ) ) { OutStreamer -> SwitchSection ( TLOFCOFF . getDrectveSection ( ) ) ; OutStreamer -> EmitBytes ( Flags ) ; } SM . serializeToStackMapSection ( ) ; }


<s> break ; case <STR_LIT> : case <STR_LIT> : if ( ! Subtarget -> useOddSPReg ( ) ) { MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget -> isABI_FPXX ( ) && ! Subtarget -> hasMTHC1 ( ) ) MI . addOperand ( MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isGlobal ( ) && MI . getOperand ( <NUM_LIT> ) . getGlobal ( ) -> getGlobalIdentifier ( ) == <STR_LIT> ) emitMCountABI ( MI , MBB , MF ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isMCSymbol ( ) && MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) -> getName ( ) == <STR_LIT> ) emitMCountABI ( MI , MBB , MF ) ; break ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isMCSymbol ( ) && MI . getOperand ( <NUM_LIT> ) . getMCSymbol ( ) -> getName ( ) == <STR_LIT> ) emitMCountABI ( MI , MBB , MF ) ; break ; default : if ( replaceUsesWithZeroReg ( MRI , MI ) ) DeadNullInsts . push_back ( & MI ) ; } }


<s> <ISA_LIT>CallFrameOptimization :: InstClassification <ISA_LIT>CallFrameOptimization :: classifyInstruction ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const <ISA_LIT>RegisterInfo & RegInfo , DenseSet < unsigned int > & UsedRegs ) { if ( MI == MBB . end ( ) ) return Exit ; switch ( MI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineOperand ImmOp = MI -> getOperand ( <STR_LIT> ) ; return ImmOp . getImm ( ) == - <NUM_LIT> ? Convert : Exit ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; }


<s> if ( ( Addr & <NUM_LIT> ) != <NUM_LIT> || SignExtend32 < <NUM_LIT> > ( Addr ) != Addr ) return nullptr ; return DAG . getConstant ( ( int ) C -> getZExtValue ( ) >> <NUM_LIT> , SDLoc ( Op ) , DAG . getTargetLoweringInfo ( ) . getPointerTy ( DAG . getDataLayout ( ) ) ) . getNode ( ) ;


<s> SDValue GOT = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty , IsForTls ) , getTargetNode ( N , Ty , DAG , GOTFlag ) ) ; SDValue Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , GOT , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; unsigned LoFlag = IsN32OrN64 ? <STR_LIT> : <STR_LIT> ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , Ty , getTargetNode ( N , Ty , DAG , LoFlag ) ) ; return DAG . getNode ( <STR_LIT> , DL , Ty , Load , Lo ) ;


<s> printMemReference ( MI , OpNo , O ) ;


<s> if ( Val . getOpcode ( ) != <STR_LIT> ) return false ; EVT VT1 = Val . getValueType ( ) ; if ( ! VT1 . isSimple ( ) || ! VT1 . isInteger ( ) || ! VT2 . isSimple ( ) || ! VT2 . isInteger ( ) ) return false ; switch ( VT1 . getSimpleVT ( ) . SimpleTy ) {


<s> case <STR_LIT> : retType = <STR_LIT> :: I16x8 ; break ; case <STR_LIT> : retType = <STR_LIT> :: I32x4 ; break ; case <STR_LIT> : retType = <STR_LIT> :: F32x4 ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } for ( MachineBasicBlock & MBB : reverse ( MF ) ) { for ( MachineInstr & MI : reverse ( MBB ) ) { if ( MI . isPosition ( ) || MI . isDebugValue ( ) ) continue ; if ( MI . getOpcode ( ) == <STR_LIT> ) { BlockTops [ & MI ] -> getOperand ( <NUM_LIT> ) . setImm ( int32_t ( retType ) ) ; continue ;


<s> sign = SIGNBIT ; a1 = ( long ) - ( unsigned long ) a1 ; if ( a1 < <NUM_LIT> ) { dl . l . upper = SIGNBIT | ( ( <NUM_LIT> + EXCESSD ) << <NUM_LIT> ) ; dl . l . lower = <NUM_LIT> ; return dl . d ; } } while ( a1 < <NUM_LIT> ) { a1 <<= <NUM_LIT> ; exp -= <NUM_LIT> ; } while ( a1 < <NUM_LIT> ) { a1 <<= <NUM_LIT> ;


<s> if ( numE == <NUM_LIT> ) return <NUM_LIT> * alignE ; else return numE * alignE ; } const StructType * STy = dyn_cast < StructType > ( Ty ) ; if ( STy ) { unsigned int alignStruct = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = STy -> getNumElements ( ) ; i != e ; i ++ ) {

Type * ETy = STy -> getElementType ( i ) ;


<s> bool isRegOrImmWithInputMods ( ) const { return Kind == Register || isInlinableImm ( ) ;


<s> static void unicosmk_output_default_externs ( FILE * file ) { static const char * const externs [ ] = { <STR_LIT> } ; int i ; int n ; n = ARRAY_SIZE ( externs ) ; for ( i = <NUM_LIT> ; i < n ; i ++ ) fprintf ( file , <STR_LIT> , externs [ i ] ) ;


<s> StackOffset += RegSize ; } if ( MFI -> adjustsStack ( ) ) { <ISA_LIT>FI -> setRAStackOffset ( <NUM_LIT> ) ; MFI -> setObjectOffset ( MFI -> CreateStackObject ( RegSize , RegSize , true ) , StackOffset ) ; TopCPUSavedRegOff = StackOffset ; StackOffset += RegSize ; }


return __builtin_loongson_psubd_s ( s , t ) ;


<s> default : break ; } if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( name [ <NUM_LIT> ] == '@' && name [ <NUM_LIT> ] == '.' ) encoding = name [ <NUM_LIT> ] ; else encoding = <NUM_LIT> ; if ( flag_function_sections || DECL_COMDAT_GROUP ( decl ) ) mep_unique_section ( decl , <NUM_LIT> ) ; else if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) { if ( encoding == 'f' ) return vftext_section ; else return vtext_section ; } else if ( encoding == 'f' ) return ftext_section ; else return text_section ; } if ( TREE_CODE ( decl ) == VAR_DECL ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( name [ <NUM_LIT> ] == '@' && name [ <NUM_LIT> ] == '.' ) switch ( name [ <NUM_LIT> ] ) { case 'b' : return based_section ; case 't' :

if ( readonly ) return srodata_section ;


<s> static DecodeStatus readInstruction32 ( const MemoryObject & region , uint64_t address , uint64_t & size , uint32_t & insn ) { uint8_t Bytes [ <NUM_LIT> ] ;

if ( region . readBytes ( address , <NUM_LIT> , Bytes ) == - <NUM_LIT> ) {


<s> uint64_t TSFlags = Desc . TSFlags ; if ( TSFlags & <STR_LIT> ) OS << <STR_LIT> ; unsigned Flags = MI -> getFlags ( ) ; if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; else if ( Flags & <STR_LIT> ) OS << <STR_LIT> ; printInstruction ( MI , OS ) ; printAnnotation ( OS , Annot ) ;

if ( CommentStream ) EmitAny<ISA_LIT>InstComments ( MI , * CommentStream , getRegisterName ) ;


<s> return decodeOperand_AVLdSt_Any ( Inst , Imm , <ISA_LIT>Disassembler :: OPW96 , Decoder ) ;


<s> static DecodeStatus DecodeBranchTarget21MM ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) { int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: createImm ( BranchOffset ) ) ; return MCDisassembler :: Success ;


<s> OutgoingArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , MachineInstrBuilder MIB , CCAssignFn * AssignFn , CCAssignFn * AssignFnVarArg , bool IsTailCall = false , int FPDiff = <NUM_LIT> ) : ValueHandler ( MIRBuilder , MRI , AssignFn ) , MIB ( MIB ) , AssignFnVarArg ( AssignFnVarArg ) , IsTailCall ( IsTailCall ) , FPDiff ( FPDiff ) , StackSize ( <NUM_LIT> ) {


<s> const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;

return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , dl , FR , Op . getOperand ( <NUM_LIT> ) , SV , <NUM_LIT> ) ;


<s> assert ( ! Subtarget . isTargetMachO ( ) ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; MachineInstr * ResumeMI = Subtarget . getFrameLowering ( ) -> emitStackProbe ( * BB -> getParent ( ) , * BB , MI , DL , false ) ; MachineBasicBlock * ResumeBB = ResumeMI -> getParent ( ) ; MI -> eraseFromParent ( ) ; return ResumeBB ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( const Function & ) const override {


<s> static const uint16_t ReservedGPR32 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const uint16_t ReservedGPR64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ; typedef TargetRegisterClass :: const_iterator RegIter ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedGPR32 ) ; ++ I ) Reserved . set ( ReservedGPR32 [ I ] ) ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedGPR64 ) ; ++ I ) Reserved . set ( ReservedGPR64 [ I ] ) ; if ( Subtarget . has<ISA_LIT>64 ( ) ) { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } else { for ( RegIter Reg = <STR_LIT> . begin ( ) , EReg = <STR_LIT> . end ( ) ; Reg != EReg ; ++ Reg ) Reserved . set ( * Reg ) ; } if ( MF . getTarget ( ) . getFrameLowering ( ) -> hasFP ( MF ) ) { if ( Subtarget . in<ISA_LIT>16Mode ( ) ) Reserved . set ( <STR_LIT> ) ; else { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; }


<s> SDValue OneSubAC = DAG . getNode ( <STR_LIT> , DL , VT , OneSubA , Op . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) , OneSubAC ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : Opc = <STR_LIT> ; BT = BRIG_TYPE_U32 ; break ; case <STR_LIT> : Opc = <STR_LIT> ; BT = BRIG_TYPE_U64 ; break ; case <STR_LIT> : Opc = <STR_LIT> ; BT = BRIG_TYPE_B1 ; break ; } if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } switch ( RC -> getID ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , MI , DL , get ( Opc ) ) . addReg ( DestReg , RegState :: Define ) . addFrameIndex ( FrameIndex ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addImm ( BT ) . addImm ( <STR_LIT> ) . addImm ( MMO -> getAlignment ( ) ) . addImm ( BRIG_WIDTH_1 ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; break ;


<s> SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; if ( ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op0 ) ) { if ( Op1 -> hasOneUse ( ) && Op1 . getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) ) { APInt XorC = cast < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) -> getAPIntValue ( ) ; EVT VT = Op0 . getValueType ( ) ; SDValue NewXor = DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , Op1 . getOperand ( <NUM_LIT> ) , DAG . getConstant ( ~ XorC , SDLoc ( Op1 ) , VT ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , NewXor , DAG . getConstant ( C -> getAPIntValue ( ) + <NUM_LIT> , SDLoc ( N ) , VT ) ) ;


<s> LoadSDNode * LD = cast < LoadSDNode > ( N ) ; return DAG . getLoad ( LD -> getMemoryVT ( ) , N -> getDebugLoc ( ) , LD -> getChain ( ) , LD -> getBasePtr ( ) , LD -> getSrcValue ( ) , LD -> getSrcValueOffset ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> getAlignment ( ) ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) {

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> if ( Opd2Info == TargetTransformInfo :: OK_UniformConstantValue ) { auto VT = TLI -> getValueType ( DL , Ty ) ; if ( TLI -> isOperationLegalOrCustom ( <STR_LIT> , VT ) ) { int MulCost = getArithmeticInstrCost ( Instruction :: Mul , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int AddCost = getArithmeticInstrCost ( Instruction :: Add , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; int ShrCost = getArithmeticInstrCost ( Instruction :: AShr , Ty , CostKind , Opd1Info , Opd2Info , TargetTransformInfo :: OP_None , TargetTransformInfo :: OP_None ) ; return MulCost * <NUM_LIT> + AddCost * <NUM_LIT> + ShrCost * <NUM_LIT> + <NUM_LIT> ; } } Cost += BaseT :: getArithmeticInstrCost ( Opcode , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; if ( Ty -> isVectorTy ( ) ) { Cost += getArithmeticInstrCost ( Instruction :: ExtractElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += getArithmeticInstrCost ( Instruction :: InsertElement , Ty , CostKind , Opd1Info , Opd2Info , Opd1PropInfo , Opd2PropInfo ) ; Cost += Cost ; }


<s> debug_rtx ( x ) ; if ( reg_class_subset_p ( rclass , CR_REGS ) ) rv = mep_secondary_copro_reload_class ( rclass , x ) ;

else if ( MEP_NONGENERAL_CLASS ( rclass ) && ( mep_nonregister ( x ) || mep_nongeneral_reg ( x ) ) ) rv = GENERAL_REGS ;


<s> const Value * Ptr = MemNode -> getMemOperand ( ) -> getValue ( ) ;

if ( ! Ptr || isa < UndefValue > ( Ptr ) || isa < Argument > ( Ptr ) || isa < Constant > ( Ptr ) || isa < GlobalValue > ( Ptr ) ) return true ;


<s> } if ( Args . size ( ) != <NUM_LIT> || ( ! isa < SExtInst > ( Args [ <NUM_LIT> ] ) && ! isa < ZExtInst > ( Args [ <NUM_LIT> ] ) ) || ! Args [ <NUM_LIT> ] -> hasOneUse ( ) ) return false ; auto * Extend = cast < CastInst > ( Args [ <NUM_LIT> ] ) ; auto DstTyL = TLI -> getTypeLegalizationCost ( DL , DstTy ) ; unsigned DstElTySize = DstTyL . second . getScalarSizeInBits ( ) ; if ( ! DstTyL . second . isVector ( ) || DstElTySize != DstTy -> getScalarSizeInBits ( ) ) return false ;

auto * SrcTy = toVectorTy ( Extend -> getSrcTy ( ) ) ;


<s> case <STR_LIT> : break ; default : llvm_unreachable ( <STR_LIT> ) ; } unsigned FrameSize = MF . getFrameInfo ( ) . getStackSize ( ) ; MachineOperand & Off = MI . getOperand ( <NUM_LIT> ) ; int64_t NewOff = Off . getImm ( ) - ( FrameSize + HEXAGON_LRFP_SIZE ) ;

if ( HII -> isValidOffset ( Opc , NewOff ) ) {


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const {


<s> while ( PrevI -> isDebugInstr ( ) && PrevI != MBB . begin ( ) ) -- PrevI ; MachineInstr & PrevMI = * PrevI ; unsigned Opcode = PrevMI . getOpcode ( ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MachineOperand & MO = PrevMI . getOperand ( PrevMI . getNumOperands ( ) - <NUM_LIT> ) ; if ( MO . getReg ( ) != <STR_LIT> ) return false ; unsigned NewOpc = ( isThumb2 ? <STR_LIT> : <STR_LIT> ) ; assert ( ( ( isThumb2 && Opcode == <STR_LIT> ) || Opcode == <STR_LIT> ) && <STR_LIT> ) ; PrevMI . setDesc ( TII -> get ( NewOpc ) ) ; MO . setReg ( <STR_LIT> ) ; PrevMI . copyImplicitOps ( * MBB . getParent ( ) , * MBBI ) ; MBB . erase ( MBBI ) ; MachineFrameInfo & MFI = MBB . getParent ( ) -> getFrameInfo ( ) ; assert ( MFI . isCalleeSavedInfoValid ( ) && <STR_LIT> ) ; for ( CalleeSavedInfo & Info : MFI . getCalleeSavedInfo ( ) ) { if ( Info . getReg ( ) == <STR_LIT> ) { Info . setRestored ( false ) ; break ; }


<s> unsigned V2 = <STR_LIT> ( MO1 . getImm ( ) ) ; unsigned Binary = <NUM_LIT> << <NUM_LIT> ; Binary |= II -> getPredicate ( & MI ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , MO0 ) << <STR_LIT> ; Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= getMachineSoImmOpValue ( <STR_LIT> ( V1 ) ) ; emitWordLE ( Binary ) ; Binary = <NUM_LIT> << <NUM_LIT> ;


<s> unsigned x = <NUM_LIT> ; bool retval = llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISKERNEL_FUNCTION ] , x ) ; if ( ! retval ) { return F . getCallingConv ( ) == llvm :: CallingConv :: PTX_Kernel ; } return ( x == <NUM_LIT> ) ;


<s> else if ( result == <NUM_LIT> ) return true ; unsigned ID = AFI -> createPICLabelUId ( ) ; MachineBasicBlock * NewIsland = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = std :: next ( MachineFunction :: iterator ( WaterBB ) ) ; } else { DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = std :: prev ( MachineFunction :: iterator ( NewMBB ) ) ; IP = std :: find ( WaterList . begin ( ) , WaterList . end ( ) , WaterBB ) ; if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ; NewWaterList . insert ( NewIsland ) ; } if ( IP != WaterList . end ( ) ) WaterList . erase ( IP ) ; MF -> insert ( NewMBB , NewIsland ) ; updateForInsertedWaterBlock ( NewIsland ) ; U . HighWaterMark = NewIsland ; U . CPEMI = BuildMI ( NewIsland , DebugLoc ( ) , CPEMI -> getDesc ( ) ) . addImm ( ID ) . addOperand ( CPEMI -> getOperand ( <NUM_LIT> ) ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; ++ NumCPEs ; decrementCPEReferenceCount ( CPI , CPEMI ) ; NewIsland -> setAlignment ( getCPELogAlign ( U . CPEMI ) ) ; BBInfo [ NewIsland -> getNumber ( ) ] . Size += Size ; adjustBBOffsetsAfter ( std :: prev ( MachineFunction :: iterator ( NewIsland ) ) ) ;

for ( unsigned i = <NUM_LIT> , e = UserMI -> getNumOperands ( ) ; i != e ; ++ i ) if ( UserMI -> getOperand ( i ) . isCPI ( ) ) {


<s> if ( TrueVal - <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , CondV , FalseV ) ; if ( TrueVal + <NUM_LIT> == FalseVal ) return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , FalseV , CondV ) ; } translateSetCCForBranch ( DL , LHS , RHS , CCVal , DAG ) ; SDValue TargetCC = DAG . getCondCode ( CCVal ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , TrueV , FalseV } ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Ops ) ; } SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , XLenVT ) ; SDValue SetNE = DAG . getCondCode ( <STR_LIT> ) ;

SDValue Ops [ ] = { CondV , Zero , SetNE , TrueV , FalseV } ;


<s> for ( MBBVector :: const_iterator iterBlk = OrderedBlks . begin ( ) , iterBlkEnd = OrderedBlks . end ( ) ; iterBlk != iterBlkEnd ; ++ iterBlk , ++ i ) {

dbgs ( ) << <STR_LIT> << ( * iterBlk ) -> getNumber ( ) ;


<s> return DAG . getTruncStore ( N -> getChain ( ) , SDLoc ( Op ) , N -> getVal ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , <STR_LIT> , N -> isVolatile ( ) , N -> isNonTemporal ( ) , N -> getAlignment ( ) , N -> getAAInfo ( ) ) ; } if ( N -> getMemoryVT ( ) == <STR_LIT> ) return DAG . getTruncStore ( N -> getChain ( ) , SDLoc ( Op ) , N -> getVal ( ) , N -> getBasePtr ( ) , N -> getPointerInfo ( ) , <STR_LIT> , N -> isVolatile ( ) , N -> isNonTemporal ( ) , N -> getAlignment ( ) , N -> getAAInfo ( ) ) ;


<s> switch ( MO . getTargetFlags ( ) ) {

default : llvm_unreachable ( <STR_LIT> ) ;


<s> return new pass_handle_trap_shadows ( ctxt ) ;


<s> EVT VT = Src . getValueType ( ) ; SDValue Copy ( DAG . getMachineNode ( <STR_LIT> , DL , VT , Src ) , <NUM_LIT> ) ; return Op . getNode ( ) -> getNumValues ( ) == <NUM_LIT> ? DAG . getCopyToReg ( Chain , DL , Reg , Copy ) : DAG . getCopyToReg ( Chain , DL , Reg , Copy , Op . getNumOperands ( ) == <NUM_LIT> ? Op . getOperand ( <NUM_LIT> ) : SDValue ( ) ) ;


<s> if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else if ( RC == & <STR_LIT> ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveModuleOddSPReg ( bool Enabled , bool IsO32ABI ) { <ISA_LIT>TargetStreamer :: emitDirectiveModuleOddSPReg ( Enabled , IsO32ABI ) ; ABIFlagsSection . OddSPReg = Enabled ;


<s> if ( EHPad && EHPad != MBB ) return nullptr ; EHPad = MBB ; continue ; } if ( MBB == & MF -> front ( ) ) return nullptr ;

WL . append ( MBB -> pred_begin ( ) , MBB -> pred_end ( ) ) ;


<s> SDValue Bodds = DAG . getVectorShuffle ( VT , dl , B , B , UnpackMask ) ; SDValue Evens = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , A ) , DAG . getBitcast ( <STR_LIT> , B ) ) ; SDValue Odds = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getBitcast ( <STR_LIT> , Aodds ) , DAG . getBitcast ( <STR_LIT> , Bodds ) ) ; Evens = DAG . getBitcast ( VT , Evens ) ; Odds = DAG . getBitcast ( VT , Odds ) ; static const int ShufMask [ ] = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; return DAG . getVectorShuffle ( VT , dl , Evens , Odds , ShufMask ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ! Subtarget . hasDQI ( ) && <STR_LIT> ) ; KnownBits AKnown = DAG . computeKnownBits ( A ) ; KnownBits BKnown = DAG . computeKnownBits ( B ) ; APInt LowerBitsMask = APInt :: getLowBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; bool ALoIsZero = LowerBitsMask . isSubsetOf ( AKnown . Zero ) ; bool BLoIsZero = LowerBitsMask . isSubsetOf ( BKnown . Zero ) ; APInt UpperBitsMask = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ; bool AHiIsZero = UpperBitsMask . isSubsetOf ( AKnown . Zero ) ; bool BHiIsZero = UpperBitsMask . isSubsetOf ( BKnown . Zero ) ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , dl , VT ) ; SDValue AloBlo = Zero ; if ( ! ALoIsZero && ! BLoIsZero ) AloBlo = DAG . getNode ( <STR_LIT> , dl , VT , A , B ) ; SDValue AloBhi = Zero ; if ( ! ALoIsZero && ! BHiIsZero ) { SDValue Bhi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , B , <NUM_LIT> , DAG ) ; AloBhi = DAG . getNode ( <STR_LIT> , dl , VT , A , Bhi ) ; } SDValue AhiBlo = Zero ; if ( ! AHiIsZero && ! BLoIsZero ) { SDValue Ahi = getTargetVShiftByConstNode ( <STR_LIT> , dl , VT , A , <NUM_LIT> , DAG ) ;

AhiBlo = DAG . getNode ( <STR_LIT> , dl , VT , Ahi , B ) ;


<s> MachineBasicBlock :: iterator E = I -> getParent ( ) -> end ( ) ; MachineBasicBlock :: iterator MBBI = I ; MachineInstr * FirstMI = I ; ++ MBBI ; unsigned Opc = FirstMI -> getOpcode ( ) ; bool MayLoad = FirstMI -> mayLoad ( ) ; bool IsUnscaled = isUnscaledLdst ( Opc ) ; unsigned Reg = FirstMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned BaseReg = FirstMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int Offset = FirstMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( FirstMI -> modifiesRegister ( BaseReg , TRI ) ) return E ; int OffsetStride = IsUnscaled && Enable<ISA_LIT>UnscaledMemOp ? getMemSize ( FirstMI ) : <NUM_LIT> ; if ( ! inBoundsForPair ( IsUnscaled , Offset , OffsetStride ) ) return E ; BitVector ModifiedRegs , UsedRegs ; ModifiedRegs . resize ( TRI -> getNumRegs ( ) ) ; UsedRegs . resize ( TRI -> getNumRegs ( ) ) ; SmallVector < MachineInstr * , <NUM_LIT> > MemInsns ; for ( unsigned Count = <NUM_LIT> ; MBBI != E && Count < Limit ; ++ MBBI ) { MachineInstr * MI = MBBI ; if ( MI -> isDebugValue ( ) ) continue ; ++ Count ; bool CanMergeOpc = Opc == MI -> getOpcode ( ) ; SExtIdx = - <NUM_LIT> ; if ( ! CanMergeOpc ) { bool IsValidLdStrOpc ; unsigned NonSExtOpc = getMatchingNonSExtOpcode ( Opc , & IsValidLdStrOpc ) ; if ( ! IsValidLdStrOpc ) continue ; SExtIdx = NonSExtOpc == ( unsigned ) Opc ? <NUM_LIT> : <NUM_LIT> ; CanMergeOpc = NonSExtOpc == getMatchingNonSExtOpcode ( MI -> getOpcode ( ) ) ; } if ( CanMergeOpc && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { unsigned MIBaseReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int MIOffset = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( BaseReg == MIBaseReg && ( ( Offset == MIOffset + OffsetStride ) || ( Offset + OffsetStride == MIOffset ) ) ) { int MinOffset = Offset < MIOffset ? Offset : MIOffset ; if ( MI -> hasOrderedMemoryRef ( ) || TII -> isLdStPairSuppressed ( MI ) ) return E ; bool MIIsUnscaled = isUnscaledLdst ( MI -> getOpcode ( ) ) ; if ( ! inBoundsForPair ( MIIsUnscaled , MinOffset , OffsetStride ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ; if ( MI -> mayLoadOrStore ( ) ) MemInsns . push_back ( MI ) ; continue ; } if ( IsUnscaled && Enable<ISA_LIT>UnscaledMemOp && ( alignTo ( MinOffset , OffsetStride ) != MinOffset ) ) { trackRegDefsUses ( MI , ModifiedRegs , UsedRegs , TRI ) ;


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { verifyInstructionPredicates ( MI , computeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; if ( MI . getOpcode ( ) == <STR_LIT> ) { MCFixupKind Fixup = MCFixupKind ( <STR_LIT> ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MI . getOperand ( <NUM_LIT> ) . getExpr ( ) , Fixup ) ) ; return ; } if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) {


<s> static __inline qword si_mpyhha ( qword a , qword b , qword c ) { return ( ( qword ) ( vec_add ( vec_mule ( ( vec_short8 ) ( a ) , ( vec_short8 ) ( b ) ) , ( vec_int4 ) ( c ) ) ) ) ;


<s> <STR_LIT> getCmpLibcallReturnType ( ) const override {


<s> if ( MI . getOpcode ( ) == <STR_LIT> ) { for ( auto & I : <ISA_LIT>MCInstrInfo :: bundleInstructions ( MI ) ) { MCInst & BMI = const_cast < MCInst & > ( * I . getInst ( ) ) ; if ( isJmpMCInst ( BMI , Label ) ) { return true ; } } return false ; } else { bool IsJmp = false ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : IsJmp = true ; break ; default : return false ; } if ( IsJmp ) { assert ( MI . getNumOperands ( ) >= <NUM_LIT> ) ; const MCOperand & ValueOperand = MI . getOperand ( <NUM_LIT> ) ; if ( ValueOperand . isExpr ( ) ) { Label = MCOperandToString ( ValueOperand ) ; }


<s> void <ISA_LIT>TargetStreamer :: emitTextAttribute ( unsigned Attribute , StringRef String ) {


<s> static FunctionPass * createBasicSGPRRegisterAllocator ( ) { return createBasicRegisterAllocator ( onlyAllocateSGPRs ) ;


<s> } else { for ( unsigned i = <NUM_LIT> ; i < Size ; ++ i ) { unsigned Shift = IsLittleEndian ? i * <NUM_LIT> : ( Size - <NUM_LIT> - i ) * <NUM_LIT> ; EmitByte ( ( Val >> Shift ) & <NUM_LIT> , OS ) ; } }


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) { return new <ISA_LIT>DAGToDAGISel ( TM , OptLevel ) ;


<s> temp = gen_reg_rtx ( Pmode ) ; temp = expand_binop ( Pmode , and_optab , str_addr_base_reg , GEN_INT ( <NUM_LIT> ) , temp , <NUM_LIT> , OPTAB_DIRECT ) ; gcc_assert ( REG_P ( temp ) ) ; highest_index_to_load_reg = expand_binop ( Pmode , sub_optab , GEN_INT ( <NUM_LIT> ) , temp , highest_index_to_load_reg , <NUM_LIT> , OPTAB_DIRECT ) ; gcc_assert ( REG_P ( highest_index_to_load_reg ) ) ; emit_insn ( gen_vllv16qi ( str_reg , convert_to_mode ( SImode , highest_index_to_load_reg , <NUM_LIT> ) , gen_rtx_MEM ( BLKmode , str_addr_base_reg ) ) ) ; into_loop_label = gen_label_rtx ( ) ; s390_emit_jump ( into_loop_label , NULL_RTX ) ; emit_barrier ( ) ; } emit_label ( is_aligned_label ) ; LABEL_NUSES ( is_aligned_label ) = INTVAL ( alignment ) < <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ; emit_move_insn ( highest_index_to_load_reg , GEN_INT ( <NUM_LIT> ) ) ; emit_label ( loop_start_label ) ; LABEL_NUSES ( loop_start_label ) = <NUM_LIT> ; mem = gen_rtx_MEM ( V16QImode , gen_rtx_PLUS ( Pmode , str_idx_reg , str_addr_base_reg ) ) ; set_mem_align ( mem , <NUM_LIT> ) ; emit_move_insn ( str_reg , mem ) ;


<s> explicit <ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) {


<s> eliminatePhis ( SuccB ) ; HII -> removeBranch ( * PredB ) ; PredB -> removeSuccessor ( SuccB ) ;

PredB -> splice ( PredB -> end ( ) , SuccB , SuccB -> begin ( ) , SuccB -> end ( ) ) ;


<s> FunctionPass * create<ISA_LIT>PostLegalizeCombiner ( bool IsOptNone ) {

return new <ISA_LIT>PostLegalizerCombiner ( IsOptNone ) ;


<s> rtx def_set = single_set ( insn ) ; if ( def_set && REG_P ( SET_DEST ( def_set ) ) && ! HARD_REGISTER_P ( SET_DEST ( def_set ) ) ) bitmap_set_bit ( defs , REGNO ( SET_DEST ( def_set ) ) ) ; df_ref ref ; for ( ref = DF_INSN_UID_DEFS ( insn_uid ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( ! HARD_REGISTER_P ( DF_REF_REG ( ref ) ) ) if ( ! analyze_register_chain ( candidates , ref , disallowed ) ) return false ; if ( def_set && GET_CODE ( SET_SRC ( def_set ) ) == VEC_SELECT ) return true ; for ( ref = DF_INSN_UID_USES ( insn_uid ) ; ref ; ref = DF_REF_NEXT_LOC ( ref ) ) if ( ! DF_REF_REG_MEM_P ( ref ) ) if ( ! analyze_register_chain ( candidates , ref , disallowed ) ) return false ;


<s> decc$to_vms ( filespec , translate_unix , <NUM_LIT> , <NUM_LIT> ) ; strcpy ( new_host_filespec , filename_buff ) ; return new_host_filespec ; }


<s> Symbol = Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = AsmPrinter . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ; HasOffset = false ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = AsmPrinter . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } const MCExpr * Expr = MCSymbolRefExpr :: Create ( Symbol , Kind , Ctx ) ;

if ( HasOffset ) if ( int64_t Offset = MO . getOffset ( ) ) {


<s> bool iss6_0Ext ( ) const { return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , true , true , true ) ;


<s> static bool detectZextAbsDiff ( const SDValue & Abs , SDValue & Op0 , SDValue & Op1 ) { SDValue AbsOp1 = Abs -> getOperand ( <NUM_LIT> ) ; if ( AbsOp1 . getOpcode ( ) != <STR_LIT> ) return false ; Op0 = AbsOp1 . getOperand ( <NUM_LIT> ) ; Op1 = AbsOp1 . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) != <STR_LIT> || Op0 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> || Op1 . getOpcode ( ) != <STR_LIT> || Op1 . getOperand ( <NUM_LIT> ) . getValueType ( ) . getVectorElementType ( ) != <STR_LIT> ) return false ;


<s> if ( <STR_LIT> . contains ( Src ) ) return std :: make_pair ( ( unsigned ) <STR_LIT> , ( unsigned ) <STR_LIT> ) ;


<s> case AsmToken :: Real : { int64_t IntVal ; if ( getParser ( ) . parseAbsoluteExpression ( IntVal ) ) return MatchOperand_ParseFail ; APFloat F ( BitsToDouble ( IntVal ) ) ; if ( Minus ) F . changeSign ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , F . bitcastToAPInt ( ) . getZExtValue ( ) , S , <ISA_LIT>Operand :: ImmTyNone , true ) ) ; return MatchOperand_Success ; } default : return Minus ? MatchOperand_ParseFail : MatchOperand_NoMatch ; }


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( Offset ) . addMemOperand ( MMO ) ;


<s> return ( int64x1_t ) __builtin_neon_vreinterpretdiv4hi ( __a ) ;


<s> case HImode : return <STR_LIT> ; case SImode : case SFmode : return <STR_LIT> ; } } else if ( ZERO_P ( src ) ) return <STR_LIT> ; } else if ( FPR_P ( dest_regno ) ) { if ( GET_CODE ( src ) == REG ) { int src_regno = REGNO ( src ) ; if ( GPR_P ( src_regno ) ) return <STR_LIT> ; else if ( FPR_P ( src_regno ) ) { if ( TARGET_HARD_FLOAT ) return <STR_LIT> ; else return <STR_LIT> ; } } else if ( GET_CODE ( src ) == MEM ) { if ( mode == SImode || mode == SFmode ) return <STR_LIT> ; } else if ( ZERO_P ( src ) ) return <STR_LIT> ; } } else if ( GET_CODE ( dest ) == MEM ) { if ( GET_CODE ( src ) == REG ) { int src_regno = REGNO ( src ) ; machine_mode mode = GET_MODE ( dest ) ; if ( GPR_P ( src_regno ) ) { switch ( mode ) { default : break ; case QImode : return <STR_LIT> ; case HImode : return <STR_LIT> ; case SImode : case SFmode : return <STR_LIT> ; } } else if ( FPR_P ( src_regno ) && ( mode == SImode || mode == SFmode ) ) return <STR_LIT> ; } else if ( ZERO_P ( src ) ) { machine_mode mode = GET_MODE ( dest ) ; switch ( mode ) { default : break ; case QImode :


<s> static SDValue PerformADCCombine ( SDNode * N , SelectionDAG & DAG , <ISA_LIT>TargetLowering :: DAGCombinerInfo & DCI ) { if ( <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) ) && <STR_LIT> ( N -> getOperand ( <NUM_LIT> ) ) && SDValue ( N , <NUM_LIT> ) . use_empty ( ) ) { DebugLoc DL = N -> getDebugLoc ( ) ;

EVT VT = N -> getValueType ( <NUM_LIT> ) ;


<s> rtx ( * gen_round ) ( rtx , rtx , rtx ) ; switch ( mode ) { case SFmode : gen_copysign = gen_copysignsf3 ; gen_round = gen_sse4_1_roundsf2 ; break ; case DFmode : gen_copysign = gen_copysigndf3 ; gen_round = gen_sse4_1_rounddf2 ; break ; default : gcc_unreachable ( ) ; } fmt = REAL_MODE_FORMAT ( mode ) ; real_2expN ( & half_minus_pred_half , - ( fmt -> p ) - <NUM_LIT> , mode ) ;


<s> const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const override {


<s> void <ISA_LIT>Z80TargetStreamer :: finish ( ) {


<s> unsigned encodeExpcnt ( const IsaVersion & Version , unsigned Waitcnt , unsigned Expcnt ) { return packBits ( Expcnt , Waitcnt , getExpcntBitShift ( Version . Major ) , getExpcntBitWidth ( Version . Major ) ) ;


<s> unsigned NumGPRs ; if ( CCInfo . isFirstByValRegValid ( ) ) NumGPRs = <STR_LIT> - CCInfo . getFirstByValReg ( ) ; else { unsigned int firstUnalloced ; firstUnalloced = CCInfo . getFirstUnallocated ( GPRArgRegs , sizeof ( GPRArgRegs ) / sizeof ( GPRArgRegs [ <NUM_LIT> ] ) ) ; NumGPRs = ( firstUnalloced <= <NUM_LIT> ) ? ( <NUM_LIT> - firstUnalloced ) : <NUM_LIT> ; } unsigned Align = MF . getTarget ( ) . getFrameLowering ( ) -> getStackAlignment ( ) ; VARegSize = NumGPRs * <NUM_LIT> ; VARegSaveSize = ( VARegSize + Align - <NUM_LIT> ) & ~ ( Align - <NUM_LIT> ) ;


<s> machine_mode tmode , mode1 ; tree arg0 , arg1 , arg2 ; int elt ; rtx op0 , op1 , target ; arg0 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg1 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; arg2 = CALL_EXPR_ARG ( exp , <NUM_LIT> ) ; tmode = TYPE_MODE ( TREE_TYPE ( arg0 ) ) ; mode1 = TYPE_MODE ( TREE_TYPE ( TREE_TYPE ( arg0 ) ) ) ; gcc_assert ( VECTOR_MODE_P ( tmode ) ) ; op0 = expand_expr ( arg0 , NULL_RTX , tmode , EXPAND_NORMAL ) ; op1 = expand_expr ( arg1 , NULL_RTX , mode1 , EXPAND_NORMAL ) ; elt = get_element_number ( TREE_TYPE ( arg0 ) , arg2 ) ; if ( GET_MODE ( op1 ) != mode1 && GET_MODE ( op1 ) != VOIDmode ) op1 = convert_modes ( mode1 , GET_MODE ( op1 ) , op1 , true ) ; op0 = force_reg ( tmode , op0 ) ; op1 = force_reg ( mode1 , op1 ) ; target = gen_reg_rtx ( tmode ) ; emit_move_insn ( target , op0 ) ; ix86_expand_vector_set ( true , target , op1 , elt ) ; return target ;


<s> if ( FP_REGNO_P ( regno ) ) return regno - FIRST_FPR_REGNO + <NUM_LIT> ; if ( ALTIVEC_REGNO_P ( regno ) ) return regno - FIRST_ALTIVEC_REGNO + <NUM_LIT> ; if ( regno == LR_REGNO ) return <NUM_LIT> ; if ( regno == CTR_REGNO ) return <NUM_LIT> ; if ( regno == CA_REGNO ) return <NUM_LIT> ; if ( format == <NUM_LIT> && regno == CR2_REGNO ) return <NUM_LIT> ; if ( CR_REGNO_P ( regno ) ) return regno - CR0_REGNO + <NUM_LIT> ; if ( regno == VRSAVE_REGNO ) return <NUM_LIT> ;

if ( regno == VSCR_REGNO ) return <NUM_LIT> ;


unsigned long __element_selector_54 = ( __mask >> <NUM_LIT> ) & <NUM_LIT> ;


<s> if ( Str == <STR_LIT> ) { Val = <NUM_LIT> ; return MatchOperand_Success ; } if ( Str . startswith ( <STR_LIT> ) ) { Str = Str . drop_front ( <NUM_LIT> ) ; if ( Str == <STR_LIT> ) { Val = <NUM_LIT> ; return MatchOperand_Success ; } if ( Str . getAsInteger ( <NUM_LIT> , Val ) ) return MatchOperand_ParseFail ; if ( Val > <NUM_LIT> ) errorExpTgt ( ) ; return MatchOperand_Success ; } if ( Str . startswith ( <STR_LIT> ) ) { Str = Str . drop_front ( <NUM_LIT> ) ; if ( Str . getAsInteger ( <NUM_LIT> , Val ) ) return MatchOperand_ParseFail ; if ( Val > <NUM_LIT> || ( Val == <NUM_LIT> && ! isGFX10 ( ) ) ) errorExpTgt ( ) ; Val += <NUM_LIT> ; return MatchOperand_Success ; } if ( isGFX10 ( ) && Str == <STR_LIT> ) { Val = <NUM_LIT> ; return MatchOperand_Success ; } if ( Str . startswith ( <STR_LIT> ) ) { Str = Str . drop_front ( <NUM_LIT> ) ; if ( Str . getAsInteger ( <NUM_LIT> , Val ) ) return MatchOperand_ParseFail ; if ( Val >= <NUM_LIT> ) errorExpTgt ( ) ; Val += <NUM_LIT> ; return MatchOperand_Success ; } if ( Str . startswith ( <STR_LIT> ) ) { Str = Str . drop_front ( <NUM_LIT> ) ; if ( Str . getAsInteger ( <NUM_LIT> , Val ) ) return MatchOperand_ParseFail ;


<s> CC = DAG . getCondCode ( SwapInvCC ) ; } } } if ( isHWTrueValue ( True ) && isHWFalseValue ( False ) && ( CompareVT == VT || VT == <STR_LIT> ) ) { return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , True , False , CC ) ; } if ( isZero ( LHS ) ) { <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; <STR_LIT> CCSwapped = <STR_LIT> ( CCOpcode ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } else { <STR_LIT> CCInv = <STR_LIT> ( CCOpcode , CompareVT . isInteger ( ) ) ; CCSwapped = <STR_LIT> ( CCInv ) ; if ( isCondCodeLegal ( CCSwapped , CompareVT . getSimpleVT ( ) ) ) { std :: swap ( True , False ) ; std :: swap ( LHS , RHS ) ; CC = DAG . getCondCode ( CCSwapped ) ; } } } if ( isZero ( RHS ) ) { SDValue Cond = LHS ; SDValue Zero = RHS ; <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; if ( CompareVT != VT ) { True = DAG . getNode ( <STR_LIT> , DL , CompareVT , True ) ; False = DAG . getNode ( <STR_LIT> , DL , CompareVT , False ) ; } switch ( CCOpcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CCOpcode = <STR_LIT> ( CCOpcode , CompareVT == <STR_LIT> ) ; Temp = True ; True = False ; False = Temp ; break ; default : break ; } SDValue SelectNode = DAG . getNode ( <STR_LIT> , DL , CompareVT , Cond , Zero , True , False , DAG . getCondCode ( CCOpcode ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectNode ) ; } SDValue MinMax = LowerMinMax ( Op , DAG ) ; if ( MinMax . getNode ( ) ) { return MinMax ; } SDValue HWTrue , HWFalse ;


<s> ( RC == & <STR_LIT> ? & <STR_LIT> : RC ) ) ; return FastISel :: FastEmitInst_rr ( MachineInstOpcode , UseRC , Op0 , Op0IsKill , Op1 , Op1IsKill ) ;


<s> if ( MI . isMoveReg ( ) ) { Dest = MI . getOperand ( <NUM_LIT> ) ; Src = MI . getOperand ( <NUM_LIT> ) ; return true ;


<s> const LLT Ty = Query . Types [ TypeIdx ] ; unsigned Size = Ty . getSizeInBits ( ) ; assert ( Size % <NUM_LIT> == <NUM_LIT> ) ;

return std :: make_pair ( TypeIdx , LLT :: scalarOrVector ( ElementCount :: getFixed ( Size / <NUM_LIT> ) , <NUM_LIT> ) ) ;


<s> void <ISA_LIT>FunctionInfo :: getTypeDescriptor ( Type * Ty , std :: string & Desc ) const { <ISA_LIT>FunctionInfo * MFI = const_cast < <ISA_LIT>FunctionInfo * > ( this ) ; const DataLayout & DL = MF . getDataLayout ( ) ; const <ISA_LIT>TargetLowering & TLI = * MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( MF . getFunction ( ) ) . getTargetLowering ( ) ; if ( isa < ArrayType > ( Ty ) ) { Desc += <STR_LIT> ; getTypeDescriptor ( cast < SequentialType > ( Ty ) -> getElementType ( ) , Desc ) ; } else if ( isa < PointerType > ( Ty ) ) {

getTypeDescriptor ( cast < PointerType > ( Ty ) -> getElementType ( ) , Desc ) ;


<s> static bool ExplicitlyBranchesTo ( MachineBasicBlock * Pred , MachineBasicBlock * MBB ) { for ( MachineInstr & MI : Pred -> terminators ( ) ) if ( ! <STR_LIT> ( MI ) ) for ( MachineOperand & MO : MI . explicit_operands ( ) ) if ( MO . isMBB ( ) && MO . getMBB ( ) == MBB ) return true ;


<s> case <STR_LIT> : { EVT VT ; switch ( Intrinsic ) { case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; default : VT = <STR_LIT> ; break ; } Info . opc = <STR_LIT> ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = - VT . getStoreSize ( ) + <NUM_LIT> ; Info . size = <NUM_LIT> * VT . getStoreSize ( ) - <NUM_LIT> ; Info . align = <NUM_LIT> ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { EVT VT ; switch ( Intrinsic ) { case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; case <STR_LIT> : VT = <STR_LIT> ; break ; default : VT = <STR_LIT> ; break ; } Info . opc = <STR_LIT> ; Info . memVT = VT ; Info . ptrVal = I . getArgOperand ( <NUM_LIT> ) ; Info . offset = <NUM_LIT> ; Info . size = VT . getStoreSize ( ) ; Info . align = <NUM_LIT> ; Info . vol = false ; Info . readMem = false ; Info . writeMem = true ; return true ; } default : break ; } return false ;


<s> if ( ITCounter == <NUM_LIT> ) ITState = <NUM_LIT> ; else {

unsigned short NewITState4_0 = slice ( ITState , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( hasReservedCallFrame ( MF ) ) { fixStackStores ( MBB , MI , TII , false ) ; return MBB . erase ( MI ) ; } DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned int Opcode = MI -> getOpcode ( ) ; int Amount = TII . getFrameSize ( * MI ) ; if ( Amount != <NUM_LIT> ) { assert ( getStackAlign ( ) == Align ( <NUM_LIT> ) && <STR_LIT> ) ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { fixStackStores ( MBB , MI , TII , true ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned addOpcode ; if ( isUInt < <NUM_LIT> > ( Amount ) ) { addOpcode = <STR_LIT> ; } else { addOpcode = <STR_LIT> ; Amount = - Amount ; } BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( addOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; } } return MBB . erase ( MI ) ;


<s> <ISA_LIT>ISelAddressMode ( ) : BaseType ( RegBase ) , Scale ( <NUM_LIT> ) , IndexReg ( ) , Disp ( <NUM_LIT> ) , Segment ( ) , GV ( <NUM_LIT> ) , CP ( <NUM_LIT> ) , BlockAddr ( <NUM_LIT> ) , ES ( <NUM_LIT> ) , JT ( - <NUM_LIT> ) , Align ( <NUM_LIT> ) , SymbolFlags ( <STR_LIT> ) {


<s> return _mm_srl_si64 ( __m , __count ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>TargetMachine & tm ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( tm , * this ) , TM ( tm ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemBytes = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : MemBytes = <NUM_LIT> ; return true ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return new <ISA_LIT>SetP2AlignOperands ( ) ;


<s> if ( ! Match ) continue ; if ( Match . getScalarValueSizeInBits ( ) != BitWidth ) continue ; unsigned MatchSizeInBits = Match . getValueSizeInBits ( ) ; if ( ! ( MatchSizeInBits == <NUM_LIT> || ( MatchSizeInBits == <NUM_LIT> && ( ( Subtarget . hasAVX ( ) && BitWidth >= <NUM_LIT> ) || Subtarget . hasAVX2 ( ) ) ) ) ) return SDValue ( ) ; if ( Match . getValueType ( ) . getVectorNumElements ( ) <= <NUM_LIT> ) return SDValue ( ) ; if ( DAG . ComputeNumSignBits ( Match ) != BitWidth ) return SDValue ( ) ; MVT MaskVT ; if ( <NUM_LIT> == BitWidth || <NUM_LIT> == BitWidth ) MaskVT = <STR_LIT> ( <STR_LIT> ( BitWidth ) , MatchSizeInBits / BitWidth ) ; else MaskVT = <STR_LIT> ( <STR_LIT> , MatchSizeInBits / <NUM_LIT> ) ; APInt CompareBits ; <STR_LIT> CondCode ; if ( Op == <STR_LIT> ) { CompareBits = APInt :: getNullValue ( <NUM_LIT> ) ; CondCode = <STR_LIT> :: SETNE ; } else { CompareBits = APInt :: getLowBitsSet ( <NUM_LIT> , MaskVT . getVectorNumElements ( ) ) ; CondCode = <STR_LIT> :: SETEQ ; } unsigned ResWidth = std :: max ( BitWidth , <NUM_LIT> ) ; APInt ResOnes = APInt :: getAllOnesValue ( ResWidth ) ; APInt ResZero = APInt :: getNullValue ( ResWidth ) ; EVT ResVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , ResWidth ) ; SDLoc DL ( Extract ) ;

SDValue Res = DAG . getBitcast ( MaskVT , Match ) ;


<s> bool isiOS = Subtarget -> isTargetIOS ( ) ; if ( isThumb2 ) { return isiOS ? <STR_LIT> : <STR_LIT> ; } else { return isiOS ? <STR_LIT> : <STR_LIT> ; }


<s> int i [ <NUM_LIT> ] ; } x ; vec_uchar16 mask ; x . i [ <NUM_LIT> ] = count << <NUM_LIT> ; mask = ( count & <NUM_LIT> ) ? vec_splat_u8 ( <NUM_LIT> ) : vec_splat_u8 ( - <NUM_LIT> ) ; return ( ( qword ) ( vec_and ( vec_slo ( ( vec_uchar16 ) ( a ) , x . v ) , mask ) ) ) ;


<s> if ( M . debug_compile_units ( ) . empty ( ) ) return false ;


<s> virtual const TargetSubtargetInfo * getSubtargetImpl ( const Function & ) const override {


<s> static bool sh_scalar_mode_supported_p ( machine_mode mode ) { if ( TARGET_SHMEDIA32 && mode == TImode ) return false ;

return default_scalar_mode_supported_p ( mode ) ;


return ( __m128i ) __builtin_ia32_vphaddubw ( ( __v16qi ) __A ) ;


<s> unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock * NewMBB ; unsigned UserOffset = GetOffsetOf ( UserMI ) + ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ; int result = LookForExistingCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; unsigned ID = AFI -> createConstPoolEntryUId ( ) ; if ( ! LookForWater ( U , UserOffset , & NewMBB ) ) { DOUT << <STR_LIT> ; CreateNewWater ( CPUserIndex , UserOffset , & NewMBB ) ; } MachineBasicBlock * NewIsland = MF . CreateMachineBasicBlock ( ) ; MF . insert ( NewMBB , NewIsland ) ; UpdateForInsertedWaterBlock ( NewIsland ) ; DecrementOldEntry ( CPI , CPEMI ) ; U . CPEMI = BuildMI ( NewIsland , DebugLoc :: getUnknownLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( ID ) . addConstantPoolIndex ( CPI ) . addImm ( Size ) ; CPEntries [ CPI ] . push_back ( CPEntry ( U . CPEMI , ID , <NUM_LIT> ) ) ; NumCPEs ++ ; BBOffsets [ NewIsland -> getNumber ( ) ] = BBOffsets [ NewMBB -> getNumber ( ) ] ;

if ( isThumb && BBOffsets [ NewIsland -> getNumber ( ) ] % <NUM_LIT> != <NUM_LIT> ) Size += <NUM_LIT> ;


<s> case <STR_LIT> : { Row = II -> getArgOperand ( <NUM_LIT> ) ; Col = II -> getArgOperand ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { switch ( OpNo ) { case <NUM_LIT> : Row = II -> getArgOperand ( <NUM_LIT> ) ; Col = II -> getArgOperand ( <NUM_LIT> ) ; break ; case <NUM_LIT> : Row = II -> getArgOperand ( <NUM_LIT> ) ; Col = II -> getArgOperand ( <NUM_LIT> ) ; break ; case <NUM_LIT> : Row = II -> getArgOperand ( <NUM_LIT> ) ; Col = II -> getArgOperand ( <NUM_LIT> ) ; break ; } break ; } } return std :: make_pair ( Row , Col ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>DomainReassignmentPass ( ) {

return new <ISA_LIT>DomainReassignment ( ) ;


<s> assert ( Value <= <NUM_LIT> && <STR_LIT> ) ; O << ( unsigned int ) Value ;


<s> tree decl ; gcc_assert ( GET_CODE ( sym ) == SYMBOL_REF ) ; decl = SYMBOL_REF_DECL ( sym ) ; if ( SYMBOL_REF_TLS_MODEL ( sym ) != <NUM_LIT> ) return false ;

if ( TARGET_ARCH_R2 && ( TARGET_BYPASS_CACHE || TARGET_BYPASS_CACHE_VOLATILE ) ) return false ;


<s> BB -> getInstList ( ) . push_back ( PtrCast ) ; Args . push_back ( PtrCast ) ; } else if ( ArgType -> isStructTy ( ) || ParamType -> isStructTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; WrapperNeeded = false ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Args . size ( ) << <STR_LIT> << * ParamType << <STR_LIT> << * ArgType << <STR_LIT> ) ; TypeMismatch = true ; break ; } } } if ( WrapperNeeded && ! TypeMismatch ) { for ( ; PI != PE ; ++ PI ) Args . push_back ( UndefValue :: get ( * PI ) ) ; if ( F -> isVarArg ( ) ) for ( ; AI != AE ; ++ AI ) Args . push_back ( & * AI ) ; CallInst * Call = CallInst :: Create ( F , Args , <STR_LIT> , BB ) ; Type * ExpectedRtnType = F -> getFunctionType ( ) -> getReturnType ( ) ; Type * RtnType = Ty -> getReturnType ( ) ; if ( RtnType -> isVoidTy ( ) ) { ReturnInst :: Create ( M -> getContext ( ) , BB ) ; } else if ( ExpectedRtnType -> isVoidTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * RtnType << <STR_LIT> ) ; ReturnInst :: Create ( M -> getContext ( ) , UndefValue :: get ( RtnType ) , BB ) ; } else if ( RtnType == ExpectedRtnType ) { ReturnInst :: Create ( M -> getContext ( ) , Call , BB ) ; } else if ( CastInst :: isBitOrNoopPointerCastable ( ExpectedRtnType , RtnType , DL ) ) { Instruction * Cast = CastInst :: CreateBitOrPointerCast ( Call , RtnType , <STR_LIT> ) ; BB -> getInstList ( ) . push_back ( Cast ) ; ReturnInst :: Create ( M -> getContext ( ) , Cast , BB ) ; } else if ( RtnType -> isStructTy ( ) || ExpectedRtnType -> isStructTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; WrapperNeeded = false ; } else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << F -> getName ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ExpectedRtnType << <STR_LIT> << * RtnType << <STR_LIT> ) ; TypeMismatch = true ; } }


<s> if ( mcInst . getOpcode ( ) == <STR_LIT> ) mcInst . setOpcode ( <STR_LIT> ) ; else if ( mcInst . getOpcode ( ) == <STR_LIT> ) mcInst . setOpcode ( <STR_LIT> ) ; } insn . numImmediatesTranslated = <NUM_LIT> ; for ( const auto & Op : insn . operands ) { if ( Op . encoding != ENCODING_NONE ) { if ( translateOperand ( mcInst , Op , insn , Dis ) ) { return true ; } } } return false ;


<s> const struct machine_function * m = cfun -> machine ; unsigned last_reg = m -> call_ms2sysv_extra_regs + MIN_REGS - <NUM_LIT> ; gcc_assert ( m -> call_ms2sysv_extra_regs <= MAX_EXTRA_REGS ) ;

return m_regs [ last_reg ] . offset + STUB_INDEX_OFFSET ;


<s> if ( Cond [ <NUM_LIT> ] . getImm ( ) != - <NUM_LIT> ) { BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addMBB ( TBB ) ;


<s> -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ;


<s> void <ISA_LIT>AsmPrinter :: printConstantFP ( const ConstantFP * CFP , raw_ostream & O ) { uint64_t Val = CFP -> getValueAPF ( ) . bitcastToAPInt ( ) . getZExtValue ( ) ; if ( CFP -> getType ( ) -> isFloatTy ( ) ) printFloat ( static_cast < uint32_t > ( Val ) , O ) ; else if ( CFP -> getType ( ) -> isDoubleTy ( ) ) printDouble ( Val , O ) ;


<s> return __builtin_mve_vhaddq_uv8hi ( __a , __b ) ;


<s> MachineInstr * ResMI = nullptr ; if ( MI . getOpcode ( ) == TargetOpcode :: G_INTRIN<ISA_LIT>C && MI . getIntrinsicID ( ) == <STR_LIT> ) ResMI = MRI . getVRegDef ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; return ResMI ; } ; auto getSqrtSrc = [ = ] ( const MachineInstr & MI ) { MachineInstr * SqrtSrcMI = nullptr ; mi_match ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_GFSqrt ( m_MInstr ( SqrtSrcMI ) ) ) ; return SqrtSrcMI ; } ; MachineInstr * RcpSrcMI = nullptr , * SqrtSrcMI = nullptr ; if ( ( RcpSrcMI = getRcpSrc ( MI ) ) && ( SqrtSrcMI = getSqrtSrc ( * RcpSrcMI ) ) ) { MatchInfo = [ SqrtSrcMI , & MI ] ( MachineIRBuilder & B ) { B . buildIntrinsic ( <STR_LIT> , { MI . getOperand ( <NUM_LIT> ) } , false ) . addUse ( SqrtSrcMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . setMIFlags ( MI . getFlags ( ) ) ;


<s> return Ctx . getRegisterInfo ( ) . getEncodingValue ( MO . getReg ( ) ) & <NUM_LIT> ;


<s> if ( AllocaAmount < <NUM_LIT> || AllocaAmount > StackProbeSize ) return Probe ;

if ( CurrentOffset + AllocaAmount <= StackProbeSize ) return Sub ;


<s> if ( isInt < <NUM_LIT> > ( ImmSh ) ) { Imm = ImmSh ; } else { Remainder = Imm ; Shift = <NUM_LIT> ; Imm >>= <NUM_LIT> ; } } unsigned Result = <NUM_LIT> ; unsigned Lo = Imm & <NUM_LIT> ; if ( isInt < <NUM_LIT> > ( Imm ) ) { ++ Result ; } else if ( Lo ) { Result += <NUM_LIT> ;


<s> if ( F . isVarArg ( ) ) return false ; if ( Ret -> getNumOperands ( ) > <NUM_LIT> ) { SmallVector < <STR_LIT> , <NUM_LIT> > Outs ; GetReturnInfo ( F . getReturnType ( ) , F . getAttributes ( ) . getRetAttributes ( ) , Outs , TLI ) ; SmallVector < CCValAssign , <NUM_LIT> > ValLocs ; CCState CCInfo ( CC , F . isVarArg ( ) , * FuncInfo . MF , TM , ValLocs , I -> getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; const Value * RV = Ret -> getOperand ( <NUM_LIT> ) ; unsigned Reg = getRegForValue ( RV ) ; if ( Reg == <NUM_LIT> ) return false ; if ( ValLocs . size ( ) != <NUM_LIT> ) return false ; CCValAssign & VA = ValLocs [ <NUM_LIT> ] ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) return false ; if ( ! VA . isRegLoc ( ) ) return false ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; unsigned SrcReg = Reg + VA . getValNo ( ) ; EVT SrcVT = TLI . getValueType ( RV -> getType ( ) ) ; EVT DstVT = VA . getValVT ( ) ;


<s> case GlobalValue :: WeakODRLinkage : case GlobalValue :: ExternalLinkage : case GlobalValue :: CommonLinkage : emitArrayBound ( GVSym , GV ) ; OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_Global ) ; if ( GV -> hasWeakLinkage ( ) || GV -> hasLinkOnceLinkage ( ) || GV -> hasCommonLinkage ( ) ) OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_Weak ) ; LLVM_FALLTHROUGH ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : break ; default : llvm_unreachable ( <STR_LIT> ) ; } EmitAlignment ( Align > <NUM_LIT> ? Align : <NUM_LIT> , GV ) ; if ( GV -> isThreadLocal ( ) ) { report_fatal_error ( <STR_LIT> ) ; } unsigned Size = DL . getTypeAllocSize ( C -> getType ( ) ) ; if ( MAI -> hasDotTypeDotSizeDirective ( ) ) {

OutStreamer -> EmitSymbolAttribute ( GVSym , MCSA_ELF_TypeObject ) ;


<s> MachineFunctionPass ( ID ) , TII ( nullptr ) , TRI ( nullptr ) {

initialize<ISA_LIT>CFGStructurizerPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> case TargetOpcode :: G_GEP : return selectG_GEP ( I ) ; case TargetOpcode :: G_LOAD : return selectG_LOAD ( I ) ; case TargetOpcode :: G_STORE : return selectG_STORE ( I ) ; }


<s> case nodeType :: LOOP : retValue += <STR_LIT> ; break ; case nodeType :: EXIT : retValue += <STR_LIT> ; break ; case nodeType :: LATCH : retValue += <STR_LIT> ; break ; case nodeType :: SWITCH_BRANCH : retValue += <STR_LIT> ; break ; default : retValue += <STR_LIT> ; break ; } retValue += <STR_LIT> + to_string ( MBB -> getNumber ( ) ) ; retValue += <STR_LIT> + to_string ( cycle ) ; retValue += <STR_LIT> ; string retValue2 ; raw_string_ostream stream ( retValue2 ) ; SCEVValue -> print ( stream ) ; retValue2 = stream . str ( ) ; bool noChange = false ; do { noChange = false ; auto a = retValue2 . find ( '<' ) ; auto b = retValue2 . find ( '>' ) ; if ( a < retValue2 . size ( ) ) { retValue2 . replace ( a , b + <NUM_LIT> - a , <STR_LIT> ) ; noChange = true ; } a = retValue2 . find ( '{' ) ; b = retValue2 . find ( '}' ) ; if ( a < retValue2 . size ( ) ) { retValue2 . replace ( a , <NUM_LIT> , <STR_LIT> ) ; retValue2 . replace ( b - <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; noChange = true ; } } while ( noChange ) ; retValue = retValue + retValue2 + <STR_LIT> ; raw_string_ostream streamN ( retValue ) ; streamN << LD ; retValue = streamN . str ( ) ; retValue += <STR_LIT> ;


<s> static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; for ( unsigned R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) markSuperRegs ( Reserved , <STR_LIT> + R ) ; } const TargetRegisterClass & RC = <STR_LIT> ; for ( unsigned Reg : RC ) for ( MCSubRegIterator SI ( Reg , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) markSuperRegs ( Reserved , Reg ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ;


<s> if ( Indices . size ( ) != Factor || UseMaskForCond || UseMaskForGaps ) return BaseT :: getInterleavedMemoryOpCost ( Opcode , VecTy , Factor , Indices , Alignment , AddressSpace , UseMaskForCond , UseMaskForGaps ) ;

return getMemoryOpCost ( Opcode , VecTy , MaybeAlign ( Alignment ) , AddressSpace , nullptr ) ;


<s> static DecodeStatus DecodeIntRegsLow8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { return DecodeIntRegsRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> bool Is64Bit = Subtarget -> is64Bit ( ) ; EVT SPTy = Is64Bit ? <STR_LIT> : <STR_LIT> ; if ( getTargetMachine ( ) . Options . EnableSegmentedStacks ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( Is64Bit ) { const Function * F = MF . getFunction ( ) ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I ) if ( I -> hasNestAttr ( ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; } const TargetRegisterClass * AddrRegClass = getRegClassFor ( Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; unsigned Vreg = MRI . createVirtualRegister ( AddrRegClass ) ; Chain = DAG . getCopyToReg ( Chain , dl , Vreg , Size ) ; SDValue Value = DAG . getNode ( <STR_LIT> , dl , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; SDValue Ops1 [ <NUM_LIT> ] = { Value , Chain } ;

return DAG . getMergeValues ( Ops1 , <NUM_LIT> , dl ) ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> } else if ( from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) { return - ( crtl -> args . pretend_args_size + tilepro_saved_regs_size ( ) ) ; } else if ( from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM ) { return STACK_POINTER_OFFSET + total_size ; }

else if ( from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM ) {


<s> return ( int64x2_t ) __builtin_aarch64_ssubl2v4si ( __a , __b ) ;


<s> auto Res = std :: make_unique < <ISA_LIT>Operand > ( OpKind :: MovDGUnpack , StartLoc , EndLoc ) ; Res -> MovDGUnpack . Val = Val ; return Res ;


<s> * src = adjust_address ( * src , mode , <NUM_LIT> ) ; * dst = adjust_address ( * dst , mode , <NUM_LIT> ) ; emit_insn ( aarch64_gen_load_pair ( mode , reg1 , * src , reg2 , aarch64_progress_pointer ( * src ) ) ) ; emit_insn ( aarch64_gen_store_pair ( mode , * dst , reg1 , aarch64_progress_pointer ( * dst ) , reg2 ) ) ; * src = aarch64_move_pointer ( * src , <NUM_LIT> ) ; * dst = aarch64_move_pointer ( * dst , <NUM_LIT> ) ; return ; } rtx reg = gen_reg_rtx ( mode ) ; * src = adjust_address ( * src , mode , <NUM_LIT> ) ; * dst = adjust_address ( * dst , mode , <NUM_LIT> ) ; emit_move_insn ( reg , * src ) ;


<s> else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_803 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_803 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_805 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_807 ;

else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_810 ;


<s> if ( arch == llvm :: Triple :: x86 || pConfig . targets ( ) . triple ( ) . getEnvironment ( ) == llvm :: Triple :: GNUX32 ) { m_RelEntrySize = <NUM_LIT> ; m_RelaEntrySize = <NUM_LIT> ; if ( arch == llvm :: Triple :: x86 ) m_PointerRel = llvm :: ELF :: R_386_32 ; else m_PointerRel = llvm :: ELF :: R_<ISA_LIT>_64_32 ; } else { m_RelEntrySize = <NUM_LIT> ; m_RelaEntrySize = <NUM_LIT> ; m_PointerRel = llvm :: ELF :: R_<ISA_LIT>_64_64 ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addRegOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addMemImm12OffsetOperands ( Inst , <NUM_LIT> ) ; ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> addCondCodeOperands ( Inst , <NUM_LIT> ) ;


<s> static reg_class_t xstormy16_preferred_reload_class ( rtx x , reg_class_t rclass ) { if ( rclass == GENERAL_REGS && ( MEM_P ( x ) || GET_CODE ( x ) == POST_INC || GET_CODE ( x ) == PRE_DEC || GET_CODE ( x ) == PRE_MODIFY ) ) return EIGHT_REGS ;


<s> return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Or : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Sub : return SelectBinaryIntOp ( I , <STR_LIT> ) ; case Instruction :: Ret : return SelectRet ( I ) ; case Instruction :: Trunc : return SelectTrunc ( I ) ; case Instruction :: ZExt : case Instruction :: SExt : return SelectIntExt ( I ) ; default : break ;


<s> void <ISA_LIT>16InstrInfo :: ExpandRetRA16 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned Opc ) const {

BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( Opc ) ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case InlineAsm :: Constraint_i : case InlineAsm :: Constraint_m : case InlineAsm :: Constraint_Q : case InlineAsm :: Constraint_Um : case InlineAsm :: Constraint_Un : case InlineAsm :: Constraint_Uq : case InlineAsm :: Constraint_Us : case InlineAsm :: Constraint_Ut : case InlineAsm :: Constraint_Uv : case InlineAsm :: Constraint_Uy : OutOps . push_back ( Op ) ; return false ; }


<s> } } bool FirstVReg = true ; for ( unsigned Idx = <NUM_LIT> , IdxE = MRI -> getNumVirtRegs ( ) ; Idx != IdxE ; ++ Idx ) { unsigned VReg = TargetRegisterInfo :: index2VirtReg ( Idx ) ; if ( FirstVReg ) { OS << ( First ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> ; First = false ; } OS << ( FirstVReg ? <STR_LIT> : <STR_LIT> ) << getRegTypeName ( VReg ) ; FirstVReg = false ; } if ( ! First ) OutStreamer -> EmitRawText ( OS . str ( ) ) ;

AsmPrinter :: EmitFunctionBodyStart ( ) ;


<s> MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ; const MCObjectFileInfo & OFI = * MCA . getContext ( ) . getObjectFileInfo ( ) ; MCSection & TextSection = * OFI . getTextSection ( ) ; MCA . registerSection ( TextSection ) ; MCSection & DataSection = * OFI . getDataSection ( ) ; MCA . registerSection ( DataSection ) ; MCSection & BSSSection = * OFI . getBSSSection ( ) ; MCA . registerSection ( BSSSection ) ; TextSection . setAlignment ( std :: max ( <NUM_LIT> , TextSection . getAlignment ( ) ) ) ; DataSection . setAlignment ( std :: max ( <NUM_LIT> , DataSection . getAlignment ( ) ) ) ; BSSSection . setAlignment ( std :: max ( <NUM_LIT> , BSSSection . getAlignment ( ) ) ) ; if ( RoundSectionSizes ) { MCStreamer & OS = getStreamer ( ) ;


<s> if ( isSGetReg ( MI -> getOpcode ( ) ) && checkGetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( * MI ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( checkAnyInstHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; return NoHazard ;


<s> APInt Op0Zero , Op0One ; APInt Op1Zero , Op1One ; DAG . computeKnownBits ( Op0 , Op0Zero , Op0One , Depth ) ; DAG . computeKnownBits ( Op1 , Op1Zero , Op1One , Depth ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> <STR_LIT> e = static_cast < <STR_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ; O << <STR_LIT> ( e ) ; }


<s> <STR_LIT> ArgFlags = Outs [ i ] . Flags ; Type * OrigTy = CLI ? CLI -> getArgs ( ) [ Outs [ i ] . OrigArgIndex ] . Ty : nullptr ; <STR_LIT> ABI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getTargetABI ( ) ; if ( CC_<ISA_LIT> ( MF . getDataLayout ( ) , ABI , i , ArgVT , ArgVT , CCValAssign :: Full , ArgFlags , CCInfo , Outs [ i ] . IsFixed , IsRet , OrigTy , * this , FirstMaskArgument ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << EVT ( ArgVT ) . getEVTString ( ) << <STR_LIT> ) ; llvm_unreachable ( nullptr ) ; }


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return ( MI -> getNumOperands ( ) - <NUM_LIT> ) * <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) * <NUM_LIT> ; }


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx , false ) ;


<s> unsigned Rsrc2Reg = Rsrc1Reg + <NUM_LIT> ; unsigned ScratchSizeKey = PALMD :: Key :: CS_SCRATCH_<ISA_LIT>ZE ; switch ( MF . getFunction ( ) . getCallingConv ( ) ) { case CallingConv :: <ISA_LIT>_PS : ScratchSizeKey = PALMD :: Key :: PS_SCRATCH_<ISA_LIT>ZE ; break ; case CallingConv :: <ISA_LIT>_VS : ScratchSizeKey = PALMD :: Key :: VS_SCRATCH_<ISA_LIT>ZE ; break ; case CallingConv :: <ISA_LIT>_GS : ScratchSizeKey = PALMD :: Key :: GS_SCRATCH_<ISA_LIT>ZE ; break ; case CallingConv :: <ISA_LIT>_ES : ScratchSizeKey = PALMD :: Key :: ES_SCRATCH_<ISA_LIT>ZE ; break ; case CallingConv :: <ISA_LIT>_HS : ScratchSizeKey = PALMD :: Key :: HS_SCRATCH_<ISA_LIT>ZE ; break ; case CallingConv :: <ISA_LIT>_LS : ScratchSizeKey = PALMD :: Key :: LS_SCRATCH_<ISA_LIT>ZE ; break ; } unsigned NumUsedVgprsKey = ScratchSizeKey + PALMD :: Key :: VS_NUM_USED_VGPRS - PALMD :: Key :: VS_SCRATCH_<ISA_LIT>ZE ; unsigned NumUsedSgprsKey = ScratchSizeKey + PALMD :: Key :: VS_NUM_USED_SGPRS - PALMD :: Key :: VS_SCRATCH_<ISA_LIT>ZE ; PALMetadataMap [ NumUsedVgprsKey ] = CurrentProgramInfo . NumVGPRsForWavesPerEU ; PALMetadataMap [ NumUsedSgprsKey ] = CurrentProgramInfo . NumSGPRsForWavesPerEU ; if ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) { PALMetadataMap [ Rsrc1Reg ] |= CurrentProgramInfo . ComputePGMRSrc1 ; PALMetadataMap [ Rsrc2Reg ] |= CurrentProgramInfo . ComputePGMRSrc2 ; PALMetadataMap [ ScratchSizeKey ] |= alignTo ( CurrentProgramInfo . ScratchSize , <NUM_LIT> ) ; } else { PALMetadataMap [ Rsrc1Reg ] |= S_00B028_VGPRS ( CurrentProgramInfo . VGPRBlocks ) | S_00B028_SGPRS ( CurrentProgramInfo . SGPRBlocks ) ; if ( CurrentProgramInfo . ScratchBlocks > <NUM_LIT> ) PALMetadataMap [ Rsrc2Reg ] |= S_00B84C_SCRATCH_EN ( <NUM_LIT> ) ; PALMetadataMap [ ScratchSizeKey ] |= alignTo ( CurrentProgramInfo . ScratchSize , <NUM_LIT> ) ;


<s> } } forwardITPosition ( ) ; if ( Inst . getOpcode ( ) == <STR_LIT> ) return false ; Inst . setLoc ( IDLoc ) ; Out . EmitInstruction ( Inst , STI ) ; return false ; case Match_MissingFeature : { assert ( ErrorInfo && <STR_LIT> ) ; std :: string Msg = <STR_LIT> ; uint64_t Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( ErrorInfo ) * <NUM_LIT> - <NUM_LIT> ) ; ++ i ) { if ( ErrorInfo & Mask ) { Msg += <STR_LIT> ; Msg += getSubtargetFeatureName ( ErrorInfo & Mask ) ; } Mask <<= <NUM_LIT> ; } return Error ( IDLoc , Msg ) ; } case Match_InvalidOperand : { SMLoc ErrorLoc = IDLoc ; if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : return Error ( IDLoc , <STR_LIT> , ( ( <ISA_LIT>Operand & ) * Operands [ <NUM_LIT> ] ) . getLocRange ( ) ) ; case Match_RequiresNotITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresITBlock : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresV6 : return Error ( IDLoc , <STR_LIT> ) ; case Match_RequiresThumb2 : return Error ( IDLoc , <STR_LIT> ) ; case Match_ImmRange0_15 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_ImmRange0_239 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_AlignedMemoryRequiresNone : case Match_DupAlignedMemoryRequiresNone : case Match_AlignedMemoryRequires16 : case Match_DupAlignedMemoryRequires16 : case Match_AlignedMemoryRequires32 : case Match_DupAlignedMemoryRequires32 : case Match_AlignedMemoryRequires64 : case Match_DupAlignedMemoryRequires64 : case Match_AlignedMemoryRequires64or128 : case Match_DupAlignedMemoryRequires64or128 : case Match_AlignedMemoryRequires64or128or256 : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getAlignmentLoc ( ) ; if ( ErrorLoc == SMLoc ( ) ) ErrorLoc = IDLoc ; switch ( MatchResult ) { default : llvm_unreachable ( <STR_LIT> ) ; case Match_AlignedMemoryRequiresNone : case Match_DupAlignedMemoryRequiresNone : return Error ( ErrorLoc , <STR_LIT> ) ; case Match_AlignedMemoryRequires16 : case Match_DupAlignedMemoryRequires16 : return Error ( ErrorLoc , <STR_LIT> ) ;


<s> return ( __m512i ) __builtin_ia32_cvtpd2uqq512_mask ( ( __v8df ) __A , ( __v8di ) _mm512_setzero_si512 ( ) , ( __mmask8 ) - <NUM_LIT> , _MM_FROUND_CUR_DIRECTION ) ;


<s> MCGNode * getNode ( const char * name ) const { for ( MCGNodes :: const_iterator i ( Nodes . begin ( ) ) , ie ( Nodes . end ( ) ) ; i != ie ; i ++ ) { if ( ! ( * i ) -> isUnknown ( ) && ( * i ) -> getMF ( ) -> getFunction ( ) . getName ( ) == name ) return * i ; } return NULL ;


<s> } if ( TableEntry -> isUpdating ) MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( TableEntry -> hasWritebackOperand ) { const MachineOperand & AM6Offset = MI . getOperand ( OpIdx ++ ) ; if ( TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> || TableEntry -> RealOpc == <STR_LIT> ) { assert ( AM6Offset . getReg ( ) == <NUM_LIT> && <STR_LIT> <STR_LIT> ) ; } else { MIB . add ( AM6Offset ) ; } } unsigned SrcOpIdx = <NUM_LIT> ; if ( TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> && TableEntry -> RealOpc != <STR_LIT> ) { if ( RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc || RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc ) SrcOpIdx = OpIdx ++ ; } MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; MIB . add ( MI . getOperand ( OpIdx ++ ) ) ; if ( SrcOpIdx != <NUM_LIT> ) { MachineOperand MO = MI . getOperand ( SrcOpIdx ) ; MO . setImplicit ( true ) ; MIB . add ( MO ) ; } MIB . addReg ( DstReg , RegState :: ImplicitDefine | getDeadRegState ( DstIsDead ) ) ;


<s> Module * M = II -> getParent ( ) -> getParent ( ) -> getParent ( ) ; Type * DestTy = II -> getType ( ) ; Type * SrcTy = NewV -> getType ( ) ; Function * NewDecl = <STR_LIT> ( M , II -> getIntrinsicID ( ) , { DestTy , SrcTy } ) ; II -> setArgOperand ( <NUM_LIT> , NewV ) ; II -> setCalledFunction ( NewDecl ) ; return II ; } case <STR_LIT> : case <STR_LIT> : { unsigned TrueAS = IntrID == <STR_LIT> ? <ISA_LIT>AS :: LOCAL_ADDRESS : <ISA_LIT>AS :: PRIVATE_ADDRESS ; unsigned NewAS = NewV -> getType ( ) -> getPointerAddressSpace ( ) ; LLVMContext & Ctx = NewV -> getType ( ) -> getContext ( ) ; ConstantInt * NewVal = ( TrueAS == NewAS ) ? ConstantInt :: getTrue ( Ctx ) : ConstantInt :: getFalse ( Ctx ) ; return NewVal ; } case <STR_LIT> : { unsigned OldAS = OldV -> getType ( ) -> getPointerAddressSpace ( ) ; unsigned NewAS = NewV -> getType ( ) -> getPointerAddressSpace ( ) ; Value * MaskOp = II -> getArgOperand ( <NUM_LIT> ) ; Type * MaskTy = MaskOp -> getType ( ) ; bool DoTruncate = false ; if ( ! getTLI ( ) -> isNoopAddrSpaceCast ( OldAS , NewAS ) ) { if ( DL . getPointerSizeInBits ( OldAS ) != <NUM_LIT> || DL . getPointerSizeInBits ( NewAS ) != <NUM_LIT> ) return nullptr ; KnownBits Known = computeKnownBits ( MaskOp , DL , <NUM_LIT> , nullptr , II ) ; if ( Known . countMinLeadingOnes ( ) < <NUM_LIT> ) return nullptr ; DoTruncate = true ; } IRBuilder < > B ( II ) ; if ( DoTruncate ) { MaskTy = B . getInt32Ty ( ) ; MaskOp = B . CreateTrunc ( MaskOp , MaskTy ) ; } return B . CreateIntrinsic ( <STR_LIT> , { NewV -> getType ( ) , MaskTy } , { NewV , MaskOp } ) ; } default : return nullptr ;


<s> bool isTargetKnownWindowsMSVC ( ) const { return TargetTriple . isKnownWindowsMSVCEnvironment ( ) ;


<s> LSDASection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; EHFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfAbbrevSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfInfoSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfLineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfFrameSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfPubTypesSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ; DwarfDebugInlineSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;

DwarfStrSection = new <ISA_LIT>Section ( MCSection :: SV_ELF , SectionKind :: getMetadata ( ) ) ;


<s> type = TREE_TYPE ( current_function_decl ) ;

return lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( type ) ) != NULL ;


<s> static inline rtx gen_frame_load ( rtx reg , rtx frame_reg , int offset ) { return gen_frame_set ( reg , frame_reg , offset , false ) ;


<s> auto NewI = MIB . buildInstr ( Is64Bit ? <STR_LIT> : <STR_LIT> , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } , { I . getOperand ( <NUM_LIT> ) . getReg ( ) } ) ; for ( auto & RenderFn : * Imm1Fn ) RenderFn ( NewI ) ; for ( auto & RenderFn : * Imm2Fn ) RenderFn ( NewI ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * NewI , TII , TRI , RBI ) ;


<s> int first_reg ; for ( first_reg = <NUM_LIT> ; first_reg <= <NUM_LIT> ; first_reg ++ ) if ( save_reg_p ( first_reg ) ) break ; if ( flag_pic && crtl -> uses_pic_offset_table && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM ) return RS6000_PIC_OFFSET_TABLE_REGNUM ; return first_reg ;


<s> if ( FP_REGISTER_P ( regno ) && ( mode == SFmode || mode == SCmode || ( ( mode == DFmode || mode == DCmode ) && ( ( regno - FIRST_FP_REG ) & <NUM_LIT> ) == <NUM_LIT> ) ) ) return mode ; return choose_hard_reg_mode ( regno , nregs , NULL ) ;


<s> void <ISA_LIT>ConstantPoolValue :: dump ( ) const {


<s> Filler ( ) : MachineFunctionPass ( ID ) , TM ( nullptr ) {


<s> bool macho_lo_sum_memory_operand ( rtx x , machine_mode mode ) {

if ( ! TARGET_MACHO || ! flag_pic || mode != SImode || ! MEM_P ( x ) ) return false ;


<s> bool Split = false ; unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case TargetOpcode :: PHI : case TargetOpcode :: COPY : { Register DstR = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MRI -> getRegClass ( DstR ) == DoubleRC ) { createHalfInstr ( Opc , MI , PairMap , isub_lo ) ; createHalfInstr ( Opc , MI , PairMap , isub_hi ) ; Split = true ; } break ; } case A2_andp : createHalfInstr ( A2_and , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_and , MI , PairMap , isub_hi ) ; Split = true ; break ; case A2_orp : createHalfInstr ( A2_or , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_or , MI , PairMap , isub_hi ) ; Split = true ; break ; case A2_xorp : createHalfInstr ( A2_xor , MI , PairMap , isub_lo ) ; createHalfInstr ( A2_xor , MI , PairMap , isub_hi ) ; Split = true ; break ; case L2_loadrd_io : case L2_loadrd_pi : case S2_storerd_io : case S2_storerd_pi : splitMemRef ( MI , PairMap ) ; Split = true ; break ; case A2_tfrpi : case CONST64 : splitImmediate ( MI , PairMap ) ; Split = true ; break ; case A2_combineii : case A4_combineir : case A4_combineii : case A4_combineri : case A2_combinew : splitCombine ( MI , PairMap ) ; Split = true ; break ; case A2_sxtw : splitExt ( MI , PairMap ) ; Split = true ; break ; case S2_asl_i_p : case S2_asr_i_p : case S2_lsr_i_p : splitShift ( MI , PairMap ) ; Split = true ; break ; case S2_asl_i_p_or : splitAslOr ( MI , PairMap ) ; Split = true ; break ; default : llvm_unreachable ( <STR_LIT> ) ; return false ;


<s> <ISA_LIT>DebugValueManager :: <ISA_LIT>DebugValueManager ( MachineInstr * Instr ) {

Instr -> collectDebugValues ( DbgValues ) ;


<s> unsigned Opc = Subtarget . isThumb ( ) ? <STR_LIT> : <STR_LIT> ; int Align = - Subtarget . getStackAlignment ( ) . value ( ) ;

BuildMI ( MBB , It , DebugLoc ( ) , get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( Align ) . add ( predOps ( <STR_LIT> ) ) ;


<s> insn = emit_move_insn ( r10 , GEN_INT ( amount ) ) ; if ( amount < <NUM_LIT> ) RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = emit_add ( stack_pointer_rtx , stack_pointer_rtx , r10 ) ; if ( amount < <NUM_LIT> ) RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; } else { insn = emit_add ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( amount ) ) ;


<s> uint32_t ChildAI ; if ( IsPreserveDIAccessIndexCall ( CI , CIKind , ChildMeta , ChildAI ) && IsValidAIChain ( ParentMeta , ParentAI , ChildMeta ) ) { AIChain [ CI ] = std :: make_pair ( Parent , Kind ) ; traceAICall ( CI , CIKind , ChildMeta , ChildAI ) ; } else { BaseAICalls [ Parent ] = Kind ; } } else if ( auto * GI = dyn_cast < GetElementPtrInst > ( Inst ) ) { if ( GI -> hasAllZeroIndices ( ) ) traceGEP ( GI , Parent , Kind , ParentMeta , ParentAI ) ; else BaseAICalls [ Parent ] = Kind ; }


<s> static bool vax_mode_dependent_address_p ( const_rtx x , addr_space_t as ATTRIBUTE_UNUSED ) { rtx xfoo0 , xfoo1 ; if ( GET_CODE ( x ) != PLUS ) return false ; xfoo0 = XEXP ( x , <NUM_LIT> ) ; xfoo1 = XEXP ( x , <NUM_LIT> ) ; if ( CONST_INT_P ( xfoo0 ) && REG_P ( xfoo1 ) ) return false ; if ( CONST_INT_P ( xfoo1 ) && REG_P ( xfoo0 ) ) return false ; if ( ! flag_pic && CONSTANT_ADDRESS_P ( xfoo0 ) && REG_P ( xfoo1 ) ) return false ; if ( ! flag_pic && CONSTANT_ADDRESS_P ( xfoo1 ) && REG_P ( xfoo0 ) ) return false ;


<s> const AMDGPUSubtarget & ST = TM -> getSubtarget < AMDGPUSubtarget > ( ) ;

addPass ( createAMDGPUPromoteAlloca ( ST ) ) ;


<s> EmitImmediate ( const MCOperand & DispOp , SMLoc Loc , unsigned Size , MCFixupKind FixupKind , unsigned & CurByte , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , int ImmOffset ) const { const MCExpr * Expr = nullptr ; if ( DispOp . isImm ( ) ) { if ( FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 && FixupKind != FK_PCRel_4 ) { EmitConstant ( DispOp . getImm ( ) + ImmOffset , Size , CurByte , OS ) ; return ; } Expr = MCConstantExpr :: create ( DispOp . getImm ( ) , Ctx ) ; } else { Expr = DispOp . getExpr ( ) ; } if ( ( FixupKind == FK_Data_4 || FixupKind == FK_Data_8 || FixupKind == MCFixupKind ( <STR_LIT> ) ) ) { GlobalOffsetTableExprKind Kind = StartsWithGlobalOffsetTable ( Expr ) ; if ( Kind != GOT_None ) { assert ( ImmOffset == <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) { FixupKind = MCFixupKind ( <STR_LIT> ) ; } else { assert ( Size == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; } if ( Kind == GOT_Normal ) ImmOffset = CurByte ; } else if ( Expr -> getKind ( ) == MCExpr :: SymbolRef ) { if ( HasSecRelSymbolRef ( Expr ) ) { FixupKind = MCFixupKind ( FK_SecRel_4 ) ; } } else if ( Expr -> getKind ( ) == MCExpr :: Binary ) { const MCBinaryExpr * Bin = static_cast < const MCBinaryExpr * > ( Expr ) ;

if ( HasSecRelSymbolRef ( Bin -> getLHS ( ) ) || HasSecRelSymbolRef ( Bin -> getRHS ( ) ) ) {


<s> if ( MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . isMetadata ( ) ) { LoopMD = MI -> getOperand ( MI -> getNumOperands ( ) - <NUM_LIT> ) . getMetadata ( ) ; } if ( LoopMD ) return getLoopTakenFromMetadata ( LoopMD ) ; return false ;


<s> * Fast = ! Subtarget -> isMisaligned128StoreSlow ( ) || VT . getStoreSize ( ) != <NUM_LIT> || Align <= <NUM_LIT> || VT == <STR_LIT> ; } return true ;


<s> if ( Match2 == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ <NUM_LIT> ] ; if ( Match3 == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ <NUM_LIT> ] ; if ( Match4 == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ <NUM_LIT> ] ; SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumMatches ; ++ i ) { if ( i != <NUM_LIT> ) OS << <STR_LIT> ; if ( i + <NUM_LIT> == NumMatches ) OS << <STR_LIT> ; OS << <STR_LIT> << Base << MatchChars [ i ] << <STR_LIT> ; } OS << <STR_LIT> ; Error ( IDLoc , OS . str ( ) ) ; return true ; } if ( ( Match1 == Match_MnemonicFail ) && ( Match2 == Match_MnemonicFail ) && ( Match3 == Match_MnemonicFail ) && ( Match4 == Match_MnemonicFail ) ) { if ( ! WasOriginallyInvalidOperand ) { return Error ( IDLoc , <STR_LIT> + Base + <STR_LIT> , Op -> getLocRange ( ) ) ; } if ( OrigErrorInfo != ~ <NUM_LIT> ) { if ( OrigErrorInfo >= Operands . size ( ) ) return Error ( IDLoc , <STR_LIT> ) ; <ISA_LIT>Operand * Operand = ( <ISA_LIT>Operand * ) Operands [ OrigErrorInfo ] ; if ( Operand -> getStartLoc ( ) . isValid ( ) ) { SMRange OperandRange = Operand -> getLocRange ( ) ; return Error ( Operand -> getStartLoc ( ) , <STR_LIT> , OperandRange ) ; } } return Error ( IDLoc , <STR_LIT> ) ; } if ( ( Match1 == Match_MissingFeature ) + ( Match2 == Match_MissingFeature ) + ( Match3 == Match_MissingFeature ) + ( Match4 == Match_MissingFeature ) == <NUM_LIT> ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } if ( ( Match1 == Match_InvalidOperand ) + ( Match2 == Match_InvalidOperand ) + ( Match3 == Match_InvalidOperand ) + ( Match4 == Match_InvalidOperand ) == <NUM_LIT> ) { Error ( IDLoc , <STR_LIT> ) ; return true ; } Error ( IDLoc , <STR_LIT> ) ; return true ;


<s> return CheckImmRange ( <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , false , true , true ) ;


<s> bool <ISA_LIT>TargetMachine :: isNoopAddrSpaceCast ( unsigned SrcAS , unsigned DestAS ) const { assert ( SrcAS != DestAS && <STR_LIT> ) ;

if ( getPointerSize ( SrcAS ) != getPointerSize ( DestAS ) ) return false ;


<s> if ( ! FalseTy . isInteger ( ) ) return SDValue ( ) ; ConstantSDNode * FalseC = dyn_cast < ConstantSDNode > ( False ) ; if ( ! FalseC ) return SDValue ( ) ; const SDLoc DL ( N ) ; if ( ! FalseC -> getZExtValue ( ) ) { <STR_LIT> CC = cast < CondCodeSDNode > ( SetCC . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue True = N -> getOperand ( <NUM_LIT> ) ; SetCC = DAG . getSetCC ( DL , SetCC . getValueType ( ) , SetCC . getOperand ( <NUM_LIT> ) , SetCC . getOperand ( <NUM_LIT> ) , <STR_LIT> ( CC , SetCC . getValueType ( ) ) ) ; return DAG . getNode ( <STR_LIT> , DL , FalseTy , SetCC , False , True ) ;


<s> void <ISA_LIT>InstPrinter :: printS20ImmOperand ( const MCInst * MI , int OpNum , raw_ostream & O ) { if ( MI -> getOperand ( OpNum ) . isImm ( ) ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ;


<s> unsigned Sm = decodeVFPRm ( insn , true ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Sm ) ) ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Sm + <NUM_LIT> ) ) ) ; OpIdx += <NUM_LIT> ; } else { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , decodeVFPRm ( insn , false ) ) ) ) ; ++ OpIdx ; }


<s> void addSImm7s8Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;


<s> return ( TSFlags & <STR_LIT> ) != <NUM_LIT> ;


<s> switch ( get_attr_type ( insn ) ) { case TYPE_DIV : case TYPE_SDIV : case TYPE_DDIV :


<s> auto * ConstMask = dyn_cast < ConstantDataVector > ( Mask ) ; if ( ! ConstMask ) return false ; unsigned AddrSpace = cast < PointerType > ( Ptr -> getType ( ) ) -> getAddressSpace ( ) ; PointerType * VecPtrTy = PointerType :: get ( Vec -> getType ( ) , AddrSpace ) ; Value * PtrCast = IC . Builder . CreateBitCast ( Ptr , VecPtrTy , <STR_LIT> ) ; Constant * BoolMask = getNegativeIsTrueBoolVec ( ConstMask ) ;

IC . Builder . CreateMaskedStore ( Vec , PtrCast , Align ( <NUM_LIT> ) , BoolMask ) ;


<s> MachineInstr * SDWADstOperand :: potentialToConvert ( const <ISA_LIT>InstrInfo * TII ) { MachineRegisterInfo * MRI = getMRI ( ) ; MachineInstr * ParentMI = getParentInst ( ) ; MachineOperand * Replaced = getReplacedOperand ( ) ; assert ( Replaced -> isReg ( ) ) ; for ( MachineOperand & PotentialMO : MRI -> def_operands ( Replaced -> getReg ( ) ) ) { if ( ! isSubregOf ( * Replaced , PotentialMO , MRI -> getTargetRegisterInfo ( ) ) ) continue ; if ( ! isSameBB ( getParentInst ( ) , PotentialMO . getParent ( ) ) || ! isSameReg ( * Replaced , PotentialMO ) ) return nullptr ; for ( MachineOperand & UseMO : MRI -> use_operands ( PotentialMO . getReg ( ) ) ) { if ( isSubregOf ( UseMO , PotentialMO , MRI -> getTargetRegisterInfo ( ) ) && UseMO . getParent ( ) != ParentMI ) {


<s> return __builtin_mve_vcmpgeq_v4si ( __a , __b ) ;


<s> auto Undef = B . buildUndef ( SrcTy ) ; DupSrc = B . buildConcatVectors ( SrcTy . changeElementCount ( ElementCount :: getFixed ( <NUM_LIT> ) ) , { Src1Reg , Undef . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ; } B . buildInstr ( MatchInfo . first , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) } , { DupSrc , Lane } ) ; MI . eraseFromParent ( ) ;


<s> unsigned getCallEncoding ( const MCInst & MI , unsigned int OpNum , SmallVectorImpl < MCFixup > & Fixups ) const {

return getPCRelEncoding ( MI , OpNum , Fixups , <STR_LIT> , <NUM_LIT> ) ;


<s> bool <ISA_LIT>TargetMachine :: addPostRegAlloc ( PassManagerBase & PM , CodeGenOpt :: Level OptLevel ) { PM . add ( create<ISA_LIT>MemSelOptimizerPass ( ) ) ; return true ;


<s> const std :: vector < IndexAndAttrSet > & getAttributeGroups ( ) const {


<s> BBInfo . InQueue = false ; VSETVLIInfo InInfo ; if ( MBB . pred_empty ( ) ) { InInfo . setUnknown ( ) ; } else { for ( MachineBasicBlock * P : MBB . predecessors ( ) ) InInfo = InInfo . intersect ( BlockInfo [ P -> getNumber ( ) ] . Exit ) ; }


<s> if ( MI -> hasUnmodeledSideEffects ( ) ) return false ;

if ( MI -> getOpcode ( ) == TargetOpcode :: LIFETIME_END ) return false ;


<s> if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 ) ; if ( isSingleInputShuffleMask ( Mask ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( RepeatedMask , DAG ) ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; if ( isShuffleEquivalent ( Mask , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V2 ) ; for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) if ( RepeatedMask [ i ] >= <NUM_LIT> ) RepeatedMask [ i ] -= <NUM_LIT> ; return lowerVectorShuffleWithSHUFPS ( DL , <STR_LIT> , RepeatedMask , V1 , V2 , DAG ) ; } if ( isSingleInputShuffleMask ( Mask ) ) { SDValue VPermMask [ <NUM_LIT> ] ;

for ( int i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) VPermMask [ i ] = Mask [ i ] < <NUM_LIT> ? DAG . getUNDEF ( <STR_LIT> ) : DAG . getConstant ( Mask [ i ] , <STR_LIT> ) ;


<s> static const char * aarch64_mangle_type ( const_tree type ) { if ( lang_hooks . types_compatible_p ( CONST_CAST_TREE ( type ) , va_list_type ) ) return <STR_LIT> ;

if ( TREE_CODE ( type ) == REAL_TYPE && TYPE_PRECISION ( type ) == <NUM_LIT> ) return <STR_LIT> ;


<s> <STR_LIT> e = static_cast < <STR_LIT> > ( MI -> getOperand ( OpNo ) . getImm ( ) ) ;


<s> <ISA_LIT>MCExpr :: VariantKind Kind = ( <ISA_LIT>MCExpr :: VariantKind ) MO . getTargetFlags ( ) ;

const MCSymbolRefExpr * MCSym = MCSymbolRefExpr :: create ( Symbol , AP . OutContext ) ;


<s> else set = nullptr ; } uint8_t sew = get_sew ( insn -> rtl ( ) ) ; enum vlmul_type vlmul = get_vlmul ( insn -> rtl ( ) ) ; uint8_t ratio = get_attr_ratio ( insn -> rtl ( ) ) ; if ( ratio == INVALID_ATTRIBUTE ) ratio = calculate_ratio ( sew , vlmul ) ; bool ta = tail_agnostic_p ( insn -> rtl ( ) ) ; bool ma = mask_agnostic_p ( insn -> rtl ( ) ) ;

int merge_op_idx = get_attr_merge_op_idx ( insn -> rtl ( ) ) ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_ARM , false ) {


<s> const TargetInstrInfo * TII = MF . getSubtarget ( ) . getInstrInfo ( ) ; MachineInstr * cmpInst = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg1 ( reg ) ) ; lastCheck -> insert ( CI , cmpInst ) ; MachineInstr * copyMoveM = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( reg ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( reg ) ; lastCheck -> insert ( CI , copyMoveM ) ; MachineInstr * copyMoveD = BuildMI ( MF , DL3 , TII -> get ( <STR_LIT> ) ) . addReg ( getSlaveReg1 ( reg ) ) . addReg ( getSlaveReg2 ( reg ) ) . addReg ( getSlaveReg1 ( reg ) ) ; lastCheck -> insert ( CI , copyMoveD ) ;


<s> bool isToken ( ) const override { return Kind == k_Token ;


<s> if ( GET_CODE ( x ) == POST_MODIFY ) return ( RTX_OK_FOR_BASE_P ( XEXP ( x , <NUM_LIT> ) , strict ) && CONSTANT_ADDRESS_P ( XEXP ( x , <NUM_LIT> ) ) ) ; } if ( GET_CODE ( x ) != PLUS ) return false ; base = XEXP ( x , <NUM_LIT> ) ; index = XEXP ( x , <NUM_LIT> ) ; if ( ! REG_P ( base ) ) return false ; if ( REG_P ( index ) ) { if ( ! TARGET_AM33 ) return false ; return ( REGNO_GENERAL_P ( REGNO ( base ) , strict ) && REGNO_GENERAL_P ( REGNO ( index ) , strict ) ) ; } if ( ! REGNO_STRICT_OK_FOR_BASE_P ( REGNO ( base ) , strict ) ) return false ; if ( CONST_INT_P ( index ) ) return IN_RANGE ( INTVAL ( index ) , - <NUM_LIT> - <NUM_LIT> , <NUM_LIT> ) ; if ( CONSTANT_ADDRESS_P ( index ) ) return ! flag_pic || mn10300_legitimate_pic_operand_p ( index ) ;


<s> if ( IsPCRel ) { switch ( ( unsigned ) Fixup . getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case FK_PCRel_2 : Type = ELF :: R_TEERISC_32_PCREL ; break ; }


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == <NUM_LIT> ) return false ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; Target = Addr + Size + Imm ; return true ;


<s> RegisterTargetMachine < <ISA_LIT>ebTargetMachine > A ( The<ISA_LIT>64Target ) ;

RegisterTargetMachine < <ISA_LIT>elTargetMachine > B ( The<ISA_LIT>64elTarget ) ;