<s> } case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getHiddenGVStubEntry ( Sym ) ; if ( ! StubSym . getPointer ( ) ) { assert ( MO . isGlobal ( ) && <STR_LIT> ) ; StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } break ; } case <STR_LIT> : { MachineModuleInfoImpl :: StubValueTy & StubSym = getMachOMMI ( ) . getFnStubEntry ( Sym ) ; if ( StubSym . getPointer ( ) ) return Sym ; if ( MO . isGlobal ( ) ) { StubSym = MachineModuleInfoImpl :: StubValueTy ( AsmPrinter . getSymbol ( MO . getGlobal ( ) ) , ! MO . getGlobal ( ) -> hasInternalLinkage ( ) ) ; } else { StubSym = MachineModuleInfoImpl ::

StubValueTy ( Ctx . GetOrCreateSymbol ( OrigName ) , false ) ;


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return & FrameLowering ;


<s> return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm ) ;


<s> pcrel_opt ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_pcrel_opt , ctxt ) {


<s> uint64_t <ISA_LIT>InstrInfo :: getElementSizeForOpcode ( unsigned Opc ) const { return get ( Opc ) . TSFlags & <STR_LIT> ;


<s> const MCSchedClassDesc * SC = TSchedModel . resolveSchedClass ( & MI ) ; assert ( TSchedModel . getWriteProcResBegin ( SC ) != TSchedModel . getWriteProcResEnd ( SC ) ) ;

return TSchedModel . getWriteProcResBegin ( SC ) -> Cycles ;


<s> if ( SUBTARGET_FRAME_POINTER_REQUIRED ) return true ; if ( TARGET_32BIT_MS_ABI && cfun -> calls_setjmp ) return true ;

if ( TARGET_64BIT_MS_ABI && get_frame_size ( ) > SEH_MAX_FRAME_SIZE ) return true ;


<s> auto Res = std :: make_unique < <ISA_LIT>Operand > ( OpKind :: RoundMode , StartLoc , EndLoc ) ; Res -> RoundMode . Name = Name ; Res -> RoundMode . Val = Val ; return Res ;


<s> Register Def = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Use = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineBasicBlock * CondBrTarget = BrCond -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; B . setInsertPt ( B . getMBB ( ) , BrCond -> getIterator ( ) ) ; if ( IntrID == <STR_LIT> ) { B . buildInstr ( <STR_LIT> ) . addDef ( Def ) . addUse ( Use ) . addMBB ( UncondBrTarget ) ; } else { B . buildInstr ( <STR_LIT> ) . addDef ( Def ) . addUse ( Use ) . addMBB ( UncondBrTarget ) . addImm ( <NUM_LIT> ) ; } if ( Br ) { Br -> getOperand ( <NUM_LIT> ) . setMBB ( CondBrTarget ) ; } else { B . buildBr ( * CondBrTarget ) ; } MRI . setRegClass ( Def , TRI -> getWaveMaskRegClass ( ) ) ; MRI . setRegClass ( Use , TRI -> getWaveMaskRegClass ( ) ) ; MI . eraseFromParent ( ) ; BrCond -> eraseFromParent ( ) ; return true ; } return false ; } case <STR_LIT> : { MachineInstr * Br = nullptr ; MachineBasicBlock * UncondBrTarget = nullptr ; if ( MachineInstr * BrCond = verifyCFIntrinsic ( MI , MRI , Br , UncondBrTarget ) ) { const <ISA_LIT>RegisterInfo * TRI = static_cast < const <ISA_LIT>RegisterInfo * > ( MRI . getTargetRegisterInfo ( ) ) ; MachineBasicBlock * CondBrTarget = BrCond -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Register Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; B . setInsertPt ( B . getMBB ( ) , BrCond -> getIterator ( ) ) ; B . buildInstr ( <STR_LIT> ) . addUse ( Reg ) . addMBB ( UncondBrTarget ) ; if ( Br ) Br -> getOperand ( <NUM_LIT> ) . setMBB ( CondBrTarget ) ; else B . buildBr ( * CondBrTarget ) ; MI . eraseFromParent ( ) ; BrCond -> eraseFromParent ( ) ; MRI . setRegClass ( Reg , TRI -> getWaveMaskRegClass ( ) ) ; return true ; } return false ; } case <STR_LIT> : if ( ! <STR_LIT> ( B . getMF ( ) . getFunction ( ) . getCallingConv ( ) ) ) { B . buildConstant ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , <NUM_LIT> ) ; MI . eraseFromParent ( ) ; return true ; } return legalizePreloadedArgIntrin ( MI , MRI , B , <STR_LIT> ) ; case <STR_LIT> :

return legalizeImplicitArgPtr ( MI , MRI , B ) ;


<s> MEM_NOTRAP_P ( mem ) = <NUM_LIT> ; set_mem_alias_set ( mem , get_varargs_alias_set ( ) ) ; return mem ;


<s> __attribute__ ( ( vector_size ( <NUM_LIT> ) ) ) ;


<s> bool <ISA_LIT>AsmParser :: ParseInstruction ( ParseInstructionInfo & Info , StringRef Name , AsmToken ID , OperandVector & Operands ) {


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : Res . setOpcode ( <STR_LIT> ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; Res . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Res . addOperand ( Inst . getOperand ( <NUM_LIT> ) ) ; break ;


<s> } else if ( GET_CODE ( addr ) == REG ) { base = addr ; offset = const0_rtx ; } if ( base != NULL_RTX ) { int regno = REGNO ( base ) ; if ( regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM ) { if ( ( ( cfun != <NUM_LIT> && REGNO_POINTER_ALIGN ( regno ) >= desired * BITS_PER_UNIT ) || ( optimize && reload_completed ) ) && ( INTVAL ( offset ) & ( desired - <NUM_LIT> ) ) == <NUM_LIT> ) return <NUM_LIT> ; }


<s> return isMemDisp12 ( BDXMem , ADDR64Reg ) ;


<s> __o = __builtin_aarch64_ld4rv2si ( ( const __builtin_aarch64_simd_si * ) __a ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int32x2_t ) __builtin_aarch64_get_dregxiv2si ( __o , <NUM_LIT> ) ; return ret ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ;

Inst . addOperand ( MCOperand :: createImm ( ( CE -> getValue ( ) - <NUM_LIT> ) / <NUM_LIT> ) ) ;


<s> } for ( ; i < insn_data [ icode ] . n_operands && arglist != <NUM_LIT> ; i ++ ) ops [ i ] = mips_prepare_builtin_arg ( icode , i , & arglist ) ; switch ( i ) { case <NUM_LIT> : emit_insn ( GEN_FCN ( icode ) ( ops [ <NUM_LIT> ] , ops [ <NUM_LIT> ] ) ) ; break ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> return CurDAG -> getTargetConstant ( Imm , dl , <STR_LIT> ) ;


<s> if ( MEM_VOLATILE_P ( mem [ i ] ) ) return false ; extract_base_offset_in_addr ( mem [ i ] , base + i , offset + i ) ; if ( base [ i ] == NULL_RTX || offset [ i ] == NULL_RTX ) return false ; } rclass = REG_P ( reg [ <NUM_LIT> ] ) && FP_REGNUM_P ( REGNO ( reg [ <NUM_LIT> ] ) ) ? FP_REGS : GENERAL_REGS ; for ( int i = <NUM_LIT> ; i < num_insns ; i ++ ) if ( REG_P ( reg [ i ] ) && FP_REGNUM_P ( REGNO ( reg [ i ] ) ) ) { if ( rclass != FP_REGS ) return false ; } else { if ( rclass != GENERAL_REGS ) return false ; } if ( rclass == GENERAL_REGS && load ) for ( int i = <NUM_LIT> ; i < num_insns - <NUM_LIT> ; i ++ ) if ( reg_mentioned_p ( reg [ i ] , mem [ i ] ) ) return false ; for ( int i = <NUM_LIT> ; i < num_insns - <NUM_LIT> ; i ++ ) if ( ! rtx_equal_p ( base [ i ] , base [ i + <NUM_LIT> ] ) ) return false ; for ( int i = <NUM_LIT> ; i < num_insns ; i ++ ) offvals [ i ] = INTVAL ( offset [ i ] ) ; msize = GET_MODE_SIZE ( mode ) . to_constant ( ) ; qsort ( offvals , num_insns , sizeof ( HOST_WIDE_INT ) , aarch64_host_wide_int_compare ) ; if ( ! ( offvals [ <NUM_LIT> ] == offvals [ <NUM_LIT> ] + msize && offvals [ <NUM_LIT> ] == offvals [ <NUM_LIT> ] + msize ) ) return false ; if ( offvals [ <NUM_LIT> ] - offvals [ <NUM_LIT> ] >= msize * <NUM_LIT> ) return false ; if ( offvals [ <NUM_LIT> ] % msize != offvals [ <NUM_LIT> ] % msize ) return false ; if ( mode == SImode && ( aarch64_tune_params . extra_tuning_flags & AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW ) && ! optimize_size && MEM_ALIGN ( mem [ <NUM_LIT> ] ) < <NUM_LIT> * BITS_PER_UNIT ) return false ;


<s> SDValue GRTop , GRTopAddr ; GRTopAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( Offset , DL , PtrVT ) ) ; GRTop = DAG . getFrameIndex ( FuncInfo -> getVarArgsGPRIndex ( ) , PtrVT ) ; GRTop = DAG . getNode ( <STR_LIT> , DL , PtrVT , GRTop , DAG . getConstant ( GPRSize , DL , PtrVT ) ) ; GRTop = DAG . getZExtOrTrunc ( GRTop , DL , PtrMemVT ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , GRTop , GRTopAddr , MachinePointerInfo ( SV , Offset ) , Align ( PtrSize ) ) ) ; } Offset += PtrSize ; int FPRSize = FuncInfo -> getVarArgsFPRSize ( ) ; if ( FPRSize > <NUM_LIT> ) { SDValue VRTop , VRTopAddr ; VRTopAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( Offset , DL , PtrVT ) ) ; VRTop = DAG . getFrameIndex ( FuncInfo -> getVarArgsFPRIndex ( ) , PtrVT ) ; VRTop = DAG . getNode ( <STR_LIT> , DL , PtrVT , VRTop , DAG . getConstant ( FPRSize , DL , PtrVT ) ) ; VRTop = DAG . getZExtOrTrunc ( VRTop , DL , PtrMemVT ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , VRTop , VRTopAddr , MachinePointerInfo ( SV , Offset ) , Align ( PtrSize ) ) ) ; } Offset += PtrSize ; SDValue GROffsAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( Offset , DL , PtrVT ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , DAG . getConstant ( - GPRSize , DL , <STR_LIT> ) , GROffsAddr , MachinePointerInfo ( SV , Offset ) , Align ( <NUM_LIT> ) ) ) ; Offset += <NUM_LIT> ; SDValue VROffsAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , VAList , DAG . getConstant ( Offset , DL , PtrVT ) ) ; MemOps . push_back ( DAG . getStore ( Chain , DL , DAG . getConstant ( - FPRSize , DL , <STR_LIT> ) , VROffsAddr , MachinePointerInfo ( SV , Offset ) , Align ( <NUM_LIT> ) ) ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOps ) ;


<s> OffsetRegNum = TryParseRegister ( ) ; if ( OffsetRegNum != - <NUM_LIT> ) { OffsetIsReg = true ; E = CurLoc ; } } if ( OffsetRegNum != - <NUM_LIT> ) { const AsmToken & Tok = Parser . getTok ( ) ; if ( Tok . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; const AsmToken & Tok = Parser . getTok ( ) ; if ( ParseShift ( ShiftType , ShiftAmount , E ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; OffsetRegShifted = true ; } } else { const AsmToken & HashTok = Parser . getTok ( ) ; if ( HashTok . isNot ( AsmToken :: Hash ) ) return Error ( HashTok . getLoc ( ) , <STR_LIT> ) ; Parser . Lex ( ) ;

if ( getParser ( ) . ParseExpression ( Offset ) ) return true ;


<s> eliminatePhis ( SuccB ) ; HII -> removeBranch ( * PredB ) ; PredB -> removeSuccessor ( SuccB ) ; PredB -> splice ( PredB -> end ( ) , SuccB , SuccB -> begin ( ) , SuccB -> end ( ) ) ;

PredB -> transferSuccessorsAndUpdatePHIs ( SuccB ) ;


<s> } case <STR_LIT> : return ELF :: R_<ISA_LIT>_32 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_7_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_13_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_16_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI_PM_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI_PM_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI_PM_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_6_ADIW ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MS8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MS8_LDI_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI_GS ; case <STR_LIT> :


<s> if ( NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , arg . mode , arg . type ) >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS ) return <NUM_LIT> ; needed_reg_count = NDS32_NEED_N_REGS_FOR_ARG ( arg . mode , arg . type ) ;

remaining_reg_count = NDS32_MAX_GPR_REGS_FOR_ARGS - ( NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG ( cum -> gpr_offset , arg . mode , arg . type ) - NDS32_GPR_ARG_FIRST_REGNUM ) ;


<s> case amImmediate : case amAbsolute : if ( Bytes . size ( ) < ( Words + <NUM_LIT> ) * <NUM_LIT> ) { Size = <NUM_LIT> ; return DecodeStatus :: Fail ; } Insn |= ( uint64_t ) <STR_LIT> :: read16le ( Bytes . data ( ) + <NUM_LIT> ) << <NUM_LIT> ; ++ Words ; break ; default : break ; } switch ( DstAM ) { case amIndexed : case amSymbolic : case amAbsolute : if ( Bytes . size ( ) < ( Words + <NUM_LIT> ) * <NUM_LIT> ) {


<s> if ( ! CSel0 -> hasOneUse ( ) || ! CSel1 -> hasOneUse ( ) ) return SDValue ( ) ; if ( ! isNullConstant ( CSel0 . getOperand ( <NUM_LIT> ) ) || ! isOneConstant ( CSel0 . getOperand ( <NUM_LIT> ) ) || ! isNullConstant ( CSel1 . getOperand ( <NUM_LIT> ) ) || ! isOneConstant ( CSel1 . getOperand ( <NUM_LIT> ) ) ) return SDValue ( ) ; SDValue Cmp0 = CSel0 . getOperand ( <NUM_LIT> ) ; SDValue Cmp1 = CSel1 . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC0 = ( <STR_LIT> ) CSel0 . getConstantOperandVal ( <NUM_LIT> ) ; <STR_LIT> CC1 = ( <STR_LIT> ) CSel1 . getConstantOperandVal ( <NUM_LIT> ) ; if ( ! Cmp0 -> hasOneUse ( ) || ! Cmp1 -> hasOneUse ( ) ) return SDValue ( ) ; if ( Cmp1 . getOpcode ( ) != <STR_LIT> && Cmp0 . getOpcode ( ) == <STR_LIT> ) { std :: swap ( Cmp0 , Cmp1 ) ; std :: swap ( CC0 , CC1 ) ; } if ( Cmp1 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDLoc DL ( N ) ; SDValue CCmp ; if ( N -> getOpcode ( ) == <STR_LIT> ) { <STR_LIT> InvCC0 = <STR_LIT> ( CC0 ) ; SDValue Condition = DAG . getConstant ( InvCC0 , DL , MVT_CC ) ; unsigned NZCV = <STR_LIT> ( CC1 ) ; SDValue NZCVOp = DAG . getConstant ( NZCV , DL , <STR_LIT> ) ; CCmp = DAG . getNode ( <STR_LIT> , DL , MVT_CC , Cmp1 . getOperand ( <NUM_LIT> ) , Cmp1 . getOperand ( <NUM_LIT> ) , NZCVOp , Condition , Cmp0 ) ; } else {


<s> <ISA_LIT>SelectionDAGInfo ( const <ISA_LIT>TargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) {


<s> instr_iterator CmpIt = CmpI , NextIt = llvm :: next ( CmpIt ) ; for ( instr_iterator I = NextIt , E = BB -> instr_end ( ) ; I != E ; ++ I ) { MachineInstr * In = & * I ; for ( unsigned i = <NUM_LIT> , n = In -> getNumOperands ( ) ; i < n ; ++ i ) { MachineOperand & MO = In -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isUse ( ) ) { if ( MO . getReg ( ) == PredR ) return false ; } } if ( In == BumpI ) { instr_iterator After = BumpI ; instr_iterator From = CmpI ; BB -> splice ( llvm :: next ( After ) , BB , From ) ; FoundBump = true ; break ; }


<s> static void addOperands ( MachineInstrBuilder & MIB , ArrayRef < MachineOperand > MOs , int PtrOffset = <NUM_LIT> ) { unsigned NumAddrOps = MOs . size ( ) ; if ( NumAddrOps < <NUM_LIT> ) {

for ( unsigned i = <NUM_LIT> ; i != NumAddrOps ; ++ i ) MIB . addOperand ( MOs [ i ] ) ;


<s> unsigned Reg = VMRegDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: createReg ( Reg ) ) ;


<s> bool getMAIIsDGEMM ( unsigned Opc ) { const MAIInstInfo * Info = getMAIInstInfoHelper ( Opc ) ;

return Info ? Info -> is_dgemm : false ;


<s> int visium_interrupt_function_p ( void ) {


<s> DEBUG ( errs ( ) << <STR_LIT> ) ; DEBUG ( N -> dump ( CurDAG ) ) ; DEBUG ( errs ( ) << <STR_LIT> ) ; if ( N -> isMachineOpcode ( ) ) { DEBUG ( errs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; N -> setNodeId ( - <NUM_LIT> ) ; return NULL ; } switch ( N -> getOpcode ( ) ) { case <STR_LIT> : { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; assert ( VT == <STR_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; unsigned Opc = <STR_LIT> ; SDNode * res ; if ( N -> hasOneUse ( ) ) { res = CurDAG -> SelectNodeTo ( N , Opc , VT , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } else { res = CurDAG -> getMachineNode ( Opc , dl , VT , TFI , CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ) ; } return res ;


<s> lo = gen_rtx_REG ( SImode , LO_REGNO ) ; if ( dest ) pattern = gen_mulsi3r ( lo , dest , copy_rtx ( dest ) , mep_mulr_source ( insn , dest , src1 , src2 ) ) ;

else pattern = gen_mulsi3_lo ( lo , src1 , src2 ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & ctx , const <ISA_LIT>AsmPrinter & ap ) : Ctx ( ctx ) , AP ( ap ) {


<s> & <STR_LIT> ; Register ImmReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ImmReg ) . addImm ( Imm ) ) ; return ImmReg ; } } unsigned ResultReg = <NUM_LIT> ; if ( Subtarget -> useMovt ( ) ) ResultReg = fastEmit_i ( VT , VT , <STR_LIT> , CI -> getZExtValue ( ) ) ; if ( ResultReg ) return ResultReg ; if ( VT != <STR_LIT> ) return <NUM_LIT> ; Align Alignment = DL . getPrefTypeAlign ( C -> getType ( ) ) ; unsigned Idx = MCP . getConstantPoolIndex ( C , Alignment ) ; ResultReg = createResultReg ( TLI . getRegClassFor ( VT ) ) ;

if ( isThumb2 ) AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addConstantPoolIndex ( Idx ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShifts ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerDivRem ( Op , DAG ) ;


<s> vmovn_u16 ( uint16x8_t a ) { uint8x8_t result ;

__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) : ) ;


<s> std :: pair < bool , SDNode * > <ISA_LIT>SEDAGToDAGISel :: selectNode ( SDNode * Node ) { unsigned Opcode = Node -> getOpcode ( ) ; SDLoc DL ( Node ) ; SDNode * Result ; switch ( Opcode ) { default : break ; case <STR_LIT> : { SDValue InFlag = Node -> getOperand ( <NUM_LIT> ) ; Result = selectAddESubE ( <STR_LIT> , InFlag , InFlag . getOperand ( <NUM_LIT> ) , DL , Node ) ; return std :: make_pair ( true , Result ) ; } case <STR_LIT> : { if ( Subtarget -> hasDSP ( ) ) break ; SDValue InFlag = Node -> getOperand ( <NUM_LIT> ) ; Result = selectAddESubE ( <STR_LIT> , InFlag , InFlag . getValue ( <NUM_LIT> ) , DL , Node ) ; return std :: make_pair ( true , Result ) ; } case <STR_LIT> : { ConstantFPSDNode * CN = dyn_cast < ConstantFPSDNode > ( Node ) ; if ( Node -> getValueType ( <NUM_LIT> ) == <STR_LIT> && CN -> isExactlyValue ( + <NUM_LIT> ) ) { SDValue Zero = CurDAG -> getCopyFromReg ( CurDAG -> getEntryNode ( ) , DL , <STR_LIT> , <STR_LIT> ) ; Result = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Zero , Zero ) ; return std :: make_pair ( true , Result ) ; } break ; } case <STR_LIT> : { const ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Node ) ; unsigned Size = CN -> getValueSizeInBits ( <NUM_LIT> ) ; assert ( Size == <NUM_LIT> && <STR_LIT> ) ; if ( Size == <NUM_LIT> ) break ; } case <STR_LIT> : { switch ( cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : break ; } break ; } case <STR_LIT> : { switch ( cast < ConstantSDNode > ( Node -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default :


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( const <ISA_LIT>Subtarget & STI ) : TargetInstrInfoImpl ( <ISA_LIT>Insts , array_lengthof ( <ISA_LIT>Insts ) ) , RI ( * this , STI ) {


<s> if ( ! TARGET_32BIT ) return false ; * p1 = CC_REGNUM ;


<s> if ( addend ) { x = gen_rtx_PLUS ( SImode , x , addend ) ; orig_x = x ; } else return x ; } if ( ! TARGET_ARM ) { if ( TARGET_THUMB2 ) return x ; return thumb_legitimize_address ( x , orig_x , mode ) ; } if ( GET_CODE ( x ) == PLUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( CONSTANT_P ( xop0 ) && ! symbol_mentioned_p ( xop0 ) ) xop0 = force_reg ( SImode , xop0 ) ; if ( CONSTANT_P ( xop1 ) && ! CONST_INT_P ( xop1 ) && ! symbol_mentioned_p ( xop1 ) ) xop1 = force_reg ( SImode , xop1 ) ; if ( ARM_BASE_REGISTER_RTX_P ( xop0 ) && CONST_INT_P ( xop1 ) ) { HOST_WIDE_INT n , low_n ; rtx base_reg , val ; n = INTVAL ( xop1 ) ; if ( mode == DImode || mode == DFmode ) { low_n = n & <NUM_LIT> ; n &= ~ <NUM_LIT> ; if ( low_n > <NUM_LIT> ) { n += <NUM_LIT> ; low_n -= <NUM_LIT> ; } } else { low_n = ( ( mode ) == TImode ? <NUM_LIT> : n >= <NUM_LIT> ? ( n & <NUM_LIT> ) : - ( ( - n ) & <NUM_LIT> ) ) ; n -= low_n ; } base_reg = gen_reg_rtx ( SImode ) ; val = force_operand ( plus_constant ( Pmode , xop0 , n ) , NULL_RTX ) ; emit_move_insn ( base_reg , val ) ; x = plus_constant ( Pmode , base_reg , low_n ) ; } else if ( xop0 != XEXP ( x , <NUM_LIT> ) || xop1 != XEXP ( x , <NUM_LIT> ) ) x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } else if ( GET_CODE ( x ) == MINUS ) { rtx xop0 = XEXP ( x , <NUM_LIT> ) ; rtx xop1 = XEXP ( x , <NUM_LIT> ) ; if ( CONSTANT_P ( xop0 ) ) xop0 = force_reg ( SImode , xop0 ) ;

if ( CONSTANT_P ( xop1 ) && ! symbol_mentioned_p ( xop1 ) ) xop1 = force_reg ( SImode , xop1 ) ;


int64_t Flags = MCI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> static DecodeStatus DecodeDPRRegListOperand ( llvm :: MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { DecodeStatus S = MCDisassembler :: Success ; unsigned Vd = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; unsigned regs = ( Val & <NUM_LIT> ) / <NUM_LIT> ; if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < ( regs - <NUM_LIT> ) ; ++ i ) {

if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , ++ Vd , Address , Decoder ) ) ) return MCDisassembler :: Fail ;


<s> if ( ! SelectAddr ( Node , Ptr , Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 ) ) return <NUM_LIT> ; enum AtomicOpc Op ; switch ( Node -> getOpcode ( ) ) { default : return <NUM_LIT> ; case <STR_LIT> : Op = OR ; break ; case <STR_LIT> : Op = AND ; break ; case <STR_LIT> : Op = XOR ; break ; case <STR_LIT> : Op = ADD ; break ; } Val = getAtomicLoadArithTargetConstant ( CurDAG , dl , Op , NVT , Val ) ; bool isUnOp = ! Val . getNode ( ) ; bool isCN = Val . getNode ( ) && ( Val . getOpcode ( ) == <STR_LIT> ) ; unsigned Opc = <NUM_LIT> ; switch ( NVT . getSimpleVT ( ) . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : if ( isCN ) Opc = AtomicOpcTbl [ Op ] [ ConstantI8 ] ; else Opc = AtomicOpcTbl [ Op ] [ I8 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI16 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI16 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I16 ] ; break ; case <STR_LIT> : if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI32 ] ; else Opc = AtomicOpcTbl [ Op ] [ ConstantI32 ] ; } else Opc = AtomicOpcTbl [ Op ] [ I32 ] ; break ; case <STR_LIT> : Opc = AtomicOpcTbl [ Op ] [ I64 ] ; if ( isCN ) { if ( immSext8 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ SextConstantI64 ] ; else if ( i64immSExt32 ( Val . getNode ( ) ) ) Opc = AtomicOpcTbl [ Op ] [ ConstantI64 ] ; } break ; } assert ( Opc != <NUM_LIT> && <STR_LIT> ) ; SDValue Ret ; SDValue Undef = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: IMPLICIT_DEF , dl , NVT ) , <NUM_LIT> ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( Node ) -> getMemOperand ( ) ; if ( isUnOp ) { SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Chain } ; Ret = SDValue ( CurDAG -> getMachineNode ( Opc , dl , <STR_LIT> , Ops ) , <NUM_LIT> ) ; } else { SDValue Ops [ ] = { Tmp0 , Tmp1 , Tmp2 , Tmp3 , Tmp4 , Val , Chain } ;


<s> if ( isSSetReg ( MI -> getOpcode ( ) ) && checkSetRegHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( isRFE ( MI -> getOpcode ( ) ) && checkRFEHazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0MovRelInterpHazard ( ) && ( TII . isVINTRP ( * MI ) || isSMovRel ( MI -> getOpcode ( ) ) ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( ST . hasReadM0SendMsgHazard ( ) && isSendMsgTraceDataOrGDS ( TII , * MI ) && checkReadM0Hazards ( MI ) > <NUM_LIT> ) return NoopHazard ; if ( MI -> isInlineAsm ( ) && checkInlineAsmHazards ( MI ) > <NUM_LIT> ) return NoopHazard ;

if ( checkAnyInstHazards ( MI ) > <NUM_LIT> ) return NoopHazard ;


<s> inline SDValue XformSToSM3Imm ( unsigned Imm , SDLoc DL ) { return CurDAG -> getTargetConstant ( Imm - <NUM_LIT> , DL , <STR_LIT> ) ;


<s> bool <ISA_LIT>LowerRefTypesIntPtrConv :: runOnFunction ( Function & F ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> <STR_LIT> << F . getName ( ) << '\n' ) ; std :: set < Instruction * > worklist ; for ( inst_iterator I = inst_begin ( F ) , E = inst_end ( F ) ; I != E ; ++ I ) {

PtrToIntInst * PTI = dyn_cast < PtrToIntInst > ( & * I ) ;


<s> AU . addRequired < <ISA_LIT>ModuleAnalysis > ( ) ;

AU . addPreserved < <ISA_LIT>ModuleAnalysis > ( ) ;


<s> int RegNo = tryParseRegister ( ) ; if ( RegNo == - <NUM_LIT> ) return true ; Operands . push_back ( <ISA_LIT>Operand :: CreateReg ( RegNo , S , Parser . getTok ( ) . getLoc ( ) ) ) ; const AsmToken & ExclaimTok = Parser . getTok ( ) ; if ( ExclaimTok . is ( AsmToken :: Exclaim ) ) { Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( ExclaimTok . getString ( ) , ExclaimTok . getLoc ( ) ) ) ; Parser . Lex ( ) ; return false ; } if ( Parser . getTok ( ) . is ( AsmToken :: LBrac ) ) { SMLoc SIdx = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; if ( getParser ( ) . ParseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) { TokError ( <STR_LIT> ) ; return MatchOperand_ParseFail ; } SMLoc E = Parser . getTok ( ) . getLoc ( ) ; if ( Parser . getTok ( ) . isNot ( AsmToken :: RBrac ) ) { Error ( E , <STR_LIT> ) ; return MatchOperand_ParseFail ; } Parser . Lex ( ) ; Operands . push_back ( <ISA_LIT>Operand :: CreateVectorIndex ( MCE -> getValue ( ) , SIdx , E , getContext ( ) ) ) ; } return false ;


<s> } while ( MBB != InsertBB ) { if ( CannotProvideElements ( MBB , NumElements ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } MBB = * MBB -> pred_begin ( ) ; } auto IsValidSub = [ ] ( MachineInstr * MI , unsigned ExpectedVecWidth ) { unsigned ImmOpIdx = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : ImmOpIdx = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : ImmOpIdx = <NUM_LIT> ; break ; } return MI -> getOperand ( ImmOpIdx ) . getImm ( ) == ExpectedVecWidth ; } ; MBB = VCTP -> getParent ( ) ; if ( MachineInstr * Def = RDA . getReachingMIDef ( & MBB -> back ( ) , NumElements ) ) { SmallPtrSet < MachineInstr * , <NUM_LIT> > ElementChain ; SmallPtrSet < MachineInstr * , <NUM_LIT> > Ignore = { VCTP } ; unsigned ExpectedVectorWidth = getTailPredVectorWidth ( VCTP -> getOpcode ( ) ) ; if ( RDA . isSafeToRemove ( Def , ElementChain , Ignore ) ) { bool FoundSub = false ; for ( auto * MI : ElementChain ) { if ( isMovRegOpcode ( MI -> getOpcode ( ) ) ) continue ; if ( isSubImmOpcode ( MI -> getOpcode ( ) ) ) {

if ( FoundSub || ! IsValidSub ( MI , ExpectedVectorWidth ) ) return false ;


<s> } if ( SDValue Shift = lowerVectorShuffleAsShift ( DL , <STR_LIT> , V1 , V2 , Mask , Zeroable , Subtarget , DAG ) ) return Shift ; if ( SDValue Rotate = lowerVectorShuffleAsRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Rotate = lowerVectorShuffleAsByteRotate ( DL , <STR_LIT> , V1 , V2 , Mask , Subtarget , DAG ) ) return Rotate ; if ( SDValue Unpck = lowerVectorShuffleWithUNPCK ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ) return Unpck ; if ( SDValue V = lowerVectorShuffleToEXPAND ( DL , <STR_LIT> , Zeroable , Mask , V1 , V2 , DAG , Subtarget ) ) return V ;

return lowerVectorShuffleWithPERMV ( DL , <STR_LIT> , Mask , V1 , V2 , DAG ) ;


<s> arg_words = crtl -> args . info . arg_words ; f_stk = TYPE_FIELDS ( va_list_type_node ) ; f_reg = DECL_CHAIN ( f_stk ) ; f_ndx = DECL_CHAIN ( f_reg ) ; stk = build3 ( COMPONENT_REF , TREE_TYPE ( f_stk ) , valist , f_stk , NULL_TREE ) ; reg = build3 ( COMPONENT_REF , TREE_TYPE ( f_reg ) , unshare_expr ( valist ) , f_reg , NULL_TREE ) ; ndx = build3 ( COMPONENT_REF , TREE_TYPE ( f_ndx ) , unshare_expr ( valist ) , f_ndx , NULL_TREE ) ; u = make_tree ( sizetype , expand_builtin_saveregs ( ) ) ; u = fold_convert ( ptr_type_node , u ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , reg , u ) ; TREE_SIDE_EFFECTS ( t ) = <NUM_LIT> ; expand_expr ( t , const0_rtx , VOIDmode , EXPAND_NORMAL ) ; u = make_tree ( ptr_type_node , virtual_incoming_args_rtx ) ; u = fold_build_pointer_plus_hwi ( u , - <NUM_LIT> ) ; t = build2 ( MODIFY_EXPR , ptr_type_node , stk , u ) ;


<s> switch ( RetVT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ;

bool RHSIsKill = hasTrivialKill ( RHS ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> const unsigned SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; const LLT DstTy = MRI . getType ( DstReg ) ; const LLT SrcTy = MRI . getType ( SrcReg ) ; if ( SrcTy == LLT :: scalar ( <NUM_LIT> ) ) { unsigned AndOpc ; if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ; else if ( DstTy == LLT :: scalar ( <NUM_LIT> ) ) AndOpc = <STR_LIT> ;


<s> static void emitThumbRegPlusImmInReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator & MBBI , const DebugLoc & dl , unsigned DestReg , unsigned BaseReg , int NumBytes , bool CanChangeCC , const TargetInstrInfo & TII , const <ISA_LIT>BaseRegisterInfo & MRI , unsigned MIFlags = MachineInstr :: NoFlags ) { MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; bool isHigh = ! is<ISA_LIT>LowRegister ( DestReg ) || ( BaseReg != <NUM_LIT> && ! is<ISA_LIT>LowRegister ( BaseReg ) ) ; bool isSub = false ; if ( NumBytes < <NUM_LIT> && ! isHigh && CanChangeCC ) { isSub = true ; NumBytes = - NumBytes ; } unsigned LdReg = DestReg ; if ( DestReg == <STR_LIT> ) assert ( BaseReg == <STR_LIT> && <STR_LIT> ) ; if ( ! is<ISA_LIT>LowRegister ( DestReg ) && ! MRI . isVirtualRegister ( DestReg ) ) LdReg = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; if ( NumBytes <= <NUM_LIT> && NumBytes >= <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else if ( NumBytes < <NUM_LIT> && NumBytes >= - <NUM_LIT> && CanChangeCC ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . add ( t1CondCodeOp ( ) ) . addReg ( LdReg , RegState :: Kill ) . setMIFlags ( MIFlags ) ; } else if ( ST . genExecuteOnly ( ) ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , LdReg ) . addImm ( NumBytes ) . setMIFlags ( MIFlags ) ; } else MRI . emitLoadConstPool ( MBB , MBBI , dl , LdReg , <NUM_LIT> , NumBytes , <STR_LIT> , <NUM_LIT> , MIFlags ) ; int Opc = ( isSub ) ? <STR_LIT> : ( ( isHigh || ! CanChangeCC ) ? <STR_LIT> : <STR_LIT> ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , dl , TII . get ( Opc ) , DestReg ) ; if ( Opc != <STR_LIT> ) MIB = MIB . add ( t1CondCodeOp ( ) ) ; if ( DestReg == <STR_LIT> || isSub ) MIB . addReg ( BaseReg ) . addReg ( LdReg , RegState :: Kill ) ; else MIB . addReg ( LdReg ) . addReg ( BaseReg , RegState :: Kill ) ; MIB . add ( predOps ( <STR_LIT> ) ) ;


<s> unsigned VecRegBitWidth = VF * LoadSize ; if ( VecRegBitWidth > <NUM_LIT> && VecTy -> getScalarSizeInBits ( ) < <NUM_LIT> ) return <NUM_LIT> / LoadSize ; return VF ;


<s> aarch64_crc_builtin_datum * d = & aarch64_crc_builtin_data [ i ] ; tree argtype = aarch64_simd_builtin_std_type ( d -> mode , qualifier_unsigned ) ; tree ftype = build_function_type_list ( usi_type , usi_type , argtype , NULL_TREE ) ; tree attrs = aarch64_get_attributes ( FLAG_NONE , d -> mode ) ; tree fndecl = aarch64_general_add_builtin ( d -> name , ftype , d -> fcode , attrs ) ; aarch64_builtin_decls [ d -> fcode ] = fndecl ;


<s> Base = CurDAG -> getTargetFrameIndex ( FI , TLI -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; } else if ( N . getOpcode ( ) == <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) { Base = N . getOperand ( <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( <STR_LIT> ( <STR_LIT> , <NUM_LIT> ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } int RHSC ; if ( isScaledConstantInRange ( N . getOperand ( <NUM_LIT> ) , <NUM_LIT> , - <NUM_LIT> + <NUM_LIT> , <NUM_LIT> , RHSC ) ) { Base = N . getOperand ( <NUM_LIT> ) ; if ( Base . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( Base ) -> getIndex ( ) ;


<s> rtx part = XVECEXP ( pattern , <NUM_LIT> , i ) ; if ( GET_CODE ( part ) == USE && GET_MODE ( XEXP ( part , <NUM_LIT> ) ) == Pmode && GENERAL_REGISTER_P ( true_regnum ( XEXP ( part , <NUM_LIT> ) ) ) ) return XEXP ( part , <NUM_LIT> ) ;


<s> emit_insn ( gen_addxf3 ( e1 , e1 , e2 ) ) ; ix86_emit_i387_log1p ( e2 , e1 ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ;


<s> PrintDebugValueComment ( MI , OS ) ; return ; } if ( InConstantPool && MI -> getOpcode ( ) != <STR_LIT> ) { OutStreamer . EmitDataRegion ( MCDR_DataRegionEnd ) ; InConstantPool = false ; } if ( MI -> getOpcode ( ) == <STR_LIT> ) { unsigned LabelId = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CPIdx = ( unsigned ) MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; if ( ! InConstantPool ) { OutStreamer . EmitDataRegion ( MCDR_DataRegion ) ; InConstantPool = true ; }

OutStreamer . EmitLabel ( GetCPISymbol ( LabelId ) ) ;


<s> void <ISA_LIT>InstrInfo :: copyPhysReg ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned DestReg , unsigned SrcReg , bool KillSrc ) const { BuildMI ( MBB , I , I -> getDebugLoc ( ) , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; unsigned Op = <NUM_LIT> ; unsigned VR = <NUM_LIT> ; Reloc :: Model RM = MF -> getTarget ( ) . getRelocationModel ( ) ; bool UseImmLabel = ( MF -> getTarget ( ) . getCodeModel ( ) == CodeModel :: Small ) && ( RM == Reloc :: Static || RM == Reloc :: DynamicNoPIC ) ; if ( UseImmLabel ) { Op = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; } else { const TargetRegisterClass * TRC = ( PVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; VR = MRI -> createVirtualRegister ( TRC ) ; Op = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( Subtarget . is64Bit ( ) ) BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( DispatchBB ) . addReg ( <NUM_LIT> ) ; else BuildMI ( * MBB , MI , DL , TII -> get ( <STR_LIT> ) , VR ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( DispatchBB , Subtarget . classifyBlockAddressReference ( ) ) . addReg ( <NUM_LIT> ) ; } MachineInstrBuilder MIB = BuildMI ( * MBB , MI , DL , TII -> get ( Op ) ) ; addFrameReference ( MIB , FI , <NUM_LIT> ) ;

if ( UseImmLabel ) MIB . addMBB ( DispatchBB ) ;


<s> <ISA_LIT>ompactTargetMachine :: <ISA_LIT>ompactTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , Subtarget ( TT , CPU , FS ) , DataLayout ( Subtarget . getDataLayout ( ) ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) {


<s> DownBlk = TrueMBB ; DEBUG ( dbgs ( ) << <STR_LIT> << HeadMBB -> getNumber ( ) << <STR_LIT> << TrueMBB -> getNumber ( ) << <STR_LIT> << TrueMBB -> succ_size ( ) << <STR_LIT> << FalseMBB -> getNumber ( ) << <STR_LIT> ; ) ; while ( DownBlk ) { DEBUG ( dbgs ( ) << <STR_LIT> << DownBlk -> getNumber ( ) ; ) ; if ( singlePathTo ( FalseMBB , DownBlk ) == SinglePath_InPath ) { DEBUG ( dbgs ( ) << <STR_LIT> ; ) ; Num += cloneOnSideEntryTo ( HeadMBB , TrueMBB , DownBlk ) ; Num += cloneOnSideEntryTo ( HeadMBB , FalseMBB , DownBlk ) ; numClonedBlock += Num ; Num += serialPatternMatch ( * HeadMBB -> succ_begin ( ) ) ; Num += serialPatternMatch ( * std :: next ( HeadMBB -> succ_begin ( ) ) ) ; Num += ifPatternMatch ( HeadMBB ) ; assert ( Num > <NUM_LIT> ) ; break ; }


<s> unsigned <ISA_LIT>InstrInfo :: getNumFlatOffsetBits ( bool Signed ) const { if ( ST . getGeneration ( ) >= <ISA_LIT>Subtarget :: GFX10 ) return Signed ? <NUM_LIT> : <NUM_LIT> ; return Signed ? <NUM_LIT> : <NUM_LIT> ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const uint64_t StackSize = MFI . getStackSize ( ) ; if ( MFI . isFixedObjectIndex ( FI ) && TRI -> needsStackRealignment ( MF ) && ! STI . isTargetWin64 ( ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ; const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ;

if ( ! IgnoreSPUpdates && ! TFI -> hasReservedCallFrame ( MF ) ) return getFrameIndexReference ( MF , FI , FrameReg ) ;


<s> rtx scratch2 = gen_rtx_REG ( Pmode , RV_REGNUM ) ; emit_move_insn ( scratch2 , GEN_INT ( hi ) ) ; emit_insn ( gen_add2_insn ( scratch , scratch2 ) ) ; } tmp = plus_constant ( Pmode , scratch , lo ) ; tmp = gen_rtx_MEM ( Pmode , tmp ) ; emit_move_insn ( scratch , tmp ) ; emit_insn ( gen_add2_insn ( this_rtx , scratch ) ) ; } if ( ! TREE_USED ( function ) ) { assemble_external ( function ) ; TREE_USED ( function ) = <NUM_LIT> ; } funexp = XEXP ( DECL_RTL ( function ) , <NUM_LIT> ) ; gcc_assert ( SYMBOL_REF_LOCAL_P ( funexp ) ) ; funexp = gen_rtx_MEM ( FUNCTION_MODE , funexp ) ; insn = emit_call_insn ( gen_sibcall ( funexp , const0_rtx ) ) ; SIBLING_CALL_P ( insn ) = <NUM_LIT> ; emit_barrier ( ) ; insn = get_insns ( ) ; shorten_branches ( insn ) ; assemble_start_function ( thunk_fndecl , fnname ) ; final_start_function ( insn , file , <NUM_LIT> ) ;


<s> <ISA_LIT>MCCodeEmitter ( MCContext & ctx , MCInstrInfo const & MCII ) : Ctx ( ctx ) , MCII ( MCII ) {


<s> void mep_final_prescan_insn ( rtx_insn * insn , rtx * operands ATTRIBUTE_UNUSED , int noperands ATTRIBUTE_UNUSED ) {

if ( GET_MODE ( insn ) == BImode && get_attr_slots ( insn ) != SLOTS_CORE ) fputc ( '+' , asm_out_file ) ;


<s> case EXCESS_PRECISION_TYPE_STANDARD : case EXCESS_PRECISION_TYPE_IMPLICIT : if ( ! TARGET_80387 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; else if ( ! TARGET_MIX_SSE_I387 ) { if ( ! TARGET_SSE_MATH ) return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE ; else if ( TARGET_SSE2 ) return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT ; } return ( type == EXCESS_PRECISION_TYPE_STANDARD ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT : FLT_EVAL_METHOD_UNPREDICTABLE ) ; default : gcc_unreachable ( ) ; } return FLT_EVAL_METHOD_UNPREDICTABLE ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { unsigned Opc = Align < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; BuildMI ( MBB , I , DL , get ( Opc ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , KillFlag ) . addMemOperand ( MMO ) ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note_rtx ) ; offset = callee_save_size - UNITS_PER_WORD ; } else { rtx tmp_reg = gen_rtx_REG ( Pmode , A9_REG ) ; emit_move_insn ( tmp_reg , GEN_INT ( total_size ) ) ; insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp_reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; note_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , - total_size ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note_rtx ) ; offset = total_size - UNITS_PER_WORD ; } } for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; ++ regno ) { if ( xtensa_call_save_reg ( regno ) ) { rtx x = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( offset ) ) ; rtx mem = gen_frame_mem ( SImode , x ) ; rtx reg = gen_rtx_REG ( SImode , regno ) ; offset -= UNITS_PER_WORD ; insn = emit_move_insn ( mem , reg ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , gen_rtx_SET ( mem , reg ) ) ; } } if ( total_size > <NUM_LIT> || ( ! callee_save_size && total_size > <NUM_LIT> ) ) { rtx tmp_reg = gen_rtx_REG ( Pmode , A9_REG ) ; emit_move_insn ( tmp_reg , GEN_INT ( total_size - callee_save_size ) ) ; insn = emit_insn ( gen_subsi3 ( stack_pointer_rtx , stack_pointer_rtx , tmp_reg ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; note_rtx = gen_rtx_SET ( stack_pointer_rtx , plus_constant ( Pmode , stack_pointer_rtx , callee_save_size - total_size ) ) ; add_reg_note ( insn , REG_FRAME_RELATED_EXPR , note_rtx ) ; } } if ( frame_pointer_needed ) { if ( cfun -> machine -> set_frame_ptr_insn ) { rtx_insn * first ; push_topmost_sequence ( ) ; first = get_insns ( ) ; pop_topmost_sequence ( ) ; for ( insn = first ; insn != cfun -> machine -> set_frame_ptr_insn ; insn = NEXT_INSN ( insn ) ) { if ( INSN_P ( insn ) ) {

PATTERN ( insn ) = replace_rtx ( copy_rtx ( PATTERN ( insn ) ) , hard_frame_pointer_rtx , stack_pointer_rtx ) ;


<s> __o = __builtin_aarch64_set_qregoiv2di_ssps ( __o , ( poly64x2_t ) val . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> State = IES_GT ; IC . pushOperator ( IC_GT ) ; break ; }


<s> unsigned Idx = ConstantPool -> getConstantPoolIndex ( C , <NUM_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( DestReg , getDefRegState ( true ) , SubIdx ) . addConstantPoolIndex ( Idx ) . addImm ( ( int64_t ) <STR_LIT> ) . addReg ( <NUM_LIT> ) . setMIFlags ( MIFlags ) ;


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned WaveSize = ST . getWavefrontSize ( ) ; unsigned Size = FrameInfo . getObjectSize ( FI ) ; unsigned NumLanes = Size / <NUM_LIT> ; if ( NumLanes > WaveSize ) return false ; assert ( Size >= <NUM_LIT> && <STR_LIT> ) ; assert ( TRI -> spillSGPRToVGPR ( ) && <STR_LIT> ) ; for ( unsigned I = <NUM_LIT> ; I < NumLanes ; ++ I , ++ NumVGPRSpillLanes ) { Register LaneVGPR ; unsigned VGPRIndex = ( NumVGPRSpillLanes % WaveSize ) ; if ( VGPRIndex == <NUM_LIT> ) { LaneVGPR = TRI -> findUnusedRegister ( MRI , & <STR_LIT> , MF ) ;


<s> sinkMBB -> splice ( sinkMBB -> begin ( ) , BB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , BB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( BB ) ; BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , DL , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ;

BuildMI ( BB , DL , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ;


<s> if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . readsRegister ( <STR_LIT> ) ) UsedVL = true ; if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . readsRegister ( <STR_LIT> ) ) UsedVTYPE = true ; if ( ! isVectorConfigInstr ( MI ) ) continue ; if ( PrevMI ) { if ( ! UsedVL && ! UsedVTYPE ) { ToDelete . push_back ( PrevMI ) ; } else if ( ! UsedVTYPE && isVLPreservingConfig ( MI ) ) { PrevMI -> getOperand ( <NUM_LIT> ) . setImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; ToDelete . push_back ( & MI ) ; continue ; } } PrevMI = & MI ; UsedVL = false ; UsedVTYPE = false ; Register VRegDef = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

if ( VRegDef != <STR_LIT> && ! ( VRegDef . isVirtual ( ) && MRI -> use_nodbg_empty ( VRegDef ) ) ) UsedVL = true ;


<s> static bool tilepro_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) {


<s> static bool contains ( const T & container , const U & contained ) { return container . count ( contained ) ;


<s> eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>InstrInfo & TII = * static_cast < const <ISA_LIT>InstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { MachineInstr * Old = I ; uint64_t Amount = Old -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { unsigned Align = getStackAlignment ( ) ; Amount = ( Amount + Align - <NUM_LIT> ) / Align * Align ; assert ( Amount % <NUM_LIT> == <NUM_LIT> ) ; Amount /= <NUM_LIT> ;


<s> __inline__ static unsigned long long sh_media_MSHLLD_W ( unsigned long long mm , unsigned int mn ) { unsigned long long res ; __asm__ ( <STR_LIT> : <STR_LIT> ( res ) : <STR_LIT> ( mm ) , <STR_LIT> ( mn ) ) ; return res ;


<s> } return Offset ; } if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) { if ( isFixed || ( hasMovingSP && ! RegInfo -> hasBasePointer ( MF ) ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } else if ( hasMovingSP ) { assert ( RegInfo -> hasBasePointer ( MF ) && <STR_LIT> ) ; if ( AFI -> isThumb2Function ( ) ) { if ( FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } } else if ( AFI -> isThumbFunction ( ) ) { if ( Offset >= <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> && Offset <= <NUM_LIT> ) return Offset ; if ( AFI -> isThumb2Function ( ) && FPOffset >= - <NUM_LIT> && FPOffset < <NUM_LIT> ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } else if ( Offset > ( FPOffset < <NUM_LIT> ? - FPOffset : FPOffset ) ) { FrameReg = RegInfo -> getFrameRegister ( MF ) ; return FPOffset ; } } if ( RegInfo -> hasBasePointer ( MF ) ) {

FrameReg = RegInfo -> getBaseRegister ( ) ;


<s> case <STR_LIT> : { unsigned PredReg = <NUM_LIT> ; <STR_LIT> CC = getInstrPredicate ( MI , PredReg ) ; if ( CC == <STR_LIT> || PredReg != <STR_LIT> ) return nullptr ; MI = TargetInstrInfo :: commuteInstruction ( MI , NewMI ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { return CSR_PCS_SaveList ;


<s> if ( I -> getType ( ) != CI -> getOperand ( <NUM_LIT> ) -> getType ( ) || ! ( ( Subtarget -> hasSSE1 ( ) && RetVT == <STR_LIT> ) || ( Subtarget -> hasSSE2 ( ) && RetVT == <STR_LIT> ) ) ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; CmpInst :: Predicate Predicate = optimizeCmpPredicate ( CI ) ; if ( Predicate == CmpInst :: FCMP_ORD || Predicate == CmpInst :: FCMP_UNO ) { const auto * CmpRHSC = dyn_cast < ConstantFP > ( CmpRHS ) ; if ( CmpRHSC && CmpRHSC -> isNullValue ( ) ) CmpRHS = CmpLHS ; } unsigned CC ; bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>SSEConditionCode ( Predicate ) ; if ( CC > <NUM_LIT> ) return false ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; static unsigned OpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] [ <NUM_LIT> ] = { { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } , { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; bool HasAVX = Subtarget -> hasAVX ( ) ; unsigned * Opc = nullptr ; switch ( RetVT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ HasAVX ] [ <NUM_LIT> ] ; break ; case <STR_LIT> : Opc = & OpcTable [ <NUM_LIT> ] [ HasAVX ] [ <NUM_LIT> ] ; break ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ; const Value * RHS = I -> getOperand ( <NUM_LIT> ) ; unsigned LHSReg = getRegForValue ( LHS ) ; bool LHSIsKill = hasTrivialKill ( LHS ) ; unsigned RHSReg = getRegForValue ( RHS ) ; bool RHSIsKill = hasTrivialKill ( RHS ) ; unsigned CmpLHSReg = getRegForValue ( CmpLHS ) ; bool CmpLHSIsKill = hasTrivialKill ( CmpLHS ) ; unsigned CmpRHSReg = getRegForValue ( CmpRHS ) ;

bool CmpRHSIsKill = hasTrivialKill ( CmpRHS ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , CodeModel :: Model CM , CodeGenOpt :: Level OL , bool LittleEndian ) : LLVMTargetMachine ( T , computeDataLayout ( TT , LittleEndian ) , TT , CPU , FS , Options , getEffectiveRelocModel ( TT , RM ) , CM , OL ) , TLOF ( createTLOF ( getTargetTriple ( ) ) ) , Subtarget ( TT , CPU , FS , * this , LittleEndian ) { initReciprocals ( * this , Subtarget ) ; initAsmInfo ( ) ;


<s> return __builtin_aarch64_reduc_smin_scal_v2si ( __a ) ;


<s> case TLS_LDO32 : fputs ( <STR_LIT> , fp ) ; break ; case TLS_IE32 : fputs ( <STR_LIT> , fp ) ; break ; case TLS_LE32 : fputs ( <STR_LIT> , fp ) ; break ; default : gcc_unreachable ( ) ; } switch ( reloc ) { case TLS_GD32 : case TLS_LDM32 : case TLS_IE32 : fputs ( <STR_LIT> , fp ) ; output_addr_const ( fp , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; fputs ( <STR_LIT> , fp ) ; output_addr_const ( fp , XVECEXP ( x , <NUM_LIT> , <NUM_LIT> ) ) ; fputc ( ')' , fp ) ; break ;


<s> const <ISA_LIT>InstrInfo * <ISA_LIT>InstrInfo :: create ( <ISA_LIT>Subtarget & STI ) { return new <ISA_LIT>InstrInfo ( STI ) ;


<s> void <ISA_LIT>_CCState :: HandleByVal ( unsigned ValNo , EVT ValVT , EVT LocVT , CCValAssign :: LocInfo LocInfo , int MinSize , int MinAlign , <STR_LIT> ArgFlags ) {

unsigned Align = ArgFlags . getByValAlign ( ) ;


<s> const GlobalObject * GO = GV -> getBaseObject ( ) ; if ( GO && TLOF -> IsGlobalInSmallSection ( GO , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN64 ( ) ) ; return Subtarget . hasSym32 ( ) ? getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) : getAddrNonPICSym64 ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasLocalLinkage ( ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) , GV -> isThreadLocal ( ) ) ; if ( Subtarget . useXGOT ( ) || HugeGOT ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , GV -> isThreadLocal ( ) ) ;

return getAddrGlobal ( N , SDLoc ( N ) , Ty , DAG , ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ? <STR_LIT> : <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) , GV -> isThreadLocal ( ) ) ;


<s> assert ( XLenVT == N . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) && <STR_LIT> ) ; auto EltVT = N . getValueType ( ) . getVectorElementType ( ) ; if ( EltVT . bitsLT ( XLenVT ) ) { SplatImm = SignExtend64 ( SplatImm , EltVT . getSizeInBits ( ) ) ; } if ( ! isInt < <NUM_LIT> > ( SplatImm ) ) return false ;

SplatVal = CurDAG -> getTargetConstant ( SplatImm , SDLoc ( N ) , XLenVT ) ;


<s> vst1_f64 ( float64_t * a , float64x1_t b ) { * a = b [ <NUM_LIT> ] ;


<s> static __inline qword si_cgthi ( qword a , signed short b ) { return ( ( qword ) ( vec_cmpgt ( ( vec_short8 ) ( a ) , vec_splat ( ( vec_short8 ) ( si_from_short ( b ) ) , <NUM_LIT> ) ) ) ) ;


<s> if ( MV66 ) return <STR_LIT> ; if ( MV67 ) return <STR_LIT> ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; assert ( Subtarget -> isTargetWindows ( ) && <STR_LIT> ) ; assert ( Subtarget -> isThumb2 ( ) && <STR_LIT> ) ; switch ( TM . getCodeModel ( ) ) { case CodeModel :: Small : case CodeModel :: Medium : case CodeModel :: Default : case CodeModel :: Kernel : BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) ) . add ( predOps ( <STR_LIT> ) ) . addExternalSymbol ( <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Define | RegState :: Dead ) ; break ; case CodeModel :: Large : case CodeModel :: JITDefault : { MachineRegisterInfo & MRI = MBB -> getParent ( ) -> getRegInfo ( ) ; unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ;

BuildMI ( * MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) . addExternalSymbol ( <STR_LIT> ) ;


<s> if ( Name . find ( <STR_LIT> ) != std :: string :: npos ) { if ( Name . endswith ( <STR_LIT> ) || Name . endswith ( <STR_LIT> ) ) DblSpaced = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ; if ( Name . endswith ( <STR_LIT> ) || Name . endswith ( <STR_LIT> ) ) DblSpaced = slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ;


<s> State . addLoc ( CCValAssign :: getMem ( VA1 . getValNo ( ) , VA1 . getValVT ( ) , State . AllocateStack ( XLenInBytes , StackAlign ) , VA1 . getLocVT ( ) , CCValAssign :: Full ) ) ; State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , Align ( XLenInBytes ) ) , LocVT2 , CCValAssign :: Full ) ) ; return false ; } if ( Register Reg = State . AllocateReg ( ArgGPRs ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo2 , ValVT2 , Reg , LocVT2 , CCValAssign :: Full ) ) ; } else { State . addLoc ( CCValAssign :: getMem ( ValNo2 , ValVT2 , State . AllocateStack ( XLenInBytes , Align ( XLenInBytes ) ) , LocVT2 , CCValAssign :: Full ) ) ;


<s> if ( ! AlwaysInline && ( Align & <NUM_LIT> ) == <NUM_LIT> && DAG . MaskedValueIsZero ( Size , APInt ( SizeBitWidth , <NUM_LIT> ) ) ) { const TargetLowering & TLI = * DAG . getSubtarget ( ) . getTargetLowering ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ;

CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) ) . setDiscardResult ( ) ;


<s> else if ( n_ready > <NUM_LIT> ) return <NUM_LIT> ; } if ( ia64_final_schedule ) { int deleted = <NUM_LIT> ; int nr_need_stop = <NUM_LIT> ; for ( insnp = ready ; insnp < e_ready ; insnp ++ ) if ( safe_group_barrier_needed ( * insnp ) ) nr_need_stop ++ ; if ( reorder_type == <NUM_LIT> && n_ready == nr_need_stop ) return <NUM_LIT> ; if ( reorder_type == <NUM_LIT> ) return <NUM_LIT> ; insnp = e_ready ; while ( insnp -- > ready + deleted ) while ( insnp >= ready + deleted ) { rtx_insn * insn = * insnp ; if ( ! safe_group_barrier_needed ( insn ) ) break ; memmove ( ready + <NUM_LIT> , ready , ( insnp - ready ) * sizeof ( rtx ) ) ; * ready = insn ; deleted ++ ; } n_ready -= deleted ; ready += deleted ; } current_cycle = clock_var ; if ( reload_completed && mem_ops_in_group [ clock_var % <NUM_LIT> ] >= ia64_max_memory_insns ) { int moved = <NUM_LIT> ; insnp = e_ready ; while ( insnp -- > ready + moved ) while ( insnp >= ready + moved ) { rtx_insn * insn = * insnp ; if ( ! is_load_p ( insn ) ) break ; memmove ( ready + <NUM_LIT> , ready , ( insnp - ready ) * sizeof ( rtx ) ) ; * ready = insn ; moved ++ ; } n_ready -= moved ; ready += moved ;


<s> const MCBinaryExpr * BinaryExpr = dyn_cast < MCBinaryExpr > ( getImm ( ) ) ; assert ( isa < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) && cast < <ISA_LIT>MCExpr > ( BinaryExpr -> getLHS ( ) ) -> getKind ( ) == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ABS_LO ) ; Inst . addOperand ( MCOperand :: createExpr ( getImm ( ) ) ) ; } else assert ( false && <STR_LIT> ) ;


<s> case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineVTRUNC ( N , DAG ) ; case <STR_LIT> : return combineAndnp ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combine<ISA_LIT>INT_TO_FP ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineCVTP2I_CVTTP2I ( N , DAG , DCI ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineExtInVec ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorPack ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftVar ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineVectorShiftImm ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorInsert ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineShuffle ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return combineFMA ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> :


<s> SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; return Result ; } else if ( Subtarget -> isRWPI ( ) && ! IsRO ) { SDValue RelAddr ; if ( Subtarget -> useMovt ( DAG . getMachineFunction ( ) ) ) { ++ NumMovwMovt ; SDValue G = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , <STR_LIT> ) ; RelAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , G ) ; } else { <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( GV , <STR_LIT> ) ; SDValue CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;

RelAddr = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , MachinePointerInfo :: getConstantPool ( DAG . getMachineFunction ( ) ) ) ;


<s> return MachineJumpTableInfo :: EK_BlockAddress ;


<s> unsigned PReg = PMO . getReg ( ) ; unsigned PRegNum = PMO . isUndef ( ) ? UINT_MAX : get<ISA_LIT>RegisterNumbering ( PReg ) ; unsigned Count = <NUM_LIT> ; for ( unsigned i = SIndex + <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { int NewOffset = MemOps [ i ] . Offset ; const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : get<ISA_LIT>RegisterNumbering ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isNotVFP && RegNum > PRegNum ) || ( ( Size < <NUM_LIT> || Count < <NUM_LIT> ) && RegNum == PRegNum + <NUM_LIT> ) ) ) { Offset += Size ; PRegNum = RegNum ; ++ Count ; } else { MergeOpsUpdate ( MBB , MemOps , SIndex , i , insertAfter , SOffset , Base , false , Opcode , Pred , PredReg , Scratch , dl , Merges ) ; MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch , MemOps , Merges ) ; return ; } if ( MemOps [ i ] . Position > MemOps [ insertAfter ] . Position ) insertAfter = i ;


<s> OS << <STR_LIT> << Name << <STR_LIT> << Name << '\n' ;


<s> switch ( Opcode ) { case <STR_LIT> : { SDValue imm = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) ; unsigned Opc = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; EVT VT = Subtarget . isRV64 ( ) ? <STR_LIT> : <STR_LIT> ; if ( Node -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI , imm ) ; return CurDAG -> getMachineNode ( Opc , DL , VT , TFI , imm ) ; } } SDNode * ResNode = SelectCode ( Node ) ; DEBUG ( errs ( ) << <STR_LIT> ; if ( ResNode == NULL || ResNode == Node ) Node -> dump ( CurDAG ) ; else ResNode -> dump ( CurDAG ) ;


<s> } reg = MO . getReg ( ) ; if ( reg == AMDGPU :: VCC ) { VCCUsed = true ; continue ; } switch ( reg ) { default : break ; case AMDGPU :: EXEC : case AMDGPU :: M0 : continue ; } if ( AMDGPU :: SReg_32RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_32RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: SReg_64RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_64RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_96RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: SReg_128RegClass . contains ( reg ) ) { isSGPR = true ; width = <NUM_LIT> ; } else if ( AMDGPU :: VReg_128RegClass . contains ( reg ) ) { isSGPR = false ; width = <NUM_LIT> ; } else if ( AMDGPU :: SReg_256RegClass . contains ( reg ) ) { isSGPR = true ;


<s> for ( unsigned i = <NUM_LIT> ; i < sizeof ( Bops ) / sizeof ( Bops [ <NUM_LIT> ] ) ; ++ i ) if ( MI -> getOpcode ( ) == Bops [ i ] ) { BI = MI ; ++ insInBops ; } } } if ( insInBops != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << insInBops << <STR_LIT> ) ; return nullptr ; }


<s> return ( EncVal << <NUM_LIT> ) | ( EncVal << <NUM_LIT> ) ;


<s> auto & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; if ( ! isSupportedType ( DL , TLI , Val -> getType ( ) ) ) return false ; SmallVector < ArgInfo , <NUM_LIT> > SplitVTs ; SmallVector < unsigned , <NUM_LIT> > Regs ; ArgInfo RetInfo ( VReg , Val -> getType ( ) ) ; setArgFlags ( RetInfo , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( RetInfo , SplitVTs , MF , [ & ] ( unsigned Reg , uint64_t Offset ) { Regs . push_back ( Reg ) ; } ) ; if ( Regs . size ( ) > <NUM_LIT> ) MIRBuilder . buildUnmerge ( Regs , VReg ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) , F . isVarArg ( ) ) ; OutgoingValueHandler RetHandler ( MIRBuilder , MF . getRegInfo ( ) , Ret , AssignFn ) ;

return handleAssignments ( MIRBuilder , SplitVTs , RetHandler ) ;


<s> unsigned LogAlign = Log2_32 ( Align ) ; MachineBasicBlock :: iterator InsAt = InsPoint [ LogAlign ] ; MachineInstr * CPEMI = BuildMI ( * BB , InsAt , DebugLoc ( ) , TII -> get ( <STR_LIT> ) ) . addImm ( i ) . addConstantPoolIndex ( i ) . addImm ( Size ) ; CPEMIs . push_back ( CPEMI ) ; for ( unsigned a = LogAlign + <NUM_LIT> ; a <= MaxLogAlign ; ++ a ) if ( InsPoint [ a ] == InsAt ) InsPoint [ a ] = CPEMI ; CPEntries . emplace_back ( <NUM_LIT> , CPEntry ( CPEMI , i ) ) ; ++ NumCPEs ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << i << <STR_LIT> << Size << <STR_LIT> << Align << '\n' ) ; } LLVM_DEBUG ( BB -> dump ( ) ) ;


<s> tree arm_builtin_vectorized_function ( unsigned int fn , tree type_out , tree type_in ) { machine_mode in_mode , out_mode ; int in_n , out_n ; bool out_unsigned_p = TYPE_UNSIGNED ( type_out ) ; if ( ! TARGET_NEON ) return NULL_TREE ; if ( TREE_CODE ( type_out ) != VECTOR_TYPE || TREE_CODE ( type_in ) != VECTOR_TYPE ) return NULL_TREE ; out_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; out_n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; ( TARGET_FPU_ARMV8 \ && flag_unsafe_math_optimizations \ && ARM_CHECK_BUILTIN_MODE_1 ( C ) ) ( out_mode == SFmode && out_n == C \ && in_mode == SFmode && in_n == C ) ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> ) \ ? arm_builtin_decl ( ARM_BUILTIN_NEON_ ## N ## v2sf , false ) \ : ( ARM_CHECK_BUILTIN_MODE ( <NUM_LIT> ) \ ? arm_builtin_decl ( ARM_BUILTIN_NEON_ ## N ## v4sf , false ) \ : NULL_TREE ) ) switch ( fn ) { CASE_CFN_FLOOR : return ARM_FIND_VRINT_VARIANT ( vrintm ) ;


<s> } else { ResultReg = createResultReg ( & <STR_LIT> ) ; LdrOpc = <STR_LIT> ; } BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( LdrOpc ) , ResultReg ) . addReg ( ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> | <STR_LIT> | OpFlags ) ; if ( ! Subtarget -> isTargetILP32 ( ) ) return ResultReg ; unsigned Result64 = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: SUBREG_TO_REG ) ) . addDef ( Result64 ) . addImm ( <NUM_LIT> ) . addReg ( ResultReg , RegState :: Kill ) . addImm ( <STR_LIT> ) ; return Result64 ; } else { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | OpFlags ) ; ResultReg = createResultReg ( & <STR_LIT> ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( ADRPReg ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> | <STR_LIT> | OpFlags ) . addImm ( <NUM_LIT> ) ;


<s> return __builtin_neon_vmaxfv4hf ( __a , __b ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CC , false , * FuncInfo . MF , TM , RVLocs , * Context ) ; CCInfo . AnalyzeCallResult ( RetVT , CCAssignFnForCall ( CC , true ) ) ; if ( RVLocs . size ( ) == <NUM_LIT> && RetVT == <STR_LIT> ) { EVT DestVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; TargetRegisterClass * DstRC = TLI . getRegClassFor ( DestVT ) ; unsigned ResultReg = createResultReg ( DstRC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; } else { assert ( RVLocs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; EVT CopyVT = RVLocs [ <NUM_LIT> ] . getValVT ( ) ; if ( RetVT == <STR_LIT> || RetVT == <STR_LIT> || RetVT == <STR_LIT> ) CopyVT = <STR_LIT> ; TargetRegisterClass * DstRC = TLI . getRegClassFor ( CopyVT ) ; unsigned ResultReg = createResultReg ( DstRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UsedRegs . push_back ( RVLocs [ <NUM_LIT> ] . getLocReg ( ) ) ; UpdateValueMap ( I , ResultReg ) ; } }


<s> static inline bool isValidCoprocessorNumber ( unsigned Num , const FeatureBitset & featureBits ) {

if ( featureBits [ <STR_LIT> ] && ( Num & <NUM_LIT> ) != <NUM_LIT> ) return false ;


<s> for ( i = <NUM_LIT> ; i != NumElts ; ++ i ) { Val = SVOp -> getMaskElt ( i ) ; if ( Val >= <NUM_LIT> ) break ; }

if ( Val >= ( int ) NumElts ) Val -= NumElts - NumLaneElts ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> bool <ISA_LIT>FastISel :: <ISA_LIT>SelectLoad ( const Instruction * I ) { if ( cast < LoadInst > ( I ) -> isAtomic ( ) ) return false ; MVT VT ; if ( ! isTypeLegal ( I -> getType ( ) , VT , true ) ) return false ; <ISA_LIT>AddressMode AM ;

if ( ! <ISA_LIT>SelectAddress ( I -> getOperand ( <NUM_LIT> ) , AM ) ) return false ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> case ROUND_MOD_EXPR : case EXACT_DIV_EXPR : stmt_cost = ix86_division_cost ( ix86_cost , mode ) ; break ; case RSHIFT_EXPR : case LSHIFT_EXPR : case LROTATE_EXPR : case RROTATE_EXPR : { tree op2 = gimple_assign_rhs2 ( stmt_info -> stmt ) ; stmt_cost = ix86_shift_rotate_cost ( ix86_cost , mode , TREE_CODE ( op2 ) == INTEGER_CST , cst_and_fits_in_hwi ( op2 ) ? int_cst_value ( op2 ) : - <NUM_LIT> , true , false , false , NULL , NULL ) ; } break ; case NOP_EXPR : if ( tree_nop_conversion_p ( TREE_TYPE ( gimple_assign_lhs ( stmt_info -> stmt ) ) , TREE_TYPE ( gimple_assign_rhs1 ( stmt_info -> stmt ) ) ) ) stmt_cost = <NUM_LIT> ; break ; case BIT_IOR_EXPR : case ABS_EXPR : case MIN_EXPR : case MAX_EXPR : case BIT_XOR_EXPR : case BIT_AND_EXPR : case BIT_NOT_EXPR : if ( SSE_FLOAT_MODE_P ( mode ) && TARGET_SSE_MATH ) stmt_cost = ix86_cost -> sse_op ; else if ( VECTOR_MODE_P ( mode ) ) stmt_cost = ix86_vec_cost ( mode , ix86_cost -> sse_op , true ) ; else stmt_cost = ix86_cost -> add ; break ; default : break ; } } if ( kind == vec_construct && stmt_info && STMT_VINFO_TYPE ( stmt_info ) == load_vec_info_type && STMT_VINFO_MEMORY_ACCESS_TYPE ( stmt_info ) == VMAT_ELEMENTWISE && TREE_CODE ( DR_STEP ( STMT_VINFO_DATA_REF ( stmt_info ) ) ) != INTEGER_CST ) {

stmt_cost = ix86_builtin_vectorization_cost ( kind , vectype , misalign ) ;


<s> unsigned getMaxWavesPerCU ( ) const { if ( getGeneration ( ) >= <ISA_LIT>Subtarget :: SOUTHERN_ISLANDS ) return <NUM_LIT> ;


<s> int Src1ModIdx = <STR_LIT> ( Opc , <STR_LIT> :: src1_modifiers ) ; int Src2ModIdx = <STR_LIT> ( Opc , <STR_LIT> :: src2_modifiers ) ; MI . removeOperand ( Src2ModIdx ) ; MI . removeOperand ( Src1ModIdx ) ; MI . removeOperand ( Src0ModIdx ) ;


<s> return D ( <STR_LIT> , R ( a ) , R ( b ) ) ;


<s> for ( uint64_t i = <NUM_LIT> ; i != depth ; ++ i ) { SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , FrameAddr , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; FrameAddr = DAG . getLoad ( <STR_LIT> , dl , Chain , Ptr , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ;


<s> MachineBasicBlock * CatchRetTarget = CatchRet -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( STI . is64Bit ( ) ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( <NUM_LIT> ) . addMBB ( CatchRetTarget ) . addReg ( <NUM_LIT> ) ; } else { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addMBB ( CatchRetTarget ) ; } CatchRetTarget -> setHasAddressTaken ( ) ;


<s> SwitchToEHSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_ALLOC , SectionKind :: getDataRel ( ) , FnStart ) ;


<s> return gen_int_mode ( type , Pmode ) ;


<s> virtual const <ISA_LIT>InstrInfo * getInstrInfo ( ) const { return & InstrInfo ;


<s> if ( isSMRD ( * FirstLdSt ) && isSMRD ( * SecondLdSt ) ) return true ;

return ( isMUBUF ( * FirstLdSt ) || isMTBUF ( * FirstLdSt ) ) && ( isMUBUF ( * SecondLdSt ) || isMTBUF ( * SecondLdSt ) ) ;


<s> InsertPt = ++ cast < Instruction > ( Ptr ) -> getIterator ( ) ; assert ( InsertPt != InsertPt -> getParent ( ) -> end ( ) && <STR_LIT> ) ; } Instruction * PtrInGlobal = new AddrSpaceCastInst ( Ptr , PointerType :: getWithSamePointeeType ( cast < PointerType > ( Ptr -> getType ( ) ) , ADDRESS_SPACE_GLOBAL ) , Ptr -> getName ( ) , & * InsertPt ) ;

Value * PtrInGeneric = new AddrSpaceCastInst ( PtrInGlobal , Ptr -> getType ( ) , Ptr -> getName ( ) , & * InsertPt ) ;


<s> static void lm32_setup_incoming_varargs ( cumulative_args_t cum_v , machine_mode mode , tree type , int * pretend_size , int no_rtl ) { CUMULATIVE_ARGS * cum = get_cumulative_args ( cum_v ) ; int first_anon_arg ; tree fntype ; fntype = TREE_TYPE ( current_function_decl ) ; if ( stdarg_p ( fntype ) ) first_anon_arg = * cum + LM32_FIRST_ARG_REG ;


<s> for ( const auto & ArgIdx : enumerate ( Args ) ) { MVT ArgVT = ArgIdx . value ( ) . VT ;

if ( ArgVT . isScalableVector ( ) && ArgVT . getVectorElementType ( ) . SimpleTy == <STR_LIT> ) return ArgIdx . index ( ) ;


<s> FixFSMULD :: FixFSMULD ( ) : LEONMachineFunctionPass ( ID ) {


<s> return ( ( Immed >> <NUM_LIT> ) == <NUM_LIT> || ( ( Immed & <NUM_LIT> ) == <NUM_LIT> && Immed >> <NUM_LIT> == <NUM_LIT> ) ) ;


<s> unsigned SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) ; } return false ;


<s> if ( OpNo == <NUM_LIT> ) { return Error ( Lexer . getLoc ( ) , <STR_LIT> ) ; } return ParsePredicateOperand ( Operands ) ; } if ( Lexer . is ( AsmToken :: Dollar ) ) { StringRef Mnemonic = ( ( <ISA_LIT>Operand * ) Operands [ <NUM_LIT> ] ) -> getToken ( ) ; if ( isPredSrcOperand ( Mnemonic , OpNo ) ) { return ParsePredicateOperand ( Operands , true ) ; } return ParseRegister ( Operands ) ; }

if ( Lexer . is ( AsmToken :: Identifier ) ) {


<s> return forceScalarizeMaskedGather ( VTy , Alignment ) ;


<s> if ( TM -> getOptLevel ( ) != CodeGenOpt :: None && EnableGlobalMerge ) addPass ( createGlobalMergePass ( TM -> getTargetLowering ( ) ) ) ;


for ( unsigned i = <NUM_LIT> ; i < Offsets . size ( ) ; ++ i ) PerformArgSplit ( SplitArgs [ FirstRegIdx + i ] . Reg , Offsets [ i ] * <NUM_LIT> ) ;


<s> PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ;


<s> if ( count != <NUM_LIT> ) return const0_rtx ;

return get_hard_reg_initial_val ( Pmode , RETURN_ADDR_REGNUM ) ;


<s> static DecodeStatus DecodeShiftRightImm64 ( MCInst & Inst , unsigned Val , uint64_t Address , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Val ) ) ; return MCDisassembler :: Success ;


<s> RegT = get<ISA_LIT>RegisterNumbering ( RegT ) ; Binary |= ( RegT << <STR_LIT> ) ; Binary |= encodeNEONRn ( MI , <NUM_LIT> ) ;


<s> initLiveRegs ( LiveRegs , TRI , FuncInfo , MF , MBB , MBBI , true ) ; MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister ( MRI , LiveRegs , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addReg ( TRI . getSubReg ( RetAddrReg , <STR_LIT> ) ) ; int DwordOff = <NUM_LIT> ; buildPrologSpill ( ST , TRI , * FuncInfo , LiveRegs , MF , MBB , MBBI , TmpVGPR , FI , DwordOff ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addReg ( TRI . getSubReg ( RetAddrReg , <STR_LIT> ) ) ; DwordOff = <NUM_LIT> ; buildPrologSpill ( ST , TRI , * FuncInfo , LiveRegs , MF , MBB , MBBI , TmpVGPR , FI , DwordOff ) ; buildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createOffset ( nullptr , MCRI -> getDwarfRegNum ( <STR_LIT> , false ) , MFI . getObjectOffset ( FI ) * ST . getWavefrontSize ( ) ) ) ; } if ( EXECSaveIndex && spilledToMemory ( MF , * EXECSaveIndex ) ) { const int FI = * EXECSaveIndex ; assert ( ! MFI . isDeadObjectIndex ( FI ) ) ; initLiveRegs ( LiveRegs , TRI , FuncInfo , MF , MBB , MBBI , true ) ; MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister ( MRI , LiveRegs , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addReg ( TRI . getSubReg ( <STR_LIT> , <STR_LIT> ) ) ; int DwordOff = <NUM_LIT> ; buildPrologSpill ( ST , TRI , * FuncInfo , LiveRegs , MF , MBB , MBBI , TmpVGPR , FI , DwordOff ) ; if ( ! ST . isWave32 ( ) ) { BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , TmpVGPR ) . addReg ( TRI . getSubReg ( <STR_LIT> , <STR_LIT> ) ) ; DwordOff = <NUM_LIT> ; buildPrologSpill ( ST , TRI , * FuncInfo , LiveRegs , MF , MBB , MBBI , TmpVGPR , FI , DwordOff ) ; } buildCFI ( MBB , MBBI , DL , MCCFIInstruction :: createOffset ( nullptr , MCRI -> getDwarfRegNum ( <STR_LIT> , false ) , MFI . getObjectOffset ( FI ) * ST . getWavefrontSize ( ) ) ) ; } } if ( ! emitSpillsToMem ) { if ( RASaveIndex && ! spilledToMemory ( MF , * RASaveIndex ) ) { MCRegister RetAddrReg = TRI . getReturnAddressReg ( MF ) ;

if ( ! MBB . isLiveIn ( RetAddrReg ) ) MBB . addLiveIn ( RetAddrReg ) ;


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( r ) : <STR_LIT> ( x ) , <STR_LIT> ( y ) , <STR_LIT> ( z ) ) ; return r ;


<s> if ( ! AddRec ) return p_SEL -> getZero ( Expr -> getType ( ) ) ;

if ( AddRec -> getLoop ( ) == TargetLoop ) return AddRec -> getStepRecurrence ( * p_SEL ) ;


<s> return ( __m256 ) __builtin_ia32_reduceps256_mask ( ( __v8sf ) __A , __B , ( __v8sf ) _mm256_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> bool isCheapToSpeculateCttz ( ) const override {


<s> setOperationAction ( <STR_LIT> , LegalPackedVT , Custom ) ; setOperationAction ( <STR_LIT> , LegalPackedVT , Custom ) ; } for ( MVT VT : <STR_LIT> ( ) ) { MVT ElemVT = VT . getVectorElementType ( ) ; unsigned ElemBits = ElemVT . getScalarSizeInBits ( ) ; if ( ElemBits != <NUM_LIT> && ElemBits != <NUM_LIT> ) continue ; for ( unsigned MemOpc : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( MemOpc , VT , Custom ) ; const <STR_LIT> IntReductionOCs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( unsigned IntRedOpc : IntReductionOCs ) setOperationAction ( IntRedOpc , VT , Custom ) ; }


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned ScratchWaveOffsetReg = MFI -> getScratchWaveOffsetReg ( ) ; if ( ScratchWaveOffsetReg == <STR_LIT> || ! MRI . isPhysRegUsed ( ScratchWaveOffsetReg ) ) { assert ( MFI -> getStackPtrOffsetReg ( ) == <STR_LIT> ) ; return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; } unsigned SPReg = MFI -> getStackPtrOffsetReg ( ) ; if ( ST . hasSGPRInitBug ( ) ) return std :: make_pair ( ScratchWaveOffsetReg , SPReg ) ; unsigned NumPreloaded = MFI -> getNumPreloadedSGPRs ( ) ; ArrayRef < MCPhysReg > AllSGPRs = getAllSGPRs ( ST , MF ) ; if ( NumPreloaded > AllSGPRs . size ( ) ) return std :: make_pair ( ScratchWaveOffsetReg , SPReg ) ; AllSGPRs = AllSGPRs . slice ( NumPreloaded ) ; unsigned ReservedRegCount = <NUM_LIT> ; if ( AllSGPRs . size ( ) < ReservedRegCount ) return std :: make_pair ( ScratchWaveOffsetReg , SPReg ) ; bool HandledScratchWaveOffsetReg = ScratchWaveOffsetReg != TRI -> reservedPrivateSegmentWaveByteOffsetReg ( MF ) ; for ( MCPhysReg Reg : AllSGPRs . drop_back ( ReservedRegCount ) ) { if ( ! MRI . isPhysRegUsed ( Reg ) && MRI . isAllocatable ( Reg ) ) { if ( ! HandledScratchWaveOffsetReg ) { HandledScratchWaveOffsetReg = true ; MRI . replaceRegWith ( ScratchWaveOffsetReg , Reg ) ; MFI -> setScratchWaveOffsetReg ( Reg ) ; ScratchWaveOffsetReg = Reg ; break ; } }


<s> bool cris_frame_pointer_required ( void ) { return ! crtl -> sp_is_unchanging ;


<s> LLVMTargetMachine ( T , <STR_LIT> , TT , CPU , FS , Options , RM . getValueOr ( Reloc :: Model :: Static ) , CM . getValueOr ( CodeModel :: Model :: Tiny ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) , DefaultSubtarget ( TT , CPU , FS , * this ) {


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; } if ( ! FrameSize ) { return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ;


<s> if ( ( ! CONST_INT_P ( offset ) ) || ( ( INTVAL ( offset ) & <NUM_LIT> ) != <NUM_LIT> ) ) return false ; sym = XEXP ( addr , <NUM_LIT> ) ; }

if ( ( GET_CODE ( sym ) == SYMBOL_REF ) && CONSTANT_POOL_ADDRESS_P ( sym ) ) return true ;


<s> else PFIndexes [ i ] = M [ i ] ; } unsigned PFTableIndex = PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] * <NUM_LIT> + PFIndexes [ <NUM_LIT> ] ; unsigned PFEntry = PerfectShuffleTable [ PFTableIndex ] ; unsigned Cost = ( PFEntry >> <NUM_LIT> ) ; if ( Cost <= <NUM_LIT> ) return true ; } bool DummyBool ; int DummyInt ; unsigned DummyUnsigned ; return ( ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isREVMask ( M , VT , <NUM_LIT> ) || isREVMask ( M , VT , <NUM_LIT> ) || isREVMask ( M , VT , <NUM_LIT> ) || isEXTMask ( M , VT , DummyBool , DummyUnsigned ) || isTRNMask ( M , VT , DummyUnsigned ) || isUZPMask ( M , VT , DummyUnsigned ) || isZIPMask ( M , VT , DummyUnsigned ) || isTRN_v_undef_Mask ( M , VT , DummyUnsigned ) || isUZP_v_undef_Mask ( M , VT , DummyUnsigned ) || isZIP_v_undef_Mask ( M , VT , DummyUnsigned ) || isINSMask ( M , VT . getVectorNumElements ( ) , DummyBool , DummyInt ) || isConcatMask ( M , VT , VT . getSizeInBits ( ) == <NUM_LIT> ) ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

return DisableFramePointerElim ( MF ) || MFI -> hasVarSizedObjects ( ) ;


<s> case Register : Reg = o . Reg ; break ; case Immediate : Imm = o . Imm ; break ; case Token : Tok = o . Tok ; break ;


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result ; if ( OpFlags == <STR_LIT> && <STR_LIT> ( Offset , M ) ) { Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , Offset ) ; Offset = <NUM_LIT> ; } else { Result = DAG . getTargetGlobalAddress ( GV , dl , PtrVT , <NUM_LIT> , OpFlags ) ; } if ( Subtarget -> isPICStyleRIPRel ( ) && ( M == CodeModel :: Small || M == CodeModel :: Kernel ) ) Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; else Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , Result ) ; if ( isGlobalRelativeToPICBase ( OpFlags ) ) {

Result = DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getNode ( <STR_LIT> , dl , PtrVT ) , Result ) ;


<s> unsigned DstRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcRegS = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! <STR_LIT> . contains ( DstRegS , SrcRegS ) ) return false ; const TargetRegisterInfo * TRI = & getRegisterInfo ( ) ; unsigned DstRegD = TRI -> getMatchingSuperReg ( DstRegS , <STR_LIT> , & <STR_LIT> ) ; unsigned SrcRegD = TRI -> getMatchingSuperReg ( SrcRegS , <STR_LIT> , & <STR_LIT> ) ; if ( ! DstRegD || ! SrcRegD ) return false ; if ( ! MI -> definesRegister ( DstRegD , TRI ) || MI -> readsRegister ( DstRegD , TRI ) ) return false ; if ( MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ) return false ; DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; MachineInstrBuilder MIB ( * MI -> getParent ( ) -> getParent ( ) , MI ) ; int ImpDefIdx = MI -> findRegisterDefOperandIdx ( DstRegD ) ; if ( ImpDefIdx != - <NUM_LIT> ) MI -> RemoveOperand ( ImpDefIdx ) ; MI -> setDesc ( get ( <STR_LIT> ) ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( DstRegD ) ; MI -> getOperand ( <NUM_LIT> ) . setReg ( SrcRegD ) ; AddDefaultPred ( MIB ) ; MI -> getOperand ( <NUM_LIT> ) . setIsUndef ( ) ;

MIB . addReg ( SrcRegS , RegState :: Implicit ) ;


<s> bool isReg ( ) const { return Kind == Register ;


<s> NodeAddr < UseNode * > UseUN = * I ; assert ( ! ( UseUN . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) && <STR_LIT> ) ; NodeAddr < StmtNode * > UseIA = UseUN . Addr -> getOwner ( * DFG ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Print < NodeAddr < InstrNode * >> ( UseIA , * DFG ) << <STR_LIT> ) ; MachineInstr * UseMI = UseIA . Addr -> getCode ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << UseMI -> getParent ( ) -> getNumber ( ) << <STR_LIT> << * UseMI << <STR_LIT> ) ; const MCInstrDesc & UseMID = UseMI -> getDesc ( ) ; assert ( HII -> getAddrMode ( UseMI ) == <STR_LIT> ) ; auto UsePos = MachineBasicBlock :: iterator ( UseMI ) ; MachineBasicBlock :: instr_iterator InsertPt = UsePos . getInstrIterator ( ) ; short NewOpCode = getBaseWithLongOffset ( UseMI ) ;

assert ( NewOpCode >= <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ;


<s> args . reserve ( nargs ) ; for ( unsigned int i = <NUM_LIT> ; i < nargs ; ++ i ) args . quick_push ( expand_normal ( CALL_EXPR_ARG ( call_expr , i ) ) ) ;


<s> if ( Offset < <NUM_LIT> ) return SDValue ( ) ; if ( ( Offset % <NUM_LIT> ) & <NUM_LIT> ) return SDValue ( ) ; int64_t StartOffset = Offset & ~ <NUM_LIT> ; if ( StartOffset ) Ptr = DAG . getNode ( <STR_LIT> , Ptr . getDebugLoc ( ) , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( StartOffset , Ptr . getValueType ( ) ) ) ; int EltNo = ( Offset - StartOffset ) >> <NUM_LIT> ; int Mask [ <NUM_LIT> ] = { EltNo , EltNo , EltNo , EltNo } ; EVT VT = ( PVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue V1 = DAG . getLoad ( VT , dl , Chain , Ptr , LD -> getSrcValue ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ; V1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V1 ) ; return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getVectorShuffle ( <STR_LIT> , dl , V1 , DAG . getUNDEF ( <STR_LIT> ) , & Mask [ <NUM_LIT> ] ) ) ; } return SDValue ( ) ;


<s> unsigned Val = cast < ConstantSDNode > ( Arg ) -> getZExtValue ( ) ; if ( Val < NumElems ) MaskVec . push_back ( DAG . getConstant ( Val + NumElems , EltVT ) ) ; else MaskVec . push_back ( DAG . getConstant ( Val - NumElems , EltVT ) ) ; }

return DAG . getNode ( <STR_LIT> , dl , MaskVT , & MaskVec [ <NUM_LIT> ] , NumElems ) ;


if ( TREE_CODE ( * node ) != FUNCTION_DECL ) {


<s> VT = <STR_LIT> ; } } else { if ( Len >= <NUM_LIT> && Alignment == <NUM_LIT> ) VT = <STR_LIT> ; else { VT = <STR_LIT> ; } } bool RV ; Register ResultReg ; RV = <ISA_LIT>EmitLoad ( VT , ResultReg , Src ) ; assert ( RV && <STR_LIT> ) ; RV = <ISA_LIT>EmitStore ( VT , ResultReg , Dest ) ;


<s> LowerSETCC ( SDValue Op , SelectionDAG & DAG ) const {


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const Target & T , const MCSubtargetInfo & STI , const MCRegisterInfo & MRI , const MCTargetOptions & Options ) {

const Triple & TT = STI . getTargetTriple ( ) ;


<s> <ISA_LIT>LinuxMCAsmInfo :: <ISA_LIT>LinuxMCAsmInfo ( bool is64Bit ) { AlignmentIsInBytes = false ; CommentString = <STR_LIT> ; GlobalPrefix = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; WeakRefDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ; PCSymbol = <STR_LIT> ; HasLEB128 = true ; if ( ! is64Bit ) ExceptionsType = ExceptionHandling :: Dwarf ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = is64Bit ? <STR_LIT> : <NUM_LIT> ;


<s> return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , DL , VT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> static inline bool isImmHF ( uint64_t Val ) { return ( Val & ~ <NUM_LIT> ) == <NUM_LIT> ;


<s> BlockSet AddedToWorkList ; Blocks . insert ( Entry ) ; for ( auto * Pred : Entry -> predecessors ( ) ) { if ( ! Enterers . count ( Pred ) ) { WorkList . push_back ( Pred ) ; AddedToWorkList . insert ( Pred ) ; } }


<s> StubLayout Result = { <NUM_LIT> * <NUM_LIT> , <NUM_LIT> } ;


<s> emit_move_insn ( target , mem ) ; return target ; } rtx_vector_builder int_builder ( VNx16QImode , builder . npatterns ( ) , builder . nelts_per_pattern ( ) ) ;

for ( unsigned int i = <NUM_LIT> ; i < builder . encoded_nelts ( ) ; ++ i ) int_builder . quick_push ( INTVAL ( builder . elt ( i ) ) ? constm1_rtx : const0_rtx ) ;


<s> MachineInstr * MI = MRI -> getVRegDef ( SReg ) ; if ( ! MI ) return <STR_LIT> ; MachineOperand * MO = MI -> findRegisterDefOperand ( SReg ) ; if ( ! MO ) return <STR_LIT> ; assert ( MO -> isReg ( ) && <STR_LIT> ) ;

if ( MI -> isCopy ( ) && usesRegClass ( MI -> getOperand ( <NUM_LIT> ) , & <STR_LIT> ) ) {


<s> return vabs_f64 ( __a ) <= vabs_f64 ( __b ) ;


<s> op = copy_insn ( op ) ; for_each_rtx ( & op , mips_rewrite_small_data_1 , <NUM_LIT> ) ;


<s> static __inline __m64 _mm_mulhi_pi32 ( __m64 a , __m64 b ) { return ( __m64 ) __builtin_arm_wmulwsm ( ( __v2si ) a , ( __v2si ) b ) ;


<s> Reg = QuadFPRegs [ regIdx / <NUM_LIT> ] ; break ; case rk_DoubleReg : regIdx = Reg - <STR_LIT> ; if ( regIdx % <NUM_LIT> || regIdx > <NUM_LIT> ) return nullptr ; Reg = QuadFPRegs [ regIdx / <NUM_LIT> ] ; break ; }


<s> case <STR_LIT> : case <STR_LIT> : { unsigned ArgWidth ; if ( II . getIntrinsicID ( ) == <STR_LIT> ) { ArgWidth = <NUM_LIT> ; } else { auto Arg = II . getArgOperand ( <NUM_LIT> ) ; auto ArgType = cast < FixedVectorType > ( Arg -> getType ( ) ) ; ArgWidth = ArgType -> getNumElements ( ) ; } APInt DemandedElts = DemandedMask . zextOrTrunc ( ArgWidth ) ; Type * VTy = II . getType ( ) ; if ( DemandedElts . isNullValue ( ) ) { return ConstantInt :: getNullValue ( VTy ) ; } Known . Zero . setBitsFrom ( ArgWidth ) ; KnownBitsComputed = true ; break ;


<s> bool <ISA_LIT>TargetMachine :: addAssemblyEmitter ( PassManagerBase & PM , bool Fast , raw_ostream & Out ) { PM . add ( create<ISA_LIT>CodePrinterPass ( Out , * this , Fast ) ) ;


<s> void Liveness :: emptify ( RefMap & M ) {

for ( auto I = M . begin ( ) , E = M . end ( ) ; I != E ; ) I = I -> second . empty ( ) ? M . erase ( I ) : std :: next ( I ) ;


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; EVT OpVT = Vec . getValueType ( ) ; unsigned Opc = IsSigned ? <STR_LIT> : <STR_LIT> ; if ( VT . getVectorNumElements ( ) == <NUM_LIT> ) { assert ( OpVT == <STR_LIT> && <STR_LIT> ) ; if ( VT . getSizeInBits ( ) == OpVT . getSizeInBits ( ) ) return Op ; return DAG . UnrollVectorOp ( Op . getNode ( ) ) ; } if ( VT . getSizeInBits ( ) > OpVT . getSizeInBits ( ) ) { assert ( Vec . getValueType ( ) == <STR_LIT> && VT == <STR_LIT> && <STR_LIT> ) ; Vec = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) ; return DAG . getNode ( Opc , dl , VT , Vec ) ; } else if ( VT . getSizeInBits ( ) < OpVT . getSizeInBits ( ) ) { EVT CastVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , OpVT . getVectorElementType ( ) . getSizeInBits ( ) ) ; CastVT = EVT :: getVectorVT ( * DAG . getContext ( ) , CastVT , VT . getVectorNumElements ( ) ) ; Vec = DAG . getNode ( Opc , dl , CastVT , Vec ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vec ) ;


<s> default_file_start ( ) ; fprintf ( asm_out_file , <STR_LIT> , ( flag_pic ? <STR_LIT> : <STR_LIT> ) ) ; if ( ! riscv_mrelax ) fprintf ( asm_out_file , <STR_LIT> ) ;

if ( riscv_emit_attribute_p ) riscv_emit_attribute ( ) ;


<s> unsigned <ISA_LIT>SEDAGToDAGISel :: getMSACtrlReg ( const SDValue RegIdx ) const { uint64_t RegNum = cast < ConstantSDNode > ( RegIdx ) -> getZExtValue ( ) ;

return <STR_LIT> . getRegister ( RegNum ) ;


<s> BBInfo [ MBB -> getNumber ( ) ] . Size -= delta ; MBB -> back ( ) . eraseFromParent ( ) ; MBB -> addSuccessor ( DestBB ) ; std :: next ( MBB -> getIterator ( ) ) -> removeSuccessor ( DestBB ) ; } MachineBasicBlock * NextBB = & * ++ MBB -> getIterator ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * DestBB ) << <STR_LIT> << printMBBReference ( * NextBB ) << <STR_LIT> ) ; BuildMI ( MBB , DebugLoc ( ) , TII -> get ( MI -> getOpcode ( ) ) ) . addMBB ( NextBB ) . addImm ( CC ) . addReg ( CCReg ) ; Br . MI = & MBB -> back ( ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; if ( isThumb ) BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) . add ( predOps ( <STR_LIT> ) ) ; else BuildMI ( MBB , DebugLoc ( ) , TII -> get ( Br . UncondBr ) ) . addMBB ( DestBB ) ; BBInfo [ MBB -> getNumber ( ) ] . Size += TII -> getInstSizeInBytes ( MBB -> back ( ) ) ; unsigned MaxDisp = getUnconditionalBrDisp ( Br . UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & MBB -> back ( ) , MaxDisp , false , Br . UncondBr ) ) ; BBInfo [ MI -> getParent ( ) -> getNumber ( ) ] . Size -= TII -> getInstSizeInBytes ( * MI ) ; MI -> eraseFromParent ( ) ; adjustBBOffsetsAfter ( MBB ) ;


<s> void setFramePointerOffset ( int Idx ) { FramePointerOffset = Idx ;


<s> const std :: vector < <ISA_LIT>Section * > & ROSections = PTOF -> ROSections ; for ( unsigned i = <NUM_LIT> ; i < ROSections . size ( ) ; i ++ ) { const std :: vector < const GlobalVariable * > & Items = ROSections [ i ] -> Items ; if ( ! Items . size ( ) ) continue ; O << <STR_LIT> ; OutStreamer . SwitchSection ( PTOF -> ROSections [ i ] -> S_ ) ; for ( unsigned j = <NUM_LIT> ; j < Items . size ( ) ; j ++ ) { O << Mang -> getMangledName ( Items [ j ] ) ; Constant * C = Items [ j ] -> getInitializer ( ) ; int AddrSpace = Items [ j ] -> getType ( ) -> getAddressSpace ( ) ; EmitGlobalConstant ( C , AddrSpace ) ;


<s> bool <ISA_LIT>SEDAGToDAGISel :: selectIntAddrSImm10Lsl1 ( SDValue Addr , SDValue & Base , SDValue & Offset ) const { if ( selectAddrFrameIndex ( Addr , Base , Offset ) ) return true ; if ( selectAddrFrameIndexOffset ( Addr , Base , Offset , <NUM_LIT> , <NUM_LIT> ) ) return true ; return selectAddrDefault ( Addr , Base , Offset ) ;


<s> assert ( TargetRegisterInfo :: virtReg2Index ( VReg ) < WARegs . size ( ) ) ; WARegs [ TargetRegisterInfo :: virtReg2Index ( VReg ) ] = WAReg ;


if ( GET_CODE ( op ) == SUBREG ) op = SUBREG_REG ( op ) ;


<s> if ( <ISA_LIT>Features [ <STR_LIT> ] || <ISA_LIT>Features [ <STR_LIT> ] ) { return SPUInstrLayout ; }


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( StringRef Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'b' : case 'r' : case 'f' :


<s> for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Required . Array [ i ] <= WaitedOn . Array [ i ] ) continue ; NeedWait = true ; if ( Ordered [ i ] ) { unsigned Value = LastIssued . Array [ i ] - Required . Array [ i ] ; Counts . Array [ i ] = std :: min ( Value , WaitCounts . Array [ i ] ) ; } else Counts . Array [ i ] = <NUM_LIT> ; WaitedOn . Array [ i ] = LastIssued . Array [ i ] - Counts . Array [ i ] ; } if ( ! NeedWait ) return false ;

if ( Counts . Named . EXP == <NUM_LIT> ) ExpInstrTypesSeen = <NUM_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: GetF64FormalArgument ( CCValAssign & VA , CCValAssign & NextVA , SDValue & Root , SelectionDAG & DAG , DebugLoc dl ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; const TargetRegisterClass * RC ; if ( AFI -> isThumb1OnlyFunction ( ) ) RC = <STR_LIT> ; else RC = <STR_LIT> ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; SDValue ArgValue = DAG . getCopyFromReg ( Root , dl , Reg , <STR_LIT> ) ; SDValue ArgValue2 ; if ( NextVA . isMemLoc ( ) ) { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; int FI = MFI -> CreateFixedObject ( <NUM_LIT> , NextVA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; ArgValue2 = DAG . getLoad ( <STR_LIT> , dl , Root , FIN , MachinePointerInfo :: getFixedStack ( FI ) , false , false , false , <NUM_LIT> ) ; } else {

Reg = MF . addLiveIn ( NextVA . getLocReg ( ) , RC ) ;


<s> return JumpTableEntryInfo [ Idx ] . first ;


return isImm ( ) || ( isReg ( ) && isRegClass ( <STR_LIT> ) ) ;


<s> const MachineOperand & MO1 = MI -> getOperand ( Op ) ; assert ( TargetRegisterInfo :: isPhysicalRegister ( MO1 . getReg ( ) ) ) ; O << <STR_LIT> << TRI -> getAsmName ( MO1 . getReg ( ) ) << <STR_LIT> ;


<s> bool <ISA_LIT>ElimCompare :: convertToBRCT ( MachineInstr & MI , MachineInstr & Compare , SmallVectorImpl < MachineInstr * > & CCUsers ) { unsigned Opcode = MI . getOpcode ( ) ; unsigned BRCT ; if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else if ( Opcode == <STR_LIT> ) BRCT = <STR_LIT> ; else return false ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != - <NUM_LIT> ) return false ; if ( CCUsers . size ( ) != <NUM_LIT> ) return false ; MachineInstr * Branch = CCUsers [ <NUM_LIT> ] ; if ( Branch -> getOpcode ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> || Branch -> getOperand ( <NUM_LIT> ) . getImm ( ) != <STR_LIT> ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = Branch ; for ( ++ MBBI ; MBBI != MBBE ; ++ MBBI ) if ( getRegReferences ( * MBBI , SrcReg ) ) return false ; MachineOperand Target ( Branch -> getOperand ( <NUM_LIT> ) ) ; while ( Branch -> getNumOperands ( ) ) Branch -> RemoveOperand ( <NUM_LIT> ) ;

Branch -> setDesc ( TII -> get ( BRCT ) ) ;


<s> if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ;

SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ;