<s> if ( darwin_emit_branch_islands && GET_CODE ( operands [ dest_operand_number ] ) == SYMBOL_REF && ( INTVAL ( operands [ cookie_operand_number ] ) & CALL_LONG ) ) { tree labelname ; tree funname = get_identifier ( XSTR ( operands [ dest_operand_number ] , <NUM_LIT> ) ) ; if ( no_previous_def ( funname ) ) { rtx label_rtx = gen_label_rtx ( ) ; char * label_buf , temp_buf [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( temp_buf , <STR_LIT> , CODE_LABEL_NUMBER ( label_rtx ) ) ; label_buf = temp_buf [ <NUM_LIT> ] == '*' ? temp_buf + <NUM_LIT> : temp_buf ;

labelname = get_identifier ( label_buf ) ;


<s> void <ISA_LIT>AsmPrinter :: EmitFunctionBodyEnd ( ) {


<s> pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Unresolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Create ( * ( m_pGOT -> begin ( ) ) , <NUM_LIT> ) , ResolveInfo :: Hidden ) ; } else { m_pGOTSymbol = pBuilder . AddSymbol < IRBuilder :: Force , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Create ( * ( m_pGOT -> begin ( ) ) , <NUM_LIT> ) , ResolveInfo :: Hidden ) ; }


<s> static bool arm_pass_by_reference ( cumulative_args_t , const function_arg_info & arg ) { return arg . type && TREE_CODE ( TYPE_SIZE ( arg . type ) ) != INTEGER_CST ;


<s> break ; case MCFragment :: FT_Align : { Size = <NUM_LIT> ; break ; } case MCFragment :: FT_Relaxable : { auto & RF = cast < MCRelaxableFragment > ( * K ) ; auto & Inst = const_cast < MCInst & > ( RF . getInst ( ) ) ; while ( Size > <NUM_LIT> && <ISA_LIT>MCInstrInfo :: bundleSize ( Inst ) < <NUM_LIT> ) { MCInst * Nop = new ( Asm . getContext ( ) ) MCInst ; Nop -> setOpcode ( <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createInst ( Nop ) ) ; Size -= <NUM_LIT> ; if ( ! <ISA_LIT>MCChecker ( * MCII , RF . getSubtargetInfo ( ) , Inst , Inst , * Asm . getContext ( ) . getRegisterInfo ( ) ) . check ( ) ) { Inst . erase ( Inst . end ( ) - <NUM_LIT> ) ; Size = <NUM_LIT> ; } } bool Error = <ISA_LIT>MCShuffle ( true , * MCII , RF . getSubtargetInfo ( ) , Inst ) ;


<s> S . SwitchSection ( Context . getELFSection ( ElfNote :: SectionName , ELF :: SHT_NOTE , ELF :: SHF_ALLOC ) ) ; S . EmitIntValue ( NameSZ , <NUM_LIT> ) ; S . EmitValue ( DescSZ , <NUM_LIT> ) ; S . EmitIntValue ( NoteType , <NUM_LIT> ) ; S . EmitBytes ( Name ) ; S . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; EmitDesc ( S ) ; S . EmitValueToAlignment ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; S . PopSection ( ) ;


<s> static unsigned int iq2000_function_arg_boundary ( machine_mode mode , const_tree type ) {

return ( type != NULL_TREE ? ( TYPE_ALIGN ( type ) <= PARM_BOUNDARY ? PARM_BOUNDARY : TYPE_ALIGN ( type ) ) : ( GET_MODE_ALIGNMENT ( mode ) <= PARM_BOUNDARY ? PARM_BOUNDARY : GET_MODE_ALIGNMENT ( mode ) ) ) ;


<s> unsigned LhsReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RhsReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; CmpInst :: Predicate Predicate = ( CmpInst :: Predicate ) I . getOperand ( <NUM_LIT> ) . getPredicate ( ) ; static const uint16_t SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> } } ; const uint16_t * SETFOpc = nullptr ; switch ( Predicate ) { default : break ; case CmpInst :: FCMP_OEQ : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; case CmpInst :: FCMP_UNE : SETFOpc = & SETFOpcTable [ <NUM_LIT> ] [ <NUM_LIT> ] ; break ; } unsigned OpCmp ; LLT Ty = MRI . getType ( LhsReg ) ; switch ( Ty . getSizeInBits ( ) ) { default : return false ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; case <NUM_LIT> : OpCmp = <STR_LIT> ; break ; } unsigned ResultReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; RBI . constrainGenericRegister ( ResultReg , * getRegClass ( LLT :: scalar ( <NUM_LIT> ) , * RBI . getRegBank ( ResultReg , MRI , TRI ) ) , MRI ) ; if ( SETFOpc ) { MachineInstr & CmpInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( OpCmp ) ) . addReg ( LhsReg ) . addReg ( RhsReg ) ; unsigned FlagReg1 = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned FlagReg2 = MRI . createVirtualRegister ( & <STR_LIT> ) ; MachineInstr & Set1 = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg1 ) ; MachineInstr & Set2 = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( SETFOpc [ <NUM_LIT> ] ) , FlagReg2 ) ;

MachineInstr & Set3 = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( SETFOpc [ <NUM_LIT> ] ) , ResultReg ) . addReg ( FlagReg1 ) . addReg ( FlagReg2 ) ;


<s> DstVT = <STR_LIT> ( DstVT , NumDstElts ) ; Shuffle = SrcVT != MaskVT ? unsigned ( <STR_LIT> ) : unsigned ( <STR_LIT> ) ; return true ; } } } if ( ( ( MaskEltSize == <NUM_LIT> ) || ( MaskEltSize == <NUM_LIT> && Subtarget . hasSSE2 ( ) ) ) && isUndefOrEqual ( Mask [ <NUM_LIT> ] , <NUM_LIT> ) && isUndefOrZeroInRange ( Mask , <NUM_LIT> , NumMaskElts - <NUM_LIT> ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = ! Subtarget . hasSSE2 ( ) ? <STR_LIT> : MaskVT ; return true ; } if ( MaskVT . is128BitVector ( ) && Subtarget . hasSSE3 ( ) && AllowFloatDomain ) { if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is256BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; } } if ( MaskVT . is512BitVector ( ) && AllowFloatDomain ) { assert ( Subtarget . hasAVX512 ( ) && <STR_LIT> ) ; if ( isTargetShuffleEquivalent ( Mask , { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ) ) { Shuffle = <STR_LIT> ; SrcVT = DstVT = <STR_LIT> ; return true ; }


<s> int FromSize = getSizeOf ( FromSTy ) ; int ToSize = getSizeOf ( ToSTy ) ; assert ( FromSize % ToSize == <NUM_LIT> || ToSize % FromSize == <NUM_LIT> ) ; auto * MaskTy = cast < VectorType > ( Mask -> getType ( ) ) ; int FromCount = MaskTy -> getElementCount ( ) . getFixedValue ( ) ; int ToCount = ( FromCount * FromSize ) / ToSize ;

assert ( ( FromCount * FromSize ) % ToSize == <NUM_LIT> ) ;


<s> if ( <ISA_LIT>ScalarSSEf32 ) Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) Opc = HasAVX512 ? <STR_LIT> : HasAVX ? <STR_LIT> : <STR_LIT> ; else Opc = <STR_LIT> ; break ; case <STR_LIT> : return <NUM_LIT> ; } Align Alignment = DL . getPrefTypeAlign ( CFP -> getType ( ) ) ; unsigned PICBase = <NUM_LIT> ; unsigned char OpFlag = Subtarget -> classifyLocalReference ( nullptr ) ; if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( OpFlag == <STR_LIT> ) PICBase = getInstrInfo ( ) -> getGlobalBaseReg ( FuncInfo . MF ) ; else if ( Subtarget -> is64Bit ( ) && TM . getCodeModel ( ) == CodeModel :: Small ) PICBase = <STR_LIT> ; unsigned CPI = MCP . getConstantPoolIndex ( CFP , Alignment . value ( ) ) ;

unsigned ResultReg = createResultReg ( TLI . getRegClassFor ( VT . SimpleTy ) ) ;


<s> return ( int16x4_t ) __builtin_neon_vminsv4hi ( __a , __b ) ;


return ( poly16x4_t ) __builtin_neon_vld1_lanev4hi ( ( const __builtin_neon_hi * ) __a , ( int16x4_t ) __b , __c ) ;


<s> DeadInstrs . clear ( ) ; MRI = & Fn . getRegInfo ( ) ; for ( MachineBasicBlock & MBB : Fn ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; for ( MachineInstr & HiLUI : MBB ) { MachineInstr * LoADDI = nullptr ; if ( ! detectLuiAddiGlobal ( HiLUI , LoADDI ) ) continue ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * LoADDI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) << <STR_LIT> ) ; MadeChange |= detectAndFoldOffset ( HiLUI , * LoADDI ) ;


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const {


<s> else if ( ( Const = getIfConst ( Add -> getOperand ( <NUM_LIT> ) ) ) ) Summand = Add -> getOperand ( <NUM_LIT> ) ; else return ReturnFalse ; int64_t Immediate = Const . getValue ( ) << TypeScale ; if ( Immediate > <NUM_LIT> || Immediate < - <NUM_LIT> || Immediate % <NUM_LIT> != <NUM_LIT> ) return ReturnFalse ; return std :: pair < Value * , int64_t > ( Summand , Immediate ) ;


<s> static bool CompareMBBNumbers ( const MachineBasicBlock * LHS , const MachineBasicBlock * RHS ) { return LHS -> getNumber ( ) < RHS -> getNumber ( ) ;


<s> static SDValue lowerMSASplatImm ( SDValue Op , unsigned ImmOp , SelectionDAG & DAG ) { return DAG . getConstant ( Op -> getConstantOperandVal ( ImmOp ) , SDLoc ( Op ) , Op -> getValueType ( <NUM_LIT> ) ) ;


<s> int64_t v = ( int64_t ) N -> getSExtValue ( ) ;

return isShiftedInt < <NUM_LIT> , <NUM_LIT> > ( v ) ;


<s> return IntegerType :: get ( Ctx , <NUM_LIT> ) ;


<s> return new <ISA_LIT>IRDecorator ( ) ;


<s> if ( crtl -> profile ) return false ; if ( mips16_cfun_returns_in_fpr_p ( ) ) return false ;

return ( cfun -> machine -> frame . total_size == <NUM_LIT> && ! cfun -> machine -> use_frame_header_for_callee_saved_regs ) ;


<s> SDValue Ops [ <NUM_LIT> ] ; std :: tie ( Ops [ <NUM_LIT> ] , Ops [ <NUM_LIT> ] ) = scalarizeVectorLoad ( Load , DAG ) ; return DAG . getMergeValues ( Ops , SL ) ; } SDValue BasePtr = Load -> getBasePtr ( ) ; EVT MemVT = Load -> getMemoryVT ( ) ; const MachinePointerInfo & SrcValue = Load -> getMemOperand ( ) -> getPointerInfo ( ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = getSplitDestVTs ( VT , DAG ) ; std :: tie ( LoMemVT , HiMemVT ) = getSplitDestVTs ( MemVT , DAG ) ; std :: tie ( Lo , Hi ) = splitVector ( Op , SL , LoVT , HiVT , DAG ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned BaseAlign = Load -> getAlignment ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , LoVT , Load -> getChain ( ) , BasePtr , SrcValue , LoMemVT , BaseAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HiPtr = DAG . getObjectPtrOffset ( SL , BasePtr , Size ) ; SDValue HiLoad = DAG . getExtLoad ( Load -> getExtensionType ( ) , SL , HiVT , Load -> getChain ( ) , HiPtr , SrcValue . getWithOffset ( LoMemVT . getStoreSize ( ) ) , HiMemVT , HiAlign , Load -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue Join ;


<s> StringRef getPassName ( ) const override {


<s> bool isPICStyleStubNoDynamic ( ) const { return PICStyle == PICStyles :: StubDynamicNoPIC ;


<s> } else return NULL_RTX ; } else if ( CONSTANT_P ( addr ) ) addr = frv_ifcvt_load_value ( addr , insn ) ; else return NULL_RTX ; if ( addr == NULL_RTX ) return NULL_RTX ;

else if ( XEXP ( mem , <NUM_LIT> ) != addr ) return change_address ( mem , mode , addr ) ;


<s> std :: string DataLayout = std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> <STR_LIT> ) ; if ( hasHWFP64 ( ) ) { DataLayout . append ( <STR_LIT> ) ; } if ( is64bit ( ) ) { DataLayout . append ( <STR_LIT> ) ; } else { DataLayout . append ( <STR_LIT> ) ;


<s> gcc_assert ( GET_MODE_CLASS ( mode ) == MODE_VECTOR_BOOL && mode == GET_MODE ( pred1 [ <NUM_LIT> ] ) && aarch64_sve_gp_strictness ( pred1 [ <NUM_LIT> ] , SImode ) ) ;

return ( pred1 [ <NUM_LIT> ] == CONSTM1_RTX ( mode ) || INTVAL ( pred1 [ <NUM_LIT> ] ) == SVE_RELAXED_GP || rtx_equal_p ( pred1 [ <NUM_LIT> ] , pred2 ) ) ;


<s> return <ISA_LIT>Lowering . SelectAddressRegImm ( N , Disp , Base , * CurDAG , false ) ;


<s> static rtx mips16_stub_function ( const char * name ) { rtx x ; x = gen_rtx_SYMBOL_REF ( Pmode , ggc_strdup ( name ) ) ; SYMBOL_REF_FLAGS ( x ) |= ( SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION ) ; return x ;


<s> const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ; int64_t Value = CE -> getValue ( ) ;

return Value >= <NUM_LIT> && Value <= <NUM_LIT> ;


<s> if ( Opcode == Instruction :: And ) { if ( Imm == <NUM_LIT> || Imm == <NUM_LIT> ) return <NUM_LIT> ; return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( ~ Imm , Ty , CostKind ) ) ; } if ( Opcode == Instruction :: Add ) return std :: min ( getIntImmCost ( Imm , Ty , CostKind ) , getIntImmCost ( - Imm , Ty , CostKind ) ) ; if ( Opcode == Instruction :: ICmp && Imm . isNegative ( ) && Ty -> getIntegerBitWidth ( ) == <NUM_LIT> ) { int64_t NegImm = - Imm . getSExtValue ( ) ; if ( ST -> isThumb2 ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; if ( ST -> isThumb ( ) && NegImm < <NUM_LIT> << <NUM_LIT> ) return <NUM_LIT> ; }

if ( Opcode == Instruction :: Xor && Imm . isAllOnesValue ( ) ) return <NUM_LIT> ;


<s> if ( Op . isReg ( ) ) Op . setIsKill ( false ) ; return Op ;


<s> } , [ = ] ( MachineInstrBuilder & MIB ) { const MachineMemOperand * MMO = * MI -> memoperands_begin ( ) ; const MachinePointerInfo & PtrInfo = MMO -> getPointerInfo ( ) ; if ( isStackPtrRelative ( PtrInfo ) ) MIB . addReg ( Info -> getStackPtrOffsetReg ( ) ) ; else MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset & <NUM_LIT> ) ; } } } ; } assert ( Offset == <NUM_LIT> || Offset == - <NUM_LIT> ) ; Optional < int > FI ; Register VAddr = Root . getReg ( ) ; if ( const MachineInstr * RootDef = MRI -> getVRegDef ( Root . getReg ( ) ) ) { if ( isBaseWithConstantOffset ( Root , * MRI ) ) { const MachineOperand & LHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineOperand & RHS = RootDef -> getOperand ( <NUM_LIT> ) ; const MachineInstr * LHSDef = MRI -> getVRegDef ( LHS . getReg ( ) ) ; const MachineInstr * RHSDef = MRI -> getVRegDef ( RHS . getReg ( ) ) ; if ( LHSDef && RHSDef ) { int64_t PossibleOffset = RHSDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; if ( <ISA_LIT>InstrInfo :: isLegalMUBUFImmOffset ( PossibleOffset ) && ( ! STI . privateMemoryResourceIsRangeChecked ( ) || KnownBits -> signBitIsZero ( LHS . getReg ( ) ) ) ) { if ( LHSDef -> getOpcode ( ) == <STR_LIT> ) FI = LHSDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; else VAddr = LHS . getReg ( ) ; Offset = PossibleOffset ; } } } else if ( RootDef -> getOpcode ( ) == <STR_LIT> ) { FI = RootDef -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; } } return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( Info -> getScratchRSrcReg ( ) ) ; } , [ = ] ( MachineInstrBuilder & MIB ) {

if ( FI . hasValue ( ) ) MIB . addFrameIndex ( FI . getValue ( ) ) ;


<s> if ( ( ( Subtarget . hasSSSE3 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) || ( Subtarget . hasInt256 ( ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) ) && isHorizontalBinOp ( Op0 , Op1 , true ) ) return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , Op0 , Op1 ) ;

return OptimizeConditionalInDecrement ( N , DAG ) ;


<s> vec_short8 hi , lo ; hi = ( vec_short8 ) ( spu_sl ( spu_add ( spu_mule ( a , b ) , round ) , <NUM_LIT> ) ) ;

lo = ( vec_short8 ) ( spu_rlmask ( spu_add ( spu_mulo ( a , b ) , round ) , - <NUM_LIT> ) ) ;


<s> for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; TargetRegisterClass * RC = VA . getLocReg ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( RC -> contains ( VA . getLocReg ( ) ) && <STR_LIT> ) ; assert ( RC -> hasType ( RegVT ) && <STR_LIT> ) ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( VA . getLocReg ( ) , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } else {

assert ( VA . isMemLoc ( ) && <STR_LIT> ) ;


<s> emit_insn ( gen_sse2_lshrv1ti3 ( tmp2 , op1 , GEN_INT ( <NUM_LIT> - bits ) ) ) ; emit_insn ( gen_iorv1ti3 ( tmp3 , tmp1 , tmp2 ) ) ; emit_move_insn ( operands [ <NUM_LIT> ] , tmp3 ) ; return ; } rtx op1_v4si = force_reg ( V4SImode , gen_lowpart ( V4SImode , op1 ) ) ; rtx lobits ; rtx hibits ; switch ( bits >> <NUM_LIT> ) { case <NUM_LIT> : lobits = op1_v4si ; hibits = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_pshufd ( hibits , op1_v4si , GEN_INT ( <NUM_LIT> ) ) ) ; break ; case <NUM_LIT> : lobits = gen_reg_rtx ( V4SImode ) ; hibits = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_pshufd ( lobits , op1_v4si , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_sse2_pshufd ( hibits , op1_v4si , GEN_INT ( <NUM_LIT> ) ) ) ; break ; case <NUM_LIT> : lobits = gen_reg_rtx ( V4SImode ) ; hibits = gen_reg_rtx ( V4SImode ) ; emit_insn ( gen_sse2_pshufd ( lobits , op1_v4si , GEN_INT ( <NUM_LIT> ) ) ) ; emit_insn ( gen_sse2_pshufd ( hibits , op1_v4si , GEN_INT ( <NUM_LIT> ) ) ) ; break ; default : lobits = gen_reg_rtx ( V4SImode ) ;


<s> std_expand_builtin_va_start ( valist , nextarg ) ;


<s> const DataLayout & DL = GV -> getParent ( ) -> getDataLayout ( ) ; if ( GVKind . isCommon ( ) || GVKind . isBSSLocal ( ) ) { unsigned Align = GV -> getAlignment ( ) ? GV -> getAlignment ( ) : DL . getPreferredAlignment ( GV ) ; uint64_t Size = DL . getTypeAllocSize ( GV -> getType ( ) -> getElementType ( ) ) ; if ( GVKind . isBSSLocal ( ) ) OutStreamer -> EmitXCOFFLocalCommonSymbol ( GVSym , Size , Csect -> getQualNameSymbol ( ) , Align ) ; else OutStreamer -> EmitCommonSymbol ( Csect -> getQualNameSymbol ( ) , Size , Align ) ;


<s> unsigned getNumFixupKinds ( ) const { return <STR_LIT> ;


<s> static DecodeStatus DecodePredRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { bool flag = RegNo >> <NUM_LIT> ; unsigned reg = RegNo & <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateReg ( PRegsTable [ reg ] ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( flag ) ) ;


<s> default : return new AMDGPU7XXDevice ( ptr ) ; } } else if ( deviceName == <STR_LIT> ) { assert ( ! is64bit && <STR_LIT> ) ; assert ( ! is64on32bit && <STR_LIT> <STR_LIT> ) ; return new AMDGPUCypressDevice ( ptr ) ; } else if ( deviceName == <STR_LIT> ) { assert ( ! is64bit && <STR_LIT> ) ; assert ( ! is64on32bit && <STR_LIT> <STR_LIT> ) ; return new AMDGPUEvergreenDevice ( ptr ) ; } else if ( deviceName == <STR_LIT> ) { assert ( ! is64bit && <STR_LIT> ) ; assert ( ! is64on32bit && <STR_LIT> <STR_LIT> ) ; return new AMDGPURedwoodDevice ( ptr ) ; } else if ( deviceName == <STR_LIT> ) { assert ( ! is64bit && <STR_LIT> ) ; assert ( ! is64on32bit && <STR_LIT> <STR_LIT> ) ; return new AMDGPUCedarDevice ( ptr ) ; } else if ( deviceName == <STR_LIT> || deviceName == <STR_LIT> ) { assert ( ! is64bit && <STR_LIT> ) ; assert ( ! is64on32bit && <STR_LIT> <STR_LIT> ) ; return new AMDGPUNIDevice ( ptr ) ; } else if ( deviceName == <STR_LIT> ) { assert ( ! is64bit && <STR_LIT> ) ; assert ( ! is64on32bit && <STR_LIT> <STR_LIT> ) ; return new AMDGPUCaymanDevice ( ptr ) ; } else if ( deviceName == <STR_LIT> ) {


<s> type_suffix_index suffix = parse_element_type ( instance , format ) ; return find_type_suffix ( type_suffixes [ suffix ] . tclass , type_suffixes [ suffix ] . element_bits / <NUM_LIT> ) ; } if ( ch == 'h' ) { type_suffix_index suffix = parse_element_type ( instance , format ) ; if ( suffix == TYPE_SUFFIX_b ) return suffix ; return find_type_suffix ( type_suffixes [ suffix ] . tclass , type_suffixes [ suffix ] . element_bits / <NUM_LIT> ) ; } if ( ch == '0' || ch == '1' ) return instance . type_suffix_ids [ ch - '0' ] ; gcc_unreachable ( ) ;


return ( int ) __builtin_ia32_vcvtss2si32 ( ( __v4sf ) __A , __R ) ;


<s> MachineInstr * UserMI = U . MI ; MachineInstr * CPEMI = U . CPEMI ; unsigned CPI = CPEMI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned Size = CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned UserOffset = getUserOffset ( U ) ; int result = findInRangeCPEntry ( U , UserOffset ) ; if ( result == <NUM_LIT> ) return false ; else if ( result == <NUM_LIT> ) return true ; MachineBasicBlock * NewIsland = MF -> CreateMachineBasicBlock ( ) ; MachineBasicBlock * NewMBB ; water_iterator IP ; if ( findAvailableWater ( U , UserOffset , IP ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; MachineBasicBlock * WaterBB = * IP ; if ( NewWaterList . erase ( WaterBB ) ) NewWaterList . insert ( NewIsland ) ; NewMBB = & * ++ WaterBB -> getIterator ( ) ; } else { if ( ! NoLoadRelaxation ) { result = findLongFormInRangeCPEntry ( U , UserOffset ) ; if ( result != <NUM_LIT> ) return true ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; createNewWater ( CPUserIndex , UserOffset , NewMBB ) ; MachineBasicBlock * WaterBB = & * -- NewMBB -> getIterator ( ) ; IP = llvm :: find ( WaterList , WaterBB ) ;

if ( IP != WaterList . end ( ) ) NewWaterList . erase ( WaterBB ) ;


<s> MachineBasicBlock * getSucc ( ) { return Succ ;


<s> } insn_change_watermark watermark ; validate_change ( rinsn , & PATTERN ( rinsn ) , new_pat , true ) ; if ( ! recog ( attempt , change ) || ! change_is_worthwhile ( change , false ) ) return false ; remove_reg_equal_equiv_notes ( rinsn ) ; confirm_change_group ( ) ;


<s> if ( is_arch && ( ARCH_AVR2 == arch_id || ARCH_AVR25 == arch_id ) ) { sp8_spec = <STR_LIT> ; } else { sp8_spec = sp8 ? <STR_LIT> : <STR_LIT> ; } fprintf ( f , <STR_LIT> <STR_LIT> ) ; if ( is_arch ) fprintf ( f , <STR_LIT> , arch -> name ) ; else fprintf ( f , <STR_LIT> , mcu -> name , arch -> name , sp8 ? <NUM_LIT> : <NUM_LIT> ) ; fprintf ( f , <STR_LIT> , header ) ; if ( is_device ) fprintf ( f , <STR_LIT> , help_copy_paste ) ; if ( is_device ) { fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , mcu -> name ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> ) ; fprintf ( f , <STR_LIT> , mcu -> name ) ; fprintf ( f , <STR_LIT> ) ; } int n_flash = <NUM_LIT> + ( mcu -> flash_size - <NUM_LIT> ) / <NUM_LIT> ; fprintf ( f , <STR_LIT> <STR_LIT> , n_flash ) ; fprintf ( f , <STR_LIT> , rmw ? <STR_LIT> : <STR_LIT> ) ; fprintf ( f , <STR_LIT> , errata_skip ? <STR_LIT> : <STR_LIT> ) ; fprintf ( f , <STR_LIT> , absdata ? <STR_LIT> : <STR_LIT> ) ; fprintf ( f , <STR_LIT> , arch -> name ) ; fprintf ( f , <STR_LIT> , ASM_RELAX_SPEC ) ; fprintf ( f , <STR_LIT> , rmw ? <STR_LIT> : <STR_LIT> ) ;


<s> SDValue addV = DAG . getNode ( <STR_LIT> , DL , RHS . getValueType ( ) , LHS , RHS . getOperand ( <NUM_LIT> ) ) ; return DAG . getSetCC ( DL , N -> getValueType ( <NUM_LIT> ) , addV , DAG . getConstant ( <NUM_LIT> , DL , addV . getValueType ( ) ) , CC ) ; } if ( VT . getScalarType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> || <STR_LIT> ( CC ) ) ) { bool IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; bool IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; if ( ! IsSEXT0 || ! IsVZero1 ) { std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ( CC ) ; IsSEXT0 = ( LHS . getOpcode ( ) == <STR_LIT> ) && ( LHS . getOperand ( <NUM_LIT> ) . getValueType ( ) . getScalarType ( ) == <STR_LIT> ) ; IsVZero1 = <STR_LIT> ( RHS . getNode ( ) ) ; }


<s> case <STR_LIT> : case <STR_LIT> : addRegOffset ( MIB , InRegLEA , true , MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Src2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool IsKill2 = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; assert ( ! MI . getOperand ( <NUM_LIT> ) . isUndef ( ) && <STR_LIT> ) ; unsigned InRegLEA2 = <NUM_LIT> ; MachineInstr * InsMI2 = nullptr ; if ( Src == Src2 ) { addRegReg ( MIB , InRegLEA , true , InRegLEA , false ) ; } else { if ( Subtarget . is64Bit ( ) ) InRegLEA2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; else InRegLEA2 = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MFI , & * MIB , MI . getDebugLoc ( ) , get ( <STR_LIT> ) , InRegLEA2 ) ; InsMI2 = BuildMI ( * MFI , & * MIB , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( InRegLEA2 , RegState :: Define , SubReg ) . addReg ( Src2 , getKillRegState ( IsKill2 ) ) ; addRegReg ( MIB , InRegLEA , true , InRegLEA2 , true ) ; } if ( LV && IsKill2 && InsMI2 ) LV -> replaceKillInstruction ( Src2 , MI , * InsMI2 ) ; break ; } } MachineInstr * NewMI = MIB ; MachineInstr * ExtMI = BuildMI ( * MFI , MBBI , MI . getDebugLoc ( ) , get ( TargetOpcode :: COPY ) ) . addReg ( Dest , RegState :: Define | getDeadRegState ( IsDead ) ) . addReg ( OutRegLEA , RegState :: Kill , SubReg ) ; if ( LV ) {

LV -> getVarInfo ( InRegLEA ) . Kills . push_back ( NewMI ) ;


<s> bool evaluateBranch ( const MCInst & Inst , uint64_t Addr , uint64_t Size , uint64_t & Target ) const override { if ( Inst . getNumOperands ( ) == <NUM_LIT> ) return false ; if ( Info -> get ( Inst . getOpcode ( ) ) . OpInfo [ <NUM_LIT> ] . OperandType == MCOI :: OPERAND_PCREL ) { int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; Target = Addr + Size + Imm ; return true ; } else { int64_t Imm = Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Imm == <NUM_LIT> ) return false ; Target = Imm ; return true ;


<s> return __builtin_loongson_paddw_s ( s , t ) ;


return ( __m256 ) __builtin_ia32_broadcastf32x4_256_mask ( ( __v4sf ) __A , ( __v8sf ) _mm256_undefined_pd ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> MCOperand <ISA_LIT>MCInstLower :: LowerSymbolOperand ( const MachineOperand & MO , MCSymbol * Sym ) const { const MCExpr * Expr = MCSymbolRefExpr :: Create ( Sym , Ctx ) ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ;


<s> const TargetOptions & Options = getTargetMachine ( ) . Options ; EVT VT = getValueType ( User -> getOperand ( <NUM_LIT> ) -> getType ( ) ) ; if ( isFMAFasterThanFMulAndFAdd ( VT ) && isOperationLegalOrCustom ( <STR_LIT> , VT ) && ( Options . AllowFPOpFusion == FPOpFusion :: Fast || Options . UnsafeFPMath ) ) return false ;


<s> SDValue Ptr = lowerKernArgParameterPtr ( DAG , DL , DAG . getEntryNode ( ) , Offset ) ; MachinePointerInfo PtrInfo ( <ISA_LIT>AS :: CONSTANT_ADDRESS ) ;

return DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , PtrInfo , Alignment , MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant ) ;


<s> bool doInitialization ( Loop * L , LPPassManager & LPM ) override { LoadPairs . clear ( ) ; WideLoads . clear ( ) ; return true ;


<s> EmitByte ( INSTR_ALU , OS ) ; uint64_t InstWord01 = getBinaryCodeForInstr ( MI , Fixups ) ; if ( ( STI . getFeatureBits ( ) & AMDGPU :: FeatureR600ALUInst ) && ! ( MCDesc . TSFlags & <STR_LIT> ) ) { uint64_t ISAOpCode = InstWord01 & ( <NUM_LIT> << <NUM_LIT> ) ; InstWord01 &= ~ ( <NUM_LIT> << <NUM_LIT> ) ; InstWord01 |= ISAOpCode << <NUM_LIT> ; }

unsigned SrcNum = MCDesc . TSFlags & <STR_LIT> ? <NUM_LIT> :


<s> static void frv_output_dwarf_dtprel ( FILE * file , int size , rtx x ) { gcc_assert ( size == <NUM_LIT> ) ;


return ( ( unsigned long long ) __builtin_sh_media_MMACNFX_WL ( ( v2hi ) mm_l , ( v2hi ) mn_l , ( uv2si ) mw ) ) ;


<s> } } ; static const StringRef HSAIntrinsicToAttr [ ] [ <NUM_LIT> ] = { { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } ; bool Changed = addAttrsForIntrinsics ( M , IntrinsicToAttr ) ; if ( TT . getOS ( ) == Triple :: AMDHSA ) { Changed |= addAttrsForIntrinsics ( M , HSAIntrinsicToAttr ) ; for ( Function & F : M ) {

if ( F . hasFnAttribute ( <STR_LIT> ) ) continue ;


<s> const <ISA_LIT>Subtarget & SubtargetA = a . getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>Subtarget & SubtargetB = b . getMF ( ) -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;

return SubtargetA . hasV8_3aOps ( ) == SubtargetB . hasV8_3aOps ( ) ;


<s> if ( TREE_CODE ( type ) == VECTOR_TYPE ) { if ( ( TARGET_SPE && SPE_VECTOR_MODE ( TYPE_MODE ( type ) ) ) || ( TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE ( TYPE_MODE ( type ) ) ) ) { if ( align < <NUM_LIT> ) align = <NUM_LIT> ;


<s> DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MF , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; for ( unsigned i = <NUM_LIT> , e = Addr . size ( ) ; i != e ; ++ i ) MIB . addOperand ( Addr [ i ] ) ;


<s> while ( Op . getOpcode ( ) == <STR_LIT> ) Op = Op . getOperand ( <NUM_LIT> ) ; BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( Op . getNode ( ) ) ;


<s> case REG : case SUBREG : info -> type = ADDRESS_REG ; info -> reg = x ; info -> offset = const0_rtx ; return riscv_valid_base_register_p ( info -> reg , mode , strict_p ) ; case PLUS : info -> type = ADDRESS_REG ; info -> reg = XEXP ( x , <NUM_LIT> ) ;

info -> offset = XEXP ( x , <NUM_LIT> ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; Chain = DAG . getCALLSEQ_START ( Chain , DAG . getConstant ( NumBytes , getPointerTy ( ) , true ) ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; int Offset = VA . getLocMemOffset ( ) ; MemOpChains . push_back ( DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Arg , DAG . getConstant ( Offset / <NUM_LIT> , <STR_LIT> ) ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ;


<s> void setCalleeSavedFrameSize ( unsigned bytes ) {


<s> operands [ <NUM_LIT> ] = gen_rtx_REG ( SImode , re_callee_saved ) ; sp_adjust = cfun -> machine -> local_size + cfun -> machine -> out_args_size + cfun -> machine -> callee_saved_area_gpr_padding_bytes + cfun -> machine -> callee_saved_fpr_regs_size ; if ( satisfies_constraint_Iu08 ( GEN_INT ( sp_adjust ) ) && NDS32_DOUBLE_WORD_ALIGN_P ( sp_adjust ) && ! cfun -> calls_alloca ) operands [ <NUM_LIT> ] = GEN_INT ( sp_adjust ) ; else operands [ <NUM_LIT> ] = GEN_INT ( <NUM_LIT> ) ; snprintf ( pattern , sizeof ( pattern ) , <STR_LIT> ) ; output_asm_insn ( pattern , operands ) ; return <STR_LIT> ;


<s> return MachinePointerInfo ( MF . getPSVManager ( ) . getGlobalValueCallEntry ( GV ) ) ;


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; WhichResult = ( M [ <NUM_LIT> ] == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; i += <NUM_LIT> ) { if ( ( M [ i ] >= <NUM_LIT> && ( unsigned ) M [ i ] != i + WhichResult ) || ( M [ i + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + <NUM_LIT> ] != i + WhichResult ) ) return false ; } return true ;


<s> if ( PIdx == - <NUM_LIT> ) { PredReg = <NUM_LIT> ; return <STR_LIT> ; }

PredReg = MI . getOperand ( PIdx + <NUM_LIT> ) . getReg ( ) ;


<s> MachineInstr & MI = * MBBI ; unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; uint64_t Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( DstReg == <STR_LIT> || DstReg == <STR_LIT> ) { MI . eraseFromParent ( ) ; return true ; } SmallVector < <ISA_LIT>_IMM :: ImmInsnModel , <NUM_LIT> > Insn ; <ISA_LIT>_IMM :: expandMOVImm ( Imm , BitSize , Insn ) ; assert ( Insn . size ( ) != <NUM_LIT> ) ; SmallVector < MachineInstrBuilder , <NUM_LIT> > MIBS ; for ( auto I = Insn . begin ( ) , E = Insn . end ( ) ; I != E ; ++ I ) { bool LastItem = std :: next ( I ) == E ; switch ( I -> Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( BitSize == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addImm ( I -> Op2 ) ) ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && LastItem ) ) . addImm ( I -> Op1 ) . addImm ( I -> Op2 ) ) ; } break ; case <STR_LIT> : case <STR_LIT> : { unsigned DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; MIBS . push_back ( BuildMI ( MBB , MBBI , MI . getDebugLoc ( ) , TII -> get ( I -> Opcode ) ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead && LastItem ) ) . addReg ( DstReg ) . addImm ( I -> Op1 ) . addImm ( I -> Op2 ) ) ; } break ; } } transferImpOps ( MI , MIBS . front ( ) , MIBS . back ( ) ) ; MI . eraseFromParent ( ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> TmpInst . addOperand ( MCOperand :: createImm ( Imm1 ) ) ;

TmpInst . addOperand ( MCOperand :: createImm ( Imm2 ) ) ;


<s> break ; } case <STR_LIT> : { StoreSDNode * SD = dyn_cast < StoreSDNode > ( Parent ) ; switch ( SD -> getMemoryVT ( ) . getSizeInBits ( ) ) { case <NUM_LIT> : case <NUM_LIT> : AliasReg = TM . getFrameLowering ( ) -> hasFP ( * MF ) ? AliasFPReg : get<ISA_LIT>16SPAliasReg ( ) ; return ; } break ;


<s> static <ISA_LIT>Operand CreateReg ( unsigned RegNo ) { <ISA_LIT>Operand Res ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI , bool IsILP32 ) : MCELFObjectTargetWriter ( ! IsILP32 , OSABI , ELF :: EM_AARCH64 , true ) , IsILP32 ( IsILP32 ) {


<s> void <ISA_LIT>InstPrinter :: printExpSrc1 ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {

printExpSrcN ( MI , OpNo , STI , O , <NUM_LIT> ) ;


<s> static void nds32_option_override ( void ) { if ( TARGET_ISA_V2 ) { target_flags &= ~ MASK_V3PUSH ; } if ( TARGET_ISA_V3 ) { if ( nds32_arch_option == ARCH_V3J ) target_flags |= MASK_REDUCED_REGS ; } if ( TARGET_ISA_V3M ) { target_flags |= MASK_REDUCED_REGS ; target_flags &= ~ MASK_EXT_PERF ; target_flags &= ~ MASK_EXT_PERF2 ; target_flags &= ~ MASK_EXT_STRING ; if ( flag_pic ) error ( <STR_LIT> ) ; } if ( TARGET_REDUCED_REGS ) { int r ; for ( r = <NUM_LIT> ; r <= <NUM_LIT> ; r ++ ) fixed_regs [ r ] = call_used_regs [ r ] = <NUM_LIT> ; for ( r = <NUM_LIT> ; r <= <NUM_LIT> ; r ++ ) fixed_regs [ r ] = call_used_regs [ r ] = <NUM_LIT> ; } if ( TARGET_FORCE_FP_AS_GP ) fixed_regs [ FP_REGNUM ] = call_used_regs [ FP_REGNUM ] = <NUM_LIT> ; if ( ! TARGET_16_BIT ) { target_flags &= ~ MASK_V3PUSH ; } if ( TARGET_HARD_FLOAT && ! ( TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE ) ) { if ( nds32_arch_option == ARCH_V3S || nds32_arch_option == ARCH_V3F ) error ( <STR_LIT> <STR_LIT> ) ; else error ( <STR_LIT> <STR_LIT> ) ; }


<s> TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: Fast , RetTy , Callee , & Args , <NUM_LIT> ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; return CallResult . first ;


<s> bool hasFastHorizontalOps ( ) const {


<s> if ( NVOpcode >= <NUM_LIT> ) return NVOpcode ; switch ( MI -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> const TargetOperandInfo & TOI = MI -> getDesc ( ) . OpInfo [ opNum ] ;

const TargetRegisterClass * RC = TOI . getRegClass ( TRI ) ;


<s> if ( CC == <STR_LIT> ) { if ( EFLAGS . getOpcode ( ) == <STR_LIT> && EFLAGS . hasOneUse ( ) && EFLAGS . getValueType ( ) . isInteger ( ) && ! isa < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ) { SDValue NewSub = DAG . getNode ( <STR_LIT> , SDLoc ( EFLAGS ) , EFLAGS . getNode ( ) -> getVTList ( ) , EFLAGS . getOperand ( <NUM_LIT> ) , EFLAGS . getOperand ( <NUM_LIT> ) ) ; SDValue NewEFLAGS = SDValue ( NewSub . getNode ( ) , EFLAGS . getResNo ( ) ) ; return MaterializeSETB ( DL , NewEFLAGS , DAG , N -> getSimpleValueType ( <NUM_LIT> ) ) ; } } if ( CC == <STR_LIT> ) return MaterializeSETB ( DL , EFLAGS , DAG , N -> getSimpleValueType ( <NUM_LIT> ) ) ; if ( SDValue Flags = checkBoolTestSetCCCombine ( EFLAGS , CC ) ) { SDValue Cond = DAG . getConstant ( CC , DL , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , N -> getVTList ( ) , Cond , Flags ) ;


<s> unsigned Shift = ( NumLaneElts == <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; unsigned Mask = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { int Elt = N -> getMaskElt ( i ) ; if ( Elt < <NUM_LIT> ) continue ; Elt &= NumLaneElts - <NUM_LIT> ; unsigned ShAmt = ( i << Shift ) % <NUM_LIT> ; Mask |= Elt << ShAmt ; } return Mask ;


<s> if ( slice ( insn , <NUM_LIT> , <NUM_LIT> ) == <NUM_LIT> ) { d = decodeVFPRd ( insn , true ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , d ) ) ) ; m = decodeVFPRm ( insn , SP ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassID , m ) ) ) ; } else { d = decodeVFPRd ( insn , SP ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClassID , d ) ) ) ; m = decodeVFPRm ( insn , true ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , m ) ) ) ; }


<s> MaxJumpTableSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case Falkor : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; break ; case Kryo : MaxInterleaveFactor = <NUM_LIT> ; VectorInsertExtractBaseCost = <NUM_LIT> ; CacheLineSize = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case NeoverseE1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case NeoverseN1 : PrefFunctionLogAlignment = <NUM_LIT> ; break ; case Saphira : MaxInterleaveFactor = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX2T99 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MaxInterleaveFactor = <NUM_LIT> ; PrefetchDistance = <NUM_LIT> ; MinPrefetchStride = <NUM_LIT> ; MaxPrefetchIterationsAhead = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case ThunderX : case ThunderXT88 : case ThunderXT81 : case ThunderXT83 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; MinVectorRegisterBitWidth = <NUM_LIT> ; break ; case TSV110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ; PrefLoopLogAlignment = <NUM_LIT> ; break ; case ThunderX3T110 : CacheLineSize = <NUM_LIT> ; PrefFunctionLogAlignment = <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : { const MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; if ( Dst . isReg ( ) && Dst . getReg ( ) == ( ST . isWave32 ( ) ? <STR_LIT> : <STR_LIT> ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) ) return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } case <STR_LIT> : case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; }


<s> uint64_t Disp = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; uint64_t Len = getMachineOpValue ( MI , MI . getOperand ( OpNum + <NUM_LIT> ) , Fixups , STI ) ; assert ( isUInt < <NUM_LIT> > ( Base ) && isUInt < <NUM_LIT> > ( Disp ) && isUInt < <NUM_LIT> > ( Len ) ) ;

return ( Len << <NUM_LIT> ) | ( Base << <NUM_LIT> ) | Disp ;


<s> const TargetRegisterClass * RC ; std :: string Prefix ; unsigned long long Reg ; std :: pair < bool , bool > R = parsePhysicalReg ( C , Prefix , Reg ) ; if ( ! R . first ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( ( Prefix == <STR_LIT> || Prefix == <STR_LIT> ) ) { if ( R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; RC = TRI -> getRegClass ( Prefix == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; return std :: make_pair ( * ( RC -> begin ( ) ) , RC ) ; } if ( ! R . second ) return std :: make_pair ( <NUM_LIT> , nullptr ) ; if ( Prefix == <STR_LIT> ) { if ( VT == <STR_LIT> ) VT = ( Subtarget . isFP64bit ( ) || ! ( Reg % <NUM_LIT> ) ) ? <STR_LIT> : <STR_LIT> ; RC = getRegClassFor ( VT ) ;


<s> EVT LoadedVT = LD -> getMemoryVT ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Base ) -> getOffset ( ) ; if ( Offset != <NUM_LIT> && OffsetFitsS11 ( LoadedVT , Offset ) ) { MVT PointerTy = TLI -> getPointerTy ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Base ) -> getGlobal ( ) ; SDValue TargAddr = CurDAG -> getTargetGlobalAddress ( GV , dl , PointerTy , <NUM_LIT> ) ; SDNode * NewBase = CurDAG -> getMachineNode ( <STR_LIT> , dl , PointerTy , TargAddr ) ; if ( LoadedVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( LoadedVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( LoadedVT == <STR_LIT> ) Opcode = <STR_LIT> ; else if ( LoadedVT == <STR_LIT> ) Opcode = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; SDValue TargetConstOff = CurDAG -> getTargetConstant ( Offset , PointerTy ) ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , LD -> getValueType ( <NUM_LIT> ) , <STR_LIT> , SDValue ( NewBase , <NUM_LIT> ) , TargetConstOff , Chain ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ;

MemOp [ <NUM_LIT> ] = LD -> getMemOperand ( ) ;


<s> if ( ! Flags . isSRet ( ) ) { return NotStructReturn ; } if ( Flags . isInReg ( ) ) { return RegStructReturn ; } return StackStructReturn ;


<s> static inline bool UsesMaskPolicy ( uint64_t TSFlags ) { return TSFlags & UsesMaskPolicyMask ;


<s> getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( Name . consume_front ( <STR_LIT> ) ) { lmul = APInt ( <NUM_LIT> , Name , <NUM_LIT> ) ; if ( lmul != <NUM_LIT> && lmul != <NUM_LIT> && lmul != <NUM_LIT> && lmul != <NUM_LIT> ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; if ( getLexer ( ) . is ( AsmToken :: EndOfStatement ) ) { Operands . push_back ( <ISA_LIT>Operand :: createVTypeImm ( sew , lmul , ediv , S , isRV64 ( ) ) ) ; return MatchOperand_Success ; } } if ( ! getLexer ( ) . is ( AsmToken :: Comma ) ) return MatchOperand_NoMatch ; getLexer ( ) . Lex ( ) ; Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; if ( Name . consume_front ( <STR_LIT> ) ) { ediv = APInt ( <NUM_LIT> , Name , <NUM_LIT> ) ; if ( ediv != <NUM_LIT> && ediv != <NUM_LIT> && ediv != <NUM_LIT> && ediv != <NUM_LIT> ) return MatchOperand_NoMatch ;


<s> void <ISA_LIT>ImmToReg :: printImmUse ( ) { dbgs ( ) << <STR_LIT> << <STR_LIT> ;


<s> const MCExpr * <ISA_LIT>_64MachoTargetObjectFile :: getTTypeGlobalReference ( const GlobalValue * GV , unsigned Encoding , Mangler & Mang , const TargetMachine & TM , MachineModuleInfo * MMI , MCStreamer & Streamer ) const { if ( ( Encoding & DW_EH_PE_indirect ) && ( Encoding & DW_EH_PE_pcrel ) ) { const MCSymbol * Sym = TM . getSymbol ( GV , Mang ) ; const MCExpr * Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_GOTPCREL , getContext ( ) ) ; const MCExpr * Four = MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) ; return MCBinaryExpr :: createAdd ( Res , Four , getContext ( ) ) ;


<s> return __builtin_aarch64_urshlv2si_uus ( __a , __b ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; const <ISA_LIT>Disassembler * Dis = static_cast < const <ISA_LIT>Disassembler * > ( Decoder ) ; unsigned Reg = Dis -> getReg ( <STR_LIT> , RegNo ) ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ;


<s> bool higherOccupancy ( const <ISA_LIT>Subtarget & ST , const GCNRegPressure & O ) const {

return getOccupancy ( ST ) > O . getOccupancy ( ST ) ;


<s> const MCSection * TheSection = OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MachO :: S_NON_LAZY_SYMBOL_POINTERS , SectionKind :: getMetadata ( ) ) ; OutStreamer . SwitchSection ( TheSection ) ; for ( auto & Stub : Stubs ) emitNonLazySymbolPointer ( OutStreamer , Stub . first , Stub . second ) ; Stubs . clear ( ) ; OutStreamer . AddBlankLine ( ) ; } SM . serializeToStackMapSection ( ) ; OutStreamer . EmitAssemblerFlag ( MCAF_SubsectionsViaSymbols ) ; } if ( Subtarget -> isTargetKnownWindowsMSVC ( ) && MMI -> usesVAFloatArgument ( ) ) { StringRef SymbolName = Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; MCSymbol * S = MMI -> getContext ( ) . GetOrCreateSymbol ( SymbolName ) ; OutStreamer . EmitSymbolAttribute ( S , MCSA_Global ) ; } if ( Subtarget -> isTargetCOFF ( ) ) { std :: vector < const MCSymbol * > DLLExportedFns , DLLExportedGlobals ; for ( const auto & Function : M ) if ( Function . hasDLLExportStorageClass ( ) && ! Function . isDeclaration ( ) ) DLLExportedFns . push_back ( getSymbol ( & Function ) ) ; for ( const auto & Global : M . globals ( ) ) if ( Global . hasDLLExportStorageClass ( ) && ! Global . isDeclaration ( ) ) DLLExportedGlobals . push_back ( getSymbol ( & Global ) ) ; for ( const auto & Alias : M . aliases ( ) ) { if ( ! Alias . hasDLLExportStorageClass ( ) ) continue ; if ( Alias . getType ( ) -> getElementType ( ) -> isFunctionTy ( ) ) DLLExportedFns . push_back ( getSymbol ( & Alias ) ) ; else DLLExportedGlobals . push_back ( getSymbol ( & Alias ) ) ;


<s> getParser ( ) . getStreamer ( ) . EmitAssemblerFlag ( isThumb ( ) ? MCAF_Code16 : MCAF_Code32 ) ; Warning ( Loc , Twine ( <STR_LIT> ) + ( WasThumb ? <STR_LIT> : <STR_LIT> ) + <STR_LIT> + ( ! WasThumb ? <STR_LIT> : <STR_LIT> ) + <STR_LIT> ) ; }


<s> if ( CurDAG -> isBaseWithConstantOffset ( Addr ) ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ; ConstantSDNode * C1 = cast < ConstantSDNode > ( N1 ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) { SDValue N2 = N0 . getOperand ( <NUM_LIT> ) ; SDValue N3 = N0 . getOperand ( <NUM_LIT> ) ; Addr64 = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N2 ; VAddr = N3 ; } else { VAddr = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; Ptr = N0 ; } if ( isLegalMUBUFImmOffset ( C1 ) ) { Offset = CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ; return ; } else if ( isUInt < <NUM_LIT> > ( C1 -> getZExtValue ( ) ) ) { Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ; SOffset = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , CurDAG -> getTargetConstant ( C1 -> getZExtValue ( ) , DL , <STR_LIT> ) ) , <NUM_LIT> ) ; return ; } } if ( Addr . getOpcode ( ) == <STR_LIT> ) { SDValue N0 = Addr . getOperand ( <NUM_LIT> ) ; SDValue N1 = Addr . getOperand ( <NUM_LIT> ) ;


<s> StructType * ST = cast < StructType > ( T ) ; if ( ST -> getNumElements ( ) != <NUM_LIT> ) break ;

if ( ( ST -> getElementType ( <NUM_LIT> ) -> isFloatTy ( ) ) && ( ST -> getElementType ( <NUM_LIT> ) -> isFloatTy ( ) ) ) return CFRet ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const GCNTargetMachine & TM ) : <ISA_LIT>Subtarget ( TT , GPU , FS , TM ) , InstrInfo ( * this ) , FrameLowering ( TargetFrameLowering :: StackGrowsUp , getStackAlignment ( ) , <NUM_LIT> ) , TLInfo ( TM , * this ) { CallLoweringInfo . reset ( new <ISA_LIT>CallLowering ( * getTargetLowering ( ) ) ) ; Legalizer . reset ( new <ISA_LIT>LegalizerInfo ( * this , TM ) ) ; RegBankInfo . reset ( new <ISA_LIT>RegisterBankInfo ( * getRegisterInfo ( ) ) ) ;

InstSelector . reset ( new <ISA_LIT>InstructionSelector ( * this , * static_cast < <ISA_LIT>RegisterBankInfo * > ( RegBankInfo . get ( ) ) ) ) ;


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount == <NUM_LIT> ) return MBB . erase ( I ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; const DebugLoc & DL = I -> getDebugLoc ( ) ; unsigned Opc = I -> getOpcode ( ) ; bool IsDestroy = Opc == TII -> getCallFrameDestroyOpcode ( ) ; uint64_t CalleePopAmount = IsDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ;


<s> } else { if ( standard_80387_constant_p ( op0 ) == <NUM_LIT> || ( MEM_P ( op0 ) && ! ( standard_80387_constant_p ( op1 ) == <NUM_LIT> || MEM_P ( op1 ) ) ) ) { enum rtx_code new_code = ix86_fp_swap_condition ( code ) ; if ( new_code != UNKNOWN ) { std :: swap ( op0 , op1 ) ; code = new_code ; } } if ( ! REG_P ( op0 ) ) op0 = force_reg ( op_mode , op0 ) ; if ( CONSTANT_P ( op1 ) ) { int tmp = standard_80387_constant_p ( op1 ) ; if ( tmp == <NUM_LIT> ) op1 = validize_mem ( force_const_mem ( op_mode , op1 ) ) ; else if ( tmp == <NUM_LIT> ) { if ( TARGET_CMOVE ) op1 = force_reg ( op_mode , op1 ) ; } else op1 = force_reg ( op_mode , op1 ) ; } } if ( ix86_fp_comparison_cost ( code ) > ix86_fp_comparison_cost ( swap_condition ( code ) ) && ( REG_P ( op1 ) || can_create_pseudo_p ( ) ) ) {


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const std :: string & TT , const std :: string & CPU , const std :: string & FS , TargetMachine & TM , bool LittleEndian ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , ARMProcFamily ( Others ) , HasFPARMv8 ( false ) , HasNEON ( false ) , HasCrypto ( false ) , HasCRC ( false ) , HasZeroCycleRegMove ( false ) , HasZeroCycleZeroing ( false ) , CPUString ( CPU ) , TargetTriple ( TT ) , DL ( isTargetMachO ( ) ? <STR_LIT> : ( LittleEndian ? <STR_LIT> : <STR_LIT> ) ) , FrameLowering ( ) , InstrInfo ( initializeSubtargetDependencies ( FS ) ) , TSInfo ( & DL ) , TLInfo ( TM ) {


<s> SDValue BasePtr = DAG . getCopyFromReg ( Chain , SL , MRI . getLiveInVirtReg ( InputPtrReg -> getRegister ( ) ) , PtrVT ) ; return DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( Offset , SL , PtrVT ) ) ;


<s> int hw_before , hw_after ; s390_function_num_hotpatch_hw ( decl , & hw_before , & hw_after ) ; if ( hw_before > <NUM_LIT> ) { unsigned int function_alignment ; int i ; asm_fprintf ( asm_out_file , <STR_LIT> <STR_LIT> , hw_before ) ; for ( i = <NUM_LIT> ; i < hw_before ; i ++ ) fputs ( <STR_LIT> , asm_out_file ) ; function_alignment = MAX ( <NUM_LIT> , DECL_ALIGN ( decl ) / BITS_PER_UNIT ) ; if ( ! DECL_USER_ALIGN ( decl ) ) function_alignment = MAX ( function_alignment , ( unsigned int ) align_functions ) ; fputs ( <STR_LIT> , asm_out_file ) ; ASM_OUTPUT_ALIGN ( asm_out_file , floor_log2 ( function_alignment ) ) ; } if ( S390_USE_TARGET_ATTRIBUTE && TARGET_DEBUG_ARG ) { asm_fprintf ( asm_out_file , <STR_LIT> , fname , s390_arch ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , s390_tune ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , s390_stack_guard ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , s390_stack_size ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , s390_branch_cost ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , s390_warn_framesize ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , TARGET_BACKCHAIN ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , TARGET_HARD_DFP ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , ! TARGET_SOFT_FLOAT ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , TARGET_OPT_HTM ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , TARGET_OPT_VX ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , TARGET_PACKED_STACK ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , TARGET_SMALL_EXEC ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , TARGET_MVCLE ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , TARGET_ZVECTOR ) ; asm_fprintf ( asm_out_file , <STR_LIT> , fname , s390_warn_dynamicstack_p ) ; }

ASM_OUTPUT_LABEL ( asm_out_file , fname ) ;


<s> ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregciv8qi ( __o , <NUM_LIT> ) ;


<s> if ( LHS . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( ! RHS . getNode ( ) ) { assert ( LHS . getValueType ( ) == Op . getValueType ( ) && <STR_LIT> ) ; return LHS ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue CCVal ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , <STR_LIT> ( CC , true ) , CCVal , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CCVal , Cmp ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> || LHS . getValueType ( ) == <STR_LIT> ) ; SDValue Cmp = emitComparison ( LHS , RHS , CC , dl , DAG ) ; <STR_LIT> CC1 , CC2 ; changeFPCCTo<ISA_LIT>CC ( CC , CC1 , CC2 ) ; if ( CC2 == <STR_LIT> ) { changeFPCCTo<ISA_LIT>CC ( <STR_LIT> ( CC , false ) , CC1 , CC2 ) ; SDValue CC1Val = DAG . getConstant ( CC1 , dl , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , dl , VT , FVal , TVal , CC1Val , Cmp ) ; } else { SDValue CC1Val = DAG . getConstant ( CC1 , dl , <STR_LIT> ) ; SDValue CS1 = DAG . getNode ( <STR_LIT> , dl , VT , TVal , FVal , CC1Val , Cmp ) ; SDValue CC2Val = DAG . getConstant ( CC2 , dl , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , TVal , CS1 , CC2Val , Cmp ) ;


<s> for ( unsigned j = <NUM_LIT> ; j != array_lengthof ( ViableForN ) ; ++ j ) if ( ViableForN [ j ] ) { uint64_t N = j + <NUM_LIT> ; if ( ( uint64_t ) Mask [ i ] == ( ( ( uint64_t ) i << N ) & ModMask ) ) IsAnyViable = true ; else ViableForN [ j ] = false ; } if ( ! IsAnyViable ) break ; }

for ( unsigned j = <NUM_LIT> ; j != array_lengthof ( ViableForN ) ; ++ j ) if ( ViableForN [ j ] ) return j + <NUM_LIT> ;


<s> if ( N . getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; OffImm = CurDAG -> getTargetConstant ( RHSC * ( <NUM_LIT> << Shift ) , SDLoc ( N ) , <STR_LIT> ) ; return true ; } }


<s> ret . val [ <NUM_LIT> ] = ( int8x8_t ) __builtin_aarch64_get_dregoiv8qi ( __o , <NUM_LIT> ) ; return ret ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; ParseSubtargetFeatures ( CPUName , FS ) ; return * this ;


<s> void asm_conditional_branch ( rtx insn , rtx * operands , int n_nops , int predict_taken ) { int offset = branch_dest ( insn ) - INSN_ADDRESSES ( INSN_UID ( insn ) ) ; int len = ( offset >= - <NUM_LIT> && offset <= <NUM_LIT> ? <NUM_LIT> : offset >= - <NUM_LIT> && offset <= <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; int bp = predict_taken && len == <NUM_LIT> ? <NUM_LIT> : cbranch_predicted_taken_p ( insn ) ; int idx = ( bp << <NUM_LIT> ) | ( GET_CODE ( operands [ <NUM_LIT> ] ) == EQ ? BRF : BRT ) ; output_asm_insn ( ccbranch_templates [ idx ] [ len ] , operands ) ;

gcc_assert ( n_nops == <NUM_LIT> || ! bp ) ;


<s> if ( T . empty ( ) ) return RegisterRef ( ) ; return RegisterRef ( T . begin ( ) -> first , T . begin ( ) -> second ) ;


<s> setAction ( { G_PHI , s64 } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB , G_MUL , G_AND , G_OR , G_XOR } ) setAction ( { BinOp , s64 } , Legal ) ; for ( unsigned MemOp : { G_LOAD , G_STORE } ) setAction ( { MemOp , s64 } , Legal ) ; setAction ( { G_GEP , <NUM_LIT> , s64 } , Legal ) ; getActionDefinitionsBuilder ( G_PTRTOINT ) . legalForCartesianProduct ( { s1 , s8 , s16 , s32 , s64 } , { p0 } ) . maxScalar ( <NUM_LIT> , s64 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_INTTOPTR ) . legalFor ( { { p0 , s64 } } ) ; setAction ( { TargetOpcode :: G_CONSTANT , s64 } , Legal ) ;

for ( unsigned extOp : { G_ZEXT , G_SEXT , G_ANYEXT } ) {


<s> int cris_legitimate_pic_operand ( rtx x ) {


<s> BB -> addSuccessor ( copy0MBB ) ; BB -> addSuccessor ( sinkMBB ) ; BuildMI ( BB , dl , TII -> get ( Opc2 ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( BB , dl , TII -> get ( Opc1 ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ; BuildMI ( * BB , BB -> begin ( ) , dl , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ; MI -> eraseFromParent ( ) ;


<s> a = ( __vector unsigned short ) vec_splats ( __A ) ; b = ( __vector unsigned short ) vec_splats ( __B ) ; w0 = vec_vmuleuh ( a , b ) ; w1 = vec_vmulouh ( a , b ) ;

c = ( __vector unsigned short ) vec_perm ( w0 , w1 , xform1 ) ;


<s> if ( EnableMCR ) addPass ( & MachineCombinerID ) ; if ( EnableCondBrTuning ) addPass ( create<ISA_LIT>CondBrTuning ( ) ) ; if ( EnableEarlyIfConversion ) addPass ( & EarlyIfConverterID ) ; if ( EnableStPairSuppress ) addPass ( create<ISA_LIT>StorePairSuppressPass ( ) ) ;

addPass ( create<ISA_LIT>SIMDInstrOptPass ( ) ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MII , unsigned SrcReg , bool isKill , int FrameIdx , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> DstA = decodeAField ( Insn ) ; DecodeGPR32RegisterClass ( Inst , DstA , Address , Decoder ) ; LImm = ( Insn >> <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( LImm ) ) ;

Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;


<s> case CmpInst :: ICMP_SGT : return <STR_LIT> ; case CmpInst :: ICMP_SGE : return <STR_LIT> ; case CmpInst :: ICMP_SLT : return <STR_LIT> ; case CmpInst :: ICMP_SLE : return <STR_LIT> ; case CmpInst :: ICMP_UGT : return <STR_LIT> ; case CmpInst :: ICMP_UGE : return <STR_LIT> ; case CmpInst :: ICMP_ULT : return <STR_LIT> ;


<s> if ( ! MayClobberFrom && ! MayClobberTo ) return false ; if ( ( MayClobberFrom && ! MayClobberTo ) || ( ! MayClobberFrom && MayClobberTo ) ) return true ; return ! ( ( MBBFrom == MBBTo && MDT . dominates ( Clobber , & * From ) && MDT . dominates ( Clobber , & * To ) ) || MDT . properlyDominates ( Clobber -> getParent ( ) , MBBTo ) ) ; } ; return ( llvm :: any_of ( Clobbers , interferes ) ) || ( llvm :: any_of ( Inits , [ & ] ( InitListMap :: value_type & C ) { return C . first != Init . first && llvm :: any_of ( C . second , interferes ) ; } ) ) ; } ; if ( MDT . dominates ( MI1 , MI2 ) ) { if ( ! intereferes ( MI2 , MI1 ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI2 -> getParent ( ) -> getNumber ( ) << <STR_LIT> << * MI2 ) ; MI2 -> eraseFromParent ( ) ; Defs . erase ( I2 ++ ) ; Changed = true ; continue ; } } else if ( MDT . dominates ( MI2 , MI1 ) ) { if ( ! intereferes ( MI1 , MI2 ) ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI1 -> getParent ( ) -> getNumber ( ) << <STR_LIT> << * MI1 ) ; MI1 -> eraseFromParent ( ) ; Defs . erase ( I1 ++ ) ; Changed = true ; break ; }


<s> void <ISA_LIT>FunctionInfo :: createEhDataRegsFI ( ) { for ( int I = <NUM_LIT> ; I < <NUM_LIT> ; ++ I ) { const <ISA_LIT>Subtarget & ST = MF . getTarget ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetRegisterClass * RC = ST . isABI_N64 ( ) ? & <STR_LIT> : & <STR_LIT> ; EhDataRegFI [ I ] = MF . getFrameInfo ( ) -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ;


<s> Register VOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; Register SOffset = MI . getOperand ( <NUM_LIT> + OpOffset ) . getReg ( ) ; unsigned AuxiliaryData = MI . getOperand ( <NUM_LIT> + OpOffset ) . getImm ( ) ; MachineMemOperand * MMO = * MI . memoperands_begin ( ) ; unsigned ImmOffset ; std :: tie ( VOffset , ImmOffset ) = splitBufferOffsets ( B , VOffset ) ; updateBufferMMO ( MMO , VOffset , SOffset , ImmOffset , VIndex , * B . getMRI ( ) ) ; auto MIB = B . buildInstr ( getBufferAtomicPseudo ( IID ) ) ; if ( HasReturn ) MIB . addDef ( Dst ) ; MIB . addUse ( VData ) ; if ( IsCmpSwap ) MIB . addReg ( CmpVal ) ;

MIB . addUse ( RSrc ) . addUse ( VIndex ) . addUse ( VOffset ) . addUse ( SOffset ) . addImm ( ImmOffset ) . addImm ( AuxiliaryData ) . addImm ( HasVIndex ? - <NUM_LIT> : <NUM_LIT> ) . addMemOperand ( MMO ) ;


Inst . addOperand ( MCOperand :: CreateReg ( Memory . BaseRegNum ) ) ;


<s> static inline void FromUint8Array ( const uint8_t * Array , size_t Length , T & Data ) { std :: size_t SizeType = sizeof ( T ) ;


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { auto * MFI = MF . getFrameInfo ( ) ; assert ( MFI -> getCalleeSavedInfo ( ) . empty ( ) && <STR_LIT> ) ; auto * WFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; if ( ! needsSP ( MF , * MFI ) ) return ; uint64_t StackSize = MFI -> getStackSize ( ) ; const auto * TII = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; auto & MRI = MF . getRegInfo ( ) ; auto InsertPt = MBB . begin ( ) ; DebugLoc DL ; unsigned SPAddr = MRI . createVirtualRegister ( & <STR_LIT> ) ; unsigned SPReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; auto * SPSymbol = MF . createExternalSymbolName ( <STR_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , SPAddr ) . addExternalSymbol ( SPSymbol ) ; auto * LoadMMO = new MachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , StackSize ? SPReg : ( unsigned ) <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SPAddr ) . addImm ( <NUM_LIT> ) . addMemOperand ( LoadMMO ) ; WFI -> stackifyVReg ( SPAddr ) ;


<s> ThumbTargetMachine :: ThumbTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>BaseTargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL ) , InstrInfo ( Subtarget . hasThumb2 ( ) ? ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( Subtarget ) ) : ( ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( Subtarget ) ) ) , DL ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : Subtarget . isAAPCS_ABI ( ) ? std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) : std :: string ( <STR_LIT> <STR_LIT> <STR_LIT> ) ) , TLInfo ( * this ) , TSInfo ( * this ) , FrameLowering ( Subtarget . hasThumb2 ( ) ? new <ISA_LIT>FrameLowering ( Subtarget ) : ( <ISA_LIT>FrameLowering * ) new Thumb1FrameLowering ( Subtarget ) ) , STTI ( & TLInfo ) , VTTI ( & TLInfo ) {


<s> static __inline qword si_rothm ( qword a , qword b ) { vec_ushort8 neg_b ; vec_ushort8 mask ;

neg_b = ( vec_ushort8 ) vec_sub ( vec_splat_s16 ( <NUM_LIT> ) , ( vec_short8 ) ( b ) ) ;


<s> sinkMBB -> addSuccessor ( exitMBB , BranchProbability :: getOne ( ) ) ; BuildMI ( loop1MBB , DL , TII -> get ( LL ) , Scratch ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loop1MBB , DL , TII -> get ( <STR_LIT> ) , Scratch2 ) . addReg ( Scratch ) . addReg ( Mask ) ; BuildMI ( loop1MBB , DL , TII -> get ( BNE ) ) . addReg ( Scratch2 ) . addReg ( ShiftCmpVal ) . addMBB ( sinkMBB ) ; BuildMI ( loop2MBB , DL , TII -> get ( <STR_LIT> ) , Scratch ) . addReg ( Scratch , RegState :: Kill ) . addReg ( Mask2 ) ; BuildMI ( loop2MBB , DL , TII -> get ( <STR_LIT> ) , Scratch ) . addReg ( Scratch , RegState :: Kill ) . addReg ( ShiftNewVal ) ; BuildMI ( loop2MBB , DL , TII -> get ( SC ) , Scratch ) . addReg ( Scratch , RegState :: Kill ) . addReg ( Ptr ) . addImm ( <NUM_LIT> ) ; BuildMI ( loop2MBB , DL , TII -> get ( BEQ ) ) . addReg ( Scratch , RegState :: Kill ) . addReg ( ZERO ) . addMBB ( loop1MBB ) ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Scratch2 ) . addReg ( ShiftAmnt ) ; if ( STI -> has<ISA_LIT>32r2 ( ) ) { BuildMI ( sinkMBB , DL , TII -> get ( SEOp ) , Dest ) . addReg ( Dest ) ; } else { const unsigned ShiftImm = I -> getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addImm ( ShiftImm ) ; BuildMI ( sinkMBB , DL , TII -> get ( <STR_LIT> ) , Dest ) . addReg ( Dest , RegState :: Kill ) . addImm ( ShiftImm ) ; } LivePhysRegs LiveRegs ; computeAndAddLiveIns ( LiveRegs , * loop1MBB ) ; computeAndAddLiveIns ( LiveRegs , * loop2MBB ) ; computeAndAddLiveIns ( LiveRegs , * sinkMBB ) ; computeAndAddLiveIns ( LiveRegs , * exitMBB ) ; NMBBI = BB . end ( ) ;


<s> int64_t Value2 = Value >> Shift ; if ( ( ( Value & ( int64_t ) maskTrailingZeros < uint64_t > ( Shift ) ) == Value ) && ( Value2 >= LBound ) && ( Value2 < HBound ) ) return true ;


<s> void AMDGPUInstPrinter :: printIfSet ( const MCInst * MI , unsigned OpNo , raw_ostream & O , StringRef Asm ) {

const MCOperand & Op = MI -> getOperand ( OpNo ) ;


<s> if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == <NUM_LIT> ) copies <<= <NUM_LIT> ; else step >>= <NUM_LIT> ; if ( vspltis_constant ( op , step , copies ) ) return true ; if ( step == <NUM_LIT> ) copies <<= <NUM_LIT> ;


<s> FunctionPass * llvm :: create<ISA_LIT>EnqueueExits ( ) { return new EnqueueExitsPass ;


<s> MachineInstr * New = MIB . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: srsrc ) ) . add ( * TII -> getNamedOperand ( * CI . I , <STR_LIT> :: soffset ) ) . addImm ( MergedOffset ) . addImm ( JoinedFormat ) . addImm ( CI . GLC ) . addImm ( CI . SLC ) . addImm ( <NUM_LIT> ) . addImm ( CI . DLC ) . addImm ( <NUM_LIT> ) . addMemOperand ( combineKnownAdjacentMMOs ( * MBB -> getParent ( ) , MMOa , MMOb ) ) ; std :: pair < unsigned , unsigned > SubRegIdx = getSubRegIdxs ( CI , Paired ) ; const unsigned SubRegIdx0 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const unsigned SubRegIdx1 = std :: get < <NUM_LIT> > ( SubRegIdx ) ; const MCInstrDesc & CopyDesc = TII -> get ( TargetOpcode :: COPY ) ; const auto * Dest0 = TII -> getNamedOperand ( * CI . I , <STR_LIT> :: vdata ) ; const auto * Dest1 = TII -> getNamedOperand ( * Paired . I , <STR_LIT> :: vdata ) ; BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest0 ) . addReg ( DestReg , <NUM_LIT> , SubRegIdx0 ) ; MachineInstr * Copy1 = BuildMI ( * MBB , Paired . I , DL , CopyDesc ) . add ( * Dest1 ) . addReg ( DestReg , RegState :: Kill , SubRegIdx1 ) ; moveInstsAfter ( Copy1 , InstsToMove ) ; CI . I -> eraseFromParent ( ) ;


<s> static rtx arm_expand_mve_builtin ( int fcode , tree exp , rtx target ) { if ( fcode >= ARM_BUILTIN_MVE_BASE && ! TARGET_HAVE_MVE ) { fatal_error ( input_location , <STR_LIT> <STR_LIT> ) ; return const0_rtx ; }

arm_builtin_datum * d = & mve_builtin_data [ fcode - ARM_BUILTIN_MVE_PATTERN_START ] ;


<s> const int Opcode = MI . getOpcode ( ) ; if ( ! isLEA ( Opcode ) ) return ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != <NUM_LIT> || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) || ! TII -> isSafeToClobberEFLAGS ( * MFI , I ) ) return ; const unsigned DstR = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const unsigned SrcR2 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ( SrcR1 == <NUM_LIT> || SrcR1 != DstR ) && ( SrcR2 == <NUM_LIT> || SrcR2 != DstR ) ) return ;

if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> ) return ;


<s> void assignValueToAddress ( Register ValVReg , Register Addr , uint64_t Size , MachinePointerInfo & MPO , CCValAssign & VA ) override {

MachineFunction & MF = MIRBuilder . getMF ( ) ;


<s> return ( __m128 ) __builtin_ia32_cvtpd2ps_mask ( ( __v2df ) __A , ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> bool isTailCall = ( RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ) ; bool isInterrupt = RetOpcode == <STR_LIT> || RetOpcode == <STR_LIT> ; SmallVector < unsigned , <NUM_LIT> > Regs ; unsigned i = CSI . size ( ) ; while ( i != <NUM_LIT> ) { unsigned LastReg = <NUM_LIT> ; bool DeleteRet = false ; for ( ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ; if ( ! ( Func ) ( Reg , STI . isTargetMachO ( ) ) ) continue ; if ( Reg >= <STR_LIT> && Reg < <STR_LIT> + NumAlignedDPRCS2Regs ) continue ; if ( Reg == <STR_LIT> && ! isTailCall && ! isVarArg && ! isInterrupt && STI . hasV5TOps ( ) ) { Reg = <STR_LIT> ; LdmOpc = AFI -> isThumbFunction ( ) ? <STR_LIT> : <STR_LIT> ; DeleteRet = true ; } if ( NoGap && LastReg && LastReg != Reg - <NUM_LIT> ) break ;


<s> unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; } unsigned R4BaseReg = NextReg ; if ( NumAlignedDPRCS2Regs >= <NUM_LIT> ) { unsigned SupReg = TRI -> getMatchingSuperReg ( NextReg , <STR_LIT> , & <STR_LIT> ) ; AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , NextReg ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SupReg , RegState :: ImplicitDefine ) ) ; NextReg += <NUM_LIT> ; NumAlignedDPRCS2Regs -= <NUM_LIT> ; }


<s> if ( B -> isEHPad ( ) || B -> hasAddressTaken ( ) ) return false ; if ( B -> succ_size ( ) == <NUM_LIT> ) return false ; for ( auto & MI : * B ) { if ( MI . isDebugValue ( ) ) continue ; if ( MI . isConditionalBranch ( ) ) return false ; unsigned Opc = MI . getOpcode ( ) ; bool IsJMP = ( Opc == <STR_LIT> ) ; if ( ! isPredicableStore ( & MI ) && ! IsJMP && ! isSafeToSpeculate ( & MI ) ) return false ; for ( const MachineOperand & MO : MI . operands ( ) ) { if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( R ) ) continue ; switch ( MRI -> getRegClass ( R ) -> getID ( ) ) { case <STR_LIT> :


<s> buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIRRC -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MIRRC -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ; MI . eraseFromParent ( ) ;


<s> ELF<ISA_LIT>AsmBackend ( const Target & T , uint8_t OSABI ) :

<ISA_LIT>AsmBackend ( T ) , OSABI ( OSABI ) {


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : TargetInstrInfoImpl ( <ISA_LIT>Insts , array_lengthof ( <ISA_LIT>Insts ) ) , RI ( * this ) {


<s> if ( ! I -> getOperand ( i ) . isFI ( ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> ) { Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; } switch ( I -> getDesc ( ) . TSFlags & <STR_LIT> ) { case <STR_LIT> : case <STR_LIT> : Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : if ( hasFP ( MF ) && AFI -> hasStackFrame ( ) ) Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ;


<s> bool <ISA_LIT>FunctionInfo :: globalBaseRegSet ( ) const { return GlobalBaseReg ;


<s> SDValue Glue = M0 . getValue ( <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; for ( unsigned i = <NUM_LIT> , e = N -> getNumOperands ( ) ; i != e ; ++ i ) { Ops . push_back ( N -> getOperand ( i ) ) ; }


<s> virtual void EmitARM64WinCFISetFP ( ) {


<s> AAAMDWorkGroupSize ( const IRPosition & IRP , Attributor & A ) : Base ( IRP ) {


<s> uint64_t FrameSize = MFI . getStackSize ( ) ; Align StackAlign = getStackAlign ( ) ; uint64_t MaxCallSize = alignTo ( MFI . getMaxCallFrameSize ( ) , StackAlign ) ;

MFI . setMaxCallFrameSize ( MaxCallSize ) ;


<s> intptr_t * RetAddrLoc = & StackPtr [ <NUM_LIT> ] ; __msan_unpoison ( RetAddrLoc , sizeof ( * RetAddrLoc ) ) ; assert ( * RetAddrLoc == RetAddr && <STR_LIT> ) ; bool isStub = ( ( unsigned char * ) RetAddr ) [ <NUM_LIT> ] == <NUM_LIT> ; RetAddr -- ; RetAddr -= <NUM_LIT> ; DEBUG ( dbgs ( ) << <STR_LIT> << ( void * ) RetAddr << <STR_LIT> << ( void * ) StackPtr << <STR_LIT> << TheVM -> getFunctionReferencedName ( ( void * ) RetAddr ) << <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; assert ( ( ( unsigned char * ) RetAddr ) [ - <NUM_LIT> ] == <NUM_LIT> && <STR_LIT> ) ; intptr_t NewVal = ( intptr_t ) JITCompilerFunction ( ( void * ) RetAddr ) ; assert ( isStub && <STR_LIT> <STR_LIT> ) ; * ( intptr_t * ) RetAddr = ( intptr_t ) ( NewVal - RetAddr - <NUM_LIT> ) ; if ( isStub ) { intptr_t diff = NewVal - RetAddr + <NUM_LIT> ;

if ( diff >= - <NUM_LIT> && diff <= <NUM_LIT> ) {


<s> Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . is64Bit ( ) ) { Subtarget . setPICStyle ( PICStyles :: RIPRel ) ; } else if ( Subtarget . isTargetCygMing ( ) ) { Subtarget . setPICStyle ( PICStyles :: None ) ; } else if ( Subtarget . isTargetDarwin ( ) ) { if ( getRelocationModel ( ) == Reloc :: PIC_ ) Subtarget . setPICStyle ( PICStyles :: StubPIC ) ; else {

assert ( getRelocationModel ( ) == Reloc :: DynamicNoPIC ) ;


<s> default : break ; case 's' : case 'v' : case 'a' : return C_RegisterClass ; } } return TargetLowering :: getConstraintType ( Constraint ) ;


<s> else if ( warn_psabi_flags & WARN_PSABI_ZERO_WIDTH_BITFIELD ) inform ( input_location , <STR_LIT> <STR_LIT> , TYPE_MAIN_VARIANT ( type ) , url12 ) ; } * count = ag_count ; } else return false ; } else if ( GET_MODE_CLASS ( mode ) == MODE_FLOAT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_INT || GET_MODE_CLASS ( mode ) == MODE_VECTOR_FLOAT ) { * count = <NUM_LIT> ; new_mode = mode ; } else if ( GET_MODE_CLASS ( mode ) == MODE_COMPLEX_FLOAT ) { * count = <NUM_LIT> ; new_mode = ( mode == DCmode ? DFmode : SFmode ) ; } else return false ; if ( ! use_vfp_abi ( pcs_variant , ARM_NUM_REGS ( new_mode ) > <NUM_LIT> ) ) return false ; * base_mode = new_mode ; if ( TARGET_GENERAL_REGS_ONLY ) error ( <STR_LIT> , type ) ;


<s> mode = GET_MODE ( mem ) ; if ( TARGET_HAVE_LDACQ && INTVAL ( mod_f ) == MEMMODEL_ACQUIRE && INTVAL ( mod_s ) == MEMMODEL_RELEASE ) mod_s = GEN_INT ( MEMMODEL_ACQ_REL ) ; switch ( mode ) { case QImode : case HImode : rval = gen_reg_rtx ( SImode ) ; oldval = convert_modes ( SImode , mode , oldval , true ) ; case SImode : if ( ! arm_add_operand ( oldval , SImode ) ) oldval = force_reg ( SImode , oldval ) ; break ; case DImode : if ( ! cmpdi_operand ( oldval , mode ) ) oldval = force_reg ( mode , oldval ) ; break ; default : gcc_unreachable ( ) ; } switch ( mode ) { case QImode : gen = gen_atomic_compare_and_swapqi_1 ; break ; case HImode : gen = gen_atomic_compare_and_swaphi_1 ; break ; case SImode : gen = gen_atomic_compare_and_swapsi_1 ; break ; case DImode : gen = gen_atomic_compare_and_swapdi_1 ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( rval , mem , oldval , newval , is_weak , mod_s , mod_f ) ) ; if ( mode == QImode || mode == HImode ) emit_move_insn ( operands [ <NUM_LIT> ] , gen_lowpart ( mode , rval ) ) ; x = gen_rtx_REG ( CCmode , CC_REGNUM ) ; x = gen_rtx_EQ ( SImode , x , const0_rtx ) ; emit_insn ( gen_rtx_SET ( VOIDmode , bval , x ) ) ;


<s> if ( FP_REGNO_P ( cfun_gpr_save_slot ( i ) ) ) { rtx_insn * insn = emit_move_insn ( gen_rtx_REG ( DImode , cfun_gpr_save_slot ( i ) ) , gen_rtx_REG ( DImode , i ) ) ; RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ;

add_reg_note ( insn , REG_CFA_REGISTER , PATTERN ( insn ) ) ;


<s> MemInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; MemInst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; MemInst . addOperand ( MCOperand :: createImm ( StackOffset ) ) ; expandMemInst ( MemInst , IDLoc , Instructions , IsLoad , true ) ;


<s> unsigned getMinPrefetchStride ( ) { return <NUM_LIT> ;


<s> int func = BUILT_IN_COMPLEX_MUL_MIN + mode - MIN_MODE_COMPLEX_FLOAT ; return ( built_in_function ) func ;


<s> RegisterAsmInfo < <ISA_LIT>TargetAsmInfo > Z ( The<ISA_LIT>Target ) ;


<s> const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getFirstTerminator ( ) ; DebugLoc DL ; unsigned ScratchExecCopy = <STR_LIT> ; for ( const <ISA_LIT>MachineFunctionInfo :: SGPRSpillVGPRCSR & Reg : FuncInfo -> getSGPRSpillVGPRs ( ) ) { if ( ! Reg . FI . hasValue ( ) ) continue ; if ( ScratchExecCopy == <STR_LIT> ) { LivePhysRegs LiveRegs ( * ST . getRegisterInfo ( ) ) ; LiveRegs . addLiveIns ( MBB ) ; ScratchExecCopy = findScratchNonCalleeSaveRegister ( MF , LiveRegs , <STR_LIT> ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) , ScratchExecCopy ) . addImm ( - <NUM_LIT> ) ; } TII -> loadRegFromStackSlot ( MBB , MBBI , Reg . VGPR , Reg . FI . getValue ( ) , & <STR_LIT> , & TII -> getRegisterInfo ( ) ) ;


<s> void <ISA_LIT>InstrInfo :: legalizeOperandsVOP3 ( MachineRegisterInfo & MRI , MachineInstr & MI ) const { unsigned Opc = MI . getOpcode ( ) ; int VOP3Idx [ <NUM_LIT> ] = { <STR_LIT> ( Opc , <STR_LIT> :: src0 ) , <STR_LIT> ( Opc , <STR_LIT> :: src1 ) , <STR_LIT> ( Opc , <STR_LIT> :: src2 ) } ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { MachineOperand & Src1 = MI . getOperand ( VOP3Idx [ <NUM_LIT> ] ) ; MachineOperand & Src2 = MI . getOperand ( VOP3Idx [ <NUM_LIT> ] ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( Src1 . isReg ( ) && ! RI . isSGPRClass ( MRI . getRegClass ( Src1 . getReg ( ) ) ) ) { Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; } if ( Src2 . isReg ( ) && ! RI . isSGPRClass ( MRI . getRegClass ( Src2 . getReg ( ) ) ) ) { Register Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src2 ) ; Src2 . ChangeToRegister ( Reg , false ) ; } } int ConstantBusLimit = ST . getConstantBusLimit ( Opc ) ; int LiteralLimit = ST . hasVOP3Literal ( ) ? <NUM_LIT> : <NUM_LIT> ; SmallDenseSet < unsigned > SGPRsUsed ; Register SGPRReg = findUsedSGPR ( MI , VOP3Idx ) ;


<s> src = change_address ( src , VOIDmode , src_addr ) ; temp = expand_binop ( mode , add_optab , count , constm1_rtx , count , <NUM_LIT> , <NUM_LIT> ) ; if ( temp != count ) emit_move_insn ( count , temp ) ; temp = expand_binop ( mode , ashr_optab , count , GEN_INT ( <NUM_LIT> ) , blocks , <NUM_LIT> , <NUM_LIT> ) ; if ( temp != blocks ) emit_move_insn ( blocks , temp ) ; emit_cmp_and_jump_insns ( blocks , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , loop_end_label ) ; emit_label ( loop_start_label ) ; emit_insn ( gen_movmem_short ( dst , src , GEN_INT ( <NUM_LIT> ) ) ) ; s390_load_address ( dst_addr , gen_rtx_PLUS ( Pmode , dst_addr , GEN_INT ( <NUM_LIT> ) ) ) ; s390_load_address ( src_addr , gen_rtx_PLUS ( Pmode , src_addr , GEN_INT ( <NUM_LIT> ) ) ) ; temp = expand_binop ( mode , add_optab , blocks , constm1_rtx , blocks , <NUM_LIT> , <NUM_LIT> ) ; if ( temp != blocks ) emit_move_insn ( blocks , temp ) ; emit_cmp_and_jump_insns ( blocks , const0_rtx , EQ , NULL_RTX , mode , <NUM_LIT> , loop_end_label ) ; emit_jump ( loop_start_label ) ; emit_label ( loop_end_label ) ; emit_insn ( gen_movmem_short ( dst , src , convert_to_mode ( Pmode , count , <NUM_LIT> ) ) ) ; emit_label ( end_label ) ; }


<s> return __builtin_arm_crc32ch ( __a , __b ) ;


<s> void EmitConstant ( uint64_t Val , unsigned Size , raw_ostream & OS ) const {

for ( unsigned i = <NUM_LIT> ; i != Size ; ++ i ) {


<s> bool isConstantImm ( ) const { return isImm ( ) && isa < MCConstantExpr > ( getImm ( ) ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ;


<s> auto OpNum = <STR_LIT> ( Opcode , <STR_LIT> :: offset ) ; assert ( OpNum != - <NUM_LIT> ) ; const auto & Op = Inst . getOperand ( OpNum ) ; if ( ! hasFlatOffsets ( ) && Op . getImm ( ) != <NUM_LIT> ) { Error ( getFlatOffsetLoc ( Operands ) , <STR_LIT> ) ; return false ; } if ( TSFlags & ( <STR_LIT> | <STR_LIT> ) ) { unsigned OffsetSize = <STR_LIT> ( getSTI ( ) , true ) ; if ( ! isIntN ( OffsetSize , Op . getImm ( ) ) ) { Error ( getFlatOffsetLoc ( Operands ) , Twine ( <STR_LIT> ) + Twine ( OffsetSize ) + <STR_LIT> ) ; return false ; } } else { unsigned OffsetSize = <STR_LIT> ( getSTI ( ) , false ) ; if ( ! isUIntN ( OffsetSize , Op . getImm ( ) ) ) { Error ( getFlatOffsetLoc ( Operands ) , Twine ( <STR_LIT> ) + Twine ( OffsetSize ) + <STR_LIT> ) ; return false ; } }


<s> static inline ShiftOpc getShiftOpcForNode ( SDValue N ) { switch ( N . getOpcode ( ) ) { default : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( HII -> isNewValueInst ( J ) || HII -> isMemOp ( J ) || HII -> isMemOp ( I ) ) return true ; } else { bool MopStI = HII -> isMemOp ( I ) || StoreI ; bool MopStJ = HII -> isMemOp ( J ) || StoreJ ; if ( MopStI && MopStJ ) return true ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> int64_t Value = CE -> getValue ( ) ;

return <STR_LIT> ( - Value ) != - <NUM_LIT> ;


<s> const auto SignBitMask = B . buildConstant ( S32 , UINT32_C ( <NUM_LIT> ) << <NUM_LIT> ) ; auto SignBit = B . buildAnd ( S32 , Hi , SignBitMask ) ; const auto FractMask = B . buildConstant ( S64 , ( UINT64_C ( <NUM_LIT> ) << FractBits ) - <NUM_LIT> ) ; const auto Zero32 = B . buildConstant ( S32 , <NUM_LIT> ) ; auto SignBit64 = B . buildMerge ( S64 , { Zero32 . getReg ( <NUM_LIT> ) , SignBit . getReg ( <NUM_LIT> ) } ) ; auto Shr = B . buildAShr ( S64 , FractMask , Exp ) ; auto Not = B . buildNot ( S64 , Shr ) ;

auto Tmp0 = B . buildAnd ( S64 , Src , Not ) ;


<s> HOST_WIDE_INT regno ; enum reg_class rclass ; if ( GET_CODE ( reg ) == SUBREG ) reg = SUBREG_REG ( reg ) ; if ( ! REG_P ( reg ) ) return NO_REG_TYPE ; regno = REGNO ( reg ) ; if ( regno >= FIRST_PSEUDO_REGISTER ) { if ( ! lra_in_progress && ! reload_in_progress && ! reload_completed ) return PSEUDO_REG_TYPE ; regno = true_regnum ( reg ) ; if ( regno < <NUM_LIT> || regno >= FIRST_PSEUDO_REGISTER ) return PSEUDO_REG_TYPE ; }


<s> MachineRegisterInfo & MRI = Inst . getMF ( ) -> getRegInfo ( ) ; MachineOperand & SAddr = Inst . getOperand ( OldSAddrIdx ) ; if ( RI . isSGPRReg ( MRI , SAddr . getReg ( ) ) ) return false ; int NewVAddrIdx = <STR_LIT> ( NewOpc , <STR_LIT> :: vaddr ) ; if ( NewVAddrIdx < <NUM_LIT> ) return false ; int OldVAddrIdx = <STR_LIT> ( Opc , <STR_LIT> :: vaddr ) ; MachineInstr * VAddrDef = nullptr ; if ( OldVAddrIdx >= <NUM_LIT> ) { MachineOperand & VAddr = Inst . getOperand ( OldVAddrIdx ) ; VAddrDef = MRI . getUniqueVRegDef ( VAddr . getReg ( ) ) ; if ( ! VAddrDef || VAddrDef -> getOpcode ( ) != <STR_LIT> || ! VAddrDef -> getOperand ( <NUM_LIT> ) . isImm ( ) || VAddrDef -> getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) return false ; } const MCInstrDesc & NewDesc = get ( NewOpc ) ; Inst . setDesc ( NewDesc ) ; if ( OldVAddrIdx == NewVAddrIdx ) { MachineOperand & NewVAddr = Inst . getOperand ( NewVAddrIdx ) ; MRI . removeRegOperandFromUseList ( & NewVAddr ) ; MRI . moveOperands ( & NewVAddr , & SAddr , <NUM_LIT> ) ; Inst . RemoveOperand ( OldSAddrIdx ) ; MRI . removeRegOperandFromUseList ( & NewVAddr ) ; MRI . addRegOperandToUseList ( & NewVAddr ) ;


<s> static int branch_dest ( rtx branch ) { rtx dest = SET_SRC ( PATTERN ( branch ) ) ; int dest_uid ; if ( GET_CODE ( dest ) == IF_THEN_ELSE ) dest = XEXP ( dest , <NUM_LIT> ) ; dest = XEXP ( dest , <NUM_LIT> ) ;


<s> switch ( op_code ) { case LTU : case LEU : case GEU : case GTU : return aarch64_sve_cmp_immediate_p ( x , false ) ; case LT : case LE : case GE : case GT : case NE : case EQ : return aarch64_sve_cmp_immediate_p ( x , true ) ; default :


<s> int FI = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned NeedAlign = HRI . getSpillAlignment ( <STR_LIT> ) ; unsigned HasAlign = MFI . getObjectAlignment ( FI ) ; unsigned LoadOpc = NeedAlign <= HasAlign ? <STR_LIT> : <STR_LIT> ; BuildMI ( B , It , DL , HII . get ( LoadOpc ) , DstR ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . setMemRefs ( MI -> memoperands_begin ( ) , MI -> memoperands_end ( ) ) ; B . erase ( It ) ; return true ;


<s> LLVM_EXPLICIT operator bool ( ) const { return Def || Use ;


<s> void <ISA_LIT>RegisterSema :: setSF ( <STR_LIT> SF , Value * Val ) { SFVals [ SF ] = Val ;

if ( ! Val -> hasName ( ) ) Val -> setName ( ( Twine ( getSFName ( SF ) ) + <STR_LIT> + utostr ( SFAssignments [ SF ] ++ ) ) . str ( ) ) ;


<s> printMemReference ( MI , OpNo , O ) ;


<s> const MachineOperand & MO2 = MI -> getOperand ( OpNum + <NUM_LIT> ) ; unsigned JTI = MO1 . getIndex ( ) ; O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << JTI << '_' << MO2 . getImm ( ) << <STR_LIT> ; const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ; const MachineJumpTableInfo * MJTI = MF -> getJumpTableInfo ( ) ; const std :: vector < MachineJumpTableEntry > & JT = MJTI -> getJumpTables ( ) ; const std :: vector < MachineBasicBlock * > & JTBBs = JT [ JTI ] . MBBs ; bool ByteOffset = false , HalfWordOffset = false ; if ( MI -> getOpcode ( ) == <STR_LIT> ) ByteOffset = true ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) HalfWordOffset = true ;

for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) {


<s> if ( mask -> isZeroValue ( ) ) { auto inse = dyn_cast < InsertElementInst > ( shuffl -> getOperand ( <NUM_LIT> ) ) ; if ( inse && o01 ) { sum1 = build_op ( I , o01 , inse -> getOperand ( <NUM_LIT> ) ) ; } } } else { Constant * cv = dyn_cast < Constant > ( op1 ) ; VectorType * cvt = cast < VectorType > ( op1 -> getType ( ) ) ; if ( cv && cvt ) { unsigned int veclen = cvt -> getNumElements ( ) ; if ( isa < ConstantVector > ( cv ) || isa < ConstantDataVector > ( cv ) ) { Constant * first = cv -> getAggregateElement ( <NUM_LIT> ) ; bool elements_are_not_equal = false ; if ( ! all_zero_shuffle ) { for ( unsigned i = <NUM_LIT> ; i < veclen ; i ++ ) { Constant * current = cv -> getAggregateElement ( i ) ; if ( current != first && ! isa < UndefValue > ( current ) ) { elements_are_not_equal = true ; break ; } } } if ( ! elements_are_not_equal && o01 ) { sum1 = build_op ( I , o01 , first ) ; } } else if ( cv -> isZeroValue ( ) && o01 ) { sum1 = build_op ( I , o01 , cv -> getAggregateElement ( <NUM_LIT> ) ) ; } } } if ( sum1 ) { Value * v2 = UndefValue :: get ( t1 ) ; Type * current_t = t1 ; int veclen = current_t -> getVectorNumElements ( ) ; Value * inse = Builder . CreateInsertElement ( v2 , sum1 , ConstantInt :: get ( I32Type , <NUM_LIT> ) ) ; if ( veclen == <NUM_LIT> ) current_t = VectorType :: get ( I32Type , <NUM_LIT> ) ; else if ( veclen == <NUM_LIT> ) current_t = VectorType :: get ( I32Type , <NUM_LIT> ) ; else if ( veclen == <NUM_LIT> ) current_t = VectorType :: get ( I32Type , <NUM_LIT> ) ; else llvm_unreachable ( <STR_LIT> ) ; Constant * Zeromask = ConstantInt :: get ( current_t , <NUM_LIT> ) ; Value * insshf = Builder . CreateShuffleVector ( inse , v2 , Zeromask ) ; if ( insshf ) { I . replaceAllUsesWith ( insshf ) ;


<s> GetExternalSymbolSymbol ( const MachineOperand & MO ) const { switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; } return Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ;


<s> SDValue Ch = Node -> getChain ( ) ; SDValue Ptr = Node -> getBasePtr ( ) ; SDValue Val = Node -> getValue ( ) ; const MachinePointerInfo & MPI = Node -> getPointerInfo ( ) ; unsigned Alignment = Node -> getAlignment ( ) ; MachineMemOperand * MMO = Node -> getMemOperand ( ) ; AAMDNodes AAInfo = Node -> getAAInfo ( ) ; unsigned RC , LoTy , LoIdx , HiTy , HiIdx , HiOff ; bool Split = <STR_LIT> ( MMO -> getSize ( ) , <STR_LIT> , RC , LoTy , LoIdx , HiTy , HiIdx , HiOff ) ; assert ( Split && <STR_LIT> ) ; SDValue Lo = EmitExtractSubreg ( LoIdx , DL , Val , DAG ) ; Lo = DAG . getStore ( Ch , DL , Lo , Ptr , MPI , Alignment , MMO -> getFlags ( ) , AAInfo ) ; Ptr = DAG . getMemBasePlusOffset ( Ptr , HiOff , DL ) ;

SDValue Hi = EmitExtractSubreg ( HiIdx , DL , Val , DAG ) ;


<s> FMA3_AVX512_FULL_GROUP ( VFMSUB ) ; FMA3_AVX512_FULL_GROUP ( VFNMADD ) ; FMA3_AVX512_FULL_GROUP ( VFNMSUB ) ; FMA3_AVX512_VECTOR_GROUP ( VFMADDSUB ) ;

FMA3_AVX512_VECTOR_GROUP ( VFMSUBADD ) ;


<s> return RegNo ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> * RegNo ; } } else if ( MO . isImm ( ) ) { return static_cast < unsigned > ( MO . getImm ( ) ) ;


return ( uint32x4_t ) __builtin_neon_vpaddluv8hi ( ( int16x8_t ) __a ) ;


<s> bool isInstBasic ( uint16_t Opcode ) const { return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> if ( GET_CODE ( reg ) == SUBREG ) { offset = SUBREG_BYTE ( reg ) ; reg = SUBREG_REG ( reg ) ; } gen_ashift ( type , n , gen_rtx_SUBREG ( SImode , reg , offset ) ) ; break ;


<s> void <ISA_LIT>AsmPrinter :: emitBasicBlockEnd ( const MachineBasicBlock & MBB ) { if ( & MBB . getParent ( ) -> back ( ) == & MBB ) return ; const MachineBasicBlock * Next = MBB . getNextNode ( ) ; bool followedByFStart = isFStart ( Next ) ; if ( followedByFStart ) { OutStreamer -> emitLabel ( CurrCodeEnd ) ;


<s> if ( PhysicalRegisterInfo :: isRegMaskId ( RR . Reg ) ) { const uint32_t * MB = PRI . getRegMaskBits ( RR . Reg ) ; for ( unsigned i = <NUM_LIT> , e = PRI . getTRI ( ) . getNumRegs ( ) ; i != e ; ++ i ) { if ( MB [ i / <NUM_LIT> ] & ( <NUM_LIT> << ( i % <NUM_LIT> ) ) ) continue ; if ( ! hasCoverOf ( RegisterRef ( i , LaneBitmask :: getAll ( ) ) ) ) return false ; } return true ; } RegisterRef NR = PRI . normalize ( RR ) ; if ( NR . Mask . none ( ) ) return true ; auto F = Masks . find ( NR . Reg ) ; if ( F != Masks . end ( ) ) {

if ( ( NR . Mask & F -> second ) == NR . Mask ) return true ;


<s> MachineModuleInfoMachO & MMIMachO = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) ; MachineModuleInfoImpl :: StubValueTy & StubSym = GV -> hasHiddenVisibility ( ) ? MMIMachO . getHiddenGVStubEntry ( MCSym ) : MMIMachO . getGVStubEntry ( MCSym ) ; if ( StubSym . getPointer ( ) == <NUM_LIT> ) StubSym = MachineModuleInfoImpl ::

StubValueTy ( getSymbol ( GV ) , ! GV -> hasInternalLinkage ( ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>LoopDataPrefetchPass ( ) { return new <ISA_LIT>LoopDataPrefetch ( ) ;


<s> <ISA_LIT>ELFObjectWriter ( uint8_t OSABI , uint16_t EMachine ) : MCELFObjectTargetWriter ( false , OSABI , EMachine , true ) {


<s> fpu_save_off = regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) ; } else { regs_off = <NUM_LIT> + <NUM_LIT> ; fpu_save_off = regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) ; } this_cfa = ( int ) context -> cfa ; new_cfa = * ( int * ) ( ( context -> cfa ) + ( regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( <NUM_LIT> * <NUM_LIT> ) ) ) ; fpu_save = * ( int * ) ( ( this_cfa ) + ( fpu_save_off ) ) ; fs -> cfa_how = CFA_REG_OFFSET ; fs -> cfa_reg = <NUM_LIT> ; fs -> cfa_offset = new_cfa - ( int ) context -> cfa ; for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( i == <NUM_LIT> ) continue ; fs -> regs . reg [ i ] . how = REG_SAVED_OFFSET ; fs -> regs . reg [ i ] . loc . offset = this_cfa + ( regs_off + ( <NUM_LIT> * <NUM_LIT> ) + ( i * <NUM_LIT> ) ) - new_cfa ; } for ( i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) {

fs -> regs . reg [ i + <NUM_LIT> ] . how = REG_SAVED_OFFSET ;


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( Subtarget -> hasSIMD128 ( ) ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; if ( EnableUnimplementedWasmSIMDInstrs ) { addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; } } computeRegisterProperties ( Subtarget -> getRegisterInfo ( ) ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , MVTPtr , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; for ( auto T : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , T , Legal ) ; for ( auto CC : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setCondCodeAction ( CC , T , Expand ) ; for ( auto Op : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Op , T , Expand ) ; for ( auto Op : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( Op , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Legal ) ; setOperationAction ( <STR_LIT> , T , Expand ) ; setOperationAction ( <STR_LIT> , T , Expand ) ; setLoadExtAction ( <STR_LIT> , T , <STR_LIT> , Expand ) ; setTruncStoreAction ( T , <STR_LIT> , Expand ) ; } for ( auto T : { <STR_LIT> , <STR_LIT> } ) { for ( auto Op : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { setOperationAction ( Op , T , Expand ) ;


<s> if ( std :: find ( Latches . begin ( ) , Latches . end ( ) , * PI ) == Latches . end ( ) ) Preds . push_back ( * PI ) ; }

BB = llvm :: SplitBlockPredecessors ( BB , Preds , <STR_LIT> , DT , LI , false ) ;


<s> return new THMTo<ISA_LIT>Stub ( m_pData , m_Size , fixup_begin ( ) , fixup_end ( ) , m_bUsingThumb2 ) ;


<s> default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'l' : if ( type -> isIntegerTy ( ) ) { if ( Subtarget -> isThumb ( ) ) weight = CW_SpecificReg ; else weight = CW_Register ; } break ; case 'w' : if ( type -> isFloatingPointTy ( ) ) weight = CW_Register ;


<s> unsigned ExpandCount = <NUM_LIT> ; do { assert ( ExpandCount < <NUM_LIT> && <STR_LIT> ) ; ( void ) ExpandCount ; bool BlockModified = expandMBB ( MBB ) ; Modified |= BlockModified ; ExpandCount ++ ; ContinueExpanding = BlockModified ; } while ( ContinueExpanding ) ; }


<s> int n_patterns = d -> perm . encoding ( ) . npatterns ( ) ; poly_int64 vec_len = d -> perm . length ( ) ; for ( int i = <NUM_LIT> ; i < n_patterns ; ++ i ) if ( ! known_eq ( d -> perm [ i ] , i ) && ! known_eq ( d -> perm [ i ] , vec_len + i ) ) return false ; for ( int i = n_patterns ; i < n_patterns * <NUM_LIT> ; i ++ ) if ( ! d -> perm . series_p ( i , n_patterns , i , n_patterns ) && ! d -> perm . series_p ( i , n_patterns , vec_len + i , n_patterns ) ) return false ; if ( d -> testing_p ) return true ; machine_mode pred_mode = aarch64_sve_pred_mode ( vmode ) ; rtx_vector_builder builder ( pred_mode , n_patterns , <NUM_LIT> ) ; for ( int i = <NUM_LIT> ; i < n_patterns * <NUM_LIT> ; i ++ ) { rtx elem = known_eq ( d -> perm [ i ] , i ) ? CONST1_RTX ( BImode ) : CONST0_RTX ( BImode ) ; builder . quick_push ( elem ) ; }


<s> static rtx move_from_acc ( unsigned int opno , rtx_insn * after ) { rtx dest = OP ( opno ) ; machine_mode mode = GET_MODE ( dest ) ;

if ( REG_P ( dest ) && REGNO ( dest ) < <NUM_LIT> ) return dest ;


<s> <ISA_LIT>TTI ( const <ISA_LIT>TargetMachine * TM ) : ImmutablePass ( ID ) , TM ( TM ) , ST ( TM -> getSubtargetImpl ( ) ) , TLI ( TM -> getTargetLowering ( ) ) { initialize<ISA_LIT>TTIPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerImplicitZextParam ( SelectionDAG & DAG , SDValue Op , MVT VT , unsigned Offset ) const { SDLoc SL ( Op ) ; SDValue Param = LowerParameter ( DAG , <STR_LIT> , <STR_LIT> , SL , DAG . getEntryNode ( ) , Offset , false ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Param , DAG . getValueType ( VT ) ) ;


return ( int8x16_t ) __builtin_neon_vclsv16qi ( __a ) ;