<s> if ( ! canPairLdStOpc ( FirstOpc , SecondOpc ) ) return false ; if ( ! isCandidateToMergeOrPair ( FirstLdSt ) || ! isCandidateToMergeOrPair ( SecondLdSt ) ) return false ; int64_t Offset1 = FirstLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( FirstOpc ) && ! scaleOffset ( FirstOpc , Offset1 ) ) return false ; int64_t Offset2 = SecondLdSt . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( isUnscaledLdSt ( SecondOpc ) && ! scaleOffset ( SecondOpc , Offset2 ) ) return false ;

if ( Offset1 > <NUM_LIT> || Offset1 < - <NUM_LIT> ) return false ;


<s> bool <ISA_LIT>InstrInfo :: getMemOpBaseRegImmOfs ( MachineInstr & LdSt , unsigned & BaseReg , int64_t & Offset , const TargetRegisterInfo * TRI ) const {


<s> assert ( ReservedVGPRInfoItr != FuncInfo -> getSGPRSpillVGPRs ( ) . end ( ) ) ; auto Index = std :: distance ( FuncInfo -> getSGPRSpillVGPRs ( ) . begin ( ) , ReservedVGPRInfoItr ) ; FuncInfo -> setSGPRSpillVGPRs ( LowestAvailableVGPR , FI , Index ) ; for ( MachineBasicBlock & MBB : MF ) { assert ( LowestAvailableVGPR . isValid ( ) && <STR_LIT> ) ; MBB . addLiveIn ( LowestAvailableVGPR ) ; MBB . sortUniqueLiveIns ( ) ; } return true ;


<s> bool uns_p = ( code == ASHIFTRT ) ? false : true ; if ( qimode == E_V64QImode ) return false ; if ( ! TARGET_AVX512BW ) return false ; if ( ( qimode == V8QImode || qimode == V16QImode ) && ! TARGET_AVX512VL ) return false ; if ( qimode == V32QImode && ( TARGET_PREFER_AVX128 || TARGET_PREFER_AVX256 ) ) return false ; switch ( qimode ) { case E_V8QImode : himode = V8HImode ; gen_extend = uns_p ? gen_zero_extendv8qiv8hi2 : gen_extendv8qiv8hi2 ; gen_truncate = gen_truncv8hiv8qi2 ; break ; case E_V16QImode : himode = V16HImode ; gen_extend = uns_p ? gen_zero_extendv16qiv16hi2 : gen_extendv16qiv16hi2 ; gen_truncate = gen_truncv16hiv16qi2 ; break ;


<s> return ( __m64 ) __builtin_ia32_psradi ( ( __v2si ) __m , __count ) ;


<s> if ( NumOps != <NUM_LIT> ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; unsigned LinkageSize = Subtarget . getFrameLowering ( ) -> getLinkageSize ( ) ; unsigned NumBytes = LinkageSize + <NUM_LIT> * PtrByteSize ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , dl ) ; SDValue CallSeqStart = Chain ; if ( ! isFunctionGlobalAddress ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) report_fatal_error ( <STR_LIT> ) ;

SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ;


<s> DEBUG ( errs ( ) << <STR_LIT> << ( unsigned ) RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ) ; llvm_unreachable ( <STR_LIT> ) ; } case <STR_LIT> : unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; ArgIn = DAG . getCopyFromReg ( Chain , dl , VReg , RegVT ) ; CFRegNode . push_back ( ArgIn . getValue ( ArgIn -> getNumValues ( ) - <NUM_LIT> ) ) ; } } else { assert ( VA . isMemLoc ( ) ) ; unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) ; assert ( ( ObjSize <= StackSlotSize ) && <STR_LIT> ) ; int FI = MFI . CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; ArgIn = DAG . getLoad ( VA . getLocVT ( ) , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } const ArgDataPair ADP = { ArgIn , Ins [ i ] . Flags } ; ArgData . push_back ( ADP ) ; } if ( IsVarArg ) { static const MCPhysReg ArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; auto * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned FirstVAReg = CCInfo . getFirstUnallocated ( ArgRegs ) ; if ( FirstVAReg < array_lengthof ( ArgRegs ) ) { int Offset = <NUM_LIT> ; int VarFI = MFI . CreateFixedObject ( ( array_lengthof ( ArgRegs ) - FirstVAReg ) * <NUM_LIT> , CCInfo . getNextStackOffset ( ) , true ) ; AFI -> setVarArgsFrameIndex ( VarFI ) ; SDValue FIN = DAG . getFrameIndex ( VarFI , <STR_LIT> ) ; for ( unsigned i = FirstVAReg ; i < array_lengthof ( ArgRegs ) ; i ++ ) { unsigned VReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ;

RegInfo . addLiveIn ( ArgRegs [ i ] , VReg ) ;


<s> auto IDLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; <ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ; } else if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setInnerLoop ( MCB ) ; } else if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) { <ISA_LIT>MCInstrInfo :: setOuterLoop ( MCB ) ; } else if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) { if ( getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ) <ISA_LIT>MCInstrInfo :: setMemReorderDisabled ( MCB ) ; else return getParser ( ) . Error ( IDLoc , MemNoShuffMsg ) ; } else if ( Option . compare_insensitive ( <STR_LIT> ) == <NUM_LIT> ) { } else return getParser ( ) . Error ( IDLoc , llvm :: Twine ( <STR_LIT> ) + Option + <STR_LIT> ) ;


<s> static bool isZeroImm ( const MachineOperand & op ) {

return op . isImm ( ) && op . getImm ( ) == <NUM_LIT> ;


<s> const MCOperand & IndexReg = MI . getOperand ( Op + <STR_LIT> ) ; if ( ( BaseReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( BaseReg . getReg ( ) ) ) || ( IndexReg . getReg ( ) != <NUM_LIT> && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( IndexReg . getReg ( ) ) ) ) return true ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : LogicalShift = true ; ShiftLeft = true ; break ; } assert ( ( LogicalShift || ! ShiftLeft ) && <STR_LIT> ) ; Value * Vec = II . getArgOperand ( <NUM_LIT> ) ; Value * Amt = II . getArgOperand ( <NUM_LIT> ) ; auto * VT = cast < FixedVectorType > ( II . getType ( ) ) ; Type * SVT = VT -> getElementType ( ) ; int NumElts = VT -> getNumElements ( ) ; int BitWidth = SVT -> getIntegerBitWidth ( ) ; KnownBits KnownAmt = llvm :: computeKnownBits ( Amt , II . getModule ( ) -> getDataLayout ( ) ) ; if ( KnownAmt . getMaxValue ( ) . ult ( BitWidth ) ) { return ( LogicalShift ? ( ShiftLeft ? Builder . CreateShl ( Vec , Amt ) : Builder . CreateLShr ( Vec , Amt ) ) : Builder . CreateAShr ( Vec , Amt ) ) ; } auto * CShift = dyn_cast < Constant > ( Amt ) ; if ( ! CShift ) return nullptr ; bool AnyOutOfRange = false ; SmallVector < int , <NUM_LIT> > ShiftAmts ; for ( int I = <NUM_LIT> ; I < NumElts ; ++ I ) { auto * CElt = CShift -> getAggregateElement ( I ) ; if ( isa_and_nonnull < UndefValue > ( CElt ) ) { ShiftAmts . push_back ( - <NUM_LIT> ) ; continue ; } auto * COp = dyn_cast_or_null < ConstantInt > ( CElt ) ; if ( ! COp ) return nullptr ; APInt ShiftVal = COp -> getValue ( ) ; if ( ShiftVal . uge ( BitWidth ) ) { AnyOutOfRange = LogicalShift ; ShiftAmts . push_back ( LogicalShift ? BitWidth : BitWidth - <NUM_LIT> ) ; continue ; } ShiftAmts . push_back ( ( int ) ShiftVal . getZExtValue ( ) ) ; } auto OutOfRange = [ & ] ( int Idx ) { return ( Idx < <NUM_LIT> ) || ( BitWidth <= Idx ) ; } ; if ( llvm :: all_of ( ShiftAmts , OutOfRange ) ) { SmallVector < Constant * , <NUM_LIT> > ConstantVec ; for ( int Idx : ShiftAmts ) { if ( Idx < <NUM_LIT> ) { ConstantVec . push_back ( UndefValue :: get ( SVT ) ) ;


return isDarwinABI ( ) ? <NUM_LIT> : ( is<ISA_LIT>64 ( ) ? <NUM_LIT> : <NUM_LIT> ) ;


<s> return __builtin_ia32_vcvtqq2ph512_mask_round ( ( __v8di ) __B , _mm_setzero_ph ( ) , __A , __C ) ;


<s> address += get_attr_length ( insn ) ; if ( ( table = is_jump_table ( insn ) ) != NULL ) { address += get_jump_table_size ( table ) ; insn = table ; } } } fix = minipool_fix_head ; while ( fix ) { Mfix * ftmp ; Mfix * fdel ; Mfix * last_added_fix ; Mfix * last_barrier = NULL ; Mfix * this_fix ; while ( fix && GET_CODE ( fix -> insn ) == BARRIER ) fix = fix -> next ; if ( fix == NULL ) break ; last_added_fix = NULL ; for ( ftmp = fix ; ftmp ; ftmp = ftmp -> next ) { if ( GET_CODE ( ftmp -> insn ) == BARRIER ) { if ( ftmp -> address >= minipool_vector_head -> max_address ) break ; last_barrier = ftmp ; } else if ( ( ftmp -> minipool = add_minipool_forward_ref ( ftmp ) ) == NULL ) break ; last_added_fix = ftmp ; } if ( last_barrier != NULL ) { for ( fdel = last_barrier -> next ; fdel && fdel != ftmp ; fdel = fdel -> next ) { fdel -> minipool -> refcount -- ; fdel -> minipool = NULL ; } ftmp = last_barrier ; } else {


<s> SDValue V ; bool First = true ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { bool IsNonZero = ( NonZeros & ( <NUM_LIT> << i ) ) != <NUM_LIT> ; if ( IsNonZero ) { if ( First ) { First = false ; if ( NumZero || <NUM_LIT> != i ) V = getZeroVector ( <STR_LIT> , Subtarget , DAG , dl ) ; else { assert ( <NUM_LIT> == i && <STR_LIT> ) ; V = DAG . getAnyExtOrTrunc ( Op . getOperand ( i ) , dl , <STR_LIT> ) ; V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V ) ; V = DAG . getBitcast ( <STR_LIT> , V ) ; continue ; } } V = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , V , Op . getOperand ( i ) , DAG . getIntPtrConstant ( i , dl ) ) ; } } return V ;


<s> Register getBaseRegister ( ) const { return BasePtr ;


<s> return ( ( int ) ( spu_extract ( spu_gather ( spu_andc ( spu_cmpeq ( exp , exp_mask ) , spu_cmpeq ( man , <NUM_LIT> ) ) ) , <NUM_LIT> ) != <NUM_LIT> ) ) ;


<s> MIB . addReg ( MIB . getReg ( <NUM_LIT> ) , getUndefRegState ( MIB -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) ) ;


<s> union { __ev64_opaque__ v ; uint64_t i ; } u ;


<s> if ( SelectShifterOperandReg ( TrueVal , CPTmp0 , CPTmp1 , CPTmp2 ) ) { SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ;

SDValue Ops [ ] = { FalseVal , CPTmp0 , CPTmp1 , CPTmp2 , CC , CCR , InFlag } ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Swap = true ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : SSECC = <NUM_LIT> ; break ; case <STR_LIT> : Swap = true ; case <STR_LIT> : SSECC = <NUM_LIT> ; break ;


<s> void AMDGPUInstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { switch ( Op . getReg ( ) ) { case AMDGPU :: PRED_SEL_OFF : break ; default : printRegOperand ( Op . getReg ( ) , O ) ; break ; } } else if ( Op . isImm ( ) ) { printImmediate ( Op . getImm ( ) , O ) ; } else if ( Op . isFPImm ( ) ) { O << Op . getFPImm ( ) ; } else if ( Op . isExpr ( ) ) { const MCExpr * Exp = Op . getExpr ( ) ; Exp -> print ( O ) ; } else { assert ( ! <STR_LIT> ) ; }


<s> unsigned regIdx = ConstExpr -> getValue ( ) ; if ( regIdx > <NUM_LIT> || MISCRegs [ regIdx ] == <STR_LIT> ) return false ; Op . Kind = k_Register ; Op . Reg . RegNum = MISCRegs [ regIdx ] ;


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> } if ( address . index ) { if ( address . base ) putc ( ',' , file ) ; fprintf ( file , <STR_LIT> , M68K_REGNAME ( REGNO ( address . index ) ) , GET_MODE ( address . index ) == HImode ? 'w' : 'l' ) ; if ( address . scale != <NUM_LIT> ) fprintf ( file , <STR_LIT> , address . scale ) ; } putc ( ')' , file ) ; } else { if ( ! address . offset && ! address . index ) fprintf ( file , <STR_LIT> , M68K_REGNAME ( REGNO ( address . base ) ) ) ; else { if ( labelno >= <NUM_LIT> ) asm_fprintf ( file , <STR_LIT> , labelno ) ; else { if ( address . base ) fputs ( M68K_REGNAME ( REGNO ( address . base ) ) , file ) ; fprintf ( file , <STR_LIT> ) ; if ( address . offset ) output_addr_const ( file , address . offset ) ; } if ( address . index ) { fprintf ( file , <STR_LIT> , M68K_REGNAME ( REGNO ( address . index ) ) , GET_MODE ( address . index ) == HImode ? 'w' : 'l' ) ; if ( address . scale != <NUM_LIT> ) fprintf ( file , <STR_LIT> , address . scale ) ; } putc ( ')' , file ) ; } }


<s> Register <ISA_LIT>LegalizerInfo :: insertLiveInCopy ( MachineIRBuilder & B , MachineRegisterInfo & MRI , Register LiveIn , Register PhyReg ) const { assert ( PhyReg . isPhysical ( ) && <STR_LIT> ) ; if ( ! MRI . getVRegDef ( LiveIn ) ) { MachineBasicBlock & OrigInsBB = B . getMBB ( ) ; auto OrigInsPt = B . getInsertPt ( ) ; MachineBasicBlock & EntryMBB = B . getMF ( ) . front ( ) ; EntryMBB . addLiveIn ( PhyReg ) ; B . setInsertPt ( EntryMBB , EntryMBB . begin ( ) ) ; B . buildCopy ( LiveIn , PhyReg ) ;

B . setInsertPt ( OrigInsBB , OrigInsPt ) ;


<s> assert ( XLenVT == N . getOperand ( <NUM_LIT> ) . getSimpleValueType ( ) && <STR_LIT> ) ; MVT EltVT = N . getSimpleValueType ( ) . getVectorElementType ( ) ; if ( EltVT . bitsLT ( XLenVT ) ) SplatImm = SignExtend64 ( SplatImm , EltVT . getSizeInBits ( ) ) ; if ( ! ValidateImm ( SplatImm ) ) return false ; SplatVal = DAG . getTargetConstant ( SplatImm , SDLoc ( N ) , XLenVT ) ; return true ;


<s> for ( unsigned I = Intr -> VAddrStart ; I < EndIdx ; I ++ ) { MachineOperand & SrcOp = MI . getOperand ( ArgOffset + I ) ; if ( ! SrcOp . isReg ( ) ) continue ; Register AddrReg = SrcOp . getReg ( ) ; if ( ( I < Intr -> GradientStart ) || ( I >= Intr -> GradientStart && I < Intr -> CoordStart && ! IsG16 ) || ( I >= Intr -> CoordStart && ! IsA16 ) ) { if ( ( I < Intr -> GradientStart ) && IsA16 && ( B . getMRI ( ) -> getType ( AddrReg ) == S16 ) ) { PackedAddrs . push_back ( B . buildBuildVector ( V2S16 , { AddrReg , B . buildUndef ( S16 ) . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ) ; } else { AddrReg = B . buildBitcast ( V2S16 , AddrReg ) . getReg ( <NUM_LIT> ) ; PackedAddrs . push_back ( AddrReg ) ; } } else { if ( ( ( I + <NUM_LIT> ) >= EndIdx ) || ( ( Intr -> NumGradients / <NUM_LIT> ) % <NUM_LIT> == <NUM_LIT> && ( I == static_cast < unsigned > ( Intr -> GradientStart + ( Intr -> NumGradients / <NUM_LIT> ) - <NUM_LIT> ) || I == static_cast < unsigned > ( Intr -> GradientStart + Intr -> NumGradients - <NUM_LIT> ) ) ) || ! MI . getOperand ( ArgOffset + I + <NUM_LIT> ) . isReg ( ) ) { PackedAddrs . push_back ( B . buildBuildVector ( V2S16 , { AddrReg , B . buildUndef ( S16 ) . getReg ( <NUM_LIT> ) } ) . getReg ( <NUM_LIT> ) ) ; } else { PackedAddrs . push_back ( B . buildBuildVector ( V2S16 , { AddrReg , MI . getOperand ( ArgOffset + I + <NUM_LIT> ) . getReg ( ) } ) . getReg ( <NUM_LIT> ) ) ;


<s> if ( ! NoOpt ) { if ( ! DisableHardwareLoops ) addPass ( create<ISA_LIT>FixupHwLoops ( ) , false ) ;

addPass ( create<ISA_LIT>Packetizer ( ) , false ) ;


<s> const MCOperand & Op2 = MI -> getOperand ( opNum + <NUM_LIT> ) ; bool PrintedFirstOperand = false ; if ( Op1 . isReg ( ) && Op1 . getReg ( ) != <STR_LIT> ) { printOperand ( MI , opNum , STI , O ) ; PrintedFirstOperand = true ; } const bool SkipSecondOperand = PrintedFirstOperand && ( ( Op2 . isReg ( ) && Op2 . getReg ( ) == <STR_LIT> ) || ( Op2 . isImm ( ) && Op2 . getImm ( ) == <NUM_LIT> ) ) ; if ( ! SkipSecondOperand ) {


<s> <ISA_LIT>CodeEmitter ( TargetMachine & tm , JITCodeEmitter & mce ) : MachineFunctionPass ( ID ) , TM ( tm ) , MCE ( mce ) {


BTFType . Info = IsUnion << <NUM_LIT> | Kind << <NUM_LIT> ;


<s> void LLVMInitializePowerPCTarget ( ) { RegisterTargetMachine < <ISA_LIT>32TargetMachine > A ( The<ISA_LIT>32Target ) ; RegisterTargetMachine < <ISA_LIT>64TargetMachine > B ( The<ISA_LIT>64Target ) ;

RegisterTargetMachine < <ISA_LIT>64TargetMachine > C ( The<ISA_LIT>64LETarget ) ;


<s> <ISA_LIT>Z80DAGToDAGISel ( <ISA_LIT>Z80TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Subtarget ( nullptr ) {


<s> return SelectAddrMode2Worker ( Op , N , Base , Offset , Opc ) == AM2_BASE ;


<s> BitVector Reserved ( getNumRegs ( ) ) ; const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; if ( TFI -> hasFP ( MF ) ) { for ( MCSubRegIterator I ( <STR_LIT> , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) -> getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ; unsigned BasePtr = get<ISA_LIT>SubSuperRegister ( getBaseRegister ( ) , <NUM_LIT> ) ; for ( MCSubRegIterator I ( BasePtr , this , true ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) Reserved . set ( <STR_LIT> + n ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( ! Is64Bit || ! MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ) {


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> virtual const <ISA_LIT>ompactInstrInfo * getInstrInfo ( ) const {


<s> auto MOTW = llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ;

return createELFObjectWriter ( std :: move ( MOTW ) , OS , true ) ;


<s> static rtx xtensa_expand_builtin ( tree exp , rtx target , rtx subtarget ATTRIBUTE_UNUSED , machine_mode mode ATTRIBUTE_UNUSED , int ignore ) { tree fndecl = TREE_OPERAND ( CALL_EXPR_FN ( exp ) , <NUM_LIT> ) ; unsigned int fcode = DECL_MD_FUNCTION_CODE ( fndecl ) ; switch ( fcode ) { case XTENSA_BUILTIN_UMULSIDI3 : return expand_call ( exp , target , ignore ) ; default :


<s> obstack_free ( & argv_obstack , NULL ) ; size_t symbol_name_len = strlen ( target_so_filename ) ; char * symbol_name = XALLOCAVEC ( char , symbol_name_len + <NUM_LIT> ) ; for ( size_t i = <NUM_LIT> ; i < symbol_name_len ; i ++ ) { char c = target_so_filename [ i ] ; if ( ! ISALNUM ( c ) ) c = '_' ; symbol_name [ i ] = c ; } symbol_name [ symbol_name_len ] = '\0' ; char * opt_for_objcopy [ <NUM_LIT> ] ; opt_for_objcopy [ <NUM_LIT> ] = XALLOCAVEC ( char , sizeof ( <STR_LIT> ) + symbol_name_len + strlen ( symbols [ <NUM_LIT> ] ) ) ; opt_for_objcopy [ <NUM_LIT> ] = XALLOCAVEC ( char , sizeof ( <STR_LIT> ) + symbol_name_len + strlen ( symbols [ <NUM_LIT> ] ) ) ; opt_for_objcopy [ <NUM_LIT> ] = XALLOCAVEC ( char , sizeof ( <STR_LIT> ) + symbol_name_len + strlen ( symbols [ <NUM_LIT> ] ) ) ; sprintf ( opt_for_objcopy [ <NUM_LIT> ] , <STR_LIT> , symbol_name , symbols [ <NUM_LIT> ] ) ; sprintf ( opt_for_objcopy [ <NUM_LIT> ] , <STR_LIT> , symbol_name , symbols [ <NUM_LIT> ] ) ; sprintf ( opt_for_objcopy [ <NUM_LIT> ] , <STR_LIT> , symbol_name , symbols [ <NUM_LIT> ] ) ; obstack_init ( & argv_obstack ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , target_so_filename ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , opt_for_objcopy [ <NUM_LIT> ] ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , opt_for_objcopy [ <NUM_LIT> ] ) ; obstack_ptr_grow ( & argv_obstack , <STR_LIT> ) ; obstack_ptr_grow ( & argv_obstack , opt_for_objcopy [ <NUM_LIT> ] ) ; obstack_ptr_grow ( & argv_obstack , NULL ) ; new_argv = XOBFINISH ( & argv_obstack , char * * ) ;

fork_execute ( new_argv [ <NUM_LIT> ] , new_argv , false ) ;


<s> bool mep_epilogue_uses ( int regno ) { if ( regno == LP_REGNO && ( profile_arc_flag > <NUM_LIT> || profile_flag > <NUM_LIT> ) ) return true ;

return ( reload_completed && mep_interrupt_saved_reg ( regno ) ) ;


<s> unsigned Opc = isThumb2 ? <STR_LIT> : <STR_LIT> ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) . addFrameIndex ( Addr . Base . FI ) . addImm ( <NUM_LIT> ) ) ; Addr . Base . Reg = ResultReg ; Addr . BaseType = Address :: RegBase ; } if ( needsLowering ) { Addr . Base . Reg = fastEmit_ri_ ( <STR_LIT> , <STR_LIT> , Addr . Base . Reg , Addr . Offset , <STR_LIT> ) ;


<s> unsigned VmcntHi = ( ( <NUM_LIT> << getVmcntBitWidthHi ( ) ) - <NUM_LIT> ) << getVmcntBitWidthLo ( ) ; return VmcntLo | VmcntHi ;


<s> bool CPSR = false ; if ( DefinesOptionalPredicate ( MI , & CPSR ) ) MIB . add ( CPSR ? t1CondCodeOp ( ) : condCodeOp ( ) ) ; return MIB ;


<s> DOUT << <STR_LIT> << std :: hex << std :: setw ( <NUM_LIT> ) << std :: setfill ( '0' ) << Binary << std :: dec << <STR_LIT> ;


<s> MVT VT = Op . getSimpleValueType ( ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isOperationLegalOrCustom ( <STR_LIT> , VT ) ) return SDValue ( ) ; SDLoc DL ( Op ) ; unsigned NumElems = Op . getNumOperands ( ) ; SDValue VecIn1 ; SDValue VecIn2 ; SmallVector < unsigned , <NUM_LIT> > InsertIndices ; SmallVector < int , <NUM_LIT> > Mask ( NumElems , - <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { unsigned Opc = Op . getOperand ( i ) . getOpcode ( ) ; if ( Opc == <STR_LIT> ) continue ; if ( Opc != <STR_LIT> ) { if ( InsertIndices . size ( ) > <NUM_LIT> ) return SDValue ( ) ; InsertIndices . push_back ( i ) ; continue ; } SDValue ExtractedFromVec = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; SDValue ExtIdx = Op . getOperand ( i ) . getOperand ( <NUM_LIT> ) ; if ( ExtractedFromVec . getValueType ( ) != VT ) return SDValue ( ) ; if ( ! isa < ConstantSDNode > ( ExtIdx ) ) return SDValue ( ) ; if ( VecIn1 . getNode ( ) == <NUM_LIT> ) VecIn1 = ExtractedFromVec ; else if ( VecIn1 != ExtractedFromVec ) { if ( VecIn2 . getNode ( ) == <NUM_LIT> ) VecIn2 = ExtractedFromVec ; else if ( VecIn2 != ExtractedFromVec ) return SDValue ( ) ; } unsigned Idx = cast < ConstantSDNode > ( ExtIdx ) -> getZExtValue ( ) ; if ( ExtractedFromVec == VecIn1 ) Mask [ i ] = Idx ; else if ( ExtractedFromVec == VecIn2 ) Mask [ i ] = Idx + NumElems ; }

if ( VecIn1 . getNode ( ) == <NUM_LIT> ) return SDValue ( ) ;


<s> SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) return DCI . CombineTo ( N , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 , N1 ) , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ; ConstantSDNode * N0C = dyn_cast < ConstantSDNode > ( N0 ) ; ConstantSDNode * N1C = dyn_cast < ConstantSDNode > ( N1 ) ;


<s> bool isFPRasZPR ( ) const { return Kind == k_Register && Reg . Kind == RegKind :: Scalar && <ISA_LIT>MCRegisterClasses [ Class ] . contains ( getReg ( ) ) ;


<s> FoldAsLoadDefReg = <NUM_LIT> ; return nullptr ; } DefMI = MRI -> getVRegDef ( FoldAsLoadDefReg ) ; assert ( DefMI ) ; bool SawStore = false ; if ( ! DefMI -> isSafeToMove ( nullptr , SawStore ) ) return nullptr ; unsigned SrcOperandId = <NUM_LIT> ; bool FoundSrcOperand = false ; for ( unsigned i = <NUM_LIT> , e = MI . getDesc ( ) . getNumOperands ( ) ; i != e ; ++ i ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) ) continue ; unsigned Reg = MO . getReg ( ) ;

if ( Reg != FoldAsLoadDefReg ) continue ;


<s> DecodeStatus S = Decode3OpInstruction ( fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) , Op1 , Op2 , Op3 ) ; if ( S == MCDisassembler :: Success ) {

DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ;


<s> if ( _U_Qfcmp ( a , b , <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ;

return ( _U_Qfcmp ( a , b , <NUM_LIT> ) != <NUM_LIT> ? <NUM_LIT> : - <NUM_LIT> ) ;


<s> void setTokenValue ( StringRef Value ) { assert ( Kind == Token && <STR_LIT> ) ; Tok . Data = Value . data ( ) ; Tok . Length = Value . size ( ) ;


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> <ISA_LIT>MCELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , raw_pwrite_stream & OS , std :: unique_ptr < MCCodeEmitter > Emitter , MCAssembler * Assembler ) : MCELFStreamer ( Context , std :: move ( TAB ) , OS , std :: move ( Emitter ) ) , MCII ( create<ISA_LIT>MCInstrInfo ( ) ) {


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const { uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ;

return create<ISA_LIT>ELFObjectWriter ( OS , OSABI ) ;


<s> unsigned CallOp ; if ( Is64Bit ) CallOp = IsLargeCodeModel ? <STR_LIT> : <STR_LIT> ; else CallOp = <STR_LIT> ; StringRef Symbol = STI . getTargetLowering ( ) -> getStackProbeSymbolName ( MF ) ; MachineInstrBuilder CI ; MachineBasicBlock :: iterator ExpansionMBBI = std :: prev ( MBBI ) ; if ( Is64Bit && MF . getTarget ( ) . getCodeModel ( ) == CodeModel :: Large ) { BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addExternalSymbol ( MF . createExternalSymbolName ( Symbol ) ) ; CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addReg ( <STR_LIT> ) ; } else { CI = BuildMI ( MBB , MBBI , DL , TII . get ( CallOp ) ) . addExternalSymbol ( MF . createExternalSymbolName ( Symbol ) ) ; }


<s> return DAG . getNode ( <STR_LIT> , DL , VT , NewLD ) ; } if ( Load -> getAddressSpace ( ) == <STR_LIT> && isa < GlobalVariable > ( GetUnderlyingObject ( Load -> getMemOperand ( ) -> getValue ( ) ) ) ) { SDValue Ptr = DAG . getZExtOrTrunc ( Load -> getBasePtr ( ) , DL , getPointerTy ( <STR_LIT> ) ) ; Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Load -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; } if ( Load -> getAddressSpace ( ) != <STR_LIT> || ExtType == <STR_LIT> || Load -> getMemoryVT ( ) . bitsGE ( <STR_LIT> ) ) return SDValue ( ) ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Ret = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Load -> getChain ( ) , Ptr , DAG . getTargetConstant ( <NUM_LIT> , <STR_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue ByteIdx = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Load -> getBasePtr ( ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue ShiftAmt = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , ByteIdx , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; Ret = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , ShiftAmt ) ; EVT MemEltVT = MemVT . getScalarType ( ) ; if ( ExtType == <STR_LIT> ) { SDValue MemEltVTNode = DAG . getValueType ( MemEltVT ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Ret , MemEltVTNode ) ; }

return DAG . getZeroExtendInReg ( Ret , DL , MemEltVT ) ;


<s> if ( UA . Addr -> getFlags ( ) & NodeAttrs :: PhiRef ) { NodeAddr < PhiNode * > PA = UA . Addr -> getOwner ( * DFG ) ; NodeId id = PA . Id ; const Liveness :: RefMap & phiUse = LV -> getRealUses ( id ) ; DEBUG ( dbgs ( ) << <STR_LIT> << Print < Liveness :: RefMap > ( phiUse , * DFG ) << <STR_LIT> ) ; if ( phiUse . size ( ) > <NUM_LIT> ) { for ( auto I : phiUse ) { if ( DR != I . first ) continue ; auto phiUseSet = I . second ; for ( auto phiUI : phiUseSet ) {

NodeAddr < UseNode * > phiUA = DFG -> addr < UseNode * > ( phiUI ) ;


<s> MachineInstrBuilder MIB = BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( Reg , getDefRegState ( true ) | getDeadRegState ( RegDeadKill ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) | getUndefRegState ( BaseUndef ) ) ; MIB . addImm ( Offset ) . addImm ( Pred ) . addReg ( PredReg ) ;


<s> inline static bool isPreOp ( unsigned AluOp ) {


<s> <STR_LIT> getPredicate ( const MachineInstr * MI ) const { int PIdx = MI -> findFirstPredOperandIdx ( ) ;

return PIdx != - <NUM_LIT> ? ( <STR_LIT> ) MI -> getOperand ( PIdx ) . getImm ( ) : <STR_LIT> ;


<s> else { if ( GET_CODE ( base_addr ) == POST_INC && REG_P ( XEXP ( base_addr , <NUM_LIT> ) ) ) return true ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : CCOpcode = <STR_LIT> ( CCOpcode , CompareVT == <STR_LIT> ) ; Temp = True ; True = False ; False = Temp ; break ; default : break ; } SDValue SelectNode = DAG . getNode ( <STR_LIT> , DL , CompareVT , Cond , Zero , True , False , DAG . getCondCode ( CCOpcode ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , SelectNode ) ; } if ( isHWTrueValue ( False ) && isHWFalseValue ( True ) ) { <STR_LIT> CCOpcode = cast < CondCodeSDNode > ( CC ) -> get ( ) ; std :: swap ( False , True ) ; CC = DAG . getCondCode ( <STR_LIT> ( CCOpcode , CompareVT == <STR_LIT> ) ) ; } if ( isHWTrueValue ( True ) && isHWFalseValue ( False ) ) { if ( CompareVT != VT ) { if ( VT == <STR_LIT> && CompareVT == <STR_LIT> ) { SDValue Boolean = DAG . getNode ( <STR_LIT> , DL , CompareVT , LHS , RHS , DAG . getConstant ( - <NUM_LIT> , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , CC ) ; SDValue LSB = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Boolean , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , LSB ) ; } else if ( VT == <STR_LIT> && CompareVT == <STR_LIT> ) { SDValue BoolAsFlt = DAG . getNode ( <STR_LIT> , DL , CompareVT , LHS , RHS , DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) , DAG . getConstantFP ( <NUM_LIT> , <STR_LIT> ) , CC ) ; SDValue Neg = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BoolAsFlt ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Neg ) ; } else { assert ( ! <STR_LIT> ) ; } } else { return DAG . getNode ( <STR_LIT> , DL , VT , LHS , RHS , True , False , CC ) ; } } SDValue MinMax = LowerMinMax ( Op , DAG ) ;


<s> if ( Kind < FirstTargetFixupKind ) return MCAsmBackend :: getFixupKindInfo ( Kind ) ; assert ( unsigned ( Kind - FirstTargetFixupKind ) < getNumFixupKinds ( ) && <STR_LIT> ) ; return Infos [ Kind - FirstTargetFixupKind ] ;


<s> if ( Op . isReg ( ) ) { for ( const MachineOperand & Def : MRI -> def_operands ( Op . getReg ( ) ) ) { if ( ! isSameReg ( Op , Def ) ) continue ;

const MachineInstr * DefInst = Def . getParent ( ) ;


<s> static bool expandOffset ( <ISA_LIT>AddressingMode & AM , bool IsBase , SDValue Op0 , ConstantSDNode * Op1 ) { int64_t TestOffset = AM . Offset + Op1 -> getSExtValue ( ) ; if ( selectOffset ( AM . OffR , TestOffset ) ) { AM . Base = Op0 ;


<s> MachineBasicBlock * DestBB = MI -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( BBIsInRange ( MI , DestBB , Br . MaxDisp ) ) return false ;

if ( ! Br . isCond ) return FixUpUnconditionalBr ( MF , Br ) ;


<s> Ctx ( ctx ) , ST ( st ) , AP ( ap ) {


<s> int JunkFI = MFI . CreateStackObject ( TRI -> getSpillSize ( * RC ) , TRI -> getSpillAlign ( * RC ) , true ) ; C<ISA_LIT> . push_back ( CalleeSavedInfo ( Reg , JunkFI ) ) ; } } if ( ! C<ISA_LIT> . empty ( ) ) { for ( MachineBasicBlock * SaveBlock : SaveBlocks ) insertCSRSaves ( ST , * SaveBlock , C<ISA_LIT> , LIS ) ; assert ( SaveBlocks . size ( ) == <NUM_LIT> && <STR_LIT> ) ; updateLiveness ( MF , C<ISA_LIT> ) ;

for ( MachineBasicBlock * RestoreBlock : RestoreBlocks ) insertCSRRestores ( * RestoreBlock , C<ISA_LIT> , LIS ) ;


<s> bool HasPackedStackAttr = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; bool IsVarArg = MF . getFunction ( ) . isVarArg ( ) ;

bool CallConv = MF . getFunction ( ) . getCallingConv ( ) != CallingConv :: GHC ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const <ISA_LIT>BaseTargetMachine & TM , bool IsLittle ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , UseMulOps ( UseFusedMulOps ) , GenExecuteOnly ( EnableExecuteOnly ) , CPUString ( CPU ) , IsLittle ( IsLittle ) , TargetTriple ( TT ) , Options ( TM . Options ) , TM ( TM ) , FrameLowering ( initializeFrameLowering ( CPU , FS ) ) , InstrInfo ( isThumb1Only ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new Thumb1InstrInfo ( * this ) : ! isThumb ( ) ? ( <ISA_LIT>BaseInstrInfo * ) new <ISA_LIT>InstrInfo ( * this ) : ( <ISA_LIT>BaseInstrInfo * ) new Thumb2InstrInfo ( * this ) ) , TLInfo ( TM , * this ) {


<s> Optional < ParamLoadedValue > <ISA_LIT>BaseInstrInfo :: describeLoadedValue ( const MachineInstr & MI , Register Reg ) const {

if ( auto DstSrcPair = isCopyInstrImpl ( MI ) ) {


<s> bool <ISA_LIT>AsmPrinter :: runOnMachineFunction ( MachineFunction & MF ) { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SMShadowTracker . startFunction ( MF ) ; CodeEmitter . reset ( TM . getTarget ( ) . createMCCodeEmitter ( * Subtarget -> getInstrInfo ( ) , * Subtarget -> getRegisterInfo ( ) , MF . getContext ( ) ) ) ; EmitFPOData = Subtarget -> isTargetWin32 ( ) && MF . getMMI ( ) . getModule ( ) -> getCodeViewFlag ( ) ; SetupMachineFunction ( MF ) ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Local = MF . getFunction ( ) -> hasLocalLinkage ( ) ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Local ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ) ;

OutStreamer -> EmitCOFFSymbolType ( COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ) ;


<s> MI -> eraseFromParent ( ) ; } if ( ! hasFP ( MF ) ) return ; const unsigned int ALLOCFRAME_MAX = <NUM_LIT> ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOStore , <NUM_LIT> , <NUM_LIT> ) ; if ( NumBytes >= ALLOCFRAME_MAX ) { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ; unsigned CallerSavedReg = HRI . getFirstCallerSavedNonParamReg ( ) ; BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , CallerSavedReg ) . addImm ( NumBytes ) ; BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP ) . addReg ( CallerSavedReg ) ; } else { BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) ) . addImm ( NumBytes ) . addMemOperand ( MMO ) ; } if ( AlignStack ) {

BuildMI ( MBB , InsertPt , dl , HII . get ( <STR_LIT> ) , SP ) . addReg ( SP ) . addImm ( - int64_t ( MaxAlign ) ) ;


<s> return TargetIRAnalysis ( [ this ] ( const Function & F ) { return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;


<s> emitKernelArg ( DL , Int64Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int16Ty , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; Offset += <NUM_LIT> ; auto Int8PtrTy = Type :: getInt8PtrTy ( Func . getContext ( ) , <ISA_LIT>AS :: GLOBAL_ADDRESS ) ; if ( M -> getNamedMetadata ( <STR_LIT> ) ) { emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; } else Offset += <NUM_LIT> ; if ( M -> getModuleFlag ( <STR_LIT> ) ) { emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; } else Offset += <NUM_LIT> ; emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; Offset += <NUM_LIT> ; if ( Func . hasFnAttribute ( <STR_LIT> ) ) { emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ; emitKernelArg ( DL , Int8PtrTy , Align ( <NUM_LIT> ) , <STR_LIT> , Offset , Args ) ;


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( DstReg ) && ( <STR_LIT> . contains ( DstReg ) || <STR_LIT> . contains ( DstReg ) ) ) return false ;

unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> case AMDGPU :: INTERP_PAIR_XY : case AMDGPU :: INTERP_PAIR_ZW : case AMDGPU :: INTERP_VEC_LOAD : case AMDGPU :: COPY : case AMDGPU :: DOT_4 : return true ; default :


<s> errs ( ) << <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! FeatureBits [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ; TargetABI = ABI_Unknown ; } else if ( ABIName . endswith ( <STR_LIT> ) && ! FeatureBits [ <STR_LIT> ] ) { errs ( ) << <STR_LIT> <STR_LIT> <STR_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

return Inst . getParent ( ) -> getParent ( ) -> getTarget ( ) . Options . UnsafeFPMath ;


<s> riscv_emit_stack_tie ( ) ; } if ( known_gt ( size , <NUM_LIT> ) ) { poly_int64 scalable_frame ( <NUM_LIT> , <NUM_LIT> ) ; if ( ! size . is_constant ( ) ) { poly_int64 scalable_frame = size ; scalable_frame . coeffs [ <NUM_LIT> ] = size . coeffs [ <NUM_LIT> ] ; riscv_v_adjust_scalable_frame ( stack_pointer_rtx , scalable_frame , false ) ; size -= scalable_frame ; } HOST_WIDE_INT constant_frame = size . to_constant ( ) ; if ( constant_frame == <NUM_LIT> ) return ; if ( SMALL_OPERAND ( - constant_frame ) ) { insn = gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , GEN_INT ( - constant_frame ) ) ; RTX_FRAME_RELATED_P ( emit_insn ( insn ) ) = <NUM_LIT> ; } else { riscv_emit_move ( RISCV_PROLOGUE_TEMP ( Pmode ) , GEN_INT ( - constant_frame ) ) ; emit_insn ( gen_add3_insn ( stack_pointer_rtx , stack_pointer_rtx , RISCV_PROLOGUE_TEMP ( Pmode ) ) ) ;

insn = plus_constant ( Pmode , stack_pointer_rtx , - constant_frame ) ;


<s> if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = GetOppositeBranchCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; }


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; R . AddMulPair ( PMul0 , PMul1 ) ; return true ; } else if ( AreSequentialLoads ( Ld3 , Ld2 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PMul1 -> Exchange = true ; R . AddMulPair ( PMul0 , PMul1 ) ; return true ; } } else if ( AreSequentialLoads ( Ld1 , Ld0 , PMul0 -> VecLd ) && AreSequentialLoads ( Ld2 , Ld3 , PMul1 -> VecLd ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; PMul0 -> Exchange = true ; R . AddMulPair ( PMul1 , PMul0 ) ; return true ; } return false ; } ; MulCandList & Muls = R . getMuls ( ) ; const unsigned Elems = Muls . size ( ) ; SmallPtrSet < const Instruction * , <NUM_LIT> > Paired ; for ( unsigned i = <NUM_LIT> ; i < Elems ; ++ i ) { MulCandidate * PMul0 = static_cast < MulCandidate * > ( Muls [ i ] . get ( ) ) ; if ( Paired . count ( PMul0 -> Root ) ) continue ; for ( unsigned j = <NUM_LIT> ; j < Elems ; ++ j ) { if ( i == j ) continue ; MulCandidate * PMul1 = static_cast < MulCandidate * > ( Muls [ j ] . get ( ) ) ; if ( Paired . count ( PMul1 -> Root ) ) continue ; const Instruction * Mul0 = PMul0 -> Root ; const Instruction * Mul1 = PMul1 -> Root ; if ( Mul0 == Mul1 ) continue ; assert ( PMul0 != PMul1 && <STR_LIT> ) ; if ( CanPair ( R , PMul0 , PMul1 ) ) {


<s> bool <ISA_LIT>PacketizerList :: promoteToDotNew ( MachineInstr * MI , SDep :: Kind DepType , MachineBasicBlock :: iterator & MII , const TargetRegisterClass * RC ) { assert ( DepType == SDep :: Data ) ; int NewOpcode ;

if ( RC == & <STR_LIT> ) NewOpcode = HII -> getDotNewPredOp ( MI , MBPI ) ;


<s> SDValue AMDGPUTargetLowering :: LowerFFLOOR ( SDValue Op , SelectionDAG & DAG ) const { SDLoc SL ( Op ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; SDValue Trunc = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; const SDValue Zero = DAG . getConstantFP ( <NUM_LIT> , SL , <STR_LIT> ) ; const SDValue NegOne = DAG . getConstantFP ( - <NUM_LIT> , SL , <STR_LIT> ) ; EVT SetCCVT = getSetCCResultType ( * DAG . getContext ( ) , <STR_LIT> ) ; SDValue Lt0 = DAG . getSetCC ( SL , SetCCVT , Src , Zero , <STR_LIT> ) ; SDValue NeTrunc = DAG . getSetCC ( SL , SetCCVT , Src , Trunc , <STR_LIT> ) ;

SDValue And = DAG . getNode ( <STR_LIT> , SL , SetCCVT , Lt0 , NeTrunc ) ;


<s> bool <ISA_LIT>ExpandPseudo :: runOnMachineFunction ( MachineFunction & MF ) { STI = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ; TII = STI -> getInstrInfo ( ) ; TRI = STI -> getRegisterInfo ( ) ; AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) Modified |= ExpandMBB ( * MFI ) ; if ( Verify<ISA_LIT>Pseudo ) MF . verify ( this , <STR_LIT> ) ;


<s> MCObjectWriter * llvm :: create<ISA_LIT>MachObjectWriter ( raw_ostream & OS , uint32_t CPUType , uint32_t CPUSubtype ) { return createMachObjectWriter ( new <ISA_LIT>MachObjectWriter ( CPUType , CPUSubtype ) , OS , true ) ;


<s> if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; return ( RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ) ;


<s> MCSection * <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const { if ( Kind . isReadOnly ( ) && <STR_LIT> ( GV ) && TM . getTargetTriple ( ) . getOS ( ) != Triple :: AMDHSA ) return TextSection ;

return TargetLoweringObjectFileELF :: SelectSectionForGlobal ( GV , Kind , Mang , TM ) ;


<s> use_iterator I = MRI -> use_begin ( Reg . R ) , E = MRI -> use_end ( ) ; if ( I == E ) { DEBUG ( dbgs ( ) << <STR_LIT> << PrintReg ( Reg . R , TRI , Reg . S ) << '\n' ) ;

MachineInstr * DefI = MRI -> getVRegDef ( Reg . R ) ;


<s> if ( ! Subtarget -> isTargetLinux ( ) ) return false ; if ( ForceGlobalVarStackProtectorCookie ) return false ; if ( Subtarget -> is64Bit ( ) ) { Offset = <NUM_LIT> ; if ( getTargetMachine ( ) . getCodeModel ( ) == CodeModel :: Kernel ) AddressSpace = <NUM_LIT> ; else AddressSpace = <NUM_LIT> ; } else { Offset = <NUM_LIT> ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & sti ) : TargetFrameLowering ( StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( sti ) {


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . setPreservesCFG ( ) ; AU . addPreservedID ( MachineLoopInfoID ) ;

AU . addPreservedID ( MachineDominatorsID ) ;


<s> LLVMContext & Ctx = OrigArg . Ty -> getContext ( ) ; SmallVector < EVT , <NUM_LIT> > SplitVTs ; SmallVector < uint64_t , <NUM_LIT> > Offsets ; ComputeValueVTs ( TLI , DL , OrigArg . Ty , SplitVTs , & Offsets , <NUM_LIT> ) ; assert ( SplitVTs . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SplitArgs . emplace_back ( OrigArg . Reg , SplitVTs [ <NUM_LIT> ] . getTypeForEVT ( Ctx ) , OrigArg . Flags , OrigArg . IsFixed ) ;


<s> void <ISA_LIT>InstPrinter :: printRegisterList ( const MCInst * MI , int opNum , raw_ostream & O ) { for ( int i = opNum , e = MI -> getNumOperands ( ) - <NUM_LIT> ; i != e ; ++ i ) { if ( i != opNum ) O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( i ) . getReg ( ) ) ;


<s> bool isHI32DSPAsm ( ) const { return Kind == k_Register && Reg . Kind == Kind_HI32DSP ;


<s> } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> BranchCode = static_cast < <STR_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ; <STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; if ( OldBranchCode == BranchCode ) continue ; return true ;


<s> return isNEONReplicate ( <NUM_LIT> , NumBytes , false , true ) ;


<s> uint32_t ShiftAmount = Log2_32 ( NumOfVReg - <NUM_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else if ( isPowerOf2_32 ( NumOfVReg + <NUM_LIT> ) ) { Register ScaledRegister = MRI . createVirtualRegister ( & <STR_LIT> ) ; uint32_t ShiftAmount = Log2_32 ( NumOfVReg + <NUM_LIT> ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , ScaledRegister ) . addReg ( VL ) . addImm ( ShiftAmount ) . setMIFlag ( Flag ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( ScaledRegister , RegState :: Kill ) . addReg ( VL , RegState :: Kill ) . setMIFlag ( Flag ) ; } else { Register N = MRI . createVirtualRegister ( & <STR_LIT> ) ; movImm ( MBB , II , DL , N , NumOfVReg , Flag ) ; if ( ! STI . hasStdExtM ( ) ) MF . getFunction ( ) . getContext ( ) . diagnose ( DiagnosticInfoUnsupported { MF . getFunction ( ) , <STR_LIT> } ) ; BuildMI ( MBB , II , DL , get ( <STR_LIT> ) , VL ) . addReg ( VL , RegState :: Kill ) . addReg ( N , RegState :: Kill ) . setMIFlag ( Flag ) ; }


<s> case CallingConv :: PreserveMost : return CSR_64_RT_MostRegs_SaveList ; case CallingConv :: PreserveAll : if ( HasAVX ) return CSR_64_RT_AllRegs_AVX_SaveList ; return CSR_64_RT_AllRegs_SaveList ; case CallingConv :: CXX_FAST_TLS : if ( Is64Bit ) return MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> isSplitCSR ( ) ? CSR_64_CXX_TLS_Darwin_PE_SaveList : CSR_64_TLS_Darwin_SaveList ; break ; case CallingConv :: Intel_OCL_BI : { if ( HasAVX512 && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX512 && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX512_SaveList ; if ( HasAVX && IsWin64 ) return CSR_Win64_Intel_OCL_BI_AVX_SaveList ; if ( HasAVX && Is64Bit ) return CSR_64_Intel_OCL_BI_AVX_SaveList ; if ( ! HasAVX && ! IsWin64 && Is64Bit ) return CSR_64_Intel_OCL_BI_SaveList ; break ; } case CallingConv :: HHVM : return CSR_64_HHVM_SaveList ; case CallingConv :: <ISA_LIT>_RegCall : if ( Is64Bit ) { if ( IsWin64 ) { return ( HasSSE ? CSR_Win64_RegCall_SaveList : CSR_Win64_RegCall_NoSSE_SaveList ) ; } else { return ( HasSSE ? CSR_SysV64_RegCall_SaveList : CSR_SysV64_RegCall_NoSSE_SaveList ) ; } } else { return ( HasSSE ? CSR_32_RegCall_SaveList : CSR_32_RegCall_NoSSE_SaveList ) ; } case CallingConv :: CFGuard_Check : assert ( ! Is64Bit && <STR_LIT> ) ; return ( HasSSE ? CSR_Win32_CFGuard_Check_SaveList : CSR_Win32_CFGuard_Check_NoSSE_SaveList ) ; case CallingConv :: Cold : if ( Is64Bit ) return CSR_64_MostRegs_SaveList ; break ; case CallingConv :: Win64 : if ( ! HasSSE ) return CSR_Win64_NoSSE_SaveList ; return CSR_Win64_SaveList ; case CallingConv :: <ISA_LIT>_64_SysV : if ( CallsEHReturn ) return CSR_64EHRet_SaveList ; return CSR_64_SaveList ; case CallingConv :: <ISA_LIT>_INTR : if ( Is64Bit ) { if ( HasAVX512 ) return CSR_64_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_64_AllRegs_AVX_SaveList ; if ( HasSSE ) return CSR_64_AllRegs_SaveList ; return CSR_64_AllRegs_NoSSE_SaveList ; } else { if ( HasAVX512 ) return CSR_32_AllRegs_AVX512_SaveList ; if ( HasAVX ) return CSR_32_AllRegs_AVX_SaveList ;

if ( HasSSE ) return CSR_32_AllRegs_SSE_SaveList ;


<s> Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI -> getType ( DstReg ) ; LLT SrcTy = MRI -> getType ( SrcReg ) ; const unsigned SrcSize = SrcTy . getSizeInBits ( ) ; const unsigned DstSize = DstTy . getSizeInBits ( ) ; unsigned Offset = I . getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Offset % <NUM_LIT> != <NUM_LIT> || DstSize > <NUM_LIT> ) return false ; const TargetRegisterClass * DstRC = TRI . getConstrainedRegClassForOperand ( I . getOperand ( <NUM_LIT> ) , * MRI ) ; if ( ! DstRC || ! RBI . constrainGenericRegister ( DstReg , * DstRC , * MRI ) ) return false ; const RegisterBank * SrcBank = RBI . getRegBank ( SrcReg , * MRI , TRI ) ; const TargetRegisterClass * SrcRC = TRI . getRegClassForSizeOnBank ( SrcSize , * SrcBank , * MRI ) ; if ( ! SrcRC ) return false ; unsigned SubReg = <ISA_LIT>RegisterInfo :: getSubRegFromChannel ( Offset / <NUM_LIT> , DstSize / <NUM_LIT> ) ; SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubReg ) ; if ( ! SrcRC ) return false ; SrcReg = constrainOperandRegClass ( * MF , TRI , * MRI , TII , RBI , I , * SrcRC , I . getOperand ( <NUM_LIT> ) ) ;

const DebugLoc & DL = I . getDebugLoc ( ) ;


<s> IdxList [ IdxC ++ ] = ConstantInt :: get ( Int32Ty , <NUM_LIT> ) ; } while ( ++ nax <= Num ) { GepNode * N = NA [ nax - <NUM_LIT> ] ; IdxList [ IdxC ++ ] = N -> Idx ; if ( nax < Num ) { Type * NextTy = next_type ( N -> PTy , N -> Idx ) ; if ( NextTy != NA [ nax ] -> PTy ) break ; } } ArrayRef < Value * > A ( IdxList , IdxC ) ; Type * InpTy = Input -> getType ( ) ; Type * ElTy = cast < PointerType > ( InpTy -> getScalarType ( ) ) -> getElementType ( ) ; NewInst = GetElementPtrInst :: Create ( ElTy , Input , A , <STR_LIT> , & * At ) ;

DEBUG ( dbgs ( ) << <STR_LIT> << * NewInst << '\n' ) ;


<s> const <ISA_LIT>FrameLowering & TFI = * getFrameLowering ( MF ) ;


<s> static int stackSlotSize ( ) { return <NUM_LIT> ;


<s> OutgoingArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , MachineInstrBuilder MIB , CCAssignFn * AssignFn ) : ValueHandler ( MIRBuilder , MRI , AssignFn ) , MIB ( MIB ) {


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; if ( isSupportedMnemo ( Mnemo , FBS , getMatchedVariants ( ) ) ) return false ; getParser ( ) . clearPendingErrors ( ) ; StringRef VariantName = getMatchedVariantName ( ) ; if ( ! VariantName . empty ( ) && isSupportedMnemo ( Mnemo , FBS ) ) { return Error ( IDLoc , Twine ( VariantName , <STR_LIT> ) ) ; } if ( isSupportedMnemo ( Mnemo , FeatureBitset ( ) . set ( ) ) ) { return Error ( IDLoc , <STR_LIT> ) ; } std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( Mnemo , FBS ) ; return Error ( IDLoc , <STR_LIT> + Suggestion ) ;


<s> O << getRegisterName ( MO . getReg ( ) ) ; } else if ( MO . isImm ( ) ) { O << MO . getImm ( ) ;


<s> const MCExpr * Expr = MCSymbolRefExpr :: create ( getSymbol ( RVCPV -> getGlobalValue ( ) ) , getModifierVariantKind ( RVCPV -> getModifier ( ) ) , OutContext ) ; uint64_t Size = getDataLayout ( ) . getTypeAllocSize ( RVCPV -> getType ( ) ) ; OutStreamer -> EmitValue ( Expr , Size ) ;


<s> FieldInit += IDStr ; if ( isa < StructType > ( ElmTy ) ) FieldInit += <STR_LIT> ; else FieldInit += <STR_LIT> ; FieldInit += ElmTyStr ; FieldInit += <STR_LIT> ; FieldInit += ClassName ; FieldInit += <STR_LIT> ; IDStr [ <NUM_LIT> ] = '\0' ; sprintf ( IDStr , <STR_LIT> , FieldID ) ; FieldInit += IDStr ; FieldInit += <STR_LIT> ; MFI -> getTypeDescriptor ( Ty , FieldInit ) ; if ( isa < StructType > ( ElmTy ) ) { for ( unsigned i = <NUM_LIT> ; i < NumElm ; i ++ ) { FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += ClassName ; FieldInit += <STR_LIT> ; IDStr [ <NUM_LIT> ] = '\0' ; sprintf ( IDStr , <STR_LIT> , FieldID ) ; FieldInit += IDStr ; FieldInit += <STR_LIT> ; MFI -> getTypeDescriptor ( Ty , FieldInit ) ; if ( i < <NUM_LIT> ) FieldInit += <STR_LIT> ; else FieldInit += <STR_LIT> ; IDStr [ <NUM_LIT> ] = '\0' ; sprintf ( IDStr , <STR_LIT> , i ) ; FieldInit += IDStr ; FieldInit += <STR_LIT> ; FieldInit += ElmTyStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += ElmTyStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; } } } else if ( isa < StructType > ( Ty ) ) { char IDStr [ <NUM_LIT> ] = { '\0' } ; std :: string TypeStr = EmitTypeString ( Ty ) ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += TypeStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += TypeStr ; FieldInit += <STR_LIT> ; FieldInit += <STR_LIT> ; FieldInit += ClassName ; FieldInit += <STR_LIT> ;


<s> if ( SubVer >= '7' && SubVer <= '9' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) { <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'e' && TT [ Idx + <NUM_LIT> ] == 'm' ) { <ISA_LIT>ArchFeature = <STR_LIT> ; } else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '6' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == '2' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 'm' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '5' ) { if ( Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' && TT [ Idx + <NUM_LIT> ] == 'e' ) <ISA_LIT>ArchFeature = <STR_LIT> ; else <ISA_LIT>ArchFeature = <STR_LIT> ; } else if ( SubVer == '4' && Len >= Idx + <NUM_LIT> && TT [ Idx + <NUM_LIT> ] == 't' ) <ISA_LIT>ArchFeature = <STR_LIT> ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == OtherModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } if ( type == MVEVMVNModImm ) return SDValue ( ) ; if ( ( SplatBits & ~ <NUM_LIT> ) == <NUM_LIT> && ( ( SplatBits | SplatUndef ) & <NUM_LIT> ) == <NUM_LIT> ) { OpCmode = <NUM_LIT> ; Imm = SplatBits >> <NUM_LIT> ; break ; } return SDValue ( ) ; case <NUM_LIT> : { if ( type != VMOVModImm ) return SDValue ( ) ; uint64_t BitMask = <NUM_LIT> ; uint64_t Val = <NUM_LIT> ; unsigned ImmMask = <NUM_LIT> ;


<s> Root = SPScope :: createSPScopeTree ( MF , getAnalysis < MachineLoopInfo > ( ) , TII ) ;


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) {


<s> case <STR_LIT> : return expandSelectCC ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return emitEHSjLjSetJmp ( MI , BB ) ; case <STR_LIT> : case <STR_LIT> :


<s> getAddrMode5OpValue ( const MCInst & MI , unsigned OpIdx , SmallVectorImpl < MCFixup > & Fixups ) const { unsigned Reg , Imm8 ; bool isAdd ; const MCOperand & MO = MI . getOperand ( OpIdx ) ; if ( ! MO . isReg ( ) ) { Reg = get<ISA_LIT>RegisterNumbering ( <STR_LIT> ) ; Imm8 = <NUM_LIT> ; isAdd = false ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; MCFixupKind Kind ;

if ( isThumb2 ( ) ) Kind = MCFixupKind ( <STR_LIT> ) ;


<s> int <ISA_LIT>TTIImpl :: getMemcpyCost ( const Instruction * I ) { const MemCpyInst * MI = dyn_cast < MemCpyInst > ( I ) ; assert ( MI && <STR_LIT> ) ; ConstantInt * C = dyn_cast < ConstantInt > ( MI -> getLength ( ) ) ; const unsigned LibCallCost = <NUM_LIT> ;


<s> if ( getMemOperandWithOffsetWidth ( MIa , BaseOpA , OffsetA , WidthA , TRI ) && getMemOperandWithOffsetWidth ( MIb , BaseOpB , OffsetB , WidthB , TRI ) ) { if ( BaseOpA -> isIdenticalTo ( * BaseOpB ) ) { int LowOffset = std :: min ( OffsetA , OffsetB ) ; int HighOffset = std :: max ( OffsetA , OffsetB ) ; int LowWidth = ( LowOffset == OffsetA ) ? WidthA : WidthB ;

if ( LowOffset + LowWidth <= HighOffset ) return true ;


<s> MachineSDNode * NewNode = nullptr ; auto Type0 = N -> getValueType ( <NUM_LIT> ) ; auto Type1 = N -> getValueType ( <NUM_LIT> ) ; auto Op0 = N -> getOperand ( <NUM_LIT> ) ; auto Op1 = N -> getOperand ( <NUM_LIT> ) ; auto Op2 = N -> getOperand ( <NUM_LIT> ) ; SDLoc Dl ( N ) ; if ( isNullConstant ( Op2 ) ) { auto * CA = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , Type1 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , SDValue ( CA , <NUM_LIT> ) } ) ; } else if ( isOneConstant ( Op2 ) ) { auto * CA = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , Type1 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , SDValue ( CA , <NUM_LIT> ) } ) ; } else { NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , Op2 } ) ; }


<s> const MCSymbolRefExpr * SRE ; if ( const MCBinaryExpr * BE = dyn_cast < MCBinaryExpr > ( Expr ) ) { SRE = dyn_cast < MCSymbolRefExpr > ( BE -> getLHS ( ) ) ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( BE -> getRHS ( ) ) ; assert ( SRE && CE && <STR_LIT> ) ; Offset = CE -> getValue ( ) ; } else { SRE = dyn_cast < MCSymbolRefExpr > ( Expr ) ; assert ( SRE && <STR_LIT> ) ; } const MCSymbolRefExpr :: VariantKind Kind = SRE -> getKind ( ) ; assert ( Kind == MCSymbolRefExpr :: VK_None || Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_LO || Kind == MCSymbolRefExpr :: VK_<ISA_LIT>_HI ) ; OS << SRE -> getSymbol ( ) ; if ( Offset ) { if ( Offset > <NUM_LIT> ) { OS << '+' ;


<s> void <ISA_LIT>MCInstrInfo :: SetImplicitBits ( MCInst & MCI , std :: bitset < <NUM_LIT> > Bits ) { SanityCheckImplicitOperands ( MCI ) ;

MCI . getOperand ( MCI . getNumOperands ( ) - <NUM_LIT> ) . setImm ( Bits . to_ulong ( ) ) ;


<s> return Error ( IDLoc , <STR_LIT> ) ; } Inst . setOpcode ( Inst . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; Out . emitInstruction ( Inst , getSTI ( ) ) ; return false ; } else if ( Inst . getOpcode ( ) == <STR_LIT> || Inst . getOpcode ( ) == <STR_LIT> ) { if ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) < Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) return Error ( IDLoc , <STR_LIT> ) ; } else if ( Inst . getOpcode ( ) == <STR_LIT> ) { if ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) < Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ) return Error ( IDLoc , <STR_LIT> ) ; } else if ( Inst . getOpcode ( ) == <STR_LIT> ) { if ( Inst . getOperand ( <NUM_LIT> ) . getImm ( ) > <NUM_LIT> || Inst . getOperand ( <NUM_LIT> ) . getImm ( ) < <NUM_LIT> ) return Error ( IDLoc , <STR_LIT> ) ; } Out . emitInstruction ( Inst , getSTI ( ) ) ;


<s> printMemReference ( MI , OpNo , O ) ;


<s> x = gen_rtx_AND ( mode , cmp , operands [ <NUM_LIT> + negate ] ) ; emit_insn ( gen_rtx_SET ( t , x ) ) ; f = gen_reg_rtx ( mode ) ; x = gen_rtx_NOT ( mode , cmp ) ; x = gen_rtx_AND ( mode , x , operands [ <NUM_LIT> - negate ] ) ; emit_insn ( gen_rtx_SET ( f , x ) ) ; x = gen_rtx_IOR ( mode , t , f ) ; emit_insn ( gen_rtx_SET ( operands [ <NUM_LIT> ] , x ) ) ; }


<s> void <ISA_LIT>TargetWasmStreamer :: emitResult ( MCSymbol * Symbol , ArrayRef < MVT > Types ) {


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( Subtarget -> isSingleFloat ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; if ( ! Subtarget -> hasSEInReg ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> Update = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ;

Opc = CurDAG -> getTargetConstant ( <STR_LIT> ( false ) , <STR_LIT> ) ;


<s> SDValue ChainLo1 = ChainLo , ChainLo2 = ChainLo , ChainHi1 = ChainHi , ChainHi2 = ChainHi ; if ( ChainLo . getOpcode ( ) == <STR_LIT> ) { ChainLo1 = ChainLo . getOperand ( <NUM_LIT> ) ; ChainLo2 = ChainLo . getOperand ( <NUM_LIT> ) ; } if ( ChainHi . getOpcode ( ) == <STR_LIT> ) { ChainHi1 = ChainHi . getOperand ( <NUM_LIT> ) ; ChainHi2 = ChainHi . getOperand ( <NUM_LIT> ) ; } SDValue Store1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ChainLo1 , SrcLo1 , PtrLo , PtrHi , DAG . getConstant ( <NUM_LIT> + StoreOffset , <STR_LIT> ) ) ; SDValue Store2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ChainLo2 , SrcLo2 , PtrLo , PtrHi , DAG . getConstant ( <NUM_LIT> + StoreOffset , <STR_LIT> ) ) ; SDValue Store3 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ChainHi1 , SrcHi1 , PtrLo , PtrHi , DAG . getConstant ( <NUM_LIT> + StoreOffset , <STR_LIT> ) ) ; SDValue Store4 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ChainHi2 , SrcHi2 , PtrLo , PtrHi , DAG . getConstant ( <NUM_LIT> + StoreOffset , <STR_LIT> ) ) ; SDValue RetLo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , getChain ( Store1 ) , getChain ( Store2 ) ) ; SDValue RetHi = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , getChain ( Store3 ) , getChain ( Store4 ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , RetLo , RetHi ) ; } else if ( ValueType == <STR_LIT> ) { SDValue SrcLo , SrcHi ; GetExpandedParts ( Src , DAG , SrcLo , SrcHi ) ; SDValue ChainLo = Chain , ChainHi = Chain ; if ( Chain . getOpcode ( ) == <STR_LIT> ) { ChainLo = Chain . getOperand ( <NUM_LIT> ) ; ChainHi = Chain . getOperand ( <NUM_LIT> ) ; } SDValue Store1 = DAG . getStore ( ChainLo , dl , SrcLo , Ptr , NULL , <NUM_LIT> + StoreOffset ) ;

Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , DAG . getConstant ( <NUM_LIT> , Ptr . getValueType ( ) ) ) ;


<s> emit_label ( label ) ; label = gen_rtx_LABEL_REF ( DImode , label ) ; if ( before == NULL ) before = scratch ; emit_load_locked ( mode , before , mem ) ; if ( code == NOT ) x = gen_rtx_AND ( mode , gen_rtx_NOT ( mode , before ) , val ) ; else x = gen_rtx_fmt_ee ( code , mode , before , val ) ; if ( after ) emit_insn ( gen_rtx_SET ( VOIDmode , after , copy_rtx ( x ) ) ) ;

emit_insn ( gen_rtx_SET ( VOIDmode , scratch , x ) ) ;


<s> return BaseT :: getOperandsScalarizationOverhead ( Args , Tys ) ;


<s> bool <ISA_LIT>CFGStructurizer :: isCondBranch ( MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) {


<s> unsigned Offset = <NUM_LIT> ; unsigned LocMemOffset = <NUM_LIT> ; unsigned MemCpySize = ByValSize ; if ( ! IsRegLoc ) LocMemOffset = VA . getLocMemOffset ( ) ; else { const unsigned * Reg = std :: find ( <ISA_LIT>64IntRegs , <ISA_LIT>64IntRegs + <NUM_LIT> , VA . getLocReg ( ) ) ; const unsigned * RegEnd = <ISA_LIT>64IntRegs + <NUM_LIT> ; for ( ; ( Reg != RegEnd ) && ( ByValSize >= Offset + <NUM_LIT> ) ; ++ Reg , Offset += <NUM_LIT> ) { SDValue LoadPtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getLoad ( <STR_LIT> , dl , Chain , LoadPtr , MachinePointerInfo ( ) , false , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; RegsToPass . push_back ( std :: make_pair ( * Reg , LoadVal ) ) ; } if ( ! ( MemCpySize = ByValSize - Offset ) ) return ; if ( Reg != RegEnd ) { assert ( ( ByValSize < Offset + <NUM_LIT> ) && <STR_LIT> ) ; SDValue Val ; for ( unsigned LoadSize = <NUM_LIT> ; Offset < ByValSize ; LoadSize /= <NUM_LIT> ) { unsigned RemSize = ByValSize - Offset ; if ( RemSize < LoadSize ) continue ; SDValue LoadPtr = DAG . getNode ( <STR_LIT> , dl , PtrTy , Arg , DAG . getConstant ( Offset , PtrTy ) ) ; SDValue LoadVal = DAG . getExtLoad ( <STR_LIT> , dl , <STR_LIT> , Chain , LoadPtr , MachinePointerInfo ( ) , <STR_LIT> ( LoadSize * <NUM_LIT> ) , false , false , Alignment ) ; MemOpChains . push_back ( LoadVal . getValue ( <NUM_LIT> ) ) ; unsigned OffsetDW = ( Offset % <NUM_LIT> ) * <NUM_LIT> ; unsigned Shamt = isLittle ? OffsetDW : <NUM_LIT> - ( OffsetDW + LoadSize * <NUM_LIT> ) ; SDValue Shift = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LoadVal , DAG . getConstant ( Shamt , <STR_LIT> ) ) ; Val = Val . getNode ( ) ? DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Val , Shift ) :


<s> static bool write_as_kernel ( tree attrs ) { return ( lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE || lookup_attribute ( <STR_LIT> , attrs ) != NULL_TREE ) ;


<s> auto * HalfTy = HalfV -> getType ( ) ; return FullTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) == <NUM_LIT> * HalfTy -> getPrimitiveSizeInBits ( ) . getFixedSize ( ) ; } ; auto extractHalf = [ ] ( Value * FullV , Value * HalfV ) { auto * FullVT = cast < FixedVectorType > ( FullV -> getType ( ) ) ; auto * HalfVT = cast < FixedVectorType > ( HalfV -> getType ( ) ) ; return FullVT -> getNumElements ( ) == <NUM_LIT> * HalfVT -> getNumElements ( ) ; } ; ArrayRef < int > M1 , M2 ; Value * S1Op1 , * S2Op1 ; if ( ! match ( Op1 , m_Shuffle ( m_Value ( S1Op1 ) , m_Undef ( ) , m_Mask ( M1 ) ) ) || ! match ( Op2 , m_Shuffle ( m_Value ( S2Op1 ) , m_Undef ( ) , m_Mask ( M2 ) ) ) ) return false ; if ( ! areTypesHalfed ( S1Op1 , Op1 ) || ! areTypesHalfed ( S2Op1 , Op2 ) || ! extractHalf ( S1Op1 , Op1 ) || ! extractHalf ( S2Op1 , Op2 ) ) return false ;


<s> return ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasVarSizedObjects ( ) || MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getManipulatesSP ( ) ) ;


<s> return ( Attributes & KMergeMasked ) != <NUM_LIT> ;


<s> return DecodeMem ( Inst , insn , Address , Decoder , false , DecodeI64RegisterClass ) ;


<s> MF . getFunction ( ) . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) . getAsInteger ( <NUM_LIT> , StackProbeSize ) ; } NoStackArgProbe = MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ; if ( NoStackArgProbe ) StackProbeSize = INT64_MAX ; LoweringMap Lowerings ; computeLowerings ( MF , Lowerings ) ; for ( auto & P : Lowerings ) lower ( P . first , P . second ) ;


<s> unsigned Rm = decodeRm ( insn ) ; unsigned Rd = decodeNEONRd ( insn ) ; bool WB = Rm != <NUM_LIT> ; unsigned RmEnum = <NUM_LIT> ; if ( WB && Rm != <NUM_LIT> ) RmEnum = getRegisterEnum ( B , <STR_LIT> , Rm ) ; if ( Store ) { assert ( OpIdx < NumOps && OpInfo [ <NUM_LIT> ] . RegClass == <STR_LIT> && <STR_LIT> ) ; if ( WB ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Rn ) ) ) ; ++ OpIdx ; } assert ( ( OpIdx + <NUM_LIT> ) < NumOps && OpInfo [ OpIdx ] . RegClass == <STR_LIT> && OpInfo [ OpIdx + <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Rn ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ; OpIdx += <NUM_LIT> ; if ( WB ) { MI . addOperand ( MCOperand :: CreateReg ( RmEnum ) ) ; ++ OpIdx ; } assert ( OpIdx < NumOps && ( OpInfo [ OpIdx ] . RegClass == <STR_LIT> || OpInfo [ OpIdx ] . RegClass == <STR_LIT> ) && <STR_LIT> ) ; RegClass = OpInfo [ OpIdx ] . RegClass ; while ( OpIdx < NumOps && ( unsigned ) OpInfo [ OpIdx ] . RegClass == RegClass ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , Rd , DRegPair ) ) ) ; Rd += Inc ; ++ OpIdx ; } if ( OpIdx < NumOps && OpInfo [ OpIdx ] . RegClass < <NUM_LIT> && ! OpInfo [ OpIdx ] . isPredicate ( ) && ! OpInfo [ OpIdx ] . isOptionalDef ( ) ) { MI . addOperand ( MCOperand :: CreateImm ( decodeLaneIndex ( insn ) ) ) ; ++ OpIdx ; } } else { RegClass = OpInfo [ <NUM_LIT> ] . RegClass ; while ( OpIdx < NumOps && ( unsigned ) OpInfo [ OpIdx ] . RegClass == RegClass ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , RegClass , Rd , DRegPair ) ) ) ; Rd += Inc ; ++ OpIdx ; } if ( WB ) { MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Rn ) ) ) ; ++ OpIdx ; } assert ( ( OpIdx + <NUM_LIT> ) < NumOps && OpInfo [ OpIdx ] . RegClass == <STR_LIT> && OpInfo [ OpIdx + <NUM_LIT> ] . RegClass < <NUM_LIT> && <STR_LIT> ) ; MI . addOperand ( MCOperand :: CreateReg ( getRegisterEnum ( B , <STR_LIT> , Rn ) ) ) ; MI . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;


<s> static bool ft32_frame_pointer_required ( void ) {


<s> NodeAddr < BlockNode * > FuncNode :: getEntryBlock ( const DataFlowGraph & G ) { MachineBasicBlock * EntryB = & getCode ( ) -> front ( ) ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( LLVMContext & Context , EVT VT ) const { return <STR_LIT> ;


<s> const MUBUFInfo * Info = getMUBUFOpcodeHelper ( Opc ) ; return Info ? Info -> has_vaddr : false ;


<s> break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( ArgReg ) ; CLI . OutRegs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { return false ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; if ( isa < UndefValue > ( ArgVal ) ) continue ; unsigned ArgSize = ( ArgVT . getSizeInBits ( ) + <NUM_LIT> ) / <NUM_LIT> ; unsigned BEAlign = <NUM_LIT> ; if ( ArgSize < <NUM_LIT> && ! Subtarget -> isLittleEndian ( ) ) BEAlign = <NUM_LIT> - ArgSize ; Address Addr ; Addr . setKind ( Address :: RegBase ) ; Addr . setReg ( <STR_LIT> ) ; Addr . setOffset ( VA . getLocMemOffset ( ) + BEAlign ) ; Align Alignment = DL . getABITypeAlign ( ArgVal -> getType ( ) ) ; MachineMemOperand * MMO = FuncInfo . MF -> getMachineMemOperand ( MachinePointerInfo :: getStack ( * FuncInfo . MF , Addr . getOffset ( ) ) , MachineMemOperand :: MOStore , ArgVT . getStoreSize ( ) , Alignment ) ;

if ( ! emitStore ( ArgVT , ArgReg , Addr , MMO ) ) return false ;


<s> <ISA_LIT>MCInstLower ( MCContext & Ctx , AsmPrinter & Printer ) : Ctx ( Ctx ) , Printer ( Printer ) {


<s> int mmix_function_arg_regno_p ( int regno , int incoming ) {


<s> if ( ! has_vector_insn ( cfun ) ) return <NUM_LIT> ; init ( ) ; if ( ! optimize ) simple_vsetvl ( ) ; else lazy_vsetvl ( ) ; done ( ) ;


<s> if ( sh_multcost >= <NUM_LIT> ) return sh_multcost ; if ( TARGET_SHMEDIA ) return optimize_size ? <NUM_LIT> : <NUM_LIT> ; if ( TARGET_SH2 ) { if ( optimize_size ) return <NUM_LIT> ; return <NUM_LIT> ; }


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue DestBB = Op . getOperand ( <NUM_LIT> ) ; if ( LHS . getValueType ( ) == <STR_LIT> ) { softenSetCCOperands ( DAG , <STR_LIT> , LHS , RHS , CC , dl ) ; if ( RHS . getNode ( ) == <NUM_LIT> ) { RHS = DAG . getConstant ( <NUM_LIT> , LHS . getValueType ( ) ) ; CC = <STR_LIT> ; } } if ( LHS . getValueType ( ) . isInteger ( ) ) { SDValue A64cc ; SDValue CmpOp = getSelectableIntSetCC ( LHS , RHS , CC , A64cc , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , CmpOp , A64cc , DestBB ) ; } <STR_LIT> CondCode , Alternative = <STR_LIT> ; CondCode = FPCCToA64CC ( CC , Alternative ) ; SDValue A64cc = DAG . getConstant ( CondCode , <STR_LIT> ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS , DAG . getCondCode ( CC ) ) ; SDValue A64BR_CC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , SetCC , A64cc , DestBB ) ; if ( Alternative != <STR_LIT> ) { A64cc = DAG . getConstant ( Alternative , <STR_LIT> ) ; A64BR_CC = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , A64BR_CC , SetCC , A64cc , DestBB ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , VT , ResLo , ResHi ) ; } } else { unsigned ReducedSizeInBits = ReducedVT . getSizeInBits ( ) ; if ( ( RegSize % ReducedSizeInBits ) != <NUM_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( RegSize / ReducedSizeInBits , DAG . getUNDEF ( ReducedVT ) ) ; Ops [ <NUM_LIT> ] = NewN0 ; NewN0 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; Ops [ <NUM_LIT> ] = NewN1 ; NewN1 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; if ( Mode == MULU8 || Mode == MULS8 ) { SDValue Mul = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue Res = DAG . getNode ( Mode == MULU8 ? <STR_LIT> : <STR_LIT> , DL , ResVT , Mul ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } else { SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ;

SDValue Res = getUnpackl ( DAG , DL , OpsVT , MulLo , MulHi ) ;


<s> if ( ! SetHiMI -> getOperand ( <NUM_LIT> ) . isImm ( ) ) return false ; int64_t imm = SetHiMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( imm ) ) return false ; imm = ( imm << <NUM_LIT> ) & <NUM_LIT> ; assert ( RestoreMI -> getOpcode ( ) == <STR_LIT> ) ; RestoreMI -> setDesc ( TII -> get ( <STR_LIT> ) ) ;

RestoreMI -> getOperand ( <NUM_LIT> ) . setReg ( reg - <STR_LIT> + <STR_LIT> ) ;


<s> if ( Kind == MCExpr :: Binary ) { unsigned Res = getExprOpValue ( cast < MCBinaryExpr > ( Expr ) -> getLHS ( ) , Fixups , STI ) ; Res += getExprOpValue ( cast < MCBinaryExpr > ( Expr ) -> getRHS ( ) , Fixups , STI ) ; return Res ; } if ( Kind == MCExpr :: Target ) { const <ISA_LIT>MCExpr * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Expr ) ; <STR_LIT> FixupKind = <STR_LIT> ( <NUM_LIT> ) ; switch ( <ISA_LIT>Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: CEK_GPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOT_CALL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOT : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_ABS_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_ABS_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_TLSGD : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_TLSLDM : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_DTP_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_DTP_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOTTPREL : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_TP_HI : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_TP_LO : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOT_HI16 : FixupKind = <STR_LIT> ; break ; case <ISA_LIT>MCExpr :: CEK_GOT_LO16 : FixupKind = <STR_LIT> ; break ; } Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , MCFixupKind ( FixupKind ) ) ) ; return <NUM_LIT> ; }


<s> Scale = <NUM_LIT> ; isT2 = true ; } else if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { NewOpc = <STR_LIT> ; Scale = <NUM_LIT> ; isT2 = true ; } else return false ; if ( ! Op0 -> hasOneMemOperand ( ) || ! ( * Op0 -> memoperands_begin ( ) ) -> getValue ( ) || ( * Op0 -> memoperands_begin ( ) ) -> isVolatile ( ) ) return false ; unsigned Align = ( * Op0 -> memoperands_begin ( ) ) -> getAlignment ( ) ; const Function * Func = MF -> getFunction ( ) ; unsigned ReqAlign = STI -> hasV6Ops ( ) ? TD -> getABITypeAlignment ( Type :: getInt64Ty ( Func -> getContext ( ) ) ) : <NUM_LIT> ; if ( Align < ReqAlign ) return false ; int OffImm = getMemoryOpOffset ( Op0 ) ; if ( isT2 ) { int Limit = ( <NUM_LIT> << <NUM_LIT> ) * Scale ;

if ( OffImm >= Limit || ( OffImm <= - Limit ) || ( OffImm & ( Scale - <NUM_LIT> ) ) ) return false ;


<s> rtx rv ; machine_mode mode = TYPE_MODE ( valtype ) ; if ( ! POINTER_TYPE_P ( valtype ) ) return gen_rtx_REG ( mode , FIRST_DATA_REGNUM ) ;

else if ( ! TARGET_PTR_A0D0 || ! outgoing || cfun -> returns_struct ) return gen_rtx_REG ( mode , FIRST_ADDRESS_REGNUM ) ;


<s> unsigned Opcode = MCID . getOpcode ( ) ; if ( ! ( <STR_LIT> ( Opcode ) || <STR_LIT> ( Opcode ) || <STR_LIT> ( Opcode ) ) ) return - <NUM_LIT> ;

unsigned NumUses = MCID . getNumOperands ( ) - MCID . getNumDefs ( ) ;


<s> unsigned RelaxedOp = getRelaxedOpcode ( Inst , Is16BitMode ) ; if ( RelaxedOp == Inst . getOpcode ( ) ) { SmallString < <NUM_LIT> > Tmp ; raw_svector_ostream OS ( Tmp ) ; Inst . dump_pretty ( OS ) ; OS << <STR_LIT> ;

report_fatal_error ( <STR_LIT> + OS . str ( ) ) ;


<s> void <ISA_LIT>MCAsmStreamer :: FinishImpl ( ) { flushValues ( ) ; flushLabel ( true ) ; for ( auto * Symbol : Symbols ) { if ( Symbol -> isUndefined ( ) ) { OS << <STR_LIT> ; Symbol -> print ( OS , MAI ) ; EmitEOL ( ) ;


<s> unsigned Bits = getBinaryCodeForInstr ( MI , Fixups , STI ) ; if ( Ctx . getAsmInfo ( ) -> isLittleEndian ( ) ) { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } else { <STR_LIT> :: Writer < <STR_LIT> > ( OS ) . write < uint32_t > ( Bits ) ; } unsigned tlsOpNo = <NUM_LIT> ; switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : tlsOpNo = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : tlsOpNo = <NUM_LIT> ; break ; } if ( tlsOpNo != <NUM_LIT> ) { const MCOperand & MO = MI . getOperand ( tlsOpNo ) ; uint64_t op = getMachineOpValue ( MI , MO , Fixups , STI ) ; assert ( op == <NUM_LIT> && <STR_LIT> ) ; ( void ) op ; }


<s> unsigned align = fieldFromInstruction32 ( Val , <NUM_LIT> , <NUM_LIT> ) ; if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , Rm , Address , Decoder ) ) ) return MCDisassembler :: Fail ;

if ( ! align ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;


<s> std :: vector < std :: string > max_gt_r0 ( Ax a , StepZIDS bs ) { return D ( <STR_LIT> , R ( a ) , <STR_LIT> , bs ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const {


<s> if ( RC == & <STR_LIT> || RC == & <STR_LIT> ) return & <STR_LIT> ; return RC ;


<s> gep_type_iterator GTI = gep_type_begin ( U ) ; for ( User :: const_op_iterator i = U -> op_begin ( ) + <NUM_LIT> , e = U -> op_end ( ) ; i != e ; ++ i , ++ GTI ) { const Value * Op = * i ; if ( StructType * STy = dyn_cast < StructType > ( * GTI ) ) { const StructLayout * SL = DL . getStructLayout ( STy ) ; unsigned Idx = cast < ConstantInt > ( Op ) -> getZExtValue ( ) ; TmpOffset += SL -> getElementOffset ( Idx ) ; } else { uint64_t S = DL . getTypeAllocSize ( GTI . getIndexedType ( ) ) ; for ( ; ; ) { if ( const ConstantInt * CI = dyn_cast < ConstantInt > ( Op ) ) { TmpOffset += CI -> getSExtValue ( ) * S ; break ; } if ( canFoldAddIntoGEP ( U , Op ) ) { ConstantInt * CI = cast < ConstantInt > ( cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ) ; TmpOffset += CI -> getSExtValue ( ) * S ; Op = cast < AddOperator > ( Op ) -> getOperand ( <NUM_LIT> ) ; continue ; } goto unsupported_gep ; } } } Addr . setOffset ( TmpOffset ) ; if ( ComputeAddress ( U -> getOperand ( <NUM_LIT> ) , Addr ) ) return true ; Addr = SavedAddr ; unsupported_gep : break ; } case Instruction :: Alloca : { const AllocaInst * AI = cast < AllocaInst > ( Obj ) ; DenseMap < const AllocaInst * , int > :: iterator SI = FuncInfo . StaticAllocaMap . find ( AI ) ; if ( SI != FuncInfo . StaticAllocaMap . end ( ) ) { Addr . setKind ( Address :: FrameIndexBase ) ; Addr . setFI ( SI -> second ) ; return true ; } break ; } } if ( ! Addr . isValid ( ) ) Addr . setReg ( getRegForValue ( Obj ) ) ;


<s> const MachineInstr & J = * MII ; return producesStall ( J , MI ) ; } for ( ++ MII ; MII != MIE && MII -> isInsideBundle ( ) ; ++ MII ) { const MachineInstr & J = * MII ; if ( producesStall ( J , MI ) ) return true ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , raw_ostream & O , StringRef Annot ) { printInstruction ( MI , O ) ;


<s> if ( x ) { return profile_probability :: from_reg_br_prob_note ( XINT ( x , <NUM_LIT> ) ) >= profile_probability :: even ( ) ; }


<s> if ( I != MBB . begin ( ) ) I -- ; else return Changed ; if ( I -> getOpcode ( ) == <STR_LIT> && I -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & MBBN ) { ++ NumDelJmp ; MBB . erase ( I ) ; Changed = true ; } return Changed ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackendEL32 ( const Target & T , const MCRegisterInfo & MRI , StringRef TT , StringRef CPU ) { if ( Triple ( TT ) . isOSNaCl ( ) ) return new NaCl<ISA_LIT>AsmBackend ( T , false ) ; return new <ISA_LIT>AsmBackend ( T , Triple ( TT ) . getOS ( ) , true , false ) ;


<s> Value * Src = ZExt -> getOperand ( <NUM_LIT> ) ; if ( ZExt -> getSrcTy ( ) == ZExt -> getDestTy ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * ZExt << <STR_LIT> ) ; ReplaceAllUsersOfWith ( ZExt , Src ) ; continue ; } if ( NewInsts . count ( Src ) && isa < TruncInst > ( Src ) && Src -> getType ( ) == OrigTy ) {

auto * Trunc = cast < TruncInst > ( Src ) ;


<s> MCInst TmpInst ; TmpInst . setOpcode ( MI -> getOpcode ( ) ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( Lower<ISA_LIT>MachineOperandToMCOperand ( MO , MCOp , * this ) ) TmpInst . addOperand ( MCOp ) ;


<s> unsigned e = VT . getVectorNumElements ( ) / <NUM_LIT> ;

for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) if ( ! isUndefOrEqual ( Mask [ i ] , i ) ) return false ;


<s> return AsmToken ( lexedToken ) ; case AsmToken :: Percent : { const AsmToken & nextToken = lexTentative ( ) ; if ( nextToken . getKind ( ) == AsmToken :: Identifier ) { unsigned regID = MatchRegisterName ( nextToken . getString ( ) ) ; if ( regID ) { lexDefinite ( ) ; StringRef regStr ( lexedToken . getString ( ) . data ( ) , lexedToken . getString ( ) . size ( ) + nextToken . getString ( ) . size ( ) ) ; return AsmToken ( AsmToken :: Register , regStr , static_cast < int64_t > ( regID ) ) ; } else { return AsmToken ( lexedToken ) ; } } else { return AsmToken ( lexedToken ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < Size ; i ++ ) { EmitByte ( Code , OS ) ;


<s> bool isAMXInstruction ( MachineInstr & MI ) {

if ( MI . isPHI ( ) || MI . isDebugInstr ( ) || MI . getNumOperands ( ) < <NUM_LIT> ) return false ;


<s> const MCOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { printRegName ( O , MO . getReg ( ) ) ; } else if ( MO . isExpr ( ) ) {

MO . getExpr ( ) -> print ( O , & MAI ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : { Register SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; ShapeT Shape = getTileShape ( SrcReg , VRM , MRI ) ; VRM -> assignVirt2Shape ( VirtReg , Shape ) ; return Shape ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

MachineOperand & MO1 = MI -> getOperand ( <NUM_LIT> ) ;


<s> if ( ! LI . findIndexesLiveAt ( Indexes , std :: back_inserter ( LiveIdxs ) ) ) continue ; if ( ! LI . hasSubRanges ( ) ) { for ( auto <ISA_LIT> : LiveIdxs ) LiveRegMap [ <ISA_LIT>I . getInstructionFromIndex ( <ISA_LIT> ) ] [ Reg ] = MRI . getMaxLaneMaskForVReg ( Reg ) ; } else for ( const auto & S : LI . subranges ( ) ) { SRLiveIdxs . clear ( ) ; S . findIndexesLiveAt ( LiveIdxs , std :: back_inserter ( SRLiveIdxs ) ) ; for ( auto <ISA_LIT> : SRLiveIdxs ) LiveRegMap [ <ISA_LIT>I . getInstructionFromIndex ( <ISA_LIT> ) ] [ Reg ] |= S . LaneMask ; } } return LiveRegMap ;


<s> void <ISA_LIT>FunctionInfo :: addToScratchAllocationSet ( unsigned Reg ) { if ( scratchAllocations . find ( Reg ) == scratchAllocations . end ( ) ) {

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << Reg << <STR_LIT> ) ;


<s> if ( <STR_LIT> ( MI . getOpcode ( ) , Op ) ) { if ( IsPCRel ) { assert ( Alt && <STR_LIT> ) ; MCO = MI . getOperand ( MIOpIdx + <STR_LIT> ) ; } else { MCO = MI . getOperand ( MIOpIdx + ( Alt ? <STR_LIT> : <STR_LIT> ) ) ; } } else { assert ( ! Alt && <STR_LIT> ) ; MCO = MI . getOperand ( MIOpIdx ) ; } unsigned RegNum = MCO . getReg ( ) ; auto RI = Ctx . getRegisterInfo ( ) ; unsigned Written = <NUM_LIT> ; if ( Reg ) { uint32_t Val = RI -> getEncodingValue ( RegNum ) ; Buffer |= ( Val & <NUM_LIT> ) << Offset ;


<s> static void load_reg ( int reg , HOST_WIDE_INT disp , int base ) { rtx dest = gen_rtx_REG ( word_mode , reg ) ; rtx basereg = gen_rtx_REG ( Pmode , base ) ; rtx src ; if ( VAL_14_BITS_P ( disp ) ) src = gen_rtx_MEM ( word_mode , plus_constant ( Pmode , basereg , disp ) ) ; else if ( TARGET_64BIT && ! VAL_32_BITS_P ( disp ) ) { rtx delta = GEN_INT ( disp ) ; rtx tmpreg = gen_rtx_REG ( Pmode , <NUM_LIT> ) ;


<s> static inline unsigned int popcount ( unsigned int mask ) { unsigned int count = <NUM_LIT> ; while ( mask ) { ++ count ; mask &= ~ ( mask & - mask ) ; }


<s> rtx op1 = XEXP ( op , <NUM_LIT> ) ; if ( ! REG_P ( op0 ) ) return <NUM_LIT> ; if ( GET_CODE ( op1 ) != CONST_INT ) return <NUM_LIT> ; if ( mode == HImode || mode == HFmode ) return IS_UINT5_CONST ( INTVAL ( op1 ) + <NUM_LIT> ) ; return IS_UINT5_CONST ( INTVAL ( op1 ) ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; } SDValue SOShImm = CurDAG -> getTargetConstant ( <STR_LIT> ( SOVal ) , <STR_LIT> ) ; SDValue CC = CurDAG -> getTargetConstant ( CCVal , <STR_LIT> ) ; SDValue Ops [ ] = { FalseVal , CPTmp0 , SOShImm , CC , CCR , InFlag } ; return CurDAG -> SelectNodeTo ( N , Opc , <STR_LIT> , Ops , <NUM_LIT> ) ; } return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> unsigned OpIdx = <NUM_LIT> ; if ( TID . getNumDefs ( ) == <NUM_LIT> ) Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) << <STR_LIT> ; Binary |= getMachineOpValue ( MI , OpIdx ++ ) ;


<s> gimple * def_stmt = SSA_NAME_DEF_STMT ( TREE_OPERAND ( expr , <NUM_LIT> ) ) ; if ( def_stmt && is_gimple_assign ( def_stmt ) ) expr = gimple_assign_rhs1 ( def_stmt ) ; } if ( is_attr_preserve_access ( expr ) ) { auto_vec < unsigned int , <NUM_LIT> > accessors ; tree container = bpf_core_compute ( expr , & accessors ) ; if ( accessors . length ( ) < <NUM_LIT> ) continue ; accessors . reverse ( ) ; container = TREE_TYPE ( container ) ; const char * section_name ; if ( DECL_SECTION_NAME ( fn -> decl ) ) section_name = DECL_SECTION_NAME ( fn -> decl ) ; else section_name = <STR_LIT> ; label = gen_label_rtx ( ) ; LABEL_PRESERVE_P ( label ) = <NUM_LIT> ;


<s> FunctionPass * llvm :: create<ISA_LIT>DelaySlotFillerPass ( const <ISA_LIT>TargetMachine & ) { return new Filler ( ) ;


<s> if ( GPR_P ( regno ) || regno == AP_FIRST ) base = GPR_FIRST ; else if ( FPR_P ( regno ) ) base = FPR_FIRST ; else if ( ACC_P ( regno ) ) base = ACC_FIRST ; else if ( SPR_P ( regno ) ) return mode == SImode ; else return <NUM_LIT> ; if ( GET_MODE_SIZE ( mode ) < <NUM_LIT> ) return <NUM_LIT> ; mask = ( GET_MODE_SIZE ( mode ) / <NUM_LIT> ) - <NUM_LIT> ; } return ( ( ( regno - base ) & mask ) == <NUM_LIT> ) ; } return <NUM_LIT> ;


<s> SDLoc dl ( N ) ; SmallVector < SDValue , <NUM_LIT> > Regs ( N -> op_begin ( ) + <NUM_LIT> , N -> op_begin ( ) + <NUM_LIT> + NumVecs ) ; SDValue RegSeq = createZTuple ( Regs ) ; unsigned Opc ; SDValue Offset , Base ; std :: tie ( Opc , Base , Offset ) = findAddrModeSVELoadStore < Scale > ( N , Opc_rr , Opc_ri , N -> getOperand ( NumVecs + <NUM_LIT> ) , CurDAG -> getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue Ops [ ] = { RegSeq , N -> getOperand ( NumVecs + <NUM_LIT> ) , Base , Offset , N -> getOperand ( <NUM_LIT> ) } ; SDNode * St = CurDAG -> getMachineNode ( Opc , dl , N -> getValueType ( <NUM_LIT> ) , Ops ) ; ReplaceNode ( N , St ) ;


<s> <ISA_LIT>ControlFlowFinalizer ( TargetMachine & tm ) : MachineFunctionPass ( ID ) {


<s> for ( auto I = V . begin ( ) , E = V . end ( ) ; I != E ; ++ I ) { if ( reg == I -> getReg ( ) ) return I ; }


<s> assignValueToReg ( NewRegs [ <NUM_LIT> ] , NextVA . getLocReg ( ) , NextVA ) ; bool IsLittle = MIRBuilder . getMF ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) . isLittle ( ) ; if ( ! IsLittle ) std :: swap ( NewRegs [ <NUM_LIT> ] , NewRegs [ <NUM_LIT> ] ) ; MIRBuilder . buildSequence ( Arg . Reg , NewRegs , { <NUM_LIT> , <NUM_LIT> } ) ;


<s> I != E ; ++ I ) { ReleasePred ( SU , & * I ) ; if ( I -> isAssignedRegDep ( ) ) {

if ( ! LiveRegDefs [ I -> getReg ( ) ] ) {


<s> BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; fixStackStores ( MBB , MI , TII , <STR_LIT> ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned addOpcode ; if ( isUInt < <NUM_LIT> > ( Amount ) ) { addOpcode = <STR_LIT> ; } else { addOpcode = <STR_LIT> ; Amount = - Amount ; }


<s> bool <ISA_LIT>LegalizerInfo :: legalizeShuffleVector ( MachineInstr & MI , MachineRegisterInfo & MRI , MachineIRBuilder & B ) const { const LLT V2S16 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; Register Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT DstTy = MRI . getType ( Dst ) ; LLT SrcTy = MRI . getType ( Src0 ) ;

if ( SrcTy == V2S16 && DstTy == V2S16 && <STR_LIT> ( MI . getOperand ( <NUM_LIT> ) . getShuffleMask ( ) ) ) return true ;


<s> inline hashval_t wrapped_symbol_hasher :: hash ( const value_type * v ) { return htab_hash_string ( v ) ;


<s> bool hasDivideIn<ISA_LIT>Mode ( ) const {


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> bool isAliased ( const MachineFrameInfo * ) const override { return false ;


<s> RegDomain Domain = NoDomain ; visitRegister ( C , Reg , Domain , Worklist ) ; while ( ! Worklist . empty ( ) ) { unsigned CurReg = Worklist . pop_back_val ( ) ; if ( ! C . insertEdge ( CurReg ) ) continue ; EnclosedEdges . set ( Register :: virtReg2Index ( Reg ) ) ; MachineInstr * DefMI = MRI -> getVRegDef ( CurReg ) ; encloseInstr ( C , DefMI ) ; int OpEnd = DefMI -> getNumOperands ( ) ; const MCInstrDesc & Desc = DefMI -> getDesc ( ) ; int MemOp = <STR_LIT> ( Desc . TSFlags ) ; if ( MemOp != - <NUM_LIT> ) MemOp += <STR_LIT> ( Desc ) ; for ( int OpIdx = <NUM_LIT> ; OpIdx < OpEnd ; ++ OpIdx ) { if ( OpIdx == MemOp ) { OpIdx += ( <STR_LIT> - <NUM_LIT> ) ; continue ; }

auto & Op = DefMI -> getOperand ( OpIdx ) ;


<s> int zero_and_one ( rtx operand1 , rtx operand2 ) {

return GET_CODE ( operand1 ) == CONST_INT && GET_CODE ( operand2 ) == CONST_INT && ( ( ( INTVAL ( operand1 ) == <NUM_LIT> ) && ( INTVAL ( operand2 ) == <NUM_LIT> ) ) || ( ( INTVAL ( operand1 ) == <NUM_LIT> ) && ( INTVAL ( operand2 ) == <NUM_LIT> ) ) ) ;


<s> SDValue Disp = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; SDValue Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ; const SDValue Ops [ ] = { VSrc , Base , getI8Imm ( Scale -> getSExtValue ( ) ) , VIdx , Disp , Segment , VMask , Chain } ; SDNode * ResNode = CurDAG -> getMachineNode ( Opc , Node -> getDebugLoc ( ) , VSrc . getValueType ( ) , <STR_LIT> , Ops , array_lengthof ( Ops ) ) ;


<s> <ISA_LIT>TargetLowering :: ConstraintType <ISA_LIT>TargetLowering :: getConstraintType ( const std :: string & Constraint ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { default : break ; case 'd' : case 'y' : case 'f' : return C_RegisterClass ; } }

return TargetLowering :: getConstraintType ( Constraint ) ;


<s> static bool pa_function_ok_for_sibcall ( tree decl , tree exp ATTRIBUTE_UNUSED ) { if ( TARGET_64BIT ) return false ; if ( TARGET_PORTABLE_RUNTIME ) return false ;

return decl && targetm . binds_local_p ( decl ) ;


return isRegIdx ( ) && RegIdx . Kind & RegKind_FGR && RegIdx . Index <= <NUM_LIT> ;


if ( ! ( ( __eax ^ __ebx ) & <NUM_LIT> ) ) return <NUM_LIT> ;


<s> assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) . isFloatingPoint ( ) ) ; SDValue Src = Op . getOperand ( <NUM_LIT> ) ; if ( Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src ) ; SDValue Tmp ; switch ( Op . getSimpleValueType ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : ( <ISA_LIT>SubTarget . hasFPCVT ( ) ? <STR_LIT> : <STR_LIT> ) , dl , <STR_LIT> , Src ) ; break ; case <STR_LIT> : assert ( ( Op . getOpcode ( ) == <STR_LIT> || <ISA_LIT>SubTarget . hasFPCVT ( ) ) && <STR_LIT> ) ; Tmp = DAG . getNode ( Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> , dl , <STR_LIT> , Src ) ; break ; }

bool i32Stack = Op . getValueType ( ) == <STR_LIT> && <ISA_LIT>SubTarget . hasSTFIWX ( ) && ( Op . getOpcode ( ) == <STR_LIT> || <ISA_LIT>SubTarget . hasFPCVT ( ) ) ;


<s> unsigned <ISA_LIT>CodeGenPrepare :: numBitsUnsigned ( Value * Op , unsigned ScalarSize ) const { KnownBits Known = computeKnownBits ( Op , * DL , <NUM_LIT> , AC ) ; return ScalarSize - Known . countMinLeadingZeros ( ) ;


<s> void <ISA_LIT>MCCodeEmitter :: EmitByte ( unsigned char C , raw_ostream & OS ) const { OS << ( char ) C ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; const BasicBlock * BB = MBB . getBasicBlock ( ) ; MachineInstr & MI = * MBBI ; DebugLoc DL = MI . getDebugLoc ( ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned CCValid = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned CCMask = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; LivePhysRegs LiveRegs ( & TII -> getRegisterInfo ( ) ) ; LiveRegs . addLiveOuts ( MBB ) ; for ( auto I = std :: prev ( MBB . end ( ) ) ; I != MBBI ; -- I ) LiveRegs . stepBackward ( * I ) ; MachineBasicBlock * RestMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , RestMBB ) ; RestMBB -> splice ( RestMBB -> begin ( ) , & MBB , MI , MBB . end ( ) ) ; RestMBB -> transferSuccessors ( & MBB ) ; for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) RestMBB -> addLiveIn ( * I ) ; MachineBasicBlock * MoveMBB = MF . CreateMachineBasicBlock ( BB ) ; MF . insert ( std :: next ( MachineFunction :: iterator ( MBB ) ) , MoveMBB ) ; MoveMBB -> addLiveIn ( SrcReg ) ; for ( auto I = LiveRegs . begin ( ) ; I != LiveRegs . end ( ) ; ++ I ) MoveMBB -> addLiveIn ( * I ) ;

BuildMI ( & MBB , DL , TII -> get ( <STR_LIT> ) ) . addImm ( CCValid ) . addImm ( CCMask ^ CCValid ) . addMBB ( RestMBB ) ;


<s> uint64_t MaskSize = countPopulation ( Mask ) ; if ( Shift == <NUM_LIT> && MaskSize == <NUM_LIT> ) return false ; if ( Shift + MaskSize > NVT . getSizeInBits ( ) ) return false ; SDValue C = CurDAG -> getConstant ( Shift | ( MaskSize << <NUM_LIT> ) , dl , NVT ) ; SDValue New = CurDAG -> getNode ( <STR_LIT> , dl , NVT , N0 -> getOperand ( <NUM_LIT> ) , C ) ; ReplaceNode ( Node , New . getNode ( ) ) ;


<s> static void rx_elf_asm_destructor ( rtx symbol , int priority ) {

rx_elf_asm_cdtor ( symbol , priority , false ) ;


<s> return ( unsigned char ) __builtin_ia32_ktestzqi ( __A , __B ) ;


<s> if ( <STR_LIT> . hasSubClassEq ( RC ) || MO . getSubReg ( ) == <STR_LIT> || MO . getSubReg ( ) == <STR_LIT> ) return & <STR_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) || MO . getSubReg ( ) == <STR_LIT> || MO . getSubReg ( ) == <STR_LIT> ) return & <STR_LIT> ; if ( VRM && VRM -> hasPhys ( MO . getReg ( ) ) ) { unsigned PhysReg = VRM -> getPhys ( MO . getReg ( ) ) ; if ( <STR_LIT> . contains ( PhysReg ) ) return & <STR_LIT> ; assert ( <STR_LIT> . contains ( PhysReg ) && <STR_LIT> ) ; return & <STR_LIT> ;


<s> if ( cfun -> machine -> base_reg ) regs_ever_live [ REGNO ( cfun -> machine -> base_reg ) ] = <NUM_LIT> ;


<s> } unsigned int numVRs = MRI -> getNumVirtRegs ( ) ; for ( unsigned i = <NUM_LIT> ; i < numVRs ; i ++ ) { unsigned int vr = TRI -> index2VirtReg ( i ) ; const TargetRegisterClass * RC = MRI -> getRegClass ( vr ) ; std :: map < unsigned , unsigned > & regmap = VRidGlobal2LocalMap [ RC -> getID ( ) ] ; int n = regmap . size ( ) ; regmap . insert ( std :: make_pair ( vr , n + <NUM_LIT> ) ) ; } O << <STR_LIT> << <ISA_LIT>NumRegisters << <STR_LIT> ; O << <STR_LIT> << <ISA_LIT>NumRegisters << <STR_LIT> ; O << <STR_LIT> << <ISA_LIT>NumRegisters << <STR_LIT> ; O << <STR_LIT> << <ISA_LIT>NumRegisters << <STR_LIT> ;


<s> switch ( Opcode ) { case AMDGPU :: PRED_X : case AMDGPU :: COPY : case AMDGPU :: CONST_COPY : case AMDGPU :: INTERP_PAIR_XY : case AMDGPU :: INTERP_PAIR_ZW : case AMDGPU :: INTERP_VEC_LOAD : case AMDGPU :: DOT_4 : return IDAlu ; default : return IDOther ;


<s> BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , ResultReg ) . addReg ( Reg ) ;


<s> if ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) [ <NUM_LIT> ] ) return OutContext . GetOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ;

return OutContext . GetOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ;


<s> <STR_LIT> ; } else if ( IsFormat ) { Opc = IsD16 ? <STR_LIT> : <STR_LIT> ; } else { switch ( MemSize ) { case <NUM_LIT> : Opc = <STR_LIT> ; break ; case <NUM_LIT> : Opc = <STR_LIT> ; break ; default : Opc = <STR_LIT> ; break ; } } Register LoadDstReg ; bool IsExtLoad = ( ! IsD16 && MemSize < <NUM_LIT> ) || ( IsD16 && ! Ty . isVector ( ) ) ; LLT UnpackedTy = Ty . changeElementSize ( <NUM_LIT> ) ; if ( IsExtLoad ) LoadDstReg = B . getMRI ( ) -> createGenericVirtualRegister ( S32 ) ; else if ( Unpacked && IsD16 && Ty . isVector ( ) ) LoadDstReg = B . getMRI ( ) -> createGenericVirtualRegister ( UnpackedTy ) ; else LoadDstReg = Dst ; if ( ! VIndex ) VIndex = B . buildConstant ( S32 , <NUM_LIT> ) . getReg ( <NUM_LIT> ) ; auto MIB = B . buildInstr ( Opc ) . addDef ( LoadDstReg ) . addUse ( RSrc ) . addUse ( VIndex ) . addUse ( VOffset ) . addUse ( SOffset ) . addImm ( ImmOffset ) ; if ( IsTyped ) MIB . addImm ( Format ) ; MIB . addImm ( AuxiliaryData ) . addImm ( HasVIndex ? - <NUM_LIT> : <NUM_LIT> ) . addMemOperand ( MMO ) ; if ( LoadDstReg != Dst ) { B . setInsertPt ( B . getMBB ( ) , ++ B . getInsertPt ( ) ) ; if ( IsExtLoad ) B . buildTrunc ( Dst , LoadDstReg ) ; else { auto Unmerge = B . buildUnmerge ( S32 , LoadDstReg ) ; SmallVector < Register , <NUM_LIT> > Repack ; for ( unsigned I = <NUM_LIT> , N = Unmerge -> getNumOperands ( ) - <NUM_LIT> ; I != N ; ++ I ) Repack . push_back ( B . buildTrunc ( EltTy , Unmerge . getReg ( I ) ) . getReg ( <NUM_LIT> ) ) ;