<s> Inst . setLoc ( Loc ) ; Out . emitInstruction ( Inst , STI ) ;


<s> Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ;

return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> TargetLoweringObjectFileMachO & TLOFMacho = static_cast < TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextSection ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getTextCoalSection ( ) ) ; OutStreamer . SwitchSection ( TLOFMacho . getConstTextCoalSection ( ) ) ; if ( RelocM == Reloc :: DynamicNoPIC ) { const MCSection * sect = TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } else { const MCSection * sect = TLOFMacho . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS , <NUM_LIT> , SectionKind :: getText ( ) ) ; OutStreamer . SwitchSection ( sect ) ; } } } O << <STR_LIT> ; if ( Subtarget -> isTargetELF ( ) ) { std :: string CPUString = Subtarget -> getCPUString ( ) ; if ( CPUString != <STR_LIT> ) O << <STR_LIT> << CPUString << '\n' ; if ( Subtarget -> hasVFP2 ( ) ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; if ( ! UnsafeFPMath ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> ; if ( FiniteOnlyFPMath ( ) ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; else O << <STR_LIT> << <STR_LIT> << <STR_LIT> ; O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> ; if ( Subtarget -> isAAPCS_ABI ( ) && FloatABIType == FloatABI :: Hard ) O << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> << <STR_LIT> ;


<s> Ops . push_back ( CurDAG -> getTargetConstant ( <STR_LIT> , Loc , <STR_LIT> ) ) ;


<s> Register Undef = MRI . createVirtualRegister ( IsAGPR ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , get ( <STR_LIT> ) , Undef ) ; Register NewVR = MRI . createVirtualRegister ( IsAGPR ? & <STR_LIT> : & <STR_LIT> ) ; BuildMI ( * BB , MI , DL , get ( <STR_LIT> ) , NewVR ) . addReg ( DataReg , <NUM_LIT> , Op . getSubReg ( ) ) . addImm ( <STR_LIT> ) . addReg ( Undef ) . addImm ( <STR_LIT> ) ;


for ( regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( ( ( ( regs_ever_live [ regno ] && ! call_used_regs [ regno ] ) || ( regno == ( int ) PIC_OFFSET_TABLE_REGNUM && ( current_function_uses_pic_offset_table || ( flag_pic && regs_ever_live [ regno + <NUM_LIT> ] && ! call_used_regs [ regno + <NUM_LIT> ] ) ) ) ) && ( regno != FRAME_POINTER_REGNUM || ! frame_pointer_needed ) && regno != CRIS_SRP_REGNUM ) || ( current_function_calls_eh_return && ( regno == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) || regno == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) || regno == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) || regno == EH_RETURN_DATA_REGNO ( <NUM_LIT> ) ) ) ) offs += <NUM_LIT> ;


<s> return TLSOffset ; assert ( <NUM_LIT> && <STR_LIT> ) ; return <NUM_LIT> ;


<s> Op -> StartLoc = S ; Op -> EndLoc = S ; return Op ;


<s> MVT ElemTy = VecTy . getVectorElementType ( ) ; unsigned VecLen = VecTy . getVectorNumElements ( ) ; unsigned HwLen = Subtarget . getVectorLength ( ) ; if ( ElemTy == <STR_LIT> && VecLen == <NUM_LIT> * HwLen ) return TargetLoweringBase :: TypeSplitVector ; if ( ElemTy == <STR_LIT> ) ElemTy = <STR_LIT> ; ArrayRef < MVT > Tys = Subtarget . getHVXElementTypes ( ) ; if ( llvm :: is_contained ( Tys , ElemTy ) ) { unsigned VecWidth = VecTy . getSizeInBits ( ) ;

bool HaveThreshold = HvxWidenThreshold . getNumOccurrences ( ) > <NUM_LIT> ;


<s> MachineBasicBlock :: iterator ItrMI = MI ; for ( auto I = std :: next ( ItrMI ) , E = BB -> end ( ) ; I != E ; ++ I ) { if ( I -> readsRegister ( <STR_LIT> ) ) return true ;

if ( I -> definesRegister ( <STR_LIT> ) ) return false ;


<s> int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( <NUM_LIT> , <NUM_LIT> , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , PtrVT ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Chain , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Four = DAG . getConstant ( <NUM_LIT> , PtrVT ) ; SDValue Addr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StackSlot , Four ) ; SDValue CWD = DAG . getLoad ( <STR_LIT> , dl , Store , Addr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ; SDValue CWD1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue CWD2 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue RetVal = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CWD1 , CWD2 ) ; return DAG . getNode ( ( VT . getSizeInBits ( ) < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) , dl , VT , RetVal ) ;


<s> width = GEN_INT ( GET_MODE_BITSIZE ( mode ) ) ; mask = GEN_INT ( mode == QImode ? <NUM_LIT> : <NUM_LIT> ) ; emit_insn ( gen_extxl ( dest , scratch , width , addr ) ) ; if ( oldval == const0_rtx ) { emit_move_insn ( cond , const0_rtx ) ; x = gen_rtx_NE ( DImode , dest , const0_rtx ) ; } else { x = gen_rtx_EQ ( DImode , dest , oldval ) ; emit_insn ( gen_rtx_SET ( cond , x ) ) ; x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; } emit_unlikely_jump ( x , label2 ) ; emit_insn ( gen_mskxl ( cond , scratch , mask , addr ) ) ; if ( newval != const0_rtx ) emit_insn ( gen_iordi3 ( cond , cond , newval ) ) ; emit_store_conditional ( DImode , cond , mem , cond ) ; if ( ! is_weak ) { x = gen_rtx_EQ ( DImode , cond , const0_rtx ) ; emit_unlikely_jump ( x , label1 ) ; } if ( ! is_mm_relaxed ( mod_f ) ) emit_label ( XEXP ( label2 , <NUM_LIT> ) ) ; alpha_post_atomic_barrier ( mod_s ) ; if ( is_mm_relaxed ( mod_f ) ) emit_label ( XEXP ( label2 , <NUM_LIT> ) ) ;


<s> assert ( alignedStackSize <= getEffectiveStackCacheSize ( ) ) ; unsigned stackFrameSize = alignedStackSize / <NUM_LIT> ; MachineInstr * Inst = NULL ; if ( stackFrameSize ) { assert ( isUInt < <NUM_LIT> > ( stackFrameSize ) && <STR_LIT> ) ; DebugLoc DL = ( MI != MBB . end ( ) ) ? MI -> getDebugLoc ( ) : DebugLoc ( ) ; const TargetInstrInfo & TII = * TM . getInstrInfo ( ) ; Inst = AddDefaultPred ( BuildMI ( MBB , MI , DL , TII . get ( Opcode ) ) ) . addImm ( stackFrameSize ) ; } return Inst ;


<s> if ( EltSz == <NUM_LIT> ) return false ; unsigned NumElts = VT . getVectorNumElements ( ) ; if ( M . size ( ) != NumElts && M . size ( ) != NumElts * <NUM_LIT> ) return false ; for ( unsigned i = <NUM_LIT> ; i < M . size ( ) ; i += NumElts ) { WhichResult = SelectPairHalf ( NumElts , M , i ) ; unsigned Idx = WhichResult * NumElts / <NUM_LIT> ; for ( unsigned j = <NUM_LIT> ; j < NumElts ; j += <NUM_LIT> ) { if ( ( M [ i + j ] >= <NUM_LIT> && ( unsigned ) M [ i + j ] != Idx ) || ( M [ i + j + <NUM_LIT> ] >= <NUM_LIT> && ( unsigned ) M [ i + j + <NUM_LIT> ] != Idx ) ) return false ; Idx += <NUM_LIT> ; }


<s> APInt AI = FP . bitcastToAPInt ( ) ; return std :: string ( AI . isNegative ( ) ? <STR_LIT> : <STR_LIT> ) + <STR_LIT> + utohexstr ( AI . getZExtValue ( ) & ( AI . getBitWidth ( ) == <NUM_LIT> ? INT64_C ( <NUM_LIT> ) : INT64_C ( <NUM_LIT> ) ) , true ) ; } static const size_t BufBytes = <NUM_LIT> ; char buf [ BufBytes ] ; auto Written = FP . convertToHexString ( buf , <NUM_LIT> , false , APFloat :: rmNearestTiesToEven ) ; ( void ) Written ; assert ( Written != <NUM_LIT> ) ;


<s> unsigned i = <NUM_LIT> ; for ( auto & Arg : F . args ( ) ) { if ( DL . getTypeStoreSize ( Arg . getType ( ) ) . isZero ( ) ) continue ; ArgInfo OrigArg { VRegs [ i ] , Arg } ; setArgFlags ( OrigArg , i + AttributeList :: FirstArgIndex , DL , F ) ; if ( Arg . hasAttribute ( Attribute :: SwiftAsync ) ) MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> setHasSwiftAsyncContext ( true ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ i ; } if ( ! MBB . empty ( ) ) MIRBuilder . setInstr ( * MBB . begin ( ) ) ; const <ISA_LIT>TargetLowering & TLI = * getTLI < <ISA_LIT>TargetLowering > ( ) ; CCAssignFn * AssignFn = TLI . CCAssignFnForCall ( F . getCallingConv ( ) , false ) ; <ISA_LIT>IncomingValueAssigner Assigner ( AssignFn , AssignFn ) ; FormalArgHandler Handler ( MIRBuilder , MRI ) ;

if ( ! determineAndHandleAssignments ( Handler , Assigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ) return false ;


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) {


<s> static void init_sched_state ( c6x_sched_context_t sc ) { sc -> last_scheduled_insn = NULL ; sc -> last_scheduled_iter0 = NULL ; sc -> issued_this_cycle = <NUM_LIT> ; memset ( sc -> jump_cycles , <NUM_LIT> , sizeof sc -> jump_cycles ) ; memset ( sc -> jump_cond , <NUM_LIT> , sizeof sc -> jump_cond ) ; sc -> jump_cycle_index = <NUM_LIT> ; sc -> delays_finished_at = <NUM_LIT> ; sc -> curr_sched_clock = <NUM_LIT> ; sc -> prev_cycle_state_ctx = xmalloc ( dfa_state_size ) ; memset ( sc -> reg_n_accesses , <NUM_LIT> , sizeof sc -> reg_n_accesses ) ; memset ( sc -> reg_n_xaccesses , <NUM_LIT> , sizeof sc -> reg_n_xaccesses ) ; memset ( sc -> reg_set_in_cycle , <NUM_LIT> , sizeof sc -> reg_set_in_cycle ) ; state_reset ( sc -> prev_cycle_state_ctx ) ;


<s> return __builtin_aarch64_smaxv16qi ( __a , __b ) ;


<s> if ( ! MI ) return nullptr ; if ( ! isPredicable ( * MI ) ) return nullptr ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isFI ( ) || MO . isCPI ( ) || MO . isJTI ( ) ) return nullptr ; if ( ! MO . isReg ( ) ) continue ; if ( MO . isTied ( ) ) return nullptr ; if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) return nullptr ; if ( MO . isDef ( ) && ! MO . isDead ( ) ) return nullptr ; } bool DontMoveAcrossStores = true ; if ( ! MI -> isSafeToMove ( nullptr , DontMoveAcrossStores ) ) return nullptr ;


<s> if ( ! isUInt < <NUM_LIT> > ( CUVal64 ) ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'J' : if ( CVal64 < - <NUM_LIT> || CVal64 > <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; case 'K' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'L' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'M' : if ( ! isUInt < <NUM_LIT> > ( CUVal64 ) ) return ; if ( Ty . getSimpleVT ( ) == <STR_LIT> ) { Ty = <STR_LIT> ; } Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'N' : if ( CVal64 != - <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; case 'O' : if ( CUVal64 != <NUM_LIT> && CUVal64 != <NUM_LIT> && CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'P' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'R' : if ( CVal64 < - <NUM_LIT> || CVal64 > <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; } break ;


<s> else Section = OutStreamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_PROGBITS , ELF :: SHF_WRITE | ELF :: SHF_ALLOC , SectionKind :: getReadOnly ( ) ) ; OutStreamer . SwitchSection ( Section ) ; for ( MapVector < MCSymbol * , MCSymbol * > :: iterator I = TOC . begin ( ) , E = TOC . end ( ) ; I != E ; ++ I ) { OutStreamer . EmitLabel ( I -> second ) ; MCSymbol * S = OutContext . GetOrCreateSymbol ( I -> first -> getName ( ) ) ; if ( is<ISA_LIT>64 ) TS . emitTCEntry ( * S ) ; else OutStreamer . EmitSymbolValue ( S , <NUM_LIT> ) ; } } MachineModuleInfoELF & MMIELF = MMI -> getObjFileInfo < MachineModuleInfoELF > ( ) ; MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) {

OutStreamer . SwitchSection ( getObjFileLowering ( ) . getDataSection ( ) ) ;


<s> Lexer . Lex ( ) ; if ( Lexer . isNot ( AsmToken :: Integer ) ) { Err << <STR_LIT> ; return false ; } return true ;


<s> const unsigned char * pc = context -> ra ; if ( * ( unsigned int * ) ( pc + <NUM_LIT> ) != <NUM_LIT> ) return NULL ; if ( * ( unsigned int * ) ( pc + <NUM_LIT> ) == <NUM_LIT> || * ( unsigned int * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) { struct sigframe { char gap [ SIGNAL_FRAMESIZE ] ; unsigned long pad [ <NUM_LIT> ] ; struct gcc_regs * regs ; } * frame = ( struct sigframe * ) context -> cfa ; return frame -> regs ; } else if ( * ( unsigned int * ) ( pc + <NUM_LIT> ) == <NUM_LIT> || * ( unsigned int * ) ( pc + <NUM_LIT> ) == <NUM_LIT> ) { struct rt_sigframe { char gap [ SIGNAL_FRAMESIZE + <NUM_LIT> ] ; char siginfo [ <NUM_LIT> ] ; struct gcc_ucontext uc ; } * frame = ( struct rt_sigframe * ) context -> cfa ;


<s> bool <ISA_LIT>InstrInfo :: usesVertexCache ( const MachineInstr * MI ) const {

const MachineFunction * MF = MI -> getParent ( ) -> getParent ( ) ;


<s> auto MIBLO = buildMI ( MBB , MBBI , Op ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcLoReg , getKillRegState ( SrcIsKill ) ) ; MIBLO -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MIBHI = buildMI ( MBB , MBBI , Op ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcHiReg , getKillRegState ( SrcIsKill ) ) ; if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MI . eraseFromParent ( ) ;


<s> frame = & cfun -> machine -> frame ; if ( frame_pointer_needed && ! ( TARGET_CPRESTORE_DIRECTIVE && ! load_p ) ) { * base = hard_frame_pointer_rtx ; * offset = frame -> args_size - frame -> hard_frame_pointer_offset ; } else { * base = stack_pointer_rtx ; * offset = frame -> args_size ; }


<s> if ( CPU . empty ( ) ) CPU = <STR_LIT> ;


<s> const TargetRegisterClass * SrcRC = getRegClass ( SrcTy , SrcRB ) ; if ( ! SrcRC ) return false ; unsigned SubIdx ; if ( DstRC == SrcRC ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else if ( DstRC == & <STR_LIT> ) { SubIdx = <STR_LIT> ; } else { return false ; } SrcRC = TRI . getSubClassWithSubReg ( SrcRC , SubIdx ) ; if ( ! RBI . constrainGenericRegister ( SrcReg , * SrcRC , MRI ) || ! RBI . constrainGenericRegister ( DstReg , * DstRC , MRI ) ) { DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ;


<s> return getGlobalBaseReg ( ) ; case <STR_LIT> : { SDValue imm = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; int FI = dyn_cast < FrameIndexSDNode > ( Node ) -> getIndex ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , VT ) ; unsigned Opc = <STR_LIT> ; if ( Node -> hasOneUse ( ) ) return CurDAG -> SelectNodeTo ( Node , Opc , VT , TFI , imm ) ; return CurDAG -> getMachineNode ( Opc , dl , VT , TFI , imm ) ; } case <STR_LIT> : { if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { SDValue Chain = Node -> getOperand ( <NUM_LIT> ) ; SDValue Callee = Node -> getOperand ( <NUM_LIT> ) ; SDValue R20Reg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ; SDValue InFlag ( <NUM_LIT> , <NUM_LIT> ) ; if ( ( isa < GlobalAddressSDNode > ( Callee ) ) || ( isa < ExternalSymbolSDNode > ( Callee ) ) ) { SDValue GPReg = CurDAG -> getRegister ( <STR_LIT> , <STR_LIT> ) ;

SDValue Ops [ ] = { Callee , GPReg , Chain } ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> int64_t Imm = ShiftExtend . Amount / <NUM_LIT> ;

Inst . addOperand ( MCOperand :: CreateImm ( Imm ) ) ;


<s> return ; } const GlobalValue * GV = cast < GlobalValue > ( ( * MI -> memoperands_begin ( ) ) -> getValue ( ) ) ; if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isGVInGOT ( GV ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ;

else if ( MF . getTarget ( ) . isPositionIndependent ( ) ) expandLoadStackGuardBase ( MI , <STR_LIT> , <STR_LIT> ) ;


<s> SpillKind Kind = HasTC ? SK_FromMemTailcall : SK_FromMem ; const char * RestoreFn = getSpillFunctionFor ( MaxR , Kind ) ; auto & HTM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; bool IsPIC = HTM . getRelocationModel ( ) == Reloc :: PIC_ ; DebugLoc DL = MI != MBB . end ( ) ? MI -> getDebugLoc ( ) : MBB . getLastNonDebugInstr ( ) -> getDebugLoc ( ) ; MachineInstr * DeallocCall = nullptr ; if ( HasTC ) { unsigned ROpc = IsPIC ? <STR_LIT> : <STR_LIT> ; DeallocCall = BuildMI ( MBB , MI , DL , HII . get ( ROpc ) ) . addExternalSymbol ( RestoreFn ) ; } else { MachineBasicBlock :: iterator It = MBB . getFirstTerminator ( ) ; assert ( It -> isReturn ( ) && std :: next ( It ) == MBB . end ( ) ) ; unsigned ROpc = IsPIC ? <STR_LIT> : <STR_LIT> ; DeallocCall = BuildMI ( MBB , It , DL , HII . get ( ROpc ) ) . addExternalSymbol ( RestoreFn ) ;

DeallocCall -> copyImplicitOps ( MF , * It ) ;


<s> if ( S != MCDisassembler :: Success ) return Decode2OpInstructionFail ( Inst , Insn , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op2 , Address , Decoder ) ; return S ;


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { bool reserveCallFrame = hasReservedCallFrame ( MF ) ; unsigned Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = TII . getFrameSize ( * I ) ; uint64_t InternalAmt = ( isDestroy || Amount ) ? TII . getFrameAdjustment ( * I ) : <NUM_LIT> ; I = MBB . erase ( I ) ; auto InsertPos = skipDebugInstructionsForward ( I , MBB . end ( ) ) ; if ( ! reserveCallFrame ) { unsigned StackAlign = getStackAlignment ( ) ; Amount = alignTo ( Amount , StackAlign ) ; const Function & F = MF . getFunction ( ) ; bool WindowsCFI = MF . getTarget ( ) . getMCAsmInfo ( ) -> usesWindowsCFI ( ) ; bool DwarfCFI = ! WindowsCFI && MF . needsFrameMoves ( ) ; bool HasDwarfEHHandlers = ! WindowsCFI && ! MF . getLandingPads ( ) . empty ( ) ; if ( HasDwarfEHHandlers && ! isDestroy && MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getHasPushSequences ( ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createGnuArgsSize ( nullptr , Amount ) ) ; if ( Amount == <NUM_LIT> ) return I ; Amount -= InternalAmt ;

if ( isDestroy && InternalAmt && DwarfCFI && ! hasFP ( MF ) ) BuildCFI ( MBB , InsertPos , DL , MCCFIInstruction :: createAdjustCfaOffset ( nullptr , - InternalAmt ) ) ;


<s> int64_t Val = Memory . OffsetImm -> getValue ( ) ;

return ( Val == std :: numeric_limits < int32_t > :: min ( ) ) || ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) ;


<s> assert ( Op . getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; SDValue V3 = Op . getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && C ) return Op ; if ( Subtarget . isISA3_1 ( ) ) { if ( ( VT == <STR_LIT> || VT == <STR_LIT> ) && ! Subtarget . is<ISA_LIT>64 ( ) ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , V3 ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { if ( ! C || ( VT == <STR_LIT> && dyn_cast < LoadSDNode > ( V2 ) ) ) return DAG . getNode ( <STR_LIT> , dl , VT , V1 , V2 , V3 ) ; return Op ; } } if ( ! C ) return SDValue ( ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDValue Mtvsrz = DAG . getNode ( <STR_LIT> , dl , VT , V2 ) ; unsigned BytesInEachElement = VT . getVectorElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; unsigned InsertAtElement = C -> getZExtValue ( ) ; unsigned InsertAtByte = InsertAtElement * BytesInEachElement ; if ( Subtarget . isLittleEndian ( ) ) { InsertAtByte = ( <NUM_LIT> - BytesInEachElement ) - InsertAtByte ; } return DAG . getNode ( <STR_LIT> , dl , VT , V1 , Mtvsrz , DAG . getConstant ( InsertAtByte , dl , <STR_LIT> ) ) ; } return Op ;


<s> void <ISA_LIT>InstPrinter :: printVectorIndex ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) {

O << <STR_LIT> << MI -> getOperand ( OpNum ) . getImm ( ) << <STR_LIT> ;


<s> static tree nds32_merge_decl_attributes ( tree olddecl , tree newdecl ) { tree combined_attrs ;

combined_attrs = merge_attributes ( DECL_ATTRIBUTES ( olddecl ) , DECL_ATTRIBUTES ( newdecl ) ) ;


<s> e . rotate_inputs_left ( <NUM_LIT> , <NUM_LIT> ) ; insn_code icode = code_for_aarch64_lane ( unspec , e . vector_mode ( <NUM_LIT> ) ) ; return e . use_exact_insn ( icode ) ;


<s> BuildMI ( BB , DL , TII -> get ( Opc ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( sinkMBB ) ; BB = copy0MBB ; BB -> addSuccessor ( sinkMBB ) ; BB = sinkMBB ;

BuildMI ( * BB , BB -> begin ( ) , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ;


<s> OS << Print < NodeId > ( RA . Id , G ) << '<' << Print < RegisterRef > ( RA . Addr -> getRegRef ( G ) , G ) << '>' ; if ( RA . Addr -> getFlags ( ) & NodeAttrs :: Fixed ) OS << '!' ;


<s> unsigned <STR_LIT> ( Type * Ty , bool IsComplex ) const {

unsigned NumVectorInstToHideOverhead = <NUM_LIT> ;


<s> const Function * F = MF . getFunction ( ) ; if ( ( ! IsMemset || ZeroMemset ) && Subtarget -> hasNEON ( ) && ! F -> getAttributes ( ) . hasAttribute ( AttributeSet :: FunctionIndex , Attribute :: NoImplicitFloat ) ) { bool Fast ; if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsUnalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) { return <STR_LIT> ;

} else if ( Size >= <NUM_LIT> && ( memOpAlign ( SrcAlign , DstAlign , <NUM_LIT> ) || ( allowsUnalignedMemoryAccesses ( <STR_LIT> , <NUM_LIT> , & Fast ) && Fast ) ) ) {


<s> Inst . addOperand ( MCOperand :: CreateReg ( Reg . RegNum ) ) ;


<s> dbgs ( ) << <STR_LIT> << CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) << <STR_LIT> << MaxDisp << format ( <STR_LIT> , UserOffset ) << <STR_LIT> << Block << <STR_LIT> << format ( <STR_LIT> , BBI . Offset , BBI . postOffset ( ) ) << * MI << format ( <STR_LIT> , CPEOffset , int ( CPEOffset - UserOffset ) ) ;


<s> unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; if ( Reg ) { assert ( Reg == <STR_LIT> && <STR_LIT> ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; SDLoc DL ( Op ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( MF . getDataLayout ( ) ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;

return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FI , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) , false , false , <NUM_LIT> ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ObjectCodeEmitterPass ( <ISA_LIT>TargetMachine & TM , ObjectCodeEmitter & OCE ) {

return new Emitter < ObjectCodeEmitter > ( TM , OCE ) ;


<s> case <STR_LIT> : \ case <STR_LIT> : \ return <STR_LIT> ;


<s> case <STR_LIT> : MI . eraseFromParent ( ) ; break ; case <STR_LIT> : { unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RI . getSubReg ( Dst , <STR_LIT> ) ; const MachineOperand & SrcOp = MI . getOperand ( <NUM_LIT> ) ; assert ( ! SrcOp . isFPImm ( ) ) ; if ( SrcOp . isImm ( ) ) { APInt Imm ( <NUM_LIT> , SrcOp . getImm ( ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addImm ( Imm . getLoBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addImm ( Imm . getHiBits ( <NUM_LIT> ) . getZExtValue ( ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } else { assert ( SrcOp . isReg ( ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstLo ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DstHi ) . addReg ( RI . getSubReg ( SrcOp . getReg ( ) , <STR_LIT> ) ) . addReg ( Dst , RegState :: Implicit | RegState :: Define ) ; } MI . eraseFromParent ( ) ; break ; } case <STR_LIT> : { unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned DstLo = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned DstHi = RI . getSubReg ( Dst , <STR_LIT> ) ; unsigned Src0 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Src1 = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

const MachineOperand & SrcCond = MI . getOperand ( <NUM_LIT> ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : <ISA_LIT>BaseTargetMachine ( T , TT , FS , false ) , InstrInfo ( Subtarget ) , DataLayout ( Subtarget . isAPCS_ABI ( ) ? std :: string ( <STR_LIT> ) : std :: string ( <STR_LIT> ) ) , TLInfo ( * this ) {


<s> SDValue NewMask = DAG . getConstant ( Mask >> ShiftAmt , VT ) ; SDValue NewAnd = DAG . getNode ( <STR_LIT> , DL , VT , X , NewMask ) ; SDValue NewShift = DAG . getNode ( <STR_LIT> , DL , VT , NewAnd , Shift . getOperand ( <NUM_LIT> ) ) ; InsertDAGNode ( DAG , N , NewMask ) ; InsertDAGNode ( DAG , N , NewAnd ) ; InsertDAGNode ( DAG , N , NewShift ) ; DAG . ReplaceAllUsesWith ( N , NewShift ) ;


<s> return new <ISA_LIT>TransformIntrin ( ) ;


<s> void setLastNamedArgFrameIndex ( int v ) {


<s> TargetTransformInfo :: getAnalysisUsage ( AU ) ;


<s> case <STR_LIT> : switch ( DestTy . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : switch ( DestTy . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; case <STR_LIT> : return IsSigned ? <STR_LIT> : <STR_LIT> ; } case <STR_LIT> : switch ( DestTy . SimpleTy ) {


<s> SDValue Chain = N -> getOperand ( <NUM_LIT> ) ; SDValue Ops [ ] = { N -> getOperand ( <NUM_LIT> ) , Chain } ; const EVT ResTys [ ] = { <STR_LIT> , <STR_LIT> } ; SDNode * Ld = CurDAG -> getMachineNode ( Opc , dl , ResTys , Ops ) ; SDValue SuperReg = SDValue ( Ld , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumVecs ; ++ i ) ReplaceUses ( SDValue ( N , i ) , CurDAG -> getTargetExtractSubreg ( SubRegIdx + i , dl , VT , SuperReg ) ) ; ReplaceUses ( SDValue ( N , NumVecs ) , SDValue ( Ld , <NUM_LIT> ) ) ; if ( auto * MemIntr = dyn_cast < MemIntrinsicSDNode > ( N ) ) {

MachineMemOperand * MemOp = MemIntr -> getMemOperand ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( CantUseSP ( MFI ) ) return MRI -> canReserveReg ( BasePtr ) ;


if ( unrolled_advsimd_niters > ( unsigned int ) param_max_completely_peel_times ) return ;


<s> static AliasResult getAliasResult ( unsigned AS1 , unsigned AS2 ) { static_assert ( <ISA_LIT>AS :: MAX_<ISA_LIT>_ADDRESS <= <NUM_LIT> , <STR_LIT> ) ;


<s> case <STR_LIT> : return combineUIntToFP ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFaddFsub ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFneg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineTruncate ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAnd ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineFAndn ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFOr ( N , DAG , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinFMax ( N , DAG ) ; case <STR_LIT> : case <STR_LIT> : return combineFMinNumFMaxNum ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineBT ( N , DAG , DCI ) ; case <STR_LIT> : case <STR_LIT> : return combineZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineSignExtendInReg ( N , DAG , Subtarget ) ; case <STR_LIT> : return combineSetCC ( N , DAG , Subtarget ) ; case <STR_LIT> : return combine<ISA_LIT>SetCC ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : return combineBrCond ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVectorShift ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : return combineVSZext ( N , DAG , DCI , Subtarget ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> void <ISA_LIT>ATTInstPrinter :: printMemOffset ( const MCInst * MI , unsigned Op , raw_ostream & O ) { const MCOperand & DispSpec = MI -> getOperand ( Op ) ; const MCOperand & SegReg = MI -> getOperand ( Op + <NUM_LIT> ) ; O << markup ( <STR_LIT> ) ; if ( SegReg . getReg ( ) ) { printOperand ( MI , Op + <NUM_LIT> , O ) ; O << ':' ; } if ( DispSpec . isImm ( ) ) { O << formatImm ( DispSpec . getImm ( ) ) ;


<s> return * static_cast < const BlackfinTargetMachine & > ( TM ) . getInstrInfo ( ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) { RegisterTarget < Triple :: dlx > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> MachineModuleInfoELF :: SymbolListTy Stubs = MMIELF . GetGVStubList ( ) ; if ( ! Stubs . empty ( ) ) { OutStreamer . SwitchSection ( TLOFELF . getDataRelSection ( ) ) ; const DataLayout * TD = TM . getDataLayout ( ) ; for ( unsigned i = <NUM_LIT> , e = Stubs . size ( ) ; i != e ; ++ i ) { OutStreamer . EmitLabel ( Stubs [ i ] . first ) ; OutStreamer . EmitSymbolValue ( Stubs [ i ] . second . getPointer ( ) , TD -> getPointerSize ( <NUM_LIT> ) ) ; } Stubs . clear ( ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>FunctionInfo * AFI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = AFI -> createConstPoolEntryUId ( ) ; EVT PtrVT = getPointerTy ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; Reloc :: Model RelocM = getTargetMachine ( ) . getRelocationModel ( ) ; SDValue CPAddr ; unsigned PCAdj = ( RelocM != Reloc :: PIC_ ) ? <NUM_LIT> : ( Subtarget -> isThumb ( ) ? <NUM_LIT> : <NUM_LIT> ) ; <ISA_LIT>ConstantPoolValue * CPV = new <ISA_LIT>ConstantPoolValue ( MF . getFunction ( ) , <ISA_LIT>PCLabelIndex , <STR_LIT> , PCAdj ) ; CPAddr = DAG . getTargetConstantPool ( CPV , PtrVT , <NUM_LIT> ) ; CPAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , CPAddr ) ;

SDValue Result = DAG . getLoad ( PtrVT , dl , DAG . getEntryNode ( ) , CPAddr , PseudoSourceValue :: getConstantPool ( ) , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> if ( ! opnd . isReg ( ) ) return false ; MachineInstr * PhiDef = MRI -> getVRegDef ( opnd . getReg ( ) ) ; if ( ! PhiDef || PhiDef -> isPHI ( ) || PhiDef -> getOpcode ( ) == <STR_LIT> ) return false ; } } if ( DefInsn -> getOpcode ( ) == <STR_LIT> ) {

MachineOperand & opnd = DefInsn -> getOperand ( <NUM_LIT> ) ;


<s> bool hasMVE ( ) const { return getSTI ( ) . getFeatureBits ( ) [ <STR_LIT> ] ;


<s> Stub * <ISA_LIT>LA25Stub :: doClone ( ) {

return new <ISA_LIT>LA25Stub ( m_Target , m_pData , m_Size , fixup_begin ( ) , fixup_end ( ) ) ;


<s> int cmov_cnt = <NUM_LIT> ; for ( rtx_insn * insn = seq ; insn ; insn = NEXT_INSN ( insn ) ) { rtx set = single_set ( insn ) ; if ( ! set ) continue ; if ( GET_CODE ( SET_SRC ( set ) ) != IF_THEN_ELSE ) continue ; rtx src = SET_SRC ( set ) ; enum machine_mode mode = GET_MODE ( src ) ; if ( GET_MODE_CLASS ( mode ) != MODE_INT && GET_MODE_CLASS ( mode ) != MODE_FLOAT ) continue ; if ( ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) || ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) ) ) continue ;

if ( ++ cmov_cnt > <NUM_LIT> ) return false ;


<s> Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , <STR_LIT> , AM . Disp ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp ) ; else if ( AM . ES ) Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> ) ; else if ( AM . JT != - <NUM_LIT> ) Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> ) ;

else Disp = CurDAG -> getTargetConstant ( AM . Disp , <STR_LIT> ) ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { PM . add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ;


<s> rtx xops [ <NUM_LIT> ] ; ASM_GENERATE_INTERNAL_LABEL ( loop_lab , <STR_LIT> , labelno ++ ) ; ASM_OUTPUT_INTERNAL_LABEL ( asm_out_file , loop_lab ) ; xops [ <NUM_LIT> ] = reg1 ; xops [ <NUM_LIT> ] = GEN_INT ( - PROBE_INTERVAL ) ; output_asm_insn ( <STR_LIT> , xops ) ; fputs ( <STR_LIT> , asm_out_file ) ; output_asm_insn ( <STR_LIT> , xops ) ; xops [ <NUM_LIT> ] = reg2 ; xops [ <NUM_LIT> ] = gen_rtx_REG ( BImode , PR_REG ( <NUM_LIT> ) ) ; output_asm_insn ( <STR_LIT> , xops ) ;

fprintf ( asm_out_file , <STR_LIT> , reg_names [ PR_REG ( <NUM_LIT> ) ] ) ;


<s> if ( OpWidth == <NUM_LIT> ) return Subtarget . canUseCMPXCHG8B ( ) && ! Subtarget . is64Bit ( ) ;

if ( OpWidth == <NUM_LIT> ) return Subtarget . canUseCMPXCHG16B ( ) ;


<s> DebugLoc DL ; if ( I != MBB . end ( ) && ! I -> isDebugInstr ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction * MF = MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF -> getFrameInfo ( ) ; MachineMemOperand * MMO = MF -> getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( * MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const {

return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || MF . getFrameInfo ( ) . hasStackObjects ( ) ;


<s> BaseVal = V ; V = getBrevLdObject ( V ) ; } while ( BaseVal != V ) ;

if ( const PHINode * PN = dyn_cast < PHINode > ( V ) ) return returnEdge ( PN , IntrBaseVal ) ;


<s> <ISA_LIT>FunctionInfo :: ~ <ISA_LIT>FunctionInfo ( ) {


<s> Offset = <NUM_LIT> ; } else if ( DAG . isBaseWithConstantOffset ( Ptr ) && isa < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) ) { FI = cast < FrameIndexSDNode > ( Ptr . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Offset = Ptr . getConstantOperandVal ( <NUM_LIT> ) ; Ptr = Ptr . getOperand ( <NUM_LIT> ) ; } else { return SDValue ( ) ; } unsigned RequiredAlign = VT . getSizeInBits ( ) / <NUM_LIT> ; SDValue Chain = LD -> getChain ( ) ; MachineFrameInfo * MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; if ( DAG . InferPtrAlignment ( Ptr ) < RequiredAlign ) { if ( MFI -> isFixedObjectIndex ( FI ) ) { return SDValue ( ) ; } else { MFI -> setObjectAlignment ( FI , RequiredAlign ) ; } } if ( Offset < <NUM_LIT> ) return SDValue ( ) ;

if ( ( Offset % RequiredAlign ) & <NUM_LIT> ) return SDValue ( ) ;


<s> if ( DispOp . isImm ( ) ) { if ( FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 && FixupKind != FK_PCRel_4 ) { EmitConstant ( DispOp . getImm ( ) + ImmOffset , Size , CurByte , OS ) ; return ; } Expr = MCConstantExpr :: Create ( DispOp . getImm ( ) , Ctx ) ; } else { Expr = DispOp . getExpr ( ) ; } if ( FixupKind == FK_Data_4 && StartsWithGlobalOffsetTable ( Expr ) ) { assert ( ImmOffset == <NUM_LIT> ) ; FixupKind = MCFixupKind ( <STR_LIT> ) ; ImmOffset = CurByte ;


<s> vqtbx4q_s8 ( int8x16_t r , int8x16x4_t tab , uint8x16_t idx ) { __builtin_aarch64_simd_xi __o ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ; __o = __builtin_aarch64_set_qregxiv16qi ( __o , tab . val [ <NUM_LIT> ] , <NUM_LIT> ) ;


<s> aligned_p = <NUM_LIT> ; break ; } fputs ( <STR_LIT> , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'B' ) ; fputc ( '\n' , asm_out_file ) ; return true ; case <NUM_LIT> : if ( GET_CODE ( x ) != CONST_INT ) { aligned_p = <NUM_LIT> ; break ; } fputs ( <STR_LIT> , asm_out_file ) ; mmix_print_operand ( asm_out_file , x , 'W' ) ; fputc ( '\n' , asm_out_file ) ; return true ;


<s> inline bool BitTracker :: has ( unsigned Reg ) const {

return Map . find ( Reg ) != Map . end ( ) ;


<s> unsigned DstReg = MRI . createVirtualRegister ( SRC ) ; unsigned SubRegs = VRC -> getSize ( ) / <NUM_LIT> ; SmallVector < unsigned , <NUM_LIT> > SRegs ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { unsigned SGPR = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * UseMI -> getParent ( ) , UseMI , UseMI -> getDebugLoc ( ) , get ( <STR_LIT> ) , SGPR ) . addReg ( SrcReg , <NUM_LIT> , RI . getSubRegFromChannel ( i ) ) ; SRegs . push_back ( SGPR ) ; } MachineInstrBuilder MIB = BuildMI ( * UseMI -> getParent ( ) , UseMI , UseMI -> getDebugLoc ( ) , get ( <STR_LIT> ) , DstReg ) ; for ( unsigned i = <NUM_LIT> ; i < SubRegs ; ++ i ) { MIB . addReg ( SRegs [ i ] ) ; MIB . addImm ( RI . getSubRegFromChannel ( i ) ) ; } return DstReg ;


return getModifiers ( ) . hasFPModifiers ( ) ;


<s> DebugLoc dl = Op . getDebugLoc ( ) ; if ( Depth > <NUM_LIT> ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( TD -> getPointerSize ( ) , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , FrameAddr , Offset ) , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; } SDValue RetAddrFI = getReturnAddressFrameIndex ( DAG ) ; return DAG . getLoad ( getPointerTy ( ) , dl , DAG . getEntryNode ( ) , RetAddrFI , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ;


<s> int Idx = getOprIdx < const MCSubtargetInfo & > ( Name , Msg , MSG_<ISA_LIT>ZE , STI ) ;

return ( Idx < <NUM_LIT> ) ? Idx : Msg [ Idx ] . Encoding ;


<s> classifyPressureSet ( i , <STR_LIT> , SGPRPressureSets ) ; classifyPressureSet ( i , <STR_LIT> , VGPRPressureSets ) ; classifyPressureSet ( i , <STR_LIT> , AGPRPressureSets ) ; } std :: vector < unsigned > PressureSetRegUnits ( NumRegPressureSets , <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = getNumRegUnits ( ) ; i != e ; ++ i ) { const int * PSets = getRegUnitPressureSets ( i ) ; for ( unsigned j = <NUM_LIT> ; PSets [ j ] != - <NUM_LIT> ; ++ j ) { ++ PressureSetRegUnits [ PSets [ j ] ] ; } } unsigned VGPRMax = <NUM_LIT> , SGPRMax = <NUM_LIT> , AGPRMax = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < NumRegPressureSets ; ++ i ) { if ( isVGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > VGPRMax ) { VGPRSetID = i ; VGPRMax = PressureSetRegUnits [ i ] ; continue ; }

if ( isSGPRPressureSet ( i ) && PressureSetRegUnits [ i ] > SGPRMax ) {


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = SPRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> bool isRhazRs ( ) const { return Kind == OpKind :: RhazRs ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > W ( getTheARM64_32Target ( ) ) ;

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > V ( getThe<ISA_LIT>_32Target ( ) ) ;


<s> bool force32BitJumpTables ( ) const { return Force32BitJumpTables ;


<s> SMShadowTracker . emitShadowPadding ( * OutStreamer , getSubtargetInfo ( ) ) ;


<s> HadVectorOp = true ; VSETVLIInfo NewInfo = computeInfoForInstr ( MI , TSFlags , MRI ) ; if ( ! BBInfo . Change . isValid ( ) ) { BBInfo . Change = NewInfo ; } else { if ( ! canSkipVSETVLIForLoadStore ( MI , NewInfo , BBInfo . Change ) && needVSETVLI ( NewInfo , BBInfo . Change ) ) BBInfo . Change = NewInfo ; } } if ( MI . isCall ( ) || MI . isInlineAsm ( ) || MI . modifiesRegister ( <STR_LIT> ) || MI . modifiesRegister ( <STR_LIT> ) ) { BBInfo . Change = <STR_LIT> ( ) ;


<s> <ISA_LIT>SelectionDAGInfo :: ~ <ISA_LIT>SelectionDAGInfo ( ) {


<s> MachineInstr * NewGlob = nullptr ; NewGlob = BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII -> get ( NewOpcd ) ) ; if ( HasVdst ) NewGlob -> addOperand ( MF , MI . getOperand ( <NUM_LIT> ) ) ; NewGlob -> addOperand ( MF , MachineOperand :: CreateReg ( IndexReg , false ) ) ; if ( VData ) NewGlob -> addOperand ( MF , * VData ) ; NewGlob -> addOperand ( MF , MachineOperand :: CreateReg ( BaseReg , false ) ) ; NewGlob -> addOperand ( * TII -> getNamedOperand ( MI , <STR_LIT> :: offset ) ) ; MachineOperand * Glc = TII -> getNamedOperand ( MI , <STR_LIT> :: glc ) ; if ( Glc ) NewGlob -> addOperand ( MF , * Glc ) ; MachineOperand * DLC = TII -> getNamedOperand ( MI , <STR_LIT> :: dlc ) ; if ( DLC ) NewGlob -> addOperand ( MF , * DLC ) ; NewGlob -> addOperand ( * TII -> getNamedOperand ( MI , <STR_LIT> :: slc ) ) ; MachineOperand * VDstInOp = TII -> getNamedOperand ( MI , <STR_LIT> :: vdst_in ) ; if ( VDstInOp ) NewGlob -> addOperand ( MF , * VDstInOp ) ; NewGlob -> copyImplicitOps ( MF , MI ) ;


<s> if ( CPEs [ J ] . RefCount == <NUM_LIT> && CPEs [ J ] . CPEMI ) { removeDeadCPEMI ( CPEs [ J ] . CPEMI ) ; CPEs [ J ] . CPEMI = nullptr ; MadeChange = true ; } } }


<s> for ( oper = MI -> getNumOperands ( ) - <NUM_LIT> ; oper >= <NUM_LIT> ; -- oper ) { MachineOperand & MO = MI -> getOperand ( oper ) ; if ( MO . isReg ( ) && ! MO . isUse ( ) && ! MO . isImplicit ( ) ) { break ; } if ( MO . isReg ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToRegister ( MO . getReg ( ) , MO . isDef ( ) , MO . isImplicit ( ) , MO . isKill ( ) , MO . isDead ( ) , MO . isUndef ( ) , MO . isDebug ( ) ) ; } else if ( MO . isImm ( ) ) { MI -> getOperand ( oper + <NUM_LIT> ) . ChangeToImmediate ( MO . getImm ( ) ) ; } else if ( MO . isGlobal ( ) ) { assert ( hasGAOpnd == false && <STR_LIT> ) ; tmpOpnds . push_back ( MO ) ; hasGAOpnd = true ; GAIdx = oper ; continue ; } else { assert ( false && <STR_LIT> ) ; } } }

int regPos = invertJump ? <NUM_LIT> : <NUM_LIT> ;


<s> } SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Op . getOperand ( i * <NUM_LIT> + <NUM_LIT> ) , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ; else return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;


<s> offsets = arm_get_frame_offsets ( ) ;

return offsets -> outgoing_args != <NUM_LIT> ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue DstPtr = Op . getOperand ( <NUM_LIT> ) ; SDValue SrcPtr = Op . getOperand ( <NUM_LIT> ) ; const Value * DstSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; const Value * SrcSV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ; return DAG . getMemcpy ( Chain , DL , DstPtr , SrcPtr , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) , <NUM_LIT> , false , false , false , MachinePointerInfo ( DstSV ) , MachinePointerInfo ( SrcSV ) ) ;


<s> if ( ! isLoadTypeLegal ( I -> getType ( ) , VT ) ) return false ; Address Addr ; if ( ! ComputeAddress ( I -> getOperand ( <NUM_LIT> ) , Addr ) ) return false ; unsigned ResultReg ;

if ( ! EmitLoad ( VT , ResultReg , Addr , cast < LoadInst > ( I ) -> getAlignment ( ) ) ) return false ;


<s> if ( ! getReqNTIDx ( F , reqntidx ) ) reqntidx = <NUM_LIT> ; else specified = true ; if ( ! getReqNTIDy ( F , reqntidy ) ) reqntidy = <NUM_LIT> ; else specified = true ; if ( ! getReqNTIDz ( F , reqntidz ) ) reqntidz = <NUM_LIT> ; else specified = true ; if ( specified ) O << <STR_LIT> << reqntidx << <STR_LIT> << reqntidy << <STR_LIT> << reqntidz << <STR_LIT> ; unsigned maxntidx , maxntidy , maxntidz ; specified = false ; if ( ! getMaxNTIDx ( F , maxntidx ) ) maxntidx = <NUM_LIT> ; else specified = true ; if ( ! getMaxNTIDy ( F , maxntidy ) ) maxntidy = <NUM_LIT> ; else specified = true ; if ( ! getMaxNTIDz ( F , maxntidz ) ) maxntidz = <NUM_LIT> ; else specified = true ; if ( specified ) O << <STR_LIT> << maxntidx << <STR_LIT> << maxntidy << <STR_LIT> << maxntidz << <STR_LIT> ; unsigned mincta ; if ( getMinCTASm ( F , mincta ) ) O << <STR_LIT> << mincta << <STR_LIT> ; unsigned maxnreg ; if ( getMaxNReg ( F , maxnreg ) ) O << <STR_LIT> << maxnreg << <STR_LIT> ;


<s> if ( LogicalShift ) return DAG . getConstant ( <NUM_LIT> , SDLoc ( N ) , VT ) ; NewShiftVal = NumBitsPerElt - <NUM_LIT> ; } return DAG . getNode ( Opcode , SDLoc ( N ) , VT , N0 . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( NewShiftVal , SDLoc ( N ) , <STR_LIT> ) ) ; } if ( LogicalShift && ( ShiftVal % <NUM_LIT> ) == <NUM_LIT> ) { SDValue Op ( N , <NUM_LIT> ) ; if ( SDValue Res = combine<ISA_LIT>ShufflesRecursively ( Op , DAG , Subtarget ) ) return Res ; } APInt UndefElts ; SmallVector < APInt , <NUM_LIT> > EltBits ; if ( N -> isOnlyUserOf ( N0 . getNode ( ) ) && getTargetConstantBitsFromNode ( N0 , NumBitsPerElt , UndefElts , EltBits ) ) { assert ( EltBits . size ( ) == VT . getVectorNumElements ( ) && <STR_LIT> ) ; for ( APInt & Elt : EltBits ) { if ( <STR_LIT> == Opcode ) Elt <<= ShiftVal ; else if ( <STR_LIT> == Opcode ) Elt . ashrInPlace ( ShiftVal ) ; else Elt . lshrInPlace ( ShiftVal ) ; }

return getConstVector ( EltBits , UndefElts , VT . getSimpleVT ( ) , DAG , SDLoc ( N ) ) ;


<s> const TargetInstrDesc & TID = get ( Opc ) ; const TargetOperandInfo & TOI = TID . OpInfo [ Index ] ; const TargetRegisterClass * RC = TOI . isLookupPtrRegClass ( ) ? RI . getPointerRegClass ( ) : RI . getRegClass ( TOI . RegClass ) ; unsigned NumDefs = TID . NumDefs ; std :: vector < SDValue > AddrOps ; std :: vector < SDValue > BeforeOps ; std :: vector < SDValue > AfterOps ; DebugLoc dl = N -> getDebugLoc ( ) ; unsigned NumOps = N -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i != NumOps - <NUM_LIT> ; ++ i ) { SDValue Op = N -> getOperand ( i ) ; if ( i >= Index - NumDefs && i < Index - NumDefs + <NUM_LIT> ) AddrOps . push_back ( Op ) ; else if ( i < Index - NumDefs ) BeforeOps . push_back ( Op ) ; else if ( i > Index - NumDefs ) AfterOps . push_back ( Op ) ; } SDValue Chain = N -> getOperand ( NumOps - <NUM_LIT> ) ; AddrOps . push_back ( Chain ) ; SDNode * Load = <NUM_LIT> ; const MachineFunction & MF = DAG . getMachineFunction ( ) ; if ( FoldedLoad ) { MVT VT = * RC -> vt_begin ( ) ; bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . needsStackRealignment ( MF ) ; Load = DAG . getTargetNode ( getLoadRegOpcode ( RC , isAligned ) , dl , VT , <STR_LIT> , & AddrOps [ <NUM_LIT> ] , AddrOps . size ( ) ) ; NewNodes . push_back ( Load ) ; } std :: vector < MVT > VTs ; const TargetRegisterClass * DstRC = <NUM_LIT> ; if ( TID . getNumDefs ( ) > <NUM_LIT> ) { const TargetOperandInfo & DstTOI = TID . OpInfo [ <NUM_LIT> ] ; DstRC = DstTOI . isLookupPtrRegClass ( ) ? RI . getPointerRegClass ( ) : RI . getRegClass ( DstTOI . RegClass ) ; VTs . push_back ( * DstRC -> vt_begin ( ) ) ; }

for ( unsigned i = <NUM_LIT> , e = N -> getNumValues ( ) ; i != e ; ++ i ) {


<s> if ( ! Src1Ty . isVector ( ) || ! Src2Ty . isVector ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } unsigned BytesPerElt = DstTy . getElementType ( ) . getSizeInBits ( ) / <NUM_LIT> ; SmallVector < Constant * , <NUM_LIT> > CstIdxs ; for ( int Val : Mask ) { Val = Val < <NUM_LIT> ? <NUM_LIT> : Val ; for ( unsigned Byte = <NUM_LIT> ; Byte < BytesPerElt ; ++ Byte ) { unsigned Offset = Byte + Val * BytesPerElt ; CstIdxs . emplace_back ( ConstantInt :: get ( Type :: getInt8Ty ( Ctx ) , Offset ) ) ; } } Constant * CPVal = ConstantVector :: get ( CstIdxs ) ; MachineInstr * IndexLoad = emitLoadFromConstantPool ( CPVal , MIB ) ; if ( ! IndexLoad ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( DstTy . getSizeInBits ( ) != <NUM_LIT> ) { assert ( DstTy . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; MachineInstr * Concat = emitVectorConcat ( None , Src1Reg , Src2Reg , MIB ) ; if ( ! Concat ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } IndexLoad = emitScalarToVector ( <NUM_LIT> , & <STR_LIT> , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) , MIB ) ; auto TBL1 = MIB . buildInstr ( <STR_LIT> , { & <STR_LIT> } , { Concat -> getOperand ( <NUM_LIT> ) . getReg ( ) , IndexLoad -> getOperand ( <NUM_LIT> ) . getReg ( ) } ) ;

constrainSelectedInstRegOperands ( * TBL1 , TII , TRI , RBI ) ;


<s> void <ISA_LIT>SEInstrInfo :: ExpandBuildPairF64 ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { unsigned DstReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , HiReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const MCInstrDesc & Mtc1Tdd = get ( <STR_LIT> ) ; DebugLoc dl = I -> getDebugLoc ( ) ; const TargetRegisterInfo & TRI = getRegisterInfo ( ) ;

BuildMI ( MBB , I , dl , Mtc1Tdd , TRI . getSubReg ( DstReg , <STR_LIT> ) ) . addReg ( LoReg ) ;


<s> nios2_builtin_decls [ code ] = fndecl ;


<s> EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ShadowRegI8 ) . addReg ( ShadowRegI8 ) ) ; MCSymbol * DoneSym = Ctx . createTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: create ( DoneSym , Ctx ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( AddressRegI32 ) ) ; EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addReg ( ScratchRegI32 ) . addReg ( ScratchRegI32 ) . addImm ( <NUM_LIT> ) ) ; switch ( AccessSize ) { default : llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : break ; case <NUM_LIT> : { const MCExpr * Disp = MCConstantExpr :: create ( <NUM_LIT> , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , ScratchRegI32 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; EmitLEA ( * Op , <STR_LIT> , ScratchRegI32 , Out ) ; break ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerABS ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ;


<s> return isMem512 ( ) && isMemIndexReg ( <STR_LIT> , <STR_LIT> ) ;


<s> return ( ( vec_double2 ) ( si_dfa ( ( qword ) ( a ) , ( qword ) ( b ) ) ) ) ;


<s> if ( ! Subtarget -> hasV6Ops ( ) ) return false ; else if ( ! Subtarget -> hasV6Ops ( ) ) { if ( ! Subtarget -> isTargetDarwin ( ) ) return false ; } switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> unsigned JumpOffset = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; Inst . addOperand ( MCOperand :: CreateImm ( JumpOffset ) ) ;


<s> if ( TARGET_SIMD && aarch64_vector_mode_p ( mode1 ) && aarch64_vector_mode_p ( mode2 ) ) return true ;


<s> if ( ! CONST_INT_P ( op [ nopnds ] ) ) error ( <STR_LIT> , arg_num ) ; else error ( <STR_LIT> <STR_LIT> , arg_num ) ; return const0_rtx ; } op [ nopnds ] = copy_to_mode_reg ( insn_op -> mode , op [ nopnds ] ) ; } nopnds ++ ; } switch ( fcode ) { case RS6000_BIF_TENDALL : case RS6000_BIF_TRESUME : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; break ; case RS6000_BIF_TSUSPEND : op [ nopnds ++ ] = GEN_INT ( <NUM_LIT> ) ; break ; default : break ; } rtx cr = NULL_RTX ; if ( uses_spr ) { machine_mode mode = TARGET_POWERPC64 ? DImode : SImode ; op [ nopnds ++ ] = gen_rtx_CONST_INT ( mode , htm_spr_num ( fcode ) ) ; } else if ( bif_is_htmcr ( * bifaddr ) ) { cr = gen_reg_rtx ( CCmode ) ; op [ nopnds ++ ] = cr ; } rtx pat ; switch ( nopnds ) { case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> : pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ; break ; case <NUM_LIT> :

pat = GEN_FCN ( icode ) ( op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] , op [ <NUM_LIT> ] ) ;


<s> void <ISA_LIT>SEFrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const <ISA_LIT>SEInstrInfo & TII = * static_cast < const <ISA_LIT>SEInstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; unsigned SP = STI . isABI_N64 ( ) ? <STR_LIT> : <STR_LIT> ;

TII . adjustStackPtr ( SP , Amount , MBB , I ) ;


<s> static bool isZeroExtended ( SDNode * N , SelectionDAG & DAG ) { if ( N -> getOpcode ( ) == <STR_LIT> || <STR_LIT> ( N ) ) return true ; if ( isExtendedBUILD_VECTOR ( N , DAG , false ) ) return true ; return false ;


<s> Thumb1FrameLowering :: Thumb1FrameLowering ( const <ISA_LIT>Subtarget & sti ) : <ISA_LIT>FrameLowering ( sti ) {


return STI . getTargetTriple ( ) . startswith ( <STR_LIT> ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> parts . index = XVECEXP ( addr , <NUM_LIT> , <NUM_LIT> ) ; addr = XVECEXP ( addr , <NUM_LIT> , <NUM_LIT> ) ; } else ok = ix86_decompose_address ( addr , & parts ) ; gcc_assert ( ok ) ; base = parts . base ; index = parts . index ; disp = parts . disp ; scale = parts . scale ; if ( ADDR_SPACE_GENERIC_P ( as ) ) as = parts . seg ; else gcc_assert ( ADDR_SPACE_GENERIC_P ( parts . seg ) ) ; if ( ! ADDR_SPACE_GENERIC_P ( as ) ) { const char * string ; if ( as == ADDR_SPACE_SEG_FS ) string = ( ASSEMBLER_DIALECT == ASM_ATT ? <STR_LIT> : <STR_LIT> ) ; else if ( as == ADDR_SPACE_SEG_GS ) string = ( ASSEMBLER_DIALECT == ASM_ATT ? <STR_LIT> : <STR_LIT> ) ; else gcc_unreachable ( ) ; fputs ( string , file ) ; } if ( TARGET_64BIT && ! base && ! index && ! no_rip ) { rtx symbol = disp ; if ( GET_CODE ( disp ) == CONST && GET_CODE ( XEXP ( disp , <NUM_LIT> ) ) == PLUS && CONST_INT_P ( XEXP ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) ) ) symbol = XEXP ( XEXP ( disp , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( symbol ) == LABEL_REF || ( GET_CODE ( symbol ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( symbol ) == <NUM_LIT> ) ) base = pc_rtx ; } if ( ! base && ! index ) { if ( CONST_INT_P ( disp ) ) { if ( ASSEMBLER_DIALECT == ASM_INTEL && parts . seg == ADDR_SPACE_GENERIC ) fputs ( <STR_LIT> , file ) ; fprintf ( file , HOST_WIDE_INT_PRINT_DEC , INTVAL ( disp ) ) ; } else if ( flag_pic ) output_pic_addr_const ( file , disp , <NUM_LIT> ) ; else output_addr_const ( file , disp ) ; } else { if ( SImode_address_operand ( addr , VOIDmode ) ) { if ( flag_checking ) { gcc_assert ( TARGET_64BIT ) ; switch ( GET_CODE ( addr ) ) { case SUBREG : gcc_assert ( GET_MODE ( addr ) == SImode ) ; gcc_assert ( GET_MODE ( SUBREG_REG ( addr ) ) == DImode ) ; break ; case ZERO_EXTEND : case AND : gcc_assert ( GET_MODE ( addr ) == DImode ) ; break ; default : gcc_unreachable ( ) ; } } gcc_assert ( ! code ) ; code = 'k' ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( <STR_LIT> ( Literal . getZExtValue ( ) , AsmParser -> hasInv2PiInlineImm ( ) ) ) { Inst . addOperand ( MCOperand :: createImm ( Literal . getZExtValue ( ) ) ) ; setImmKindConst ( ) ; return ; } if ( <STR_LIT> ( InstDesc , OpNum ) ) { if ( Literal . getLoBits ( <NUM_LIT> ) != <NUM_LIT> ) { const_cast < <ISA_LIT>AsmParser * > ( AsmParser ) -> Warning ( Inst . getLoc ( ) , <STR_LIT> <STR_LIT> ) ; } Inst . addOperand ( MCOperand :: createImm ( Literal . lshr ( <NUM_LIT> ) . getZExtValue ( ) ) ) ; setImmKindLiteral ( ) ; return ; } llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { bool lost ; APFloat FPLiteral ( APFloat :: IEEEdouble ( ) , Literal ) ; FPLiteral . convert ( * getOpFltSemantics ( OpTy ) , APFloat :: rmNearestTiesToEven , & lost ) ; uint64_t ImmVal = FPLiteral . bitcastToAPInt ( ) . getZExtValue ( ) ; Inst . addOperand ( MCOperand :: createImm ( ImmVal ) ) ; setImmKindLiteral ( ) ; return ; } default : llvm_unreachable ( <STR_LIT> ) ; } return ; } switch ( OpTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( isSafeTruncation ( Val , <NUM_LIT> ) && <STR_LIT> ( static_cast < int32_t > ( Val ) , AsmParser -> hasInv2PiInlineImm ( ) ) ) { Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; setImmKindConst ( ) ; return ; } Inst . addOperand ( MCOperand :: createImm ( Val & <NUM_LIT> ) ) ; setImmKindLiteral ( ) ; return ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( <STR_LIT> ( Val , AsmParser -> hasInv2PiInlineImm ( ) ) ) { Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; setImmKindConst ( ) ; return ; } Inst . addOperand ( MCOperand :: createImm ( Lo_32 ( Val ) ) ) ; setImmKindLiteral ( ) ;


<s> while ( ! MBB -> pred_empty ( ) ) { MachineBasicBlock * Pred = * MBB -> pred_begin ( ) ; transferSuccessor ( Pred , MBB , newBB ) ; } newBB -> addSuccessor ( MBB , <NUM_LIT> ) ;

MF -> insert ( MachineFunction :: iterator ( MBB ) , newBB ) ;


<s> return ( __m128i ) __builtin_ia32_pmovsqw128_mask ( ( __v2di ) __A , ( __v8hi ) _mm_undefined_si128 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ;

if ( MI -> modifiesRegister ( <STR_LIT> , TRI ) ) return true ;


<s> Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else if ( Ty == LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ) { Opc = ImmVal ? <STR_LIT> : <STR_LIT> ; } else {


<s> continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> BranchCode = static_cast < <STR_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( BranchCode == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ; } assert ( Cond . size ( ) == <NUM_LIT> ) ; assert ( TBB ) ; if ( TBB != I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) return true ;

<STR_LIT> OldBranchCode = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ;


<s> return __builtin_mve_vqrshlq_sv4si ( __a , __b ) ;


<s> const <ISA_LIT>Subtarget * Subtarget = & tm . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget -> isDarwin ( ) ) return new <ISA_LIT>DarwinAsmPrinter ( tm , Streamer ) ; return new <ISA_LIT>LinuxAsmPrinter ( tm , Streamer ) ;


<s> bool functionModified = false ; Function :: iterator I = function . begin ( ) ; TerminatorInst * firstTerminatorInst = ( I ++ ) -> getTerminator ( ) ; for ( Function :: iterator E = function . end ( ) ; I != E ; ++ I ) { for ( BasicBlock :: iterator BI = I -> begin ( ) , BE = I -> end ( ) ; BI != BE ; ) { AllocaInst * allocaInst = dyn_cast < AllocaInst > ( BI ++ ) ; if ( allocaInst && isa < ConstantInt > ( allocaInst -> getArraySize ( ) ) ) {

allocaInst -> moveBefore ( firstTerminatorInst ) ;


<s> return NULL ; case ALPHA_FPTM_U : return <STR_LIT> ; case ALPHA_FPTM_SU : return <STR_LIT> ; case ALPHA_FPTM_SUI : return <STR_LIT> ; default : gcc_unreachable ( ) ; } break ; case TRAP_SUFFIX_U_SU_SUI : switch ( alpha_fptm ) { case ALPHA_FPTM_N : return NULL ; case ALPHA_FPTM_U : return <STR_LIT> ; case ALPHA_FPTM_SU : return <STR_LIT> ; case ALPHA_FPTM_SUI : return <STR_LIT> ; default : gcc_unreachable ( ) ;


<s> int64_t Val = CE -> getValue ( ) ; return ( Val > - <NUM_LIT> && Val < <NUM_LIT> ) || ( Val == std :: numeric_limits < int32_t > :: min ( ) ) ; }


<s> static SDValue LowerAtomicLoadStore ( SDValue Op , SelectionDAG & DAG ) { if ( isStrongerThanMonotonic ( cast < AtomicSDNode > ( Op ) -> getSuccessOrdering ( ) ) ) return SDValue ( ) ;


<s> uint16x4_t result ; __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ; return result ;


<s> if ( defs . test ( i ) ) return true ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> if ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ; } else if ( TM . getRelocationModel ( ) == Reloc :: DynamicNoPIC ) { OutStreamer . SwitchSection ( OutContext . getMachOSection ( <STR_LIT> , <STR_LIT> , MCSectionMachO :: S_SYMBOL_STUBS | MCSectionMachO :: S_ATTR_PURE_INSTRUCTIONS , <NUM_LIT> , SectionKind :: getText ( ) ) ) ;


<s> if ( res < <NUM_LIT> && warn_psabi ) inform ( input_location , <STR_LIT> <STR_LIT> , type ) ; if ( res > <NUM_LIT> && warn_psabi ) inform ( input_location , <STR_LIT> <STR_LIT> , type ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , LHS , TV , FV ) ; case <STR_LIT> : case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : if ( LHS . getValueType ( ) == <STR_LIT> ) LHS = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS ) , TV , FV ) ; } SDValue Cmp ; switch ( CC ) { default : break ; case <STR_LIT> : std :: swap ( TV , FV ) ; LLVM_FALLTHROUGH ; case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; Sel1 = DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; if ( Sel1 . getValueType ( ) == <STR_LIT> ) Sel1 = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Sel1 ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) , Sel1 , FV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , FV , TV ) ; case <STR_LIT> : case <STR_LIT> : Cmp = DAG . getNode ( <STR_LIT> , dl , CmpVT , LHS , RHS , Flags ) ; if ( Cmp . getValueType ( ) == <STR_LIT> ) Cmp = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Cmp ) ; return DAG . getNode ( <STR_LIT> , dl , ResVT , Cmp , TV , FV ) ; case <STR_LIT> :


<s> S = Parser . getTok ( ) . getLoc ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , S ) ) ; Parser . Lex ( ) ; } return false ; } StringRef Identifier ; if ( Parser . parseIdentifier ( Identifier ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; MCSymbol * Sym = getContext ( ) . GetOrCreateSymbol ( <STR_LIT> + Identifier ) ; const MCExpr * Res = MCSymbolRefExpr :: Create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( Res , S , E ) ) ; return false ; } case AsmToken :: Identifier : case AsmToken :: LParen : case AsmToken :: Minus : case AsmToken :: Plus : case AsmToken :: Integer : case AsmToken :: String : { const MCExpr * IdVal ; SMLoc S = Parser . getTok ( ) . getLoc ( ) ; if ( getParser ( ) . parseExpression ( IdVal ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; Operands . push_back ( <STR_LIT> ( IdVal , S , E ) ) ; return false ; } case AsmToken :: Percent : { const MCExpr * IdVal ;


return ( __m256 ) __builtin_ia32_compresssf256_mask ( ( __v8sf ) __A , ( __v8sf ) _mm256_setzero_ps ( ) , ( __mmask8 ) __U ) ;


<s> MVT WVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * VT . getVectorNumElements ( ) ) ; if ( VT != <STR_LIT> && ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( WVT ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget . hasSSE41 ( ) && ( N0 . getOpcode ( ) == <STR_LIT> && N0 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) && ( N1 . getOpcode ( ) == <STR_LIT> && N1 . getOperand ( <NUM_LIT> ) . getScalarValueSizeInBits ( ) <= <NUM_LIT> ) ) return SDValue ( ) ; APInt Mask17 = APInt :: getHighBitsSet ( <NUM_LIT> , <NUM_LIT> ) ;

if ( ! DAG . MaskedValueIsZero ( N1 , Mask17 ) || ! DAG . MaskedValueIsZero ( N0 , Mask17 ) ) return SDValue ( ) ;


<s> O << OffsetOp . getImm ( ) ; } else { assert ( <NUM_LIT> && <STR_LIT> ) ; } assert ( RegOp . isReg ( ) && <STR_LIT> ) ; O << <STR_LIT> << getRegisterName ( RegOp . getReg ( ) ) << <STR_LIT> ;


<s> bool <ISA_LIT>LibCalls :: isUnsafeMath ( const CallInst * CI ) const { if ( auto Op = dyn_cast < FPMathOperator > ( CI ) ) if ( Op -> isFast ( ) ) return true ; const Function * F = CI -> getParent ( ) -> getParent ( ) ;

Attribute Attr = F -> getFnAttribute ( <STR_LIT> ) ;


<s> FuncName = GV -> getName ( ) . data ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; assert ( funcType != nullptr ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; SmallVector < SDValue , <NUM_LIT> > VarOps ; SDVTList VTs = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; Type * retType = funcType -> getReturnType ( ) ; SDValue RetValue ; if ( ! retType -> isVoidTy ( ) ) { MVT PtrVT = getPointerTy ( DL , <STR_LIT> ) ; RetValue = DAG . getTargetExternalSymbol ( PM . getParamName ( PM . addCallRetParam ( retType , PM . mangleArg ( & Mang , FuncName , DL ) ) ) , PtrVT ) ; unsigned NElts ; Type * EmitTy = <STR_LIT> ( retType , NElts , DL ) ; BrigType BT = getParamBrigType ( EmitTy , DL , CLI . RetSExt ) ; unsigned Align = <STR_LIT> ( retType , DL , false ) ; const SDValue ArgDeclOps [ ] = { RetValue , DAG . getTargetConstant ( BT , dl , <STR_LIT> ) , DAG . getTargetConstant ( NElts , dl , PtrVT ) , DAG . getTargetConstant ( Align , dl , <STR_LIT> ) , Chain , InFlag } ; SDNode * ArgDeclNode = DAG . getMachineNode ( <STR_LIT> , dl , VTs , ArgDeclOps ) ; SDValue ArgDecl ( ArgDeclNode , <NUM_LIT> ) ; Chain = SDValue ( ArgDeclNode , <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; VarOps . push_back ( RetValue ) ; } VarOps . push_back ( DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; unsigned FirstArg = VarOps . size ( ) ; unsigned int j = <NUM_LIT> , k = <NUM_LIT> ; Function :: const_arg_iterator ai ; Function :: const_arg_iterator ae ; if ( calleeFunc ) { ai = calleeFunc -> arg_begin ( ) ; ae = calleeFunc -> arg_end ( ) ; } MVT ArgPtrVT = getPointerTy ( DL , <STR_LIT> ) ; MDBuilder MDB ( * DAG . getContext ( ) ) ; for ( FunctionType :: param_iterator pb = funcType -> param_begin ( ) , pe = funcType -> param_end ( ) ; pb != pe ; ++ pb , ++ ai , ++ k ) { Type * type = * pb ; std :: string ParamName ; if ( calleeFunc && ai != ae ) { ParamName = PM . mangleArg ( & Mang , ai -> getName ( ) , DL ) ; } if ( ParamName . empty ( ) ) {


<s> if ( ! usingDefaultRegAlloc ( ) ) report_fatal_error ( RegAllocOptNotSupportedMessage ) ;

addPass ( createSGPRAllocPass ( false ) ) ;


<s> static MachineBasicBlock * getBranchTarget ( const MachineInstr & MI ) { assert ( isUnconditionalBranch ( MI ) || isConditionalBranch ( MI ) ) ; return MI . getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> if ( ParseDirectiveMajorMinor ( Major , Minor ) ) return true ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; Lex ( ) ; if ( ParseAsAbsoluteExpression ( Stepping ) ) return TokError ( <STR_LIT> ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: String ) ) return TokError ( <STR_LIT> ) ; VendorName = getLexer ( ) . getTok ( ) . getStringContents ( ) ; Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: Comma ) ) return TokError ( <STR_LIT> ) ; Lex ( ) ;


<s> return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4 ( Op , DAG ) ; if ( Res . getNode ( ) ) return Res ; } EVT VT = Op . getValueType ( ) ; DebugLoc dl = Op . getDebugLoc ( ) ; if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { SDValue Vec = Op . getOperand ( <NUM_LIT> ) ; unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec ) , Op . getOperand ( <NUM_LIT> ) ) ) ; EVT EltVT = <STR_LIT> ; SDValue Extract = DAG . getNode ( <STR_LIT> , dl , EltVT , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDValue Assert = DAG . getNode ( <STR_LIT> , dl , EltVT , Extract , DAG . getValueType ( VT ) ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Assert ) ; } else if ( VT . getSizeInBits ( ) == <NUM_LIT> ) { unsigned Idx = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Idx == <NUM_LIT> ) return Op ;

int Mask [ <NUM_LIT> ] = { Idx , - <NUM_LIT> , - <NUM_LIT> , - <NUM_LIT> } ;


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; StringRef Name = Mapper . toString ( MO . getImm ( ) , ValidName ) ; if ( ValidName ) O << Name ; else O << '#' << MO . getImm ( ) ;


<s> <STR_LIT> ( const TargetOptions & pTargetOptions ) : GNUInfo ( pTargetOptions . triple ( ) ) , m_Options ( pTargetOptions ) {


<s> bool <ISA_LIT>TargetLowering :: isConstantUnsignedBitfieldExtractLegal ( unsigned Opc , LLT Ty1 , LLT Ty2 ) const { return ( Ty1 == LLT :: scalar ( <NUM_LIT> ) || Ty1 == LLT :: scalar ( <NUM_LIT> ) ) && Ty2 == LLT :: scalar ( <NUM_LIT> ) ;


<s> if ( ! hasFlatOffsets ( ) && Op . getImm ( ) != <NUM_LIT> ) { Error ( getFlatOffsetLoc ( Operands ) , <STR_LIT> ) ; return false ; } if ( TSFlags & ( <STR_LIT> | <STR_LIT> ) ) { unsigned OffsetSize = <STR_LIT> ( getSTI ( ) , true ) ; if ( ! isIntN ( OffsetSize , Op . getImm ( ) ) ) { Error ( getFlatOffsetLoc ( Operands ) , Twine ( <STR_LIT> ) + Twine ( OffsetSize ) + <STR_LIT> ) ; return false ; } } else { unsigned OffsetSize = <STR_LIT> ( getSTI ( ) , false ) ; if ( ! isUIntN ( OffsetSize , Op . getImm ( ) ) ) { Error ( getFlatOffsetLoc ( Operands ) , Twine ( <STR_LIT> ) + Twine ( OffsetSize ) + <STR_LIT> ) ; return false ; } }


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI ) : MCDisassembler ( STI ) {


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> sese -> remove ( pseudo_node_t ( me , dir ) ) ; FOR_EACH_EDGE ( e , ei , edges ) { basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ; if ( bb_sese * t_sese = BB_GET_SESE ( target ) ) { if ( t_sese -> node < sese -> node + dir && ! ( dir < <NUM_LIT> && sese -> parent == t_sese -> node ) ) sese -> push ( pseudo_node_t ( target , usd * t_sese -> dir ) ) ; } else { sese -> push ( pseudo_node_t ( <NUM_LIT> , <NUM_LIT> ) ) ; } } if ( ! sese -> brackets . length ( ) || ! edges || ! edges -> length ( ) ) { hi_back = <NUM_LIT> ; node_back = pseudo_node_t ( <NUM_LIT> , <NUM_LIT> ) ; sese -> push ( node_back ) ; } sese -> high = hi_back < hi_child ? node_back : node_child ; if ( num_children > <NUM_LIT> ) { hi_child = depth ; if ( dir < <NUM_LIT> && child ) { node_child = sese -> high ; hi_child = node_child . second ; if ( node_child . first ) hi_child += BB_GET_SESE ( node_child . first ) -> node ; } FOR_EACH_EDGE ( e , ei , edges ) { basic_block target = * ( basic_block * ) ( ( char * ) e + offset ) ; if ( target == child ) continue ; bb_sese * t_sese = BB_GET_SESE ( target ) ; if ( ! t_sese ) continue ; if ( t_sese -> parent != sese -> node ) continue ; int t_hi = t_sese -> high . second ; if ( basic_block child_hi_block = t_sese -> high . first ) t_hi += BB_GET_SESE ( child_hi_block ) -> node ; if ( hi_child > t_hi ) { hi_child = t_hi ; node_child = t_sese -> high ; } } sese -> push ( node_child ) ;


<s> uint64_t Val = MI -> getOperand ( OpNum ) . getImm ( ) ; O << <STR_LIT> ;

O . write_hex ( <STR_LIT> ( Val , <NUM_LIT> ) ) ;


<s> if ( ALL_FIXED_POINT_MODE_P ( mode ) && GET_MODE_PRECISION ( mode ) <= <NUM_LIT> * BITS_PER_WORD ) return true ;

return default_scalar_mode_supported_p ( mode ) ;


<s> static bool shouldEmitGOTReloc ( const GlobalValue * GV , const TargetMachine & TM ) {

return GV -> getType ( ) -> getAddressSpace ( ) == <ISA_LIT>AS :: GLOBAL_ADDRESS && ! TM . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ;


<s> assert ( T == AM . Segment ) ; AM . Segment = Copy ; EVT VT = N . getValueType ( ) ; unsigned Complexity = <NUM_LIT> ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase ) if ( AM . Base_Reg . getNode ( ) ) Complexity = <NUM_LIT> ; else AM . Base_Reg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; else if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) Complexity = <NUM_LIT> ; if ( AM . IndexReg . getNode ( ) ) Complexity ++ ; else AM . IndexReg = CurDAG -> getRegister ( <NUM_LIT> , VT ) ; if ( AM . Scale > <NUM_LIT> ) Complexity ++ ; if ( AM . hasSymbolicDisplacement ( ) ) { if ( Subtarget -> is64Bit ( ) ) Complexity = <NUM_LIT> ; else Complexity += <NUM_LIT> ; } if ( AM . Disp && ( AM . Base_Reg . getNode ( ) || AM . IndexReg . getNode ( ) ) ) Complexity ++ ; if ( Complexity <= <NUM_LIT> ) return false ;

getAddressOperands ( AM , Base , Scale , Index , Disp , Segment ) ;


<s> const MCInstrDesc & Desc = MII . get ( Opc ) ; if ( ( Desc . TSFlags & <STR_LIT> ) == <NUM_LIT> ) return true ;

int DimIdx = <STR_LIT> ( Opc , <STR_LIT> :: dim ) ;


<s> OS << <STR_LIT> ; emitReturnList ( Sig ) ;


<s> asm_fprintf ( f , <STR_LIT> , PC_REGNUM , PC_REGNUM ) ; } else if ( TARGET_THUMB2 ) { fprintf ( f , <STR_LIT> ) ; asm_fprintf ( f , <STR_LIT> , STATIC_CHAIN_REGNUM , PC_REGNUM ) ; asm_fprintf ( f , <STR_LIT> , PC_REGNUM , PC_REGNUM ) ; } else { ASM_OUTPUT_ALIGN ( f , <NUM_LIT> ) ; fprintf ( f , <STR_LIT> ) ;


__builtin_aarch64_st1v4hi ( ( __builtin_aarch64_simd_hi * ) a , b ) ;


<s> if ( INSN_ADDRESSES_SET_P ( ) ) return INSN_ADDRESSES ( INSN_UID ( lab ) ) > INSN_ADDRESSES ( INSN_UID ( insn ) ) ; while ( insn ) {


<s> MachineInstr * Clone = MF -> CloneMachineInstr ( DBI ) ; Clone -> getOperand ( <NUM_LIT> ) . setReg ( NewReg ) ; MBB -> insert ( Insert , Clone ) ;


<s> BasicBlockInfo ( ) : Offset ( <NUM_LIT> ) , Size ( <NUM_LIT> ) {


<s> else if ( TM . getOptLevel ( ) > CodeGenOpt :: None ) OptimizationGoal = <NUM_LIT> ; else OptimizationGoal = <NUM_LIT> ; if ( OptimizationGoals == - <NUM_LIT> ) OptimizationGoals = OptimizationGoal ; else if ( OptimizationGoals != ( int ) OptimizationGoal ) OptimizationGoals = <NUM_LIT> ; if ( Subtarget -> isTargetCOFF ( ) ) { bool Internal = F -> hasInternalLinkage ( ) ; COFF :: SymbolStorageClass Scl = Internal ? COFF :: IMAGE_SYM_CLASS_STATIC : COFF :: IMAGE_SYM_CLASS_EXTERNAL ; int Type = COFF :: IMAGE_SYM_DTYPE_FUNCTION << COFF :: SCT_COMPLEX_TYPE_SHIFT ; OutStreamer -> BeginCOFFSymbolDef ( CurrentFnSym ) ; OutStreamer -> EmitCOFFSymbolStorageClass ( Scl ) ; OutStreamer -> EmitCOFFSymbolType ( Type ) ;


<s> return __builtin_mve_vrmulhq_m_uv8hi ( __arm_vuninitializedq_u16 ( ) , __a , __b , __p ) ;


<s> else if ( MI -> getOpcode ( ) == <STR_LIT> ) assert ( ( TF == <STR_LIT> || TF == <STR_LIT> || TF == <STR_LIT> ) && <STR_LIT> ) ; else assert ( ( TF == <STR_LIT> || TF == <STR_LIT> || TF == <STR_LIT> || TF == <STR_LIT> ) && <STR_LIT> ) ; } bool CloseParen = true ; switch ( TF ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : CloseParen = false ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <STR_LIT> << StringRef ( getRegisterName ( MO . getReg ( ) ) ) . lower ( ) ; break ; case MachineOperand :: MO_Immediate : O << ( int ) MO . getImm ( ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : O << GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) -> getName ( ) ; break ; case MachineOperand :: MO_ExternalSymbol : O << MO . getSymbolName ( ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << MO . getIndex ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; MachineBasicBlock :: iterator I , Next ; for ( I = MBB . begin ( ) ; I != MBB . end ( ) ; I = Next ) { Next = std :: next ( I ) ; MachineInstr & MI = * I ; if ( MI . getOpcode ( ) == <STR_LIT> ) { unsigned Reg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( Reg ) ; if ( RC == & <STR_LIT> ) MRI . setRegClass ( Reg , & <STR_LIT> ) ; continue ; } if ( MI . getOpcode ( ) != <STR_LIT> ) continue ; const MachineOperand & Dst = MI . getOperand ( <NUM_LIT> ) ; const MachineOperand & Src = MI . getOperand ( <NUM_LIT> ) ; if ( ! TargetRegisterInfo :: isVirtualRegister ( Src . getReg ( ) ) || ! TargetRegisterInfo :: isVirtualRegister ( Dst . getReg ( ) ) ) continue ; const TargetRegisterClass * DstRC = MRI . getRegClass ( Dst . getReg ( ) ) ; const TargetRegisterClass * SrcRC = MRI . getRegClass ( Src . getReg ( ) ) ; if ( DstRC == & <STR_LIT> && TRI -> getCommonSubClass ( SrcRC , & <STR_LIT> ) ) { I1Defs . push_back ( Dst . getReg ( ) ) ; DebugLoc DL = MI . getDebugLoc ( ) ; MachineInstr * DefInst = MRI . getUniqueVRegDef ( Src . getReg ( ) ) ; if ( DefInst -> getOpcode ( ) == <STR_LIT> ) { if ( DefInst -> getOperand ( <NUM_LIT> ) . isImm ( ) ) { I1Defs . push_back ( Dst . getReg ( ) ) ; int64_t Val = DefInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ; assert ( Val == <NUM_LIT> || Val == - <NUM_LIT> ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( Dst ) . addImm ( Val ) ; MI . eraseFromParent ( ) ; continue ; } } BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( Dst ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) . addOperand ( Src ) ;


<s> const TargetRegisterClass * RC = nullptr ; switch ( VT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf32 ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : if ( <ISA_LIT>ScalarSSEf64 ) { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } else { Opc = <STR_LIT> ; RC = & <STR_LIT> ; } break ; case <STR_LIT> : return <NUM_LIT> ; } unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) ; return ResultReg ;


return ( ( vec_double2 ) ( si_fesd ( ( qword ) ( a ) ) ) ) ;


<s> case <NUM_LIT> : return createRegOperand ( TMA_HI ) ; case <NUM_LIT> : return createRegOperand ( M0 ) ; case <NUM_LIT> : return createRegOperand ( SGPR_NULL ) ; case <NUM_LIT> : return createRegOperand ( EXEC_LO ) ; case <NUM_LIT> : return createRegOperand ( EXEC_HI ) ; case <NUM_LIT> : return createRegOperand ( SRC_SHARED_BASE ) ; case <NUM_LIT> : return createRegOperand ( SRC_SHARED_LIMIT ) ; case <NUM_LIT> : return createRegOperand ( SRC_PRIVATE_BASE ) ; case <NUM_LIT> : return createRegOperand ( SRC_PRIVATE_LIMIT ) ; case <NUM_LIT> : return createRegOperand ( SRC_POPS_EXITING_WAVE_ID ) ; case <NUM_LIT> : return createRegOperand ( SRC_VCCZ ) ; case <NUM_LIT> : return createRegOperand ( SRC_EXECZ ) ; case <NUM_LIT> : return createRegOperand ( SRC_SCC ) ;

case <NUM_LIT> : return createRegOperand ( LDS_DIRECT ) ;


<s> void <ISA_LIT>CFGStructurizer :: removeSuccessor ( MachineBasicBlock * MBB ) {

while ( MBB -> succ_size ( ) ) MBB -> removeSuccessor ( * MBB -> succ_begin ( ) ) ;


<s> if ( RelocM == Reloc :: PIC_ || RelocM == Reloc :: DynamicNoPIC ) { const TargetLoweringObjectFileMachO & TLOFMacho = static_cast < const TargetLoweringObjectFileMachO & > ( getObjFileLowering ( ) ) ; SetVector < const MCSection * , SmallVector < const MCSection * , <NUM_LIT> > , SmallPtrSet < const MCSection * , <NUM_LIT> > > TextSections ; TextSections . insert ( TLOFMacho . getTextSection ( ) ) ;

for ( Module :: iterator F = M . begin ( ) , e = M . end ( ) ; F != e ; ++ F ) if ( ! F -> isDeclaration ( ) && ! F -> hasAvailableExternallyLinkage ( ) ) TextSections . insert ( TLOFMacho . SectionForGlobal ( F , Mang , TM ) ) ;


<s> SDValue MulLHS = LHS . getOperand ( <NUM_LIT> ) ; SDValue MulRHS = LHS . getOperand ( <NUM_LIT> ) ; SDValue AddRHS = RHS ; if ( numBitsUnsigned ( MulLHS , DAG ) <= <NUM_LIT> && numBitsUnsigned ( MulRHS , DAG ) <= <NUM_LIT> ) { MulLHS = DAG . getZExtOrTrunc ( MulLHS , SL , <STR_LIT> ) ; MulRHS = DAG . getZExtOrTrunc ( MulRHS , SL , <STR_LIT> ) ; AddRHS = DAG . getZExtOrTrunc ( AddRHS , SL , <STR_LIT> ) ; return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , false ) ; } if ( numBitsSigned ( MulLHS , DAG ) <= <NUM_LIT> && numBitsSigned ( MulRHS , DAG ) <= <NUM_LIT> ) { MulLHS = DAG . getSExtOrTrunc ( MulLHS , SL , <STR_LIT> ) ; MulRHS = DAG . getSExtOrTrunc ( MulRHS , SL , <STR_LIT> ) ; AddRHS = DAG . getSExtOrTrunc ( AddRHS , SL , <STR_LIT> ) ; return getMad64_32 ( DAG , SL , VT , MulLHS , MulRHS , AddRHS , true ) ; } return SDValue ( ) ; } if ( SDValue V = reassociateScalarOps ( N , DAG ) ) { return V ; } if ( VT != <STR_LIT> || ! DCI . isAfterLegalizeDAG ( ) ) return SDValue ( ) ; unsigned Opc = LHS . getOpcode ( ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) std :: swap ( RHS , LHS ) ; Opc = RHS . getOpcode ( ) ; switch ( Opc ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { auto Cond = RHS . getOperand ( <NUM_LIT> ) ; if ( ! isBoolSGPR ( Cond ) ) break ; SDVTList VTList = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Args [ ] = { LHS , DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , Cond } ; Opc = ( Opc == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opc , SL , VTList , Args ) ; } case <STR_LIT> : { auto C = dyn_cast < ConstantSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C || C -> getZExtValue ( ) != <NUM_LIT> ) break ;

SDValue Args [ ] = { LHS , RHS . getOperand ( <NUM_LIT> ) , RHS . getOperand ( <NUM_LIT> ) } ;


<s> if ( UseOp . isReg ( ) && ( ( UseOp . getSubReg ( ) && OpToFold . isReg ( ) ) || UseOp . isImplicit ( ) ) ) { return ; } bool FoldingImm = OpToFold . isImm ( ) ; APInt Imm ; if ( FoldingImm ) { unsigned UseReg = UseOp . getReg ( ) ; const TargetRegisterClass * UseRC = TargetRegisterInfo :: isVirtualRegister ( UseReg ) ? MRI . getRegClass ( UseReg ) : TRI . getPhysRegClass ( UseReg ) ; Imm = APInt ( <NUM_LIT> , OpToFold . getImm ( ) ) ; const MCInstrDesc & FoldDesc = TII -> get ( OpToFold . getParent ( ) -> getOpcode ( ) ) ; const TargetRegisterClass * FoldRC = TRI . getRegClass ( FoldDesc . OpInfo [ <NUM_LIT> ] . RegClass ) ; if ( FoldRC -> getSize ( ) == <NUM_LIT> && UseOp . getSubReg ( ) ) { if ( UseRC -> getSize ( ) != <NUM_LIT> ) return ; if ( UseOp . getSubReg ( ) == <STR_LIT> ) { Imm = Imm . getLoBits ( <NUM_LIT> ) ; } else { assert ( UseOp . getSubReg ( ) == <STR_LIT> ) ; Imm = Imm . getHiBits ( <NUM_LIT> ) ; } } if ( UseMI -> getOpcode ( ) == <STR_LIT> ) { unsigned DestReg = UseMI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * DestRC = TargetRegisterInfo :: isVirtualRegister ( DestReg ) ? MRI . getRegClass ( DestReg ) : TRI . getPhysRegClass ( DestReg ) ; unsigned MovOp = TII -> getMovOpcode ( DestRC ) ; if ( MovOp == <STR_LIT> ) return ; UseMI -> setDesc ( TII -> get ( MovOp ) ) ; CopiesToReplace . push_back ( UseMI ) ; }


<s> static hsa_status_t get_heap_region ( hsa_region_t region , void * data __attribute__ ( ( unused ) ) ) {

return get_memory_region ( region , & heap_region , HSA_REGION_GLOBAL_FLAG_COARSE_GRAINED ) ;


<s> case AMDGPU :: <ISA_LIT>_END_CF : if ( -- Depth == <NUM_LIT> && HaveKill ) { SkipIfDead ( MI ) ; HaveKill = false ; } EndCf ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_KILL : if ( Depth == <NUM_LIT> ) SkipIfDead ( MI ) ; else HaveKill = true ; Kill ( MI ) ; break ; case AMDGPU :: S_BRANCH : Branch ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_INDIRECT_SRC : IndirectSrc ( MI ) ; break ; case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V2 : case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V4 : case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V8 : case AMDGPU :: <ISA_LIT>_INDIRECT_DST_V16 : IndirectDst ( MI ) ; break ; case AMDGPU :: V_INTERP_P1_F32 : case AMDGPU :: V_INTERP_P2_F32 : case AMDGPU :: V_INTERP_MOV_F32 : NeedWQM = true ; break ; } } } if ( NeedWQM ) { MachineBasicBlock & MBB = MF . front ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DebugLoc ( ) , TII -> get ( AMDGPU :: S_WQM_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) ; }


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InChain , Op ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , InChain , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ) ;


<s> unsigned IssueWidth = TSM . getIssueWidth ( ) ; for ( unsigned i = <NUM_LIT> , e = IssueWidth * NOOPsToAdd ; i != e ; ++ i ) BuildMI ( * MBB , MBBI , DL , TSM . getInstrInfo ( ) -> get ( <STR_LIT> ) ) ;


<s> return ( uint8x8_t ) __builtin_neon_vshrn_nv8hi ( ( int16x8_t ) __a , __b ) ;


<s> if ( VT . getSizeInBits ( ) / <NUM_LIT> > LS -> getAlignment ( ) ) { assert ( TLI . allowsUnalignedMemoryAccesses ( VT ) && <STR_LIT> ) ; if ( VT == <STR_LIT> ) return false ; } } if ( FrameIndexSDNode * FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , ValTy ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , ValTy ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { Base = Addr . getOperand ( <NUM_LIT> ) ; Offset = Addr . getOperand ( <NUM_LIT> ) ; return true ; } if ( TM . getRelocationModel ( ) != Reloc :: PIC_ ) { if ( ( Addr . getOpcode ( ) == <STR_LIT> || Addr . getOpcode ( ) == <STR_LIT> ) ) return false ;


<s> static int alpha_set_memflags_1 ( rtx * xp , void * data ) { rtx x = * xp , orig = ( rtx ) data ; if ( GET_CODE ( x ) != MEM ) return <NUM_LIT> ; MEM_VOLATILE_P ( x ) = MEM_VOLATILE_P ( orig ) ; MEM_IN_STRUCT_P ( x ) = MEM_IN_STRUCT_P ( orig ) ; MEM_SCALAR_P ( x ) = MEM_SCALAR_P ( orig ) ;

MEM_NOTRAP_P ( x ) = MEM_NOTRAP_P ( orig ) ;


<s> void <ISA_LIT>TargetStreamer :: emitRawBytes ( StringRef Data ) { MCTargetStreamer :: emitRawBytes ( Data ) ; const MCAsmInfo * MAI = Streamer . getContext ( ) . getAsmInfo ( ) ; const char * Directive = MAI -> getData8bitsDirective ( ) ; unsigned NumElements = Data . size ( ) ; const unsigned MaxLen = <NUM_LIT> ; unsigned NumChunks = <NUM_LIT> + ( ( NumElements - <NUM_LIT> ) / MaxLen ) ; for ( unsigned I = <NUM_LIT> ; I < NumChunks ; ++ I ) { SmallString < <NUM_LIT> > Str ; raw_svector_ostream OS ( Str ) ; const char * Label = Directive ; for ( auto It = std :: next ( Data . bytes_begin ( ) , I * MaxLen ) , End = ( I == NumChunks - <NUM_LIT> ) ? Data . bytes_end ( ) : std :: next ( Data . bytes_begin ( ) , ( I + <NUM_LIT> ) * MaxLen ) ; It != End ; ++ It ) {


<s> case FK_Data_8 : return ( ( Fixup . getOffset ( ) % <NUM_LIT> ) ? ELF :: R_<ISA_LIT>ARC_UA64 : ELF :: R_<ISA_LIT>ARC_64 ) ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_13 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_H44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_M44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_L44 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HH22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_HM10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_GOT22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_GOT10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_GOT13 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_GD_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDM_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDO_HIX22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDO_LOX10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LDO_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_HI22 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_LO10 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_LD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_LDX ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_IE_ADD ; case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LE_HIX22 ;

case <STR_LIT> : return ELF :: R_<ISA_LIT>ARC_TLS_LE_LOX10 ;


<s> emit_block_move ( m_tramp , assemble_trampoline_template ( ) , GEN_INT ( TRAMPOLINE_SIZE ) , BLOCK_OP_NORMAL ) ; mem = adjust_address ( m_tramp , SImode , <NUM_LIT> ) ;


<s> reportParseError ( <STR_LIT> ) ; return false ; } Options . setMacro ( ) ;


<s> void <ISA_LIT>InstrInfo :: insertNoop ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI ) const { unsigned Directive = Subtarget . getCPUDirective ( ) ; unsigned Opcode ; switch ( Directive ) { default : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> return true ; } if ( isa < PointerType > ( Ty ) && AS == <STR_LIT> ) { return false ; } if ( Offs < <NUM_LIT> ) Offs = - Offs ; if ( AM . BaseGV == nullptr && AM . HasBaseReg && AM . Scale == <NUM_LIT> && isUInt < <NUM_LIT> > ( Offs ) ) { return true ; } return false ;


<s> bb . v = ( vec_double2 ) ( b ) ; dd . d [ <NUM_LIT> ] = aa . d [ <NUM_LIT> ] * bb . d [ <NUM_LIT> ] ;


<s> for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { x = XVECEXP ( vals , <NUM_LIT> , i ) ; if ( ! mips_constant_elt_p ( x ) ) nvar ++ , one_var = i ; if ( i > <NUM_LIT> && ! rtx_equal_p ( x , XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ) ) all_same = false ; } if ( ISA_HAS_MSA ) { if ( all_same ) { rtx same = XVECEXP ( vals , <NUM_LIT> , <NUM_LIT> ) ; rtx temp , temp2 ; if ( CONST_INT_P ( same ) && nvar == <NUM_LIT> && mips_signed_immediate_p ( INTVAL ( same ) , <NUM_LIT> , <NUM_LIT> ) ) { switch ( vmode ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : temp = gen_rtx_CONST_VECTOR ( vmode , XVEC ( vals , <NUM_LIT> ) ) ; emit_move_insn ( target , temp ) ; return ; default : gcc_unreachable ( ) ; } } temp = gen_reg_rtx ( imode ) ; if ( imode == GET_MODE ( same ) ) temp2 = same ; else if ( GET_MODE_SIZE ( imode ) >= UNITS_PER_WORD ) temp2 = simplify_gen_subreg ( imode , same , GET_MODE ( same ) , <NUM_LIT> ) ; else temp2 = lowpart_subreg ( imode , same , GET_MODE ( same ) ) ; emit_move_insn ( temp , temp2 ) ; switch ( vmode ) { case V16QImode : case V8HImode : case V4SImode : case V2DImode : mips_emit_move ( target , gen_rtx_VEC_DUPLICATE ( vmode , temp ) ) ; break ; case V4SFmode : emit_insn ( gen_msa_splati_w_f_scalar ( target , temp ) ) ; break ; case V2DFmode : emit_insn ( gen_msa_splati_d_f_scalar ( target , temp ) ) ; break ; default : gcc_unreachable ( ) ; } } else { rtvec vec = shallow_copy_rtvec ( XVEC ( vals , <NUM_LIT> ) ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) RTVEC_ELT ( vec , i ) = CONST0_RTX ( imode ) ; emit_move_insn ( target , gen_rtx_CONST_VECTOR ( vmode , vec ) ) ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) { rtx temp = gen_reg_rtx ( imode ) ; emit_move_insn ( temp , XVECEXP ( vals , <NUM_LIT> , i ) ) ;


<s> if ( GET_CODE ( x ) == LO_SUM && REG_P ( XEXP ( x , <NUM_LIT> ) ) && v850_reg_ok_for_base_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) && CONSTANT_P ( XEXP ( x , <NUM_LIT> ) ) && ( ! CONST_INT_P ( XEXP ( x , <NUM_LIT> ) ) || ( ( mode == QImode || INTVAL ( XEXP ( x , <NUM_LIT> ) ) % <NUM_LIT> == <NUM_LIT> ) && constraint_satisfied_p ( XEXP ( x , <NUM_LIT> ) , CONSTRAINT_K ) ) ) && GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( word_mode ) ) return true ; if ( special_symbolref_operand ( x , mode ) && ( GET_MODE_SIZE ( mode ) <= GET_MODE_SIZE ( word_mode ) ) ) return true ; if ( GET_CODE ( x ) == PLUS && v850_rtx_ok_for_base_p ( XEXP ( x , <NUM_LIT> ) , strict_p ) && ( constraint_satisfied_p ( XEXP ( x , <NUM_LIT> ) , CONSTRAINT_K ) || ( TARGET_V850E2V3_UP && ( mode == SImode || mode == HImode || mode == QImode ) && constraint_satisfied_p ( XEXP ( x , <NUM_LIT> ) , CONSTRAINT_W ) ) ) && ( ( mode == QImode || INTVAL ( XEXP ( x , <NUM_LIT> ) ) % <NUM_LIT> == <NUM_LIT> ) && CONST_OK_FOR_K ( INTVAL ( XEXP ( x , <NUM_LIT> ) ) + ( GET_MODE_NUNITS ( mode ) * UNITS_PER_WORD ) ) ) ) return true ;


<s> int Iters = D -> iterations ( ) ; BasicBlock * BB = PN -> getParent ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * PN << <STR_LIT> ) ; SmallVector < Instruction * , <NUM_LIT> > PNUsers ; for ( auto UI = PN -> use_begin ( ) , E = PN -> use_end ( ) ; UI != E ; ++ UI ) { Use & U = * UI ; Instruction * User = cast < Instruction > ( U . getUser ( ) ) ; if ( User -> getParent ( ) != BB ) continue ; if ( ReplacedInsts . count ( User ) ) { LLVM_DEBUG ( dbgs ( ) << * User << <STR_LIT> ) ; continue ; } if ( isa < PHINode > ( User ) ) continue ; if ( User -> mayHaveSideEffects ( ) ) continue ; if ( ! canReplace ( User ) ) continue ; PNUsers . push_back ( User ) ; } LLVM_DEBUG ( dbgs ( ) << PNUsers . size ( ) << <STR_LIT> ) ; for ( Instruction * I : PNUsers ) { for ( auto UI = BEInst -> use_begin ( ) , E = BEInst -> use_end ( ) ; UI != E ; ++ UI ) { Use & U = * UI ; Instruction * BEUser = cast < Instruction > ( U . getUser ( ) ) ; if ( BEUser -> getParent ( ) != BB ) continue ; if ( ! isEquivalentOperation ( I , BEUser ) ) continue ; int NumOperands = I -> getNumOperands ( ) ; std :: map < Instruction * , DepChain * > DepChains ; CallInst * C1 = dyn_cast < CallInst > ( I ) ; if ( ( I && I -> isCommutative ( ) ) || ( C1 && isCallInstCommutative ( C1 ) ) ) { bool Found = false ; for ( int OpNo = <NUM_LIT> ; OpNo < NumOperands ; ++ OpNo ) { Value * Op = I -> getOperand ( OpNo ) ; Instruction * OpInst = dyn_cast < Instruction > ( Op ) ; Found = false ; for ( int T = <NUM_LIT> ; T < NumOperands ; ++ T ) { Value * BEOp = BEUser -> getOperand ( T ) ; Instruction * BEOpInst = dyn_cast < Instruction > ( BEOp ) ; if ( ! OpInst && ! BEOpInst ) {


<s> EVT VTs [ ] = { Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , <STR_LIT> } ; SDValue CompNode = DAG . getNode ( <STR_LIT> , dl , VTs , Ops , <NUM_LIT> ) ; SDValue Flags = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getRegister ( <STR_LIT> , <STR_LIT> ) , CompNode . getValue ( <NUM_LIT> ) ) ; unsigned BitNo ; bool InvertBit ; switch ( cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ) { default : case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = true ; break ; case <NUM_LIT> : BitNo = <NUM_LIT> ; InvertBit = false ; break ; case <NUM_LIT> :