<s> const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( Subtarget . isSingleFloat ( ) ) return CSR_SingleFloatOnly_RegMask ; if ( Subtarget . isABI_CheriPureCap ( ) ) return CSR_Cheri_Purecap_RegMask ; if ( Subtarget . isCheri ( ) ) return CSR_N64_Cheri_RegMask ; if ( Subtarget . isABI_N64 ( ) ) return CSR_N64_RegMask ; if ( Subtarget . isABI_N32 ( ) ) return CSR_N32_RegMask ; if ( Subtarget . isFP64bit ( ) ) return CSR_O32_FP64_RegMask ; if ( Subtarget . isFPXX ( ) ) return CSR_O32_FPXX_RegMask ; return CSR_O32_RegMask ;


<s> } if ( CmpI -> getOpcode ( ) == <STR_LIT> && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ImmValue ) { IsThumb1 = true ; return true ; } if ( ( CmpI -> getOpcode ( ) == <STR_LIT> || CmpI -> getOpcode ( ) == <STR_LIT> ) && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . isReg ( ) && OI -> getOperand ( <NUM_LIT> ) . isReg ( ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) { IsThumb1 = false ; return true ; } if ( CmpI -> getOpcode ( ) == <STR_LIT> && ( OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> || OI -> getOpcode ( ) == <STR_LIT> ) && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg && OI -> getOperand ( <NUM_LIT> ) . getReg ( ) == SrcReg2 ) { IsThumb1 = true ; return true ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFixedLengthConcatVectorsToSVE ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; unsigned NumOperands = Op -> getNumOperands ( ) ; assert ( NumOperands > <NUM_LIT> && isPowerOf2_32 ( NumOperands ) && <STR_LIT> ) ; auto SrcOp1 = Op . getOperand ( <NUM_LIT> ) ; auto SrcOp2 = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; EVT SrcVT = SrcOp1 . getValueType ( ) ; if ( NumOperands > <NUM_LIT> ) { SmallVector < SDValue , <NUM_LIT> > Ops ; EVT PairVT = SrcVT . getDoubleNumVectorElementsVT ( * DAG . getContext ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < NumOperands ; I += <NUM_LIT> ) Ops . push_back ( DAG . getNode ( <STR_LIT> , DL , PairVT , Op -> getOperand ( I ) , Op -> getOperand ( I + <NUM_LIT> ) ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Ops ) ;


<s> Target & getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;


<s> return ( __m128 ) __builtin_ia32_cvtdq2ps ( ( __v4si ) __A ) ;


<s> const std :: vector < MachineBasicBlock * > & MBBs = I . MBBs ; for ( MachineBasicBlock * MBB : MBBs ) MBB -> setAlignment ( MIPS_NACL_BUNDLE_ALIGN ) ; } }


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( CC == CallingConv :: AnyReg ) { if ( Subtarget . hasVSX ( ) ) return CSR_64_AllRegs_VSX_RegMask ; if ( Subtarget . hasAltivec ( ) ) return CSR_64_AllRegs_Altivec_RegMask ; return CSR_64_AllRegs_RegMask ;


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , const std :: string & CPU , const std :: string & FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , FS ) , HasDistinctOps ( false ) , HasLoadStoreOnCond ( false ) , HasHighWord ( false ) , HasFPExtension ( false ) , HasPopulationCount ( false ) , HasFastSerialization ( false ) , HasInterlockedAccess1 ( false ) , HasMiscellaneousExtensions ( false ) , HasTransactionalExecution ( false ) , HasProcessorAssist ( false ) , HasVector ( false ) , TargetTriple ( TT ) , InstrInfo ( initializeSubtargetDependencies ( CPU , FS ) ) , TLInfo ( TM , * this ) , TSInfo ( ) , FrameLowering ( ) {


<s> else x = gen_pop ( gen_rtx_REG ( SImode , rn ) ) ; x = emit_insn ( x ) ; sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; reg = copy_rtx ( GET_CODE ( PATTERN ( x ) ) == PARALLEL ? SET_DEST ( XVECEXP ( PATTERN ( x ) , <NUM_LIT> , <NUM_LIT> ) ) : SET_DEST ( PATTERN ( x ) ) ) ; add_reg_note ( x , REG_CFA_RESTORE , reg ) ; add_reg_note ( x , REG_CFA_ADJUST_CFA , gen_rtx_SET ( sp_reg , plus_constant ( SImode , sp_reg , GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ; add_reg_note ( x , REG_INC , gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ) ; RTX_FRAME_RELATED_P ( x ) = <NUM_LIT> ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: emitSignExtendToI32InReg ( MachineInstr & MI , MachineBasicBlock * BB , unsigned Size , unsigned DstReg , unsigned SrcReg ) const { const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( Subtarget . has<ISA_LIT>32r2 ( ) && Size == <NUM_LIT> ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return BB ; } if ( Subtarget . has<ISA_LIT>32r2 ( ) && Size == <NUM_LIT> ) { BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( SrcReg ) ; return BB ; } MachineFunction * MF = BB -> getParent ( ) ; MachineRegisterInfo & RegInfo = MF -> getRegInfo ( ) ; const TargetRegisterClass * RC = getRegClassFor ( <STR_LIT> ) ; unsigned ScrReg = RegInfo . createVirtualRegister ( RC ) ; assert ( Size < <NUM_LIT> ) ; int64_t ShiftImm = <NUM_LIT> - ( Size * <NUM_LIT> ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , ScrReg ) . addReg ( SrcReg ) . addImm ( ShiftImm ) ; BuildMI ( BB , DL , TII -> get ( <STR_LIT> ) , DstReg ) . addReg ( ScrReg ) . addImm ( ShiftImm ) ; return BB ;


<s> SDLoc dl ( Op ) ; if ( ST -> getAlignment ( ) == <NUM_LIT> ) { SDValue Low = Value ; SDValue High = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Value , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue StoreLow = DAG . getTruncStore ( Chain , dl , Low , BasePtr , ST -> getPointerInfo ( ) , <STR_LIT> , <NUM_LIT> , ST -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) ; SDValue StoreHigh = DAG . getTruncStore ( Chain , dl , High , HighAddr , ST -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , <STR_LIT> , <NUM_LIT> , ST -> getMemOperand ( ) -> getFlags ( ) ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , StoreLow , StoreHigh ) ; } Type * IntPtrTy = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; Entry . Ty = IntPtrTy ;


<s> RetOps . push_back ( Chain ) ; RetOps . push_back ( DAG . getTargetConstant ( FuncInfo -> getBytesToPopOnReturn ( ) , dl , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = OutVals [ i ] ; EVT ValVT = ValToCopy . getValueType ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) { if ( ValVT . isVector ( ) && ValVT . getVectorElementType ( ) == <STR_LIT> ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getBitcast ( VA . getLocVT ( ) , ValToCopy ) ; assert ( VA . getLocInfo ( ) != CCValAssign :: FPExt && <STR_LIT> ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget . is64Bit ( ) && ! Subtarget . hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget . is64Bit ( ) && ! Subtarget . hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget . is64Bit ( ) ) {


<s> <ISA_LIT>GOTPLT :: ~ <ISA_LIT>GOTPLT ( ) {


<s> if ( Src . getValueType ( ) . getScalarSizeInBits ( ) < <NUM_LIT> ) Src = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Src . getValueType ( ) ) ) return SDValue ( ) ; if ( Src . getValueType ( ) == <STR_LIT> && DAG . MaskedValueIsZero ( BitNo , APInt ( BitNo . getValueSizeInBits ( ) , <NUM_LIT> ) ) ) Src = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; if ( Src . getValueType ( ) != BitNo . getValueType ( ) ) { if ( BitNo . getOpcode ( ) == <STR_LIT> && BitNo -> hasOneUse ( ) ) BitNo = DAG . getNode ( <STR_LIT> , DL , Src . getValueType ( ) , DAG . getNode ( <STR_LIT> , DL , Src . getValueType ( ) , BitNo . getOperand ( <NUM_LIT> ) ) , DAG . getNode ( <STR_LIT> , DL , Src . getValueType ( ) , BitNo . getOperand ( <NUM_LIT> ) ) ) ; else BitNo = DAG . getNode ( <STR_LIT> , DL , Src . getValueType ( ) , BitNo ) ; }

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , BitNo ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitParam ( ArrayRef < MVT > Types ) {


<s> return DAG . getBuildVector ( <STR_LIT> , SDLoc ( N ) , { BVN -> getOperand ( LowElt ) , BVN -> getOperand ( LowElt + <NUM_LIT> ) } ) ; } assert ( N -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; unsigned EltSize = VT . getScalarSizeInBits ( ) / <NUM_LIT> ; unsigned NumElts = VT . getVectorNumElements ( ) ; MVT TruncVT = <STR_LIT> ( EltSize ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; SDLoc dl ( N ) ; for ( unsigned i = <NUM_LIT> ; i != NumElts ; ++ i ) { ConstantSDNode * C = cast < ConstantSDNode > ( N -> getOperand ( i ) ) ; const APInt & CInt = C -> getAPIntValue ( ) ; Ops . push_back ( DAG . getConstant ( CInt . zextOrTrunc ( <NUM_LIT> ) , dl , <STR_LIT> ) ) ; }

return DAG . getBuildVector ( <STR_LIT> ( TruncVT , NumElts ) , dl , Ops ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const TargetInstrInfo & tii ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> , <STR_LIT> ) , TII ( tii ) {


<s> MachineBasicBlock :: iterator Loc = MemOps [ SIndex ] . MBBI ; DebugLoc dl = Loc -> getDebugLoc ( ) ; const MachineOperand & PMO = Loc -> getOperand ( <NUM_LIT> ) ; unsigned PReg = PMO . getReg ( ) ; unsigned PRegNum = PMO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( PReg ) ; unsigned Count = <NUM_LIT> ; unsigned Limit = ~ <NUM_LIT> ; switch ( Opcode ) { default : break ; case <STR_LIT> : Limit = <NUM_LIT> ; break ; case <STR_LIT> : Limit = <NUM_LIT> ; break ; case <STR_LIT> : Limit = <NUM_LIT> ; break ; case <STR_LIT> : Limit = <NUM_LIT> ; break ; } for ( unsigned i = SIndex + <NUM_LIT> , e = MemOps . size ( ) ; i != e ; ++ i ) { int NewOffset = MemOps [ i ] . Offset ; const MachineOperand & MO = MemOps [ i ] . MBBI -> getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; unsigned RegNum = MO . isUndef ( ) ? UINT_MAX : TRI -> getEncodingValue ( Reg ) ; if ( Reg != <STR_LIT> && NewOffset == Offset + ( int ) Size && ( ( isNotVFP && RegNum > PRegNum ) || ( ( Count < Limit ) && RegNum == PRegNum + <NUM_LIT> ) ) ) { Offset += Size ; PRegNum = RegNum ; ++ Count ; } else { MergeOpsUpdate ( MBB , MemOps , SIndex , i , insertAfter , SOffset , Base , false , Opcode , Pred , PredReg , Scratch , dl , Merges ) ; MergeLDR_STR ( MBB , i , Base , Opcode , Size , Pred , PredReg , Scratch , MemOps , Merges ) ; return ; } if ( MemOps [ i ] . Position > MemOps [ insertAfter ] . Position ) insertAfter = i ; } bool BaseKill = Loc -> findRegisterUseOperandIdx ( Base , true ) != - <NUM_LIT> ; MergeOpsUpdate ( MBB , MemOps , SIndex , MemOps . size ( ) , insertAfter , SOffset , Base , BaseKill , Opcode , Pred , PredReg , Scratch , dl , Merges ) ;


<s> static const char * rs6000_mangle_type ( const_tree type ) { type = TYPE_MAIN_VARIANT ( type ) ; if ( TREE_CODE ( type ) != VOID_TYPE && TREE_CODE ( type ) != BOOLEAN_TYPE && TREE_CODE ( type ) != INTEGER_TYPE && TREE_CODE ( type ) != REAL_TYPE ) return NULL ; if ( type == bool_char_type_node ) return <STR_LIT> ; if ( type == bool_short_type_node ) return <STR_LIT> ; if ( type == pixel_type_node ) return <STR_LIT> ;

if ( type == bool_int_type_node ) return <STR_LIT> ;


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> UsedRegs [ Reg / <NUM_LIT> ] |= <NUM_LIT> << ( Reg & <NUM_LIT> ) ;

if ( const unsigned * RegAliases = TRI . getAliasSet ( Reg ) ) for ( ; ( Reg = * RegAliases ) ; ++ RegAliases ) UsedRegs [ Reg / <NUM_LIT> ] |= <NUM_LIT> << ( Reg & <NUM_LIT> ) ;


<s> void LLVMInitialize<ISA_LIT>AsmPrinter ( ) {

RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( The<ISA_LIT>Target ) ;


<s> static bool CC_<ISA_LIT>_APCS_Custom_f64 ( unsigned ValNo , MVT ValVT , MVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , CCState & State ) { if ( ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo , State , true ) ) return false ; if ( LocVT == <STR_LIT> && ! f64AssignAPCS ( ValNo , ValVT , LocVT , LocInfo , State , false ) ) return false ;


<s> V1 = Extract128BitVector ( V1 , EltNo , DAG , dl ) ; if ( EltNo >= NumElems / <NUM_LIT> ) EltNo -= NumElems / <NUM_LIT> ; } EVT EltVT = SrcVT . getVectorElementType ( ) ; if ( EltVT == <STR_LIT> || EltVT == <STR_LIT> ) V1 = PromoteSplati8i16 ( V1 , DAG , EltNo ) ; if ( Is256BitVec ) {

V1 = DAG . getNode ( <STR_LIT> , dl , SrcVT , V1 , V1 ) ;


<s> OS << <STR_LIT> << Reg << <STR_LIT> ;


<s> if ( ! Shift ) return false ; uint64_t Amount = Shift -> getZExtValue ( ) ; if ( Amount >= N . getValueType ( ) . getSizeInBits ( ) ) return false ; ShiftVal = Amount ;


<s> return <STR_LIT> ; } } return TranslateInteger<ISA_LIT>CC ( SetCCOpcode ) ; } if ( <STR_LIT> ( LHS . getNode ( ) ) && ! <STR_LIT> ( RHS . getNode ( ) ) ) { SetCCOpcode = getSetCCSwappedOperands ( SetCCOpcode ) ; std :: swap ( LHS , RHS ) ; } switch ( SetCCOpcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : std :: swap ( LHS , RHS ) ; break ; } switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; }


<s> Op -> Memory . BaseRegNum = BaseRegNum ; Op -> Memory . OffsetImm = OffsetImm ; Op -> Memory . OffsetRegNum = OffsetRegNum ; Op -> Memory . ShiftType = ShiftType ; Op -> Memory . ShiftImm = ShiftImm ; Op -> Memory . Alignment = Alignment ; Op -> Memory . isNegative = isNegative ; Op -> StartLoc = S ; Op -> EndLoc = E ; Op -> AlignmentLoc = AlignmentLoc ; return Op ;


<s> FunctionPass * llvm :: create<ISA_LIT>TOCRegDepsPass ( ) {


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : Invert = true ; return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : Invert = true ; return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : Invert = true ; return <NUM_LIT> ; case <STR_LIT> : Invert = true ; return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerSELECT ( Op , DAG ) ; case <STR_LIT> : return lowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return lowerEXTRACT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return lowerVASTART ( Op , DAG ) ; case <STR_LIT> : return lowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return lowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return lowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , true ) ; case <STR_LIT> : return lowerShiftRightParts ( Op , DAG , false ) ; case <STR_LIT> : { assert ( Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( Op ) ; SDValue Op0 = Op . getOperand ( <NUM_LIT> ) ; if ( Op . getValueType ( ) != <STR_LIT> || Op0 . getValueType ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue NewOp0 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewOp0 ) ; return FPConv ; } }


<s> ConcreteRegion ( const T * Region ) : Region ( Region ) {


<s> static void adjustICmpTruncate ( SelectionDAG & DAG , const SDLoc & DL , Comparison & C ) { if ( C . Op0 . getOpcode ( ) == <STR_LIT> && C . Op0 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && C . Op1 . getOpcode ( ) == <STR_LIT> && cast < ConstantSDNode > ( C . Op1 ) -> getZExtValue ( ) == <NUM_LIT> ) { auto * L = cast < LoadSDNode > ( C . Op0 . getOperand ( <NUM_LIT> ) ) ; if ( L -> getMemoryVT ( ) . getStoreSizeInBits ( ) <= C . Op0 . getValueSizeInBits ( ) ) { unsigned Type = L -> getExtensionType ( ) ; if ( ( Type == <STR_LIT> && C . ICmpType != <STR_LIT> ) || ( Type == <STR_LIT> && C . ICmpType != <STR_LIT> ) ) { C . Op0 = C . Op0 . getOperand ( <NUM_LIT> ) ;

C . Op1 = DAG . getConstant ( <NUM_LIT> , DL , C . Op0 . getValueType ( ) ) ;


<s> DEBUG ( dbgs ( ) << <STR_LIT> ; Tmp -> dump ( ) ; ) ; ( void ) Tmp ; SrcVec = DstReg ; } Pos = BuildMI ( MBB , Pos , DL , TII -> get ( AMDGPU :: COPY ) , Reg ) . addReg ( SrcVec ) ; DEBUG ( dbgs ( ) << <STR_LIT> ; Pos -> dump ( ) ; ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; for ( MachineRegisterInfo :: use_iterator It = MRI -> use_begin ( Reg ) , E = MRI -> use_end ( ) ; It != E ; ++ It ) { DEBUG ( dbgs ( ) << <STR_LIT> ; ( * It ) . dump ( ) ; dbgs ( ) << <STR_LIT> ) ; SwizzleInput ( * It , RemapChan ) ; DEBUG ( ( * It ) . dump ( ) ) ; } R<ISA_LIT> -> Instr -> eraseFromParent ( ) ; R<ISA_LIT> -> Instr = Pos ; R<ISA_LIT> -> RegToChan = UpdatedRegToChan ; R<ISA_LIT> -> UndefReg = UpdatedUndef ; return Pos ;


<s> void <ISA_LIT>InstrInfo :: buildOutlinedFrame ( MachineBasicBlock & MBB , MachineFunction & MF , const outliner :: OutlinedFunction & OF ) const { if ( OF . FrameConstructionID == MachineOutlinerTailCall ) return ; MachineInstr * retq = BuildMI ( MF , DebugLoc ( ) , get ( <STR_LIT> ) ) ;


<s> return gen_rtx_SET ( VOIDmode , dest , GEN_INT ( val & ~ ( HOST_WIDE_INT ) <NUM_LIT> ) ) ;


<s> void <ISA_LIT>InstrInfo :: insertOutlinerPrologue ( MachineBasicBlock & MBB , MachineFunction & MF , const MachineOutlinerInfo & MInfo ) const {


<s> PB . registerLoopOptimizerEndEPCallback ( [ = ] ( LoopPassManager & LPM , OptimizationLevel Level ) { LPM . addPass ( <ISA_LIT>VectorLoopCarriedReusePass ( ) ) ;


<s> HiPart = DAG . getNode ( <STR_LIT> , dl , VTs , Ops , <NUM_LIT> ) ; } else HiPart = DAG . getLoad ( <STR_LIT> , dl , DAG . getEntryNode ( ) , JTI , NULL , <NUM_LIT> ) ; SDValue Lo = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , JTI ) ; ResNode = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , HiPart , Lo ) ; return ResNode ;


<s> if ( Tok . isNot ( AsmToken :: Identifier ) ) return TokError ( <STR_LIT> ) ; StringRef SymbolName = Tok . getIdentifier ( ) ; MCSymbol * Sym = getContext ( ) . lookupSymbol ( SymbolName ) ; if ( ! Sym ) return TokError ( <STR_LIT> ) ; Parser . Lex ( ) ; if ( parseToken ( AsmToken :: EndOfStatement ) ) return addErrorSuffix ( <STR_LIT> ) ; getTargetStreamer ( ) . emitDirectiveVariantPCS ( Sym ) ; return false ;


<s> static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; __v4sf a , b , c ; a = vec_splat ( ( __v4sf ) __A , <NUM_LIT> ) ; b = vec_splat ( ( __v4sf ) __B , <NUM_LIT> ) ;


<s> for ( unsigned Pos = <NUM_LIT> , e = NumTZ ; Pos > e ; -- Pos ) { bool T = ( ( Mask >> Pos ) & <NUM_LIT> ) == CondBit0 ; if ( T ) O << 't' ;


<s> bool parsePrimaryExpr ( const MCExpr * & Res , SMLoc & EndLoc ) override {

return MCTargetAsmParser :: parsePrimaryExpr ( Res , EndLoc ) ;


<s> PM -> add ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) , getOptLevel ( ) ) ) ; return false ;


<s> CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) if ( ! ArgLocs [ i ] . isRegLoc ( ) ) return false ; } bool Unused = false ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; ++ i ) { if ( ! Ins [ i ] . Used ) { Unused = true ; break ; } } if ( Unused ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) return false ; } } if ( ! CCMatch ) { SmallVector < CCValAssign , <NUM_LIT> > RVLocs1 ; CCState CCInfo1 ( CalleeCC , false , DAG . getMachineFunction ( ) , RVLocs1 , * DAG . getContext ( ) ) ; CCInfo1 . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs2 ; CCState CCInfo2 ( CallerCC , false , DAG . getMachineFunction ( ) , RVLocs2 , * DAG . getContext ( ) ) ; CCInfo2 . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; if ( RVLocs1 . size ( ) != RVLocs2 . size ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = RVLocs1 . size ( ) ; i != e ; ++ i ) { if ( RVLocs1 [ i ] . isRegLoc ( ) != RVLocs2 [ i ] . isRegLoc ( ) ) return false ; if ( RVLocs1 [ i ] . getLocInfo ( ) != RVLocs2 [ i ] . getLocInfo ( ) ) return false ; if ( RVLocs1 [ i ] . isRegLoc ( ) ) { if ( RVLocs1 [ i ] . getLocReg ( ) != RVLocs2 [ i ] . getLocReg ( ) ) return false ; } else { if ( RVLocs1 [ i ] . getLocMemOffset ( ) != RVLocs2 [ i ] . getLocMemOffset ( ) ) return false ; } } } if ( ! Outs . empty ( ) ) {

SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i , ++ FuncArg ) { EVT VT = Ins [ i ] . VT ; Type * ArgType = FuncArg -> getType ( ) ; unsigned ArgSizeInBits = ArgType -> isPointerTy ( ) ? <NUM_LIT> : ArgType -> getPrimitiveSizeInBits ( ) ; unsigned ArgBytes = ArgSizeInBits >> <NUM_LIT> ; EVT ArgVT ;

if ( ArgSizeInBits < VT . getSizeInBits ( ) ) {


<s> SDNode * <ISA_LIT>TargetLowering :: PostISelFolding ( MachineSDNode * Node , SelectionDAG & DAG ) const { const <ISA_LIT>InstrInfo * TII = getSubtarget ( ) -> getInstrInfo ( ) ; unsigned Opcode = Node -> getMachineOpcode ( ) ; if ( TII -> isMIMG ( Opcode ) && ! TII -> get ( Opcode ) . mayStore ( ) && ! TII -> isGather4 ( Opcode ) ) { return adjustWritemask ( Node , DAG ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { legalizeTargetIndependentNode ( Node , DAG ) ; return Node ; } switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : { SDValue Src0 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src1 = Node -> getOperand ( <NUM_LIT> ) ; SDValue Src2 = Node -> getOperand ( <NUM_LIT> ) ; if ( ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) != <STR_LIT> ) && ( Src0 == Src1 || Src0 == Src2 ) ) break ; MVT VT = Src0 . getValueType ( ) . getSimpleVT ( ) ; const TargetRegisterClass * RC = getRegClassFor ( VT ) ; MachineRegisterInfo & MRI = DAG . getMachineFunction ( ) . getRegInfo ( ) ; SDValue UndefReg = DAG . getRegister ( MRI . createVirtualRegister ( RC ) , VT ) ; SDValue ImpDef = DAG . getCopyToReg ( DAG . getEntryNode ( ) , SDLoc ( Node ) , UndefReg , Src0 , SDValue ( ) ) ; if ( Src0 . isMachineOpcode ( ) && Src0 . getMachineOpcode ( ) == <STR_LIT> ) { if ( Src1 . isMachineOpcode ( ) && Src1 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src1 ; else if ( Src2 . isMachineOpcode ( ) && Src2 . getMachineOpcode ( ) != <STR_LIT> ) Src0 = Src2 ; else { assert ( Src1 . getMachineOpcode ( ) == <STR_LIT> ) ; Src0 = UndefReg ; Src1 = UndefReg ; } } else break ; SmallVector < SDValue , <NUM_LIT> > Ops = { Src0 , Src1 , Src2 } ; for ( unsigned I = <NUM_LIT> , N = Node -> getNumOperands ( ) ; I != N ; ++ I ) Ops . push_back ( Node -> getOperand ( I ) ) ;

Ops . push_back ( ImpDef . getValue ( <NUM_LIT> ) ) ;


<s> } return SDValue ( ) ; } if ( InVT == <STR_LIT> && N0 . getOpcode ( ) == <STR_LIT> && isAllOnesConstant ( N0 . getOperand ( <NUM_LIT> ) ) && N0 . hasOneUse ( ) ) { SDValue Zext = DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Zext , DAG . getConstant ( <NUM_LIT> , DL , VT ) ) ; } if ( SDValue V = combineToExtendVectorInReg ( N , DAG , DCI , Subtarget ) ) return V ;

if ( Subtarget . hasAVX ( ) && VT . is256BitVector ( ) ) if ( SDValue R = WidenMaskArithmetic ( N , DAG , DCI , Subtarget ) ) return R ;


<s> static int write_header_file ( void ) { write_autogenerated_header ( header_file ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ; write_decls ( ) ; fprintf ( header_file , <STR_LIT> ) ; fprintf ( header_file , <STR_LIT> ) ;


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { switch ( Kind ) { case CEK_None : case CEK_Special : llvm_unreachable ( <STR_LIT> ) ; break ; case CEK_ABS_HI : OS << <STR_LIT> ;


<s> long __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _pdep_u64 ( unsigned long long __X , unsigned long long __Y ) {


<s> DiagnosticPredicate isUImmScaled ( ) const {

return isImmScaled < Bits , Scale > ( false ) ;


<s> static inline SDValue getPTrue ( SelectionDAG & DAG , SDLoc DL , EVT VT , <STR_LIT> Pattern ) {

return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( Pattern , DL , <STR_LIT> ) ) ;


<s> if ( LoadVT . isVector ( ) ) { if ( Unpacked ) { EquivLoadVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , LoadVT . getVectorNumElements ( ) ) ; } else if ( ( LoadVT . getVectorNumElements ( ) % <NUM_LIT> ) == <NUM_LIT> ) { EquivLoadVT = EVT :: getVectorVT ( * DAG . getContext ( ) , LoadVT . getVectorElementType ( ) , LoadVT . getVectorNumElements ( ) + <NUM_LIT> ) ; }


<s> std :: string HSAMetadataString ; raw_string_ostream StrOS ( HSAMetadataString ) ; yaml :: Output YOut ( StrOS ) ; YOut << HSAMetadataRoot ; if ( DumpHSAMetadata ) dump ( StrOS . str ( ) ) ; if ( VerifyHSAMetadata ) verify ( StrOS . str ( ) ) ;


<s> if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! isN64 ( ) ) return getAddrNonPIC ( N , Ty , DAG ) ;

return getAddrLocal ( N , Ty , DAG , isN32 ( ) || isN64 ( ) ) ;


<s> case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_LO : case MCSymbolRefExpr :: VK_<ISA_LIT>_ABS_HI : case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHER : case MCSymbolRefExpr :: VK_<ISA_LIT>_HIGHEST : break ; default : return false ; } if ( isa < MCBinaryExpr > ( BE -> getLHS ( ) ) ) {

if ( ! isa < MCConstantExpr > ( BE -> getRHS ( ) ) ) return false ;


<s> if ( ! TREE_CONSTANT ( decl ) ) readonly = <NUM_LIT> ; break ; default : break ; } if ( TREE_CODE ( decl ) == FUNCTION_DECL ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( name [ <NUM_LIT> ] == '@' && name [ <NUM_LIT> ] == '.' ) encoding = name [ <NUM_LIT> ] ; else encoding = <NUM_LIT> ; if ( flag_function_sections || DECL_COMDAT_GROUP ( decl ) ) mep_unique_section ( decl , <NUM_LIT> ) ; else if ( lookup_attribute ( <STR_LIT> , TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ) ) { if ( encoding == 'f' ) return vftext_section ; else return vtext_section ; } else if ( encoding == 'f' ) return ftext_section ; else return text_section ; } if ( TREE_CODE ( decl ) == VAR_DECL ) { const char * name = XSTR ( XEXP ( DECL_RTL ( decl ) , <NUM_LIT> ) , <NUM_LIT> ) ; if ( name [ <NUM_LIT> ] == '@' && name [ <NUM_LIT> ] == '.' ) switch ( name [ <NUM_LIT> ] ) { case 'b' : return based_section ; case 't' : if ( readonly ) return srodata_section ; if ( DECL_INITIAL ( decl ) ) return sdata_section ; return tinybss_section ; case 'f' : if ( readonly ) return frodata_section ; return far_section ; case 'i' : case 'I' :

error_at ( DECL_SOURCE_LOCATION ( decl ) , <STR_LIT> , decl ) ;


<s> return ( cond == EQ || cond == NE ) ;


<s> if ( MO . isReg ( ) || MO . isImm ( ) ) return getMachineOpValue ( MI , MO , Fixups , STI ) ;

Fixups . push_back ( MCFixup :: Create ( <NUM_LIT> , MO . getExpr ( ) , ( MCFixupKind ) <STR_LIT> ) ) ;


return __builtin_ia32_ps512_256ps ( __A ) ;


<s> return RegIdx . RegInfo -> getRegClass ( ClassID ) . getRegister ( RegIdx . Index ) ;


<s> static inline uint64_t decodeAdvSIMDModImmType7 ( uint8_t Imm ) {


<s> if ( ! force && R -> MaxPressure . less ( ST , MaxPressure , TgtOcc ) ) break ; BuildDAG DAG ( * R , * this ) ; const auto MinSchedule = makeMinRegSchedule ( DAG . getTopRoots ( ) , * this ) ; const auto RP = getSchedulePressure ( * R , MinSchedule ) ; LLVM_DEBUG ( if ( R -> MaxPressure . less ( ST , RP , TgtOcc ) ) { dbgs ( ) << <STR_LIT> ; printSchedRP ( dbgs ( ) , R -> MaxPressure , RP ) ; } ) ;

if ( ! force && MaxPressure . less ( ST , RP , TgtOcc ) ) break ;


<s> if ( m_pEXIDX != NULL && m_pEXIDX -> size ( ) != <NUM_LIT> ) { FragmentRef * exidx_start = FragmentRef :: Create ( m_pEXIDX -> getSectionData ( ) -> front ( ) , <NUM_LIT> ) ; FragmentRef * exidx_end = FragmentRef :: Create ( m_pEXIDX -> getSectionData ( ) -> front ( ) , m_pEXIDX -> size ( ) ) ; m_pEXIDXStart = pBuilder . AddSymbol < IRBuilder :: AsReferred , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , exidx_start , ResolveInfo :: Default ) ; m_pEXIDXEnd = pBuilder . AddSymbol < IRBuilder :: AsReferred , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: Object , ResolveInfo :: Define , ResolveInfo :: Local , <NUM_LIT> , <NUM_LIT> , exidx_end , ResolveInfo :: Default ) ; if ( m_pEXIDXStart != NULL ) pModule . getSymbolTable ( ) . changeToDynamic ( * m_pEXIDXStart ) ; if ( m_pEXIDXEnd != NULL ) pModule . getSymbolTable ( ) . changeToDynamic ( * m_pEXIDXEnd ) ; } else { m_pEXIDXStart = pBuilder . AddSymbol < IRBuilder :: AsReferred , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: NoType , ResolveInfo :: Define , ResolveInfo :: Absolute , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Null ( ) , ResolveInfo :: Default ) ; m_pEXIDXEnd = pBuilder . AddSymbol < IRBuilder :: AsReferred , IRBuilder :: Resolve > ( <STR_LIT> , ResolveInfo :: NoType , ResolveInfo :: Define , ResolveInfo :: Absolute , <NUM_LIT> , <NUM_LIT> , FragmentRef :: Null ( ) , ResolveInfo :: Default ) ; }


<s> static bool tilepro_legitimate_constant_p ( machine_mode mode ATTRIBUTE_UNUSED , rtx x ) { switch ( GET_CODE ( x ) ) { case CONST : case SYMBOL_REF : return ! tilepro_tls_referenced_p ( x ) ; default :


<s> SMShadowTracker . emitShadowPadding ( OutStreamer , getSubtargetInfo ( ) ) ; SM . recordStackMap ( MI ) ; unsigned NumShadowBytes = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;

SMShadowTracker . reset ( NumShadowBytes ) ;


<s> static inline bool offset_below_red_zone_p ( HOST_WIDE_INT offset ) { return offset < ( DEFAULT_ABI == ABI_V4 ? <NUM_LIT> : TARGET_32BIT ? - <NUM_LIT> : - <NUM_LIT> ) ;


<s> const char * getPassName ( ) const override { return <STR_LIT> ;


<s> } if ( isInt < <NUM_LIT> > ( ImmValue ) ) { TOut . emitRRI ( OpImmCode , DstReg , SrcReg , ImmValue , IDLoc , STI ) ; TOut . emitRRI ( <STR_LIT> , DstReg , DstReg , <NUM_LIT> , IDLoc , STI ) ; } else { unsigned ImmReg = DstReg ; if ( DstReg == SrcReg ) { unsigned ATReg = getATReg ( Inst . getLoc ( ) ) ; if ( ! ATReg ) return true ; ImmReg = ATReg ; }

if ( loadImmediate ( ImmValue , ImmReg , <STR_LIT> , isInt < <NUM_LIT> > ( ImmValue ) , false , IDLoc , Out , STI ) ) return true ;


<s> Index = VPGN -> getIndex ( ) ; Mask = VPGN -> getMask ( ) ; PassThru = DAG . getUNDEF ( VT ) ; VL = VPGN -> getVectorLength ( ) ; LoadExtType = <STR_LIT> ; } else { auto * MGN = cast < MaskedGatherSDNode > ( Op . getNode ( ) ) ; Index = MGN -> getIndex ( ) ; Mask = MGN -> getMask ( ) ; PassThru = MGN -> getPassThru ( ) ; LoadExtType = MGN -> getExtensionType ( ) ; } MVT IndexVT = Index . getSimpleValueType ( ) ; MVT XLenVT = Subtarget . getXLenVT ( ) ; assert ( VT . getVectorElementCount ( ) == IndexVT . getVectorElementCount ( ) && <STR_LIT> ) ; assert ( BasePtr . getSimpleValueType ( ) == XLenVT && <STR_LIT> ) ; assert ( LoadExtType == <STR_LIT> && <STR_LIT> ) ; ( void ) LoadExtType ; bool IsUnmasked = <STR_LIT> ( Mask . getNode ( ) ) ; MVT ContainerVT = VT ; if ( VT . isFixedLengthVector ( ) ) { ContainerVT = getContainerForFixedLengthVector ( VT ) ; IndexVT = <STR_LIT> ( IndexVT . getVectorElementType ( ) , ContainerVT . getVectorElementCount ( ) ) ; Index = convertToScalableVector ( IndexVT , Index , DAG , Subtarget ) ; if ( ! IsUnmasked ) { MVT MaskVT = getMaskTypeFor ( ContainerVT ) ;

Mask = convertToScalableVector ( MaskVT , Mask , DAG , Subtarget ) ;


<s> SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue TargetCC ; SDValue Flag = EmitCMP ( LHS , RHS , CC , dl , DAG , TargetCC ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { LHS , RHS , TargetCC , Flag } ; return DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ;


<s> for ( seq = cfun -> emit -> sequence_stack ; seq ; insn = seq -> first , seq = seq -> next ) ; while ( insn ) { if ( reg_mentioned_p ( sp , insn ) ) return true ; if ( reg_mentioned_p ( fb , insn ) ) return true ;


<s> bool <ISA_LIT>TargetLowering :: isFPImmLegal ( const APFloat & Imm , EVT VT ) const { if ( VT != <STR_LIT> && VT != <STR_LIT> ) return false ;


<s> case CCValAssign :: AExt : { bool Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; if ( ! Emitted ) Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; if ( ! Emitted ) Emitted = FastEmitExtend ( <STR_LIT> , VA . getLocVT ( ) , Arg , ArgVT , Arg ) ; assert ( Emitted && <STR_LIT> ) ; ( void ) Emitted ; ArgVT = VA . getLocVT ( ) ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; } default : llvm_unreachable ( <STR_LIT> ) ; } if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( TargetOpcode :: COPY ) , VA . getLocReg ( ) ) . addReg ( Arg ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT> ) return false ; CCValAssign & NextVA = ArgLocs [ ++ i ] ; if ( ! ( VA . isRegLoc ( ) && NextVA . isRegLoc ( ) ) ) return false ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( <STR_LIT> ) , VA . getLocReg ( ) ) . addReg ( NextVA . getLocReg ( ) , RegState :: Define ) . addReg ( Arg ) ) ; RegArgs . push_back ( VA . getLocReg ( ) ) ; RegArgs . push_back ( NextVA . getLocReg ( ) ) ; } else { assert ( VA . isMemLoc ( ) ) ;


<s> void ValueEnumerator :: dropFunctionFromMetadata ( MetadataMapType :: value_type & FirstMD ) { SmallVector < const MDNode * , <NUM_LIT> > Worklist ; auto push = [ & Worklist ] ( MetadataMapType :: value_type & MD ) { auto & Entry = MD . second ; if ( ! Entry . F ) return ;


<s> if ( VT . getSizeInBits ( ) != N -> getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) ) return SDValue ( ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; if ( Subtarget -> hasNEON ( ) && <STR_LIT> ( N0 . getNode ( ) ) && N0 . hasOneUse ( ) && ! cast < LoadSDNode > ( N0 ) -> isVolatile ( ) ) { LoadSDNode * LN0 = cast < LoadSDNode > ( N0 ) ; SDValue Load = DAG . getLoad ( VT , SDLoc ( N ) , LN0 -> getChain ( ) , LN0 -> getBasePtr ( ) , LN0 -> getPointerInfo ( ) , LN0 -> getAlignment ( ) , LN0 -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LN0 , <NUM_LIT> ) , Load . getValue ( <NUM_LIT> ) ) ; unsigned Opcode = ( N -> getOpcode ( ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( Opcode , SDLoc ( N ) , VT , Load ) ; } return SDValue ( ) ;


<s> void GCNUpwardRPTracker :: reset ( const MachineInstr & MI ) { MRI = & MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; LiveRegs = getLiveRegsAfter ( MI , LIS ) ;

MaxPressure = CurPressure = getRegPressure ( * MRI , LiveRegs ) ;


<s> } if ( ImageStore && Subtarget -> hasImageStoreD16Bug ( ) ) { EVT IntStoreVT = StoreVT . changeTypeToInteger ( ) ; SDValue IntVData = DAG . getNode ( <STR_LIT> , DL , IntStoreVT , VData ) ; SmallVector < SDValue , <NUM_LIT> > Elts ; DAG . ExtractVectorElements ( IntVData , Elts ) ; SmallVector < SDValue , <NUM_LIT> > PackedElts ; for ( unsigned I = <NUM_LIT> ; I < Elts . size ( ) / <NUM_LIT> ; I += <NUM_LIT> ) { SDValue Pair = DAG . getBuildVector ( <STR_LIT> , DL , { Elts [ I * <NUM_LIT> ] , Elts [ I * <NUM_LIT> + <NUM_LIT> ] } ) ; SDValue IntPair = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Pair ) ; PackedElts . push_back ( IntPair ) ; } PackedElts . resize ( PackedElts . size ( ) * <NUM_LIT> , DAG . getUNDEF ( <STR_LIT> ) ) ;

EVT VecVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , PackedElts . size ( ) ) ;


<s> EVT Ty = Op . getValueType ( ) ; return getAddr ( N , Ty , DAG , true , true ) ;


<s> MemoryBound = MemBoundAttr . getValueAsBool ( ) ; Attribute WaveLimitAttr = F . getFnAttribute ( <STR_LIT> ) ; WaveLimiter = WaveLimitAttr . getValueAsBool ( ) ; CallingConv :: ID CC = F . getCallingConv ( ) ;

if ( CC == CallingConv :: <ISA_LIT>_KERNEL || CC == CallingConv :: SPIR_KERNEL ) ExplicitKernArgSize = ST . getExplicitKernArgSize ( F , MaxKernArgAlign ) ;


<s> TC . endOfFunction ( ErrorLoc ) ; if ( ! LastFunctionLabel ) return ; auto TempSym = getContext ( ) . createLinkerPrivateTempSymbol ( ) ; getStreamer ( ) . emitLabel ( TempSym ) ;

auto Start = MCSymbolRefExpr :: create ( LastFunctionLabel , getContext ( ) ) ;


<s> <ISA_LIT>MachineCFGStructurizer :: PathToKind <ISA_LIT>MachineCFGStructurizer :: singlePathTo ( MachineBasicBlock * SrcMBB , MachineBasicBlock * DstMBB , bool AllowSideEntry ) const { assert ( DstMBB ) ; if ( SrcMBB == DstMBB ) return SinglePath_InPath ; while ( SrcMBB && SrcMBB -> succ_size ( ) == <NUM_LIT> ) { SrcMBB = * SrcMBB -> succ_begin ( ) ; if ( SrcMBB == DstMBB ) return SinglePath_InPath ; if ( ! AllowSideEntry && SrcMBB -> pred_size ( ) > <NUM_LIT> ) return Not_SinglePath ; } if ( SrcMBB && SrcMBB -> succ_size ( ) == <NUM_LIT> ) return SinglePath_NotInPath ;


<s> return ( ( CCMask & <STR_LIT> ) | ( CCMask & <STR_LIT> ? <STR_LIT> : <NUM_LIT> ) | ( CCMask & <STR_LIT> ? <STR_LIT> : <NUM_LIT> ) | ( CCMask & <STR_LIT> ) ) ;


<s> InstructionCost <ISA_LIT>TTIImpl :: getShuffleCost ( TTI :: ShuffleKind Kind , Type * Tp , ArrayRef < int > Mask , int Index , Type * SubTp ) {


<s> const <ISA_LIT>Subtarget & get<ISA_LIT>Subtarget ( ) const { return * get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) ;


<s> int <ISA_LIT>TTIImpl :: getArithmeticReductionCost ( unsigned Opcode , VectorType * ValTy , bool IsPairwiseForm , TTI :: TargetCostKind CostKind ) { if ( isa < ScalableVectorType > ( ValTy ) ) return getArithmeticReductionCostSVE ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; if ( IsPairwiseForm ) return BaseT :: getArithmeticReductionCost ( Opcode , ValTy , IsPairwiseForm , CostKind ) ; std :: pair < int , MVT > LT = TLI -> getTypeLegalizationCost ( DL , ValTy ) ;


<s> rtx arm_gen_compare_reg ( enum rtx_code code , rtx x , rtx y , rtx scratch ) { machine_mode mode ; rtx cc_reg ; int dimode_comparison = GET_MODE ( x ) == DImode || GET_MODE ( y ) == DImode ; if ( dimode_comparison && ! REG_P ( x ) ) x = force_reg ( DImode , x ) ; mode = SELECT_CC_MODE ( code , x , y ) ; cc_reg = gen_rtx_REG ( mode , CC_REGNUM ) ; if ( dimode_comparison && mode != CC_CZmode ) { rtx clobber , set ; if ( mode == CC_Zmode && y != const0_rtx ) { gcc_assert ( ! reload_completed ) ; x = expand_binop ( DImode , xor_optab , x , y , NULL_RTX , <NUM_LIT> , OPTAB_WIDEN ) ; y = const0_rtx ; } if ( reload_completed ) gcc_assert ( scratch != NULL && GET_MODE ( scratch ) == SImode ) ; else scratch = gen_rtx_SCRATCH ( SImode ) ; clobber = gen_rtx_CLOBBER ( VOIDmode , scratch ) ; set = gen_rtx_SET ( VOIDmode , cc_reg , gen_rtx_COMPARE ( mode , x , y ) ) ;

emit_insn ( gen_rtx_PARALLEL ( VOIDmode , gen_rtvec ( <NUM_LIT> , set , clobber ) ) ) ;


<s> if ( skipFunction ( MF . getFunction ( ) ) ) return false ; if ( IsCombinesDisabled ) return false ; bool HasChanged = false ; ST = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; TRI = ST -> getRegisterInfo ( ) ; TII = ST -> getInstrInfo ( ) ; const Function & F = MF . getFunction ( ) ; bool OptForSize = F . hasFnAttribute ( Attribute :: OptimizeForSize ) ; ShouldCombineAggressively = MF . getTarget ( ) . getOptLevel ( ) <= CodeGenOpt :: Default ; if ( ! OptForSize && ST -> isTinyCore ( ) ) IsConst64Disabled = true ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { PotentiallyNewifiableTFR . clear ( ) ; findPotentialNewifiableTFRs ( * BI ) ; for ( MachineBasicBlock :: iterator MI = BI -> begin ( ) , End = BI -> end ( ) ; MI != End ; ) { MachineInstr & I1 = * MI ++ ; if ( I1 . isDebugInstr ( ) ) continue ; if ( ShouldCombineAggressively && PotentiallyNewifiableTFR . count ( & I1 ) ) continue ;

if ( ! isCombinableInstType ( I1 , TII , ShouldCombineAggressively ) ) continue ;


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;

return new <ISA_LIT>AsmBackend ( STI , OSABI , TT . isArch64Bit ( ) , Options ) ;


<s> unsigned NewVReg = MRI . createVirtualRegister ( SrcRC ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: SUBREG_TO_REG ) , NewVReg ) . addImm ( <NUM_LIT> ) . add ( SrcMO ) . addImm ( <STR_LIT> ) ; SrcMO . setReg ( NewVReg ) ; } else if ( ! IsVSReg ( DstMO . getReg ( ) , MRI ) && IsVSReg ( SrcMO . getReg ( ) , MRI ) ) { Changed = true ; const TargetRegisterClass * DstRC = & <STR_LIT> ; assert ( ( IsF8Reg ( DstMO . getReg ( ) , MRI ) || IsVSFReg ( DstMO . getReg ( ) , MRI ) || IsVSSReg ( DstMO . getReg ( ) , MRI ) ) && <STR_LIT> ) ; unsigned NewVReg = MRI . createVirtualRegister ( DstRC ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVReg ) . add ( SrcMO ) ; SrcMO . setReg ( NewVReg ) ; SrcMO . setSubReg ( <STR_LIT> ) ;


<s> TargetRegistry :: RegisterMCSubtargetInfo ( TheARM64leTarget , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( TheARM64beTarget , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>leTarget , create<ISA_LIT>leAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( The<ISA_LIT>beTarget , create<ISA_LIT>beAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( TheARM64leTarget , create<ISA_LIT>leAsmBackend ) ; TargetRegistry :: RegisterMCAsmBackend ( TheARM64beTarget , create<ISA_LIT>beAsmBackend ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>leTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( The<ISA_LIT>beTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( TheARM64leTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCCodeEmitter ( TheARM64beTarget , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>leTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( The<ISA_LIT>beTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( TheARM64leTarget , createMCStreamer ) ; TargetRegistry :: RegisterMCObjectStreamer ( TheARM64beTarget , createMCStreamer ) ;

TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>leTarget , create<ISA_LIT>MCInstPrinter ) ;


<s> Tile64Type type = Tile64TypeOf ( MI ) ; return ( type == TypeMeS || type == TypeMeL ) ;


<s> const TargetRegisterClass * <ISA_LIT>InstrInfo :: getOpRegClass ( const MachineInstr & MI , unsigned OpNo ) const { const MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; const MCInstrDesc & Desc = get ( MI . getOpcode ( ) ) ;

if ( MI . isVariadic ( ) || OpNo >= Desc . getNumOperands ( ) || Desc . OpInfo [ OpNo ] . RegClass == - <NUM_LIT> ) {


<s> assert ( WideTy . isSimple ( ) ) ; return Subtarget . isHVXVectorType ( WideTy . getSimpleVT ( ) , true ) ; }


<s> <ISA_LIT>Operand ( KindTy K ) : MCParsedAsmOperand ( ) , Kind ( K ) {


<s> __asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) , <STR_LIT> ( c ) : ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: getGlobalBaseReg ( ) { unsigned GlobalBaseReg = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseReg ( ) ;

return CurDAG -> getRegister ( GlobalBaseReg , getTargetLowering ( ) -> getPointerTy ( CurDAG -> getDataLayout ( ) ) ) . getNode ( ) ;


<s> const <ISA_LIT>InstrInfo * TII = MF . getSubtarget < GCNSubtarget > ( ) . getInstrInfo ( ) ; for ( const CalleeSavedInfo & CS : C<ISA_LIT> ) { unsigned Reg = CS . getReg ( ) ; if ( CS . isSpilledToReg ( ) ) {

BuildMI ( MBB , MBBI , DebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , CS . getDstReg ( ) ) . addReg ( Reg , getKillRegState ( true ) ) ;


<s> EVT <ISA_LIT>TargetLowering :: getOptimalMemOpType ( uint64_t Size , unsigned DstAlign , unsigned SrcAlign , bool IsMemset , bool ZeroMemset , bool MemcpyStrSrc , MachineFunction & MF ) const { if ( Size >= <NUM_LIT> && DstAlign >= <NUM_LIT> ) return <STR_LIT> ;


<s> const MachineOperand & MO2 = MI . getOperand ( OpIdx ) ; unsigned AM3Opc = ( ImplicitRn == <STR_LIT> ) ? <NUM_LIT> : MI . getOperand ( OpIdx + <NUM_LIT> ) . getImm ( ) ; Binary |= ( ( <STR_LIT> ( AM3Opc ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) << <STR_LIT> ) ; if ( MO2 . getReg ( ) ) { Binary |= <ISA_LIT>RegisterInfo :: getRegisterNumbering ( MO2 . getReg ( ) ) ; emitWordLE ( Binary ) ; return ; } Binary |= <NUM_LIT> << <STR_LIT> ; if ( unsigned ImmOffs = <STR_LIT> ( AM3Opc ) ) {

Binary |= ( ImmOffs >> <NUM_LIT> ) << <STR_LIT> ;


<s> assert ( RC -> contains ( PReg ) && <STR_LIT> ) ;

unsigned VReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ;


<s> fn = SYMBOL_REF_DECL ( fnx ) ; if ( ! fn ) return FALSE ; vis = DECL_VISIBILITY ( fn ) ; if ( vis == VISIBILITY_PROTECTED ) vis = VISIBILITY_DEFAULT ; else if ( flag_shlib ) return TRUE ; ret = default_binds_local_p_1 ( fn , flag_pic ) ; DECL_VISIBILITY ( fn ) = vis ; return ret ;


<s> MBB -> insert ( MI , EarlierMI ) ; MachineOperand & HighRegOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowRegOp = MI -> getOperand ( <NUM_LIT> ) ; HighRegOp . setReg ( RI . getSubReg ( HighRegOp . getReg ( ) , <STR_LIT> ) ) ; LowRegOp . setReg ( RI . getSubReg ( LowRegOp . getReg ( ) , <STR_LIT> ) ) ; MachineOperand & HighOffsetOp = EarlierMI -> getOperand ( <NUM_LIT> ) ;

MachineOperand & LowOffsetOp = MI -> getOperand ( <NUM_LIT> ) ;


<s> m_InputTLSGdSymbols . insert ( & pInfo ) ; m_MultipartList . back ( ) . m_TLSNum += <NUM_LIT> ; m_MultipartList . back ( ) . m_TLSDynNum += <NUM_LIT> ;


<s> AllocaInst * <ISA_LIT>LibCalls :: insertAlloca ( CallInst * UI , IRBuilder < > & B , const char * prefix ) { BasicBlock :: iterator ItNew = getEntryIns ( UI ) ; Function * UCallee = UI -> getCalledFunction ( ) ; Type * RetType = UCallee -> getReturnType ( ) ; B . SetInsertPoint ( & * ItNew ) ; AllocaInst * Alloc = B . CreateAlloca ( RetType , nullptr , std :: string ( prefix ) + UI -> getName ( ) ) ;

Alloc -> setAlignment ( Align ( UCallee -> getParent ( ) -> getDataLayout ( ) . getTypeAllocSize ( RetType ) ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( getVectorIndex ( ) ) ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>InsertVSETVLIPass ( ) {


<s> gen = gen_aarch64_split_simd_movv8hi ; break ; case E_V4SImode : gen = gen_aarch64_split_simd_movv4si ; break ; case E_V2DImode : gen = gen_aarch64_split_simd_movv2di ; break ; case E_V8HFmode : gen = gen_aarch64_split_simd_movv8hf ; break ; case E_V4SFmode : gen = gen_aarch64_split_simd_movv4sf ; break ; case E_V2DFmode : gen = gen_aarch64_split_simd_movv2df ; break ; default : gcc_unreachable ( ) ; } emit_insn ( gen ( dst , src ) ) ;


<s> if ( GroupingCost != <NUM_LIT> ) dbgs ( ) << <STR_LIT> << GroupingCost ; if ( ResourcesCost != <NUM_LIT> ) dbgs ( ) << <STR_LIT> << ResourcesCost ;


if ( SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack ( DL , <STR_LIT> , V1 , V2 , Mask , DAG ) ) return Unpack ;


<s> if ( MF -> getFunction ( ) -> getCallingConv ( ) == CallingConv :: AnyReg ) return CSR_<ISA_LIT>_AllRegs_SaveList ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( <NUM_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; <ISA_LIT>CC <ISA_LIT>CCInfo ( CallConv , ABI . IsO32 ( ) , CCInfo ) ; Function :: const_arg_iterator FuncArg = DAG . getMachineFunction ( ) . getFunction ( ) . arg_begin ( ) ; bool UseSoftFloat = Subtarget . abiUsesSoftFloat ( ) ; <ISA_LIT>CCInfo . analyzeFormalArguments ( Ins , UseSoftFloat , FuncArg ) ; <ISA_LIT>FI -> setFormalArgInfo ( CCInfo . getNextStackOffset ( ) , <ISA_LIT>CCInfo . hasByValArg ( ) ) ; std :: vector < SDValue > OutChains ; unsigned CurArgIdx = <NUM_LIT> ; <STR_LIT> ByValArg = <ISA_LIT>CCInfo . byval_begin ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( Ins [ i ] . isOrigArg ( ) ) { std :: advance ( FuncArg , Ins [ i ] . getOrigArgIndex ( ) - CurArgIdx ) ; CurArgIdx = Ins [ i ] . getOrigArgIndex ( ) ; } EVT ValVT = VA . getValVT ( ) ; <STR_LIT> Flags = Ins [ i ] . Flags ; bool IsRegLoc = VA . isRegLoc ( ) ; if ( Flags . isByVal ( ) ) { assert ( Flags . getByValSize ( ) && <STR_LIT> ) ; assert ( ByValArg != <ISA_LIT>CCInfo . byval_end ( ) ) ; copyByValRegs ( Chain , DL , OutChains , DAG , Flags , InVals , & * FuncArg , <ISA_LIT>CCInfo , * ByValArg ) ; ++ ByValArg ; continue ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;

unsigned Reg = GPRDecoderTable [ RegNo ] ;


<s> else return false ; if ( rtx_equal_p ( op0 , true_cond ) && rtx_equal_p ( op1 , false_cond ) ) ; else if ( rtx_equal_p ( op1 , true_cond ) && rtx_equal_p ( op0 , false_cond ) && ! HONOR_NANS ( compare_mode ) && ! HONOR_SIGNED_ZEROS ( compare_mode ) ) max_p = ! max_p ;


<s> EVT DstVT = N -> getValueType ( <NUM_LIT> ) ; <STR_LIT> AM = LD -> getAddressingMode ( ) ; bool IsPre = AM == <STR_LIT> || AM == <STR_LIT> ; unsigned Opcode = <NUM_LIT> ; <STR_LIT> ExtType = LD -> getExtensionType ( ) ; bool InsertTo64 = false ; if ( VT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else if ( ExtType == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = true ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { if ( ExtType == <STR_LIT> ) { if ( DstVT == <STR_LIT> ) Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; else Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; InsertTo64 = DstVT == <STR_LIT> ; DstVT = <STR_LIT> ; } } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ; } else if ( VT == <STR_LIT> || VT . is64BitVector ( ) ) { Opcode = IsPre ? <STR_LIT> : <STR_LIT> ;


<s> return ( intptr_t ) ( MR -> getResultPointer ( ) ) ; case <STR_LIT> : return ( intptr_t ) ( MR -> getResultPointer ( ) ) - MR -> getConstantVal ( ) ; case <STR_LIT> : return getJumpTableBaseAddr ( MR -> getJumpTableIndex ( ) ) ; case <STR_LIT> : case <STR_LIT> : return getConstantPoolEntryAddr ( MR -> getConstantPoolIndex ( ) ) ;


<s> static DecodeStatus DecodeT2ShifterImmOperand ( MCInst & Inst , uint32_t Val , uint64_t Address , const void * Decoder ) {

DecodeStatus S = MCDisassembler :: Success ;


FiTmpOffsetMap . clear ( ) ; SetTmpSize ( <NUM_LIT> ) ;


<s> EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ; const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ; unsigned BaseAlign = Store -> getAlignment ( ) ; unsigned Size = LoMemVT . getStoreSize ( ) ; unsigned HiAlign = MinAlign ( BaseAlign , Size ) ; SDValue LoStore = DAG . getTruncStore ( Chain , SL , Lo , BasePtr , SrcValue , LoMemVT , BaseAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ;

SDValue HiStore = DAG . getTruncStore ( Chain , SL , Hi , HiPtr , SrcValue . getWithOffset ( Size ) , HiMemVT , HiAlign , Store -> getMemOperand ( ) -> getFlags ( ) ) ;


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

TargetRegistry :: RegisterTarget ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> , [ ] ( Triple :: ArchType ) { return false ; } , false ) ;


<s> case <NUM_LIT> : if ( ! Subtarget -> hasUsableDSOffset ( ) && Alignment < Align ( <NUM_LIT> ) ) return false ; RequiredAlignment = Align ( <NUM_LIT> ) ; if ( Subtarget -> hasUnalignedDSAccessEnabled ( ) ) { if ( IsFast ) * IsFast = true ; return true ; } break ; case <NUM_LIT> : if ( ! Subtarget -> hasDS96AndDS128 ( ) ) return false ; if ( Subtarget -> hasUnalignedDSAccessEnabled ( ) ) { if ( IsFast ) * IsFast = Alignment >= RequiredAlignment || Alignment < Align ( <NUM_LIT> ) ; return true ; } break ; case <NUM_LIT> : if ( ! Subtarget -> hasDS96AndDS128 ( ) || ! Subtarget -> useDS128 ( ) ) return false ; RequiredAlignment = Align ( <NUM_LIT> ) ; if ( Subtarget -> hasUnalignedDSAccessEnabled ( ) ) { if ( IsFast ) * IsFast = Alignment >= RequiredAlignment || Alignment < Align ( <NUM_LIT> ) ; return true ; } break ; default :


<s> Reserved . set ( <STR_LIT> ) ; } if ( Subtarget . is<ISA_LIT>64 ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! EnableRegisterScavenging ) Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( Subtarget . isSVR4ABI ( ) ) { Reserved . set ( <STR_LIT> ) ; } } if ( needsFP ( MF ) ) Reserved . set ( <STR_LIT> ) ;


<s> bool IsStrict = Op -> isStrictFPOpcode ( ) ;

SDValue In = Op . getOperand ( IsStrict ? <NUM_LIT> : <NUM_LIT> ) ;


<s> static rtx tilegx_got_symbol ( void ) { if ( g_got_symbol == NULL ) g_got_symbol = gen_rtx_SYMBOL_REF ( Pmode , <STR_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : if ( DecodeRegListOperand ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( Base ) ) ; Inst . addOperand ( MCOperand :: CreateImm ( Offset ) ) ; break ; case <STR_LIT> : Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; default :


<s> void <ISA_LIT>IntelInstPrinter :: printInst ( const MCInst * MI , raw_ostream & OS , StringRef Annot , const MCSubtargetInfo & STI ) { const MCInstrDesc & Desc = MII . get ( MI -> getOpcode ( ) ) ; uint64_t TSFlags = Desc . TSFlags ; unsigned Flags = MI -> getFlags ( ) ;

if ( ( TSFlags & <STR_LIT> ) || ( Flags & <STR_LIT> ) ) OS << <STR_LIT> ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ; APInt APIntShiftAmt ; if ( <STR_LIT> ( Amt , APIntShiftAmt ) ) { uint64_t ShiftAmt = APIntShiftAmt . urem ( VT . getScalarSizeInBits ( ) ) ; return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , DAG . getTargetConstant ( ShiftAmt , DL , <STR_LIT> ) ) ; } return DAG . getNode ( IsFSHR ? <STR_LIT> : <STR_LIT> , DL , VT , Op0 , Op1 , Amt ) ; } assert ( ( VT == <STR_LIT> || VT == <STR_LIT> || VT == <STR_LIT> ) && <STR_LIT> ) ; bool OptForSize = DAG . getMachineFunction ( ) . getFunction ( ) . hasOptSize ( ) ; if ( ! OptForSize && Subtarget . isSHLDSlow ( ) ) return SDValue ( ) ; if ( IsFSHR ) std :: swap ( Op0 , Op1 ) ;

if ( VT == <STR_LIT> ) Amt = DAG . getNode ( <STR_LIT> , DL , Amt . getValueType ( ) , Amt , DAG . getConstant ( <NUM_LIT> , DL , Amt . getValueType ( ) ) ) ;


<s> return ( EltSize >= <NUM_LIT> || ShuffleVectorSDNode :: isSplatMask ( & M [ <NUM_LIT> ] , VT ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVREVMask ( M , VT , <NUM_LIT> ) || isVEXTMask ( M , VT , ReverseVEXT , Imm ) || isVTRNMask ( M , VT , WhichResult ) || isVUZPMask ( M , VT , WhichResult ) || isVZIPMask ( M , VT , WhichResult ) || isVTRN_v_undef_Mask ( M , VT , WhichResult ) || isVUZP_v_undef_Mask ( M , VT , WhichResult ) || isVZIP_v_undef_Mask ( M , VT , WhichResult ) ) ;


<s> bool runOnFunction ( Function & F ) override { visit ( F ) ; return false ;


<s> return ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) && ( ( Imm >> <NUM_LIT> ) == ( Imm & <NUM_LIT> ) ) ;


<s> if ( ! Subtarget . hasVInstructionsI64 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF16 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF32 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget . hasVInstructionsF64 ( ) ) return false ; break ; } if ( EltVT . getSizeInBits ( ) > Subtarget . getMaxELENForFixedLengthVectors ( ) ) return false ;

unsigned LMul = divideCeil ( VT . getSizeInBits ( ) , MinVLen ) ;


<s> } if ( rs6000_hard_regno_nregs [ m ] [ r ] > <NUM_LIT> ) len += fprintf ( stderr , <STR_LIT> , comma , GET_MODE_NAME ( m ) , rs6000_hard_regno_nregs [ m ] [ r ] ) ; else len += fprintf ( stderr , <STR_LIT> , comma , GET_MODE_NAME ( m ) ) ; comma = <STR_LIT> ; } if ( call_used_regs [ r ] ) { if ( len > <NUM_LIT> ) { fprintf ( stderr , <STR_LIT> ) ; len = <NUM_LIT> ; comma = <STR_LIT> ; } len += fprintf ( stderr , <STR_LIT> , comma , <STR_LIT> ) ; comma = <STR_LIT> ; } if ( fixed_regs [ r ] ) {


<s> SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , MaskVT , <STR_LIT> ) ; SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; if ( Src . isUndef ( ) ) Src = getZeroVector ( Op . getSimpleValueType ( ) , Subtarget , DAG , dl ) ;

SDValue Ops [ ] = { Src , VMask , Base , Scale , Index , Disp , Segment , Chain } ;


<s> assert ( Op . getSimpleValueType ( ) . is256BitVector ( ) && Op . getSimpleValueType ( ) . isInteger ( ) && <STR_LIT> ) ; return Lower256IntArith ( Op , DAG ) ;


<s> assert ( ISD && <STR_LIT> ) ; EVT SrcTy = TLI -> getValueType ( Src ) ; EVT DstTy = TLI -> getValueType ( Dst ) ; if ( ! SrcTy . isSimple ( ) || ! DstTy . isSimple ( ) ) return VectorTargetTransformImpl :: getCastInstrCost ( Opcode , Dst , Src ) ; const <ISA_LIT>Subtarget & ST = TLI -> getTargetMachine ( ) . getSubtarget < <ISA_LIT>Subtarget > ( ) ; static const <ISA_LIT>TypeConversionCostTblEntry AVXConversionTbl [ ] = { { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ; if ( ST . hasAVX ( ) ) { int Idx = FindInConvertTable ( AVXConversionTbl , array_lengthof ( AVXConversionTbl ) , ISD , DstTy . getSimpleVT ( ) , SrcTy . getSimpleVT ( ) ) ; if ( Idx != - <NUM_LIT> ) return AVXConversionTbl [ Idx ] . Cost ; } return VectorTargetTransformImpl :: getCastInstrCost ( Opcode , Dst , Src ) ;


<s> if ( Callee . isReg ( ) ) MIB -> getOperand ( <NUM_LIT> ) . setReg ( constrainOperandRegClass ( MF , * TRI , MRI , * MF . getSubtarget ( ) . getInstrInfo ( ) , * MF . getSubtarget ( ) . getRegBankInfo ( ) , * MIB , MIB -> getDesc ( ) , Callee . getReg ( ) , <NUM_LIT> ) ) ; CCAssignFn * RetAssignFn = TLI . CCAssignFnForReturn ( F . getCallingConv ( ) ) ; if ( OrigRet . Reg ) { SplitArgs . clear ( ) ; SmallVector < uint64_t , <NUM_LIT> > RegOffsets ; SmallVector < unsigned , <NUM_LIT> > SplitRegs ; splitToValueTypes ( OrigRet , SplitArgs , DL , MRI , [ & ] ( unsigned Reg , uint64_t Offset ) { RegOffsets . push_back ( Offset ) ; SplitRegs . push_back ( Reg ) ; } ) ; CallReturnHandler Handler ( MIRBuilder , MRI , MIB , RetAssignFn ) ; if ( ! handleAssignments ( MIRBuilder , SplitArgs , Handler ) ) return false ; if ( ! RegOffsets . empty ( ) ) MIRBuilder . buildSequence ( OrigRet . Reg , SplitRegs , RegOffsets ) ; } CallSeqStart . addImm ( Handler . StackSize ) . addImm ( <NUM_LIT> ) ; MIRBuilder . buildInstr ( <STR_LIT> ) . addImm ( Handler . StackSize ) . addImm ( <NUM_LIT> ) ;


<s> DecodeStatus S = MCDisassembler :: Success ; const FeatureBitset & featureBits = ( ( const MCDisassembler * ) Decoder ) -> getSubtargetInfo ( ) . getFeatureBits ( ) ;

if ( ( RegNo == <NUM_LIT> && ! featureBits [ <STR_LIT> ] ) || RegNo == <NUM_LIT> ) S = MCDisassembler :: SoftFail ;


<s> <ISA_LIT>Operand ( KindTy K ) : MCParsedAsmOperand ( ) , Kind ( K ) {


<s> if ( ! IsConstantImm ) IsValid = <ISA_LIT>AsmParser :: classifySymbolRef ( getImm ( ) , VK , Imm ) ; else IsValid = isShiftedInt < N - <NUM_LIT> , <NUM_LIT> > ( Imm ) ; return IsValid && VK == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ;


<s> if ( Subtarget . isDarwinABI ( ) ) { FPOpOut = getFramePointerFrameIndex ( DAG ) ; FPOpOut = DAG . getLoad ( VT , dl , Chain , FPOpOut , MachinePointerInfo ( ) ) ;

Chain = SDValue ( FPOpOut . getNode ( ) , <NUM_LIT> ) ;


<s> if ( left ) return aarch64_const_vec_all_same_in_range_p ( x , <NUM_LIT> , bit_width - <NUM_LIT> ) ;

else return aarch64_const_vec_all_same_in_range_p ( x , <NUM_LIT> , bit_width ) ;


<s> BTFType . NameOff = BDebug . addString ( ETy -> getName ( ) ) ; DINodeArray Elements = ETy -> getElements ( ) ; for ( const auto Element : Elements ) { const auto * Enum = cast < DIEnumerator > ( Element ) ; struct <STR_LIT> BTFEnum ; BTFEnum . NameOff = BDebug . addString ( Enum -> getName ( ) ) ; BTFEnum . Val = static_cast < uint32_t > ( Enum -> getValue ( ) ) ; EnumValues . push_back ( BTFEnum ) ; }


<s> switch ( insn_type ) { case TYPE_STORE : if ( dep_type == TYPE_IALU || dep_type == TYPE_SHIFT ) { if ( GET_CODE ( pat ) != SET || GET_CODE ( dep_pat ) != SET ) break ;

if ( rtx_equal_p ( SET_DEST ( dep_pat ) , SET_SRC ( pat ) ) ) return <NUM_LIT> ;


<s> if ( DCI . isBeforeLegalizeOps ( ) ) { if ( Subtarget . has<ISA_LIT>32 ( ) && ! Subtarget . has<ISA_LIT>32r6 ( ) && ! Subtarget . in<ISA_LIT>16Mode ( ) && N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) return performMADD_MSUBCombine ( N , DAG , Subtarget ) ; return SDValue ( ) ;


<s> static Register getFPReg ( const <ISA_LIT>Subtarget & STI ) {


<s> return __builtin_mve_vcvtaq_m_uv4si ( __arm_vuninitializedq_u32 ( ) , __a , __p ) ;


<s> switch ( getLexer ( ) . getKind ( ) ) { default : return MatchOperand_ParseFail ; case AsmToken :: Integer : { int64_t Imm ; if ( getParser ( ) . parseAbsoluteExpression ( Imm ) ) return MatchOperand_ParseFail ; Operands . push_back ( AMDGPUOperand :: CreateImm ( Imm , S ) ) ; return MatchOperand_Success ; }


<s> return ( __m256i ) __builtin_ia32_vpconflictsi_256_mask ( ( __v8si ) __A , ( __v8si ) _mm256_setzero_si256 ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> DebugLoc dl = V0 . getNode ( ) -> getDebugLoc ( ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;

SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , <STR_LIT> ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override { AU . addRequired < LiveIntervals > ( ) ; AU . addPreserved < LiveIntervals > ( ) ;


<s> int64_t AddrDispShift ; assert ( calcInstrDist ( First , Last ) > <NUM_LIT> && <STR_LIT> ) ; if ( ! isReplaceable ( First , Last , AddrDispShift ) ) { ++ I2 ; continue ; } for ( auto UI = MRI -> use_begin ( Last . getOperand ( <NUM_LIT> ) . getReg ( ) ) , UE = MRI -> use_end ( ) ; UI != UE ; ) { MachineOperand & MO = * UI ++ ; MachineInstr & MI = * MO . getParent ( ) ; const MCInstrDesc & Desc = MI . getDesc ( ) ;

int MemOpNo = <STR_LIT> ( Desc . TSFlags ) + <STR_LIT> ( Desc ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerUINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const {

assert ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> if ( ( Flags & <STR_LIT> ) == <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI ) ; CannotTailPredicate = true ; }


<s> return PALMD :: Key :: VS_SCRATCH_<ISA_LIT>ZE ; case CallingConv :: <ISA_LIT>_GS : return PALMD :: Key :: GS_SCRATCH_<ISA_LIT>ZE ; case CallingConv :: <ISA_LIT>_ES : return PALMD :: Key :: ES_SCRATCH_<ISA_LIT>ZE ; case CallingConv :: <ISA_LIT>_HS : return PALMD :: Key :: HS_SCRATCH_<ISA_LIT>ZE ; case CallingConv :: <ISA_LIT>_LS : return PALMD :: Key :: LS_SCRATCH_<ISA_LIT>ZE ; default : return PALMD :: Key :: CS_SCRATCH_<ISA_LIT>ZE ;


<s> unsigned VarArgsBytes = MFI . getObjectSize ( AFI -> getVarArgsFrameIndex ( ) ) ; unsigned Opc = <STR_LIT> ; if ( isUInt < <NUM_LIT> > ( VarArgsBytes ) ) Opc = <STR_LIT> ; else if ( isInt < <NUM_LIT> > ( VarArgsBytes ) ) Opc = <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII -> get ( Opc ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( VarArgsBytes ) ; } if ( hasFP ( MF ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( - <NUM_LIT> ) ; AlreadyAdjusted += <NUM_LIT> ; } if ( UseSaveRestoreFunclet && Last > <STR_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; StackSlotsUsedByFunclet = Last - <STR_LIT> ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( <NUM_LIT> * StackSlotsUsedByFunclet ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) . addExternalSymbol ( store_funclet_name [ Last - <STR_LIT> ] ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; AlreadyAdjusted += <NUM_LIT> * ( StackSlotsUsedByFunclet + <NUM_LIT> ) ; SavedBlink = true ; } if ( MFI . hasCalls ( ) && ! SavedBlink ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; BuildMI ( MBB , MBBI , dl , TII -> get ( <STR_LIT> ) ) ; AlreadyAdjusted += <NUM_LIT> ; } if ( AFI -> MaxCallStackReq > <NUM_LIT> ) MFI . setStackSize ( MFI . getStackSize ( ) + AFI -> MaxCallStackReq ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( MFI . getStackSize ( ) - AlreadyAdjusted ) << <STR_LIT> ) ; generateStackAdjustment ( MBB , MBBI , * ST . getInstrInfo ( ) , dl , - ( MFI . getStackSize ( ) - AlreadyAdjusted ) , <STR_LIT> ) ; if ( hasFP ( MF ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;

BuildMI ( MBB , MBBI , dl , TII -> get ( isUInt < <NUM_LIT> > ( MFI . getStackSize ( ) ) ? <STR_LIT> : <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( MFI . getStackSize ( ) ) ;


<s> static __inline qword si_fnms ( qword a , qword b , qword c ) {

return ( ( qword ) ( vec_nmsub ( ( vec_float4 ) ( a ) , ( vec_float4 ) ( b ) , ( vec_float4 ) ( c ) ) ) ) ;


<s> assert ( LinkerConfig :: DynObj == pConfig . codeGenType ( ) || LinkerConfig :: Exec == pConfig . codeGenType ( ) || LinkerConfig :: Binary == pConfig . codeGenType ( ) ) ; m_PLT0 = hexagon_plt0 ; m_PLT0Size = sizeof ( hexagon_plt0 ) ; new <ISA_LIT>PLT0 ( * m_pSectionData ) ; pSection . setAlign ( <NUM_LIT> ) ;


<s> x = emit_insn ( x ) ; sp_reg = gen_rtx_REG ( SImode , STACK_POINTER_REGNUM ) ; reg = copy_rtx ( GET_CODE ( PATTERN ( x ) ) == PARALLEL ? SET_DEST ( XVECEXP ( PATTERN ( x ) , <NUM_LIT> , <NUM_LIT> ) ) : SET_DEST ( PATTERN ( x ) ) ) ; add_reg_note ( x , REG_CFA_RESTORE , reg ) ;

add_reg_note ( x , REG_CFA_ADJUST_CFA , gen_rtx_SET ( SImode , sp_reg , plus_constant ( SImode , sp_reg , GET_MODE_SIZE ( GET_MODE ( reg ) ) ) ) ) ;


<s> for ( unsigned Loc = RepeatedSequenceLocs [ <NUM_LIT> ] . getStartIdx ( ) ; Loc < RepeatedSequenceLocs [ <NUM_LIT> ] . getEndIdx ( ) + <NUM_LIT> ; Loc ++ ) { if ( MBBI -> isCFIInstruction ( ) ) CFICount ++ ; MBBI ++ ; } for ( outliner :: Candidate & C : RepeatedSequenceLocs ) { std :: vector < MCCFIInstruction > CFIInstructions = C . getMF ( ) -> getFrameInstructions ( ) ; if ( CFICount > <NUM_LIT> && CFICount != CFIInstructions . size ( ) ) return outliner :: OutlinedFunction ( ) ;


<s> SDValue Ptr = Ld -> getBasePtr ( ) ; SDValue Increment = DAG . getConstant ( <NUM_LIT> , dl , TLI . getPointerTy ( ) ) ; EVT HalfVT = EVT :: getVectorVT ( * DAG . getContext ( ) , MemVT . getScalarType ( ) , NumElems / <NUM_LIT> ) ; SDValue Load1 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , Alignment ) ; Ptr = DAG . getNode ( <STR_LIT> , dl , Ptr . getValueType ( ) , Ptr , Increment ) ; SDValue Load2 = DAG . getLoad ( HalfVT , dl , Ld -> getChain ( ) , Ptr , Ld -> getPointerInfo ( ) , Ld -> isVolatile ( ) , Ld -> isNonTemporal ( ) , Ld -> isInvariant ( ) , std :: min ( <NUM_LIT> , Alignment ) ) ;

SDValue TF = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Load1 . getValue ( <NUM_LIT> ) , Load2 . getValue ( <NUM_LIT> ) ) ;


<s> static unsigned getFramePointerSaveOffset ( bool is<ISA_LIT>64 , bool isDarwinABI ) { if ( isDarwinABI ) return is<ISA_LIT>64 ? - <NUM_LIT> : - <NUM_LIT> ; return is<ISA_LIT>64 ? - <NUM_LIT> : - <NUM_LIT> ;


<s> SDNode * T = CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( N ) , ResTy , N -> getOperand ( <NUM_LIT> ) ) ; ReplaceNode ( N , T ) ;


<s> if ( Op . getOpcode ( ) == <STR_LIT> || Op . getOpcode ( ) == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , VT , Op , IMask ) ; if ( PreservedSrc . isUndef ( ) ) PreservedSrc = getZeroVector ( VT , Subtarget , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , VT , IMask , Op , PreservedSrc ) ;


<s> MachineBasicBlock :: iterator End = MBB . end ( ) ; -- End ; assert ( End -> getOpcode ( ) == <STR_LIT> ) ; -- End ; if ( & MI != & * End ) return false ; } if ( FallthroughOpc != <STR_LIT> ) { MachineOperand & MO = MI . getOperand ( <NUM_LIT> ) ; unsigned Reg = MO . getReg ( ) ; if ( ! MFI . isVRegStackified ( Reg ) ) { unsigned NewReg = MRI . createVirtualRegister ( MRI . getRegClass ( Reg ) ) ;

BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII . get ( CopyLocalOpc ) , NewReg ) . addReg ( Reg ) ;


<s> if ( info -> vrsave_mask ) fprintf ( stderr , <STR_LIT> , info -> vrsave_mask ) ; if ( info -> push_p ) fprintf ( stderr , <STR_LIT> , info -> push_p ) ; if ( info -> calls_p ) fprintf ( stderr , <STR_LIT> , info -> calls_p ) ; if ( info -> gp_save_offset ) fprintf ( stderr , <STR_LIT> , info -> gp_save_offset ) ; if ( info -> fp_save_offset ) fprintf ( stderr , <STR_LIT> , info -> fp_save_offset ) ; if ( info -> altivec_save_offset ) fprintf ( stderr , <STR_LIT> , info -> altivec_save_offset ) ; if ( info -> spe_gp_save_offset ) fprintf ( stderr , <STR_LIT> , info -> spe_gp_save_offset ) ; if ( info -> vrsave_save_offset ) fprintf ( stderr , <STR_LIT> , info -> vrsave_save_offset ) ; if ( info -> lr_save_offset ) fprintf ( stderr , <STR_LIT> , info -> lr_save_offset ) ; if ( info -> cr_save_offset ) fprintf ( stderr , <STR_LIT> , info -> cr_save_offset ) ; if ( info -> toc_save_offset ) fprintf ( stderr , <STR_LIT> , info -> toc_save_offset ) ; if ( info -> varargs_save_offset ) fprintf ( stderr , <STR_LIT> , info -> varargs_save_offset ) ; if ( info -> total_size ) fprintf ( stderr , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , info -> total_size ) ; if ( info -> vars_size ) fprintf ( stderr , <STR_LIT> HOST_WIDE_INT_PRINT_DEC <STR_LIT> , info -> vars_size ) ; if ( info -> parm_size ) fprintf ( stderr , <STR_LIT> , info -> parm_size ) ; if ( info -> fixed_size ) fprintf ( stderr , <STR_LIT> , info -> fixed_size ) ; if ( info -> gp_size ) fprintf ( stderr , <STR_LIT> , info -> gp_size ) ; if ( info -> spe_gp_size ) fprintf ( stderr , <STR_LIT> , info -> spe_gp_size ) ; if ( info -> fp_size ) fprintf ( stderr , <STR_LIT> , info -> fp_size ) ; if ( info -> altivec_size ) fprintf ( stderr , <STR_LIT> , info -> altivec_size ) ; if ( info -> vrsave_size ) fprintf ( stderr , <STR_LIT> , info -> vrsave_size ) ; if ( info -> altivec_padding_size ) fprintf ( stderr , <STR_LIT> , info -> altivec_padding_size ) ; if ( info -> spe_padding_size ) fprintf ( stderr , <STR_LIT> , info -> spe_padding_size ) ; if ( info -> lr_size ) fprintf ( stderr , <STR_LIT> , info -> lr_size ) ; if ( info -> cr_size ) fprintf ( stderr , <STR_LIT> , info -> cr_size ) ; if ( info -> toc_size ) fprintf ( stderr , <STR_LIT> , info -> toc_size ) ;

if ( info -> save_size ) fprintf ( stderr , <STR_LIT> , info -> save_size ) ;


<s> pass_arc_ifcvt ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_arc_ifcvt , ctxt ) {


<s> fputs ( <STR_LIT> , file ) ; break ; case <NUM_LIT> : h8300_print_operand ( file , index , 'T' ) ; fputs ( <STR_LIT> , file ) ; break ; case <NUM_LIT> : h8300_print_operand ( file , index , 'S' ) ; fputs ( <STR_LIT> , file ) ; break ; } } else { h8300_print_operand_address ( file , XEXP ( addr , <NUM_LIT> ) ) ; fprintf ( file , <STR_LIT> ) ; h8300_print_operand_address ( file , XEXP ( addr , <NUM_LIT> ) ) ; } fprintf ( file , <STR_LIT> ) ; break ; case CONST_INT : { int n = INTVAL ( addr ) ; if ( TARGET_H8300 ) n = ( int ) ( short ) n ;


<s> if ( ! Subtarget -> hasInt256 ( ) && VT . is256BitVector ( ) ) return SDValue ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue V1 = Op . getOperand ( <NUM_LIT> ) ; SDValue V2 = Op . getOperand ( <NUM_LIT> ) ; unsigned NumElems = VT . getVectorNumElements ( ) ; if ( V2 . getOpcode ( ) != <STR_LIT> || ! VT . isInteger ( ) || VT . getVectorElementType ( ) == <STR_LIT> ) return SDValue ( ) ; unsigned Shift = <NUM_LIT> ; while ( ( <NUM_LIT> << Shift ) < NumElems ) { if ( SVOp -> getMaskElt ( <NUM_LIT> << Shift ) == <NUM_LIT> ) break ; Shift += <NUM_LIT> ; if ( Shift > <NUM_LIT> ) return SDValue ( ) ; } unsigned Mask = ( <NUM_LIT> << Shift ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) {


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Subtarget ( * TM . getSubtargetImpl ( ) ) {


<s> Branch . setOpcode ( <STR_LIT> ) ; Branch . addOperand ( MCOperand :: CreateExpr ( BranchTarget ) ) ;


<s> SDValue RC = CurDAG -> getTargetConstant ( TRC -> getID ( ) , <STR_LIT> ) ; SDValue NewOp = SDValue ( CurDAG -> getMachineNode ( TargetOpcode :: COPY_TO_REGCLASS , SDLoc ( Op ) , Op . getValueType ( ) , Op , RC ) , <NUM_LIT> ) ;


<s> return isLegalToVectorizeMemChain ( ChainSizeInBytes , Alignment , AddrSpace ) ;


<s> bool <ISA_LIT>TTIImpl :: isLegalMaskedGather ( Type * DataTy , MaybeAlign Alignment ) { if ( ! ( ST -> hasAVX512 ( ) || ( ST -> hasFastGather ( ) && ST -> hasAVX2 ( ) ) ) ) return false ; if ( auto * DataVTy = dyn_cast < VectorType > ( DataTy ) ) {

unsigned NumElts = DataVTy -> getNumElements ( ) ;


<s> if ( mips_expand_vselect_vconcat ( d -> target , d -> op0 , d -> op1 , d -> perm , nelt ) ) return true ; for ( i = <NUM_LIT> ; i < nelt ; ++ i ) perm2 [ i ] = ( d -> perm [ i ] + nelt ) & ( <NUM_LIT> * nelt - <NUM_LIT> ) ; if ( mips_expand_vselect_vconcat ( d -> target , d -> op1 , d -> op0 , perm2 , nelt ) ) return true ; } if ( mips_expand_vpc_loongson_even_odd ( d ) ) return true ; if ( mips_expand_vpc_loongson_pshufh ( d ) ) return true ; if ( mips_expand_vpc_loongson_bcast ( d ) ) return true ;


<s> MachineOperand & DstMO = MI . getOperand ( <NUM_LIT> ) ; MachineOperand & SrcMO = MI . getOperand ( <NUM_LIT> ) ; if ( IsVSReg ( DstMO . getReg ( ) , MRI ) && ! IsVSReg ( SrcMO . getReg ( ) , MRI ) ) { Changed = true ; const TargetRegisterClass * SrcRC = & <STR_LIT> ; assert ( ( IsF8Reg ( SrcMO . getReg ( ) , MRI ) || IsVSSReg ( SrcMO . getReg ( ) , MRI ) || IsVSFReg ( SrcMO . getReg ( ) , MRI ) ) && <STR_LIT> ) ; unsigned NewVReg = MRI . createVirtualRegister ( SrcRC ) ; BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: SUBREG_TO_REG ) , NewVReg ) . addImm ( <NUM_LIT> ) . addOperand ( SrcMO ) . addImm ( <STR_LIT> ) ; SrcMO . setReg ( NewVReg ) ; } else if ( ! IsVSReg ( DstMO . getReg ( ) , MRI ) && IsVSReg ( SrcMO . getReg ( ) , MRI ) ) { Changed = true ; const TargetRegisterClass * DstRC = & <STR_LIT> ; assert ( ( IsF8Reg ( DstMO . getReg ( ) , MRI ) || IsVSFReg ( DstMO . getReg ( ) , MRI ) || IsVSSReg ( DstMO . getReg ( ) , MRI ) ) && <STR_LIT> ) ; unsigned NewVReg = MRI . createVirtualRegister ( DstRC ) ;

BuildMI ( MBB , MI , MI . getDebugLoc ( ) , TII -> get ( TargetOpcode :: COPY ) , NewVReg ) . addOperand ( SrcMO ) ;


<s> virtual bool addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> if ( RegOffsets . lookup ( <STR_LIT> ) != ( - <NUM_LIT> - StackAdjust ) ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << StackAdjust << <STR_LIT> << CFARegisterOffset << <STR_LIT> << RegOffsets [ <NUM_LIT> ] << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } if ( RegOffsets . lookup ( <STR_LIT> ) != ( - <NUM_LIT> - StackAdjust ) ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } uint32_t CompactUnwindEncoding = CU :: UNWIND_<ISA_LIT>_MODE_FRAME ; switch ( StackAdjust ) { case <NUM_LIT> : break ; case <NUM_LIT> : CompactUnwindEncoding |= <NUM_LIT> ; break ; case <NUM_LIT> : CompactUnwindEncoding |= <NUM_LIT> ; break ; case <NUM_LIT> : CompactUnwindEncoding |= <NUM_LIT> ; break ; default : DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << StackAdjust << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } static struct { unsigned Reg ; unsigned Encoding ; } GPRCSRegs [ ] = { { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_FIRST_PUSH_R6 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_FIRST_PUSH_R5 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_FIRST_PUSH_R4 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R12 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R11 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R10 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R9 } , { <STR_LIT> , CU :: UNWIND_<ISA_LIT>_FRAME_SECOND_PUSH_R8 } } ; int CurOffset = - <NUM_LIT> - StackAdjust ; for ( auto CSReg : GPRCSRegs ) { auto Offset = RegOffsets . find ( CSReg . Reg ) ; if ( Offset == RegOffsets . end ( ) ) continue ; int RegOffset = Offset -> second ; if ( RegOffset != CurOffset - <NUM_LIT> ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << MRI . getName ( CSReg . Reg ) << <STR_LIT> << RegOffset << <STR_LIT> << CurOffset << <STR_LIT> ) ; return CU :: UNWIND_<ISA_LIT>_MODE_DWARF ; } CompactUnwindEncoding |= CSReg . Encoding ; CurOffset -= <NUM_LIT> ; } if ( FloatRegCount == <NUM_LIT> ) return CompactUnwindEncoding ; CompactUnwindEncoding &= ~ CU :: UNWIND_<ISA_LIT>_MODE_MASK ; CompactUnwindEncoding |= CU :: UNWIND_<ISA_LIT>_MODE_FRAME_D ; if ( FloatRegCount > <NUM_LIT> ) { DEBUG_WITH_TYPE ( <STR_LIT> , llvm :: dbgs ( ) << <STR_LIT> << FloatRegCount << <STR_LIT> ) ;


<s> -- OpUsefulBits ; if ( Op . getOperand ( <NUM_LIT> ) == Orig ) { Mask = ResultUsefulBits & OpUsefulBits ; Mask = Mask . shl ( LSB ) ; } if ( Op . getOperand ( <NUM_LIT> ) == Orig ) Mask |= ( ResultUsefulBits & ~ OpUsefulBits ) ; } else { uint64_t Width = MSB + <NUM_LIT> ; uint64_t LSB = UsefulBits . getBitWidth ( ) - Imm ; OpUsefulBits = OpUsefulBits . shl ( Width ) ; -- OpUsefulBits ; OpUsefulBits = OpUsefulBits . shl ( LSB ) ; if ( Op . getOperand ( <NUM_LIT> ) == Orig ) { Mask = ResultUsefulBits & OpUsefulBits ; Mask . lshrInPlace ( LSB ) ; }


<s> int length = get_attr_length ( insn ) ; if ( branch_to_delay_slot_p ( insn ) ) { if ( which_alternative == <NUM_LIT> ) return <STR_LIT> ; else if ( which_alternative == <NUM_LIT> ) { output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT> ; } else { output_asm_insn ( <STR_LIT> , operands ) ; return <STR_LIT> ; } } if ( which_alternative == <NUM_LIT> ) { int nullify = INSN_ANNULLED_BRANCH_P ( insn ) ; int xdelay ; if ( length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = <NUM_LIT> ; if ( ! nullify && length == <NUM_LIT> && dbr_sequence_length ( ) == <NUM_LIT> ) nullify = forward_branch_p ( insn ) ; switch ( length ) { case <NUM_LIT> : if ( nullify ) { if ( branch_needs_nop_p ( insn ) ) return <STR_LIT> ; else return <STR_LIT> ; } else return <STR_LIT> ;


<s> } assert ( BitWidth == <NUM_LIT> || BitWidth == <NUM_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Words ; for ( unsigned i = <NUM_LIT> ; i != BitWidth / <NUM_LIT> ; ++ i ) { SDValue W = extractHvxElementReg ( VQ , DAG . getConstant ( i , dl , <STR_LIT> ) , dl , <STR_LIT> , DAG ) ; Words . push_back ( W ) ; } SmallVector < SDValue , <NUM_LIT> > Combines ; assert ( Words . size ( ) % <NUM_LIT> == <NUM_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = Words . size ( ) ; i < e ; i += <NUM_LIT> ) { SDValue C = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , { Words [ i ] , Words [ i + <NUM_LIT> ] } ) ; Combines . push_back ( C ) ; } if ( BitWidth == <NUM_LIT> ) return Combines [ <NUM_LIT> ] ; return DAG . getNode ( <STR_LIT> , dl , ResTy , Combines ) ;


<s> if ( MF . getInfo < <ISA_LIT>FunctionInfo > ( ) -> shouldSignReturnAddress ( ) ) return true ;

return ( getFramePointerReg ( ) == <STR_LIT> && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) || isThumb1Only ( ) ;


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MVT VT = Op . getSimpleValueType ( ) ; unsigned RA = ABI . IsN64 ( ) ? <STR_LIT> : <STR_LIT> ; MFI -> setReturnAddressIsTaken ( true ) ;

unsigned Reg = MF . addLiveIn ( RA , getRegClassFor ( VT ) ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :

return DAG . getNode ( Opc , dl , VT , V1 , V2 ) ;


<s> return __builtin_aarch64_ushlv2si_uus ( __a , __b ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerEH_SJLJ_DISPATCHSETUP ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> FixupLEAPass :: RegUsageState FixupLEAPass :: usesRegister ( MachineOperand & p , MachineBasicBlock :: iterator I ) { RegUsageState RegUsage = RU_NotUsed ; MachineInstr * MI = I ; for ( unsigned int i = <NUM_LIT> ; i < MI -> getNumOperands ( ) ; ++ i ) { MachineOperand & opnd = MI -> getOperand ( i ) ; if ( opnd . isReg ( ) && opnd . getReg ( ) == p . getReg ( ) ) { if ( opnd . isDef ( ) ) return RU_Write ; RegUsage = RU_Read ; }


<s> assert ( Kind == Immediate && <STR_LIT> ) ; return Imm . Val ;


<s> if ( CSI . empty ( ) ) return false ; DebugLoc DL ; if ( MI != MBB . end ( ) ) DL = MI -> getDebugLoc ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) {


<s> if ( specified ) O << <STR_LIT> << reqntidx << <STR_LIT> << reqntidy << <STR_LIT> << reqntidz << <STR_LIT> ; unsigned maxntidx , maxntidy , maxntidz ; specified = false ; if ( ! llvm :: getMaxNTIDx ( F , maxntidx ) ) maxntidx = <NUM_LIT> ; else specified = true ; if ( ! llvm :: getMaxNTIDy ( F , maxntidy ) ) maxntidy = <NUM_LIT> ; else specified = true ; if ( ! llvm :: getMaxNTIDz ( F , maxntidz ) ) maxntidz = <NUM_LIT> ; else specified = true ; if ( specified ) O << <STR_LIT> << maxntidx << <STR_LIT> << maxntidy << <STR_LIT> << maxntidz << <STR_LIT> ; unsigned mincta ;

if ( llvm :: getMinCTASm ( F , mincta ) ) O << <STR_LIT> << mincta << <STR_LIT> ;


<s> SDLoc DL ( Node ) ; const GlobalValue * GV = Node -> getGlobal ( ) ; int64_t Offset = Node -> getOffset ( ) ; EVT PtrVT = getPointerTy ( ) ; Reloc :: Model RM = DAG . getTarget ( ) . getRelocationModel ( ) ; CodeModel :: Model CM = DAG . getTarget ( ) . getCodeModel ( ) ; SDValue Result ; if ( Subtarget . isPC32DBLSymbol ( GV , RM , CM ) ) { uint64_t Anchor = Offset & ~ uint64_t ( <NUM_LIT> ) ; Result = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; Offset -= Anchor ; if ( Offset != <NUM_LIT> && ( Offset & <NUM_LIT> ) == <NUM_LIT> ) { SDValue Full = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , Anchor + Offset ) ; Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Full , Result ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine * TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> if ( ! ST -> hasVscnt ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_ACCESS , Inst ) ; else if ( ( Inst . mayLoad ( ) && <STR_LIT> ( Inst . getOpcode ( ) ) == - <NUM_LIT> ) || ( TII -> isMIMG ( Inst ) && ! Inst . mayLoad ( ) && ! Inst . mayStore ( ) ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_READ_ACCESS , Inst ) ; else if ( Inst . mayStore ( ) ) ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMEM_WRITE_ACCESS , Inst ) ; if ( ST -> vmemWriteNeedsExpWaitcnt ( ) && ( Inst . mayStore ( ) || <STR_LIT> ( Inst . getOpcode ( ) ) != - <NUM_LIT> ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , VMW_GPR_LOCK , Inst ) ; } } else if ( TII -> isSMRD ( Inst ) ) { ScoreBrackets -> updateByEvent ( TII , TRI , MRI , SMEM_ACCESS , Inst ) ; } else if ( Inst . isCall ( ) ) { if ( callWaitsOnFunctionReturn ( Inst ) ) { ScoreBrackets -> applyWaitcnt ( <STR_LIT> :: allZero ( ST -> hasVscnt ( ) ) ) ; } else { ScoreBrackets -> applyWaitcnt ( <STR_LIT> ( ) ) ; } } else { switch ( Inst . getOpcode ( ) ) { case <STR_LIT> :


<s> const <ISA_LIT>RegisterInfo * RI = STI . getRegisterInfo ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const <ISA_LIT>InstrInfo * TII = STI . getInstrInfo ( ) ; Register FPReg = <STR_LIT> ; Register SPReg = <STR_LIT> ; auto LastFrameDestroy = std :: prev ( MBBI , MFI . getCalleeSavedInfo ( ) . size ( ) ) ; uint64_t StackSize = MFI . getStackSize ( ) ; if ( hasFramePointer ) StackSize ++ ; if ( RI -> needsStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) ) { assert ( hasFP ( MF ) && <STR_LIT> ) ; BuildMI ( MBB , LastFrameDestroy , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( const auto & Entry : CSI ) { Register Reg = Entry . getReg ( ) ; unsigned CFIIndex = MF . addFrameInst ( MCCFIInstruction :: createRestore ( nullptr , RI -> getDwarfRegNum ( Reg , true ) ) ) ; BuildMI ( MBB , MBBI , DL , TII -> get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; } if ( hasFramePointer ) {

BuildMI ( MBB , MBBI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( StackSize - <NUM_LIT> ) ;


<s> bool IsFill = false ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : RC = & <STR_LIT> ; IsFill = true ; break ; case <STR_LIT> : RC = & <STR_LIT> ; IsFill = true ; break ; case <STR_LIT> : RC = & <STR_LIT> ; IsFill = true ; break ; case <STR_LIT> : RC = & <STR_LIT> ; IsFill = true ; break ; case <STR_LIT> : RC = & <STR_LIT> ; IsFill = true ; break ; case <STR_LIT> : RC = & <STR_LIT> ; IsFill = true ; break ; case <STR_LIT> : RC = & <STR_LIT> ; IsFill = true ; break ; case <STR_LIT> : RC = & <STR_LIT> ; IsFill = true ; break ; case <STR_LIT> : RC = & <STR_LIT> ; IsSpill = true ; break ; case <STR_LIT> : RC = & <STR_LIT> ; IsSpill = true ; break ; case <STR_LIT> : RC = & <STR_LIT> ; IsSpill = true ; break ; case <STR_LIT> : RC = & <STR_LIT> ; IsSpill = true ; break ; case <STR_LIT> :


<s> static inline hashval_t hash ( tree_map * m ) {


<s> unsigned Other = MCELF :: getOther ( SymbolData ) << <NUM_LIT> ; Other &= ~ ELF :: STO_<ISA_LIT>64_LOCAL_MASK ; Other |= ( MCELF :: getOther ( Data ) << <NUM_LIT> ) & ELF :: STO_<ISA_LIT>64_LOCAL_MASK ;

MCELF :: setOther ( SymbolData , Other >> <NUM_LIT> ) ;


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> else if ( Opcode != <STR_LIT> ) return None ; if ( ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isReg ( ) || ! MI . getOperand ( <NUM_LIT> ) . isImm ( ) ) return None ; Offset = MI . getOperand ( <NUM_LIT> ) . getImm ( ) * Sign ;

return RegImmPair { MI . getOperand ( <NUM_LIT> ) . getReg ( ) , Offset } ;


<s> unsigned <ISA_LIT>FastISel :: fastEmitInst_r ( unsigned MachineInstOpcode , const TargetRegisterClass * RC , unsigned Op0 ) {

const TargetRegisterClass * UseRC = ( RC == & <STR_LIT> ? & <STR_LIT> :


<s> CallReturnHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , MachineInstrBuilder & MIB ) : <ISA_LIT>IncomingValueHandler ( MIRBuilder , MRI ) , MIB ( MIB ) {


<s> LLT StoreVT = MRI . getType ( Reg ) ; if ( ! StoreVT . isVector ( ) || StoreVT . getElementType ( ) != S16 ) return Reg ; auto Unmerge = B . buildUnmerge ( S16 , Reg ) ; SmallVector < Register , <NUM_LIT> > WideRegs ;

for ( int I = <NUM_LIT> , E = Unmerge -> getNumOperands ( ) - <NUM_LIT> ; I != E ; ++ I ) WideRegs . push_back ( Unmerge . getReg ( I ) ) ;


<s> unsigned ResultReg = createResultReg ( RC ) ; addFullAddress ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) , ResultReg ) , AM ) ; return ResultReg ;


<s> if ( ! arch && strcmp ( argv [ <NUM_LIT> ] , <STR_LIT> ) ) return NULL ; if ( arch ) cpu = <STR_LIT> ; return concat ( <STR_LIT> , argv [ <NUM_LIT> ] , <STR_LIT> , cpu , NULL ) ;


<s> if ( TARGET_DEBUG_D_MODE ) { fprintf ( stderr , <STR_LIT> , ( long ) fntype ) ; if ( ! fntype ) fputc ( '\n' , stderr ) ; else { tree ret_type = TREE_TYPE ( fntype ) ;

fprintf ( stderr , <STR_LIT> , get_tree_code_name ( TREE_CODE ( fntype ) ) , get_tree_code_name ( TREE_CODE ( ret_type ) ) ) ;


<s> uint32_t getAddrMode3OpValue ( const MachineInstr & MI , unsigned Op ) const { return <NUM_LIT> ;


<s> SDValue R600TargetLowering :: LowerEXTRACT_VECTOR_ELT ( SDValue Op , SelectionDAG & DAG ) const { SDLoc DL ( Op ) ; SDValue Vector = Op . getOperand ( <NUM_LIT> ) ; SDValue Index = Op . getOperand ( <NUM_LIT> ) ;

if ( isa < ConstantSDNode > ( Index ) || Vector . getOpcode ( ) == <STR_LIT> ) return Op ;


<s> return Kind == k_Register && Reg . isVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const {


<s> unsigned Q = fieldFromInstruction32 ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( Q ) { if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } else { if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; } Inst . addOperand ( MCOperand :: CreateImm ( imm ) ) ; switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeDPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( ! Check ( S , DecodeQPRRegisterClass ( Inst , Rd , Address , Decoder ) ) ) return MCDisassembler :: Fail ; break ; default : break ;


<s> void <ISA_LIT>InstPrinter :: printVectorListThree ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) + <NUM_LIT> ) ; O << <STR_LIT> ;


<s> bool isImmediate ( const MachineOperand & MO ) const { int64_t V ; return checkForImmediate ( MO , V ) ;


<s> if ( ! Amount ) break ; LLVM_FALLTHROUGH ; } case Sub : assert ( Amount > <NUM_LIT> ) ; if ( Amount == SlotSize ) { unsigned RegA = Is64Bit ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , I , DL , TII -> get ( Is64Bit ? <STR_LIT> : <STR_LIT> ) ) . addReg ( RegA , RegState :: Undef ) ; } else { BuildMI ( * MBB , I , DL , TII -> get ( getSubOpcode ( Is64BitAlloca , Amount ) ) , StackPtr ) . addReg ( StackPtr ) . addImm ( Amount ) ; } break ; case Probe : if ( ! NoStackArgProbe ) { unsigned RegA = Is64BitAlloca ? <STR_LIT> : <STR_LIT> ; BuildMI ( * MBB , MI , DL , TII -> get ( TargetOpcode :: COPY ) , RegA ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ;

STI -> getFrameLowering ( ) -> emitStackProbe ( * MBB -> getParent ( ) , * MBB , MI , DL , false ) ;


<s> pass_rl78_move_elim ( gcc :: context * ctxt ) : rtl_opt_pass ( pass_data_rl78_move_elim , ctxt ) {


<s> MachineInstr * MI = & * I ; Register CmpReg1 = <NUM_LIT> , CmpReg2 = <NUM_LIT> ; int CmpMask = <NUM_LIT> , CmpValue = <NUM_LIT> ; if ( ! TII -> analyzeCompare ( * MI , CmpReg1 , CmpReg2 , CmpMask , CmpValue ) ) continue ; MachineBasicBlock * TBB = nullptr , * FBB = nullptr ; SmallVector < MachineOperand , <NUM_LIT> > Cond ; if ( TII -> analyzeBranch ( * MI -> getParent ( ) , TBB , FBB , Cond , false ) ) continue ; Comparison :: Kind Cmp = getComparisonKind ( MI -> getOpcode ( ) , nullptr , nullptr , <NUM_LIT> ) ; if ( Cmp == <NUM_LIT> ) continue ; if ( CmpReg2 != <NUM_LIT> && CmpReg2 == Reg ) Cmp = Comparison :: getSwappedComparison ( Cmp ) ; if ( Comparison :: isSigned ( Cmp ) ) return false ;

if ( ( Cmp & Comparison :: G ) || Cmp == Comparison :: NE ) return false ;


<s> if ( Addr . getOpcode ( ) == <STR_LIT> ) { Target = Addr . getOperand ( <NUM_LIT> ) ; return true ; } return false ;


<s> if ( data_ref_p ( op ) ) return true ;