<s> MRI . setRegBank ( Tmp , RegBank ) ; MachineInstr & InsertInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: G_INSERT ) , Tmp ) . addReg ( DefReg ) . addReg ( I . getOperand ( Idx ) . getReg ( ) ) . addImm ( ( Idx - <NUM_LIT> ) * SrcSize ) ; DefReg = Tmp ; if ( ! select ( InsertInst , CoverageInfo ) ) return false ; }

MachineInstr & CopyInst = * BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , DstReg ) . addReg ( DefReg ) ;


<s> if ( Size == <NUM_LIT> ) return ( getGeneration ( ) >= SOUTHERN_ISLANDS ) ; return false ;


<s> Types . push_back ( v4i32 ) ; NeedToReplace = true ; Name = Name + <STR_LIT> ; } else if ( Arg -> getType ( ) -> isVectorTy ( ) && Arg -> getType ( ) -> getVectorNumElements ( ) == <NUM_LIT> && Arg -> getType ( ) -> getVectorElementType ( ) == Type :: getInt32Ty ( I . getContext ( ) ) ) { Type * ElementTy = Arg -> getType ( ) -> getVectorElementType ( ) ; std :: string TypeName = <STR_LIT> ; InsertElementInst * Def = cast < InsertElementInst > ( Arg ) ; Args . push_back ( Def -> getOperand ( <NUM_LIT> ) ) ;


<s> switch ( Constraint [ <NUM_LIT> ] ) { case 'q' : case 'v' : if ( Subtarget . useHVXOps ( ) ) return C_Register ;


<s> <ISA_LIT>65816GenSubtargetInfo ( TT , CPU , FS ) { std :: string CPUName = CPU ;

ParseSubtargetFeatures ( CPUName , FS ) ;


<s> return <ISA_LIT>ArchVersion == <ISA_LIT>32I ;


<s> bool isMem ( ) const override { return isMemImm ( ) || isMemRegImm ( ) || isMemRegReg ( ) ;


<s> rtx src = gen_rtx_UNSPEC ( d -> vmode , gen_rtvec ( <NUM_LIT> , d -> op0 ) , UNSPEC_REV ) ; emit_set_insn ( d -> target , src ) ;


<s> static void buildPrologSpill ( const GCNSubtarget & ST , const <ISA_LIT>RegisterInfo & TRI , const <ISA_LIT>MachineFunctionInfo & FuncInfo , LivePhysRegs & LiveRegs , MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , const DebugLoc & DL , Register SpillReg , int FI ) { unsigned Opc = ST . enableFlatScratch ( ) ? <STR_LIT> : <STR_LIT> ; MachineFrameInfo & FrameInfo = MF . getFrameInfo ( ) ; MachinePointerInfo PtrInfo = MachinePointerInfo :: getFixedStack ( MF , FI ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOStore , FrameInfo . getObjectSize ( FI ) , FrameInfo . getObjectAlign ( FI ) ) ;


<s> MVT EltVT = Op . getSimpleValueType ( ) ; assert ( ( EltVT == <STR_LIT> ) && <STR_LIT> ) ; assert ( ( VecVT . getVectorNumElements ( ) <= <NUM_LIT> || Subtarget . hasBWI ( ) ) && <STR_LIT> ) ; if ( ! isa < ConstantSDNode > ( Idx ) ) { MVT ExtVT = ( VecVT == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , dl , ExtVT , Vec ) ; SDValue Elt = DAG . getNode ( <STR_LIT> , dl , ExtVT . getVectorElementType ( ) , Ext , Idx ) ; return DAG . getNode ( <STR_LIT> , dl , EltVT , Elt ) ; }

unsigned IdxVal = cast < ConstantSDNode > ( Idx ) -> getZExtValue ( ) ;


<s> if ( InsertPt != MBB . end ( ) ) { DL = InsertPt -> getDebugLoc ( ) ; } BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , OffsetReg ) . addImm ( StackSize ) ; auto * SPSymbol = MF . createExternalSymbolName ( <STR_LIT> ) ;

BuildMI ( MBB , InsertPt , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( OffsetReg ) ;


<s> bool <ISA_LIT>GlobalMerge :: runOnFunction ( Function & F ) {


<s> llvm_unreachable ( <STR_LIT> ) ; } const uint32_t Binary = getBinaryCodeForInstr ( MI , Fixups , STI ) ; emitConstant ( Binary , Desc . getSize ( ) , OS ) ; ++ MCNumEmitted ;


<s> assert ( Offset . isImm ( ) && <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , BaseAddr . getReg ( ) ) ; unsigned OffsetVal = Offset . getImm ( ) ; if ( OffsetVal ) { O << <STR_LIT> << Offset . getImm ( ) ;


<s> std :: string <STR_LIT> ( const Triple & TT ) { std :: string FS ; FS = <STR_LIT> ; return FS ;


<s> MachineInstr * EarlierMI = MF . CloneMachineInstr ( & * MI ) ; MBB -> insert ( MI , EarlierMI ) ; MachineOperand & HighRegOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowRegOp = MI -> getOperand ( <NUM_LIT> ) ; HighRegOp . setReg ( RI . getSubReg ( HighRegOp . getReg ( ) , <STR_LIT> ) ) ; LowRegOp . setReg ( RI . getSubReg ( LowRegOp . getReg ( ) , <STR_LIT> ) ) ; MachineOperand & HighOffsetOp = EarlierMI -> getOperand ( <NUM_LIT> ) ; MachineOperand & LowOffsetOp = MI -> getOperand ( <NUM_LIT> ) ; LowOffsetOp . setImm ( LowOffsetOp . getImm ( ) + <NUM_LIT> ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ; EarlierMI -> getOperand ( <NUM_LIT> ) . setIsKill ( false ) ;

unsigned HighOpcode = getOpcodeForOffset ( NewOpcode , HighOffsetOp . getImm ( ) ) ;


<s> return ( uint64x2_t ) __builtin_neon_vqsubuv2di ( ( int64x2_t ) __a , ( int64x2_t ) __b ) ;


<s> enum indirect_thunk_prefix indirect_thunk_need_prefix ( rtx_insn * insn ) { enum indirect_thunk_prefix need_prefix ; if ( ( cfun -> machine -> indirect_branch_type == indirect_branch_thunk_extern ) && ix86_notrack_prefixed_insn_p ( insn ) ) { need_prefix = indirect_thunk_prefix_nt ; } else need_prefix = indirect_thunk_prefix_none ; return need_prefix ;


<s> } if ( Subtarget . hasInt256 ( ) ) { assert ( VT . getSizeInBits ( ) > <NUM_LIT> && <STR_LIT> ) ; if ( InVT . getVectorNumElements ( ) != NumElts ) return DAG . getNode ( Op . getOpcode ( ) , dl , VT , In ) ; unsigned ExtOpc = Opc == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( ExtOpc , dl , VT , In ) ; } if ( Subtarget . hasAVX ( ) ) { assert ( VT . is256BitVector ( ) && <STR_LIT> ) ; MVT HalfVT = VT . getHalfNumVectorElementsVT ( ) ; int HalfNumElts = HalfVT . getVectorNumElements ( ) ; unsigned NumSrcElts = InVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > HiMask ( NumSrcElts , SM_SentinelUndef ) ; for ( int i = <NUM_LIT> ; i != HalfNumElts ; ++ i ) HiMask [ i ] = HalfNumElts + i ; SDValue Lo = DAG . getNode ( Opc , dl , HalfVT , In ) ; SDValue Hi = DAG . getVectorShuffle ( InVT , dl , In , DAG . getUNDEF ( InVT ) , HiMask ) ; Hi = DAG . getNode ( Opc , dl , HalfVT , Hi ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Lo , Hi ) ; } assert ( Opc == <STR_LIT> && <STR_LIT> ) ; assert ( VT . is128BitVector ( ) && InVT . is128BitVector ( ) && <STR_LIT> ) ; SDValue Curr = In ; SDValue SignExt = Curr ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , const MCRegisterInfo & mri ) : MRI ( mri ) , MCII ( mcii ) {


<s> for ( auto & CS : CSI ) { unsigned Reg = CS . getReg ( ) ; int Offset = getRegSpillOffset ( MF , Reg ) ; if ( Offset ) { if ( <STR_LIT> . contains ( Reg ) && StartSPOffset > Offset ) { LowGPR = Reg ; StartSPOffset = Offset ; } Offset -= <STR_LIT> ; int FrameIdx = MFFrame . CreateFixedSpillStackObject ( <NUM_LIT> , Offset ) ; CS . setFrameIdx ( FrameIdx ) ; } else CS . setFrameIdx ( INT32_MAX ) ; } ZFI -> setRestoreGPRRegs ( LowGPR , HighGPR , StartSPOffset ) ; if ( IsVarArg ) { unsigned FirstGPR = ZFI -> getVarArgsFirstGPR ( ) ; if ( FirstGPR < <STR_LIT> ) { unsigned Reg = <STR_LIT> [ FirstGPR ] ; int Offset = getRegSpillOffset ( MF , Reg ) ; if ( StartSPOffset > Offset ) { LowGPR = Reg ; StartSPOffset = Offset ; } } } ZFI -> setSpillGPRRegs ( LowGPR , HighGPR , StartSPOffset ) ; int CurrOffset = - <STR_LIT> ; if ( usePackedStack ( MF ) ) CurrOffset += StartSPOffset ; for ( auto & CS : CSI ) { if ( CS . getFrameIdx ( ) != INT32_MAX ) continue ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( secondReg && ! TargetRegisterInfo :: isPhysicalRegister ( cmpOp2 ) ) { MachineInstr * def = MRI . getVRegDef ( cmpOp2 ) ; if ( def -> getOpcode ( ) == TargetOpcode :: COPY ) return false ; } } ++ II ; for ( MachineBasicBlock :: iterator localII = II ; localII != end ; ++ localII ) { if ( ! commonChecksToProhibitNewValueJump ( optLocation , localII ) ) return false ; if ( localII -> modifiesRegister ( pReg , TRI ) || localII -> readsRegister ( pReg , TRI ) ) return false ; if ( localII -> modifiesRegister ( cmpReg1 , TRI ) || ( secondReg && localII -> modifiesRegister ( cmpOp2 , TRI ) ) ) return false ; }


<s> assert ( TTI -> getPrefetchDistance ( ) && <STR_LIT> ) ; bool MadeChange = false ;

for ( auto I = LI -> begin ( ) , IE = LI -> end ( ) ; I != IE ; ++ I ) for ( auto L = df_begin ( * I ) , LE = df_end ( * I ) ; L != LE ; ++ L ) MadeChange |= runOnLoop ( * L ) ;


<s> ZExtInst * ZextOffs = dyn_cast < ZExtInst > ( Offsets ) ; if ( ZextOffs ) Offsets = ZextOffs -> getOperand ( <NUM_LIT> ) ; FixedVectorType * OffsetType = cast < FixedVectorType > ( Offsets -> getType ( ) ) ; if ( ! ZextOffs || cast < FixedVectorType > ( ZextOffs -> getDestTy ( ) ) -> getElementType ( ) -> getScalarSizeInBits ( ) != <NUM_LIT> ) if ( ! checkOffsetSize ( Offsets , OffsetsElemCount ) ) return nullptr ; if ( Ty != Offsets -> getType ( ) ) { if ( ( Ty -> getElementType ( ) -> getScalarSizeInBits ( ) < OffsetType -> getElementType ( ) -> getScalarSizeInBits ( ) ) ) {

Offsets = Builder . CreateTrunc ( Offsets , Ty ) ;


<s> if ( ! new_reg ) { new_reg = gen_reg_rtx ( GET_MODE ( and_base ) ) ; and_mask = XEXP ( and_op , <NUM_LIT> ) ; } rtx copy = gen_rtx_SET ( new_reg , and_base ) ; rtx_insn * new_insn = emit_insn_after ( copy , and_insn ) ; set_block_for_insn ( new_insn , BLOCK_FOR_INSN ( and_insn ) ) ; df_insn_rescan ( new_insn ) ; } XEXP ( mem , <NUM_LIT> ) = gen_rtx_AND ( GET_MODE ( new_reg ) , new_reg , and_mask ) ;


<s> static unsigned findScratchNonCalleeSaveRegister ( MachineBasicBlock * MBB ) { MachineFunction * MF = MBB -> getParent ( ) ; if ( & MF -> front ( ) == MBB ) return <STR_LIT> ; RegScavenger RS ; RS . enterBasicBlock ( MBB ) ; if ( ! RS . isRegUsed ( <STR_LIT> ) ) return <STR_LIT> ; const <ISA_LIT>Subtarget & Subtarget = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ;

const <ISA_LIT>RegisterInfo * RegInfo = Subtarget . getRegisterInfo ( ) ;


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( bool _is64Bit , uint8_t OSABI , bool _isN64 , bool IsLittleEndian ) : MCELFObjectTargetWriter ( _is64Bit , OSABI , ELF :: EM_MIPS , ( _isN64 ) ? true : false , _isN64 ) {


<s> int count ATTRIBUTE_UNUSED ; machine_mode ag_mode ATTRIBUTE_UNUSED ; if ( ! use_vfp_abi ( pcs_variant , false ) ) return false ; return aapcs_vfp_is_call_or_return_candidate ( pcs_variant , mode , type , & ag_mode , & count ) ;


<s> if ( IsVGPR ) I . addOperand ( * MF , MachineOperand :: CreateReg ( <STR_LIT> , false , true ) ) ;

return RBI . constrainGenericRegister ( DstReg , IsVGPR ? <STR_LIT> : <STR_LIT> , * MRI ) ;


<s> SDLoc DL ( N ) ; unsigned Opc = <STR_LIT> ; SDValue Op0 = N0 . getOperand ( <NUM_LIT> ) ; SDValue Op1 = N1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt0 . getOpcode ( ) == <STR_LIT> || ShAmt0 . getOpcode ( ) == <STR_LIT> ) { Opc = <STR_LIT> ; std :: swap ( Op0 , Op1 ) ; std :: swap ( ShAmt0 , ShAmt1 ) ; std :: swap ( ShMsk0 , ShMsk1 ) ; } auto GetFunnelShift = [ & DAG , & DL , VT , Opc , & ShiftVT ] ( SDValue Op0 , SDValue Op1 , SDValue Amt ) { if ( Opc == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; return DAG . getNode ( Opc , DL , VT , Op0 , Op1 , DAG . getNode ( <STR_LIT> , DL , ShiftVT , Amt ) ) ; } ; if ( ShAmt1 . getOpcode ( ) == <STR_LIT> ) { SDValue Mask = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( auto * MaskC = dyn_cast < ConstantSDNode > ( Mask ) ) { unsigned InnerShift = ( <STR_LIT> == Opc ? <STR_LIT> : <STR_LIT> ) ; SDValue ShAmt1Op0 = ShAmt1 . getOperand ( <NUM_LIT> ) ; if ( ShAmt1Op0 . getOpcode ( ) == <STR_LIT> ) ShAmt1Op0 = ShAmt1Op0 . getOperand ( <NUM_LIT> ) ; if ( MaskC -> getSExtValue ( ) == ( Bits - <NUM_LIT> ) && ( ShAmt1Op0 == ShAmt0 || ShAmt1Op0 == ShMsk0 ) ) { if ( Op1 . getOpcode ( ) == InnerShift && isa < ConstantSDNode > ( Op1 . getOperand ( <NUM_LIT> ) ) && Op1 . getConstantOperandAPInt ( <NUM_LIT> ) . isOneValue ( ) ) { return GetFunnelShift ( Op0 , Op1 . getOperand ( <NUM_LIT> ) , ShAmt0 ) ; } if ( InnerShift == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> && Op1 . getOperand ( <NUM_LIT> ) == Op1 . getOperand ( <NUM_LIT> ) ) { return GetFunnelShift ( Op0 , Op1 . getOperand ( <NUM_LIT> ) , ShAmt0 ) ; } }


<s> dbgs ( ) << <STR_LIT> << PrintReg ( getBBSelectRegOut ( ) , TRI ) << <STR_LIT> ; dumpDepth ( depth ) ;

if ( getSucc ( ) ) dbgs ( ) << <STR_LIT> << getSucc ( ) -> getNumber ( ) << <STR_LIT> ;


<s> return SelectImm ( Addr . getOperand ( <NUM_LIT> ) , Base ) && SelectImm ( Addr . getOperand ( <NUM_LIT> ) , Offset ) ; } if ( SelectImm ( Addr , Base ) ) { assert ( Addr . getValueType ( ) . isSimple ( ) && <STR_LIT> ) ;

Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , Addr . getValueType ( ) . getSimpleVT ( ) ) ;


<s> JumpTableSDNode * JT = cast < JumpTableSDNode > ( Op ) ; DebugLoc dl = JT -> getDebugLoc ( ) ; EVT PtrVT = getPointerTy ( ) ; switch ( getTargetMachine ( ) . getCodeModel ( ) ) { case CodeModel :: Small : return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT ) , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; case CodeModel :: Large : return DAG . getNode ( <STR_LIT> , dl , PtrVT , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) , DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , <STR_LIT> ) ) ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> bool AMDGPUInstrInfo :: canFoldMemoryOperand ( const MachineInstr * MI , ArrayRef < unsigned > Ops ) const { return false ;


<s> SmallVector < const User * , <NUM_LIT> > Stack ( GV -> users ( ) ) ; while ( ! Stack . empty ( ) ) {

const User * U = Stack . pop_back_val ( ) ;


<s> StringRef getSamplerAddressingModeName ( SamplerAddressingMode e ) { switch ( e ) { CASE ( SamplerAddressingMode , None ) CASE ( SamplerAddressingMode , ClampToEdge ) CASE ( SamplerAddressingMode , Clamp ) CASE ( SamplerAddressingMode , Repeat ) CASE ( SamplerAddressingMode , RepeatMirrored ) break ; } llvm_unreachable ( <STR_LIT> ) ;


<s> bool <ISA_LIT>TargetLowering :: hasSPE ( ) const {


<s> llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> s390_expand_cs_tdsi ( mode , btarget , vtarget , mem , cmp , new_rtx , is_weak ) ; break ; case E_HImode : case E_QImode : s390_expand_cs_hqi ( mode , btarget , vtarget , mem , cmp , new_rtx , is_weak ) ; break ;


<s> if ( MO . isReg ( ) ) return MRI . getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) ) ; assert ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: SymbolRef ) ; assert ( false && <STR_LIT> ) ;


<s> <ISA_LIT>MCLowerPrePass ( ) : ModulePass ( ID ) {


<s> MCInst mci ; mci . setOpcode ( <STR_LIT> ) ; AddFunctionStartAddressMetadata ( ) ; EmitMCInstruction ( mci ) ;


if ( SDValue PSHUFB = lowerShuffleWithPSHUFB ( DL , <STR_LIT> , Mask , V1 , V2 , Zeroable , Subtarget , DAG ) ) return PSHUFB ;


<s> const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>InstrInfo * TII = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) . getInstrInfo ( ) ; bool Done = rewrite<ISA_LIT>FrameIndex ( MI , i , BaseReg , Off , TII ) ; assert ( Done && <STR_LIT> ) ; ( void ) Done ;


<s> print ( dbgs ( ) , ValueMap , <STR_LIT> ) ; dbgs ( ) << '\n' ; print ( dbgs ( ) , MetadataMap , <STR_LIT> ) ;


<s> if ( ! TARGET_AVX512F ) return NULL_TREE ; if ( ( TREE_CODE ( index_type ) != INTEGER_TYPE && ! POINTER_TYPE_P ( index_type ) ) || ( TYPE_MODE ( index_type ) != SImode && TYPE_MODE ( index_type ) != DImode ) ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) > POINTER_SIZE ) return NULL_TREE ; if ( TYPE_PRECISION ( index_type ) < POINTER_SIZE && TYPE_UNSIGNED ( index_type ) ) return NULL_TREE ; if ( scale <= <NUM_LIT> || scale > <NUM_LIT> || ( scale & ( scale - <NUM_LIT> ) ) != <NUM_LIT> ) return NULL_TREE ; si = TYPE_MODE ( index_type ) == SImode ; switch ( TYPE_MODE ( vectype ) ) { case E_V8DFmode : code = si ? IX86_BUILTIN_SCATTERALTSIV8DF : IX86_BUILTIN_SCATTERDIV8DF ;


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ) ; TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; SavedRegs . set ( <STR_LIT> ) ;


<s> const <ISA_LIT>MachineFunctionInfo * AFI = MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

return AFI -> isInterruptOrSignalHandler ( ) ? CSR_Interrupts_SaveList : CSR_Normal_SaveList ;


<s> FunctionPass * llvm :: create<ISA_LIT>DelJmpPass ( <ISA_LIT>TargetMachine & tm ) {


<s> enum attr_itanium_class dep_class ; enum attr_itanium_class insn_class ; insn_class = ia64_safe_itanium_class ( insn ) ; dep_class = ia64_safe_itanium_class ( dep_insn ) ; if ( dep_type == REG_DEP_TRUE && ( dep_class == ITANIUM_CLASS_ST || dep_class == ITANIUM_CLASS_STF ) && ( insn_class == ITANIUM_CLASS_BR || insn_class == ITANIUM_CLASS_SCALL ) ) return <NUM_LIT> ; if ( dw == MIN_DEP_WEAK ) return PARAM_VALUE ( PARAM_SCHED_MEM_TRUE_DEP_COST ) ; else if ( dw > MIN_DEP_WEAK ) { if ( mflag_sched_fp_mem_deps_zero_cost && dep_class == ITANIUM_CLASS_STF ) return <NUM_LIT> ; else return cost ; }

if ( dep_type != REG_DEP_OUTPUT ) return cost ;


<s> for ( unsigned I = <NUM_LIT> ; I < NumAttr ; ++ I ) { F . removeFnAttr ( AttributeNames [ I ] ) ; if ( NewAttrs [ I ] ) {

LLVM_DEBUG ( dbgs ( ) << '\t' << NewAttrs [ I ] -> getAsString ( ) << '\n' ) ;


<s> SDValue Flag = EmitCMP ( LHS , RHS , TargetCC , CC , dl , DAG ) ;

return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Chain , Dest , TargetCC , Flag ) ;


<s> void printJT2BlockOperand ( const MCInst * MI , unsigned OpNum ) {


<s> const TargetInstrDesc & TID = MI . getDesc ( ) ; unsigned Reloc = ( ( TID . TSFlags & <STR_LIT> ) == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; emitConstPoolAddress ( MO . getIndex ( ) , Reloc ) ; } else if ( MO . isJTI ( ) ) emitJumpTableAddress ( MO . getIndex ( ) , <STR_LIT> ) ; else if ( MO . isMBB ( ) ) emitMachineBasicBlock ( MO . getMBB ( ) , <STR_LIT> ) ; else { cerr << MO ; llvm_unreachable ( <NUM_LIT> ) ; } return <NUM_LIT> ;


<s> for ( Iter I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( ! hasUnoccupiedSlot ( & * I ) ) continue ; ++ FilledSlots ; Changed = true ; if ( ! DisableDelaySlotFiller && ( TM . getOptLevel ( ) != CodeGenOpt :: None ) ) { if ( searchBackward ( MBB , I ) ) continue ; if ( I -> isTerminator ( ) ) {

if ( searchSuccBBs ( MBB , I ) ) continue ;


<s> case <STR_LIT> : { MachineFunction & MF = * MBB . getParent ( ) ; unsigned CPI = Orig . getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; BuildMI ( MBB , I , Orig . getDebugLoc ( ) , get ( Opcode ) , DestReg ) . addConstantPoolIndex ( CPI ) . addImm ( PCLabelId ) . cloneMemRefs ( Orig ) ; break ; }


<s> void <ISA_LIT>InstPrinter :: printFPR ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {

const MCOperand & MO = MI -> getOperand ( OpNo ) ;


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) {

return new <ISA_LIT>TargetELFStreamer ( S ) ;


<s> const std :: vector < CalleeSavedInfo > & CSI = MFI . getCalleeSavedInfo ( ) ; for ( std :: vector < CalleeSavedInfo > :: const_iterator I = CSI . begin ( ) , E = CSI . end ( ) ; I != E ; ++ I ) { int64_t Offset = MFI . getObjectOffset ( I -> getFrameIdx ( ) ) ; unsigned Reg = I -> getReg ( ) ; unsigned DReg = MRI -> getDwarfRegNum ( Reg , true ) ; unsigned CFIIndex = MMI . addFrameInst ( MCCFIInstruction :: createOffset ( nullptr , DReg , Offset ) ) ; BuildMI ( MBB , MBBI , dl , TII . get ( TargetOpcode :: CFI_INSTRUCTION ) ) . addCFIIndex ( CFIIndex ) ; }


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> <STR_LIT> Pred = getInstrPredicate ( First , PredReg ) ; DebugLoc DL = First -> getDebugLoc ( ) ; MachineInstr * Merged = nullptr ; if ( Cand . CanMergeToLSDouble ) Merged = CreateLoadStoreDouble ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged && Cand . CanMergeToLSMulti ) Merged = CreateLoadStoreMulti ( MBB , InsertBefore , Offset , Base , BaseKill , Opcode , Pred , PredReg , DL , Regs ) ; if ( ! Merged ) return nullptr ; iterator EarliestI ( Cand . Instrs [ Cand . EarliestMIIdx ] ) ; bool EarliestAtBegin = false ; if ( EarliestI == MBB . begin ( ) ) { EarliestAtBegin = true ; } else { EarliestI = std :: prev ( EarliestI ) ; } for ( MachineInstr * MI : Cand . Instrs ) MBB . erase ( MI ) ; if ( EarliestAtBegin ) EarliestI = MBB . begin ( ) ; else EarliestI = std :: next ( EarliestI ) ; auto FixupRange = make_range ( EarliestI , iterator ( Merged ) ) ; if ( isLoadSingle ( Opcode ) ) { for ( MachineInstr & MI : FixupRange ) { for ( unsigned & ImpDefReg : ImpDefs ) { for ( MachineOperand & MO : MI . implicit_operands ( ) ) { if ( ! MO . isReg ( ) || MO . getReg ( ) != ImpDefReg ) continue ; if ( MO . readsReg ( ) ) MO . setIsUndef ( ) ; else if ( MO . isDef ( ) ) ImpDefReg = <NUM_LIT> ; } } } MachineInstrBuilder MIB ( * Merged -> getParent ( ) -> getParent ( ) , Merged ) ; for ( unsigned ImpDef : ImpDefs ) MIB . addReg ( ImpDef , RegState :: ImplicitDefine ) ; } else { assert ( isi32Store ( Opcode ) || Opcode == <STR_LIT> || Opcode == <STR_LIT> ) ; for ( MachineInstr & MI : FixupRange ) { for ( MachineOperand & MO : MI . uses ( ) ) { if ( ! MO . isReg ( ) || ! MO . isKill ( ) ) continue ; if ( KilledRegs . count ( MO . getReg ( ) ) ) MO . setIsKill ( false ) ; } } assert ( ImpDefs . empty ( ) ) ; }


<s> break ; case LT : libfunc = op_mode == DFmode ? ltdf_libfunc : ltsf_libfunc ; break ; case LE : libfunc = op_mode == DFmode ? ledf_libfunc : lesf_libfunc ; break ; default : gcc_unreachable ( ) ; } start_sequence ( ) ; cmp = emit_library_call_value ( libfunc , <NUM_LIT> , LCT_CONST , SImode , op0 , op_mode , op1 , op_mode ) ; insns = get_insns ( ) ; end_sequence ( ) ; emit_libcall_block ( insns , cmp , cmp , gen_rtx_fmt_ee ( code , SImode , op0 , op1 ) ) ;

return gen_rtx_fmt_ee ( jump_code , mode , cmp , const0_rtx ) ;


<s> return ParseImmediate ( Operands , <NUM_LIT> , true ) ;


<s> static LaneBitmask getUsedRegMask ( const MachineOperand & MO , const MachineRegisterInfo & MRI , const LiveIntervals & LIS ) {

assert ( MO . isUse ( ) && MO . isReg ( ) && Register :: isVirtualRegister ( MO . getReg ( ) ) ) ;


<s> bool isAligned = ( RI . getStackAlignment ( ) >= <NUM_LIT> ) || RI . needsStackRealignment ( MF ) ; unsigned Opc = getLoadRegOpcode ( DestReg , RC , isAligned , TM ) ;

DebugLoc DL = DebugLoc :: getUnknownLoc ( ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ( CouldJump ? <STR_LIT> : <STR_LIT> ) << ( CouldCall ? <STR_LIT> : <STR_LIT> ) << <STR_LIT> << MBB . getName ( ) << <STR_LIT> ) ; const <ISA_LIT>InstrInfo * TII = static_cast < const <ISA_LIT>InstrInfo * > ( MBB . getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ) ; unsigned HintNum = <NUM_LIT> ; if ( CouldCall ) HintNum |= <NUM_LIT> ; if ( CouldJump ) HintNum |= <NUM_LIT> ; assert ( HintNum != <NUM_LIT> && <STR_LIT> ) ; auto MBBI = MBB . begin ( ) ;

for ( ; MBBI != MBB . end ( ) && MBBI -> isMetaInstruction ( ) ; ++ MBBI ) ;


<s> return isMemDisp12 ( BDMem , ADDR64Reg ) ;


<s> MachineRegisterInfo & MRI = MBB . getParent ( ) -> getRegInfo ( ) ; assert ( MRI . getRegClass ( DstReg ) == & <STR_LIT> && <STR_LIT> ) ; if ( Cond . size ( ) == <NUM_LIT> ) { unsigned SReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . add ( Cond [ <NUM_LIT> ] ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) . addReg ( SReg ) ; } else if ( Cond . size ( ) == <NUM_LIT> ) { assert ( Cond [ <NUM_LIT> ] . isImm ( ) && <STR_LIT> ) ; switch ( Cond [ <NUM_LIT> ] . getImm ( ) ) { case <ISA_LIT>InstrInfo :: SCC_TRUE : { unsigned SReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . addImm ( - <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: SCC_FALSE : { unsigned SReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . addImm ( <NUM_LIT> ) . addImm ( - <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: VCCNZ : { MachineOperand RegOp = Cond [ <NUM_LIT> ] ; RegOp . setImplicit ( false ) ; unsigned SReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . add ( RegOp ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( FalseReg ) . addReg ( TrueReg ) . addReg ( SReg ) ; break ; } case <ISA_LIT>InstrInfo :: VCCZ : { MachineOperand RegOp = Cond [ <NUM_LIT> ] ; RegOp . setImplicit ( false ) ; unsigned SReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , SReg ) . add ( RegOp ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( TrueReg ) . addReg ( FalseReg ) . addReg ( SReg ) ; break ; }


<s> unsigned Delta = <NUM_LIT> ; unsigned CPEOffset = UserBBI . postOffset ( CPELogAlign ) + Delta ; if ( isOffsetInRange ( UserOffset , CPEOffset , U ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << printMBBReference ( * UserMBB ) << format ( <STR_LIT> , CPEOffset ) ) ; NewMBB = & * ++ UserMBB -> getIterator ( ) ; int UncondBr = <STR_LIT> ; BuildMI ( UserMBB , DebugLoc ( ) , TII -> get ( UncondBr ) ) . addMBB ( NewMBB ) ; unsigned MaxDisp = getUnconditionalBrDisp ( UncondBr ) ; ImmBranches . push_back ( ImmBranch ( & UserMBB -> back ( ) , MaxDisp , false , UncondBr ) ) ; BBInfo [ UserMBB -> getNumber ( ) ] . Size += Delta ; adjustBBOffsetsAfter ( UserMBB ) ; return ; } } unsigned LogAlign = MF -> getAlignment ( ) ; assert ( LogAlign >= CPELogAlign && <STR_LIT> ) ; unsigned BaseInsertOffset = UserOffset + U . getMaxDisp ( ) ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; BaseInsertOffset -= <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) << <STR_LIT> << LogAlign << '\n' ) ; if ( BaseInsertOffset + <NUM_LIT> >= UserBBI . postOffset ( ) ) { BaseInsertOffset = UserBBI . postOffset ( ) - <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << format ( <STR_LIT> , BaseInsertOffset ) ) ; } unsigned EndInsertOffset = BaseInsertOffset + <NUM_LIT> + CPEMI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; MachineBasicBlock :: iterator MI = UserMI ; ++ MI ; unsigned CPUIndex = CPUserIndex + <NUM_LIT> ; unsigned NumCPUsers = CPUsers . size ( ) ; for ( unsigned Offset = UserOffset + TII -> getInstSizeInBytes ( * UserMI ) ; Offset < BaseInsertOffset ; Offset += TII -> getInstSizeInBytes ( * MI ) , MI = std :: next ( MI ) ) {

assert ( MI != UserMBB -> end ( ) && <STR_LIT> ) ;


<s> DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , MI , dl , NewMCID ) ; switch ( OpTransfer ) { case OT_Operand2 : MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; break ; case OT_Operands02 : { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; break ; } case OT_OperandsXOR : { if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } break ; } case OT_OperandsMovep : case OT_OperandsLwp : case OT_OperandsSwp : { if ( ConsecutiveForward ) { MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI2 -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( OpTransfer == OT_OperandsMovep ) MIB . add ( MI2 -> getOperand ( <NUM_LIT> ) ) ; else MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { MIB . add ( MI2 -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI2 -> getOperand ( <NUM_LIT> ) ) ; if ( OpTransfer == OT_OperandsMovep ) MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; else MIB . add ( MI2 -> getOperand ( <NUM_LIT> ) ) ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MI2 << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; MBB . erase_instr ( MI2 ) ; return true ; } default : llvm_unreachable ( <STR_LIT> ) ; } MIB . setMIFlags ( MI -> getFlags ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * MIB ) ; MBB . erase_instr ( MI ) ; return true ; }


<s> FastISel * <ISA_LIT>TargetLowering :: createFastISel ( FunctionLoweringInfo & FuncInfo , const TargetLibraryInfo * LibInfo ) const { return <STR_LIT> ( FuncInfo , LibInfo ) ;


<s> static void ia64_emit_insn_before ( rtx insn , rtx_insn * before ) {


<s> for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ;

ResultVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ;


<s> case LGKM_CNT : { if ( EventUBs [ SMEM_ACCESS ] > ScoreLBs [ LGKM_CNT ] && EventUBs [ SMEM_ACCESS ] <= ScoreUBs [ LGKM_CNT ] ) { return true ; } int NumEventTypes = <NUM_LIT> ; if ( EventUBs [ LDS_ACCESS ] > ScoreLBs [ LGKM_CNT ] && EventUBs [ LDS_ACCESS ] <= ScoreUBs [ LGKM_CNT ] ) { NumEventTypes ++ ; } if ( EventUBs [ GDS_ACCESS ] > ScoreLBs [ LGKM_CNT ] && EventUBs [ GDS_ACCESS ] <= ScoreUBs [ LGKM_CNT ] ) { NumEventTypes ++ ; } if ( EventUBs [ SQ_MESSAGE ] > ScoreLBs [ LGKM_CNT ] && EventUBs [ SQ_MESSAGE ] <= ScoreUBs [ LGKM_CNT ] ) { NumEventTypes ++ ; }


<s> Type * VecEltTy = MaskTy -> getVectorElementType ( ) ; if ( ! VecEltTy -> isIntegerTy ( ) ) return ; unsigned EltTySize = VecEltTy -> getIntegerBitWidth ( ) ; if ( EltTySize < <NUM_LIT> || EltTySize > ElSize ) return ; unsigned NumElements = MaskTySize / ElSize ; assert ( ( NumElements == <NUM_LIT> || NumElements == <NUM_LIT> || NumElements == <NUM_LIT> || NumElements == <NUM_LIT> ) && <STR_LIT> ) ; ShuffleMask . reserve ( NumElements ) ; unsigned NumElementsPerLane = <NUM_LIT> / ElSize ; unsigned Factor = ElSize / EltTySize ; for ( unsigned i = <NUM_LIT> ; i < NumElements ; ++ i ) { Constant * COp = C -> getAggregateElement ( i * Factor ) ; if ( ! COp ) { ShuffleMask . clear ( ) ; return ;

} else if ( isa < UndefValue > ( COp ) ) {


<s> const <ISA_LIT>TargetMachine & TM = TPC -> getTM < <ISA_LIT>TargetMachine > ( ) ; ST = & TM . getSubtarget < GCNSubtarget > ( F ) ; DA = & getAnalysis < DivergenceAnalysis > ( ) ; HasUnsafeFPMath = hasUnsafeFPMath ( F ) ; AMDGPUA<ISA_LIT> = TM . get<ISA_LIT>AS ( ) ; bool MadeChange = false ; for ( BasicBlock & BB : F ) { BasicBlock :: iterator Next ; for ( BasicBlock :: iterator I = BB . begin ( ) , E = BB . end ( ) ; I != E ; I = Next ) {


<s> uint32_t FixupOffset = Layout . getFragmentOffset ( Fragment ) + Fixup . getOffset ( ) ; unsigned IsPCRel = Writer -> isFixupKindPCRel ( Asm , Fixup . getKind ( ) ) ; unsigned Type = MachO :: <ISA_LIT>_RELOC_HALF ; const MCSymbol * A = & Target . getSymA ( ) -> getSymbol ( ) ; if ( ! A -> getFragment ( ) ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> + A -> getName ( ) + <STR_LIT> ) ; return ; } uint32_t Value = Writer -> getSymbolAddress ( * A , Layout ) ; uint32_t Value2 = <NUM_LIT> ; uint64_t SecAddr = Writer -> getSectionAddress ( A -> getFragment ( ) -> getParent ( ) ) ; FixedValue += SecAddr ; if ( const MCSymbolRefExpr * B = Target . getSymB ( ) ) { const MCSymbol * SB = & B -> getSymbol ( ) ; if ( ! SB -> getFragment ( ) ) { Asm . getContext ( ) . reportError ( Fixup . getLoc ( ) , <STR_LIT> + B -> getSymbol ( ) . getName ( ) + <STR_LIT> ) ; return ; } Type = MachO :: <ISA_LIT>_RELOC_HALF_SECTDIFF ; Value2 = Writer -> getSymbolAddress ( B -> getSymbol ( ) , Layout ) ; FixedValue -= Writer -> getSectionAddress ( SB -> getFragment ( ) -> getParent ( ) ) ; } unsigned ThumbBit = <NUM_LIT> ; unsigned MovtBit = <NUM_LIT> ; switch ( ( unsigned ) Fixup . getKind ( ) ) { default : break ; case <STR_LIT> : MovtBit = <NUM_LIT> ; if ( Asm . isThumbFunc ( A ) ) FixedValue &= <NUM_LIT> ; break ; case <STR_LIT> : if ( Asm . isThumbFunc ( A ) ) FixedValue &= <NUM_LIT> ; MovtBit = <NUM_LIT> ; LLVM_FALLTHROUGH ;


<s> static void nios2_init_fpu_builtins ( int start_code ) { tree fndecl ; char builtin_name [ <NUM_LIT> ] = <STR_LIT> ; unsigned int i , n = strlen ( <STR_LIT> ) ; for ( i = <NUM_LIT> ; i < ARRAY_SIZE ( nios2_fpu_insn ) ; i ++ ) { snprintf ( builtin_name + n , sizeof ( builtin_name ) - n , <STR_LIT> , N2FPU_NAME ( i ) ) ; fndecl = add_builtin_function ( builtin_name , nios2_ftype ( N2FPU_FTCODE ( i ) ) , start_code + i , BUILT_IN_MD , NULL , NULL_TREE ) ; nios2_register_builtin_fndecl ( start_code + i , fndecl ) ;


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; DebugLoc DL = Op . getDebugLoc ( ) ; SDValue CondRes = createFPCmp ( DAG , Op . getOperand ( <NUM_LIT> ) ) ; if ( CondRes . getOpcode ( ) != <STR_LIT> ) return Op ; SDValue CCNode = CondRes . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = ( <STR_LIT> ) cast < ConstantSDNode > ( CCNode ) -> getZExtValue ( ) ;

SDValue BrCode = DAG . getConstant ( getFPBranchCodeFromCond ( CC ) , <STR_LIT> ) ;


<s> if ( MO . getTargetFlags ( ) == <STR_LIT> ) { SmallString < <NUM_LIT> > TempNameStr ; TempNameStr += StringRef ( MO . getSymbolName ( ) ) ; TempNameStr += StringRef ( <STR_LIT> ) ; MCSymbol * Sym = GetExternalSymbolSymbol ( TempNameStr . str ( ) ) ; MCSymbol * & StubSym = MMI -> getObjFileInfo < MachineModuleInfoMachO > ( ) . getFnStubEntry ( Sym ) ; if ( StubSym == <NUM_LIT> ) { TempNameStr . erase ( TempNameStr . end ( ) - <NUM_LIT> , TempNameStr . end ( ) ) ; StubSym = OutContext . GetOrCreateSymbol ( TempNameStr . str ( ) ) ; } SymToPrint = StubSym ; } else { SymToPrint = GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; } if ( SymToPrint -> getName ( ) [ <NUM_LIT> ] != '$' ) O << * SymToPrint ; else O << '(' << * SymToPrint << '(' ; break ; } } switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : O << <STR_LIT> ; PrintPICBaseSymbol ( ) ; O << ']' ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : O << '-' ; PrintPICBaseSymbol ( ) ; break ;

case <STR_LIT> : O << <STR_LIT> ; break ;


<s> break ; default : gcc_unreachable ( ) ; } break ; case FLOAT : switch ( GET_MODE ( operands [ <NUM_LIT> ] ) ) { case SImode : func = <STR_LIT> ; if ( TARGET_ARCH64 ) operands [ <NUM_LIT> ] = gen_rtx_SIGN_EXTEND ( DImode , operands [ <NUM_LIT> ] ) ; break ; case DImode : func = <STR_LIT> ; break ; default : gcc_unreachable ( ) ; } break ; case UNSIGNED_FLOAT : switch ( GET_MODE ( operands [ <NUM_LIT> ] ) ) { case SImode : func = <STR_LIT> ; if ( TARGET_ARCH64 ) operands [ <NUM_LIT> ] = gen_rtx_ZERO_EXTEND ( DImode , operands [ <NUM_LIT> ] ) ; break ; case DImode : func = <STR_LIT> ; break ; default :


<s> assert ( N == <NUM_LIT> && isMemorySIMDNoIndex ( ) && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateReg ( Mem . BaseRegNum ) ) ;


<s> if ( cmpval != <NUM_LIT> && cmpval != <NUM_LIT> ) return - <NUM_LIT> ; int t ; if ( t_reg_operand ( XEXP ( op , <NUM_LIT> ) , GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) ) t = <NUM_LIT> ; else if ( negt_reg_operand ( XEXP ( op , <NUM_LIT> ) , GET_MODE ( XEXP ( op , <NUM_LIT> ) ) ) ) t = <NUM_LIT> ; else return - <NUM_LIT> ;


<s> MachineInstr * ReplaceTLSBaseAddrCall ( MachineInstr * I , unsigned TLSBaseAddrReg ) { MachineFunction * MF = I -> getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF -> getTarget ( ) ) ;

const bool is64Bit = TM -> getSubtarget < <ISA_LIT>Subtarget > ( ) . is64Bit ( ) ;


<s> void <ISA_LIT>PassConfig :: addPreRegAlloc ( ) {


<s> const MCExpr * Res ; if ( getLexer ( ) . getKind ( ) != AsmToken :: Identifier ) return MatchOperand_NoMatch ; if ( getLexer ( ) . peekTok ( ) . getKind ( ) != AsmToken :: EndOfStatement ) return MatchOperand_NoMatch ; StringRef Identifier ; if ( getParser ( ) . parseIdentifier ( Identifier ) ) return MatchOperand_ParseFail ; <ISA_LIT>MCExpr :: VariantKind Kind ; if ( IsCap ) { Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CCALL ; Identifier . consume_back ( <STR_LIT> ) ; } else { Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL ; if ( Identifier . consume_back ( <STR_LIT> ) ) Kind = <ISA_LIT>MCExpr :: VK_<ISA_LIT>_CALL_PLT ; } MCSymbol * Sym = getContext ( ) . getOrCreateSymbol ( Identifier ) ; Res = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Res = <ISA_LIT>MCExpr :: create ( Res , Kind , getContext ( ) ) ; Operands . push_back ( <ISA_LIT>Operand :: createImm ( Res , S , E , isRV64 ( ) ) ) ; return MatchOperand_Success ;


<s> os << <STR_LIT> << t . first << <STR_LIT> << t . second << <STR_LIT> ; } os << <STR_LIT> ; os . indent ( indent + <NUM_LIT> ) << <STR_LIT> ; for ( auto t : Remnants ) { os << t << <STR_LIT> ; } os << <STR_LIT> ; printInstructions ( os , indent + <NUM_LIT> ) ;


<s> TargetLoweringBase :: LegalizeTypeAction <ISA_LIT>TargetLowering :: getPreferredVectorAction ( MVT VT ) const { if ( VT == <STR_LIT> && Subtarget . hasAVX512 ( ) && ! Subtarget . hasBWI ( ) ) return TypeSplitVector ; if ( VT . getVectorNumElements ( ) != <NUM_LIT> && VT . getVectorElementType ( ) != <STR_LIT> ) return TypeWidenVector ; return TargetLoweringBase :: getPreferredVectorAction ( VT ) ;


<s> void setStaticStackVariable ( const GlobalVariable * Var ) { StaticStackVariable = Var ;


<s> const BasicBlock * BBB = B -> getParent ( ) ; if ( ABB != BBB ) return PDT -> dominates ( ABB , BBB ) ; for ( const Instruction & I : * ABB ) { if ( & I == B ) return true ; if ( & I == A ) return false ;


<s> void addT2SOImmNotOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> return ShuffleMask ( Mask . take_back ( H ) ) ;


<s> SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Offset = Op . getOperand ( <NUM_LIT> ) ; SDValue Handler = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; const <ISA_LIT>RegisterInfo * RegInfo = Subtarget -> getRegisterInfo ( ) ; unsigned FrameReg = RegInfo -> getFrameRegister ( DAG . getMachineFunction ( ) ) ; assert ( ( ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) || ( FrameReg == <STR_LIT> && PtrVT == <STR_LIT> ) ) && <STR_LIT> ) ; SDValue Frame = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , PtrVT ) ; unsigned StoreAddrReg = ( PtrVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , Frame , DAG . getIntPtrConstant ( RegInfo -> getSlotSize ( ) , dl ) ) ;

StoreAddr = DAG . getNode ( <STR_LIT> , dl , PtrVT , StoreAddr , Offset ) ;


<s> setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; if ( ! HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; } } const MVT FloatTypes [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : FloatTypes ) { addRegisterClass ( VT , & <STR_LIT> ) ; if ( ! HasMVEFP ) setAllExpand ( VT ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT . getVectorElementType ( ) , Custom ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; if ( HasMVEFP ) { setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Legal ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ;


<s> unsigned MulOpc = Signed ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( MulOpc , SL , <STR_LIT> , N0 , N1 ) ; } unsigned MulOpc = Signed ? <STR_LIT> : <STR_LIT> ; SDValue Mul = DAG . getNode ( MulOpc , SL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , N0 , N1 ) ;

return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Mul . getValue ( <NUM_LIT> ) , Mul . getValue ( <NUM_LIT> ) ) ;


<s> MachineInstr * CommutedMI = TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ; if ( ! CommutedMI ) return nullptr ; CommutedMI -> getOperand ( CommutedMI -> findFirstPredOperandIdx ( ) ) . setImm ( <STR_LIT> ( CC ) ) ;


<s> return ( uint16x8_t ) __builtin_neon_vsubwuv8qi ( ( int16x8_t ) __a , ( int8x8_t ) __b ) ;


<s> bool mips_small_data_pattern_p ( rtx op ) {

return mips_small_data_pattern_1 ( op , SYMBOL_CONTEXT_LEA ) ;


<s> Type * ArgTy = I -> getType ( ) ; if ( ArgTy -> isStructTy ( ) || ArgTy -> isArrayTy ( ) || ArgTy -> isVectorTy ( ) ) return false ; EVT ArgVT = TLI . getValueType ( DL , ArgTy ) ; if ( ! ArgVT . isSimple ( ) ) return false ; switch ( ArgVT . getSimpleVT ( ) . SimpleTy ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; default : return false ; } } static const MCPhysReg GPRArgRegs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; const TargetRegisterClass * RC = & <STR_LIT> ; Idx = <NUM_LIT> ; for ( Function :: const_arg_iterator I = F -> arg_begin ( ) , E = F -> arg_end ( ) ; I != E ; ++ I , ++ Idx ) { unsigned SrcReg = GPRArgRegs [ Idx ] ; unsigned DstReg = FuncInfo . MF -> addLiveIn ( SrcReg , RC ) ; unsigned ResultReg = createResultReg ( RC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , ResultReg ) . addReg ( DstReg , getKillRegState ( true ) ) ;


<s> MCObjectWriter * <ISA_LIT>AsmBackend :: createObjectWriter ( raw_pwrite_stream & OS ) const {

return create<ISA_LIT>ELFObjectWriter ( OS , MCELFObjectTargetWriter :: getOSABI ( OSType ) ) ;


<s> } unsigned QueuePtr = MRI . createGenericVirtualRegister ( LLT :: pointer ( <ISA_LIT>AS :: CONSTANT_ADDRESS , <NUM_LIT> ) ) ; MIRBuilder . buildConstant ( QueuePtr , <NUM_LIT> ) ; uint32_t StructOffset = ( AS == <ISA_LIT>AS :: LOCAL_ADDRESS ) ? <NUM_LIT> : <NUM_LIT> ; Value * V = UndefValue :: get ( PointerType :: get ( Type :: getInt8Ty ( MF . getFunction ( ) . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ) ; MachinePointerInfo PtrInfo ( V , StructOffset ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MODereferenceable | MachineMemOperand :: MOInvariant , <NUM_LIT> , MinAlign ( <NUM_LIT> , StructOffset ) ) ;

Register LoadResult = MRI . createGenericVirtualRegister ( S32 ) ;


<s> switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> unsigned allBits = makeAllBits ( b , hvxInsts [ startIdx ] . Lanes ) ; if ( ( allBits & usedUnits ) == <NUM_LIT> ) { if ( checkHVXPipes ( hvxInsts , startIdx + <NUM_LIT> , usedUnits | allBits ) ) return true ; }


<s> addPass ( create<ISA_LIT>LowerI1CopiesPass ( ) ) ; addPass ( create<ISA_LIT>FixupVectorISelPass ( ) ) ; return false ;


<s> rtx plus = XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ; if ( GET_CODE ( XEXP ( plus , <NUM_LIT> ) ) == SYMBOL_REF && CONST_INT_P ( XEXP ( plus , <NUM_LIT> ) ) ) { fprintf ( file , <STR_LIT> , reg_names [ REGNO ( XEXP ( x , <NUM_LIT> ) ) ] ) ; output_addr_const ( file , plus ) ; } else abort ( ) ; } break ; default : abort ( ) ; }


<s> if ( ! AlwaysInline && ( Align & <NUM_LIT> ) != <NUM_LIT> ) return SDValue ( ) ; const MVT BlockType = getOptimalRepmovsType ( Subtarget , Align ) ; const uint64_t BlockBytes = BlockType . getSizeInBits ( ) / <NUM_LIT> ; const uint64_t BlockCount = Size / BlockBytes ; const uint64_t BytesLeft = Size % BlockBytes ; SDValue RepMovs = emitRepmovs ( Subtarget , DAG , dl , Chain , Dst , Src , DAG . getIntPtrConstant ( BlockCount , dl ) , BlockType ) ; if ( BytesLeft == <NUM_LIT> ) return RepMovs ; assert ( BytesLeft && <STR_LIT> ) ; if ( DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) return emitRepmovsB ( Subtarget , DAG , dl , Chain , Dst , Src , Size ) ; SmallVector < SDValue , <NUM_LIT> > Results ; Results . push_back ( RepMovs ) ; unsigned Offset = Size - BytesLeft ; EVT DstVT = Dst . getValueType ( ) ; EVT SrcVT = Src . getValueType ( ) ; Results . push_back ( DAG . getMemcpy ( Chain , dl , DAG . getNode ( <STR_LIT> , dl , DstVT , Dst , DAG . getConstant ( Offset , dl , DstVT ) ) , DAG . getNode ( <STR_LIT> , dl , SrcVT , Src , DAG . getConstant ( Offset , dl , SrcVT ) ) , DAG . getConstant ( BytesLeft , dl , SizeVT ) , Align , isVolatile , true , false , DstPtrInfo . getWithOffset ( Offset ) , SrcPtrInfo . getWithOffset ( Offset ) ) ) ;

return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Results ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>HazardSchedule ( ) { return new <ISA_LIT>HazardSchedule ( ) ;


<s> const TargetInstrInfo * TII = getTargetMachine ( ) . getInstrInfo ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; const BasicBlock * BB = MBB -> getBasicBlock ( ) ; MachineFunction :: iterator I = MBB ; ++ I ; MachineInstr :: mmo_iterator MMOBegin = MI -> memoperands_begin ( ) ; MachineInstr :: mmo_iterator MMOEnd = MI -> memoperands_end ( ) ; unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; const TargetRegisterClass * RC = MRI . getRegClass ( DstReg ) ; assert ( RC -> hasType ( <STR_LIT> ) && <STR_LIT> ) ; unsigned mainDstReg = MRI . createVirtualRegister ( RC ) ; unsigned restoreDstReg = MRI . createVirtualRegister ( RC ) ; MVT PVT = getPointerTy ( ) ; assert ( ( PVT == <STR_LIT> || PVT == <STR_LIT> ) && <STR_LIT> ) ; MachineBasicBlock * thisMBB = MBB ; MachineBasicBlock * mainMBB = MF -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * sinkMBB = MF -> CreateMachineBasicBlock ( BB ) ; MF -> insert ( I , mainMBB ) ; MF -> insert ( I , sinkMBB ) ; MachineInstrBuilder MIB ; sinkMBB -> splice ( sinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; sinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; const int64_t LabelOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t TOCOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const int64_t BPOffset = <NUM_LIT> * PVT . getStoreSize ( ) ; const TargetRegisterClass * PtrRC = getRegClassFor ( PVT ) ; unsigned LabelReg = MRI . createVirtualRegister ( PtrRC ) ; unsigned BufReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( Subtarget . is<ISA_LIT>64 ( ) && Subtarget . isSVR4ABI ( ) ) {

MIB = BuildMI ( * thisMBB , MI , DL , TII -> get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addImm ( TOCOffset ) . addReg ( BufReg ) ;


<s> tmp = gen_reg_rtx ( Pmode ) ; unspec = gen_rtx_UNSPEC ( Pmode , gen_rtvec ( <NUM_LIT> , symbol ) , UNSPEC_PLTOFF ) ;

emit_move_insn ( tmp , gen_rtx_CONST ( Pmode , unspec ) ) ;


<s> rtx ( * gen ) ( rtx , rtx ) ; if ( acq ) { switch ( mode ) { case QImode : gen = gen_arm_load_acquire_exclusiveqi ; break ; case HImode : gen = gen_arm_load_acquire_exclusivehi ; break ; case SImode : gen = gen_arm_load_acquire_exclusivesi ; break ; case DImode : gen = gen_arm_load_acquire_exclusivedi ; break ; default : gcc_unreachable ( ) ; } }


<s> void setupMF ( MachineFunction & MF , GISelKnownBits * KB , CodeGenCoverage & CoverageInfo , ProfileSummaryInfo * PSI , BlockFrequencyInfo * BFI ) override {

InstructionSelector :: setupMF ( MF , KB , CoverageInfo , PSI , BFI ) ;


<s> <ISA_LIT>FunctionInfo ( MachineFunction & MF ) : MF ( MF ) , SRetReturnReg ( <NUM_LIT> ) , GlobalBaseReg ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) , InArgFIRange ( std :: make_pair ( - <NUM_LIT> , <NUM_LIT> ) ) , OutArgFIRange ( std :: make_pair ( - <NUM_LIT> , <NUM_LIT> ) ) , GlobalRegFI ( <NUM_LIT> ) , DynAllocFI ( <NUM_LIT> ) , MaxCallFrameSize ( <NUM_LIT> ) , EmitNOAT ( false ) {


<s> Operands . push_back ( <ISA_LIT>Operand :: CreateSysReg ( Tok . getString ( ) , getLoc ( ) , STI . getFeatureBits ( ) , getContext ( ) ) ) ; Parser . Lex ( ) ;


<s> if ( LoadMI -> hasOneMemOperand ( ) ) Alignment = ( * LoadMI -> memoperands_begin ( ) ) -> getAlignment ( ) ; else switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; case <STR_LIT> : Alignment = <NUM_LIT> ; break ; default : return nullptr ; } if ( Ops . size ( ) == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> && Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned NewOpc = <NUM_LIT> ; switch ( MI -> getOpcode ( ) ) { default : return nullptr ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; case <STR_LIT> : NewOpc = <STR_LIT> ; break ; } MI -> setDesc ( get ( NewOpc ) ) ; MI -> getOperand ( <NUM_LIT> ) . ChangeToImmediate ( <NUM_LIT> ) ; } else if ( Ops . size ( ) != <NUM_LIT> ) return nullptr ; if ( LoadMI -> getOperand ( <NUM_LIT> ) . getSubReg ( ) != MI -> getOperand ( Ops [ <NUM_LIT> ] ) . getSubReg ( ) ) return nullptr ; SmallVector < MachineOperand , <STR_LIT> > MOs ; switch ( LoadMI -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Small && MF . getTarget ( ) . getCodeModel ( ) != CodeModel :: Kernel ) return nullptr ; unsigned PICBase = <NUM_LIT> ; if ( MF . getTarget ( ) . getRelocationModel ( ) == Reloc :: PIC_ ) { if ( Subtarget . is64Bit ( ) ) PICBase = <STR_LIT> ; else return nullptr ; } MachineConstantPool & MCP = * MF . getConstantPool ( ) ; Type * Ty ; unsigned Opc = LoadMI -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) Ty = Type :: getFloatTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> ) Ty = Type :: getDoubleTy ( MF . getFunction ( ) -> getContext ( ) ) ; else if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ;

else Ty = VectorType :: get ( Type :: getInt32Ty ( MF . getFunction ( ) -> getContext ( ) ) , <NUM_LIT> ) ;


<s> return <NUM_LIT> <= Val && Val <= <NUM_LIT> ;


<s> IPI -> second . push_back ( & Use ) ; Instruction * OldInstr = IPI -> first ; InsertPts [ NewPt ] = std :: move ( IPI -> second ) ; InsertPts . erase ( OldInstr ) ;


<s> switch ( ConstraintLetter ) { case 'I' : if ( ! isUInt < <NUM_LIT> > ( CUVal64 ) ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'J' : if ( CVal64 < - <NUM_LIT> || CVal64 > <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; case 'K' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'L' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'M' : if ( ! isUInt < <NUM_LIT> > ( CUVal64 ) ) return ; if ( Ty . getSimpleVT ( ) == <STR_LIT> ) { Ty = <STR_LIT> ; } Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'N' : if ( CVal64 != - <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; case 'O' : if ( CUVal64 != <NUM_LIT> && CUVal64 != <NUM_LIT> && CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'P' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ;


<s> static SDValue getMOVL ( SelectionDAG & DAG , const SDLoc & dl , MVT VT , SDValue V1 , SDValue V2 ) { unsigned NumElems = VT . getVectorNumElements ( ) ;


<s> if ( GET_CODE ( value ) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P ( value ) ) { fputs ( <STR_LIT> , asm_out_file ) ; output_addr_const ( asm_out_file , value ) ; fputs ( <STR_LIT> , asm_out_file ) ;


<s> addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> MVT VT = Op1 . getSimpleValueType ( ) ; MVT EVT = VT . getVectorElementType ( ) ; unsigned n = VT . getVectorNumElements ( ) ; SmallVector < SDValue , <NUM_LIT> > ULTOp1 ; for ( unsigned i = <NUM_LIT> ; i < n ; ++ i ) { ConstantSDNode * Elt = dyn_cast < ConstantSDNode > ( BV -> getOperand ( i ) ) ; if ( ! Elt || Elt -> isOpaque ( ) || Elt -> getValueType ( <NUM_LIT> ) != EVT ) return SDValue ( ) ; APInt Val = Elt -> getAPIntValue ( ) ; if ( Val == <NUM_LIT> ) return SDValue ( ) ; ULTOp1 . push_back ( DAG . getConstant ( Val - <NUM_LIT> , EVT ) ) ; }

return DAG . getNode ( <STR_LIT> , SDLoc ( Op1 ) , VT , ULTOp1 . data ( ) , ULTOp1 . size ( ) ) ;


<s> int SubVecNumElts = SubVecVT . getVectorNumElements ( ) ; SmallVector < int , <NUM_LIT> > Mask ( VecNumElts ) ; for ( int i = <NUM_LIT> ; i != VecNumElts ; ++ i ) Mask [ i ] = i ; for ( int i = <NUM_LIT> ; i != SubVecNumElts ; ++ i ) Mask [ i + IdxVal ] = i + ExtIdxVal + VecNumElts ; return DAG . getVectorShuffle ( OpVT , dl , Vec , SubVec . getOperand ( <NUM_LIT> ) , Mask ) ; } } SmallVector < SDValue , <NUM_LIT> > SubVectorOps ; if ( collectConcatOps ( N , SubVectorOps ) ) if ( SDValue Fold = combineConcatVectorOps ( dl , OpVT , SubVectorOps , DAG , DCI , Subtarget ) ) return Fold ; if ( ( IdxVal == OpVT . getVectorNumElements ( ) / <NUM_LIT> ) && Vec . getOpcode ( ) == <STR_LIT> && OpVT . getSizeInBits ( ) == SubVecVT . getSizeInBits ( ) * <NUM_LIT> && isNullConstant ( Vec . getOperand ( <NUM_LIT> ) ) && ! Vec . getOperand ( <NUM_LIT> ) . isUndef ( ) && Vec . hasOneUse ( ) ) { Vec = DAG . getNode ( <STR_LIT> , dl , OpVT , DAG . getUNDEF ( OpVT ) , Vec . getOperand ( <NUM_LIT> ) , Vec . getOperand ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , dl , OpVT , Vec , SubVec , N -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ( ) ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; assert ( checkAllSuperRegsMarked ( Reserved ) ) ;


<s> bool OddDeadKill = isLd ? MI -> getOperand ( <NUM_LIT> ) . isDead ( ) : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OddUndef = MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; bool BaseKill = BaseOp . isKill ( ) ; bool BaseUndef = BaseOp . isUndef ( ) ; bool OffKill = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; bool OffUndef = isT2 ? false : MI -> getOperand ( <NUM_LIT> ) . isUndef ( ) ; int OffImm = getMemoryOpOffset ( * MI ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( * MI , PredReg ) ; if ( OddRegNum > EvenRegNum && OffImm == <NUM_LIT> ) { unsigned NewOpc = ( isLd ) ? ( isT2 ? <STR_LIT> : <STR_LIT> ) : ( isT2 ? <STR_LIT> : <STR_LIT> ) ; if ( isLd ) { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getDefRegState ( isLd ) | getDeadRegState ( EvenDeadKill ) ) . addReg ( OddReg , getDefRegState ( isLd ) | getDeadRegState ( OddDeadKill ) ) ; ++ NumLDRD2LDM ; } else { BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( BaseReg , getKillRegState ( BaseKill ) ) . addImm ( Pred ) . addReg ( PredReg ) . addReg ( EvenReg , getKillRegState ( EvenDeadKill ) | getUndefRegState ( EvenUndef ) ) . addReg ( OddReg , getKillRegState ( OddDeadKill ) | getUndefRegState ( OddUndef ) ) ; ++ NumSTRD2STM ; } } else { unsigned NewOpc = ( isLd ) ? ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; unsigned NewOpc2 = ( isLd ) ? ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) : ( isT2 ? ( OffImm + <NUM_LIT> < <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) : <STR_LIT> ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; if ( isLd && ( BaseKill || OffKill ) && ( TRI -> regsOverlap ( EvenReg , BaseReg ) ) ) {

assert ( ! TRI -> regsOverlap ( OddReg , BaseReg ) ) ;


<s> StringRef getPassName ( ) const override {


<s> <ISA_LIT>PLT :: ~ <ISA_LIT>PLT ( ) {


<s> if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { unsigned CRReg = getCRFromCRBit ( SrcReg ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( CRReg ) ; getKillRegState ( KillSrc ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg , RegState :: Kill ) . addImm ( TRI -> getEncodingValue ( CRReg ) * <NUM_LIT> + ( <NUM_LIT> - getCRBitValue ( SrcReg ) ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; NumGPRtoVSRSpill ++ ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ; } else if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; getKillRegState ( KillSrc ) ; return ;


<s> void <ISA_LIT>AsmPrinter :: printOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { const MachineOperand & MO = MI -> getOperand ( opNum ) ; bool closeP = false ; if ( MO . getTargetFlags ( ) ) closeP = true ; switch ( MO . getTargetFlags ( ) ) { case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ;


<s> bool <ISA_LIT>InstrInfo :: BlockHasNoFallThrough ( const MachineBasicBlock & MBB ) const {

return ( ! MBB . empty ( ) && isUncondBranch ( & MBB . back ( ) ) ) ;


<s> const std :: string & <ISA_LIT>AbsoluteStub :: name ( ) const { return m_Name ;


<s> unsigned Opc = Op . getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { if ( ! Op . hasOneUse ( ) || ! Subtarget . hasAnyFMA ( ) || ! isTypeLegal ( VT ) || ! ( SVT == <STR_LIT> || SVT == <STR_LIT> ) || ! isOperationLegal ( <STR_LIT> , VT ) ) break ; SmallVector < SDValue , <NUM_LIT> > NewOps ( Op . getNumOperands ( ) , SDValue ( ) ) ;

for ( int i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) NewOps [ i ] = getCheaperNegatedExpression ( Op . getOperand ( i ) , DAG , LegalOperations , ForCodeSize , Depth + <NUM_LIT> ) ;


<s> return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return <NUM_LIT> ; default :


<s> assert ( cast < ConstantDataSequential > ( Operand ) -> isCString ( ) && <STR_LIT> ) ; StringRef ReflectArg = cast < ConstantDataSequential > ( Operand ) -> getAsString ( ) ; ReflectArg = ReflectArg . substr ( <NUM_LIT> , ReflectArg . size ( ) - <NUM_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << ReflectArg << <STR_LIT> ) ; int ReflectVal = <NUM_LIT> ; if ( ReflectArg == <STR_LIT> ) { if ( auto * Flag = mdconst :: extract_or_null < ConstantInt > ( F . getParent ( ) -> getModuleFlag ( <STR_LIT> ) ) ) ReflectVal = Flag -> getSExtValue ( ) ; } else if ( ReflectArg == <STR_LIT> ) { ReflectVal = SmVersion * <NUM_LIT> ; } Call -> replaceAllUsesWith ( ConstantInt :: get ( Call -> getType ( ) , ReflectVal ) ) ; ToRemove . push_back ( Call ) ;


<s> } StringRef Name = Symbol . Name ; if ( Symbol . Type == ELF :: STT_OBJECT && Name . endswith ( StringRef ( <STR_LIT> ) ) ) { Size = <NUM_LIT> ;

return decodeKernelDescriptor ( Name . drop_back ( <NUM_LIT> ) , Bytes , Address ) ;


<s> switch ( get_attr_type ( insn ) ) { case TYPE_ILD : case TYPE_LDSYM : case TYPE_FLD : case TYPE_LD_L : return EV4_IBX ; case TYPE_IADD : case TYPE_ILOG : case TYPE_ICMOV : case TYPE_ICMP : case TYPE_FST : case TYPE_SHIFT :


<s> void <ISA_LIT>AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) {


<s> fprintf ( stderr , <STR_LIT> ) ; return false ; } fprintf ( stderr , <STR_LIT> ) ; return true ; } if ( GET_CODE ( x ) == REG && GEN_REG ( REGNO ( x ) , strict ) ) { fprintf ( stderr , <STR_LIT> ) ; return true ; } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GEN_REG ( REGNO ( XEXP ( x , <NUM_LIT> ) ) , strict ) && const_in_range ( XEXP ( x , <NUM_LIT> ) , - <NUM_LIT> , <NUM_LIT> ) ) { fprintf ( stderr , <STR_LIT> ) ; return true ; } if ( GET_CODE ( x ) == PLUS && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == REG && GEN_REG ( REGNO ( XEXP ( x , <NUM_LIT> ) ) , strict ) && GET_CODE ( XEXP ( x , <NUM_LIT> ) ) == CONST && ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC || ( GET_CODE ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) ) == PLUS && GET_CODE ( XEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) == UNSPEC && GET_CODE ( XEXP ( XEXP ( XEXP ( x , <NUM_LIT> ) , <NUM_LIT> ) , <NUM_LIT> ) ) == CONST_INT ) ) ) { fprintf ( stderr , <STR_LIT> ) ; return true ; } the_tag = mep_section_tag ( x ) ; if ( the_tag == 'f' ) {


<s> return ( gpc_reg_operand ( operands [ <NUM_LIT> ] , mode ) || gpc_reg_operand ( operands [ <NUM_LIT> ] , mode ) ) ;


<s> return ( __m128i ) __builtin_ia32_vcvtph2uw128_mask ( __B , ( __v8hi ) _mm_setzero_si128 ( ) , __A ) ;


<s> if ( isa < UndefValue > ( Ptr ) || isa < Argument > ( Ptr ) || isa < Constant > ( Ptr ) || isa < GlobalValue > ( Ptr ) ) return true ; const Instruction * I = dyn_cast_or_null < Instruction > ( Ptr ) ;

return I && I -> getMetadata ( <STR_LIT> ) ;


<s> auto * TPC = & getAnalysis < TargetPassConfig > ( ) ; const Function & F = MF . getFunction ( ) ; <ISA_LIT>PostLegalizerLoweringInfo PCInfo ( F . hasOptSize ( ) , F . hasMinSize ( ) ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ;


<s> bool easy_altivec_constant ( rtx op , machine_mode mode ) { unsigned step , copies ; if ( mode == VOIDmode ) mode = GET_MODE ( op ) ; else if ( mode != GET_MODE ( op ) ) return false ; if ( mode == V2DFmode ) return zero_constant ( op , mode ) ; else if ( mode == V2DImode ) { if ( GET_CODE ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) != CONST_INT || GET_CODE ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) != CONST_INT ) return false ; if ( zero_constant ( op , mode ) ) return true ; if ( INTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) == - <NUM_LIT> && INTVAL ( CONST_VECTOR_ELT ( op , <NUM_LIT> ) ) == - <NUM_LIT> ) return true ; return false ; }

else if ( mode == V1TImode ) return false ;


<s> return static_cast < <ISA_LIT>VSEW > ( VSEW ) ;


<s> void setStackLimit ( unsigned limit ) {


<s> EVT MemVT = Store -> getMemoryVT ( ) ; SDValue Chain = Store -> getChain ( ) ; SDValue BasePtr = Store -> getBasePtr ( ) ; SDLoc SL ( Op ) ; EVT LoVT , HiVT ; EVT LoMemVT , HiMemVT ; SDValue Lo , Hi ; std :: tie ( LoVT , HiVT ) = DAG . GetSplitDestVTs ( VT ) ; std :: tie ( LoMemVT , HiMemVT ) = DAG . GetSplitDestVTs ( MemVT ) ; std :: tie ( Lo , Hi ) = DAG . SplitVector ( Val , SL , LoVT , HiVT ) ; EVT PtrVT = BasePtr . getValueType ( ) ; SDValue HiPtr = DAG . getNode ( <STR_LIT> , SL , PtrVT , BasePtr , DAG . getConstant ( LoMemVT . getStoreSize ( ) , SL , PtrVT ) ) ;

const MachinePointerInfo & SrcValue = Store -> getMemOperand ( ) -> getPointerInfo ( ) ;


<s> void <ISA_LIT>AnalyzeImmediate :: GetInstSeqLsSHL ( uint64_t Imm , unsigned RemSize , InstSeqLs & SeqLs ) { unsigned Shamt = countTrailingZeros ( Imm ) ;

GetInstSeqLs ( Imm >> Shamt , RemSize - Shamt , SeqLs ) ;


<s> static struct machine_function * arc_init_machine_status ( void ) { struct machine_function * machine ; machine = ggc_cleared_alloc < machine_function > ( ) ; machine -> fn_type = ARC_FUNCTION_UNKNOWN ; machine -> force_short_suffix = - <NUM_LIT> ;


<s> SrcSubIdx = DstSubIdx = <NUM_LIT> ; if ( MI . getOpcode ( ) == <STR_LIT> || MI . getOpcode ( ) == <STR_LIT> ) {

DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> bool <ISA_LIT>InstrInfo :: isDependent ( const MachineInstr & ProdMI , const MachineInstr & ConsMI ) const { if ( ! ProdMI . getDesc ( ) . getNumDefs ( ) ) return false ; auto & HRI = getRegisterInfo ( ) ; SmallVector < unsigned , <NUM_LIT> > DefsA ; SmallVector < unsigned , <NUM_LIT> > DefsB ; SmallVector < unsigned , <NUM_LIT> > UsesA ; SmallVector < unsigned , <NUM_LIT> > UsesB ; parseOperands ( ProdMI , DefsA , UsesA ) ; parseOperands ( ConsMI , DefsB , UsesB ) ; for ( auto & RegA : DefsA ) for ( auto & RegB : UsesB ) { if ( RegA == RegB ) return true ; if ( TargetRegisterInfo :: isPhysicalRegister ( RegA ) ) for ( MCSubRegIterator SubRegs ( RegA , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegB == * SubRegs ) return true ; if ( TargetRegisterInfo :: isPhysicalRegister ( RegB ) ) for ( MCSubRegIterator SubRegs ( RegB , & HRI ) ; SubRegs . isValid ( ) ; ++ SubRegs ) if ( RegA == * SubRegs ) return true ; }


<s> MachineOperand * Data = TII -> getNamedOperand ( MI , <STR_LIT> :: vdata ) ; if ( Data && Op . isIdenticalTo ( * Data ) ) return true ; } for ( MachineInstr :: mop_iterator I = MI . operands_begin ( ) , E = MI . operands_end ( ) ; I != E ; ++ I ) { if ( I -> isReg ( ) && I -> isUse ( ) ) return Op . isIdenticalTo ( * I ) ; }


<s> emit_move_insn ( gpos , gen_rtx_SUBREG ( SImode , gpos_qi , <NUM_LIT> ) ) ; emit_cmp_and_jump_insns ( gpos , loadlen , GE , NULL_RTX , SImode , <NUM_LIT> , full_label ) ; emit_insn ( gen_vstlv16qi ( vsrc , gpos , dst ) ) ; force_expand_binop ( Pmode , add_optab , dst_addr , gpos , result , <NUM_LIT> , OPTAB_DIRECT ) ; emit_jump ( exit_label ) ; emit_barrier ( ) ; emit_label ( full_label ) ; LABEL_NUSES ( full_label ) = <NUM_LIT> ; force_expand_binop ( Pmode , and_optab , src_addr , GEN_INT ( <NUM_LIT> ) , temp , <NUM_LIT> , OPTAB_DIRECT ) ; emit_move_insn ( offset , GEN_INT ( <NUM_LIT> ) ) ; force_expand_binop ( Pmode , sub_optab , offset , temp , offset , <NUM_LIT> , OPTAB_DIRECT ) ; emit_insn ( gen_vstlv16qi ( vsrc , gen_lowpart ( SImode , offset ) , dst ) ) ; force_expand_binop ( Pmode , add_optab , offset , const1_rtx , offset , <NUM_LIT> , OPTAB_DIRECT ) ; emit_move_insn ( src_addr_reg , src_addr ) ; emit_move_insn ( dst_addr_reg , dst_addr ) ; emit_label ( loop_label ) ; LABEL_NUSES ( loop_label ) = <NUM_LIT> ; emit_move_insn ( vsrc , gen_rtx_MEM ( V16QImode , gen_rtx_PLUS ( Pmode , src_addr_reg , offset ) ) ) ; emit_insn ( gen_vec_vfenesv16qi ( vpos , vsrc , vsrc , GEN_INT ( VSTRING_FLAG_ZS | VSTRING_FLAG_CS ) ) ) ; add_int_reg_note ( s390_emit_ccraw_jump ( <NUM_LIT> , EQ , done_label ) , REG_BR_PROB , profile_probability :: very_unlikely ( ) . to_reg_br_prob_note ( ) ) ; emit_move_insn ( gen_rtx_MEM ( V16QImode , gen_rtx_PLUS ( Pmode , dst_addr_reg , offset ) ) , vsrc ) ; force_expand_binop ( Pmode , add_optab , offset , GEN_INT ( <NUM_LIT> ) , offset , <NUM_LIT> , OPTAB_DIRECT ) ; emit_jump ( loop_label ) ; emit_barrier ( ) ; emit_label ( done_label ) ; LABEL_NUSES ( done_label ) = <NUM_LIT> ; force_expand_binop ( Pmode , add_optab , dst_addr_reg , offset , dst_addr_reg , <NUM_LIT> , OPTAB_DIRECT ) ;

emit_insn ( gen_vec_extractv16qiqi ( gpos_qi , vpos , GEN_INT ( <NUM_LIT> ) ) ) ;


<s> bool <ISA_LIT>CodeGenPrepare :: canWidenScalarExtLoad ( LoadInst & I ) const { Type * Ty = I . getType ( ) ; const DataLayout & DL = Mod -> getDataLayout ( ) ; int TySize = DL . getTypeSizeInBits ( Ty ) ; Align Alignment = DL . getValueOrABITypeAlignment ( I . getAlign ( ) , Ty ) ;

return I . isSimple ( ) && TySize < <NUM_LIT> && Alignment >= <NUM_LIT> && DA -> isUniform ( & I ) ;


<s> Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ; continue ; } } return Result ; } static const unsigned OpTable [ <NUM_LIT> ] [ <NUM_LIT> ] = { { <STR_LIT> :: src0 , <STR_LIT> :: src0_sel } , { <STR_LIT> :: src1 , <STR_LIT> :: src1_sel } , { <STR_LIT> :: src2 , <STR_LIT> :: src2_sel } , } ; for ( unsigned j = <NUM_LIT> ; j < <NUM_LIT> ; j ++ ) { int SrcIdx = getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ; if ( SrcIdx < <NUM_LIT> ) break ; MachineOperand & MO = MI . getOperand ( SrcIdx ) ; Register Reg = MO . getReg ( ) ; if ( Reg == <STR_LIT> ) { MachineOperand & Sel = MI . getOperand ( getOperandIdx ( MI . getOpcode ( ) , OpTable [ j ] [ <NUM_LIT> ] ) ) ; Result . push_back ( std :: make_pair ( & MO , Sel . getImm ( ) ) ) ;


<s> if ( TREE_CODE ( exp ) == STRING_CST && ! optimize_size ) return MAX ( align , BITS_PER_WORD ) ; return align ;


<s> switch ( TheTriple . getObjectFormat ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case Triple :: MachO : { MCStreamer * S = createMachOStreamer ( Ctx , MAB , OS , Emitter , false ) ; new <ISA_LIT>TargetStreamer ( * S ) ; return S ; } case Triple :: COFF : assert ( TheTriple . isOSWindows ( ) && <STR_LIT> ) ; return create<ISA_LIT>WinCOFFStreamer ( Ctx , MAB , * Emitter , OS ) ; case Triple :: ELF :

return create<ISA_LIT>ELFStreamer ( Ctx , MAB , OS , Emitter , false , TheTriple . getArch ( ) == Triple :: thumb ) ;


<s> SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; MachineFunction & MF = DAG . getMachineFunction ( ) ; isTailCall = false ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; const Function * F = nullptr ; if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) { const GlobalValue * GV = G -> getGlobal ( ) ; F = cast < Function > ( GV ) ; Callee = DAG . getTargetGlobalAddress ( GV , DL , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } else if ( const ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) { Callee = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; } if ( isVarArg ) { CCInfo . AnalyzeCallOperands ( Outs , ArgCC_<ISA_LIT>_Vararg ) ; } else { analyzeArguments ( & CLI , F , & DAG . getDataLayout ( ) , Outs , ArgLocs , CCInfo ) ; } unsigned NumBytes = CCInfo . getNextStackOffset ( ) ; Chain = DAG . getCALLSEQ_START ( Chain , NumBytes , <NUM_LIT> , DL ) ; SmallVector < std :: pair < unsigned , SDValue > , <NUM_LIT> > RegsToPass ; unsigned AI , AE ; bool HasStackArgs = false ; for ( AI = <NUM_LIT> , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) { CCValAssign & VA = ArgLocs [ AI ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ AI ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: BCvt :


<s> return & InstrInfo . getRegisterInfo ( ) ;


<s> IncomingArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , CCAssignFn * AssignFn ) : ValueHandler ( MIRBuilder , MRI , AssignFn ) , StackUsed ( <NUM_LIT> ) {


<s> CallInst . addOperand ( Callee ) ; OutStreamer . EmitInstruction ( CallInst , STI ) ;


<s> const AsmToken & Tok = Parser . getTok ( ) ; int64_t OrigDispVal , DotDispVal ; if ( const MCConstantExpr * OrigDisp = dyn_cast < MCConstantExpr > ( Disp ) ) OrigDispVal = OrigDisp -> getValue ( ) ; else return Error ( Tok . getLoc ( ) , <STR_LIT> ) ; StringRef DotDispStr = Tok . getString ( ) ; if ( DotDispStr . startswith ( <STR_LIT> ) ) DotDispStr = DotDispStr . drop_front ( <NUM_LIT> ) ; if ( Tok . is ( AsmToken :: Real ) ) { APInt DotDisp ; DotDispStr . getAsInteger ( <NUM_LIT> , DotDisp ) ; DotDispVal = DotDisp . getZExtValue ( ) ; } else if ( isParsingInlineAsm ( ) && Tok . is ( AsmToken :: Identifier ) ) { unsigned DotDisp ; std :: pair < StringRef , StringRef > BaseMember = DotDispStr . split ( '.' ) ; if ( SemaCallback -> LookupInlineAsmField ( BaseMember . first , BaseMember . second , DotDisp ) ) return Error ( Tok . getLoc ( ) , <STR_LIT> ) ;


<s> } else { auto & HMFI = * MF -> getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned AR = HMFI . getStackAlignBaseVReg ( ) ; SDValue CH = CurDAG -> getEntryNode ( ) ; SDValue Ops [ ] = { CurDAG -> getCopyFromReg ( CH , DL , AR , <STR_LIT> ) , FI , Zero } ; R = CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , Ops ) ;


<s> if ( Kind . isMergeableConst8 ( ) ) return MergeableConst8Section ; if ( Kind . isMergeableConst16 ( ) ) return MergeableConst16Section ;

assert ( ( Kind . isReadOnly ( ) || Kind . isReadOnlyWithRel ( ) ) && <STR_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < <ISA_LIT>Samplers . size ( ) ; i ++ ) { if ( getSamplerSymbol ( i ) . empty ( ) ) { sprintf ( buf , <STR_LIT> , <STR_LIT> , index ) ; <ISA_LIT>Samplers [ i ] -> setSym ( buf ) ; index ++ ; }


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) . hasVarSizedObjects ( ) ;


<s> if ( frame_pointer_needed ) slot_address = loongarch_add_offset ( scratch , hard_frame_pointer_rtx , - UNITS_PER_WORD ) ; else slot_address = loongarch_add_offset ( scratch , stack_pointer_rtx , cfun -> machine -> frame . gp_sp_offset ) ; loongarch_emit_move ( gen_frame_mem ( GET_MODE ( address ) , slot_address ) , address ) ;


<s> static bool mep_general_reg ( rtx x ) {

while ( GET_CODE ( x ) == SUBREG ) x = XEXP ( x , <NUM_LIT> ) ;


return __builtin_aarch64_lrounduv2sfv2si_us ( __a ) ;


<s> unsigned addrspace = <NUM_LIT> ; if ( MI -> getOpcode ( ) == <STR_LIT> ) return false ;

if ( isLoadInstr ( * MI , addrspace ) ) if ( addrspace == <STR_LIT> :: SHARED ) return false ;


<s> ~ <ISA_LIT>AsmBackendNaClELF ( ) override {


<s> } else { Result = ( uint64_t ) slice ( byte , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> | ( uint64_t ) slice ( byte , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; if ( bit6 ) Result |= <NUM_LIT> << <NUM_LIT> ; else Result |= <NUM_LIT> << <NUM_LIT> ; }


<s> unsigned Depth = cast < ConstantInt > ( I . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { DestReg = createResultReg ( RC ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( LdrOpc ) , DestReg ) . addReg ( SrcReg ) . addImm ( <NUM_LIT> ) ) ; SrcReg = DestReg ; } UpdateValueMap ( & I , SrcReg ) ; return true ; } case <STR_LIT> : case <STR_LIT> : { const MemTransferInst & MTI = cast < MemTransferInst > ( I ) ; if ( MTI . isVolatile ( ) ) return false ; bool isMemCpy = ( I . getIntrinsicID ( ) == <STR_LIT> ) ; if ( isa < ConstantInt > ( MTI . getLength ( ) ) && isMemCpy ) { uint64_t Len = cast < ConstantInt > ( MTI . getLength ( ) ) -> getZExtValue ( ) ; if ( <ISA_LIT>IsMemCpySmall ( Len ) ) { Address Dest , Src ; if ( ! <ISA_LIT>ComputeAddress ( MTI . getRawDest ( ) , Dest ) || ! <ISA_LIT>ComputeAddress ( MTI . getRawSource ( ) , Src ) ) return false ; unsigned Alignment = MTI . getAlignment ( ) ; if ( <ISA_LIT>TryEmitSmallMemCpy ( Dest , Src , Len , Alignment ) ) return true ; } } if ( ! MTI . getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; if ( MTI . getSourceAddressSpace ( ) > <NUM_LIT> || MTI . getDestAddressSpace ( ) > <NUM_LIT> ) return false ; const char * IntrMemName = isa < MemCpyInst > ( I ) ? <STR_LIT> : <STR_LIT> ; return SelectCall ( & I , IntrMemName ) ; } case <STR_LIT> : { const MemSetInst & MSI = cast < MemSetInst > ( I ) ; if ( MSI . isVolatile ( ) ) return false ; if ( ! MSI . getLength ( ) -> getType ( ) -> isIntegerTy ( <NUM_LIT> ) ) return false ; if ( MSI . getDestAddressSpace ( ) > <NUM_LIT> ) return false ; return SelectCall ( & I , <STR_LIT> ) ; } case <STR_LIT> : { BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DL , TII . get ( Subtarget -> useNaClTrap ( ) ? <STR_LIT> : <STR_LIT> ) ) ; return true ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> return new <ISA_LIT>LowerStructArgs ( ) ;


<s> static void hi8 ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) {

Value = ( Value & <NUM_LIT> ) >> <NUM_LIT> ;


<s> using namespace TargetOpcode ; unsigned NumOperands = MI . getNumOperands ( ) ; const ValueMapping * OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ; switch ( Opc ) { case G_ADD : OperandsMapping = & <STR_LIT> [ <STR_LIT> ] ;


<s> return new <ISA_LIT>PassConfig ( this , PM ) ;


<s> unsigned getReturnRegsCount ( ) const {


<s> void <ISA_LIT>DbgInfo :: EmitAuxEntry ( const std :: string VarName , int Aux [ ] , int Num , std :: string TagName ) {

O << <STR_LIT> << VarName << <STR_LIT> ;


<s> unsigned int gmask = cfun -> machine -> frame_info . gmask ; unsigned int frame_size_to_allocate ; int first_offset = <NUM_LIT> ; size = ARC_STACK_ALIGN ( size ) ; size = ( ! cfun -> machine -> frame_info . initialized ? arc_compute_frame_size ( size ) : cfun -> machine -> frame_info . total_size ) ; if ( flag_stack_usage_info ) current_function_static_stack_size = size ; frame_size_to_allocate = size ; gcc_assert ( ! ( size == <NUM_LIT> && gmask ) ) ; if ( cfun -> machine -> frame_info . pretend_size != <NUM_LIT> ) { gcc_assert ( cfun -> machine -> frame_info . pretend_size <= <NUM_LIT> ) ; frame_stack_add ( - ( HOST_WIDE_INT ) cfun -> machine -> frame_info . pretend_size ) ; frame_size_to_allocate -= cfun -> machine -> frame_info . pretend_size ; } if ( MUST_SAVE_RETURN_ADDR ) { rtx ra = gen_rtx_REG ( SImode , RETURN_ADDR_REGNUM ) ; rtx mem = gen_frame_mem ( Pmode , gen_rtx_PRE_DEC ( Pmode , stack_pointer_rtx ) ) ; frame_move_inc ( mem , ra , stack_pointer_rtx , <NUM_LIT> ) ; frame_size_to_allocate -= UNITS_PER_WORD ; } if ( cfun -> machine -> frame_info . reg_size ) { first_offset = - cfun -> machine -> frame_info . reg_size ; arc_save_restore ( stack_pointer_rtx , gmask , <NUM_LIT> , & first_offset ) ; frame_size_to_allocate -= cfun -> machine -> frame_info . reg_size ; } if ( frame_pointer_needed ) {

rtx addr = gen_rtx_PLUS ( Pmode , stack_pointer_rtx , GEN_INT ( - UNITS_PER_WORD + first_offset ) ) ;


<s> if ( TARGET_P9_VECTOR ) return <NUM_LIT> ; if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return <NUM_LIT> ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == <NUM_LIT> ) return <NUM_LIT> ; if ( elements == <NUM_LIT> ) { switch ( misalign ) { case <NUM_LIT> : return <NUM_LIT> ; case - <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ; return <NUM_LIT> ; case unaligned_store : case vector_scatter_store : if ( TARGET_EFFICIENT_UNALIGNED_VSX ) return <NUM_LIT> ; if ( TARGET_VSX && TARGET_ALLOW_MOVMISALIGN ) { elements = TYPE_VECTOR_SUBPARTS ( vectype ) ; if ( elements == <NUM_LIT> ) return <NUM_LIT> ; if ( elements == <NUM_LIT> ) { switch ( misalign ) { case <NUM_LIT> : return <NUM_LIT> ; case - <NUM_LIT> : case <NUM_LIT> : case <NUM_LIT> : return <NUM_LIT> ; default : gcc_unreachable ( ) ; } } } if ( TARGET_ALTIVEC ) gcc_unreachable ( ) ;


<s> Opcode = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : Opcode = <STR_LIT> ; break ; } SDVTList VTs = CurDAG -> getVTList ( <STR_LIT> ) ; SDValue Ops [ ] = { Address , Base , Modifier , Offset , Chain } ; SDNode * Result = CurDAG -> getMachineNode ( Opcode , dl , VTs , Ops ) ; MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemIntrinsicSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ;


<s> uint32_t <ISA_LIT>PrintfInfo :: getOperandID ( uint32_t idx ) { return mOperands [ idx ] ;


<s> if ( sparc_cpu == PROCESSOR_ULTRASPARC || sparc_cpu == PROCESSOR_ULTRASPARC3 ) return <NUM_LIT> ; if ( ( <NUM_LIT> << sparc_cpu ) & ( ( <NUM_LIT> << PROCESSOR_SUPERSPARC ) | ( <NUM_LIT> << PROCESSOR_HYPERSPARC ) | ( <NUM_LIT> << PROCESSOR_SPARCLITE86X ) ) ) return <NUM_LIT> ;


<s> rtx call [ <NUM_LIT> ] ; rtx insn ; int cookie_val = INTVAL ( cookie ) ; bool make_island = false ; if ( ( cookie_val & CALL_LONG ) != <NUM_LIT> && GET_CODE ( func_desc ) == SYMBOL_REF ) { if ( darwin_emit_branch_islands && TARGET_32BIT ) make_island = true ; else { func = rs6000_longcall_ref ( func_desc , NULL_RTX ) ; cookie_val &= ~ CALL_LONG ; } } if ( GET_CODE ( func ) != SYMBOL_REF ) { func = force_reg ( Pmode , func ) ; func_addr = gen_rtx_REG ( Pmode , CTR_REGNO ) ; emit_move_insn ( func_addr , func ) ; } else func_addr = func ; call [ <NUM_LIT> ] = gen_rtx_CALL ( VOIDmode , gen_rtx_MEM ( SImode , func_addr ) , tlsarg ) ; if ( value != NULL_RTX ) call [ <NUM_LIT> ] = gen_rtx_SET ( value , call [ <NUM_LIT> ] ) ; call [ <NUM_LIT> ] = gen_rtx_USE ( VOIDmode , GEN_INT ( cookie_val ) ) ; if ( sibcall ) call [ <NUM_LIT> ] = simple_return_rtx ; else call [ <NUM_LIT> ] = gen_hard_reg_clobber ( Pmode , LR_REGNO ) ;

insn = gen_rtx_PARALLEL ( VOIDmode , gen_rtvec_v ( <NUM_LIT> , call ) ) ;


<s> return ( uint8x16_t ) __builtin_neon_vshluv16qi ( ( int8x16_t ) __a , __b ) ;


<s> tmp = ( __v16qu ) _mm_loadu_si128 ( p ) ; mask = ( __v16qu ) vec_cmpgt ( ( __v16qu ) __B , ( __v16qu ) hibit ) ;

tmp = vec_sel ( tmp , ( __v16qu ) __A , mask ) ;


<s> unsigned Reg = DFPRegDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ;


<s> Parser . Lex ( ) ; } if ( getLexer ( ) . is ( AsmToken :: LBrac ) ) return ParseIntelBracExpression ( SegReg , Size ) ; if ( ! ParseRegister ( SegReg , Start , End ) ) { if ( getLexer ( ) . isNot ( AsmToken :: Colon ) ) return ErrorOperand ( Start , <STR_LIT> ) ; Parser . Lex ( ) ; if ( getLexer ( ) . isNot ( AsmToken :: LBrac ) ) return ErrorOperand ( Start , <STR_LIT> ) ; return ParseIntelBracExpression ( SegReg , Size ) ; } const MCExpr * Disp = MCConstantExpr :: Create ( <NUM_LIT> , getParser ( ) . getContext ( ) ) ; if ( getParser ( ) . parseExpression ( Disp , End ) ) return <NUM_LIT> ; bool NeedSizeDir = false ; bool IsVarDecl = false ; if ( isParsingInlineAsm ( ) ) { if ( const MCSymbolRefExpr * SymRef = dyn_cast < MCSymbolRefExpr > ( Disp ) ) { const MCSymbol & Sym = SymRef -> getSymbol ( ) ; unsigned tLength , tSize , tType ; SemaCallback -> LookupInlineAsmIdentifier ( Sym . getName ( ) , NULL , tLength , tSize , tType , IsVarDecl ) ; if ( ! Size ) Size = tType * <NUM_LIT> ; NeedSizeDir = Size > <NUM_LIT> ; } } if ( ! isParsingInlineAsm ( ) ) return <STR_LIT> ( Disp , Start , End , Size ) ; else {


<s> int FPSI = FI -> getFramePointerSaveIndex ( ) ; if ( ! FPSI ) { int FPOffset = Subtarget . getFrameLowering ( ) -> getFramePointerSaveOffset ( ) ; FPSI = MF . getFrameInfo ( ) -> CreateFixedObject ( is<ISA_LIT>64 ? <NUM_LIT> : <NUM_LIT> , FPOffset , true ) ;

FI -> setFramePointerSaveIndex ( FPSI ) ;


<s> b = ( __vector unsigned int ) vec_abs ( ( __v4sf ) __B ) ; c = ( __vector unsigned int ) vec_cmpgt ( a , float_exp_mask ) ; d = ( __vector unsigned int ) vec_cmpgt ( b , float_exp_mask ) ;

return ( ( __m128 ) vec_or ( c , d ) ) ;


<s> if ( mode == TFmode && ! ( TARGET_ARCH64 && TARGET_HARD_QUAD ) ) return <NUM_LIT> ; if ( mode == TImode ) return <NUM_LIT> ; if ( TARGET_ARCH32 && ! optimize && ( mode == DFmode || mode == DImode ) ) return <NUM_LIT> ; } else if ( USE_AS_OFFSETABLE_LO10 && GET_CODE ( rs1 ) == LO_SUM && TARGET_ARCH64 && ! TARGET_CM_MEDMID && RTX_OK_FOR_OLO10_P ( rs2 , mode ) ) { rs2 = NULL ; imm1 = XEXP ( rs1 , <NUM_LIT> ) ; rs1 = XEXP ( rs1 , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || ( GET_CODE ( rs1 ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( rs1 ) ) ) return <NUM_LIT> ; } } else if ( GET_CODE ( addr ) == LO_SUM ) { rs1 = XEXP ( addr , <NUM_LIT> ) ; imm1 = XEXP ( addr , <NUM_LIT> ) ; if ( ! CONSTANT_P ( imm1 ) || ( GET_CODE ( rs1 ) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL ( rs1 ) ) ) return <NUM_LIT> ; if ( mode == TFmode && TARGET_ARCH32 ) return <NUM_LIT> ; if ( reload_in_progress && GET_CODE ( rs1 ) == HIGH && XEXP ( rs1 , <NUM_LIT> ) == imm1 ) return <NUM_LIT> ; } else if ( GET_CODE ( addr ) == CONST_INT && SMALL_INT ( addr ) ) return <NUM_LIT> ; else return <NUM_LIT> ; if ( GET_CODE ( rs1 ) == SUBREG ) rs1 = SUBREG_REG ( rs1 ) ; if ( ! REG_P ( rs1 ) ) return <NUM_LIT> ; if ( rs2 ) { if ( GET_CODE ( rs2 ) == SUBREG ) rs2 = SUBREG_REG ( rs2 ) ; if ( ! REG_P ( rs2 ) ) return <NUM_LIT> ; } if ( strict ) { if ( ! REGNO_OK_FOR_BASE_P ( REGNO ( rs1 ) ) || ( rs2 && ! REGNO_OK_FOR_BASE_P ( REGNO ( rs2 ) ) ) ) return <NUM_LIT> ; } else {

if ( ( ! SPARC_INT_REG_P ( REGNO ( rs1 ) ) && REGNO ( rs1 ) != FRAME_POINTER_REGNUM && REGNO ( rs1 ) < FIRST_PSEUDO_REGISTER ) || ( rs2 && ( ! SPARC_INT_REG_P ( REGNO ( rs2 ) ) && REGNO ( rs2 ) != FRAME_POINTER_REGNUM && REGNO ( rs2 ) < FIRST_PSEUDO_REGISTER ) ) ) return <NUM_LIT> ;


<s> end_sequence ( ) ; if ( ! seq ) return NULL ; if ( INSN_P ( seq ) ) { insn = seq ; while ( insn != NULL_RTX ) { RTX_FRAME_RELATED_P ( insn ) = <NUM_LIT> ; insn = NEXT_INSN ( insn ) ; } seq = emit_insn ( seq ) ; } else { seq = emit_insn ( seq ) ; RTX_FRAME_RELATED_P ( seq ) = <NUM_LIT> ; }


<s> bool <ISA_LIT>InstrInfo :: isLateSourceInstr ( const MachineInstr & MI ) const { return MI . getDesc ( ) . getSchedClass ( ) == <STR_LIT> :: CVI_VX_LATE ;


<s> void <ISA_LIT>RegisterInfo :: eliminateFrameIndex ( MachineBasicBlock :: iterator II , int SPAdj , unsigned FIOperandNum , RegScavenger * RS ) const { MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>FunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>FunctionInfo > ( ) ; unsigned i = <NUM_LIT> ; while ( ! MI . getOperand ( i ) . isFI ( ) ) { ++ i ; assert ( i < MI . getNumOperands ( ) && <STR_LIT> ) ; } DEBUG ( errs ( ) << <STR_LIT> << MF . getFunction ( ) -> getName ( ) << <STR_LIT> ;


<s> EVT SrcVT = Op . getOperand ( <NUM_LIT> ) . getValueType ( ) ; if ( SrcVT . isVector ( ) ) { if ( SrcVT == <STR_LIT> && Op . getValueType ( ) == <STR_LIT> ) { return Op ; } return SDValue ( ) ; } assert ( SrcVT . getSimpleVT ( ) <= <STR_LIT> && SrcVT . getSimpleVT ( ) >= <STR_LIT> && <STR_LIT> ) ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) ) return Op ; if ( SrcVT == <STR_LIT> && isScalarFPTypeInSSEReg ( Op . getValueType ( ) ) && Subtarget -> is64Bit ( ) ) { return Op ; } DebugLoc dl = Op . getDebugLoc ( ) ; unsigned Size = SrcVT . getSizeInBits ( ) / <NUM_LIT> ; MachineFunction & MF = DAG . getMachineFunction ( ) ; int SSFI = MF . getFrameInfo ( ) -> CreateStackObject ( Size , Size , false ) ; SDValue StackSlot = DAG . getFrameIndex ( SSFI , getPointerTy ( ) ) ; SDValue Chain = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , PseudoSourceValue :: getFixedStack ( SSFI ) , <NUM_LIT> , false , false , <NUM_LIT> ) ;

return BuildFILD ( Op , SrcVT , Chain , StackSlot , DAG ) ;


<s> for ( MachineBasicBlock * S : MBB -> predecessors ( ) ) if ( S == PrevBB && ! TII -> analyzeBranch ( * PrevBB , TBB , FBB , Cond ) && ! TBB && ! FBB ) return S ;


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) continue ; if ( ! I -> isBranch ( ) ) break ;


<s> unsigned <ISA_LIT>RegisterInfo :: getRARegister ( ) const { return ! Subtarget . is<ISA_LIT>64 ( ) ? <STR_LIT> : <STR_LIT> ;


<s> fprintf ( theFile , <STR_LIT> , Prefix , Num ) ; return ; } if ( strcmp ( Prefix , <STR_LIT> ) == <NUM_LIT> ) { fprintf ( theFile , <STR_LIT> , Num ) ; return ; } fprintf ( theFile , <STR_LIT> , Prefix , Num ) ;


<s> unsigned NewPostIncOpcode = getPostIndexedLoadStoreOpcode ( BaseAccess -> getOpcode ( ) , IncrementOffset > <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; if ( ! isLegalAddressImm ( NewPostIncOpcode , IncrementOffset , TII ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } SmallPtrSet < MachineInstr * , <NUM_LIT> > SuccessorAccesses ; for ( auto * Use : OtherAccesses ) { if ( DT -> dominates ( BaseAccess , Use ) ) { SuccessorAccesses . insert ( Use ) ; unsigned BaseOp = getBaseOperandIndex ( * Use ) ; if ( ! isLegalAddressImm ( Use -> getOpcode ( ) , Use -> getOperand ( BaseOp + <NUM_LIT> ) . getImm ( ) - IncrementOffset , TII ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } else if ( ! DT -> dominates ( Use , BaseAccess ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; BaseAccess -> dump ( ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Increment -> dump ( ) ) ; Register NewBaseReg = Increment -> getOperand ( <NUM_LIT> ) . getReg ( ) ; MachineInstr * BaseAccessPost = createPostIncLoadStore ( BaseAccess , IncrementOffset , NewBaseReg , TII , TRI ) ; BaseAccess -> eraseFromParent ( ) ; Increment -> eraseFromParent ( ) ; ( void ) BaseAccessPost ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; BaseAccessPost -> dump ( ) ) ; for ( auto * Use : SuccessorAccesses ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Use -> dump ( ) ) ; unsigned BaseOp = getBaseOperandIndex ( * Use ) ; Use -> getOperand ( BaseOp ) . setReg ( NewBaseReg ) ; int OldOffset = Use -> getOperand ( BaseOp + <NUM_LIT> ) . getImm ( ) ; Use -> getOperand ( BaseOp + <NUM_LIT> ) . setImm ( OldOffset - IncrementOffset ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Use -> dump ( ) ) ; } for ( MachineOperand & Op : MRI -> use_nodbg_operands ( NewBaseReg ) ) Op . setIsKill ( false ) ;


<s> case CCNOmode : if ( req_mode != CCNOmode && ( req_mode != CCmode || XEXP ( SET_SRC ( set ) , <NUM_LIT> ) != const0_rtx ) ) return <NUM_LIT> ; break ; case CCmode : if ( req_mode == CCGCmode ) return <NUM_LIT> ; case CCGCmode : if ( req_mode == CCGOCmode || req_mode == CCNOmode ) return <NUM_LIT> ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNum , unsigned AsmVariant , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { llvm_unreachable ( <STR_LIT> ) ; } const MachineOperand & MO = MI -> getOperand ( OpNum ) ; ( void ) MO ; assert ( MO . isReg ( ) && <STR_LIT> ) ;

if ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> ) {


<s> void printTBAddrMode ( const MCInst * MI , unsigned OpNum ) {


<s> rtx gen_acc2 ( void ) { return gen_rtx_REG ( SImode , TARGET_BIG_ENDIAN ? <NUM_LIT> : <NUM_LIT> ) ;


<s> return ( Dfmt << DFMT_SHIFT ) | ( Nfmt << NFMT_SHIFT ) ;


<s> RS . forward ( I ) ; AuxReg = RS . FindUnusedReg ( & <STR_LIT> ) ; if ( ! AuxReg ) { WithColor :: warning ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ; continue ; } MO . setReg ( AuxReg ) ; BuildMI ( BB , I , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , AuxReg ) . addReg ( <STR_LIT> ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { MachineOperand & MO = I . getOperand ( <NUM_LIT> ) ; if ( MO . isReg ( ) && MO . getReg ( ) == <STR_LIT> ) { RegScavenger RS ; RS . enterBasicBlock ( BB ) ; RS . forward ( I ) ; AuxReg = RS . FindUnusedReg ( & <STR_LIT> ) ; if ( ! AuxReg ) { WithColor :: warning ( ) << <STR_LIT> << MF . getName ( ) << <STR_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { EVT VT = Op . getValueType ( ) ; if ( VT . isVector ( ) ) return LowerVectorINT_TO_FP ( Op , DAG ) ; if ( ! Subtarget -> hasFP64 ( ) && Op . getValueType ( ) == <STR_LIT> ) { RTLIB :: Libcall LC ; if ( Op . getOpcode ( ) == <STR_LIT> ) LC = RTLIB :: getSINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;

else LC = RTLIB :: getUINTTOFP ( Op . getOperand ( <NUM_LIT> ) . getValueType ( ) , Op . getValueType ( ) ) ;


<s> if ( CONTROL_REGNO_P ( regno ) ) return CONTROL_REGS ; if ( CR_REGNO_P ( regno ) ) { int i , j ; for ( i = USER0_REGS ; i <= USER3_REGS ; ++ i ) { if ( ! TEST_HARD_REG_BIT ( reg_class_contents [ i ] , regno ) ) continue ; for ( j = <NUM_LIT> ; j < N_REG_CLASSES ; ++ j ) { enum reg_class sub = reg_class_subclasses [ i ] [ j ] ; if ( sub == LIM_REG_CLASSES ) return i ;

if ( TEST_HARD_REG_BIT ( reg_class_contents [ sub ] , regno ) ) break ;


<s> Triple :: OSType OS = TT . getOS ( ) ; return OS == Triple :: Darwin || OS == Triple :: MacOSX || OS == Triple :: IOS ;


<s> void printHex16ImmOperand ( const MCInst * MI , int OpNum ) {


<s> if ( ! hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) Amount = - Amount ; if ( Amount ) tm . getInstrInfo ( ) -> adjustStackPtr ( <STR_LIT> , Amount , MBB , I ) ;


<s> if ( ! getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) . empty ( ) ) return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getLinkerPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ;

return OutContext . getOrCreateSymbol ( Twine ( getDataLayout ( ) . getPrivateGlobalPrefix ( ) ) + <STR_LIT> + Twine ( getFunctionNumber ( ) ) + <STR_LIT> + Twine ( CPID ) ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( Ctx ) ;


<s> case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; case <STR_LIT> : assert ( Subtarget -> is64Bit ( ) && <STR_LIT> ) ; Reg = <STR_LIT> ; size = <NUM_LIT> ; break ; } SDValue cpIn = DAG . getCopyToReg ( Op . getOperand ( <NUM_LIT> ) , dl , Reg , Op . getOperand ( <NUM_LIT> ) , SDValue ( ) ) ; SDValue Ops [ ] = { cpIn . getValue ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , DAG . getTargetConstant ( size , <STR_LIT> ) , cpIn . getValue ( <NUM_LIT> ) } ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , dl , Tys , Ops , <NUM_LIT> ) ; SDValue cpOut = DAG . getCopyFromReg ( Result . getValue ( <NUM_LIT> ) , dl , Reg , T , Result . getValue ( <NUM_LIT> ) ) ;


<s> return __builtin_ia32_rorhi ( __X , __C ) ;


<s> MCObjectWriter * createObjectWriter ( raw_ostream & OS ) const override {

uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( OSType ) ;


<s> const LLT v4s32 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; const LLT v2s64 = LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) ; for ( unsigned BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s64 , v2s64 } ) setAction ( { BinOp , Ty } , Legal ) ; for ( unsigned BinOp : { G_ADD , G_SUB } ) for ( auto Ty : { v4s32 } ) setAction ( { BinOp , Ty } , Legal ) ;


<s> for ( auto SI : Stores ) { const MachineMemOperand & SMO = getStoreTarget ( SI ) ; if ( ! SMO . getValue ( ) ) return true ; MemoryLocation SL ( SMO . getValue ( ) , SMO . getSize ( ) , SMO . getAAInfo ( ) ) ;

if ( ! AA -> isNoAlias ( L , SL ) ) return true ;


<s> void <ISA_LIT>PassConfig :: addIRPasses ( ) {

addPass ( createAtomicExpandPass ( & get<ISA_LIT>TargetMachine ( ) ) ) ;


<s> static inline unsigned IsCMP ( unsigned Op ) { switch ( Op ) { default : return false ; case <STR_LIT> : case <STR_LIT> :


<s> Value * MVEGatherScatterLowering :: tryCreateMaskedScatterBase ( IntrinsicInst * I , Value * Ptr , IRBuilder < > & Builder , int64_t Increment ) { using namespace PatternMatch ; Value * Input = I -> getArgOperand ( <NUM_LIT> ) ; auto * Ty = cast < VectorType > ( Input -> getType ( ) ) ; if ( ! ( Ty -> getNumElements ( ) == <NUM_LIT> && Ty -> getScalarSizeInBits ( ) == <NUM_LIT> ) ) {


<s> SDValue getAddrGlobal ( NodeTy * N , SDLoc DL , EVT Ty , SelectionDAG & DAG , unsigned Flag , SDValue Chain , const MachinePointerInfo & PtrInfo ) const { SDValue Tgt = DAG . getNode ( <STR_LIT> , DL , Ty , getGlobalReg ( DAG , Ty ) , getTargetNode ( N , Ty , DAG , Flag ) ) ; return DAG . getLoad ( Ty , DL , Chain , Tgt , PtrInfo , false , false , false , <NUM_LIT> ) ;


<s> assert ( ! ArgType -> isFloatTy ( ) && <STR_LIT> ) ; ArgVT = <STR_LIT> ( ArgSizeInBits ) ; } else { ArgVT = VT ; } PointerType * PtrTy = PointerType :: get ( VT . getTypeForEVT ( * DAG . getContext ( ) ) , <STR_LIT> ) ; SDValue Arg = DAG . getExtLoad ( <STR_LIT> , DL , VT , DAG . getRoot ( ) , DAG . getConstant ( ParamOffsetBytes , <STR_LIT> ) , MachinePointerInfo ( UndefValue :: get ( PtrTy ) ) , ArgVT , false , false , ArgBytes ) ; InVals . push_back ( Arg ) ; ParamOffsetBytes += ArgBytes ; }


<s> else MaskBit = ( ITState . Mask >> ( <NUM_LIT> - ITState . CurPosition ) ) & <NUM_LIT> ; return MaskBit ? ITState . Cond : <STR_LIT> ( ITState . Cond ) ;


<s> case <STR_LIT> : return MCSymbolRefExpr :: VK_GOT ; case <STR_LIT> : return MCSymbolRefExpr :: VK_INDNTPOFF ; } llvm_unreachable ( <STR_LIT> ) ;


<s> printThumbLdrLabelOperand ( MI , OpNum , STI , O ) ;


<s> Iter Filler ; RegDU . setCallerSaved ( * Slot ) ;

if ( ! searchRange ( MBB , std :: next ( Slot ) , MBB . end ( ) , RegDU , NM , Slot , Filler ) ) return false ;


<s> int total_frame_size ; int sp_offset ; int save_regs_base ; int save_offset ; total_frame_size = cfun -> machine -> total_size ; if ( flag_stack_usage_info ) current_function_static_stack_size = total_frame_size ; if ( ! UBYTE_INT ( total_frame_size ) ) { pru_add_to_sp ( cfun -> machine -> save_regs_offset - total_frame_size , REG_NOTE_MAX ) ; save_regs_base = <NUM_LIT> ; sp_offset = - cfun -> machine -> save_regs_offset ;


<s> if ( SM ) SM -> PrintMessage ( I . first , SourceMgr :: DK_Note , I . second ) ; } Context . reportError ( Loc , Msg ) ;