<s> DEBUG ( dbgs ( ) << <STR_LIT> << * GV << '\n' ) ; auto * NewPtr = ConstantExpr :: getPointerCast ( GV , AddrCast -> getType ( ) ) ; AddrCast -> replaceAllUsesWith ( NewPtr ) ; F . addFnAttr ( <STR_LIT> , RuntimeHandle ) ; F . setLinkage ( GlobalValue :: ExternalLinkage ) ; for ( auto U : NewPtr -> users ( ) ) { if ( auto * I = dyn_cast < Instruction > ( & * U ) ) { auto * F = I -> getParent ( ) -> getParent ( ) ; Callers . insert ( F ) ; collectCallers ( F , Callers ) ; } } Changed = true ; } } for ( auto F : Callers ) {

if ( F -> getCallingConv ( ) != CallingConv :: <ISA_LIT>_KERNEL ) continue ;


<s> case LSHIFTRT : if ( ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , <NUM_LIT> ) ) , <NUM_LIT> , <NUM_LIT> ) ) return false ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; break ; case NEG : case NOT : break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ;


<s> return __builtin_aarch64_clrsbv16qi ( __a ) ;


<s> const TargetRegisterClass * RC = STI . in<ISA_LIT>16Mode ( ) ? & <STR_LIT> : STI . inMicro<ISA_LIT>Mode ( ) ? & <STR_LIT> : static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) . getABI ( ) . IsN64 ( ) ? & <STR_LIT> : & <STR_LIT> ; return GlobalBaseReg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ;


<s> assert ( UF != Uses . end ( ) && <STR_LIT> ) ; UseSet & Us = UF -> second ; for ( const auto & U : Us ) Values . push_back ( U -> getUser ( ) ) ; } NodeChildrenMap :: iterator CF = NCM . find ( N ) ; if ( CF != NCM . end ( ) ) { NodeVect & Cs = CF -> second ; llvm :: append_range ( Work , Cs ) ; }


<s> const TargetRegisterClass * Thumb1RegisterInfo :: getLargestLegalSuperClass ( const TargetRegisterClass * RC ) const { if ( <STR_LIT> . hasSubClassEq ( RC ) ) return <STR_LIT> ; return <ISA_LIT>BaseRegisterInfo :: getLargestLegalSuperClass ( RC ) ;


<s> markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , getFramePointerReg ( STI ) ) ; if ( hasBasePointer ( MF ) ) markSuperRegs ( Reserved , BasePtr ) ; if ( STI . isR9Reserved ( ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! STI . hasVFP3 ( ) || STI . hasD16 ( ) ) { static_assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> , <STR_LIT> ) ; for ( unsigned R = <NUM_LIT> ; R < <NUM_LIT> ; ++ R ) markSuperRegs ( Reserved , <STR_LIT> + R ) ; } const TargetRegisterClass & RC = <STR_LIT> ;

for ( unsigned Reg : RC ) for ( MCSubRegIterator SI ( Reg , this ) ; SI . isValid ( ) ; ++ SI ) if ( Reserved . test ( * SI ) ) markSuperRegs ( Reserved , Reg ) ;


<s> SDValue TrueValue = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseValue = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ;

EVT TrueType = TrueValue . getValueType ( ) ;


<s> bool allocateSeparateGVMemory ( ) const override { return true ;


Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> __arm_cdp ( const unsigned int __coproc , const unsigned int __opc1 , const unsigned int __CRd , const unsigned int __CRn , const unsigned int __CRm , const unsigned int __opc2 ) { __builtin_arm_cdp ( __coproc , __opc1 , __CRd , __CRn , __CRm , __opc2 ) ;


<s> bool SelectDupZero ( SDValue N ) { switch ( N -> getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : { auto Opnd0 = N -> getOperand ( <NUM_LIT> ) ; if ( auto CN = dyn_cast < ConstantSDNode > ( Opnd0 ) ) if ( CN -> isZero ( ) ) return true ; if ( auto CN = dyn_cast < ConstantFPSDNode > ( Opnd0 ) ) if ( CN -> isZero ( ) ) return true ; break ;


<s> MCSection * <ISA_LIT>HSATargetObjectFile :: SelectSectionForGlobal ( const GlobalValue * GV , SectionKind Kind , Mangler & Mang , const TargetMachine & TM ) const { if ( Kind . isText ( ) && ! GV -> hasComdat ( ) ) return getTextSection ( ) ; if ( <STR_LIT> ( GV ) ) { if ( isAgentAllocation ( GV ) ) return DataGlobalAgentSection ; if ( isProgramAllocation ( GV ) ) return DataGlobalProgramSection ; }

return <ISA_LIT>TargetObjectFile :: SelectSectionForGlobal ( GV , Kind , Mang , TM ) ;


<s> Relocation :: Type type = pRelocation . type ( ) ; if ( type >= sizeof ( <ISA_LIT>_64ApplyFunctions ) / sizeof ( <ISA_LIT>_64ApplyFunctions [ <NUM_LIT> ] ) ) { return Unknown ; } return <ISA_LIT>_64ApplyFunctions [ type ] . func ( pRelocation , * this ) ;


<s> case TYPE_DDIV : case TYPE_VECDIV : case TYPE_SSQRT : case TYPE_DSQRT : return false ;


<s> MachineRegisterInfo & MRI = Root . getParent ( ) -> getMF ( ) -> getRegInfo ( ) ; MachineInstr * PtrAdd = getOpcodeDef ( TargetOpcode :: G_PTR_ADD , Root . getReg ( ) , MRI ) ; if ( ! PtrAdd || ! isWorthFoldingIntoExtendedReg ( * PtrAdd , MRI ) ) return None ; MachineInstr * OffsetInst = getDefIgnoringCopies ( PtrAdd -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ;

return selectExtendedSHL ( Root , PtrAdd -> getOperand ( <NUM_LIT> ) , OffsetInst -> getOperand ( <NUM_LIT> ) , SizeInBytes , false ) ;


<s> if ( Ty . getSizeInBits ( ) <= <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return GetAllRegSet ? & <STR_LIT> : & <STR_LIT> ; if ( Ty . getSizeInBits ( ) == <NUM_LIT> ) return & <STR_LIT> ; return nullptr ; } if ( RB . getID ( ) == <STR_LIT> ) { switch ( Ty . getSizeInBits ( ) ) { case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; case <NUM_LIT> : return & <STR_LIT> ; }


<s> return __arm_vld1q_z_f32 ( __base , __p ) ;


<s> rtx tmp = gen_rtx_REG ( Pmode , TEMP_REG_NUM ) ; emit_insn ( gen_load_got_register ( pic_offset_table_rtx , tmp ) ) ;

emit_insn ( gen_add3_insn ( pic_offset_table_rtx , pic_offset_table_rtx , tmp ) ) ;


<s> bool <ISA_LIT>TargetMachine :: symbolicAddressesAreRIPRel ( ) const { return getRelocationModel ( ) != Reloc :: Static && Subtarget . isPICStyleRIPRel ( ) ;


<s> MachineBasicBlock * NextBB = std :: next ( MBBI ) ;

for ( MachineBasicBlock :: succ_iterator I = MBB -> succ_begin ( ) , E = MBB -> succ_end ( ) ; I != E ; ++ I ) if ( * I == NextBB ) return true ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { DebugLoc dl = Op . getDebugLoc ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue Result = DAG . getBlockAddress ( BA , getPointerTy ( ) , true ) ; return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Result ) ;


<s> getTargetStreamer ( ) . EmitARM64WinCFISaveFPLR ( Offset ) ;


<s> return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ; } if ( Src == <STR_LIT> && Dest == <STR_LIT> ) { SDValue Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue Hi = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo , Hi ) ;


<s> VSETVLIInfo ( ) : AVLImm ( <NUM_LIT> ) , TailAgnostic ( false ) , MaskAgnostic ( false ) , MaskRegOp ( false ) , StoreOp ( false ) , ScalarMovOp ( false ) , SEWLMULRatioOnly ( false ) {


<s> for ( unsigned int regno = <NUM_LIT> ; regno < FIRST_PSEUDO_REGISTER ; regno ++ ) if ( TEST_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ) { if ( regno >= SPARC_FCC_REG || ( regno >= SPARC_FIRST_FP_REG && ! TARGET_VIS ) ) CLEAR_HARD_REG_BIT ( need_zeroed_hardregs , regno ) ; else if ( regno >= SPARC_FIRST_V9_FP_REG && ( regno & <NUM_LIT> ) ) ; else {


<s> REAL_VALUE_TYPE r ; if ( ! const_vec_duplicate_p ( x , & elt ) || ! CONST_DOUBLE_P ( elt ) ) return false ; r = * CONST_DOUBLE_REAL_VALUE ( elt ) ; if ( negate_p ) r = real_value_negate ( & r ) ; if ( real_equal ( & r , & dconst1 ) ) return true ;

if ( real_equal ( & r , & dconsthalf ) ) return true ;


<s> RTX_FRAME_RELATED_P ( x ) = <NUM_LIT> ;


SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ;


<s> case E_QImode : return V16QImode ; case E_HImode : return V8HImode ; case E_SImode : return V4SImode ; case E_DImode : return V2DImode ; case E_SFmode : return V4SFmode ;


<s> GEPInfo GEPInfo ( * PtrMI ) ; for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { const MachineOperand & GEPOp = PtrMI -> getOperand ( i ) ; const MachineInstr * OpDef = MRI . getUniqueVRegDef ( GEPOp . getReg ( ) ) ; assert ( OpDef ) ; if ( i == <NUM_LIT> && isConstant ( * OpDef ) ) { assert ( GEPInfo . Imm == <NUM_LIT> ) ; GEPInfo . Imm = OpDef -> getOperand ( <NUM_LIT> ) . getCImm ( ) -> getSExtValue ( ) ; continue ; } const RegisterBank * OpBank = RBI . getRegBank ( GEPOp . getReg ( ) , MRI , TRI ) ; if ( OpBank -> getID ( ) == <STR_LIT> ) GEPInfo . SgprParts . push_back ( GEPOp . getReg ( ) ) ;

else GEPInfo . VgprParts . push_back ( GEPOp . getReg ( ) ) ;


eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {


<s> OutStreamer -> SwitchSection ( cast < MCSymbolXCOFF > ( CurrentFnDescSym ) -> getContainingCsect ( ) ) ; OutStreamer -> emitLabel ( CurrentFnDescSym ) ; OutStreamer -> emitValue ( MCSymbolRefExpr :: create ( CurrentFnSym , OutContext ) , PointerSize ) ;

const MCSymbol * TOCBaseSym = cast < MCSectionXCOFF > ( getObjFileLowering ( ) . getTOCBaseSection ( ) ) -> getQualNameSymbol ( ) ;


<s> machine_mode in_mode , out_mode ; int in_n , out_n ; if ( TREE_CODE ( type_out ) != VECTOR_TYPE || TREE_CODE ( type_in ) != VECTOR_TYPE ) return NULL_TREE ; out_mode = TYPE_MODE ( TREE_TYPE ( type_out ) ) ; out_n = TYPE_VECTOR_SUBPARTS ( type_out ) ; in_mode = TYPE_MODE ( TREE_TYPE ( type_in ) ) ; in_n = TYPE_VECTOR_SUBPARTS ( type_in ) ; switch ( fn ) { CASE_CFN_IFLOOR : CASE_CFN_LFLOOR : if ( flag_trapping_math || ! TARGET_SSE4_1 ) break ; if ( out_mode == SImode && in_mode == DFmode ) { if ( out_n == <NUM_LIT> && in_n == <NUM_LIT> ) return ix86_get_builtin ( IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX ) ; else if ( out_n == <NUM_LIT> && in_n == <NUM_LIT> ) return ix86_get_builtin ( IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256 ) ; else if ( out_n == <NUM_LIT> && in_n == <NUM_LIT> ) return ix86_get_builtin ( IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512 ) ; } break ; CASE_CFN_ICEIL : CASE_CFN_LCEIL : if ( flag_trapping_math || ! TARGET_SSE4_1 ) break ; if ( out_mode == SImode && in_mode == DFmode ) { if ( out_n == <NUM_LIT> && in_n == <NUM_LIT> ) return ix86_get_builtin ( IX86_BUILTIN_CEILPD_VEC_PACK_SFIX ) ; else if ( out_n == <NUM_LIT> && in_n == <NUM_LIT> ) return ix86_get_builtin ( IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256 ) ; else if ( out_n == <NUM_LIT> && in_n == <NUM_LIT> ) return ix86_get_builtin ( IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512 ) ; } break ; CASE_CFN_IRINT : CASE_CFN_LRINT : if ( out_mode == SImode && in_mode == DFmode ) { if ( out_n == <NUM_LIT> && in_n == <NUM_LIT> ) return ix86_get_builtin ( IX86_BUILTIN_VEC_PACK_SFIX ) ; else if ( out_n == <NUM_LIT> && in_n == <NUM_LIT> ) return ix86_get_builtin ( IX86_BUILTIN_VEC_PACK_SFIX256 ) ; else if ( out_n == <NUM_LIT> && in_n == <NUM_LIT> ) return ix86_get_builtin ( IX86_BUILTIN_VEC_PACK_SFIX512 ) ; } break ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; default :


<s> outs ( ) << <STR_LIT> << higherByte << <STR_LIT> ; outs ( ) << <STR_LIT> << lowerByte << <STR_LIT> ; if ( ImmVal == <NUM_LIT> ) { SDValue _constVal = CurDAG -> getTargetConstant ( <NUM_LIT> , N , <STR_LIT> ) ; SDValue _width = CurDAG -> getTargetConstant ( <NUM_LIT> , N , <STR_LIT> ) ; SDValue _pos = CurDAG -> getTargetConstant ( <NUM_LIT> , N , <STR_LIT> ) ; return CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , _constVal , _pos , _width ) ; } if ( ImmSVal < <NUM_LIT> || ( higherByte != <NUM_LIT> && lowerByte != <NUM_LIT> ) ) { outs ( ) << <STR_LIT> ; return SelectCode ( N ) ; } else if ( higherByte == <NUM_LIT> && lowerByte != <NUM_LIT> ) { uint64_t posLSB = getFFS ( lowerByte ) - <NUM_LIT> ; uint64_t numSetBits = getNumSetBits ( lowerByte ) ; uint64_t numConsecBits = getNumConsecutiveOnes ( lowerByte ) ; if ( numSetBits != numConsecBits ) return SelectCode ( N ) ; if ( numConsecBits > <NUM_LIT> ) return SelectCode ( N ) ; int64_t Const4Val = ipow ( numConsecBits ) - <NUM_LIT> ; outs ( ) << <STR_LIT> << posLSB << <STR_LIT> ; outs ( ) << <STR_LIT> << Const4Val << <STR_LIT> ; SDValue _constVal = CurDAG -> getTargetConstant ( Const4Val , N , <STR_LIT> ) ; SDValue _width = CurDAG -> getTargetConstant ( width , N , <STR_LIT> ) ; SDValue _pos = CurDAG -> getTargetConstant ( posLSB , N , <STR_LIT> ) ; return CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , _constVal , _pos , _width ) ; } else if ( higherByte != <NUM_LIT> && lowerByte == <NUM_LIT> ) { uint64_t posLSB = getFFS ( higherByte ) - <NUM_LIT> ; uint64_t numSetBits = getNumSetBits ( higherByte ) ; uint64_t numConsecBits = getNumConsecutiveOnes ( higherByte ) ; outs ( ) << <STR_LIT> << posLSB << <STR_LIT> ; outs ( ) << <STR_LIT> << numConsecBits << <STR_LIT> ; if ( numSetBits != numConsecBits ) return SelectCode ( N ) ; if ( ( posLSB + numConsecBits ) > <NUM_LIT> ) return SelectCode ( N ) ; SDValue _constVal = CurDAG -> getTargetConstant ( <NUM_LIT> , N , <STR_LIT> ) ; SDValue _width = CurDAG -> getTargetConstant ( numConsecBits , N , <STR_LIT> ) ; SDValue _pos = CurDAG -> getTargetConstant ( posLSB , N , <STR_LIT> ) ; return CurDAG -> getMachineNode ( <STR_LIT> , N , <STR_LIT> , _constVal , _pos , _width ) ; } } uint64_t LoMask = <NUM_LIT> ; uint64_t HiMask = <NUM_LIT> ; uint64_t ImmLo = ( ImmVal & LoMask ) ; int64_t ImmSLo = ( ImmSVal & LoMask ) - <NUM_LIT> ; uint64_t ImmHi = ( ImmVal & HiMask ) ; SDValue ConstLo = CurDAG -> getTargetConstant ( ImmLo , N , <STR_LIT> ) ; SDValue ConstSImm = CurDAG -> getTargetConstant ( ImmSVal , N , <STR_LIT> ) ; SDValue ConstEImm = CurDAG -> getTargetConstant ( ImmVal , N , <STR_LIT> ) ; SDValue ConstHi ; int64_t ImmLo_ext64 = ( int16_t ) ImmLo ;

int64_t hiShift = ( ImmSVal - ImmLo_ext64 ) >> <NUM_LIT> ;


<s> if ( ! BasePtr ) return nullptr ; Value * Store = tryCreateIncrementingGatScat ( I , BasePtr , Offsets , GEP , Builder ) ; if ( Store ) return Store ; int Scale = computeScale ( BasePtr -> getType ( ) -> getPointerElementType ( ) -> getPrimitiveSizeInBits ( ) , MemoryTy -> getScalarSizeInBits ( ) ) ; if ( Scale == - <NUM_LIT> ) return nullptr ; if ( ! match ( Mask , m_One ( ) ) ) return Builder . CreateIntrinsic ( <STR_LIT> , { BasePtr -> getType ( ) , Offsets -> getType ( ) , Input -> getType ( ) , Mask -> getType ( ) } , { BasePtr , Offsets , Input , Builder . getInt32 ( MemoryTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) , Mask } ) ; else return Builder . CreateIntrinsic ( <STR_LIT> , { BasePtr -> getType ( ) , Offsets -> getType ( ) , Input -> getType ( ) } , { BasePtr , Offsets , Input , Builder . getInt32 ( MemoryTy -> getScalarSizeInBits ( ) ) , Builder . getInt32 ( Scale ) } ) ;


<s> return recog_data . operand [ get_attr_vl_op_idx ( rinsn ) ] ; }

return SET_DEST ( XVECEXP ( PATTERN ( rinsn ) , <NUM_LIT> , <NUM_LIT> ) ) ;


__builtin_ia32_storedqudi256_mask ( ( long long * ) __P , ( __v4di ) __A , ( __mmask8 ) __U ) ;


<s> static SDValue AddRequiredExtensionForVMULL ( SDValue N , SelectionDAG & DAG , const EVT & OrigTy , const EVT & ExtTy , unsigned ExtOpcode ) { assert ( ExtTy . is128BitVector ( ) && <STR_LIT> ) ; if ( OrigTy . getSizeInBits ( ) >= <NUM_LIT> ) return N ;

EVT NewVT = getExtensionTo64Bits ( OrigTy ) ;


<s> bool res = false ; for ( insn = prev_nonnote_nondebug_insn ( current_output_insn ) ; insn != NULL_RTX ; insn = prev_nonnote_nondebug_insn ( insn ) ) { if ( LABEL_P ( insn ) ) break ; if ( ! INSN_P ( insn ) ) continue ; if ( recog_memoized ( insn ) == - <NUM_LIT> ) continue ; enum attr_update_Z updated = get_attr_update_Z ( insn ) ; rtx set = single_set ( insn ) ; bool must_break = ( set != NULL_RTX && rtx_equal_p ( operand , SET_DEST ( set ) ) ) ; switch ( updated ) { case UPDATE_Z_NO : break ; case UPDATE_Z_CLOBBER : must_break = true ; break ; case UPDATE_Z_UPDATE_Z :


<s> return regno == NVPTX_RETURN_REGNUM ;


<s> SDValue NewLD1 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , BasePtr , LD -> getPointerInfo ( ) , LD -> getAlignment ( ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; SDValue OffsetPtr = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; SDValue NewLD2 = DAG . getLoad ( <STR_LIT> , DL , LD -> getChain ( ) , OffsetPtr , LD -> getPointerInfo ( ) . getWithOffset ( <NUM_LIT> ) , std :: min ( <NUM_LIT> , LD -> getAlignment ( ) ) , LD -> getMemOperand ( ) -> getFlags ( ) ) ; DAG . ReplaceAllUsesOfValueWith ( SDValue ( LD , <NUM_LIT> ) , NewLD2 . getValue ( <NUM_LIT> ) ) ; if ( DCI . DAG . getDataLayout ( ) . isBigEndian ( ) ) std :: swap ( NewLD1 , NewLD2 ) ; SDValue Result = DCI . CombineTo ( N , NewLD1 , NewLD2 ) ; return Result ;


<s> if ( SDValue V = combineBinOpToReduce ( N , DAG ) ) return V ;

return combineSelectAndUseCommutative ( N , DAG , false ) ;


<s> static int vax_address_cost ( rtx x ) { return ( <NUM_LIT> + ( GET_CODE ( x ) == REG ? <NUM_LIT> : vax_address_cost_1 ( x ) ) ) ;


<s> for ( const auto & Record : Updates ) InsertionOrder . insert ( std :: make_pair ( Record . C , InsertionOrder . size ( ) ) ) ; std :: stable_sort ( Updates . begin ( ) , Updates . end ( ) , [ & InsertionOrder ] ( const UpdateRecord & L , const UpdateRecord & R ) {

return InsertionOrder . lookup ( L . C ) < InsertionOrder . lookup ( R . C ) ;


<s> default : gcc_unreachable ( ) ; case ABI_AIX : if ( DOT_SYMBOLS ) putc ( '.' , file ) ; else ASM_OUTPUT_INTERNAL_LABEL_PREFIX ( file , <STR_LIT> ) ; break ;


<s> void <ISA_LIT>SchedStrategy :: releaseBottomNode ( SUnit * SU ) {

DEBUG ( dbgs ( ) << <STR_LIT> ; SU -> dump ( DAG ) ; ) ;


<s> PointerType * PtrTy = dyn_cast < PointerType > ( Ptr -> getType ( ) ) ; if ( ! PtrTy && Ptr -> getType ( ) -> isVectorTy ( ) ) PtrTy = dyn_cast < PointerType > ( cast < VectorType > ( Ptr -> getType ( ) ) -> getElementType ( ) ) ; assert ( PtrTy && <STR_LIT> ) ; unsigned AddressSpace = PtrTy -> getAddressSpace ( ) ; bool Scalarize = false ;

if ( ( Opcode == Instruction :: Load && ! isLegalMaskedGather ( SrcVTy , Align ( Alignment ) ) ) || ( Opcode == Instruction :: Store && ! isLegalMaskedScatter ( SrcVTy , Align ( Alignment ) ) ) ) Scalarize = true ;


<s> MachineConstEvaluator ( MachineFunction & Fn ) : TRI ( * Fn . getSubtarget ( ) . getRegisterInfo ( ) ) , MF ( Fn ) , CX ( Fn . getFunction ( ) . getContext ( ) ) {


<s> FunctionPass * createR600LowerConstCopy ( TargetMachine & tm ) { return new R600LowerConstCopy ( tm ) ;


<s> return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerUINT_TO_FP ( SDValue Op , SelectionDAG & DAG ) const { SDValue N0 = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; if ( Op . getValueType ( ) . isVector ( ) ) return lowerUINT_TO_FP_vec ( Op , DAG ) ; if ( DAG . SignBitIsZero ( N0 ) ) return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , N0 ) ; MVT SrcVT = N0 . getSimpleValueType ( ) ; MVT DstVT = Op . getSimpleValueType ( ) ; if ( SrcVT == <STR_LIT> && DstVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i64 ( Op , DAG ) ; if ( SrcVT == <STR_LIT> && <ISA_LIT>ScalarSSEf64 ) return LowerUINT_TO_FP_i32 ( Op , DAG ) ; if ( Subtarget -> is64Bit ( ) && SrcVT == <STR_LIT> && DstVT == <STR_LIT> ) return SDValue ( ) ; SDValue StackSlot = DAG . CreateStackTemporary ( <STR_LIT> ) ; if ( SrcVT == <STR_LIT> ) { SDValue WordOff = DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) ) ; SDValue OffsetSlot = DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , StackSlot , WordOff ) ; SDValue Store1 = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Store2 = DAG . getStore ( Store1 , dl , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , OffsetSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; SDValue Fild = BuildFILD ( Op , <STR_LIT> , Store2 , StackSlot , DAG ) ; return Fild ; } assert ( SrcVT == <STR_LIT> && <STR_LIT> ) ; SDValue Store = DAG . getStore ( DAG . getEntryNode ( ) , dl , Op . getOperand ( <NUM_LIT> ) , StackSlot , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; int SSFI = cast < FrameIndexSDNode > ( StackSlot ) -> getIndex ( ) ; MachineMemOperand * MMO = DAG . getMachineFunction ( ) . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( SSFI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , <NUM_LIT> ) ; SDVTList Tys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ;

SDValue Ops [ ] = { Store , StackSlot , DAG . getValueType ( <STR_LIT> ) } ;


<s> MCAsmBackend * llvm :: create<ISA_LIT>AsmBackend ( const llvm :: Target & T , const llvm :: MCSubtargetInfo & STI , const llvm :: MCRegisterInfo & MRI , const llvm :: MCTargetOptions & Options ) {

return new <ISA_LIT>AsmBackend ( T , STI . getTargetTriple ( ) . getOS ( ) ) ;


<s> else if ( TREE_CODE ( type ) == COMPLEX_TYPE ) { if ( TYPE_MODE ( type ) == DCmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ( TYPE_MODE ( type ) == XCmode || TYPE_MODE ( type ) == TCmode ) && align < <NUM_LIT> ) return <NUM_LIT> ; } else if ( ( TREE_CODE ( type ) == RECORD_TYPE || TREE_CODE ( type ) == UNION_TYPE || TREE_CODE ( type ) == QUAL_UNION_TYPE ) && TYPE_FIELDS ( type ) ) { if ( DECL_MODE ( TYPE_FIELDS ( type ) ) == DFmode && align < <NUM_LIT> ) return <NUM_LIT> ; if ( ALIGN_MODE_128 ( DECL_MODE ( TYPE_FIELDS ( type ) ) ) && align < <NUM_LIT> ) return <NUM_LIT> ; }

else if ( TREE_CODE ( type ) == REAL_TYPE || TREE_CODE ( type ) == VECTOR_TYPE || TREE_CODE ( type ) == INTEGER_TYPE ) {


<s> for ( unsigned I = <NUM_LIT> , E = array_lengthof ( Match ) ; I != E ; ++ I ) { Tmp . back ( ) = Suffixes [ I ] ; Match [ I ] = MatchInstructionImpl ( Operands , Inst , ErrorInfoIgnore , MatchingInlineAsm , isParsingIntelSyntax ( ) ) ; if ( Match [ I ] == Match_MissingFeature ) ErrorInfoMissingFeature = ErrorInfoIgnore ; } Op . setTokenValue ( Base ) ; unsigned NumSuccessfulMatches = std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_Success ) ; if ( NumSuccessfulMatches == <NUM_LIT> ) { Inst . setLoc ( IDLoc ) ; if ( ! MatchingInlineAsm ) EmitInstruction ( Inst , Operands , Out ) ; Opcode = Inst . getOpcode ( ) ; return false ; } if ( NumSuccessfulMatches > <NUM_LIT> ) { char MatchChars [ <NUM_LIT> ] ; unsigned NumMatches = <NUM_LIT> ; for ( unsigned I = <NUM_LIT> , E = array_lengthof ( Match ) ; I != E ; ++ I ) if ( Match [ I ] == Match_Success ) MatchChars [ NumMatches ++ ] = Suffixes [ I ] ; SmallString < <NUM_LIT> > Msg ; raw_svector_ostream OS ( Msg ) ; OS << <STR_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumMatches ; ++ i ) { if ( i != <NUM_LIT> ) OS << <STR_LIT> ; if ( i + <NUM_LIT> == NumMatches ) OS << <STR_LIT> ; OS << <STR_LIT> << Base << MatchChars [ i ] << <STR_LIT> ; } OS << <STR_LIT> ; Error ( IDLoc , OS . str ( ) , EmptyRanges , MatchingInlineAsm ) ; return true ; } if ( std :: count ( std :: begin ( Match ) , std :: end ( Match ) , Match_MnemonicFail ) == <NUM_LIT> ) { if ( ! WasOriginallyInvalidOperand ) {

ArrayRef < SMRange > Ranges = MatchingInlineAsm ? EmptyRanges : Op . getLocRange ( ) ;


<s> static SDValue lowerV16I32VectorShuffle ( const SDLoc & DL , ArrayRef < int > Mask , SDValue V1 , SDValue V2 , const <ISA_LIT>Subtarget & Subtarget , SelectionDAG & DAG ) { assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ;

SmallVector < int , <NUM_LIT> > RepeatedMask ;


<s> int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) { unsigned SlotSize = RegInfo -> getSlotSize ( ) ; ReturnAddrIndex = MF . getFrameInfo ( ) -> CreateFixedObject ( SlotSize , - ( int64_t ) SlotSize , false ) ; FuncInfo -> setRAIndex ( ReturnAddrIndex ) ; }

return DAG . getFrameIndex ( ReturnAddrIndex , Subtarget -> is64Bit ( ) ? <STR_LIT> : <STR_LIT> ) ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) {

SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( RegNo > <NUM_LIT> ) return Fail ; unsigned Register = ZZDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return Success ;


<s> SDValue ShiftVal = Op . getOperand ( <NUM_LIT> ) ; uint64_t MaskVal = LaneT . getSizeInBits ( ) - <NUM_LIT> ; SDValue MaskedShiftVal = DAG . getNode ( <STR_LIT> , DL , ShiftVal . getValueType ( ) , ShiftVal , DAG . getConstant ( MaskVal , DL , ShiftVal . getValueType ( ) ) ) ; return DAG . UnrollVectorOp ( DAG . getNode ( Op . getOpcode ( ) , DL , Op . getValueType ( ) , Op . getOperand ( <NUM_LIT> ) , MaskedShiftVal ) . getNode ( ) ) ;


<s> EVT InScalarVT = InVT . getVectorElementType ( ) ; if ( InScalarVT . getSizeInBits ( ) <= ScalarVT . getSizeInBits ( ) ) return SDValue ( ) ; if ( ! Subtarget . hasSSE2 ( ) ) return SDValue ( ) ; if ( In . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; auto IsConstVectorInRange = [ ] ( SDValue V , unsigned Min , unsigned Max ) { BuildVectorSDNode * BV = dyn_cast < BuildVectorSDNode > ( V ) ; if ( ! BV || ! BV -> isConstant ( ) ) return false ; for ( SDValue Op : V -> ops ( ) ) { ConstantSDNode * C = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! C ) return false ; const APInt & Val = C -> getAPIntValue ( ) ; if ( Val . ult ( Min ) || Val . ugt ( Max ) ) return false ; } return true ; } ; auto LHS = In . getOperand ( <NUM_LIT> ) ; auto RHS = In . getOperand ( <NUM_LIT> ) ; if ( ! IsConstVectorInRange ( RHS , <NUM_LIT> , <NUM_LIT> ) ) return SDValue ( ) ; if ( LHS . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Operands [ <NUM_LIT> ] ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; Operands [ <NUM_LIT> ] = LHS . getOperand ( <NUM_LIT> ) ; auto AVGBuilder = [ ] ( SelectionDAG & DAG , const SDLoc & DL , ArrayRef < SDValue > Ops ) { return DAG . getNode ( <STR_LIT> , DL , Ops [ <NUM_LIT> ] . getValueType ( ) , Ops ) ; } ;

if ( IsConstVectorInRange ( Operands [ <NUM_LIT> ] , <NUM_LIT> , ScalarVT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ) && Operands [ <NUM_LIT> ] . getOpcode ( ) == <STR_LIT> && Operands [ <NUM_LIT> ] . getOperand ( <NUM_LIT> ) . getValueType ( ) == VT ) {


<s> assert ( ! RegInfo -> needsStackRealignment ( MF ) && <STR_LIT> ) ;

return ( MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( ) || MFI -> isFrameAddressTaken ( ) ) ;


<s> if ( mode == V16SFmode || mode == V8DFmode ) emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , b ) , UNSPEC_RCP14 ) ) ) ; else emit_insn ( gen_rtx_SET ( x0 , gen_rtx_UNSPEC ( mode , gen_rtvec ( <NUM_LIT> , b ) , UNSPEC_RCP ) ) ) ; emit_insn ( gen_rtx_SET ( e0 , gen_rtx_MULT ( mode , x0 , b ) ) ) ;


<s> i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( MO . isReg ( ) && MO . isDef ( ) && MO . getReg ( ) == <STR_LIT> ) { definesCPSR = true ; if ( MO . isDead ( ) ) deadCPSR = true ; MI -> RemoveOperand ( i ) ; break ; } } if ( ! definesCPSR ) { assert ( ! NewOpc && <STR_LIT> ) ; return ; } assert ( deadCPSR == ! Node -> hasAnyUseOfValue ( <NUM_LIT> ) && <STR_LIT> ) ; if ( deadCPSR ) { assert ( ! MI -> getOperand ( ccOutIdx ) . getReg ( ) && <STR_LIT> ) ; return ; }

MachineOperand & MO = MI -> getOperand ( ccOutIdx ) ;


<s> unsigned getMemBaseReg ( ) const { assert ( isMem ( ) && <STR_LIT> ) ;


<s> SDValue helperConvertvvpNodeCreate ( const SDValue & SDNodeArg , SDLoc & DL , SelectionDAG & DAG , unsigned opType , unsigned switchType , EVT ResultVT ) { SmallVector < SDValue , <NUM_LIT> > Ops ( <NUM_LIT> ) ; Ops [ <NUM_LIT> ] = SDNodeArg ; Ops [ <NUM_LIT> ] = DAG . getTargetConstant ( opType , DL , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getTargetConstant ( switchType , DL , <STR_LIT> ) ; Ops [ <NUM_LIT> ] = DAG . getUNDEF ( ResultVT ) ; Ops [ <NUM_LIT> ] = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;

Ops [ <NUM_LIT> ] = DAG . getTargetConstant ( <NUM_LIT> , DL , <STR_LIT> ) ;


<s> Value * RegNodeI8 = Builder . CreateBitCast ( RegNode , Builder . getInt8PtrTy ( ) ) ; Builder . CreateCall ( <STR_LIT> ( TheModule , <STR_LIT> ) , { RegNodeI8 } ) ; if ( isAsynchronousEHPersonality ( Personality ) ) calculateSEHStateNumbers ( & F , FuncInfo ) ; else calculateWinCXXEHStateNumbers ( & F , FuncInfo ) ; DenseMap < BasicBlock * , ColorVector > BlockColors = colorEHFunclets ( F ) ; for ( BasicBlock & BB : F ) { int BaseState = - <NUM_LIT> ; auto & BBColors = BlockColors [ & BB ] ;

assert ( BBColors . size ( ) == <NUM_LIT> && <STR_LIT> ) ;


<s> static unsigned getRetOpcode ( const <ISA_LIT>Subtarget & Subtarget ) {

return Subtarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ;


<s> void addRegQBRCOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( QFRegs [ getReg ( ) ] ) ) ;


<s> MFI -> setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc DL ( Op ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , DL , <STR_LIT> , VT ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; while ( Depth -- ) { const unsigned Offset = - <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , DL , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , DL ) ) ;

FrameAddr = DAG . getLoad ( VT , DL , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> EVT RootVT = Root . getValueType ( ) ; unsigned RootSizeInBits = RootVT . getSizeInBits ( ) ; unsigned Scale = WideSizeInBits / RootSizeInBits ; assert ( ( WideSizeInBits % RootSizeInBits ) == <NUM_LIT> && <STR_LIT> ) ; EVT WideSVT = WideInputs [ <NUM_LIT> ] . getValueType ( ) . getScalarType ( ) ; if ( llvm :: any_of ( WideInputs , [ & WideSVT , & DAG ] ( SDValue Op ) { return ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( Op . getValueType ( ) ) || Op . getValueType ( ) . getScalarType ( ) != WideSVT ; } ) ) return SDValue ( ) ; for ( SDValue & NewInput : WideInputs ) { assert ( ( WideSizeInBits % NewInput . getValueSizeInBits ( ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( WideSizeInBits > NewInput . getValueSizeInBits ( ) ) NewInput = widenSubVector ( NewInput , false , Subtarget , DAG , SDLoc ( NewInput ) , WideSizeInBits ) ; assert ( WideSizeInBits == NewInput . getValueSizeInBits ( ) && <STR_LIT> ) ; } for ( unsigned i = <NUM_LIT> ; i != NumInputs ; ++ i ) Offsets [ i ] += i * Scale * NumMaskElts ; SmallVector < int , <NUM_LIT> > WideMask ( BaseMask . begin ( ) , BaseMask . end ( ) ) ; for ( int & M : WideMask ) { if ( M < <NUM_LIT> ) continue ; M = ( M % NumMaskElts ) + Offsets [ M / NumMaskElts ] ; } WideMask . append ( ( Scale - <NUM_LIT> ) * NumMaskElts , SM_SentinelUndef ) ; resolveTargetShuffleInputsAndMask ( WideInputs , WideMask ) ; assert ( ! WideInputs . empty ( ) && <STR_LIT> ) ;

if ( WideInputs . size ( ) > <NUM_LIT> ) return SDValue ( ) ;


<s> bool mn10300_function_value_regno_p ( const unsigned int regno ) { return ( regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM ) ;


<s> static bool rl78_can_eliminate ( const int from ATTRIBUTE_UNUSED , const int to ATTRIBUTE_UNUSED ) { return true ;


<s> int Reg = getIntOperandFromRegisterString ( RegString -> getString ( ) ) ; if ( Reg != - <NUM_LIT> ) return CurDAG -> getMachineNode ( <STR_LIT> , DL , N -> getSimpleValueType ( <NUM_LIT> ) , <STR_LIT> , CurDAG -> getTargetConstant ( Reg , DL , <STR_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; <STR_LIT> mapper ; bool IsValidSpecialReg ;

Reg = mapper . fromString ( RegString -> getString ( ) , Subtarget -> getFeatureBits ( ) , IsValidSpecialReg ) ;


<s> return MachineJumpTableInfo :: EK_Inline ; } else { return TargetLowering :: getJumpTableEncoding ( ) ; }


<s> Value * <ISA_LIT>RegisterSema :: getSF ( <STR_LIT> SF ) {


<s> return std :: make_pair ( TF & Mask , TF & ~ Mask ) ;


<s> bool NEONPreAllocPass :: runOnMachineFunction ( MachineFunction & MF ) { TII = MF . getTarget ( ) . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; bool Modified = false ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , E = MF . end ( ) ; MFI != E ; ++ MFI ) { MachineBasicBlock & MBB = * MFI ; Modified |= PreAllocNEONRegisters ( MBB ) ; }


<s> <ISA_LIT>Operand * Op = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; <ISA_LIT>Operand * Op2 = static_cast < <ISA_LIT>Operand * > ( Operands [ <NUM_LIT> ] ) ; Operands [ <NUM_LIT> ] = <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , Op -> getStartLoc ( ) , Context ) ; Operands . push_back ( Operands [ <NUM_LIT> ] ) ; unsigned ZeroReg = <STR_LIT> ; if ( <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Operands [ <NUM_LIT> ] -> getReg ( ) ) ) ZeroReg = <STR_LIT> ;

Operands [ <NUM_LIT> ] = <ISA_LIT>Operand :: CreateReg ( ZeroReg , false , Op2 -> getStartLoc ( ) , Op2 -> getEndLoc ( ) , Context ) ;


<s> std :: vector < const Type * > ArgTys ; bool IsVarArg = false ; return FunctionType :: get ( ResultTy , ArgTys , IsVarArg ) ;


<s> VA = RVLocs [ ++ i ] ; Lo = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Lo . getValue ( <NUM_LIT> ) ; InFlag = Lo . getValue ( <NUM_LIT> ) ; VA = RVLocs [ ++ i ] ; Hi = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , <STR_LIT> , InFlag ) ; Chain = Hi . getValue ( <NUM_LIT> ) ; InFlag = Hi . getValue ( <NUM_LIT> ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo , Hi ) ; Val = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Vec , Val , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } } else { Val = DAG . getCopyFromReg ( Chain , dl , VA . getLocReg ( ) , VA . getLocVT ( ) , InFlag ) ; Chain = Val . getValue ( <NUM_LIT> ) ; InFlag = Val . getValue ( <NUM_LIT> ) ; } switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , Val ) ; break ; } InVals . push_back ( Val ) ;


<s> SDValue <ISA_LIT>TargetLowering :: getRsqrtEstimate ( SDValue Operand , DAGCombinerInfo & DCI , unsigned & ExtraSteps , bool & UseOneConst ) const { UseOneConst = true ;

return getEstimate ( * Subtarget , DCI , <STR_LIT> , Operand , ExtraSteps ) ;


<s> static DecodeStatus DecodePCRel24BranchTarget ( MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { int32_t Offset = SignExtend32 < <NUM_LIT> > ( Imm ) ; Inst . addOperand ( MCOperand :: createImm ( Offset ) ) ; return MCDisassembler :: Success ;


<s> if ( Kind >= FirstTargetFixupKind ) assert ( <STR_LIT> ) ;

return MCAsmBackend :: getFixupKindInfo ( Kind ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , SDLoc DL , SelectionDAG & DAG ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; SmallVector < CCValAssign , <NUM_LIT> > RetLocs ; CCState RetCCInfo ( CallConv , IsVarArg , MF , TM , RetLocs , * DAG . getContext ( ) ) ; RetCCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; if ( RetLocs . empty ( ) ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain ) ; SDValue Glue ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; for ( unsigned I = <NUM_LIT> , E = RetLocs . size ( ) ; I != E ; ++ I ) { CCValAssign & VA = RetLocs [ I ] ; SDValue RetValue = OutVals [ I ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; RetValue = convertValVTToLocVT ( DAG , DL , VA , RetValue ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( DCI . isBeforeLegalize ( ) ) break ; return performMemSDNodeCombine ( cast < MemSDNode > ( N ) , DCI ) ; case <STR_LIT> : return performAndCombine ( N , DCI ) ; case <STR_LIT> : return performOrCombine ( N , DCI ) ; case <STR_LIT> : return performXorCombine ( N , DCI ) ; case <STR_LIT> : return performZeroExtendCombine ( N , DCI ) ; case <STR_LIT> : return performSignExtendInRegCombine ( N , DCI ) ; case <STR_LIT> : return performClassCombine ( N , DCI ) ; case <STR_LIT> : return performFCanonicalizeCombine ( N , DCI ) ; case <STR_LIT> : return performRcpCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue Src = N -> getOperand ( <NUM_LIT> ) ; if ( Src . isUndef ( ) ) return Src ; break ; } case <STR_LIT> : case <STR_LIT> : return performUCharToFloatCombine ( N , DCI ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return performCvtF32UByteNCombine ( N , DCI ) ; case <STR_LIT> : return performFMed3Combine ( N , DCI ) ; case <STR_LIT> : return performCvtPkRTZCombine ( N , DCI ) ; case <STR_LIT> : return performClampCombine ( N , DCI ) ; case <STR_LIT> : { SelectionDAG & DAG = DCI . DAG ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; if ( VT == <STR_LIT> || VT == <STR_LIT> ) { SDLoc SL ( N ) ; SDValue Src = N -> getOperand ( <NUM_LIT> ) ; EVT EltVT = Src . getValueType ( ) ; if ( EltVT == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; SDValue Ext = DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Src ) ; return DAG . getNode ( <STR_LIT> , SL , VT , Ext ) ; } break ; } case <STR_LIT> : return performExtractVectorEltCombine ( N , DCI ) ; case <STR_LIT> : return performInsertVectorEltCombine ( N , DCI ) ; }

return <ISA_LIT>TargetLowering :: PerformDAGCombine ( N , DCI ) ;


<s> MVT MTy = LT . second ; int ISD = TLI -> InstructionOpcodeToISD ( Opcode ) ; assert ( ISD && <STR_LIT> ) ; static const CostTblEntry CostTblNoPairwise [ ] { { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , { <STR_LIT> , <STR_LIT> , <NUM_LIT> } , } ;

if ( const auto * Entry = CostTableLookup ( CostTblNoPairwise , ISD , MTy ) ) return LT . first * Entry -> Cost ;


<s> BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( MI . getOpcode ( ) ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( isEOP ( I ) ) ; break ; case <STR_LIT> : BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : { MachineInstr * NewMI = BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; TII -> addFlag ( * NewMI , <NUM_LIT> , MO_FLAG_PUSH ) ; BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; break ; } case <STR_LIT> : { MachineInstr * NewMI = BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <STR_LIT> ) . addImm ( <NUM_LIT> ) ; TII -> addFlag ( * NewMI , <NUM_LIT> , MO_FLAG_PUSH ) ; BuildMI ( * BB , I , BB -> findDebugLoc ( I ) , TII -> get ( <STR_LIT> ) ) . add ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; break ; } case <STR_LIT> : case <STR_LIT> : { bool isLastInstructionOfItsType = true ; unsigned InstExportType = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; for ( MachineBasicBlock :: iterator NextExportInst = std :: next ( I ) , EndBlock = BB -> end ( ) ; NextExportInst != EndBlock ; NextExportInst = std :: next ( NextExportInst ) ) { if ( NextExportInst -> getOpcode ( ) == <STR_LIT> || NextExportInst -> getOpcode ( ) == <STR_LIT> ) {

unsigned CurrentInstExportType = NextExportInst -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> if ( TREE_READONLY ( decl ) ) return false ; if ( ! TARGET_VOLATILE_CACHE_SET && TREE_THIS_VOLATILE ( decl ) ) return false ; attr = TYPE_ATTRIBUTES ( TREE_TYPE ( decl ) ) ; if ( lookup_attribute ( <STR_LIT> , attr ) ) return false ; attr = DECL_ATTRIBUTES ( decl ) ; if ( lookup_attribute ( <STR_LIT> , attr ) ) return false ; if ( DECL_SECTION_NAME ( decl ) != <NUM_LIT> ) {

const char * name = DECL_SECTION_NAME ( decl ) ;


<s> unsigned Sel = MI -> getOperand ( OpNo ) . getImm ( ) ; switch ( Sel ) { case <NUM_LIT> : O << 'X' ; break ; case <NUM_LIT> : O << 'Y' ; break ; case <NUM_LIT> : O << 'Z' ; break ; case <NUM_LIT> : O << 'W' ; break ; case <NUM_LIT> : O << '0' ; break ; case <NUM_LIT> : O << '1' ; break ; case <NUM_LIT> : O << '_' ; break ; default : break ;


<s> void <ISA_LIT>PassConfig :: addPreSched2 ( ) { if ( getOptLevel ( ) != CodeGenOpt :: None && get<ISA_LIT>TargetMachine ( ) . getSubtargetImpl ( ) -> hasLoadStoreOnCond ( ) ) addPass ( & IfConverterID ) ;


<s> rtx symref ; if ( alignment < <NUM_LIT> || alignment > <NUM_LIT> ) return false ; if ( ! s390_loadrelative_operand_p ( addr , & symref , & addend ) ) return false ; if ( addend & ( alignment - <NUM_LIT> ) ) return false ; if ( GET_CODE ( symref ) == SYMBOL_REF ) { switch ( alignment ) { case <NUM_LIT> : return ! SYMBOL_FLAG_NOTALIGN8_P ( symref ) ;

case <NUM_LIT> : return ! SYMBOL_FLAG_NOTALIGN4_P ( symref ) ;


<s> MachineInstr * DeallocCall = nullptr ; if ( HasTC ) { unsigned ROpc = <STR_LIT> ; DeallocCall = BuildMI ( MBB , MI , DL , HII . get ( ROpc ) ) . addExternalSymbol ( RestoreFn ) ; } else { MachineBasicBlock :: iterator It = MBB . getFirstTerminator ( ) ; assert ( It -> isReturn ( ) && std :: next ( It ) == MBB . end ( ) ) ; unsigned ROpc = <STR_LIT> ; DeallocCall = BuildMI ( MBB , It , DL , HII . get ( ROpc ) ) . addExternalSymbol ( RestoreFn ) ; DeallocCall -> copyImplicitOps ( MF , * It ) ; } addCalleeSaveRegistersAsImpOperand ( DeallocCall , MaxR , true ) ;


<s> MachineOperand & NewVAddr = Inst . getOperand ( NewVAddrIdx ) ; MRI . removeRegOperandFromUseList ( & NewVAddr ) ; MRI . moveOperands ( & NewVAddr , & SAddr , <NUM_LIT> ) ; Inst . removeOperand ( OldSAddrIdx ) ; MRI . removeRegOperandFromUseList ( & NewVAddr ) ; MRI . addRegOperandToUseList ( & NewVAddr ) ; } else { assert ( OldSAddrIdx == NewVAddrIdx ) ; if ( OldVAddrIdx >= <NUM_LIT> ) { int NewVDstIn = <STR_LIT> ( NewOpc , <STR_LIT> :: vdst_in ) ; if ( NewVDstIn != - <NUM_LIT> ) { int OldVDstIn = <STR_LIT> ( Opc , <STR_LIT> :: vdst_in ) ; Inst . untieRegOperand ( OldVDstIn ) ; } Inst . removeOperand ( OldVAddrIdx ) ; if ( NewVDstIn != - <NUM_LIT> ) { int NewVDst = <STR_LIT> ( NewOpc , <STR_LIT> :: vdst ) ; Inst . tieOperands ( NewVDst , NewVDstIn ) ;


<s> virtual const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const {

return & getInstrInfo ( ) -> getRegisterInfo ( ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & tm , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( tm , OptLevel ) , Subtarget ( nullptr ) , OptForMinSize ( false ) , IndirectTlsSegRefs ( false ) {


<s> static __inline qword si_from_double ( double d ) { union { qword q ; double d [ <NUM_LIT> ] ; } x ; x . d [ <NUM_LIT> ] = d ;


<s> EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue GotAddr = getTargetNode ( N , Ty , DAG , <STR_LIT> | Flags ) ;

return DAG . getNode ( <STR_LIT> , DL , Ty , GotAddr ) ;


<s> return ( __m256d ) __builtin_ia32_gathersiv4df ( ( __v4df ) src , base , ( __v4si ) index , ( __v4df ) mask , scale ) ;


<s> if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; if ( RC == & <STR_LIT> ) return <STR_LIT> ; llvm_unreachable ( <STR_LIT> ) ;


<s> static bool CC_<ISA_LIT>32_VarArgs ( unsigned ValNo , EVT ValVT , EVT LocVT , CCValAssign :: LocInfo LocInfo , <STR_LIT> ArgFlags , <ISA_LIT>_CCState & State , int NonVarArgsParams , int CurrentParam , bool ForceMem ) { unsigned ByValSize = <NUM_LIT> ; if ( ArgFlags . isByVal ( ) && ( ( ByValSize = ArgFlags . getByValSize ( ) ) > ( MVT ( <STR_LIT> ) . getSizeInBits ( ) / <NUM_LIT> ) ) ) { ForceMem = true ; } if ( ! ForceMem && ( ( NonVarArgsParams == - <NUM_LIT> ) || ( CurrentParam <= NonVarArgsParams ) ) ) { if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> || LocVT == <STR_LIT> ) { static const unsigned RegList1 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList1 , <NUM_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT . getSimpleVT ( ) , Reg , LocVT . getSimpleVT ( ) , LocInfo ) ) ; return false ; } }

if ( LocVT == <STR_LIT> || LocVT == <STR_LIT> ) {


<s> virtual const <ISA_LIT>Z80SelectionDAGInfo * getSelectionDAGInfo ( ) const {


<s> return ( unsigned long long ) __builtin_ia32_vcvttss2usi64 ( ( __v4sf ) __A , __R ) ;


<s> const auto * Dest1 = TII -> getNamedOperand ( * CI . Paired , <STR_LIT> :: vdst ) ; unsigned NewOffset0 = CI . Offset0 ; unsigned NewOffset1 = CI . Offset1 ; unsigned Opc = CI . UseST64 ? read2ST64Opcode ( CI . EltSize ) : read2Opcode ( CI . EltSize ) ; unsigned SubRegIdx0 = ( CI . EltSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned SubRegIdx1 = ( CI . EltSize == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; if ( NewOffset0 > NewOffset1 ) { std :: swap ( NewOffset0 , NewOffset1 ) ; std :: swap ( SubRegIdx0 , SubRegIdx1 ) ; } assert ( ( isUInt < <NUM_LIT> > ( NewOffset0 ) && isUInt < <NUM_LIT> > ( NewOffset1 ) ) && ( NewOffset0 != NewOffset1 ) && <STR_LIT> ) ; const MCInstrDesc & Read2Desc = TII -> get ( Opc ) ; const TargetRegisterClass * SuperRC = ( CI . EltSize == <NUM_LIT> ) ? & <STR_LIT> : & <STR_LIT> ; unsigned DestReg = MRI -> createVirtualRegister ( SuperRC ) ; DebugLoc DL = CI . I -> getDebugLoc ( ) ; unsigned BaseReg = AddrReg -> getReg ( ) ; unsigned BaseRegFlags = <NUM_LIT> ; if ( CI . BaseOff ) { unsigned ImmReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MBB , CI . Paired , DL , TII -> get ( <STR_LIT> ) , ImmReg ) . addImm ( CI . BaseOff ) ; BaseReg = MRI -> createVirtualRegister ( & <STR_LIT> ) ;


<s> if ( isTargetNaCl ( ) ) stackAlignment = <NUM_LIT> ; UseMovt = hasV6T2Ops ( ) && ArmUseMOVT ; if ( isTargetMachO ( ) ) { IsR9Reserved = ReserveR9 || ! HasV6Ops ; SupportsTailCall = ! isTargetIOS ( ) || ! getTargetTriple ( ) . isOSVersionLT ( <NUM_LIT> , <NUM_LIT> ) ; } else { IsR9Reserved = ReserveR9 ; SupportsTailCall = ! isThumb1Only ( ) ; } if ( Align == DefaultAlign ) { AllowsUnalignedMem = ( hasV7Ops ( ) && ( isTargetLinux ( ) || isTargetNaCl ( ) || isTargetNetBSD ( ) ) ) || ( hasV6Ops ( ) && ( isTargetMachO ( ) || isTargetNetBSD ( ) ) ) ; } else { AllowsUnalignedMem = ! ( Align == StrictAlign ) ; } if ( isV6M ( ) ) AllowsUnalignedMem = false ; switch ( IT ) { case DefaultIT : RestrictIT = hasV8Ops ( ) ; break ; case RestrictedIT : RestrictIT = true ; break ; case NoRestrictedIT : RestrictIT = false ; break ; } const FeatureBitset & Bits = getFeatureBits ( ) ;

if ( ( Bits [ <STR_LIT> ] || Bits [ <STR_LIT> ] ) && ( Options . UnsafeFPMath || isTargetDarwin ( ) ) ) UseNEONForSinglePrecisionFP = true ;


<s> } int kernel_argc = argc - kernel_arg ; char * * kernel_argv = & argv [ kernel_arg ] ; init_device ( ) ; load_image ( kernel_argv [ <NUM_LIT> ] ) ; size_t args_size = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < kernel_argc ; i ++ ) args_size += strlen ( kernel_argv [ i ] ) + <NUM_LIT> ; struct kernargs * kernargs = device_malloc ( sizeof ( * kernargs ) , kernargs_region ) ; struct argdata { int64_t argv_data [ kernel_argc ] ; char strings [ args_size ] ; } * args = device_malloc ( sizeof ( struct argdata ) , kernargs_region ) ; size_t heap_size = <NUM_LIT> * <NUM_LIT> * <NUM_LIT> ; struct heap * heap = device_malloc ( heap_size , heap_region ) ; XHSA ( hsa_fns . hsa_memory_assign_agent_fn ( heap , device , HSA_ACCESS_PERMISSION_RW ) , <STR_LIT> ) ; kernargs -> argc = kernel_argc ; kernargs -> argv = ( int64_t ) args -> argv_data ; kernargs -> out_ptr = ( int64_t ) & kernargs -> output_data ; kernargs -> output_data . return_value = <NUM_LIT> ; kernargs -> output_data . next_output = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i < ( sizeof ( kernargs -> output_data . queue ) / sizeof ( kernargs -> output_data . queue [ <NUM_LIT> ] ) ) ; i ++ ) kernargs -> output_data . queue [ i ] . written = <NUM_LIT> ; kernargs -> output_data . consumed = <NUM_LIT> ; int offset = <NUM_LIT> ; for ( int i = <NUM_LIT> ; i < kernel_argc ; i ++ ) { size_t arg_len = strlen ( kernel_argv [ i ] ) + <NUM_LIT> ; args -> argv_data [ i ] = ( int64_t ) & args -> strings [ offset ] ; memcpy ( & args -> strings [ offset ] , kernel_argv [ i ] , arg_len + <NUM_LIT> ) ; offset += arg_len ; } kernargs -> heap_ptr = ( int64_t ) heap ; hsa_fns . hsa_memory_copy_fn ( & heap -> size , & heap_size , sizeof ( heap_size ) ) ; run ( init_array_kernel , kernargs ) ; run ( main_kernel , kernargs ) ; unsigned int return_value = ( unsigned int ) kernargs -> output_data . return_value ; run ( fini_array_kernel , kernargs ) ; unsigned int upper = ( return_value & ~ <NUM_LIT> ) >> <NUM_LIT> ; if ( upper == <NUM_LIT> ) { printf ( <STR_LIT> ) ;


<s> return new <ISA_LIT>BundlingPass ( tm ) ;


<s> break ; case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_JumpTableIndex : Hash = hash_combine ( Hash , Val . Disp -> getIndex ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : Hash = hash_combine ( Hash , Val . Disp -> getSymbolName ( ) ) ; break ; case MachineOperand :: MO_GlobalAddress : Hash = hash_combine ( Hash , Val . Disp -> getGlobal ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : Hash = hash_combine ( Hash , Val . Disp -> getBlockAddress ( ) ) ; break ; case MachineOperand :: MO_MCSymbol :

Hash = hash_combine ( Hash , Val . Disp -> getMCSymbol ( ) ) ;


<s> return ( int32x4_t ) __builtin_neon_vqdmullv4hi ( __a , __b ) ;


<s> CUMULATIVE_ARGS next_cum = * get_cumulative_args ( cum ) ; ia64_function_arg_advance ( pack_cumulative_args ( & next_cum ) , mode , type , <NUM_LIT> ) ; if ( next_cum . words < MAX_ARGUMENT_SLOTS ) { int n = MAX_ARGUMENT_SLOTS - next_cum . words ; * pretend_size = n * UNITS_PER_WORD ;


<s> switch ( RegName [ <NUM_LIT> ] ) { case 'r' : case 'f' : case 'q' : case 'v' :

if ( RegName [ <NUM_LIT> ] == 's' ) return RegName + <NUM_LIT> ;


<s> void <ISA_LIT>TargetLowering :: computeMaskedBitsForTargetNode ( const SDValue Op , APInt & KnownZero , APInt & KnownOne , const SelectionDAG & DAG , unsigned Depth ) const { KnownZero = KnownOne = APInt ( KnownZero . getBitWidth ( ) , <NUM_LIT> ) ; switch ( Op . getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> :


<s> SDLoc DL ( GA ) ; const GlobalValue * GV = GA -> getGlobal ( ) ; EVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; TLSModel :: Model model = getTargetMachine ( ) . getTLSModel ( GV ) ; if ( model == TLSModel :: GeneralDynamic || model == TLSModel :: LocalDynamic ) { unsigned Flag = ( model == TLSModel :: LocalDynamic ) ? <STR_LIT> : <STR_LIT> ; SDValue TGA = DAG . getTargetGlobalAddress ( GV , DL , PtrVT , <NUM_LIT> , Flag ) ; SDValue Argument = DAG . getNode ( <STR_LIT> , DL , PtrVT , getGlobalReg ( DAG , PtrVT ) , TGA ) ; unsigned PtrSize = PtrVT . getSizeInBits ( ) ; IntegerType * PtrTy = Type :: getIntNTy ( * DAG . getContext ( ) , PtrSize ) ; SDValue TlsGetAddr = DAG . getExternalSymbol ( <STR_LIT> , PtrVT ) ; ArgListTy Args ; ArgListEntry Entry ; Entry . Node = Argument ; Entry . Ty = PtrTy ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( DL ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , PtrTy , TlsGetAddr , std :: move ( Args ) ) ;

std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ;


<s> Reserved . set ( getBaseRegister ( ) ) ; for ( MCSubRegIterator I ( getBaseRegister ( ) , this ) ; I . isValid ( ) ; ++ I ) Reserved . set ( * I ) ; } Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { static const uint16_t GPR64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; for ( MCRegAliasIterator AI ( GPR64 [ n ] , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; assert ( <STR_LIT> == <STR_LIT> + <NUM_LIT> ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } }


<s> MCAsmParser & Parser = getParser ( ) ; SMLoc SS = getLoc ( ) ; const AsmToken & TokE = Parser . getTok ( ) ; if ( TokE . isNot ( AsmToken :: Identifier ) ) return MatchOperand_NoMatch ; if ( ! TokE . getString ( ) . equals_lower ( <STR_LIT> ) || Parser . getLexer ( ) . peekTok ( ) . isNot ( AsmToken :: Hash ) ) return MatchOperand_NoMatch ; Operands . push_back ( <ISA_LIT>Operand :: CreateToken ( <STR_LIT> , false , SS , getContext ( ) ) ) ; Parser . Lex ( ) ; Parser . Lex ( ) ; const MCExpr * ImmVal ; SS = getLoc ( ) ; if ( Parser . parseExpression ( ImmVal ) ) return MatchOperand_ParseFail ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( ImmVal ) ; if ( ! MCE ) return MatchOperand_ParseFail ; int Val = MCE -> getValue ( ) ;

Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( MCConstantExpr :: create ( Val , getContext ( ) ) , SS , getLoc ( ) , getContext ( ) ) ) ;


<s> MI = BuildMI ( MBB , Before , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , SaveOrig ) . addImm ( - <NUM_LIT> ) ; LIS -> InsertMachineInstrInMaps ( * MI ) ;


<s> if ( CALL_P ( insn ) ) return <STR_LIT> ;

if ( reg_mentioned_p ( gen_rtx_REG ( SImode , LR_REGNUM ) , insn ) ) return <STR_LIT> ;


<s> case <NUM_LIT> : return riscv_pass_fpr_single ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; case <NUM_LIT> : return riscv_pass_fpr_pair ( mode , fregno , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset , fregno + <NUM_LIT> , TYPE_MODE ( fields [ <NUM_LIT> ] . type ) , fields [ <NUM_LIT> ] . offset ) ; default : gcc_unreachable ( ) ; } if ( ( info -> num_fprs = riscv_pass_mode_in_fpr_p ( mode ) ) && info -> fpr_offset + info -> num_fprs <= MAX_ARGS_IN_REGISTERS ) switch ( GET_MODE_CLASS ( mode ) ) { case MODE_FLOAT : return gen_rtx_REG ( mode , fregno ) ; case MODE_COMPLEX_FLOAT :

return riscv_pass_fpr_pair ( mode , fregno , GET_MODE_INNER ( mode ) , <NUM_LIT> , fregno + <NUM_LIT> , GET_MODE_INNER ( mode ) , GET_MODE_UNIT_SIZE ( mode ) ) ;


<s> bool <ISA_LIT>IndexMap :: runOnFunction ( Function & F ) { p_func = & F ; p_SE = & getAnalysis < ScalarEvolutionWrapperPass > ( ) . getSE ( ) ; p_LI = & getAnalysis < LoopInfoWrapperPass > ( ) . getLoopInfo ( ) ; collectDataLoop ( F , p_SE , p_LI ) ; sort ( ) ;


<s> SDValue RHS1 = Extract128BitVector ( RHS , <NUM_LIT> , DAG , dl ) ; SDValue RHS2 = Extract128BitVector ( RHS , NumElems / <NUM_LIT> , DAG , dl ) ; MVT EltVT = VT . getVectorElementType ( ) ; MVT NewVT = <STR_LIT> ( EltVT , NumElems / <NUM_LIT> ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS1 , RHS1 , CC ) , DAG . getNode ( Op . getOpcode ( ) , dl , NewVT , LHS2 , RHS2 , CC ) ) ;


<s> unsigned BaseReg ( <STR_LIT> . getRegister ( BaseIdx ) ) ; return getMatchingSuperReg ( BaseReg , <STR_LIT> , & <STR_LIT> ) ;


<s> if ( VReg == <NUM_LIT> ) return <NUM_LIT> ;

return signExtend ( VReg , V , From , To ) ;


<s> bool <ISA_LIT>TTIImpl :: isLegalToInferAttributeForFunction ( Function * F ) const { if ( F -> isDeclaration ( ) && ! F -> hasFnAttribute ( ( Attribute :: OptimizeNone ) ) && F -> getName ( ) == <STR_LIT> ) return true ;


<s> bool isGFX8_GFX9_GFX10 ( const MCSubtargetInfo & STI ) {

return isVI ( STI ) || isGFX9 ( STI ) || isGFX10 ( STI ) ;


<s> BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( SrcReg2 ) ; } MII = MBB -> erase ( MI ) ; -- MII ; } else if ( Opc == <STR_LIT> ) { int DestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int SrcReg1 = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; int Immed1 = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; int Immed2 = MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg1 ) . addImm ( Immed1 ) ; BuildMI ( * MBB , MII , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg1 ) . addImm ( Immed2 ) ; MII = MBB -> erase ( MI ) ; -- MII ; }


<s> uint64_t RequiredAlign = std :: max ( AlignVal , StackAlign ) ; uint64_t ExtraAlignSpace = RequiredAlign - StackAlign ; Register SPReg = getStackPointerRegisterToSaveRestore ( ) ; SDValue NeededSpace = Size ; SDValue OldSP = DAG . getCopyFromReg ( Chain , DL , SPReg , <STR_LIT> ) ; SDValue Backchain ; if ( StoreBackchain ) Backchain = DAG . getLoad ( <STR_LIT> , DL , Chain , getBackchainAddress ( OldSP , DAG ) , MachinePointerInfo ( ) ) ; if ( ExtraAlignSpace ) NeededSpace = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NeededSpace , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ; SDValue NewSP ; if ( hasInlineStackProbe ( MF ) ) { NewSP = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Chain , OldSP , NeededSpace ) ; Chain = NewSP . getValue ( <NUM_LIT> ) ; } else { NewSP = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OldSP , NeededSpace ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , NewSP ) ; } SDValue ArgAdjust = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> ) ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSP , ArgAdjust ) ; if ( RequiredAlign > StackAlign ) {

Result = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Result , DAG . getConstant ( ExtraAlignSpace , DL , <STR_LIT> ) ) ;


<s> if ( ABI . IsO32 ( ) ) PrivateGlobalPrefix = <STR_LIT> ; else if ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = PrivateGlobalPrefix ; AlignmentIsInBytes = false ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; GPRel32Directive = <STR_LIT> ; GPRel64Directive = <STR_LIT> ; DTPRel32Directive = <STR_LIT> ; DTPRel64Directive = <STR_LIT> ; TPRel32Directive = <STR_LIT> ; TPRel64Directive = <STR_LIT> ; UseAssignmentForEHBegin = true ;


<s> const char * <ISA_LIT>Relocator :: getName ( Relocation :: Type pType ) const {

return ApplyFunctions [ pType ] . name ;


<s> a = ( __vector signed short ) vec_splats ( __m1 ) ; b = ( __vector signed short ) vec_splats ( __m2 ) ; c = vec_add ( a , b ) ; return ( __builtin_unpack_vector_int128 ( ( __vector __int128_t ) c , <NUM_LIT> ) ) ; __m64_union m1 , m2 , res ;


<s> if ( lang_hooks . types_compatible_p ( lang_hooks . types . type_promotes_to ( in_type ) , lang_hooks . types . type_promotes_to ( b_arg_type ) ) ) { match_type ++ ; continue ; } if ( TREE_CODE ( b_arg_type ) == INTEGER_TYPE && TREE_CODE ( in_type ) == INTEGER_TYPE ) { match_type ++ ; continue ; } if ( POINTER_TYPE_P ( b_arg_type ) && POINTER_TYPE_P ( in_type ) && ! ( TYPE_QUALS ( TREE_TYPE ( in_type ) ) & ~ TYPE_QUALS ( TREE_TYPE ( b_arg_type ) ) ) && ( TYPE_QUALS ( TREE_TYPE ( b_arg_type ) ) & ~ TYPE_QUALS ( TREE_TYPE ( in_type ) ) ) ) { tree qual_in_type = build_qualified_type ( TREE_TYPE ( in_type ) , TYPE_QUALS ( TREE_TYPE ( b_arg_type ) ) ) ; if ( lang_hooks . types_compatible_p ( qual_in_type , TREE_TYPE ( b_arg_type ) ) ) { match_type ++ ; continue ; } } mismatch : if ( TARGET_DEBUG_ARG ) { fprintf ( stderr , <STR_LIT> , i + <NUM_LIT> ) ; print_generic_expr ( stderr , in_type , TDF_VOPS | TDF_MEMSYMS ) ; fprintf ( stderr , <STR_LIT> ) ; print_generic_expr ( stderr , b_arg_type , TDF_VOPS | TDF_MEMSYMS ) ; fprintf ( stderr , <STR_LIT> ) ;


<s> unsigned getSmallDataThreshold ( ) const { return <ISA_LIT>_SMALL_DATA_THRESHOLD ;


<s> } SDValue FrameAddr = getFRAMEADDR ( depth - <NUM_LIT> , Op , DAG , Subtarget ) ; unsigned Offset = ( Subtarget -> is64Bit ( ) ) ? <NUM_LIT> : <NUM_LIT> ; SDValue Ptr = DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , DAG . getIntPtrConstant ( Offset , dl ) ) ; RetAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , Ptr , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;


<s> __v2df result = ( __v2df ) __A ; double db = __B ;


<s> const <ISA_LIT>TargetObjectFile * TLOF = static_cast < const <ISA_LIT>TargetObjectFile * > ( getTargetMachine ( ) . getObjFileLowering ( ) ) ; const GlobalObject * GO = GV -> getBaseObject ( ) ; if ( GO && TLOF -> IsGlobalInSmallSection ( GO , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ; return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ; } if ( GV -> hasLocalLinkage ( ) ) return getAddrLocal ( N , SDLoc ( N ) , Ty , DAG , ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ; if ( LargeGOT ) return getAddrGlobalLargeGOT ( N , SDLoc ( N ) , Ty , DAG , <STR_LIT> , <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ; return getAddrGlobal ( N , SDLoc ( N ) , Ty , DAG , ( ABI . IsN32 ( ) || ABI . IsN64 ( ) ) ? <STR_LIT> : <STR_LIT> , DAG . getEntryNode ( ) , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; bool ValidName ; std :: string Name = Mapper . toString ( MO . getImm ( ) , ValidName ) ; if ( ValidName ) {


<s> ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; ShufIdxs [ <NUM_LIT> ] = <NUM_LIT> ; break ; case OP_VSPLTISW0 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSPLTISW1 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSPLTISW2 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSPLTISW3 : for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) ShufIdxs [ i ] = ( i & <NUM_LIT> ) + <NUM_LIT> ; break ; case OP_VSLDOI4 : return BuildVSLDOI ( OpLHS , OpRHS , <NUM_LIT> , OpLHS . getValueType ( ) , DAG , dl ) ; case OP_VSLDOI8 : return BuildVSLDOI ( OpLHS , OpRHS , <NUM_LIT> , OpLHS . getValueType ( ) , DAG , dl ) ; case OP_VSLDOI12 :


<s> return Kind == k_VectorListAllLanes && ! VectorList . isDoubleSpaced ;


<s> <ISA_LIT>AsmBackend ( const Target & T , const StringRef TT ) : MCAsmBackend ( ) {


<s> unsigned OrOpCodes [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; unsigned OrOpCode = OrOpCodes [ Log2_32 ( Bytes ) ] ; auto OrI = BuildMI ( MBB , InsertPt , Loc , TII -> get ( OrOpCode ) , NewReg ) . addReg ( StateReg ) . addReg ( Reg ) ; OrI -> addRegisterDead ( <STR_LIT> , TRI ) ; ++ NumInstsInserted ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; OrI -> dump ( ) ; dbgs ( ) << <STR_LIT> ) ; if ( FlagsReg ) restoreEFLAGS ( MBB , InsertPt , Loc , FlagsReg ) ;


<s> if ( MI . isDebugInstr ( ) ) return false ; if ( MI . isCall ( ) ) { if ( doesNotReturn ( MI ) ) return true ;

for ( auto I : MBB -> successors ( ) ) if ( I -> isEHPad ( ) ) return true ;


<s> unsigned getCFInstrCost ( unsigned Opcode , TTI :: TargetCostKind CostKind ) {


<s> O << <STR_LIT> ; break ; case ADDRESS_SPACE_SHARED : O << <STR_LIT> ; break ; default : report_fatal_error ( <STR_LIT> + llvm :: Twine ( AddressSpace ) ) ;


<s> static bool ia64_modes_tieable_p ( machine_mode mode1 , machine_mode mode2 ) { return ( GET_MODE_CLASS ( mode1 ) == GET_MODE_CLASS ( mode2 ) && ( ( mode1 == XFmode || mode1 == XCmode || mode1 == RFmode ) == ( mode2 == XFmode || mode2 == XCmode || mode2 == RFmode ) ) && ( mode1 == BImode ) == ( mode2 == BImode ) ) ;


<s> auto ScratchRSrcReg = MIRBuilder . buildCopy ( LLT :: vector ( <NUM_LIT> , <NUM_LIT> ) , FuncInfo . getScratchRSrcReg ( ) ) ; MIRBuilder . buildCopy ( <STR_LIT> , ScratchRSrcReg ) ; CallInst . addReg ( <STR_LIT> , RegState :: Implicit ) ; } for ( std :: pair < MCRegister , Register > ArgReg : ImplicitArgRegs ) { MIRBuilder . buildCopy ( ( Register ) ArgReg . first , ArgReg . second ) ; CallInst . addReg ( ArgReg . first , RegState :: Implicit ) ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: systemz , true > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned Index , StringRef Str , RegKind RegKind , const MCRegisterInfo * RegInfo , SMLoc S , SMLoc E , <ISA_LIT>AsmParser & Parser , unsigned RealRegister = <STR_LIT> ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( k_RegisterIndex , Parser ) ;


<s> if ( getTargetMachine ( ) . shouldAssumeDSOLocal ( * GV -> getParent ( ) , GV ) ) { MachineFunction & MF = DAG . getMachineFunction ( ) ; MVT PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; const char * BaseName ; if ( GV -> getValueType ( ) -> isFunctionTy ( ) ) { BaseName = MF . createExternalSymbolName ( <STR_LIT> ) ; OperandFlags = <STR_LIT> ; } else { BaseName = MF . createExternalSymbolName ( <STR_LIT> ) ; OperandFlags = <STR_LIT> ; }

SDValue BaseAddr = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getTargetExternalSymbol ( BaseName , PtrVT ) ) ;


<s> return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'l' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'e' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'q' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 't' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; case 'w' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'x' : case 'X' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; case 'y' : case 'Y' : return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; case 'z' :


<s> if ( Op == <STR_LIT> || Op == <STR_LIT> || Op == <STR_LIT> ) { return true ; } if ( Op == <STR_LIT> || Op == <STR_LIT> ) { for ( unsigned i = <NUM_LIT> ; i < N . getNumOperands ( ) ; ++ i ) {

if ( isAddressBase ( N . getOperand ( i ) ) ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> int Color = getFunctionColor ( F ) ; if ( Color >= <NUM_LIT> ) Section -> setColor ( Color ) ; }


<s> CommentString = <STR_LIT> ; Code16Directive = <STR_LIT> ; Code32Directive = <STR_LIT> ; SupportsDebugInformation = true ; switch ( TheTriple . getOS ( ) ) { case Triple :: Bitrig : case Triple :: NetBSD : case Triple :: NaCl : ExceptionsType = ExceptionHandling :: DwarfCFI ; break ; default :

ExceptionsType = ExceptionHandling :: <ISA_LIT> ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ;


<s> MachineBasicBlock :: iterator I = MI , BeforeI = I ; bool AtStart = I == MBB . begin ( ) ; if ( ! AtStart ) -- BeforeI ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; ++ i ) { unsigned Reg = CSI [ i ] . getReg ( ) ; if ( Reg == <STR_LIT> ) continue ; if ( ( Reg == <STR_LIT> || Reg == <STR_LIT> ) && MustSaveTOC ) continue ; if ( Reg == <STR_LIT> ) { CR2Spilled = true ; CSIIndex = i ; continue ; } else if ( Reg == <STR_LIT> ) { CR3Spilled = true ; continue ; } else if ( Reg == <STR_LIT> ) { CR4Spilled = true ; continue ; } else { if ( ( CR2Spilled || CR3Spilled || CR4Spilled ) && ! ( <STR_LIT> <= Reg && Reg <= <STR_LIT> ) ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; CR2Spilled = CR3Spilled = CR4Spilled = false ; } if ( CSI [ i ] . isSpilledToReg ( ) ) { DebugLoc DL ; NumPEReloadVSR ++ ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( CSI [ i ] . getDstReg ( ) , getKillRegState ( true ) ) ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , I , Reg , CSI [ i ] . getFrameIdx ( ) , RC , TRI ) ; assert ( I != MBB . begin ( ) && <STR_LIT> ) ; } } if ( AtStart ) I = MBB . begin ( ) ; else { I = BeforeI ; ++ I ; } } if ( CR2Spilled || CR3Spilled || CR4Spilled ) { bool is31 = needsFP ( * MF ) ; restoreCRs ( Subtarget . is<ISA_LIT>64 ( ) , is31 , CR2Spilled , CR3Spilled , CR4Spilled , MBB , I , CSI , CSIIndex ) ; }


<s> if ( i != PR_REG && ( i != FPSCR_REG || ! skip_fpscr ) && TEST_HARD_REG_BIT ( * mask , i ) ) push ( i ) ; } if ( TEST_HARD_REG_BIT ( * mask , PR_REG ) ) push ( PR_REG ) ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : Value = <NUM_LIT> ; return true ; case <STR_LIT> : Value = <NUM_LIT> ; return true ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) != Reg ) return false ; Value = <NUM_LIT> ;


<s> return ( int32x4_t ) __builtin_neon_vreinterpretv4siv2di ( ( int64x2_t ) __a ) ;


if ( GET_CODE ( op ) == SYMBOL_REF ) return SYMBOL_REF_MODEL ( op ) != M32R_MODEL_LARGE ;


<s> unsigned CmpOpcode = EFLAGS . getOpcode ( ) ; if ( CmpOpcode != <STR_LIT> && CmpOpcode != <STR_LIT> ) return SDValue ( ) ; auto * CmpConstant = dyn_cast < ConstantSDNode > ( EFLAGS . getOperand ( <NUM_LIT> ) ) ; if ( ! CmpConstant ) return SDValue ( ) ; const APInt & CmpVal = CmpConstant -> getAPIntValue ( ) ; SDValue CmpOp = EFLAGS . getOperand ( <NUM_LIT> ) ; unsigned CmpBits = CmpOp . getValueSizeInBits ( ) ; assert ( CmpBits == CmpVal . getBitWidth ( ) && <STR_LIT> ) ; if ( CmpOp . getOpcode ( ) == <STR_LIT> ) CmpOp = CmpOp . getOperand ( <NUM_LIT> ) ; if ( CmpOp . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue Vec = CmpOp . getOperand ( <NUM_LIT> ) ; MVT VecVT = Vec . getSimpleValueType ( ) ; assert ( ( VecVT . is128BitVector ( ) || VecVT . is256BitVector ( ) ) && <STR_LIT> ) ; unsigned NumElts = VecVT . getVectorNumElements ( ) ; unsigned NumEltBits = VecVT . getScalarSizeInBits ( ) ; bool IsAnyOf = CmpOpcode == <STR_LIT> && CmpVal . isNullValue ( ) ; bool IsAllOf = CmpOpcode == <STR_LIT> && NumElts <= CmpBits && CmpVal . isMask ( NumElts ) ; if ( ! IsAnyOf && ! IsAllOf ) return SDValue ( ) ; if ( Vec . getOpcode ( ) == <STR_LIT> ) { SDValue BC = peekThroughBitcasts ( Vec ) ; MVT BCVT = BC . getSimpleValueType ( ) ; unsigned BCNumElts = BCVT . getVectorNumElements ( ) ; unsigned BCNumEltBits = BCVT . getScalarSizeInBits ( ) ; if ( ( BCNumEltBits == <NUM_LIT> || BCNumEltBits == <NUM_LIT> ) && BCNumEltBits > NumEltBits && DAG . ComputeNumSignBits ( BC ) > ( BCNumEltBits - NumEltBits ) ) { SDLoc DL ( EFLAGS ) ; unsigned CmpMask = IsAnyOf ? <NUM_LIT> : ( ( <NUM_LIT> << BCNumElts ) - <NUM_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BC ) , DAG . getConstant ( CmpMask , DL , <STR_LIT> ) ) ;


<s> CUMULATIVE_ARGS * pcum = get_cumulative_args ( pcum_v ) ; gcc_assert ( pcum -> pcs_variant == ARM_PCS_AAPCS64 ) ; if ( mode == VOIDmode ) return NULL_RTX ;

aarch64_layout_arg ( pcum_v , mode , type , named ) ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) { return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> sri -> icode = CODE_FOR_nothing ; sri -> t_icode = CODE_FOR_nothing ; sri -> extra_cost = <NUM_LIT> ; icode = ( ( in_p ) ? reg_addr [ mode ] . reload_load : reg_addr [ mode ] . reload_store ) ; if ( REG_P ( x ) || register_operand ( x , mode ) ) { enum rs6000_reg_type to_type = reg_class_to_reg_type [ ( int ) rclass ] ; bool altivec_p = ( rclass == ALTIVEC_REGS ) ; enum rs6000_reg_type from_type = register_to_reg_type ( x , & altivec_p ) ; if ( ! in_p ) std :: swap ( to_type , from_type ) ; if ( rs6000_secondary_reload_move ( to_type , from_type , mode , sri , altivec_p ) ) { icode = ( enum insn_code ) sri -> icode ; default_p = false ; done_p = true ; ret = NO_REGS ; } } if ( x == CONST0_RTX ( mode ) && VSX_REG_CLASS_P ( rclass ) ) { ret = NO_REGS ; default_p = false ; done_p = true ; } if ( ! done_p && reg_addr [ mode ] . scalar_in_vmx_p && ! mode_supports_vmx_dform ( mode ) && ( rclass == VSX_REGS || rclass == ALTIVEC_REGS ) && ( memory_p || ( GET_CODE ( x ) == CONST_DOUBLE ) ) ) { ret = FLOAT_REGS ; default_p = false ; done_p = true ; } if ( ! done_p && icode != CODE_FOR_nothing && memory_p ) { int extra_cost = rs6000_secondary_reload_memory ( XEXP ( x , <NUM_LIT> ) , rclass , mode ) ; if ( extra_cost >= <NUM_LIT> ) { done_p = true ; ret = NO_REGS ; if ( extra_cost > <NUM_LIT> ) { sri -> extra_cost = extra_cost ; sri -> icode = icode ; } } } if ( ! done_p && TARGET_POWERPC64 && reg_class_to_reg_type [ ( int ) rclass ] == GPR_REG_TYPE && memory_p && GET_MODE_SIZE ( GET_MODE ( x ) ) >= UNITS_PER_WORD ) { rtx addr = XEXP ( x , <NUM_LIT> ) ; rtx off = address_offset ( addr ) ; if ( off != NULL_RTX ) { unsigned int extra = GET_MODE_SIZE ( GET_MODE ( x ) ) - UNITS_PER_WORD ; unsigned HOST_WIDE_INT offset = INTVAL ( off ) ;

if ( GET_CODE ( addr ) == LO_SUM ? ( <NUM_LIT> && ( ( offset & <NUM_LIT> ) != <NUM_LIT> || ( ( offset & <NUM_LIT> ) ^ <NUM_LIT> ) >= <NUM_LIT> - extra ) ) : ( offset + <NUM_LIT> < <NUM_LIT> - extra && ( offset & <NUM_LIT> ) != <NUM_LIT> ) ) {


<s> return CalleeSaveStackHasFreeSpace ;


<s> assert ( PersonalityIndex == <STR_LIT> :: AEABI_UNWIND_CPP_PR0 && <STR_LIT> ) ; assert ( Opcodes . size ( ) == <NUM_LIT> && <STR_LIT> ) ; uint64_t Intval = Opcodes [ <NUM_LIT> ] | Opcodes [ <NUM_LIT> ] << <NUM_LIT> | Opcodes [ <NUM_LIT> ] << <NUM_LIT> | Opcodes [ <NUM_LIT> ] << <NUM_LIT> ; emitIntValue ( Intval , Opcodes . size ( ) ) ;


<s> virtual const <ISA_LIT>TargetLowering * getTargetLowering ( ) const {


<s> SDValue <ISA_LIT>TargetLowering :: LowerRETURNADDR ( SDValue Op , SelectionDAG & DAG ) const { auto MFI = DAG . getMachineFunction ( ) . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = Op . getConstantOperandVal ( <NUM_LIT> ) ; if ( Depth ) { report_fatal_error ( <STR_LIT> + DAG . getMachineFunction ( ) . getName ( ) ) ;


<s> SMLoc S = getLexer ( ) . getTok ( ) . getLoc ( ) ; if ( ! ParseImmediate ( Operands ) || ! ParseSymbolReference ( Operands ) ) { return false ; } return Error ( S , <STR_LIT> ) ;


<s> case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ; case <NUM_LIT> : return <STR_LIT> ;

default : llvm_unreachable ( <STR_LIT> ) ;


<s> if ( REG_P ( op ) ) regnum = REGNO ( op ) ;

else if ( GET_CODE ( op ) == PLUS && REG_P ( XEXP ( op , <NUM_LIT> ) ) && CONST_INT_P ( XEXP ( op , <NUM_LIT> ) ) ) regnum = REGNO ( XEXP ( op , <NUM_LIT> ) ) ;


<s> NVVMIntrRangePass :: NVVMIntrRangePass ( ) : NVVMIntrRangePass ( NVVMIntrRangeSM ) {


<s> static void emitByte ( uint8_t C , raw_ostream & OS ) {


<s> unsigned int base_length ; switch ( mode ) { case QImode : if ( addr == NULL_RTX ) return <NUM_LIT> ; if ( h8300_eightbit_constant_address_p ( addr ) ) return <NUM_LIT> ; base_length = <NUM_LIT> ; break ; case HImode : if ( addr == NULL_RTX ) { if ( REG_P ( src ) ) return <NUM_LIT> ; if ( src == const0_rtx ) return <NUM_LIT> ; return <NUM_LIT> ; } base_length = <NUM_LIT> ; break ; case SImode : if ( addr == NULL_RTX ) { if ( REG_P ( src ) ) return <NUM_LIT> ; if ( GET_CODE ( src ) == CONST_INT ) { if ( src == const0_rtx ) return <NUM_LIT> ; if ( ( INTVAL ( src ) & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ( INTVAL ( src ) & <NUM_LIT> ) == <NUM_LIT> ) return <NUM_LIT> ; if ( ( INTVAL ( src ) & <NUM_LIT> ) == ( ( INTVAL ( src ) >> <NUM_LIT> ) & <NUM_LIT> ) ) return <NUM_LIT> ; } return <NUM_LIT> ; } base_length = <NUM_LIT> ; break ; case SFmode : if ( addr == NULL_RTX ) { if ( REG_P ( src ) ) return <NUM_LIT> ; if ( satisfies_constraint_G ( src ) ) return <NUM_LIT> ; return <NUM_LIT> ; } base_length = <NUM_LIT> ; break ; default : gcc_unreachable ( ) ; } if ( GET_CODE ( addr ) == PRE_DEC || GET_CODE ( addr ) == POST_INC ) { if ( mode == QImode || mode == HImode ) return base_length - <NUM_LIT> ; else return base_length - <NUM_LIT> ; } if ( GET_CODE ( addr ) == REG ) return base_length - <NUM_LIT> ; return base_length ; } else { unsigned int base_length ; switch ( mode ) { case QImode : if ( addr == NULL_RTX ) return <NUM_LIT> ; if ( h8300_eightbit_constant_address_p ( addr ) ) return <NUM_LIT> ; base_length = <NUM_LIT> ; break ; case HImode : if ( addr == NULL_RTX ) { if ( REG_P ( src ) ) return <NUM_LIT> ; if ( src == const0_rtx ) return <NUM_LIT> ; return <NUM_LIT> ; } base_length = <NUM_LIT> ; break ; case SImode : if ( addr == NULL_RTX ) { if ( REG_P ( src ) ) { if ( REGNO ( src ) == MAC_REG || REGNO ( dest ) == MAC_REG ) return <NUM_LIT> ; else return <NUM_LIT> ;


<s> for ( size_t i = <NUM_LIT> ; i < LastSig . Returns . size ( ) ; i ++ ) { auto EVT = LastSig . Returns [ i ] ; auto PVT = Stack [ Stack . size ( ) - LastSig . Returns . size ( ) + i ] ; if ( PVT != EVT ) return typeError ( ErrorLoc , StringRef ( <STR_LIT> ) + <STR_LIT> ( PVT ) + <STR_LIT> + <STR_LIT> ( EVT ) ) ;


<s> EVT VT = Op . getValueType ( ) ; SDValue Tmp1 = Op ; SDValue Tmp2 = Op . getValue ( <NUM_LIT> ) ; SDValue Tmp3 = Op . getOperand ( <NUM_LIT> ) ; SDValue Chain = Tmp1 . getOperand ( <NUM_LIT> ) ; Register SPReg = Info -> getStackPtrOffsetReg ( ) ; Chain = DAG . getCALLSEQ_START ( Chain , <NUM_LIT> , <NUM_LIT> , dl ) ; SDValue Size = Tmp2 . getOperand ( <NUM_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , dl , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; MaybeAlign Alignment = cast < ConstantSDNode > ( Tmp3 ) -> getMaybeAlignValue ( ) ; const GCNSubtarget & ST = MF . getSubtarget < GCNSubtarget > ( ) ; const TargetFrameLowering * TFL = ST . getFrameLowering ( ) ; unsigned Opc = TFL -> getStackGrowthDirection ( ) == TargetFrameLowering :: StackGrowsUp ? <STR_LIT> : <STR_LIT> ; SDValue ScaledSize = DAG . getNode ( <STR_LIT> , dl , VT , Size , DAG . getConstant ( ST . getWavefrontSizeLog2 ( ) , dl , <STR_LIT> ) ) ; Align StackAlign = TFL -> getStackAlign ( ) ; Tmp1 = DAG . getNode ( Opc , dl , VT , SP , ScaledSize ) ; if ( Alignment && * Alignment > StackAlign ) { Tmp1 = DAG . getNode ( <STR_LIT> , dl , VT , Tmp1 , DAG . getConstant ( - ( uint64_t ) Alignment -> value ( ) << ST . getWavefrontSizeLog2 ( ) , dl , VT ) ) ; } Chain = DAG . getCopyToReg ( Chain , dl , SPReg , Tmp1 ) ;

Tmp2 = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , dl , true ) , SDValue ( ) , dl ) ;


<s> void <ISA_LIT>DAGToDAGISel :: transferMemOperands ( SDNode * N , SDNode * Result ) { MachineSDNode :: mmo_iterator MemOp = MF -> allocateMemRefsArray ( <NUM_LIT> ) ; MemOp [ <NUM_LIT> ] = cast < MemSDNode > ( N ) -> getMemOperand ( ) ; cast < MachineSDNode > ( Result ) -> setMemRefs ( MemOp , MemOp + <NUM_LIT> ) ;


<s> unsigned Reg = TRI -> getEncodingValue ( Op . getReg ( ) ) ; if ( TRI -> isVGPR ( MRIA , Op . getReg ( ) ) ) { assert ( Reg >= RegisterEncoding . VGPR0 && Reg <= RegisterEncoding . VGPRL ) ; Result . first = Reg - RegisterEncoding . VGPR0 ; assert ( Result . first >= <NUM_LIT> && Result . first < SQ_MAX_PGM_VGPRS ) ; } else if ( TRI -> isSGPRReg ( MRIA , Op . getReg ( ) ) ) { assert ( Reg >= RegisterEncoding . SGPR0 && Reg < SQ_MAX_PGM_SGPRS ) ; Result . first = Reg - RegisterEncoding . SGPR0 + NUM_ALL_VGPRS ; assert ( Result . first >= NUM_ALL_VGPRS && Result . first < SQ_MAX_PGM_SGPRS + NUM_ALL_VGPRS ) ; } else return { - <NUM_LIT> , - <NUM_LIT> } ; const MachineInstr & MIA = * MI ; const TargetRegisterClass * RC = TII -> getOpRegClass ( MIA , OpNo ) ;


<s> return inPicMode ( ) && ! ( isABI_N32 ( ) || isABI_N64 ( ) ) ;


<s> int size = bitsize / BITS_PER_UNIT ; rtx src_mem = adjust_address ( force_const_mem ( word_mode , src ) , BLKmode , GET_MODE_SIZE ( word_mode ) - size ) ; dest = adjust_address ( dest , BLKmode , <NUM_LIT> ) ; set_mem_size ( dest , GEN_INT ( size ) ) ; s390_expand_movmem ( dest , src_mem , GEN_INT ( size ) ) ; } else if ( register_operand ( src , word_mode ) ) { if ( bitsize <= GET_MODE_BITSIZE ( SImode ) ) emit_move_insn ( gen_rtx_ZERO_EXTRACT ( word_mode , dest , op1 , const0_rtx ) , src ) ; else { int stcmh_width = bitsize - GET_MODE_BITSIZE ( SImode ) ; int size = stcmh_width / BITS_PER_UNIT ; emit_move_insn ( adjust_address ( dest , SImode , size ) , gen_lowpart ( SImode , src ) ) ; set_mem_size ( dest , GEN_INT ( size ) ) ; emit_move_insn ( gen_rtx_ZERO_EXTRACT ( word_mode , dest , GEN_INT ( stcmh_width ) , const0_rtx ) , gen_rtx_LSHIFTRT ( word_mode , src , GEN_INT ( GET_MODE_BITSIZE ( SImode ) ) ) ) ; } } else return false ; return true ; } if ( TARGET_ZARCH && register_operand ( dest , word_mode ) && ( bitpos % <NUM_LIT> ) == <NUM_LIT> && ( bitsize % <NUM_LIT> ) == <NUM_LIT> && const_int_operand ( src , VOIDmode ) ) { HOST_WIDE_INT val = INTVAL ( src ) ; int regpos = bitpos + bitsize ; while ( regpos > bitpos ) { enum machine_mode putmode ; int putsize ; if ( TARGET_EXTIMM && ( regpos % <NUM_LIT> == <NUM_LIT> ) && ( regpos >= bitpos + <NUM_LIT> ) ) putmode = SImode ; else putmode = HImode ;

putsize = GET_MODE_BITSIZE ( putmode ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RelocID = <STR_LIT> ; break ; case <STR_LIT> : RelocID = <STR_LIT> ; break ; } MCE . addRelocation ( GetRelocation ( MO , RelocID ) ) ; return <NUM_LIT> ;


<s> switch ( Inst . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ;


<s> rtx label = operands [ <NUM_LIT> ] ; emit_insn ( gen_rtx_SET ( gen_rtx_REG ( CCFPmode , <NUM_LIT> ) , gen_rtx_fmt_ee ( code , CCFPmode , operand0 , operand1 ) ) ) ;

emit_jump_insn ( gen_rtx_SET ( pc_rtx , gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_fmt_ee ( NE , VOIDmode , gen_rtx_REG ( CCFPmode , <NUM_LIT> ) , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , label ) , pc_rtx ) ) ) ;


<s> return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; } case <STR_LIT> : return MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; }


<s> static inline unsigned slice ( uint32_t Bits , unsigned From , unsigned To ) { assert ( From < <NUM_LIT> && To < <NUM_LIT> && From >= To ) ; return ( Bits >> To ) & ( ( <NUM_LIT> << ( From - To + <NUM_LIT> ) ) - <NUM_LIT> ) ;


<s> case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; case <NUM_LIT> : AddrReg = <STR_LIT> . getRegister ( Address ) ; break ; } MachineInstr * MOVA = buildDefaultInstruction ( * MBB , I , <STR_LIT> , <STR_LIT> , OffsetReg ) ; setImmOperand ( * MOVA , <STR_LIT> :: write , <NUM_LIT> ) ; MachineInstrBuilder Mov = buildDefaultInstruction ( * MBB , I , <STR_LIT> , AddrReg , ValueReg ) . addReg ( <STR_LIT> , RegState :: Implicit | RegState :: Kill ) ; setImmOperand ( * Mov , <STR_LIT> :: dst_rel , <NUM_LIT> ) ;


<s> if ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> ) { SDValue MulOp0 = N -> getOperand ( <NUM_LIT> ) ; SDValue MulOp1 = N -> getOperand ( <NUM_LIT> ) ; SDValue OP0 ; SDValue OP1 ; if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext0 = MulOp0 . getOperand ( <NUM_LIT> ) ; if ( Sext0 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } OP0 = Sext0 ; } else if ( MulOp0 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp0 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDValue Chain = LD -> getChain ( ) ; SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; OP0 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LD -> getBasePtr ( ) , TargetConst0 , Chain ) , <NUM_LIT> ) ; } else { return SelectCode ( N ) ; } if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { SDValue Sext1 = MulOp1 . getOperand ( <NUM_LIT> ) ; if ( Sext1 . getNode ( ) -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { return SelectCode ( N ) ; } OP1 = Sext1 ; } else if ( MulOp1 . getOpcode ( ) == <STR_LIT> ) { LoadSDNode * LD = cast < LoadSDNode > ( MulOp1 . getNode ( ) ) ; if ( LD -> getMemoryVT ( ) != <STR_LIT> || LD -> getExtensionType ( ) != <STR_LIT> || LD -> getAddressingMode ( ) != <STR_LIT> ) { return SelectCode ( N ) ; } SDValue Chain = LD -> getChain ( ) ; SDValue TargetConst0 = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; OP1 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , <STR_LIT> , LD -> getBasePtr ( ) , TargetConst0 , Chain ) , <NUM_LIT> ) ; } else { return SelectCode ( N ) ; } SDNode * Result = CurDAG -> getMachineNode ( <STR_LIT> , dl , <STR_LIT> , OP0 , OP1 ) ; ReplaceUses ( N , Result ) ; return Result ;


<s> static bool isFunctionSignatureRef ( const MCSymbolRefExpr * Ref ) {

return Ref -> getKind ( ) == MCSymbolRefExpr :: VK_<ISA_LIT>_TYPEINDEX ;


<s> __o = __builtin_aarch64_ld2v2df ( ( const __builtin_aarch64_simd_df * ) __a ) ; ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregoiv2df ( __o , <NUM_LIT> ) ; ret . val [ <NUM_LIT> ] = ( float64x2_t ) __builtin_aarch64_get_qregoiv2df ( __o , <NUM_LIT> ) ; return ret ;


<s> else return Changed ; if ( I -> getOpcode ( ) == <STR_LIT> && I -> getOperand ( <NUM_LIT> ) . getMBB ( ) == & MBBN ) { ++ NumDelJmp ; MBB . erase ( I ) ; Changed = true ; }


<s> void limitOccupancy ( unsigned Limit ) {

if ( Occupancy > Limit ) Occupancy = Limit ;


<s> unsigned <ISA_LIT>ConstantIslands :: getUserOffset ( CPUser & U ) const { unsigned UserOffset = getOffsetOf ( U . MI ) ; const BasicBlockInfo & BBI = BBInfo [ U . MI -> getParent ( ) -> getNumber ( ) ] ; unsigned KnownBits = BBI . internalKnownBits ( ) ;

UserOffset += ( isThumb ? <NUM_LIT> : <NUM_LIT> ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> rtx offset = <NUM_LIT> ; if ( GET_CODE ( addr ) == CONST && flag_pic ) { offset = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ; addr = XEXP ( XEXP ( addr , <NUM_LIT> ) , <NUM_LIT> ) ;


<s> if ( OpWidth == <NUM_LIT> ) return ! Subtarget -> is64Bit ( ) ; else if ( OpWidth == <NUM_LIT> ) return Subtarget -> hasCmpxchg16b ( ) ; else return false ;


<s> MachineInstr * LastInst = I ; unsigned LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { if ( isUncondBranchOpcode ( LastOpc ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } if ( isCondBranchOpcode ( LastOpc ) ) { parseCondBranch ( LastInst , TBB , Cond ) ; return false ; } return true ; } MachineInstr * SecondLastInst = I ; unsigned SecondLastOpc = SecondLastInst -> getOpcode ( ) ; if ( AllowModify && isUncondBranchOpcode ( LastOpc ) ) { while ( isUncondBranchOpcode ( SecondLastOpc ) ) { LastInst -> eraseFromParent ( ) ; LastInst = SecondLastInst ; LastOpc = LastInst -> getOpcode ( ) ; if ( I == MBB . begin ( ) || ! isUnpredicatedTerminator ( -- I ) ) { TBB = LastInst -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; return false ; } else { SecondLastInst = I ; SecondLastOpc = SecondLastInst -> getOpcode ( ) ; } } } if ( SecondLastInst && I != MBB . begin ( ) && isUnpredicatedTerminator ( -- I ) ) return true ;

if ( isCondBranchOpcode ( SecondLastOpc ) && isUncondBranchOpcode ( LastOpc ) ) {


<s> unsigned IsPCRelConstant = MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_Constant ; const static MCFixupKindInfo InfosLE [ <STR_LIT> ] = { { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , IsPCRelConstant | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel | MCFixupKindInfo :: FKF_IsAlignedDownTo32Bits } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } , { <STR_LIT> , <NUM_LIT> , <NUM_LIT> , MCFixupKindInfo :: FKF_IsPCRel } , {


<s> void <ISA_LIT>CopyElision :: ExitScope ( MachineBasicBlock * MBB ) {

LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MBB -> getName ( ) << '\n' ) ;


<s> <ISA_LIT>AsmBackend ( const Target & T , const MCRegisterInfo & MRI , const Triple & TT , StringRef CPU , bool N32 ) : TheTriple ( TT ) , IsLittle ( TT . isLittleEndian ( ) ) , IsN32 ( N32 ) {


<s> if ( ! BCVT . isVector ( ) || BCVT . getVectorNumElements ( ) != OriginalVT . getVectorNumElements ( ) ) return SDValue ( ) ; InVec = InVec . getOperand ( <NUM_LIT> ) ; } EVT CurrentVT = InVec . getValueType ( ) ; if ( ! isTargetShuffle ( InVec . getOpcode ( ) ) ) return SDValue ( ) ; if ( ! InVec . hasOneUse ( ) ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > ShuffleMask ; bool UnaryShuffle ; if ( ! getTargetShuffleMask ( InVec . getNode ( ) , CurrentVT . getSimpleVT ( ) , ShuffleMask , UnaryShuffle ) ) return SDValue ( ) ; unsigned NumElems = CurrentVT . getVectorNumElements ( ) ; int Elt = cast < ConstantSDNode > ( EltNo ) -> getZExtValue ( ) ; int Idx = ( Elt > ( int ) NumElems ) ? - <NUM_LIT> : ShuffleMask [ Elt ] ; SDValue LdNode = ( Idx < ( int ) NumElems ) ? InVec . getOperand ( <NUM_LIT> ) : InVec . getOperand ( <NUM_LIT> ) ; unsigned AllowedUses = InVec . getNumOperands ( ) > <NUM_LIT> && InVec . getOperand ( <NUM_LIT> ) == InVec . getOperand ( <NUM_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; if ( LdNode . getOpcode ( ) == <STR_LIT> ) { if ( ! LdNode . getNode ( ) -> hasNUsesOfValue ( AllowedUses , <NUM_LIT> ) ) return SDValue ( ) ; AllowedUses = <NUM_LIT> ;

LdNode = LdNode . getOperand ( <NUM_LIT> ) ;


<s> bool IsIntegerValue = true ; if ( Tag % <NUM_LIT> ) IsIntegerValue = false ; SMLoc ValueExprLoc = Parser . getTok ( ) . getLoc ( ) ; if ( IsIntegerValue ) { const MCExpr * ValueExpr ; if ( Parser . parseExpression ( ValueExpr ) ) return true ; const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( ValueExpr ) ; if ( ! CE ) return Error ( ValueExprLoc , <STR_LIT> ) ; IntegerValue = CE -> getValue ( ) ; } else { if ( Parser . getTok ( ) . isNot ( AsmToken :: String ) ) return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; StringValue = Parser . getTok ( ) . getStringContents ( ) ; Parser . Lex ( ) ; } if ( Parser . parseToken ( AsmToken :: EndOfStatement , <STR_LIT> ) ) return true ; if ( IsIntegerValue ) getTargetStreamer ( ) . emitAttribute ( Tag , IntegerValue ) ; else if ( Tag != <STR_LIT> ) getTargetStreamer ( ) . emitTextAttribute ( Tag , StringValue ) ; else { StringRef Arch = StringValue ; for ( auto Feature : <ISA_LIT>FeatureKV ) if ( llvm :: <STR_LIT> ( Feature . Key ) ) clearFeatureBits ( Feature . Value , Feature . Key ) ; auto ParseResult = llvm :: <STR_LIT> ( StringValue , true , true ) ; if ( ! ParseResult ) { std :: string Buffer ; raw_string_ostream OutputErrMsg ( Buffer ) ; handleAllErrors ( ParseResult . takeError ( ) , [ & ] ( llvm :: StringError & ErrMsg ) { OutputErrMsg << <STR_LIT> << Arch << <STR_LIT> << ErrMsg . getMessage ( ) ;


<s> for ( unsigned I = <NUM_LIT> ; I < Operands . size ( ) ; ++ I ) if ( static_cast < <ISA_LIT>Operand * > ( Operands [ I ] ) -> isCondCode ( ) ) CondLoc = Operands [ I ] -> getStartLoc ( ) ; return Error ( CondLoc , <STR_LIT> + StringRef ( <ISA_LIT>CondCodeToString ( <STR_LIT> ( Cond ) ) ) + <STR_LIT> + <ISA_LIT>CondCodeToString ( <STR_LIT> ( ITCond ) ) + <STR_LIT> ) ; } } else if ( isThumbTwo ( ) && MCID . isPredicable ( ) && Inst . getOperand ( MCID . findFirstPredOperandIdx ( ) ) . getImm ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> && Inst . getOpcode ( ) != <STR_LIT> ) return Error ( Loc , <STR_LIT> ) ; const unsigned Opcode = Inst . getOpcode ( ) ; switch ( Opcode ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { const unsigned RtReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( RtReg == <STR_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; const unsigned Rt = MRI -> getEncodingValue ( RtReg ) ; if ( ( Rt & <NUM_LIT> ) == <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; const unsigned Rt2 = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rt2 != Rt + <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { const unsigned Rn = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rn == Rt || Rn == Rt2 ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> <STR_LIT> ) ; } return false ; } case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { unsigned Rt = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Rt2 = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rt2 == Rt ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : { unsigned Rt = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Rt2 = MRI -> getEncodingValue ( Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; if ( Rt2 != Rt + <NUM_LIT> ) return Error ( Operands [ <NUM_LIT> ] -> getStartLoc ( ) , <STR_LIT> ) ; return false ; } case <STR_LIT> : case <STR_LIT> : {


<s> SDValue <ISA_LIT>TargetLowering :: LowerVASTART ( SDValue Op , SelectionDAG & DAG ) const {

return Subtarget -> isTargetDarwin ( ) ? LowerDarwin_VASTART ( Op , DAG ) : LowerAAPCS_VASTART ( Op , DAG ) ;