<s> SDLoc DL ( Op ) ; assert ( Op . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V1 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( V2 . getSimpleValueType ( ) == <STR_LIT> && <STR_LIT> ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( Op ) ; ArrayRef < int > Mask = SVOp -> getMask ( ) ; assert ( Mask . size ( ) == <NUM_LIT> && <STR_LIT> ) ; SDValue LowV = V1 , HighV = V2 ; int NewMask [ <NUM_LIT> ] = { Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] , Mask [ <NUM_LIT> ] } ; int NumV2Elements = std :: count_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) ; if ( NumV2Elements == <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V1 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( Mask , DAG ) ) ; if ( NumV2Elements == <NUM_LIT> ) { int V2Index = std :: find_if ( Mask . begin ( ) , Mask . end ( ) , [ ] ( int M ) { return M >= <NUM_LIT> ; } ) - Mask . begin ( ) ; int V2AdjIndex = V2Index ^ <NUM_LIT> ; if ( Mask [ V2AdjIndex ] == - <NUM_LIT> ) { if ( V2Index < <NUM_LIT> ) std :: swap ( LowV , HighV ) ; NewMask [ V2Index ] -= <NUM_LIT> ; } else { int V1Index = V2AdjIndex ; int BlendMask [ <NUM_LIT> ] = { Mask [ V2Index ] - <NUM_LIT> , <NUM_LIT> , Mask [ V1Index ] , <NUM_LIT> } ; V2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , V2 , V1 , getV4<ISA_LIT>ShuffleImm8ForMask ( BlendMask , DAG ) ) ;


<s> if ( ( mask & <NUM_LIT> ) != <NUM_LIT> ) { for ( i = <NUM_LIT> ; i < <NUM_LIT> ; i <<= <NUM_LIT> ) if ( ( mask & i ) == <NUM_LIT> ) ++ count ; mask |= <NUM_LIT> ; } if ( bytes_saved ) * bytes_saved = count * UNITS_PER_WORD ;


<s> EVT VT = N -> getValueType ( <NUM_LIT> ) ; ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; if ( ! RHS ) return SDValue ( ) ; SDValue LHS = N -> getOperand ( <NUM_LIT> ) ; unsigned RHSVal = RHS -> getZExtValue ( ) ; if ( ! RHSVal ) return LHS ; SDLoc SL ( N ) ; SelectionDAG & DAG = DCI . DAG ; switch ( LHS -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : { SDValue X = LHS -> getOperand ( <NUM_LIT> ) ; if ( VT == <STR_LIT> && RHSVal == <NUM_LIT> && X . getValueType ( ) == <STR_LIT> && isOperationLegal ( <STR_LIT> , <STR_LIT> ) ) { SDValue Vec = DAG . getBuildVector ( <STR_LIT> , SL , { DAG . getConstant ( <NUM_LIT> , SL , <STR_LIT> ) , LHS -> getOperand ( <NUM_LIT> ) } ) ; return DAG . getNode ( <STR_LIT> , SL , <STR_LIT> , Vec ) ; } if ( VT != <STR_LIT> ) break ; KnownBits Known ; DAG . computeKnownBits ( X , Known ) ; unsigned LZ = Known . countMinLeadingZeros ( ) ; if ( LZ < RHSVal ) break ; EVT XVT = X . getValueType ( ) ; SDValue Shl = DAG . getNode ( <STR_LIT> , SL , XVT , X , SDValue ( RHS , <NUM_LIT> ) ) ; return DAG . getZExtOrTrunc ( Shl , SL , VT ) ; } }

if ( VT != <STR_LIT> ) return SDValue ( ) ;


<s> MAI = new <ISA_LIT>COFFMCAsmInfoMicrosoft ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } break ; default : if ( TheTriple . isOSBinFormatMachO ( ) ) MAI = new <ISA_LIT>MCAsmInfoDarwin ( TT ) ; else MAI = new <ISA_LIT>ELFMCAsmInfo ( TT ) ; break ; } unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ;

MAI -> addInitialFrameState ( MCCFIInstruction :: createDefCfa ( nullptr , Reg , <NUM_LIT> ) ) ;


<s> if ( ! rfn ) return NULL ; gimple_call_set_fndecl ( call , rfn -> decl ) ; return call ;


<s> bool <ISA_LIT>ElimCompare :: optimizeCompareZero ( MachineInstr & Compare , SmallVectorImpl < MachineInstr * > & CCUsers ) { if ( ! isCompareZero ( Compare ) ) return false ; unsigned SrcReg = getCompareSourceReg ( Compare ) ; MachineBasicBlock & MBB = * Compare . getParent ( ) ; MachineBasicBlock :: iterator MBBI = Compare , MBBE = MBB . begin ( ) ; Reference CCRefs ; Reference SrcRefs ; while ( MBBI != MBBE ) { -- MBBI ; MachineInstr & MI = * MBBI ; if ( resultTests ( MI , SrcReg ) ) { if ( ! CCRefs . Use && ! SrcRefs ) { if ( convertToBRCT ( MI , Compare , CCUsers ) ) { BranchOnCounts += <NUM_LIT> ; return true ; } if ( convertToLoadAndTrap ( MI , Compare , CCUsers ) ) { LoadAndTraps += <NUM_LIT> ; return true ; } } if ( ( ! CCRefs && convertToLoadAndTest ( MI , Compare , CCUsers ) ) || ( ! CCRefs . Def && adjustCCMasksForInstr ( MI , Compare , CCUsers ) ) ) { EliminatedComparisons += <NUM_LIT> ; return true ; } } SrcRefs |= getRegReferences ( MI , SrcReg ) ; if ( SrcRefs . Def ) break ; CCRefs |= getRegReferences ( MI , <STR_LIT> ) ; if ( CCRefs . Use && CCRefs . Def ) break ; } MBBI = Compare , MBBE = MBB . end ( ) ; while ( ++ MBBI != MBBE ) { MachineInstr & MI = * MBBI ; if ( preservesValueOf ( MI , SrcReg ) ) { if ( convertToLoadAndTest ( MI , Compare , CCUsers ) ) { EliminatedComparisons += <NUM_LIT> ; return true ; } } if ( getRegReferences ( MI , SrcReg ) . Def ) return false ;

if ( getRegReferences ( MI , <STR_LIT> ) ) return false ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ;

Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> unsigned Mask = ( <NUM_LIT> << Shift ) - <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { int EltIdx = SVOp -> getMaskElt ( i ) ; if ( ( i & Mask ) != <NUM_LIT> && EltIdx != - <NUM_LIT> ) return SDValue ( ) ; if ( ( i & Mask ) == <NUM_LIT> && ( unsigned ) EltIdx != ( i >> Shift ) ) return SDValue ( ) ; } LLVMContext * Context = DAG . getContext ( ) ; unsigned NBits = VT . getVectorElementType ( ) . getSizeInBits ( ) << Shift ; EVT NeVT = EVT :: getIntegerVT ( * Context , NBits ) ; EVT NVT = EVT :: getVectorVT ( * Context , NeVT , NumElems >> Shift ) ; if ( ! isTypeLegal ( NVT ) ) return SDValue ( ) ; unsigned SignificantBits = NVT . getSizeInBits ( ) >> Shift ; if ( V1 . getOpcode ( ) == <STR_LIT> && V1 . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) . getSizeInBits ( ) == SignificantBits ) { SDValue V = V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; ConstantSDNode * CIdx = dyn_cast < ConstantSDNode > ( V1 . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ) ; if ( CIdx && CIdx -> getZExtValue ( ) == <NUM_LIT> && ( ! <STR_LIT> ( V . getNode ( ) ) || ! V . hasOneUse ( ) ) ) { if ( V . getValueSizeInBits ( ) > V1 . getValueSizeInBits ( ) ) { unsigned Ratio = V . getValueSizeInBits ( ) / V1 . getValueSizeInBits ( ) ; EVT FullVT = V . getValueType ( ) ; EVT SubVecVT = EVT :: getVectorVT ( * Context , FullVT . getVectorElementType ( ) , FullVT . getVectorNumElements ( ) / Ratio ) ; V = DAG . getNode ( <STR_LIT> , DL , SubVecVT , V , DAG . getIntPtrConstant ( <NUM_LIT> ) ) ; } V1 = DAG . getNode ( <STR_LIT> , DL , V1 . getValueType ( ) , V ) ; } } return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , NVT , V1 ) ) ;


<s> bool <ISA_LIT>EarlyIfConversion :: runOnMachineFunction ( MachineFunction & MF ) { if ( skipFunction ( * MF . getFunction ( ) ) ) return false ; auto & ST = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; HII = ST . getInstrInfo ( ) ; TRI = ST . getRegisterInfo ( ) ; MFN = & MF ; MRI = & MF . getRegInfo ( ) ; MDT = & getAnalysis < MachineDominatorTree > ( ) ; MLI = & getAnalysis < MachineLoopInfo > ( ) ; MBPI = Enable<ISA_LIT>BP ? & getAnalysis < MachineBranchProbabilityInfo > ( ) : nullptr ; Deleted . clear ( ) ; bool Changed = false ; for ( MachineLoopInfo :: iterator I = MLI -> begin ( ) , E = MLI -> end ( ) ; I != E ; ++ I ) Changed |= visitLoop ( * I ) ;


<s> if ( Second . mayStore ( ) && First . getOpcode ( ) == <STR_LIT> ) { const MachineOperand & Op = Second . getOperand ( <NUM_LIT> ) ; if ( Op . isReg ( ) && Op . isUse ( ) && Op . getReg ( ) == <STR_LIT> ) return true ; } if ( DisableNVSchedule ) return false ; if ( mayBeNewStore ( Second ) ) { const MachineOperand & Stored = Second . getOperand ( Second . getNumOperands ( ) - <NUM_LIT> ) ; if ( ! Stored . isReg ( ) ) return false ; for ( unsigned i = <NUM_LIT> , e = First . getNumOperands ( ) ; i < e ; ++ i ) { const MachineOperand & Op = First . getOperand ( i ) ;

if ( Op . isReg ( ) && Op . isDef ( ) && Op . getReg ( ) == Stored . getReg ( ) ) return true ;


<s> TargetLowering :: AtomicExpansionKind <ISA_LIT>TargetLowering :: shouldExpandAtomicRMWInIR ( AtomicRMWInst * AI ) const { unsigned Size = AI -> getType ( ) -> getPrimitiveSizeInBits ( ) ; if ( EnableQuadwordAtomics && Subtarget . hasQuadwordAtomics ( ) && Size == <NUM_LIT> ) return AtomicExpansionKind :: MaskedIntrinsic ;

return TargetLowering :: shouldExpandAtomicRMWInIR ( AI ) ;


<s> if ( isX87Reg ( MO . getReg ( ) ) ) return true ; }


<s> const <ISA_LIT>RegisterInfo & HRI = * Subtarget . getRegisterInfo ( ) ; unsigned LR = HRI . getRARegister ( ) ; if ( ( Op . getOpcode ( ) != <STR_LIT> && Op . getOpcode ( ) != <STR_LIT> ) || HMFI . hasClobberLR ( ) ) return Op ; unsigned NumOps = Op . getNumOperands ( ) ; if ( Op . getOperand ( NumOps - <NUM_LIT> ) . getValueType ( ) == <STR_LIT> ) -- NumOps ; for ( unsigned i = InlineAsm :: Op_FirstOperand ; i != NumOps ; ) { unsigned Flags = cast < ConstantSDNode > ( Op . getOperand ( i ) ) -> getZExtValue ( ) ;

unsigned NumVals = InlineAsm :: getNumOperandRegisters ( Flags ) ;


<s> for ( unsigned BinOp : { G_FADD , G_FSUB , G_FMUL , G_FDIV } ) for ( auto Ty : { s32 , v4s32 } ) setAction ( { BinOp , Ty } , Legal ) ;

for ( unsigned MemOp : { G_LOAD , G_STORE } ) for ( auto Ty : { v4s32 , v2s64 } ) setAction ( { MemOp , Ty } , Legal ) ;


<s> unsigned const4 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned s1 = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; unsigned is32Bit = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( ! is32Bit ) return MCDisassembler :: Fail ; DecodeStatus status = DecodeDataRegsRegisterClass ( Inst , s1 , Address , Decoder ) ; if ( status != MCDisassembler :: Success ) return status ;

Inst . addOperand ( MCOperand :: createImm ( const4 ) ) ;


<s> int i , j ; for ( i = <NUM_LIT> ; i < sizeof dest / sizeof dest [ <NUM_LIT> ] ; i ++ ) for ( j = <NUM_LIT> ; j < sizeof src / sizeof src [ <NUM_LIT> ] ; j ++ ) define_insn ( & dest [ i ] , & src [ j ] , <STR_LIT> ) ; exit ( <NUM_LIT> ) ;


<s> MachineInstrBuilder buildLoad ( const DstOp & Res , Register Addr , LLT MemTy , MachinePointerInfo & MPO ) {

MachineFunction & MF = MIRBuilder . getMF ( ) ;


<s> void <ISA_LIT>RegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : ArgRegClass = & <STR_LIT> ; break ; } unsigned VReg = RegInfo . createVirtualRegister ( ArgRegClass ) ; RegInfo . addLiveIn ( ArgRegs [ ArgRegIdx ] , VReg ) ; ArgVal = DAG . getCopyFromReg ( Chain , dl , VReg , ObjectVT ) ; ++ ArgRegIdx ; } else { int FI = MFI -> CreateFixedObject ( ObjSize , ArgOffset , true , false ) ; SDValue FIN = DAG . getFrameIndex ( FI , PtrVT ) ; ArgVal = DAG . getLoad ( ObjectVT , dl , Chain , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; ArgOffset += StackSlotSize ; } InVals . push_back ( ArgVal ) ; Chain = ArgVal . getOperand ( <NUM_LIT> ) ; } if ( isVarArg ) { SmallVector < SDValue , <NUM_LIT> - <NUM_LIT> + <NUM_LIT> > MemOps ; for ( ; ArgRegIdx != NumArgRegs ; ++ ArgRegIdx ) { VarArgsFrameIndex = MFI -> CreateFixedObject ( StackSlotSize , ArgOffset , true , false ) ; SDValue FIN = DAG . getFrameIndex ( VarArgsFrameIndex , PtrVT ) ; unsigned VReg = MF . addLiveIn ( ArgRegs [ ArgRegIdx ] , & <STR_LIT> ) ; SDValue ArgVal = DAG . getRegister ( VReg , <STR_LIT> ) ; SDValue Store = DAG . getStore ( Chain , dl , ArgVal , FIN , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = Store . getOperand ( <NUM_LIT> ) ; MemOps . push_back ( Store ) ; ArgOffset += StackSlotSize ; }

if ( ! MemOps . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOps [ <NUM_LIT> ] , MemOps . size ( ) ) ;


assert ( Kind == Register && <STR_LIT> ) ;


<s> if ( isDarwinABI ) { FPOpOut = getFramePointerFrameIndex ( DAG ) ; FPOpOut = DAG . getLoad ( VT , dl , Chain , FPOpOut , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ; Chain = SDValue ( FPOpOut . getNode ( ) , <NUM_LIT> ) ; } }


<s> SelectionDAG & DAG = CLI . DAG ; DebugLoc & dl = CLI . DL ; SmallVector < <STR_LIT> , <NUM_LIT> > & Outs = CLI . Outs ; SmallVector < SDValue , <NUM_LIT> > & OutVals = CLI . OutVals ; SmallVector < <STR_LIT> , <NUM_LIT> > & Ins = CLI . Ins ; SDValue Chain = CLI . Chain ; SDValue Callee = CLI . Callee ; bool & isTailCall = CLI . IsTailCall ; CallingConv :: ID CallConv = CLI . CallConv ; bool isVarArg = CLI . IsVarArg ; if ( isTailCall ) isTailCall = IsEligibleForTailCallOptimization ( Callee , CallConv , isVarArg , Ins , DAG ) ; if ( <ISA_LIT>SubTarget . isSVR4ABI ( ) ) { if ( <ISA_LIT>SubTarget . is<ISA_LIT>64 ( ) ) return LowerCall_64SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; else return LowerCall_32SVR4 ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ; } return LowerCall_Darwin ( Chain , Callee , CallConv , isVarArg , isTailCall , Outs , OutVals , Ins , dl , DAG , InVals ) ;


__builtin_ia32_pmovdw128mem_mask ( ( unsigned long long * ) __P , ( __v4si ) __A , __M ) ;


<s> EnclosedEdges . resize ( MRI -> getNumVirtRegs ( ) ) ; EnclosedInstrs . clear ( ) ; std :: vector < Closure > Closures ; unsigned ClosureID = <NUM_LIT> ; for ( unsigned Idx = <NUM_LIT> ; Idx < MRI -> getNumVirtRegs ( ) ; ++ Idx ) { Register Reg = Register :: index2VirtReg ( Idx ) ; if ( ! isGPR ( MRI -> getRegClass ( Reg ) ) ) continue ; if ( EnclosedEdges . test ( Idx ) ) continue ; Closure C ( ClosureID ++ , { MaskDomain } ) ; buildClosure ( C , Reg ) ; if ( ! C . empty ( ) && C . isLegal ( MaskDomain ) ) Closures . push_back ( std :: move ( C ) ) ; } for ( Closure & C : Closures ) { LLVM_DEBUG ( C . dump ( MRI ) ) ; if ( isReassignmentProfitable ( C , MaskDomain ) ) { reassign ( C , MaskDomain ) ; ++ NumClosuresConverted ; Changed = true ; }


<s> Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ;


<s> assert ( ( N == <NUM_LIT> ) && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemBaseReg ( ) ) ) ;


<s> if ( FeatureBitSet . any ( ) && ( FeatureBitSet & FeatureBits ) . none ( ) ) return false ; return Name == Other ;


<s> bool <ISA_LIT>FastISel :: emitFCmp ( MVT RetVT , const Value * LHS , const Value * RHS ) { if ( RetVT != <STR_LIT> && RetVT != <STR_LIT> ) return false ; bool UseImm = false ; if ( const auto * CFP = dyn_cast < ConstantFP > ( RHS ) ) if ( CFP -> isZero ( ) && ! CFP -> isNegative ( ) ) UseImm = true ; unsigned LHSReg = getRegForValue ( LHS ) ; if ( ! LHSReg ) return false ; if ( UseImm ) { unsigned Opc = ( RetVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( Opc ) ) . addReg ( LHSReg ) ; return true ;


<s> void SCEVParser :: computeStride ( ) { if ( const SCEVAddRecExpr * AddRec = dyn_cast < SCEVAddRecExpr > ( p_SCEVP ) ) { const SCEV * StepRec = AddRec -> getStepRecurrence ( * p_SEL ) ; if ( StepRec -> getSCEVType ( ) == SCEVTypes :: scConstant && AddRec -> isAffine ( ) ) { m_StepInducation = p_SEL -> getUnsignedRangeMax ( StepRec ) . getZExtValue ( ) ; const SCEV * scev1 = AddRec -> getStart ( ) ; searchForValue ( scev1 , m_InsVec ) ;


<s> Value * <ISA_LIT>IREmitter :: visitFMAX ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> Op -> Kind = MEMORY_REG_REG ; Op -> Mem . BaseReg = BaseReg ; Op -> Mem . AluOp = AluOp ; Op -> Mem . OffsetReg = OffsetReg ;


<s> unsigned <ISA_LIT>Subtarget :: getMinSubfunctionAlignment ( ) const { return ceil ( log2 ( MinSubfunctionAlign ) ) ;


<s> PointerType * Int8PtrTy = Type :: getInt8PtrTy ( LI . getContext ( ) , AS ) ; auto * NewPtr = IRB . CreateBitCast ( IRB . CreateConstGEP1_64 ( IRB . CreatePointerBitCastOrAddrSpaceCast ( Base , Int8PtrTy ) , Offset - Adjust ) , Int32PtrTy ) ; LoadInst * NewLd = IRB . CreateAlignedLoad ( IRB . getInt32Ty ( ) , NewPtr , Align ( <NUM_LIT> ) ) ; NewLd -> copyMetadata ( LI ) ; NewLd -> setMetadata ( LLVMContext :: MD_range , nullptr ) ; unsigned ShAmt = Adjust * <NUM_LIT> ; auto * NewVal = IRB . CreateBitCast ( IRB . CreateTrunc ( IRB . CreateLShr ( NewLd , ShAmt ) , IntNTy ) , LI . getType ( ) ) ; LI . replaceAllUsesWith ( NewVal ) ;


<s> tree gimple_folder :: convert_pred ( gimple_seq & stmts , tree vectype , unsigned int argno ) { tree pred = gimple_call_arg ( call , argno ) ; if ( known_eq ( TYPE_VECTOR_SUBPARTS ( TREE_TYPE ( pred ) ) , TYPE_VECTOR_SUBPARTS ( vectype ) ) ) return pred ;

return gimple_build ( & stmts , VIEW_CONVERT_EXPR , truth_type_for ( vectype ) , pred ) ;


<s> static rtx c4x_struct_value_rtx ( tree fntype ATTRIBUTE_UNUSED , int incoming ATTRIBUTE_UNUSED ) { return gen_rtx_REG ( Pmode , AR0_REGNO ) ;


<s> if ( TM -> Options . ThreadModel == ThreadModel :: Single ) addPass ( createLowerAtomicPass ( ) ) ; else addPass ( createAtomicExpandPass ( ) ) ; addPass ( create<ISA_LIT>LowerGlobalDtors ( ) ) ; addPass ( create<ISA_LIT>FixFunctionBitcasts ( ) ) ; if ( getOptLevel ( ) != CodeGenOpt :: None ) addPass ( create<ISA_LIT>OptimizeReturned ( ) ) ;


<s> unsigned HalfBits = HalfType -> getPrimitiveSizeInBits ( ) ; IntegerType * FullType = IntegerType :: get ( getContext ( ) , HalfBits * <NUM_LIT> ) ; Value * DivHi = Builder . CreateCast ( Instruction :: ZExt , Op0 , FullType ) ; Value * DivLo = Builder . CreateCast ( Instruction :: ZExt , Op1 , FullType ) ; Dividend = Builder . CreateOr ( Builder . CreateShl ( DivHi , ConstantInt :: get ( FullType , HalfBits ) ) , DivLo ) ; Divisor = getOperand ( <NUM_LIT> ) ; } else { Dividend = getOperand ( <NUM_LIT> ) ;


<s> getPALMetadata ( ) -> toBlob ( Type , Blob ) ; if ( Blob . empty ( ) ) return ;

EmitNote ( Vendor , MCConstantExpr :: create ( Blob . size ( ) , getContext ( ) ) , Type , [ & ] ( MCELFStreamer & OS ) { OS . EmitBytes ( Blob ) ; } ) ;


<s> SMLoc S = Parser . getTok ( ) . getLoc ( ) ; int64_t Dfmt = <NUM_LIT> , Nfmt = <NUM_LIT> ; bool GotDfmt = false , GotNfmt = false ; while ( ! GotDfmt || ! GotNfmt ) { if ( ! GotDfmt ) { auto Res = parseIntWithPrefix ( <STR_LIT> , Dfmt ) ; if ( Res != MatchOperand_NoMatch ) { if ( Res != MatchOperand_Success ) return Res ; if ( Dfmt >= <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } GotDfmt = true ; Parser . Lex ( ) ; continue ; } } if ( ! GotNfmt ) { auto Res = parseIntWithPrefix ( <STR_LIT> , Nfmt ) ; if ( Res != MatchOperand_NoMatch ) { if ( Res != MatchOperand_Success ) return Res ; if ( Nfmt >= <NUM_LIT> ) { Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; return MatchOperand_ParseFail ; } GotNfmt = true ; Parser . Lex ( ) ; continue ; } } break ; } if ( ! GotDfmt && ! GotNfmt ) return MatchOperand_NoMatch ; auto Format = Dfmt | Nfmt << <NUM_LIT> ; Operands . push_back ( <ISA_LIT>Operand :: CreateImm ( this , Format , S , <ISA_LIT>Operand :: ImmTyFORMAT ) ) ; return MatchOperand_Success ;


<s> TargetPassConfig :: addPreISel ( ) ; addPass ( create<ISA_LIT>LowerRefTypesIntPtrConv ( ) ) ; return false ;


<s> else if ( offset < <NUM_LIT> * GET_MODE_SIZE ( mode ) + <NUM_LIT> ) delta = <NUM_LIT> * GET_MODE_SIZE ( mode ) ; else delta = offset & ( ~ <NUM_LIT> * GET_MODE_SIZE ( mode ) ) ; xop0 = force_operand ( plus_constant ( Pmode , xop0 , offset - delta ) , NULL_RTX ) ; x = plus_constant ( Pmode , xop0 , delta ) ; } else if ( offset < <NUM_LIT> && offset > - <NUM_LIT> ) x = force_operand ( x , NULL_RTX ) ; else { xop1 = force_reg ( SImode , xop1 ) ; x = gen_rtx_PLUS ( SImode , xop0 , xop1 ) ; } } else if ( GET_CODE ( x ) == PLUS && s_register_operand ( XEXP ( x , <NUM_LIT> ) , SImode ) && ! s_register_operand ( XEXP ( x , <NUM_LIT> ) , SImode ) ) { rtx xop0 = force_operand ( XEXP ( x , <NUM_LIT> ) , NULL_RTX ) ; x = gen_rtx_PLUS ( SImode , xop0 , XEXP ( x , <NUM_LIT> ) ) ;


<s> static inline ShiftOpc getAM2ShiftOpc ( unsigned AM2Opc ) { return ( ShiftOpc ) ( AM2Opc >> <NUM_LIT> ) ;


<s> static void StoreTailCallArgumentsToStackSlot ( SelectionDAG & DAG , SDValue Chain , const SmallVectorImpl < TailCallArgumentInfo > & TailCallArgs , SmallVectorImpl < SDValue > & MemOpChains , const SDLoc & dl ) { for ( unsigned i = <NUM_LIT> , e = TailCallArgs . size ( ) ; i != e ; ++ i ) { SDValue Arg = TailCallArgs [ i ] . Arg ;

SDValue FIN = TailCallArgs [ i ] . FrameIdxOp ;


<s> if ( s390_function_arg_size ( mode , type ) > <NUM_LIT> ) return false ;

if ( ! type ) return VECTOR_MODE_P ( mode ) ;


<s> __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) __crc32d ( unsigned int __C , unsigned int __V ) { return __builtin_ia32_crc32si ( __C , __V ) ;


<s> if ( I -> isDebugValue ( ) ) continue ; if ( ! isUnpredicatedTerminator ( I ) ) break ; if ( ! I -> isBranch ( ) ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) return true ; if ( I -> getOpcode ( ) == <STR_LIT> ) { if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( llvm :: next ( I ) != MBB . end ( ) ) llvm :: next ( I ) -> eraseFromParent ( ) ; Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ;


<s> SDValue NewML = DAG . getMaskedLoad ( VT , DL , ML -> getChain ( ) , ML -> getBasePtr ( ) , ML -> getMask ( ) , DAG . getUNDEF ( VT ) , ML -> getMemoryVT ( ) , ML -> getMemOperand ( ) , ML -> getExtensionType ( ) ) ; SDValue Blend = DAG . getSelect ( DL , VT , ML -> getMask ( ) , NewML , ML -> getSrc0 ( ) ) ;

return DCI . CombineTo ( ML , Blend , NewML . getValue ( <NUM_LIT> ) , true ) ;


<s> RegisterMCAsmInfo < <ISA_LIT>MCAsmInfo > X ( The<ISA_LIT>Target ) ; TargetRegistry :: RegisterMCCodeGenInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCCodeGenInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( The<ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCInstPrinter ( The<ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ;


<s> Subtarget = & TM . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> unsigned getMem132Opcode ( ) const {


<s> explicit <ISA_LIT>ISelListener ( ) {


<s> case llvm :: ELF :: EF_MIPS_ARCH_32 : case llvm :: ELF :: EF_MIPS_ARCH_32R2 : case llvm :: ELF :: EF_MIPS_ARCH_32R6 : return <NUM_LIT> ; case llvm :: ELF :: EF_MIPS_ARCH_64 :


<s> static DecodeStatus DecodeFCCRegsRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: CreateReg ( FCCRegDecoderTable [ RegNo ] ) ) ; return MCDisassembler :: Success ;


<s> bool isSOP2 ( uint16_t Opcode ) const {

return get ( Opcode ) . TSFlags & <STR_LIT> ;


<s> CanFold = true ; } unsigned SVTNumElts = SVT . getVectorNumElements ( ) ; ShuffleVectorSDNode * SVOp = cast < ShuffleVectorSDNode > ( N ) ; for ( unsigned i = <NUM_LIT> , e = SVTNumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) == ( int ) ( i * <NUM_LIT> ) ; for ( unsigned i = SVTNumElts , e = NumElts ; i != e && CanFold ; ++ i ) CanFold = SVOp -> getMaskElt ( i ) < <NUM_LIT> ; if ( CanFold ) { SDValue BC00 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue BC01 = DAG . getBitcast ( VT , BC0 . getOperand ( <NUM_LIT> ) ) ; SDValue NewBinOp = DAG . getNode ( BC0 . getOpcode ( ) , dl , VT , BC00 , BC01 ) ; return DAG . getVectorShuffle ( VT , dl , NewBinOp , N1 , & SVOp -> getMask ( ) [ <NUM_LIT> ] ) ; } } } SmallVector < SDValue , <NUM_LIT> > Elts ; for ( unsigned i = <NUM_LIT> , e = VT . getVectorNumElements ( ) ; i != e ; ++ i ) Elts . push_back ( getShuffleScalarElt ( N , i , DAG , <NUM_LIT> ) ) ; if ( SDValue LD = EltsFromConsecutiveLoads ( VT , Elts , dl , DAG , true ) ) return LD ;

if ( isTargetShuffle ( N -> getOpcode ( ) ) ) {


gcc_assert ( ! aarch64_sve_mode_p ( mode ) ) ;


<s> void setISAExtensionFromPredicates ( const PredicateLibrary & P ) { if ( P . hasCn<ISA_LIT> ( ) ) ISAExtension = <STR_LIT> ; else ISAExtension = <STR_LIT> ;


<s> for ( unsigned i = <NUM_LIT> ; i != NumElems ; ++ i ) { int Idx = SVOp -> getMaskElt ( i ) ; if ( Idx >= <NUM_LIT> ) { if ( Idx < ( int ) NumElems ) Idx += NumElems ; else Idx -= NumElems ;


<s> SDValue Glue = expandIntrinsicWChainHelper ( N , DL , DAG , Opcode , <NUM_LIT> , Subtarget , Results ) ; if ( Opcode != <STR_LIT> ) return ; SDValue Chain = Results [ <NUM_LIT> ] ; SDValue ecx = DAG . getCopyFromReg ( Chain , DL , <STR_LIT> , <STR_LIT> , Glue ) ; Results [ <NUM_LIT> ] = ecx ;

Results . push_back ( ecx . getValue ( <NUM_LIT> ) ) ;


<s> <ISA_LIT>LowerIntrinsics ( ) : ModulePass ( ID ) {


<s> case <STR_LIT> : if ( ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) && ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { if ( Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( SrcReg , false , false , isKill ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } else { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( <STR_LIT> ) ) . addReg ( DstReg , true , false , false , isDead ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } } break ; case <STR_LIT> : case <STR_LIT> : if ( ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) && ( MI -> getOperand ( <NUM_LIT> ) . isReg ( ) ) ) { const TargetRegisterClass * RC = RI . getRegClass ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned StoreOpc , LoadOpc ; if ( RC == <STR_LIT> ) { LoadOpc = <STR_LIT> ; StoreOpc = <STR_LIT> ; } else if ( RC == <STR_LIT> ) { LoadOpc = <STR_LIT> ; StoreOpc = <STR_LIT> ; } else assert ( <NUM_LIT> && <STR_LIT> ) ; if ( Ops [ <NUM_LIT> ] == <NUM_LIT> ) { unsigned SrcReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isKill = MI -> getOperand ( <NUM_LIT> ) . isKill ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( StoreOpc ) ) . addReg ( SrcReg , false , false , isKill ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } else { unsigned DstReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; bool isDead = MI -> getOperand ( <NUM_LIT> ) . isDead ( ) ; NewMI = BuildMI ( MF , MI -> getDebugLoc ( ) , get ( LoadOpc ) ) . addReg ( DstReg , true , false , false , isDead ) . addImm ( <NUM_LIT> ) . addFrameIndex ( FI ) ; } } break ; }


<s> virtual const char * getPassName ( ) const override { return <STR_LIT> ;


<s> auto TA = addr < DefNode * > ( RDA . Addr -> getReachedDef ( ) ) ; if ( TA . Id == DA . Id ) { RDA . Addr -> setReachedDef ( Sib ) ; } else { while ( TA . Id != <NUM_LIT> ) { NodeId S = TA . Addr -> getSibling ( ) ; if ( S == DA . Id ) { TA . Addr -> setSibling ( Sib ) ; break ; } TA = addr < DefNode * > ( S ) ; } } if ( ! ReachedDefs . empty ( ) ) { auto Last = NodeAddr < DefNode * > ( ReachedDefs . back ( ) ) ; Last . Addr -> setSibling ( RDA . Addr -> getReachedDef ( ) ) ; RDA . Addr -> setReachedDef ( ReachedDefs . front ( ) . Id ) ; }


<s> } } unsigned NumElts = VT . getVectorNumElements ( ) ; bool isOnlyLowElement = true ; bool usesOnlyOneValue = true ; bool hasDominantValue = false ; bool isConstant = true ; DenseMap < SDValue , unsigned > ValueCounts ; SDValue Value ; for ( unsigned i = <NUM_LIT> ; i < NumElts ; ++ i ) { SDValue V = Op . getOperand ( i ) ; if ( V . getOpcode ( ) == <STR_LIT> ) continue ; if ( i > <NUM_LIT> ) isOnlyLowElement = false ; if ( ! isa < ConstantFPSDNode > ( V ) && ! isa < ConstantSDNode > ( V ) ) isConstant = false ; ValueCounts . insert ( std :: make_pair ( V , <NUM_LIT> ) ) ; unsigned & Count = ValueCounts [ V ] ; if ( ++ Count > ( NumElts / <NUM_LIT> ) ) { hasDominantValue = true ; Value = V ; } } if ( ValueCounts . size ( ) != <NUM_LIT> ) usesOnlyOneValue = false ; if ( ! Value . getNode ( ) && ValueCounts . size ( ) > <NUM_LIT> ) Value = ValueCounts . begin ( ) -> first ; if ( ValueCounts . size ( ) == <NUM_LIT> ) return DAG . getUNDEF ( VT ) ; if ( isOnlyLowElement && ! <STR_LIT> ( Value . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , Value ) ; unsigned EltSize = VT . getVectorElementType ( ) . getSizeInBits ( ) ; if ( hasDominantValue && EltSize <= <NUM_LIT> ) { if ( ! isConstant ) { SDValue N ; if ( Value -> getOpcode ( ) == <STR_LIT> && isa < ConstantSDNode > ( Value -> getOperand ( <NUM_LIT> ) ) ) { N = DAG . getNode ( <STR_LIT> , DL , VT , Value -> getOperand ( <NUM_LIT> ) , Value -> getOperand ( <NUM_LIT> ) ) ;

} else N = DAG . getNode ( <STR_LIT> , DL , VT , Value ) ;


<s> SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; switch ( getLexer ( ) . getKind ( ) ) {


<s> return isUInt < <NUM_LIT> > ( getConstantImm ( ) ) ; } return isImm ( ) && isAcceptableSymbolRef ( getImm ( ) ) ;


<s> MVT <ISA_LIT>TargetLowering :: getRegisterTypeForCallingConv ( LLVMContext & Context , CallingConv :: ID CC , EVT VT ) const { if ( VT == <STR_LIT> && Subtarget . hasStdExtF ( ) && ! Subtarget . hasStdExtZfh ( ) ) return <STR_LIT> ;

return TargetLowering :: getRegisterTypeForCallingConv ( Context , CC , VT ) ;


<s> LastInstWritesM0 = false ; ReturnsVoid = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> returnsVoid ( ) ; memset ( & UsedRegs , <NUM_LIT> , sizeof ( UsedRegs ) ) ; memset ( & DefinedRegs , <NUM_LIT> , sizeof ( DefinedRegs ) ) ; for ( MachineFunction :: iterator BI = MF . begin ( ) , BE = MF . end ( ) ; BI != BE ; ++ BI ) { MachineBasicBlock & MBB = * BI ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) , E = MBB . end ( ) ;


<s> static const MachineOperand & getLdStOffsetOp ( const MachineInstr & MI ) {

unsigned Idx = isPairedLdSt ( MI ) ? <NUM_LIT> : <NUM_LIT> ;


<s> int i ; if ( mep_leaf_registers [ <NUM_LIT> ] != enable ) for ( i = <NUM_LIT> ; i < FIRST_PSEUDO_REGISTER ; i ++ ) mep_leaf_registers [ i ] = enable ;


<s> } else { unsigned ReducedSizeInBits = ReducedVT . getSizeInBits ( ) ; if ( ( RegSize % ReducedSizeInBits ) != <NUM_LIT> ) return SDValue ( ) ; SmallVector < SDValue , <NUM_LIT> > Ops ( RegSize / ReducedSizeInBits , DAG . getUNDEF ( ReducedVT ) ) ; Ops [ <NUM_LIT> ] = NewN0 ; NewN0 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; Ops [ <NUM_LIT> ] = NewN1 ; NewN1 = DAG . getNode ( <STR_LIT> , DL , OpsVT , Ops ) ; if ( Mode == MULU8 || Mode == MULS8 ) { SDValue Mul = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue Res = DAG . getNode ( Mode == MULU8 ? <STR_LIT> : <STR_LIT> , DL , ResVT , Mul ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ; } else { SDValue MulLo = DAG . getNode ( <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; SDValue MulHi = DAG . getNode ( Mode == MULS16 ? <STR_LIT> : <STR_LIT> , DL , OpsVT , NewN0 , NewN1 ) ; MVT ResVT = <STR_LIT> ( <STR_LIT> , RegSize / <NUM_LIT> ) ; SDValue Res = getUnpackl ( DAG , DL , OpsVT , MulLo , MulHi ) ; Res = DAG . getBitcast ( ResVT , Res ) ; return DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getIntPtrConstant ( <NUM_LIT> , DL ) ) ;


<s> MLI = & getAnalysis < MachineLoopInfo > ( ) ; MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> isSSA ( ) ) return false ; bool Changed = false ; SmallSetVector < MachineInstr * , <NUM_LIT> > ToBeRemoved ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : MBB ) { switch ( MI . getOpcode ( ) ) { default : break ; case <STR_LIT> : Changed = visitAND < uint32_t > ( MI , ToBeRemoved ) ; break ; case <STR_LIT> : Changed = visitAND < uint64_t > ( MI , ToBeRemoved ) ; break ; case <STR_LIT> : Changed = visitORR ( MI , ToBeRemoved ) ; }


<s> STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg2 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_vreplace_un_v4si || icode == CODE_FOR_vreplace_un_v4sf ) { STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg2 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } else if ( icode == CODE_FOR_vsldb_v16qi || icode == CODE_FOR_vsldb_v8hi || icode == CODE_FOR_vsldb_v4si || icode == CODE_FOR_vsldb_v2di || icode == CODE_FOR_vsrdb_v16qi || icode == CODE_FOR_vsrdb_v8hi || icode == CODE_FOR_vsrdb_v4si || icode == CODE_FOR_vsrdb_v2di ) { STRIP_NOPS ( arg2 ) ; if ( TREE_CODE ( arg2 ) != INTEGER_CST || ! IN_RANGE ( TREE_INT_CST_LOW ( arg2 ) , <NUM_LIT> , <NUM_LIT> ) ) { error ( <STR_LIT> ) ; return CONST0_RTX ( tmode ) ; } } if ( target == <NUM_LIT> || GET_MODE ( target ) != tmode || ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( target , tmode ) ) target = gen_reg_rtx ( tmode ) ;

if ( ! ( * insn_data [ icode ] . operand [ <NUM_LIT> ] . predicate ) ( op0 , mode0 ) ) op0 = copy_to_mode_reg ( mode0 , op0 ) ;


<s> MachineInstr * CondDef = MRI . getVRegDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; while ( CondDef ) { if ( ! MRI . hasOneUse ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; unsigned Opc = CondDef -> getOpcode ( ) ; if ( Opc != TargetOpcode :: COPY && Opc != TargetOpcode :: G_TRUNC ) break ; if ( Opc == TargetOpcode :: COPY && Register :: isPhysicalRegister ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ) return false ; CondDef = MRI . getVRegDef ( CondDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; } if ( ! CondDef ) return false ; unsigned CondOpc = CondDef -> getOpcode ( ) ; if ( CondOpc != TargetOpcode :: G_ICMP && CondOpc != TargetOpcode :: G_FCMP ) return false ; <STR_LIT> CondCode ;

if ( CondOpc == TargetOpcode :: G_ICMP ) {


<s> default : gcc_unreachable ( ) ; } gcc_unreachable ( ) ; case FRAME_POINTER_REGNUM : switch ( to ) { case THUMB_HARD_FRAME_POINTER_REGNUM : return <NUM_LIT> ; case ARM_HARD_FRAME_POINTER_REGNUM : return offsets -> frame - offsets -> soft_frame ; case STACK_POINTER_REGNUM : return offsets -> outgoing_args - offsets -> soft_frame ; default : gcc_unreachable ( ) ;


<s> } assert ( Rotation != <NUM_LIT> && <STR_LIT> ) ; assert ( ( Lo || Hi ) && <STR_LIT> ) ; if ( ! Lo ) Lo = Hi ; else if ( ! Hi ) Hi = Lo ; int Scale = <NUM_LIT> / NumLaneElts ; if ( Subtarget -> hasSSSE3 ( ) ) { MVT AlignVT = <STR_LIT> ( <STR_LIT> , <NUM_LIT> * NumLanes ) ; Lo = DAG . getNode ( <STR_LIT> , DL , AlignVT , Lo ) ; Hi = DAG . getNode ( <STR_LIT> , DL , AlignVT , Hi ) ; return DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , AlignVT , Hi , Lo , DAG . getConstant ( Rotation * Scale , <STR_LIT> ) ) ) ; } assert ( VT . getSizeInBits ( ) == <NUM_LIT> && <STR_LIT> ) ; assert ( Mask . size ( ) <= <NUM_LIT> && <STR_LIT> ) ; int LoByteShift = <NUM_LIT> - Rotation * Scale ; int HiByteShift = Rotation * Scale ;

Lo = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Lo ) ;


<s> static rtx aarch64_gen_unspec_cond ( rtx_code code , machine_mode pred_mode , rtx pred , rtx op0 , rtx op1 ) {

rtvec vec = gen_rtvec ( <NUM_LIT> , pred , op0 , op1 ) ;


<s> unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; BuildMI ( MBB , MBB . getFirstNonPHI ( ) , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( Src ) ; if ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) != <NUM_LIT> ) { BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , Dst ) . addReg ( <STR_LIT> ) . addReg ( Dst ) ; } BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( Dst ) ; Skip ( MI , MI . getOperand ( <NUM_LIT> ) ) ; BuildMI ( MBB , & MI , DL , TII -> get ( <STR_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addReg ( Dst ) ; MI . eraseFromParent ( ) ;


<s> if ( mips_classify_address ( & addr , x , mode , false ) ) switch ( addr . type ) { case ADDRESS_REG : if ( msa_p ) { if ( mips_signed_immediate_p ( INTVAL ( addr . offset ) , <NUM_LIT> , mips_ldst_scaled_shift ( mode ) ) ) return <NUM_LIT> ; else return <NUM_LIT> ; } if ( TARGET_MIPS16 && ! mips16_unextended_reference_p ( mode , addr . reg , UINTVAL ( addr . offset ) ) ) return factor * <NUM_LIT> ;


<s> void init ( VLIWMachineScheduler * dag , const TargetSchedModel * smodel ) {


<s> unsigned Opc ; switch ( RetVT . SimpleTy ) { default : return false ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } const Value * Cond = I -> getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = <STR_LIT> ; const auto * CI = dyn_cast < CmpInst > ( Cond ) ; if ( CI && ( CI -> getParent ( ) == I -> getParent ( ) ) ) { bool NeedSwap ; std :: tie ( CC , NeedSwap ) = get<ISA_LIT>ConditionCode ( CI -> getPredicate ( ) ) ; if ( CC > <STR_LIT> ) return false ; const Value * CmpLHS = CI -> getOperand ( <NUM_LIT> ) ; const Value * CmpRHS = CI -> getOperand ( <NUM_LIT> ) ; if ( NeedSwap ) std :: swap ( CmpLHS , CmpRHS ) ; EVT CmpVT = TLI . getValueType ( DL , CmpLHS -> getType ( ) ) ; if ( ! <ISA_LIT>FastEmitCompare ( CmpLHS , CmpRHS , CmpVT , CI -> getDebugLoc ( ) ) ) return false ; } else { unsigned CondReg = getRegForValue ( Cond ) ; if ( CondReg == <NUM_LIT> ) return false ; bool CondIsKill = hasTrivialKill ( Cond ) ; if ( MRI . getRegClass ( CondReg ) == & <STR_LIT> ) BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addReg ( CondReg ) ; else BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) ) . addReg ( CondReg , getKillRegState ( CondIsKill ) ) . addImm ( <NUM_LIT> ) ; } const Value * LHS = I -> getOperand ( <NUM_LIT> ) ;

const Value * RHS = I -> getOperand ( <NUM_LIT> ) ;


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & O ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; printOperand ( MI , OpNo , O ) ; return false ;


<s> bool <ISA_LIT>HardwareLoops :: isInvalidLoopOperation ( const MachineInstr * MI ) const { if ( MI -> getDesc ( ) . isCall ( ) ) return true ; if ( isHardwareLoop ( MI ) ) return true ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; if ( ! MO . isReg ( ) || ! MO . isDef ( ) ) continue ; unsigned R = MO . getReg ( ) ; if ( R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> || R == <STR_LIT> ) return true ;


<s> for ( MachineFunction :: iterator BB = MF . begin ( ) , E = MF . end ( ) ; BB != E ; ++ BB ) for ( MachineBasicBlock :: iterator I = BB -> begin ( ) ; I != BB -> end ( ) ; ++ I ) if ( I -> getOpcode ( ) == FrameSetupOpcode ) Changed |= adjustCallSequence ( MF , * BB , I ) ;


<s> if ( TYPE_SIZE ( type ) && integer_zerop ( TYPE_SIZE ( type ) ) ) return NO_ABI_IDENTITY ; piece p = { } ; if ( <STR_LIT> ( type , & p . num_zr , & p . num_pr ) ) { machine_mode mode = TYPE_MODE_RAW ( type ) ; gcc_assert ( VECTOR_MODE_P ( mode ) && ( ! TARGET_SVE || aarch64_sve_mode_p ( mode ) ) ) ;


<s> unsigned RegOp = IsStore ? <NUM_LIT> : <NUM_LIT> ; unsigned AddrOp = AddrBase + <NUM_LIT> ; assert ( Inst . getNumOperands ( ) == <NUM_LIT> && Inst . getOperand ( RegOp ) . isReg ( ) && Inst . getOperand ( AddrBase + <STR_LIT> ) . isReg ( ) && Inst . getOperand ( AddrBase + <STR_LIT> ) . isImm ( ) && Inst . getOperand ( AddrBase + <STR_LIT> ) . isReg ( ) && Inst . getOperand ( AddrBase + <STR_LIT> ) . isReg ( ) && ( Inst . getOperand ( AddrOp ) . isExpr ( ) || Inst . getOperand ( AddrOp ) . isImm ( ) ) && <STR_LIT> ) ; unsigned Reg = Inst . getOperand ( RegOp ) . getReg ( ) ; if ( Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> && Reg != <STR_LIT> ) return ; bool Absolute = true ;

if ( Inst . getOperand ( AddrOp ) . isExpr ( ) ) {


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; if ( MFI . hasCalls ( ) && MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; if ( MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) || MFI . hasStackMap ( ) || MFI . hasPatchPoint ( ) || RegInfo -> needsStackRealignment ( MF ) ) return true ; if ( ! MFI . isMaxCallFrameSizeComputed ( ) || MFI . getMaxCallFrameSize ( ) > DefaultSafeSPDisplacement ) return true ; return false ;


return isRegKind ( ) && ! Reg . Mods . hasModifiers ( ) ;


<s> _mm_cvt_roundsh_u64 ( __m128h __A , const int __R ) { return ( long long ) __builtin_ia32_vcvtsh2usi64_round ( __A , __R ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerFNEG ( SDValue Op , SelectionDAG & DAG ) const { LLVMContext * Context = DAG . getContext ( ) ; SDLoc dl ( Op ) ; MVT VT = Op . getValueType ( ) . getSimpleVT ( ) ; MVT EltVT = VT ; unsigned NumElts = VT == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; if ( VT . isVector ( ) ) { EltVT = VT . getVectorElementType ( ) ; NumElts = VT . getVectorNumElements ( ) ; } Constant * C ; if ( EltVT == <STR_LIT> ) C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEdouble , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; else C = ConstantFP :: get ( * Context , APFloat ( APFloat :: IEEEsingle , APInt ( <NUM_LIT> , <NUM_LIT> << <NUM_LIT> ) ) ) ; C = ConstantVector :: getSplat ( NumElts , C ) ; SDValue CPIdx = DAG . getConstantPool ( C , getPointerTy ( ) ) ; unsigned Alignment = cast < ConstantPoolSDNode > ( CPIdx ) -> getAlignment ( ) ; SDValue Mask = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , CPIdx , MachinePointerInfo :: getConstantPool ( ) , false , false , false , Alignment ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCONCAT_VECTORS ( SDValue Op , SelectionDAG & DAG ) const { SDNode * Node = Op . getNode ( ) ; SDLoc dl ( Node ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; unsigned NumOperands = Node -> getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> ; i < NumOperands ; ++ i ) {

SDValue SubOp = Node -> getOperand ( i ) ;


<s> const InstrItineraryData * getInstrItineraryData ( ) const override { return & InstrItins ;


<s> static void nvptx_end_call_args ( void ) {

cfun -> machine -> start_call = NULL_RTX ;


<s> CombinerHelper Helper ( Observer , B , KB , MDT ) ; if ( Generated . tryCombineAll ( Observer , MI , B , Helper ) ) return true ; switch ( MI . getOpcode ( ) ) { case TargetOpcode :: G_CONCAT_VECTORS : return Helper . tryCombineConcatVectors ( MI ) ; case TargetOpcode :: G_SHUFFLE_VECTOR : return Helper . tryCombineShuffleVector ( MI ) ;


<s> if ( isStringOfOnes ( Mask , LSB , Length ) ) { Start = <NUM_LIT> - ( LSB + Length - <NUM_LIT> ) ; End = <NUM_LIT> - LSB ; return true ; } if ( isStringOfOnes ( Mask ^ Used , LSB , Length ) ) { assert ( LSB > <NUM_LIT> && <STR_LIT> ) ; assert ( LSB + Length < BitSize && <STR_LIT> ) ; Start = <NUM_LIT> - ( LSB - <NUM_LIT> ) ; End = <NUM_LIT> - ( LSB + Length ) ; return true ; } return false ;


<s> bool <ISA_LIT>RemoveRedundancyVSETVL :: removeRedundancy ( ) { if ( ! redundancyVSETVLI . size ( ) ) return false ;

for ( MachineInstr * instr : redundancyVSETVLI ) {


<s> unsigned NumElts = VT . getVectorNumElements ( ) ; if ( NumElts == <NUM_LIT> ) return true ; if ( NumElts == <NUM_LIT> && VT . is128BitVector ( ) ) { return ( isMOVLMask ( Mask , VT ) || isCommutedMOVLMask ( Mask , VT , true ) || isSHUFPMask ( Mask , VT , Subtarget -> hasFp256 ( ) ) || isSHUFPMask ( Mask , VT , Subtarget -> hasFp256 ( ) , true ) ) ;


<s> Value * <ISA_LIT>IREmitter :: visitCMOV ( const SDNode * N ) {

llvm_unreachable ( <STR_LIT> ) ; return NULL ;


<s> unsigned Src = I -> getOperand ( <NUM_LIT> ) . getReg ( ) , FI = I -> getOperand ( <NUM_LIT> ) . getIndex ( ) ;

BuildMI ( MBB , I , I -> getDebugLoc ( ) , TII . get ( TargetOpcode :: COPY ) , VR ) . addReg ( Src , getKillRegState ( I -> getOperand ( <NUM_LIT> ) . isKill ( ) ) ) ;


return __builtin_mve_vcvtq_m_to_f_sv8hf ( __arm_vuninitializedq_f16 ( ) , __a , __p ) ;


<s> vmlaq_s16 ( int16x8_t a , int16x8_t b , int16x8_t c ) {


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( ) {


<s> bool EvaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const override { return false ;


<s> BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( CmpOpc ) ) . addReg ( regX ) . addImm ( imm ) ; BuildMI ( * BB , MI , MI . getDebugLoc ( ) , TII -> get ( BtOpc ) ) . addMBB ( target ) ; MI . eraseFromParent ( ) ; return BB ;


<s> <ISA_LIT>ELFObjectWriter :: ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> if ( RC == <STR_LIT> || ( TargetRegisterInfo :: isPhysicalRegister ( DestReg ) && is<ISA_LIT>LowRegister ( DestReg ) ) ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( PseudoSourceValue :: getFixedStack ( FI ) , MachineMemOperand :: MOLoad , <NUM_LIT> , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ;

AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Module & M , const std :: string & FS ) : DataLayout ( <STR_LIT> ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , JITInfo ( * this ) , Subtarget ( M , FS ) , TLInfo ( * this ) {


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : NeedDisjointWriteback = true ; WritebackReg = Inst . getOperand ( <NUM_LIT> ) . getReg ( ) ; break ; } if ( Val == <NUM_LIT> ) return MCDisassembler :: Fail ; for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; ++ i ) { if ( Val & ( <NUM_LIT> << i ) ) { if ( ! Check ( S , DecodeGPRRegisterClass ( Inst , i , Address , Decoder ) ) ) return MCDisassembler :: Fail ; if ( NeedDisjointWriteback && WritebackReg == Inst . end ( ) [ - <NUM_LIT> ] . getReg ( ) ) Check ( S , MCDisassembler :: SoftFail ) ; } }


<s> const MachineOperand * BaseOp ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , OffsetIsScalable , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ;


<s> Value * <ISA_LIT>IREmitter :: visitVPERMV ( const SDNode * N ) {


<s> const <ISA_LIT>Subtarget & SubTarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; Metadata * isCFProtectionSupported = MF . getMMI ( ) . getModule ( ) -> getModuleFlag ( <STR_LIT> ) ; const <ISA_LIT>TargetMachine * TM = static_cast < const <ISA_LIT>TargetMachine * > ( & MF . getTarget ( ) ) ; bool isJITwithCET = TM -> isJIT ( ) ; bool isJITwithCET = false ; if ( ! isCFProtectionSupported && ! IndirectBranchTracking && ! isJITwithCET ) return false ; bool Changed = false ; TII = SubTarget . getInstrInfo ( ) ; EndbrOpcode = SubTarget . is64Bit ( ) ? <STR_LIT> : <STR_LIT> ; if ( ( TM -> getCodeModel ( ) == CodeModel :: Large || MF . getFunction ( ) . hasAddressTaken ( ) || ! MF . getFunction ( ) . hasLocalLinkage ( ) ) && ! MF . getFunction ( ) . doesNoCfCheck ( ) ) { auto MBB = MF . begin ( ) ; Changed |= addENDBR ( * MBB , MBB -> begin ( ) ) ; } for ( auto & MBB : MF ) { if ( MBB . hasAddressTaken ( ) ) Changed |= addENDBR ( MBB , MBB . begin ( ) ) ; for ( MachineBasicBlock :: iterator I = MBB . begin ( ) ; I != MBB . end ( ) ; ++ I ) { if ( I -> isCall ( ) && IsCallReturnTwice ( I -> getOperand ( <NUM_LIT> ) ) ) Changed |= addENDBR ( MBB , std :: next ( I ) ) ; } if ( TM -> Options . ExceptionModel == ExceptionHandling :: SjLj ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef GPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , GPU , FS ) , TargetTriple ( TT ) , Gen ( TT . getArch ( ) == Triple :: amdgcn ? SOUTHERN_ISLANDS : <ISA_LIT> ) , IsaVersion ( ISAVersion0_0_0 ) , WavefrontSize ( <NUM_LIT> ) , LocalMemorySize ( <NUM_LIT> ) , LDSBankCount ( <NUM_LIT> ) , MaxPrivateElementSize ( <NUM_LIT> ) , FastFMAF32 ( false ) , HalfRate64Ops ( false ) , FP32Denormals ( false ) , FP64FP16Denormals ( false ) , FPExceptions ( false ) , FlatForGlobal ( false ) , UnalignedScratchAccess ( false ) , UnalignedBufferAccess ( false ) , EnableXNACK ( false ) , DebuggerInsertNops ( false ) , DebuggerReserveRegs ( false ) , DebuggerEmitPrologue ( false ) , EnableVGPRSpilling ( false ) , EnablePromoteAlloca ( false ) , EnableLoadStoreOpt ( false ) , EnableUnsafeDSOffsetFolding ( false ) , Enable<ISA_LIT>Scheduler ( false ) , DumpCode ( false ) , FP64 ( false ) , IsGCN ( false ) , GCN1Encoding ( false ) , GCN3Encoding ( false ) , CIInsts ( false ) , SGPRInitBug ( false ) , HasSMemRealTime ( false ) , Has16BitInsts ( false ) , HasMovrel ( false ) , HasVGPRIndexMode ( false ) , HasScalarStores ( false ) , HasInv2PiInlineImm ( false ) , HasSDWA ( false ) , HasDPP ( false ) , FlatAddressSpace ( false ) , <ISA_LIT>ALUInst ( false ) , CaymanISA ( false ) , CFALUBug ( false ) , HasVertexCache ( false ) , TexVTXClauseSize ( <NUM_LIT> ) , ScalarizeGlobal ( false ) , FeatureDisable ( false ) , InstrItins ( getInstrItineraryForCPU ( GPU ) ) { initializeSubtargetDependencies ( TT , GPU , FS ) ;


<s> unsigned asB = LocB . Ptr -> getType ( ) -> getPointerAddressSpace ( ) ; AliasResult Result = getAliasResult ( asA , asB ) ;

if ( Result == NoAlias ) return Result ;


<s> case <STR_LIT> : opc = <STR_LIT> ; break ; default : ; } if ( opc ) { DEBUG ( dbgs ( ) << <STR_LIT> << MI ) ; MI . setDesc ( TII -> get ( opc ) ) ; Rewritten ++ ; return true ;


<s> if ( Ty -> isFP128Ty ( ) ) return true ;

if ( Ty -> isStructTy ( ) && Ty -> getStructNumElements ( ) == <NUM_LIT> && Ty -> getStructElementType ( <NUM_LIT> ) -> isFP128Ty ( ) ) return true ;


<s> <ISA_LIT>AsmParser :: OperandMatchResultTy <ISA_LIT>AsmParser :: parseJumpTarget ( OperandVector & Operands ) { MCAsmParser & Parser = getParser ( ) ; DEBUG ( dbgs ( ) << <STR_LIT> ) ; SMLoc S = getLexer ( ) . getLoc ( ) ; OperandMatchResultTy ResTy = parseImm ( Operands ) ; if ( ResTy != MatchOperand_NoMatch ) return ResTy ; ResTy = parseAnyRegister ( Operands ) ;


<s> DecodeStatus Result = readInstruction32 ( Region , Address , Size , Insn , isBigEndian ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decode<ISA_LIT>64Instruction32 ( instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { Size = <NUM_LIT> ; return Result ; }

Result = decode<ISA_LIT>Instruction32 ( instr , Insn , Address , this , STI ) ;


<s> REG_POINTER ( cfun -> machine -> split_stack_arg_pointer ) = <NUM_LIT> ; pat = gen_rtx_SET ( cfun -> machine -> split_stack_arg_pointer , gen_rtx_REG ( Pmode , <NUM_LIT> ) ) ; push_topmost_sequence ( ) ; emit_insn_after ( pat , get_insns ( ) ) ; pop_topmost_sequence ( ) ;


<s> case 'c' : return make_vector < unsigned > ( I0 , I1 , I2 , I3 , B0 , B1 , B2 , B3 , L0 , L1 , L2 , L3 , <NUM_LIT> ) ; case 't' : return make_vector < unsigned > ( LT0 , LT1 , <NUM_LIT> ) ; case 'u' : return make_vector < unsigned > ( LB0 , LB1 , <NUM_LIT> ) ; case 'k' : return make_vector < unsigned > ( LC0 , LC1 , <NUM_LIT> ) ;

case 'y' : return make_vector < unsigned > ( RETS , RETN , RETI , RETX , RETE , ASTAT , SEQSTAT , USP , <NUM_LIT> ) ;


<s> LoadInp1 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Opr1 ) ; LoadInp2 = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Opr2 ) ; if ( isa < ConstantSDNode > ( LoadInp1 . getNode ( ) ) ) LoadInp1 = LoadOperand ( DAG , DL , <STR_LIT> , LoadInp1 ) ; if ( isa < ConstantSDNode > ( LoadInp2 . getNode ( ) ) ) LoadInp2 = LoadOperand ( DAG , DL , <STR_LIT> , LoadInp2 ) ;

BinOp = DAG . getNode ( LowerBinOp , DL , <STR_LIT> , { LoadInp1 , LoadInp2 } ) ;


<s> case 'l' : return C_RegisterClass ; case 'w' : return C_RegisterClass ; case 'h' : return C_RegisterClass ; case 'x' : return C_RegisterClass ; case 't' : return C_RegisterClass ; case 'j' : return C_Other ; case 'Q' : return C_Memory ;


<s> for ( register_cache_type :: iterator mem_operand = register_cache . begin ( ) ; mem_operand != register_cache . end ( ) ; mem_operand ++ ) { int base_register = std :: get < <NUM_LIT> > ( * mem_operand ) ;

int index_register = std :: get < <NUM_LIT> > ( * mem_operand ) ;


<s> Optional < ValueAndVReg > MaybeOffset = getConstantVRegValWithLookThrough ( RHS . getReg ( ) , MRI , true ) ; if ( ! MaybeOffset ) return { Root , <NUM_LIT> } ; return { RootI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MaybeOffset -> Value } ;


<s> const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , MCSymbolRefExpr :: VK_None , getContext ( ) ) ; Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( <NUM_LIT> , getContext ( ) ) , getContext ( ) ) ;

return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: MEK_DTPREL , Expr , getContext ( ) ) ;


<s> YamlIO . mapOptional ( <STR_LIT> , MFI . MemoryBound , false ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . WaveLimiter , false ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . ScratchRSrcReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . ScratchWaveOffsetReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . FrameOffsetReg , StringValue ( <STR_LIT> ) ) ; YamlIO . mapOptional ( <STR_LIT> , MFI . StackPtrOffsetReg , StringValue ( <STR_LIT> ) ) ;

YamlIO . mapOptional ( <STR_LIT> , MFI . ArgInfo ) ;


<s> if ( label != <NUM_LIT> ) { targetm . asm_out . internal_label ( asm_out_file , <STR_LIT> , CODE_LABEL_NUMBER ( label ) ) ; asm_fprintf ( asm_out_file , <STR_LIT> , regno ) ; }


<s> static bool BBHasFallthrough ( MachineBasicBlock * MBB ) { MachineFunction :: iterator MBBI = MBB ;

if ( llvm :: next ( MBBI ) == MBB -> getParent ( ) -> end ( ) ) return false ;


<s> <ISA_LIT>elTargetMachine :: <ISA_LIT>elTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Reloc :: Model RM , CodeModel :: Model CM , CodeGenOpt :: Level OL ) : <ISA_LIT>TargetMachine ( T , TT , CPU , FS , Options , RM , CM , OL , true ) {


<s> unsigned Opcode = Op -> getOpcode ( ) ; assert ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && <STR_LIT> ) ; bool IsSigned = ( Opcode == <STR_LIT> ) ; EVT VT = Op -> getValueType ( <NUM_LIT> ) ; Type * Ty = VT . getTypeForEVT ( * DAG . getContext ( ) ) ; RTLIB :: Libcall LC ; switch ( VT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I8 : RTLIB :: UDIVREM_I8 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I16 : RTLIB :: UDIVREM_I16 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I32 : RTLIB :: UDIVREM_I32 ; break ; } SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( SDValue const & Value : Op -> op_values ( ) ) { Entry . Node = Value ; Entry . Ty = Value . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ;


<s> const <ISA_LIT>InstrInfo & TII = * TM . getInstrInfo ( ) ; const <ISA_LIT>RegisterInfo & RegInfo = * TM . getRegisterInfo ( ) ; unsigned StackPtr = RegInfo . getStackRegister ( ) ; bool reseveCallFrame = hasReservedCallFrame ( MF ) ; int Opcode = I -> getOpcode ( ) ; bool isDestroy = Opcode == TII . getCallFrameDestroyOpcode ( ) ; bool IsLP64 = STI . isTarget64BitLP64 ( ) ; DebugLoc DL = I -> getDebugLoc ( ) ; uint64_t Amount = ! reseveCallFrame ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; uint64_t CalleeAmt = isDestroy ? I -> getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; I = MBB . erase ( I ) ; if ( ! reseveCallFrame ) { if ( Amount == <NUM_LIT> ) return ;

unsigned StackAlign = TM . getFrameLowering ( ) -> getStackAlignment ( ) ;


<s> Count /= <NUM_LIT> ; for ( uint64_t i = <NUM_LIT> ; i != Count ; ++ i ) OW -> write32 ( <NUM_LIT> ) ; return true ;


<s> return isImm ( - <NUM_LIT> , <NUM_LIT> ) ;


<s> if ( ConditionVT . getSizeInBits ( ) < <NUM_LIT> ) return <STR_LIT> ;

return TargetLoweringBase :: getPreferredSwitchConditionType ( Context , ConditionVT ) ;


<s> static DecodeStatus decodePC24DBLBranchOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const MCDisassembler * Decoder ) {

return decodePCDBLOperand < <NUM_LIT> > ( Inst , Imm , Address , true , Decoder ) ;


<s> unsigned GlobalBaseReg = MF -> getInfo < <ISA_LIT>FunctionInfo > ( ) -> getGlobalBaseReg ( ) ; return CurDAG -> getRegister ( GlobalBaseReg , TLI . getPointerTy ( ) ) . getNode ( ) ;


<s> if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ; else BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( TBB ) ; } else BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) ; return <NUM_LIT> ; } BuildMI ( & MBB , DL , get ( BccOpc ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) . addOperand ( Cond [ <NUM_LIT> ] ) ;

if ( isThumb ) BuildMI ( & MBB , DL , get ( BOpc ) ) . addMBB ( FBB ) . addImm ( <STR_LIT> ) . addReg ( <NUM_LIT> ) ;


<s> MachineLocation Src ( FPReg , <NUM_LIT> ) ; Moves . push_back ( MachineMove ( <NUM_LIT> , Dst , Src ) ) ;


<s> <ISA_LIT>AS get<ISA_LIT>AS ( ) const {


<s> PrintLaneMaskOpt ( LaneBitmask M ) : Mask ( M ) {


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; if ( TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . isV9 ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> const <ISA_LIT>RegisterInfo * TRI = ST . getRegisterInfo ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! FuncInfo -> isEntryFunction ( ) ) { FuncInfo -> allocateWWMReservedSpillSlots ( MFI , * TRI ) ; } const bool SpillVGPRToAGPR = ST . hasMAIInsts ( ) && FuncInfo -> hasSpilledVGPRs ( ) && EnableSpillVGPRToAGPR ; if ( SpillVGPRToAGPR ) { BitVector SpillFIs ( MFI . getObjectIndexEnd ( ) , false ) ; BitVector NonVGPRSpillFIs ( MFI . getObjectIndexEnd ( ) , false ) ; bool SeenDbgInstr = false ; for ( MachineBasicBlock & MBB : MF ) { for ( MachineInstr & MI : llvm :: make_early_inc_range ( MBB ) ) { int FrameIndex ; if ( MI . isDebugInstr ( ) ) SeenDbgInstr = true ; if ( TII -> isVGPRSpill ( MI ) ) { unsigned FIOp = <STR_LIT> ( MI . getOpcode ( ) , <STR_LIT> :: vaddr ) ; int FI = MI . getOperand ( FIOp ) . getIndex ( ) ; Register VReg = TII -> getNamedOperand ( MI , <STR_LIT> :: vdata ) -> getReg ( ) ; if ( FuncInfo -> allocateVGPRSpillToAGPR ( MF , FI , TRI -> isAGPR ( MRI , VReg ) ) ) { RS -> enterBasicBlock ( MBB ) ; TRI -> eliminateFrameIndex ( MI , <NUM_LIT> , FIOp , RS ) ; SpillFIs . set ( FI ) ; continue ; } } else if ( TII -> isStoreToStackSlot ( MI , FrameIndex ) || TII -> isLoadFromStackSlot ( MI , FrameIndex ) ) if ( ! MFI . isFixedObjectIndex ( FrameIndex ) ) NonVGPRSpillFIs . set ( FrameIndex ) ; } } for ( unsigned FI : SpillFIs . set_bits ( ) ) if ( ! NonVGPRSpillFIs . test ( FI ) ) FuncInfo -> setVGPRToAGPRSpillDead ( FI ) ; for ( MachineBasicBlock & MBB : MF ) { for ( MCPhysReg Reg : FuncInfo -> getVGPRSpillAGPRs ( ) ) MBB . addLiveIn ( Reg ) ; for ( MCPhysReg Reg : FuncInfo -> getAGPRSpillVGPRs ( ) ) MBB . addLiveIn ( Reg ) ; MBB . sortUniqueLiveIns ( ) ; if ( ! SpillFIs . empty ( ) && SeenDbgInstr ) { for ( MachineInstr & MI : MBB ) { if ( MI . isDebugValue ( ) && MI . getOperand ( <NUM_LIT> ) . isFI ( ) && SpillFIs [ MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ] ) { MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( Register ( ) , false ) ; } } } } } bool HaveSGPRToVMemSpill = FuncInfo -> removeDeadFrameIndices ( MFI , true ) ; assert ( allSGPRSpillsAreDead ( MF ) && <STR_LIT> ) ;

if ( ! allStackObjectsAreDead ( MFI ) ) {


<s> case MachineOperand :: MO_ExternalSymbol : MCO = GetSymbolRef ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP ) ; break ; case MachineOperand :: MO_BlockAddress : MCO = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP ) ; break ; }


<s> ExternalSymbolSDNode * ES = dyn_cast < ExternalSymbolSDNode > ( SDValue ( N , <NUM_LIT> ) ) ; DebugLoc dl = ES -> getDebugLoc ( ) ; SDValue TES = DAG . getTargetExternalSymbol ( ES -> getSymbol ( ) , <STR_LIT> ) ;

SDValue Offset = DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ;


<s> unsigned <ISA_LIT>RegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {

const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;


<s> void <ISA_LIT>MCInstLower :: Initialize ( MCContext * C ) { Ctx = C ;


<s> assert ( ( Count % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; OW -> WriteZeros ( Count ) ; return true ;


<s> bool llvm :: isKernelFunction ( const Function & F ) { unsigned x = <NUM_LIT> ; bool retval = llvm :: findOneNVVMAnnotation ( & F , llvm :: PropertyAnnotationNames [ llvm :: PROPERTY_ISKERNEL_FUNCTION ] , x ) ; if ( retval == false ) { if ( F . getCallingConv ( ) == llvm :: CallingConv :: PTX_Kernel ) return true ;


<s> assert ( ( TargetPos >= <NUM_LIT> ) && MI -> getOperand ( TargetPos ) . isMBB ( ) ) ; MI -> getOperand ( TargetPos ) . setMBB ( NewTarget ) ; if ( EnableBranchPrediction && isPredicatedNew ( MI ) ) { NewOpcode = reversePrediction ( NewOpcode ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; NewMI -> dump ( ) ; ) ; MFI -> erase ( MBI ) ; MachineBasicBlock :: iterator J = static_cast < MachineBasicBlock :: iterator > ( NewMI ) ;


<s> break ; case <NUM_LIT> : append_name ( <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; }


<s> const char * prefix = gen_prefix ( decl ) ; if ( prefix == NULL ) { if ( TREE_CODE ( decl ) == FUNCTION_DECL ) return text_section ; else if ( has_attr ( ATTR_NOINIT , decl ) ) return noinit_section ; else if ( has_attr ( ATTR_PERSIST , decl ) ) return persist_section ; else return default_select_section ( decl , reloc , align ) ; } const char * sec ; switch ( categorize_decl_for_section ( decl , reloc ) ) { case SECCAT_TEXT : sec = <STR_LIT> ; break ; case SECCAT_DATA : sec = <STR_LIT> ; break ; case SECCAT_BSS : sec = <STR_LIT> ; break ; case SECCAT_RODATA : sec = <STR_LIT> ; break ; case SECCAT_RODATA_MERGE_STR : case SECCAT_RODATA_MERGE_STR_INIT : case SECCAT_RODATA_MERGE_CONST : case SECCAT_SRODATA : case SECCAT_DATA_REL : case SECCAT_DATA_REL_LOCAL : case SECCAT_DATA_REL_RO : case SECCAT_DATA_REL_RO_LOCAL : case SECCAT_SDATA : case SECCAT_SBSS : case SECCAT_TDATA : case SECCAT_TBSS : return default_select_section ( decl , reloc , align ) ; default : gcc_unreachable ( ) ; } const char * dec_name = DECL_SECTION_NAME ( decl ) ;

char * name = ACONCAT ( ( prefix , sec , dec_name , NULL ) ) ;


<s> if ( MI -> isPseudo ( ) ) llvm_unreachable ( <STR_LIT> ) ; MCInst TmpInst0 ;

MCInstLowering . lower ( MI , TmpInst0 ) ;


<s> unsigned Reg = IntRegDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: CreateReg ( Reg ) ) ; return MCDisassembler :: Success ;


<s> MachineInstr * <ISA_LIT>InstructionSelector :: emitADD ( Register DefReg , MachineOperand & LHS , MachineOperand & RHS , MachineIRBuilder & MIRBuilder ) const { const std :: array < std :: array < unsigned , <NUM_LIT> > , <NUM_LIT> > OpcTable {

{ { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } , { <STR_LIT> , <STR_LIT> } } } ;


<s> static void set_pic_reg_ever_live ( ) {

if ( reload_in_progress ) df_set_regs_ever_live ( REGNO ( pic_offset_table_rtx ) , true ) ;


PM . addPass ( createCGSCCToFunctionPassAdaptor ( std :: move ( FPM ) ) ) ;


<s> unsigned CPI = Orig . getOperand ( <NUM_LIT> ) . getIndex ( ) ; unsigned PCLabelId = duplicateCPV ( MF , CPI ) ; Orig . getOperand ( <NUM_LIT> ) . setIndex ( CPI ) ; Orig . getOperand ( <NUM_LIT> ) . setImm ( PCLabelId ) ;


<s> unsigned char Emitter < CodeEmitter > :: getVEXRegisterEncoding ( const MachineInstr & MI , unsigned OpNum ) const { unsigned SrcReg = MI . getOperand ( OpNum ) . getReg ( ) ; unsigned SrcRegNum = get<ISA_LIT>RegNum ( MI . getOperand ( OpNum ) . getReg ( ) ) ; if ( <STR_LIT> ( SrcReg ) ) SrcRegNum |= <NUM_LIT> ; return ( ~ SrcRegNum ) & <NUM_LIT> ;


<s> continue ; } if ( JUMP_P ( insn ) ) { rtx_jump_table_data * table ; if ( tablejump_p ( insn , NULL , & table ) ) { rtvec vec = table -> get_labels ( ) ; int j ; rtx_insn * label ; for ( j = GET_NUM_ELEM ( vec ) - <NUM_LIT> ; j >= <NUM_LIT> ; -- j ) { label = as_a < rtx_insn * > ( XEXP ( RTVEC_ELT ( vec , j ) , <NUM_LIT> ) ) ; bti_insn = gen_bti_j ( ) ; emit_insn_after ( bti_insn , label ) ;


<s> if ( ! Is64Bit ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } } if ( ! Is64Bit || ! TM . getSubtarget < <ISA_LIT>Subtarget > ( ) . hasAVX512 ( ) ) { for ( unsigned n = <NUM_LIT> ; n != <NUM_LIT> ; ++ n ) { for ( MCRegAliasIterator AI ( <STR_LIT> + n , this , true ) ; AI . isValid ( ) ; ++ AI ) Reserved . set ( * AI ) ; } }


<s> <ISA_LIT>Section ( SectionVariant V , SectionKind K ) : MCSection ( V , K ) {


<s> fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits ) ; fprintf ( file , <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) ; fprintf ( file , <STR_LIT> , bits , loc ) ; fprintf ( file , <STR_LIT> , bits , loc , loc ) ; if ( cfun -> machine -> unisimt_predicate ) { int master = REGNO ( cfun -> machine -> unisimt_master ) ; int pred = REGNO ( cfun -> machine -> unisimt_predicate ) ; fprintf ( file , <STR_LIT> , master , loc ) ; if ( cfun -> machine -> unisimt_outside_simt_predicate ) { int pred_outside_simt = REGNO ( cfun -> machine -> unisimt_outside_simt_predicate ) ; fprintf ( file , <STR_LIT> , pred_outside_simt , master ) ; }


<s> static void emitPostSt ( MachineBasicBlock * BB , MachineInstr * Pos , const TargetInstrInfo * TII , const DebugLoc & dl , unsigned StSize , unsigned Data , unsigned AddrIn , unsigned AddrOut , bool IsThumb1 , bool IsThumb2 ) { unsigned StOpc = getStOpcode ( StSize , IsThumb1 , IsThumb2 ) ; assert ( StOpc != <NUM_LIT> && <STR_LIT> ) ; if ( StSize >= <NUM_LIT> ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) , AddrOut ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) . addReg ( Data ) ) ; } else if ( IsThumb1 ) { AddDefaultPred ( BuildMI ( * BB , Pos , dl , TII -> get ( StOpc ) ) . addReg ( Data ) . addReg ( AddrIn ) . addImm ( <NUM_LIT> ) ) ; MachineInstrBuilder MIB = BuildMI ( * BB , Pos , dl , TII -> get ( <STR_LIT> ) , AddrOut ) ;


<s> } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( ( uint32_t ) ( C - <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != <NUM_LIT> && isLegalArithImmed ( C - <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C - <NUM_LIT> ) : C - <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != INT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != INT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ; case <STR_LIT> : case <STR_LIT> : if ( ( VT == <STR_LIT> && C != UINT32_MAX && isLegalArithImmed ( ( uint32_t ) ( C + <NUM_LIT> ) ) ) || ( VT == <STR_LIT> && C != UINT64_MAX && isLegalArithImmed ( C + <NUM_LIT> ) ) ) { CC = ( CC == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; C = ( VT == <STR_LIT> ) ? ( uint32_t ) ( C + <NUM_LIT> ) : C + <NUM_LIT> ; RHS = DAG . getConstant ( C , dl , VT ) ; } break ;


<s> <ISA_LIT>CodeEmitter ( TargetMachine & tm , JITCodeEmitter & mce ) : MachineFunctionPass ( ID ) , JTI ( <NUM_LIT> ) , II ( ( const <ISA_LIT>BaseInstrInfo * ) tm . getInstrInfo ( ) ) , TD ( tm . getTargetData ( ) ) , TM ( tm ) , MCE ( mce ) , MCPEs ( <NUM_LIT> ) , MJTEs ( <NUM_LIT> ) , IsPIC ( TM . getRelocationModel ( ) == Reloc :: PIC_ ) , IsThumb ( false ) {


<s> if ( X != LHS . getOperand ( <NUM_LIT> ) ) return SDValue ( ) ; if ( RCC == <STR_LIT> ) { const ConstantFPSDNode * C1 = dyn_cast < ConstantFPSDNode > ( RHS . getOperand ( <NUM_LIT> ) ) ; if ( ! C1 || ! C1 -> isInfinity ( ) || C1 -> isNegative ( ) ) return SDValue ( ) ; const uint32_t Mask = <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ; static_assert ( ( ( ~ ( <STR_LIT> | <STR_LIT> | <STR_LIT> | <STR_LIT> ) ) & <NUM_LIT> ) == Mask , <STR_LIT> ) ; SDLoc DL ( N ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , X , DAG . getConstant ( Mask , DL , <STR_LIT> ) ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AllocateStack ( ArgsPreserved , <NUM_LIT> ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; if ( VA . isRegLoc ( ) ) { unsigned VReg = MF . addLiveIn ( VA . getLocReg ( ) , getRegClassFor ( VA . getLocVT ( ) ) ) ; SDValue Arg = DAG . getCopyFromReg ( Chain , DL , VReg , VA . getLocVT ( ) ) ; if ( VA . getValVT ( ) == <STR_LIT> && VA . needsCustom ( ) ) Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , Arg , DAG . getValueType ( VA . getValVT ( ) ) ) ; break ;


<s> in_section = NULL ; cfun -> machine -> in_nsubspa = <NUM_LIT> ; } if ( cfun -> is_thunk ) return ; if ( INSN_ADDRESSES_SET_P ( ) ) { last_address = extra_nop ? <NUM_LIT> : <NUM_LIT> ; insn = get_last_nonnote_insn ( ) ; if ( insn ) { last_address += INSN_ADDRESSES ( INSN_UID ( insn ) ) ; if ( INSN_P ( insn ) ) last_address += insn_default_length ( insn ) ; } last_address = ( ( last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - <NUM_LIT> ) & ~ ( FUNCTION_BOUNDARY / BITS_PER_UNIT - <NUM_LIT> ) ) ; } else last_address = UINT_MAX ; update_total_code_bytes ( last_address ) ;


<s> TargetPassConfig * GCNTargetMachine :: createPassConfig ( PassManagerBase & PM ) {

return new GCNPassConfig ( * this , PM ) ;


<s> return TargetTransformInfo ( <ISA_LIT>TTIImpl ( this , F ) ) ;


<s> LLT ValTy = MRI -> getType ( ValReg ) ; unsigned VecSize = VecTy . getSizeInBits ( ) ; unsigned ValSize = ValTy . getSizeInBits ( ) ; const RegisterBank * VecRB = RBI . getRegBank ( VecReg , * MRI , TRI ) ; const RegisterBank * ValRB = RBI . getRegBank ( ValReg , * MRI , TRI ) ; const RegisterBank * IdxRB = RBI . getRegBank ( IdxReg , * MRI , TRI ) ; assert ( VecTy . getElementType ( ) == ValTy ) ; if ( IdxRB -> getID ( ) != <STR_LIT> ) return false ; const TargetRegisterClass * VecRC = TRI . getRegClassForTypeOnBank ( VecTy , * VecRB , * MRI ) ; const TargetRegisterClass * ValRC = TRI . getRegClassForTypeOnBank ( ValTy , * ValRB , * MRI ) ; if ( ! RBI . constrainGenericRegister ( VecReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( DstReg , * VecRC , * MRI ) || ! RBI . constrainGenericRegister ( ValReg , * ValRC , * MRI ) || ! RBI . constrainGenericRegister ( IdxReg , <STR_LIT> , * MRI ) ) return false ; if ( VecRB -> getID ( ) == <STR_LIT> && ValSize != <NUM_LIT> ) return false ; unsigned SubReg ; std :: tie ( IdxReg , SubReg ) = computeIndirectRegIndex ( * MRI , TRI , VecRC , IdxReg , ValSize / <NUM_LIT> ) ; const bool IndexMode = VecRB -> getID ( ) == <STR_LIT> && STI . useVGPRIndexMode ( ) ; MachineBasicBlock * BB = MI . getParent ( ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; if ( IndexMode ) { BuildMI ( * BB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( IdxReg ) . addImm ( <STR_LIT> :: DST_ENABLE ) ; } else {

BuildMI ( * BB , & MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( IdxReg ) ;


<s> if ( unsigned Reg = State . AllocateReg ( <STR_LIT> ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } static const MCPhysReg RegList1 [ ] = { <STR_LIT> , <STR_LIT> } ; static const MCPhysReg RegList2 [ ] = { <STR_LIT> , <STR_LIT> } ; if ( unsigned Reg = State . AllocateReg ( RegList1 , RegList2 ) ) { State . addLoc ( CCValAssign :: getReg ( ValNo , ValVT , Reg , LocVT , LocInfo ) ) ; return false ; } unsigned Offset = State . AllocateStack ( <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) ; State . addLoc ( CCValAssign :: getMem ( ValNo , ValVT , Offset , LocVT , LocInfo ) ) ;


<s> LEONMachineFunctionPass :: LEONMachineFunctionPass ( char & ID ) : MachineFunctionPass ( ID ) {


<s> int64_t MulAmt = C -> getSExtValue ( ) ; unsigned ShiftAmt = CountTrailingZeros_64 ( MulAmt ) ; ShiftAmt = ShiftAmt & ( <NUM_LIT> - <NUM_LIT> ) ; SDValue V = N -> getOperand ( <NUM_LIT> ) ; DebugLoc DL = N -> getDebugLoc ( ) ; SDValue Res ; MulAmt >>= ShiftAmt ; if ( MulAmt >= <NUM_LIT> ) { if ( isPowerOf2_32 ( MulAmt - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt - <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmt + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmt + <NUM_LIT> ) , <STR_LIT> ) ) , V ) ; } else return SDValue ( ) ; } else { uint64_t MulAmtAbs = - MulAmt ; if ( isPowerOf2_32 ( MulAmtAbs + <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs + <NUM_LIT> ) , <STR_LIT> ) ) ) ; } else if ( isPowerOf2_32 ( MulAmtAbs - <NUM_LIT> ) ) { Res = DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getNode ( <STR_LIT> , DL , VT , V , DAG . getConstant ( Log2_32 ( MulAmtAbs - <NUM_LIT> ) , <STR_LIT> ) ) ) ; Res = DAG . getNode ( <STR_LIT> , DL , VT , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) , Res ) ; } else return SDValue ( ) ; } if ( ShiftAmt != <NUM_LIT> ) Res = DAG . getNode ( <STR_LIT> , DL , VT , Res , DAG . getConstant ( ShiftAmt , <STR_LIT> ) ) ;


<s> int xstormy16_epilogue_uses ( int regno ) { if ( reload_completed && call_used_or_fixed_reg_p ( regno ) ) { const int ifun = xstormy16_interrupt_function_p ( ) ; return REG_NEEDS_SAVE ( regno , ifun ) ;


<s> void <ISA_LIT>TargetLowering :: initVPUActions ( ) {


<s> assert ( isMatchingStore ( LoadInst , StoreInst ) && <STR_LIT> ) ; int LoadSize = getMemScale ( LoadInst ) ; int StoreSize = getMemScale ( StoreInst ) ; int UnscaledStOffset = TII -> isUnscaledLdSt ( StoreInst ) ? getLdStOffsetOp ( StoreInst ) . getImm ( ) : getLdStOffsetOp ( StoreInst ) . getImm ( ) * StoreSize ; int UnscaledLdOffset = TII -> isUnscaledLdSt ( LoadInst ) ? getLdStOffsetOp ( LoadInst ) . getImm ( ) : getLdStOffsetOp ( LoadInst ) . getImm ( ) * LoadSize ; return ( UnscaledStOffset <= UnscaledLdOffset ) && ( UnscaledLdOffset + LoadSize <= ( UnscaledStOffset + StoreSize ) ) ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> case <STR_LIT> : case <STR_LIT> : assert ( MI . getDesc ( ) . getNumOperands ( ) >= <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ;

SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( Ctx ) ;


<s> inline SDValue getI32Imm ( unsigned Imm ) {

return CurDAG -> getTargetConstant ( Imm , <STR_LIT> ) ;


return __builtin_mve_vrev64q_uv4si ( __a ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; const MCConstantExpr * MCE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; assert ( MCE && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> insn -> regBase = MODRM_REG_AX ; insn -> eaRegBase = EA_REG_AX ; break ; case <NUM_LIT> : insn -> regBase = MODRM_REG_EAX ; insn -> eaRegBase = EA_REG_EAX ; break ; case <NUM_LIT> : insn -> regBase = MODRM_REG_RAX ; insn -> eaRegBase = EA_REG_RAX ; break ; } reg |= rFromREX ( insn -> rexPrefix ) << <NUM_LIT> ; rm |= bFromREX ( insn -> rexPrefix ) << <NUM_LIT> ; evexrm = <NUM_LIT> ; if ( insn -> vectorExtensionType == TYPE_EVEX && insn -> mode == MODE_64BIT ) { reg |= r2FromEVEX2of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ; evexrm = xFromEVEX2of4 ( insn -> vectorExtensionPrefix [ <NUM_LIT> ] ) << <NUM_LIT> ; } insn -> reg = ( Reg ) ( insn -> regBase + reg ) ; switch ( insn -> addressSize ) { case <NUM_LIT> : { EABase eaBaseBase = EA_BASE_BX_SI ; switch ( mod ) { case <NUM_LIT> : if ( rm == <NUM_LIT> ) { insn -> eaBase = EA_BASE_NONE ; insn -> eaDisplacement = EA_DISP_16 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; } else { insn -> eaBase = ( EABase ) ( eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_NONE ; } break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_8 ; insn -> displacementSize = <NUM_LIT> ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( eaBaseBase + rm ) ; insn -> eaDisplacement = EA_DISP_16 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = ( EABase ) ( insn -> eaRegBase + rm ) ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; } break ; } case <NUM_LIT> : case <NUM_LIT> : { EABase eaBaseBase = ( insn -> addressSize == <NUM_LIT> ? EA_BASE_EAX : EA_BASE_RAX ) ; switch ( mod ) { case <NUM_LIT> : insn -> eaDisplacement = EA_DISP_NONE ; switch ( rm & <NUM_LIT> ) { case <NUM_LIT> : insn -> eaBase = ( insn -> addressSize == <NUM_LIT> ? EA_BASE_sib : EA_BASE_sib64 ) ; if ( readSIB ( insn ) || readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; case <NUM_LIT> : insn -> eaBase = EA_BASE_NONE ; insn -> eaDisplacement = EA_DISP_32 ; if ( readDisplacement ( insn ) ) return - <NUM_LIT> ; break ; default : insn -> eaBase = ( EABase ) ( eaBaseBase + rm ) ; break ; } break ; case <NUM_LIT> :


<s> static DecodeStatus DecodeVecShiftL32Imm ( MCInst & Inst , unsigned Imm , uint64_t Addr , const MCDisassembler * Decoder ) { return DecodeVecShiftLImm ( Inst , Imm , <NUM_LIT> ) ;


<s> else return must_pass_in_stack_var_size_or_pad ( mode , type ) ;


<s> SDValue B = N -> getOperand ( <NUM_LIT> ) ; SDValue C = N -> getOperand ( <NUM_LIT> ) ; bool NegA = ( A . getOpcode ( ) == <STR_LIT> ) ; bool NegB = ( B . getOpcode ( ) == <STR_LIT> ) ; bool NegC = ( C . getOpcode ( ) == <STR_LIT> ) ; bool NegMul = ( NegA != NegB ) ; if ( NegA ) A = A . getOperand ( <NUM_LIT> ) ; if ( NegB ) B = B . getOperand ( <NUM_LIT> ) ; if ( NegC ) C = C . getOperand ( <NUM_LIT> ) ; unsigned Opcode ; if ( ! NegMul ) Opcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ; else Opcode = ( ! NegC ) ? <STR_LIT> : <STR_LIT> ;

return DAG . getNode ( Opcode , dl , VT , A , B , C ) ;


<s> UnwindOpcodeStreamer ( SmallVectorImpl < uint8_t > & V ) : Vec ( V ) , Pos ( <NUM_LIT> ) {


<s> return ( float32x2_t ) __builtin_neon_vreinterpretv2sfv8qi ( ( int8x8_t ) __a ) ;


<s> if ( Val == DoubleToBits ( - <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( <NUM_LIT> ) ) return <NUM_LIT> ; if ( Val == DoubleToBits ( - <NUM_LIT> ) ) return <NUM_LIT> ;


<s> static void mapping ( IO & YamlIO , <ISA_LIT>MachineFunctionInfo & MFI ) {

YamlIO . mapOptional ( <STR_LIT> , MFI . VarArgsFrameIndex ) ;


<s> void <ISA_LIT>AddressSanitizer :: ComputeMemOperandAddress ( <ISA_LIT>Operand & Op , <STR_LIT> VT , unsigned Reg , MCContext & Ctx , MCStreamer & Out ) { int64_t Displacement = <NUM_LIT> ; if ( IsStackReg ( Op . getMemBaseReg ( ) ) ) Displacement -= OrigSPOffset ; if ( IsStackReg ( Op . getMemIndexReg ( ) ) ) Displacement -= OrigSPOffset * Op . getMemScale ( ) ; assert ( Displacement >= <NUM_LIT> ) ; if ( Displacement == <NUM_LIT> ) { EmitLEA ( Op , VT , Reg , Out ) ; return ; } int64_t Residue ; std :: unique_ptr < <ISA_LIT>Operand > NewOp = AddDisplacement ( Op , Displacement , Ctx , & Residue ) ; EmitLEA ( * NewOp , VT , Reg , Out ) ; while ( Residue != <NUM_LIT> ) { const MCConstantExpr * Disp = MCConstantExpr :: create ( ApplyDisplacementBounds ( Residue ) , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > DispOp = <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , Reg , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ; EmitLEA ( * DispOp , VT , Reg , Out ) ;


<s> void resetTopOperands ( MachineInstr * Instr ) { assert ( hasRemainingOperands ( Instr ) && <STR_LIT> <STR_LIT> ) ;

Worklist . back ( ) = reverse ( Instr -> explicit_uses ( ) ) ;


<s> else d_add_builtin_version ( <STR_LIT> ) ; if ( mips_abi == ABI_32 ) d_add_builtin_version ( <STR_LIT> ) ; else if ( mips_abi == ABI_EABI ) d_add_builtin_version ( <STR_LIT> ) ;

else if ( mips_abi == ABI_N32 ) d_add_builtin_version ( <STR_LIT> ) ;


<s> void <ISA_LIT>LDBackend :: doCreateProgramHdrs ( Module & pModule ) {


<s> plus1 = XEXP ( address , <NUM_LIT> ) ; if ( REG_P ( plus0 ) && CONST_INT_P ( plus1 ) ) return COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; else if ( ARITHMETIC_P ( plus0 ) || ARITHMETIC_P ( plus1 ) ) return COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ; else if ( REG_P ( plus0 ) && REG_P ( plus1 ) ) return COSTS_N_INSNS ( <NUM_LIT> ) ; return COSTS_N_INSNS ( <NUM_LIT> ) ; default :


<s> addPass ( create<ISA_LIT>CollapseMOVEMPass ( ) ) ;


<s> else if ( IDVal == <STR_LIT> ) parseDirectiveInst ( Loc ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFINegateRAState ( ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveCFIBKeyFrame ( ) ; else if ( IDVal == <STR_LIT> ) parseDirectiveArchExtension ( Loc ) ; else if ( IsMachO ) { if ( IDVal == MCLOHDirectiveName ( ) ) parseDirectiveLOH ( IDVal , Loc ) ; else return true ; } else return true ;


<s> const TargetRegisterClass * TRC = MRI -> getRegClass ( RegNo ) ; for ( MVT T : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) if ( TRC -> hasType ( T ) ) return T ; DEBUG ( errs ( ) << <STR_LIT> << RegNo ) ; llvm_unreachable ( <STR_LIT> ) ;


<s> <ISA_LIT>GOT :: ~ <ISA_LIT>GOT ( ) {


<s> extern __inline __m256d __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm256_maskz_loadu_pd ( __mmask8 __U , void const * __P ) { return ( __m256d ) __builtin_ia32_loadupd256_mask ( ( const double * ) __P , ( __v4df ) _mm256_setzero_pd ( ) , ( __mmask8 ) __U ) ;


<s> MachineBasicBlock * MBB = MI -> getParent ( ) ; MachineInstrBuilder MIB = BuildMI ( * MBB , MI , MI -> getDebugLoc ( ) , TII -> get ( <STR_LIT> ) ) ; MIB . addDef ( <STR_LIT> ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . add ( MI -> getOperand ( <NUM_LIT> ) ) ; MIB . addImm ( <STR_LIT> ) ;


<s> O << <STR_LIT> ; printOperand ( MI , opNum , O ) ; O << <STR_LIT> ;


<s> if ( ! tls_get_addr_libfunc ) tls_get_addr_libfunc = init_one_libfunc ( <STR_LIT> ) ; return tls_get_addr_libfunc ;


<s> if ( Address . getOpcode ( ) == <STR_LIT> && ! MatchSegmentBaseAddress ( Address , AM ) ) return false ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> void emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> case CF_TC : Opcode = isEg ? <STR_LIT> : <STR_LIT> ; break ; case CF_VC : Opcode = isEg ? <STR_LIT> : <STR_LIT> ; break ; case CF_CALL_FS : Opcode = isEg ? <STR_LIT> : <STR_LIT> ; break ; case CF_WHILE_LOOP : Opcode = isEg ? <STR_LIT> : <STR_LIT> ; break ; case CF_END_LOOP : Opcode = isEg ? <STR_LIT> : <STR_LIT> ; break ; case CF_LOOP_BREAK : Opcode = isEg ? <STR_LIT> : <STR_LIT> ; break ; case CF_LOOP_CONTINUE : Opcode = isEg ? <STR_LIT> : <STR_LIT> ;


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool has<ISA_LIT>16Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool hasNo<ISA_LIT>16Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool HasMicro<ISA_LIT>Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool HasNoMicro<ISA_LIT>Attr = ! F . getFnAttribute ( <STR_LIT> ) . hasAttribute ( Attribute :: None ) ; bool softFloat = F . hasFnAttribute ( <STR_LIT> ) && F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( has<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( hasNo<ISA_LIT>16Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( HasMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; else if ( HasNoMicro<ISA_LIT>Attr ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; if ( softFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( N . getOpcode ( ) == <STR_LIT> || N . getOpcode ( ) == <STR_LIT> ) { if ( isIntS32Immediate ( N . getOperand ( <NUM_LIT> ) , imm ) ) return false ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return false ; Base = N . getOperand ( <NUM_LIT> ) ; Index = N . getOperand ( <NUM_LIT> ) ;


<s> unsigned LoadOpcode , StoreOpcode ; TII . getLoadStoreOpcodes ( RC , LoadOpcode , StoreOpcode ) ; BuildMI ( MBB , SaveMBBI , DL , TII . get ( StoreOpcode ) ) . addReg ( Reg , RegState :: Kill ) . addReg ( Base ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) ;

BuildMI ( MBB , UseMBBI , DL , TII . get ( LoadOpcode ) , Reg ) . addReg ( Base ) . addImm ( Offset ) . addReg ( <NUM_LIT> ) ;


<s> Thumb2RegisterInfo :: Thumb2RegisterInfo ( const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>Subtarget & sti ) : <ISA_LIT>BaseRegisterInfo ( tii , sti ) {


<s> MCInst UncompressedMI ; if ( PrintAliases && ! NoAliases ) Res = uncompressInst ( UncompressedMI , * MI , MRI , STI ) ; if ( Res ) NewMI = const_cast < MCInst * > ( & UncompressedMI ) ;

if ( ! PrintAliases || NoAliases || ! printAliasInstr ( NewMI , Address , STI , O ) ) printInstruction ( NewMI , Address , STI , O ) ;


<s> DebugLoc DL = N -> getDebugLoc ( ) ; if ( N0 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N0 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N0 . getOperand ( <NUM_LIT> ) , N1 ) ;

if ( N1 . getOpcode ( ) == <STR_LIT> && <STR_LIT> ( N1 . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) return DAG . getNode ( <STR_LIT> , DL , VT , N1 . getOperand ( <NUM_LIT> ) , N0 ) ;


<s> Op -> PSBHint . Data = Str . data ( ) ; Op -> PSBHint . Length = Str . size ( ) ; Op -> StartLoc = S ; Op -> EndLoc = S ;


<s> extern __inline __m128 __attribute__ ( ( __gnu_inline__ , __always_inline__ , __artificial__ ) ) _mm_max_ss ( __m128 __A , __m128 __B ) { __v4sf a , b , c ; static const __vector unsigned int mask = { <NUM_LIT> , <NUM_LIT> , <NUM_LIT> , <NUM_LIT> } ; a = vec_splat ( __A , <NUM_LIT> ) ; b = vec_splat ( __B , <NUM_LIT> ) ; c = vec_max ( a , b ) ; return ( vec_sel ( ( __v4sf ) __A , c , mask ) ) ;


<s> Kind = <STR_LIT> ; BTFType . Info = Kind << <NUM_LIT> ;


<s> analyzeFormalArgumentsCompute ( CCInfo , Ins ) ; } for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const <STR_LIT> & In = Ins [ i ] ; EVT VT = In . VT ; EVT MemVT = VA . getLocVT ( ) ; if ( ! VT . isVector ( ) && MemVT . isVector ( ) ) { MemVT = MemVT . getVectorElementType ( ) ; } if ( <STR_LIT> ( CallConv ) ) { Register Reg = MF . addLiveIn ( VA . getLocReg ( ) , & <STR_LIT> ) ; SDValue Register = DAG . getCopyFromReg ( Chain , DL , Reg , VT ) ; InVals . push_back ( Register ) ; continue ; } <STR_LIT> Ext = <STR_LIT> ;

if ( MemVT . getScalarSizeInBits ( ) != VT . getScalarSizeInBits ( ) ) {


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : const MachineOperand * BaseOp ; OffsetIsScalable = false ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ; return true ;


<s> ptr -> x_arm_arch_string = opts -> x_arm_arch_string ; ptr -> x_arm_cpu_string = opts -> x_arm_cpu_string ; ptr -> x_arm_tune_string = opts -> x_arm_tune_string ;


<s> static std :: string getFrameLabel ( const std :: string & Func ) { std :: string Func1 = addPrefix ( Func ) ;

std :: string tag = getTagName ( FRAME_LABEL ) ;


<s> explicit <ISA_LIT>FunctionInfo ( MachineFunction & MF ) {


<s> case <STR_LIT> : case <STR_LIT> : assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtM ( ) && <STR_LIT> ) ; if ( N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> || N -> getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) return ; Results . push_back ( customLegalizeToWOp ( N , DAG ) ) ; break ; case <STR_LIT> : { assert ( N -> getValueType ( <NUM_LIT> ) == <STR_LIT> && Subtarget . is64Bit ( ) && Subtarget . hasStdExtF ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; SDValue Op0 = N -> getOperand ( <NUM_LIT> ) ; if ( Op0 . getValueType ( ) != <STR_LIT> ) return ; SDValue FPConv = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 ) ; Results . push_back ( DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , FPConv ) ) ; break ; }


<s> unsigned Reg = MRI . createVirtualRegister ( & <STR_LIT> ) ; const DebugLoc & DL = MI . getDebugLoc ( ) ; BuildMI ( * MI . getParent ( ) , MI , DL , get ( <STR_LIT> ) , Reg ) . add ( Src1 ) ; Src1 . ChangeToRegister ( Reg , false ) ; return ; } if ( HasImplicitSGPR || ! MI . isCommutable ( ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int Src0Idx = <STR_LIT> ( Opc , <STR_LIT> :: src0 ) ; MachineOperand & Src0 = MI . getOperand ( Src0Idx ) ; if ( ( ! Src1 . isImm ( ) && ! Src1 . isReg ( ) ) || ! isLegalRegOperand ( MRI , InstrDesc . OpInfo [ Src1Idx ] , Src0 ) ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } int CommutedOpc = commuteOpcode ( MI ) ; if ( CommutedOpc == - <NUM_LIT> ) { legalizeOpWithMove ( MI , Src1Idx ) ; return ; } MI . setDesc ( get ( CommutedOpc ) ) ; unsigned Src0Reg = Src0 . getReg ( ) ; unsigned Src0SubReg = Src0 . getSubReg ( ) ; bool Src0Kill = Src0 . isKill ( ) ; if ( Src1 . isImm ( ) ) Src0 . ChangeToImmediate ( Src1 . getImm ( ) ) ; else if ( Src1 . isReg ( ) ) { Src0 . ChangeToRegister ( Src1 . getReg ( ) , false , false , Src1 . isKill ( ) ) ; Src0 . setSubReg ( Src1 . getSubReg ( ) ) ; } else llvm_unreachable ( <STR_LIT> ) ; Src1 . ChangeToRegister ( Src0Reg , false , false , Src0Kill ) ; Src1 . setSubReg ( Src0SubReg ) ;


<s> return D ( <STR_LIT> , <STR_LIT> ) ;


<s> switch ( GET_CODE ( cmp ) ) { case EQ : case NE : break ; case LTU : cmp = gen_rtx_GTU ( HImode , OP ( <NUM_LIT> ) , OP ( <NUM_LIT> ) ) ; break ; case GTU : cmp = gen_rtx_LTU ( HImode , OP ( <NUM_LIT> ) , OP ( <NUM_LIT> ) ) ; break ; case LEU : cmp = gen_rtx_GEU ( HImode , OP ( <NUM_LIT> ) , OP ( <NUM_LIT> ) ) ; break ; case GEU : cmp = gen_rtx_LEU ( HImode , OP ( <NUM_LIT> ) , OP ( <NUM_LIT> ) ) ; break ; case LT : case GT : case LE : case GE : debug_rtx ( insn ) ; default : gcc_unreachable ( ) ; }

if ( GET_CODE ( cmp ) == EQ || GET_CODE ( cmp ) == NE ) PATTERN ( insn ) = gen_cbranchhi4_real ( cmp , OP ( <NUM_LIT> ) , OP ( <NUM_LIT> ) , OP ( <NUM_LIT> ) ) ;


<s> StringRef getSysReg ( ) const { assert ( Kind == KindTy :: SystemRegister && <STR_LIT> ) ; return StringRef ( SysReg . Data , SysReg . Length ) ;


<s> bool return_address_on_stack = cris_return_address_on_stack ( ) ; int ap_fp_offset = <NUM_LIT> + ( return_address_on_stack ? <NUM_LIT> : <NUM_LIT> ) ; if ( fromreg == ARG_POINTER_REGNUM && toreg == HARD_FRAME_POINTER_REGNUM ) return ap_fp_offset ;

if ( fromreg == FRAME_POINTER_REGNUM && toreg == STACK_POINTER_REGNUM ) return fp_sp_offset ;


<s> if ( Fast ) { switch ( VT . getSizeInBits ( ) ) { default : * Fast = true ; break ; case <NUM_LIT> : * Fast = ! Subtarget . isUnalignedMem16Slow ( ) ; break ; case <NUM_LIT> : * Fast = ! Subtarget . isUnalignedMem32Slow ( ) ; break ; } } if ( ! ! ( Flags & MachineMemOperand :: MONonTemporal ) && VT . isVector ( ) ) {

if ( ! ! ( Flags & MachineMemOperand :: MOLoad ) ) return ( Alignment < <NUM_LIT> || ! Subtarget . hasSSE41 ( ) ) ;


<s> const <ISA_LIT>InstrInfo * getInstrInfo ( ) const {


<s> if ( DisableFavorNonGeneric ) return false ; bool Changed = false ; for ( BasicBlock & B : F ) { for ( Instruction & I : B ) { if ( isa < LoadInst > ( I ) ) {

Changed |= optimizeMemoryInstruction ( & I , <NUM_LIT> ) ;


<s> StringRef getPassName ( ) const override {


<s> } } if ( isMAI ( Opcode ) ) { int MFMAOp = <STR_LIT> ( Opcode ) ; if ( MFMAOp != - <NUM_LIT> ) Opcode = MFMAOp ; } int MCOp = <STR_LIT> ( Opcode , Gen ) ; if ( MCOp == - <NUM_LIT> ) return Opcode ; if ( ST . hasGFX90AInsts ( ) ) { uint16_t NMCOp = ( uint16_t ) - <NUM_LIT> ; if ( ST . hasGFX940Insts ( ) ) NMCOp = <STR_LIT> ( Opcode , <STR_LIT> ) ; if ( NMCOp == ( uint16_t ) - <NUM_LIT> ) NMCOp = <STR_LIT> ( Opcode , <STR_LIT> ) ;


<s> return __builtin_aarch64_uqrshrn_nv8hi_uus ( __a , __b ) ;


<s> case Instruction :: ICmp : return Builder . CreateICmp ( CmpInst :: Predicate ( C -> getPredicate ( ) ) , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: FCmp : llvm_unreachable ( <STR_LIT> <STR_LIT> ) ; case Instruction :: ExtractElement : return Builder . CreateExtractElement ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: InsertElement : return Builder . CreateInsertElement ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: ShuffleVector : return Builder . CreateShuffleVector ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; case Instruction :: ExtractValue : return Builder . CreateExtractValue ( NewOperands [ <NUM_LIT> ] , C -> getIndices ( ) ) ; case Instruction :: InsertValue : return Builder . CreateInsertValue ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , C -> getIndices ( ) ) ; case Instruction :: GetElementPtr : return cast < GEPOperator > ( C ) -> isInBounds ( ) ? Builder . CreateGEP ( cast < GEPOperator > ( C ) -> getSourceElementType ( ) , NewOperands [ <NUM_LIT> ] , makeArrayRef ( & NewOperands [ <NUM_LIT> ] , NumOperands - <NUM_LIT> ) ) : Builder . CreateInBoundsGEP ( cast < GEPOperator > ( C ) -> getSourceElementType ( ) , NewOperands [ <NUM_LIT> ] , makeArrayRef ( & NewOperands [ <NUM_LIT> ] , NumOperands - <NUM_LIT> ) ) ; case Instruction :: Select : return Builder . CreateSelect ( NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; default : if ( Instruction :: isBinaryOp ( Opcode ) ) { return Builder . CreateBinOp ( Instruction :: BinaryOps ( C -> getOpcode ( ) ) , NewOperands [ <NUM_LIT> ] , NewOperands [ <NUM_LIT> ] ) ; } if ( Instruction :: isCast ( Opcode ) ) { return Builder . CreateCast ( Instruction :: CastOps ( C -> getOpcode ( ) ) , NewOperands [ <NUM_LIT> ] , C -> getType ( ) ) ; } llvm_unreachable ( <STR_LIT> ) ; }


<s> const MCConstantExpr * CE = cast < MCConstantExpr > ( getImm ( ) ) ;

Inst . addOperand ( MCOperand :: createImm ( ( CE -> getValue ( ) - <NUM_LIT> ) / <NUM_LIT> ) ) ;


<s> virtual const <ISA_LIT>Subtarget * getSubtargetImpl ( ) const {


<s> <ISA_LIT>RegisterBankInfo :: <ISA_LIT>RegisterBankInfo ( const TargetRegisterInfo & TRI ) : <ISA_LIT>GenRegisterBankInfo ( ) {


<s> <ISA_LIT>AsmPrinter :: <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , SM ( * this ) , FM ( * this ) , FunctionMagicLabelCount ( <NUM_LIT> ) , CFICheckLabelCount ( <NUM_LIT> ) {


<s> void addRegQBRCOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> int m32c_hard_regno_ok ( int regno , enum machine_mode mode ) {

return m32c_hard_regno_nregs ( regno , mode ) != <NUM_LIT> ;