<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) { unsigned Idx = IsLittleEndian ? i : <NUM_LIT> - i ;

Data [ Offset + Idx ] |= uint8_t ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> for ( unsigned i = <NUM_LIT> ; i < Waste ; ++ i ) Reg = State -> AllocateReg ( GPRArgRegs ) ; if ( ! Reg ) return ; unsigned Excess = <NUM_LIT> * ( <STR_LIT> - Reg ) ; const unsigned NSAAOffset = State -> getNextStackOffset ( ) ; if ( NSAAOffset != <NUM_LIT> && Size > Excess ) { while ( State -> AllocateReg ( GPRArgRegs ) ) ; return ; } unsigned ByValRegBegin = Reg ; unsigned ByValRegEnd = std :: min < unsigned > ( Reg + Size / <NUM_LIT> , <STR_LIT> ) ; State -> addInRegsParamInfo ( ByValRegBegin , ByValRegEnd ) ; for ( unsigned i = Reg + <NUM_LIT> ; i != ByValRegEnd ; ++ i ) State -> AllocateReg ( GPRArgRegs ) ; Size = std :: max < int > ( Size - Excess , <NUM_LIT> ) ;


<s> if ( fndecl != NULL_TREE && TREE_CODE ( fndecl ) == FUNCTION_DECL ) call_abi = ix86_function_abi ( fndecl ) ; else call_abi = ix86_function_type_abi ( fndecl ) ;


<s> case LSHIFTRT : if ( ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) || ! IN_RANGE ( INTVAL ( XEXP ( src , <NUM_LIT> ) ) , <NUM_LIT> , <NUM_LIT> ) ) return false ; break ; case PLUS : case MINUS : case IOR : case XOR : case AND : if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) return false ; break ; case NEG : case NOT : break ; case REG : return true ; case MEM : case CONST_INT : return REG_P ( dst ) ; default : return false ; } if ( ! REG_P ( XEXP ( src , <NUM_LIT> ) ) && ! MEM_P ( XEXP ( src , <NUM_LIT> ) ) && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) && ( GET_CODE ( src ) != AND || GET_CODE ( XEXP ( src , <NUM_LIT> ) ) != NOT || ! REG_P ( XEXP ( XEXP ( src , <NUM_LIT> ) , <NUM_LIT> ) ) ) ) return false ; if ( ( GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != DImode && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) || ( GET_CODE ( src ) != NEG && GET_CODE ( src ) != NOT && GET_MODE ( XEXP ( src , <NUM_LIT> ) ) != DImode && ! CONST_INT_P ( XEXP ( src , <NUM_LIT> ) ) ) ) return false ;


<s> if ( ! MI . isPHI ( ) ) continue ; for ( unsigned i = <NUM_LIT> , e = MI . getNumOperands ( ) + <NUM_LIT> ; i != e ; i += <NUM_LIT> ) { MachineOperand & MO = MI . getOperand ( i ) ; if ( MO . getMBB ( ) == OrigMBB ) { MachineInstrBuilder MIB ( * MI . getParent ( ) -> getParent ( ) , & MI ) ; MIB . addReg ( MI . getOperand ( i - <NUM_LIT> ) . getReg ( ) ) . addMBB ( NewMBB ) ;


<s> static void report_not_enum ( location_t location , tree fndecl , unsigned int argno , HOST_WIDE_INT actual , tree enumtype ) { error_at ( location , <STR_LIT> <STR_LIT> , actual , argno + <NUM_LIT> , fndecl , enumtype ) ;


<s> } ; auto IsHazardFn = [ InstType , & IsHazardInst ] ( MachineInstr * I ) { if ( ! I -> isBranch ( ) ) return false ; auto IsHazardFn = [ InstType , IsHazardInst ] ( MachineInstr * I ) { auto InstType2 = IsHazardInst ( I ) ; return InstType2 && InstType != InstType2 ; } ; auto IsExpiredFn = [ InstType , & IsHazardInst ] ( MachineInstr * I , int ) { if ( ! I ) return false ; auto InstType2 = IsHazardInst ( I ) ; if ( InstType == InstType2 ) return true ; return I -> getOpcode ( ) == <STR_LIT> && I -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && ! I -> getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> return ( __m128i ) __builtin_ia32_cvtpd2uqq128_mask ( ( __v2df ) __A , ( __v2di ) _mm_setzero_di ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> if ( MFI -> hasImplicitBufferPtr ( ) ) { unsigned Rsrc01 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; if ( <STR_LIT> ( MF . getFunction ( ) . getCallingConv ( ) ) ) { const MCInstrDesc & Mov64 = TII -> get ( <STR_LIT> ) ; BuildMI ( MBB , I , DL , Mov64 , Rsrc01 ) . addReg ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; } else { const MCInstrDesc & LoadDwordX2 = TII -> get ( <STR_LIT> ) ; PointerType * PtrTy = PointerType :: get ( Type :: getInt64Ty ( MF . getFunction ( ) . getContext ( ) ) , <ISA_LIT>AS :: CONSTANT_ADDRESS ) ; MachinePointerInfo PtrInfo ( UndefValue :: get ( PtrTy ) ) ; auto MMO = MF . getMachineMemOperand ( PtrInfo , MachineMemOperand :: MOLoad | MachineMemOperand :: MOInvariant | MachineMemOperand :: MODereferenceable , <NUM_LIT> , <NUM_LIT> ) ; BuildMI ( MBB , I , DL , LoadDwordX2 , Rsrc01 ) . addReg ( MFI -> getImplicitBufferPtrUserSGPR ( ) ) . addImm ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; } } else { unsigned Rsrc0 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; unsigned Rsrc1 = TRI -> getSubReg ( ScratchRsrcReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , SMovB32 , Rsrc0 ) . addExternalSymbol ( <STR_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ; BuildMI ( MBB , I , DL , SMovB32 , Rsrc1 ) . addExternalSymbol ( <STR_LIT> ) . addReg ( ScratchRsrcReg , RegState :: ImplicitDefine ) ;


<s> MachineBasicBlock * <ISA_LIT>SETargetLowering :: emitCapEqual ( MachineInstr & MI , MachineBasicBlock * BB ) const { bool is64 = ( MI . getOpcode ( ) == <STR_LIT> ) ; unsigned Op = Subtarget . useCheriExactEquals ( ) ? ( is64 ? <STR_LIT> : <STR_LIT> ) : ( is64 ? <STR_LIT> : <STR_LIT> ) ;

const TargetInstrInfo * TII = Subtarget . getInstrInfo ( ) ;


return ( int8x16_t ) __builtin_neon_vdup_nv16qi ( ( __builtin_neon_qi ) __a ) ;


<s> bool <ISA_LIT>TargetMachine :: addPostRegAlloc ( PassManagerBase & PM ) { return false ;


<s> static DecodeStatus DecodeBranchTargetMM ( MCInst & Inst , unsigned Offset , uint64_t Address , const void * Decoder ) {

int32_t BranchOffset = SignExtend32 < <NUM_LIT> > ( Offset ) << <NUM_LIT> ;


<s> Binary |= getAddrModeUPBits ( <STR_LIT> ( MO . getImm ( ) ) ) ; if ( <STR_LIT> ( MO . getImm ( ) ) ) Binary |= <NUM_LIT> << <STR_LIT> ; Binary |= encodeVFPRd ( MI , OpIdx + <NUM_LIT> ) ; unsigned NumRegs = <NUM_LIT> ; for ( unsigned i = OpIdx + <NUM_LIT> , e = MI . getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI . getOperand ( i ) ; if ( ! MO . isReg ( ) || MO . isImplicit ( ) ) break ; ++ NumRegs ; }


<s> if ( ( MI . getNumOperands ( ) > OpNo + <NUM_LIT> ) && MI . getOperand ( OpNo + <NUM_LIT> ) . isReg ( ) ) FrameReg = MI . getOperand ( OpNo + <NUM_LIT> ) . getReg ( ) ; else FrameReg = <STR_LIT> ; } } int64_t Offset ; bool IsKill = false ; Offset = SPOffset + ( int64_t ) StackSize ; Offset += MI . getOperand ( OpNo + <NUM_LIT> ) . getImm ( ) ; DEBUG ( errs ( ) << <STR_LIT> << Offset << <STR_LIT> << <STR_LIT> ) ; if ( ! MI . isDebugValue ( ) && ! <ISA_LIT>16InstrInfo :: validImmediate ( MI . getOpcode ( ) , FrameReg , Offset ) ) { MachineBasicBlock & MBB = * MI . getParent ( ) ; DebugLoc DL = II -> getDebugLoc ( ) ; unsigned NewImm ; const <ISA_LIT>16InstrInfo & TII = * static_cast < const <ISA_LIT>16InstrInfo * > ( MBB . getParent ( ) -> getTarget ( ) . getInstrInfo ( ) ) ; FrameReg = TII . loadImmediate ( FrameReg , Offset , MBB , II , DL , NewImm ) ; Offset = SignExtend64 < <NUM_LIT> > ( NewImm ) ; IsKill = true ; } MI . getOperand ( OpNo ) . ChangeToRegister ( FrameReg , false , false , IsKill ) ;

MI . getOperand ( OpNo + <NUM_LIT> ) . ChangeToImmediate ( Offset ) ;


<s> bool CheckReturn ( const SmallVectorImpl < <STR_LIT> > & ArgsFlags , CCAssignFn Fn ) { PreAnalyzeReturnForF128 ( ArgsFlags ) ; bool Return = CCState :: CheckReturn ( ArgsFlags , Fn ) ;


<s> void <ISA_LIT>MCCodeEmitter :: EmitInstruction ( uint64_t Val , unsigned Size , raw_ostream & OS ) const {

for ( unsigned i = <NUM_LIT> ; i < Size ; ++ i ) {


<s> void printDstIdx8 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) {


<s> CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( auto & Loc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , Loc . getLocReg ( ) , Loc . getValVT ( ) , InGlue ) . getValue ( <NUM_LIT> ) ; InGlue = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; }


<s> Base = ( AM . BaseType == <ISA_LIT>ISelAddressMode :: FrameIndexBase ) ? CurDAG -> getTargetFrameIndex ( AM . Base_FrameIndex , TLI -> getPointerTy ( ) ) : AM . Base_Reg ; Scale = getI8Imm ( AM . Scale , DL ) ; Index = AM . IndexReg ; if ( AM . GV ) Disp = CurDAG -> getTargetGlobalAddress ( AM . GV , SDLoc ( ) , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else if ( AM . CP ) Disp = CurDAG -> getTargetConstantPool ( AM . CP , <STR_LIT> , AM . Align , AM . Disp , AM . SymbolFlags ) ; else if ( AM . ES ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetExternalSymbol ( AM . ES , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . JT != - <NUM_LIT> ) { assert ( ! AM . Disp && <STR_LIT> ) ; Disp = CurDAG -> getTargetJumpTable ( AM . JT , <STR_LIT> , AM . SymbolFlags ) ; } else if ( AM . BlockAddr ) Disp = CurDAG -> getTargetBlockAddress ( AM . BlockAddr , <STR_LIT> , AM . Disp , AM . SymbolFlags ) ; else Disp = CurDAG -> getTargetConstant ( AM . Disp , DL , <STR_LIT> ) ; if ( AM . Segment . getNode ( ) ) Segment = AM . Segment ; else Segment = CurDAG -> getRegister ( <NUM_LIT> , <STR_LIT> ) ;


<s> V1 = convertToScalableVector ( ContainerVT , V1 , DAG , Subtarget ) ; assert ( Lane < ( int ) NumElts && <STR_LIT> ) ; SDValue Gather = DAG . getNode ( <STR_LIT> , DL , ContainerVT , V1 , DAG . getConstant ( Lane , DL , XLenVT ) , TrueMask , VL ) ; return convertFromScalableVector ( VT , Gather , DAG , Subtarget ) ; } } bool IsSelect = all_of ( enumerate ( SVN -> getMask ( ) ) , [ & ] ( const auto & MaskIdx ) { int MaskIndex = MaskIdx . value ( ) ; return MaskIndex < <NUM_LIT> || MaskIdx . index ( ) == ( unsigned ) MaskIndex % NumElts ; } ) ; assert ( ! V1 . isUndef ( ) && <STR_LIT> ) ; SmallVector < SDValue > MaskVals ; SmallVector < SDValue > GatherIndicesLHS , GatherIndicesRHS ; bool SwapOps = DAG . isSplatValue ( V2 ) && ! DAG . isSplatValue ( V1 ) ; bool InvertMask = IsSelect == SwapOps ; for ( int MaskIndex : SVN -> getMask ( ) ) { bool SelectMaskVal = ( MaskIndex < ( int ) NumElts ) ^ InvertMask ; MaskVals . push_back ( DAG . getConstant ( SelectMaskVal , DL , XLenVT ) ) ; if ( ! IsSelect ) { bool IsLHSOrUndefIndex = MaskIndex < ( int ) NumElts ; GatherIndicesLHS . push_back ( IsLHSOrUndefIndex && MaskIndex >= <NUM_LIT> ? DAG . getConstant ( MaskIndex , DL , XLenVT ) : DAG . getUNDEF ( XLenVT ) ) ; GatherIndicesRHS . push_back ( IsLHSOrUndefIndex ? DAG . getUNDEF ( XLenVT ) : DAG . getConstant ( MaskIndex - NumElts , DL , XLenVT ) ) ; } } if ( SwapOps ) { std :: swap ( V1 , V2 ) ; std :: swap ( GatherIndicesLHS , GatherIndicesRHS ) ; } assert ( MaskVals . size ( ) == NumElts && <STR_LIT> ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , NumElts ) ; SDValue SelectMask = DAG . getBuildVector ( MaskVT , DL , MaskVals ) ; if ( IsSelect ) return DAG . getNode ( <STR_LIT> , DL , VT , SelectMask , V1 , V2 ) ; if ( VT . getScalarSizeInBits ( ) == <NUM_LIT> && VT . getVectorNumElements ( ) > <NUM_LIT> ) { return SDValue ( ) ; } unsigned GatherOpc = <STR_LIT> ; MVT IndexVT = VT . changeTypeToInteger ( ) ; if ( IndexVT . getScalarType ( ) . bitsGT ( XLenVT ) ) { GatherOpc = <STR_LIT> ;

IndexVT = IndexVT . changeVectorElementType ( <STR_LIT> ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) {

return std :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case FK_SecRel_4 : case FK_Data_4 : return <NUM_LIT> ; case FK_PCRel_8 : case FK_SecRel_8 : case FK_Data_8 : case <STR_LIT> : return <NUM_LIT> ; }


<s> unsigned Opc , ZReg ; switch ( RetVT . SimpleTy ) { default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : RetVT = <STR_LIT> ; Opc = <STR_LIT> ; ZReg = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; ZReg = <STR_LIT> ; break ; } const TargetRegisterClass * RC = ( RetVT == <STR_LIT> ) ? & <STR_LIT> : & <STR_LIT> ;

return fastEmitInst_rrr ( Opc , RC , Op0 , Op1 , ZReg ) ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setHasCopyImplyingStackAdjustment ( true ) ; }

TargetLoweringBase :: finalizeLowering ( MF ) ;


<s> KnownBits Known = DAG . computeKnownBits ( Value ) ;

return Known . countMinTrailingZeros ( ) >= <NUM_LIT> ;


<s> static const MCPhysReg ReservedGPR32 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg ReservedGPR64 [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; BitVector Reserved ( getNumRegs ( ) ) ; for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedGPR32 ) ; ++ I ) Reserved . set ( ReservedGPR32 [ I ] ) ; if ( Subtarget . isTargetNaCl ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; } for ( unsigned I = <NUM_LIT> ; I < array_lengthof ( ReservedGPR64 ) ; ++ I ) Reserved . set ( ReservedGPR64 [ I ] ) ; if ( ! Subtarget . isABICalls ( ) ) { Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> return ( __m128i ) __builtin_ia32_pmovsxdq128_mask ( ( __v4si ) __X , ( __v2di ) _mm_setzero_si128 ( ) , ( __mmask8 ) __U ) ;


<s> if ( emitPseudoExpansionLowering ( * OutStreamer , & * I ) ) continue ; if ( I -> isBundle ( ) ) continue ; if ( I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> || I -> getOpcode ( ) == <STR_LIT> ) { emitPseudoIndirectBranch ( * OutStreamer , & * I ) ; continue ; } if ( I -> isPseudo ( ) && ! Subtarget -> in<ISA_LIT>16Mode ( ) && ! isLongBranchPseudo ( I -> getOpcode ( ) ) ) llvm_unreachable ( <STR_LIT> ) ; MCInst TmpInst0 ; MCInstLowering . Lower ( & * I , TmpInst0 ) ; EmitToStreamer ( * OutStreamer , TmpInst0 ) ;

} while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ;


<s> Inst . addOperand ( MCOperand :: CreateImm ( getMemScale ( ) ) ) ; Inst . addOperand ( MCOperand :: CreateReg ( getMemIndexReg ( ) ) ) ;

Inst . addOperand ( MCOperand :: CreateMCValue ( getMemDisp ( ) ) ) ;


<s> static bool is_branch_slot_insn ( rtx_insn * insn ) { if ( ! insn || ! NONDEBUG_INSN_P ( insn ) || GET_CODE ( PATTERN ( insn ) ) == USE || GET_CODE ( PATTERN ( insn ) ) == CLOBBER ) return false ; if ( rs6000_sched_groups ) { enum attr_type type = get_attr_type ( insn ) ; if ( type == TYPE_BRANCH || type == TYPE_JMPREG ) return true ;


<s> Function * Func = Arg -> getParent ( ) ; Instruction * FirstInst = & ( Func -> getEntryBlock ( ) . front ( ) ) ; PointerType * PType = dyn_cast < PointerType > ( Arg -> getType ( ) ) ; assert ( PType && <STR_LIT> ) ; Type * StructType = PType -> getElementType ( ) ; const DataLayout & DL = Func -> getParent ( ) -> getDataLayout ( ) ;

unsigned AS = DL . getAllocaAddrSpace ( ) ;


<s> intptr_t Addr = ( intptr_t ) MCE . getCurrentPCValue ( ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; EmitBranchToAt ( Addr , ( intptr_t ) Fn , false , is64Bit ) ; sys :: Memory :: InvalidateInstructionCache ( ( void * ) Addr , <NUM_LIT> * <NUM_LIT> ) ; return MCE . finishGVStub ( F ) ; } MCE . startGVStub ( F , <NUM_LIT> * <NUM_LIT> ) ; intptr_t Addr = ( intptr_t ) MCE . getCurrentPCValue ( ) ; if ( is64Bit ) { MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; } else if ( TM . getSubtargetImpl ( ) -> isMachoABI ( ) ) { MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; MCE . emitWordBE ( <NUM_LIT> ) ; } else {


<s> if ( MI -> getOpcode ( ) == <STR_LIT> ) ByteOffset = true ; else if ( MI -> getOpcode ( ) == <STR_LIT> ) HalfWordOffset = true ; for ( unsigned i = <NUM_LIT> , e = JTBBs . size ( ) ; i != e ; ++ i ) { MachineBasicBlock * MBB = JTBBs [ i ] ; if ( ByteOffset ) O << MAI -> getData8bitsDirective ( ) ; else if ( HalfWordOffset ) O << MAI -> getData16bitsDirective ( ) ; if ( ByteOffset || HalfWordOffset ) O << '(' << * MBB -> getSymbol ( OutContext ) << <STR_LIT> << * JTISymbol << <STR_LIT> ;

else O << <STR_LIT> << * MBB -> getSymbol ( OutContext ) ;


<s> <ISA_LIT>ScalarSSEf32 = Subtarget -> hasSSE1 ( ) ; <ISA_LIT>StackPtr = Subtarget -> has64BitPointers ( ) ? <STR_LIT> : <STR_LIT> ; TD = getDataLayout ( ) ;


<s> if ( ! Features [ <STR_LIT> ] ) StrippedAtomics = stripAtomics ( M ) ; if ( ! Features [ <STR_LIT> ] ) StrippedTLS = stripThreadLocals ( M ) ;

if ( StrippedAtomics && ! StrippedTLS ) stripThreadLocals ( M ) ;


<s> <ISA_LIT>Operand * Op = new <ISA_LIT>Operand ( k_Token ) ; Op -> Tok . Data = Str . data ( ) ; Op -> Tok . Length = Str . size ( ) ;


<s> ( const TargetRegisterClass * ) & <STR_LIT> ; unsigned CopyReg = createResultReg ( CopyRC ) ; BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( TargetOpcode :: COPY ) , CopyReg ) . addReg ( InputReg ) ; InputReg = CopyReg ; } unsigned ResultReg = FastEmitInst_extractsubreg ( <STR_LIT> , InputReg , true , <STR_LIT> ) ; if ( ! ResultReg ) return false ; UpdateValueMap ( I , ResultReg ) ;


<s> if ( ! rtx_equal_p ( DF_REF_REG ( base_use ) , base_reg ) ) continue ; struct df_link * base_def_link = DF_REF_CHAIN ( base_use ) ; if ( ! base_def_link || base_def_link -> next ) break ; if ( DF_REF_IS_ARTIFICIAL ( base_def_link -> ref ) ) break ;


<s> return SelectLoad ( I ) ; case Instruction :: Store : return SelectStore ( I ) ; case Instruction :: Br : return SelectBranch ( I ) ; case Instruction :: ICmp : case Instruction :: FCmp : return SelectCmp ( I ) ; case Instruction :: FPExt : return SelectFPExt ( I ) ; case Instruction :: FPTrunc : return SelectFPTrunc ( I ) ; case Instruction :: SIToFP : return SelectSIToFP ( I ) ; case Instruction :: FPToSI : return SelectFPToSI ( I ) ; case Instruction :: FAdd : return SelectBinaryOp ( I , <STR_LIT> ) ; case Instruction :: FSub : return SelectBinaryOp ( I , <STR_LIT> ) ; case Instruction :: FMul : return SelectBinaryOp ( I , <STR_LIT> ) ; case Instruction :: SDiv :


<s> SetVector < Value * > CurrentVisited ; WorkList . insert ( V ) ; auto AddLegalInst = [ & ] ( Value * V ) { if ( CurrentVisited . count ( V ) ) return true ; if ( isa < GetElementPtrInst > ( V ) ) return true ; if ( ! isSupportedValue ( V ) || ( shouldPromote ( V ) && ! isLegalToPromote ( V ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << * V << <STR_LIT> ) ; return false ; } WorkList . insert ( V ) ; return true ; } ; while ( ! WorkList . empty ( ) ) { Value * V = WorkList . back ( ) ; WorkList . pop_back ( ) ; if ( CurrentVisited . count ( V ) ) continue ; if ( ! isa < Instruction > ( V ) && ! isSource ( V ) ) continue ; if ( AllVisited . count ( V ) ) return false ; CurrentVisited . insert ( V ) ; AllVisited . insert ( V ) ; if ( isSink ( V ) ) Sinks . insert ( cast < Instruction > ( V ) ) ; if ( isSource ( V ) ) Sources . insert ( V ) ; if ( ! isSink ( V ) && ! isSource ( V ) ) { if ( auto * I = dyn_cast < Instruction > ( V ) ) { for ( auto & U : I -> operands ( ) ) { if ( ! AddLegalInst ( U ) ) return false ; } }


<s> bool <ISA_LIT>RegisterInfo :: hasReservedCallFrame ( MachineFunction & MF ) const { return ! MF . getFrameInfo ( ) -> hasVarSizedObjects ( ) ;


<s> } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; useAM3 = true ; } break ; case <STR_LIT> : if ( Alignment && Alignment < <NUM_LIT> && ! Subtarget -> allowsUnalignedMem ( ) ) return false ; if ( isThumb2 ) { if ( Addr . Offset < <NUM_LIT> && Addr . Offset > - <NUM_LIT> && Subtarget -> hasV6T2Ops ( ) ) StrOpc = <STR_LIT> ; else StrOpc = <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) { unsigned MoveReg = createResultReg ( TLI . getRegClassFor ( <STR_LIT> ) ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( <STR_LIT> ) , MoveReg ) . addReg ( SrcReg ) ) ; SrcReg = MoveReg ; VT = <STR_LIT> ; StrOpc = isThumb2 ? <STR_LIT> : <STR_LIT> ; } else { StrOpc = <STR_LIT> ; } break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; if ( Alignment && Alignment < <NUM_LIT> ) return false ; StrOpc = <STR_LIT> ; break ; } <ISA_LIT>SimplifyAddress ( Addr , VT , useAM3 ) ; SrcReg = constrainOperandRegClass ( TII . get ( StrOpc ) , SrcReg , <NUM_LIT> ) ;

MachineInstrBuilder MIB = BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( StrOpc ) ) . addReg ( SrcReg ) ;


<s> if ( ! matchAddressRecursively ( N . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && ! matchAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) return false ; AM = Backup ; if ( ! matchAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && ! matchAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) return false ; AM = Backup ; if ( AM . BaseType == <ISA_LIT>ISelAddressMode :: RegBase && ! AM . Base_Reg . getNode ( ) && ! AM . IndexReg . getNode ( ) ) { N = Handle . getValue ( ) ; AM . Base_Reg = N . getOperand ( <NUM_LIT> ) ; AM . IndexReg = N . getOperand ( <NUM_LIT> ) ;


<s> } else { for ( MCRegister Reg : RC ) { if ( LiveRegs . available ( MRI , Reg ) ) return Reg ; } } if ( ! Unused ) report_fatal_error ( <STR_LIT> ) ;


<s> COMDATSymName += scalarConstantToHexString ( C ) ; } else if ( const auto * VTy = dyn_cast < VectorType > ( Ty ) ) { uint64_t NumBits = VTy -> getBitWidth ( ) ; if ( NumBits == <NUM_LIT> || NumBits == <NUM_LIT> ) { COMDATSymName = NumBits == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; for ( int I = VTy -> getNumElements ( ) - <NUM_LIT> , E = - <NUM_LIT> ; I != E ; -- I ) COMDATSymName += scalarConstantToHexString ( C -> getAggregateElement ( I ) ) ; } } if ( ! COMDATSymName . empty ( ) ) { unsigned Characteristics = COFF :: IMAGE_SCN_CNT_INITIALIZED_DATA | COFF :: IMAGE_SCN_MEM_READ | COFF :: IMAGE_SCN_LNK_COMDAT ; return getContext ( ) . getCOFFSection ( <STR_LIT> , Characteristics , Kind , COMDATSymName , COFF :: IMAGE_COMDAT_SELECT_ANY ) ; } } } return TargetLoweringObjectFile :: getSectionForConstant ( Kind , C ) ;


<s> case <STR_LIT> : return LogicOp ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return LogicOp ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return LogicOp ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; case <STR_LIT> : return LogicOp ( <NUM_LIT> , <NUM_LIT> , <NUM_LIT> ) ; default : return LogicOp ( ) ; }


<s> default : if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; case AsmToken :: Identifier : StringRef Name = getLexer ( ) . getTok ( ) . getIdentifier ( ) ; Register RegNo ; matchRegisterNameHelper ( isRV32E ( ) , RegNo , Name ) ; if ( RegNo == <STR_LIT> ) RegNo = <STR_LIT> ; if ( RegNo == <STR_LIT> ) { if ( HadParens ) getLexer ( ) . UnLex ( LParen ) ; return MatchOperand_NoMatch ; }

if ( HadParens ) Operands . push_back ( <ISA_LIT>Operand :: createToken ( <STR_LIT> , FirstS , isRV64 ( ) ) ) ;


<s> continue ; } if ( isUndefInRange ( Mask , Hi , HalfSize - Hi ) ) { } else if ( ( ! Base || ( Base == V1 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Hi ) ) { Base = V1 ; } else if ( ( ! Base || ( Base == V2 ) ) && isSequentialOrUndefInRange ( Mask , Hi , HalfSize - Hi , Size + Hi ) ) { Base = V2 ; } else { continue ; } BitLen = ( Len * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ; BitIdx = ( Idx * VT . getScalarSizeInBits ( ) ) & <NUM_LIT> ;


<s> tree a ; if ( TREE_CODE ( func ) != FUNCTION_DECL ) return <NUM_LIT> ; a = lookup_attribute ( <STR_LIT> , DECL_ATTRIBUTES ( func ) ) ;


<s> void <ISA_LIT>OffsetAllocator :: ExitScopeIfDone ( MachineDomTreeNode * Node , DenseMap < MachineDomTreeNode * , unsigned > & OpenChildren ) { if ( OpenChildren [ Node ] ) return ; ExitScope ( Node -> getBlock ( ) ) ; while ( MachineDomTreeNode * Parent = Node -> getIDom ( ) ) { unsigned Left = -- OpenChildren [ Parent ] ; if ( Left != <NUM_LIT> ) break ; ExitScope ( Parent -> getBlock ( ) ) ;


<s> static bool mips_valid_base_register_p ( rtx x , machine_mode mode , bool strict_p ) { if ( ! strict_p && GET_CODE ( x ) == SUBREG ) x = SUBREG_REG ( x ) ; return ( REG_P ( x ) && mips_regno_mode_ok_for_base_p ( REGNO ( x ) , mode , strict_p ) ) ;


<s> return Sub != <NUM_LIT> ? TRI -> getSubRegIndexLaneMask ( Sub ) : MRI -> getMaxLaneMaskForVReg ( Reg ) ;


<s> const SDValue Src = N -> getOperand ( <NUM_LIT> ) ; const EVT SrcVT = Src -> getValueType ( <NUM_LIT> ) ; assert ( SrcVT . isScalableVector ( ) && <STR_LIT> ) ; SDLoc DL ( N ) ; MVT SrcElVT = SrcVT . getVectorElementType ( ) . getSimpleVT ( ) ; if ( SrcVT . getSizeInBits ( ) . getKnownMinSize ( ) > <STR_LIT> ) return SDValue ( ) ; if ( SrcElVT . isFloatingPoint ( ) ) if ( ( SrcVT != <STR_LIT> ) && ( SrcVT != <STR_LIT> ) ) return SDValue ( ) ; SDValue Base = N -> getOperand ( <NUM_LIT> ) ; SDValue Offset = N -> getOperand ( <NUM_LIT> ) ; if ( Opcode == <STR_LIT> ) { Offset = getScaledOffsetForBitWidth ( DAG , Offset , DL , SrcElVT . getSizeInBits ( ) ) ; Opcode = <STR_LIT> ; } if ( Opcode == <STR_LIT> && Offset . getValueType ( ) . isVector ( ) ) std :: swap ( Base , Offset ) ; if ( Opcode == <STR_LIT> ) { if ( ! isValidImmForSVEVecImmAddrMode ( Offset , SrcVT . getScalarSizeInBits ( ) / <NUM_LIT> ) ) { if ( <STR_LIT> == Base . getValueType ( ) . getSimpleVT ( ) . SimpleTy ) Opcode = <STR_LIT> ; else Opcode = <STR_LIT> ; std :: swap ( Base , Offset ) ; } } auto & TLI = DAG . getTargetLoweringInfo ( ) ; if ( ! TLI . isTypeLegal ( Base . getValueType ( ) ) ) return SDValue ( ) ; if ( ! OnlyPackedOffsets && Offset . getValueType ( ) . getSimpleVT ( ) . SimpleTy == <STR_LIT> ) Offset = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Offset ) . getValue ( <NUM_LIT> ) ; if ( ! TLI . isTypeLegal ( Offset . getValueType ( ) ) ) return SDValue ( ) ; EVT HwSrcVt = getSVEContainerType ( SrcVT ) ; SDValue InputVT = DAG . getValueType ( SrcVT ) ; if ( SrcVT . isFloatingPoint ( ) ) InputVT = DAG . getValueType ( HwSrcVt ) ; SDVTList VTs = DAG . getVTList ( <STR_LIT> ) ; SDValue SrcNew ; if ( Src . getValueType ( ) . isFloatingPoint ( ) ) SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Src ) ;

else SrcNew = DAG . getNode ( <STR_LIT> , DL , HwSrcVt , Src ) ;


<s> return __builtin_mve_vabdq_fv8hf ( __a , __b ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasDQI ( ) ) return <NUM_LIT> ; if ( RI . getEncodingValue ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) >= <NUM_LIT> ) return <NUM_LIT> ; if ( RI . getEncodingValue ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) >= <NUM_LIT> ) return <NUM_LIT> ; if ( NumOperands == <NUM_LIT> && RI . getEncodingValue ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) >= <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == MI . getOperand ( <NUM_LIT> ) . getReg ( ) && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> && MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) == <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ; case <STR_LIT> :


<s> if ( DstSel ) { SDWAInst . add ( * DstSel ) ; } else { SDWAInst . addImm ( <STR_LIT> :: SdwaSel :: DWORD ) ; } } if ( <STR_LIT> ( SDWAOpcode , <STR_LIT> :: dst_unused ) != - <NUM_LIT> ) { MachineOperand * DstUnused = TII -> getNamedOperand ( MI , <STR_LIT> :: dst_unused ) ; if ( DstUnused ) { SDWAInst . add ( * DstUnused ) ; } else { SDWAInst . addImm ( <STR_LIT> :: DstUnused :: UNUSED_PAD ) ; } } assert ( <STR_LIT> ( SDWAOpcode , <STR_LIT> :: src0_sel ) != - <NUM_LIT> ) ; MachineOperand * Src0Sel = TII -> getNamedOperand ( MI , <STR_LIT> :: src0_sel ) ; if ( Src0Sel ) { SDWAInst . add ( * Src0Sel ) ; } else { SDWAInst . addImm ( <STR_LIT> :: SdwaSel :: DWORD ) ; } if ( Src1 ) { assert ( <STR_LIT> ( SDWAOpcode , <STR_LIT> :: src1_sel ) != - <NUM_LIT> ) ; MachineOperand * Src1Sel = TII -> getNamedOperand ( MI , <STR_LIT> :: src1_sel ) ; if ( Src1Sel ) { SDWAInst . add ( * Src1Sel ) ; } else { SDWAInst . addImm ( <STR_LIT> :: SdwaSel :: DWORD ) ; } } auto DstUnused = TII -> getNamedOperand ( MI , <STR_LIT> :: dst_unused ) ; if ( DstUnused && DstUnused -> getImm ( ) == <STR_LIT> :: DstUnused :: UNUSED_PRESERVE ) { assert ( Dst && Dst -> isTied ( ) ) ; assert ( Opcode == static_cast < unsigned int > ( SDWAOpcode ) ) ; auto PreserveDstIdx = <STR_LIT> ( SDWAOpcode , <STR_LIT> :: vdst ) ; assert ( PreserveDstIdx != - <NUM_LIT> ) ; auto TiedIdx = MI . findTiedOperandIdx ( PreserveDstIdx ) ; auto Tied = MI . getOperand ( TiedIdx ) ; SDWAInst . add ( Tied ) ; SDWAInst -> tieOperands ( PreserveDstIdx , SDWAInst -> getNumOperands ( ) - <NUM_LIT> ) ; } bool Converted = false ; for ( auto & Operand : SDWAOperands ) { LLVM_DEBUG ( dbgs ( ) << * SDWAInst << <STR_LIT> << * Operand ) ; if ( PotentialMatches . count ( Operand -> getParentInst ( ) ) == <NUM_LIT> ) Converted |= Operand -> convertToSDWA ( * SDWAInst , TII ) ; } if ( Converted ) { ConvertedInstructions . push_back ( SDWAInst ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getPC26Encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( MO . isImm ( ) || MO . isExpr ( ) && <STR_LIT> ) ;

const MCExpr * Expr = MO . isImm ( ) ? MCConstantExpr :: create ( MO . getImm ( ) , Ctx ) : MO . getExpr ( ) ;


emit_insn ( gen_subsi3 ( operands [ <NUM_LIT> ] , tmp1 , tmp2 ) ) ;


<s> void ix86_emit_i387_asinh ( rtx op0 , rtx op1 ) { rtx e1 = gen_reg_rtx ( XFmode ) ; rtx e2 = gen_reg_rtx ( XFmode ) ; rtx scratch = gen_reg_rtx ( HImode ) ; rtx flags = gen_rtx_REG ( CCNOmode , FLAGS_REG ) ; rtx cst1 , tmp ; rtx_code_label * jump_label = gen_label_rtx ( ) ; rtx_insn * insn ; emit_insn ( gen_mulxf3 ( e1 , op1 , op1 ) ) ; cst1 = force_reg ( XFmode , CONST1_RTX ( XFmode ) ) ; emit_insn ( gen_addxf3 ( e2 , e1 , cst1 ) ) ; emit_insn ( gen_sqrtxf2 ( e2 , e2 ) ) ; emit_insn ( gen_addxf3 ( e2 , e2 , cst1 ) ) ; emit_insn ( gen_divxf3 ( e1 , e1 , e2 ) ) ; emit_insn ( gen_fxamxf2_i387 ( scratch , op1 ) ) ; emit_insn ( gen_absxf2 ( e2 , op1 ) ) ; emit_insn ( gen_addxf3 ( e1 , e1 , e2 ) ) ; ix86_emit_i387_log1p ( e2 , e1 ) ; emit_insn ( gen_testqi_ext_1_ccno ( scratch , GEN_INT ( <NUM_LIT> ) ) ) ; tmp = gen_rtx_IF_THEN_ELSE ( VOIDmode , gen_rtx_EQ ( VOIDmode , flags , const0_rtx ) , gen_rtx_LABEL_REF ( VOIDmode , jump_label ) , pc_rtx ) ; insn = emit_jump_insn ( gen_rtx_SET ( pc_rtx , tmp ) ) ; predict_jump ( REG_BR_PROB_BASE * <NUM_LIT> / <NUM_LIT> ) ; JUMP_LABEL ( insn ) = jump_label ; emit_insn ( gen_negxf2 ( e2 , e2 ) ) ;


<s> void initialize ( ScheduleDAGMI * dag ) override {


<s> static void cris_setup_incoming_varargs ( cumulative_args_t ca_v , const function_arg_info & , int * pretend_arg_size , int second_time ) { CUMULATIVE_ARGS * ca = get_cumulative_args ( ca_v ) ; if ( ca -> regs < CRIS_MAX_ARGS_IN_REGS ) { int stdarg_regs = CRIS_MAX_ARGS_IN_REGS - ca -> regs ; cfun -> machine -> stdarg_regs = stdarg_regs ; * pretend_arg_size = stdarg_regs * <NUM_LIT> ;


<s> if ( to == QImode ) return ( class_contents [ rclass ] [ <NUM_LIT> ] & <NUM_LIT> ) ; if ( class_contents [ rclass ] [ <NUM_LIT> ] & <NUM_LIT> && GET_MODE_SIZE ( from ) > <NUM_LIT> ) return <NUM_LIT> ; if ( GET_MODE_SIZE ( from ) > <NUM_LIT> ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> Mode = TargetSubtargetInfo :: ANTIDEP_NONE ; CriticalPathRCs . clear ( ) ; CriticalPathRCs . push_back ( has<ISA_LIT>64 ( ) ? & <STR_LIT> : & <STR_LIT> ) ; return OptLevel >= CodeGenOpt :: Aggressive ;


<s> <ISA_LIT>Z80RegisterInfo :: <ISA_LIT>Z80RegisterInfo ( <ISA_LIT>Z80TargetMachine & tm , const TargetInstrInfo & tii ) : <ISA_LIT>Z80GenRegisterInfo ( <STR_LIT> ) , TM ( tm ) , TII ( tii ) {


<s> static MCCodeGenInfo * create<ISA_LIT>MCCodeGenInfo ( StringRef TT , Reloc :: Model RM , CodeModel :: Model CM ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM , CM ) ;


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Op = DAG . getTargetGlobalAddress ( GV , dl , getPointerTy ( ) ) ;

return DAG . getNode ( <STR_LIT> , dl , getPointerTy ( ) , Op ) ;


<s> if ( AsmPrinterCtor ) PM . add ( AsmPrinterCtor ( errs ( ) , * this , OptLevel , true ) ) ; }


<s> case <STR_LIT> : return LowerINT_TO_FP ( Op , DAG ) ; case <STR_LIT> : return LowerFLT_ROUNDS_ ( Op , DAG ) ; case <STR_LIT> : return LowerSHL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRL_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerSRA_PARTS ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerFunnelShift ( Op , DAG ) ; case <STR_LIT> : return LowerBUILD_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerVECTOR_SHUFFLE ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_WO_CHAIN ( Op , DAG ) ; case <STR_LIT> : return LowerSCALAR_TO_VECTOR ( Op , DAG ) ; case <STR_LIT> : return LowerINSERT_VECTOR_ELT ( Op , DAG ) ; case <STR_LIT> : return LowerMUL ( Op , DAG ) ; case <STR_LIT> : return LowerFP_EXTEND ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerFP_ROUND ( Op , DAG ) ; case <STR_LIT> : return LowerROTL ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return LowerBITCAST ( Op , DAG ) ; case <STR_LIT> : return LowerRETURNADDR ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ; case <STR_LIT> : return LowerINTRINSIC_VOID ( Op , DAG ) ; case <STR_LIT> : return LowerBSWAP ( Op , DAG ) ; case <STR_LIT> : return LowerATOMIC_CMP_SWAP ( Op , DAG ) ;


<s> bool <ISA_LIT>TTIImpl :: isLSRCostLess ( TargetTransformInfo :: LSRCost & C1 , TargetTransformInfo :: LSRCost & C2 ) { return std :: tie ( C1 . Insns , C1 . NumRegs , C1 . AddRecCost , C1 . NumIVMuls , C1 . NumBaseAdds , C1 . ScaleCost , C1 . ImmCost , C1 . SetupCost ) < std :: tie ( C2 . Insns , C2 . NumRegs , C2 . AddRecCost , C2 . NumIVMuls , C2 . NumBaseAdds , C2 . ScaleCost , C2 . ImmCost , C2 . SetupCost ) ;


<s> if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , ValToCopy ) ; if ( ( ValVT == <STR_LIT> || ValVT == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE1 ( ) ) ) { report_fatal_error ( <STR_LIT> ) ; } if ( ValVT == <STR_LIT> && ( Subtarget -> is64Bit ( ) && ! Subtarget -> hasSSE2 ( ) ) ) report_fatal_error ( <STR_LIT> ) ; if ( VA . getLocReg ( ) == <STR_LIT> || VA . getLocReg ( ) == <STR_LIT> ) { if ( isScalarFPTypeInSSEReg ( VA . getValVT ( ) ) ) ValToCopy = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , ValToCopy ) ; RetOps . push_back ( ValToCopy ) ; continue ; } if ( Subtarget -> is64Bit ( ) ) {


<s> <STR_LIT> ParseRegType ( const StringRef & RegType ) {

return StringSwitch < <STR_LIT> > ( RegType ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <STR_LIT> ) ;


<s> break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ) ; break ; }


<s> Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> : Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ; break ; case <NUM_LIT> :


<s> bool <ISA_LIT>BaseInstrInfo :: getExtractSubregLikeInputs ( const MachineInstr & MI , unsigned DefIdx , RegSubRegPairAndIdx & InputReg ) const { assert ( DefIdx < MI . getDesc ( ) . getNumDefs ( ) && <STR_LIT> ) ; assert ( MI . isExtractSubregLike ( ) && <STR_LIT> ) ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : const MachineOperand & MOReg = MI . getOperand ( <NUM_LIT> ) ; InputReg . Reg = MOReg . getReg ( ) ; InputReg . SubReg = MOReg . getSubReg ( ) ; InputReg . SubIdx = DefIdx == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ; return true ;


<s> if ( ! GVA ) return false ; if ( ! Kind . isBSS ( ) && ! Kind . isDataRel ( ) ) return false ;

if ( Kind . isMergeable1ByteCString ( ) ) return false ;


<s> return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> : return std :: make_pair ( <STR_LIT> , <STR_LIT> ) ; case <NUM_LIT> :


<s> plus0 = XEXP ( address , <NUM_LIT> ) ; plus1 = XEXP ( address , <NUM_LIT> ) ; if ( REG_P ( plus0 ) && CONST_INT_P ( plus1 ) ) { if ( satisfies_constraint_Iu03 ( plus1 ) ) return ( COSTS_N_INSNS ( <NUM_LIT> ) - <NUM_LIT> ) ;

else return COSTS_N_INSNS ( <NUM_LIT> ) ;


<s> MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; if ( ArgVT . isVector ( ) || ArgVT . getSizeInBits ( ) > <NUM_LIT> ) return false ; if ( VA . isRegLoc ( ) && ! VA . needsCustom ( ) ) { continue ; } else if ( VA . needsCustom ( ) ) { if ( VA . getLocVT ( ) != <STR_LIT> || ! VA . isRegLoc ( ) || ! ArgLocs [ ++ i ] . isRegLoc ( ) ) return false ; } else { switch ( ArgVT . SimpleTy ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; case <STR_LIT> : if ( ! Subtarget -> hasVFP2 ( ) ) return false ; break ; } } } NumBytes = CCInfo . getNextStackOffset ( ) ; unsigned AdjStackDown = TII . getCallFrameSetupOpcode ( ) ; AddOptionalDefs ( BuildMI ( * FuncInfo . MBB , FuncInfo . InsertPt , DbgLoc , TII . get ( AdjStackDown ) ) . addImm ( NumBytes ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; const Value * ArgVal = Args [ VA . getValNo ( ) ] ; unsigned Arg = ArgRegs [ VA . getValNo ( ) ] ; MVT ArgVT = ArgVTs [ VA . getValNo ( ) ] ; assert ( ( ! ArgVT . isVector ( ) && ArgVT . getSizeInBits ( ) <= <NUM_LIT> ) && <STR_LIT> ) ; switch ( VA . getLocInfo ( ) ) { case CCValAssign :: Full : break ; case CCValAssign :: SExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , false ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: AExt : case CCValAssign :: ZExt : { MVT DestVT = VA . getLocVT ( ) ; Arg = <ISA_LIT>EmitIntExt ( ArgVT , Arg , DestVT , true ) ; assert ( Arg != <NUM_LIT> && <STR_LIT> ) ; ArgVT = DestVT ; break ; } case CCValAssign :: BCvt : { unsigned BC = FastEmit_r ( ArgVT , VA . getLocVT ( ) , <STR_LIT> , Arg , false ) ; assert ( BC != <NUM_LIT> && <STR_LIT> ) ; Arg = BC ; ArgVT = VA . getLocVT ( ) ; break ; }

default : llvm_unreachable ( <STR_LIT> ) ;


<s> return Kind == k_Register && Reg . Kind == RegKind :: NeonVector && <ISA_LIT>MCRegisterClasses [ <STR_LIT> ] . contains ( Reg . RegNum ) ;


<s> break ; } if ( func && POINTER_TYPE_P ( TREE_TYPE ( TREE_TYPE ( func ) ) ) ) return gen_rtx_PARALLEL ( mode , gen_rtvec ( <NUM_LIT> , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , A0_REG ) , const0_rtx ) , gen_rtx_EXPR_LIST ( VOIDmode , gen_rtx_REG ( mode , D0_REG ) , const0_rtx ) ) ) ; else if ( POINTER_TYPE_P ( valtype ) ) return gen_rtx_REG ( mode , A0_REG ) ; else return gen_rtx_REG ( mode , D0_REG ) ;


<s> if ( Node -> Flags & GepNode :: Root ) if ( ! isInvariantIn ( Node -> BaseVal , L ) ) return false ; return isInvariantIn ( Node -> Idx , L ) ;


<s> return ScalarSize >= <NUM_LIT> && numBitsSigned ( V , ScalarSize ) < <NUM_LIT> ;


<s> if ( dumpclassfile && ! enablejvmassembler ) llvm :: errs ( ) << <STR_LIT> <STR_LIT> ;


<s> bool <ISA_LIT>TargetLowering :: useLoadStackGuardNode ( ) const {

return Subtarget . isTargetMachO ( ) && Subtarget . is64Bit ( ) ;


<s> std :: string CPU = ! CPUAttr . hasAttribute ( Attribute :: None ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string FS = ! FSAttr . hasAttribute ( Attribute :: None ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; bool SoftFloat = F . getFnAttribute ( <STR_LIT> ) . getValueAsString ( ) == <STR_LIT> ; if ( SoftFloat ) FS += FS . empty ( ) ? <STR_LIT> : <STR_LIT> ; std :: string Key = CPU + FS ; if ( F . hasMinSize ( ) ) Key += <STR_LIT> ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = llvm :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , FS , * this , isLittle , F . hasMinSize ( ) ) ; if ( ! I -> isThumb ( ) && ! I -> has<ISA_LIT>Ops ( ) ) F . getContext ( ) . emitError ( <STR_LIT> + F . getName ( ) + <STR_LIT> <STR_LIT> ) ; }


<s> bool mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const override { return false ;


<s> case PROCESSOR_OCTEON2 : case PROCESSOR_OCTEON3 : case PROCESSOR_I6400 : case PROCESSOR_GS264E : return <NUM_LIT> ; case PROCESSOR_SB1 : case PROCESSOR_SB1A : return <NUM_LIT> ; case PROCESSOR_LOONGSON_2E : case PROCESSOR_LOONGSON_2F : case PROCESSOR_GS464 : case PROCESSOR_GS464E : case PROCESSOR_P5600 : case PROCESSOR_P6600 : return <NUM_LIT> ; case PROCESSOR_XLP : return ( reload_completed ? <NUM_LIT> : <NUM_LIT> ) ; default : return <NUM_LIT> ;


<s> unsigned Dst = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned ListPtr = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; LLT PtrTy = MRI . getType ( ListPtr ) ; LLT IntPtrTy = LLT :: scalar ( PtrTy . getSizeInBits ( ) ) ; const unsigned PtrSize = PtrTy . getSizeInBits ( ) / <NUM_LIT> ; unsigned List = MRI . createGenericVirtualRegister ( PtrTy ) ; MIRBuilder . buildLoad ( List , ListPtr , * MF . getMachineMemOperand ( MachinePointerInfo ( ) , MachineMemOperand :: MOLoad , PtrSize , PtrSize ) ) ; unsigned DstPtr ; if ( Align > PtrSize ) { auto AlignMinus1 = MIRBuilder . buildConstant ( IntPtrTy , Align - <NUM_LIT> ) ;

unsigned ListTmp = MRI . createGenericVirtualRegister ( PtrTy ) ;


<s> SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ;

if ( ! N -> hasAnyUseOfValue ( <NUM_LIT> ) ) return DCI . CombineTo ( N , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VT , N0 , N1 ) , DAG . getNode ( <STR_LIT> , SDLoc ( N ) , <STR_LIT> ) ) ;


<s> DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; -- i ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ;

bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ;


<s> std :: unique_ptr < <ISA_LIT>Operand > <ISA_LIT>AsmParser :: defaultMaskRegOp ( ) const { return <ISA_LIT>Operand :: createReg ( <STR_LIT> , llvm :: SMLoc ( ) , llvm :: SMLoc ( ) , isRV64 ( ) ) ;


<s> case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; case <NUM_LIT> : Inst . setOpcode ( <STR_LIT> ) ; break ; } const MCExpr * Disp = MCConstantExpr :: create ( kShadowOffset , Ctx ) ; std :: unique_ptr < <ISA_LIT>Operand > Op ( <STR_LIT> ( getPointerWidth ( ) , <NUM_LIT> , Disp , ShadowRegI64 , <NUM_LIT> , <NUM_LIT> , SMLoc ( ) , SMLoc ( ) ) ) ; Op -> addMemOperands ( Inst , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ; EmitInstruction ( Out , Inst ) ; } MCSymbol * DoneSym = Ctx . createTempSymbol ( ) ; const MCExpr * DoneExpr = MCSymbolRefExpr :: create ( DoneSym , Ctx ) ;

EmitInstruction ( Out , MCInstBuilder ( <STR_LIT> ) . addExpr ( DoneExpr ) ) ;


<s> <ISA_LIT>HazardRecognizer ( const InstrItineraryData * ItinData , const <ISA_LIT>BaseInstrInfo & tii , const <ISA_LIT>BaseRegisterInfo & tri , const <ISA_LIT>Subtarget & sti , const ScheduleDAG * DAG ) : ScoreboardHazardRecognizer ( ItinData , DAG , <STR_LIT> ) , TII ( tii ) , TRI ( tri ) , STI ( sti ) , LastMI ( <NUM_LIT> ) {


<s> return true ; } case FusionFeature :: FK_SldiAdd : return ( matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) && matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ) || ( matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) && matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ) ; case FusionFeature :: FK_RotateLeftXor : return matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) && matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_RotateRightXor : return matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) && matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_LoadCmp1 : case FusionFeature :: FK_LoadCmp2 : { const MachineOperand & BT = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! BT . isReg ( ) || ( ! Register :: isVirtualRegister ( BT . getReg ( ) ) && BT . getReg ( ) != <STR_LIT> ) ) return false ; if ( SecondMI . getOpcode ( ) == <STR_LIT> && matchingImmOps ( SecondMI , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> ) ) return true ; return matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) ; } case FusionFeature :: FK_LoadCmp3 : { const MachineOperand & BT = SecondMI . getOperand ( <NUM_LIT> ) ; if ( ! BT . isReg ( ) || ( ! Register :: isVirtualRegister ( BT . getReg ( ) ) && BT . getReg ( ) != <STR_LIT> ) ) return false ; return matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , <NUM_LIT> ) || matchingImmOps ( SecondMI , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> ) ; } case FusionFeature :: FK_ZeroMoveCTR : return ( FirstMI . getOpcode ( ) != <STR_LIT> && FirstMI . getOpcode ( ) != <STR_LIT> ) || matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ; case FusionFeature :: FK_ZeroMoveLR : return ( FirstMI . getOpcode ( ) != <STR_LIT> && FirstMI . getOpcode ( ) != <STR_LIT> ) || matchingImmOps ( FirstMI , <NUM_LIT> , <NUM_LIT> ) ;


<s> int loongarch_idiv_insns ( machine_mode mode ATTRIBUTE_UNUSED ) { int count ; count = <NUM_LIT> ; if ( loongarch_check_zero_div_p ( ) ) count += <NUM_LIT> ; return count ;


<s> return STI -> getFeatureBits ( ) . test ( FeatureCodeObjectV3 ) ;


<s> bool <ISA_LIT>TargetLowering :: isFPExtFree ( EVT VT ) const { assert ( VT . isFloatingPoint ( ) ) ; return true ;


<s> Streamer . SwitchSection ( AttributeSection ) ; } else { AttributeSection = Streamer . getContext ( ) . getELFSection ( <STR_LIT> , ELF :: SHT_<ISA_LIT>_ATTRIBUTES , <NUM_LIT> ) ; Streamer . SwitchSection ( AttributeSection ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; } const size_t VendorHeaderSize = <NUM_LIT> + CurrentVendor . size ( ) + <NUM_LIT> ; const size_t TagHeaderSize = <NUM_LIT> + <NUM_LIT> ; const size_t ContentsSize = calculateContentSize ( ) ; Streamer . EmitIntValue ( VendorHeaderSize + TagHeaderSize + ContentsSize , <NUM_LIT> ) ; Streamer . EmitBytes ( CurrentVendor ) ; Streamer . EmitIntValue ( <NUM_LIT> , <NUM_LIT> ) ; Streamer . EmitIntValue ( <STR_LIT> , <NUM_LIT> ) ;

Streamer . EmitIntValue ( TagHeaderSize + ContentsSize , <NUM_LIT> ) ;


<s> mi -> getOperand ( <NUM_LIT> ) . setIsUndef ( mi -> getOperand ( <NUM_LIT> ) . isUndef ( ) ) ; mi -> RemoveOperand ( <NUM_LIT> ) ; mi -> setDesc ( TII -> get ( TargetOpcode :: COPY ) ) ; ( -- getIterForMI ( MI ) ) -> eraseFromParent ( ) ; goto reloop ; } } outs ( ) << <STR_LIT> ; outs ( ) << MBB << <STR_LIT> ; outs ( ) . flush ( ) ; } spilledRegisters . clear ( ) ; BEGINNING : for ( LiveRange * LR : interferenceGraph ) { delete LR ; } interferenceGraph . clear ( ) ; interferenceGraphRetrieval . clear ( ) ; livenessInformation . clear ( ) ; phiNodes . clear ( ) ; calcGlobalLivenessInfo ( MF , regInfo ) ; if ( interferenceGraph . size ( ) > <NUM_LIT> && color ( MF , regInfo ) == EXIT_STATUS_T :: SPILLED ) { goto BEGINNING ; } for ( MachineInstr * MI : getPhiNodes ( ) ) { MI -> eraseFromParent ( ) ; } MF . getProperties ( ) . set ( MachineFunctionProperties :: Property :: NoPHIs ) ; MF . getProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ; outs ( ) << <STR_LIT> ; for ( auto & MBB : MF ) { outs ( ) << <STR_LIT> ;


<s> const char * res = StringSwitch < const char * > ( Name . lower ( ) ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( nullptr ) ; return res ;


<s> case ALPHA_FPRM_MINF : return <STR_LIT> ; case ALPHA_FPRM_CHOP : return <STR_LIT> ; case ALPHA_FPRM_DYN : return <STR_LIT> ; default : gcc_unreachable ( ) ; } break ; case ROUND_SUFFIX_C : return <STR_LIT> ; default : gcc_unreachable ( ) ; }


<s> mcld :: TargetRegistry :: RegisterTargetLDBackend ( mcld :: The<ISA_LIT>Target , mcld :: create<ISA_LIT>LDBackend ) ; mcld :: TargetRegistry :: RegisterTargetLDBackend ( mcld :: TheThumbTarget , mcld :: create<ISA_LIT>LDBackend ) ;


<s> if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineMemOperand * MMO = GetMemOperand ( MBB , FI , MachineMemOperand :: MOLoad ) ; unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ;

BuildMI ( MBB , I , DL , get ( Opc ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const {


<s> getUImm6Lsl2Encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; if ( MO . isImm ( ) ) { unsigned Value = MO . getImm ( ) ; return Value >> <NUM_LIT> ;


<s> SDValue AMDGPUTargetLowering :: LowerFormalArguments ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , DebugLoc DL , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i < e ; ++ i ) { InVals . push_back ( SDValue ( ) ) ;


return ( __m128 ) __builtin_ia32_cvtqq2ps128_mask ( ( __v2di ) __A , ( __v4sf ) _mm_setzero_ps ( ) , ( __mmask8 ) - <NUM_LIT> ) ;


<s> void EmitARM64WinCFISaveFRegPX ( unsigned Reg , int Offset ) override {

OS << <STR_LIT> << Reg << <STR_LIT> << Offset << <STR_LIT> ;


<s> if ( cost > <NUM_LIT> && ( value & <NUM_LIT> ) == <NUM_LIT> ) { int shift = ctz_hwi ( value ) ; unsigned HOST_WIDE_INT x = value ; x = sext_hwi ( x >> shift , HOST_BITS_PER_WIDE_INT - shift ) ; if ( shift > IMM_BITS && ! SMALL_OPERAND ( x ) && LUI_OPERAND ( x << IMM_BITS ) ) shift -= IMM_BITS , x <<= IMM_BITS ; alt_cost = <NUM_LIT> + riscv_build_integer_1 ( alt_codes , x , mode ) ; if ( alt_cost < cost ) { alt_codes [ alt_cost - <NUM_LIT> ] . code = ASHIFT ; alt_codes [ alt_cost - <NUM_LIT> ] . value = shift ; memcpy ( codes , alt_codes , sizeof ( alt_codes ) ) ; cost = alt_cost ; }


<s> DEBUG ( dbgs ( ) << <STR_LIT> ) ; Operands . push_back ( <STR_LIT> ( Token . getIntVal ( ) , getContext ( ) . getRegisterInfo ( ) , S , Token . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; }

DEBUG ( dbgs ( ) << Parser . getTok ( ) . getKind ( ) << <STR_LIT> ) ;


<s> <ISA_LIT>DummyPA ( ) : MachineFunctionPass ( ID ) {


<s> unsigned AttrInd = i - CS . arg_begin ( ) + <NUM_LIT> ; if ( CS . paramHasAttr ( AttrInd , Attribute :: SExt ) ) Flags . setSExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: ZExt ) ) Flags . setZExt ( ) ; if ( CS . paramHasAttr ( AttrInd , Attribute :: InReg ) || CS . paramHasAttr ( AttrInd , Attribute :: StructRet ) || CS . paramHasAttr ( AttrInd , Attribute :: Nest ) || CS . paramHasAttr ( AttrInd , Attribute :: ByVal ) ) return false ; Type * ArgTy = ( * i ) -> getType ( ) ; MVT ArgVT ; if ( ! isTypeLegal ( ArgTy , ArgVT ) && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> && ArgVT != <STR_LIT> ) return false ; unsigned Arg = getRegForValue ( * i ) ; if ( Arg == <NUM_LIT> ) return false ; unsigned OriginalAlignment = DL . getABITypeAlignment ( ArgTy ) ; Flags . setOrigAlign ( OriginalAlignment ) ; Args . push_back ( * i ) ; ArgRegs . push_back ( Arg ) ; ArgVTs . push_back ( ArgVT ) ; ArgFlags . push_back ( Flags ) ; } SmallVector < unsigned , <NUM_LIT> > RegArgs ; unsigned NumBytes ; if ( ! ProcessCallArgs ( Args , ArgRegs , ArgVTs , ArgFlags , RegArgs , CC , NumBytes , isVarArg ) ) return false ; bool UseReg = false ; const GlobalValue * GV = dyn_cast < GlobalValue > ( Callee ) ; if ( ! GV || Subtarget -> genLongCalls ( ) ) UseReg = true ; unsigned CalleeReg = <NUM_LIT> ; if ( UseReg ) {

if ( IntrMemName ) CalleeReg = getLibcallReg ( IntrMemName ) ;


<s> if ( ! isRegInClass ( MO , QPRs ) && AllowScalars ) continue ; if ( auto * OpDef = RDA . getMIOperand ( & MI , MO ) ) if ( FalseLanesZero . count ( OpDef ) ) continue ;


<s> fputs ( <STR_LIT> , file ) ; break ; case <NUM_LIT> : fputs ( <STR_LIT> , file ) ; break ; default : gcc_unreachable ( ) ; }


<s> } } const MCInstrDesc & NewMCID = TII -> get ( Entry . NarrowOpc1 ) ; unsigned PredReg = <NUM_LIT> ; <STR_LIT> Pred = getInstrPredicate ( MI , PredReg ) ; bool SkipPred = false ; if ( Pred != <STR_LIT> ) { if ( ! NewMCID . isPredicable ( ) ) return false ; } else { SkipPred = ! NewMCID . isPredicable ( ) ; } bool HasCC = false ; bool CCDead = false ; if ( MCID . hasOptionalDef ( ) ) { unsigned NumOps = MCID . getNumOperands ( ) ; HasCC = ( MI -> getOperand ( NumOps - <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) ; if ( HasCC && MI -> getOperand ( NumOps - <NUM_LIT> ) . isDead ( ) ) CCDead = true ; } if ( ! VerifyPredAndCC ( MI , Entry , false , Pred , LiveCPSR , HasCC , CCDead ) ) return false ; if ( Entry . PartFlag && NewMCID . hasOptionalDef ( ) && HasCC && canAddPseudoFlagDep ( CPSRDef , MI ) ) return false ; DebugLoc dl = MI -> getDebugLoc ( ) ; MachineInstrBuilder MIB = BuildMI ( MBB , * MI , dl , NewMCID ) ; MIB . addOperand ( MI -> getOperand ( <NUM_LIT> ) ) ; if ( NewMCID . hasOptionalDef ( ) ) { if ( HasCC ) AddDefaultT1CC ( MIB , CCDead ) ; else AddNoT1CC ( MIB ) ; } unsigned NumOps = MCID . getNumOperands ( ) ; for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { if ( i < NumOps && MCID . OpInfo [ i ] . isOptionalDef ( ) ) continue ; if ( ( MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> || MCID . getOpcode ( ) == <STR_LIT> ) && i == <NUM_LIT> ) continue ;

bool isPred = ( i < NumOps && MCID . OpInfo [ i ] . isPredicate ( ) ) ;


<s> explicit <ISA_LIT>16DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OL ) : <ISA_LIT>DAGToDAGISel ( TM , OL ) {


<s> } if ( val1 == - <NUM_LIT> || val2 == - <NUM_LIT> ) { error ( <STR_LIT> , <STR_LIT> ) ; break ; } else if ( val1 > s390_hotpatch_hw_max || val2 > s390_hotpatch_hw_max ) { error ( <STR_LIT> , <STR_LIT> , s390_hotpatch_hw_max ) ; break ; } s390_hotpatch_hw_before_label = val1 ; s390_hotpatch_hw_after_label = val2 ; break ; } default : gcc_unreachable ( ) ; } } init_machine_status = s390_init_machine_status ; if ( ! ( target_flags_explicit & MASK_ZARCH ) ) { if ( TARGET_64BIT ) target_flags |= MASK_ZARCH ; else target_flags &= ~ MASK_ZARCH ; } if ( s390_arch == PROCESSOR_max ) { s390_arch_string = TARGET_ZARCH ? <STR_LIT> : <STR_LIT> ; s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5 ; s390_arch_flags = processor_flags_table [ ( int ) s390_arch ] ; } if ( s390_tune == PROCESSOR_max ) { s390_tune = s390_arch ; s390_tune_flags = s390_arch_flags ; } if ( TARGET_ZARCH && ! TARGET_CPU_ZARCH ) error ( <STR_LIT> , s390_arch_string ) ; if ( TARGET_64BIT && ! TARGET_ZARCH ) error ( <STR_LIT> ) ; if ( ! ( target_flags_explicit & MASK_HARD_DFP ) && TARGET_DFP ) target_flags |= MASK_HARD_DFP ; if ( ! ( target_flags_explicit & MASK_OPT_HTM ) && TARGET_CPU_HTM && TARGET_ZARCH ) target_flags |= MASK_OPT_HTM ; if ( TARGET_HARD_DFP && ! TARGET_DFP ) { if ( target_flags_explicit & MASK_HARD_DFP ) { if ( ! TARGET_CPU_DFP ) error ( <STR_LIT> <STR_LIT> , s390_arch_string ) ; if ( ! TARGET_ZARCH ) error ( <STR_LIT> <STR_LIT> ) ; } else target_flags &= ~ MASK_HARD_DFP ; } if ( ( target_flags_explicit & MASK_SOFT_FLOAT ) && TARGET_SOFT_FLOAT ) { if ( ( target_flags_explicit & MASK_HARD_DFP ) && TARGET_HARD_DFP ) error ( <STR_LIT> ) ; target_flags &= ~ MASK_HARD_DFP ; } switch ( s390_tune ) { case PROCESSOR_2084_Z990 : s390_cost = & z990_cost ; break ; case PROCESSOR_2094_Z9_109 : s390_cost = & z9_109_cost ;


<s> bool Is32Bit = is32Bit ( VT ) ; Even = DAG . getTargetExtractSubreg ( <STR_LIT> ( Is32Bit ) , DL , VT , Result ) ;

Odd = DAG . getTargetExtractSubreg ( <STR_LIT> ( Is32Bit ) , DL , VT , Result ) ;


return CheckImmRange ( <NUM_LIT> , <NUM_LIT> , false , false , false ) ;


<s> } Val = F . bitcastToAPInt ( ) . getZExtValue ( ) ; } else { Val = Negate ? - Val : Val ; } Inst . addOperand ( MCOperand :: createImm ( Val ) ) ; } else {

Inst . addOperand ( MCOperand :: createImm ( getImm ( ) ) ) ;


<s> void <ISA_LIT>InstrInfo :: insertOutlinerPrologue ( MachineBasicBlock & MBB , MachineFunction & MF , const MachineOutlinerInfo & MInfo ) const {


<s> if ( VT . isVector ( ) || Size > <NUM_LIT> ) return SDValue ( ) ; if ( Subtarget -> has16BitInsts ( ) && VT . getScalarType ( ) . bitsLE ( <STR_LIT> ) ) return SDValue ( ) ; SelectionDAG & DAG = DCI . DAG ; SDLoc DL ( N ) ; SDValue N0 = N -> getOperand ( <NUM_LIT> ) ; SDValue N1 = N -> getOperand ( <NUM_LIT> ) ; if ( N0 . getOpcode ( ) == <STR_LIT> ) N0 = N0 . getOperand ( <NUM_LIT> ) ; if ( N1 . getOpcode ( ) == <STR_LIT> ) N1 = N1 . getOperand ( <NUM_LIT> ) ; SDValue Mul ; if ( Subtarget -> hasMulU24 ( ) && isU24 ( N0 , DAG ) && isU24 ( N1 , DAG ) ) { N0 = DAG . getZExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getZExtOrTrunc ( N1 , DL , <STR_LIT> ) ; Mul = getMul24 ( DAG , DL , N0 , N1 , Size , false ) ; } else if ( Subtarget -> hasMulI24 ( ) && isI24 ( N0 , DAG ) && isI24 ( N1 , DAG ) ) { N0 = DAG . getSExtOrTrunc ( N0 , DL , <STR_LIT> ) ; N1 = DAG . getSExtOrTrunc ( N1 , DL , <STR_LIT> ) ; Mul = getMul24 ( DAG , DL , N0 , N1 , Size , true ) ;


<s> void FixupSFBPass :: buildCopies ( int Size , MachineInstr * LoadInst , int64_t LdDispImm , MachineInstr * StoreInst , int64_t StDispImm , int64_t LMMOffset , int64_t SMMOffset ) { int LdDisp = LdDispImm ; int StDisp = StDispImm ; while ( Size > <NUM_LIT> ) { if ( ( Size - MOV128SZ >= <NUM_LIT> ) && isYMMLoadOpcode ( LoadInst -> getOpcode ( ) ) ) { Size = Size - MOV128SZ ; buildCopy ( LoadInst , YMMtoXMMLoadMap . at ( LoadInst -> getOpcode ( ) ) , LdDisp , StoreInst , YMMtoXMMStoreMap . at ( StoreInst -> getOpcode ( ) ) , StDisp , MOV128SZ , LMMOffset , SMMOffset ) ; LdDisp += MOV128SZ ; StDisp += MOV128SZ ; LMMOffset += MOV128SZ ; SMMOffset += MOV128SZ ; continue ; } if ( Size - MOV64SZ >= <NUM_LIT> && Is64Bit ) { Size = Size - MOV64SZ ; buildCopy ( LoadInst , <STR_LIT> , LdDisp , StoreInst , <STR_LIT> , StDisp , MOV64SZ , LMMOffset , SMMOffset ) ;


<s> static int ix86_avx_u128_mode_needed ( rtx_insn * insn ) { if ( CALL_P ( insn ) ) { rtx link ; for ( link = CALL_INSN_FUNCTION_USAGE ( insn ) ; link ; link = XEXP ( link , <NUM_LIT> ) ) { if ( GET_CODE ( XEXP ( link , <NUM_LIT> ) ) == USE ) { rtx arg = XEXP ( XEXP ( link , <NUM_LIT> ) , <NUM_LIT> ) ; if ( ix86_check_avx256_register ( arg ) ) return AVX_U128_DIRTY ; } } return AVX_U128_CLEAN ; }


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIdx ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIdx ) , MFI . getObjectAlignment ( FrameIdx ) ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIdx ) . addReg ( <NUM_LIT> ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addMemOperand ( MMO ) ;


<s> for ( unsigned i = <NUM_LIT> ; i != <NUM_LIT> ; ++ i ) Data [ Offset + i ] |= uint8_t ( ( Value >> ( ( <NUM_LIT> - i - <NUM_LIT> ) * <NUM_LIT> ) ) & <NUM_LIT> ) ;


<s> } for ( insn = get_insns ( ) ; insn ; insn = NEXT_INSN ( insn ) ) { if ( GET_CODE ( insn ) == JUMP_INSN && GET_CODE ( PATTERN ( insn ) ) != ADDR_VEC && GET_CODE ( PATTERN ( insn ) ) != ADDR_DIFF_VEC && get_attr_far_jump ( insn ) == FAR_JUMP_YES ) {

cfun -> machine -> far_jump_used = <NUM_LIT> ;


<s> DebugLoc DL = I . getDebugLoc ( ) ; MachineInstr * Ins = BuildMI ( * BB , & I , DL , TII . get ( TargetOpcode :: INSERT_SUBREG ) ) . addDef ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addImm ( SubReg ) ; for ( const MachineOperand & MO : Ins -> operands ( ) ) { if ( ! MO . isReg ( ) ) continue ;

if ( Register :: isPhysicalRegister ( MO . getReg ( ) ) ) continue ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = * MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlignment ( FI ) ) ; DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> || RC == & <STR_LIT> ) { AddDefaultPred ( BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ) ; return ; } if ( <STR_LIT> . hasSubClassEq ( RC ) ) { MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; MRI -> constrainRegClass ( DestReg , & <STR_LIT> ) ;

MachineInstrBuilder MIB = BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) ;


<s> void <ISA_LIT>MCInstPrinter :: printRegName ( raw_ostream & os , unsigned reg ) const {


<s> MCObjectWriter * llvm :: create<ISA_LIT>ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI ) { MCELFObjectTargetWriter * MOTW = new <ISA_LIT>ELFObjectWriter ( OSABI ) ;

return createELFObjectWriter ( MOTW , OS , true ) ;


<s> assert ( MCE && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: CreateImm ( MCE -> getValue ( ) ) ) ;


<s> RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) ) ; LastArgStackLoc = ( FirstStackArgLoc + VA . getLocMemOffset ( ) ) ; int FI = MFI -> CreateFixedObject ( VA . getValVT ( ) . getSizeInBits ( ) / <NUM_LIT> , LastArgStackLoc , true , false ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , PtrOff , NULL , <NUM_LIT> , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } unsigned char OpFlag = <STR_LIT> ; if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , getPointerTy ( ) , <NUM_LIT> , OpFlag ) ; else if ( ExternalSymbolSDNode * S = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( S -> getSymbol ( ) , getPointerTy ( ) , OpFlag ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; } if ( InFlag . getNode ( ) ) Ops . push_back ( InFlag ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , & Ops [ <NUM_LIT> ] , Ops . size ( ) ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( NumBytes , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , InFlag ) ; if ( ! Ins . empty ( ) ) InFlag = Chain . getValue ( <NUM_LIT> ) ;

return LowerCallResult ( Chain , InFlag , CallConv , isVarArg , Ins , dl , DAG , InVals ) ;


<s> BuildVectorSDNode * BVN = dyn_cast < BuildVectorSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ; SDLoc dl ( N ) ; EVT VT = N -> getValueType ( <NUM_LIT> ) ; SelectionDAG & DAG = DCI . DAG ; if ( ! DAG . getTargetLoweringInfo ( ) . isTypeLegal ( VT ) ) return SDValue ( ) ; APInt SplatBits , SplatUndef ; unsigned SplatBitSize ; bool HasAnyUndefs ; if ( BVN && BVN -> isConstantSplat ( SplatBits , SplatUndef , SplatBitSize , HasAnyUndefs ) ) { if ( SplatBitSize <= <NUM_LIT> ) { EVT VbicVT ; SDValue Val = isNEONModifiedImm ( ( ~ SplatBits ) . getZExtValue ( ) , SplatUndef . getZExtValue ( ) , SplatBitSize , DAG , VbicVT , VT . is128BitVector ( ) , OtherModImm ) ; if ( Val . getNode ( ) ) { SDValue Input = DAG . getNode ( <STR_LIT> , dl , VbicVT , N -> getOperand ( <NUM_LIT> ) ) ; SDValue Vbic = DAG . getNode ( <STR_LIT> , dl , VbicVT , Input , Val ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Vbic ) ; } } } if ( ! Subtarget -> isThumb1Only ( ) ) { SDValue Result = combineSelectAndUseCommutative ( N , true , DCI ) ; if ( Result . getNode ( ) ) return Result ;


<s> CMPTermImag8_match ( Register & LHS , Register & RHS , Register & Flag ) : Cmp_match ( LHS , Flag ) , RHS ( RHS ) {


<s> if ( Subtarget . isLittleEndian ( ) ) VectorIndex = <NUM_LIT> ; Op = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Op , DAG . getTargetConstant ( VectorIndex , dl , <STR_LIT> ) ) ;


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return lowerATOMIC_FENCE ( Op , DAG ) ; case <STR_LIT> : return lowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return lowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return lowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return lowerGlobalTLSAddress ( Op , DAG ) ; case <STR_LIT> : return lowerLOAD ( Op , DAG ) ; case <STR_LIT> : return lowerSTORE ( Op , DAG ) ; case <STR_LIT> :


<s> const Triple & TT = STI . getTargetTriple ( ) ; uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( TT . getOS ( ) ) ;

StringRef CPUString = <ISA_LIT>_MC :: select<ISA_LIT>CPU ( STI . getCPU ( ) ) ;


<s> if ( Subtarget . hasNEON ( ) ) PM . add ( createExecutionDependencyFixPass ( & <STR_LIT> ) ) ; } PM . add ( create<ISA_LIT>ExpandPseudoPass ( ) ) ; if ( OptLevel != CodeGenOpt :: None ) { if ( ! Subtarget . isThumb1Only ( ) ) PM . add ( createIfConverterPass ( ) ) ; } if ( Subtarget . isThumb2 ( ) ) PM . add ( createThumb2ITBlockPass ( ) ) ; return true ;


<s> if ( MOI . getOrdering ( ) == AtomicOrdering :: Acquire || MOI . getOrdering ( ) == AtomicOrdering :: SequentiallyConsistent ) { Changed |= CC -> insertWait ( MI , MOI . getScope ( ) , MOI . getInstrAddrSpace ( ) , <STR_LIT> , MOI . getIsCrossAddressSpaceOrdering ( ) , Position :: AFTER ) ; Changed |= CC -> insertAcquire ( MI , MOI . getScope ( ) , MOI . getOrderingAddrSpace ( ) , Position :: AFTER ) ; } return Changed ; }

Changed |= CC -> enableVolatileAndOrNonTemporal ( MI , MOI . getInstrAddrSpace ( ) , <STR_LIT> , MOI . isVolatile ( ) , MOI . isNonTemporal ( ) ) ;


<s> int <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , unsigned & FrameReg ) const {

const MachineFrameInfo * MFFrame = MF . getFrameInfo ( ) ;


<s> if ( ! Expr ) Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> ) ) ;

else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: CreateImm ( CE -> getValue ( ) ) ) ;


<s> int64_t Offset = <NUM_LIT> ; if ( ! selectMUBUFAddr64Impl ( Root , VAddr , RSrcReg , SOffset , Offset ) ) return { } ; return { { [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( RSrcReg ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addReg ( VAddr ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { if ( SOffset ) MIB . addReg ( SOffset ) ; else MIB . addImm ( <NUM_LIT> ) ; } , [ = ] ( MachineInstrBuilder & MIB ) { MIB . addImm ( Offset ) ;

} , addZeroImm , addZeroImm , addZeroImm } } ;


<s> if ( Mask == - <NUM_LIT> ) return - <NUM_LIT> ; return Mask << <NUM_LIT> ; } if ( Reg != <STR_LIT> && Reg != <STR_LIT> ) { return - <NUM_LIT> ; } if ( Flags . empty ( ) || Flags == <STR_LIT> ) return Mask | <NUM_LIT> ; for ( char Flag : Flags ) { int FlagVal ; switch ( Flag ) { case 'c' : FlagVal = <NUM_LIT> ; break ; case 'x' : FlagVal = <NUM_LIT> ; break ; case 's' : FlagVal = <NUM_LIT> ; break ; case 'f' : FlagVal = <NUM_LIT> ; break ; default : FlagVal = <NUM_LIT> ; } if ( ! FlagVal || ( Mask & FlagVal ) ) return - <NUM_LIT> ; Mask |= FlagVal ; } if ( Reg == <STR_LIT> ) Mask |= <NUM_LIT> ;


<s> while ( EmittedNumMemOps < NumMemOps ) { for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcSV , SrcSVOff + SrcOff , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; SrcOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; for ( i = <NUM_LIT> ; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps ; ++ i ) { TFOps [ i ] = DAG . getStore ( Chain , dl , Loads [ i ] , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Dst , DAG . getConstant ( DstOff , <STR_LIT> ) ) , DstSV , DstSVOff + DstOff , false , false , <NUM_LIT> ) ; DstOff += VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; EmittedNumMemOps += i ; } if ( BytesLeft == <NUM_LIT> ) return Chain ; unsigned BytesLeftSave = BytesLeft ; i = <NUM_LIT> ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } Loads [ i ] = DAG . getLoad ( VT , dl , Chain , DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Src , DAG . getConstant ( SrcOff , <STR_LIT> ) ) , SrcSV , SrcSVOff + SrcOff , false , false , <NUM_LIT> ) ; TFOps [ i ] = Loads [ i ] . getValue ( <NUM_LIT> ) ; ++ i ; SrcOff += VTSize ; BytesLeft -= VTSize ; } Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & TFOps [ <NUM_LIT> ] , i ) ; i = <NUM_LIT> ; BytesLeft = BytesLeftSave ; while ( BytesLeft ) { if ( BytesLeft >= <NUM_LIT> ) { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; } else { VT = <STR_LIT> ; VTSize = <NUM_LIT> ; }


<s> const uint16_t * <ISA_LIT>Z80RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { static const uint16_t CalleeSavedRegs [ ] = { <STR_LIT> , <STR_LIT> , <NUM_LIT> } ;


<s> MachineBasicBlock * DestMBB = cast < BasicBlockSDNode > ( Dest ) -> getBasicBlock ( ) ; BlockAddress * BA = BlockAddress :: get ( const_cast < Function * > ( MF . getFunction ( ) ) , const_cast < BasicBlock * > ( DestMBB -> getBasicBlock ( ) ) ) ; DestMBB -> setHasAddressTaken ( ) ; SDValue BlockPtr = DAG . getBlockAddress ( BA , PtrVT ) ; Chain = DAG . getCopyToReg ( Chain , DL , ReturnReg , BlockPtr ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Chain , DAG . getRegister ( ReturnReg , PtrVT ) ) ;


<s> <ISA_LIT>LowerI1Copies ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>LowerI1CopiesPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> for ( int i = QuarterSize ; i < QuarterSize * <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , NumElems , NumElems + HalfSize ) ) return false ; for ( int i = QuarterSize * <NUM_LIT> ; i < QuarterSize * <NUM_LIT> ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , HalfSize , NumElems ) ) return false ; for ( int i = QuarterSize * <NUM_LIT> ; i < NumElems ; ++ i ) if ( ! isUndefOrInRange ( Mask [ i ] , NumElems + HalfSize , NumElems * <NUM_LIT> ) ) return false ; return true ;


<s> case <STR_LIT> : case <STR_LIT> : if ( OpNum == <NUM_LIT> ) { unsigned Imm = MI . getOperand ( MI . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ; unsigned ZMask = Imm & <NUM_LIT> ; unsigned DstIdx = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned SrcIdx = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; unsigned RCSize = getRegClass ( MI . getDesc ( ) , OpNum , & RI , MF ) -> getSize ( ) ; if ( Size <= RCSize && <NUM_LIT> <= Align ) { int PtrOffset = SrcIdx * <NUM_LIT> ; unsigned NewImm = ( DstIdx << <NUM_LIT> ) | ZMask ; unsigned NewOpCode = ( MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * NewMI = FuseInst ( MF , NewOpCode , OpNum , MOs , InsertPt , MI , * this , PtrOffset ) ; NewMI -> getOperand ( NewMI -> getNumOperands ( ) - <NUM_LIT> ) . setImm ( NewImm ) ; return NewMI ; } } break ; case <STR_LIT> : case <STR_LIT> : if ( OpNum == <NUM_LIT> ) { unsigned RCSize = getRegClass ( MI . getDesc ( ) , OpNum , & RI , MF ) -> getSize ( ) ; if ( Size <= RCSize && <NUM_LIT> <= Align ) { unsigned NewOpCode = ( MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) ; MachineInstr * NewMI = FuseInst ( MF , NewOpCode , OpNum , MOs , InsertPt , MI , * this , <NUM_LIT> ) ; return NewMI ; } }


<s> return ( uint64x1_t ) { __builtin_aarch64_sqshlu_ndi_uss ( __a [ <NUM_LIT> ] , __b ) } ;


<s> SmallSet < BasicBlock * , <NUM_LIT> > BBChanged ; for ( auto & Bucket : Buckets ) { if ( prepareBasesForCommoningChains ( Bucket ) ) MadeChange |= rewriteLoadStoresForCommoningChains ( L , Bucket , BBChanged ) ;


<s> void printCustom ( raw_ostream & OS ) const override { OS << <STR_LIT> ;


<s> SDValue FalseVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstantFP ( <NUM_LIT> , DL , ElementType ) ) ;

SDValue TrueVal = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstantFP ( - <NUM_LIT> , DL , ElementType ) ) ;


<s> void <ISA_LIT>InstPrinter :: printVectorListTwoSpaced ( const MCInst * MI , unsigned OpNum , raw_ostream & O ) { unsigned Reg = MI -> getOperand ( OpNum ) . getReg ( ) ; unsigned Reg0 = MRI . getSubReg ( Reg , <STR_LIT> ) ; unsigned Reg1 = MRI . getSubReg ( Reg , <STR_LIT> ) ; O << <STR_LIT> ; printRegName ( O , Reg0 ) ; O << <STR_LIT> ; printRegName ( O , Reg1 ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( getReg ( Decoder , <STR_LIT> , RegNo ) ) ) ;


<s> static unsigned getADDriOpcode ( unsigned is64Bit , int64_t Imm ) { if ( is64Bit ) { if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ; return <STR_LIT> ; } else { if ( isInt < <NUM_LIT> > ( Imm ) ) return <STR_LIT> ;


<s> dbgs ( ) << __func__ << <STR_LIT> << PrintReg ( VR , HRI ) << <STR_LIT> << PrintORL ( AVs , HRI ) << <STR_LIT> ; } if ( AVs . size ( ) == <NUM_LIT> ) return false ; using iterator = OrderedRegisterList :: iterator ; BitValueOrdering BVO ( BaseOrd ) ; const BitTracker :: RegisterCell & RC = CMS -> lookup ( VR ) ; uint16_t W = RC . width ( ) ; using RSRecord = std :: pair < unsigned , uint16_t > ; using RSListType = std :: vector < RSRecord > ; using LRSMapType = DenseMap < unsigned , RSListType > ; LRSMapType LM ; for ( uint16_t S = <NUM_LIT> ; S < W ; ++ S ) { iterator B = AVs . begin ( ) , E = AVs . end ( ) ; uint16_t L ; for ( L = <NUM_LIT> ; L < W - S ; ++ L ) { RegisterCellBitCompareSel RCB ( VR , S + L , L , BVO , * CMS ) ; iterator NewB = std :: lower_bound ( B , E , VR , RCB ) ; iterator NewE = std :: upper_bound ( NewB , E , VR , RCB ) ; if ( L > <NUM_LIT> ) { for ( iterator I = B ; I != NewB ; ++ I ) LM [ L ] . push_back ( std :: make_pair ( * I , S ) ) ; for ( iterator I = NewE ; I != E ; ++ I ) LM [ L ] . push_back ( std :: make_pair ( * I , S ) ) ; } B = NewB , E = NewE ; if ( B == E ) break ; } assert ( B == E || L == W - S ) ; if ( B != E ) { for ( iterator I = B ; I != E ; ++ I ) LM [ L ] . push_back ( std :: make_pair ( * I , S ) ) ;


<s> switch ( ( insn >> <NUM_LIT> ) & <NUM_LIT> ) {


<s> return llvm :: make_unique < <ISA_LIT>ELFObjectWriter > ( OSABI ) ;


<s> void <ISA_LIT>MachineFunctionInfo :: anchor ( ) {


return getModifiers ( ) . hasIntModifiers ( ) ;


<s> SDValue Disp = DAG . getTargetConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; SDValue Segment = DAG . getRegister ( <NUM_LIT> , <STR_LIT> ) ; unsigned MinElts = std :: min ( Index . getSimpleValueType ( ) . getVectorNumElements ( ) , Src . getSimpleValueType ( ) . getVectorNumElements ( ) ) ; MVT MaskVT = <STR_LIT> ( <STR_LIT> , MinElts ) ;

SDValue VMask = getMaskNode ( Mask , MaskVT , Subtarget , DAG , dl ) ;


<s> DebugLoc DL = MI . getDebugLoc ( ) ; unsigned Src = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;

BuildMI ( MBB , & MI , DL , TII -> get ( AMDGPU :: S_ANDN2_B64 ) , AMDGPU :: EXEC ) . addReg ( AMDGPU :: EXEC ) . addReg ( Src ) ;


<s> const MCExpr * Expr = MCSymbolRefExpr :: create ( Sym , Ctx ) ;

if ( ! MO . isJTI ( ) && MO . getOffset ( ) ) llvm_unreachable ( <STR_LIT> ) ;


<s> return MatchOperand_Success ; } Index = matchFPURegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ; return MatchOperand_Success ; } Index = matchFCCRegisterName ( Identifier ) ; if ( Index != - <NUM_LIT> ) { Operands . push_back ( <STR_LIT> ( Index , getContext ( ) . getRegisterInfo ( ) , S , getLexer ( ) . getLoc ( ) , * this ) ) ;


<s> explicit <ISA_LIT>StoreCombine ( ) : BasicBlockPass ( ID ) {


<s> return SDValue ( ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> :


<s> if ( arg . aggregate_type_p ( ) ) basereg = <NUM_LIT> ; else { gcc_checking_assert ( ! COMPLEX_MODE_P ( arg . mode ) ) ; if ( TARGET_FPREGS && GET_MODE_CLASS ( arg . mode ) == MODE_FLOAT ) basereg = <NUM_LIT> + <NUM_LIT> ; else basereg = <NUM_LIT> ; } { if ( arg . end_marker_p ( ) ) return alpha_arg_info_reg_val ( * cum ) ; num_args = cum -> num_args ; if ( num_args >= <NUM_LIT> || targetm . calls . must_pass_in_stack ( arg ) ) return NULL_RTX ; } { if ( * cum >= <NUM_LIT> ) return NULL_RTX ; num_args = * cum ; if ( arg . end_marker_p ( ) ) basereg = <NUM_LIT> ;

else if ( targetm . calls . must_pass_in_stack ( arg ) ) return NULL_RTX ;


<s> SDValue Op1 = N -> getOperand ( <NUM_LIT> ) ; auto UsePMADDWD = [ & ] ( SDValue Op ) { ShrinkMode Mode ; return Op . getOpcode ( ) == <STR_LIT> && canReduceVMulWidth ( Op . getNode ( ) , DAG , Mode ) && Mode != ShrinkMode :: MULU16 && ( ! Subtarget . hasSSE41 ( ) || ( Op -> isOnlyUserOf ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) && Op -> isOnlyUserOf ( Op . getOperand ( <NUM_LIT> ) . getNode ( ) ) ) ) ; } ; SDValue MulOp , OtherOp ; if ( UsePMADDWD ( Op0 ) ) { MulOp = Op0 ; OtherOp = Op1 ; } else if ( UsePMADDWD ( Op1 ) ) { MulOp = Op1 ; OtherOp = Op0 ; } else return SDValue ( ) ; SDLoc DL ( N ) ; EVT ReducedVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) ) ; EVT MAddVT = EVT :: getVectorVT ( * DAG . getContext ( ) , <STR_LIT> , VT . getVectorNumElements ( ) / <NUM_LIT> ) ;

SDValue N0 = DAG . getNode ( <STR_LIT> , DL , ReducedVT , MulOp -> getOperand ( <NUM_LIT> ) ) ;


<s> if ( MI . getOperand ( OpndIdx ) . isImm ( ) && ! isShiftedInt < Width , Scale > ( MI . getOperand ( OpndIdx ) . getImm ( ) ) ) {


return ( float32x4_t ) __builtin_neon_vreinterpretv4sfv4si ( __a ) ;


<s> Entry . isZExt = false ; Entry . isSRet = true ; Args . push_back ( Entry ) ; Entry . Node = Arg ; Entry . Ty = ArgTy ; Entry . isSExt = false ; Entry . isZExt = false ; Args . push_back ( Entry ) ; const char * LibcallName = ( ArgVT == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; SDValue Callee = DAG . getExternalSymbol ( LibcallName , getPointerTy ( DL ) ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( DAG . getEntryNode ( ) ) . setCallee ( CallingConv :: C , Type :: getVoidTy ( * DAG . getContext ( ) ) , Callee , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = LowerCallTo ( CLI ) ; SDValue LoadSin = DAG . getLoad ( ArgVT , dl , CallResult . second , SRet , MachinePointerInfo ( ) , false , false , false , <NUM_LIT> ) ;

SDValue Add = DAG . getNode ( <STR_LIT> , dl , PtrVT , SRet , DAG . getIntPtrConstant ( ArgVT . getStoreSize ( ) , dl ) ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> SDValue <ISA_LIT>TargetLowering :: lowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { EVT Ty = Op . getValueType ( ) ; GlobalAddressSDNode * N = cast < GlobalAddressSDNode > ( Op ) ; const GlobalValue * GV = N -> getGlobal ( ) ; if ( getTargetMachine ( ) . getRelocationModel ( ) != Reloc :: PIC_ && ! ABI . IsN64 ( ) ) { const <ISA_LIT>TargetObjectFile & TLOF = ( const <ISA_LIT>TargetObjectFile & ) getObjFileLowering ( ) ; if ( TLOF . IsGlobalInSmallSection ( GV , getTargetMachine ( ) ) ) return getAddrGPRel ( N , SDLoc ( N ) , Ty , DAG ) ;

return getAddrNonPIC ( N , SDLoc ( N ) , Ty , DAG ) ;


<s> } else if ( insn_op -> mode == V1DImode && GET_MODE ( op [ arg_count ] ) == DImode ) op [ arg_count ] = gen_lowpart ( V1DImode , op [ arg_count ] ) ; else if ( insn_op -> mode == V1SImode && GET_MODE ( op [ arg_count ] ) == SImode ) op [ arg_count ] = gen_lowpart ( V1SImode , op [ arg_count ] ) ; if ( ! ( * insn_data [ icode ] . operand [ idx ] . predicate ) ( op [ arg_count ] , insn_op -> mode ) ) op [ arg_count ] = copy_to_mode_reg ( insn_op -> mode , op [ arg_count ] ) ;


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveSetNoMacro ( ) {


<s> bool Signed = N -> getOpcode ( ) == <STR_LIT> ; if ( OffsetVal == <NUM_LIT> ) { unsigned SignBits = Signed ? ( <NUM_LIT> - WidthVal + <NUM_LIT> ) : ( <NUM_LIT> - WidthVal ) ; unsigned OpSignBits = DAG . ComputeNumSignBits ( BitsFrom ) ; if ( OpSignBits >= SignBits ) return BitsFrom ; EVT SmallVT = EVT :: getIntegerVT ( * DAG . getContext ( ) , WidthVal ) ; if ( Signed ) { return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , BitsFrom , DAG . getValueType ( SmallVT ) ) ; } return DAG . getZeroExtendInReg ( BitsFrom , DL , SmallVT ) ; } if ( ConstantSDNode * CVal = dyn_cast < ConstantSDNode > ( BitsFrom ) ) { if ( Signed ) { return constantFoldBFE < int32_t > ( DAG , CVal -> getSExtValue ( ) , OffsetVal , WidthVal ) ; } return constantFoldBFE < uint32_t > ( DAG , CVal -> getZExtValue ( ) , OffsetVal , WidthVal ) ; } if ( ( OffsetVal + WidthVal ) >= <NUM_LIT> ) { SDValue ShiftVal = DAG . getConstant ( OffsetVal , <STR_LIT> ) ; return DAG . getNode ( Signed ? <STR_LIT> : <STR_LIT> , DL , <STR_LIT> , BitsFrom , ShiftVal ) ; } if ( BitsFrom . hasOneUse ( ) ) { APInt Demanded = APInt :: getBitsSet ( <NUM_LIT> , OffsetVal , OffsetVal + WidthVal ) ; APInt KnownZero , KnownOne ; TargetLowering :: TargetLoweringOpt TLO ( DAG , ! DCI . isBeforeLegalize ( ) , ! DCI . isBeforeLegalizeOps ( ) ) ; const TargetLowering & TLI = DAG . getTargetLoweringInfo ( ) ; if ( TLO . ShrinkDemandedConstant ( BitsFrom , Demanded ) || TLI . SimplifyDemandedBits ( BitsFrom , Demanded , KnownZero , KnownOne , TLO ) ) {


<s> SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , SDLoc ( SAddr ) , <STR_LIT> , TFI , SAddr . getOperand ( <NUM_LIT> ) ) , <NUM_LIT> ) ; } const <ISA_LIT>InstrInfo * TII = Subtarget -> getInstrInfo ( ) ; if ( ! TII -> isLegalFLATOffset ( COffsetVal , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) { int64_t RemainderOffset = COffsetVal ; int64_t ImmField = <NUM_LIT> ; const unsigned NumBits = <STR_LIT> ( * Subtarget , true ) ; int64_t D = <NUM_LIT> << ( NumBits - <NUM_LIT> ) ; RemainderOffset = ( COffsetVal / D ) * D ; ImmField = COffsetVal - RemainderOffset ; assert ( TII -> isLegalFLATOffset ( ImmField , <ISA_LIT>AS :: PRIVATE_ADDRESS , true ) ) ; assert ( RemainderOffset + ImmField == COffsetVal ) ; COffsetVal = ImmField ; SDLoc DL ( N ) ; SDValue AddOffset = getMaterializedScalarImm32 ( Lo_32 ( RemainderOffset ) , DL ) ; SAddr = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , DL , <STR_LIT> , SAddr , AddOffset ) , <NUM_LIT> ) ; } Offset = CurDAG -> getTargetConstant ( COffsetVal , SDLoc ( ) , <STR_LIT> ) ; return true ;


<s> return AlignedBy4 ; } if ( VT . bitsLT ( <STR_LIT> ) ) return false ; if ( IsFast ) * IsFast = true ;

return VT . bitsGT ( <STR_LIT> ) && Align % <NUM_LIT> == <NUM_LIT> ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TM ( TM ) , STI ( STI ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) {


<s> auto Expr = <ISA_LIT>MCExpr :: create ( MCConstantExpr :: create ( MO . getImm ( ) , AP . OutContext ) , AP . OutContext ) ; <ISA_LIT>MCInstrInfo :: setMustExtend ( * Expr , MustExtend ) ; MCO = MCOperand :: createExpr ( Expr ) ; break ; } case MachineOperand :: MO_MachineBasicBlock : { MCExpr const * Expr = MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , AP . OutContext ) ; Expr = <ISA_LIT>MCExpr :: create ( Expr , AP . OutContext ) ; <ISA_LIT>MCInstrInfo :: setMustExtend ( * Expr , MustExtend ) ; MCO = MCOperand :: createExpr ( Expr ) ; break ; } case MachineOperand :: MO_GlobalAddress : MCO = GetSymbolRef ( MO , AP . getSymbol ( MO . getGlobal ( ) ) , AP , MustExtend ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCO = GetSymbolRef ( MO , AP . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) , AP , MustExtend ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCO = GetSymbolRef ( MO , AP . GetJTISymbol ( MO . getIndex ( ) ) , AP , MustExtend ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCO = GetSymbolRef ( MO , AP . GetCPISymbol ( MO . getIndex ( ) ) , AP , MustExtend ) ; break ; case MachineOperand :: MO_BlockAddress : MCO = GetSymbolRef ( MO , AP . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) , AP , MustExtend ) ; break ; } MCI -> addOperand ( MCO ) ; } AP . <ISA_LIT>ProcessInstruction ( * MCI , * MI ) ; <ISA_LIT>MCInstrInfo :: extendIfNeeded ( AP . OutContext , MCII , MCB , * MCI ) ;

MCB . addOperand ( MCOperand :: createInst ( MCI ) ) ;


<s> return ( ( LastFlat [ LGKM_CNT ] > ScoreLBs [ LGKM_CNT ] && LastFlat [ LGKM_CNT ] <= ScoreUBs [ LGKM_CNT ] ) || ( LastFlat [ VM_CNT ] > ScoreLBs [ VM_CNT ] && LastFlat [ VM_CNT ] <= ScoreUBs [ VM_CNT ] ) ) ;


<s> rtx lane ; if ( d -> vec_flags == VEC_SVE_PRED || d -> perm . encoding ( ) . encoded_nelts ( ) != <NUM_LIT> || ! d -> perm [ <NUM_LIT> ] . is_constant ( & elt ) ) return false ; if ( ( d -> vec_flags & VEC_SVE_DATA ) && elt * ( aarch64_sve_container_bits ( vmode ) / <NUM_LIT> ) >= <NUM_LIT> ) return false ; if ( d -> testing_p ) return true ; in0 = d -> op0 ; lane = GEN_INT ( elt ) ; rtx parallel = gen_rtx_PARALLEL ( vmode , gen_rtvec ( <NUM_LIT> , lane ) ) ; rtx select = gen_rtx_VEC_SELECT ( GET_MODE_INNER ( vmode ) , in0 , parallel ) ; emit_set_insn ( out , gen_rtx_VEC_DUPLICATE ( vmode , select ) ) ;


<s> return ( uint16x8_t ) __builtin_neon_vcgeuv8hi ( ( int16x8_t ) __b , ( int16x8_t ) __a ) ;


<s> return PowerOf2Floor ( std :: max < unsigned > ( std :: min < unsigned > ( RVVVectorELENMax , <NUM_LIT> ) , <NUM_LIT> ) ) ;


<s> static DecodeStatus DecodeFixedPointScaleImm64 ( llvm :: MCInst & Inst , unsigned Imm , uint64_t Addr , const void * Decoder ) { Inst . addOperand ( MCOperand :: CreateImm ( <NUM_LIT> - Imm ) ) ; return Success ;


<s> void printThumbLdrLabelOperand ( const MCInst * MI , uint64_t , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { printThumbLdrLabelOperand ( MI , OpNum , STI , O ) ;


<s> DecodeGRRegsRegisterClass ( Inst , Op1 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op4 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op2 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op3 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op5 , Address , Decoder ) ; DecodeGRRegsRegisterClass ( Inst , Op6 , Address , Decoder ) ;


<s> const GlobalVariable * GV = M -> getNamedGlobal ( <STR_LIT> ) ; if ( GV ) { unsigned Offset = allocateLDSGlobal ( M -> getDataLayout ( ) , * GV ) ;


<s> else fn = gen_call_internal ; pattern = fn ( addr , args_size ) ; } else if ( GET_CODE ( result ) == PARALLEL && XVECLEN ( result , <NUM_LIT> ) == <NUM_LIT> ) { rtx ( * fn ) ( rtx , rtx , rtx , rtx ) ; rtx reg1 , reg2 ; if ( type == MIPS_CALL_SIBCALL ) fn = gen_sibcall_value_multiple_internal ; else fn = gen_call_value_multiple_internal ; reg1 = XEXP ( XVECEXP ( result , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ; reg2 = XEXP ( XVECEXP ( result , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ; pattern = fn ( reg1 , addr , args_size , reg2 ) ; } else { rtx ( * fn ) ( rtx , rtx , rtx ) ; if ( type == MIPS_CALL_SIBCALL ) fn = gen_sibcall_value_internal ; else fn = gen_call_value_internal ; if ( GET_CODE ( result ) == PARALLEL && XVECLEN ( result , <NUM_LIT> ) == <NUM_LIT> ) result = XEXP ( XVECEXP ( result , <NUM_LIT> , <NUM_LIT> ) , <NUM_LIT> ) ; pattern = fn ( result , addr , args_size ) ; } return mips_emit_call_insn ( pattern , orig_addr , addr , lazy_p ) ;


<s> bool ImmSigned = is<ISA_LIT>ImmediateSigned ( MID . TSFlags ) ; if ( has<ISA_LIT>Immediate ( MID . TSFlags ) && ImmSigned ) { unsigned ImmOpNo = get<ISA_LIT>ImmediateOpNo ( MID . TSFlags ) ;

unsigned ImmSize = get<ISA_LIT>ImmediateSize ( MID . TSFlags ) ;


<s> rtx p ; if ( D_REG_P ( reg ) ) x_reg = gen_rtx_REG ( SImode , HARD_X_REGNUM ) ; else x_reg = <NUM_LIT> ; for ( p = PREV_INSN ( x ) ; p && GET_CODE ( p ) != CODE_LABEL ; p = PREV_INSN ( p ) ) if ( INSN_P ( p ) ) { rtx body ; body = PATTERN ( p ) ; if ( GET_CODE ( body ) == CALL_INSN ) break ; if ( GET_CODE ( body ) == JUMP_INSN ) break ; if ( GET_CODE ( body ) == SET ) { rtx dst = XEXP ( body , <NUM_LIT> ) ; if ( GET_CODE ( dst ) == REG && REGNO ( dst ) == REGNO ( reg ) ) break ; if ( x_reg && rtx_equal_p ( dst , x_reg ) ) break ; if ( find_regno_note ( p , REG_DEAD , REGNO ( reg ) ) ) return <NUM_LIT> ; } else if ( reg_mentioned_p ( reg , p ) || ( x_reg && reg_mentioned_p ( x_reg , p ) ) ) break ; } for ( p = x ; p ; p = NEXT_INSN ( p ) ) { rtx body ; if ( GET_CODE ( p ) == CODE_LABEL || GET_CODE ( p ) == JUMP_INSN || GET_CODE ( p ) == CALL_INSN || GET_CODE ( p ) == BARRIER ) break ; if ( GET_CODE ( p ) != INSN ) continue ; body = PATTERN ( p ) ; if ( GET_CODE ( body ) == SET ) { rtx src = XEXP ( body , <NUM_LIT> ) ;


<s> case AtomicOrdering :: Release : return <STR_LIT> ; case AtomicOrdering :: AcquireRelease : return <STR_LIT> ; case AtomicOrdering :: SequentiallyConsistent : return <STR_LIT> ; }


<s> if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; if ( Imm & <NUM_LIT> ) EncVal |= <NUM_LIT> ; return ( EncVal << <NUM_LIT> ) | EncVal ;


<s> if ( V2 . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SmallVector < int , <NUM_LIT> > MaskVals ( SVOp -> getMask ( ) . begin ( ) , SVOp -> getMask ( ) . end ( ) ) ;

return getPSHUFB ( MaskVals , V1 , dl , DAG ) ;


<s> unsigned Opc = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) Opc = <STR_LIT> ; assert ( Opc && <STR_LIT> ) ;

BuildMI ( MBB , I , DL , get ( Opc ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> PrintRegSet ( const RegisterSet & S , const TargetRegisterInfo * RI ) : RS ( S ) , TRI ( RI ) {


<s> RegisterAsmPrinter < <ISA_LIT>AsmPrinter > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>ompact32 ) ; if ( MF . getRegInfo ( ) . liveout_empty ( ) ) { for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) if ( RVLocs [ i ] . isRegLoc ( ) ) { MF . getRegInfo ( ) . addLiveOut ( RVLocs [ i ] . getLocReg ( ) ) ; } } SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ;

assert ( VA . isRegLoc ( ) && <STR_LIT> ) ;


<s> break ; case ORDERED : case UNORDERED : case UNGT : case UNLT : case UNEQ : case UNGE : case UNLE : case LTGT : qpfunc = ( TARGET_ARCH64 ? <STR_LIT> : <STR_LIT> ) ; break ; default : gcc_unreachable ( ) ; } if ( TARGET_ARCH64 ) { if ( MEM_P ( x ) ) { tree expr = MEM_EXPR ( x ) ; if ( expr ) mark_addressable ( expr ) ; slot0 = x ; } else { slot0 = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; emit_move_insn ( slot0 , x ) ; } if ( MEM_P ( y ) ) { tree expr = MEM_EXPR ( y ) ; if ( expr ) mark_addressable ( expr ) ; slot1 = y ; } else { slot1 = assign_stack_temp ( TFmode , GET_MODE_SIZE ( TFmode ) ) ; emit_move_insn ( slot1 , y ) ; } libfunc = gen_rtx_SYMBOL_REF ( Pmode , qpfunc ) ; emit_library_call ( libfunc , LCT_NORMAL , DImode , XEXP ( slot0 , <NUM_LIT> ) , Pmode , XEXP ( slot1 , <NUM_LIT> ) , Pmode ) ; mode = DImode ; } else {


<s> } } if ( ! SrcReg ) SrcReg = getRegForValue ( Op0 ) ; if ( ! SrcReg ) return false ; auto * SI = cast < StoreInst > ( I ) ; if ( SI -> isAtomic ( ) ) { AtomicOrdering Ord = SI -> getOrdering ( ) ; if ( isReleaseOrStronger ( Ord ) ) { unsigned AddrReg = getRegForValue ( PtrV ) ; return emitStoreRelease ( VT , SrcReg , AddrReg , createMachineMemOperandFor ( I ) ) ; } } Address Addr ; if ( ! computeAddress ( PtrV , Addr , Op0 -> getType ( ) ) ) return false ; if ( ! emitStore ( VT , SrcReg , Addr , createMachineMemOperandFor ( I ) ) ) return false ;


<s> auto VRegAndVal = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; if ( ! VRegAndVal ) { std :: swap ( ConstantReg , TestReg ) ; VRegAndVal = getConstantVRegValWithLookThrough ( ConstantReg , MRI ) ; } if ( VRegAndVal ) { if ( HasZext ) C = VRegAndVal -> Value . getZExtValue ( ) ; else C = VRegAndVal -> Value . getSExtValue ( ) ; } break ; } case TargetOpcode :: G_ASHR : case TargetOpcode :: G_LSHR : case TargetOpcode :: G_SHL : { TestReg = MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; auto VRegAndVal = getConstantVRegValWithLookThrough ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , MRI ) ; if ( VRegAndVal ) C = VRegAndVal -> Value . getSExtValue ( ) ; break ; } } if ( ! C || ! TestReg . isValid ( ) ) break ; Register NextReg ; unsigned TestRegSize = MRI . getType ( TestReg ) . getSizeInBits ( ) ; switch ( Opc ) { default : break ; case TargetOpcode :: G_AND : if ( ( * C >> Bit ) & <NUM_LIT> ) NextReg = TestReg ; break ; case TargetOpcode :: G_SHL : if ( * C <= Bit && ( Bit - * C ) < TestRegSize ) { NextReg = TestReg ; Bit = Bit - * C ; } break ; case TargetOpcode :: G_ASHR : NextReg = TestReg ; Bit = Bit + * C ; if ( Bit >= TestRegSize ) Bit = TestRegSize - <NUM_LIT> ; break ; case TargetOpcode :: G_LSHR : if ( ( Bit + * C ) < TestRegSize ) { NextReg = TestReg ; Bit = Bit + * C ; } break ; case TargetOpcode :: G_XOR :

if ( ( * C >> Bit ) & <NUM_LIT> ) Invert = ! Invert ;


<s> void <ISA_LIT>GNULDBackend :: addNonPICBranchSym ( ResolveInfo * rsym ) { m_HasNonPICBranchSyms . insert ( rsym ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : const MachineOperand * BaseOp ; unsigned Width ; OffsetIsScalable = false ; if ( ! getMemOperandWithOffsetWidth ( LdSt , BaseOp , Offset , Width , TRI ) ) return false ; BaseOps . push_back ( BaseOp ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectGEP ( Register ResVReg , const <ISA_LIT>Type * ResType , MachineInstr & I ) const { unsigned Opcode = I . getOperand ( <NUM_LIT> ) . getImm ( ) ? <STR_LIT> : <STR_LIT> ; auto Res = BuildMI ( * I . getParent ( ) , I , I . getDebugLoc ( ) , TII . get ( Opcode ) ) . addDef ( ResVReg ) . addUse ( GR . get<ISA_LIT>TypeID ( ResType ) ) . addUse ( I . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; for ( unsigned i = <NUM_LIT> ; i < I . getNumExplicitOperands ( ) ; ++ i ) Res . addUse ( I . getOperand ( i ) . getReg ( ) ) ; return Res . constrainAllUses ( TII , TRI , RBI ) ;


__asm__ ( <STR_LIT> : <STR_LIT> ( result ) : <STR_LIT> ( a ) , <STR_LIT> ( b ) : ) ;


<s> TargetLowering :: ArgListEntry Entry ; Entry . Ty = DAG . getDataLayout ( ) . getIntPtrType ( * DAG . getContext ( ) ) ; Entry . Node = Dst ; Args . push_back ( Entry ) ; Entry . Node = Src ; Args . push_back ( Entry ) ; Entry . Node = Size ; Args . push_back ( Entry ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( Chain ) . setCallee ( TLI . getLibcallCallingConv ( RTLIB :: MEMCPY ) , Type :: getVoidTy ( * DAG . getContext ( ) ) , DAG . getExternalSymbol ( <STR_LIT> , TLI . getPointerTy ( DAG . getDataLayout ( ) ) ) , std :: move ( Args ) , <NUM_LIT> ) . setDiscardResult ( ) ; std :: pair < SDValue , SDValue > CallResult = TLI . LowerCallTo ( CLI ) ;


<s> const <ISA_LIT>InstrInfo * TII = ST . getInstrInfo ( ) ; MachineBasicBlock * MBB = MI -> getParent ( ) ; const DebugLoc & DL = MI -> getDebugLoc ( ) ; bool IsStore = MI -> mayStore ( ) ; unsigned Opc = MI -> getOpcode ( ) ; int LoadStoreOp = IsStore ? getOffsetMUBUFStore ( Opc ) : getOffsetMUBUFLoad ( Opc ) ; if ( LoadStoreOp == - <NUM_LIT> ) return false ; const MachineOperand * Reg = TII -> getNamedOperand ( * MI , <STR_LIT> :: vdata ) ;

if ( spillVGPRtoAGPR ( ST , MI , Index , <NUM_LIT> , Reg -> getReg ( ) , false ) . getInstr ( ) ) return true ;


<s> for ( const <STR_LIT> & Out : Outs ) { assert ( ! Out . Flags . isByVal ( ) && <STR_LIT> ) ; assert ( ! Out . Flags . isNest ( ) && <STR_LIT> ) ; assert ( Out . IsFixed && <STR_LIT> ) ; if ( Out . Flags . isInAlloca ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInConsecutiveRegs ( ) ) fail ( DL , DAG , <STR_LIT> ) ; if ( Out . Flags . isInConsecutiveRegsLast ( ) ) fail ( DL , DAG , <STR_LIT> ) ;


addRegOrImmWithInputModsOperands ( Inst , N ) ;