<s> static void adjustBranch ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) {

unsigned_width ( Size + <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ;


<s> static void adjustBranch ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) { unsigned_width ( Size + <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ;

<STR_LIT> :: adjustBranchTarget ( Value ) ;


<s> case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: hh8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: ldi :: ms8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: lo8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: hi8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: hh8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: ms8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ; Value &= <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; adjust :: unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ; Value &= <NUM_LIT> ; break ; case <STR_LIT> : adjust :: fixup_6 ( Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: fixup_6_adiw ( Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: fixup_port5 ( Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: fixup_port6 ( Fixup , Value , Ctx ) ; break ; case FK_Data_1 : case FK_Data_2 :


<s> break ; case <STR_LIT> : adjust :: ldi :: lo8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : adjust :: pm ( Value ) ; adjust :: ldi :: lo8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: ldi :: hi8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : adjust :: pm ( Value ) ; adjust :: ldi :: hi8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: hh8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: ldi :: ms8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: lo8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: hi8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : case <STR_LIT> : if ( Kind == <STR_LIT> ) adjust :: pm ( Value ) ; adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: hh8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: ldi :: neg ( Value ) ; adjust :: ldi :: ms8 ( Size , Fixup , Value , Ctx ) ; break ; case <STR_LIT> : adjust :: unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ; Value &= <NUM_LIT> ; break ; case <STR_LIT> : Value >>= <NUM_LIT> ; adjust :: unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ; Value &= <NUM_LIT> ; break ; case <STR_LIT> : adjust :: fixup_6 ( Fixup , Value , Ctx ) ; break ;


<s> static void adjustRelativeBranch ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) { signed_width ( Size + <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ;


<s> if ( Value == <NUM_LIT> ) return ; MCFixupKindInfo Info = getFixupKindInfo ( Fixup . getKind ( ) ) ; auto NumBits = Info . TargetSize + Info . TargetOffset ; auto NumBytes = ( NumBits / <NUM_LIT> ) + ( ( NumBits % <NUM_LIT> ) == <NUM_LIT> ? <NUM_LIT> : <NUM_LIT> ) ; Value <<= Info . TargetOffset ; unsigned Offset = Fixup . getOffset ( ) ; assert ( Offset + NumBytes <= Data . size ( ) && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> ; i < NumBytes ; ++ i ) { uint8_t mask = ( ( ( Value >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ) ) ; Data [ Offset + i ] |= mask ; }


<s> std :: unique_ptr < MCObjectTargetWriter > <ISA_LIT>AsmBackend :: createObjectTargetWriter ( ) const {

return create<ISA_LIT>ELFObjectWriter ( MCELFObjectTargetWriter :: getOSABI ( OSType ) ) ;


<s> static void fixup ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) { uint64_t upper = Value & <NUM_LIT> ; uint64_t lower = Value & <NUM_LIT> ; Value = ( upper << <NUM_LIT> ) | lower ;


<s> uint64_t lower = Value & <NUM_LIT> ;

Value = ( upper << <NUM_LIT> ) | lower ;


<s> adjustRelativeBranch ( Size , Fixup , Value , Ctx ) ; Value &= <NUM_LIT> ;


<s> unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ;

Value = ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ;


<s> Value = ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ;


<s> unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ; Value = ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ;


<s> static void fixup_6_adiw ( const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) { unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ;

Value = ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ;


<s> adjustRelativeBranch ( Size , Fixup , Value , Ctx ) ;


<s> static void fixup_port5 ( const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) { unsigned_width ( <NUM_LIT> , Value , std :: string ( <STR_LIT> ) , Fixup , Ctx ) ;


<s> Value = ( ( Value & <NUM_LIT> ) << <NUM_LIT> ) | ( Value & <NUM_LIT> ) ;


<s> unsigned getNumFixupKinds ( ) const override { return <STR_LIT> ;


<s> Value = ( Value & <NUM_LIT> ) >> <NUM_LIT> ;

ldi :: fixup ( Size , Fixup , Value , Ctx ) ;


<s> static void lo8 ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) { Value &= <NUM_LIT> ; ldi :: fixup ( Size , Fixup , Value , Ctx ) ;


<s> static void lo8 ( unsigned Size , const MCFixup & Fixup , uint64_t & Value , MCContext * Ctx = nullptr ) {


<s> <ISA_LIT>AsmBackend ( Triple :: OSType OSType ) : MCAsmBackend ( <STR_LIT> ) , OSType ( OSType ) {


<s> Value = ( Value & <NUM_LIT> ) >> <NUM_LIT> ; ldi :: fixup ( Size , Fixup , Value , Ctx ) ;


<s> switch ( ( unsigned ) Fixup . getKind ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> if ( ! isIntN ( Width , Value ) ) { std :: string Diagnostic = <STR_LIT> + Description ; int64_t Min = minIntN ( Width ) ; int64_t Max = maxIntN ( Width ) ; Diagnostic += <STR_LIT> + std :: to_string ( Min ) + <STR_LIT> + std :: to_string ( Max ) + <STR_LIT> ; if ( Ctx ) { Ctx -> reportFatalError ( Fixup . getLoc ( ) , Diagnostic ) ; } else { llvm_unreachable ( Diagnostic . c_str ( ) ) ; } }


<s> Diagnostic += <STR_LIT> + std :: to_string ( Max ) + <STR_LIT> ; if ( Ctx ) { Ctx -> reportFatalError ( Fixup . getLoc ( ) , Diagnostic ) ; } else {

llvm_unreachable ( Diagnostic . c_str ( ) ) ;


<s> static void unsigned_width ( unsigned Width , uint64_t Value , std :: string Description , const MCFixup & Fixup , MCContext * Ctx = nullptr ) { if ( ! isUIntN ( Width , Value ) ) { std :: string Diagnostic = <STR_LIT> + Description ; int64_t Max = maxUIntN ( Width ) ; Diagnostic += <STR_LIT> + std :: to_string ( Max ) + <STR_LIT> ; if ( Ctx ) {

Ctx -> reportFatalError ( Fixup . getLoc ( ) , Diagnostic ) ;


<s> assert ( ( Count % <NUM_LIT> ) == <NUM_LIT> && <STR_LIT> ) ; OS . write_zeros ( Count ) ; return true ;


<s> else if ( const MCConstantExpr * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;

else Inst . addOperand ( MCOperand :: createExpr ( Expr ) ) ;


<s> const auto * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( ~ ( uint8_t ) CE -> getValue ( ) ) ) ;


<s> void addImmCom8Operands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ; const auto * CE = cast < MCConstantExpr > ( getImm ( ) ) ; Inst . addOperand ( MCOperand :: createImm ( ~ ( uint8_t ) CE -> getValue ( ) ) ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ; addExpr ( Inst , getImm ( ) ) ;


<s> assert ( Kind == k_Register && <STR_LIT> ) ; assert ( N == <NUM_LIT> && <STR_LIT> ) ;

Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> assert ( Kind == k_Register && <STR_LIT> ) ; assert ( N == <NUM_LIT> && <STR_LIT> ) ; Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> return std :: make_unique < <ISA_LIT>Operand > ( Val , S , E ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateImm ( const MCExpr * Val , SMLoc S , SMLoc E ) {

return std :: make_unique < <ISA_LIT>Operand > ( Val , S , E ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateMemri ( unsigned RegNum , const MCExpr * Val , SMLoc S , SMLoc E ) {

return std :: make_unique < <ISA_LIT>Operand > ( RegNum , Val , S , E ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > CreateReg ( unsigned RegNum , SMLoc S , SMLoc E ) { return std :: make_unique < <ISA_LIT>Operand > ( RegNum , S , E ) ;


<s> void <ISA_LIT>AsmParser :: eatComma ( ) { if ( getLexer ( ) . is ( AsmToken :: Comma ) ) { Parser . Lex ( ) ; } else { }


<s> Inst . setLoc ( Loc ) ; Out . emitInstruction ( Inst , STI ) ; return false ;


<s> bool <ISA_LIT>AsmParser :: emit ( MCInst & Inst , SMLoc const & Loc , MCStreamer & Out ) const { Inst . setLoc ( Loc ) ; Out . emitInstruction ( Inst , STI ) ; return false ;


<s> SMLoc getEndLoc ( ) const override {


<s> const MCExpr * getImm ( ) const { assert ( ( Kind == k_Immediate || Kind == k_Memri ) && <STR_LIT> ) ;


<s> MCAsmLexer & getLexer ( ) const { return Parser . getLexer ( ) ;


<s> assert ( ( Kind == k_Register || Kind == k_Memri ) && <STR_LIT> ) ;


<s> assert ( Kind == k_Token && <STR_LIT> ) ; return Tok ;


<s> } else { <ISA_LIT>Operand const & Op = ( <ISA_LIT>Operand const & ) * Operands [ ErrorInfo ] ; if ( Op . getStartLoc ( ) != SMLoc ( ) ) { ErrorLoc = Op . getStartLoc ( ) ; } }


<s> if ( ! isImm ( ) ) return false ; const auto * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ;


<s> bool isImmCom8 ( ) const { if ( ! isImm ( ) ) return false ; const auto * CE = dyn_cast < MCConstantExpr > ( getImm ( ) ) ; if ( ! CE ) return false ;


<s> bool isReg ( ) const override { return Kind == k_Register ;


<s> bool isToken ( ) const override { return Kind == k_Token ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmParser ( ) { RegisterMCAsmParser < <ISA_LIT>AsmParser > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> void makeImm ( MCExpr const * Ex ) { Kind = k_Immediate ;


<s> Kind = k_Immediate ; RegImm = { <NUM_LIT> , Ex } ;


<s> void makeToken ( StringRef Token ) {


<s> void makeToken ( StringRef Token ) { Kind = k_Token ; Tok = Token ;


<s> case Match_Success : return emit ( Inst , Loc , Out ) ; case Match_MissingFeature : return missingFeature ( Loc , ErrorInfo ) ; case Match_InvalidOperand : return invalidOperand ( Loc , Operands , ErrorInfo ) ; case Match_MnemonicFail : return Error ( Loc , <STR_LIT> ) ; default : return true ;


<s> MCAsmParserExtension :: Initialize ( Parser ) ; MRI = getContext ( ) . getRegisterInfo ( ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ;


<s> <ISA_LIT>Operand ( unsigned Reg , MCExpr const * Imm , SMLoc const & S , SMLoc const & E ) : Base ( ) , Kind ( k_Memri ) , RegImm ( { Reg , Imm ) , Start ( S ) , End ( E ) {


<s> } else if ( IDVal . lower ( ) == <STR_LIT> || IDVal . lower ( ) == <STR_LIT> ) { parseLiteralValues ( SIZE_WORD , DirectiveID . getLoc ( ) ) ;

} else if ( IDVal . lower ( ) == <STR_LIT> ) {


<s> bool <ISA_LIT>AsmParser :: ParseDirective ( llvm :: AsmToken DirectiveID ) { StringRef IDVal = DirectiveID . getIdentifier ( ) ; if ( IDVal . lower ( ) == <STR_LIT> ) { parseLiteralValues ( SIZE_LONG , DirectiveID . getLoc ( ) ) ;

} else if ( IDVal . lower ( ) == <STR_LIT> || IDVal . lower ( ) == <STR_LIT> ) {


<s> while ( getLexer ( ) . isNot ( AsmToken :: EndOfStatement ) ) { if ( ! first ) eatComma ( ) ; first = false ; auto MatchResult = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( MatchResult == MatchOperand_Success ) { continue ; } if ( MatchResult == MatchOperand_ParseFail ) {


<s> } if ( Parser . getTok ( ) . getKind ( ) == AsmToken :: Identifier && Parser . getLexer ( ) . peekTok ( ) . getKind ( ) == AsmToken :: LParen ) { StringRef ModifierName = Parser . getTok ( ) . getString ( ) ; <ISA_LIT>MCExpr :: VariantKind ModifierKind = <ISA_LIT>MCExpr :: getKindByName ( ModifierName . str ( ) . c_str ( ) ) ; if ( ModifierKind != <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { Parser . Lex ( ) ; Parser . Lex ( ) ; } else { return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; } MCSymbol * Symbol = getContext ( ) . getOrCreateSymbol ( Parser . getTok ( ) . getString ( ) ) ; <ISA_LIT>Streamer . emitValueForModiferKind ( Symbol , SizeInBytes , L , ModifierKind ) ; return false ; }


<s> } { if ( getParser ( ) . parseExpression ( Expression ) ) return MatchOperand_ParseFail ; E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; } Operands . push_back ( <STR_LIT> ( RegNo , Expression , S , E ) ) ;


<s> bool <ISA_LIT>AsmParser :: parseOperand ( OperandVector & Operands ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; switch ( getLexer ( ) . getKind ( ) ) { default : return Error ( Parser . getTok ( ) . getLoc ( ) , <STR_LIT> ) ; case AsmToken :: Identifier : if ( ! tryParseRegisterOperand ( Operands ) ) { return false ; } LLVM_FALLTHROUGH ; case AsmToken :: LParen : case AsmToken :: Integer : case AsmToken :: Dot : return tryParseExpression ( Operands ) ; case AsmToken :: Plus : case AsmToken :: Minus : {

switch ( getLexer ( ) . peekTok ( ) . getKind ( ) ) {


<s> StartLoc = Parser . getTok ( ) . getLoc ( ) ; RegNo = parseRegister ( false ) ; EndLoc = Parser . getTok ( ) . getLoc ( ) ;


<s> int <ISA_LIT>AsmParser :: parseRegisterName ( ) { int RegNum = parseRegisterName ( & MatchRegisterName ) ;

if ( RegNum == <STR_LIT> ) RegNum = parseRegisterName ( & MatchRegisterAltName ) ;


<s> int RegNum = parseRegisterName ( & MatchRegisterName ) ; if ( RegNum == <STR_LIT> ) RegNum = parseRegisterName ( & MatchRegisterAltName ) ;


<s> case k_Register : O << <STR_LIT> << getReg ( ) ; break ; case k_Immediate : O << <STR_LIT> << * getImm ( ) << <STR_LIT> ; break ; case k_Memri : { O << <STR_LIT> << getReg ( ) << '+' << * getImm ( ) << <STR_LIT> ; break ; } }


<s> break ; case k_Register : O << <STR_LIT> << getReg ( ) ; break ; case k_Immediate : O << <STR_LIT> << * getImm ( ) << <STR_LIT> ; break ; case k_Memri : { O << <STR_LIT> << getReg ( ) << '+' << * getImm ( ) << <STR_LIT> ;


<s> return MRI -> getMatchingSuperReg ( Reg , From , Class ) ;


<s> return true ; } MCExpr const * Expression ; if ( getParser ( ) . parseExpression ( Expression ) ) return true ; SMLoc E = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ;

Operands . push_back ( <STR_LIT> ( Expression , S , E ) ) ;


<s> RegNo = parseRegister ( true ) ; EndLoc = Parser . getTok ( ) . getLoc ( ) ;

if ( RegNo == <STR_LIT> ) return MatchOperand_NoMatch ;


<s> AsmToken const & T = Parser . getTok ( ) ; Operands . push_back ( <STR_LIT> ( RegNo , T . getLoc ( ) , T . getEndLoc ( ) ) ) ; Parser . Lex ( ) ;


<s> bool <ISA_LIT>AsmParser :: tryParseRegisterOperand ( OperandVector & Operands ) { int RegNo = parseRegister ( ) ; if ( RegNo == <STR_LIT> ) return true ; AsmToken const & T = Parser . getTok ( ) ; Operands . push_back ( <STR_LIT> ( RegNo , T . getLoc ( ) , T . getEndLoc ( ) ) ) ; Parser . Lex ( ) ;


<s> <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( AsmOp ) ; MatchClassKind Expected = static_cast < MatchClassKind > ( ExpectedKind ) ; if ( Op . isImm ( ) ) { if ( MCConstantExpr const * Const = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) { int64_t RegNum = Const -> getValue ( ) ; std :: ostringstream RegName ; RegName << <STR_LIT> << RegNum ; RegNum = MatchRegisterName ( RegName . str ( ) . c_str ( ) ) ; if ( RegNum != <STR_LIT> ) { Op . makeReg ( RegNum ) ; if ( validateOperandClass ( Op , Expected ) == Match_Success ) { return Match_Success ; } } } } if ( Op . isReg ( ) ) { if ( isSubclass ( Expected , MCK_DREGS ) ) { unsigned correspondingDREG = toDREG ( Op . getReg ( ) ) ; if ( correspondingDREG != <STR_LIT> ) { Op . makeReg ( correspondingDREG ) ;

return validateOperandClass ( Op , Expected ) ;


<s> MatchClassKind Expected = static_cast < MatchClassKind > ( ExpectedKind ) ; if ( Op . isImm ( ) ) { if ( MCConstantExpr const * Const = dyn_cast < MCConstantExpr > ( Op . getImm ( ) ) ) { int64_t RegNum = Const -> getValue ( ) ; std :: ostringstream RegName ; RegName << <STR_LIT> << RegNum ; RegNum = MatchRegisterName ( RegName . str ( ) . c_str ( ) ) ; if ( RegNum != <STR_LIT> ) { Op . makeReg ( RegNum ) ; if ( validateOperandClass ( Op , Expected ) == Match_Success ) { return Match_Success ;


<s> <ISA_LIT>MCInstLower MCInstLowering ( OutContext , * this ) ; MCInst I ; MCInstLowering . lowerInstruction ( * MI , I ) ; EmitToStreamer ( * OutStreamer , I ) ;


MCInstLowering . lowerInstruction ( * MI , I ) ;


<s> StringRef getPassName ( ) const override {


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmPrinter ( ) { llvm :: RegisterAsmPrinter < llvm :: <ISA_LIT>AsmPrinter > X ( llvm :: getThe<ISA_LIT>Target ( ) ) ;


<s> if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { bool IsProgMem = GV -> getAddressSpace ( ) == <STR_LIT> ; if ( IsProgMem ) { const MCExpr * Expr = MCSymbolRefExpr :: create ( getSymbol ( GV ) , Ctx ) ; return <ISA_LIT>MCExpr :: create ( <ISA_LIT>MCExpr :: VK_<ISA_LIT>_PM , Expr , false , Ctx ) ; } }

return AsmPrinter :: lowerConstant ( CV ) ;


<s> MCContext & Ctx = OutContext ; if ( const GlobalValue * GV = dyn_cast < GlobalValue > ( CV ) ) { bool IsProgMem = GV -> getAddressSpace ( ) == <STR_LIT> ;


<s> <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MRI ( * TM . getMCRegisterInfo ( ) ) {


<s> ( void ) MO ; assert ( MO . isReg ( ) && <STR_LIT> ) ; if ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> ) { O << <STR_LIT> ; } else { assert ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> O << <STR_LIT> ; } else { assert ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; O << <STR_LIT> ; } unsigned OpFlags = MI -> getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) ; unsigned NumOpRegs = InlineAsm :: getNumOperandRegisters ( OpFlags ) ; if ( NumOpRegs == <NUM_LIT> ) { O << '+' << MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ; }


<s> switch ( MO . getType ( ) ) { case MachineOperand :: MO_Register : O << <ISA_LIT>InstPrinter :: getPrettyRegisterName ( MO . getReg ( ) , MRI ) ; break ; case MachineOperand :: MO_Immediate : O << MO . getImm ( ) ; break ; case MachineOperand :: MO_GlobalAddress :


<s> case MachineOperand :: MO_GlobalAddress : O << getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; }


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( Field << <NUM_LIT> ) ) ;


<s> static DecodeStatus decodeFFMULRdRr ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned d = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; unsigned r = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ;

if ( DecodeGPR8RegisterClass ( Inst , r , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ;


<s> if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( DecodeGPR8RegisterClass ( Inst , r , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ;


<s> unsigned b = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; Inst . addOperand ( MCOperand :: createImm ( addr ) ) ;

Inst . addOperand ( MCOperand :: createImm ( b ) ) ;


<s> unsigned addr = <NUM_LIT> ; addr |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; addr |= fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) << <NUM_LIT> ; unsigned reg = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ; if ( DecodeGPR8RegisterClass ( Inst , reg , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( addr ) ) ; return MCDisassembler :: Success ;


<s> if ( decodeFRd ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;


<s> static DecodeStatus decodeFLPMX ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { if ( decodeFRd ( Inst , Insn , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createReg ( <STR_LIT> ) ) ;


<s> static DecodeStatus decodeFMOVWRdRr ( MCInst & Inst , unsigned Insn , uint64_t Address , const void * Decoder ) { unsigned r = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) * <NUM_LIT> ; unsigned d = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) * <NUM_LIT> ; if ( DecodeGPR8RegisterClass ( Inst , r , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; return MCDisassembler :: Success ;


<s> unsigned rr = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) + <NUM_LIT> ; if ( DecodeGPR8RegisterClass ( Inst , rd , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ;

if ( DecodeGPR8RegisterClass ( Inst , rr , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ;


<s> unsigned d = fieldFromInstruction ( Insn , <NUM_LIT> , <NUM_LIT> ) ;

if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ;


<s> if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ;


<s> if ( DecodeGPR8RegisterClass ( Inst , d , Address , Decoder ) == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( k ) ) ;


<s> unsigned Register = GPRDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> static DecodeStatus DecodeGPR8RegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GPRDecoderTable [ RegNo ] ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GPRDecoderTable [ RegNo + <NUM_LIT> ] ;


<s> unsigned Register = GPRDecoderTable [ RegNo + <NUM_LIT> ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> static DecodeStatus DecodePTRREGSRegisterClass ( MCInst & Inst , unsigned RegNo , uint64_t Address , const void * Decoder ) {


<s> static const uint8_t * getDecoderTable ( uint64_t Size ) { switch ( Size ) { case <NUM_LIT> : return DecoderTable16 ; case <NUM_LIT> : return DecoderTable32 ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> static const uint8_t * getDecoderTable ( uint64_t Size ) {


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result ; { Result = readInstruction16 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } { Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { return Result ; } return MCDisassembler :: Fail ; }


<s> DecodeStatus <ISA_LIT>Disassembler :: getInstruction ( MCInst & Instr , uint64_t & Size , ArrayRef < uint8_t > Bytes , uint64_t Address , raw_ostream & CStream ) const { uint32_t Insn ; DecodeStatus Result ; { Result = readInstruction16 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) return Result ; } { Result = readInstruction32 ( Bytes , Address , Size , Insn ) ; if ( Result == MCDisassembler :: Fail ) return MCDisassembler :: Fail ; Result = decodeInstruction ( getDecoderTable ( Size ) , Instr , Insn , Address , this , STI ) ; if ( Result != MCDisassembler :: Fail ) { return Result ; } return MCDisassembler :: Fail ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Disassembler ( ) {

TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> Size = <NUM_LIT> ; Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Size = <NUM_LIT> ;

Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ;


<s> Size = <NUM_LIT> ; return MCDisassembler :: Fail ; } Size = <NUM_LIT> ; Insn = ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) | ( Bytes [ <NUM_LIT> ] << <NUM_LIT> ) ; return MCDisassembler :: Success ;


<s> virtual ~ <ISA_LIT>Disassembler ( ) {


<s> return ELF :: R_<ISA_LIT>_13_PCREL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_16 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_16_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI_PM ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI_PM_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HI8_LDI_PM_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_HH8_LDI_PM_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_CALL ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_6 ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_6_ADIW ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MS8_LDI ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_MS8_LDI_NEG ; case <STR_LIT> : return ELF :: R_<ISA_LIT>_LO8_LDI_GS ; case <STR_LIT> :


<s> <ISA_LIT>ELFObjectWriter :: <ISA_LIT>ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_IAMCU , true ) {


<s> virtual ~ <ISA_LIT>ELFObjectWriter ( ) {


<s> else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_<ISA_LIT>5 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_<ISA_LIT>51 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_<ISA_LIT>6 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_<ISA_LIT>TINY ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_XMEGA1 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_XMEGA2 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_XMEGA3 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_XMEGA4 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_XMEGA5 ; else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_XMEGA6 ;

else if ( Features [ <STR_LIT> ] ) EFlags |= ELF :: EF_<ISA_LIT>_ARCH_XMEGA7 ;


return static_cast < MCELFStreamer & > ( Streamer ) ;


<s> return static_cast < MCELFStreamer & > ( Streamer ) ;


<s> EFlags |= getEFlagsForFeatureSet ( STI . getFeatureBits ( ) ) ; MCA . setELFHeaderEFlags ( EFlags ) ;


<s> <ISA_LIT>ELFStreamer :: <ISA_LIT>ELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : <ISA_LIT>TargetStreamer ( S ) {

MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ;


<s> MachineInstrBuilder buildMI ( Block & MBB , BlockIt MBBI , unsigned Opcode , Register DstReg ) {

return BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( Opcode ) , DstReg ) ;


<s> return BuildMI ( MBB , MBBI , MBBI -> getDebugLoc ( ) , TII -> get ( Opcode ) , DstReg ) ;


<s> FunctionPass * create<ISA_LIT>ExpandPseudoPass ( ) { return new <ISA_LIT>ExpandPseudo ( ) ;


<s> TRI -> splitReg ( SrcReg , SrcLoReg , SrcHiReg ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , OpLo ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcLoReg , getKillRegState ( SrcIsKill ) ) ; auto MIBHI = buildMI ( MBB , MBBI , OpHi ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcHiReg , getKillRegState ( SrcIsKill ) ) ; if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MIBHI -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ; MI . eraseFromParent ( ) ; return true ;


<s> Register SrcLoReg , SrcHiReg , DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( SrcReg , SrcLoReg , SrcHiReg ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ;

buildMI ( MBB , MBBI , OpLo ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcLoReg , getKillRegState ( SrcIsKill ) ) ;


<s> buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define , getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; auto MIBHI = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MI . eraseFromParent ( ) ; return true ;


<s> bool <ISA_LIT>ExpandPseudo :: expandAtomic ( Block & MBB , BlockIt MBBI , Func f ) { MachineInstr & MI = * MBBI ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( SCRATCH_REGISTER , RegState :: Define ) . addImm ( SREG_ADDR ) ;

buildMI ( MBB , MBBI , <STR_LIT> ) . addImm ( <NUM_LIT> ) ;


<s> return expandAtomic ( MBB , MBBI , [ & ] ( MachineInstr & MI ) { auto DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; auto PtrOp = MI . getOperand ( <NUM_LIT> ) ; auto SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoadOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned StoreOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; buildMI ( MBB , MBBI , LoadOpcode , DstReg ) . addReg ( PtrOp . getReg ( ) ) ;

buildMI ( MBB , MBBI , ArithOpcode , DstReg ) . addReg ( DstReg ) . addReg ( SrcReg ) ;


<s> auto SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LoadOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; unsigned StoreOpcode = ( Width == <NUM_LIT> ) ? <STR_LIT> : <STR_LIT> ; buildMI ( MBB , MBBI , LoadOpcode , DstReg ) . addReg ( PtrOp . getReg ( ) ) ;


<s> bool <ISA_LIT>ExpandPseudo :: expandAtomicBinaryOp ( unsigned Opcode , Block & MBB , BlockIt MBBI ) {

return expandAtomicBinaryOp ( Opcode , MBB , MBBI , [ ] ( MachineInstr & MI ) { } ) ;


<s> expandLogic ( unsigned Op , Block & MBB , BlockIt MBBI ) { MachineInstr & MI = * MBBI ; Register SrcLoReg , SrcHiReg , DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( SrcReg , SrcLoReg , SrcHiReg ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ;

auto MIBLO = buildMI ( MBB , MBBI , Op ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcLoReg , getKillRegState ( SrcIsKill ) ) ;


<s> TRI -> splitReg ( SrcReg , SrcLoReg , SrcHiReg ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; auto MIBLO = buildMI ( MBB , MBBI , Op ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcLoReg , getKillRegState ( SrcIsKill ) ) ; MIBLO -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;

auto MIBHI = buildMI ( MBB , MBBI , Op ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( SrcHiReg , getKillRegState ( SrcIsKill ) ) ;


<s> expandLogicImm ( unsigned Op , Block & MBB , BlockIt MBBI ) { MachineInstr & MI = * MBBI ; Register DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Lo8 = Imm & <NUM_LIT> ;

unsigned Hi8 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ;


<s> bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; unsigned Imm = MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned Lo8 = Imm & <NUM_LIT> ; unsigned Hi8 = ( Imm >> <NUM_LIT> ) & <NUM_LIT> ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; if ( ! isLogicImmOpRedundant ( Op , Lo8 ) ) { auto MIBLO = buildMI ( MBB , MBBI , Op ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( SrcIsKill ) ) . addImm ( Lo8 ) ;

MIBLO -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIRRC -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MIRRC -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ; MI . eraseFromParent ( ) ;


<s> bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;

auto MI1 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ;


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI1 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstLoReg ) ; MI1 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI2 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ;

MI2 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI1 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstLoReg ) ; MI1 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI2 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI2 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI3 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstLoReg ) ;

if ( ImpIsDead ) MI3 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;


<s> bool <ISA_LIT>ExpandPseudo :: expandLSLW8Rd ( Block & MBB , BlockIt MBBI ) { MachineInstr & MI = * MBBI ; Register DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ;

TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ;


<s> bool <ISA_LIT>ExpandPseudo :: expandLSLW8Rd ( Block & MBB , BlockIt MBBI ) { MachineInstr & MI = * MBBI ; Register DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ;

buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg ) ;


<s> bool <ISA_LIT>ExpandPseudo :: expandLSRB7Rd ( Block & MBB , BlockIt MBBI ) { MachineInstr & MI = * MBBI ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) -> getOperand ( <NUM_LIT> ) . setIsUndef ( true ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIRRC -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;

MIRRC -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ;


<s> bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) -> getOperand ( <NUM_LIT> ) . setIsUndef ( true ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; auto MIRRC = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) . addReg ( DstReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIRRC -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MIRRC -> getOperand ( <NUM_LIT> ) . setIsKill ( ) ; MI . eraseFromParent ( ) ;


<s> bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MIBHI = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; if ( ImpIsDead ) MIBHI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; MI . eraseFromParent ( ) ;


<s> bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; TRI -> splitReg ( DstReg , DstLoReg , DstHiReg ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) ; buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) ; auto MI0 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ; MI0 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; auto MI1 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstLoReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstLoReg , getKillRegState ( DstIsKill ) ) . addReg ( DstHiReg ) ; MI1 -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;

auto MI2 = buildMI ( MBB , MBBI , <STR_LIT> ) . addReg ( DstHiReg , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( DstHiReg , getKillRegState ( DstIsKill ) ) . addImm ( <NUM_LIT> ) ;


<s> Register DstLoReg , DstHiReg ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool DstIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ; bool DstIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ;

bool ImpIsDead = MI . getOperand ( <NUM_LIT> ) . isDead ( ) ;


<s> bool <ISA_LIT>ExpandPseudo :: expandMBB ( MachineBasicBlock & MBB ) { bool Modified = false ;

BlockIt MBBI = MBB . begin ( ) , E = MBB . end ( ) ;


<s> bool <ISA_LIT>ExpandPseudo :: expandMBB ( MachineBasicBlock & MBB ) { bool Modified = false ; BlockIt MBBI = MBB . begin ( ) , E = MBB . end ( ) ; while ( MBBI != E ) { BlockIt NMBBI = std :: next ( MBBI ) ; Modified |= expandMI ( MBB , MBBI ) ; MBBI = NMBBI ; } return Modified ;


<s> EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; case <STR_LIT> : EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ; EXPAND ( <STR_LIT> ) ;


<s> StringRef getPassName ( ) const override { return <ISA_LIT>_EXPAND_PSEUDO_NAME ;


<s> return <ISA_LIT>_EXPAND_PSEUDO_NAME ;


<s> MachineRegisterInfo & getRegInfo ( Block & MBB ) {

return MBB . getParent ( ) -> getRegInfo ( ) ;


<s> bool <ISA_LIT>ExpandPseudo :: isLogicImmOpRedundant ( unsigned Op , unsigned ImmVal ) const {

if ( Op == <STR_LIT> && ImmVal == <NUM_LIT> ) return true ;


<s> if ( Op == <STR_LIT> && ImmVal == <NUM_LIT> ) return true ; return false ;


<s> <ISA_LIT>ExpandPseudo ( ) : MachineFunctionPass ( ID ) { initialize<ISA_LIT>ExpandPseudoPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> MF . getProperties ( ) . set ( MachineFunctionProperties :: Property :: TracksLiveness ) ; for ( Block & MBB : MF ) { bool ContinueExpanding = true ; unsigned ExpandCount = <NUM_LIT> ; do { assert ( ExpandCount < <NUM_LIT> && <STR_LIT> ) ; bool BlockModified = expandMBB ( MBB ) ; Modified |= BlockModified ; ExpandCount ++ ; ContinueExpanding = BlockModified ; } while ( ContinueExpanding ) ;


<s> MachineBasicBlock & MBB = * MI . getParent ( ) ; RegScavenger RS ; RS . enterBasicBlock ( MBB ) ; RS . forward ( MI ) ; BitVector Candidates = TRI -> getAllocatableSet ( * MBB . getParent ( ) , & <STR_LIT> ) ; for ( MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) && MO . getReg ( ) != <NUM_LIT> && ! MO . isDef ( ) && ! Register :: isVirtualRegister ( MO . getReg ( ) ) ) Candidates . reset ( MO . getReg ( ) ) ; }

BitVector Available = RS . getRegsAvailable ( & <STR_LIT> ) ;


<s> RS . enterBasicBlock ( MBB ) ; RS . forward ( MI ) ; BitVector Candidates = TRI -> getAllocatableSet ( * MBB . getParent ( ) , & <STR_LIT> ) ; for ( MachineOperand & MO : MI . operands ( ) ) { if ( MO . isReg ( ) && MO . getReg ( ) != <NUM_LIT> && ! MO . isDef ( ) && ! Register :: isVirtualRegister ( MO . getReg ( ) ) ) Candidates . reset ( MO . getReg ( ) ) ; }


<s> inline void adjustBranchTarget ( T & val ) { val >>= <NUM_LIT> ;


<s> bool <ISA_LIT>FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const {


<s> FunctionPass * create<ISA_LIT>DynAllocaSRPass ( ) { return new <ISA_LIT>DynAllocaSR ( ) ;


<s> return new <ISA_LIT>FrameAnalyzer ( ) ;


<s> FunctionPass * create<ISA_LIT>FrameAnalyzerPass ( ) {


<s> void <ISA_LIT>FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const {

TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;


<s> if ( hasFP ( MF ) ) { SavedRegs . set ( <STR_LIT> ) ;


<s> MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; fixStackStores ( MBB , MI , TII , <STR_LIT> ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned addOpcode ; if ( isUInt < <NUM_LIT> > ( Amount ) ) { addOpcode = <STR_LIT> ; } else { addOpcode = <STR_LIT> ; Amount = - Amount ; } BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( addOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ;


<s> DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned int Opcode = MI -> getOpcode ( ) ; int Amount = TII . getFrameSize ( * MI ) ; if ( Amount != <NUM_LIT> ) { assert ( getStackAlign ( ) == Align ( <NUM_LIT> ) && <STR_LIT> ) ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; fixStackStores ( MBB , MI , TII , <STR_LIT> ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned addOpcode ; if ( isUInt < <NUM_LIT> > ( Amount ) ) { addOpcode = <STR_LIT> ; } else { addOpcode = <STR_LIT> ; Amount = - Amount ; } BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( addOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ; BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; }


<s> return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ; } unsigned Opcode ; if ( isUInt < <NUM_LIT> > ( FrameSize ) ) { Opcode = <STR_LIT> ; } else { Opcode = <STR_LIT> ; FrameSize = - FrameSize ; } MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( Opcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( FrameSize ) ; MI -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;

BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ;


<s> const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; if ( ! hasFP ( MF ) && ! AFI -> isInterruptOrSignalHandler ( ) ) { return ; } MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> getDesc ( ) . isReturn ( ) && <STR_LIT> ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( ! FrameSize ) { restoreStatusRegister ( MF , MBB ) ; return ; }


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> , RegState :: Kill ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } if ( ! HasFP ) { return ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; while ( ( MBBI != MBB . end ( ) ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && ( MBBI -> getOpcode ( ) == <STR_LIT> || MBBI -> getOpcode ( ) == <STR_LIT> ) ) { ++ MBBI ; } BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; for ( MachineFunction :: iterator I = std :: next ( MF . begin ( ) ) , E = MF . end ( ) ; I != E ; ++ I ) { I -> addLiveIn ( <STR_LIT> ) ; } if ( ! FrameSize ) { return ; }

unsigned Opcode = ( isUInt < <NUM_LIT> > ( FrameSize ) ) ? <STR_LIT> : <STR_LIT> ;


<s> continue ; } assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; unsigned STOpc = ( Opcode == <STR_LIT> ) ? <STR_LIT> : <STR_LIT> ; MI . setDesc ( TII . get ( STOpc ) ) ; MI . getOperand ( <NUM_LIT> ) . setReg ( FP ) ;


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> return ( FuncInfo -> getHasSpills ( ) || FuncInfo -> getHasAllocas ( ) || FuncInfo -> getHasStackArgs ( ) ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

return hasFP ( MF ) && ! MFI . hasVarSizedObjects ( ) ;


<s> return hasFP ( MF ) && ! MFI . hasVarSizedObjects ( ) ;


<s> <ISA_LIT>DynAllocaSR ( ) : MachineFunctionPass ( ID ) {


<s> <ISA_LIT>FrameAnalyzer ( ) : MachineFunctionPass ( ID ) {


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , - <NUM_LIT> ) {


<s> unsigned Reg = CCSI . getReg ( ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ;

BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , Reg ) ;


<s> const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & CCSI : CSI ) { unsigned Reg = CCSI . getReg ( ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ;


<s> BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( <NUM_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) ; }


<s> DebugLoc DL = EntryMBB . findDebugLoc ( MBBI ) ; Register SPCopy = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( EntryMBB , MBBI , DL , TII . get ( <STR_LIT> ) , SPCopy ) . addReg ( <STR_LIT> ) ; for ( MachineBasicBlock & MBB : MF ) { if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ;

BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SPCopy , RegState :: Kill ) ;


<s> unsigned RegLoNum = MRI . getSubReg ( RegNum , <STR_LIT> ) ;

RegNum = ( RegLoNum != <STR_LIT> ) ? RegLoNum : RegNum ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> void <ISA_LIT>InstPrinter :: printMemri ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { assert ( MI -> getOperand ( OpNo ) . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; printOperand ( MI , OpNo , O ) ; if ( OffsetOp . isImm ( ) ) { int64_t Offset = OffsetOp . getImm ( ) ; if ( Offset >= <NUM_LIT> ) O << '+' ; O << Offset ; } else if ( OffsetOp . isExpr ( ) ) { O << * OffsetOp . getExpr ( ) ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> assert ( MI -> getOperand ( OpNo ) . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; printOperand ( MI , OpNo , O ) ; if ( OffsetOp . isImm ( ) ) { int64_t Offset = OffsetOp . getImm ( ) ; if ( Offset >= <NUM_LIT> ) O << '+' ; O << Offset ;


<s> O << <STR_LIT> ; return ; } if ( OpNo >= MI -> size ( ) ) { O << <STR_LIT> ; return ; } const MCOperand & Op = MI -> getOperand ( OpNo ) ; if ( Op . isReg ( ) ) { bool isPtrReg = ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) || ( MOI . RegClass == <STR_LIT> ) ; if ( isPtrReg ) { O << getRegisterName ( Op . getReg ( ) , <STR_LIT> ) ; } else { O << getPrettyRegisterName ( Op . getReg ( ) , MRI ) ; } } else if ( Op . isImm ( ) ) { O << formatImm ( Op . getImm ( ) ) ;


<s> while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) { continue ; } if ( ! isUnpredicatedTerminator ( * I ) ) { break ; } if ( ! I -> getDesc ( ) . isBranch ( ) ) { return true ; } if ( I -> getOpcode ( ) == <STR_LIT> ) { UnCondBrIter = I ; if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) { std :: next ( I ) -> eraseFromParent ( ) ; } Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ;

if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) {


<s> bool <ISA_LIT>InstrInfo :: analyzeBranch ( MachineBasicBlock & MBB , MachineBasicBlock * & TBB , MachineBasicBlock * & FBB , SmallVectorImpl < MachineOperand > & Cond , bool AllowModify ) const { MachineBasicBlock :: iterator I = MBB . end ( ) ; MachineBasicBlock :: iterator UnCondBrIter = MBB . end ( ) ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugInstr ( ) ) { continue ; } if ( ! isUnpredicatedTerminator ( * I ) ) { break ; } if ( ! I -> getDesc ( ) . isBranch ( ) ) { return true ; } if ( I -> getOpcode ( ) == <STR_LIT> ) { UnCondBrIter = I ; if ( ! AllowModify ) { TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } while ( std :: next ( I ) != MBB . end ( ) ) { std :: next ( I ) -> eraseFromParent ( ) ; } Cond . clear ( ) ; FBB = <NUM_LIT> ; if ( MBB . isLayoutSuccessor ( I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ) { TBB = <NUM_LIT> ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; UnCondBrIter = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } <STR_LIT> BranchCode = getCondFromBranchOpc ( I -> getOpcode ( ) ) ; if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = getOppositeCondition ( BranchCode ) ; unsigned JNCC = getBrCond ( BranchCode ) . getOpcode ( ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( JNCC ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; continue ;


<s> unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { if ( STI . hasMOVW ( ) && <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { Register DestLo , DestHi , SrcLo , SrcHi ; TRI . splitReg ( DestReg , DestLo , DestHi ) ; TRI . splitReg ( SrcReg , SrcLo , SrcHi ) ;

BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestLo ) . addReg ( SrcLo , getKillRegState ( KillSrc ) ) ;


<s> case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ; case <STR_LIT> : return get ( <STR_LIT> ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ;


<s> case TargetOpcode :: INLINEASM_BR : { const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const <ISA_LIT>TargetMachine & TM = static_cast < const <ISA_LIT>TargetMachine & > ( MF . getTarget ( ) ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ;

return TII . getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ;


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {


<s> if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; auto & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; auto & CondMI = * BuildMI ( & MBB , DL , getBrCond ( CC ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; ++ Count ; if ( FBB ) { auto & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> auto & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; auto & CondMI = * BuildMI ( & MBB , DL , getBrCond ( CC ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; ++ Count ;


<s> unsigned <ISA_LIT>InstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & NewDestBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const { auto & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( & NewDestBB ) ;


<s> switch ( BranchOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> bool <ISA_LIT>InstrInfo :: isBranchOffsetInRange ( unsigned BranchOp , int64_t BrOffset ) const { switch ( BranchOp ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return isIntN ( <NUM_LIT> , BrOffset ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> case <STR_LIT> : { if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } default : break ; } return <NUM_LIT> ;


<s> MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlign ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ;

} else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) {


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {


<s> assert ( Cond . size ( ) == <NUM_LIT> && <STR_LIT> ) ;

<STR_LIT> CC = static_cast < <STR_LIT> > ( Cond [ <NUM_LIT> ] . getImm ( ) ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlign ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ;


<s> void <ISA_LIT>InstrInfo :: storeRegToStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , Register SrcReg , bool isKill , int FrameIndex , const TargetRegisterClass * RC , const TargetRegisterInfo * TRI ) const { MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; AFI -> setHasSpills ( true ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlign ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else {


<s> StringRef getPassName ( ) const override {


<s> <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Subtarget ( nullptr ) {


<s> LLVM_DEBUG ( errs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; N -> setNodeId ( - <NUM_LIT> ) ; return ;


<s> } case <STR_LIT> : { if ( ( ! isPre && Offs != <NUM_LIT> ) || ( isPre && Offs != - <NUM_LIT> ) ) { return false ; } Opcode = ( isPre ) ? <STR_LIT> : <STR_LIT> ; break ; } default : return false ; } SDNode * ResNode = CurDAG -> getMachineNode ( Opcode , SDLoc ( N ) , VT , PtrVT , <STR_LIT> , LD -> getBasePtr ( ) , LD -> getChain ( ) ) ;


<s> int Offs = cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getSExtValue ( ) ; switch ( VT . SimpleTy ) { case <STR_LIT> : { if ( ( ! isPre && Offs != <NUM_LIT> ) || ( isPre && Offs != - <NUM_LIT> ) ) { return false ; } Opcode = ( isPre ) ? <STR_LIT> : <STR_LIT> ; break ; } case <STR_LIT> : { if ( ( ! isPre && Offs != <NUM_LIT> ) || ( isPre && Offs != - <NUM_LIT> ) ) {


<s> <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( LD -> getExtensionType ( ) != <STR_LIT> || AM != <STR_LIT> ) { return <NUM_LIT> ; } unsigned Opcode = <NUM_LIT> ; int Offs = cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getSExtValue ( ) ; switch ( VT . SimpleTy ) { case <STR_LIT> : { if ( Offs != <NUM_LIT> ) { return <NUM_LIT> ; } Opcode = <STR_LIT> ; break ; } case <STR_LIT> : {


<s> unsigned Reg ; bool CanHandleRegImmOpt = ImmNode && ImmNode -> getAPIntValue ( ) . ult ( <NUM_LIT> ) ; if ( CopyFromRegOp -> getOpcode ( ) == <STR_LIT> ) { RegisterSDNode * RegNode = cast < RegisterSDNode > ( CopyFromRegOp -> getOperand ( <NUM_LIT> ) ) ; Reg = RegNode -> getReg ( ) ; CanHandleRegImmOpt &= ( Register :: isVirtualRegister ( Reg ) || <STR_LIT> . contains ( Reg ) ) ; } else { CanHandleRegImmOpt = false ; } if ( CanHandleRegImmOpt ) { SDValue Base , Disp ; if ( RI . getRegClass ( Reg ) != & <STR_LIT> ) { SDLoc dl ( CopyFromRegOp ) ; Register VReg = RI . createVirtualRegister ( & <STR_LIT> ) ; SDValue CopyToReg = CurDAG -> getCopyToReg ( CopyFromRegOp , dl , VReg , CopyFromRegOp ) ; SDValue NewCopyFromRegOp = CurDAG -> getCopyFromReg ( CopyToReg , dl , VReg , TL . getPointerTy ( DL ) ) ; Base = NewCopyFromRegOp ; } else { Base = CopyFromRegOp ; } if ( ImmNode -> getValueType ( <NUM_LIT> ) != <STR_LIT> ) { Disp = CurDAG -> getTargetConstant ( ImmNode -> getAPIntValue ( ) . getZExtValue ( ) , dl , <STR_LIT> ) ; } else { Disp = ImmOp ; } OutOps . push_back ( Base ) ; OutOps . push_back ( Disp ) ; return false ; } } Register VReg = RI . createVirtualRegister ( & <STR_LIT> ) ; SDValue CopyToReg = CurDAG -> getCopyToReg ( Op , dl , VReg , Op ) ; SDValue CopyFromReg = CurDAG -> getCopyFromReg ( CopyToReg , dl , VReg , TL . getPointerTy ( DL ) ) ;


<s> auto DL = CurDAG -> getDataLayout ( ) ; const RegisterSDNode * RegNode = dyn_cast < RegisterSDNode > ( Op ) ; if ( RegNode && RI . getRegClass ( RegNode -> getReg ( ) ) == & <STR_LIT> ) { OutOps . push_back ( Op ) ; return false ; } if ( Op -> getOpcode ( ) == <STR_LIT> ) { SDValue Base , Disp ; if ( SelectAddr ( Op . getNode ( ) , Op , Base , Disp ) ) { OutOps . push_back ( Base ) ; OutOps . push_back ( Disp ) ; return false ; } return true ; } if ( Op -> getOpcode ( ) == <STR_LIT> || Op -> getOpcode ( ) == <STR_LIT> ) { SDValue CopyFromRegOp = Op -> getOperand ( <NUM_LIT> ) ; SDValue ImmOp = Op -> getOperand ( <NUM_LIT> ) ; ConstantSDNode * ImmNode = dyn_cast < ConstantSDNode > ( ImmOp ) ; unsigned Reg ; bool CanHandleRegImmOpt = ImmNode && ImmNode -> getAPIntValue ( ) . ult ( <NUM_LIT> ) ;

if ( CopyFromRegOp -> getOpcode ( ) == <STR_LIT> ) {


<s> SDLoc DL ( N ) ; MVT Type = N -> getSimpleValueType ( <NUM_LIT> ) ; assert ( Type == <STR_LIT> && <STR_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned MachineOp = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Lhs = N -> getOperand ( <NUM_LIT> ) ; SDValue Rhs = N -> getOperand ( <NUM_LIT> ) ; SDNode * Mul = CurDAG -> getMachineNode ( MachineOp , DL , <STR_LIT> , Lhs , Rhs ) ;

SDValue InChain = CurDAG -> getEntryNode ( ) ;


<s> unsigned Opcode = N -> getOpcode ( ) ; SDLoc DL ( N ) ; switch ( Opcode ) { case <STR_LIT> : return select < <STR_LIT> > ( N ) ;


<s> unsigned Opcode = N -> getOpcode ( ) ; SDLoc DL ( N ) ; switch ( Opcode ) { case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : case <STR_LIT> : return selectMultiplication ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ;


<s> MVT VT = Args [ i ] . VT ; if ( UseStack ) { auto evt = EVT ( VT ) . getTypeForEVT ( CCInfo . getContext ( ) ) ; unsigned Offset = CCInfo . AllocateStack ( TD -> getTypeAllocSize ( evt ) , TD -> getABITypeAlign ( evt ) ) ; CCInfo . addLoc ( CCValAssign :: getMem ( i , VT , Offset , VT , CCValAssign :: Full ) ) ; } else { unsigned Reg ; if ( VT == <STR_LIT> ) { Reg = CCInfo . AllocateReg ( RegList8 [ RegIdx ] ) ; } else if ( VT == <STR_LIT> ) { Reg = CCInfo . AllocateReg ( RegList16 [ RegIdx ] ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }


<s> for ( unsigned i = <NUM_LIT> ; i != NumArgs ; ++ i ) { MVT VT = Args [ i ] . VT ; unsigned Reg ; if ( VT == <STR_LIT> ) { Reg = CCInfo . AllocateReg ( RegList8 [ RegIdx ] ) ; } else if ( VT == <STR_LIT> ) { Reg = CCInfo . AllocateReg ( RegList16 [ RegIdx ] ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } assert ( Reg && <STR_LIT> ) ; CCInfo . addLoc ( CCValAssign :: getReg ( i , VT , Reg , VT , CCValAssign :: Full ) ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ; return CCInfo . CheckReturn ( Outs , RetCC_<ISA_LIT>_BUILTIN ) ; }

unsigned TotalBytes = getTotalArgumentsSizeInBytes ( Outs ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return insertShift ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : return insertMul ( MI , MBB ) ; } assert ( ( Opc == <STR_LIT> || Opc == <STR_LIT> ) && <STR_LIT> ) ; const <ISA_LIT>InstrInfo & TII = ( const <ISA_LIT>InstrInfo & ) * MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getInstrInfo ( ) ; DebugLoc dl = MI . getDebugLoc ( ) ; MachineFunction * MF = MBB -> getParent ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock * FallThrough = MBB -> getFallThrough ( ) ; if ( FallThrough != nullptr ) { BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( FallThrough ) ; } MachineBasicBlock * trueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * falseMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineFunction :: iterator I ; for ( I = MF -> begin ( ) ; I != MF -> end ( ) && & ( * I ) != MBB ; ++ I ) ; if ( I != MF -> end ( ) ) ++ I ; MF -> insert ( I , trueMBB ) ;


<s> <STR_LIT> getCmpLibcallReturnType ( ) const override {


<s> unsigned <ISA_LIT>TargetLowering :: getInlineAsmMemConstraint ( StringRef ConstraintCode ) const { switch ( ConstraintCode [ <NUM_LIT> ] ) { case 'Q' : return InlineAsm :: Constraint_Q ;


<s> if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != <NUM_LIT> ) ) { return false ; } Base = Op -> getOperand ( <NUM_LIT> ) ; Offset = DAG . getConstant ( RHSC , DL , <STR_LIT> ) ; AM = <STR_LIT> ;


<s> SDLoc DL ( N ) ; if ( const LoadSDNode * LD = dyn_cast < LoadSDNode > ( N ) ) { VT = LD -> getMemoryVT ( ) ; Op = LD -> getBasePtr ( ) . getNode ( ) ; if ( LD -> getExtensionType ( ) != <STR_LIT> ) return false ; if ( <STR_LIT> ( LD ) ) { return false ; } } else if ( const StoreSDNode * ST = dyn_cast < StoreSDNode > ( N ) ) { VT = ST -> getMemoryVT ( ) ; Op = ST -> getBasePtr ( ) . getNode ( ) ; if ( <STR_LIT> ( ST ) ) { return false ; } } else { return false ; } if ( VT != <STR_LIT> && VT != <STR_LIT> ) { return false ; } if ( Op -> getOpcode ( ) != <STR_LIT> && Op -> getOpcode ( ) != <STR_LIT> ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ;

if ( ( VT == <STR_LIT> && RHSC != - <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != - <NUM_LIT> ) ) {


<s> } if ( Op -> getOpcode ( ) != <STR_LIT> && Op -> getOpcode ( ) != <STR_LIT> ) { return false ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) ) { int RHSC = RHS -> getSExtValue ( ) ; if ( Op -> getOpcode ( ) == <STR_LIT> ) RHSC = - RHSC ; if ( ( VT == <STR_LIT> && RHSC != - <NUM_LIT> ) || ( VT == <STR_LIT> && RHSC != - <NUM_LIT> ) ) { return false ; } Base = Op -> getOperand ( <NUM_LIT> ) ;

Offset = DAG . getConstant ( RHSC , DL , <STR_LIT> ) ;


<s> case 'e' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'q' : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case 'r' : if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; else if ( VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 't' : if ( VT == <STR_LIT> ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; break ; case 'w' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; break ; case 'x' : case 'X' : if ( VT == <STR_LIT> || VT == <STR_LIT> ) return std :: make_pair ( unsigned ( <STR_LIT> ) , & <STR_LIT> ) ; break ; case 'y' : case 'Y' :


<s> if ( VT == LLT :: scalar ( <NUM_LIT> ) ) { Reg = StringSwitch < unsigned > ( RegName ) . Case ( <STR_LIT> , <STR_LIT> ) . Case ( <STR_LIT> , <STR_LIT> ) . Default ( <NUM_LIT> ) ; } else {


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT LHSTy ) const override { return <STR_LIT> ;


<s> default : weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'd' : case 'r' : case 'l' : weight = CW_Register ; break ; case 'a' : case 'b' : case 'e' : case 'q' : case 't' : case 'w' : case 'x' : case 'X' : case 'y' : case 'Y' : case 'z' : case 'Z' : weight = CW_SpecificReg ; break ; case 'G' : if ( const ConstantFP * C = dyn_cast < ConstantFP > ( CallOperandVal ) ) { if ( C -> isZero ( ) ) { weight = CW_Constant ; } } break ; case 'I' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( isUInt < <NUM_LIT> > ( C -> getZExtValue ( ) ) ) { weight = CW_Constant ; } } break ; case 'J' : if ( const ConstantInt * C = dyn_cast < ConstantInt > ( CallOperandVal ) ) { if ( ( C -> getSExtValue ( ) >= - <NUM_LIT> ) && ( C -> getSExtValue ( ) <= <NUM_LIT> ) ) { weight = CW_Constant ; } }


<s> return nullptr ; NODE ( RET_FLAG ) ; NODE ( RETI_FLAG ) ; NODE ( CALL ) ; NODE ( WRAPPER ) ; NODE ( LSL ) ; NODE ( LSR ) ; NODE ( ROL ) ; NODE ( ROR ) ;


<s> for ( const ArgT & Arg : Args ) { TotalBytes += Arg . VT . getStoreSize ( ) ;


<s> static unsigned getTotalArgumentsSizeInBytes ( const SmallVectorImpl < ArgT > & Args ) {


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: insertMul ( MachineInstr & MI , MachineBasicBlock * BB ) const { const TargetInstrInfo & TII = * Subtarget . getInstrInfo ( ) ; MachineBasicBlock :: iterator I ( MI ) ; ++ I ; if ( isCopyMulResult ( I ) ) ++ I ; if ( isCopyMulResult ( I ) ) ++ I ; BuildMI ( * BB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; return BB ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> if ( I -> getOpcode ( ) == <STR_LIT> ) { Register SrcReg = I -> getOperand ( <NUM_LIT> ) . getReg ( ) ; return ( SrcReg == <STR_LIT> || SrcReg == <STR_LIT> ) ; } return false ;


<s> bool <ISA_LIT>TargetLowering :: isLegalAddressingMode ( const DataLayout & DL , const AddrMode & AM , Type * Ty , unsigned AS , Instruction * I ) const { int64_t Offs = AM . BaseOffs ; if ( AM . BaseGV && ! AM . HasBaseReg && AM . Scale == <NUM_LIT> && Offs == <NUM_LIT> ) { return true ; } if ( isa < PointerType > ( Ty ) && AS == <STR_LIT> ) { return false ; }


<s> bool <ISA_LIT>TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> if ( ! isUInt < <NUM_LIT> > ( CUVal64 ) ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'J' : if ( CVal64 < - <NUM_LIT> || CVal64 > <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; case 'K' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'L' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'M' : if ( ! isUInt < <NUM_LIT> > ( CUVal64 ) ) return ; if ( Ty . getSimpleVT ( ) == <STR_LIT> ) { Ty = <STR_LIT> ; } Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'N' : if ( CVal64 != - <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; case 'O' : if ( CUVal64 != <NUM_LIT> && CUVal64 != <NUM_LIT> && CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'P' : if ( CUVal64 != <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CUVal64 , DL , Ty ) ; break ; case 'R' : if ( CVal64 < - <NUM_LIT> || CVal64 > <NUM_LIT> ) return ; Result = DAG . getTargetConstant ( CVal64 , DL , Ty ) ; break ; } break ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBlockAddress ( SDValue Op , SelectionDAG & DAG ) const { auto DL = DAG . getDataLayout ( ) ;

const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ;


<s> SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( DL ) ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getPointerTy ( DL ) , Result ) ;


<s> SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , TargetCC , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , TargetCC , Cmp ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerBR_CC ( SDValue Op , SelectionDAG & DAG ) const { SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDLoc dl ( Op ) ; SDValue TargetCC ;

SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , TargetCC , DAG , dl ) ;


<s> bool HasStackArgs = false ; for ( AI = <NUM_LIT> , AE = ArgLocs . size ( ) ; AI != AE ; ++ AI ) { CCValAssign & VA = ArgLocs [ AI ] ; EVT RegVT = VA . getLocVT ( ) ; SDValue Arg = OutVals [ AI ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; case CCValAssign :: BCvt : Arg = DAG . getNode ( <STR_LIT> , DL , RegVT , Arg ) ; break ; } if ( VA . isMemLoc ( ) ) { HasStackArgs = true ; break ; } RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } if ( HasStackArgs ) { SmallVector < SDValue , <NUM_LIT> > MemOpChains ; for ( ; AI != AE ; AI ++ ) { CCValAssign & VA = ArgLocs [ AI ] ; SDValue Arg = OutVals [ AI ] ; assert ( VA . isMemLoc ( ) ) ; SDValue PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , DAG . getRegister ( <STR_LIT> , getPointerTy ( DAG . getDataLayout ( ) ) ) , DAG . getIntPtrConstant ( VA . getLocMemOffset ( ) + <NUM_LIT> , DL ) ) ; MemOpChains . push_back ( DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( MF , VA . getLocMemOffset ( ) ) ) ) ; } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , MemOpChains ) ; } SDValue InFlag ; for ( auto Reg : RegsToPass ) { Chain = DAG . getCopyToReg ( Chain , DL , Reg . first , Reg . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; for ( auto Reg : RegsToPass ) {

Ops . push_back ( DAG . getRegister ( Reg . first , Reg . second . getValueType ( ) ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerCallResult ( SDValue Chain , SDValue InFlag , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Ins , const SDLoc & dl , SelectionDAG & DAG , SmallVectorImpl < SDValue > & InVals ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; if ( CallConv == CallingConv :: <ISA_LIT>_BUILTIN ) { CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>_BUILTIN ) ; } else { analyzeReturnValues ( Ins , CCInfo ) ; } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ;


<s> break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I16 : RTLIB :: UDIVREM_I16 ; break ; case <STR_LIT> : LC = IsSigned ? RTLIB :: SDIVREM_I32 : RTLIB :: UDIVREM_I32 ; break ; } SDValue InChain = DAG . getEntryNode ( ) ; TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( SDValue const & Value : Op -> op_values ( ) ) { Entry . Node = Value ; Entry . Ty = Value . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . IsSExt = IsSigned ; Entry . IsZExt = ! IsSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty ) ;


<s> } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT LocVT = VA . getLocVT ( ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DL ) ) ; InVals . push_back ( DAG . getLoad ( LocVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ) ; } } if ( isVarArg ) { unsigned StackSize = CCInfo . getNextStackOffset ( ) ; <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ;

AFI -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ;


<s> int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , getPointerTy ( DL ) , Offset ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getPointerTy ( DL ) , Result ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { auto DL = DAG . getDataLayout ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , getPointerTy ( DL ) , Offset ) ;


<s> return LowerShifts ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> :


<s> switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShifts ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerDivRem ( Op , DAG ) ;


<s> SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ;


<s> SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { TrueV , FalseV , TargetCC , Cmp } ; return DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ;


<s> SDLoc dl ( Op ) ; SDValue TargetCC ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , TargetCC , DAG , dl ) ; SDVTList VTs = DAG . getVTList ( Op . getValueType ( ) , <STR_LIT> ) ; SDValue Ops [ ] = { TrueV , FalseV , TargetCC , Cmp } ;

return DAG . getNode ( <STR_LIT> , dl , VTs , Ops ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerSETCC ( SDValue Op , SelectionDAG & DAG ) const { SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDLoc DL ( Op ) ; SDValue TargetCC ; SDValue Cmp = get<ISA_LIT>Cmp ( LHS , RHS , CC , TargetCC , DAG , DL ) ; SDValue TrueV = DAG . getConstant ( <NUM_LIT> , DL , Op . getValueType ( ) ) ;

SDValue FalseV = DAG . getConstant ( <NUM_LIT> , DL , Op . getValueType ( ) ) ;


<s> const MachineFunction & MF = DAG . getMachineFunction ( ) ; const <ISA_LIT>MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;


<s> Results . push_back ( Sub ) ; } break ; } default : { SDValue Res = LowerOperation ( SDValue ( N , <NUM_LIT> ) , DAG ) ;

for ( unsigned I = <NUM_LIT> , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ;


<s> unsigned getCalleeSavedFrameSize ( ) const { return CalleeSavedFrameSize ;


<s> bool getHasAllocas ( ) const { return HasAllocas ;


<s> bool getHasSpills ( ) const { return HasSpills ;


<s> bool getHasStackArgs ( ) const { return HasStackArgs ;


<s> int getVarArgsFrameIndex ( ) const { return VarArgsFrameIndex ;


<s> return isInterruptHandler ( ) || isSignalHandler ( ) ;


<s> unsigned CallConv = MF . getFunction ( ) . getCallingConv ( ) ; this -> IsInterruptHandler = CallConv == CallingConv :: X86_INTR || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ;

this -> IsSignalHandler = CallConv == CallingConv :: X86_INTR || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ;


<s> this -> IsInterruptHandler = CallConv == CallingConv :: X86_INTR || MF . getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ;


<s> void setCalleeSavedFrameSize ( unsigned Bytes ) {


<s> void setVarArgsFrameIndex ( int Idx ) { VarArgsFrameIndex = Idx ;


<s> CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = true ;


<s> CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ;


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> size_t WordCount = Size / <NUM_LIT> ; for ( int64_t i = WordCount - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { uint16_t Word = ( Val >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ; <STR_LIT> :: write ( OS , Word , <STR_LIT> :: little ) ;


<s> Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; }


<s> assert ( MI . getOperand ( OpNo ) . isImm ( ) ) ; auto Imm = MI . getOperand ( OpNo ) . getImm ( ) ;


<s> auto Imm = MI . getOperand ( OpNo ) . getImm ( ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeImm ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { auto MO = MI . getOperand ( OpNo ) ; if ( MO . isExpr ( ) ) { if ( isa < <ISA_LIT>MCExpr > ( MO . getExpr ( ) ) ) { return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ; } MCFixupKind FixupKind = static_cast < MCFixupKind > ( Fixup ) ; Fixups . push_back ( MCFixup :: create ( Offset , MO . getExpr ( ) , FixupKind , MI . getLoc ( ) ) ) ; return <NUM_LIT> ;


<s> void <ISA_LIT>MCCodeEmitter :: encodeInstruction ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCInstrDesc & Desc = MCII . get ( MI . getOpcode ( ) ) ; unsigned Size = Desc . getSize ( ) ; assert ( Size > <NUM_LIT> && <STR_LIT> ) ; uint64_t BinaryOpCode = getBinaryCodeForInstr ( MI , Fixups , STI ) ; emitInstruction ( BinaryOpCode , Size , STI , OS ) ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: encodeLDSTPtrReg ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { auto MO = MI . getOperand ( OpNo ) ; assert ( MO . isReg ( ) ) ;


<s> uint8_t RegBit = <NUM_LIT> ; switch ( RegOp . getReg ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RegBit = <NUM_LIT> ; break ; case <STR_LIT> : RegBit = <NUM_LIT> ; break ; } int8_t OffsetBits ; if ( OffsetOp . isImm ( ) ) { OffsetBits = OffsetOp . getImm ( ) ; } else if ( OffsetOp . isExpr ( ) ) {


<s> auto OffsetOp = MI . getOperand ( OpNo + <NUM_LIT> ) ; assert ( RegOp . isReg ( ) && <STR_LIT> ) ; uint8_t RegBit = <NUM_LIT> ; switch ( RegOp . getReg ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RegBit = <NUM_LIT> ; break ; case <STR_LIT> : RegBit = <NUM_LIT> ; break ; } int8_t OffsetBits ; if ( OffsetOp . isImm ( ) ) {


<s> if ( MO . isExpr ( ) ) { Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( Fixup ) , MI . getLoc ( ) ) ) ; return <NUM_LIT> ; } assert ( MO . isImm ( ) ) ; auto target = MO . getImm ( ) ;

<STR_LIT> :: adjustBranchTarget ( target ) ;


Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , MCFixupKind ( Fixup ) , MI . getLoc ( ) ) ) ;


<s> MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } if ( Kind == MCExpr :: Target ) { <ISA_LIT>MCExpr const * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Expr ) ; int64_t Result ; if ( <ISA_LIT>Expr -> evaluateAsConstant ( Result ) ) { return Result ; } MCFixupKind FixupKind = static_cast < MCFixupKind > ( <ISA_LIT>Expr -> getFixupKind ( ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , <ISA_LIT>Expr , FixupKind ) ) ; return <NUM_LIT> ;


<s> if ( MO . isDFPImm ( ) ) return static_cast < unsigned > ( bit_cast < double > ( MO . getDFPImm ( ) ) ) ; assert ( MO . isExpr ( ) ) ;

return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ;


<s> assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; unsigned Opcode = MI . getOpcode ( ) ; bool IsRegX = MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> || MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ; bool IsPredec = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; bool IsPostinc = Opcode == <STR_LIT> || Opcode == <STR_LIT> ; if ( IsRegX || IsPredec || IsPostinc ) { EncodedValue |= ( <NUM_LIT> << <NUM_LIT> ) ; } return EncodedValue ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) : MCII ( MCII ) , Ctx ( Ctx ) {


<s> return new <ISA_LIT>MCELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( CE ) ) ;


<s> MCStreamer * create<ISA_LIT>ELFStreamer ( Triple const & TT , MCContext & Context , std :: unique_ptr < MCAsmBackend > MAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > CE ) { return new <ISA_LIT>MCELFStreamer ( Context , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( CE ) ) ;


<s> MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_X86_ABS8 ; MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_NONE ; if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_None ) { Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF8 ; if ( SizeInBytes == SIZE_LONG ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF32 ; else if ( SizeInBytes == SIZE_WORD ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_DIFF16 ; } else if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_LO8 ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_LO8 ;

else if ( ModifierKind == <ISA_LIT>MCExpr :: VK_<ISA_LIT>_HI8 ) Kind = MCSymbolRefExpr :: VK_<ISA_LIT>_HI8 ;


<s> <ISA_LIT>MCELFStreamer ( MCContext & Context , std :: unique_ptr < MCAsmBackend > TAB , std :: unique_ptr < MCObjectWriter > OW , std :: unique_ptr < MCCodeEmitter > Emitter , MCAssembler * Assembler ) : MCELFStreamer ( Context , std :: move ( TAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) , MCII ( create<ISA_LIT>MCInstrInfo ( ) ) {


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( VariantKind Kind , const MCExpr * Expr , bool Negated , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr , Negated ) ;


<s> if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) { Result = evaluateAsInt64 ( Value . getConstant ( ) ) ;


<s> MCValue Value ; bool isRelocatable = getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ; if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) {

Result = evaluateAsInt64 ( Value . getConstant ( ) ) ;