<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> void addBFOffsetOperands ( MCInst & Inst , unsigned N ) const {

assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> void addConditionCodeOperands ( MCInst & Inst , unsigned N ) const { assert ( N == <NUM_LIT> && <STR_LIT> ) ;


<s> assert ( N == <NUM_LIT> && <STR_LIT> ) ; addExpr ( Inst , getImm ( ) ) ;


<s> void addExpr ( MCInst & Inst , const MCExpr * Expr ) const { if ( ! Expr ) Inst . addOperand ( MCOperand :: createImm ( <NUM_LIT> ) ) ;

else if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) Inst . addOperand ( MCOperand :: createImm ( CE -> getValue ( ) ) ) ;


<s> Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


Inst . addOperand ( MCOperand :: createReg ( getReg ( ) ) ) ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( OpKind_Imm , StartLoc , EndLoc ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createReg ( unsigned Num , SMLoc StartLoc , SMLoc EndLoc ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( OpKind_Reg , StartLoc , EndLoc ) ; Op -> Reg . RegNo = Num ; return Op ;


<s> auto Op = std :: make_unique < <ISA_LIT>Operand > ( OpKind_Reg , StartLoc , EndLoc ) ; Op -> Reg . RegNo = Num ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createToken ( StringRef Str , SMLoc Loc ) {

auto Op = std :: make_unique < <ISA_LIT>Operand > ( OpKind_Token , Loc , Loc ) ;


<s> static std :: unique_ptr < <ISA_LIT>Operand > createToken ( StringRef Str , SMLoc Loc ) { auto Op = std :: make_unique < <ISA_LIT>Operand > ( OpKind_Token , Loc , Loc ) ; Op -> Tok . Token = Str ;


<s> SMLoc getEndLoc ( ) const override {


<s> SMLoc getEndLoc ( ) const override { return EndLoc ;


<s> unsigned getReg ( ) const override {


<s> SMLoc getStartLoc ( ) const override { return StartLoc ;


<s> <ISA_LIT>TargetStreamer & getTargetStreamer ( ) { assert ( getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) && <STR_LIT> ) ; MCTargetStreamer & TS = * getParser ( ) . getStreamer ( ) . getTargetStreamer ( ) ;

return static_cast < <ISA_LIT>TargetStreamer & > ( TS ) ;


<s> StringRef getToken ( ) const { assert ( isToken ( ) && <STR_LIT> ) ; return Tok . Token ;


<s> bool inRange ( const MCExpr * Expr , int64_t MinValue , int64_t MaxValue ) { if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { int64_t Value = CE -> getValue ( ) ;

return Value >= MinValue && Value <= MaxValue ;


return isImm ( <NUM_LIT> , <NUM_LIT> ) ;


<s> return isImm ( <NUM_LIT> , <NUM_LIT> ) ;


<s> bool isImm ( int64_t MinValue , int64_t MaxValue ) const {

return Kind == OpKind_Imm && inRange ( Imm , MinValue , MaxValue ) ;


<s> bool isReg ( ) const override { return Kind == OpKind_Reg ;


return isImm ( - <NUM_LIT> , <NUM_LIT> ) ;


<s> bool isToken ( ) const override { return Kind == OpKind_Token ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>AsmParser ( ) {

RegisterMCAsmParser < <ISA_LIT>AsmParser > x ( getThe<ISA_LIT>Target ( ) ) ;


<s> <ISA_LIT>Operand ( OperandKind kind , SMLoc startLoc , SMLoc endLoc ) : Kind ( kind ) , StartLoc ( startLoc ) , EndLoc ( endLoc ) {


<s> if ( ErrorInfo != ~ <NUM_LIT> ) { if ( ErrorInfo >= Operands . size ( ) ) return Error ( IdLoc , <STR_LIT> ) ; ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; } return Error ( ErrorLoc , <STR_LIT> ) ; } case Match_MnemonicFail : { FeatureBitset FBS = ComputeAvailableFeatures ( getSTI ( ) . getFeatureBits ( ) ) ; <ISA_LIT>Operand & Op = static_cast < <ISA_LIT>Operand & > ( * Operands [ <NUM_LIT> ] ) ; std :: string Suggestion = <ISA_LIT>MnemonicSpellCheck ( Op . getToken ( ) , FBS , <NUM_LIT> ) ; return Error ( IdLoc , <STR_LIT> + Suggestion ) ; } } if ( MatchResult > FIRST_TARGET_MATCH_RESULT_TY ) { SMLoc ErrorLoc = IdLoc ; if ( ErrorInfo != ~ <NUM_LIT> && ErrorInfo >= Operands . size ( ) ) return Error ( ErrorLoc , <STR_LIT> ) ; } switch ( MatchResult ) { case Match_InvalidBitfield : case Match_InvalidBitfieldWidth : case Match_InvalidBitfieldOffset : case Match_InvalidPixelRotationSize : { SMLoc ErrorLoc = ( ( <ISA_LIT>Operand & ) * Operands [ ErrorInfo ] ) . getStartLoc ( ) ; return Error ( ErrorLoc , getMatchKindDiag ( ( <ISA_LIT>MatchResultTy ) MatchResult ) ) ; } }


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: parseBFOffset ( OperandVector & Operands ) { MCContext & Ctx = getContext ( ) ; SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Lexer . isNot ( AsmToken :: Less ) ) { return MatchOperand_NoMatch ; }


<s> SMLoc StartLoc = Parser . getTok ( ) . getLoc ( ) ; Optional < AsmToken > WidthTok ; int64_t Width = <NUM_LIT> , Offset ; if ( Lexer . is ( AsmToken :: Integer ) ) { WidthTok = Parser . getTok ( ) ; Width = Parser . getTok ( ) . getIntVal ( ) ; Parser . Lex ( ) ; } if ( Lexer . isNot ( AsmToken :: Less ) ) { if ( WidthTok ) Lexer . UnLex ( WidthTok . getValue ( ) ) ; return MatchOperand_NoMatch ; } Parser . Lex ( ) ; if ( Lexer . isNot ( AsmToken :: Integer ) ) return MatchOperand_ParseFail ;

Offset = Parser . getTok ( ) . getIntVal ( ) ;


<s> if ( CC == <NUM_LIT> ) return MatchOperand_NoMatch ; } Parser . Lex ( ) ; SMLoc EndLoc = SMLoc :: getFromPointer ( Parser . getTok ( ) . getLoc ( ) . getPointer ( ) - <NUM_LIT> ) ; const MCExpr * CCExpr = MCConstantExpr :: create ( CC , getContext ( ) ) ; Operands . push_back ( <STR_LIT> ( CCExpr , StartLoc , EndLoc ) ) ; return MatchOperand_Success ;


<s> setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . emitDirectiveRequires881100 ( ) ; return false ; } return true ;


<s> MCSubtargetInfo & STI = copySTI ( ) ; STI . setDefaultFeatures ( <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; setAvailableFeatures ( ComputeAvailableFeatures ( STI . getFeatureBits ( ) ) ) ; getTargetStreamer ( ) . emitDirectiveRequires881100 ( ) ; return false ;


<s> OperandMatchResultTy Result = MatchOperandParserImpl ( Operands , Mnemonic ) ; if ( Result == MatchOperand_Success ) return Result ; if ( Result == MatchOperand_ParseFail ) { Parser . eatToEndOfStatement ( ) ; return Result ; } assert ( Result == MatchOperand_NoMatch && <STR_LIT> ) ; if ( Lexer . is ( AsmToken :: Percent ) ) {


<s> const int64_t MinVal = - ( <NUM_LIT> << Bits ) ; const int64_t MaxVal = ( <NUM_LIT> << Bits ) - <NUM_LIT> ; auto isOutOfRangeConstant = [ & ] ( const MCExpr * E ) -> bool { if ( auto * CE = dyn_cast < MCConstantExpr > ( E ) ) { int64_t Value = CE -> getValue ( ) ; if ( ( Value & <NUM_LIT> ) || Value < MinVal || Value > MaxVal ) return true ; } return false ; } ; if ( auto * CE = dyn_cast < MCConstantExpr > ( Expr ) ) { if ( isOutOfRangeConstant ( CE ) ) {


<s> OperandMatchResultTy parsePCRel16 ( OperandVector & Operands ) {

return parsePCRel ( Operands , <NUM_LIT> ) ;


<s> OperandMatchResultTy parsePCRel26 ( OperandVector & Operands ) { return parsePCRel ( Operands , <NUM_LIT> ) ;


<s> bool <ISA_LIT>AsmParser :: ParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) {

return parseRegister ( RegNo , StartLoc , EndLoc , false ) ;


<s> SMLoc StartLoc , EndLoc ; if ( parseRegister ( RegNo , StartLoc , EndLoc , false ) ) return true ; if ( Lexer . isNot ( AsmToken :: RBrac ) ) return true ;

SMLoc RBracLoc = Parser . getTok ( ) . getLoc ( ) ;


<s> SMLoc LBracketLoc = Parser . getTok ( ) . getLoc ( ) ; if ( Lexer . isNot ( AsmToken :: LBrac ) ) return true ; Parser . Lex ( ) ; unsigned RegNo ; SMLoc StartLoc , EndLoc ; if ( parseRegister ( RegNo , StartLoc , EndLoc , false ) ) return true ; if ( Lexer . isNot ( AsmToken :: RBrac ) ) return true ; SMLoc RBracLoc = Parser . getTok ( ) . getLoc ( ) ; Parser . Lex ( ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , LBracketLoc ) ) ; Operands . push_back ( <STR_LIT> ( RegNo , StartLoc , EndLoc ) ) ; Operands . push_back ( <STR_LIT> ( <STR_LIT> , RBracLoc ) ) ; return false ;


<s> void print ( raw_ostream & OS ) const override { switch ( Kind ) { case OpKind_Imm :

OS << <STR_LIT> << getImm ( ) << <STR_LIT> ;


<s> OperandMatchResultTy <ISA_LIT>AsmParser :: tryParseRegister ( unsigned & RegNo , SMLoc & StartLoc , SMLoc & EndLoc ) { bool Result = parseRegister ( RegNo , StartLoc , EndLoc , true ) ; bool PendingErrors = getParser ( ) . hasPendingError ( ) ; getParser ( ) . clearPendingErrors ( ) ; if ( PendingErrors ) return MatchOperand_ParseFail ;

if ( Result ) return MatchOperand_NoMatch ;


<s> switch ( AsmOp . getReg ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return Match_Success ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> :


<s> MCInst LoweredMI ; switch ( I -> getOpcode ( ) ) { case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; default : <ISA_LIT>MCInstLower Lower ( MF -> getContext ( ) , * this ) ; Lower . lower ( & * I , LoweredMI ) ; break ; }

EmitToStreamer ( * OutStreamer , LoweredMI ) ;


<s> LoweredMI = MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; break ; default : <ISA_LIT>MCInstLower Lower ( MF -> getContext ( ) , * this ) ; Lower . lower ( & * I , LoweredMI ) ; break ; } EmitToStreamer ( * OutStreamer , LoweredMI ) ;

} while ( ( ++ I != E ) && I -> isInsideBundle ( ) ) ;


<s> return static_cast < <ISA_LIT>TargetStreamer & > ( * OutStreamer -> getTargetStreamer ( ) ) ;


<s> explicit <ISA_LIT>AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) {


<s> bool <ISA_LIT>AsmPrinter :: PrintAsmOperand ( const MachineInstr * MI , unsigned OpNo , const char * ExtraCode , raw_ostream & OS ) { if ( ExtraCode ) return AsmPrinter :: PrintAsmOperand ( MI , OpNo , ExtraCode , OS ) ; <ISA_LIT>MCInstLower Lower ( MF -> getContext ( ) , * this ) ; MCOperand MO ( Lower . lowerOperand ( MI -> getOperand ( OpNo ) ) ) ;

<ISA_LIT>InstPrinter :: printOperand ( MO , MAI , OS ) ;


<s> static const MCPhysReg HiRegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg LoRegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; static const MCPhysReg ShadowRegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; MCRegister RegHi = State . AllocateReg ( HiRegList , ShadowRegList ) ; if ( RegHi == <NUM_LIT> ) return false ; MCRegister RegLo = State . AllocateReg ( LoRegList ) ;


<s> static const MCPhysReg ShadowRegList [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; MCRegister RegHi = State . AllocateReg ( HiRegList , ShadowRegList ) ; if ( RegHi == <NUM_LIT> ) return false ; MCRegister RegLo = State . AllocateReg ( LoRegList ) ; assert ( RegLo && <STR_LIT> ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , RegHi , LocVT , LocInfo ) ) ;

State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , RegLo , LocVT , LocInfo ) ) ;


<s> State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , RegHi , LocVT , LocInfo ) ) ; State . addLoc ( CCValAssign :: getCustomReg ( ValNo , ValVT , RegLo , LocVT , LocInfo ) ) ; return true ;


<s> assert ( VA . needsCustom ( ) && <STR_LIT> ) ; if ( VA . getValVT ( ) != <STR_LIT> ) return <NUM_LIT> ; CCValAssign NextVA = VAs [ <NUM_LIT> ] ; assert ( NextVA . needsCustom ( ) && <STR_LIT> ) ; assert ( NextVA . getValVT ( ) == <STR_LIT> && <STR_LIT> ) ; assert ( VA . getValNo ( ) == NextVA . getValNo ( ) && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ;

assert ( NextVA . isRegLoc ( ) && <STR_LIT> ) ;


<s> assert ( VA . getValNo ( ) == NextVA . getValNo ( ) && <STR_LIT> ) ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; assert ( NextVA . isRegLoc ( ) && <STR_LIT> ) ; Register NewRegs [ ] = { MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) , MRI . createGenericVirtualRegister ( LLT :: scalar ( <NUM_LIT> ) ) } ;

assignValueToReg ( NewRegs [ <NUM_LIT> ] , VA . getLocReg ( ) , VA ) ;


<s> markPhysRegUsed ( PhysReg ) ; if ( ValSize == LocSize ) { MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; } else { assert ( ValSize < LocSize && <STR_LIT> ) ;

auto PhysRegToVReg = MIRBuilder . buildCopy ( LLT :: scalar ( LocSize ) , PhysReg ) ;


<s> assert ( ValSize <= <NUM_LIT> && <STR_LIT> ) ; assert ( LocSize <= <NUM_LIT> && <STR_LIT> ) ; markPhysRegUsed ( PhysReg ) ; if ( ValSize == LocSize ) { MIRBuilder . buildCopy ( ValVReg , PhysReg ) ; } else { assert ( ValSize < LocSize && <STR_LIT> ) ; auto PhysRegToVReg = MIRBuilder . buildCopy ( LLT :: scalar ( LocSize ) , PhysReg ) ;

MIRBuilder . buildTrunc ( ValVReg , PhysRegToVReg ) ;


<s> CallReturnHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , MachineInstrBuilder MIB ) : <ISA_LIT>IncomingValueHandler ( MIRBuilder , MRI ) , MIB ( MIB ) {


<s> FormalArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI ) : <ISA_LIT>IncomingValueHandler ( MIRBuilder , MRI ) {


<s> Register <ISA_LIT>IncomingValueHandler :: getStackAddress ( uint64_t Size , int64_t Offset , MachinePointerInfo & MPO , <STR_LIT> Flags ) { auto & MFI = MIRBuilder . getMF ( ) . getFrameInfo ( ) ; const bool IsImmutable = ! Flags . isByVal ( ) ; int FI = MFI . CreateFixedObject ( Size , Offset , IsImmutable ) ;

MPO = MachinePointerInfo :: getFixedStack ( MIRBuilder . getMF ( ) , FI ) ;


<s> llvm :: LLT FramePtr = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; MachineInstrBuilder AddrReg = MIRBuilder . buildFrameIndex ( FramePtr , FI ) ;


<s> MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > OutArgs ; for ( auto & OrigArg : Info . OrigArgs ) { splitToValueTypes ( OrigArg , OutArgs , DL , Info . CallConv ) ; } SmallVector < ArgInfo , <NUM_LIT> > InArgs ; if ( ! Info . OrigRet . Ty -> isVoidTy ( ) ) splitToValueTypes ( Info . OrigRet , InArgs , DL , Info . CallConv ) ; MachineInstrBuilder CallSeqStart ; CallSeqStart = MIRBuilder . buildInstr ( <STR_LIT> ) ; unsigned Opc = Info . Callee . isReg ( ) ? <STR_LIT> : <STR_LIT> ; auto MIB = MIRBuilder . buildInstrNoInsert ( Opc ) ; MIB . add ( Info . Callee ) ; const uint32_t * Mask ; const <ISA_LIT>Subtarget & Subtarget = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const auto * TRI = Subtarget . getRegisterInfo ( ) ; OutgoingValueAssigner ArgAssigner ( CC_<ISA_LIT> ) ;

OutgoingArgHandler Handler ( MIRBuilder , MRI , MIB ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned I = <NUM_LIT> ; for ( const auto & Arg : F . args ( ) ) { ArgInfo OrigArg { VRegs [ I ] , Arg . getType ( ) , I } ; setArgFlags ( OrigArg , I + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ;


<s> bool <ISA_LIT>CallLowering :: lowerFormalArguments ( MachineIRBuilder & MIRBuilder , const Function & F , ArrayRef < ArrayRef < Register >> VRegs , FunctionLoweringInfo & FLI ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const auto & DL = F . getParent ( ) -> getDataLayout ( ) ; SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; unsigned I = <NUM_LIT> ; for ( const auto & Arg : F . args ( ) ) { ArgInfo OrigArg { VRegs [ I ] , Arg . getType ( ) , I } ; setArgFlags ( OrigArg , I + AttributeList :: FirstArgIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; ++ I ;


<s> bool <ISA_LIT>CallLowering :: lowerReturn ( MachineIRBuilder & MIRBuilder , const Value * Val , ArrayRef < Register > VRegs , FunctionLoweringInfo & FLI , Register SwiftErrorVReg ) const { MachineFunction & MF = MIRBuilder . getMF ( ) ; const Function & F = MF . getFunction ( ) ; MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; const <ISA_LIT>InstrInfo & TII = * STI . getInstrInfo ( ) ; auto & DL = F . getParent ( ) -> getDataLayout ( ) ; Register ReturnAddrVReg = getFunctionLiveInPhysReg ( MF , TII , <STR_LIT> , <STR_LIT> , MIRBuilder . getDebugLoc ( ) ) ; MRI . setType ( ReturnAddrVReg , LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ) ; auto MIB = MIRBuilder . buildInstrNoInsert ( <STR_LIT> ) ; bool Success = true ; if ( ! VRegs . empty ( ) ) { SmallVector < ArgInfo , <NUM_LIT> > SplitArgs ; ArgInfo OrigArg { VRegs , Val -> getType ( ) , <NUM_LIT> } ; setArgFlags ( OrigArg , AttributeList :: ReturnIndex , DL , F ) ; splitToValueTypes ( OrigArg , SplitArgs , DL , F . getCallingConv ( ) ) ; OutgoingValueAssigner ArgAssigner ( RetCC_<ISA_LIT> ) ; OutgoingArgHandler ArgHandler ( MIRBuilder , MRI , MIB ) ; Success = determineAndHandleAssignments ( ArgHandler , ArgAssigner , SplitArgs , MIRBuilder , F . getCallingConv ( ) , F . isVarArg ( ) ) ; }

MIRBuilder . buildCopy ( <STR_LIT> , ReturnAddrVReg ) ;


<s> <ISA_LIT>CallLowering :: <ISA_LIT>CallLowering ( const <ISA_LIT>TargetLowering & TLI ) : CallLowering ( & TLI ) {


<s> <ISA_LIT>IncomingValueHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI ) : CallLowering :: IncomingValueHandler ( MIRBuilder , MRI ) {


<s> OutgoingArgHandler ( MachineIRBuilder & MIRBuilder , MachineRegisterInfo & MRI , MachineInstrBuilder MIB ) : OutgoingValueHandler ( MIRBuilder , MRI ) , MIB ( MIB ) {


<s> return new <ISA_LIT>DelaySlotFiller ( ) ;


<s> FunctionPass * create<ISA_LIT>DelaySlotFiller ( ) { return new <ISA_LIT>DelaySlotFiller ( ) ;


<s> if ( MI -> mayStore ( ) ) { if ( SawStore ) return true ; SawStore = true ; if ( SawLoad ) return true ; } assert ( ( ! MI -> isCall ( ) && ! MI -> isReturn ( ) ) && <STR_LIT> ) ; for ( const MachineOperand & MO : MI -> operands ( ) ) { Register Reg ; if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ; if ( MO . isDef ( ) ) { if ( isRegInSet ( RegDefs , Reg ) || isRegInSet ( RegUses , Reg ) ) return true ; } if ( MO . isUse ( ) ) { if ( isRegInSet ( RegDefs , Reg ) ) return true ;


<s> bool SawStore = false ; for ( MachineBasicBlock :: reverse_instr_iterator I = ++ Slot . getReverse ( ) ; I != MBB . instr_rend ( ) ; ++ I ) { if ( I -> isDebugInstr ( ) ) continue ; MachineBasicBlock :: instr_iterator FI = I . getReverse ( ) ; if ( I -> isInlineAsm ( ) || I -> isLabel ( ) || FI == LastFiller || I -> isPseudo ( ) ) break ; if ( delayHasHazard ( FI , SawLoad , SawStore , RegDefs , RegUses ) ) { insertDefsUses ( FI , RegDefs , RegUses ) ; continue ; } Filler = FI ; return true ; } return false ;


<s> MachineFunctionProperties <ISA_LIT>DelaySlotFiller :: getRequiredProperties ( ) const {

return MachineFunctionProperties ( ) . set ( MachineFunctionProperties :: Property :: NoVRegs ) ;


<s> unsigned E = MI -> isCall ( ) || MI -> isReturn ( ) ? MCID . getNumOperands ( ) : MI -> getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; Register Reg ;

if ( ! MO . isReg ( ) || ! ( Reg = MO . getReg ( ) ) ) continue ;


<s> MCInstrDesc MCID = MI -> getDesc ( ) ; unsigned E = MI -> isCall ( ) || MI -> isReturn ( ) ? MCID . getNumOperands ( ) : MI -> getNumOperands ( ) ; for ( unsigned I = <NUM_LIT> ; I != E ; ++ I ) {

const MachineOperand & MO = MI -> getOperand ( I ) ;


<s> initialize<ISA_LIT>DelaySlotFillerPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> I != MBB . instr_end ( ) ; ++ I ) { if ( ( I -> getDesc ( ) . isBranch ( ) || I -> getDesc ( ) . isCall ( ) || I -> getDesc ( ) . isReturn ( ) ) && ( Opc = <STR_LIT> ( I -> getOpcode ( ) ) ) != - <NUM_LIT> ) { MachineBasicBlock :: instr_iterator InstrWithSlot = I ; MachineBasicBlock :: instr_iterator J = I ; if ( ! findDelayInstr ( MBB , I , J ) ) continue ; I -> setDesc ( TII -> get ( Opc ) ) ; MBB . splice ( std :: next ( I ) , & MBB , J ) ; ++ FilledSlots ; Changed = true ; LastFiller = ++ I ; MIBundleBuilder ( MBB , InstrWithSlot , std :: next ( LastFiller ) ) ;


<s> bool Changed = false ; for ( MachineBasicBlock & MBB : MF ) Changed |= runOnMachineBasicBlock ( MBB ) ; return Changed ;


<s> return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> static MCDisassembler * create<ISA_LIT>Disassembler ( const Target & T , const MCSubtargetInfo & STI , MCContext & Ctx ) { return new <ISA_LIT>Disassembler ( STI , Ctx ) ;


<s> static DecodeStatus decodeBFWidthOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm ) ;


<s> static DecodeStatus decodeBitFieldOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm ) ;


<s> return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm ) ;


<s> static DecodeStatus decodeCRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = CRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ; return MCDisassembler :: Success ;


<s> unsigned Register = CRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = FCRDecoderTable [ RegNo ] ; Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> unsigned Register = FCRDecoderTable [ RegNo ] ;

Inst . addOperand ( MCOperand :: createReg ( Register ) ) ;


<s> static DecodeStatus decodeGPR64RegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { return decodeGPRRegisterClass ( Inst , RegNo , Address , Decoder ) ;


<s> static DecodeStatus decodeGPRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) { if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ; unsigned Register = GPRDecoderTable [ RegNo ] ;


<s> Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > ( Imm ) ) ) ; return MCDisassembler :: Success ;


<s> if ( ! isUInt < <NUM_LIT> > ( Imm ) ) return MCDisassembler :: Fail ; Inst . addOperand ( MCOperand :: createImm ( SignExtend64 < <NUM_LIT> > ( Imm ) ) ) ; return MCDisassembler :: Success ;


<s> static DecodeStatus decodePixelRotOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) {

return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm << <NUM_LIT> ) ;


<s> static DecodeStatus decodeU16ImmOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm ) ;


<s> static DecodeStatus decodeU5ImmOOperand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) {

return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm ) ;


<s> Inst . addOperand ( MCOperand :: createImm ( Imm ) ) ;


<s> static DecodeStatus decodeVec9Operand ( MCInst & Inst , uint64_t Imm , uint64_t Address , const void * Decoder ) { return decodeUImmOperand < <NUM_LIT> > ( Inst , Imm ) ;


<s> static DecodeStatus decodeXRRegisterClass ( MCInst & Inst , uint64_t RegNo , uint64_t Address , const void * Decoder ) {

if ( RegNo > <NUM_LIT> ) return MCDisassembler :: Fail ;


<s> Size = <NUM_LIT> ; uint32_t Inst = <NUM_LIT> ;

for ( uint32_t I = <NUM_LIT> ; I < Size ; ++ I ) Inst = ( Inst << <NUM_LIT> ) | Bytes [ I ] ;


<s> TargetRegistry :: RegisterMCDisassembler ( getThe<ISA_LIT>Target ( ) , create<ISA_LIT>Disassembler ) ;


<s> <ISA_LIT>Disassembler ( const MCSubtargetInfo & STI , MCContext & Ctx ) : MCDisassembler ( STI , Ctx ) {


<s> int64_t CurOffset = - <NUM_LIT> ; for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; if ( <STR_LIT> . contains ( Reg ) ) { CS . setFrameIdx ( MFI . CreateFixedSpillStackObject ( <NUM_LIT> , CurOffset ) ) ; CurOffset -= <NUM_LIT> ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; Align Alignment = TRI -> getSpillAlign ( * RC ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; Alignment = std :: min ( Alignment , getStackAlign ( ) ) ;

CS . setFrameIdx ( MFI . CreateSpillStackObject ( Size , Alignment ) ) ;


<s> if ( <STR_LIT> . contains ( Reg ) ) { CS . setFrameIdx ( MFI . CreateFixedSpillStackObject ( <NUM_LIT> , CurOffset ) ) ; CurOffset -= <NUM_LIT> ; } else { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; Align Alignment = TRI -> getSpillAlign ( * RC ) ; unsigned Size = TRI -> getSpillSize ( * RC ) ; Alignment = std :: min ( Alignment , getStackAlign ( ) ) ; CS . setFrameIdx ( MFI . CreateSpillStackObject ( Size , Alignment ) ) ; } } return true ;


<s> TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ; MachineFrameInfo & MFFrame = MF . getFrameInfo ( ) ; if ( MFFrame . hasCalls ( ) ) SavedRegs . set ( <STR_LIT> ) ; if ( hasFP ( MF ) ) SavedRegs . set ( <STR_LIT> ) ;


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const {


<s> MachineBasicBlock :: iterator <ISA_LIT>FrameLowering :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { return MBB . erase ( I ) ;


<s> unsigned StackSize = MFI . getStackSize ( ) ; if ( StackSize ) { BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; }


<s> if ( SaveRA ) BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( MaxCallFrameSize + <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( SetupFP ) { BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) . addReg ( <STR_LIT> ) . addImm ( MaxCallFrameSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( MaxCallFrameSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; } }


<s> assert ( ( SetupFP || MaxCallFrameSize == <NUM_LIT> ) && <STR_LIT> ) ; assert ( ! SetupFP || std :: find_if ( CSI . begin ( ) , CSI . end ( ) , [ ] ( const CalleeSavedInfo & CS ) { return CS . getReg ( ) == <STR_LIT> ; } ) != CSI . end ( ) && <STR_LIT> ) ; bool SaveRA = std :: find_if ( CSI . begin ( ) , CSI . end ( ) , [ ] ( const CalleeSavedInfo & CS ) { return CS . getReg ( ) == <STR_LIT> ; } ) != CSI . end ( ) ; if ( StackSize ) { BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Define ) . addReg ( <STR_LIT> ) . addImm ( StackSize ) . setMIFlag ( MachineInstr :: FrameSetup ) ; if ( SaveRA ) BuildMI ( MBB , MBBI , DL , LII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addImm ( MaxCallFrameSize + <NUM_LIT> ) . setMIFlag ( MachineInstr :: FrameSetup ) ;


<s> return StackOffset :: getFixed ( resolveFrameIndexReference ( MF , FI , FrameReg ) ) ;


<s> StackOffset <ISA_LIT>FrameLowering :: getFrameIndexReference ( const MachineFunction & MF , int FI , Register & FrameReg ) const { return StackOffset :: getFixed ( resolveFrameIndexReference ( MF , FI , FrameReg ) ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ;

return ( MFI . hasCalls ( ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ) ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; if ( MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) ) return true ; return ( MFI . hasCalls ( ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ) ;


<s> bool <ISA_LIT>FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return true ;


<s> <ISA_LIT>FrameLowering :: <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & Subtarget ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> , Align ( <NUM_LIT> ) , false ) , STI ( Subtarget ) {


<s> void <ISA_LIT>FrameLowering :: processFunctionBeforeFrameFinalized ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

assert ( MFI . isMaxCallFrameSizeComputed ( ) && <STR_LIT> ) ;


<s> const bool HasFP = hasFP ( MF ) ; FrameReg = HasFP ? <STR_LIT> : <STR_LIT> ; int64_t Offset = HasFP ? <NUM_LIT> : MFI . getStackSize ( ) - MFI . getMaxCallFrameSize ( ) ; int64_t ObjectOffset = MFI . getObjectOffset ( FI ) ; if ( ObjectOffset < <NUM_LIT> ) Offset += - ObjectOffset - MFI . getObjectSize ( FI ) ; else Offset += ObjectOffset ;


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { return false ;


<s> const TargetSubtargetInfo & STI = MF -> getSubtarget ( ) ; const TargetInstrInfo * TII = STI . getInstrInfo ( ) ; const Register RAReg = STI . getRegisterInfo ( ) -> getRARegister ( ) ; for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; if ( ! MBB . isLiveIn ( Reg ) ) MBB . addLiveIn ( Reg ) ; if ( Reg != <STR_LIT> && Reg != <STR_LIT> ) { const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII -> storeRegToStackSlot ( MBB , MBBI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; }


<s> Width = countPopulation ( I ) ; Offset = countTrailingZeros ( I ) ; return true ;


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ;


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ; O << <STR_LIT> << Value << <STR_LIT> ;


<s> assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printBitFieldOperand ( const MCInst * MI , int OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ; assert ( isUInt < <NUM_LIT> > ( Value ) && <STR_LIT> ) ;

int64_t Width = ( Value >> <NUM_LIT> ) & <NUM_LIT> ;


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; int64_t CC = MO . getImm ( ) ; switch ( CC ) { case cc : \ O << str ; \ break ; CASE ( <NUM_LIT> , <STR_LIT> ) CASE ( <NUM_LIT> , <STR_LIT> ) CASE ( <NUM_LIT> , <STR_LIT> ) CASE ( <NUM_LIT> , <STR_LIT> ) CASE ( <NUM_LIT> , <STR_LIT> ) CASE ( <NUM_LIT> , <STR_LIT> ) default : O << CC ; }


<s> void <ISA_LIT>InstPrinter :: printCCodeOperand ( const MCInst * MI , int OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ; int64_t CC = MO . getImm ( ) ; switch ( CC ) { case cc : \ O << str ; \ break ; CASE ( <NUM_LIT> , <STR_LIT> ) CASE ( <NUM_LIT> , <STR_LIT> ) CASE ( <NUM_LIT> , <STR_LIT> ) CASE ( <NUM_LIT> , <STR_LIT> ) CASE ( <NUM_LIT> , <STR_LIT> ) CASE ( <NUM_LIT> , <STR_LIT> ) default : O << CC ;


<s> void <ISA_LIT>InstPrinter :: printInst ( const MCInst * MI , uint64_t Address , StringRef Annot , const MCSubtargetInfo & STI , raw_ostream & O ) {

printInstruction ( MI , Address , STI , O ) ;


<s> } else if ( MO . isImm ( ) ) O << MO . getImm ( ) ;

else if ( MO . isExpr ( ) ) MO . getExpr ( ) -> print ( O , MAI ) ;


<s> if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else MO . getExpr ( ) -> print ( O , & MAI ) ;


<s> const MCOperand & MO = MI -> getOperand ( OpNum ) ; if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else MO . getExpr ( ) -> print ( O , & MAI ) ;


<s> int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;

assert ( ( isUInt < <NUM_LIT> > ( Value ) || ! ( Value & <NUM_LIT> ) ) && <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printU16ImmOperand ( const MCInst * MI , int OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNum ) ;


<s> if ( MO . isImm ( ) ) { O << MO . getImm ( ) ; } else {

assert ( MO . isExpr ( ) && <STR_LIT> ) ;


<s> void <ISA_LIT>InstPrinter :: printU5ImmOOperand ( const MCInst * MI , int OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> void <ISA_LIT>InstPrinter :: printU5ImmOperand ( const MCInst * MI , int OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) {

int64_t Value = MI -> getOperand ( OpNum ) . getImm ( ) ;


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; MO . getExpr ( ) -> print ( O , & MAI ) ; }


<s> } else { assert ( MO . isExpr ( ) && <STR_LIT> ) ; MO . getExpr ( ) -> print ( O , & MAI ) ;


<s> while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( ! isAnalyzableBranchOpc ( I -> getOpcode ( ) ) || ( NumTerminators == <NUM_LIT> && ! isAnalyzableBranchOpc ( std :: prev ( I ) -> getOpcode ( ) ) ) ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ;


<s> void <ISA_LIT>InstrInfo :: anchor ( ) {


<s> } if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( <STR_LIT> ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } unsigned Opc ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else if ( <STR_LIT> . contains ( DestReg ) && <STR_LIT> . contains ( SrcReg ) ) Opc = <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ;

BuildMI ( MBB , MBBI , DL , get ( Opc ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> std :: pair < unsigned , unsigned > <ISA_LIT>InstrInfo :: decomposeMachineOperandsTargetFlags ( unsigned TF ) const { return std :: make_pair ( TF , <NUM_LIT> ) ;


<s> assert ( MI . getDesc ( ) . isBranch ( ) && <STR_LIT> ) ;

int NumOp = MI . getNumExplicitOperands ( ) ;


<s> const char * AsmStr = MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) ; return getInlineAsmLength ( AsmStr , * MF -> getTarget ( ) . getMCAsmInfo ( ) ) ; }


<s> static MachineMemOperand * getMachineMemOperand ( MachineBasicBlock & MBB , int FI , MachineMemOperand :: Flags Flags ) { MachineFunction & MF = * MBB . getParent ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

return MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ;


<s> return MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , Flags , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ;


<s> return MCInstBuilder ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> const <ISA_LIT>RegisterInfo & getRegisterInfo ( ) const {


<s> { MO_ABS_HI , <STR_LIT> } , { MO_ABS_LO , <STR_LIT> } , } ;


static const std :: pair < unsigned , const char * > Flags [ ] = {


<s> unsigned <ISA_LIT>InstrInfo :: insertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , ArrayRef < MachineOperand > Cond , const DebugLoc & DL , int * BytesAdded ) const { if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ; }

unsigned BrOpc = Cond [ <NUM_LIT> ] . getImm ( ) ;


<s> if ( BytesAdded ) * BytesAdded = <NUM_LIT> ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ; } unsigned BrOpc = Cond [ <NUM_LIT> ] . getImm ( ) ;

unsigned CC = Cond [ <NUM_LIT> ] . getImm ( ) ;


<s> DebugLoc DL ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> static bool isAnalyzableBranchOpc ( unsigned BranchOpc ) {

return BranchOpc == <STR_LIT> || BranchOpc == <STR_LIT> || BranchOpc == <STR_LIT> || BranchOpc == <STR_LIT> || BranchOpc == <STR_LIT> ;


<s> return BranchOpc == <STR_LIT> || BranchOpc == <STR_LIT> || BranchOpc == <STR_LIT> || BranchOpc == <STR_LIT> || BranchOpc == <STR_LIT> ;


<s> assert ( isAnalyzableBranchOpc ( BranchOpc ) && <STR_LIT> ) ;

int Bits = ( BranchOpc == <STR_LIT> || BranchOpc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ;


<s> int Bits = ( BranchOpc == <STR_LIT> || BranchOpc == <STR_LIT> ) ? <NUM_LIT> : <NUM_LIT> ; return isIntN ( Bits , BrOffset / <NUM_LIT> ) ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ; if ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return DestSourcePair { MI . getOperand ( <NUM_LIT> ) , MI . getOperand ( <NUM_LIT> ) } ; }


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;

return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , RegState :: Define ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) , STI ( STI ) {


<s> assert ( LastInst . getDesc ( ) . isConditionalBranch ( ) && <STR_LIT> ) ; Target = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ;

Cond . push_back ( MachineOperand :: CreateImm ( LastInst . getOpcode ( ) ) ) ;


<s> if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ;


<s> break ; case <STR_LIT> : case <STR_LIT> : { unsigned CC = Cond [ <NUM_LIT> ] . getImm ( ) ; CC = ( CC & ~ <NUM_LIT> ) | ( <NUM_LIT> - ( CC & <NUM_LIT> ) ) ; Cond [ <NUM_LIT> ] . setImm ( CC ) ; break ; } default : return true ; }


<s> MachineMemOperand * MMO = getMachineMemOperand ( MBB , FrameIndex , MachineMemOperand :: MOStore ) ;

BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> return new <ISA_LIT>InstructionSelector ( TM , Subtarget , RBI ) ;


<s> case TargetOpcode :: G_OR : { bool IsAnd = I . getOpcode ( ) == TargetOpcode :: G_AND ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . getType ( DstReg ) . isScalar ( ) ) return false ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MskReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Mask ; if ( ! mi_match ( MskReg , MRI , m_ICst ( Mask ) ) ) { std :: swap ( MskReg , SrcReg ) ; if ( ! mi_match ( MskReg , MRI , m_ICst ( Mask ) ) ) return false ; } if ( IsAnd ) Mask = ~ static_cast < uint64_t > ( Mask ) & <NUM_LIT> ; uint64_t MaskWidth , MaskOffset ; if ( ! isShiftedMask ( Mask , MaskWidth , MaskOffset ) ) return false ;

assert ( MaskWidth >= <NUM_LIT> && MaskWidth < <NUM_LIT> && <STR_LIT> ) ;


<s> bool <ISA_LIT>InstructionSelector :: earlySelect ( MachineInstr & I ) { assert ( I . getParent ( ) && <STR_LIT> ) ; assert ( I . getParent ( ) -> getParent ( ) && <STR_LIT> ) ; auto & MBB = * I . getParent ( ) ; auto & MF = * MBB . getParent ( ) ; auto & MRI = MF . getRegInfo ( ) ; switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_AND : case TargetOpcode :: G_OR : { bool IsAnd = I . getOpcode ( ) == TargetOpcode :: G_AND ; Register DstReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . getType ( DstReg ) . isScalar ( ) ) return false ; Register SrcReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register MskReg = I . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Mask ; if ( ! mi_match ( MskReg , MRI , m_ICst ( Mask ) ) ) { std :: swap ( MskReg , SrcReg ) ; if ( ! mi_match ( MskReg , MRI , m_ICst ( Mask ) ) ) return false ; } if ( IsAnd ) Mask = ~ static_cast < uint64_t > ( Mask ) & <NUM_LIT> ; uint64_t MaskWidth , MaskOffset ; if ( ! isShiftedMask ( Mask , MaskWidth , MaskOffset ) ) return false ; assert ( MaskWidth >= <NUM_LIT> && MaskWidth < <NUM_LIT> && <STR_LIT> ) ; assert ( MaskOffset >= <NUM_LIT> && MaskOffset < <NUM_LIT> && <STR_LIT> ) ; unsigned NewOpc = IsAnd ? <STR_LIT> : <STR_LIT> ; MachineInstr * MI = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( NewOpc ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( SrcReg ) . addImm ( ( MaskWidth << <NUM_LIT> ) | MaskOffset ) ; I . eraseFromParent ( ) ;

return constrainSelectedInstRegOperands ( * MI , TII , TRI , RBI ) ;


<s> case CmpInst :: ICMP_EQ : return CC0 :: EQ0 ; case CmpInst :: ICMP_NE : return CC0 :: NE0 ; case CmpInst :: ICMP_SGT : return CC0 :: GT0 ; case CmpInst :: ICMP_SGE : return CC0 :: GE0 ; case CmpInst :: ICMP_SLT : return CC0 :: LT0 ; case CmpInst :: ICMP_SLE : return CC0 :: LE0 ;


<s> switch ( Pred ) { case CmpInst :: ICMP_EQ : return ICC :: EQ ; case CmpInst :: ICMP_NE : return ICC :: NE ; case CmpInst :: ICMP_UGT : return ICC :: HI ; case CmpInst :: ICMP_UGE : return ICC :: HS ; case CmpInst :: ICMP_ULT : return ICC :: LO ; case CmpInst :: ICMP_ULE : return ICC :: LS ; case CmpInst :: ICMP_SGT : return ICC :: GT ; case CmpInst :: ICMP_SGE : return ICC :: GE ; case CmpInst :: ICMP_SLT : return ICC :: LT ; case CmpInst :: ICMP_SLE : return ICC :: LE ; default :


<s> bool IsLoad = ( GenericOpc == TargetOpcode :: G_LOAD || GenericOpc == TargetOpcode :: G_ZEXTLOAD || GenericOpc == TargetOpcode :: G_SEXTLOAD ) ; assert ( IsLoad || ! IsUnsigned && <STR_LIT> ) ; unsigned Idx = Log2_32 ( Size ) | ( static_cast < unsigned > ( Variant ) << <NUM_LIT> ) | ( IsUnsigned << <NUM_LIT> ) ; unsigned Opc = IsLoad ? LoadOpx [ Idx ] : StoreOpx [ Idx ] ; assert ( Opc != <NUM_LIT> && <STR_LIT> ) ;


<s> static const char * getName ( ) { return DEBUG_TYPE ;


<s> const RegisterBank * RegBank = RBI . getRegBank ( Reg , MRI , TRI ) ; assert ( RegBank && <STR_LIT> ) ; const unsigned Size = MRI . getType ( Reg ) . getSizeInBits ( ) ; assert ( ( RegBank -> getID ( ) == <STR_LIT> || RegBank -> getID ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( RegBank -> getID ( ) == <STR_LIT> ) return & <STR_LIT> ; if ( Size == <NUM_LIT> ) return & <STR_LIT> ; return & <STR_LIT> ;


<s> <ISA_LIT>InstructionSelector :: <ISA_LIT>InstructionSelector ( const <ISA_LIT>TargetMachine & TM , const <ISA_LIT>Subtarget & STI , const <ISA_LIT>RegisterBankInfo & RBI ) : InstructionSelector ( ) , TM ( TM ) , TII ( * STI . getInstrInfo ( ) ) , TRI ( * STI . getRegisterInfo ( ) ) , RBI ( RBI ) , {


<s> uint64_t Val = I . getOperand ( <NUM_LIT> ) . getCImm ( ) -> getZExtValue ( ) ; Val = ( Val & <NUM_LIT> ) >> <NUM_LIT> ;


<s> auto & MF = * MBB . getParent ( ) ; auto & MRI = MF . getRegInfo ( ) ; if ( ! isPreISelGenericOpcode ( I . getOpcode ( ) ) ) { if ( I . isCopy ( ) ) return selectCopy ( I , TII , MRI , TRI , RBI ) ; return true ; } if ( earlySelect ( I ) ) return true ; if ( selectImpl ( I , * CoverageInfo ) ) return true ; switch ( I . getOpcode ( ) ) { case TargetOpcode :: G_GLOBAL_VALUE : return selectGlobalValue ( I , MBB , MRI ) ;


<s> return selectGlobalValue ( I , MBB , MRI ) ; case TargetOpcode :: G_UBFX : case TargetOpcode :: G_SBFX : return selectUbfx ( I , MBB , MRI ) ; case TargetOpcode :: G_BRCOND : return selectCondBr ( I , MBB , MRI ) ; case TargetOpcode :: G_SEXTLOAD : case TargetOpcode :: G_ZEXTLOAD : case TargetOpcode :: G_LOAD : case TargetOpcode :: G_STORE : return selectLoadStore ( I , MBB , MRI ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectCondBr ( MachineInstr & I , MachineBasicBlock & MBB , MachineRegisterInfo & MRI ) const { assert ( I . getOpcode ( ) == TargetOpcode :: G_BRCOND && <STR_LIT> ) ; MachineInstr * MI = nullptr ; MachineOperand CC = I . getOperand ( <NUM_LIT> ) ; MachineOperand BB = I . getOperand ( <NUM_LIT> ) ; CmpInst :: Predicate Pred ; Register LHS , RHS ; int64_t SImm16 ; if ( mi_match ( CC . getReg ( ) , MRI , m_GICmp ( m_Pred ( Pred ) , m_Reg ( LHS ) , m_ICst ( SImm16 ) ) ) && isInt < <NUM_LIT> > ( SImm16 ) ) { if ( SImm16 == <NUM_LIT> ) { CC0 CCCode = getCCforBCOND ( Pred ) ; MI = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addImm ( static_cast < int64_t > ( CCCode ) ) . addReg ( LHS ) . add ( BB ) ; } else { Register Temp = MRI . createVirtualRegister ( & <STR_LIT> ) ; ICC CCCode = getCCforICMP ( Pred ) ; MI = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( Temp , RegState :: Define ) . addReg ( LHS ) . addImm ( SImm16 ) ; if ( ! constrainSelectedInstRegOperands ( * MI , TII , TRI , RBI ) ) return false ; MI = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addImm ( static_cast < int64_t > ( CCCode ) ) . addReg ( Temp , RegState :: Kill ) . add ( BB ) ; } } else if ( mi_match ( CC . getReg ( ) , MRI , m_GICmp ( m_Pred ( Pred ) , m_Reg ( LHS ) , m_Reg ( RHS ) ) ) ) {


<s> if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ;


<s> if ( Register :: isPhysicalRegister ( DstReg ) ) return true ; const TargetRegisterClass * RC = guessRegClass ( DstReg , MRI , TRI , RBI ) ; if ( ! RBI . constrainGenericRegister ( DstReg , * RC , MRI ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << TII . getName ( I . getOpcode ( ) ) << <STR_LIT> ) ; return false ; }


<s> if ( ! constrainSelectedInstRegOperands ( * MI , TII , TRI , RBI ) ) return false ;

MI = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addReg ( Temp , RegState :: Kill ) . addGlobalAddress ( GV , <NUM_LIT> , <STR_LIT> ) ;


<s> bool <ISA_LIT>InstructionSelector :: selectICmp ( MachineInstr & I , MachineBasicBlock & MBB , MachineRegisterInfo & MRI ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> } else if ( MachineInstr * GlobalValMI = getOpcodeDef ( TargetOpcode :: G_GLOBAL_VALUE , Ptr . getReg ( ) , MRI ) ) { const unsigned NewOpc = getLoadStoreOp ( I . getOpcode ( ) , MemSizeInBytes , LoadStore :: Imm , IsZExtLoad ) ; const GlobalValue * GV = GlobalValMI -> getOperand ( <NUM_LIT> ) . getGlobal ( ) ; Register Temp = MRI . createVirtualRegister ( & <STR_LIT> ) ; MI = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( Temp , RegState :: Define ) . addReg ( <STR_LIT> ) . addGlobalAddress ( GV ) ; MI -> getOperand ( <NUM_LIT> ) . setTargetFlags ( <STR_LIT> ) ; if ( ! constrainSelectedInstRegOperands ( * MI , TII , TRI , RBI ) ) return false ; MI = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( NewOpc ) ) . addReg ( ValReg , getDefRegState ( IsLoad ) ) . addReg ( Temp , RegState :: Kill ) . addGlobalAddress ( GV ) . addMemOperand ( MMO ) ; MI -> getOperand ( <NUM_LIT> ) . setTargetFlags ( <STR_LIT> ) ; } else if ( mi_match ( Ptr . getReg ( ) , MRI , m_GPtrAdd ( m_MInstr ( Base ) , m_ICst ( Offset ) ) ) && isUInt < <NUM_LIT> > ( Offset ) ) { Register AddrReg = Base -> getOperand ( Base -> getOpcode ( ) == TargetOpcode :: COPY ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; const unsigned NewOpc = getLoadStoreOp ( I . getOpcode ( ) , MemSizeInBytes , LoadStore :: Imm , IsZExtLoad ) ; MI = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( NewOpc ) ) . addReg ( ValReg , getDefRegState ( IsLoad ) ) . addReg ( AddrReg ) . addImm ( Offset ) . addMemOperand ( MMO ) ; } else if ( mi_match ( Ptr . getReg ( ) , MRI , m_GPtrAdd ( m_MInstr ( Base ) , m_MInstr ( Addend ) ) ) ) { Register AddrReg = Base -> getOperand ( Base -> getOpcode ( ) == TargetOpcode :: COPY ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; Register IndexReg = Base -> getOperand ( Addend -> getOpcode ( ) == TargetOpcode :: COPY ? <NUM_LIT> : <NUM_LIT> ) . getReg ( ) ; const unsigned NewOpc = getLoadStoreOp ( I . getOpcode ( ) , MemSizeInBytes , LoadStore :: RegUnscaled , IsZExtLoad ) ; MI = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( NewOpc ) ) . addReg ( ValReg , getDefRegState ( IsLoad ) ) . addReg ( AddrReg ) . addReg ( IndexReg ) . addMemOperand ( MMO ) ;


<s> int64_t WO = Width -> Value . getZExtValue ( ) << <NUM_LIT> | Offset -> Value . getZExtValue ( ) ; MachineInstr * MI = BuildMI ( MBB , I , I . getDebugLoc ( ) , TII . get ( NewOpc ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . add ( I . getOperand ( <NUM_LIT> ) ) . addImm ( WO ) ; I . eraseFromParent ( ) ; return constrainSelectedInstRegOperands ( * MI , TII , TRI , RBI ) ;


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( Subtarget . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setMinFunctionAlignment ( Align ( <NUM_LIT> ) ) ;

setPrefFunctionAlignment ( Align ( <NUM_LIT> ) ) ;


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( Subtarget . getRegisterInfo ( ) ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setMinFunctionAlignment ( Align ( <NUM_LIT> ) ) ; setPrefFunctionAlignment ( Align ( <NUM_LIT> ) ) ;


<s> getActionDefinitionsBuilder ( G_PTRTOINT ) . legalFor ( { { S32 , P0 } } ) . minScalar ( <NUM_LIT> , S32 ) ; getActionDefinitionsBuilder ( { G_ZEXT , G_SEXT , G_ANYEXT } ) . legalIf ( [ ] ( const LegalityQuery & Query ) { return false ; } ) . maxScalar ( <NUM_LIT> , S32 ) ; getActionDefinitionsBuilder ( G_TRUNC ) . legalIf ( [ ] ( const LegalityQuery & Query ) { return false ; } ) . maxScalar ( <NUM_LIT> , S32 ) ; getActionDefinitionsBuilder ( { G_SEXTLOAD , G_ZEXTLOAD } ) . legalForTypesWithMemDesc ( { { S32 , P0 , S8 , <NUM_LIT> } , { S32 , P0 , S16 , <NUM_LIT> } } ) ; getActionDefinitionsBuilder ( { G_LOAD , G_STORE } ) . legalForTypesWithMemDesc ( { { S32 , P0 , S8 , <NUM_LIT> } , { S32 , P0 , S16 , <NUM_LIT> } , { S32 , P0 , S32 , <NUM_LIT> } , { P0 , P0 , P0 , <NUM_LIT> } , { S64 , P0 , S64 , <NUM_LIT> } } ) . unsupportedIfMemSizeNotPow2 ( ) . minScalar ( <NUM_LIT> , S32 ) ;

getActionDefinitionsBuilder ( G_PTR_ADD ) . legalFor ( { { P0 , S32 } } ) . clampScalar ( <NUM_LIT> , S32 , S32 ) ;


<s> unsigned NumBytes = ( getFixupKindInfo ( Kind ) . TargetSize + <NUM_LIT> ) / <NUM_LIT> ; unsigned FullSize = <NUM_LIT> ; uint64_t CurVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) { unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; }

uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ;


<s> unsigned Idx = ( FullSize - <NUM_LIT> - i ) ; CurVal |= static_cast < uint64_t > ( static_cast < uint8_t > ( Data [ Offset + Idx ] ) ) << ( i * <NUM_LIT> ) ; } uint64_t Mask = ( static_cast < uint64_t > ( - <NUM_LIT> ) >> ( <NUM_LIT> - getFixupKindInfo ( Kind ) . TargetSize ) ) ; CurVal |= Value & Mask ;

for ( unsigned i = <NUM_LIT> ; i != NumBytes ; ++ i ) {


<s> uint8_t OSABI = MCELFObjectTargetWriter :: getOSABI ( STI . getTargetTriple ( ) . getOS ( ) ) ;

return new <ISA_LIT>MCAsmBackend ( OSABI ) ;


<s> std :: unique_ptr < MCObjectTargetWriter > createObjectTargetWriter ( ) const override {

return create<ISA_LIT>ObjectWriter ( OSABI ) ;


<s> unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - <NUM_LIT> ) ; if ( Type != - <NUM_LIT> ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ; return None ;


<s> Optional < MCFixupKind > <ISA_LIT>MCAsmBackend :: getFixupKind ( StringRef Name ) const { unsigned Type = llvm :: StringSwitch < unsigned > ( Name ) . Default ( - <NUM_LIT> ) ; if ( Type != - <NUM_LIT> ) return static_cast < MCFixupKind > ( FirstLiteralRelocationKind + Type ) ;


<s> const MCFixupKindInfo & <ISA_LIT>MCAsmBackend :: getFixupKindInfo ( MCFixupKind Kind ) const { static const MCFixupKindInfo Infos [ <STR_LIT> ] = {


<s> unsigned <ISA_LIT>MCAsmBackend :: getNumFixupKinds ( ) const { return <STR_LIT> ;


<s> unsigned <ISA_LIT>MCAsmBackend :: getNumFixupKinds ( ) const {


<s> <ISA_LIT>MCAsmBackend ( uint8_t osABI ) : MCAsmBackend ( <STR_LIT> ) , OSABI ( osABI ) {


<s> bool <ISA_LIT>MCAsmBackend :: mayNeedRelaxation ( const MCInst & Inst , const MCSubtargetInfo & STI ) const { return false ;


<s> bool <ISA_LIT>MCAsmBackend :: shouldForceRelocation ( const MCAssembler & Asm , const MCFixup & Fixup , const MCValue & Target ) { return Fixup . getKind ( ) == <STR_LIT> || Fixup . getKind ( ) == <STR_LIT> ;


<s> return Fixup . getKind ( ) == <STR_LIT> || Fixup . getKind ( ) == <STR_LIT> ;


<s> bool <ISA_LIT>MCAsmBackend :: writeNopData ( raw_ostream & OS , uint64_t Count , const MCSubtargetInfo * STI ) const { if ( ( Count % <NUM_LIT> ) != <NUM_LIT> ) return false ; for ( uint64_t I = <NUM_LIT> ; I != Count ; ++ I ) OS << <STR_LIT> ; return true ;


<s> Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ; SupportsDebugInformation = false ;

ExceptionsType = ExceptionHandling :: SjLj ;


<s> MinInstAlignment = <NUM_LIT> ; CommentString = <STR_LIT> ; ZeroDirective = <STR_LIT> ; Data64bitsDirective = <STR_LIT> ; UsesELFSectionDirectiveForBSS = true ;


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> for ( int I = ( <NUM_LIT> - <NUM_LIT> ) * <NUM_LIT> ; I >= <NUM_LIT> ; I -= <NUM_LIT> ) OS << static_cast < uint8_t > ( ( Bits >> I ) & <NUM_LIT> ) ;


<s> <ISA_LIT>MCExpr :: VariantKind ExprKind = McExpr -> getKind ( ) ; switch ( ExprKind ) { case <ISA_LIT>MCExpr :: VK_None : return <STR_LIT> ; case <ISA_LIT>MCExpr :: VK_ABS_HI : return <STR_LIT> ;


<s> if ( MO . isImm ( ) ) return static_cast < uint64_t > ( MO . getImm ( ) ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . getExpr ( ) ; assert ( isa < <ISA_LIT>MCExpr > ( Expr ) && <STR_LIT> ) ; const uint32_t Offset = <NUM_LIT> ; Fixups . push_back ( MCFixup :: create ( Offset , Expr , MCFixupKind ( FixupKind ( Expr ) ) ) ) ;


<s> assert ( MO . isImm ( ) || MO . isExpr ( ) && <STR_LIT> ) ; const MCExpr * Expr = MO . isImm ( ) ? MCConstantExpr :: create ( MO . getImm ( ) , Ctx ) : MO . getExpr ( ) ;

Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , static_cast < MCFixupKind > ( <STR_LIT> ) , MI . getLoc ( ) ) ) ;


<s> const MCExpr * Expr = MO . isImm ( ) ? MCConstantExpr :: create ( MO . getImm ( ) , Ctx ) : MO . getExpr ( ) ;


<s> const MCExpr * Expr = MO . isImm ( ) ? MCConstantExpr :: create ( MO . getImm ( ) , Ctx ) : MO . getExpr ( ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , Expr , static_cast < MCFixupKind > ( <STR_LIT> ) , MI . getLoc ( ) ) ) ; return <NUM_LIT> ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getPC26Encoding ( const MCInst & MI , unsigned OpNo , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( OpNo ) ; assert ( MO . isImm ( ) || MO . isExpr ( ) && <STR_LIT> ) ;

const MCExpr * Expr = MO . isImm ( ) ? MCConstantExpr :: create ( MO . getImm ( ) , Ctx ) : MO . getExpr ( ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) : MCII ( MCII ) , Ctx ( Ctx ) {


<s> return E -> getKind ( ) == MCExpr :: Target ;


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ;


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ;

Res = MCValue :: get ( Res . getSymA ( ) , Res . getSymB ( ) , Res . getConstant ( ) , getKind ( ) ) ;


<s> return getSubExpr ( ) -> findAssociatedFragment ( ) ;


<s> void fixELFSymbolsInTLSFixups ( MCAssembler & ) const override {


<s> VariantKind getKind ( ) const { return Kind ;


<s> const MCExpr * getSubExpr ( ) const {


<s> const MCExpr * getSubExpr ( ) const { return Expr ;


<s> explicit <ISA_LIT>MCExpr ( VariantKind Kind , const MCExpr * Expr ) : Kind ( Kind ) , Expr ( Expr ) {


<s> OS << <STR_LIT> ; break ; case VK_ABS_LO : OS << <STR_LIT> ; break ; } OS << '(' ; const MCExpr * Expr = getSubExpr ( ) ;


<s> OS << <STR_LIT> ; break ; } OS << '(' ; const MCExpr * Expr = getSubExpr ( ) ; Expr -> print ( OS , MAI ) ; OS << ')' ;


<s> Streamer . visitUsedExpr ( * getSubExpr ( ) ) ;


<s> OutMI . setOpcode ( MI -> getOpcode ( ) ) ; for ( unsigned I = <NUM_LIT> , E = MI -> getNumOperands ( ) ; I != E ; ++ I ) { const MachineOperand & MO = MI -> getOperand ( I ) ; if ( ( ! MO . isReg ( ) || ! MO . isImplicit ( ) ) && ! MO . isRegMask ( ) ) OutMI . addOperand ( lowerOperand ( MO ) ) ;


<s> case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : case MachineOperand :: MO_MCSymbol : case MachineOperand :: MO_JumpTableIndex : case MachineOperand :: MO_ConstantPoolIndex : case MachineOperand :: MO_BlockAddress : return lowerSymbolOperand ( MO ) ;


<s> MCSymbolRefExpr :: VariantKind Kind = MCSymbolRefExpr :: VK_None ; <ISA_LIT>MCExpr :: VariantKind TargetKind = <ISA_LIT>MCExpr :: VK_None ; const MCSymbol * Symbol ; bool HasOffset = true ; switch ( MO . getTargetFlags ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_ABS_HI ; break ; case <STR_LIT> : TargetKind = <ISA_LIT>MCExpr :: VK_ABS_LO ; break ; } switch ( MO . getType ( ) ) { case MachineOperand :: MO_MachineBasicBlock : Symbol = MO . getMBB ( ) -> getSymbol ( ) ; HasOffset = false ; break ; case MachineOperand :: MO_GlobalAddress : Symbol = Printer . getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : Symbol = Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : Symbol = Printer . GetJTISymbol ( MO . getIndex ( ) ) ; HasOffset = false ; break ; case MachineOperand :: MO_ConstantPoolIndex : Symbol = Printer . GetCPISymbol ( MO . getIndex ( ) ) ; break ; case MachineOperand :: MO_BlockAddress : Symbol = Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ; break ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & Ctx , AsmPrinter & Printer ) : Ctx ( Ctx ) , Printer ( Printer ) {


<s> std :: unique_ptr < MCObjectTargetWriter > llvm :: create<ISA_LIT>ObjectWriter ( uint8_t OSABI ) {

return std :: make_unique < <ISA_LIT>ObjectWriter > ( OSABI ) ;


<s> Type = ELF :: R_88K_16H ; break ; case <STR_LIT> : Type = ELF :: R_88K_16L ; break ; case <STR_LIT> : Type = ELF :: R_88K_DISP16 ; break ; case <STR_LIT> : Type = ELF :: R_88K_DISP26 ; break ; case <STR_LIT> : Type = ELF :: R_88K_NONE ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } return Type ;


<s> unsigned <STR_LIT> ( MCContext & Ctx , const MCValue & Target , const MCFixup & Fixup , bool IsPCRel ) const { unsigned Type ; unsigned Kind = static_cast < unsigned > ( Fixup . getKind ( ) ) ; switch ( Kind ) { case <STR_LIT> :


<s> <STR_LIT> ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_88K , true ) {


<s> static MCTargetStreamer * create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) { return new <ISA_LIT>TargetAsmStreamer ( S , OS ) ;


<s> static MCTargetStreamer * create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) {

return new <ISA_LIT>TargetAsmStreamer ( S , OS ) ;


<s> static MCAsmInfo * create<ISA_LIT>MCAsmInfo ( const MCRegisterInfo & MRI , const Triple & TT , const MCTargetOptions & Options ) { MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ;


<s> MCAsmInfo * MAI = new <ISA_LIT>MCAsmInfo ( TT ) ; return MAI ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {

return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> Init<ISA_LIT>MCInstrInfo ( X ) ; return X ;


<s> Init<ISA_LIT>MCRegisterInfo ( X , <STR_LIT> ) ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ;


<s> return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , FS ) ;


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) {

return new <ISA_LIT>TargetELFStreamer ( S , STI ) ;


<s> bool applyShiftAndToMak ( MachineInstr & MI , MachineRegisterInfo & MRI , std :: tuple < Register , uint32_t , uint32_t > & MatchInfo ) { assert ( MI . getOpcode ( ) == TargetOpcode :: G_SHL ) ; replaceMI ( <STR_LIT> , MI , MRI , MatchInfo ) ;


<s> bool applyShiftAndToMak ( MachineInstr & MI , MachineRegisterInfo & MRI , std :: tuple < Register , uint32_t , uint32_t > & MatchInfo ) { assert ( MI . getOpcode ( ) == TargetOpcode :: G_SHL ) ; replaceMI ( <STR_LIT> , MI , MRI , MatchInfo ) ; return true ;


<s> CombinerHelper Helper ( Observer , B ) ; <ISA_LIT>GenPostLegalizerLoweringHelper Generated ( GeneratedRuleCfg ) ; return Generated . tryCombineAll ( Observer , MI , B , Helper ) ;


<s> FunctionPass * create<ISA_LIT>PostLegalizerLowering ( ) {

return new <ISA_LIT>PostLegalizerLowering ( ) ;


<s> return new <ISA_LIT>PostLegalizerLowering ( ) ;


<s> getSelectionDAGFallbackAnalysisUsage ( AU ) ; MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> void <ISA_LIT>PostLegalizerLowering :: getAnalysisUsage ( AnalysisUsage & AU ) const { AU . addRequired < TargetPassConfig > ( ) ;


<s> StringRef getPassName ( ) const override {


<s> <ISA_LIT>PostLegalizerLoweringInfo ( bool OptSize , bool MinSize ) : CombinerInfo ( true , false , nullptr , true , OptSize , MinSize ) {

if ( ! GeneratedRuleCfg . parseCommandLineOption ( ) ) report_fatal_error ( <STR_LIT> ) ;


<s> static bool matchShiftAndToMak ( MachineInstr & MI , MachineRegisterInfo & MRI , std :: tuple < Register , uint32_t , uint32_t > & MatchInfo ) { assert ( MI . getOpcode ( ) == TargetOpcode :: G_SHL ) ; Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . getType ( DstReg ) . isScalar ( ) ) return false ; Register AndReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OfsReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Offset ; if ( ! mi_match ( OfsReg , MRI , m_ICst ( Offset ) ) ) return false ; Register SrcReg ; int64_t Mask ; if ( ! mi_match ( AndReg , MRI , m_GAnd ( m_Reg ( SrcReg ) , m_ICst ( Mask ) ) ) ) return false ; uint64_t MaskWidth , MaskOffset ; if ( ! isShiftedMask ( Mask , MaskWidth , MaskOffset ) || MaskOffset != <NUM_LIT> ) return false ; assert ( MaskWidth >= <NUM_LIT> && MaskWidth < <NUM_LIT> && <STR_LIT> ) ;

assert ( Offset >= <NUM_LIT> && Offset < <NUM_LIT> && <STR_LIT> ) ;


<s> Register DstReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( ! MRI . getType ( DstReg ) . isScalar ( ) ) return false ; Register AndReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; Register OfsReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; int64_t Offset ; if ( ! mi_match ( OfsReg , MRI , m_ICst ( Offset ) ) ) return false ; Register SrcReg ; int64_t Mask ; if ( ! mi_match ( AndReg , MRI , m_GAnd ( m_Reg ( SrcReg ) , m_ICst ( Mask ) ) ) ) return false ;


<s> const auto * TII = Subtarget . getInstrInfo ( ) ; const auto * RBI = Subtarget . getRegBankInfo ( ) ; auto Inst = MIB . buildInstr ( Opc , { MI . getOperand ( <NUM_LIT> ) . getReg ( ) } , { SrcReg } ) . addImm ( ( Width << <NUM_LIT> ) | Offset ) ; constrainSelectedInstRegOperands ( * Inst , * TII , * TRI , * RBI ) ;


<s> if ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: FailedISel ) ) return false ; assert ( MF . getProperties ( ) . hasProperty ( MachineFunctionProperties :: Property :: Legalized ) && <STR_LIT> ) ; auto * TPC = & getAnalysis < TargetPassConfig > ( ) ;

const Function & F = MF . getFunction ( ) ;


<s> <ISA_LIT>PostLegalizerLoweringInfo PCInfo ( F . hasOptSize ( ) , F . hasMinSize ( ) ) ; Combiner C ( PCInfo , TPC ) ; return C . combineMachineInstrs ( MF , nullptr ) ;


<s> <ISA_LIT>GenPreLegalizerCombinerHelper Generated ( GeneratedRuleCfg , Helper ) ; if ( Generated . tryCombineAll ( Observer , MI , B ) ) return true ;


<s> bool <ISA_LIT>PreLegalizerCombinerInfo :: combine ( GISelChangeObserver & Observer , MachineInstr & MI , MachineIRBuilder & B ) const { const auto * LI = MI . getParent ( ) -> getParent ( ) -> getSubtarget ( ) . getLegalizerInfo ( ) ; CombinerHelper Helper ( Observer , B , KB , MDT , LI ) ; <ISA_LIT>GenPreLegalizerCombinerHelper Generated ( GeneratedRuleCfg , Helper ) ; if ( Generated . tryCombineAll ( Observer , MI , B ) ) return true ;


<s> FunctionPass * create<ISA_LIT>PreLegalizerCombiner ( ) { return new <ISA_LIT>PreLegalizerCombiner ( ) ;


<s> AU . addRequired < MachineDominatorTree > ( ) ; AU . addPreserved < MachineDominatorTree > ( ) ; AU . addRequired < GISelCSEAnalysisWrapperPass > ( ) ;

AU . addPreserved < GISelCSEAnalysisWrapperPass > ( ) ;


<s> const unsigned Size = Ty . getScalarSizeInBits ( ) ; if ( ! mi_match ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_GAnd ( m_OneNonDBGUse ( m_GAShr ( m_Reg ( ShiftSrc ) , m_ICst ( ShrAmt ) ) ) , m_ICst ( AndImm ) ) ) ) return false ; auto MaybeMask = static_cast < uint64_t > ( AndImm ) ; if ( MaybeMask & ( MaybeMask + <NUM_LIT> ) ) return false ; if ( static_cast < uint64_t > ( ShrAmt ) >= Size ) return false ; uint64_t Width = APInt ( Size , AndImm ) . countTrailingOnes ( ) ; if ( static_cast < uint64_t > ( ShrAmt ) + Width >= Size && ! Helper . getKnownBits ( ) -> signBitIsZero ( ShiftSrc ) ) return false ;

MatchInfo = [ = ] ( MachineIRBuilder & B ) {


<s> Register ShiftSrc ; const unsigned Size = Ty . getScalarSizeInBits ( ) ; if ( ! mi_match ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) , MRI , m_GAnd ( m_OneNonDBGUse ( m_GAShr ( m_Reg ( ShiftSrc ) , m_ICst ( ShrAmt ) ) ) , m_ICst ( AndImm ) ) ) ) return false ; auto MaybeMask = static_cast < uint64_t > ( AndImm ) ; if ( MaybeMask & ( MaybeMask + <NUM_LIT> ) ) return false ; if ( static_cast < uint64_t > ( ShrAmt ) >= Size ) return false ; uint64_t Width = APInt ( Size , AndImm ) . countTrailingOnes ( ) ; if ( static_cast < uint64_t > ( ShrAmt ) + Width >= Size && ! Helper . getKnownBits ( ) -> signBitIsZero ( ShiftSrc ) ) return false ; MatchInfo = [ = ] ( MachineIRBuilder & B ) { auto WidthCst = B . buildConstant ( ExtractTy , Width ) ; auto LSBCst = B . buildConstant ( ExtractTy , ShrAmt ) ; B . buildInstr ( TargetOpcode :: G_UBFX , { Dst } , { ShiftSrc , LSBCst , WidthCst } ) ; } ; return true ;


<s> GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; <ISA_LIT>PreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , MDT ) ; Combiner C ( PCInfo , & TPC ) ; return C . combineMachineInstrs ( MF , CSEInfo ) ;


<s> bool EnableOpt = MF . getTarget ( ) . getOptLevel ( ) != CodeGenOpt :: None && ! skipFunction ( F ) ; GISelKnownBits * KB = & getAnalysis < GISelKnownBitsAnalysis > ( ) . get ( MF ) ; MachineDominatorTree * MDT = & getAnalysis < MachineDominatorTree > ( ) ; <ISA_LIT>PreLegalizerCombinerInfo PCInfo ( EnableOpt , F . hasOptSize ( ) , F . hasMinSize ( ) , KB , MDT ) ; Combiner C ( PCInfo , & TPC ) ;

return C . combineMachineInstrs ( MF , CSEInfo ) ;


<s> return applyDefaultMapping ( OpdMapper ) ;


<s> case TargetOpcode :: G_FMUL : case TargetOpcode :: G_FDIV : { unsigned NumOperands = MI . getNumOperands ( ) ; assert ( NumOperands <= <NUM_LIT> && <STR_LIT> ) ; InstructionMappings AltMappings ; AltMappings . push_back ( & getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getValueMapping ( PMI_XR32 ) , NumOperands ) ) ; AltMappings . push_back ( & getInstructionMapping ( <NUM_LIT> , <NUM_LIT> , getValueMapping ( PMI_XR80 ) , NumOperands ) ) ; return AltMappings ; } default : break ;


<s> const RegisterBank & <ISA_LIT>RegisterBankInfo :: getRegBankFromRegClass ( const TargetRegisterClass & RC , LLT Ty ) const { switch ( RC . getID ( ) ) { case <STR_LIT> : case <STR_LIT> : return getRegBank ( <STR_LIT> ) ;


<s> const RegisterBankInfo :: InstructionMapping & <ISA_LIT>RegisterBankInfo :: getSameKindOfOperandsMapping ( const MachineInstr & MI ) const { const unsigned Opc = MI . getOpcode ( ) ; const MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; unsigned NumOperands = MI . getNumOperands ( ) ; assert ( NumOperands <= <NUM_LIT> && <STR_LIT> ) ; LLT Ty = MRI . getType ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ; unsigned Size = Ty . getSizeInBits ( ) ; bool IsFPR = Ty . isVector ( ) || isPreISelGenericFloatingPointOpcode ( Opc ) ; PartialMappingIdx RBIdx = PMI_None ; if ( IsFPR ) { switch ( Size ) { case <NUM_LIT> : RBIdx = PMI_XR32 ; break ; case <NUM_LIT> : RBIdx = PMI_XR64 ; break ; case <NUM_LIT> : RBIdx = PMI_XR80 ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } } else { assert ( Size == <NUM_LIT> && <STR_LIT> ) ; RBIdx = PMI_GR32 ;


<s> case TargetOpcode :: G_FCOS : case TargetOpcode :: G_FSIN : case TargetOpcode :: G_FLOG10 : case TargetOpcode :: G_FLOG : case TargetOpcode :: G_FLOG2 : case TargetOpcode :: G_FSQRT : case TargetOpcode :: G_FABS : case TargetOpcode :: G_FEXP : case TargetOpcode :: G_FRINT : case TargetOpcode :: G_INTRINSIC_TRUNC : case TargetOpcode :: G_INTRINSIC_ROUND :


<s> <ISA_LIT>RegisterBankInfo :: <ISA_LIT>RegisterBankInfo ( const TargetRegisterInfo & TRI ) : <ISA_LIT>GenRegisterBankInfo ( ) {


<s> MachineInstr & MI = * II ; MachineFunction & MF = * MI . getParent ( ) -> getParent ( ) ; int FrameIndex = MI . getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; int64_t Offset = getFrameLowering ( MF ) -> resolveFrameIndexReference ( MF , FrameIndex , FrameReg ) ;

Offset += MI . getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const {


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID CC ) const { return CSR_<ISA_LIT>_RegMask ;


<s> if ( getFrameLowering ( MF ) -> hasFP ( MF ) ) return <STR_LIT> ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getPointerRegClass ( const MachineFunction & MF , unsigned Kind ) const {


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { BitVector Reserved ( getNumRegs ( ) ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;


<s> Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ; Reserved . set ( <STR_LIT> ) ;

if ( getFrameLowering ( MF ) -> hasFP ( MF ) ) Reserved . set ( <STR_LIT> ) ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> ) {


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> const TargetFrameLowering * getFrameLowering ( ) const override { return & FrameLowering ;


<s> const LegalizerInfo * getLegalizerInfo ( ) const override {


<s> const RegisterBankInfo * getRegBankInfo ( ) const override {


<s> const <ISA_LIT>RegisterInfo * getRegisterInfo ( ) const override {

return & InstrInfo . getRegisterInfo ( ) ;


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override {


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override { return & TSInfo ;


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) { static Target The<ISA_LIT>Target ; return The<ISA_LIT>Target ;


<s> addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ;


<s> addPass ( new InstructionSelect ( getOptLevel ( ) ) ) ; return false ;


<s> bool <ISA_LIT>PassConfig :: addIRTranslator ( ) {


<s> bool <ISA_LIT>PassConfig :: addLegalizeMachineIR ( ) { addPass ( new Legalizer ( ) ) ; return false ;


<s> if ( BranchRelaxation ) addPass ( & BranchRelaxationPassID ) ; if ( ! DisableDelaySlotFiller ) addPass ( create<ISA_LIT>DelaySlotFiller ( ) ) ;


<s> void <ISA_LIT>PassConfig :: addPreLegalizeMachineIR ( ) { addPass ( create<ISA_LIT>PreLegalizerCombiner ( ) ) ;


<s> addPass ( create<ISA_LIT>PreLegalizerCombiner ( ) ) ;


<s> void <ISA_LIT>PassConfig :: addPreRegBankSelect ( ) {

addPass ( create<ISA_LIT>PostLegalizerLowering ( ) ) ;


<s> std :: string Ret ; Ret += <STR_LIT> ; Ret += DataLayout :: getManglingComponent ( TT ) ;


<s> Reloc :: Model getEffectiveRelocModel ( Optional < Reloc :: Model > RM ) {

if ( ! RM . hasValue ( ) || * RM == Reloc :: DynamicNoPIC ) return Reloc :: Static ;


<s> return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> TargetLoweringObjectFile * getObjFileLowering ( ) const override {


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;

PassRegistry & PR = * PassRegistry :: getPassRegistry ( ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT , CPU , FS ) , TT , CPU , FS , Options , getEffectiveRelocModel ( RM ) , getEffectiveCodeModel ( CM , CodeModel :: Medium ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo ( ) ; setGlobalISel ( true ) ;

setGlobalISelAbort ( GlobalISelAbortMode :: Enable ) ;


<s> <ISA_LIT>TargetMachine :: ~ <ISA_LIT>TargetMachine ( ) {


<s> void <ISA_LIT>TargetELFStreamer :: emitDirectiveRequires881100 ( ) {


<s> void <ISA_LIT>TargetELFStreamer :: finish ( ) { MCAssembler & MCA = getStreamer ( ) . getAssembler ( ) ;

unsigned EFlags = MCA . getELFHeaderEFlags ( ) ;


<s> return static_cast < MCELFStreamer & > ( Streamer ) ;


<s> <ISA_LIT>TargetAsmStreamer :: <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : <ISA_LIT>TargetStreamer ( S ) , OS ( OS ) {


<s> <ISA_LIT>TargetELFStreamer :: <ISA_LIT>TargetELFStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) : <ISA_LIT>TargetStreamer ( S ) , STI ( STI ) , Streamer ( S ) , Requires88110 ( STI . getCPU ( ) == <STR_LIT> ) {


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) {