return BaseType == Base :: FrameIndexBase || BaseReg . getNode ( ) != nullptr ;


<s> return BaseType == Base :: RegBase && BaseReg . getNode ( ) != nullptr ;


return BaseType == Base :: RegBase && BaseReg . getNode ( ) != nullptr ;


<s> return GV != nullptr || CP != nullptr || ES != nullptr || MCSym != nullptr || JT != - <NUM_LIT> || BlockAddr != nullptr ;


<s> case <STR_LIT> : return llvm :: any_of ( N . getNode ( ) -> ops ( ) , [ ] ( const SDUse & U ) { return isAddressBase ( U . get ( ) ) ; } ) ; case <STR_LIT> : case <STR_LIT> :


<s> return llvm :: any_of ( N . getNode ( ) -> ops ( ) , [ ] ( const SDUse & U ) { return isAddressBase ( U . get ( ) ) ; } ) ; case <STR_LIT> :


<s> return AM == AddrType :: ARII || AM == AddrType :: PCI || AM == AddrType :: ARID || AM == AddrType :: PCD || AM == AddrType :: AL ;


if ( BaseType != Base :: RegBase ) return false ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) , Subtarget ( nullptr ) {


<s> <ISA_LIT>ISelAddressMode ( AddrType AT ) : AM ( AT ) , BaseType ( Base :: RegBase ) , Disp ( <NUM_LIT> ) , BaseFrameIndex ( <NUM_LIT> ) , IndexReg ( ) , Scale ( <NUM_LIT> ) , GV ( nullptr ) , CP ( nullptr ) , BlockAddr ( nullptr ) , ES ( nullptr ) , MCSym ( nullptr ) , JT ( - <NUM_LIT> ) , Alignment ( ) , SymbolFlags ( <STR_LIT> ) {


<s> if ( matchAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) && matchAddressRecursively ( Handle . getValue ( ) . getOperand ( <NUM_LIT> ) , AM , Depth + <NUM_LIT> ) ) { return true ; } AM = Backup ; if ( ! AM . hasBase ( ) && ! AM . hasIndexReg ( ) ) { N = Handle . getValue ( ) ; AM . BaseReg = N . getOperand ( <NUM_LIT> ) ; AM . IndexReg = N . getOperand ( <NUM_LIT> ) ; AM . Scale = <NUM_LIT> ;


<s> return true ; } AM = Backup ; if ( ! AM . hasBase ( ) && ! AM . hasIndexReg ( ) ) { N = Handle . getValue ( ) ; AM . BaseReg = N . getOperand ( <NUM_LIT> ) ; AM . IndexReg = N . getOperand ( <NUM_LIT> ) ; AM . Scale = <NUM_LIT> ; return true ; } N = Handle . getValue ( ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: matchAddress ( SDValue N , <ISA_LIT>ISelAddressMode & AM ) { return matchAddressRecursively ( N , AM , <NUM_LIT> ) ;


<s> return false ; } AM . BaseType = <ISA_LIT>ISelAddressMode :: Base :: RegBase ; AM . BaseReg = N ; return true ;


<s> bool <ISA_LIT>DAGToDAGISel :: matchLoadInAddress ( LoadSDNode * N , <ISA_LIT>ISelAddressMode & AM ) {


<s> if ( N . getOpcode ( ) == <STR_LIT> ) { if ( auto * G = dyn_cast < GlobalAddressSDNode > ( N0 ) ) { AM . GV = G -> getGlobal ( ) ; AM . Disp += G -> getOffset ( ) ; AM . SymbolFlags = G -> getTargetFlags ( ) ; } else if ( auto * CP = dyn_cast < ConstantPoolSDNode > ( N0 ) ) { AM . CP = CP -> getConstVal ( ) ; AM . Alignment = CP -> getAlign ( ) ; AM . Disp += CP -> getOffset ( ) ; AM . SymbolFlags = CP -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < ExternalSymbolSDNode > ( N0 ) ) { AM . ES = S -> getSymbol ( ) ; AM . SymbolFlags = S -> getTargetFlags ( ) ; } else if ( auto * S = dyn_cast < MCSymbolSDNode > ( N0 ) ) { AM . MCSym = S -> getMCSymbol ( ) ; } else if ( auto * J = dyn_cast < JumpTableSDNode > ( N0 ) ) { AM . JT = J -> getIndex ( ) ; AM . SymbolFlags = J -> getTargetFlags ( ) ; } else if ( auto * BA = dyn_cast < BlockAddressSDNode > ( N0 ) ) { AM . BlockAddr = BA -> getBlockAddress ( ) ; AM . Disp += BA -> getOffset ( ) ; AM . SymbolFlags = BA -> getTargetFlags ( ) ; } else llvm_unreachable ( <STR_LIT> ) ; return true ; }


<s> Subtarget = & static_cast < const <ISA_LIT>Subtarget & > ( MF . getSubtarget ( ) ) ;

return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> SDLoc DL ( Node ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << '\n' ) ; if ( Node -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; Node -> dump ( CurDAG ) ; dbgs ( ) << '\n' ) ;


<s> <ISA_LIT>ISelAddressMode AM ( <ISA_LIT>ISelAddressMode :: AddrType :: AL ) ; if ( ! matchAddress ( N , AM ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( AM . isPCRelative ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( AM . hasBase ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( AM . hasIndexReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( getSymbolicDisplacement ( AM , SDLoc ( N ) , Sym ) ) {


<s> <ISA_LIT>ISelAddressMode AM ( <ISA_LIT>ISelAddressMode :: AddrType :: ARI ) ; if ( ! matchAddress ( N , AM ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( AM . isPCRelative ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( AM . hasIndexReg ( ) || AM . Disp != <NUM_LIT> ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> return false ; } if ( getFrameIndexAddress ( AM , SDLoc ( N ) , Disp , Base ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } if ( AM . hasIndexReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! AM . hasBaseReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( getSymbolicDisplacement ( AM , SDLoc ( N ) , Disp ) ) { assert ( ! AM . Disp && <STR_LIT> ) ;


<s> if ( ! matchAddress ( N , AM ) ) return false ; if ( AM . isPCRelative ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( getFrameIndexAddress ( AM , SDLoc ( N ) , Disp , Base ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } if ( AM . hasIndexReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! AM . hasBaseReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( getSymbolicDisplacement ( AM , SDLoc ( N ) , Disp ) ) { assert ( ! AM . Disp && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; } if ( AM . Disp == <NUM_LIT> ) {


<s> if ( AM . hasSymbolicDisplacement ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( AM . Disp == <NUM_LIT> && ( ! Parent || ( Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; }

Disp = getI8Imm ( AM . Disp , SDLoc ( N ) ) ;


<s> if ( AM . isPCRelative ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! AM . hasIndexReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! AM . hasBaseReg ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( ! isAddressBase ( AM . BaseReg ) && isAddressBase ( AM . IndexReg ) ) { Base = AM . IndexReg ; Index = AM . BaseReg ; } else { Base = AM . BaseReg ; Index = AM . IndexReg ; } if ( AM . hasSymbolicDisplacement ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( AM . Disp == <NUM_LIT> && ( ! Parent || ( Parent -> getOpcode ( ) != <STR_LIT> && Parent -> getOpcode ( ) != <STR_LIT> ) ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Disp = getI8Imm ( AM . Disp , SDLoc ( N ) ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectARIPD ( SDNode * Parent , SDValue N , SDValue & Base ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: SelectARIPI ( SDNode * Parent , SDValue N , SDValue & Base ) {


<s> bool <ISA_LIT>DAGToDAGISel :: SelectPCD ( SDNode * Parent , SDValue N , SDValue & Disp ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; <ISA_LIT>ISelAddressMode AM ( <ISA_LIT>ISelAddressMode :: AddrType :: PCD ) ; if ( ! matchAddress ( N , AM ) ) return false ; if ( ! AM . isPCRelative ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } if ( AM . hasIndexReg ( ) ) {


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return false ; } Index = AM . IndexReg ; if ( getSymbolicDisplacement ( AM , SDLoc ( N ) , Disp ) ) { assert ( ! AM . Disp && <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ) ; return true ; }


<s> void setBaseReg ( SDValue Reg ) { BaseType = Base :: RegBase ; BaseReg = Reg ;


<s> void setIndexReg ( SDValue Reg ) { IndexReg = Reg ;


<s> if ( CascadedCMOV ) { unsigned Opc2 = <STR_LIT> ( ( <STR_LIT> ) CascadedCMOV -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( Jcc1MBB , DL , TII -> get ( Opc2 ) ) . addMBB ( SinkMBB ) ; } Copy0MBB -> addSuccessor ( SinkMBB ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; MachineInstrBuilder MIB ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { unsigned DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) std :: swap ( Op1Reg , Op2Reg ) ; if ( RegRewriteTable . find ( Op1Reg ) != RegRewriteTable . end ( ) ) Op1Reg = RegRewriteTable [ Op1Reg ] . first ; if ( RegRewriteTable . find ( Op2Reg ) != RegRewriteTable . end ( ) ) Op2Reg = RegRewriteTable [ Op2Reg ] . second ; MIB = BuildMI ( * SinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( Op1Reg ) . addMBB ( Copy0MBB ) . addReg ( Op2Reg ) . addMBB ( ThisMBB ) ; RegRewriteTable [ DestReg ] = std :: make_pair ( Op1Reg , Op2Reg ) ; } if ( CascadedCMOV ) { MIB . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( Jcc1MBB ) ;

BuildMI ( * SinkMBB , std :: next ( MachineBasicBlock :: iterator ( MIB . getInstr ( ) ) ) , DL , TII -> get ( TargetOpcode :: COPY ) , CascadedCMOV -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) ;


<s> CascadedCMOV = & * NextMIIt ; } MachineBasicBlock * Jcc1MBB = nullptr ; if ( CascadedCMOV ) { Jcc1MBB = F -> CreateMachineBasicBlock ( BB ) ; F -> insert ( It , Jcc1MBB ) ; Jcc1MBB -> addLiveIn ( <STR_LIT> ) ; } MachineBasicBlock * Copy0MBB = F -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( BB ) ; F -> insert ( It , Copy0MBB ) ; F -> insert ( It , SinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; MachineInstr * LastCCRSUser = CascadedCMOV ? CascadedCMOV : LastCMOV ; if ( ! LastCCRSUser -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateCCRKill ( LastCCRSUser , MBB , TRI ) ) { Copy0MBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , MBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; if ( CascadedCMOV ) { MBB -> addSuccessor ( Jcc1MBB ) ; Jcc1MBB -> addSuccessor ( Copy0MBB ) ; Jcc1MBB -> addSuccessor ( SinkMBB ) ; } else { MBB -> addSuccessor ( Copy0MBB ) ; } MBB -> addSuccessor ( SinkMBB ) ; unsigned Opc = <STR_LIT> ( CC ) ; BuildMI ( MBB , DL , TII -> get ( Opc ) ) . addMBB ( SinkMBB ) ; if ( CascadedCMOV ) { unsigned Opc2 = <STR_LIT> ( ( <STR_LIT> ) CascadedCMOV -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( Jcc1MBB , DL , TII -> get ( Opc2 ) ) . addMBB ( SinkMBB ) ; } Copy0MBB -> addSuccessor ( SinkMBB ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; MachineInstrBuilder MIB ;

for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) {


<s> SDValue BT = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , BitNo ) ; <STR_LIT> Cond = CC == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( Cond , DL , <STR_LIT> ) , BT ) ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> } unsigned StackArgsSize = <NUM_LIT> ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , IsVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; StackArgsSize = CCInfo . getNextStackOffset ( ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII , VA ) ) return false ; } } } bool PositionIndependent = isPositionIndependent ( ) ; if ( ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) || PositionIndependent ) { unsigned NumInRegs = <NUM_LIT> ; unsigned MaxInRegs = PositionIndependent ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ;


<s> } LHS = Op1 ; RHS = Op0 . getOperand ( <NUM_LIT> ) ; } } else if ( auto * AndRHS = dyn_cast < ConstantSDNode > ( Op1 ) ) { uint64_t AndRHSVal = AndRHS -> getZExtValue ( ) ; SDValue AndLHS = Op0 ; if ( AndRHSVal == <NUM_LIT> && AndLHS . getOpcode ( ) == <STR_LIT> ) { LHS = AndLHS . getOperand ( <NUM_LIT> ) ; RHS = AndLHS . getOperand ( <NUM_LIT> ) ; } if ( ! isUInt < <NUM_LIT> > ( AndRHSVal ) && isPowerOf2_64 ( AndRHSVal ) ) { LHS = AndLHS ;

RHS = DAG . getConstant ( Log2_64_Ceil ( AndRHSVal ) , DL , LHS . getValueType ( ) ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; } if ( Inverted ) MxCond = <STR_LIT> ( ( <STR_LIT> ) MxCond ) ; if ( CondOpcode == <STR_LIT> ) VTs = DAG . getVTList ( LHS . getValueType ( ) , LHS . getValueType ( ) , <STR_LIT> ) ; else VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue MxOp = DAG . getNode ( MxOpcode , DL , VTs , LHS , RHS ) ; if ( CondOpcode == <STR_LIT> ) Cond = MxOp . getValue ( <NUM_LIT> ) ; else Cond = MxOp . getValue ( <NUM_LIT> ) ; CC = DAG . getConstant ( MxCond , DL , <STR_LIT> ) ; AddTest = false ; } else { unsigned CondOpc ; if ( Cond . hasOneUse ( ) && isAndOrOfSetCCs ( Cond , CondOpc ) ) { SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( CondOpc == <STR_LIT> ) { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) ) { CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Cond = Cmp ; AddTest = false ; } } else { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) && Op . getNode ( ) -> hasOneUse ( ) ) { <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; CC = DAG . getConstant ( CCode , DL , <STR_LIT> ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> ) { SDValue FalseBB = User -> getOperand ( <NUM_LIT> ) ; SDNode * NewBR = DAG . UpdateNodeOperands ( User , User -> getOperand ( <NUM_LIT> ) , Dest ) ; assert ( NewBR == User ) ; ( void ) NewBR ; Dest = FalseBB ; Chain = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; CC = DAG . getConstant ( CCode , DL , <STR_LIT> ) ; Cond = Cmp ; AddTest = false ;


<s> MxCond = <STR_LIT> ; break ; case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( Inverted ) MxCond = <STR_LIT> ( ( <STR_LIT> ) MxCond ) ; if ( CondOpcode == <STR_LIT> ) VTs = DAG . getVTList ( LHS . getValueType ( ) , LHS . getValueType ( ) , <STR_LIT> ) ; else VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue MxOp = DAG . getNode ( MxOpcode , DL , VTs , LHS , RHS ) ; if ( CondOpcode == <STR_LIT> ) Cond = MxOp . getValue ( <NUM_LIT> ) ; else Cond = MxOp . getValue ( <NUM_LIT> ) ; CC = DAG . getConstant ( MxCond , DL , <STR_LIT> ) ; AddTest = false ; } else { unsigned CondOpc ; if ( Cond . hasOneUse ( ) && isAndOrOfSetCCs ( Cond , CondOpc ) ) { SDValue Cmp = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; if ( CondOpc == <STR_LIT> ) { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) ) { CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Chain = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ; CC = Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; Cond = Cmp ; AddTest = false ; } } else { if ( Cmp == Cond . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) && is<ISA_LIT>LogicalCmp ( Cmp ) && Op . getNode ( ) -> hasOneUse ( ) ) { <STR_LIT> CCode = ( <STR_LIT> ) Cond . getOperand ( <NUM_LIT> ) . getConstantOperandVal ( <NUM_LIT> ) ; CCode = <STR_LIT> ( CCode ) ; CC = DAG . getConstant ( CCode , DL , <STR_LIT> ) ; SDNode * User = * Op . getNode ( ) -> use_begin ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> ) { SDValue FalseBB = User -> getOperand ( <NUM_LIT> ) ; SDNode * NewBR = DAG . UpdateNodeOperands ( User , User -> getOperand ( <NUM_LIT> ) , Dest ) ; assert ( NewBR == User ) ; ( void ) NewBR ; Dest = FalseBB ; Chain = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , Chain , Dest , CC , Cmp ) ;


<s> EVT VT = Node -> getValueType ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , <NUM_LIT> , <NUM_LIT> , DL ) ; SDValue Result ; if ( SplitStack ) { auto & MRI = MF . getRegInfo ( ) ; auto SPTy = getPointerTy ( DAG . getDataLayout ( ) ) ; auto * ARClass = getRegClassFor ( SPTy ) ; unsigned Vreg = MRI . createVirtualRegister ( ARClass ) ; Chain = DAG . getCopyToReg ( Chain , DL , Vreg , Size ) ; Result = DAG . getNode ( <STR_LIT> , DL , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; } else { auto & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned SPReg = TLI . getStackPointerRegisterToSaveRestore ( ) ; assert ( SPReg && <STR_LIT> <STR_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , DL , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; const TargetFrameLowering & TFI = * Subtarget . getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Result = DAG . getNode ( <STR_LIT> , DL , VT , SP , Size ) ; if ( Align > StackAlign ) Result = DAG . getNode ( <STR_LIT> , DL , VT , Result , DAG . getConstant ( - ( uint64_t ) Align , DL , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , Result ) ; } Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , SDValue ( ) , DL ) ;

SDValue Ops [ <NUM_LIT> ] = { Result , Chain } ;


<s> SDNode * Node = Op . getNode ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , <NUM_LIT> , <NUM_LIT> , DL ) ; SDValue Result ; if ( SplitStack ) { auto & MRI = MF . getRegInfo ( ) ; auto SPTy = getPointerTy ( DAG . getDataLayout ( ) ) ; auto * ARClass = getRegClassFor ( SPTy ) ; unsigned Vreg = MRI . createVirtualRegister ( ARClass ) ; Chain = DAG . getCopyToReg ( Chain , DL , Vreg , Size ) ; Result = DAG . getNode ( <STR_LIT> , DL , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; } else { auto & TLI = DAG . getTargetLoweringInfo ( ) ; unsigned SPReg = TLI . getStackPointerRegisterToSaveRestore ( ) ; assert ( SPReg && <STR_LIT> <STR_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , DL , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ;

const TargetFrameLowering & TFI = * Subtarget . getFrameLowering ( ) ;


<s> case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCCCARRY ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT ( Op , DAG ) ; case <STR_LIT> : return LowerBRCOND ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerADDC_ADDE_SUBC_SUBE ( Op , DAG ) ; case <STR_LIT> : return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ;


<s> case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; case <STR_LIT> : MxOpcode = <STR_LIT> ; MxCond = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } if ( CondOpcode == <STR_LIT> ) VTs = DAG . getVTList ( LHS . getValueType ( ) , LHS . getValueType ( ) , <STR_LIT> ) ; else VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue MxOp = DAG . getNode ( MxOpcode , DL , VTs , LHS , RHS ) ; if ( CondOpcode == <STR_LIT> ) Cond = MxOp . getValue ( <NUM_LIT> ) ; else Cond = MxOp . getValue ( <NUM_LIT> ) ; CC = DAG . getConstant ( MxCond , DL , <STR_LIT> ) ; addTest = false ; } if ( addTest ) { if ( isTruncWithZeroHighBitsInput ( Cond , DAG ) ) Cond = Cond . getOperand ( <NUM_LIT> ) ; if ( Cond . getOpcode ( ) == <STR_LIT> && Cond . hasOneUse ( ) ) { if ( SDValue NewSetCC = LowerToBT ( Cond , <STR_LIT> , DL , DAG ) ) { CC = NewSetCC . getOperand ( <NUM_LIT> ) ; Cond = NewSetCC . getOperand ( <NUM_LIT> ) ; addTest = false ; } } } if ( addTest ) { CC = DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) ; Cond = EmitTest ( Cond , <STR_LIT> , DL , DAG ) ; } if ( Cond . getOpcode ( ) == <STR_LIT> ) { unsigned CondCode = cast < ConstantSDNode > ( CC ) -> getZExtValue ( ) ; if ( ( CondCode == <STR_LIT> || CondCode == <STR_LIT> ) && ( isAllOnesConstant ( Op1 ) || isAllOnesConstant ( Op2 ) ) && ( isNullConstant ( Op1 ) || isNullConstant ( Op2 ) ) ) { SDValue Res = DAG . getNode ( <STR_LIT> , DL , Op . getValueType ( ) , DAG . getConstant ( <STR_LIT> , DL , <STR_LIT> ) , Cond ) ; if ( isAllOnesConstant ( Op1 ) != ( CondCode == <STR_LIT> ) ) return DAG . getNOT ( DL , Res , Res . getValueType ( ) ) ; return Res ; } } if ( Op . getValueType ( ) == <STR_LIT> && Op1 . getOpcode ( ) == <STR_LIT> && Op2 . getOpcode ( ) == <STR_LIT> ) { SDValue T1 = Op1 . getOperand ( <NUM_LIT> ) , T2 = Op2 . getOperand ( <NUM_LIT> ) ;

if ( T1 . getValueType ( ) == T2 . getValueType ( ) && T1 . getOpcode ( ) != <STR_LIT> && T2 . getOpcode ( ) != <STR_LIT> ) {


<s> if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CCode , DL , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( Op0 . getValueType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isOneConstant ( Op1 ) ) { <STR_LIT> NewCC = <STR_LIT> :: getSetCCInverse ( CC , true ) ; return DAG . getSetCC ( DL , VT , Op0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , NewCC ) ;


<s> Carry = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( CarryVT , <STR_LIT> ) , Carry , DAG . getConstant ( NegOne , DL , CarryVT ) ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ; SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry . getValue ( <NUM_LIT> ) ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CC , DL , <STR_LIT> ) , Cmp . getValue ( <NUM_LIT> ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerToBT ( SDValue Op , <STR_LIT> CC , const SDLoc & DL , SelectionDAG & DAG ) const {

if ( Op . getOpcode ( ) == <STR_LIT> ) return LowerAndToBT ( Op , CC , DL , DAG ) ;


<s> SDValue ShiftRight = Op . getOperand ( <NUM_LIT> ) ;

return getBitTestCondition ( ShiftRight . getOperand ( <NUM_LIT> ) , ShiftRight . getOperand ( <NUM_LIT> ) , CC , DL , DAG ) ;


<s> assert ( Op . getOpcode ( ) == <STR_LIT> && Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShiftRight = Op . getOperand ( <NUM_LIT> ) ;


<s> setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; if ( Subtarget . atLeastM68020 ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; else setOperationAction ( <STR_LIT> , <STR_LIT> , LibCall ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , LibCall ) ; for ( auto OP : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { setOperationAction ( OP , <STR_LIT> , Promote ) ; setOperationAction ( OP , <STR_LIT> , Legal ) ; setOperationAction ( OP , <STR_LIT> , LibCall ) ; } for ( auto OP : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( OP , <STR_LIT> , Expand ) ; setOperationAction ( OP , <STR_LIT> , Expand ) ; } for ( auto OP : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( OP , <STR_LIT> , Expand ) ; setOperationAction ( OP , <STR_LIT> , Expand ) ; setOperationAction ( OP , <STR_LIT> , Expand ) ; } for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , VT , Custom ) ;


<s> setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; } setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; if ( Subtarget . atLeastM68020 ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; else setOperationAction ( <STR_LIT> , <STR_LIT> , LibCall ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , LibCall ) ; for ( auto OP : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { setOperationAction ( OP , <STR_LIT> , Promote ) ; setOperationAction ( OP , <STR_LIT> , Legal ) ; setOperationAction ( OP , <STR_LIT> , LibCall ) ; } for ( auto OP : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( OP , <STR_LIT> , Expand ) ; setOperationAction ( OP , <STR_LIT> , Expand ) ; } for ( auto OP : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( OP , <STR_LIT> , Expand ) ; setOperationAction ( OP , <STR_LIT> , Expand ) ; setOperationAction ( OP , <STR_LIT> , Expand ) ; } for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) {


<s> } else { unsigned Opcode = Def -> getOpcode ( ) ; if ( ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) && Def -> getOperand ( <NUM_LIT> ) . isFI ( ) ) { FI = Def -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; } } else if ( auto * Ld = dyn_cast < LoadSDNode > ( Arg ) ) { if ( Flags . isByVal ( ) ) return false ; SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else if ( Arg . getOpcode ( ) == <STR_LIT> && Flags . isByVal ( ) ) { FrameIndexSDNode * FINode = cast < FrameIndexSDNode > ( Arg ) ; FI = FINode -> getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; assert ( FI != INT_MAX ) ;

if ( ! MFI . isFixedObjectIndex ( FI ) ) return false ;


<s> if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) ArgValue = DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ; InVals . push_back ( ArgValue ) ; } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { if ( CCID == CallingConv :: Swift ) continue ; if ( Ins [ i ] . Flags . isSRet ( ) ) { unsigned Reg = MMFI -> getSRetReturnReg ( ) ; if ( ! Reg ) { MVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( PtrTy ) ) ; MMFI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ i ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; break ; } } unsigned StackSize = CCInfo . getNextStackOffset ( ) ; if ( shouldGuaranteeTCO ( CCID , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ) StackSize = GetAlignedArgumentStackSize ( StackSize , DAG ) ; if ( MFI . hasVAStart ( ) ) { MMFI -> setVarArgsFrameIndex ( MFI . CreateFixedObject ( <NUM_LIT> , StackSize , true ) ) ; } if ( IsVarArg && MFI . hasMustTailInVarArgFunc ( ) ) { SmallVector < MVT , <NUM_LIT> > RegParmTypes ; MVT IntVT = <STR_LIT> ; RegParmTypes . push_back ( IntVT ) ; SmallVectorImpl < ForwardedRegister > & Forwards = MMFI -> getForwardedMustTailRegParms ( ) ; CCInfo . analyzeMustTailForwardedRegisters ( Forwards , RegParmTypes , CC_<ISA_LIT> ) ; for ( ForwardedRegister & F : Forwards ) { SDValue RegVal = DAG . getCopyFromReg ( Chain , DL , F . VReg , F . VT ) ; F . VReg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( F . VT ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , F . VReg , RegVal ) ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; SmallVector < Type * , <NUM_LIT> > ArgTypes ; for ( const Argument & Arg : MF . getFunction ( ) . args ( ) ) ArgTypes . emplace_back ( Arg . getType ( ) ) ; <ISA_LIT>CCState CCInfo ( ArgTypes , CCID , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT> ) ; unsigned LastVal = ~ <NUM_LIT> ; SDValue ArgValue ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; assert ( VA . getValNo ( ) != LastVal && <STR_LIT> ) ; LastVal = VA . getValNo ( ) ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; const TargetRegisterClass * RC ; if ( RegVT == <STR_LIT> ) RC = & <STR_LIT> ; else llvm_unreachable ( <STR_LIT> ) ; unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) { ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) { ArgValue = DAG . getNode ( <STR_LIT> , DL , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) { ArgValue = DAG . getBitcast ( VA . getValVT ( ) , ArgValue ) ; } if ( VA . isExtInLoc ( ) ) { ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; } } else {


return <STR_LIT> ( DL . getPointerSizeInBits ( <NUM_LIT> ) ) ;


<s> if ( Ins . empty ( ) ) return NotStructReturn ; const <STR_LIT> & Flags = Ins [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) ) return RegStructReturn ;


<s> if ( ! Flags . isSRet ( ) ) return NotStructReturn ;

if ( Flags . isInReg ( ) ) return RegStructReturn ;


<s> if ( Outs . empty ( ) ) return NotStructReturn ; const <STR_LIT> & Flags = Outs [ <NUM_LIT> ] . Flags ; if ( ! Flags . isSRet ( ) ) return NotStructReturn ; if ( Flags . isInReg ( ) ) return RegStructReturn ; return StackStructReturn ;


<s> static bool canGuaranteeTCO ( CallingConv :: ID CC ) { return false ;


<s> if ( mi . definesRegister ( <STR_LIT> ) ) break ; } if ( miI == BB -> end ( ) ) for ( const auto * SBB : BB -> successors ( ) ) if ( SBB -> isLiveIn ( <STR_LIT> ) ) return false ;

SelectItr -> addRegisterKilled ( <STR_LIT> , TRI ) ;


<s> for ( MachineBasicBlock :: iterator miE = BB -> end ( ) ; miI != miE ; ++ miI ) { const MachineInstr & mi = * miI ; if ( mi . readsRegister ( <STR_LIT> ) ) return false ; if ( mi . definesRegister ( <STR_LIT> ) ) break ; } if ( miI == BB -> end ( ) ) for ( const auto * SBB : BB -> successors ( ) ) if ( SBB -> isLiveIn ( <STR_LIT> ) ) return false ; SelectItr -> addRegisterKilled ( <STR_LIT> , TRI ) ;


<s> SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Flags ) ;


<s> while ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> || ( Carry . getOpcode ( ) == <STR_LIT> && isOneConstant ( Carry . getOperand ( <NUM_LIT> ) ) ) ) Carry = Carry . getOperand ( <NUM_LIT> ) ; if ( Carry . getOpcode ( ) == <STR_LIT> || Carry . getOpcode ( ) == <STR_LIT> ) { if ( Carry . getConstantOperandVal ( <NUM_LIT> ) == <STR_LIT> ) return Carry . getOperand ( <NUM_LIT> ) ; }


<s> static SDValue combine<ISA_LIT>BrCond ( SDNode * N , SelectionDAG & DAG , const <ISA_LIT>Subtarget & Subtarget ) { SDLoc DL ( N ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ;

SDValue CCR = N -> getOperand ( <NUM_LIT> ) ;


<s> SDLoc DL ( N ) ; <STR_LIT> CC = <STR_LIT> ( N -> getConstantOperandVal ( <NUM_LIT> ) ) ; SDValue CCR = N -> getOperand ( <NUM_LIT> ) ; if ( SDValue Flags = combineSetCCCCR ( CCR , CC , DAG , Subtarget ) ) return getSETCC ( CC , Flags , DL , DAG ) ; return SDValue ( ) ;


<s> if ( SDValue Flags = combineSetCCCCR ( CCR , CC , DAG , Subtarget ) ) return getSETCC ( CC , Flags , DL , DAG ) ; return SDValue ( ) ;


<s> if ( CC == <STR_LIT> ) if ( SDValue Flags = combineCarryThroughADD ( CCR ) ) return Flags ;


<s> return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Flags ) ; }


<s> MVT VT = N -> getSimpleValueType ( <NUM_LIT> ) ; SDVTList VTs = DAG . getVTList ( VT , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( N ) , VTs , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , Flags ) ;


<s> SDValue SizeNode = DAG . getConstant ( Flags . getByValSize ( ) , DL , <STR_LIT> ) ;

return DAG . getMemcpy ( Chain , DL , Dst , Src , SizeNode , Flags . getNonZeroByValAlign ( ) , false , true , false , MachinePointerInfo ( ) , MachinePointerInfo ( ) ) ;


<s> return VT . bitsLE ( <STR_LIT> ) || Subtarget . atLeastM68020 ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: EmitCmp ( SDValue Op0 , SDValue Op1 , unsigned <ISA_LIT>CC , const SDLoc & DL , SelectionDAG & DAG ) const { if ( isNullConstant ( Op1 ) ) return EmitTest ( Op0 , <ISA_LIT>CC , DL , DAG ) ; assert ( ! ( isa < ConstantSDNode > ( Op1 ) && Op0 . getValueType ( ) == <STR_LIT> ) && <STR_LIT> ) ; if ( ( Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> || Op0 . getValueType ( ) == <STR_LIT> ) ) { if ( ( Op0 . getValueType ( ) == <STR_LIT> && ( isa < ConstantSDNode > ( Op0 ) || isa < ConstantSDNode > ( Op1 ) ) ) && ! DAG . getMachineFunction ( ) . getFunction ( ) . hasMinSize ( ) ) { unsigned ExtendOp = is<ISA_LIT>CCUnsigned ( <ISA_LIT>CC ) ? <STR_LIT> : <STR_LIT> ;

Op0 = DAG . getNode ( ExtendOp , DL , <STR_LIT> , Op0 ) ;


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitLoweredSegAlloca ( MachineInstr & MI , MachineBasicBlock * BB ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> if ( ! LastCCRSUser -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateCCRKill ( LastCCRSUser , MBB , TRI ) ) { Copy0MBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , MBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; if ( CascadedCMOV ) { MBB -> addSuccessor ( Jcc1MBB ) ; Jcc1MBB -> addSuccessor ( Copy0MBB ) ; Jcc1MBB -> addSuccessor ( SinkMBB ) ; } else { MBB -> addSuccessor ( Copy0MBB ) ; } MBB -> addSuccessor ( SinkMBB ) ; unsigned Opc = <STR_LIT> ( CC ) ; BuildMI ( MBB , DL , TII -> get ( Opc ) ) . addMBB ( SinkMBB ) ; if ( CascadedCMOV ) { unsigned Opc2 = <STR_LIT> ( ( <STR_LIT> ) CascadedCMOV -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( Jcc1MBB , DL , TII -> get ( Opc2 ) ) . addMBB ( SinkMBB ) ; } Copy0MBB -> addSuccessor ( SinkMBB ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; MachineInstrBuilder MIB ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { Register DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; if ( MIIt -> getOperand ( <NUM_LIT> ) . getImm ( ) == OppCC ) std :: swap ( Op1Reg , Op2Reg ) ; if ( RegRewriteTable . find ( Op1Reg ) != RegRewriteTable . end ( ) ) Op1Reg = RegRewriteTable [ Op1Reg ] . first ; if ( RegRewriteTable . find ( Op2Reg ) != RegRewriteTable . end ( ) ) Op2Reg = RegRewriteTable [ Op2Reg ] . second ;

MIB = BuildMI ( * SinkMBB , SinkInsertionPoint , DL , TII -> get ( <STR_LIT> ) , DestReg ) . addReg ( Op1Reg ) . addMBB ( Copy0MBB ) . addReg ( Op2Reg ) . addMBB ( ThisMBB ) ;


<s> } MachineBasicBlock * Copy0MBB = F -> CreateMachineBasicBlock ( BB ) ; MachineBasicBlock * SinkMBB = F -> CreateMachineBasicBlock ( BB ) ; F -> insert ( It , Copy0MBB ) ; F -> insert ( It , SinkMBB ) ; const TargetRegisterInfo * TRI = Subtarget . getRegisterInfo ( ) ; MachineInstr * LastCCRSUser = CascadedCMOV ? CascadedCMOV : LastCMOV ; if ( ! LastCCRSUser -> killsRegister ( <STR_LIT> ) && ! checkAndUpdateCCRKill ( LastCCRSUser , MBB , TRI ) ) { Copy0MBB -> addLiveIn ( <STR_LIT> ) ; SinkMBB -> addLiveIn ( <STR_LIT> ) ; } SinkMBB -> splice ( SinkMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) , MBB -> end ( ) ) ; SinkMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; if ( CascadedCMOV ) { MBB -> addSuccessor ( Jcc1MBB ) ; Jcc1MBB -> addSuccessor ( Copy0MBB ) ; Jcc1MBB -> addSuccessor ( SinkMBB ) ; } else { MBB -> addSuccessor ( Copy0MBB ) ; } MBB -> addSuccessor ( SinkMBB ) ; unsigned Opc = <STR_LIT> ( CC ) ; BuildMI ( MBB , DL , TII -> get ( Opc ) ) . addMBB ( SinkMBB ) ; if ( CascadedCMOV ) { unsigned Opc2 = <STR_LIT> ( ( <STR_LIT> ) CascadedCMOV -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; BuildMI ( Jcc1MBB , DL , TII -> get ( Opc2 ) ) . addMBB ( SinkMBB ) ; } Copy0MBB -> addSuccessor ( SinkMBB ) ; MachineBasicBlock :: iterator MIItBegin = MachineBasicBlock :: iterator ( MI ) ; MachineBasicBlock :: iterator MIItEnd = std :: next ( MachineBasicBlock :: iterator ( LastCMOV ) ) ; MachineBasicBlock :: iterator SinkInsertionPoint = SinkMBB -> begin ( ) ; DenseMap < unsigned , std :: pair < unsigned , unsigned >> RegRewriteTable ; MachineInstrBuilder MIB ; for ( MachineBasicBlock :: iterator MIIt = MIItBegin ; MIIt != MIItEnd ; ++ MIIt ) { Register DestReg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ; Register Op1Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ;

Register Op2Reg = MIIt -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> OutRetAddr = getReturnAddressFrameIndex ( DAG ) ;

OutRetAddr = DAG . getLoad ( VT , DL , Chain , OutRetAddr , MachinePointerInfo ( ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: EmitTailCallLoadRetAddr ( SelectionDAG & DAG , SDValue & OutRetAddr , SDValue Chain , bool IsTailCall , int FPDiff , const SDLoc & DL ) const { EVT VT = getPointerTy ( DAG . getDataLayout ( ) ) ;

OutRetAddr = getReturnAddressFrameIndex ( DAG ) ;


<s> int NewFO = MF . getFrameInfo ( ) . CreateFixedObject ( SlotSize , ( int64_t ) FPDiff - SlotSize , false ) ; SDValue NewFI = DAG . getFrameIndex ( NewFO , PtrVT ) ;

Chain = DAG . getStore ( Chain , DL , RetFI , NewFI , MachinePointerInfo :: getFixedStack ( DAG . getMachineFunction ( ) , NewFO ) ) ;


<s> NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : if ( ( <ISA_LIT>CC == <STR_LIT> || <ISA_LIT>CC == <STR_LIT> ) && Op -> hasOneUse ( ) && isa < ConstantSDNode > ( Op -> getOperand ( <NUM_LIT> ) ) && ! hasNonFlagsUse ( Op ) ) { EVT VT = Op . getValueType ( ) ; unsigned BitWidth = VT . getSizeInBits ( ) ; unsigned ShAmt = Op -> getConstantOperandVal ( <NUM_LIT> ) ; if ( ShAmt >= BitWidth ) break ; APInt Mask = ArithOp . getOpcode ( ) == <STR_LIT> ? APInt :: getHighBitsSet ( BitWidth , BitWidth - ShAmt ) : APInt :: getLowBitsSet ( BitWidth , BitWidth - ShAmt ) ; if ( ! Mask . isSignedIntN ( <NUM_LIT> ) ) break ; Op = DAG . getNode ( <STR_LIT> , DL , VT , Op -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( Mask , DL , VT ) ) ; } break ; case <STR_LIT> : if ( ! hasNonFlagsUse ( Op ) ) { SDValue Op0 = ArithOp -> getOperand ( <NUM_LIT> ) ; SDValue Op1 = ArithOp -> getOperand ( <NUM_LIT> ) ; EVT VT = ArithOp . getValueType ( ) ; bool IsAndn = isBitwiseNot ( Op0 ) || isBitwiseNot ( Op1 ) ; bool IsLegalAndnType = VT == <STR_LIT> || VT == <STR_LIT> ; if ( ! IsAndn || ! IsLegalAndnType ) break ; } LLVM_FALLTHROUGH ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : for ( const auto * U : Op . getNode ( ) -> uses ( ) ) if ( U -> getOpcode ( ) == <STR_LIT> ) goto default_case ; switch ( ArithOp . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; case <STR_LIT> : Opcode = <STR_LIT> ; break ; } NumOperands = <NUM_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return SDValue ( Op . getNode ( ) , <NUM_LIT> ) ; default : default_case : break ; } if ( NeedTruncation ) { EVT VT = Op . getValueType ( ) ; SDValue WideVal = Op -> getOperand ( <NUM_LIT> ) ; EVT WideVT = WideVal . getValueType ( ) ; unsigned ConvertedOp = <NUM_LIT> ; switch ( WideVal . getOpcode ( ) ) { default : break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ; break ; case <STR_LIT> : ConvertedOp = <STR_LIT> ;


<s> unsigned SlotSize = Subtarget . getSlotSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask ) ) ; } else {

Offset = ( ( ~ AlignMask ) & Offset ) + StackAlignment + ( StackAlignment - SlotSize ) ;


<s> unsigned StackAlignment = TFI . getStackAlignment ( ) ; uint64_t AlignMask = StackAlignment - <NUM_LIT> ; int64_t Offset = StackSize ; unsigned SlotSize = Subtarget . getSlotSize ( ) ; if ( ( Offset & AlignMask ) <= ( StackAlignment - SlotSize ) ) { Offset += ( ( StackAlignment - SlotSize ) - ( Offset & AlignMask ) ) ;


<s> if ( Src . getValueType ( ) == <STR_LIT> || Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ; if ( Src . getValueType ( ) != BitNo . getValueType ( ) ) BitNo = DAG . getNode ( <STR_LIT> , DL , Src . getValueType ( ) , BitNo ) ; SDValue BTST = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src , BitNo ) ;


<s> if ( Src . getValueType ( ) == <STR_LIT> || Src . getValueType ( ) == <STR_LIT> ) Src = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Src ) ;

if ( Src . getValueType ( ) != BitNo . getValueType ( ) ) BitNo = DAG . getNode ( <STR_LIT> , DL , Src . getValueType ( ) , BitNo ) ;


<s> if ( Return ) return RetCC_<ISA_LIT>_C ;


<s> return C_RegisterClass ; case 'I' : case 'J' : case 'K' : case 'L' : case 'M' : case 'N' : case 'O' : case 'P' : return C_Immediate ; case 'C' : if ( Constraint . size ( ) == <NUM_LIT> ) switch ( Constraint [ <NUM_LIT> ] ) { case '0' : case 'i' : case 'j' : return C_Immediate ; default : break ; } break ; default : break ;


<s> return Subtarget . getJumpTableEncoding ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: getPICJumpTableRelocBase ( SDValue Table , SelectionDAG & DAG ) const { if ( getJumpTableEncoding ( ) == MachineJumpTableInfo :: EK_Custom32 ) return DAG . getNode ( <STR_LIT> , SDLoc ( ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ;


<s> const MCExpr * <ISA_LIT>TargetLowering :: getPICJumpTableRelocBaseExpr ( const MachineFunction * MF , unsigned JTI , MCContext & Ctx ) const { return MCSymbolRefExpr :: create ( MF -> getJTISymbol ( JTI , Ctx ) , Ctx ) ;


<s> std :: pair < unsigned , const TargetRegisterClass * > <ISA_LIT>TargetLowering :: getRegForInlineAsmConstraint ( const TargetRegisterInfo * TRI , StringRef Constraint , MVT VT ) const { if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : case 'd' : switch ( VT . SimpleTy ) { case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default : break ; } break ; case 'a' : switch ( VT . SimpleTy ) { case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default : break ; } break ;


<s> if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : case 'd' : switch ( VT . SimpleTy ) { case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; case <STR_LIT> : return std :: make_pair ( <NUM_LIT> , & <STR_LIT> ) ; default :


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int ReturnAddrIndex = FuncInfo -> getRAIndex ( ) ; if ( ReturnAddrIndex == <NUM_LIT> ) {

unsigned SlotSize = Subtarget . getSlotSize ( ) ;


return <STR_LIT> ( <NUM_LIT> * DL . getPointerSize ( <NUM_LIT> ) ) ;


<s> return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( Cond , dl , <STR_LIT> ) , CCR ) ;


<s> static SDValue getSETCC ( <STR_LIT> Cond , SDValue CCR , const SDLoc & dl , SelectionDAG & DAG ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , DAG . getConstant ( Cond , dl , <STR_LIT> ) , CCR ) ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { return <STR_LIT> ;


<s> return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> for ( SDNode :: use_iterator UI = Op -> use_begin ( ) , UE = Op -> use_end ( ) ; UI != UE ; ++ UI ) { SDNode * User = * UI ; unsigned UOpNo = UI . getOperandNo ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> && User -> hasOneUse ( ) ) { UOpNo = User -> use_begin ( ) . getOperandNo ( ) ;


<s> ++ UI ) { SDNode * User = * UI ; unsigned UOpNo = UI . getOperandNo ( ) ; if ( User -> getOpcode ( ) == <STR_LIT> && User -> hasOneUse ( ) ) { UOpNo = User -> use_begin ( ) . getOperandNo ( ) ; User = * User -> use_begin ( ) ; }

if ( User -> getOpcode ( ) != <STR_LIT> && User -> getOpcode ( ) != <STR_LIT> && ! ( User -> getOpcode ( ) == <STR_LIT> && UOpNo == <NUM_LIT> ) ) return true ;


<s> Opc = Op . getOpcode ( ) ; if ( Opc != <STR_LIT> && Opc != <STR_LIT> ) return false ; return ( <STR_LIT> ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) && Op . getOperand ( <NUM_LIT> ) . hasOneUse ( ) && <STR_LIT> ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) ) && Op . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ) ;


<s> switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ;


<s> static bool isCMOVPseudo ( MachineInstr & MI ) { switch ( MI . getOpcode ( ) ) { case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; default : return false ;


<s> unsigned StackArgsSize = <NUM_LIT> ; if ( ! Outs . empty ( ) ) { SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CalleeCC , IsVarArg , MF , ArgLocs , C ) ; CCInfo . AnalyzeCallOperands ( Outs , CC_<ISA_LIT> ) ; StackArgsSize = CCInfo . getNextStackOffset ( ) ; if ( CCInfo . getNextStackOffset ( ) ) { MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; const <ISA_LIT>InstrInfo * TII = Subtarget . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue Arg = OutVals [ i ] ; <STR_LIT> Flags = Outs [ i ] . Flags ; if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) return false ; if ( ! VA . isRegLoc ( ) ) { if ( ! MatchingStackOffset ( Arg , VA . getLocMemOffset ( ) , Flags , MFI , MRI , TII , VA ) ) return false ; } } } bool PositionIndependent = isPositionIndependent ( ) ; if ( ( ! isa < GlobalAddressSDNode > ( Callee ) && ! isa < ExternalSymbolSDNode > ( Callee ) ) || PositionIndependent ) { unsigned NumInRegs = <NUM_LIT> ; unsigned MaxInRegs = PositionIndependent ? <NUM_LIT> : <NUM_LIT> ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( ! VA . isRegLoc ( ) ) continue ; Register Reg = VA . getLocReg ( ) ; switch ( Reg ) { default : break ; case <STR_LIT> : case <STR_LIT> : if ( ++ NumInRegs == MaxInRegs ) return false ; break ; } } } const MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; if ( ! parametersInCSRMatch ( MRI , CallerPreserved , ArgLocs , OutVals ) ) return false ; } bool CalleeWillPop = <STR_LIT> ( CalleeCC , IsVarArg , MF . getTarget ( ) . Options . GuaranteedTailCallOpt ) ; if ( unsigned BytesToPop = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) -> getBytesToPopOnReturn ( ) ) { bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize ; if ( ! CalleePopMatches ) return false ; } else if ( CalleeWillPop && StackArgsSize > <NUM_LIT> ) { return false ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> :


<s> unsigned Opc = Op . getNode ( ) -> getOpcode ( ) ; if ( Opc == <STR_LIT> ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && ( Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> || Opc == <STR_LIT> ) ) return true ; if ( Op . getResNo ( ) == <NUM_LIT> && Opc == <STR_LIT> ) return true ;


<s> SDValue VOp0 = V . getOperand ( <NUM_LIT> ) ; unsigned InBits = VOp0 . getValueSizeInBits ( ) ; unsigned Bits = V . getValueSizeInBits ( ) ; return DAG . MaskedValueIsZero ( VOp0 , APInt :: getHighBitsSet ( InBits , InBits - Bits ) ) ;


<s> static bool isTruncWithZeroHighBitsInput ( SDValue V , SelectionDAG & DAG ) {

if ( V . getOpcode ( ) != <STR_LIT> ) return false ;


<s> if ( isOneConstant ( Op . getOperand ( <NUM_LIT> ) ) ) return Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ;


<s> static bool isXor1OfSetCC ( SDValue Op ) { if ( Op . getOpcode ( ) != <STR_LIT> ) return false ; if ( isOneConstant ( Op . getOperand ( <NUM_LIT> ) ) ) return Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> && Op . getOperand ( <NUM_LIT> ) . hasOneUse ( ) ; return false ;


<s> ExtraOp = true ; break ; } if ( ! ExtraOp ) return DAG . getNode ( Opc , SDLoc ( Op ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;

return DAG . getNode ( Opc , SDLoc ( Op ) , VTs , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ;


<s> static SDValue LowerAndToBTST ( SDValue And , <STR_LIT> CC , const SDLoc & DL , SelectionDAG & DAG ) { SDValue Op0 = And . getOperand ( <NUM_LIT> ) ; SDValue Op1 = And . getOperand ( <NUM_LIT> ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) Op0 = Op0 . getOperand ( <NUM_LIT> ) ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) Op1 = Op1 . getOperand ( <NUM_LIT> ) ; SDValue LHS , RHS ; if ( Op1 . getOpcode ( ) == <STR_LIT> ) std :: swap ( Op0 , Op1 ) ; if ( Op0 . getOpcode ( ) == <STR_LIT> ) { if ( isOneConstant ( Op0 . getOperand ( <NUM_LIT> ) ) ) { unsigned BitWidth = Op0 . getValueSizeInBits ( ) ; unsigned AndBitWidth = And . getValueSizeInBits ( ) ; if ( BitWidth > AndBitWidth ) {

auto Known = DAG . computeKnownBits ( Op0 ) ;


<s> if ( ! C ) return ; int64_t Val = C -> getSExtValue ( ) ; switch ( Constraint [ <NUM_LIT> ] ) { case 'I' : if ( Val > <NUM_LIT> && Val <= <NUM_LIT> ) break ; return ; case 'J' : if ( isInt < <NUM_LIT> > ( Val ) ) break ; return ; case 'K' : if ( Val < - <NUM_LIT> || Val >= <NUM_LIT> ) break ; return ; case 'L' : if ( Val < <NUM_LIT> && Val >= - <NUM_LIT> ) break ; return ; case 'M' : if ( Val < - <NUM_LIT> || Val >= <NUM_LIT> ) break ; return ; case 'N' : if ( Val >= <NUM_LIT> && Val <= <NUM_LIT> ) break ; return ; case 'O' : if ( Val == <NUM_LIT> ) break ; return ; case 'P' : if ( Val >= <NUM_LIT> && Val <= <NUM_LIT> ) break ; return ; default : llvm_unreachable ( <STR_LIT> ) ; } Result = DAG . getTargetConstant ( Val , SDLoc ( Op ) , Op . getValueType ( ) ) ; break ; } default : break ; } } if ( Constraint . size ( ) == <NUM_LIT> ) { switch ( Constraint [ <NUM_LIT> ] ) { case 'C' : switch ( Constraint [ <NUM_LIT> ] ) { case '0' : case 'i' : case 'j' : { auto * C = dyn_cast < ConstantSDNode > ( Op ) ; if ( ! C ) break ; int64_t Val = C -> getSExtValue ( ) ; switch ( Constraint [ <NUM_LIT> ] ) { case '0' : if ( ! Val ) break ; return ;


<s> Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; } else { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , Result ) ; } if ( <STR_LIT> ( OpFlags ) ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , DL , PtrVT ) , Result ) ; } return Result ;


<s> CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; EVT CopyVT = VA . getLocVT ( ) ; Chain = DAG . getCopyFromReg ( Chain , DL , VA . getLocReg ( ) , CopyVT , InFlag ) . getValue ( <NUM_LIT> ) ; SDValue Val = Chain . getValue ( <NUM_LIT> ) ; if ( VA . isExtInLoc ( ) && VA . getValVT ( ) . getScalarType ( ) == <STR_LIT> ) Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Val ) ; }


<s> MVT PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetConstantPool ( CP -> getConstVal ( ) , PtrVT , CP -> getAlign ( ) , CP -> getOffset ( ) , OpFlag ) ; SDLoc DL ( CP ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ; if ( <STR_LIT> ( OpFlag ) ) { Result = DAG . getNode ( <STR_LIT> , DL , PtrVT , DAG . getNode ( <STR_LIT> , SDLoc ( ) , PtrVT ) , Result ) ; } return Result ;


<s> return MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , MCSymbolRefExpr :: VK_GOTOFF , Ctx ) ;


<s> const MCExpr * <ISA_LIT>TargetLowering :: LowerCustomJumpTableEntry ( const MachineJumpTableInfo * MJTI , const MachineBasicBlock * MBB , unsigned uid , MCContext & Ctx ) const { return MCSymbolRefExpr :: create ( MBB -> getSymbol ( ) , MCSymbolRefExpr :: VK_GOTOFF , Ctx ) ;


<s> SDValue Size = Op . getOperand ( <NUM_LIT> ) ; unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , <NUM_LIT> , <NUM_LIT> , DL ) ; SDValue Result ; if ( SplitStack ) { auto & MRI = MF . getRegInfo ( ) ; auto SPTy = getPointerTy ( DAG . getDataLayout ( ) ) ; auto * ARClass = getRegClassFor ( SPTy ) ; Register Vreg = MRI . createVirtualRegister ( ARClass ) ; Chain = DAG . getCopyToReg ( Chain , DL , Vreg , Size ) ; Result = DAG . getNode ( <STR_LIT> , DL , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; } else { auto & TLI = DAG . getTargetLoweringInfo ( ) ;

Register SPReg = TLI . getStackPointerRegisterToSaveRestore ( ) ;


<s> unsigned Align = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; EVT VT = Node -> getValueType ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_START ( Chain , <NUM_LIT> , <NUM_LIT> , DL ) ; SDValue Result ; if ( SplitStack ) { auto & MRI = MF . getRegInfo ( ) ; auto SPTy = getPointerTy ( DAG . getDataLayout ( ) ) ; auto * ARClass = getRegClassFor ( SPTy ) ; Register Vreg = MRI . createVirtualRegister ( ARClass ) ; Chain = DAG . getCopyToReg ( Chain , DL , Vreg , Size ) ; Result = DAG . getNode ( <STR_LIT> , DL , SPTy , Chain , DAG . getRegister ( Vreg , SPTy ) ) ; } else { auto & TLI = DAG . getTargetLoweringInfo ( ) ; Register SPReg = TLI . getStackPointerRegisterToSaveRestore ( ) ; assert ( SPReg && <STR_LIT> <STR_LIT> ) ; SDValue SP = DAG . getCopyFromReg ( Chain , DL , SPReg , VT ) ; Chain = SP . getValue ( <NUM_LIT> ) ; const TargetFrameLowering & TFI = * Subtarget . getFrameLowering ( ) ; unsigned StackAlign = TFI . getStackAlignment ( ) ; Result = DAG . getNode ( <STR_LIT> , DL , VT , SP , Size ) ; if ( Align > StackAlign ) Result = DAG . getNode ( <STR_LIT> , DL , VT , Result , DAG . getConstant ( - ( uint64_t ) Align , DL , VT ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , SPReg , Result ) ; }

Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , DL , true ) , SDValue ( ) , DL ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerExternalSymbol ( SDValue Op , SelectionDAG & DAG ) const { const char * Sym = cast < ExternalSymbolSDNode > ( Op ) -> getSymbol ( ) ; const Module * Mod = DAG . getMachineFunction ( ) . getFunction ( ) . getParent ( ) ; unsigned char OpFlag = Subtarget . classifyExternalReference ( * Mod ) ; unsigned WrapperKind = <STR_LIT> ; if ( <STR_LIT> ( OpFlag ) ) {


<s> } else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) { ArgValue = DAG . getBitcast ( VA . getValVT ( ) , ArgValue ) ; } if ( VA . isExtInLoc ( ) ) { ArgValue = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , ArgValue ) ; } } else { assert ( VA . isMemLoc ( ) ) ; ArgValue = LowerMemArgument ( Chain , CCID , Ins , DL , DAG , VA , MFI , i ) ; } if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) ArgValue = DAG . getLoad ( VA . getValVT ( ) , DL , Chain , ArgValue , MachinePointerInfo ( ) ) ; InVals . push_back ( ArgValue ) ; } for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { if ( CCID == CallingConv :: Swift ) continue ; if ( Ins [ i ] . Flags . isSRet ( ) ) { unsigned Reg = MMFI -> getSRetReturnReg ( ) ; if ( ! Reg ) { MVT PtrTy = getPointerTy ( DAG . getDataLayout ( ) ) ; Reg = MF . getRegInfo ( ) . createVirtualRegister ( getRegClassFor ( PtrTy ) ) ; MMFI -> setSRetReturnReg ( Reg ) ; } SDValue Copy = DAG . getCopyToReg ( DAG . getEntryNode ( ) , DL , Reg , InVals [ i ] ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Copy , Chain ) ; break ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; return LowerGlobalAddress ( GV , SDLoc ( Op ) , Offset , DAG ) ;


<s> auto PtrVT = getPointerTy ( DAG . getDataLayout ( ) ) ; SDValue Result = DAG . getTargetJumpTable ( JT -> getIndex ( ) , PtrVT , OpFlag ) ; SDLoc DL ( JT ) ; Result = DAG . getNode ( WrapperKind , DL , PtrVT , Result ) ;


<s> if ( VA . getLocInfo ( ) == CCValAssign :: Indirect ) ValVT = VA . getLocVT ( ) ; else ValVT = VA . getValVT ( ) ; int Offset = VA . getLocMemOffset ( ) ; if ( VA . getValVT ( ) == <STR_LIT> ) { Offset += <NUM_LIT> ; } else if ( VA . getValVT ( ) == <STR_LIT> ) { Offset += <NUM_LIT> ; } bool AlwaysUseMutable = shouldGuaranteeTCO ( CallConv , DAG . getTarget ( ) . Options . GuaranteedTailCallOpt ) ; bool IsImmutable = ! AlwaysUseMutable && ! Flags . isByVal ( ) ; if ( Flags . isByVal ( ) ) {

unsigned Bytes = Flags . getByValSize ( ) ;


<s> unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , DL ) ; PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ; if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , DL ) ; return DAG . getStore ( Chain , DL , Arg , PtrOff , MachinePointerInfo :: getStack ( DAG . getMachineFunction ( ) , LocMemOffset ) ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerMemOpCallTo ( SDValue Chain , SDValue StackPtr , SDValue Arg , const SDLoc & DL , SelectionDAG & DAG , const CCValAssign & VA , <STR_LIT> Flags ) const { unsigned LocMemOffset = VA . getLocMemOffset ( ) ; SDValue PtrOff = DAG . getIntPtrConstant ( LocMemOffset , DL ) ; PtrOff = DAG . getNode ( <STR_LIT> , DL , getPointerTy ( DAG . getDataLayout ( ) ) , StackPtr , PtrOff ) ;

if ( Flags . isByVal ( ) ) return CreateCopyOfByValArgument ( Arg , PtrOff , Chain , Flags , DAG , DL ) ;


<s> return LowerConstantPool ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerExternalSymbol ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerDYNAMIC_STACKALLOC ( Op , DAG ) ; case <STR_LIT> : return LowerShiftLeftParts ( Op , DAG ) ; case <STR_LIT> : return LowerShiftRightParts ( Op , DAG , true ) ;


<s> CCState CCInfo ( CCID , IsVarArg , MF , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT> ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ; RetOps . push_back ( Chain ) ; RetOps . push_back ( DAG . getTargetConstant ( MFI -> getBytesToPopOnReturn ( ) , DL , <STR_LIT> ) ) ; for ( unsigned i = <NUM_LIT> , e = RVLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue ValToCopy = OutVals [ i ] ; EVT ValVT = ValToCopy . getValueType ( ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ValToCopy = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ValToCopy = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , ValToCopy ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: AExt ) { if ( ValVT . isVector ( ) && ValVT . getVectorElementType ( ) == <STR_LIT> ) ValToCopy = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , ValToCopy ) ; else ValToCopy = DAG . getNode ( <STR_LIT> , DL , VA . getLocVT ( ) , ValToCopy ) ; } else if ( VA . getLocInfo ( ) == CCValAssign :: BCvt ) ValToCopy = DAG . getBitcast ( VA . getLocVT ( ) , ValToCopy ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , ValToCopy , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } if ( unsigned SRetReg = MFI -> getSRetReturnReg ( ) ) { SDValue Val = DAG . getCopyFromReg ( RetOps [ <NUM_LIT> ] , DL , SRetReg , getPointerTy ( MF . getDataLayout ( ) ) ) ; unsigned RetValReg = <STR_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RetValReg , Val , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RetValReg , getPointerTy ( DAG . getDataLayout ( ) ) ) ) ; } RetOps [ <NUM_LIT> ] = Chain ; if ( Flag . getNode ( ) ) RetOps . push_back ( Flag ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RetOps ) ;


<s> SDLoc DL ( Op ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; if ( Op0 . hasOneUse ( ) && isNullConstant ( Op1 ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( SDValue NewSetCC = LowerToBTST ( Op0 , CC , DL , DAG ) ) { if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , NewSetCC ) ; return NewSetCC ; } } if ( ( isOneConstant ( Op1 ) || isNullConstant ( Op1 ) ) && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( Op0 . getOpcode ( ) == <STR_LIT> ) { <STR_LIT> CCode = ( <STR_LIT> ) Op0 . getConstantOperandVal ( <NUM_LIT> ) ; bool Invert = ( CC == <STR_LIT> ) ^ isNullConstant ( Op1 ) ; if ( ! Invert ) return Op0 ; CCode = <STR_LIT> ( CCode ) ; SDValue SetCC = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , DAG . getConstant ( CCode , DL , <STR_LIT> ) , Op0 . getOperand ( <NUM_LIT> ) ) ; if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , SetCC ) ; return SetCC ; } } if ( Op0 . getValueType ( ) == <STR_LIT> && ( CC == <STR_LIT> || CC == <STR_LIT> ) ) { if ( isOneConstant ( Op1 ) ) { <STR_LIT> NewCC = <STR_LIT> :: getSetCCInverse ( CC , true ) ; return DAG . getSetCC ( DL , VT , Op0 , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , NewCC ) ; } if ( ! isNullConstant ( Op1 ) ) { SDValue Xor = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op0 , Op1 ) ;

return DAG . getSetCC ( DL , VT , Xor , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) , CC ) ;


<s> EVT CarryVT = Carry . getValueType ( ) ; APInt NegOne = APInt :: getAllOnes ( CarryVT . getScalarSizeInBits ( ) ) ; Carry = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( CarryVT , <STR_LIT> ) , Carry , DAG . getConstant ( NegOne , DL , CarryVT ) ) ; SDVTList VTs = DAG . getVTList ( LHS . getValueType ( ) , <STR_LIT> ) ;

SDValue Cmp = DAG . getNode ( <STR_LIT> , DL , VTs , LHS , RHS , Carry . getValue ( <NUM_LIT> ) ) ;


<s> SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , ShiftRight1Lo , RegisterSizeMinus1Shamt ) ; SDValue ShiftLeftHi = DAG . getNode ( <STR_LIT> , DL , VT , Hi , Shamt ) ; SDValue HiTrue = DAG . getNode ( <STR_LIT> , DL , VT , ShiftLeftHi , ShiftRightLo ) ; SDValue HiFalse = DAG . getNode ( <STR_LIT> , DL , VT , Lo , ShamtMinusRegisterSize ) ; SDValue CC = DAG . getSetCC ( DL , <STR_LIT> , ShamtMinusRegisterSize , Zero , <STR_LIT> ) ; Lo = DAG . getNode ( <STR_LIT> , DL , VT , CC , LoTrue , Zero ) ; Hi = DAG . getNode ( <STR_LIT> , DL , VT , CC , HiTrue , HiFalse ) ;

return DAG . getMergeValues ( { Lo , Hi } , DL ) ;


<s> SDValue Shamt = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Lo . getValueType ( ) ; unsigned ShiftRightOp = IsSRA ? <STR_LIT> : <STR_LIT> ; SDValue Zero = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue One = DAG . getConstant ( <NUM_LIT> , DL , VT ) ; SDValue MinusRegisterSize = DAG . getConstant ( - <NUM_LIT> , DL , VT ) ; SDValue RegisterSizeMinus1 = DAG . getConstant ( <NUM_LIT> - <NUM_LIT> , DL , VT ) ; SDValue ShamtMinusRegisterSize = DAG . getNode ( <STR_LIT> , DL , VT , Shamt , MinusRegisterSize ) ; SDValue RegisterSizeMinus1Shamt = DAG . getNode ( <STR_LIT> , DL , VT , RegisterSizeMinus1 , Shamt ) ;

SDValue ShiftRightLo = DAG . getNode ( <STR_LIT> , DL , VT , Lo , Shamt ) ;


<s> if ( Op . getOpcode ( ) == <STR_LIT> && Op . getValueType ( ) == <STR_LIT> ) return LowerTruncateToBTST ( Op , CC , DL , DAG ) ;


<s> static SDValue LowerTruncateToBTST ( SDValue Op , <STR_LIT> CC , const SDLoc & DL , SelectionDAG & DAG ) { assert ( Op . getOpcode ( ) == <STR_LIT> && Op . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ; if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShiftRight = Op . getOperand ( <NUM_LIT> ) ;

return getBitTestCondition ( ShiftRight . getOperand ( <NUM_LIT> ) , ShiftRight . getOperand ( <NUM_LIT> ) , CC , DL , DAG ) ;


<s> if ( Op . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return SDValue ( ) ; SDValue ShiftRight = Op . getOperand ( <NUM_LIT> ) ; return getBitTestCondition ( ShiftRight . getOperand ( <NUM_LIT> ) , ShiftRight . getOperand ( <NUM_LIT> ) , CC , DL , DAG ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; auto PtrVT = getPointerTy ( MF . getDataLayout ( ) ) ; <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; SDLoc DL ( Op ) ;

SDValue FR = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , PtrVT ) ;


<s> unsigned BaseOp = <NUM_LIT> ; unsigned Cond = <NUM_LIT> ; SDLoc DL ( Op ) ; switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; case <STR_LIT> : BaseOp = <STR_LIT> ; Cond = <STR_LIT> ; break ; }

SDVTList VTs = DAG . getVTList ( N -> getValueType ( <NUM_LIT> ) , <STR_LIT> ) ;


<s> setStackPointerRegisterToSaveRestore ( RegInfo -> getStackRegister ( ) ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; for ( auto VT : <STR_LIT> ( ) ) { setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , VT , <STR_LIT> , Promote ) ; } setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; if ( Subtarget . atLeastM68020 ( ) ) setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; else setOperationAction ( <STR_LIT> , <STR_LIT> , LibCall ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , LibCall ) ; for ( auto OP : { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { setOperationAction ( OP , <STR_LIT> , Promote ) ; setOperationAction ( OP , <STR_LIT> , Legal ) ; setOperationAction ( OP , <STR_LIT> , LibCall ) ; } for ( auto OP : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( OP , <STR_LIT> , Expand ) ; setOperationAction ( OP , <STR_LIT> , Expand ) ; } for ( auto OP : { <STR_LIT> , <STR_LIT> } ) { setOperationAction ( OP , <STR_LIT> , Expand ) ; setOperationAction ( OP , <STR_LIT> , Expand ) ; setOperationAction ( OP , <STR_LIT> , Expand ) ; } for ( auto OP : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) setOperationAction ( OP , <STR_LIT> , Custom ) ; for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) { setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; setOperationAction ( <STR_LIT> , VT , Custom ) ; } for ( auto VT : { <STR_LIT> , <STR_LIT> , <STR_LIT> } ) {


<s> SDValue Ptr = Ld -> getBasePtr ( ) ; FrameIndexSDNode * FINode = dyn_cast < FrameIndexSDNode > ( Ptr ) ; if ( ! FINode ) return false ; FI = FINode -> getIndex ( ) ; } else if ( Arg . getOpcode ( ) == <STR_LIT> && Flags . isByVal ( ) ) { FrameIndexSDNode * FINode = cast < FrameIndexSDNode > ( Arg ) ; FI = FINode -> getIndex ( ) ; Bytes = Flags . getByValSize ( ) ; } else return false ; assert ( FI != INT_MAX ) ; if ( ! MFI . isFixedObjectIndex ( FI ) ) return false ; if ( Offset != MFI . getObjectOffset ( FI ) ) return false ; if ( VA . getLocVT ( ) . getSizeInBits ( ) > Arg . getValueType ( ) . getSizeInBits ( ) ) { if ( Flags . isZExt ( ) != MFI . isObjectZExt ( FI ) || Flags . isSExt ( ) != MFI . isObjectSExt ( FI ) ) { return false ;


<s> static bool shouldGuaranteeTCO ( CallingConv :: ID CC , bool GuaranteedTailCallOpt ) { return GuaranteedTailCallOpt && canGuaranteeTCO ( CC ) ;


<s> switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> return <STR_LIT> ; } } return TranslateInteger<ISA_LIT>CC ( SetCCOpcode ) ; } if ( <STR_LIT> ( LHS . getNode ( ) ) && ! <STR_LIT> ( RHS . getNode ( ) ) ) { SetCCOpcode = getSetCCSwappedOperands ( SetCCOpcode ) ; std :: swap ( LHS , RHS ) ; } switch ( SetCCOpcode ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : std :: swap ( LHS , RHS ) ; break ; } switch ( SetCCOpcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : case <STR_LIT> : return <STR_LIT> ; }


<s> getActionDefinitionsBuilder ( G_LOAD ) . legalFor ( { S32 } ) ; getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { P0 } ) ; getActionDefinitionsBuilder ( G_ADD ) . legalFor ( { S32 } ) ; getActionDefinitionsBuilder ( G_SUB ) . legalFor ( { S32 } ) ; getActionDefinitionsBuilder ( G_MUL ) . legalFor ( { S32 } ) ;

getActionDefinitionsBuilder ( G_UDIV ) . legalFor ( { S32 } ) ;


<s> getActionDefinitionsBuilder ( G_FRAME_INDEX ) . legalFor ( { P0 } ) ; getActionDefinitionsBuilder ( G_ADD ) . legalFor ( { S32 } ) ; getActionDefinitionsBuilder ( G_SUB ) . legalFor ( { S32 } ) ; getActionDefinitionsBuilder ( G_MUL ) . legalFor ( { S32 } ) ;


<s> const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( { G_ADD , G_SUB , G_MUL , G_UDIV , G_AND } ) . legalFor ( { s8 , s16 , s32 } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ;

getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 , p0 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ;


<s> <ISA_LIT>LegalizerInfo :: <ISA_LIT>LegalizerInfo ( const <ISA_LIT>Subtarget & ST ) { using namespace TargetOpcode ; const LLT s8 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s16 = LLT :: scalar ( <NUM_LIT> ) ; const LLT s32 = LLT :: scalar ( <NUM_LIT> ) ; const LLT p0 = LLT :: pointer ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( { G_ADD , G_SUB , G_MUL , G_UDIV , G_AND } ) . legalFor ( { s8 , s16 , s32 } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) . widenScalarToNextPow2 ( <NUM_LIT> , <NUM_LIT> ) ; getActionDefinitionsBuilder ( G_CONSTANT ) . legalFor ( { s32 , p0 } ) . clampScalar ( <NUM_LIT> , s32 , s32 ) ; getActionDefinitionsBuilder ( { G_FRAME_INDEX , G_GLOBAL_VALUE } ) . legalFor ( { p0 } ) ; getActionDefinitionsBuilder ( { G_STORE , G_LOAD } ) . legalForTypesWithMemDesc ( { { s32 , p0 , s32 , <NUM_LIT> } , { s32 , p0 , s16 , <NUM_LIT> } , { s32 , p0 , s8 , <NUM_LIT> } , { s16 , p0 , s16 , <NUM_LIT> } , { s8 , p0 , s8 , <NUM_LIT> } , { p0 , p0 , s32 , <NUM_LIT> } } ) . clampScalar ( <NUM_LIT> , s8 , s32 ) ; getActionDefinitionsBuilder ( G_PTR_ADD ) . legalFor ( { { p0 , s32 } } ) ;

getLegacyLegalizerInfo ( ) . computeTables ( ) ;


<s> unsigned getBytesToPopOnReturn ( ) const {


<s> unsigned getBytesToPopOnReturn ( ) const { return BytesToPopOnReturn ;


<s> SmallVectorImpl < ForwardedRegister > & getForwardedMustTailRegParms ( ) { return ForwardedMustTailRegParms ;


<s> unsigned getGlobalBaseReg ( ) const { return GlobalBaseReg ;


<s> unsigned getGlobalBaseReg ( ) const {


<s> bool getRestoreBasePointer ( ) const {

return RestoreBasePointerOffset != <NUM_LIT> ;


<s> int getTCReturnAddrDelta ( ) const { return TailCallReturnAddrDelta ;


<s> int getVarArgsFrameIndex ( ) const { return VarArgsFrameIndex ;


<s> explicit <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : MF ( MF ) {


<s> void setCalleeSavedFrameSize ( unsigned bytes ) {


<s> void setSRetReturnReg ( unsigned Reg ) { SRetReturnReg = Reg ;


<s> void setTCReturnAddrDelta ( int delta ) { TailCallReturnAddrDelta = delta ;


<s> void setTCReturnAddrDelta ( int delta ) {


<s> void setVarArgsFrameIndex ( int Index ) {


<s> void <ISA_LIT>MachineFunctionInfo :: anchor ( ) {


<s> void <ISA_LIT>ELFMCAsmInfo :: anchor ( ) {


<s> <ISA_LIT>ELFMCAsmInfo :: <ISA_LIT>ELFMCAsmInfo ( const Triple & T ) { CodePointerSize = <NUM_LIT> ; CalleeSaveStackSlotSize = <NUM_LIT> ; IsLittleEndian = false ;


<s> getBinaryCodeForInstr ( MI , Fixups , EncodedInst , Scratch , STI ) ; ArrayRef < uint64_t > Data ( EncodedInst . getRawData ( ) , EncodedInst . getNumWords ( ) ) ; int64_t InstSize = EncodedInst . getBitWidth ( ) ; for ( uint64_t Word : Data ) { for ( int i = <NUM_LIT> ; i < <NUM_LIT> && InstSize > <NUM_LIT> ; ++ i , InstSize -= <NUM_LIT> ) {

<STR_LIT> :: write < uint16_t > ( OS , static_cast < uint16_t > ( Word ) , <STR_LIT> ) ;


<s> unsigned Opcode = MI . getOpcode ( ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MCII . getName ( Opcode ) << <STR_LIT> << Opcode << <STR_LIT> ) ; APInt EncodedInst ( <NUM_LIT> , <NUM_LIT> ) ; APInt Scratch ( <NUM_LIT> , <NUM_LIT> ) ; getBinaryCodeForInstr ( MI , Fixups , EncodedInst , Scratch , STI ) ; ArrayRef < uint64_t > Data ( EncodedInst . getRawData ( ) , EncodedInst . getNumWords ( ) ) ; int64_t InstSize = EncodedInst . getBitWidth ( ) ; for ( uint64_t Word : Data ) { for ( int i = <NUM_LIT> ; i < <NUM_LIT> && InstSize > <NUM_LIT> ; ++ i , InstSize -= <NUM_LIT> ) { <STR_LIT> :: write < uint16_t > ( OS , static_cast < uint16_t > ( Word ) , <STR_LIT> ) ; Word >>= <NUM_LIT> ; } }


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) {

return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> unsigned Opcode = MI . getOpcode ( ) ; const MCInstrDesc & Desc = MCII . get ( Opcode ) ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << MCII . getName ( Opcode ) << <STR_LIT> << Opcode << <STR_LIT> ) ; const uint8_t * Beads = getGenInstrBeads ( MI ) ; if ( ! Beads || ! * Beads ) { llvm_unreachable ( <STR_LIT> ) ; } uint64_t Buffer = <NUM_LIT> ; unsigned Offset = <NUM_LIT> ; unsigned ThisByte = <NUM_LIT> ; for ( uint8_t Bead = * Beads ; Bead ; Bead = * ++ Beads ) { if ( ! ( Bead & <NUM_LIT> ) ) { switch ( Bead >> <NUM_LIT> ) { case <STR_LIT> : continue ; } } switch ( Bead & <NUM_LIT> ) { default : llvm_unreachable ( <STR_LIT> ) ; break ; case <STR_LIT> : case <STR_LIT> :


<s> return new <ISA_LIT>MCCodeEmitter ( MCII , Ctx ) ;


<s> static unsigned EmitConstant ( uint64_t Val , unsigned Size , unsigned Pad , uint64_t & Buffer , unsigned Offset ) { assert ( Size + Offset <= <NUM_LIT> && isUIntN ( Size , Val ) && <STR_LIT> ) ;

Buffer |= ( Val & ( ( <NUM_LIT> << Size ) - <NUM_LIT> ) ) << Offset ;


<s> } unsigned char Val = ( Bead & <NUM_LIT> ) >> <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Num << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) . write_hex ( Val ) << <STR_LIT> ) ; Buffer |= ( Val << Offset ) ;


<s> unsigned Num = <NUM_LIT> ; switch ( Bead & <NUM_LIT> ) { case <STR_LIT> : Num = <NUM_LIT> ; break ; case <STR_LIT> : Num = <NUM_LIT> ; break ; case <STR_LIT> : Num = <NUM_LIT> ; break ; case <STR_LIT> : Num = <NUM_LIT> ; break ; } unsigned char Val = ( Bead & <NUM_LIT> ) >> <NUM_LIT> ; LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Num << <STR_LIT> ) ; LLVM_DEBUG ( dbgs ( ) . write_hex ( Val ) << <STR_LIT> ) ;


<s> case <STR_LIT> : Size = <NUM_LIT> ; Pad = <NUM_LIT> ; FixOffset = ThisByte ; break ; case <STR_LIT> : Size = <NUM_LIT> ; Pad = <NUM_LIT> ; FixOffset = ThisByte ; break ; case <STR_LIT> : Size = <NUM_LIT> ; Pad = <NUM_LIT> ; FixOffset = ThisByte ; break ; case <STR_LIT> : Size = <NUM_LIT> ; Pad = <NUM_LIT> ; NoExpr = true ; break ; } LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << <STR_LIT> << Op << <STR_LIT> << Size << <STR_LIT> << Alt << <STR_LIT> ) ; MCOperand MCO ; if ( <STR_LIT> ( MI . getOpcode ( ) , Op ) ) { if ( IsPCRel ) { assert ( ! Alt && <STR_LIT> ) ; MCO = MI . getOperand ( MIOpIdx + <STR_LIT> ) ; } else { MCO = MI . getOperand ( MIOpIdx + ( Alt ? <STR_LIT> : <STR_LIT> ) ) ; } if ( MCO . isExpr ( ) ) { assert ( ! NoExpr && <STR_LIT> ) ; const MCExpr * Expr = MCO . getExpr ( ) ; if ( IsPCRel && Addendum != <NUM_LIT> ) { Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( Addendum , Ctx ) , Ctx ) ; }

Fixups . push_back ( MCFixup :: create ( FixOffset , Expr , getFixupForSize ( Size , IsPCRel ) , MI . getLoc ( ) ) ) ;


<s> int LabelOffset = <NUM_LIT> ; if ( InsertPos < <NUM_LIT> ) LabelOffset = InsertByte - <NUM_LIT> ; else if ( InsertByte % <NUM_LIT> ) LabelOffset = <NUM_LIT> ; if ( LabelOffset ) Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( LabelOffset , Ctx ) , Ctx ) ; } Fixups . push_back ( MCFixup :: create ( InsertByte , Expr , getFixupForSize ( Size , true ) , MI . getLoc ( ) ) ) ; }


<s> auto MIOpIdx = <STR_LIT> ( MI . getOpcode ( ) , Op ) ; bool IsPCRel = Desc . OpInfo [ MIOpIdx ] . OperandType == MCOI :: OPERAND_PCREL ; MCOperand MCO ; if ( <STR_LIT> ( MI . getOpcode ( ) , Op ) ) { if ( IsPCRel ) { assert ( Alt && <STR_LIT> ) ; MCO = MI . getOperand ( MIOpIdx + <STR_LIT> ) ; } else { MCO = MI . getOperand ( MIOpIdx + ( Alt ? <STR_LIT> : <STR_LIT> ) ) ; } } else { assert ( ! Alt && <STR_LIT> ) ; MCO = MI . getOperand ( MIOpIdx ) ; } unsigned RegNum = MCO . getReg ( ) ; auto RI = Ctx . getRegisterInfo ( ) ; unsigned Written = <NUM_LIT> ; if ( Reg ) { uint32_t Val = RI -> getEncodingValue ( RegNum ) ; Buffer |= ( Val & <NUM_LIT> ) << Offset ; Offset += <NUM_LIT> ; Written += <NUM_LIT> ; }


<s> if ( <STR_LIT> ( MI . getOpcode ( ) , Op ) ) { if ( IsPCRel ) { assert ( Alt && <STR_LIT> ) ; MCO = MI . getOperand ( MIOpIdx + <STR_LIT> ) ; } else { MCO = MI . getOperand ( MIOpIdx + ( Alt ? <STR_LIT> : <STR_LIT> ) ) ; } } else { assert ( ! Alt && <STR_LIT> ) ; MCO = MI . getOperand ( MIOpIdx ) ; } unsigned RegNum = MCO . getReg ( ) ; auto RI = Ctx . getRegisterInfo ( ) ; unsigned Written = <NUM_LIT> ; if ( Reg ) { uint32_t Val = RI -> getEncodingValue ( RegNum ) ; Buffer |= ( Val & <NUM_LIT> ) << Offset ;


<s> if ( Expr -> evaluateAsAbsolute ( Addr ) ) { Value |= swapWord < value_t > ( static_cast < value_t > ( Addr ) ) ; return ; } unsigned InsertByte = getBytePosition < Size > ( InsertPos ) ; Fixups . push_back ( MCFixup :: create ( InsertByte , Expr , getFixupForSize ( Size , false ) , MI . getLoc ( ) ) ) ; }


<s> if ( Size % <NUM_LIT> ) { return static_cast < unsigned > ( BitPos / <NUM_LIT> + ( ( BitPos & <NUM_LIT> ) < <NUM_LIT> ? <NUM_LIT> : - <NUM_LIT> ) ) ; } else {

assert ( ! ( BitPos & <NUM_LIT> ) && <STR_LIT> ) ;


<s> if ( Size % <NUM_LIT> ) { return static_cast < unsigned > ( BitPos / <NUM_LIT> + ( ( BitPos & <NUM_LIT> ) < <NUM_LIT> ? <NUM_LIT> : - <NUM_LIT> ) ) ; } else { assert ( ! ( BitPos & <NUM_LIT> ) && <STR_LIT> ) ;


<s> return <STR_LIT> ( MI . getOpcode ( ) ) ;


<s> if ( <STR_LIT> ( RegNum ) ) Value |= <NUM_LIT> ; } else if ( Op . isImm ( ) ) { Value |= static_cast < uint64_t > ( Op . getImm ( ) ) ; } else if ( Op . isExpr ( ) ) { int64_t Addr ; if ( ! Op . getExpr ( ) -> evaluateAsAbsolute ( Addr ) ) report_fatal_error ( <STR_LIT> <STR_LIT> ) ;

Value |= static_cast < uint64_t > ( Addr ) ;


<s> <ISA_LIT>MCCodeEmitter ( const MCInstrInfo & mcii , MCContext & ctx ) : MCII ( mcii ) , Ctx ( ctx ) {


<s> if ( NumWords <= <NUM_LIT> ) return Val ; Val = <STR_LIT> :: byte_swap ( Val , <STR_LIT> ) ; value_t NewVal = <NUM_LIT> ; for ( unsigned i = <NUM_LIT> ; i != NumWords ; ++ i ) { uint16_t Part = ( Val >> ( i * <NUM_LIT> ) ) & <NUM_LIT> ;

Part = <STR_LIT> :: byte_swap ( Part , <STR_LIT> ) ;


<s> ~ <ISA_LIT>MCCodeEmitter ( ) override {


<s> MCSymbol * <ISA_LIT>MCInstLower :: GetSymbolFromOperand ( const MachineOperand & MO ) const { assert ( ( MO . isGlobal ( ) || MO . isSymbol ( ) || MO . isMBB ( ) ) && <STR_LIT> ) ; const auto & TT = TM . getTargetTriple ( ) ; if ( MO . isGlobal ( ) && TT . isOSBinFormatELF ( ) ) return AsmPrinter . getSymbolPreferLocal ( * MO . getGlobal ( ) ) ; const DataLayout & DL = MF . getDataLayout ( ) ; MCSymbol * Sym = nullptr ; SmallString < <NUM_LIT> > Name ; StringRef Suffix ; if ( ! Suffix . empty ( ) ) Name += DL . getPrivateGlobalPrefix ( ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ; AsmPrinter . getNameWithPrefix ( Name , GV ) ; } else if ( MO . isSymbol ( ) ) { Mangler :: getNameWithPrefix ( Name , MO . getSymbolName ( ) , DL ) ; } else if ( MO . isMBB ( ) ) { assert ( Suffix . empty ( ) ) ; Sym = MO . getMBB ( ) -> getSymbol ( ) ;


<s> const DataLayout & DL = MF . getDataLayout ( ) ; MCSymbol * Sym = nullptr ; SmallString < <NUM_LIT> > Name ; StringRef Suffix ; if ( ! Suffix . empty ( ) ) Name += DL . getPrivateGlobalPrefix ( ) ; if ( MO . isGlobal ( ) ) { const GlobalValue * GV = MO . getGlobal ( ) ;

AsmPrinter . getNameWithPrefix ( Name , GV ) ;


<s> for ( unsigned i = <NUM_LIT> , e = MI -> getNumOperands ( ) ; i != e ; ++ i ) { const MachineOperand & MO = MI -> getOperand ( i ) ; Optional < MCOperand > MCOp = LowerOperand ( MI , MO ) ; if ( MCOp . hasValue ( ) && MCOp . getValue ( ) . isValid ( ) ) OutMI . addOperand ( MCOp . getValue ( ) ) ; } if ( Opcode == <STR_LIT> || Opcode == <STR_LIT> ) { assert ( OutMI . getNumOperands ( ) == <NUM_LIT> && <STR_LIT> ) ; switch ( Opcode ) { case <STR_LIT> : Opcode = <STR_LIT> ;


<s> switch ( MO . getType ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case MachineOperand :: MO_Register : if ( MO . isImplicit ( ) ) return None ; return MCOperand :: createReg ( MO . getReg ( ) ) ; case MachineOperand :: MO_Immediate : return MCOperand :: createImm ( MO . getImm ( ) ) ; case MachineOperand :: MO_MachineBasicBlock : case MachineOperand :: MO_GlobalAddress : case MachineOperand :: MO_ExternalSymbol : return LowerSymbolOperand ( MO , GetSymbolFromOperand ( MO ) ) ; case MachineOperand :: MO_MCSymbol : return LowerSymbolOperand ( MO , MO . getMCSymbol ( ) ) ; case MachineOperand :: MO_JumpTableIndex : return LowerSymbolOperand ( MO , AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ) ; case MachineOperand :: MO_ConstantPoolIndex : return LowerSymbolOperand ( MO , AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) ) ;

case MachineOperand :: MO_BlockAddress :


<s> return LowerSymbolOperand ( MO , AsmPrinter . GetJTISymbol ( MO . getIndex ( ) ) ) ; case MachineOperand :: MO_ConstantPoolIndex : return LowerSymbolOperand ( MO , AsmPrinter . GetCPISymbol ( MO . getIndex ( ) ) ) ; case MachineOperand :: MO_BlockAddress :

return LowerSymbolOperand ( MO , AsmPrinter . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ;


<s> } if ( ! Expr ) { Expr = MCSymbolRefExpr :: create ( Sym , RefKind , Ctx ) ; } if ( ! MO . isJTI ( ) && ! MO . isMBB ( ) && MO . getOffset ( ) ) { Expr = MCBinaryExpr :: createAdd ( Expr , MCConstantExpr :: create ( MO . getOffset ( ) , Ctx ) , Ctx ) ; }

return MCOperand :: createExpr ( Expr ) ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MachineFunction & MF , <ISA_LIT>AsmPrinter & AP ) : Ctx ( MF . getContext ( ) ) , MF ( MF ) , TM ( MF . getTarget ( ) ) , MAI ( * TM . getMCAsmInfo ( ) ) , AsmPrinter ( AP ) {


<s> MAI -> addInitialFrameState ( Inst ) ; Inst = MCCFIInstruction :: createOffset ( nullptr , MRI . getDwarfRegNum ( <STR_LIT> , true ) , StackGrowth ) ; MAI -> addInitialFrameState ( Inst ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( X ) ; return X ;


<s> Init<ISA_LIT>MCRegisterInfo ( X , llvm :: <STR_LIT> , <NUM_LIT> , <NUM_LIT> , llvm :: <STR_LIT> ) ; return X ;


<s> MCRegisterInfo * X = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( X , llvm :: <STR_LIT> , <NUM_LIT> , <NUM_LIT> , llvm :: <STR_LIT> ) ; return X ;


<s> static MCRelocationInfo * create<ISA_LIT>MCRelocationInfo ( const Triple & TheTriple , MCContext & Ctx ) {

return llvm :: createMCRelocationInfo ( TheTriple , Ctx ) ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { std :: string ArchFS = Parse<ISA_LIT>Triple ( TT , CPU ) ; if ( ! FS . empty ( ) ) { if ( ! ArchFS . empty ( ) ) { ArchFS = ( ArchFS + <STR_LIT> + FS ) . str ( ) ; } else { ArchFS = FS . str ( ) ; } } return create<ISA_LIT>MCSubtargetInfoImpl ( TT , CPU , CPU , ArchFS ) ;


<s> TargetRegistry :: RegisterMCSubtargetInfo ( T , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( T , create<ISA_LIT>MCCodeEmitter ) ;

TargetRegistry :: RegisterMCInstPrinter ( T , create<ISA_LIT>MCInstPrinter ) ;


<s> RegisterMCAsmInfoFn X ( T , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( T , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( T , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCSubtargetInfo ( T , create<ISA_LIT>MCSubtargetInfo ) ;

TargetRegistry :: RegisterMCCodeEmitter ( T , create<ISA_LIT>MCCodeEmitter ) ;


<s> static std :: string Parse<ISA_LIT>Triple ( const Triple & TT , StringRef CPU ) {


<s> <ISA_LIT>RegisterBankInfo :: <ISA_LIT>RegisterBankInfo ( const TargetRegisterInfo & TRI ) : <ISA_LIT>GenRegisterBankInfo ( ) {


<s> BitVector Reserved ( getNumRegs ( ) ) ; auto setBitVector = [ & Reserved , this ] ( unsigned Reg ) { for ( MCRegAliasIterator I ( Reg , this , true ) ; I . isValid ( ) ; ++ I ) { Reserved . set ( * I ) ; } for ( MCSubRegIterator I ( Reg , this , true ) ; I . isValid ( ) ; ++ I ) { Reserved . set ( * I ) ; } } ; setBitVector ( <STR_LIT> ) ; setBitVector ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { setBitVector ( FramePtr ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> <STR_LIT> ) ; setBitVector ( getBaseRegister ( ) ) ; } return Reserved ;


<s> } ; setBitVector ( <STR_LIT> ) ; setBitVector ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { setBitVector ( FramePtr ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> <STR_LIT> ) ; setBitVector ( getBaseRegister ( ) ) ; }


<s> void <ISA_LIT>RegisterInfo :: anchor ( ) {


<s> if ( ! TargetRegisterInfo :: canRealignStack ( MF ) ) return false ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( CantUseSP ( MFI ) ) return MRI -> canReserveReg ( BasePtr ) ;


<s> const MachineRegisterInfo * MRI = & MF . getRegInfo ( ) ; if ( ! MRI -> canReserveReg ( FramePtr ) ) return false ; if ( CantUseSP ( MFI ) ) return MRI -> canReserveReg ( BasePtr ) ;


<s> return MFI . hasVarSizedObjects ( ) || MFI . hasOpaqueSPAdjustment ( ) ;


<s> else BasePtr = ( TFI -> hasFP ( MF ) ? FramePtr : StackPtr ) ; Base . ChangeToRegister ( BasePtr , false ) ; int64_t FIOffset ; Register IgnoredFrameReg ; if ( AfterFPPop ) { const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; FIOffset = MFI . getObjectOffset ( FIndex ) - TFI -> getOffsetOfLocalArea ( ) ; } else { FIOffset = TFI -> getFrameIndexReference ( MF , FIndex , IgnoredFrameReg ) . getFixed ( ) ; } if ( BasePtr == StackPtr ) FIOffset += SPAdj ;

Disp . ChangeToImmediate ( FIOffset + Imm ) ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID ) const {


<s> if ( RC == & <STR_LIT> ) return & <STR_LIT> ;


<s> const TargetFrameLowering * TFI = MF . getSubtarget ( ) . getFrameLowering ( ) ;

return TFI -> hasFP ( MF ) ? FramePtr : StackPtr ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getMaximalPhysRegClass ( unsigned reg , MVT VT ) const { assert ( Register :: isPhysicalRegister ( reg ) && <STR_LIT> ) ; const TargetRegisterClass * BestRC = nullptr ; for ( regclass_iterator I = regclass_begin ( ) , E = regclass_end ( ) ; I != E ; ++ I ) { const TargetRegisterClass * RC = * I ; if ( ( VT == <STR_LIT> || isTypeLegalForClass ( * RC , VT ) ) && RC -> contains ( reg ) && ( ! BestRC || ( BestRC -> hasSubClass ( RC ) && RC -> getNumRegs ( ) > BestRC -> getNumRegs ( ) ) ) ) BestRC = RC ; } assert ( BestRC && <STR_LIT> ) ; return BestRC ;


<s> ++ I ) { const TargetRegisterClass * RC = * I ; if ( ( VT == <STR_LIT> || isTypeLegalForClass ( * RC , VT ) ) && RC -> contains ( reg ) && ( ! BestRC || ( BestRC -> hasSubClass ( RC ) && RC -> getNumRegs ( ) > BestRC -> getNumRegs ( ) ) ) ) BestRC = RC ;


<s> for ( unsigned i = <NUM_LIT> ; i < TRC . getNumRegs ( ) ; ++ i ) { if ( regsOverlap ( Reg , TRC . getRegister ( i ) ) ) { return i ; }


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: getRegsForTailCall ( const MachineFunction & MF ) const {


<s> } for ( MCSubRegIterator I ( Reg , this , true ) ; I . isValid ( ) ; ++ I ) { Reserved . set ( * I ) ; } } ; for ( size_t Reg = <NUM_LIT> , Total = getNumRegs ( ) ; Reg != Total ; ++ Reg ) { if ( MF . getSubtarget < <ISA_LIT>Subtarget > ( ) . isRegisterReservedByUser ( Reg ) ) setBitVector ( Reg ) ; } setBitVector ( <STR_LIT> ) ; setBitVector ( <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) { setBitVector ( FramePtr ) ; } if ( hasBasePointer ( MF ) ) { CallingConv :: ID CC = MF . getFunction ( ) . getCallingConv ( ) ; const uint32_t * RegMask = getCallPreservedMask ( MF , CC ) ; if ( MachineOperand :: clobbersPhysReg ( RegMask , getBaseRegister ( ) ) ) report_fatal_error ( <STR_LIT> <STR_LIT> <STR_LIT> ) ;


<s> assert ( Result >= <NUM_LIT> && <STR_LIT> ) ;


<s> unsigned getStackRegister ( ) const {


<s> bool CantUseFP = hasStackRealignment ( MF ) ;


<s> const TargetRegisterClass * <ISA_LIT>RegisterInfo :: intRegClass ( unsigned size ) const { return & <STR_LIT> ;


<s> <ISA_LIT>RegisterInfo :: <ISA_LIT>RegisterInfo ( const <ISA_LIT>Subtarget & ST ) : <ISA_LIT>GenRegisterInfo ( <STR_LIT> , <NUM_LIT> , <NUM_LIT> , <STR_LIT> ) , Subtarget ( ST ) { StackPtr = <STR_LIT> ; FramePtr = <STR_LIT> ; GlobalBasePtr = <STR_LIT> ;


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const { return true ;


<s> bool <ISA_LIT>RegisterInfo :: requiresRegisterScavenging ( const MachineFunction & MF ) const {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , UserReservedRegister ( <STR_LIT> ) , TM ( TM ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , TT , FS , TM ) ) , FrameLowering ( * this , this -> getStackAlignment ( ) ) , TLInfo ( TM , * this ) , TargetTriple ( TT ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef FS , const <ISA_LIT>TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , CPU , FS ) , TM ( TM ) , TSInfo ( ) , InstrInfo ( initializeSubtargetDependencies ( CPU , TT , FS , TM ) ) , FrameLowering ( * this , this -> getStackAlignment ( ) ) , TLInfo ( TM , * this ) , TargetTriple ( TT ) {


<s> bool <ISA_LIT>Subtarget :: abiUsesSoftFloat ( ) const {


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> bool atLeastM68000 ( ) const { return SubtargetKind >= M00 ;


<s> unsigned char <ISA_LIT>Subtarget :: classifyBlockAddressReference ( ) const { return <STR_LIT> ;


<s> unsigned char <ISA_LIT>Subtarget :: classifyBlockAddressReference ( ) const {


<s> unsigned char <ISA_LIT>Subtarget :: classifyExternalReference ( const Module & M ) const { if ( TM . shouldAssumeDSOLocal ( M , nullptr ) ) return classifyLocalReference ( nullptr ) ; if ( isPositionIndependent ( ) ) return <STR_LIT> ; return <STR_LIT> ;


<s> if ( F && F -> hasFnAttribute ( Attribute :: NonLazyBind ) ) { return <STR_LIT> ; } return <STR_LIT> ;


<s> case CodeModel :: Small : case CodeModel :: Kernel : { if ( isPositionIndependent ( ) ) return <STR_LIT> ; return <STR_LIT> ; } case CodeModel :: Medium : { if ( isPositionIndependent ( ) ) return <STR_LIT> ; if ( atLeastM68020 ( ) ) return <STR_LIT> ; return <STR_LIT> ; }