<s> void <ISA_LIT>Z80AsmPrinter :: EmitFunctionBodyStart ( ) { const MachineRegisterInfo & MRI = MF -> getRegInfo ( ) ; SmallString < <NUM_LIT> > C ; raw_svector_ostream O ( C ) ; O << <STR_LIT> << MF -> getName ( ) << <STR_LIT> ; OutStreamer -> emitRawComment ( C , false ) ; C . clear ( ) ; O << <STR_LIT> ; if ( ! MRI . livein_empty ( ) ) { for ( MachineRegisterInfo :: livein_iterator I = MRI . livein_begin ( ) , E = MRI . livein_end ( ) ; I != E ; ++ I ) { O << printReg ( I -> first , MRI . getTargetRegisterInfo ( ) ) ;

if ( std :: next ( I ) != E ) O << <STR_LIT> ;


<s> if ( isVerbose ( ) ) OutStreamer -> GetCommentOS ( ) << <STR_LIT> << GlobalValue :: dropLLVMManglingEscape ( F -> getName ( ) ) << '\n' ; EmitConstantPool ( ) ; OutStreamer -> SwitchSection ( getObjFileLowering ( ) . SectionForGlobal ( F , TM ) ) ; EmitLinkage ( F , CurrentFnSym ) ; if ( isVerbose ( ) ) { F -> printAsOperand ( OutStreamer -> GetCommentOS ( ) , false , F -> getParent ( ) ) ; OutStreamer -> GetCommentOS ( ) << '\n' ; } if ( F -> hasPrefixData ( ) ) { if ( MAI -> hasSubsectionsViaSymbols ( ) ) { MCSymbol * PrefixSym = OutContext . createLinkerPrivateTempSymbol ( ) ; OutStreamer -> EmitLabel ( PrefixSym ) ; EmitGlobalConstant ( F -> getParent ( ) -> getDataLayout ( ) , F -> getPrefixData ( ) ) ; OutStreamer -> EmitSymbolAttribute ( CurrentFnSym , MCSA_AltEntry ) ; } else { EmitGlobalConstant ( F -> getParent ( ) -> getDataLayout ( ) , F -> getPrefixData ( ) ) ; } } EmitFunctionEntryLabel ( ) ; std :: vector < MCSymbol * > DeadBlockSyms ;

MMI -> takeDeletedSymbolsForFunction ( F , DeadBlockSyms ) ;


<s> MCSymbol * PrefixSym = OutContext . createLinkerPrivateTempSymbol ( ) ; OutStreamer -> EmitLabel ( PrefixSym ) ; EmitGlobalConstant ( F -> getParent ( ) -> getDataLayout ( ) , F -> getPrefixData ( ) ) ; OutStreamer -> EmitSymbolAttribute ( CurrentFnSym , MCSA_AltEntry ) ; } else { EmitGlobalConstant ( F -> getParent ( ) -> getDataLayout ( ) , F -> getPrefixData ( ) ) ; } } EmitFunctionEntryLabel ( ) ; std :: vector < MCSymbol * > DeadBlockSyms ; MMI -> takeDeletedSymbolsForFunction ( F , DeadBlockSyms ) ; for ( unsigned i = <NUM_LIT> , e = DeadBlockSyms . size ( ) ; i != e ; ++ i ) {

OutStreamer -> AddComment ( <STR_LIT> ) ;


<s> void <ISA_LIT>Z80AsmPrinter :: EmitInstruction ( const MachineInstr * MI ) {

<ISA_LIT>Z80MCInstLower MCInstLowering ( OutContext , * this ) ;


<s> <ISA_LIT>Z80AsmPrinter ( TargetMachine & TM , std :: unique_ptr < MCStreamer > Streamer ) : AsmPrinter ( TM , std :: move ( Streamer ) ) , MRI ( * TM . getMCRegisterInfo ( ) ) {


<s> StringRef getPassName ( ) const override { return <STR_LIT> ;


<s> llvm :: RegisterAsmPrinter < llvm :: <ISA_LIT>Z80AsmPrinter > X ( llvm :: getThe<ISA_LIT>Z80Target ( ) ) ;


<s> assert ( MO . isReg ( ) && <STR_LIT> ) ; if ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> ) { O << <STR_LIT> ; } else { assert ( MI -> getOperand ( OpNum ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; O << <STR_LIT> ; } unsigned OpFlags = MI -> getOperand ( OpNum - <NUM_LIT> ) . getImm ( ) ; unsigned NumOpRegs = InlineAsm :: getNumOperandRegisters ( OpFlags ) ; if ( NumOpRegs == <NUM_LIT> ) { O << '+' << MI -> getOperand ( OpNum + <NUM_LIT> ) . getImm ( ) ; } return false ;


<s> bool Error = AsmPrinter :: PrintAsmOperand ( MI , OpNum , AsmVariant , ExtraCode , O ) ;

if ( Error ) printOperand ( MI , OpNum , O ) ;


<s> O << getSymbol ( MO . getGlobal ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock :

O << * MO . getMBB ( ) -> getSymbol ( ) ;


<s> std :: unique_ptr < MCObjectWriter > create<ISA_LIT>Z80ELFObjectWriter ( raw_pwrite_stream & OS , uint8_t OSABI ) {

return createELFObjectWriter ( llvm :: make_unique < <ISA_LIT>Z80ELFObjectWriter > ( OSABI ) , OS , true ) ;


<s> <ISA_LIT>Z80ELFObjectWriter :: <ISA_LIT>Z80ELFObjectWriter ( uint8_t OSABI ) : MCELFObjectTargetWriter ( false , OSABI , ELF :: EM_NONE , true ) {


<s> virtual ~ <ISA_LIT>Z80ELFObjectWriter ( ) {


<s> unsigned EFlags = MCA . getELFHeaderEFlags ( ) ;

EFlags |= getEFlagsForFeatureSet ( STI . getFeatureBits ( ) ) ;


<s> static unsigned getEFlagsForFeatureSet ( const FeatureBitset & Features ) {


<s> static unsigned getEFlagsForFeatureSet ( const FeatureBitset & Features ) { unsigned EFlags = <NUM_LIT> ; return EFlags ;


<s> return static_cast < MCELFStreamer & > ( Streamer ) ;


<s> inline void adjustBranchTarget ( T & val ) { val >>= <NUM_LIT> ;


<s> switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> :


<s> } if ( NumBytes ) { unsigned FP = TII . getRegisterInfo ( ) . getFrameRegister ( MF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FP ) . addImm ( NumBytes ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( FP , RegState :: Kill ) ; }


<s> while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator I = std :: prev ( MBBI ) ; unsigned Opc = I -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! I -> isTerminator ( ) ) break ; MBBI -- ; } if ( NumBytes ) { unsigned FP = TII . getRegisterInfo ( ) . getFrameRegister ( MF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FP ) . addImm ( NumBytes ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( FP , RegState :: Kill ) ;


<s> void <ISA_LIT>Z80FrameLowering :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; <ISA_LIT>Z80MachineFunctionInfo * <ISA_LIT>Z80FI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ; const <ISA_LIT>Z80InstrInfo & TII = * static_cast < const <ISA_LIT>Z80InstrInfo * > ( MF . getSubtarget ( ) . getInstrInfo ( ) ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t CallFrameSize = MFI -> getMaxCallFrameSize ( ) ; uint64_t FrameSize = <ISA_LIT>Z80FI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = StackSize + CallFrameSize - FrameSize ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> ) ) MBBI ++ ; if ( NumBytes || <ISA_LIT>Z80FI -> isNeedFP ( ) ) {

unsigned FP = TII . getRegisterInfo ( ) . getFrameRegister ( MF ) ;


<s> uint64_t StackSize = MFI -> getStackSize ( ) ; uint64_t CallFrameSize = MFI -> getMaxCallFrameSize ( ) ; uint64_t FrameSize = <ISA_LIT>Z80FI -> getCalleeSavedFrameSize ( ) ; uint64_t NumBytes = StackSize + CallFrameSize - FrameSize ; while ( MBBI != MBB . end ( ) && ( MBBI -> getOpcode ( ) == <STR_LIT> ) ) MBBI ++ ; if ( NumBytes || <ISA_LIT>Z80FI -> isNeedFP ( ) ) { unsigned FP = TII . getRegisterInfo ( ) . getFrameRegister ( MF ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FP ) . addImm ( - NumBytes ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , FP ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( FP ) ; }


<s> <ISA_LIT>Z80FrameLowering :: <ISA_LIT>Z80FrameLowering ( const <ISA_LIT>Z80TargetMachine & tm ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> ) , TM ( tm ) {


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return ( MFI -> getMaxCallFrameSize ( ) > <NUM_LIT> || ( MFI -> getNumObjects ( ) > <NUM_LIT> ) ) ;


<s> if ( hasFP ( MF ) ) { unsigned FP = MF . getSubtarget ( ) . getRegisterInfo ( ) -> getFrameRegister ( MF ) ; MF . getRegInfo ( ) . setPhysRegUsed ( FP ) ; }


<s> bool <ISA_LIT>Z80FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return false ; DebugLoc dl ;

if ( MI != MBB . end ( ) ) dl = MI -> getDebugLoc ( ) ;


<s> const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; for ( unsigned i = <NUM_LIT> , e = CSI . size ( ) ; i != e ; i ++ ) BuildMI ( MBB , MI , dl , TII . get ( <STR_LIT> ) , CSI [ i ] . getReg ( ) ) ;


<s> if ( CSI . empty ( ) ) return false ; DebugLoc dl ; if ( MI != MBB . end ( ) ) dl = MI -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>Z80MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * <NUM_LIT> ) ; for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; i -- ) { unsigned Reg = CSI [ i - <NUM_LIT> ] . getReg ( ) ;


<s> MachineFunction & MF = * MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF . getSubtarget ( ) . getInstrInfo ( ) ; <ISA_LIT>Z80MachineFunctionInfo * MFI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ; MFI -> setCalleeSavedFrameSize ( CSI . size ( ) * <NUM_LIT> ) ;

for ( unsigned i = CSI . size ( ) ; i != <NUM_LIT> ; i -- ) {


<s> bool <ISA_LIT>Z80FrameLowering :: canSimplifyCallFramePseudos ( const MachineFunction & MF ) const { return false ;


<s> FunctionPass * create<ISA_LIT>Z80DynAllocaSRPass ( ) {

return new <ISA_LIT>Z80DynAllocaSR ( ) ;


<s> return new <ISA_LIT>Z80FrameAnalyzer ( ) ;


<s> FunctionPass * create<ISA_LIT>Z80FrameAnalyzerPass ( ) {

return new <ISA_LIT>Z80FrameAnalyzer ( ) ;


<s> void <ISA_LIT>Z80FrameLowering :: determineCalleeSaves ( MachineFunction & MF , BitVector & SavedRegs , RegScavenger * RS ) const {

TargetFrameLowering :: determineCalleeSaves ( MF , SavedRegs , RS ) ;


<s> const <ISA_LIT>Z80Subtarget & STI = MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ; const TargetFrameLowering & TFI = * STI . getFrameLowering ( ) ; const <ISA_LIT>Z80InstrInfo & TII = * STI . getInstrInfo ( ) ; DebugLoc DL = MI -> getDebugLoc ( ) ; unsigned int Opcode = MI -> getOpcode ( ) ; int Amount = TII . getFrameSize ( * MI ) ; assert ( Amount == <NUM_LIT> && <STR_LIT> ) ; if ( Amount != <NUM_LIT> ) { assert ( TFI . getStackAlignment ( ) == <NUM_LIT> && <STR_LIT> ) ; if ( Opcode == TII . getCallFrameSetupOpcode ( ) ) { fixStackStores ( MBB , MI , TII , true ) ; } else { assert ( Opcode == TII . getCallFrameDestroyOpcode ( ) ) ; unsigned addOpcode ; if ( isUInt < <NUM_LIT> > ( Amount ) ) { addOpcode = <STR_LIT> ; } else { addOpcode = <STR_LIT> ; Amount = - Amount ; } BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ; MachineInstr * New = BuildMI ( MBB , MI , DL , TII . get ( addOpcode ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) . addImm ( Amount ) ; New -> getOperand ( <NUM_LIT> ) . setIsDead ( ) ;

BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> , RegState :: Kill ) ;


<s> void <ISA_LIT>Z80FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { CallingConv :: ID CallConv = MF . getFunction ( ) . getCallingConv ( ) ; MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> getDesc ( ) . isReturn ( ) && <STR_LIT> ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Z80MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ; int FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; const <ISA_LIT>Z80Subtarget & STI = MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ; const <ISA_LIT>Z80InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( ! FrameSize ) { return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ; } while ( FrameSize != <NUM_LIT> ) { int ToAdd = std :: min ( <NUM_LIT> , FrameSize ) ;

MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ToAdd ) . setMIFlag ( MachineInstr :: FrameDestroy ) ;


<s> MachineBasicBlock :: iterator MBBI = MBB . getLastNonDebugInstr ( ) ; assert ( MBBI -> getDesc ( ) . isReturn ( ) && <STR_LIT> ) ; DebugLoc DL = MBBI -> getDebugLoc ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Z80MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ; int FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; const <ISA_LIT>Z80Subtarget & STI = MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ; const <ISA_LIT>Z80InstrInfo & TII = * STI . getInstrInfo ( ) ; if ( ! FrameSize ) { return ; } while ( MBBI != MBB . begin ( ) ) { MachineBasicBlock :: iterator PI = std :: prev ( MBBI ) ; int Opc = PI -> getOpcode ( ) ; if ( Opc != <STR_LIT> && ! PI -> isTerminator ( ) ) { break ; } -- MBBI ; } while ( FrameSize != <NUM_LIT> ) { int ToAdd = std :: min ( <NUM_LIT> , FrameSize ) ; MachineInstr * MI = BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) ) . addImm ( ToAdd ) . setMIFlag ( MachineInstr :: FrameDestroy ) ; MI -> findRegisterDefOperand ( <STR_LIT> ) -> setIsDead ( ) ; FrameSize -= ToAdd ;


<s> void <ISA_LIT>Z80FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const { MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; CallingConv :: ID CallConv = MF . getFunction ( ) . getCallingConv ( ) ; DebugLoc DL = ( MBBI != MBB . end ( ) ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; const <ISA_LIT>Z80Subtarget & STI = MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ; const <ISA_LIT>Z80InstrInfo & TII = * STI . getInstrInfo ( ) ; bool HasFP = hasFP ( MF ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; const <ISA_LIT>Z80MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ; int FrameSize = MFI . getStackSize ( ) - AFI -> getCalleeSavedFrameSize ( ) ; while ( ( MBBI != MBB . end ( ) ) && MBBI -> getFlag ( MachineInstr :: FrameSetup ) && ( MBBI -> getOpcode ( ) == <STR_LIT> ) ) { ++ MBBI ; } if ( ! FrameSize ) { return ; } while ( FrameSize != <NUM_LIT> ) {

int ToSubtract = std :: min ( <NUM_LIT> , FrameSize ) ;


<s> } assert ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ; if ( insertPushes ) { unsigned SrcReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; bool SrcIsKill = MI . getOperand ( <NUM_LIT> ) . isKill ( ) ; if ( Opcode == <STR_LIT> ) { BuildMI ( MBB , I , MI . getDebugLoc ( ) , TII . get ( <STR_LIT> ) ) . addReg ( TRI . getSubReg ( SrcReg , <STR_LIT> ) , getKillRegState ( SrcIsKill ) ) ;


<s> <ISA_LIT>Z80DynAllocaSR ( ) : MachineFunctionPass ( ID ) {


<s> <ISA_LIT>Z80FrameAnalyzer ( ) : MachineFunctionPass ( ID ) {


<s> <ISA_LIT>Z80FrameLowering :: <ISA_LIT>Z80FrameLowering ( ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , - <NUM_LIT> , <NUM_LIT> , false ) {


<s> bool <ISA_LIT>Z80FrameLowering :: hasFP ( const MachineFunction & MF ) const {


<s> bool <ISA_LIT>Z80FrameLowering :: hasFP ( const MachineFunction & MF ) const { return false ;


<s> bool <ISA_LIT>Z80FrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const { return false ;


<s> DebugLoc DL = MBB . findDebugLoc ( MI ) ; const MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Z80Subtarget & STI = MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; for ( const CalleeSavedInfo & CCSI : CSI ) {


<s> unsigned SPCopy = MF . getRegInfo ( ) . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( EntryMBB , MBBI , DL , TII . get ( <STR_LIT> ) , SPCopy ) . addReg ( <STR_LIT> ) ; for ( MachineBasicBlock & MBB : MF ) {

if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) {


<s> if ( ! MBB . empty ( ) && MBB . back ( ) . isReturn ( ) ) { MBBI = MBB . getLastNonDebugInstr ( ) ; DL = MBBI -> getDebugLoc ( ) ; BuildMI ( MBB , MBBI , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( SPCopy , RegState :: Kill ) ; } }


<s> for ( const CalleeSavedInfo & CCSI : reverse ( CSI ) ) { unsigned Reg = CCSI . getReg ( ) ; bool IsNotLiveIn = ! MBB . isLiveIn ( Reg ) ; assert ( TRI -> getRegSizeInBits ( * TRI -> getMinimalPhysRegClass ( Reg ) ) == <NUM_LIT> && <STR_LIT> ) ; if ( IsNotLiveIn ) { MBB . addLiveIn ( Reg ) ; } BuildMI ( MBB , MI , DL , TII . get ( <STR_LIT> ) ) . addReg ( Reg , getKillRegState ( IsNotLiveIn ) ) . setMIFlag ( MachineInstr :: FrameSetup ) ; CalleeFrameSize += <NUM_LIT> ; } <ISA_LIT>Z80FI -> setCalleeSavedFrameSize ( CalleeFrameSize ) ;


<s> bool <ISA_LIT>Z80FrameLowering :: spillCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , const std :: vector < CalleeSavedInfo > & CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) { return false ; } unsigned CalleeFrameSize = <NUM_LIT> ; DebugLoc DL = MBB . findDebugLoc ( MI ) ; MachineFunction & MF = * MBB . getParent ( ) ; const <ISA_LIT>Z80Subtarget & STI = MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ;

<ISA_LIT>Z80MachineFunctionInfo * <ISA_LIT>Z80FI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ;


<s> <ISA_LIT>Z80InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> const char * <ISA_LIT>Z80InstPrinter :: getPrettyRegisterName ( unsigned RegNo ) { return getRegisterName ( RegNo ) ;


<s> case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> : O << <STR_LIT> ; break ; case <STR_LIT> :


<s> if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ; printAnnotation ( O , Annot ) ; break ; }


<s> switch ( Opcode ) { default : if ( ! printAliasInstr ( MI , O ) ) printInstruction ( MI , O ) ;


<s> assert ( MI -> getOperand ( OpNo ) . isReg ( ) && <STR_LIT> ) ; const MCOperand & OffsetOp = MI -> getOperand ( OpNo + <NUM_LIT> ) ; printOperand ( MI , OpNo , O ) ; if ( OffsetOp . isImm ( ) ) { int64_t Offset = OffsetOp . getImm ( ) ; if ( Offset >= <NUM_LIT> ) O << '+' ; O << Offset ;


<s> if ( Op . isReg ( ) ) { O << getRegisterName ( Op . getReg ( ) ) ; } else if ( Op . isImm ( ) ) { O << Op . getImm ( ) ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ;


<s> O << Imm ; } else { assert ( Op . isExpr ( ) && <STR_LIT> ) ; O << * Op . getExpr ( ) ; }


<s> else { assert ( MI -> getOperand ( OpNo ) . isExpr ( ) ) ; O << * MI -> getOperand ( OpNo ) . getExpr ( ) ; }


<s> void <ISA_LIT>Z80InstPrinter :: printUImm8 ( const MCInst * MI , unsigned OpNo , raw_ostream & O ) { assert ( MI -> getOperand ( OpNo ) . isImm ( ) && <STR_LIT> ) ; O << format ( <STR_LIT> , ( uint8_t ) ( uint64_t ) MI -> getOperand ( OpNo ) . getImm ( ) ) ;


<s> I -> eraseFromParent ( ) ; I = MBB . end ( ) ; continue ; } TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; continue ; } assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; <STR_LIT> <ISA_LIT>Z80CC = static_cast < <STR_LIT> > ( I -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; if ( <ISA_LIT>Z80CC == <STR_LIT> ) return true ; if ( Cond . empty ( ) ) { FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( <ISA_LIT>Z80CC ) ) ; continue ; } assert ( <NUM_LIT> && <STR_LIT> ) ;


<s> MachineInstr * MILoadReg = MI -> getPrevNode ( ) ; if ( MILoadReg == NULL || MILoadReg -> getOpcode ( ) != <STR_LIT> ) return NULL ; MachineOperand & MO0 = MI -> getOperand ( <NUM_LIT> ) ; MachineOperand & MO1 = MILoadReg -> getOperand ( <NUM_LIT> ) ; reg [ <NUM_LIT> ] = MO0 . getReg ( ) ; reg [ <NUM_LIT> ] = MO1 . getReg ( ) ; unsigned PreferArg = - <NUM_LIT> ; for ( MachineFunction :: iterator MFI = MF . begin ( ) , MFE = MF . end ( ) ; MFI != MFE ; MFI ++ ) { MachineBasicBlock :: iterator MBBI = MFI -> begin ( ) ; while ( MBBI != MFI -> end ( ) ) { if ( MBBI -> getOpcode ( ) == TargetOpcode :: COPY ) { if ( MBBI -> findRegisterDefOperand ( reg [ <NUM_LIT> ] ) ) {

arg [ <NUM_LIT> ] = MBBI -> getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> unsigned DestSubReg , SrcSubReg ; DestSubReg = RI . getSubReg ( DestReg , <STR_LIT> ) ; SrcSubReg = RI . getSubReg ( SrcReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestSubReg ) . addReg ( SrcSubReg ) ; DestSubReg = RI . getSubReg ( DestReg , <STR_LIT> ) ; SrcSubReg = RI . getSubReg ( SrcReg , <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestSubReg ) . addReg ( SrcSubReg ) ; if ( KillSrc ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg ) ; return ; } else if ( <STR_LIT> . contains ( DestReg ) || <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) ; return ;


<s> return false ; } unsigned Lo , Hi ; Lo = RI . getSubReg ( Reg , <STR_LIT> ) ; Hi = RI . getSubReg ( Reg , <STR_LIT> ) ; MI -> eraseFromParent ( ) ;


<s> <ISA_LIT>Z80InstrInfo :: <ISA_LIT>Z80InstrInfo ( <ISA_LIT>Z80TargetMachine & tm ) : <ISA_LIT>Z80GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( tm , * this ) , TM ( tm ) {


<s> virtual const <ISA_LIT>Z80RegisterInfo & getRegisterInfo ( ) const {


<s> assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } unsigned Count = <NUM_LIT> ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) . addImm ( Cond [ <NUM_LIT> ] . getImm ( ) ) ; Count ++ ; if ( FBB ) {

BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ;


<s> if ( MI != MBB . end ( ) ) dl = MI -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , dl , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) ;

else if ( RC == & <STR_LIT> || <STR_LIT> . contains ( DestReg ) ) {


<s> I -- ; if ( I -> isDebugValue ( ) ) continue ;

if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ;


<s> if ( I -> getOpcode ( ) != <STR_LIT> && I -> getOpcode ( ) != <STR_LIT> ) break ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; Count ++ ; }


<s> if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , dl , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; else if ( RC == & <STR_LIT> || <STR_LIT> . contains ( SrcReg ) ) { BuildMI ( MBB , MI , dl , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; }


<s> if ( MI != MBB . end ( ) ) dl = MI -> getDebugLoc ( ) ; if ( RC == & <STR_LIT> ) BuildMI ( MBB , MI , dl , get ( <STR_LIT> ) ) . addFrameIndex ( FrameIndex ) . addImm ( <NUM_LIT> ) . addReg ( SrcReg , getKillRegState ( isKill ) ) ; else if ( RC == & <STR_LIT> || <STR_LIT> . contains ( SrcReg ) ) {


<s> if ( BranchCode == <STR_LIT> ) { return true ; } if ( Cond . empty ( ) ) { MachineBasicBlock * TargetBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; if ( AllowModify && UnCondBrIter != MBB . end ( ) && MBB . isLayoutSuccessor ( TargetBB ) ) { BranchCode = getOppositeCondition ( BranchCode ) ; MachineBasicBlock :: iterator OldInst = I ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( UnCondBrIter -> getOperand ( <NUM_LIT> ) . getMBB ( ) ) . addImm ( BranchCode ) ; BuildMI ( MBB , UnCondBrIter , MBB . findDebugLoc ( I ) , get ( <STR_LIT> ) ) . addMBB ( TargetBB ) ; OldInst -> eraseFromParent ( ) ; UnCondBrIter -> eraseFromParent ( ) ; UnCondBrIter = MBB . end ( ) ; I = MBB . end ( ) ; continue ; } FBB = TBB ; TBB = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( BranchCode ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( <NUM_LIT> ) ) ; continue ; } assert ( TBB ) ; <STR_LIT> CC = ( <STR_LIT> ) I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; const MachineBasicBlock * Dest = I -> getOperand ( <NUM_LIT> ) . getMBB ( ) ; assert ( FBB && <STR_LIT> ) ; if ( Dest != TBB && Dest != FBB ) { return true ; } if ( AllowModify ) { MachineBasicBlock :: iterator OldI = UnCondBrIter ; ++ OldI ; for ( ; OldI != I ; OldI ++ ) if ( OldI -> getOperand ( <NUM_LIT> ) . getImm ( ) == ( int ) CC ) break ; if ( OldI != I ) {


<s> SmallVector < MachineOperand , <NUM_LIT> > Cond ; MachineBasicBlock * FBB = nullptr , * TBB = nullptr ; if ( analyzeBranch ( MBB , TBB , FBB , Cond , AllowModify ) ) return true ;


<s> if ( analyzeBranch ( MBB , TBB , FBB , Cond , AllowModify ) ) return true ; return true ;


<s> if ( MRI . getRegClass ( MI . getOperand ( OpIdx2 ) . getReg ( ) ) -> hasSuperClassEq ( & <STR_LIT> ) ) {

if ( ! safeToCommute ( MI , OpIdx1 , OpIdx2 ) ) return nullptr ;


<s> MachineRegisterInfo & MRI = MI . getParent ( ) -> getParent ( ) -> getRegInfo ( ) ; if ( MRI . getRegClass ( MI . getOperand ( OpIdx2 ) . getReg ( ) ) -> hasSuperClassEq ( & <STR_LIT> ) ) { if ( ! safeToCommute ( MI , OpIdx1 , OpIdx2 ) ) return nullptr ; }

return TargetInstrInfo :: commuteInstructionImpl ( MI , NewMI , OpIdx1 , OpIdx2 ) ;


<s> TRI . splitReg ( SrcReg , SrcLo , SrcHi ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestLo ) . addReg ( SrcLo , getKillRegState ( KillSrc ) ) ; BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestHi ) . addReg ( SrcHi , getKillRegState ( KillSrc ) ) ; } else if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else if ( DestReg == <STR_LIT> && SrcReg == <STR_LIT> ) { BuildMI ( MBB , MI , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else {


<s> <ISA_LIT>Z80InstrInfo :: <ISA_LIT>Z80InstrInfo ( ) : <ISA_LIT>Z80GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ) {


<s> const <ISA_LIT>Z80Subtarget & STI = MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ; const TargetInstrInfo & TII = * STI . getInstrInfo ( ) ; return TII . getInlineAsmLength ( MI . getOperand ( <NUM_LIT> ) . getSymbolName ( ) , * TM . getMCAsmInfo ( ) ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> const <ISA_LIT>Z80RegisterInfo & getRegisterInfo ( ) const { return RI ;


<s> const <ISA_LIT>Z80RegisterInfo & getRegisterInfo ( ) const {


<s> case <STR_LIT> : return <NUM_LIT> ; case <STR_LIT> : return ( int8_t ) MI . getOperand ( <NUM_LIT> ) . getImm ( ) ;


<s> assert ( std :: next ( MBB . getIterator ( ) ) != MBB . getParent ( ) -> end ( ) && <STR_LIT> ) ; } auto & CondMI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( Dest ) . addImm ( ( int ) CC ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; ++ Count ; } if ( FBB ) { auto & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; ++ Count ; } return Count ;


<s> unsigned <ISA_LIT>Z80InstrInfo :: insertIndirectBranch ( MachineBasicBlock & MBB , MachineBasicBlock & NewDestBB , const DebugLoc & DL , int64_t BrOffset , RegScavenger * RS ) const {

auto & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( & NewDestBB ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; case <NUM_LIT> : { <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; Cond [ <NUM_LIT> ] . setImm ( ( int ) getOppositeCondition ( CC ) ) ; break ; } case <NUM_LIT> : bool FirstBlockIsT = Cond [ <NUM_LIT> ] . getImm ( ) ; Cond [ <NUM_LIT> ] . setImm ( ! FirstBlockIsT ) ; <STR_LIT> CC = ( <STR_LIT> ) Cond [ <NUM_LIT> ] . getImm ( ) ; Cond [ <NUM_LIT> ] . setImm ( ( int ) getOppositeCondition ( CC ) ) ; break ; } return true ;


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> :

return BrOffset >= - <NUM_LIT> && BrOffset <= <NUM_LIT> ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; case <STR_LIT> : case <STR_LIT> : return BrOffset >= - <NUM_LIT> && BrOffset <= <NUM_LIT> ; }


<s> FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ;


<s> default : return false ; case <STR_LIT> : case <STR_LIT> : return true ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } break ; } default : break ;


<s> return I . getOpcode ( ) == <STR_LIT> || I . getOpcode ( ) == <STR_LIT> ;


<s> bool <ISA_LIT>Z80InstrInfo :: isUnconditionalBranch ( const MachineInstr & I ) const { return I . getOpcode ( ) == <STR_LIT> || I . getOpcode ( ) == <STR_LIT> ;


<s> DebugLoc DL ; if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } MachineFunction & MF = * MBB . getParent ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { assert ( false && <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) ;


<s> unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { assert ( false && <STR_LIT> ) ; } else { llvm_unreachable ( <STR_LIT> ) ; }

BuildMI ( MBB , MI , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FrameIndex ) . addMemOperand ( MMO ) ;


<s> MachineInstr * MI = MBB . getParent ( ) -> CloneMachineInstr ( & Orig ) ; MBB . insert ( I , MI ) ; MachineInstr & NewMI = * std :: prev ( I ) ; NewMI . substituteRegister ( Orig . getOperand ( <NUM_LIT> ) . getReg ( ) , DestReg , SubIdx , TRI ) ;


<s> unsigned <ISA_LIT>Z80InstrInfo :: removeBranch ( MachineBasicBlock & MBB , int * BytesRemoved ) const { if ( BytesRemoved ) * BytesRemoved = <NUM_LIT> ; MachineBasicBlock :: iterator I = MBB . end ( ) ; unsigned Count = <NUM_LIT> ; while ( I != MBB . begin ( ) ) { -- I ; if ( I -> isDebugValue ( ) ) { continue ; } if ( ! isUnconditionalBranch ( * I ) && ! isConditionalBranch ( * I ) ) { break ; } if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ;


<s> continue ; } if ( ! isUnconditionalBranch ( * I ) && ! isConditionalBranch ( * I ) ) { break ; } if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ; I = MBB . end ( ) ; ++ Count ; } return Count ;


<s> assert ( ( Cond . size ( ) % <NUM_LIT> == <NUM_LIT> ) && <STR_LIT> ) ; return ! invertCondition ( Cond ) ;


<s> MachineInstr * LHSDef = nullptr ; MachineInstr * RHSDef = nullptr ; unsigned LHSReg = MI . getOperand ( OpIdx1 ) . getReg ( ) ; unsigned RHSReg = MI . getOperand ( OpIdx2 ) . getReg ( ) ; unsigned LHSSub = MI . getOperand ( OpIdx1 ) . getSubReg ( ) ; unsigned RHSSub = MI . getOperand ( OpIdx2 ) . getSubReg ( ) ; return false ; MachineBasicBlock :: reverse_iterator Begin = MI , End = MBB . rend ( ) ; ++ Begin ; while ( Begin != End ) { if ( ! LHSDef && Begin -> definesRegister ( LHSReg , TRI ) ) LHSDef = & * Begin ;

if ( ! RHSDef && Begin -> definesRegister ( RHSReg , TRI ) ) RHSDef = & * Begin ;


<s> if ( ! LHSDef && Begin -> definesRegister ( LHSReg , TRI ) ) LHSDef = & * Begin ; if ( ! RHSDef && Begin -> definesRegister ( RHSReg , TRI ) ) RHSDef = & * Begin ; if ( LHSDef && RHSDef ) break ; Begin ++ ; } if ( ! LHSDef || ! RHSDef ) return false ; if ( LHSDef -> getOpcode ( ) != <STR_LIT> || RHSDef -> getOpcode ( ) != <STR_LIT> ) return false ; bool LHSIsSafe = ! TRI -> isPhysicalRegister ( LHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) && ( MRI . getRegClass ( LHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) == & <STR_LIT> || MRI . getRegClass ( LHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) -> hasSuperClassEq ( & <STR_LIT> ) ) ; bool RHSIsSafe = ( TRI -> isPhysicalRegister ( RHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) && RHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) || ( ! TRI -> isPhysicalRegister ( RHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) && MRI . getRegClass ( RHSDef -> getOperand ( <NUM_LIT> ) . getReg ( ) ) == & <STR_LIT> ) ; return LHSIsSafe && RHSIsSafe ;


<s> AFI -> setHasSpills ( true ) ; DebugLoc DL ; if ( MI != MBB . end ( ) ) { DL = MI -> getDebugLoc ( ) ; } const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FrameIndex ) , MachineMemOperand :: MOStore , MFI . getObjectSize ( FrameIndex ) , MFI . getObjectAlignment ( FrameIndex ) ) ; unsigned Opcode = <NUM_LIT> ; if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { Opcode = <STR_LIT> ; } else if ( TRI -> isTypeLegalForClass ( * RC , <STR_LIT> ) ) { assert ( false && <STR_LIT> ) ;


<s> SmallVector < MachineOperand , <NUM_LIT> > Copy ( Cond . begin ( ) , Cond . end ( ) ) ; Cond . clear ( ) ; CCPair CondTuple ; if ( Cond . size ( ) == <NUM_LIT> ) CondTuple = std :: make_tuple ( ( <STR_LIT> ) Copy [ <NUM_LIT> ] . getImm ( ) , ( bool ) Copy [ <NUM_LIT> ] . getImm ( ) , <STR_LIT> , false ) ; else if ( Cond . size ( ) == <NUM_LIT> ) CondTuple = std :: make_tuple ( ( <STR_LIT> ) Copy [ <NUM_LIT> ] . getImm ( ) , ( bool ) Copy [ <NUM_LIT> ] . getImm ( ) , ( <STR_LIT> ) Copy [ <NUM_LIT> ] . getImm ( ) , ( bool ) Copy [ <NUM_LIT> ] . getImm ( ) ) ; unsigned CPClass = CCPair2CPClass . at ( CondTuple ) ; unsigned SwappedClass = swapCPClass ( CPClass ) ; CondTuple = CPClass2CCPairs . at ( SwappedClass ) . at ( <NUM_LIT> ) ; if ( std :: get < <NUM_LIT> > ( CondTuple ) != <STR_LIT> ) { Cond . push_back ( MachineOperand :: CreateImm ( std :: get < <NUM_LIT> > ( CondTuple ) ) ) ; Cond . push_back ( MachineOperand :: CreateImm ( std :: get < <NUM_LIT> > ( CondTuple ) ) ) ; } Cond . push_back ( MachineOperand :: CreateImm ( std :: get < <NUM_LIT> > ( CondTuple ) ) ) ;


<s> unsigned swapCPClass ( unsigned Class ) const {

return ( ( Class & <NUM_LIT> ) << <NUM_LIT> ) | ( ( Class & <NUM_LIT> ) >> <NUM_LIT> ) | ( Class & <NUM_LIT> ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>Z80ISelDAG ( <ISA_LIT>Z80TargetMachine & TM , CodeGenOpt :: Level OptLevel ) { return new <ISA_LIT>Z80DAGToDAGISel ( TM , OptLevel ) ;


<s> return new <ISA_LIT>Z80DAGToDAGISel ( TM , OptLevel ) ;


<s> <ISA_LIT>Z80DAGToDAGISel ( <ISA_LIT>Z80TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) {


<s> if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) {

Addr = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ;


<s> switch ( N -> getOpcode ( ) ) { case <STR_LIT> : if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( N ) ) { Addr = CurDAG -> getTargetConstant ( CN -> getZExtValue ( ) , <STR_LIT> ) ; return true ; } break ;


<s> <ISA_LIT>Z80DAGToDAGISel ( <ISA_LIT>Z80TargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) , Subtarget ( nullptr ) {


<s> bool <ISA_LIT>Z80DAGToDAGISel :: runOnMachineFunction ( MachineFunction & MF ) {

Subtarget = & MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ;


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ;

return SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> if ( N -> isMachineOpcode ( ) ) { LLVM_DEBUG ( errs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; errs ( ) << <STR_LIT> ) ; N -> setNodeId ( - <NUM_LIT> ) ;


<s> if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; if ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return false ; Reg = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ; return true ;


<s> if ( ! C ) return false ; if ( C -> getZExtValue ( ) != <NUM_LIT> ) return false ; if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> && N . getOperand ( <NUM_LIT> ) . getOpcode ( ) != <STR_LIT> ) return false ; if ( N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) . getValueType ( ) != <STR_LIT> ) return false ; Reg = N . getOperand ( <NUM_LIT> ) . getOperand ( <NUM_LIT> ) ;


<s> } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) { RHSC = - RHSC ; } if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , PtrVT ) ; Disp = CurDAG -> getTargetConstant ( RHSC , dl , <STR_LIT> ) ; return true ; }

MVT VT = cast < MemSDNode > ( Op ) -> getMemoryVT ( ) . getSimpleVT ( ) ;


<s> if ( const GlobalAddressSDNode * GA = dyn_cast < GlobalAddressSDNode > ( N ) ) { Address = CurDAG -> getTargetGlobalAddress ( GA -> getGlobal ( ) , ; } if ( const ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( N . getOperand ( <NUM_LIT> ) ) ) { int RHSC = ( int ) RHS -> getZExtValue ( ) ; if ( N . getOpcode ( ) == <STR_LIT> ) { RHSC = - RHSC ; } if ( N . getOperand ( <NUM_LIT> ) . getOpcode ( ) == <STR_LIT> ) { int FI = cast < FrameIndexSDNode > ( N . getOperand ( <NUM_LIT> ) ) -> getIndex ( ) ; Base = CurDAG -> getTargetFrameIndex ( FI , PtrVT ) ; Disp = CurDAG -> getTargetConstant ( RHSC , dl , <STR_LIT> ) ; return true ; } MVT VT = cast < MemSDNode > ( Op ) -> getMemoryVT ( ) . getSimpleVT ( ) ; if ( isUInt < <NUM_LIT> > ( RHSC ) && ( VT == <STR_LIT> || VT == <STR_LIT> ) ) { Base = N . getOperand ( <NUM_LIT> ) ; Disp = CurDAG -> getTargetConstant ( RHSC , dl , <STR_LIT> ) ; return true ; } } return false ;


<s> unsigned <ISA_LIT>Z80DAGToDAGISel :: selectIndexedProgMemLoad ( const LoadSDNode * LD , MVT VT ) { <STR_LIT> AM = LD -> getAddressingMode ( ) ; if ( LD -> getExtensionType ( ) != <STR_LIT> || AM != <STR_LIT> ) { return <NUM_LIT> ; } unsigned Opcode = <NUM_LIT> ; int Offs = cast < ConstantSDNode > ( LD -> getOffset ( ) ) -> getSExtValue ( ) ; switch ( VT . SimpleTy ) { case <STR_LIT> : { if ( Offs != <NUM_LIT> ) { return <NUM_LIT> ; } Opcode = <STR_LIT> ; break ; } case <STR_LIT> : { if ( Offs != <NUM_LIT> ) { return <NUM_LIT> ; } Opcode = <STR_LIT> ; break ; } default :


<s> bool CanHandleRegImmOpt = true ; CanHandleRegImmOpt &= ImmNode != <NUM_LIT> ; CanHandleRegImmOpt &= ImmNode -> getAPIntValue ( ) . getZExtValue ( ) < <NUM_LIT> ; if ( CopyFromRegOp -> getOpcode ( ) == <STR_LIT> ) { RegisterSDNode * RegNode = cast < RegisterSDNode > ( CopyFromRegOp -> getOperand ( <NUM_LIT> ) ) ; Reg = RegNode -> getReg ( ) ; CanHandleRegImmOpt &= ( TargetRegisterInfo :: isVirtualRegister ( Reg ) || <STR_LIT> . contains ( Reg ) ) ; } else { CanHandleRegImmOpt = false ; } if ( CanHandleRegImmOpt ) { SDValue Base , Disp ; if ( RI . getRegClass ( Reg ) != & <STR_LIT> ) { SDLoc dl ( CopyFromRegOp ) ; unsigned VReg = RI . createVirtualRegister ( & <STR_LIT> ) ; SDValue CopyToReg = CurDAG -> getCopyToReg ( CopyFromRegOp , dl , VReg , CopyFromRegOp ) ; SDValue NewCopyFromRegOp = CurDAG -> getCopyFromReg ( CopyToReg , dl , VReg , TL . getPointerTy ( DL ) ) ; Base = NewCopyFromRegOp ; } else { Base = CopyFromRegOp ;


<s> MVT Type = N -> getSimpleValueType ( <NUM_LIT> ) ; assert ( false && <STR_LIT> ) ; assert ( Type == <STR_LIT> && <STR_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned MachineOp = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Lhs = N -> getOperand ( <NUM_LIT> ) ; SDValue Rhs = N -> getOperand ( <NUM_LIT> ) ;

SDNode * Mul = CurDAG -> getMachineNode ( MachineOp , DL , <STR_LIT> , Lhs , Rhs ) ;


<s> assert ( Type == <STR_LIT> && <STR_LIT> ) ; bool isSigned = N -> getOpcode ( ) == <STR_LIT> ; unsigned MachineOp = isSigned ? <STR_LIT> : <STR_LIT> ; SDValue Lhs = N -> getOperand ( <NUM_LIT> ) ; SDValue Rhs = N -> getOperand ( <NUM_LIT> ) ; SDNode * Mul = CurDAG -> getMachineNode ( MachineOp , DL , <STR_LIT> , Lhs , Rhs ) ; SDValue InChain = CurDAG -> getEntryNode ( ) ; SDValue InGlue = SDValue ( Mul , <NUM_LIT> ) ; if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromLo = CurDAG -> getCopyFromReg ( InChain , DL , <STR_LIT> , Type , InGlue ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , CopyFromLo ) ; InChain = CopyFromLo . getValue ( <NUM_LIT> ) ; InGlue = CopyFromLo . getValue ( <NUM_LIT> ) ; } if ( N -> hasAnyUseOfValue ( <NUM_LIT> ) ) { SDValue CopyFromHi = CurDAG -> getCopyFromReg ( InChain , DL , <STR_LIT> , Type , InGlue ) ; ReplaceUses ( SDValue ( N , <NUM_LIT> ) , CopyFromHi ) ;

InChain = CopyFromHi . getValue ( <NUM_LIT> ) ;


<s> switch ( Opcode ) { case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : case <STR_LIT> : return selectMultiplication ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; case <STR_LIT> : return select < <STR_LIT> > ( N ) ; default : return false ; }


<s> TCC = <STR_LIT> ; break ; case <STR_LIT> : case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; case <STR_LIT> : TCC = <STR_LIT> ; break ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; case <STR_LIT> : TCC = <STR_LIT> ; break ; default : llvm_unreachable ( <STR_LIT> ) ; } <ISA_LIT>Z80CC = DAG . getConstant ( TCC , <STR_LIT> ) ;

if ( VT == <STR_LIT> ) return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , LHS , RHS ) ;


<s> MachineBasicBlock * <ISA_LIT>Z80TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr * MI , MachineBasicBlock * MBB ) const { unsigned Opc = MI -> getOpcode ( ) ; switch ( Opc ) { case <STR_LIT> : case <STR_LIT> : return EmitSelectInstr ( MI , MBB ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return EmitShiftInstr ( MI , MBB ) ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> MF -> insert ( I , copy1MBB ) ; copy1MBB -> splice ( copy1MBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; copy1MBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; MBB -> addSuccessor ( copy0MBB ) ; MBB -> addSuccessor ( copy1MBB ) ; BuildMI ( MBB , dl , TII . get ( <STR_LIT> ) ) . addMBB ( copy1MBB ) . addImm ( MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ) ; MBB = copy0MBB ; MBB -> addSuccessor ( copy1MBB ) ; MBB = copy1MBB ; BuildMI ( * MBB , MBB -> begin ( ) , dl , TII . get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( thisMBB ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( copy0MBB ) ;


<s> addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , & <STR_LIT> ) ; computeRegisterProperties ( ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setBooleanContents ( ZeroOrOneBooleanContent ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ;


<s> virtual MVT getScalarShiftAmountTy ( EVT LHSTy ) const { return <STR_LIT> ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> RHS_LO = DAG . getConstant ( CN -> getZExtValue ( ) & <NUM_LIT> , HalfVT ) ; RHS_HI = DAG . getConstant ( CN -> getZExtValue ( ) >> <NUM_LIT> & <NUM_LIT> , HalfVT ) ; } else { RHS_LO = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , HalfVT , RHS ) ; RHS_HI = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , HalfVT , RHS ) ; } LO = DAG . getNode ( Opc , dl , HalfVT , LHS_LO , RHS_LO ) ; HI = DAG . getNode ( Opc , dl , HalfVT , LHS_HI , RHS_HI ) ;

Res = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , VT , DAG . getUNDEF ( VT ) , LO ) ;


<s> RHS_LO = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , HalfVT , RHS ) ; RHS_HI = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , HalfVT , RHS ) ; } LO = DAG . getNode ( Opc , dl , HalfVT , LHS_LO , RHS_LO ) ; HI = DAG . getNode ( Opc , dl , HalfVT , LHS_HI , RHS_HI ) ; Res = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , VT , DAG . getUNDEF ( VT ) , LO ) ; Res = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , VT , Res , HI ) ;


<s> SDLoc dl ( Op ) ; EVT VT = Op . getValueType ( ) ; SDValue Chain = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ;

SDValue RHS = Op . getOperand ( <NUM_LIT> ) ;


<s> <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue LHS = Op . getOperand ( <NUM_LIT> ) ; SDValue RHS = Op . getOperand ( <NUM_LIT> ) ; SDValue Dest = Op . getOperand ( <NUM_LIT> ) ; SDValue <ISA_LIT>Z80CC ; SDValue Flag = EmitCMP ( LHS , RHS , <ISA_LIT>Z80CC , CC , dl , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VT , Chain , Dest , <ISA_LIT>Z80CC , Flag ) ;


<s> MemOp = DAG . getStore ( Chain , dl , Arg , PtrOff , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ; MemOpChains . push_back ( MemOp ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue Flag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; i ++ ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; SDVTList NodeTys = DAG . getVTList ( <STR_LIT> , <STR_LIT> ) ; SmallVector < SDValue , <NUM_LIT> > Ops ; Ops . push_back ( Chain ) ; Ops . push_back ( Callee ) ; const TargetRegisterInfo * TRI = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const uint32_t * Mask = TRI -> getCallPreservedMask ( CallConv ) ; Ops . push_back ( DAG . getRegisterMask ( Mask ) ) ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; i ++ ) Ops . push_back ( DAG . getRegister ( RegsToPass [ i ] . first , RegsToPass [ i ] . second . getValueType ( ) ) ) ; if ( Flag . getNode ( ) ) Ops . push_back ( Flag ) ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getConstant ( NumBytes , getPointerTy ( ) , true ) , DAG . getConstant ( <NUM_LIT> , getPointerTy ( ) , true ) , Flag , dl ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; return LowerCallResult ( Chain , Flag , CallConv , isVarArg , Ins , dl , DAG , InVals ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeCallResult ( Ins , RetCC_<ISA_LIT>Z80 ) ; for ( unsigned i = <NUM_LIT> , e = Ins . size ( ) ; i != e ; i ++ ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLocs [ i ] . getLocReg ( ) , RVLocs [ i ] . getValVT ( ) , Flag ) . getValue ( <NUM_LIT> ) ;


<s> MachineRegisterInfo & MRI = MF . getRegInfo ( ) ; <ISA_LIT>Z80MachineFunctionInfo * <ISA_LIT>Z80FI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_<ISA_LIT>Z80 ) ; assert ( ! isVarArg && <STR_LIT> ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; i ++ ) { SDValue ArgValue ; unsigned VReg ; CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; switch ( RegVT . getSimpleVT ( ) . SimpleTy ) { default : {

errs ( ) << <STR_LIT> << RegVT . getSimpleVT ( ) . SimpleTy << <STR_LIT> ;


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ;

SDValue Result = DAG . getTargetGlobalAddress ( GV , dl , VT , Offset ) ;


<s> SDValue <ISA_LIT>Z80TargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) const { SDLoc dl ( Op ) ; EVT VT = getPointerTy ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ; SDValue Result = DAG . getTargetGlobalAddress ( GV , dl , VT , Offset ) ;

return DAG . getNode ( <STR_LIT> , dl , VT , Result ) ;


<s> LoadSDNode * LD = cast < LoadSDNode > ( Op ) ; SDValue Chain = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; assert ( ! LD -> isIndexed ( ) && <STR_LIT> ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> && <STR_LIT> ) ; switch ( BasePtr . getOpcode ( ) ) { default : break ; case <STR_LIT> : return SDValue ( ) ; } SDValue Lo = DAG . getLoad ( <STR_LIT> , dl , Chain , BasePtr , MachinePointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ; SDValue Hi = DAG . getLoad ( <STR_LIT> , dl , Chain , HighAddr , MachinePointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue NewChain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Lo . getValue ( <NUM_LIT> ) , Hi . getValue ( <NUM_LIT> ) ) ; SDValue LoRes = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , <STR_LIT> , DAG . getUNDEF ( <STR_LIT> ) , Lo ) ;

SDValue HiRes = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , <STR_LIT> , LoRes , Hi ) ;


<s> LoadSDNode * LD = cast < LoadSDNode > ( Op ) ; SDValue Chain = LD -> getChain ( ) ; SDValue BasePtr = LD -> getBasePtr ( ) ; assert ( ! LD -> isIndexed ( ) && <STR_LIT> ) ; assert ( LD -> getExtensionType ( ) == <STR_LIT> && <STR_LIT> ) ; switch ( BasePtr . getOpcode ( ) ) { default : break ; case <STR_LIT> : return SDValue ( ) ; } SDValue Lo = DAG . getLoad ( <STR_LIT> , dl , Chain , BasePtr , MachinePointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ; SDValue HighAddr = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , BasePtr , DAG . getConstant ( <NUM_LIT> , <STR_LIT> ) ) ;

SDValue Hi = DAG . getLoad ( <STR_LIT> , dl , Chain , HighAddr , MachinePointerInfo ( ) , LD -> isVolatile ( ) , LD -> isNonTemporal ( ) , LD -> isInvariant ( ) , LD -> getAlignment ( ) ) ;


<s> SDValue <ISA_LIT>Z80TargetLowering :: LowerOperation ( SDValue Op , SelectionDAG & DAG ) const { switch ( Op . getOpcode ( ) ) { case <STR_LIT> : return LowerZExt ( Op , DAG ) ; case <STR_LIT> : return LowerSExt ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerSUB ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> :


<s> SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>Z80 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; i ++ ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; }


<s> CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeReturn ( Outs , RetCC_<ISA_LIT>Z80 ) ; SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; i ++ ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; }


<s> SDValue TrueV = Op . getOperand ( <NUM_LIT> ) ; SDValue FalseV = Op . getOperand ( <NUM_LIT> ) ; <STR_LIT> CC = cast < CondCodeSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> get ( ) ; SDValue <ISA_LIT>Z80CC ; SDValue Flag = EmitCMP ( LHS , RHS , <ISA_LIT>Z80CC , CC , dl , DAG ) ; return DAG . getNode ( <STR_LIT> , dl , VT , TrueV , FalseV , <ISA_LIT>Z80CC , Flag ) ;


<s> SDValue LO = DAG . getTargetInsertSubreg ( <STR_LIT> , dl , VT , DAG . getUNDEF ( VT ) , Val ) ; SDValue Add = DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( HalfVT , <STR_LIT> ) , Val , Val ) ;

SDValue Flag = Add . getValue ( <NUM_LIT> ) ;


<s> } uint64_t ShiftAmount = cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; SDValue Victim = N -> getOperand ( <NUM_LIT> ) ; switch ( Opc ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; case <STR_LIT> : Opc = <STR_LIT> ; break ; } if ( VT == <STR_LIT> ) { SDValue LO , HI , Flag ; EVT HalfVT = VT . getHalfSizedIntegerVT ( * DAG . getContext ( ) ) ; SDVTList VTs = DAG . getVTList ( HalfVT , <STR_LIT> ) ; LO = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , HalfVT , Victim ) ;

HI = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , HalfVT , Victim ) ;


<s> assert ( ! ST -> isIndexed ( ) && <STR_LIT> ) ; switch ( BasePtr . getOpcode ( ) ) { default : break ; case <STR_LIT> : if ( RegisterSDNode * RN = dyn_cast < RegisterSDNode > ( BasePtr . getOperand ( <NUM_LIT> ) ) ) if ( RN -> getReg ( ) != getTargetMachine ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) -> getFrameRegister ( DAG . getMachineFunction ( ) ) ) break ; case <STR_LIT> : return SDValue ( ) ; } SDValue Lo , Hi ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Value ) ) {

Lo = DAG . getConstant ( CN -> getZExtValue ( ) & <NUM_LIT> , <STR_LIT> ) ;


<s> SDValue BasePtr = ST -> getBasePtr ( ) ; SDValue Value = ST -> getOperand ( <NUM_LIT> ) ; assert ( ! ST -> isTruncatingStore ( ) && <STR_LIT> ) ; assert ( ! ST -> isIndexed ( ) && <STR_LIT> ) ; switch ( BasePtr . getOpcode ( ) ) { default : break ; case <STR_LIT> : if ( RegisterSDNode * RN = dyn_cast < RegisterSDNode > ( BasePtr . getOperand ( <NUM_LIT> ) ) ) if ( RN -> getReg ( ) != getTargetMachine ( ) . getSubtargetImpl ( ) -> getRegisterInfo ( ) -> getFrameRegister ( DAG . getMachineFunction ( ) ) ) break ; case <STR_LIT> : return SDValue ( ) ; } SDValue Lo , Hi ; if ( ConstantSDNode * CN = dyn_cast < ConstantSDNode > ( Value ) ) { Lo = DAG . getConstant ( CN -> getZExtValue ( ) & <NUM_LIT> , <STR_LIT> ) ; Hi = DAG . getConstant ( ( CN -> getZExtValue ( ) >> <NUM_LIT> ) & <NUM_LIT> , <STR_LIT> ) ; } else {

Lo = DAG . getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , Value ) ;


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Flag ; Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flag ) ; return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , Op0 , Op1 , Flag ) ;


<s> SDValue Op1 = Op . getOperand ( <NUM_LIT> ) ; EVT VT = Op . getValueType ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ; SDValue Flag ; Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> ) ; Flag = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Flag ) ;

return DAG . getNode ( <STR_LIT> , dl , DAG . getVTList ( VT , <STR_LIT> ) , Op0 , Op1 , Flag ) ;


<s> EVT VT = Op . getValueType ( ) ; assert ( VT == <STR_LIT> && <STR_LIT> ) ;

SDValue Tmp = DAG . getConstant ( <NUM_LIT> , VT . getHalfSizedIntegerVT ( * DAG . getContext ( ) ) ) ;


<s> default : { analyzeStandardArguments ( CLI , F , TD , Outs , Ins , CallConv , ArgLocs , CCInfo , IsCall , IsVarArg ) ; return ; }


<s> StringRef FuncName = getFunctionName ( CLI ) ; if ( FuncName . startswith ( <STR_LIT> ) || FuncName . startswith ( <STR_LIT> ) ) { } else { analyzeStandardArguments ( & CLI , F , TD , Outs , Ins , CallConv , ArgLocs , CCInfo , IsCall , IsVarArg ) ; }


<s> if ( Reg ) { CCInfo . addLoc ( CCValAssign :: getReg ( ValNo ++ , LocVT , Reg , LocVT , CCValAssign :: Full ) ) ; pos += Size ; continue ; } } UsesStack = true ; for ( unsigned j = <NUM_LIT> ; j != Size ; ++ j ) { unsigned Offset = CCInfo . AllocateStack ( TD -> getTypeAllocSize ( EVT ( LocVT ) . getTypeForEVT ( CCInfo . getContext ( ) ) ) , TD -> getABITypeAlignment ( EVT ( LocVT ) . getTypeForEVT ( CCInfo . getContext ( ) ) ) ) ; CCInfo . addLoc ( CCValAssign :: getMem ( ValNo ++ , LocVT , Offset , LocVT , CCValAssign :: Full ) ) ; } pos += Size ;


<s> bool <ISA_LIT>Z80TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ;

CCState CCInfo ( CallConv , isVarArg , MF , RVLocs , Context ) ;


<s> CCAssignFn * <ISA_LIT>Z80TargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC ) const { switch ( CC ) { default : return RetCC_<ISA_LIT>Z80 ;


<s> llvm_unreachable ( <STR_LIT> ) ; return nullptr ;


<s> <STR_LIT> getCmpLibcallReturnType ( ) const override {


<s> if ( const GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) {

return G -> getGlobal ( ) -> getName ( ) ;


<s> break ; case <STR_LIT> : LHS = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; RHS = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; case <STR_LIT> : std :: swap ( LHS , RHS ) ; CC = <STR_LIT> ; break ; case <STR_LIT> : LHS = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , LHS , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; RHS = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , RHS , DAG . getConstant ( <NUM_LIT> , DL , <STR_LIT> ) ) ; CC = <STR_LIT> ; break ;


<s> SDValue <ISA_LIT>Z80TargetLowering :: getPair ( SDValue Lo , SDValue Hi , SelectionDAG & DAG ) const {


<s> MVT getScalarShiftAmountTy ( const DataLayout & , EVT LHSTy ) const override {


<s> assert ( ! VT . isVector ( ) && <STR_LIT> ) ; return <STR_LIT> ;


<s> NODE ( CALL ) ; NODE ( WRAPPER ) ; NODE ( FI ) ; NODE ( LSL ) ; NODE ( LSR ) ; NODE ( ROL ) ; NODE ( ROR ) ; NODE ( ASR ) ; NODE ( LSLLOOP ) ; NODE ( LSRLOOP ) ; NODE ( ASRLOOP ) ; NODE ( BRCOND ) ; NODE ( CMP ) ;


<s> MachineBasicBlock * <ISA_LIT>Z80TargetLowering :: insertMul ( MachineInstr & MI , MachineBasicBlock * BB ) const {


<s> } if ( ! AM . BaseGV && AM . HasBaseReg && AM . Scale == <NUM_LIT> && Offs == <NUM_LIT> ) { return true ; } if ( ! AM . BaseGV && ! AM . HasBaseReg && AM . Scale == <NUM_LIT> && Offs == <NUM_LIT> ) { return true ;


<s> bool <ISA_LIT>Z80TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const { return true ;


<s> bool <ISA_LIT>Z80TargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> bool isSelectSupported ( SelectSupportKind ) const override {


<s> bool isSelectSupported ( SelectSupportKind ) const override { return false ;


<s> auto DL = DAG . getDataLayout ( ) ; const BlockAddress * BA = cast < BlockAddressSDNode > ( Op ) -> getBlockAddress ( ) ; SDValue Result = DAG . getTargetBlockAddress ( BA , getPointerTy ( DL ) ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getPointerTy ( DL ) , Result ) ;


<s> SDValue TargetCC ; SDValue Cmp ; if ( LHS . getValueType ( ) == <STR_LIT> ) { Cmp = geti8CC ( LHS , RHS , CC , TargetCC , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Dest , TargetCC , Cmp ) ; } else { assert ( LHS . getValueType ( ) == <STR_LIT> ) ;

TargetCC = DAG . getConstant ( CC , dl , <STR_LIT> ) ;


<s> } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; }


<s> std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ; } for ( CCValAssign const & RVLoc : RVLocs ) { Chain = DAG . getCopyFromReg ( Chain , dl , RVLoc . getLocReg ( ) , RVLoc . getValVT ( ) , InFlag ) . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; InVals . push_back ( Chain . getValue ( <NUM_LIT> ) ) ; }


<s> TargetLowering :: ArgListTy Args ; TargetLowering :: ArgListEntry Entry ; for ( SDValue const & Value : Op -> op_values ( ) ) { Entry . Node = Value ; Entry . Ty = Value . getValueType ( ) . getTypeForEVT ( * DAG . getContext ( ) ) ; Entry . IsSExt = IsSigned ; Entry . IsZExt = ! IsSigned ; Args . push_back ( Entry ) ; } SDValue Callee = DAG . getExternalSymbol ( getLibcallName ( LC ) , getPointerTy ( DAG . getDataLayout ( ) ) ) ; Type * RetTy = ( Type * ) StructType :: get ( Ty , Ty ) ; SDLoc dl ( Op ) ; TargetLowering :: CallLoweringInfo CLI ( DAG ) ; CLI . setDebugLoc ( dl ) . setChain ( InChain ) . setLibCallee ( getLibcallCallingConv ( LC ) , RetTy , Callee , std :: move ( Args ) ) . setInRegister ( ) . setSExtResult ( IsSigned ) . setZExtResult ( ! IsSigned ) ; std :: pair < SDValue , SDValue > CallInfo = LowerCallTo ( CLI ) ; return CallInfo . first ;


<s> RC = & <STR_LIT> ; } else if ( RegVT == <STR_LIT> ) { RC = & <STR_LIT> ; } else { llvm_unreachable ( <STR_LIT> ) ; } unsigned Reg = MF . addLiveIn ( VA . getLocReg ( ) , RC ) ; ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT LocVT = VA . getLocVT ( ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DL ) ) ; InVals . push_back ( DAG . getLoad ( LocVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) , <NUM_LIT> ) ) ; }


<s> ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: SExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; case CCValAssign :: ZExt : ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; break ; } InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) ) ; EVT LocVT = VA . getLocVT ( ) ; int FI = MFI . CreateFixedObject ( LocVT . getSizeInBits ( ) / <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , getPointerTy ( DL ) ) ; InVals . push_back ( DAG . getLoad ( LocVT , dl , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) , <NUM_LIT> ) ) ; } } if ( isVarArg ) { unsigned StackSize = CCInfo . getNextStackOffset ( ) ;

<ISA_LIT>Z80MachineFunctionInfo * AFI = MF . getInfo < <ISA_LIT>Z80MachineFunctionInfo > ( ) ;


<s> auto DL = DAG . getDataLayout ( ) ; int FI = cast < FrameIndexSDNode > ( Op ) -> getIndex ( ) ; SDValue Result = DAG . getTargetFrameIndex ( FI , <STR_LIT> ) ; SDValue Offset = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getPointerTy ( DL ) , Result , Offset ) ;


<s> SDValue Offset = DAG . getTargetConstant ( <NUM_LIT> , SDLoc ( Op ) , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getPointerTy ( DL ) , Result , Offset ) ;


<s> SDValue Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , getPointerTy ( DL ) , Offset ) ; return DAG . getNode ( <STR_LIT> , SDLoc ( Op ) , getPointerTy ( DL ) , Result ) ;


<s> const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; int64_t Offset = cast < GlobalAddressSDNode > ( Op ) -> getOffset ( ) ;

SDValue Result = DAG . getTargetGlobalAddress ( GV , SDLoc ( Op ) , getPointerTy ( DL ) , Offset ) ;


<s> for ( SDNode * Use : Ptr -> uses ( ) ) if ( Use -> getOpcode ( ) == <STR_LIT> && ! Use -> isPredecessorOf ( Op . getNode ( ) ) ) if ( ConstantSDNode * RHS = dyn_cast < ConstantSDNode > ( Use -> getOperand ( <NUM_LIT> ) ) ) if ( RHS -> getZExtValue ( ) == <NUM_LIT> ) { Add = Use ; break ; } if ( ! Add ) Add = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Ptr , DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ) . getNode ( ) ; SDValue Load2 = DAG . getLoad ( <STR_LIT> , dl , SDValue ( Load1 . getNode ( ) , <NUM_LIT> ) , SDValue ( Add , <NUM_LIT> ) , MMO ) ; return DAG . getMergeValues ( { getPair ( Load1 , Load2 , DAG ) , SDValue ( Load2 . getNode ( ) , <NUM_LIT> ) } , dl ) ;


<s> case <STR_LIT> : return LowerShifts ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> :


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return LowerShifts ( Op , DAG ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerFrameIndex ( Op , DAG ) ; case <STR_LIT> : return LowerBR_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSELECT_CC ( Op , DAG ) ; case <STR_LIT> : return LowerSETCC ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : case <STR_LIT> : return LowerDivRem ( Op , DAG ) ;


<s> SDValue <ISA_LIT>Z80TargetLowering :: LowerReturn ( SDValue Chain , CallingConv :: ID CallConv , bool isVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , const SmallVectorImpl < SDValue > & OutVals , const SDLoc & dl , SelectionDAG & DAG ) const { SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState CCInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , RVLocs , * DAG . getContext ( ) ) ; auto CCFunction = CCAssignFnForReturn ( CallConv ) ; CCInfo . AnalyzeReturn ( Outs , CCFunction ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; unsigned e = RVLocs . size ( ) ; if ( e > <NUM_LIT> ) { std :: reverse ( RVLocs . begin ( ) , RVLocs . end ( ) ) ; } SDValue Flag ; SmallVector < SDValue , <NUM_LIT> > RetOps ( <NUM_LIT> , Chain ) ; for ( unsigned i = <NUM_LIT> ; i != e ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , OutVals [ i ] , Flag ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; }

if ( MF . getFunction ( ) . getAttributes ( ) . hasAttribute ( AttributeList :: FunctionIndex , Attribute :: Naked ) ) {


<s> SDValue Cmp ; if ( LHS . getValueType ( ) == <STR_LIT> ) { Cmp = geti8CC ( LHS , RHS , CC , TargetCC , DAG , dl ) ; return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , TrueV , FalseV , TargetCC , Cmp ) ; }

assert ( LHS . getValueType ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> SDValue Cmp = geti8CC ( LHS , RHS , CC , TargetCC , DAG , dl ) ; SDValue Ops [ ] = { TrueV , FalseV , TargetCC , Cmp } ; return DAG . getNode ( <STR_LIT> , dl , Op . getValueType ( ) , Ops ) ; } assert ( LHS . getValueType ( ) == <STR_LIT> ) ;

SDValue Ops [ ] = { TrueV , FalseV , TargetCC , LHS , RHS } ;


<s> unsigned Opc8 ; const SDNode * N = Op . getNode ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( N ) ; if ( ! isa < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) { switch ( Op . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ; case <STR_LIT> : return DAG . getNode ( <STR_LIT> , dl , VT , N -> getOperand ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) ) ;


<s> while ( ( i != e ) && ( In [ i ] . PartOffset == Offset ) ) {

Offset += In [ i ] . VT . getStoreSize ( ) ;


<s> unsigned Bytes = ( TD -> getTypeSizeInBits ( Arg . getType ( ) ) + <NUM_LIT> ) / <NUM_LIT> ; Out . push_back ( ( Bytes + <NUM_LIT> ) / <NUM_LIT> ) ; }


<s> static SDValue PerformADDCombine ( SDNode * N , DAGCombinerInfo & DCI ) { EVT VT = N -> getValueType ( <NUM_LIT> ) ; SDLoc dl ( N ) ;

if ( VT == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) -> hasOneUse ( ) ) if ( auto * C0 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) return DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) , DCI . DAG . getTargetConstant ( * C0 -> getConstantIntValue ( ) , dl , <STR_LIT> ) ) ;


<s> if ( VT == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) -> getOpcode ( ) == <STR_LIT> && N -> getOperand ( <NUM_LIT> ) -> hasOneUse ( ) ) if ( auto * C0 = dyn_cast < ConstantSDNode > ( N -> getOperand ( <NUM_LIT> ) ) ) return DCI . DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , N -> getOperand ( <NUM_LIT> ) -> getOperand ( <NUM_LIT> ) , DCI . DAG . getTargetConstant ( * C0 -> getConstantIntValue ( ) , dl , <STR_LIT> ) ) ; return SDValue ( ) ;


<s> switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : return PerformADDCombine ( N , DCI ) ; } return SDValue ( ) ;


<s> break ; } default : { SDValue Res = LowerOperation ( SDValue ( N , <NUM_LIT> ) , DAG ) ; for ( unsigned I = <NUM_LIT> , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; break ; }


<s> SDValue Sub = DAG . getNode ( <STR_LIT> , DL , N -> getValueType ( <NUM_LIT> ) , N -> getOperand ( <NUM_LIT> ) , DAG . getConstant ( - C -> getAPIntValue ( ) , DL , C -> getValueType ( <NUM_LIT> ) ) ) ; Results . push_back ( Sub ) ; } break ; } default : { SDValue Res = LowerOperation ( SDValue ( N , <NUM_LIT> ) , DAG ) ; for ( unsigned I = <NUM_LIT> , E = Res -> getNumValues ( ) ; I != E ; ++ I ) Results . push_back ( Res . getValue ( I ) ) ; break ; }


<s> explicit <ISA_LIT>Z80MachineFunctionInfo ( MachineFunction & MF ) : needFP ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) {


<s> void setCalleeSavedFrameSize ( unsigned bytes ) { CalleeSavedFrameSize = bytes ;


<s> void <ISA_LIT>Z80MachineFunctionInfo :: anchor ( ) {


<s> explicit <ISA_LIT>Z80MachineFunctionInfo ( MachineFunction & MF ) : HasSpills ( false ) , HasAllocas ( false ) , HasStackArgs ( false ) , CalleeSavedFrameSize ( <NUM_LIT> ) , VarArgsFrameIndex ( <NUM_LIT> ) {


<s> unsigned getCalleeSavedFrameSize ( ) const {


<s> int getVarArgsFrameIndex ( ) const {


<s> void setCalleeSavedFrameSize ( unsigned Bytes ) {


<s> void setHasStackArgs ( bool B ) { HasStackArgs = B ;


<s> CommentString = <STR_LIT> ; PrivateGlobalPrefix = <STR_LIT> ; PrivateLabelPrefix = <STR_LIT> ; HexadecimalPrefix = <STR_LIT> ; UseIntegratedAssembler = false ; AsciiDirective = nullptr ; AscizDirective = nullptr ; MaxInstLength = <NUM_LIT> ; ZeroDirective = nullptr ; Data8bitsDirective = <STR_LIT> ; Data16bitsDirective = <STR_LIT> ; Data32bitsDirective = <STR_LIT> ; GlobalDirective = <STR_LIT> ; HasDotTypeDotSizeDirective = false ; HasSingleParameterDotFile = false ;


<s> MCCodeEmitter * create<ISA_LIT>Z80MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>Z80MCCodeEmitter ( MCII , Ctx ) ;


<s> MCCodeEmitter * create<ISA_LIT>Z80MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) {

return new <ISA_LIT>Z80MCCodeEmitter ( MCII , Ctx ) ;


<s> uint16_t Word = Words [ i ] ; OS << ( uint8_t ) ( ( Word & <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> size_t WordCount = Size / <NUM_LIT> ; for ( int64_t i = WordCount - <NUM_LIT> ; i >= <NUM_LIT> ; -- i ) { uint16_t Word = Words [ i ] ; OS << ( uint8_t ) ( ( Word & <NUM_LIT> ) >> <NUM_LIT> ) ; OS << ( uint8_t ) ( ( Word & <NUM_LIT> ) >> <NUM_LIT> ) ;


<s> assert ( Size > <NUM_LIT> && <STR_LIT> ) ; uint64_t BinaryOpCode = getBinaryCodeForInstr ( MI , Fixups , STI ) ; emitInstruction ( BinaryOpCode , Size , STI , OS ) ;


<s> <ISA_LIT>Z80MCCodeEmitter ( const MCInstrInfo & MCII , MCContext & Ctx ) : MCII ( MCII ) , Ctx ( Ctx ) {


<s> int64_t Result ; if ( <ISA_LIT>Z80Expr -> evaluateAsConstant ( Result ) ) { return Result ; } MCFixupKind FixupKind = static_cast < MCFixupKind > ( <ISA_LIT>Z80Expr -> getFixupKind ( ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , <ISA_LIT>Z80Expr , FixupKind ) ) ;


<s> unsigned <ISA_LIT>Z80MCCodeEmitter :: getExprOpValue ( const MCExpr * Expr , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { MCExpr :: ExprKind Kind = Expr -> getKind ( ) ; if ( Kind == MCExpr :: Binary ) { Expr = static_cast < const MCBinaryExpr * > ( Expr ) -> getLHS ( ) ; Kind = Expr -> getKind ( ) ; } if ( Kind == MCExpr :: Target ) { <ISA_LIT>Z80MCExpr const * <ISA_LIT>Z80Expr = cast < <ISA_LIT>Z80MCExpr > ( Expr ) ; int64_t Result ;

if ( <ISA_LIT>Z80Expr -> evaluateAsConstant ( Result ) ) {


<s> if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; if ( MO . isFPImm ( ) ) return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; assert ( MO . isExpr ( ) ) ;

return getExprOpValue ( MO . getExpr ( ) , Fixups , STI ) ;


<s> if ( MO . isFPImm ( ) ) return static_cast < unsigned > ( APFloat ( MO . getFPImm ( ) ) . bitcastToAPInt ( ) . getHiBits ( <NUM_LIT> ) . getLimitedValue ( ) ) ; assert ( MO . isExpr ( ) ) ;


<s> return E -> getKind ( ) == MCExpr :: Target ;


<s> const <ISA_LIT>Z80MCExpr * <ISA_LIT>Z80MCExpr :: create ( VariantKind Kind , const MCExpr * Expr , bool Negated , MCContext & Ctx ) {

return new ( Ctx ) <ISA_LIT>Z80MCExpr ( Kind , Expr , Negated ) ;


<s> return new ( Ctx ) <ISA_LIT>Z80MCExpr ( Kind , Expr , Negated ) ;


Result = evaluateAsInt64 ( Value . getConstant ( ) ) ;


<s> MCValue Value ; bool isRelocatable = getSubExpr ( ) -> evaluateAsRelocatable ( Value , nullptr , nullptr ) ; if ( ! isRelocatable ) return false ;


<s> case <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_HHI8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_PM_LO8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_PM_HI8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_PM_HH8 : Value >>= <NUM_LIT> ; break ; case <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_None :


<s> MCValue Value ; bool isRelocatable = SubExpr -> evaluateAsRelocatable ( Value , Layout , Fixup ) ; if ( ! isRelocatable ) return false ; if ( Value . isAbsolute ( ) ) { Result = MCValue :: get ( evaluateAsInt64 ( Value . getConstant ( ) ) ) ; } else { if ( ! Layout ) return false ; MCContext & Context = Layout -> getAssembler ( ) . getContext ( ) ; const MCSymbolRefExpr * Sym = Value . getSymA ( ) ; MCSymbolRefExpr :: VariantKind Modifier = Sym -> getKind ( ) ; if ( Modifier != MCSymbolRefExpr :: VK_None ) return false ; Sym = MCSymbolRefExpr :: create ( & Sym -> getSymbol ( ) , Modifier , Context ) ; Result = MCValue :: get ( Sym , Value . getSymB ( ) , Value . getConstant ( ) ) ; } return true ;


<s> MCFragment * findAssociatedFragment ( ) const override {

return getSubExpr ( ) -> findAssociatedFragment ( ) ;


<s> void fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const override {


<s> explicit <ISA_LIT>Z80MCExpr ( VariantKind Kind , const MCExpr * Expr , bool Negated ) : Kind ( Kind ) , SubExpr ( Expr ) , Negated ( Negated ) {


<s> <STR_LIT> <ISA_LIT>Z80MCExpr :: getFixupKind ( ) const { <STR_LIT> Kind = <STR_LIT> :: LastTargetFixupKind ; switch ( getKind ( ) ) { case VK_<ISA_LIT>Z80_LO8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>Z80_HI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>Z80_HH8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>Z80_HHI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>Z80_PM_LO8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>Z80_PM_HI8 : Kind = isNegated ( ) ? <STR_LIT> : <STR_LIT> ; break ; case VK_<ISA_LIT>Z80_PM_HH8 :


<s> const auto & Modifier = std :: find_if ( std :: begin ( ModifierNames ) , std :: end ( ModifierNames ) , [ this ] ( ModifierEntry const & Mod ) { return Mod . VariantKind == Kind ; } ) ;

if ( Modifier != std :: end ( ModifierNames ) ) {


<s> assert ( Kind != VK_<ISA_LIT>Z80_None ) ; if ( isNegated ( ) ) OS << '-' ; OS << getName ( ) << '(' ; getSubExpr ( ) -> print ( OS , MAI ) ;


<s> void <ISA_LIT>Z80MCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const {

Streamer . visitUsedExpr ( * getSubExpr ( ) ) ;


<s> <ISA_LIT>Z80MCInstLower ( MCContext & Ctx , AsmPrinter & Printer ) : Ctx ( Ctx ) , Printer ( Printer ) {


<s> MCOp = lowerSymbolOperand ( MO , Printer . getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_RegisterMask : continue ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ; break ; case MachineOperand :: MO_JumpTableIndex : MCOp = lowerSymbolOperand ( MO , Printer . GetJTISymbol ( MO . getIndex ( ) ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex :

MCOp = lowerSymbolOperand ( MO , Printer . GetCPISymbol ( MO . getIndex ( ) ) ) ;


<s> bool IsFunction = MO . isGlobal ( ) && isa < Function > ( MO . getGlobal ( ) ) ; if ( TF & <STR_LIT> ) { if ( IsFunction ) { Expr = <ISA_LIT>Z80MCExpr :: create ( <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_PM_LO8 , Expr , IsNegated , Ctx ) ; } else { Expr = <ISA_LIT>Z80MCExpr :: create ( <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_LO8 , Expr , IsNegated , Ctx ) ; } } else if ( TF & <STR_LIT> ) { if ( IsFunction ) { Expr = <ISA_LIT>Z80MCExpr :: create ( <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_PM_HI8 , Expr , IsNegated , Ctx ) ; } else { Expr = <ISA_LIT>Z80MCExpr :: create ( <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_HI8 , Expr , IsNegated , Ctx ) ; } } else if ( TF != <NUM_LIT> ) {


<s> if ( TF & <STR_LIT> ) { if ( IsFunction ) { Expr = <ISA_LIT>Z80MCExpr :: create ( <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_PM_LO8 , Expr , IsNegated , Ctx ) ; } else { Expr = <ISA_LIT>Z80MCExpr :: create ( <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_LO8 , Expr , IsNegated , Ctx ) ; } } else if ( TF & <STR_LIT> ) { if ( IsFunction ) { Expr = <ISA_LIT>Z80MCExpr :: create ( <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_PM_HI8 , Expr , IsNegated , Ctx ) ; } else { Expr = <ISA_LIT>Z80MCExpr :: create ( <ISA_LIT>Z80MCExpr :: VK_<ISA_LIT>Z80_HI8 , Expr , IsNegated , Ctx ) ; } } else if ( TF != <NUM_LIT> ) { llvm_unreachable ( <STR_LIT> ) ; } return MCOperand :: createExpr ( Expr ) ;


<s> void LLVMInitialize<ISA_LIT>Z80TargetMC ( ) {


<s> static MCInstPrinter * create<ISA_LIT>Z80MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { if ( SyntaxVariant == <NUM_LIT> ) { return new <ISA_LIT>Z80InstPrinter ( MAI , MII , MRI ) ; } return nullptr ;


<s> MCInstrInfo * X = new MCInstrInfo ( ) ; Init<ISA_LIT>Z80MCInstrInfo ( X ) ; return X ;


<s> Init<ISA_LIT>Z80MCRegisterInfo ( X , <NUM_LIT> ) ;


<s> static MCSubtargetInfo * create<ISA_LIT>Z80MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { return create<ISA_LIT>Z80MCSubtargetInfoImpl ( TT , CPU , FS ) ;


<s> static MCTargetStreamer * createMCAsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrint , bool isVerboseAsm ) {

return new <ISA_LIT>Z80TargetAsmStreamer ( S ) ;


<s> static MCStreamer * createMCStreamer ( const Triple & T , MCContext & Context , MCAsmBackend & MAB , raw_pwrite_stream & OS , MCCodeEmitter * Emitter , bool RelaxAll ) { return nullptr ;


<s> TargetRegistry :: RegisterMCInstPrinter ( getThe<ISA_LIT>Z80Target ( ) , create<ISA_LIT>Z80MCInstPrinter ) ; TargetRegistry :: RegisterMCCodeEmitter ( getThe<ISA_LIT>Z80Target ( ) , create<ISA_LIT>Z80MCCodeEmitter ) ;

TargetRegistry :: RegisterAsmTargetStreamer ( getThe<ISA_LIT>Z80Target ( ) , createMCAsmTargetStreamer ) ;


<s> this -> CC = CC ; this -> True = T ; this -> False = F ; initialize ( LHS , RHS ) ;


<s> if ( ! isLHSReg ( ) && isRHSReg ( ) ) {


<s> return new <ISA_LIT>Z80PostISel ( ) ;


<s> case <STR_LIT> : return expandSimple16 ( MI , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return expandSimple16 ( MI , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return expandSimple16 ( MI , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return expandSimple16 ( MI , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return expandSimple16 ( MI , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return expandSimple16 ( MI , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return expandSimple16 ( MI , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return expandSimple16 ( MI , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return expandShift16 ( MI , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ; case <STR_LIT> : return expandShift16 ( MI , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> if ( New ) { MII -> eraseFromParent ( ) ; MII = New -> getIterator ( ) ; Modified = true ; } ++ MII ; } } return Modified ;


<s> MachineInstr * Prev = MI . getPrevNode ( ) ; MachineBasicBlock * MBB = MI . getParent ( ) ; const BasicBlock * LLVM_BB = MBB -> getBasicBlock ( ) ; MachineBasicBlock * trueMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; MachineBasicBlock * falseMBB = MF -> CreateMachineBasicBlock ( LLVM_BB ) ; if ( auto * Fallthrough = MBB -> getFallThrough ( ) ) { BuildMI ( MBB , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( Fallthrough ) ; } MachineFunction :: iterator I ; for ( I = MF -> begin ( ) ; I != MF -> end ( ) && & ( * I ) != MBB ; ++ I ) ; if ( I != MF -> end ( ) ) ++ I ; MF -> insert ( I , trueMBB ) ; MF -> insert ( I , falseMBB ) ; trueMBB -> splice ( trueMBB -> begin ( ) , MBB , std :: next ( MachineBasicBlock :: iterator ( MI ) ) , MBB -> end ( ) ) ; trueMBB -> transferSuccessorsAndUpdatePHIs ( MBB ) ; if ( Opc == <STR_LIT> || Opc == <STR_LIT> ) { <STR_LIT> CC = ( <STR_LIT> ) MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; BuildMI ( MBB , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( trueMBB ) . addImm ( CC ) ; } else { <STR_LIT> CC = ( <STR_LIT> ) MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; unsigned LReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned LSub = MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ; unsigned RReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; unsigned RSub = MI . getOperand ( <NUM_LIT> ) . getSubReg ( ) ; BuildMI ( MBB , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( trueMBB ) . addImm ( CC ) . addReg ( LReg , <NUM_LIT> , LSub ) . addReg ( RReg , <NUM_LIT> , RSub ) ; } BuildMI ( MBB , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( falseMBB ) ; MBB -> addSuccessor ( falseMBB ) ; MBB -> addSuccessor ( trueMBB ) ; BuildMI ( falseMBB , dl , TII -> get ( <STR_LIT> ) ) . addMBB ( trueMBB ) ; falseMBB -> addSuccessor ( trueMBB ) ;

BuildMI ( * trueMBB , trueMBB -> begin ( ) , dl , TII -> get ( <STR_LIT> ) , MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( MBB ) . addReg ( MI . getOperand ( <NUM_LIT> ) . getReg ( ) ) . addMBB ( falseMBB ) ;


<s> unsigned SubSrc2 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( <STR_LIT> ) , SubSrc2 ) . addReg ( Src16 , <NUM_LIT> , Subreg2 ) ; unsigned Res1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto & LoOp = BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( Opc1 ) , Res1 ) . addReg ( SubSrc1 ) ; unsigned Res2 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto & HiOp = BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( Opc2 ) , Res2 ) . addReg ( SubSrc2 ) ; unsigned Res16_0 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( <STR_LIT> ) , Res16_0 ) ; unsigned Res16_1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( <STR_LIT> ) , Res16_1 ) . addReg ( Res16_0 ) . addReg ( Res1 ) . addImm ( Subreg1 ) ; MachineInstr * I = BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( <STR_LIT> ) , Dst16 ) . addReg ( Res16_1 ) . addReg ( Res2 ) . addImm ( Subreg2 ) ;


<s> RHSLo = MRI -> createVirtualRegister ( RHSClass ) ; BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( <STR_LIT> ) , RHSLo ) . addReg ( RHS16 , <NUM_LIT> , <STR_LIT> ) ; } unsigned ResLo = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto & LoOp = BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( LoOpc ) , ResLo ) . addReg ( LHSLo ) ; if ( RHSIsReg ) LoOp . addReg ( RHSLo ) ; else LoOp . addImm ( ImmLo ) ; unsigned LHSHi = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( <STR_LIT> ) , LHSHi ) . addReg ( LHS16 , <NUM_LIT> , <STR_LIT> ) ; unsigned RHSHi ; if ( RHSIsReg ) { RHSHi = MRI -> createVirtualRegister ( RHSClass ) ; BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( <STR_LIT> ) , RHSHi ) . addReg ( RHS16 , <NUM_LIT> , <STR_LIT> ) ; } unsigned ResHi = MRI -> createVirtualRegister ( & <STR_LIT> ) ; auto & HiOp = BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( HiOpc ) , ResHi ) . addReg ( LHSHi ) ; if ( RHSIsReg ) HiOp . addReg ( RHSHi ) ; else HiOp . addImm ( ImmHi ) ; unsigned Res16_0 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( <STR_LIT> ) , Res16_0 ) ; unsigned Res16_1 = MRI -> createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( <STR_LIT> ) , Res16_1 ) . addReg ( Res16_0 ) . addReg ( ResLo ) . addImm ( <STR_LIT> ) ; MachineInstr * I = BuildMI ( * MI . getParent ( ) , MI , dl , TII -> get ( <STR_LIT> ) , Dst16 ) . addReg ( Res16_1 ) . addReg ( ResHi ) . addImm ( <STR_LIT> ) ; return I ;


<s> initialize<ISA_LIT>Z80PostISelPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> StringRef getPassName ( ) const override { return PASS_NAME ;


<s> void initialize ( unsigned LHS , unsigned RHS ) { MachineRegisterInfo & MRI = True -> getParent ( ) -> getRegInfo ( ) ; LHSReg = LHS ; RHSReg = RHS ; if ( ! TargetRegisterInfo :: isPhysicalRegister ( LHS ) ) { MachineInstr * DefI = MRI . getVRegDef ( LHS ) ; if ( DefI -> getOpcode ( ) == <STR_LIT> ) { LHSReg = <NUM_LIT> ; LHSImm = DefI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; } } if ( ! TargetRegisterInfo :: isPhysicalRegister ( RHSReg ) ) { MachineInstr * DefI = MRI . getVRegDef ( RHSReg ) ; if ( DefI -> getOpcode ( ) == <STR_LIT> ) { RHSReg = <NUM_LIT> ; RHSImm = DefI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; } }


<s> bool Modified = false ; this -> MF = & MF ; const <ISA_LIT>Z80Subtarget & STI = MF . getSubtarget < <ISA_LIT>Z80Subtarget > ( ) ; TRI = STI . getRegisterInfo ( ) ; TII = STI . getInstrInfo ( ) ; MRI = & MF . getRegInfo ( ) ; Modified |= expandShiftLoop16 ( ) ; Modified |= expandPseudos ( ) ; Modified |= expandBranch16 ( ) ;


<s> if ( ! isFrameAccessInstr ( & * MII ) ) continue ; FrameAccessInfo FAI ; FAI . MI = & * MII ; FAI . StackAdjustment = Adj ; VNPair Before = getVNsBefore ( & * MII , <STR_LIT> ) ; VNPair After = getVNsAfter ( & * MII , <STR_LIT> ) ; FAI . MustSaveHL = ( ( Before . first == After . first ) || ( Before . second == After . second ) ) && ! ( Before . first == nullptr && Before . second == nullptr ) ; FAI . ChainedAccess = nullptr ; FAI . PreviousAccess = nullptr ;


<s> FunctionPass * create<ISA_LIT>Z80PostPEIPass ( ) { return new <ISA_LIT>Z80PostPEI ( ) ;


<s> return new <ISA_LIT>Z80PostPEI ( ) ;


<s> <ISA_LIT>Z80PostPEI ( ) : MachineFunctionPass ( ID ) {

initialize<ISA_LIT>Z80PreEmitPass ( * PassRegistry :: getPassRegistry ( ) ) ;


<s> } assert ( Adj != ~ <NUM_LIT> && <STR_LIT> ) ; for ( const auto Pred : BB -> predecessors ( ) ) {

if ( OutgoingAdjustments . count ( Pred ) ) assert ( OutgoingAdjustments [ Pred ] == Adj && <STR_LIT> ) ;


<s> void getAnalysisUsage ( AnalysisUsage & AU ) const override {

MachineFunctionPass :: getAnalysisUsage ( AU ) ;


<s> default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return & MI -> getOperand ( <NUM_LIT> ) ;


<s> case <STR_LIT> : return - ( int8_t ) MI -> getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return - <NUM_LIT> ; break ; case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> ) return <NUM_LIT> ; break ; case <STR_LIT> : { MachineInstr * Prev = MI -> getPrevNode ( ) ;

assert ( Prev -> getOpcode ( ) == <STR_LIT> && Prev -> getOperand ( <NUM_LIT> ) . getReg ( ) == <STR_LIT> && <STR_LIT> ) ;


<s> VNPair <ISA_LIT>Z80PostPEI :: getVNsAfter ( MachineInstr * MI , unsigned Reg ) { VNPair P = { nullptr , nullptr } ; bool FirstSet = false ; SlotIndex Idx = LI -> getInstructionIndex ( * MI ) ; for ( MCRegUnitIterator Units ( Reg , TRI ) ; Units . isValid ( ) ; ++ Units ) { LiveRange & LR = LI -> getRegUnit ( * Units ) ; VNInfo * VN = LR . getVNInfoAt ( Idx ) ; if ( ! FirstSet ) { P . first = VN ;


<s> bool FirstSet = false ; SlotIndex Idx = LI -> getInstructionIndex ( * MI ) ; for ( MCRegUnitIterator Units ( Reg , TRI ) ; Units . isValid ( ) ; ++ Units ) { LiveRange & LR = LI -> getRegUnit ( * Units ) ;

VNInfo * VN = LR . getVNInfoAt ( Idx ) ;


<s> SlotIndex Idx = LI -> getInstructionIndex ( * MI ) ; for ( MCRegUnitIterator Units ( Reg , TRI ) ; Units . isValid ( ) ; ++ Units ) { LiveRange & LR = LI -> getRegUnit ( * Units ) ; VNInfo * VN = LR . getVNInfoBefore ( Idx ) ; if ( ! FirstSet ) {


<s> for ( MCRegUnitIterator Units ( Reg , TRI ) ; Units . isValid ( ) ; ++ Units ) { LiveRange & LR = LI -> getRegUnit ( * Units ) ; VNInfo * VN = LR . getVNInfoBefore ( Idx ) ; if ( ! FirstSet ) { P . first = VN ; FirstSet = true ; } else P . second = VN ;


<s> static bool isFrameAccessInstr ( MachineInstr * MI ) { switch ( MI -> getOpcode ( ) ) { default : break ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return true ; }


<s> RS = new RegScavenger ( ) ; Accesses . clear ( ) ; OutgoingAdjustments . clear ( ) ; CollectFrameAccesses ( ) ; for ( auto & A : Accesses ) { A . MI -> dump ( ) ; errs ( ) << <STR_LIT> << A . StackAdjustment << <STR_LIT> ; errs ( ) << <STR_LIT> << A . MustSaveHL << <STR_LIT> ; } TransformFrameAccesses ( ) ; delete RS ; return ! Accesses . empty ( ) ;


<s> OutgoingAdjustments . clear ( ) ; CollectFrameAccesses ( ) ; for ( auto & A : Accesses ) { A . MI -> dump ( ) ; errs ( ) << <STR_LIT> << A . StackAdjustment << <STR_LIT> ;

errs ( ) << <STR_LIT> << A . MustSaveHL << <STR_LIT> ;


<s> BuildMI ( BB , * FAI . MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( Offset ) ; } else { BuildMI ( BB , * FAI . MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addImm ( ( int16_t ) Offset ) ; BuildMI ( BB , * FAI . MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) . addReg ( <STR_LIT> ) ; } switch ( Opcode ) { case <STR_LIT> : if ( ValueReg != <STR_LIT> ) { unsigned Lo , Hi ; TRI -> splitReg ( ValueReg , Lo , Hi ) ; BuildMI ( BB , * FAI . MI , dl , TII -> get ( <STR_LIT> ) , Lo ) . addReg ( <STR_LIT> ) ; BuildMI ( BB , * FAI . MI , dl , TII -> get ( <STR_LIT> ) , Hi ) . addReg ( <STR_LIT> ) ; } break ; case <STR_LIT> : BuildMI ( BB , * FAI . MI , dl , TII -> get ( <STR_LIT> ) , ValueReg ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : BuildMI ( BB , * FAI . MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( ValueReg ) . addReg ( <STR_LIT> ) ; break ;


<s> switch ( Opcode ) { case <STR_LIT> : if ( ValueReg != <STR_LIT> ) { unsigned Lo , Hi ; TRI -> splitReg ( ValueReg , Lo , Hi ) ; BuildMI ( BB , * FAI . MI , dl , TII -> get ( <STR_LIT> ) , Lo ) . addReg ( <STR_LIT> ) ; BuildMI ( BB , * FAI . MI , dl , TII -> get ( <STR_LIT> ) , Hi ) . addReg ( <STR_LIT> ) ; } break ; case <STR_LIT> : BuildMI ( BB , * FAI . MI , dl , TII -> get ( <STR_LIT> ) , ValueReg ) . addReg ( <STR_LIT> ) ; break ; case <STR_LIT> : BuildMI ( BB , * FAI . MI , dl , TII -> get ( <STR_LIT> ) ) . addReg ( ValueReg ) . addReg ( <STR_LIT> ) ; break ; } if ( SaveHL && ! FAI . ChainedAccess ) { BuildMI ( BB , * FAI . MI , dl , TII -> get ( <STR_LIT> ) , <STR_LIT> ) ; }


<s> unsigned RHSReg = RHSIsReg ? MI . getOperand ( <NUM_LIT> ) . getReg ( ) : <NUM_LIT> ; bool RHSIsKill = RHSIsReg ? MI . getOperand ( <NUM_LIT> ) . isKill ( ) : false ; int8_t RHSImm = ! RHSIsReg ? MI . getOperand ( <NUM_LIT> ) . getImm ( ) : <NUM_LIT> ; assert ( RHSReg != <STR_LIT> ) ; BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( DstReg ) ; auto & B = BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( NewOpc ) ) . addReg ( <STR_LIT> , RegState :: Define | getDeadRegState ( DstIsDead ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ;

if ( RHSIsReg ) B . addReg ( RHSReg , getKillRegState ( RHSIsKill ) ) ;


<s> MachineOperand & Addr = MI . getOperand ( <NUM_LIT> ) ; if ( isStore ) BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( ValueReg ) ; unsigned opcode = isStore ? <STR_LIT> : <STR_LIT> ; auto Builder = BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( opcode ) ) . addReg ( <STR_LIT> , getDefRegState ( ! isStore ) ) ; if ( Addr . isGlobal ( ) ) Builder . addGlobalAddress ( Addr . getGlobal ( ) , Addr . getOffset ( ) ) ; else if ( Addr . isImm ( ) ) Builder . addImm ( Addr . getImm ( ) ) ; Builder . cloneMemRefs ( MI ) ; MachineInstr * New = Builder ;

if ( ! isStore ) New = BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , ValueReg ) . addReg ( <STR_LIT> , getKillRegState ( true ) ) ;


<s> if ( isStore && OpValueReg != ValueReg ) BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , OpValueReg ) . addReg ( ValueReg ) ; auto Builder = BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( opcode ) ) ; if ( isPostOpc && ! isStore ) Builder . addReg ( OpValueReg , RegState :: Define ) . addReg ( PostPtrReg , RegState :: Define | getDeadRegState ( PostPtrDead ) ) ; else { if ( isPostOpc ) Builder . addReg ( PostPtrReg , RegState :: Define | getDeadRegState ( PostPtrDead ) ) ; Builder . addReg ( OpValueReg , getDefRegState ( ! isStore ) ) ; } Builder . addReg ( InPtrReg , getKillRegState ( InPtrKill && ! ( isPost && ! isPostOpc && ! PostPtrDead ) ) ) ; Builder . cloneMemRefs ( MI ) ; New = Builder ; if ( ! isStore && OpValueReg != ValueReg ) { BuildMI ( * MI . getParent ( ) , MI , DebugLoc ( ) , TII -> get ( <STR_LIT> ) , ValueReg ) . addReg ( OpValueReg , getKillRegState ( true ) ) ; } if ( isPost && ! isPostOpc && ! PostPtrDead ) {

opcode = isPostInc ? <STR_LIT> : <STR_LIT> ;