{"Template_token": ["<s>", "if", "(", "!", "FS", ".", "empty", "(", ")", ")", "{", "if", "(", "!", "ArchFS", ".", "empty", "(", ")", ")", "ArchFS", "=", "(", "Twine", "(", "ArchFS", ")", "+", "<STR_LIT>", "+", "FS", ")", ".", "str", "(", ")", ";"], "ground_truth": ["else", "ArchFS", "=", "FS", ";"], "File": "FPGAMCTargetDesc", "Func": "createFPGAMCSubtargetInfo", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139628, "Length": 41, "Cover_Rate": 0.4019607843137255}
{"Template_token": ["<s>", "if", "(", "!", "ArchFS", ".", "empty", "(", ")", ")", "ArchFS", "=", "(", "Twine", "(", "ArchFS", ")", "+", "<STR_LIT>", "+", "FS", ")", ".", "str", "(", ")", ";", "else", "ArchFS", "=", "FS", ";"], "ground_truth": ["}"], "File": "FPGAMCTargetDesc", "Func": "createFPGAMCSubtargetInfo", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139629, "Length": 32, "Cover_Rate": 0.3137254901960784}
{"Template_token": ["<s>", "void", "LLVMInitialize<ISA_LIT>TargetMC", "(", ")", "{"], "ground_truth": ["}"], "File": "FPGAMCTargetDesc", "Func": "LLVMInitializeFPGATargetMC", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139630, "Length": 6, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "void", "LLVMInitialize<ISA_LIT>TargetMC", "(", ")", "{"], "ground_truth": ["}"], "File": "FPGAMCTargetDesc", "Func": "LLVMInitializeFPGATargetMC", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139631, "Length": 6, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "std", "::", "string", "FS", ";", "return", "FS", ";"], "ground_truth": ["}"], "File": "FPGAMCTargetDesc", "Func": "ParseFPGATriple", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139632, "Length": 9, "Cover_Rate": 0.4090909090909091}
{"Template_token": ["<s>", "std", "::", "string", "<STR_LIT>", "(", "const", "Triple", "&", "TT", ")", "{", "std", "::", "string", "FS", ";", "return", "FS", ";"], "ground_truth": ["}"], "File": "FPGAMCTargetDesc", "Func": "ParseFPGATriple", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139633, "Length": 20, "Cover_Rate": 0.9090909090909091}
{"Template_token": ["<s>", "<ISA_LIT>Subtarget", "::", "<ISA_LIT>Subtarget", "(", "const", "Triple", "&", "TT", ",", "StringRef", "CPU", ",", "StringRef", "FS", ",", "const", "<ISA_LIT>TargetMachine", "&", "TM", ")", ":", "<ISA_LIT>GenSubtargetInfo", "(", "TT", ",", "CPU", ",", "FS", ")", ",", "<ISA_LIT>Family", "(", "UltraScale", ")", ",", "TM", "(", "TM", ")", ",", "TargetTriple", "(", "TT", ")", "{"], "ground_truth": ["}"], "File": "FPGASubtarget", "Func": "FPGASubtarget", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139634, "Length": 46, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "<ISA_LIT>Subtarget", "::", "<ISA_LIT>Subtarget", "(", "const", "Triple", "&", "TT", ",", "StringRef", "CPU", ",", "StringRef", "FS", ",", "const", "<ISA_LIT>TargetMachine", "&", "TM", ")", ":", "<ISA_LIT>GenSubtargetInfo", "(", "TT", ",", "CPU", ",", "FS", ")", ",", "<ISA_LIT>Family", "(", "UltraScale", ")", ",", "TM", "(", "TM", ")", ",", "TargetTriple", "(", "TT", ")", "{"], "ground_truth": ["}"], "File": "FPGASubtarget", "Func": "FPGASubtarget", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139635, "Length": 46, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "const", "Triple", "&", "getTargetTriple", "(", ")", "const", "{", "return", "TargetTriple", ";"], "ground_truth": ["}"], "File": "FPGASubtarget", "Func": "getTargetTriple", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139636, "Length": 12, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "return", "TargetTriple", ";"], "ground_truth": ["}"], "File": "FPGASubtarget", "Func": "getTargetTriple", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139637, "Length": 4, "Cover_Rate": 0.3333333333333333}
{"Template_token": ["<s>", "void", "<ISA_LIT>Subtarget", "::", "initializeEnvironment", "(", ")", "{"], "ground_truth": ["}"], "File": "FPGASubtarget", "Func": "initializeEnvironment", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139638, "Length": 8, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "void", "<ISA_LIT>Subtarget", "::", "initializeEnvironment", "(", ")", "{"], "ground_truth": ["}"], "File": "FPGASubtarget", "Func": "initializeEnvironment", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139639, "Length": 8, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "<ISA_LIT>Subtarget", "&", "<ISA_LIT>Subtarget", "::", "initializeSubtargetDependencies", "(", "StringRef", "CPU", ",", "StringRef", "FS", ")", "{", "initializeEnvironment", "(", ")", ";"], "ground_truth": ["initSubtargetFeatures", "(", "CPU", ",", "FS", ")", ";"], "File": "FPGASubtarget", "Func": "initializeSubtargetDependencies", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139640, "Length": 24, "Cover_Rate": 0.8275862068965517}
{"Template_token": ["<s>", "initSubtargetFeatures", "(", "CPU", ",", "FS", ")", ";"], "ground_truth": ["return", "*", "this", ";"], "File": "FPGASubtarget", "Func": "initializeSubtargetDependencies", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139641, "Length": 11, "Cover_Rate": 0.3793103448275862}
{"Template_token": ["<s>", "std", "::", "string", "<ISA_LIT>Name", "=", "CPU", ";", "if", "(", "<ISA_LIT>Name", ".", "empty", "(", ")", ")", "<ISA_LIT>Name", "=", "<STR_LIT>", ";"], "ground_truth": ["std", "::", "string", "FullFS", "=", "FS", ";"], "File": "FPGASubtarget", "Func": "initSubtargetFeatures", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139642, "Length": 26, "Cover_Rate": 0.5652173913043478}
{"Template_token": ["<s>", "void", "<ISA_LIT>Subtarget", "::", "initSubtargetFeatures", "(", "StringRef", "CPU", ",", "StringRef", "FS", ")", "{", "std", "::", "string", "<ISA_LIT>Name", "=", "CPU", ";", "if", "(", "<ISA_LIT>Name", ".", "empty", "(", ")", ")", "<ISA_LIT>Name", "=", "<STR_LIT>", ";", "std", "::", "string", "FullFS", "=", "FS", ";"], "ground_truth": ["ParseSubtargetFeatures", "(", "<ISA_LIT>Name", ",", "FullFS", ")", ";"], "File": "FPGASubtarget", "Func": "initSubtargetFeatures", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139643, "Length": 45, "Cover_Rate": 0.9782608695652174}
{"Template_token": ["<s>", "void", "LLVMInitialize<ISA_LIT>TargetInfo", "(", ")", "{", "RegisterTarget", "<", "Triple", "::", "fpga32", ",", "false", ">", "X", "(", "The<ISA_LIT>32Target", ",", "<STR_LIT>", ",", "<STR_LIT>", ",", "<STR_LIT>", ")", ";"], "ground_truth": ["RegisterTarget", "<", "Triple", "::", "fpga64", ",", "false", ">", "Y", "(", "The<ISA_LIT>64Target", ",", "<STR_LIT>", ",", "<STR_LIT>", ",", "<STR_LIT>", ")", ";"], "File": "FPGATargetInfo", "Func": "LLVMInitializeFPGATargetInfo", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139645, "Length": 43, "Cover_Rate": 0.9772727272727273}
{"Template_token": ["<s>", "if", "(", "TT", ".", "isArch32Bit", "(", ")", ")", "return", "<STR_LIT>", "<STR_LIT>", "<STR_LIT>", "<STR_LIT>", ";", "return", "<STR_LIT>", "<STR_LIT>", "<STR_LIT>", "<STR_LIT>", ";"], "ground_truth": ["}"], "File": "FPGATargetMachine", "Func": "computeDataLayout", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139647, "Length": 21, "Cover_Rate": 0.6363636363636364}
{"Template_token": ["<s>", "TargetPassConfig", "*", "<ISA_LIT>TargetMachine", "::", "createPassConfig", "(", "PassManagerBase", "&", "PM", ")", "{", "return", "new", "<ISA_LIT>PassConfig", "(", "*", "this", ",", "PM", ")", ";"], "ground_truth": ["}"], "File": "FPGATargetMachine", "Func": "createPassConfig", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139648, "Length": 22, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "return", "new", "<ISA_LIT>PassConfig", "(", "*", "this", ",", "PM", ")", ";"], "ground_truth": ["}"], "File": "FPGATargetMachine", "Func": "createPassConfig", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139649, "Length": 11, "Cover_Rate": 0.5}
{"Template_token": ["<s>", "<ISA_LIT>PassConfig", "(", "<ISA_LIT>TargetMachine", "&", "TM", ",", "PassManagerBase", "&", "PM", ")", ":", "TargetPassConfig", "(", "TM", ",", "PM", ")", "{"], "ground_truth": ["}"], "File": "FPGATargetMachine", "Func": "FPGAPassConfig", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139650, "Length": 19, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "<ISA_LIT>PassConfig", "(", "<ISA_LIT>TargetMachine", "&", "TM", ",", "PassManagerBase", "&", "PM", ")", ":", "TargetPassConfig", "(", "TM", ",", "PM", ")", "{"], "ground_truth": ["}"], "File": "FPGATargetMachine", "Func": "FPGAPassConfig", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139651, "Length": 19, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "<ISA_LIT>TargetMachine", "::", "<ISA_LIT>TargetMachine", "(", "const", "Target", "&", "T", ",", "const", "Triple", "&", "TT", ",", "StringRef", "CPU", ",", "StringRef", "FS", ",", "const", "TargetOptions", "&", "Options", ",", "Optional", "<", "Reloc", "::", "Model", ">", "RM", ",", "Optional", "<", "CodeModel", "::", "Model", ">", "CM", ",", "CodeGenOpt", "::", "Level", "OL", ",", "bool", "JIT", ")", ":", "LLVMTargetMachine", "(", "T", ",", "computeDataLayout", "(", "TT", ")", ",", "TT", ",", "CPU", ",", "FS", ",", "Options", ",", "getEffectiveRelocModel", "(", "TT", ",", "RM", ")", ",", "CodeModel", "::", "Large", ",", "OL", ")", ",", "Subtarget", "(", "TT", ",", "CPU", ",", "FS", ",", "*", "this", ")", "{"], "ground_truth": ["}"], "File": "FPGATargetMachine", "Func": "FPGATargetMachine", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139652, "Length": 94, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "<ISA_LIT>TargetMachine", "::", "<ISA_LIT>TargetMachine", "(", "const", "Target", "&", "T", ",", "const", "Triple", "&", "TT", ",", "StringRef", "CPU", ",", "StringRef", "FS", ",", "const", "TargetOptions", "&", "Options", ",", "Optional", "<", "Reloc", "::", "Model", ">", "RM", ",", "Optional", "<", "CodeModel", "::", "Model", ">", "CM", ",", "CodeGenOpt", "::", "Level", "OL", ",", "bool", "JIT", ")", ":", "LLVMTargetMachine", "(", "T", ",", "computeDataLayout", "(", "TT", ")", ",", "TT", ",", "CPU", ",", "FS", ",", "Options", ",", "getEffectiveRelocModel", "(", "TT", ",", "RM", ")", ",", "CodeModel", "::", "Large", ",", "OL", ")", ",", "Subtarget", "(", "TT", ",", "CPU", ",", "FS", ",", "*", "this", ")", "{"], "ground_truth": ["}"], "File": "FPGATargetMachine", "Func": "FPGATargetMachine", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139653, "Length": 94, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "return", "getTM", "<", "<ISA_LIT>TargetMachine", ">", "(", ")", ";"], "ground_truth": ["}"], "File": "FPGATargetMachine", "Func": "getFPGATargetMachine", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139656, "Length": 9, "Cover_Rate": 0.5625}
{"Template_token": ["<s>", "<ISA_LIT>TargetMachine", "&", "get<ISA_LIT>TargetMachine", "(", ")", "const", "{", "return", "getTM", "<", "<ISA_LIT>TargetMachine", ">", "(", ")", ";"], "ground_truth": ["}"], "File": "FPGATargetMachine", "Func": "getFPGATargetMachine", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139657, "Length": 16, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "StringRef", "<ISA_LIT>", "=", "!", "<ISA_LIT>Attr", ".", "hasAttribute", "(", "Attribute", "::", "None", ")", "?", "<ISA_LIT>Attr", ".", "getValueAsString", "(", ")", ":", "(", "StringRef", ")", "TargetCPU", ";", "StringRef", "FS", "=", "!", "FSAttr", ".", "hasAttribute", "(", "Attribute", "::", "None", ")", "?", "FSAttr", ".", "getValueAsString", "(", ")", ":", "(", "StringRef", ")", "TargetFS", ";", "SmallString", "<", "<NUM_LIT>", ">", "Key", ";", "Key", ".", "reserve", "(", "<ISA_LIT>", ".", "size", "(", ")", "+", "FS", ".", "size", "(", ")", ")", ";", "Key", "+=", "<ISA_LIT>", ";", "Key", "+=", "FS", ";", "auto", "&", "I", "=", "SubtargetMap", "[", "Key", "]", ";", "if", "(", "!", "I", ")", "{"], "ground_truth": ["resetTargetOptions", "(", "F", ")", ";"], "File": "FPGATargetMachine", "Func": "getSubtargetImpl", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139658, "Length": 99, "Cover_Rate": 0.6149068322981367}
{"Template_token": ["<s>", "SmallString", "<", "<NUM_LIT>", ">", "Key", ";", "Key", ".", "reserve", "(", "<ISA_LIT>", ".", "size", "(", ")", "+", "FS", ".", "size", "(", ")", ")", ";", "Key", "+=", "<ISA_LIT>", ";", "Key", "+=", "FS", ";", "auto", "&", "I", "=", "SubtargetMap", "[", "Key", "]", ";", "if", "(", "!", "I", ")", "{", "resetTargetOptions", "(", "F", ")", ";"], "ground_truth": ["I", "=", "llvm", "::", "make_unique", "<", "<ISA_LIT>Subtarget", ">", "(", "TargetTriple", ",", "<ISA_LIT>", ",", "FS", ",", "*", "this", ")", ";"], "File": "FPGATargetMachine", "Func": "getSubtargetImpl", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139659, "Length": 70, "Cover_Rate": 0.43478260869565216}
{"Template_token": ["<s>", "return", "TargetTransformInfo", "(", "<ISA_LIT>TTIImpl", "(", "this", ",", "F", ")", ")", ";"], "ground_truth": ["}"], "File": "FPGATargetMachine", "Func": "getTargetTransformInfo", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139661, "Length": 12, "Cover_Rate": 0.5217391304347826}
{"Template_token": ["<s>", "RegisterTargetMachine", "<", "<ISA_LIT>TargetMachine", ">", "X", "(", "The<ISA_LIT>32Target", ")", ";", "RegisterTargetMachine", "<", "<ISA_LIT>TargetMachine", ">", "Y", "(", "The<ISA_LIT>64Target", ")", ";", "PassRegistry", "&", "PR", "=", "*", "PassRegistry", "::", "getPassRegistry", "(", ")", ";"], "ground_truth": ["(", "void", ")", "PR", ";"], "File": "FPGATargetMachine", "Func": "LLVMInitializeFPGATarget", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139662, "Length": 34, "Cover_Rate": 0.85}
{"Template_token": ["<s>", "<ISA_LIT>TargetMachine", "::", "~", "<ISA_LIT>TargetMachine", "(", ")", "{"], "ground_truth": ["}"], "File": "FPGATargetMachine", "Func": "~FPGATargetMachine", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139663, "Length": 8, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "<ISA_LIT>TargetMachine", "::", "~", "<ISA_LIT>TargetMachine", "(", ")", "{"], "ground_truth": ["}"], "File": "FPGATargetMachine", "Func": "~FPGATargetMachine", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139664, "Length": 8, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "<ISA_LIT>TTIImpl", "(", "<ISA_LIT>TTIImpl", "&&", "Arg", ")", ":", "BaseT", "(", "std", "::", "move", "(", "static_cast", "<", "BaseT", "&", ">", "(", "Arg", ")", ")", ")", ",", "TM", "(", "std", "::", "move", "(", "Arg", ".", "TM", ")", ")", ",", "ST", "(", "std", "::", "move", "(", "Arg", ".", "ST", ")", ")", "{"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "FPGATTIImpl", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139665, "Length": 49, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "<ISA_LIT>TTIImpl", "(", "<ISA_LIT>TTIImpl", "&&", "Arg", ")", ":", "BaseT", "(", "std", "::", "move", "(", "static_cast", "<", "BaseT", "&", ">", "(", "Arg", ")", ")", ")", ",", "TM", "(", "std", "::", "move", "(", "Arg", ".", "TM", ")", ")", ",", "ST", "(", "std", "::", "move", "(", "Arg", ".", "ST", ")", ")", "{"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "FPGATTIImpl", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139666, "Length": 49, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "int", "<ISA_LIT>TTIImpl", "::", "getCallCost", "(", "const", "Function", "*", "F", ",", "ArrayRef", "<", "const", "Value", "*", ">", "Arguments", ")", "{", "return", "BaseT", "::", "getCallCost", "(", "F", ",", "Arguments", ")", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "getCallCost", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139668, "Length": 30, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "int", "<ISA_LIT>TTIImpl", "::", "getCastInstrCost", "(", "unsigned", "Opcode", ",", "Type", "*", "Dst", ",", "Type", "*", "Src", ",", "const", "Instruction", "*", "I", ")", "{"], "ground_truth": ["return", "TTI", "::", "TCC_Free", ";"], "File": "FPGATargetTransformInfo", "Func": "getCastInstrCost", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139669, "Length": 27, "Cover_Rate": 0.9642857142857143}
{"Template_token": ["<s>", "int", "<ISA_LIT>TTIImpl", "::", "getExtractWithExtendCost", "(", "unsigned", "Opcode", ",", "Type", "*", "Dst", ",", "VectorType", "*", "VecTy", ",", "unsigned", "Index", ")", "{"], "ground_truth": ["return", "TTI", "::", "TCC_Free", ";"], "File": "FPGATargetTransformInfo", "Func": "getExtractWithExtendCost", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139671, "Length": 25, "Cover_Rate": 0.9615384615384616}
{"Template_token": ["<s>", "int", "<ISA_LIT>TTIImpl", "::", "getExtractWithExtendCost", "(", "unsigned", "Opcode", ",", "Type", "*", "Dst", ",", "VectorType", "*", "VecTy", ",", "unsigned", "Index", ")", "{", "return", "TTI", "::", "TCC_Free", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "getExtractWithExtendCost", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139672, "Length": 26, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "return", "BaseT", "::", "getIntrinsicCost", "(", "IID", ",", "RetTy", ",", "Arguments", ")", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "getIntrinsicCost", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139673, "Length": 13, "Cover_Rate": 0.3611111111111111}
{"Template_token": ["<s>", "return", "BaseT", "::", "getIntrinsicCost", "(", "IID", ",", "RetTy", ",", "Arguments", ")", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "getIntrinsicCost", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139674, "Length": 13, "Cover_Rate": 0.3611111111111111}
{"Template_token": ["<s>", "uint64_t", "Min", "=", "MinAlign", "(", "SrcAlignInBytes", ",", "DestAlignInBytes", ")", ";", "KnownBits", "KB", "=", "computeKnownBits", "(", "LengthInBytes", ",", "getDataLayout", "(", ")", ")", ";"], "ground_truth": ["Min", "=", "MinAlign", "(", "Min", ",", "<NUM_LIT>", "<<", "KB", ".", "countMinTrailingZeros", "(", ")", ")", ";"], "File": "FPGATargetTransformInfo", "Func": "getMemcpyLoopLoweringType", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139676, "Length": 37, "Cover_Rate": 0.5138888888888888}
{"Template_token": ["<s>", "unsigned", "<ISA_LIT>TTIImpl", "::", "getNumberOfRegisters", "(", "bool", "Vector", ")", "{", "return", "std", "::", "numeric_limits", "<", "unsigned", ">", "::", "max", "(", ")", ">>", "<NUM_LIT>", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "getNumberOfRegisters", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139678, "Length": 24, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "return", "TTI", "::", "PSK_FastHardware", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "getPopcntSupport", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139679, "Length": 6, "Cover_Rate": 0.35294117647058826}
{"Template_token": ["<s>", "TargetTransformInfo", "::", "PopcntSupportKind", "<ISA_LIT>TTIImpl", "::", "getPopcntSupport", "(", "unsigned", "IntTyWidthInBit", ")", "{", "return", "TTI", "::", "PSK_FastHardware", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "getPopcntSupport", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139680, "Length": 17, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "return", "std", "::", "numeric_limits", "<", "unsigned", ">", "::", "max", "(", ")", ">>", "<NUM_LIT>", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "getRegisterBitWidth", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139681, "Length": 15, "Cover_Rate": 0.6}
{"Template_token": ["<s>", "return", "ST", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "getST", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139684, "Length": 4, "Cover_Rate": 0.3333333333333333}
{"Template_token": ["<s>", "const", "<ISA_LIT>TargetMachine", "*", "getTM", "(", ")", "const", "{"], "ground_truth": ["return", "TM", ";"], "File": "FPGATargetTransformInfo", "Func": "getTM", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139686, "Length": 11, "Cover_Rate": 0.9166666666666666}
{"Template_token": ["<s>", "const", "<ISA_LIT>TargetMachine", "*", "getTM", "(", ")", "const", "{", "return", "TM", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "getTM", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139687, "Length": 12, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "UP", ".", "MaxCount", "=", "<NUM_LIT>", ";", "UP", ".", "FullUnrollMaxCount", "=", "<NUM_LIT>", ";", "UP", ".", "Partial", "=", "false", ";", "UP", ".", "Runtime", "=", "false", ";"], "ground_truth": ["UP", ".", "AllowRemainder", "=", "false", ";"], "File": "FPGATargetTransformInfo", "Func": "getUnrollingPreferences", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139688, "Length": 30, "Cover_Rate": 0.43478260869565216}
{"Template_token": ["<s>", "void", "<ISA_LIT>TTIImpl", "::", "getUnrollingPreferences", "(", "Loop", "*", "L", ",", "ScalarEvolution", "&", "SE", ",", "TTI", "::", "UnrollingPreferences", "&", "UP", ")", "{", "UP", ".", "Threshold", "=", "<NUM_LIT>", ";", "UP", ".", "PartialThreshold", "=", "<NUM_LIT>", ";"], "ground_truth": ["UP", ".", "Count", "=", "<NUM_LIT>", ";"], "File": "FPGATargetTransformInfo", "Func": "getUnrollingPreferences", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139689, "Length": 38, "Cover_Rate": 0.5507246376811594}
{"Template_token": ["<s>", "int", "<ISA_LIT>TTIImpl", "::", "getUserCost", "(", "const", "User", "*", "U", ",", "ArrayRef", "<", "const", "Value", "*", ">", "Operands", ")", "{"], "ground_truth": ["if", "(", "IsFreeOperator", "(", "U", ")", ")", "return", "TTI", "::", "TCC_Free", ";"], "File": "FPGATargetTransformInfo", "Func": "getUserCost", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139690, "Length": 31, "Cover_Rate": 0.7380952380952381}
{"Template_token": ["<s>", "int", "<ISA_LIT>TTIImpl", "::", "getUserCost", "(", "const", "User", "*", "U", ",", "ArrayRef", "<", "const", "Value", "*", ">", "Operands", ")", "{", "if", "(", "IsFreeOperator", "(", "U", ")", ")", "return", "TTI", "::", "TCC_Free", ";"], "ground_truth": ["return", "BaseT", "::", "getUserCost", "(", "U", ",", "Operands", ")", ";"], "File": "FPGATargetTransformInfo", "Func": "getUserCost", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139691, "Length": 41, "Cover_Rate": 0.9761904761904762}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "hasBranchDivergence", "(", ")", "{"], "ground_truth": ["return", "true", ";"], "File": "FPGATargetTransformInfo", "Func": "hasBranchDivergence", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139693, "Length": 10, "Cover_Rate": 0.9090909090909091}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "hasBranchDivergence", "(", ")", "{", "return", "true", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "hasBranchDivergence", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139694, "Length": 11, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "switch", "(", "Opcode", ")", "{", "default", ":", "return", "Instruction", "::", "isShift", "(", "Opcode", ")", ";", "case", "Instruction", "::", "And", ":", "case", "Instruction", "::", "Or", ":", "case", "Instruction", "::", "Xor", ":", "case", "Instruction", "::", "ExtractElement", ":", "case", "Instruction", "::", "ExtractValue", ":", "case", "Instruction", "::", "InsertElement", ":", "case", "Instruction", "::", "InsertValue", ":", "return", "true", ";", "}"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "IsBitwiseBinaryOperator", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139695, "Length": 55, "Cover_Rate": 0.873015873015873}
{"Template_token": ["<s>", "static", "bool", "IsBitwiseBinaryOperator", "(", "unsigned", "Opcode", ")", "{", "switch", "(", "Opcode", ")", "{", "default", ":"], "ground_truth": ["return", "Instruction", "::", "isShift", "(", "Opcode", ")", ";"], "File": "FPGATargetTransformInfo", "Func": "IsBitwiseBinaryOperator", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139696, "Length": 23, "Cover_Rate": 0.36507936507936506}
{"Template_token": ["<s>", "if", "(", "!", "O", ")", "return", "false", ";", "auto", "Opcode", "=", "O", "->", "getOpcode", "(", ")", ";"], "ground_truth": ["Value", "*", "RHS", "=", "*", "std", "::", "prev", "(", "U", "->", "op_end", "(", ")", ")", ";"], "File": "FPGATargetTransformInfo", "Func": "IsFreeOperator", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139697, "Length": 33, "Cover_Rate": 0.36666666666666664}
{"Template_token": ["<s>", "if", "(", "!", "O", ")", "return", "false", ";", "auto", "Opcode", "=", "O", "->", "getOpcode", "(", ")", ";", "Value", "*", "RHS", "=", "*", "std", "::", "prev", "(", "U", "->", "op_end", "(", ")", ")", ";", "if", "(", "IsBitwiseBinaryOperator", "(", "Opcode", ")", "&&", "isa", "<", "Constant", ">", "(", "RHS", ")", ")", "return", "true", ";", "return", "false", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "IsFreeOperator", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139698, "Length": 55, "Cover_Rate": 0.6111111111111112}
{"Template_token": ["<s>", "static", "bool", "IsKernelFunction", "(", "const", "Function", "&", "F", ")", "{", "return", "F", ".", "getCallingConv", "(", ")", "==", "CallingConv", "::", "SPIR_KERNEL", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "IsKernelFunction", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139699, "Length": 22, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "return", "F", ".", "getCallingConv", "(", ")", "==", "CallingConv", "::", "SPIR_KERNEL", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "IsKernelFunction", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139700, "Length": 12, "Cover_Rate": 0.5454545454545454}
{"Template_token": ["<s>", "return", "true", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "isLegalAddImmediate", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139701, "Length": 4, "Cover_Rate": 0.3076923076923077}
{"Template_token": ["<s>", "return", "true", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "isLegalICmpImmediate", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139702, "Length": 4, "Cover_Rate": 0.3076923076923077}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "isLegalICmpImmediate", "(", "int64_t", "Imm", ")", "{", "return", "true", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "isLegalICmpImmediate", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139703, "Length": 13, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "isLegalMaskedLoad", "(", "Type", "*", "DataType", ")", "{", "return", "true", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "isLegalMaskedLoad", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139704, "Length": 14, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "isLegalMaskedStore", "(", "Type", "*", "DataType", ")", "{", "return", "true", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "isLegalMaskedStore", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139706, "Length": 14, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "isLegalToInferAttributeForFunction", "(", "Function", "*", "F", ")", "const", "{", "if", "(", "F", "->", "isDeclaration", "(", ")", "&&", "!", "F", "->", "hasFnAttribute", "(", "(", "Attribute", "::", "OptimizeNone", ")", ")", "&&", "F", "->", "getName", "(", ")", "==", "<STR_LIT>", ")", "return", "true", ";"], "ground_truth": ["return", "false", ";"], "File": "FPGATargetTransformInfo", "Func": "isLegalToInferAttributeForFunction", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139707, "Length": 45, "Cover_Rate": 0.9782608695652174}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "isLegalToInferAttributeForFunction", "(", "Function", "*", "F", ")", "const", "{"], "ground_truth": ["if", "(", "F", "->", "isDeclaration", "(", ")", "&&", "!", "F", "->", "hasFnAttribute", "(", "(", "Attribute", "::", "OptimizeNone", ")", ")", "&&", "F", "->", "getName", "(", ")", "==", "<STR_LIT>", ")", "return", "true", ";"], "File": "FPGATargetTransformInfo", "Func": "isLegalToInferAttributeForFunction", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139708, "Length": 42, "Cover_Rate": 0.9130434782608695}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "isLegalToVectorizeStoreChain", "(", "unsigned", "ChainSizeInBytes", ",", "unsigned", "Alignment", ",", "unsigned", "AddrSpace", ")", "const", "{"], "ground_truth": ["return", "true", ";"], "File": "FPGATargetTransformInfo", "Func": "isLegalToVectorizeStoreChain", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139710, "Length": 19, "Cover_Rate": 0.95}
{"Template_token": ["<s>", "switch", "(", "II", "->", "getIntrinsicID", "(", ")", ")", "{", "default", ":", "return", "false", ";", "case", "<STR_LIT>", ":", "return", "true", ";", "}"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "isPureFunction", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139711, "Length": 22, "Cover_Rate": 0.6470588235294118}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "isRegisterRich", "(", ")", "{", "return", "true", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "isRegisterRich", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139712, "Length": 11, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "isRegisterRich", "(", ")", "{", "return", "true", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "isRegisterRich", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139713, "Length": 11, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "return", "AS", "==", "<NUM_LIT>", ";", "}", "if", "(", "I", "->", "isAtomic", "(", ")", ")", "return", "true", ";", "if", "(", "const", "IntrinsicInst", "*", "II", "=", "dyn_cast", "<", "IntrinsicInst", ">", "(", "I", ")", ")", "{", "if", "(", "readsLocalId", "(", "II", ")", ")", "return", "true", ";", "if", "(", "readWorkgroupInvariant", "(", "II", ")", ")", "return", "false", ";", "if", "(", "isPureFunction", "(", "II", ")", ")", "return", "false", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "isSourceOfDivergence", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139714, "Length": 64, "Cover_Rate": 0.32653061224489793}
{"Template_token": ["<s>", "if", "(", "const", "IntrinsicInst", "*", "II", "=", "dyn_cast", "<", "IntrinsicInst", ">", "(", "I", ")", ")", "{", "if", "(", "readsLocalId", "(", "II", ")", ")", "return", "true", ";", "if", "(", "readWorkgroupInvariant", "(", "II", ")", ")", "return", "false", ";", "if", "(", "isPureFunction", "(", "II", ")", ")", "return", "false", ";", "}"], "ground_truth": ["if", "(", "isa", "<", "CallInst", ">", "(", "I", ")", ")", "return", "true", ";"], "File": "FPGATargetTransformInfo", "Func": "isSourceOfDivergence", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139715, "Length": 60, "Cover_Rate": 0.30612244897959184}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "isTruncateFree", "(", "Type", "*", "Ty1", ",", "Type", "*", "Ty2", ")", "{", "if", "(", "!", "Ty1", "->", "isIntegerTy", "(", ")", "||", "!", "Ty2", "->", "isIntegerTy", "(", ")", ")", "return", "false", ";", "unsigned", "NumBits1", "=", "Ty1", "->", "getPrimitiveSizeInBits", "(", ")", ";", "unsigned", "NumBits2", "=", "Ty2", "->", "getPrimitiveSizeInBits", "(", ")", ";", "return", "NumBits1", ">", "NumBits2", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "isTruncateFree", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139716, "Length": 57, "Cover_Rate": 1.0}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "isTypeLegal", "(", "Type", "*", "Ty", ")", "{"], "ground_truth": ["return", "true", ";"], "File": "FPGATargetTransformInfo", "Func": "isTypeLegal", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139717, "Length": 13, "Cover_Rate": 0.9285714285714286}
{"Template_token": ["<s>", "static", "bool", "readsLocalId", "(", "const", "IntrinsicInst", "*", "II", ")", "{", "switch", "(", "II", "->", "getIntrinsicID", "(", ")", ")", "{", "default", ":", "return", "false", ";", "case", "<STR_LIT>", ":"], "ground_truth": ["case", "<STR_LIT>", ":"], "File": "FPGATargetTransformInfo", "Func": "readsLocalId", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139718, "Length": 30, "Cover_Rate": 0.6122448979591837}
{"Template_token": ["<s>", "static", "bool", "readsLocalId", "(", "const", "IntrinsicInst", "*", "II", ")", "{", "switch", "(", "II", "->", "getIntrinsicID", "(", ")", ")", "{", "default", ":", "return", "false", ";", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "return", "true", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "readsLocalId", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139719, "Length": 40, "Cover_Rate": 0.8163265306122449}
{"Template_token": ["<s>", "return", "false", ";", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":"], "ground_truth": ["return", "true", ";"], "File": "FPGATargetTransformInfo", "Func": "readWorkgroupInvariant", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139720, "Length": 30, "Cover_Rate": 0.43478260869565216}
{"Template_token": ["<s>", "return", "false", ";", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":", "case", "<STR_LIT>", ":"], "ground_truth": ["return", "true", ";"], "File": "FPGATargetTransformInfo", "Func": "readWorkgroupInvariant", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139721, "Length": 30, "Cover_Rate": 0.43478260869565216}
{"Template_token": ["<s>", "return", "false", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "shouldBuildLookupTables", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139722, "Length": 4, "Cover_Rate": 0.36363636363636365}
{"Template_token": ["<s>", "bool", "<ISA_LIT>TTIImpl", "::", "shouldBuildLookupTables", "(", ")", "{", "return", "false", ";"], "ground_truth": ["}"], "File": "FPGATargetTransformInfo", "Func": "shouldBuildLookupTables", "Target": "FPGA", "Target_Clf": "CPU", "Compiler_Type": "LLVM", "Idx": 139723, "Length": 11, "Cover_Rate": 1.0}