<s> case <STR_LIT> : Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; } break ; } } }


<s> break ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) ) ; break ; } if ( MI . getOpcode ( ) == <STR_LIT> ) { Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) ) ; break ; } if ( MI . getOpcode ( ) == <STR_LIT> ) break ; switch ( MI . getDesc ( ) . TSFlags & <STR_LIT> ) { default : LLVM_DEBUG ( MI . dump ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; case <STR_LIT> : Limit = std :: min ( Limit , ( ( <NUM_LIT> << <NUM_LIT> ) - <NUM_LIT> ) * <NUM_LIT> ) ; break ; } break ; } } }


<s> const auto & CSI = MFI . getCalleeSavedInfo ( ) ; int MinCSFI = <NUM_LIT> ; int MaxCSFI = - <NUM_LIT> ; int Offset = MFI . getObjectOffset ( FI ) + MFI . getOffsetAdjustment ( ) ; if ( CSI . size ( ) ) { MinCSFI = CSI [ <NUM_LIT> ] . getFrameIdx ( ) ; MaxCSFI = CSI [ CSI . size ( ) - <NUM_LIT> ] . getFrameIdx ( ) ; } if ( FI >= MinCSFI && FI <= MaxCSFI ) { FrameReg = <STR_LIT> ; Offset += CFI -> getVarArgsSaveSize ( ) + CFI -> getCalleeSaveAreaSize ( ) ; } else if ( RI -> hasStackRealignment ( MF ) ) { assert ( hasFP ( MF ) ) ; if ( ! MFI . isFixedObjectIndex ( FI ) ) {

FrameReg = hasBP ( MF ) ? getBPReg ( STI ) : <STR_LIT> ;


<s> bool <ISA_LIT>FrameLowering :: restoreCalleeSavedRegisters ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator MI , MutableArrayRef < CalleeSavedInfo > CSI , const TargetRegisterInfo * TRI ) const { if ( CSI . empty ( ) ) return true ; MachineFunction * MF = MBB . getParent ( ) ; const TargetInstrInfo & TII = * MF -> getSubtarget ( ) . getInstrInfo ( ) ;


<s> if ( MI != MBB . end ( ) && ! MI -> isDebugInstr ( ) ) DL = MI -> getDebugLoc ( ) ; for ( auto & CS : reverse ( CSI ) ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . loadRegFromStackSlot ( MBB , MI , Reg , CS . getFrameIdx ( ) , RC , TRI ) ; assert ( MI != MBB . begin ( ) && <STR_LIT> ) ; }


<s> for ( auto & CS : CSI ) { Register Reg = CS . getReg ( ) ; const TargetRegisterClass * RC = TRI -> getMinimalPhysRegClass ( Reg ) ; TII . storeRegToStackSlot ( MBB , MI , Reg , true , CS . getFrameIdx ( ) , RC , TRI ) ; }


<s> } static const MCPhysReg CSF32Regs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; static const MCPhysReg CSF64Regs [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <NUM_LIT> } ; const MCPhysReg * FRegs = NULL ; if ( STI . hasFPUv2DoubleFloat ( ) || STI . hasFPUv3DoubleFloat ( ) ) FRegs = CSF64Regs ; else if ( STI . hasFPUv2SingleFloat ( ) || STI . hasFPUv3SingleFloat ( ) ) FRegs = CSF32Regs ; if ( FRegs != NULL ) { const MCPhysReg * Regs = MF . getRegInfo ( ) . getCalleeSavedRegs ( ) ; for ( unsigned i = <NUM_LIT> ; Regs [ i ] ; ++ i ) if ( <STR_LIT> . contains ( Regs [ i ] ) || <STR_LIT> . contains ( Regs [ i ] ) ) { unsigned x = <NUM_LIT> ; for ( ; FRegs [ x ] ; ++ x ) if ( FRegs [ x ] == Regs [ i ] ) break ; if ( FRegs [ x ] == <NUM_LIT> ) SavedRegs . set ( Regs [ i ] ) ; } } } CFI -> setLRIsSpilled ( SavedRegs . test ( <STR_LIT> ) ) ; unsigned CSStackSize = <NUM_LIT> ; for ( unsigned Reg : SavedRegs . set_bits ( ) ) { auto RegSize = TRI -> getRegSizeInBits ( Reg , MRI ) / <NUM_LIT> ; CSStackSize += RegSize ;


<s> explicit <ISA_LIT>FrameLowering ( const <ISA_LIT>Subtarget & STI ) : TargetFrameLowering ( StackGrowsDown , Align ( <NUM_LIT> ) , <NUM_LIT> ) , STI ( STI ) {


<s> void <ISA_LIT>FrameLowering :: emitEpilogue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> void <ISA_LIT>FrameLowering :: emitPrologue ( MachineFunction & MF , MachineBasicBlock & MBB ) const {


<s> static Register getBPReg ( const <ISA_LIT>Subtarget & STI ) {


<s> static Register getFPReg ( const <ISA_LIT>Subtarget & STI ) { return <STR_LIT> ;


<s> const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;


<s> bool <ISA_LIT>FrameLowering :: hasFP ( const MachineFunction & MF ) const {

const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ;


<s> const TargetRegisterInfo * RegInfo = MF . getSubtarget ( ) . getRegisterInfo ( ) ; const MachineFrameInfo & MFI = MF . getFrameInfo ( ) ;

return MF . getTarget ( ) . Options . DisableFramePointerElim ( MF ) || RegInfo -> hasStackRealignment ( MF ) || MFI . hasVarSizedObjects ( ) || MFI . isFrameAddressTaken ( ) ;


<s> if ( Opt == <STR_LIT> ) { ArchRegNames = true ; return true ; } if ( Opt == <STR_LIT> ) { DebugFlag = true ; return true ; } if ( Opt == <STR_LIT> ) {


<s> void <ISA_LIT>InstPrinter :: printFPR ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) {

const MCOperand & MO = MI -> getOperand ( OpNo ) ;


<s> void <ISA_LIT>InstPrinter :: printFPRRegName ( raw_ostream & O , unsigned RegNo ) const { if ( PrintBranchImmAsAddress ) O << getRegisterName ( RegNo , <STR_LIT> ) ; else O << getRegisterName ( RegNo ) ;


<s> else if ( Reg == <STR_LIT> ) O << ( useABIName ? <STR_LIT> : <STR_LIT> ) ; else if ( Reg == <STR_LIT> ) O << ( useABIName ? <STR_LIT> : <STR_LIT> ) ; else printRegName ( O , Reg ) ; } else printRegName ( O , Reg ) ; return ; } if ( MO . isImm ( ) ) { uint64_t TSFlags = MII . get ( MI -> getOpcode ( ) ) . TSFlags ;

if ( ( ( TSFlags & <STR_LIT> ) != <STR_LIT> ) && PrintBranchImmAsAddress ) O << formatHex ( MO . getImm ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printPSRFlag ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { auto V = MI -> getOperand ( OpNo ) . getImm ( ) ; ListSeparator LS ; if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) O << LS << <STR_LIT> ; if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) O << LS << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printPSRFlag ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { auto V = MI -> getOperand ( OpNo ) . getImm ( ) ; ListSeparator LS ; if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) O << LS << <STR_LIT> ; if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) O << LS << <STR_LIT> ; if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) O << LS << <STR_LIT> ; if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) O << LS << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const { if ( PrintBranchImmAsAddress ) O << getRegisterName ( RegNo , ABIRegNames ? <STR_LIT> : <STR_LIT> ) ; else O << getRegisterName ( RegNo ) ;


<s> } if ( Opt == <STR_LIT> ) { ArchRegNames = true ; return true ; }


<s> <ISA_LIT>InstPrinter ( const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) : MCInstPrinter ( MAI , MII , MRI ) {


<s> const char * <ISA_LIT>InstPrinter :: getRegisterName ( unsigned RegNo ) {

return getRegisterName ( RegNo , ArchRegNames ? <STR_LIT> : <STR_LIT> ) ;


<s> O << MO . getImm ( ) ; } return ; } assert ( MO . isExpr ( ) && <STR_LIT> ) ; O << <STR_LIT> ; MO . getExpr ( ) -> print ( O , & MAI ) ; O << <STR_LIT> ;


<s> void <ISA_LIT>InstPrinter :: printConstpool ( const MCInst * MI , uint64_t Address , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isImm ( ) ) { if ( PrintBranchImmAsAddress ) { uint64_t Target = Address + MO . getImm ( ) ; Target &= <NUM_LIT> ; O << formatHex ( Target ) ; } else { O << MO . getImm ( ) ; } return ; } assert ( MO . isExpr ( ) && <STR_LIT> ) ;


<s> if ( ! MO . isImm ( ) ) { return printOperand ( MI , OpNo , STI , O ) ; } if ( PrintBranchImmAsAddress ) { uint64_t Target = Address + MO . getImm ( ) ;


<s> void <ISA_LIT>InstPrinter :: print<ISA_LIT>SymbolOperand ( const MCInst * MI , uint64_t Address , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O ) { const MCOperand & MO = MI -> getOperand ( OpNo ) ;


<s> if ( MO . isImm ( ) ) O << MO . getImm ( ) ; else MO . getExpr ( ) -> print ( O , & MAI ) ;


<s> if ( NoAliases || ! printAliasInstr ( NewMI , Address , STI , O ) ) printInstruction ( NewMI , Address , STI , O ) ;


<s> void <ISA_LIT>InstPrinter :: printOperand ( const MCInst * MI , unsigned OpNo , const MCSubtargetInfo & STI , raw_ostream & O , const char * Modifier ) { assert ( ( Modifier == <NUM_LIT> || Modifier [ <NUM_LIT> ] == <NUM_LIT> ) && <STR_LIT> ) ; const MCOperand & MO = MI -> getOperand ( OpNo ) ; if ( MO . isReg ( ) ) { if ( MO . getReg ( ) == <STR_LIT> ) O << <STR_LIT> ; else printRegName ( O , MO . getReg ( ) ) ;


<s> } if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) { O << LS ; printRegName ( O , <STR_LIT> ) ; } if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) { O << LS ; printRegName ( O , <STR_LIT> ) ; auto Offset = ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) - <NUM_LIT> ; if ( Offset ) {


<s> } if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) { O << LS ; printRegName ( O , <STR_LIT> ) ; } if ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) { O << LS ; printRegName ( O , <STR_LIT> ) ; auto Offset = ( ( V >> <NUM_LIT> ) & <NUM_LIT> ) - <NUM_LIT> ; if ( Offset ) { O << <STR_LIT> ;

printRegName ( O , <STR_LIT> + Offset ) ;


<s> void <ISA_LIT>InstPrinter :: printRegisterSeq ( const MCInst * MI , unsigned OpNum , const MCSubtargetInfo & STI , raw_ostream & O ) { printRegName ( O , MI -> getOperand ( OpNum ) . getReg ( ) ) ; O << <STR_LIT> ; printRegName ( O , MI -> getOperand ( OpNum + <NUM_LIT> ) . getReg ( ) ) ;


<s> printRegName ( O , MI -> getOperand ( OpNum + <NUM_LIT> ) . getReg ( ) ) ;


<s> void <ISA_LIT>InstPrinter :: printRegName ( raw_ostream & O , unsigned RegNo ) const {


<s> TBB = FBB = nullptr ; Cond . clear ( ) ; MachineBasicBlock :: iterator I = MBB . getLastNonDebugInstr ( ) ; if ( I == MBB . end ( ) || ! isUnpredicatedTerminator ( * I ) ) return false ; MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = <NUM_LIT> ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ;

if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) {


<s> MachineBasicBlock :: iterator FirstUncondOrIndirectBr = MBB . end ( ) ; int NumTerminators = <NUM_LIT> ; for ( auto J = I . getReverse ( ) ; J != MBB . rend ( ) && isUnpredicatedTerminator ( * J ) ; J ++ ) { NumTerminators ++ ; if ( J -> getDesc ( ) . isUnconditionalBranch ( ) || J -> getDesc ( ) . isIndirectBranch ( ) ) { FirstUncondOrIndirectBr = J . getReverse ( ) ; } } if ( AllowModify && FirstUncondOrIndirectBr != MBB . end ( ) ) { while ( std :: next ( FirstUncondOrIndirectBr ) != MBB . end ( ) ) { std :: next ( FirstUncondOrIndirectBr ) -> eraseFromParent ( ) ; NumTerminators -- ; } I = FirstUncondOrIndirectBr ; } if ( I -> getDesc ( ) . isIndirectBranch ( ) ) return true ; if ( NumTerminators > <NUM_LIT> ) return true ; if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { TBB = getBranchDestBlock ( * I ) ; return false ; } if ( NumTerminators == <NUM_LIT> && I -> getDesc ( ) . isConditionalBranch ( ) ) { parseCondBranch ( * I , TBB , Cond ) ; return false ; } if ( NumTerminators == <NUM_LIT> && std :: prev ( I ) -> getDesc ( ) . isConditionalBranch ( ) && I -> getDesc ( ) . isUnconditionalBranch ( ) ) { parseCondBranch ( * std :: prev ( I ) , TBB , Cond ) ; FBB = getBranchDestBlock ( * I ) ; return false ;


<s> if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { if ( STI . hasE2 ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { assert ( DestReg < <STR_LIT> ) ; assert ( DestReg < <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , RegState :: Define ) . addReg ( SrcReg , RegState :: Define ) . addReg ( DestReg , getKillRegState ( true ) ) . addReg ( DestReg , getKillRegState ( true ) ) . addReg ( SrcReg , getKillRegState ( true ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , RegState :: Define | getDeadRegState ( KillSrc ) ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; } return ; } unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2df && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v3df && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v2df && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3df && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ;


<s> v2df = STI . hasFPUv2DoubleFloat ( ) ; v3sf = STI . hasFPUv3SingleFloat ( ) ; v3df = STI . hasFPUv3DoubleFloat ( ) ;


<s> assert ( MI . getDesc ( ) . isBranch ( ) && <STR_LIT> ) ; int NumOp = MI . getNumExplicitOperands ( ) ; assert ( MI . getOperand ( NumOp - <NUM_LIT> ) . isMBB ( ) && <STR_LIT> ) ;

return MI . getOperand ( NumOp - <NUM_LIT> ) . getMBB ( ) ;


<s> MachineBasicBlock * <ISA_LIT>InstrInfo :: getBranchDestBlock ( const MachineInstr & MI ) const {

assert ( MI . getDesc ( ) . isBranch ( ) && <STR_LIT> ) ;


<s> MachineMemOperand * MO = MF . getMachineMemOperand ( MachinePointerInfo :: getConstantPool ( MF ) , MachineMemOperand :: MOLoad , <NUM_LIT> , Align ( <NUM_LIT> ) ) ; BuildMI ( FirstMBB , MBBI , DL , get ( <STR_LIT> ) , <STR_LIT> ) . addConstantPoolIndex ( CPI ) . addMemOperand ( MO ) ; GlobalBaseReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( FirstMBB , MBBI , DL , get ( TargetOpcode :: COPY ) , GlobalBaseReg ) . addReg ( <STR_LIT> ) ; CFI -> setGlobalBaseReg ( GlobalBaseReg ) ;


<s> unsigned <ISA_LIT>InstrInfo :: getInstSizeInBytes ( const MachineInstr & MI ) const { switch ( MI . getOpcode ( ) ) { default : return MI . getDesc ( ) . getSize ( ) ; case <STR_LIT> : return MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : return <NUM_LIT> ; case TargetOpcode :: INLINEASM_BR : case TargetOpcode :: INLINEASM : {

const MachineFunction * MF = MI . getParent ( ) -> getParent ( ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> :


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> if ( Cond . empty ( ) ) { MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ; return <NUM_LIT> ; } unsigned Opc = Cond [ <NUM_LIT> ] . getImm ( ) ; MachineInstr & CondMI = * BuildMI ( & MBB , DL , get ( Opc ) ) . add ( Cond [ <NUM_LIT> ] ) . addMBB ( TBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( CondMI ) ; if ( ! FBB ) return <NUM_LIT> ; MachineInstr & MI = * BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( FBB ) ; if ( BytesAdded ) * BytesAdded += getInstSizeInBytes ( MI ) ;


<s> if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; } return <NUM_LIT> ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; }

if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) {


<s> BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flag ) ; if ( ( Val & <NUM_LIT> ) != <NUM_LIT> ) BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( Val & <NUM_LIT> ) . setMIFlags ( Flag ) ; } else { BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addImm ( ( Val >> <NUM_LIT> ) & <NUM_LIT> ) . setMIFlags ( Flag ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flag ) ; if ( ( ( Val >> <NUM_LIT> ) & <NUM_LIT> ) != <NUM_LIT> ) BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( ( Val >> <NUM_LIT> ) & <NUM_LIT> ) . setMIFlags ( Flag ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flag ) ; if ( ( ( Val >> <NUM_LIT> ) & <NUM_LIT> ) != <NUM_LIT> ) BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( ( Val >> <NUM_LIT> ) & <NUM_LIT> ) . setMIFlags ( Flag ) ; BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( <NUM_LIT> ) . setMIFlags ( Flag ) ; if ( ( Val & <NUM_LIT> ) != <NUM_LIT> ) BuildMI ( MBB , MBBI , DL , get ( <STR_LIT> ) , DstReg ) . addReg ( DstReg ) . addImm ( Val & <NUM_LIT> ) . setMIFlags ( Flag ) ;


<s> static void parseCondBranch ( MachineInstr & LastInst , MachineBasicBlock * & Target , SmallVectorImpl < MachineOperand > & Cond ) { assert ( LastInst . getDesc ( ) . isConditionalBranch ( ) && <STR_LIT> ) ; Target = LastInst . getOperand ( <NUM_LIT> ) . getMBB ( ) ; Cond . push_back ( MachineOperand :: CreateImm ( LastInst . getOpcode ( ) ) ) ;

Cond . push_back ( LastInst . getOperand ( <NUM_LIT> ) ) ;


<s> if ( I == MBB . begin ( ) ) return <NUM_LIT> ; -- I ; if ( ! I -> getDesc ( ) . isConditionalBranch ( ) ) return <NUM_LIT> ; if ( BytesRemoved ) * BytesRemoved += getInstSizeInBytes ( * I ) ; I -> eraseFromParent ( ) ;


<s> bool <ISA_LIT>InstrInfo :: reverseBranchCondition ( SmallVectorImpl < MachineOperand > & Cond ) const { assert ( ( Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; Cond [ <NUM_LIT> ] . setImm ( getOppositeBranchOpc ( Cond [ <NUM_LIT> ] . getImm ( ) ) ) ;


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * CFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; CFI -> setSpillsCR ( ) ;

} else if ( v2sf && <STR_LIT> . hasSubClassEq ( RC ) ) Opcode = <STR_LIT> ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , RegState :: Define | getDeadRegState ( KillSrc ) ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; } return ; } unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2df && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v3df && <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v2df && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3df && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v2sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ; else if ( v3sf && <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) Opcode = <STR_LIT> ;


<s> if ( <STR_LIT> . contains ( SrcReg ) && <STR_LIT> . contains ( DestReg ) ) { if ( STI . hasE2 ( ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; } else { assert ( DestReg < <STR_LIT> ) ; assert ( DestReg < <STR_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( DestReg , RegState :: Define ) . addReg ( SrcReg , RegState :: Define ) . addReg ( DestReg , getKillRegState ( true ) ) . addReg ( DestReg , getKillRegState ( true ) ) . addReg ( SrcReg , getKillRegState ( true ) ) ; BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , RegState :: Define | getDeadRegState ( KillSrc ) ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; } return ; } unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . contains ( DestReg , SrcReg ) ) Opcode = <STR_LIT> ; else { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> << SrcReg << <STR_LIT> << DestReg ) ; LLVM_DEBUG ( I -> dump ( ) ) ; llvm_unreachable ( <STR_LIT> ) ; }

BuildMI ( MBB , I , DL , get ( Opcode ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ;


<s> default : return <NUM_LIT> ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : break ; } if ( MI . getOperand ( <NUM_LIT> ) . isFI ( ) && MI . getOperand ( <NUM_LIT> ) . isImm ( ) && MI . getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI . getOperand ( <NUM_LIT> ) . getIndex ( ) ;

return MI . getOperand ( <NUM_LIT> ) . getReg ( ) ;


<s> Opcode = <STR_LIT> ; } else if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ; CFI -> setSpillsCR ( ) ; } else { llvm_unreachable ( <STR_LIT> ) ; } MachineMemOperand * MMO = MF . getMachineMemOperand ( MachinePointerInfo :: getFixedStack ( MF , FI ) , MachineMemOperand :: MOLoad , MFI . getObjectSize ( FI ) , MFI . getObjectAlign ( FI ) ) ;

BuildMI ( MBB , I , DL , get ( Opcode ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) . addMemOperand ( MMO ) ;


<s> DebugLoc DL ; if ( I != MBB . end ( ) ) DL = I -> getDebugLoc ( ) ; MachineFunction & MF = * MBB . getParent ( ) ; <ISA_LIT>MachineFunctionInfo * CFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; unsigned Opcode = <NUM_LIT> ; if ( <STR_LIT> . hasSubClassEq ( RC ) ) { Opcode = <STR_LIT> ;

} else if ( <STR_LIT> . hasSubClassEq ( RC ) ) {


<s> <ISA_LIT>InstrInfo :: <ISA_LIT>InstrInfo ( <ISA_LIT>Subtarget & STI ) : <ISA_LIT>GenInstrInfo ( <STR_LIT> , <STR_LIT> ) , STI ( STI ) {


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; N -> setNodeId ( - <NUM_LIT> ) ; return ; } SDLoc Dl ( N ) ;


<s> LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; N -> setNodeId ( - <NUM_LIT> ) ; return ; } SDLoc Dl ( N ) ; unsigned Opcode = N -> getOpcode ( ) ; bool IsSelected = false ; switch ( Opcode ) {


<s> break ; case <STR_LIT> : IsSelected = selectAddCarry ( N ) ; break ; case <STR_LIT> : IsSelected = selectSubCarry ( N ) ; break ; case <STR_LIT> : { Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ; ReplaceNode ( N , CurDAG -> getRegister ( GP , N -> getValueType ( <NUM_LIT> ) ) . getNode ( ) ) ; IsSelected = true ; break ; } case <STR_LIT> : {

SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ;


<s> bool <ISA_LIT>DAGToDAGISel :: selectBITCAST_TO_LOHI ( SDNode * N ) { SDLoc Dl ( N ) ; auto VT = N -> getValueType ( <NUM_LIT> ) ; auto V = N -> getOperand ( <NUM_LIT> ) ; if ( ! Subtarget -> hasFPUv2DoubleFloat ( ) ) return false ;

SDValue V1 = SDValue ( CurDAG -> getMachineNode ( <STR_LIT> , Dl , VT , V ) , <NUM_LIT> ) ;


<s> FunctionPass * llvm :: create<ISA_LIT>ISelDag ( <ISA_LIT>TargetMachine & TM ) {

return new <ISA_LIT>DAGToDAGISel ( TM ) ;


<s> SDNode * <ISA_LIT>DAGToDAGISel :: createGPRPairNode ( EVT VT , SDValue V0 , SDValue V1 ) { SDLoc dl ( V0 . getNode ( ) ) ; SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ;

SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ;


<s> SDValue RegClass = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg0 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; SDValue SubReg1 = CurDAG -> getTargetConstant ( <STR_LIT> , dl , <STR_LIT> ) ; const SDValue Ops [ ] = { RegClass , V0 , SubReg0 , V1 , SubReg1 } ; return CurDAG -> getMachineNode ( TargetOpcode :: REG_SEQUENCE , dl , VT , Ops ) ;


<s> explicit <ISA_LIT>DAGToDAGISel ( <ISA_LIT>TargetMachine & TM ) : SelectionDAGISel ( TM ) {


<s> StringRef getPassName ( ) const override {


<s> auto NewCarryReg = DAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , <STR_LIT> , OldCarry ) ;

auto NewCarry = DAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? <STR_LIT> : <STR_LIT> , Dl , OldCarry . getValueType ( ) , SDValue ( NewCarryReg , <NUM_LIT> ) , DAG -> getTargetConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ;


<s> auto NewCarry = DAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? <STR_LIT> : <STR_LIT> , Dl , OldCarry . getValueType ( ) , SDValue ( NewCarryReg , <NUM_LIT> ) , DAG -> getTargetConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ) ; return SDValue ( NewCarry , <NUM_LIT> ) ;


<s> bool runOnMachineFunction ( MachineFunction & MF ) override { Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; SelectionDAGISel :: runOnMachineFunction ( MF ) ; return true ;


<s> Subtarget = & MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

SelectionDAGISel :: runOnMachineFunction ( MF ) ;


<s> void <ISA_LIT>DAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) { LLVM_DEBUG ( dbgs ( ) << <STR_LIT> ; N -> dump ( CurDAG ) ; dbgs ( ) << <STR_LIT> ) ; N -> setNodeId ( - <NUM_LIT> ) ; return ; } SDLoc Dl ( N ) ; unsigned Opcode = N -> getOpcode ( ) ; bool IsSelected = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : IsSelected = selectAddCarry ( N ) ; break ; case <STR_LIT> : IsSelected = selectSubCarry ( N ) ; break ; case <STR_LIT> : { Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ; ReplaceNode ( N , CurDAG -> getRegister ( GP , N -> getValueType ( <NUM_LIT> ) ) . getNode ( ) ) ; IsSelected = true ; break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , <STR_LIT> ) ; ReplaceNode ( N , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? <STR_LIT> : <STR_LIT> , Dl , <STR_LIT> , TFI , Imm ) ) ; IsSelected = true ; break ; } case <STR_LIT> : case <STR_LIT> :


<s> SDLoc Dl ( N ) ; unsigned Opcode = N -> getOpcode ( ) ; bool IsSelected = false ; switch ( Opcode ) { default : break ; case <STR_LIT> : IsSelected = selectAddCarry ( N ) ; break ; case <STR_LIT> : IsSelected = selectSubCarry ( N ) ; break ; case <STR_LIT> : { Register GP = Subtarget -> getInstrInfo ( ) -> getGlobalBaseReg ( * MF ) ; ReplaceNode ( N , CurDAG -> getRegister ( GP , N -> getValueType ( <NUM_LIT> ) ) . getNode ( ) ) ; IsSelected = true ; break ; } case <STR_LIT> : { SDValue Imm = CurDAG -> getTargetConstant ( <NUM_LIT> , Dl , <STR_LIT> ) ; int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , <STR_LIT> ) ; ReplaceNode ( N , CurDAG -> getMachineNode ( Subtarget -> hasE2 ( ) ? <STR_LIT> : <STR_LIT> , Dl , <STR_LIT> , TFI , Imm ) ) ; IsSelected = true ; break ; } case <STR_LIT> : case <STR_LIT> : IsSelected = selectInlineAsm ( N ) ;


<s> MachineSDNode * NewNode = nullptr ; auto Type0 = N -> getValueType ( <NUM_LIT> ) ; auto Type1 = N -> getValueType ( <NUM_LIT> ) ; auto Op0 = N -> getOperand ( <NUM_LIT> ) ; auto Op1 = N -> getOperand ( <NUM_LIT> ) ; auto Op2 = N -> getOperand ( <NUM_LIT> ) ; SDLoc Dl ( N ) ; if ( isNullConstant ( Op2 ) ) { auto * CA = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , Type1 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , SDValue ( CA , <NUM_LIT> ) } ) ; } else if ( isOneConstant ( Op2 ) ) { auto * CA = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , Type1 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , SDValue ( CA , <NUM_LIT> ) } ) ; } else { NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , Op2 } ) ; }


<s> SDValue RegCopy = CurDAG -> getCopyFromReg ( Chain , dl , GPVR , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue Sub0 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue Sub1 = CurDAG -> getTargetExtractSubreg ( <STR_LIT> , dl , <STR_LIT> , RegCopy ) ; SDValue T0 = CurDAG -> getCopyToReg ( Sub0 , dl , Reg0 , Sub0 , RegCopy . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyToReg ( Sub1 , dl , Reg1 , Sub1 , T0 . getValue ( <NUM_LIT> ) ) ; std :: vector < SDValue > Ops ( GU -> op_begin ( ) , GU -> op_end ( ) - <NUM_LIT> ) ; Ops . push_back ( T1 . getValue ( <NUM_LIT> ) ) ; CurDAG -> UpdateNodeOperands ( GU , Ops ) ; } else { SDValue Chain = AsmNodeOperands [ InlineAsm :: Op_InputChain ] ; SDValue T0 = CurDAG -> getCopyFromReg ( Chain , dl , Reg0 , <STR_LIT> , Chain . getValue ( <NUM_LIT> ) ) ; SDValue T1 = CurDAG -> getCopyFromReg ( Chain , dl , Reg1 , <STR_LIT> , T0 . getValue ( <NUM_LIT> ) ) ; SDValue Pair = SDValue ( createGPRPairNode ( <STR_LIT> , T0 , T1 ) , <NUM_LIT> ) ; Register GPVR = MRI . createVirtualRegister ( & <STR_LIT> ) ; PairedReg = CurDAG -> getRegister ( GPVR , <STR_LIT> ) ; Chain = CurDAG -> getCopyToReg ( T1 , dl , GPVR , Pair , T1 . getValue ( <NUM_LIT> ) ) ; AsmNodeOperands [ InlineAsm :: Op_InputChain ] = Chain ; Glue = Chain . getValue ( <NUM_LIT> ) ; } Changed = true ; if ( PairedReg . getNode ( ) ) { OpChanged [ OpChanged . size ( ) - <NUM_LIT> ] = true ; Flag = InlineAsm :: getFlagWord ( Kind , <NUM_LIT> ) ; if ( IsTiedToChangedOp ) Flag = InlineAsm :: getFlagWordForMatchingOp ( Flag , DefIdx ) ; else Flag = InlineAsm :: getFlagWordForRegClass ( Flag , <STR_LIT> ) ; AsmNodeOperands [ AsmNodeOperands . size ( ) - <NUM_LIT> ] = CurDAG -> getTargetConstant ( Flag , dl , <STR_LIT> ) ;

AsmNodeOperands . push_back ( PairedReg ) ;


<s> OutOps . push_back ( Op ) ; return false ; default : break ; }


<s> SDLoc Dl ( N ) ; if ( isNullConstant ( Op2 ) ) { auto * CA = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , Type1 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , SDValue ( CA , <NUM_LIT> ) } ) ; } else if ( isOneConstant ( Op2 ) ) { auto * CA = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , Type1 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , SDValue ( CA , <NUM_LIT> ) } ) ; } else { auto CarryIn = InvertCarryFlag ( Subtarget , CurDAG , Dl , Op2 ) ; NewNode = CurDAG -> getMachineNode ( Subtarget -> has2E3 ( ) ? <STR_LIT> : <STR_LIT> , Dl , { Type0 , Type1 } , { Op0 , Op1 , CarryIn } ) ; }

auto CarryOut = InvertCarryFlag ( Subtarget , CurDAG , Dl , SDValue ( NewNode , <NUM_LIT> ) ) ;


<s> SDValue Addr = DAG . getNode ( <STR_LIT> , DL , Ty , { TV , TCPV } ) ; if ( ! IsPIC ) return Addr ; SDValue Result = DAG . getNode ( <STR_LIT> , DL , Ty , { DAG . getGLOBAL_OFFSET_TABLE ( Ty ) , Addr } ) ; if ( IsLocal ) return Result ;

return DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , Result , MachinePointerInfo :: getGOT ( DAG . getMachineFunction ( ) ) ) ;


<s> bool isSelectSupported ( SelectSupportKind Kind ) const override {

return ( Kind != ScalarCondVectorVal ) ;


<s> computeRegisterProperties ( STI . getRegisterInfo ( ) ) ; setBooleanContents ( UndefinedBooleanContent ) ; setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; setMaxAtomicSizeInBitsSupported ( <NUM_LIT> ) ;

setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ;


<s> setBooleanVectorContents ( ZeroOrNegativeOneBooleanContent ) ; setMaxAtomicSizeInBitsSupported ( <NUM_LIT> ) ; setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; const Align FunctionAlignment ( <NUM_LIT> ) ;

setMinFunctionAlignment ( FunctionAlignment ) ;


<s> switch ( Opcode ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue ; if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( Subtarget , DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { const unsigned XLenInBytes = <NUM_LIT> ; const MVT XLenVT = <STR_LIT> ; ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) { const Register Reg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( ArgRegs [ I ] , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; OutChains . push_back ( Store ) ;


<s> MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; EVT LocVT = VA . getLocVT ( ) ; SDValue Val ; const TargetRegisterClass * RC ; switch ( LocVT . getSimpleVT ( ) . SimpleTy ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : RC = & <STR_LIT> ; break ; } Register VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ;

return convertLocVTToValVT ( DAG , Val , VA , DL ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( ! Subtarget . hasE2 ( ) ) { setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( ! Subtarget . has2E3 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; <STR_LIT> FPOpToExpand [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( STI . useHardFloat ( ) ) { MVT AllVTy [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : AllVTy ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , VT , Expand ) ; for ( auto Op : FPOpToExpand ) setOperationAction ( Op , VT , Expand ) ; } if ( STI . hasFPUv2SingleFloat ( ) || STI . hasFPUv3SingleFloat ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Legal ) ; } if ( STI . hasFPUv2DoubleFloat ( ) || STI . hasFPUv3DoubleFloat ( ) ) { setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setTruncStoreAction ( <STR_LIT> , <STR_LIT> , Expand ) ; }


<s> case <STR_LIT> : if ( Subtarget . hasE2 ( ) ) return emitSelectPseudo ( MI , BB , <STR_LIT> ) ; else return emitSelectPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> :


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : case <STR_LIT> : if ( Subtarget . hasE2 ( ) ) return emitSelectPseudo ( MI , BB , <STR_LIT> ) ; else return emitSelectPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitSelectPseudo ( MI , BB , <STR_LIT> ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; if ( ! Subtarget . hasE2 ( ) ) { setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; }


<s> SmallVector < CCValAssign , <NUM_LIT> > <ISA_LIT>Locs ; CCState CCInfo ( CallConv , IsVarArg , MF , <ISA_LIT>Locs , Context ) ; return CCInfo . CheckReturn ( Outs , CCAssignFnForReturn ( CallConv , IsVarArg ) ) ;


<s> bool <ISA_LIT>TargetLowering :: CanLowerReturn ( CallingConv :: ID CallConv , MachineFunction & MF , bool IsVarArg , const SmallVectorImpl < <STR_LIT> > & Outs , LLVMContext & Context ) const { SmallVector < CCValAssign , <NUM_LIT> > <ISA_LIT>Locs ; CCState CCInfo ( CallConv , IsVarArg , MF , <ISA_LIT>Locs , Context ) ;

return CCInfo . CheckReturn ( Outs , CCAssignFnForReturn ( CallConv , IsVarArg ) ) ;


<s> if ( IsVarArg || ! Subtarget . useHardFloatABI ( ) ) return CC_<ISA_LIT>_ABIV2_SOFT ; else return CC_<ISA_LIT>_ABIV2_FP ;


<s> CCAssignFn * <ISA_LIT>TargetLowering :: CCAssignFnForReturn ( CallingConv :: ID CC , bool IsVarArg ) const { if ( IsVarArg || ! Subtarget . useHardFloatABI ( ) ) return RetCC_<ISA_LIT>_ABIV2_SOFT ; else return RetCC_<ISA_LIT>_ABIV2_FP ;


<s> switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , VA . getValVT ( ) , Val ) ; break ; } return Val ;


<s> EVT LocVT = VA . getLocVT ( ) ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: BCvt : Val = DAG . getNode ( <STR_LIT> , DL , LocVT , Val ) ;


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; if ( ! Subtarget . hasE2 ( ) ) { setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( ! Subtarget . has2E3 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } if ( ! Subtarget . has3r2E3r3 ( ) ) { setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; } <STR_LIT> FPCCToExtend [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , } ; <STR_LIT> FPOpToExpand [ ] = { <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> , <STR_LIT> } ; if ( STI . useHardFloat ( ) ) { MVT AllVTy [ ] = { <STR_LIT> , <STR_LIT> } ; for ( auto VT : AllVTy ) { setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; setOperationAction ( <STR_LIT> , VT , Expand ) ; for ( auto CC : FPCCToExtend ) setCondCodeAction ( CC , VT , Expand ) ; for ( auto Op : FPOpToExpand ) setOperationAction ( Op , VT , Expand ) ; }

if ( STI . hasFPUv2SingleFloat ( ) || STI . hasFPUv3SingleFloat ( ) ) {


<s> MachineBasicBlock * <ISA_LIT>TargetLowering :: EmitInstrWithCustomInserter ( MachineInstr & MI , MachineBasicBlock * BB ) const { switch ( MI . getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return emitSelectPseudo ( MI , BB , <STR_LIT> ) ; case <STR_LIT> : return emitSelectPseudo ( MI , BB , <STR_LIT> ) ;


<s> Register <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const {


<s> Register <ISA_LIT>TargetLowering :: getExceptionPointerRegister ( const Constant * PersonalityFn ) const { return <STR_LIT> ;


<s> else if ( Flags == <STR_LIT> ) return <STR_LIT> ; else if ( Flags == <STR_LIT> ) return <STR_LIT> ;


<s> if ( Flags == <STR_LIT> ) return <STR_LIT> ; else if ( Flags == <STR_LIT> ) return <STR_LIT> ; else if ( Flags == <STR_LIT> ) return <STR_LIT> ;


<s> EVT <ISA_LIT>TargetLowering :: getSetCCResultType ( const DataLayout & DL , LLVMContext & Context , EVT VT ) const { if ( ! VT . isVector ( ) ) return <STR_LIT> ;

return VT . changeVectorElementTypeToInteger ( ) ;


<s> SDValue <ISA_LIT>TargetLowering :: getStaticTLSAddr ( GlobalAddressSDNode * N , SelectionDAG & DAG , bool UseGOT ) const { MachineFunction & MF = DAG . getMachineFunction ( ) ; <ISA_LIT>MachineFunctionInfo * CFI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; unsigned <ISA_LIT>PCLabelIndex = CFI -> createPICLabelUId ( ) ; SDLoc DL ( N ) ; EVT Ty = getPointerTy ( DAG . getDataLayout ( ) ) ; <STR_LIT> Flag = UseGOT ? <STR_LIT> : <STR_LIT> ; bool AddCurrentAddr = UseGOT ? true : false ; unsigned char PCAjust = UseGOT ? <NUM_LIT> : <NUM_LIT> ; <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( N -> getGlobal ( ) , <STR_LIT> , PCAjust , Flag , AddCurrentAddr , <ISA_LIT>PCLabelIndex ) ; SDValue CAddr = DAG . getTargetConstantPool ( CPV , Ty ) ; SDValue Load ; if ( UseGOT ) { SDValue PICLabel = DAG . getTargetConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ; auto * LRWGRS = DAG . getMachineNode ( <STR_LIT> , DL , { Ty , Ty } , { CAddr , PICLabel } ) ; auto LRWADDGRS = DAG . getNode ( <STR_LIT> , DL , Ty , SDValue ( LRWGRS , <NUM_LIT> ) , SDValue ( LRWGRS , <NUM_LIT> ) ) ; Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , LRWADDGRS , MachinePointerInfo ( N -> getGlobal ( ) ) ) ; } else { Load = SDValue ( DAG . getMachineNode ( <STR_LIT> , DL , Ty , CAddr ) , <NUM_LIT> ) ; }

SDValue TPReg = DAG . getRegister ( <STR_LIT> , <STR_LIT> ) ;


<s> SDValue PICLabel = DAG . getTargetConstant ( <ISA_LIT>PCLabelIndex , DL , <STR_LIT> ) ; auto * LRWGRS = DAG . getMachineNode ( <STR_LIT> , DL , { Ty , Ty } , { CAddr , PICLabel } ) ; auto LRWADDGRS = DAG . getNode ( <STR_LIT> , DL , Ty , SDValue ( LRWGRS , <NUM_LIT> ) , SDValue ( LRWGRS , <NUM_LIT> ) ) ;

Load = DAG . getLoad ( Ty , DL , DAG . getEntryNode ( ) , LRWADDGRS , MachinePointerInfo ( N -> getGlobal ( ) ) ) ;


<s> <ISA_LIT>ConstantPoolValue * CPV = <ISA_LIT>ConstantPoolConstant :: Create ( N -> getBlockAddress ( ) , <STR_LIT> , <NUM_LIT> , getModifier ( Flags ) , false ) ; return DAG . getTargetConstantPool ( CPV , Ty ) ;


<s> return DAG . getTargetBlockAddress ( N -> getBlockAddress ( ) , Ty , N -> getOffset ( ) , Flags ) ;


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> BlockAddressSDNode * N = cast < BlockAddressSDNode > ( Op ) ;


<s> SDValue <ISA_LIT>TargetLowering :: LowerExternalSymbol ( SDValue Op , SelectionDAG & DAG ) const { ExternalSymbolSDNode * N = cast < ExternalSymbolSDNode > ( Op ) ; return getAddr ( N , DAG , false ) ;


<s> else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { const unsigned XLenInBytes = <NUM_LIT> ; const MVT XLenVT = <STR_LIT> ; ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ; unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ; const TargetRegisterClass * RC = & <STR_LIT> ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; <ISA_LIT>MachineFunctionInfo * <ISA_LIT>FI = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; int VaArgOffset , VarArgsSaveSize ; if ( ArgRegs . size ( ) == Idx ) { VaArgOffset = CCInfo . getNextStackOffset ( ) ; VarArgsSaveSize = <NUM_LIT> ; } else { VarArgsSaveSize = XLenInBytes * ( ArgRegs . size ( ) - Idx ) ; VaArgOffset = - VarArgsSaveSize ; } int FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; <ISA_LIT>FI -> setVarArgsFrameIndex ( FI ) ; for ( unsigned I = Idx ; I < ArgRegs . size ( ) ; ++ I , VaArgOffset += XLenInBytes ) { const Register Reg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( ArgRegs [ I ] , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , DL , Reg , XLenVT ) ; FI = MFI . CreateFixedObject ( XLenInBytes , VaArgOffset , true ) ; SDValue PtrOff = DAG . getFrameIndex ( FI , getPointerTy ( DAG . getDataLayout ( ) ) ) ; SDValue Store = DAG . getStore ( Chain , DL , ArgValue , PtrOff , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; cast < StoreSDNode > ( Store . getNode ( ) ) -> getMemOperand ( ) -> setValue ( ( Value * ) nullptr ) ; OutChains . push_back ( Store ) ; } <ISA_LIT>FI -> setVarArgsSaveSize ( VarArgsSaveSize ) ; } if ( ! OutChains . empty ( ) ) { OutChains . push_back ( Chain ) ; Chain = DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , OutChains ) ;


<s> default : report_fatal_error ( <STR_LIT> ) ; case CallingConv :: C : case CallingConv :: Fast : break ; } MachineFunction & MF = DAG . getMachineFunction ( ) ; std :: vector < SDValue > OutChains ; SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , IsVarArg , MF , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AnalyzeFormalArguments ( Ins , CCAssignFnForCall ( CallConv , IsVarArg ) ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; SDValue ArgValue ; bool IsF64On<ISA_LIT> = VA . getLocVT ( ) == <STR_LIT> && VA . getValVT ( ) == <STR_LIT> ; if ( IsF64On<ISA_LIT> ) ArgValue = unpack64 ( DAG , Chain , VA , DL ) ; else if ( VA . isRegLoc ( ) ) ArgValue = unpackFromRegLoc ( Subtarget , DAG , Chain , VA , DL ) ; else ArgValue = unpackFromMemLoc ( DAG , Chain , VA , DL ) ; InVals . push_back ( ArgValue ) ; } if ( IsVarArg ) { const unsigned XLenInBytes = <NUM_LIT> ; const MVT XLenVT = <STR_LIT> ; ArrayRef < MCPhysReg > ArgRegs = makeArrayRef ( GPRArgRegs ) ;

unsigned Idx = CCInfo . getFirstUnallocated ( ArgRegs ) ;


<s> const <ISA_LIT>RegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Register FrameReg = RI . getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ;

while ( Depth -- ) FrameAddr = DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , FrameAddr , MachinePointerInfo ( ) ) ;


<s> MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setFrameAddressIsTaken ( true ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; Register FrameReg = RI . getFrameRegister ( MF ) ; SDValue FrameAddr = DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , FrameReg , VT ) ;


<s> SDValue Addr = getAddr < GlobalAddressSDNode , false > ( N , DAG , IsLocal ) ; if ( Offset != <NUM_LIT> ) return DAG . getNode ( <STR_LIT> , DL , Ty , Addr , DAG . getConstant ( Offset , DL , <STR_LIT> ) ) ; return Addr ;


<s> MVT XLenVT = <STR_LIT> ; TLSModel :: Model Model = getTargetMachine ( ) . getTLSModel ( N -> getGlobal ( ) ) ; SDValue Addr ; switch ( Model ) { case TLSModel :: LocalExec : Addr = getStaticTLSAddr ( N , DAG , false ) ; break ; case TLSModel :: InitialExec : Addr = getStaticTLSAddr ( N , DAG , true ) ; break ; case TLSModel :: LocalDynamic : case TLSModel :: GeneralDynamic : Addr = getDynamicTLSAddr ( N , DAG ) ;


<s> return getAddr < JumpTableSDNode , false > ( N , DAG ) ;


<s> return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return LowerBlockAddress ( Op , DAG ) ; case <STR_LIT> : return LowerVASTART ( Op , DAG ) ; case <STR_LIT> : return LowerFRAMEADDR ( Op , DAG ) ;


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Split64 = DAG . getNode ( <STR_LIT> , DL , DAG . getVTList ( <STR_LIT> , <STR_LIT> ) , Val ) ; SDValue Lo = Split64 . getValue ( <NUM_LIT> ) ; SDValue Hi = Split64 . getValue ( <NUM_LIT> ) ; Register RegLo = VA . getLocReg ( ) ; assert ( RegLo < <STR_LIT> && <STR_LIT> ) ; Register RegHi = RegLo + <NUM_LIT> ; Chain = DAG . getCopyToReg ( Chain , DL , RegLo , Lo , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegLo , <STR_LIT> ) ) ; Chain = DAG . getCopyToReg ( Chain , DL , RegHi , Hi , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( RegHi , <STR_LIT> ) ) ; } else { Val = convertValVTToLocVT ( DAG , Val , VA , DL ) ; Chain = DAG . getCopyToReg ( Chain , DL , VA . getLocReg ( ) , Val , Glue ) ; Glue = Chain . getValue ( <NUM_LIT> ) ; RetOps . push_back ( DAG . getRegister ( VA . getLocReg ( ) , VA . getLocVT ( ) ) ) ; } } RetOps [ <NUM_LIT> ] = Chain ; if ( Glue . getNode ( ) ) { RetOps . push_back ( Glue ) ;


<s> const <ISA_LIT>RegisterInfo & RI = * Subtarget . getRegisterInfo ( ) ; MachineFunction & MF = DAG . getMachineFunction ( ) ; MachineFrameInfo & MFI = MF . getFrameInfo ( ) ; MFI . setReturnAddressIsTaken ( true ) ; if ( verifyReturnAddressArgumentIsConstant ( Op , DAG ) ) return SDValue ( ) ; EVT VT = Op . getValueType ( ) ; SDLoc dl ( Op ) ; unsigned Depth = cast < ConstantSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getZExtValue ( ) ; if ( Depth ) { SDValue FrameAddr = LowerFRAMEADDR ( Op , DAG ) ; SDValue Offset = DAG . getConstant ( <NUM_LIT> , dl , <STR_LIT> ) ; return DAG . getLoad ( VT , dl , DAG . getEntryNode ( ) , DAG . getNode ( <STR_LIT> , dl , VT , FrameAddr , Offset ) , MachinePointerInfo ( ) ) ; } unsigned Reg = MF . addLiveIn ( RI . getRARegister ( ) , getRegClassFor ( <STR_LIT> ) ) ;

return DAG . getCopyFromReg ( DAG . getEntryNode ( ) , dl , Reg , VT ) ;


<s> <ISA_LIT>MachineFunctionInfo * FuncInfo = MF . getInfo < <ISA_LIT>MachineFunctionInfo > ( ) ; SDLoc DL ( Op ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( MF . getDataLayout ( ) ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ;

return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FI , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> SDLoc DL ( Op ) ; SDValue FI = DAG . getFrameIndex ( FuncInfo -> getVarArgsFrameIndex ( ) , getPointerTy ( MF . getDataLayout ( ) ) ) ; const Value * SV = cast < SrcValueSDNode > ( Op . getOperand ( <NUM_LIT> ) ) -> getValue ( ) ; return DAG . getStore ( Op . getOperand ( <NUM_LIT> ) , DL , FI , Op . getOperand ( <NUM_LIT> ) , MachinePointerInfo ( SV ) ) ;


<s> assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Register LoVReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , LoVReg ) ; SDValue Lo = DAG . getCopyFromReg ( Chain , DL , LoVReg , <STR_LIT> ) ; SDValue Hi ; if ( VA . getLocReg ( ) == <STR_LIT> ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , <NUM_LIT> , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; Hi = DAG . getLoad ( <STR_LIT> , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } else { Register HiVReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) + <NUM_LIT> , HiVReg ) ; Hi = DAG . getCopyFromReg ( Chain , DL , HiVReg , <STR_LIT> ) ;


<s> MachineRegisterInfo & RegInfo = MF . getRegInfo ( ) ; if ( VA . isMemLoc ( ) ) { int FI = MFI . CreateFixedObject ( <NUM_LIT> , VA . getLocMemOffset ( ) , true ) ; SDValue FIN = DAG . getFrameIndex ( FI , <STR_LIT> ) ; return DAG . getLoad ( VA . getValVT ( ) , DL , Chain , FIN , MachinePointerInfo :: getFixedStack ( MF , FI ) ) ; } assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; Register LoVReg = RegInfo . createVirtualRegister ( & <STR_LIT> ) ;

RegInfo . addLiveIn ( VA . getLocReg ( ) , LoVReg ) ;


<s> break ; case <STR_LIT> : RC = Subtarget . hasFPUv2SingleFloat ( ) ? & <STR_LIT> : & <STR_LIT> ; break ; case <STR_LIT> : RC = Subtarget . hasFPUv2DoubleFloat ( ) ? & <STR_LIT> : & <STR_LIT> ; break ; } Register VReg = RegInfo . createVirtualRegister ( RC ) ; RegInfo . addLiveIn ( VA . getLocReg ( ) , VReg ) ; Val = DAG . getCopyFromReg ( Chain , DL , VReg , LocVT ) ;


<s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & ) {


<s> <ISA_LIT>MachineFunctionInfo ( MachineFunction & MF ) : MF ( MF ) {


<s> bool isCRSpilled ( ) const { return SpillsCR ;


<s> void setVarArgsFrameIndex ( int v ) {


<s> void setVarArgsSaveSize ( int Size ) {


<s> CommentString = <STR_LIT> ; ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> <ISA_LIT>MCAsmInfo :: <ISA_LIT>MCAsmInfo ( const Triple & TargetTriple ) { AlignmentIsInBytes = false ; SupportsDebugInformation = true ; CommentString = <STR_LIT> ;

ExceptionsType = ExceptionHandling :: DwarfCFI ;


<s> void <ISA_LIT>MCAsmInfo :: anchor ( ) {


<s> SupportsDebugInformation = true ; CommentString = <STR_LIT> ;


<s> break ; case <STR_LIT> : TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; break ; case <STR_LIT> : TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) ; break ; case <STR_LIT> : TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) ; break ; case <STR_LIT> : TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> - MI . getOperand ( <NUM_LIT> ) . getImm ( ) ) ; break ; case <STR_LIT> : auto V = <NUM_LIT> << MI . getOperand ( <NUM_LIT> ) . getImm ( ) ; TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( V ) ; break ;


<s> uint32_t Binary ; TmpInst = MCInstBuilder ( MI . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; writeData ( Binary , <NUM_LIT> , OS ) ; if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; Fixups [ Fixups . size ( ) - <NUM_LIT> ] . setOffset ( <NUM_LIT> ) ; writeData ( Binary , <NUM_LIT> , OS ) ;


<s> if ( ! STI . getFeatureBits ( ) [ <STR_LIT> ] ) TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; else TmpInst = MCInstBuilder ( <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; Fixups [ Fixups . size ( ) - <NUM_LIT> ] . setOffset ( <NUM_LIT> ) ;


<s> MCInst TmpInst ; uint32_t Binary ; unsigned Size = MI . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; writeData ( Binary , Size , OS ) ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;


<s> void <ISA_LIT>MCCodeEmitter :: expandNEG ( const MCInst & MI , raw_ostream & OS , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { MCInst TmpInst ; uint32_t Binary ; unsigned Size = MI . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ;

Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;


<s> uint32_t Binary ; unsigned Size = MI . getOpcode ( ) == <STR_LIT> ? <NUM_LIT> : <NUM_LIT> ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; writeData ( Binary , Size , OS ) ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ;


<s> TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) ; Binary = getBinaryCodeForInstr ( TmpInst , Fixups , STI ) ; writeData ( Binary , Size , OS ) ; TmpInst = MCInstBuilder ( Size == <NUM_LIT> ? <STR_LIT> : <STR_LIT> ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addOperand ( MI . getOperand ( <NUM_LIT> ) ) . addImm ( MI . getOperand ( <NUM_LIT> ) . getImm ( ) + <NUM_LIT> ) ;


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ;


<s> uint16_t HI16 = static_cast < uint16_t > ( Bin >> <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) <STR_LIT> :: write < uint16_t > ( OS , HI16 , <STR_LIT> ) ; <STR_LIT> :: write < uint16_t > ( OS , LO16 , <STR_LIT> ) ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR : return MCFixupKind ( <STR_LIT> ) ; }


<s> MCCodeEmitter * llvm :: create<ISA_LIT>MCCodeEmitter ( const MCInstrInfo & MCII , const MCRegisterInfo & MRI , MCContext & Ctx ) { return new <ISA_LIT>MCCodeEmitter ( Ctx , MCII ) ;


<s> <ISA_LIT>MCCodeEmitter ( MCContext & Ctx , const MCInstrInfo & MII ) : Ctx ( Ctx ) , MII ( MII ) {


<s> unsigned Size = Desc . getSize ( ) ; ++ MCNumEmitted ; uint32_t Bin = getBinaryCodeForInstr ( MI , Fixups , STI ) ; uint16_t LO16 = static_cast < uint16_t > ( Bin ) ; uint16_t HI16 = static_cast < uint16_t > ( Bin >> <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) <STR_LIT> :: write < uint16_t > ( OS , HI16 , <STR_LIT> ) ; <STR_LIT> :: write < uint16_t > ( OS , LO16 , <STR_LIT> ) ;


<s> const MCOperand & MO = MI . getOperand ( Idx ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ;

if ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: Target ) Kind = getTargetFixup ( MO . getExpr ( ) ) ;


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( FIXUP ) ;


<s> unsigned getCallSymbolOpValue ( const MCInst & MI , unsigned Idx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { const MCOperand & MO = MI . getOperand ( Idx ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ;


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( <STR_LIT> ) ; if ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: Target ) Kind = getTargetFixup ( MO . getExpr ( ) ) ;

Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ;


<s> assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = MCFixupKind ( FIXUP ) ; if ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: Target ) Kind = getTargetFixup ( MO . getExpr ( ) ) ;


<s> MCFixupKind Kind = MCFixupKind ( FIXUP ) ; if ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: Target ) Kind = getTargetFixup ( MO . getExpr ( ) ) ;


<s> MCFixupKind Kind = MCFixupKind ( FIXUP ) ; if ( MO . getExpr ( ) -> getKind ( ) == MCExpr :: Target ) Kind = getTargetFixup ( MO . getExpr ( ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ;


<s> if ( MI . getOperand ( Idx ) . getImm ( ) == <NUM_LIT> ) return <NUM_LIT> ; else if ( MI . getOperand ( Idx ) . getImm ( ) == <NUM_LIT> ) return <NUM_LIT> ; else if ( MI . getOperand ( Idx ) . getImm ( ) == <NUM_LIT> ) return <NUM_LIT> ; else if ( MI . getOperand ( Idx ) . getImm ( ) == <NUM_LIT> ) return <NUM_LIT> ;


<s> unsigned <ISA_LIT>MCCodeEmitter :: getImmJMPIX ( const MCInst & MI , unsigned Idx , SmallVectorImpl < MCFixup > & Fixups , const MCSubtargetInfo & STI ) const { if ( MI . getOperand ( Idx ) . getImm ( ) == <NUM_LIT> ) return <NUM_LIT> ;

else if ( MI . getOperand ( Idx ) . getImm ( ) == <NUM_LIT> ) return <NUM_LIT> ;


<s> if ( MO . isImm ( ) ) return ( MO . getImm ( ) >> shift ) ; assert ( MO . isExpr ( ) && <STR_LIT> ) ; MCFixupKind Kind = getTargetFixup ( MO . getExpr ( ) ) ; Fixups . push_back ( MCFixup :: create ( <NUM_LIT> , MO . getExpr ( ) , Kind , MI . getLoc ( ) ) ) ;


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; auto V = ( MO . getImm ( ) <= <NUM_LIT> ) ? <NUM_LIT> : MO . getImm ( ) ;


<s> assert ( MSB . isImm ( ) && LSB . isImm ( ) && <STR_LIT> ) ;

return MSB . getImm ( ) - LSB . getImm ( ) ;


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; return <NUM_LIT> << MO . getImm ( ) ;


<s> if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ; llvm_unreachable ( <STR_LIT> ) ;


<s> if ( MO . isReg ( ) ) return Ctx . getRegisterInfo ( ) -> getEncodingValue ( MO . getReg ( ) ) ; if ( MO . isImm ( ) ) return static_cast < unsigned > ( MO . getImm ( ) ) ;


<s> assert ( MO . isImm ( ) && <STR_LIT> ) ; return MO . getImm ( ) - <NUM_LIT> ;


<s> const MCOperand & MO = MI . getOperand ( Idx ) ; assert ( MO . isImm ( ) && <STR_LIT> ) ;


<s> unsigned Reg2 = Ctx . getRegisterInfo ( ) -> getEncodingValue ( MI . getOperand ( Op + <NUM_LIT> ) . getReg ( ) ) ; unsigned Binary = ( ( Reg1 & <NUM_LIT> ) << <NUM_LIT> ) | ( Reg2 - Reg1 ) ; return Binary ;


<s> unsigned Ry = MI . getOperand ( Idx ) . getReg ( ) ; unsigned Rz = MI . getOperand ( Idx + <NUM_LIT> ) . getImm ( ) ;

unsigned Imm = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Rz ) - Ctx . getRegisterInfo ( ) -> getEncodingValue ( Ry ) ;


<s> unsigned Imm = Ctx . getRegisterInfo ( ) -> getEncodingValue ( Rz ) - Ctx . getRegisterInfo ( ) -> getEncodingValue ( Ry ) ; return ( ( Ctx . getRegisterInfo ( ) -> getEncodingValue ( Ry ) << <NUM_LIT> ) | Imm ) ;


<s> const <ISA_LIT>MCExpr * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Expr ) ; switch ( <ISA_LIT>Expr -> getKind ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR : return MCFixupKind ( <STR_LIT> ) ; case <ISA_LIT>MCExpr :: VK_<ISA_LIT>_ADDR_HI16 : return MCFixupKind ( <STR_LIT> ) ;


<s> uint16_t HI16 = static_cast < uint16_t > ( Bin >> <NUM_LIT> ) ; if ( Size == <NUM_LIT> ) <STR_LIT> :: write < uint16_t > ( OS , HI16 , <STR_LIT> ) ; <STR_LIT> :: write < uint16_t > ( OS , LO16 , <STR_LIT> ) ;


<s> default : return true ; case VK_<ISA_LIT>_ADDR : case VK_<ISA_LIT>_PCREL : case VK_<ISA_LIT>_GOT : case VK_<ISA_LIT>_GOTPC : case VK_<ISA_LIT>_GOTOFF : case VK_<ISA_LIT>_TPOFF : case VK_<ISA_LIT>_TLSGD : return false ; } }


<s> bool <ISA_LIT>MCExpr :: evaluateAsRelocatableImpl ( MCValue & Res , const MCAsmLayout * Layout , const MCFixup * Fixup ) const { if ( ! getSubExpr ( ) -> evaluateAsRelocatable ( Res , Layout , Fixup ) ) return false ; if ( Res . getSymA ( ) && Res . getSymB ( ) ) { switch ( getKind ( ) ) { default : return true ; case VK_<ISA_LIT>_ADDR : case VK_<ISA_LIT>_PCREL :


<s> void <ISA_LIT>MCExpr :: fixELFSymbolsInTLSFixups ( MCAssembler & Asm ) const { switch ( getKind ( ) ) { default : return ; case VK_<ISA_LIT>_TPOFF : case VK_<ISA_LIT>_TLSGD : break ;


<s> switch ( Kind ) { default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_ADDR : return <STR_LIT> ; case VK_<ISA_LIT>_PCREL : return <STR_LIT> ; case VK_<ISA_LIT>_GOT : return <STR_LIT> ; case VK_<ISA_LIT>_GOTPC : return <STR_LIT> ; case VK_<ISA_LIT>_GOTOFF : return <STR_LIT> ; case VK_<ISA_LIT>_PLT : return <STR_LIT> ; case VK_<ISA_LIT>_TPOFF : return <STR_LIT> ; case VK_<ISA_LIT>_TLSGD :


<s> return <STR_LIT> ; case VK_<ISA_LIT>_GOT : return <STR_LIT> ; case VK_<ISA_LIT>_GOTPC : return <STR_LIT> ; case VK_<ISA_LIT>_GOTOFF : return <STR_LIT> ; case VK_<ISA_LIT>_PLT : return <STR_LIT> ; case VK_<ISA_LIT>_TPOFF : return <STR_LIT> ; case VK_<ISA_LIT>_TLSGD : return <STR_LIT> ; }


<s> return E -> getKind ( ) == MCExpr :: Target ;


<s> static bool classof ( const MCExpr * E ) { return E -> getKind ( ) == MCExpr :: Target ;


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) { return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr ) ;


<s> const <ISA_LIT>MCExpr * <ISA_LIT>MCExpr :: create ( const MCExpr * Expr , VariantKind Kind , MCContext & Ctx ) {

return new ( Ctx ) <ISA_LIT>MCExpr ( Kind , Expr ) ;


<s> explicit <ISA_LIT>MCExpr ( VariantKind Kind , const MCExpr * Expr ) : Kind ( Kind ) , Expr ( Expr ) {


<s> MCFragment * findAssociatedFragment ( ) const override {

return getSubExpr ( ) -> findAssociatedFragment ( ) ;


<s> default : return ; case VK_<ISA_LIT>_TLSLE : case VK_<ISA_LIT>_TLSIE : case VK_<ISA_LIT>_TLSGD : break ;


<s> switch ( getKind ( ) ) { default : return ; case VK_<ISA_LIT>_TLSLE : case VK_<ISA_LIT>_TLSIE : case VK_<ISA_LIT>_TLSGD : break ;


<s> break ; case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ; break ; } case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; break ;


<s> case MCExpr :: Binary : { const MCBinaryExpr * BE = cast < MCBinaryExpr > ( Expr ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getLHS ( ) , Asm ) ; fixELFSymbolsInTLSFixupsImpl ( BE -> getRHS ( ) , Asm ) ; break ; } case MCExpr :: SymbolRef : { const MCSymbolRefExpr & SymRef = * cast < MCSymbolRefExpr > ( Expr ) ; cast < MCSymbolELF > ( SymRef . getSymbol ( ) ) . setType ( ELF :: STT_TLS ) ; break ; } case MCExpr :: Unary : fixELFSymbolsInTLSFixupsImpl ( cast < MCUnaryExpr > ( Expr ) -> getSubExpr ( ) , Asm ) ; break ; }


<s> const MCExpr * getSubExpr ( ) const { return Expr ;


<s> default : llvm_unreachable ( <STR_LIT> ) ; case VK_<ISA_LIT>_None : case VK_<ISA_LIT>_ADDR : return <STR_LIT> ; case VK_<ISA_LIT>_ADDR_HI16 : return <STR_LIT> ; case VK_<ISA_LIT>_ADDR_LO16 : return <STR_LIT> ; case VK_<ISA_LIT>_GOT_IMM18_BY4 : case VK_<ISA_LIT>_GOT : return <STR_LIT> ; case VK_<ISA_LIT>_GOTPC : return <STR_LIT> ; case VK_<ISA_LIT>_GOTOFF : return <STR_LIT> ; case VK_<ISA_LIT>_PLT_IMM18_BY4 : case VK_<ISA_LIT>_PLT : return <STR_LIT> ; case VK_<ISA_LIT>_TLSLE : return <STR_LIT> ; case VK_<ISA_LIT>_TLSIE :


<s> case VK_<ISA_LIT>_GOTPC : return <STR_LIT> ; case VK_<ISA_LIT>_GOTOFF : return <STR_LIT> ; case VK_<ISA_LIT>_PLT_IMM18_BY4 : case VK_<ISA_LIT>_PLT : return <STR_LIT> ; case VK_<ISA_LIT>_TLSLE : return <STR_LIT> ; case VK_<ISA_LIT>_TLSIE : return <STR_LIT> ; case VK_<ISA_LIT>_TLSGD :


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { Expr -> print ( OS , MAI ) ;

OS << getVariantKindName ( getKind ( ) ) ;


<s> void <ISA_LIT>MCExpr :: printImpl ( raw_ostream & OS , const MCAsmInfo * MAI ) const { Expr -> print ( OS , MAI ) ; OS << getVariantKindName ( getKind ( ) ) ;


<s> void <ISA_LIT>MCExpr :: visitUsedExpr ( MCStreamer & Streamer ) const { Streamer . visitUsedExpr ( * getSubExpr ( ) ) ;


<s> <ISA_LIT>MCInstLower :: <ISA_LIT>MCInstLower ( MCContext & Ctx , AsmPrinter & Printer ) : Ctx ( Ctx ) , Printer ( Printer ) {


<s> for ( const MachineOperand & MO : MI -> operands ( ) ) { MCOperand MCOp ; if ( lowerOperand ( MO , MCOp ) ) OutMI . addOperand ( MCOp ) ;


<s> void <ISA_LIT>MCInstLower :: Lower ( const MachineInstr * MI , MCInst & OutMI ) const {

OutMI . setOpcode ( MI -> getOpcode ( ) ) ;


<s> break ; case MachineOperand :: MO_MachineBasicBlock : MCOp = MCOperand :: createExpr ( MCSymbolRefExpr :: create ( MO . getMBB ( ) -> getSymbol ( ) , Ctx ) ) ; break ; case MachineOperand :: MO_GlobalAddress : MCOp = lowerSymbolOperand ( MO , Printer . getSymbol ( MO . getGlobal ( ) ) ) ; break ; case MachineOperand :: MO_BlockAddress : MCOp = lowerSymbolOperand ( MO , Printer . GetBlockAddressSymbol ( MO . getBlockAddress ( ) ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : MCOp = lowerSymbolOperand ( MO , Printer . GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : MCOp = lowerSymbolOperand ( MO , Printer . GetCPISymbol ( MO . getIndex ( ) ) ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( <ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( <ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( <ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( <ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( <ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( <ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( <ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ;

TargetRegistry :: RegisterMCCodeEmitter ( <ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ;


<s> TargetRegistry :: RegisterMCAsmInfo ( <ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( <ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( <ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( <ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ;


<s> static MCTargetStreamer * create<ISA_LIT>AsmTargetStreamer ( MCStreamer & S , formatted_raw_ostream & OS , MCInstPrinter * InstPrinter , bool isVerboseAsm ) { return new <ISA_LIT>TargetAsmStreamer ( S , OS ) ;


<s> return new <ISA_LIT>TargetAsmStreamer ( S , OS ) ;


<s> static MCInstrAnalysis * create<ISA_LIT>InstrAnalysis ( const MCInstrInfo * Info ) {

return new <ISA_LIT>MCInstrAnalysis ( Info ) ;


<s> return new <ISA_LIT>MCInstrAnalysis ( Info ) ;


<s> unsigned Reg = MRI . getDwarfRegNum ( <STR_LIT> , true ) ; MCCFIInstruction Inst = MCCFIInstruction :: cfiDefCfa ( nullptr , Reg , <NUM_LIT> ) ; MAI -> addInitialFrameState ( Inst ) ; return MAI ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) { return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> static MCInstPrinter * create<ISA_LIT>MCInstPrinter ( const Triple & T , unsigned SyntaxVariant , const MCAsmInfo & MAI , const MCInstrInfo & MII , const MCRegisterInfo & MRI ) {

return new <ISA_LIT>InstPrinter ( MAI , MII , MRI ) ;


<s> static MCInstrInfo * create<ISA_LIT>MCInstrInfo ( ) { MCInstrInfo * Info = new MCInstrInfo ( ) ; Init<ISA_LIT>MCInstrInfo ( Info ) ;


<s> static MCRegisterInfo * create<ISA_LIT>MCRegisterInfo ( const Triple & TT ) { MCRegisterInfo * Info = new MCRegisterInfo ( ) ; Init<ISA_LIT>MCRegisterInfo ( Info , <STR_LIT> ) ; return Info ;


<s> std :: string CPUName = std :: string ( CPU ) ;

if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ;


<s> static MCSubtargetInfo * create<ISA_LIT>MCSubtargetInfo ( const Triple & TT , StringRef CPU , StringRef FS ) { std :: string CPUName = std :: string ( CPU ) ;


<s> static MCTargetStreamer * create<ISA_LIT>NullTargetStreamer ( MCStreamer & S ) { return new <ISA_LIT>TargetStreamer ( S ) ;


<s> static MCTargetStreamer * create<ISA_LIT>ObjectTargetStreamer ( MCStreamer & S , const MCSubtargetInfo & STI ) {

const Triple & TT = STI . getTargetTriple ( ) ;


<s> <ISA_LIT>ELFStreamer * S = new <ISA_LIT>ELFStreamer ( Ctx , std :: move ( MAB ) , std :: move ( OW ) , std :: move ( Emitter ) ) ; if ( RelaxAll ) S -> getAssembler ( ) . setRelaxAll ( true ) ; return S ;


<s> explicit <ISA_LIT>MCInstrAnalysis ( const MCInstrInfo * Info ) : MCInstrAnalysis ( Info ) {


<s> if ( isConditionalBranch ( Inst ) || isUnconditionalBranch ( Inst ) ) { int64_t Imm ; Imm = Inst . getOperand ( Inst . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ; Target = Addr + Imm ; return true ; } if ( Inst . getOpcode ( ) == <STR_LIT> ) { Target = Addr + Inst . getOperand ( <NUM_LIT> ) . getImm ( ) ; return true ; } switch ( Inst . getOpcode ( ) ) { default : return false ; case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : case <STR_LIT> : int64_t Imm = Inst . getOperand ( Inst . getNumOperands ( ) - <NUM_LIT> ) . getImm ( ) ; Target = ( ( Addr + Imm ) & <NUM_LIT> ) ; return true ; } return false ;


<s> TargetRegistry :: RegisterObjectTargetStreamer ( <ISA_LIT>Target , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( <ISA_LIT>Target , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( <ISA_LIT>Target , create<ISA_LIT>NullTargetStreamer ) ; TargetRegistry :: RegisterMCInstrAnalysis ( <ISA_LIT>Target , create<ISA_LIT>InstrAnalysis ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetMC ( ) { auto & <ISA_LIT>Target = getThe<ISA_LIT>Target ( ) ; TargetRegistry :: RegisterMCAsmBackend ( <ISA_LIT>Target , create<ISA_LIT>AsmBackend ) ; TargetRegistry :: RegisterMCAsmInfo ( <ISA_LIT>Target , create<ISA_LIT>MCAsmInfo ) ; TargetRegistry :: RegisterMCInstrInfo ( <ISA_LIT>Target , create<ISA_LIT>MCInstrInfo ) ; TargetRegistry :: RegisterMCRegInfo ( <ISA_LIT>Target , create<ISA_LIT>MCRegisterInfo ) ; TargetRegistry :: RegisterMCCodeEmitter ( <ISA_LIT>Target , create<ISA_LIT>MCCodeEmitter ) ; TargetRegistry :: RegisterMCInstPrinter ( <ISA_LIT>Target , create<ISA_LIT>MCInstPrinter ) ; TargetRegistry :: RegisterMCSubtargetInfo ( <ISA_LIT>Target , create<ISA_LIT>MCSubtargetInfo ) ; TargetRegistry :: RegisterELFStreamer ( <ISA_LIT>Target , createELFStreamer ) ; TargetRegistry :: RegisterObjectTargetStreamer ( <ISA_LIT>Target , create<ISA_LIT>ObjectTargetStreamer ) ; TargetRegistry :: RegisterAsmTargetStreamer ( <ISA_LIT>Target , create<ISA_LIT>AsmTargetStreamer ) ; TargetRegistry :: RegisterNullTargetStreamer ( <ISA_LIT>Target , create<ISA_LIT>NullTargetStreamer ) ;

TargetRegistry :: RegisterMCInstrAnalysis ( <ISA_LIT>Target , create<ISA_LIT>InstrAnalysis ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { if ( STI . hasFPUv3DoubleFloat ( ) ) return CSR_GPR_FPR64v3_ISR_SaveList ; if ( STI . hasFPUv3SingleFloat ( ) ) return CSR_GPR_FPR32v3_ISR_SaveList ; if ( STI . hasFPUv2DoubleFloat ( ) ) return CSR_GPR_FPR64_ISR_SaveList ; if ( STI . hasFPUv2SingleFloat ( ) ) return CSR_GPR_FPR32_ISR_SaveList ; return CSR_GPR_ISR_SaveList ; } if ( STI . hasFPUv2DoubleFloat ( ) || STI . hasFPUv3DoubleFloat ( ) ) return CSR_GPR_FPR64_SaveList ; if ( STI . hasFPUv2SingleFloat ( ) || STI . hasFPUv3SingleFloat ( ) ) return CSR_GPR_FPR32_SaveList ; return CSR_I32_SaveList ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID Id ) const { const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;

if ( STI . hasFPUv2DoubleFloat ( ) || STI . hasFPUv3DoubleFloat ( ) ) return CSR_GPR_FPR64_RegMask ;


<s> } if ( MI -> getOpcode ( ) == <STR_LIT> ) return false ; if ( Offset < <NUM_LIT> ) return false ; unsigned NumBits = <NUM_LIT> ; unsigned Scale = <NUM_LIT> ; switch ( AddrMode ) { case <STR_LIT> : Scale = <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> : Scale = <NUM_LIT> ; NumBits = <NUM_LIT> ; break ; case <STR_LIT> :


<s> bool requiresFrameIndexScavenging ( const MachineFunction & MF ) const override { return true ;


<s> bool requiresRegisterScavenging ( const MachineFunction & MF ) const override { return true ;


<s> MI = Temp ; MBB . erase ( II ) ; break ; } case <STR_LIT> : { Register NewReg ; if ( STI . hasE2 ( ) ) { NewReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , NewReg ) . add ( MI -> getOperand ( <NUM_LIT> ) ) ; } else { NewReg = MRI . createVirtualRegister ( & <STR_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , NewReg ) . addImm ( <NUM_LIT> ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) ) . addReg ( NewReg , RegState :: Define ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) , RegState :: Define ) . addReg ( NewReg , getKillRegState ( true ) ) . addReg ( NewReg , getKillRegState ( true ) ) . addReg ( MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) ; BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) , MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ) . addReg ( NewReg ) . addImm ( <NUM_LIT> ) ; } MI = BuildMI ( MBB , II , DL , TII -> get ( <STR_LIT> ) ) . addReg ( NewReg , getKillRegState ( true ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . add ( MI -> getOperand ( <NUM_LIT> ) ) . getInstr ( ) ; MBB . erase ( II ) ; break ; } } int FrameIndex = MI -> getOperand ( FIOperandNum ) . getIndex ( ) ; Register FrameReg ; int Offset = getFrameLowering ( MF ) -> getFrameIndexReference ( MF , FrameIndex , FrameReg ) . getFixed ( ) + MI -> getOperand ( FIOperandNum + <NUM_LIT> ) . getImm ( ) ; if ( ! isInt < <NUM_LIT> > ( Offset ) ) report_fatal_error ( <STR_LIT> ) ; bool FrameRegIsKill = false ; MachineBasicBlock :: iterator NewII ( MI ) ; if ( ! IsLegalOffset ( TII , MI , Offset ) ) { assert ( isInt < <NUM_LIT> > ( Offset ) && <STR_LIT> ) ; assert ( Offset >= <NUM_LIT> ) ; Register ScratchReg = TII -> movImm ( MBB , NewII , DL , Offset ) ; BuildMI ( MBB , NewII , DL , TII -> get ( STI . hasE2 ( ) ? <STR_LIT> : <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( FrameReg ) ; Offset = <NUM_LIT> ; FrameReg = ScratchReg ;


<s> assert ( SPAdj == <NUM_LIT> && <STR_LIT> ) ;


<s> const MCPhysReg * <ISA_LIT>RegisterInfo :: getCalleeSavedRegs ( const MachineFunction * MF ) const { const <ISA_LIT>Subtarget & STI = MF -> getSubtarget < <ISA_LIT>Subtarget > ( ) ; if ( MF -> getFunction ( ) . hasFnAttribute ( <STR_LIT> ) ) { return CSR_GPR_ISR_SaveList ; } return CSR_I32_SaveList ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getCallPreservedMask ( const MachineFunction & MF , CallingConv :: ID Id ) const {

const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ;


<s> const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; return CSR_I32_RegMask ;


<s> return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getNoPreservedMask ( ) const {


<s> const uint32_t * <ISA_LIT>RegisterInfo :: getNoPreservedMask ( ) const { return CSR_NoRegs_RegMask ;


<s> if ( ! STI . hasE2 ( ) ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) markSuperRegs ( Reserved , <STR_LIT> + i ) ; } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! STI . hasHighRegisters ( ) ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) markSuperRegs ( Reserved , <STR_LIT> + i ) ; } markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ; markSuperRegs ( Reserved , <STR_LIT> ) ;

assert ( checkAllSuperRegsMarked ( Reserved ) ) ;


<s> BitVector <ISA_LIT>RegisterInfo :: getReservedRegs ( const MachineFunction & MF ) const { const <ISA_LIT>FrameLowering * TFI = getFrameLowering ( MF ) ; const <ISA_LIT>Subtarget & STI = MF . getSubtarget < <ISA_LIT>Subtarget > ( ) ; BitVector Reserved ( getNumRegs ( ) ) ; if ( TFI -> hasBP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( TFI -> hasFP ( MF ) ) markSuperRegs ( Reserved , <STR_LIT> ) ; if ( ! STI . hasE2 ( ) ) { for ( unsigned i = <NUM_LIT> ; i < <NUM_LIT> ; i ++ ) markSuperRegs ( Reserved , <STR_LIT> + i ) ; }


<s> return HasFPUv2SingleFloat || HasFPUv2DoubleFloat ;


<s> bool hasFPUv2DoubleFloat ( ) const {


<s> bool hasFPUv2SingleFloat ( ) const { return HasFPUv2SingleFloat ;


<s> bool hasFPUv3DoubleFloat ( ) const { return HasFPUv3DoubleFloat ;


<s> bool hasFPUv3SingleFloat ( ) const {


<s> bool hasHighRegisters ( ) const { return HasHighRegisters ;


<s> HasFPUv3HalfFloat = false ; HasFPUv3SingleFloat = false ; HasFPUv3DoubleFloat = false ; HasFdivdu = false ; HasFLOATE1 = false ; HasFLOAT1E2 = false ; HasFLOAT1E3 = false ; HasFLOAT3E4 = false ; HasFLOAT7E60 = false ; HasExtendLrw = false ; HasBTST16 = false ; HasTrust = false ; HasJAVA = false ; HasCache = false ; HasNVIC = false ; HasDSP = false ; HasDSP1E2 = false ; HasDSPE60 = false ; HasDSPV2 = false ; HasDSP_Silan = false ; HasDoloop = false ; HasHardwareDivide = false ; HasHighRegisters = false ; HasVDSPV2 = false ; HasVDSP2E3 = false ; HasVDSP2E60F = false ; ReadTPHard = false ; HasVDSPV1_128 = false ; UseCCRT = false ; DumpConstPool = false ;


<s> if ( FloatABI == FloatABI :: Default ) return UseHardFloatABI ; else return FloatABI == FloatABI :: Hard ;


<s> auto FloatABI = getTargetLowering ( ) -> getTargetMachine ( ) . Options . FloatABIType ; if ( FloatABI == FloatABI :: Default ) return UseHardFloatABI ; else return FloatABI == FloatABI :: Hard ;


<s> bool hasFLOAT1E3 ( ) const { return HasFLOAT1E3 ;


<s> bool hasFLOATE1 ( ) const { return HasFLOATE1 ;


<s> bool hasFPUv3HalfFloat ( ) const { return HasFPUv3HalfFloat ;


<s> bool hasSTM ( ) const { return HasSTM ;


return HasVDSPV2 && UseHardFloat && HasFPUv3HalfFloat ;


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; UseHardFloat = false ; UseHardFloatABI = false ; HasFPUv2SingleFloat = false ; HasFPUv2DoubleFloat = false ; HasFPUv3SingleFloat = false ; HasFPUv3DoubleFloat = false ; HasBTST16 = false ; HasJAVA = false ; HasExtendLrw = false ; HasDoloop = false ; HasHighRegisters = false ;


<s> return <ISA_LIT>ProcFamily == CK802 ;


<s> bool isCK803 ( ) const { return <ISA_LIT>ProcFamily == CK803 ;


<s> bool isCK804 ( ) const { return <ISA_LIT>ProcFamily == CK804 ;


<s> return <ISA_LIT>ProcFamily == CK805 ;


<s> bool isCK805 ( ) const { return <ISA_LIT>ProcFamily == CK805 ;


<s> bool isCK810 ( ) const { return <ISA_LIT>ProcFamily == CK810 ;


<s> return <ISA_LIT>ProcFamily == CK810V ;


<s> bool isCK860 ( ) const { return <ISA_LIT>ProcFamily == CK860 ;


<s> bool smartMode ( ) const { return SmartMode ;


<s> void <ISA_LIT>Subtarget :: anchor ( ) {


<s> <ISA_LIT>Subtarget :: <ISA_LIT>Subtarget ( const Triple & TT , StringRef CPU , StringRef TuneCPU , StringRef FS , const TargetMachine & TM ) : <ISA_LIT>GenSubtargetInfo ( TT , CPU , TuneCPU , FS ) , FrameLowering ( initializeSubtargetDependencies ( TT , CPU , TuneCPU , FS ) ) , InstrInfo ( * this ) , RegInfo ( ) , TLInfo ( TM , * this ) {


<s> const <ISA_LIT>FrameLowering * getFrameLowering ( ) const override {


<s> const SelectionDAGTargetInfo * getSelectionDAGInfo ( ) const override {


<s> const <ISA_LIT>TargetLowering * getTargetLowering ( ) const override { return & TLInfo ;


<s> bool has10E60 ( ) const { return Has10E60 ;


<s> bool has3E3r1 ( ) const { return Has3E3r1 ;


<s> bool has3E7 ( ) const { return Has3E7 ;


<s> bool has3r1E3r2 ( ) const { return Has3r1E3r2 ;


<s> bool hasE2 ( ) const { return HasE2 ;


<s> bool hasMP1E2 ( ) const { return HasMP1E2 ;


<s> if ( CPUName . empty ( ) ) CPUName = <STR_LIT> ; if ( TuneCPUName . empty ( ) ) TuneCPUName = CPUName ; HasE1 = false ;


<s> HasE1 = false ; HasE2 = false ; Has2E3 = false ; HasMP = false ; Has3E3r1 = false ; Has3r1E3r2 = false ; Has3r2E3r3 = false ; Has3E7 = false ; HasMP1E2 = false ; Has7E10 = false ; Has10E60 = false ;

ParseSubtargetFeatures ( CPUName , TuneCPUName , FS ) ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>TargetInfo ( ) {

RegisterTarget < Triple :: csky > X ( getThe<ISA_LIT>Target ( ) , <STR_LIT> , <STR_LIT> , <STR_LIT> ) ;


<s> Target & llvm :: getThe<ISA_LIT>Target ( ) {


<s> void LLVMInitialize<ISA_LIT>TargetInfo ( ) {


<s> void LLVMInitialize<ISA_LIT>TargetMC ( ) {


<s> addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false ;


<s> bool <ISA_LIT>PassConfig :: addInstSelector ( ) { addPass ( create<ISA_LIT>ISelDag ( get<ISA_LIT>TargetMachine ( ) ) ) ; return false ;


<s> TargetPassConfig :: addIRPasses ( ) ;


<s> void <ISA_LIT>PassConfig :: addPreEmitPass ( ) { addPass ( create<ISA_LIT>ConstantIslandPass ( ) ) ;


<s> std :: string Ret ; Ret += <STR_LIT> ;


<s> TargetPassConfig * <ISA_LIT>TargetMachine :: createPassConfig ( PassManagerBase & PM ) {

return new <ISA_LIT>PassConfig ( * this , PM ) ;


<s> <ISA_LIT>PassConfig ( <ISA_LIT>TargetMachine & TM , PassManagerBase & PM ) : TargetPassConfig ( TM , PM ) {


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , RM . getValueOr ( Reloc :: Static ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < <ISA_LIT>ELFTargetObjectFile > ( ) ) { initAsmInfo ( ) ;


<s> return getTM < <ISA_LIT>TargetMachine > ( ) ;


<s> std :: string TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) . str ( ) : CPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ; std :: string Key = CPU + TuneCPU + FS ; auto & I = SubtargetMap [ Key ] ; if ( ! I ) { resetTargetOptions ( F ) ; I = std :: make_unique < <ISA_LIT>Subtarget > ( TargetTriple , CPU , TuneCPU , FS , * this ) ; if ( I -> useHardFloat ( ) && ! I -> hasAnyFloatExt ( ) ) errs ( ) << <STR_LIT> <STR_LIT> ; }


<s> Attribute FSAttr = F . getFnAttribute ( <STR_LIT> ) ; std :: string CPU = CPUAttr . isValid ( ) ? CPUAttr . getValueAsString ( ) . str ( ) : TargetCPU ; std :: string TuneCPU = TuneAttr . isValid ( ) ? TuneAttr . getValueAsString ( ) . str ( ) : CPU ; std :: string FS = FSAttr . isValid ( ) ? FSAttr . getValueAsString ( ) . str ( ) : TargetFS ;

std :: string Key = CPU + TuneCPU + FS ;


<s> LLVM_EXTERNAL_VISIBILITY void LLVMInitialize<ISA_LIT>Target ( ) { RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ; PassRegistry * Registry = PassRegistry :: getPassRegistry ( ) ; initialize<ISA_LIT>ConstantIslandsPass ( * Registry ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , RM . getValueOr ( Reloc :: Static ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) { initAsmInfo ( ) ;


<s> <ISA_LIT>TargetMachine :: <ISA_LIT>TargetMachine ( const Target & T , const Triple & TT , StringRef CPU , StringRef FS , const TargetOptions & Options , Optional < Reloc :: Model > RM , Optional < CodeModel :: Model > CM , CodeGenOpt :: Level OL , bool JIT ) : LLVMTargetMachine ( T , computeDataLayout ( TT ) , TT , CPU , FS , Options , RM . getValueOr ( Reloc :: Static ) , getEffectiveCodeModel ( CM , CodeModel :: Small ) , OL ) , TLOF ( std :: make_unique < TargetLoweringObjectFileELF > ( ) ) {


<s> RegisterTargetMachine < <ISA_LIT>TargetMachine > X ( getThe<ISA_LIT>Target ( ) ) ;


<s> void <ISA_LIT>ELFTargetObjectFile :: Initialize ( MCContext & Ctx , const TargetMachine & TM ) { TargetLoweringObjectFileELF :: Initialize ( Ctx , TM ) ; LSDAEncoding = dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ;

PersonalityEncoding = dwarf :: DW_EH_PE_indirect | dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ;


<s> LSDAEncoding = dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ; PersonalityEncoding = dwarf :: DW_EH_PE_indirect | dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ;

TTypeEncoding = dwarf :: DW_EH_PE_indirect | dwarf :: DW_EH_PE_pcrel | dwarf :: DW_EH_PE_sdata4 ;


<s> ELFRefKind = CE -> getKind ( ) ; } if ( const MCSymbolRefExpr * SymExpr = dyn_cast < MCSymbolRefExpr > ( Expr ) ) { const MCSymbol * Sym = & SymExpr -> getSymbol ( ) ; SymbolIndex Index = { Sym , ELFRefKind } ; if ( ConstantMap . find ( Index ) == ConstantMap . end ( ) ) { ConstantMap [ Index ] = ConstantPool -> addEntry ( getStreamer ( ) , OrigExpr , <NUM_LIT> , Loc , AdjustExpr ) ; } return ConstantMap [ Index ] ;


<s> if ( CurrentSection == nullptr ) CurrentSection = Streamer . getCurrentSectionOnly ( ) ; auto & Context = Streamer . getContext ( ) ; const MCConstantExpr * C = dyn_cast < MCConstantExpr > ( Value ) ; auto Itr = C ? CachedEntries . find ( C -> getValue ( ) ) : CachedEntries . end ( ) ; if ( Itr != CachedEntries . end ( ) ) return Itr -> second ; MCSymbol * CPEntryLabel = Context . createTempSymbol ( ) ; const auto SymRef = MCSymbolRefExpr :: create ( CPEntryLabel , Context ) ; if ( AdjustExpr ) {

const <ISA_LIT>MCExpr * <ISA_LIT>Expr = cast < <ISA_LIT>MCExpr > ( Value ) ;


<s> <ISA_LIT>TargetAsmStreamer ( MCStreamer & S , formatted_raw_ostream & OS ) : <ISA_LIT>TargetStreamer ( S ) , OS ( OS ) {


<s> <ISA_LIT>TargetStreamer :: <ISA_LIT>TargetStreamer ( MCStreamer & S ) : MCTargetStreamer ( S ) , ConstantPool ( new <ISA_LIT>ConstantPool ( ) ) {


<s> if ( CurrentSection != nullptr ) Streamer . SwitchSection ( CurrentSection ) ; Streamer . emitDataRegion ( MCDR_DataRegion ) ; for ( const ConstantPoolEntry & Entry : Entries ) { Streamer . emitCodeAlignment ( Entry . Size , Streamer . getContext ( ) . getSubtargetInfo ( ) ) ; Streamer . emitLabel ( Entry . Label ) ; Streamer . emitValue ( Entry . Value , Entry . Size , Entry . Loc ) ;


<s> Streamer . emitDataRegion ( MCDR_DataRegion ) ; for ( const ConstantPoolEntry & Entry : Entries ) { Streamer . emitCodeAlignment ( Entry . Size , Streamer . getContext ( ) . getSubtargetInfo ( ) ) ;

Streamer . emitLabel ( Entry . Label ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: emitAttribute ( unsigned Attribute , unsigned Value ) { OS << <STR_LIT> << Attribute << <STR_LIT> << Twine ( Value ) << <STR_LIT> ;


<s> void <ISA_LIT>TargetStreamer :: emitCurrentConstantPool ( ) { ConstantPool -> emitAll ( Streamer ) ; ConstantPool -> clearCache ( ) ;


<s> void <ISA_LIT>TargetStreamer :: emitTargetAttributes ( const MCSubtargetInfo & STI ) {


<s> bool <ISA_LIT>ConstantPool :: empty ( ) { return Entries . empty ( ) ;


<s> ConstantPool -> emitAll ( Streamer ) ; } finishAttributeSection ( ) ;


<s> void <ISA_LIT>TargetAsmStreamer :: finishAttributeSection ( ) {


<s> static inline <ISA_LIT>TargetStreamer :: SymbolIndex getEmptyKey ( ) { return { nullptr , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid } ;


<s> return hash_combine ( DenseMapInfo < const MCSymbol * > :: getHashValue ( V . sym ) , DenseMapInfo < int > :: getHashValue ( V . kind ) ) ;


<s> static inline <ISA_LIT>TargetStreamer :: SymbolIndex getTombstoneKey ( ) {

return { nullptr , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid } ;


<s> return { nullptr , <ISA_LIT>MCExpr :: VK_<ISA_LIT>_Invalid } ;


<s> return A . sym == B . sym && A . kind == B . kind ;