<s> break ; case GlobalValue :: ExternalLinkage : O << TAI -> getGlobalDirective ( ) << name << <STR_LIT> ; break ; case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage :


<s> switch ( l ) { default : llvm_unreachable ( <STR_LIT> ) ; case GlobalValue :: InternalLinkage : case GlobalValue :: PrivateLinkage : case GlobalValue :: LinkerPrivateLinkage : break ; case GlobalValue :: ExternalLinkage : O << TAI -> getGlobalDirective ( ) << name << <STR_LIT> ; break ; case GlobalValue :: LinkOnceAnyLinkage : case GlobalValue :: LinkOnceODRLinkage : case GlobalValue :: WeakAnyLinkage : case GlobalValue :: WeakODRLinkage : O << TAI -> getGlobalDirective ( ) << name << <STR_LIT> ; O << TAI -> getWeakDefDirective ( ) << name << <STR_LIT> ; break ; }


<s> bool BlackfinAsmPrinter :: PrintAsmMemoryOperand ( const MachineInstr * MI , unsigned OpNo , unsigned AsmVariant , const char * ExtraCode ) { if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ;


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) { if ( ExtraCode [ <NUM_LIT> ] != <NUM_LIT> ) return true ; switch ( ExtraCode [ <NUM_LIT> ] ) { default : return true ; case 'r' : break ; } }


<s> emitLinkage ( name , GV -> getLinkage ( ) ) ; EmitAlignment ( TD -> getPreferredAlignmentLog ( GV ) , GV ) ; printVisibility ( name , GV -> getVisibility ( ) ) ; O << <STR_LIT> << name << <STR_LIT> ; O << <STR_LIT> << name << ',' << TD -> getTypeAllocSize ( C -> getType ( ) ) << '\n' ; O << name << <STR_LIT> ;


if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ;


<s> if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ;


<s> printBasicBlockLabel ( MO . getMBB ( ) , false , false , false ) ; return ; case MachineOperand :: MO_GlobalAddress : O << Mang -> getMangledName ( MO . getGlobal ( ) ) ; printOffset ( MO . getOffset ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : O << Mang -> makeNameProper ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << MO . getIndex ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << TAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> EmitJumpTableInfo ( MF . getJumpTableInfo ( ) , MF ) ; const Function * F = MF . getFunction ( ) ; OutStreamer . SwitchSection ( getObjFileLowering ( ) . SectionForGlobal ( F , Mang , TM ) ) ; EmitAlignment ( <NUM_LIT> , F ) ; emitLinkage ( CurrentFnName , F -> getLinkage ( ) ) ; printVisibility ( CurrentFnName , F -> getVisibility ( ) ) ; O << <STR_LIT> << CurrentFnName << <STR_LIT> << CurrentFnName << <STR_LIT> ; if ( DW ) DW -> BeginFunction ( & MF ) ; for ( MachineFunction :: const_iterator I = MF . begin ( ) , E = MF . end ( ) ; I != E ; ++ I ) { if ( ! VerboseAsm && ( I -> pred_empty ( ) || I -> isOnlyReachableByFallthrough ( ) ) ) { } else { printBasicBlockLabel ( I , true , true , VerboseAsm ) ; O << '\n' ; } for ( MachineBasicBlock :: const_iterator II = I -> begin ( ) , E = I -> end ( ) ; II != E ; ++ II ) { printInstruction ( II ) ; ++ EmittedInsts ; } } O << <STR_LIT> << CurrentFnName << <STR_LIT> << CurrentFnName << <STR_LIT> ; if ( DW ) DW -> EndFunction ( & MF ) ; return false ;


<s> BlackfinAsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCContext & Ctx , MCStreamer & Streamer , const MCAsmInfo * MAI ) : AsmPrinter ( O , TM , Ctx , Streamer , MAI ) {


<s> void EmitInstruction ( const MachineInstr * MI ) {


<s> O << * GetGlobalValueSymbol ( MO . getGlobal ( ) ) ; printOffset ( MO . getOffset ( ) ) ; break ; case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << MO . getIndex ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ; break ;


<s> BlackfinAsmPrinter ( formatted_raw_ostream & O , TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( O , TM , Streamer ) {


<s> case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << MO . getIndex ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ;


<s> BlackfinAsmPrinter ( TargetMachine & TM , MCStreamer & Streamer ) : AsmPrinter ( TM , Streamer ) {


<s> printInstruction ( MI , OS ) ; OutStreamer . EmitRawText ( OS . str ( ) ) ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> void LLVMInitializeBlackfinAsmPrinter ( ) {

RegisterAsmPrinter < BlackfinAsmPrinter > X ( TheBlackfinTarget ) ;


<s> RegisterAsmPrinter < BlackfinAsmPrinter > X ( TheBlackfinTarget ) ;


<s> if ( ExtraCode && ExtraCode [ <NUM_LIT> ] ) return true ; O << '[' ; printOperand ( MI , OpNo , O ) ; O << ']' ; return false ;


<s> void BlackfinAsmPrinter :: printMemoryOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { printOperand ( MI , opNum , O ) ; if ( MI -> getOperand ( opNum + <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( opNum + <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) return ; O << <STR_LIT> ;

printOperand ( MI , opNum + <NUM_LIT> , O ) ;


<s> void BlackfinAsmPrinter :: printMemoryOperand ( const MachineInstr * MI , int opNum , raw_ostream & O ) { printOperand ( MI , opNum , O ) ;


<s> case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; printOffset ( MO . getOffset ( ) , O ) ; break ; case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ; case MachineOperand :: MO_ConstantPoolIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << <STR_LIT> << MO . getIndex ( ) ; break ; case MachineOperand :: MO_JumpTableIndex : O << MAI -> getPrivateGlobalPrefix ( ) << <STR_LIT> << getFunctionNumber ( ) << '_' << MO . getIndex ( ) ; break ; default : llvm_unreachable ( <STR_LIT> ) ;


<s> case MachineOperand :: MO_MachineBasicBlock : O << * MO . getMBB ( ) -> getSymbol ( ) ; return ; case MachineOperand :: MO_GlobalAddress : O << * Mang -> getSymbol ( MO . getGlobal ( ) ) ; printOffset ( MO . getOffset ( ) , O ) ; break ; case MachineOperand :: MO_ExternalSymbol : O << * GetExternalSymbolSymbol ( MO . getSymbolName ( ) ) ; break ;

case MachineOperand :: MO_ConstantPoolIndex :


<s> explicit BlackfinFrameInfo ( const BlackfinSubtarget & sti ) : TargetFrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( sti ) {


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const BlackfinRegisterInfo * RegInfo = static_cast < const BlackfinRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const BlackfinInstrInfo & TII = * static_cast < const BlackfinInstrInfo * > ( MF . getTarget ( ) . getInstrInfo ( ) ) ; MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FrameSize = MFI -> getStackSize ( ) ; assert ( FrameSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; if ( ! hasFP ( MF ) ) { assert ( ! MFI -> adjustsStack ( ) && <STR_LIT> ) ; RegInfo -> adjustRegister ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT> , FrameSize ) ; return ;


<s> int FrameSize = MFI -> getStackSize ( ) ; assert ( FrameSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; if ( ! hasFP ( MF ) ) { assert ( ! MFI -> adjustsStack ( ) && <STR_LIT> ) ; RegInfo -> adjustRegister ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT> , FrameSize ) ; return ; } BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ;


<s> } if ( FrameSize <= <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addImm ( FrameSize ) ; return ; } BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ;

RegInfo -> loadConstant ( MBB , MBBI , dl , <STR_LIT> , - FrameSize ) ;


<s> bool BlackfinFrameInfo :: hasFP ( const MachineFunction & MF ) const {

const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;


<s> return DisableFramePointerElim ( MF ) || MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) ;


<s> const BlackfinRegisterInfo * RegInfo = static_cast < const BlackfinRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const TargetRegisterClass * RC = <STR_LIT> ; if ( RegInfo -> requiresRegisterScavenging ( MF ) ) { RS -> setScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ; }


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return DisableFramePointerElim ( MF ) || MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) ;


<s> bool BlackfinFrameLowering :: hasFP ( const MachineFunction & MF ) const { const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

return DisableFramePointerElim ( MF ) || MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) ;


<s> bool BlackfinFrameLowering :: hasReservedCallFrame ( const MachineFunction & MF ) const {


<s> processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const BlackfinRegisterInfo * RegInfo = static_cast < const BlackfinRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ; const TargetRegisterClass * RC = <STR_LIT> ; if ( RegInfo -> requiresRegisterScavenging ( MF ) ) { RS -> setScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ; }


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const BlackfinRegisterInfo * RegInfo = static_cast < const BlackfinRegisterInfo * > ( MF . getTarget ( ) . getRegisterInfo ( ) ) ;

const TargetRegisterClass * RC = <STR_LIT> ;


<s> explicit BlackfinFrameLowering ( const BlackfinSubtarget & sti ) : TargetFrameLowering ( TargetFrameLowering :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) , STI ( sti ) {


<s> BlackfinInstrInfo :: BlackfinInstrInfo ( BlackfinSubtarget & ST ) : BlackfinGenInstrInfo ( <STR_LIT> , <STR_LIT> ) , RI ( ST , * this ) , Subtarget ( ST ) {


<s> } if ( <STR_LIT> . contains ( SrcReg ) ) { if ( DestReg == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) . addImm ( <NUM_LIT> ) ; return ; } if ( DestReg == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; } } if ( DestReg == <STR_LIT> && SrcReg == <STR_LIT> ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg , getKillRegState ( KillSrc ) ) ; return ; }


<s> static bool inClass ( const TargetRegisterClass & Test , unsigned Reg , const TargetRegisterClass * RC ) { if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return Test . contains ( Reg ) ;

else return Test . hasSubClassEq ( RC ) ;


<s> if ( TargetRegisterInfo :: isPhysicalRegister ( Reg ) ) return Test . contains ( Reg ) ; else return Test . hasSubClassEq ( RC ) ;


<s> if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ;


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; } if ( inClass ( <STR_LIT> , DestReg , RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; } if ( inClass ( <STR_LIT> , DestReg , RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ;


<s> } if ( inClass ( <STR_LIT> , SrcReg , RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; }

llvm_unreachable ( ( std :: string ( <STR_LIT> ) + RC -> getName ( ) ) . c_str ( ) ) ;


<s> } if ( inClass ( <STR_LIT> , SrcReg , RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; } llvm_unreachable ( ( std :: string ( <STR_LIT> ) + RC -> getName ( ) ) . c_str ( ) ) ;


<s> return true ; } if ( inClass ( <STR_LIT> , SrcReg , SrcRC ) && inClass ( <STR_LIT> , DestReg , DestRC ) ) { if ( inClass ( <STR_LIT> , SrcReg , SrcRC ) ) { BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addReg ( DestReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; } return true ; } if ( inClass ( <STR_LIT> , DestReg , DestRC ) && inClass ( <STR_LIT> , SrcReg , SrcRC ) ) { if ( inClass ( <STR_LIT> , DestReg , DestRC ) ) BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ;

else BuildMI ( MBB , I , dl , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ;


<s> assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ;


<s> DebugLoc dl = DebugLoc :: getUnknownLoc ( ) ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) {


<s> BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; } if ( inClass ( <STR_LIT> , DestReg , RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; } llvm_unreachable ( <STR_LIT> ) ;


<s> if ( inClass ( <STR_LIT> , SrcReg , RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; } llvm_unreachable ( ( std :: string ( <STR_LIT> ) + RC -> getName ( ) ) . c_str ( ) ) ;


<s> BlackfinInstrInfo :: BlackfinInstrInfo ( BlackfinSubtarget & ST ) : TargetInstrInfoImpl ( BlackfinInsts , array_lengthof ( BlackfinInsts ) ) , RI ( ST , * this ) , Subtarget ( ST ) {


<s> return true ; } if ( inClass ( <STR_LIT> , DestReg , DestRC ) && inClass ( <STR_LIT> , SrcReg , SrcRC ) ) { if ( inClass ( <STR_LIT> , DestReg , DestRC ) ) BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; else BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } if ( inClass ( <STR_LIT> , DestReg , DestRC ) && inClass ( <STR_LIT> , SrcReg , SrcRC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addReg ( SrcReg ) ; return true ; } if ( inClass ( <STR_LIT> , DestReg , DestRC ) && inClass ( <STR_LIT> , SrcReg , SrcRC ) ) {


<s> virtual const BlackfinRegisterInfo & getRegisterInfo ( ) const { return RI ;


else return & Test == RC || Test . hasSubClass ( RC ) ;


<s> unsigned BlackfinInstrInfo :: InsertBranch ( MachineBasicBlock & MBB , MachineBasicBlock * TBB , MachineBasicBlock * FBB , const SmallVectorImpl < MachineOperand > & Cond ) const { DebugLoc DL ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; }


<s> DebugLoc DL ; assert ( TBB && <STR_LIT> ) ; assert ( ( Cond . size ( ) == <NUM_LIT> || Cond . size ( ) == <NUM_LIT> ) && <STR_LIT> ) ; if ( Cond . empty ( ) ) { assert ( ! FBB && <STR_LIT> ) ; BuildMI ( & MBB , DL , get ( <STR_LIT> ) ) . addMBB ( TBB ) ; return <NUM_LIT> ; } llvm_unreachable ( <STR_LIT> ) ;


<s> default : break ; case <STR_LIT> : case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> case <STR_LIT> : if ( MI -> getOperand ( <NUM_LIT> ) . isFI ( ) && MI -> getOperand ( <NUM_LIT> ) . isImm ( ) && MI -> getOperand ( <NUM_LIT> ) . getImm ( ) == <NUM_LIT> ) { FrameIndex = MI -> getOperand ( <NUM_LIT> ) . getIndex ( ) ; return MI -> getOperand ( <NUM_LIT> ) . getReg ( ) ; }


<s> void BlackfinInstrInfo :: loadRegFromAddr ( MachineFunction & MF , unsigned DestReg , SmallVectorImpl < MachineOperand > & Addr , const TargetRegisterClass * RC , SmallVectorImpl < MachineInstr * > & NewMIs ) const { llvm_unreachable ( <STR_LIT> ) ;


<s> } if ( inClass ( <STR_LIT> , DestReg , RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; } if ( inClass ( <STR_LIT> , DestReg , RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; }


<s> void BlackfinInstrInfo :: loadRegFromStackSlot ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , unsigned DestReg , int FI , const TargetRegisterClass * RC ) const { DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; if ( inClass ( <STR_LIT> , DestReg , RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; } if ( inClass ( <STR_LIT> , DestReg , RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) , DestReg ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; }


<s> DebugLoc DL = I != MBB . end ( ) ? I -> getDebugLoc ( ) : DebugLoc ( ) ; if ( inClass ( <STR_LIT> , SrcReg , RC ) ) { BuildMI ( MBB , I , DL , get ( <STR_LIT> ) ) . addReg ( SrcReg , getKillRegState ( isKill ) ) . addFrameIndex ( FI ) . addImm ( <NUM_LIT> ) ; return ; }


<s> unsigned BlackfinIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const { if ( Len < <NUM_LIT> || Name [ <NUM_LIT> ] != '.' || Name [ <NUM_LIT> ] != 'l' || Name [ <NUM_LIT> ] != 'l' || Name [ <NUM_LIT> ] != 'v' || Name [ <NUM_LIT> ] != 'm' ) return <NUM_LIT> ; return <NUM_LIT> ;


<s> Function * BlackfinIntrinsicInfo :: getDeclaration ( Module * M , unsigned IntrID , Type * * Tys , unsigned numTy ) const {

assert ( ! isOverloaded ( IntrID ) && <STR_LIT> ) ;


<s> } ; assert ( ! isOverloaded ( IntrID ) && <STR_LIT> ) ; if ( IntrID < <STR_LIT> ) return <NUM_LIT> ;

assert ( IntrID < <STR_LIT> && <STR_LIT> ) ;


<s> static FunctionType * getType ( LLVMContext & Context , unsigned id ) { Type * ResultTy = NULL ; SmallVector < Type * , <NUM_LIT> > ArgTys ; bool IsVarArg = false ; return FunctionType :: get ( ResultTy , ArgTys , IsVarArg ) ;


<s> Function * BlackfinIntrinsicInfo :: getDeclaration ( Module * M , unsigned IntrID , const Type * * Tys , unsigned numTy ) const { assert ( ! isOverloaded ( IntrID ) && <STR_LIT> ) ;

AttrListPtr AList = getAttributes ( ( <STR_LIT> ) IntrID ) ;


<s> static const char * const names [ ] = { } ; assert ( ! isOverloaded ( IntrID ) && <STR_LIT> ) ; if ( IntrID < <STR_LIT> ) return <NUM_LIT> ; assert ( IntrID < <STR_LIT> && <STR_LIT> ) ; std :: string Result ( names [ IntrID - <STR_LIT> ] ) ; return Result ;


<s> static const FunctionType * getType ( LLVMContext & Context , unsigned id ) { const Type * ResultTy = NULL ; std :: vector < const Type * > ArgTys ;


<s> } ; if ( IntrID == <NUM_LIT> ) return false ; else return OTable [ IntrID - <STR_LIT> ] ;


<s> unsigned BlackfinIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const {


<s> unsigned BlackfinIntrinsicInfo :: lookupName ( const char * Name , unsigned Len ) const { return <NUM_LIT> ;


<s> void BlackfinDAGToDAGISel :: FixRegisterClasses ( SelectionDAG & DAG ) { const BlackfinInstrInfo & TII = getInstrInfo ( ) ; const BlackfinRegisterInfo * TRI = getRegisterInfo ( ) ; DAG . AssignTopologicalOrder ( ) ; HandleSDNode Dummy ( DAG . getRoot ( ) ) ; for ( SelectionDAG :: allnodes_iterator NI = DAG . allnodes_begin ( ) ; NI != DAG . allnodes_end ( ) ; ++ NI ) { if ( NI -> use_empty ( ) || ! NI -> isMachineOpcode ( ) ) continue ; const TargetInstrDesc & DefTID = TII . get ( NI -> getMachineOpcode ( ) ) ; for ( SDNode :: use_iterator UI = NI -> use_begin ( ) ; ! UI . atEnd ( ) ; ++ UI ) { if ( ! UI -> isMachineOpcode ( ) ) continue ;

if ( UI . getUse ( ) . getResNo ( ) >= DefTID . getNumDefs ( ) ) continue ;


<s> static inline bool isCC ( const TargetRegisterClass * RC ) {

return RC == & <STR_LIT> || <STR_LIT> . hasSubClass ( RC ) ;


<s> if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> && CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , <STR_LIT> ) ; return true ; }


<s> FrameIndexSDNode * FIN = <NUM_LIT> ; if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) {


<s> ops [ Num ] = Val ; SDValue New = DAG . UpdateNodeOperands ( SDValue ( N , <NUM_LIT> ) , ops . data ( ) , ops . size ( ) ) ;

DAG . ReplaceAllUsesWith ( N , New . getNode ( ) ) ;


<s> SmallVector < SDValue , <NUM_LIT> > ops ( N -> op_begin ( ) , N -> op_end ( ) ) ;


<s> DOUT << <STR_LIT> ; DEBUG ( CurDAG -> dump ( ) ) ;


<s> void BlackfinDAGToDAGISel :: InstructionSelect ( ) { SelectRoot ( * CurDAG ) ; DOUT << <STR_LIT> ;


<s> switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , <STR_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } } return SelectCode ( Op ) ;


<s> if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr ) ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ; return true ; } if ( Addr . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = <NUM_LIT> ; if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> && CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , <STR_LIT> ) ; return true ;


<s> BlackfinDAGToDAGISel ( BlackfinTargetMachine & TM , CodeGenOpt :: Level OptLevel ) : SelectionDAGISel ( TM , OptLevel ) {


<s> return new BlackfinDAGToDAGISel ( TM , OptLevel ) ;


<s> if ( NI -> use_empty ( ) || ! NI -> isMachineOpcode ( ) ) continue ; const MCInstrDesc & DefMCID = TII . get ( NI -> getMachineOpcode ( ) ) ; for ( SDNode :: use_iterator UI = NI -> use_begin ( ) ; ! UI . atEnd ( ) ; ++ UI ) { if ( ! UI -> isMachineOpcode ( ) ) continue ; if ( UI . getUse ( ) . getResNo ( ) >= DefMCID . getNumDefs ( ) ) continue ; const TargetRegisterClass * DefRC = TII . getRegClass ( DefMCID , UI . getUse ( ) . getResNo ( ) , TRI ) ; const MCInstrDesc & UseMCID = TII . get ( UI -> getMachineOpcode ( ) ) ; if ( UseMCID . getNumDefs ( ) + UI . getOperandNo ( ) >= UseMCID . getNumOperands ( ) ) continue ; const TargetRegisterClass * UseRC = TII . getRegClass ( UseMCID , UseMCID . getNumDefs ( ) + UI . getOperandNo ( ) , TRI ) ; if ( ! DefRC || ! UseRC ) continue ;

if ( ( isCC ( DefRC ) && ! isDCC ( UseRC ) ) || ( isCC ( UseRC ) && ! isDCC ( DefRC ) ) ) {


<s> for ( SDNode :: use_iterator UI = NI -> use_begin ( ) ; ! UI . atEnd ( ) ; ++ UI ) { if ( ! UI -> isMachineOpcode ( ) ) continue ; if ( UI . getUse ( ) . getResNo ( ) >= DefMCID . getNumDefs ( ) ) continue ; const TargetRegisterClass * DefRC = TII . getRegClass ( DefMCID , UI . getUse ( ) . getResNo ( ) , TRI ) ; const MCInstrDesc & UseMCID = TII . get ( UI -> getMachineOpcode ( ) ) ; if ( UseMCID . getNumDefs ( ) + UI . getOperandNo ( ) >= UseMCID . getNumOperands ( ) ) continue ; const TargetRegisterClass * UseRC = TII . getRegClass ( UseMCID , UseMCID . getNumDefs ( ) + UI . getOperandNo ( ) , TRI ) ; if ( ! DefRC || ! UseRC ) continue ;


<s> return * static_cast < const BlackfinTargetMachine & > ( TM ) . getInstrInfo ( ) ;


<s> virtual const char * getPassName ( ) const { return <STR_LIT> ;


<s> return <STR_LIT> . hasSubClassEq ( RC ) || isCC ( RC ) ;


<s> void BlackfinDAGToDAGISel :: PostprocessISelDAG ( ) {


<s> SDNode * BlackfinDAGToDAGISel :: Select ( SDNode * N ) { if ( N -> isMachineOpcode ( ) ) return NULL ; switch ( N -> getOpcode ( ) ) { default : break ; case <STR_LIT> : { int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , <STR_LIT> ) ; return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ; } }


<s> int FI = cast < FrameIndexSDNode > ( N ) -> getIndex ( ) ; SDValue TFI = CurDAG -> getTargetFrameIndex ( FI , <STR_LIT> ) ;

return CurDAG -> SelectNodeTo ( N , <STR_LIT> , <STR_LIT> , TFI , CurDAG -> getTargetConstant ( <NUM_LIT> , <STR_LIT> ) ) ;


<s> ConstantSDNode * CN = <NUM_LIT> ; if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> && CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , <STR_LIT> ) ; return true ; } } return false ;


<s> } if ( Addr . getOpcode ( ) == <STR_LIT> ) { ConstantSDNode * CN = <NUM_LIT> ; if ( ( FIN = dyn_cast < FrameIndexSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN = dyn_cast < ConstantSDNode > ( Addr . getOperand ( <NUM_LIT> ) ) ) && ( CN -> getSExtValue ( ) % <NUM_LIT> == <NUM_LIT> && CN -> getSExtValue ( ) >= <NUM_LIT> ) ) { Base = CurDAG -> getTargetFrameIndex ( FIN -> getIndex ( ) , <STR_LIT> ) ; Offset = CurDAG -> getTargetConstant ( CN -> getSExtValue ( ) , <STR_LIT> ) ; return true ;


<s> SmallVector < SDValue , <NUM_LIT> > ops ( N -> op_begin ( ) , N -> op_end ( ) ) ;


<s> SmallVector < SDValue , <NUM_LIT> > ops ( N -> op_begin ( ) , N -> op_end ( ) ) ; ops [ Num ] = Val ;

SDNode * New = DAG . UpdateNodeOperands ( N , ops . data ( ) , ops . size ( ) ) ;


<s> virtual MVT getShiftAmountTy ( EVT LHSTy ) const {


<s> setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> unsigned BlackfinTargetLowering :: getFunctionAlignment ( const Function * F ) const { return <NUM_LIT> ;


<s> case 'c' : return make_vector < unsigned > ( I0 , I1 , I2 , I3 , B0 , B1 , B2 , B3 , L0 , L1 , L2 , L3 , <NUM_LIT> ) ; case 't' : return make_vector < unsigned > ( LT0 , LT1 , <NUM_LIT> ) ; case 'u' : return make_vector < unsigned > ( LB0 , LB1 , <NUM_LIT> ) ; case 'k' : return make_vector < unsigned > ( LC0 , LC1 , <NUM_LIT> ) ;

case 'y' : return make_vector < unsigned > ( RETS , RETN , RETI , RETX , RETE , ASTAT , SEQSTAT , USP , <NUM_LIT> ) ;


<s> case 'W' : return make_vector < unsigned > ( R1 , R3 , R5 , R7 , <NUM_LIT> ) ; case 'c' : return make_vector < unsigned > ( I0 , I1 , I2 , I3 , B0 , B1 , B2 , B3 , L0 , L1 , L2 , L3 , <NUM_LIT> ) ; case 't' : return make_vector < unsigned > ( LT0 , LT1 , <NUM_LIT> ) ; case 'u' : return make_vector < unsigned > ( LB0 , LB1 , <NUM_LIT> ) ; case 'k' : return make_vector < unsigned > ( LC0 , LC1 , <NUM_LIT> ) ; case 'y' : return make_vector < unsigned > ( RETS , RETN , RETI , RETX , RETE , ASTAT , SEQSTAT , USP , <NUM_LIT> ) ; } return std :: vector < unsigned > ( ) ;


<s> return Pair ( <NUM_LIT> , VT == <STR_LIT> ? D16RegisterClass : DPRegisterClass ) ; case 'a' : return Pair ( <NUM_LIT> , PRegisterClass ) ; case 'd' : return Pair ( <NUM_LIT> , DRegisterClass ) ; case 'e' : return Pair ( <NUM_LIT> , AccuRegisterClass ) ; case 'A' : return Pair ( A0 , AccuRegisterClass ) ; case 'B' : return Pair ( A1 , AccuRegisterClass ) ; case 'b' : return Pair ( <NUM_LIT> , IRegisterClass ) ;

case 'v' : return Pair ( <NUM_LIT> , BRegisterClass ) ;


<s> <STR_LIT> BlackfinTargetLowering :: getSetCCResultType ( EVT VT ) const {


<s> SDNode * Carry1 = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Sum , <NUM_LIT> ) ) ; Sum = DAG . getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , SDValue ( Sum , <NUM_LIT> ) , SDValue ( CarryIn , <NUM_LIT> ) ) ; SDNode * CarryOut = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Carry1 , <NUM_LIT> ) ) ; SDValue ops [ <NUM_LIT> ] = { SDValue ( Sum , <NUM_LIT> ) , SDValue ( CarryOut , <NUM_LIT> ) } ; return DAG . getMergeValues ( ops , <NUM_LIT> , dl ) ;


<s> Sum = DAG . getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , SDValue ( Sum , <NUM_LIT> ) , SDValue ( CarryIn , <NUM_LIT> ) ) ; SDNode * CarryOut = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Carry1 , <NUM_LIT> ) ) ; SDValue ops [ <NUM_LIT> ] = { SDValue ( Sum , <NUM_LIT> ) , SDValue ( CarryOut , <NUM_LIT> ) } ; return DAG . getMergeValues ( ops , <NUM_LIT> , dl ) ;


<s> SmallVector < CCValAssign , <NUM_LIT> > ArgLocs ; CCState CCInfo ( CallConv , isVarArg , getTargetMachine ( ) , ArgLocs , * DAG . getContext ( ) ) ; CCInfo . AllocateStack ( <NUM_LIT> , <NUM_LIT> ) ; CCInfo . AnalyzeFormalArguments ( Ins , CC_Blackfin ) ; for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; TargetRegisterClass * RC = VA . getLocReg ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( RC -> contains ( VA . getLocReg ( ) ) && <STR_LIT> ) ; assert ( RC -> hasType ( RegVT ) && <STR_LIT> ) ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( VA . getLocReg ( ) , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ;


<s> Op = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ;

return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ;


<s> DebugLoc DL = Op . getDebugLoc ( ) ; const GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ;

Op = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ;


<s> SDValue BlackfinTargetLowering :: LowerJumpTable ( SDValue Op , SelectionDAG & DAG ) { DebugLoc DL = Op . getDebugLoc ( ) ;

int JTI = cast < JumpTableSDNode > ( Op ) -> getIndex ( ) ;


<s> Op . getNode ( ) -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> :

case <STR_LIT> : return LowerADDE ( Op , DAG ) ;


<s> void BlackfinTargetLowering :: ReplaceNodeResults ( SDNode * N , SmallVectorImpl < SDValue > & Results , SelectionDAG & DAG ) { DebugLoc dl = N -> getDebugLoc ( ) ; switch ( N -> getOpcode ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; return ; case <STR_LIT> : {

SDValue TheChain = N -> getOperand ( <NUM_LIT> ) ;


<s> addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; computeRegisterProperties ( ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> setStackPointerRegisterToSaveRestore ( <STR_LIT> ) ; setIntDivIsCheap ( false ) ; addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; addRegisterClass ( <STR_LIT> , <STR_LIT> ) ; computeRegisterProperties ( ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setLoadExtAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Custom ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Promote ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ; setOperationAction ( <STR_LIT> , <STR_LIT> , Expand ) ;


<s> int getVarArgsFrameOffset ( ) const {


<s> CarryIn = DAG . getTargetNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( CarryIn , <NUM_LIT> ) ) ; SDNode * Sum = DAG . getTargetNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDNode * Carry1 = DAG . getTargetNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Sum , <NUM_LIT> ) ) ; Sum = DAG . getTargetNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , SDValue ( Sum , <NUM_LIT> ) , SDValue ( CarryIn , <NUM_LIT> ) ) ; SDNode * CarryOut = DAG . getTargetNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Carry1 , <NUM_LIT> ) ) ; SDValue ops [ <NUM_LIT> ] = { SDValue ( Sum , <NUM_LIT> ) , SDValue ( CarryOut , <NUM_LIT> ) } ; return DAG . getMergeValues ( ops , <NUM_LIT> , dl ) ;


<s> SDValue OffsetN = DAG . getIntPtrConstant ( Offset ) ; OffsetN = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SPN , OffsetN ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , OffsetN , PseudoSourceValue :: getStack ( ) , Offset ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) { Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; std :: vector < EVT > NodeTys ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Callee , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( ArgsSize , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState RVInfo ( CallConv , isVarArg , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ; RVInfo . AnalyzeCallResult ( Ins , RetCC_Blackfin ) ;

for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) {


<s> TargetRegisterClass * RC = VA . getLocReg ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( RC -> contains ( VA . getLocReg ( ) ) && <STR_LIT> ) ; assert ( RC -> hasType ( RegVT ) && <STR_LIT> ) ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( VA . getLocReg ( ) , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ;

if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ;


<s> SDValue BlackfinTargetLowering :: LowerGlobalAddress ( SDValue Op , SelectionDAG & DAG ) { DebugLoc DL = Op . getDebugLoc ( ) ; GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Op = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ;


<s> DebugLoc DL = Op . getDebugLoc ( ) ; GlobalValue * GV = cast < GlobalAddressSDNode > ( Op ) -> getGlobal ( ) ; Op = DAG . getTargetGlobalAddress ( GV , <STR_LIT> ) ; return DAG . getNode ( <STR_LIT> , DL , <STR_LIT> , Op ) ;


<s> SDValue Flag ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Opi = Outs [ i ] . Val ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Opi = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Opi ) ; break ; case CCValAssign :: ZExt : Opi = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Opi ) ; break ; case CCValAssign :: AExt : Opi = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Opi ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Opi , SDValue ( ) ) ; Flag = Chain . getValue ( <NUM_LIT> ) ;


<s> case CCValAssign :: ZExt : Opi = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Opi ) ; break ; case CCValAssign :: AExt : Opi = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Opi ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Opi , SDValue ( ) ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ; } else { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;


<s> CarryIn = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( CarryIn , <NUM_LIT> ) ) ; SDNode * Sum = DAG . getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDNode * Carry1 = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Sum , <NUM_LIT> ) ) ; Sum = DAG . getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , SDValue ( Sum , <NUM_LIT> ) , SDValue ( CarryIn , <NUM_LIT> ) ) ; SDNode * CarryOut = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Carry1 , <NUM_LIT> ) ) ;

SDValue ops [ <NUM_LIT> ] = { SDValue ( Sum , <NUM_LIT> ) , SDValue ( CarryOut , <NUM_LIT> ) } ;


<s> break ; case CCValAssign :: ZExt : Opi = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Opi ) ; break ; case CCValAssign :: AExt : Opi = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Opi ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Opi , SDValue ( ) ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; } if ( Flag . getNode ( ) ) { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain , Flag ) ; } else { return DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , Chain ) ;


<s> case CCValAssign :: Full : break ; case CCValAssign :: SExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: ZExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; case CCValAssign :: AExt : Arg = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Arg ) ; break ; } if ( VA . isRegLoc ( ) ) { RegsToPass . push_back ( std :: make_pair ( VA . getLocReg ( ) , Arg ) ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; int Offset = VA . getLocMemOffset ( ) ; assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( VA . getLocVT ( ) == <STR_LIT> && <STR_LIT> ) ; SDValue SPN = DAG . getCopyFromReg ( Chain , dl , <STR_LIT> , <STR_LIT> ) ; SDValue OffsetN = DAG . getIntPtrConstant ( Offset ) ; OffsetN = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , SPN , OffsetN ) ; MemOpChains . push_back ( DAG . getStore ( Chain , dl , Arg , OffsetN , MachinePointerInfo ( ) , false , false , <NUM_LIT> ) ) ; } } if ( ! MemOpChains . empty ( ) ) Chain = DAG . getNode ( <STR_LIT> , dl , <STR_LIT> , & MemOpChains [ <NUM_LIT> ] , MemOpChains . size ( ) ) ; SDValue InFlag ; for ( unsigned i = <NUM_LIT> , e = RegsToPass . size ( ) ; i != e ; ++ i ) {

Chain = DAG . getCopyToReg ( Chain , dl , RegsToPass [ i ] . first , RegsToPass [ i ] . second , InFlag ) ;


<s> for ( unsigned i = <NUM_LIT> , e = ArgLocs . size ( ) ; i != e ; ++ i ) { CCValAssign & VA = ArgLocs [ i ] ; if ( VA . isRegLoc ( ) ) { EVT RegVT = VA . getLocVT ( ) ; TargetRegisterClass * RC = VA . getLocReg ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; assert ( RC -> contains ( VA . getLocReg ( ) ) && <STR_LIT> ) ; assert ( RC -> hasType ( RegVT ) && <STR_LIT> ) ; unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( VA . getLocReg ( ) , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } else {

assert ( VA . isMemLoc ( ) && <STR_LIT> ) ;


<s> case 'c' : case 't' : case 'u' : case 'k' : case 'x' : case 'y' : case 'w' : return C_RegisterClass ; case 'A' : case 'B' : case 'C' : case 'Z' : case 'Y' : return C_Register ; }

return TargetLowering :: getConstraintType ( Constraint ) ;


<s> using namespace <ISA_LIT> ; if ( Constraint . size ( ) != <NUM_LIT> ) return TargetLowering :: getRegForInlineAsmConstraint ( Constraint , VT ) ; switch ( Constraint [ <NUM_LIT> ] ) { case 'r' : return Pair ( <NUM_LIT> , VT == <STR_LIT> ? D16RegisterClass : DPRegisterClass ) ; case 'a' : return Pair ( <NUM_LIT> , PRegisterClass ) ; case 'd' : return Pair ( <NUM_LIT> , DRegisterClass ) ; case 'e' : return Pair ( <NUM_LIT> , AccuRegisterClass ) ; case 'A' : return Pair ( A0 , AccuRegisterClass ) ; case 'B' : return Pair ( A1 , AccuRegisterClass ) ; case 'b' : return Pair ( <NUM_LIT> , IRegisterClass ) ; case 'v' : return Pair ( <NUM_LIT> , BRegisterClass ) ; case 'f' : return Pair ( <NUM_LIT> , MRegisterClass ) ; case 'C' : return Pair ( CC , JustCCRegisterClass ) ; case 'x' : return Pair ( <NUM_LIT> , GRRegisterClass ) ; case 'w' : return Pair ( <NUM_LIT> , ALLRegisterClass ) ; case 'Z' : return Pair ( P3 , PRegisterClass ) ; case 'Y' : return Pair ( P1 , PRegisterClass ) ; case 'z' : return Pair ( <NUM_LIT> , zConsRegisterClass ) ; case 'D' : return Pair ( <NUM_LIT> , DConsRegisterClass ) ; case 'W' : return Pair ( <NUM_LIT> , WConsRegisterClass ) ; case 'c' : return Pair ( <NUM_LIT> , cConsRegisterClass ) ; case 't' : return Pair ( <NUM_LIT> , tConsRegisterClass ) ; case 'u' : return Pair ( <NUM_LIT> , uConsRegisterClass ) ; case 'k' : return Pair ( <NUM_LIT> , kConsRegisterClass ) ; case 'y' : return Pair ( <NUM_LIT> , yConsRegisterClass ) ; }


<s> EVT BlackfinTargetLowering :: getSetCCResultType ( EVT VT ) const { return <STR_LIT> ;


<s> weight = TargetLowering :: getSingleConstraintMatchWeight ( info , constraint ) ; break ; case 'a' : case 'd' : case 'z' : case 'D' : case 'W' : case 'e' : case 'b' : case 'v' : case 'f' : case 'c' : case 't' : case 'u' : case 'k' : case 'x' : case 'y' : case 'w' : return CW_Register ; case 'A' : case 'B' : case 'C' : case 'Z' : case 'Y' :


<s> case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ; }


<s> const char * BlackfinTargetLowering :: getTargetNodeName ( unsigned Opcode ) const { switch ( Opcode ) { default : return <NUM_LIT> ; case <STR_LIT> : return <STR_LIT> ; case <STR_LIT> : return <STR_LIT> ;


<s> bool BlackfinTargetLowering :: isOffsetFoldingLegal ( const GlobalAddressSDNode * GA ) const {


<s> unsigned Opcode = Op . getOpcode ( ) == <STR_LIT> ? <STR_LIT> : <STR_LIT> ; SDNode * CarryIn = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) ) ; CarryIn = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( CarryIn , <NUM_LIT> ) ) ; SDNode * Sum = DAG . getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , Op . getOperand ( <NUM_LIT> ) , Op . getOperand ( <NUM_LIT> ) ) ; SDNode * Carry1 = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Sum , <NUM_LIT> ) ) ; Sum = DAG . getMachineNode ( Opcode , dl , <STR_LIT> , <STR_LIT> , SDValue ( Sum , <NUM_LIT> ) , SDValue ( CarryIn , <NUM_LIT> ) ) ;

SDNode * CarryOut = DAG . getMachineNode ( <STR_LIT> , dl , <STR_LIT> , SDValue ( Carry1 , <NUM_LIT> ) ) ;


<s> } if ( GlobalAddressSDNode * G = dyn_cast < GlobalAddressSDNode > ( Callee ) ) Callee = DAG . getTargetGlobalAddress ( G -> getGlobal ( ) , dl , <STR_LIT> ) ; else if ( ExternalSymbolSDNode * E = dyn_cast < ExternalSymbolSDNode > ( Callee ) ) Callee = DAG . getTargetExternalSymbol ( E -> getSymbol ( ) , <STR_LIT> ) ; std :: vector < EVT > NodeTys ; NodeTys . push_back ( <STR_LIT> ) ; NodeTys . push_back ( <STR_LIT> ) ; SDValue Ops [ ] = { Chain , Callee , InFlag } ; Chain = DAG . getNode ( <STR_LIT> , dl , NodeTys , Ops , InFlag . getNode ( ) ? <NUM_LIT> : <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = DAG . getCALLSEQ_END ( Chain , DAG . getIntPtrConstant ( ArgsSize , true ) , DAG . getIntPtrConstant ( <NUM_LIT> , true ) , InFlag ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; SmallVector < CCValAssign , <NUM_LIT> > RVLocs ; CCState RVInfo ( CallConv , isVarArg , DAG . getMachineFunction ( ) , DAG . getTarget ( ) , RVLocs , * DAG . getContext ( ) ) ; RVInfo . AnalyzeCallResult ( Ins , RetCC_Blackfin ) ; for ( unsigned i = <NUM_LIT> ; i != RVLocs . size ( ) ; ++ i ) { CCValAssign & RV = RVLocs [ i ] ; unsigned Reg = RV . getLocReg ( ) ; Chain = DAG . getCopyFromReg ( Chain , dl , Reg , RVLocs [ i ] . getLocVT ( ) , InFlag ) ; SDValue Val = Chain . getValue ( <NUM_LIT> ) ; InFlag = Chain . getValue ( <NUM_LIT> ) ; Chain = Chain . getValue ( <NUM_LIT> ) ; switch ( RV . getLocInfo ( ) ) { case CCValAssign :: SExt : Val = DAG . getNode ( <STR_LIT> , dl , RV . getLocVT ( ) , Val , DAG . getValueType ( RV . getValVT ( ) ) ) ; break ; case CCValAssign :: ZExt : Val = DAG . getNode ( <STR_LIT> , dl , RV . getLocVT ( ) , Val , DAG . getValueType ( RV . getValVT ( ) ) ) ; break ; default : break ; } if ( RV . getLocInfo ( ) != CCValAssign :: Full ) Val = DAG . getNode ( <STR_LIT> , dl , RV . getValVT ( ) , Val ) ; InVals . push_back ( Val ) ;


<s> unsigned Reg = MF . getRegInfo ( ) . createVirtualRegister ( RC ) ; MF . getRegInfo ( ) . addLiveIn ( VA . getLocReg ( ) , Reg ) ; SDValue ArgValue = DAG . getCopyFromReg ( Chain , dl , Reg , RegVT ) ; if ( VA . getLocInfo ( ) == CCValAssign :: SExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; else if ( VA . getLocInfo ( ) == CCValAssign :: ZExt ) ArgValue = DAG . getNode ( <STR_LIT> , dl , RegVT , ArgValue , DAG . getValueType ( VA . getValVT ( ) ) ) ; if ( VA . getLocInfo ( ) != CCValAssign :: Full ) ArgValue = DAG . getNode ( <STR_LIT> , dl , VA . getValVT ( ) , ArgValue ) ; InVals . push_back ( ArgValue ) ; } else { assert ( VA . isMemLoc ( ) && <STR_LIT> ) ; unsigned ObjSize = VA . getLocVT ( ) . getStoreSize ( ) ;

int FI = MFI -> CreateFixedObject ( ObjSize , VA . getLocMemOffset ( ) , true ) ;


<s> Op = DAG . getTargetGlobalAddress ( GV , DL , <STR_LIT> ) ;


<s> Op = DAG . getTargetJumpTable ( JTI , <STR_LIT> ) ;


<s> Op . getNode ( ) -> dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerGlobalAddress ( Op , DAG ) ; case <STR_LIT> : llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ;


<s> llvm_unreachable ( <STR_LIT> ) ; case <STR_LIT> : return LowerJumpTable ( Op , DAG ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> : return SDValue ( ) ; case <STR_LIT> :


<s> CCValAssign & VA = RVLocs [ i ] ; assert ( VA . isRegLoc ( ) && <STR_LIT> ) ; SDValue Opi = OutVals [ i ] ; switch ( VA . getLocInfo ( ) ) { default : llvm_unreachable ( <STR_LIT> ) ; case CCValAssign :: Full : break ; case CCValAssign :: SExt : Opi = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Opi ) ; break ; case CCValAssign :: ZExt : Opi = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Opi ) ; break ; case CCValAssign :: AExt : Opi = DAG . getNode ( <STR_LIT> , dl , VA . getLocVT ( ) , Opi ) ; break ; } Chain = DAG . getCopyToReg ( Chain , dl , VA . getLocReg ( ) , Opi , SDValue ( ) ) ; Flag = Chain . getValue ( <NUM_LIT> ) ; }


<s> TargetRegistry :: RegisterMCCodeGenInfo ( TheBlackfinTarget , createBlackfinMCCodeGenInfo ) ;

TargetRegistry :: RegisterMCInstrInfo ( TheBlackfinTarget , createBlackfinMCInstrInfo ) ;


<s> RegisterMCAsmInfo < BlackfinMCAsmInfo > X ( TheBlackfinTarget ) ;

TargetRegistry :: RegisterMCCodeGenInfo ( TheBlackfinTarget , createBlackfinMCCodeGenInfo ) ;


<s> MCCodeGenInfo * createBlackfinMCCodeGenInfo ( StringRef TT , Reloc :: Model RM ) { MCCodeGenInfo * X = new MCCodeGenInfo ( ) ;


<s> MCCodeGenInfo * X = new MCCodeGenInfo ( ) ; X -> InitMCCodeGenInfo ( RM ) ;


<s> static MCRegisterInfo * createBlackfinMCRegisterInfo ( StringRef TT ) { MCRegisterInfo * X = new MCRegisterInfo ( ) ; InitBlackfinMCRegisterInfo ( X , <STR_LIT> ) ;


<s> void LLVMInitializeBlackfinMCAsmInfo ( ) { RegisterMCAsmInfo < BlackfinMCAsmInfo > X ( TheBlackfinTarget ) ;


<s> TargetRegistry :: RegisterMCInstrInfo ( TheBlackfinTarget , createBlackfinMCInstrInfo ) ;


<s> void LLVMInitializeBlackfinMCRegisterInfo ( ) {

TargetRegistry :: RegisterMCRegInfo ( TheBlackfinTarget , createBlackfinMCRegisterInfo ) ;


<s> loadConstant ( MBB , I , DL , ScratchReg , delta ) ; if ( <STR_LIT> . contains ( Reg ) ) { assert ( <STR_LIT> . contains ( ScratchReg ) && <STR_LIT> ) ;

BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addReg ( Reg , RegState :: Kill ) . addReg ( ScratchReg , RegState :: Kill ) ;


<s> BlackfinRegisterInfo :: BlackfinRegisterInfo ( BlackfinSubtarget & st , const TargetInstrInfo & tii ) : BlackfinGenRegisterInfo ( <STR_LIT> , <STR_LIT> ) , Subtarget ( st ) , TII ( tii ) {


<s> if ( I -> getOpcode ( ) == <STR_LIT> ) { adjustRegister ( MBB , I , I -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , - Amount ) ; } else { assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; adjustRegister ( MBB , I , I -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , Amount ) ; } } }


<s> DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FrameSize = MFI -> getStackSize ( ) ; assert ( FrameSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; if ( ! hasFP ( MF ) ) { assert ( ! MFI -> hasCalls ( ) && <STR_LIT> ) ; adjustRegister ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT> , FrameSize ) ; return ; }

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) ;


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; MachineBasicBlock :: iterator MBBI = prior ( MBB . end ( ) ) ; DebugLoc dl = MBBI -> getDebugLoc ( ) ; int FrameSize = MFI -> getStackSize ( ) ; assert ( FrameSize % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ;


<s> return ; } if ( FrameSize <= <NUM_LIT> ) { BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addImm ( FrameSize ) ; return ; } BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ; BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) ) . addReg ( <STR_LIT> , RegState :: Kill ) ;

BuildMI ( MBB , MBBI , dl , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( <STR_LIT> ) ;


<s> assert ( RS && <STR_LIT> ) ; unsigned Reg = RS -> FindUnusedReg ( RC ) ;

if ( Reg == <NUM_LIT> ) Reg = RS -> scavengeRegister ( RC , II , SPAdj ) ;


<s> unsigned Reg = RS -> FindUnusedReg ( RC ) ;


<s> const TargetRegisterClass * const * BlackfinRegisterInfo :: getCalleeSavedRegClasses ( const MachineFunction * MF ) const { using namespace <ISA_LIT> ;

static const TargetRegisterClass * const CalleeSavedRegClasses [ ] = {


<s> static const unsigned CalleeSavedRegs [ ] = { FP , R4 , R5 , R6 , R7 , P3 , P4 , P5 , <NUM_LIT> } ;


<s> unsigned BlackfinRegisterInfo :: getEHHandlerRegister ( ) const { llvm_unreachable ( <STR_LIT> ) ; return <NUM_LIT> ;


<s> return hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> unsigned BlackfinRegisterInfo :: getFrameRegister ( const MachineFunction & MF ) const {

return hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> if ( ( VT == <STR_LIT> || RC -> hasType ( VT ) ) && RC -> contains ( reg ) && ( ! BestRC || RC -> getNumRegs ( ) < BestRC -> getNumRegs ( ) ) ) BestRC = RC ; } assert ( BestRC && <STR_LIT> ) ;


<s> for ( regclass_iterator I = regclass_begin ( ) , E = regclass_end ( ) ; I != E ; ++ I ) { const TargetRegisterClass * RC = * I ; if ( ( VT == <STR_LIT> || RC -> hasType ( VT ) ) && RC -> contains ( reg ) && ( ! BestRC || RC -> getNumRegs ( ) < BestRC -> getNumRegs ( ) ) ) BestRC = RC ; } assert ( BestRC && <STR_LIT> ) ; return BestRC ;


<s> const TargetRegisterClass * getPointerRegClass ( unsigned Kind = <NUM_LIT> ) const { return & <STR_LIT> ;


<s> unsigned BlackfinRegisterInfo :: getRARegister ( ) const { return <STR_LIT> ;


<s> Reserved . set ( VS ) ; Reserved . set ( CYCLES ) . set ( CYCLES2 ) ; Reserved . set ( L0 ) ; Reserved . set ( L1 ) ; Reserved . set ( L2 ) ; Reserved . set ( L3 ) ; Reserved . set ( SP ) ;


<s> Reserved . set ( L0 ) ; Reserved . set ( L1 ) ; Reserved . set ( L2 ) ; Reserved . set ( L3 ) ; Reserved . set ( SP ) ; Reserved . set ( RETS ) ;

if ( hasFP ( MF ) ) Reserved . set ( FP ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return NoFramePointerElim || MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( ) ;


<s> const MachineFrameInfo * MFI = MF . getFrameInfo ( ) ;

return NoFramePointerElim || MFI -> hasCalls ( ) || MFI -> hasVarSizedObjects ( ) ;


<s> void BlackfinRegisterInfo :: loadConstant ( MachineBasicBlock & MBB , MachineBasicBlock :: iterator I , DebugLoc DL , unsigned Reg , int value ) const { if ( isInt < <NUM_LIT> > ( value ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addImm ( value ) ; return ; } if ( isUInt < <NUM_LIT> > ( value ) ) {


<s> return ; } if ( isUInt < <NUM_LIT> > ( value ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addImm ( value ) ; return ; } if ( isInt < <NUM_LIT> > ( value ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addImm ( value ) ; return ; } BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , getSubReg ( Reg , bfin_subreg_hi16 ) ) . addImm ( ( value >> <NUM_LIT> ) & <NUM_LIT> ) . addReg ( Reg , RegState :: ImplicitDefine ) ;

BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , getSubReg ( Reg , bfin_subreg_lo16 ) ) . addImm ( value & <NUM_LIT> ) . addReg ( Reg , RegState :: ImplicitKill ) . addReg ( Reg , RegState :: ImplicitDefine ) ;


<s> void BlackfinRegisterInfo :: processFunctionBeforeCalleeSavedScan ( MachineFunction & MF , RegScavenger * RS ) const { MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = <STR_LIT> ; if ( requiresRegisterScavenging ( MF ) ) { RS -> setScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ; }


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = <STR_LIT> ; if ( requiresRegisterScavenging ( MF ) ) { RS -> setScavengingFrameIndex ( MFI -> CreateStackObject ( RC -> getSize ( ) , RC -> getAlignment ( ) , false ) ) ; }


<s> void BlackfinRegisterInfo :: processFunctionBeforeFrameFinalized ( MachineFunction & MF ) const {


requiresRegisterScavenging ( const MachineFunction & MF ) const {


<s> const TargetFrameInfo & TFI = * MF . getTarget ( ) . getFrameInfo ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; return MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) - TFI . getOffsetOfLocalArea ( ) + MFI -> getOffsetAdjustment ( ) ;


<s> return MFI -> getObjectOffset ( FI ) + MFI -> getStackSize ( ) - TFI . getOffsetOfLocalArea ( ) + MFI -> getOffsetAdjustment ( ) ;


<s> } if ( isInt < <NUM_LIT> > ( value ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addImm ( value ) ; return ; } BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , getSubReg ( Reg , bfin_subreg_hi16 ) ) . addImm ( ( value >> <NUM_LIT> ) & <NUM_LIT> ) . addReg ( Reg , RegState :: ImplicitDefine ) ; BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , getSubReg ( Reg , bfin_subreg_lo16 ) ) . addImm ( value & <NUM_LIT> ) . addReg ( Reg , RegState :: ImplicitKill ) . addReg ( Reg , RegState :: ImplicitDefine ) ;


<s> MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; const TargetRegisterClass * RC = <STR_LIT> ;

if ( requiresRegisterScavenging ( MF ) ) {


<s> void BlackfinRegisterInfo :: emitPrologue ( MachineFunction & MF ) const { MachineBasicBlock & MBB = MF . front ( ) ; MachineBasicBlock :: iterator MBBI = MBB . begin ( ) ; MachineFrameInfo * MFI = MF . getFrameInfo ( ) ; DebugLoc dl = MBBI != MBB . end ( ) ? MBBI -> getDebugLoc ( ) : DebugLoc ( ) ; int FrameSize = MFI -> getStackSize ( ) ; if ( FrameSize % <NUM_LIT> ) { FrameSize = ( FrameSize + <NUM_LIT> ) & ~ <NUM_LIT> ; MFI -> setStackSize ( FrameSize ) ; } if ( ! hasFP ( MF ) ) { assert ( ! MFI -> adjustsStack ( ) && <STR_LIT> ) ;

adjustRegister ( MBB , MBBI , dl , <STR_LIT> , <STR_LIT> , - FrameSize ) ;


return DisableFramePointerElim ( MF ) || MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) ;


<s> return DisableFramePointerElim ( MF ) || MFI -> adjustsStack ( ) || MFI -> hasVarSizedObjects ( ) ;


<s> if ( isInt < <NUM_LIT> > ( value ) ) { BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , Reg ) . addImm ( value ) ; return ; }

BuildMI ( MBB , I , DL , TII . get ( <STR_LIT> ) , getSubReg ( Reg , <STR_LIT> ) ) . addImm ( ( value >> <NUM_LIT> ) & <NUM_LIT> ) . addReg ( Reg , RegState :: ImplicitDefine ) ;


<s> void BlackfinRegisterInfo :: eliminateCallFramePseudoInstr ( MachineFunction & MF , MachineBasicBlock & MBB , MachineBasicBlock :: iterator I ) const { const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; if ( ! TFI -> hasReservedCallFrame ( MF ) ) { int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { assert ( Amount % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) { adjustRegister ( MBB , I , I -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , - Amount ) ; } else { assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; adjustRegister ( MBB , I , I -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , Amount ) ; } }


<s> assert ( Amount % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) { adjustRegister ( MBB , I , I -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , - Amount ) ; } else { assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ;

adjustRegister ( MBB , I , I -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , Amount ) ;


<s> Offset += MF . getFrameInfo ( ) -> getStackSize ( ) + SPAdj ; } bool isStore = false ; switch ( MI . getOpcode ( ) ) { case <STR_LIT> : isStore = true ; case <STR_LIT> : { assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( FIPos == <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FIPos ) . ChangeToRegister ( BaseReg , false ) ; MI . getOperand ( FIPos + <NUM_LIT> ) . setImm ( Offset ) ; if ( isUInt < <NUM_LIT> > ( Offset ) ) { MI . setDesc ( TII . get ( isStore ? <STR_LIT> : <STR_LIT> ) ) ; return ; } if ( BaseReg == <STR_LIT> && isUInt < <NUM_LIT> > ( - Offset ) ) { MI . setDesc ( TII . get ( isStore ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIPos + <NUM_LIT> ) . setImm ( - Offset ) ; return ; } if ( isInt < <NUM_LIT> > ( Offset ) ) { MI . setDesc ( TII . get ( isStore ? <STR_LIT> : <STR_LIT> ) ) ; return ; } MI . dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; break ; } case <STR_LIT> : { assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( FIPos == <NUM_LIT> && <STR_LIT> ) ; loadConstant ( MBB , II , DL , DestReg , Offset ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( DestReg , false , false , true ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( BaseReg , false ) ; break ; } case <STR_LIT> : isStore = true ; case <STR_LIT> : { assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( FIPos == <NUM_LIT> && <STR_LIT> ) ;

unsigned ScratchReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ;


<s> const TargetFrameInfo * TFI = MF . getTarget ( ) . getFrameInfo ( ) ; return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> Reserved . set ( V ) ; Reserved . set ( VS ) ; Reserved . set ( CYCLES ) . set ( CYCLES2 ) ; Reserved . set ( L0 ) ; Reserved . set ( L1 ) ; Reserved . set ( L2 ) ; Reserved . set ( L3 ) ; Reserved . set ( SP ) ; Reserved . set ( RETS ) ; if ( TFI -> hasFP ( MF ) ) Reserved . set ( FP ) ; return Reserved ;


<s> isStore = true ; case <STR_LIT> : { assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( FIPos == <NUM_LIT> && <STR_LIT> ) ; MI . getOperand ( FIPos ) . ChangeToRegister ( BaseReg , false ) ; MI . getOperand ( FIPos + <NUM_LIT> ) . setImm ( Offset ) ; if ( isUint < <NUM_LIT> > ( Offset ) ) { MI . setDesc ( TII . get ( isStore ? <STR_LIT> : <STR_LIT> ) ) ; return <NUM_LIT> ; } if ( BaseReg == <STR_LIT> && isUint < <NUM_LIT> > ( - Offset ) ) { MI . setDesc ( TII . get ( isStore ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( FIPos + <NUM_LIT> ) . setImm ( - Offset ) ; return <NUM_LIT> ; } if ( isInt < <NUM_LIT> > ( Offset ) ) { MI . setDesc ( TII . get ( isStore ? <STR_LIT> : <STR_LIT> ) ) ; return <NUM_LIT> ; } MI . dump ( ) ; llvm_unreachable ( <STR_LIT> ) ; break ; } case <STR_LIT> : { assert ( MI . getOperand ( <NUM_LIT> ) . isReg ( ) && <STR_LIT> ) ; unsigned DestReg = MI . getOperand ( <NUM_LIT> ) . getReg ( ) ; assert ( FIPos == <NUM_LIT> && <STR_LIT> ) ; loadConstant ( MBB , II , DL , DestReg , Offset ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( DestReg , false , false , true ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( BaseReg , false ) ; break ; } case <STR_LIT> : isStore = true ; case <STR_LIT> : { assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( FIPos == <NUM_LIT> && <STR_LIT> ) ; unsigned ScratchReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; assert ( ScratchReg && <STR_LIT> ) ; loadConstant ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( BaseReg ) ; MI . setDesc ( TII . get ( isStore ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( ScratchReg , false , false , true ) ; MI . RemoveOperand ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { assert ( FIPos == <NUM_LIT> && <STR_LIT> ) ; MachineOperand SpillReg = MI . getOperand ( <NUM_LIT> ) ;


<s> BlackfinRegisterInfo :: BlackfinRegisterInfo ( BlackfinSubtarget & st , const TargetInstrInfo & tii ) : BlackfinGenRegisterInfo ( <STR_LIT> ) , Subtarget ( st ) , TII ( tii ) {


<s> int64_t Amount = I -> getOperand ( <NUM_LIT> ) . getImm ( ) ; if ( Amount != <NUM_LIT> ) { assert ( Amount % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; if ( I -> getOpcode ( ) == <STR_LIT> ) { adjustRegister ( MBB , I , I -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , - Amount ) ; } else { assert ( I -> getOpcode ( ) == <STR_LIT> && <STR_LIT> ) ; adjustRegister ( MBB , I , I -> getDebugLoc ( ) , <STR_LIT> , <STR_LIT> , Amount ) ; } }


<s> BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( BaseReg ) ; MI . setDesc ( TII . get ( isStore ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( ScratchReg , false , false , true ) ; MI . RemoveOperand ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { assert ( FIPos == <NUM_LIT> && <STR_LIT> ) ; MachineOperand SpillReg = MI . getOperand ( <NUM_LIT> ) ; unsigned ScratchReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; assert ( ScratchReg && <STR_LIT> ) ; if ( SpillReg . getReg ( ) == <STR_LIT> ) { BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addOperand ( SpillReg ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addOperand ( SpillReg ) ; } MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( ScratchReg , false , false , true ) ; MI . getOperand ( FIPos ) . ChangeToRegister ( BaseReg , false ) ; MI . getOperand ( FIPos + <NUM_LIT> ) . setImm ( Offset ) ; break ; } case <STR_LIT> : { assert ( FIPos == <NUM_LIT> && <STR_LIT> ) ; MachineOperand SpillReg = MI . getOperand ( <NUM_LIT> ) ; unsigned ScratchReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; assert ( ScratchReg && <STR_LIT> ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( ScratchReg , true ) ; MI . getOperand ( FIPos ) . ChangeToRegister ( BaseReg , false ) ; MI . getOperand ( FIPos + <NUM_LIT> ) . setImm ( Offset ) ; ++ II ; if ( SpillReg . getReg ( ) == <STR_LIT> ) { BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( ScratchReg , RegState :: Kill ) ; } else {

BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( ScratchReg , RegState :: Kill ) . addImm ( <NUM_LIT> ) ;


<s> const TargetFrameLowering * TFI = MF . getTarget ( ) . getFrameLowering ( ) ;

return TFI -> hasFP ( MF ) ? <STR_LIT> : <STR_LIT> ;


<s> Reserved . set ( AC1 ) ; Reserved . set ( AV0 ) ; Reserved . set ( AV0S ) ; Reserved . set ( AV1 ) ; Reserved . set ( AV1S ) ; Reserved . set ( V ) ; Reserved . set ( VS ) ; Reserved . set ( CYCLES ) . set ( CYCLES2 ) ; Reserved . set ( L0 ) ; Reserved . set ( L1 ) ;


<s> MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( BaseReg , false ) ; break ; } case <STR_LIT> : isStore = true ; case <STR_LIT> : { assert ( Offset % <NUM_LIT> == <NUM_LIT> && <STR_LIT> ) ; assert ( FIPos == <NUM_LIT> && <STR_LIT> ) ; unsigned ScratchReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; assert ( ScratchReg && <STR_LIT> ) ; loadConstant ( MBB , II , DL , ScratchReg , Offset ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg , RegState :: Kill ) . addReg ( BaseReg ) ; MI . setDesc ( TII . get ( isStore ? <STR_LIT> : <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( ScratchReg , false , false , true ) ; MI . RemoveOperand ( <NUM_LIT> ) ; break ; } case <STR_LIT> : { assert ( FIPos == <NUM_LIT> && <STR_LIT> ) ; MachineOperand SpillReg = MI . getOperand ( <NUM_LIT> ) ; unsigned ScratchReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; assert ( ScratchReg && <STR_LIT> ) ; if ( SpillReg . getReg ( ) == <STR_LIT> ) { BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addOperand ( SpillReg ) ; BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addReg ( ScratchReg ) . addImm ( <NUM_LIT> ) ; } else { BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , ScratchReg ) . addOperand ( SpillReg ) ; } MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( ScratchReg , false , false , true ) ; MI . getOperand ( FIPos ) . ChangeToRegister ( BaseReg , false ) ; MI . getOperand ( FIPos + <NUM_LIT> ) . setImm ( Offset ) ; break ; } case <STR_LIT> : { assert ( FIPos == <NUM_LIT> && <STR_LIT> ) ; MachineOperand SpillReg = MI . getOperand ( <NUM_LIT> ) ; unsigned ScratchReg = findScratchRegister ( II , RS , & <STR_LIT> , SPAdj ) ; assert ( ScratchReg && <STR_LIT> ) ; MI . setDesc ( TII . get ( <STR_LIT> ) ) ; MI . getOperand ( <NUM_LIT> ) . ChangeToRegister ( ScratchReg , true ) ; MI . getOperand ( FIPos ) . ChangeToRegister ( BaseReg , false ) ; MI . getOperand ( FIPos + <NUM_LIT> ) . setImm ( Offset ) ; ++ II ; if ( SpillReg . getReg ( ) == <STR_LIT> ) {

BuildMI ( MBB , II , DL , TII . get ( <STR_LIT> ) , <STR_LIT> ) . addReg ( ScratchReg , RegState :: Kill ) ;


<s> BlackfinSelectionDAGInfo :: BlackfinSelectionDAGInfo ( const BlackfinTargetMachine & TM ) : TargetSelectionDAGInfo ( TM ) {


<s> BlackfinSelectionDAGInfo :: ~ BlackfinSelectionDAGInfo ( ) {


<s> BlackfinTargetAsmInfo :: BlackfinTargetAsmInfo ( const Target & T , const StringRef & TT ) { GlobalPrefix = <STR_LIT> ;


<s> RegisterTarget < Triple :: bfin > X ( TheBlackfinTarget , <STR_LIT> , <STR_LIT> ) ;


<s> BlackfinTargetMachine :: BlackfinTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , FS ) , TLInfo ( * this ) , InstrInfo ( Subtarget ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {


<s> virtual BlackfinTargetLowering * getTargetLowering ( ) const {

return const_cast < BlackfinTargetLowering * > ( & TLInfo ) ;


<s> RegisterTargetMachine < BlackfinTargetMachine > X ( TheBlackfinTarget ) ;

RegisterAsmInfo < BlackfinTargetAsmInfo > Y ( TheBlackfinTarget ) ;


<s> BlackfinTargetMachine :: BlackfinTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , FS ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameInfo ( TargetFrameInfo :: StackGrowsDown , <NUM_LIT> , <NUM_LIT> ) {


<s> void LLVMInitializeBlackfinTarget ( ) { RegisterTargetMachine < BlackfinTargetMachine > X ( TheBlackfinTarget ) ; RegisterAsmInfo < BlackfinMCAsmInfo > Y ( TheBlackfinTarget ) ;


<s> BlackfinTargetMachine :: BlackfinTargetMachine ( const Target & T , const std :: string & TT , const std :: string & FS ) : LLVMTargetMachine ( T , TT ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , FS ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameInfo ( Subtarget ) {


<s> BlackfinTargetMachine :: BlackfinTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM , CodeModel :: Model CM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM , CM ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) {


<s> PM . add ( createBlackfinISelDag ( * this , OptLevel ) ) ;


<s> BlackfinTargetMachine :: BlackfinTargetMachine ( const Target & T , StringRef TT , StringRef CPU , StringRef FS , Reloc :: Model RM ) : LLVMTargetMachine ( T , TT , CPU , FS , RM ) , DataLayout ( <STR_LIT> ) , Subtarget ( TT , CPU , FS ) , TLInfo ( * this ) , TSInfo ( * this ) , InstrInfo ( Subtarget ) , FrameLowering ( Subtarget ) {


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const { return & FrameLowering ;


<s> virtual const TargetFrameLowering * getFrameLowering ( ) const {


<s> const TargetIntrinsicInfo * getIntrinsicInfo ( ) const { return & IntrinsicInfo ;


<s> return & InstrInfo . getRegisterInfo ( ) ;


<s> virtual const BlackfinSelectionDAGInfo * getSelectionDAGInfo ( ) const { return & TSInfo ;


<s> virtual const TargetData * getTargetData ( ) const {


<s> virtual const BlackfinTargetLowering * getTargetLowering ( ) const {